1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg = 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg = 0;
422 /* Register prefix used for error message. */
423 static const char *register_prefix = "%";
425 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
426 leave, push, and pop instructions so that gcc has the same stack
427 frame as in 32 bit mode. */
428 static char stackop_size = '\0';
430 /* Non-zero to optimize code alignment. */
431 int optimize_align_code = 1;
433 /* Non-zero to quieten some warnings. */
434 static int quiet_warnings = 0;
437 static const char *cpu_arch_name = NULL;
438 static char *cpu_sub_arch_name = NULL;
440 /* CPU feature flags. */
441 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
443 /* If we have selected a cpu we are generating instructions for. */
444 static int cpu_arch_tune_set = 0;
446 /* Cpu we are generating instructions for. */
447 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
449 /* CPU feature flags of cpu we are generating instructions for. */
450 static i386_cpu_flags cpu_arch_tune_flags;
452 /* CPU instruction set architecture used. */
453 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
455 /* CPU feature flags of instruction set architecture used. */
456 static i386_cpu_flags cpu_arch_isa_flags;
458 /* If set, conditional jumps are not automatically promoted to handle
459 larger than a byte offset. */
460 static unsigned int no_cond_jump_promotion = 0;
462 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
463 static symbolS *GOT_symbol;
465 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
466 unsigned int x86_dwarf2_return_column;
468 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
469 int x86_cie_data_alignment;
471 /* Interface to relax_segment.
472 There are 3 major relax states for 386 jump insns because the
473 different types of jumps add different sizes to frags when we're
474 figuring out what sort of jump to choose to reach a given label. */
477 #define UNCOND_JUMP 0
479 #define COND_JUMP86 2
484 #define SMALL16 (SMALL | CODE16)
486 #define BIG16 (BIG | CODE16)
490 #define INLINE __inline__
496 #define ENCODE_RELAX_STATE(type, size) \
497 ((relax_substateT) (((type) << 2) | (size)))
498 #define TYPE_FROM_RELAX_STATE(s) \
500 #define DISP_SIZE_FROM_RELAX_STATE(s) \
501 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
503 /* This table is used by relax_frag to promote short jumps to long
504 ones where necessary. SMALL (short) jumps may be promoted to BIG
505 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
506 don't allow a short jump in a 32 bit code segment to be promoted to
507 a 16 bit offset jump because it's slower (requires data size
508 prefix), and doesn't work, unless the destination is in the bottom
509 64k of the code segment (The top 16 bits of eip are zeroed). */
511 const relax_typeS md_relax_table[] =
514 1) most positive reach of this state,
515 2) most negative reach of this state,
516 3) how many bytes this mode will have in the variable part of the frag
517 4) which index into the table to try if we can't fit into this one. */
519 /* UNCOND_JUMP states. */
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
521 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
522 /* dword jmp adds 4 bytes to frag:
523 0 extra opcode bytes, 4 displacement bytes. */
525 /* word jmp adds 2 byte2 to frag:
526 0 extra opcode bytes, 2 displacement bytes. */
529 /* COND_JUMP states. */
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
532 /* dword conditionals adds 5 bytes to frag:
533 1 extra opcode byte, 4 displacement bytes. */
535 /* word conditionals add 3 bytes to frag:
536 1 extra opcode byte, 2 displacement bytes. */
539 /* COND_JUMP86 states. */
540 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
542 /* dword conditionals adds 5 bytes to frag:
543 1 extra opcode byte, 4 displacement bytes. */
545 /* word conditionals add 4 bytes to frag:
546 1 displacement byte and a 3 byte long branch insn. */
550 static const arch_entry cpu_arch[] =
552 { "generic32", PROCESSOR_GENERIC32,
553 CPU_GENERIC32_FLAGS },
554 { "generic64", PROCESSOR_GENERIC64,
555 CPU_GENERIC64_FLAGS },
556 { "i8086", PROCESSOR_UNKNOWN,
558 { "i186", PROCESSOR_UNKNOWN,
560 { "i286", PROCESSOR_UNKNOWN,
562 { "i386", PROCESSOR_I386,
564 { "i486", PROCESSOR_I486,
566 { "i586", PROCESSOR_PENTIUM,
568 { "i686", PROCESSOR_PENTIUMPRO,
570 { "pentium", PROCESSOR_PENTIUM,
572 { "pentiumpro", PROCESSOR_PENTIUMPRO,
574 { "pentiumii", PROCESSOR_PENTIUMPRO,
576 { "pentiumiii",PROCESSOR_PENTIUMPRO,
578 { "pentium4", PROCESSOR_PENTIUM4,
580 { "prescott", PROCESSOR_NOCONA,
582 { "nocona", PROCESSOR_NOCONA,
584 { "yonah", PROCESSOR_CORE,
586 { "core", PROCESSOR_CORE,
588 { "merom", PROCESSOR_CORE2,
590 { "core2", PROCESSOR_CORE2,
592 { "k6", PROCESSOR_K6,
594 { "k6_2", PROCESSOR_K6,
596 { "athlon", PROCESSOR_ATHLON,
598 { "sledgehammer", PROCESSOR_K8,
600 { "opteron", PROCESSOR_K8,
602 { "k8", PROCESSOR_K8,
604 { "amdfam10", PROCESSOR_AMDFAM10,
605 CPU_AMDFAM10_FLAGS },
606 { ".mmx", PROCESSOR_UNKNOWN,
608 { ".sse", PROCESSOR_UNKNOWN,
610 { ".sse2", PROCESSOR_UNKNOWN,
612 { ".sse3", PROCESSOR_UNKNOWN,
614 { ".ssse3", PROCESSOR_UNKNOWN,
616 { ".sse4.1", PROCESSOR_UNKNOWN,
618 { ".sse4.2", PROCESSOR_UNKNOWN,
620 { ".sse4", PROCESSOR_UNKNOWN,
622 { ".vmx", PROCESSOR_UNKNOWN,
624 { ".smx", PROCESSOR_UNKNOWN,
626 { ".3dnow", PROCESSOR_UNKNOWN,
628 { ".3dnowa", PROCESSOR_UNKNOWN,
630 { ".padlock", PROCESSOR_UNKNOWN,
632 { ".pacifica", PROCESSOR_UNKNOWN,
634 { ".svme", PROCESSOR_UNKNOWN,
636 { ".sse4a", PROCESSOR_UNKNOWN,
638 { ".abm", PROCESSOR_UNKNOWN,
640 { ".sse5", PROCESSOR_UNKNOWN,
644 const pseudo_typeS md_pseudo_table[] =
646 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
647 {"align", s_align_bytes, 0},
649 {"align", s_align_ptwo, 0},
651 {"arch", set_cpu_arch, 0},
655 {"ffloat", float_cons, 'f'},
656 {"dfloat", float_cons, 'd'},
657 {"tfloat", float_cons, 'x'},
659 {"slong", signed_cons, 4},
660 {"noopt", s_ignore, 0},
661 {"optim", s_ignore, 0},
662 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
663 {"code16", set_code_flag, CODE_16BIT},
664 {"code32", set_code_flag, CODE_32BIT},
665 {"code64", set_code_flag, CODE_64BIT},
666 {"intel_syntax", set_intel_syntax, 1},
667 {"att_syntax", set_intel_syntax, 0},
668 {"intel_mnemonic", set_intel_mnemonic, 1},
669 {"att_mnemonic", set_intel_mnemonic, 0},
670 {"allow_index_reg", set_allow_index_reg, 1},
671 {"disallow_index_reg", set_allow_index_reg, 0},
672 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
673 {"largecomm", handle_large_common, 0},
675 {"file", (void (*) (int)) dwarf2_directive_file, 0},
676 {"loc", dwarf2_directive_loc, 0},
677 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
680 {"secrel32", pe_directive_secrel, 0},
685 /* For interface with expression (). */
686 extern char *input_line_pointer;
688 /* Hash table for instruction mnemonic lookup. */
689 static struct hash_control *op_hash;
691 /* Hash table for register lookup. */
692 static struct hash_control *reg_hash;
695 i386_align_code (fragS *fragP, int count)
697 /* Various efficient no-op patterns for aligning code labels.
698 Note: Don't try to assemble the instructions in the comments.
699 0L and 0w are not legal. */
700 static const char f32_1[] =
702 static const char f32_2[] =
703 {0x66,0x90}; /* xchg %ax,%ax */
704 static const char f32_3[] =
705 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
706 static const char f32_4[] =
707 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
708 static const char f32_5[] =
710 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
711 static const char f32_6[] =
712 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
713 static const char f32_7[] =
714 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
715 static const char f32_8[] =
717 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
718 static const char f32_9[] =
719 {0x89,0xf6, /* movl %esi,%esi */
720 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
721 static const char f32_10[] =
722 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
723 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
724 static const char f32_11[] =
725 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
726 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
727 static const char f32_12[] =
728 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
729 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
730 static const char f32_13[] =
731 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
732 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
733 static const char f32_14[] =
734 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
735 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
736 static const char f16_3[] =
737 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
738 static const char f16_4[] =
739 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
740 static const char f16_5[] =
742 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
743 static const char f16_6[] =
744 {0x89,0xf6, /* mov %si,%si */
745 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
746 static const char f16_7[] =
747 {0x8d,0x74,0x00, /* lea 0(%si),%si */
748 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
749 static const char f16_8[] =
750 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
751 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
752 static const char jump_31[] =
753 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
754 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
755 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
756 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
757 static const char *const f32_patt[] = {
758 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
759 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
761 static const char *const f16_patt[] = {
762 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
765 static const char alt_3[] =
767 /* nopl 0(%[re]ax) */
768 static const char alt_4[] =
769 {0x0f,0x1f,0x40,0x00};
770 /* nopl 0(%[re]ax,%[re]ax,1) */
771 static const char alt_5[] =
772 {0x0f,0x1f,0x44,0x00,0x00};
773 /* nopw 0(%[re]ax,%[re]ax,1) */
774 static const char alt_6[] =
775 {0x66,0x0f,0x1f,0x44,0x00,0x00};
776 /* nopl 0L(%[re]ax) */
777 static const char alt_7[] =
778 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
779 /* nopl 0L(%[re]ax,%[re]ax,1) */
780 static const char alt_8[] =
781 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
782 /* nopw 0L(%[re]ax,%[re]ax,1) */
783 static const char alt_9[] =
784 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
785 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
786 static const char alt_10[] =
787 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
789 nopw %cs:0L(%[re]ax,%[re]ax,1) */
790 static const char alt_long_11[] =
792 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
795 nopw %cs:0L(%[re]ax,%[re]ax,1) */
796 static const char alt_long_12[] =
799 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
803 nopw %cs:0L(%[re]ax,%[re]ax,1) */
804 static const char alt_long_13[] =
808 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
813 nopw %cs:0L(%[re]ax,%[re]ax,1) */
814 static const char alt_long_14[] =
819 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
825 nopw %cs:0L(%[re]ax,%[re]ax,1) */
826 static const char alt_long_15[] =
832 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 /* nopl 0(%[re]ax,%[re]ax,1)
834 nopw 0(%[re]ax,%[re]ax,1) */
835 static const char alt_short_11[] =
836 {0x0f,0x1f,0x44,0x00,0x00,
837 0x66,0x0f,0x1f,0x44,0x00,0x00};
838 /* nopw 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_12[] =
841 {0x66,0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
845 static const char alt_short_13[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 static const char alt_short_14[] =
851 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
854 nopl 0L(%[re]ax,%[re]ax,1) */
855 static const char alt_short_15[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 static const char *const alt_short_patt[] = {
859 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
860 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
861 alt_short_14, alt_short_15
863 static const char *const alt_long_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
866 alt_long_14, alt_long_15
869 /* Only align for at least a positive non-zero boundary. */
870 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
873 /* We need to decide which NOP sequence to use for 32bit and
874 64bit. When -mtune= is used:
876 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
877 PROCESSOR_GENERIC32, f32_patt will be used.
878 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
879 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
880 alt_long_patt will be used.
881 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
882 PROCESSOR_AMDFAM10, alt_short_patt will be used.
884 When -mtune= isn't used, alt_long_patt will be used if
885 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
888 When -march= or .arch is used, we can't use anything beyond
889 cpu_arch_isa_flags. */
891 if (flag_code == CODE_16BIT)
895 memcpy (fragP->fr_literal + fragP->fr_fix,
897 /* Adjust jump offset. */
898 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
901 memcpy (fragP->fr_literal + fragP->fr_fix,
902 f16_patt[count - 1], count);
906 const char *const *patt = NULL;
908 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
910 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
911 switch (cpu_arch_tune)
913 case PROCESSOR_UNKNOWN:
914 /* We use cpu_arch_isa_flags to check if we SHOULD
915 optimize for Cpu686. */
916 if (cpu_arch_isa_flags.bitfield.cpui686)
917 patt = alt_long_patt;
921 case PROCESSOR_PENTIUMPRO:
922 case PROCESSOR_PENTIUM4:
923 case PROCESSOR_NOCONA:
925 case PROCESSOR_CORE2:
926 case PROCESSOR_GENERIC64:
927 patt = alt_long_patt;
930 case PROCESSOR_ATHLON:
932 case PROCESSOR_AMDFAM10:
933 patt = alt_short_patt;
937 case PROCESSOR_PENTIUM:
938 case PROCESSOR_GENERIC32:
945 switch (cpu_arch_tune)
947 case PROCESSOR_UNKNOWN:
948 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
949 PROCESSOR_UNKNOWN. */
955 case PROCESSOR_PENTIUM:
957 case PROCESSOR_ATHLON:
959 case PROCESSOR_AMDFAM10:
960 case PROCESSOR_GENERIC32:
961 /* We use cpu_arch_isa_flags to check if we CAN optimize
963 if (cpu_arch_isa_flags.bitfield.cpui686)
964 patt = alt_short_patt;
968 case PROCESSOR_PENTIUMPRO:
969 case PROCESSOR_PENTIUM4:
970 case PROCESSOR_NOCONA:
972 case PROCESSOR_CORE2:
973 if (cpu_arch_isa_flags.bitfield.cpui686)
974 patt = alt_long_patt;
978 case PROCESSOR_GENERIC64:
979 patt = alt_long_patt;
984 if (patt == f32_patt)
986 /* If the padding is less than 15 bytes, we use the normal
987 ones. Otherwise, we use a jump instruction and adjust
990 memcpy (fragP->fr_literal + fragP->fr_fix,
991 patt[count - 1], count);
994 memcpy (fragP->fr_literal + fragP->fr_fix,
996 /* Adjust jump offset. */
997 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1002 /* Maximum length of an instruction is 15 byte. If the
1003 padding is greater than 15 bytes and we don't use jump,
1004 we have to break it into smaller pieces. */
1005 int padding = count;
1006 while (padding > 15)
1009 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1014 memcpy (fragP->fr_literal + fragP->fr_fix,
1015 patt [padding - 1], padding);
1018 fragP->fr_var = count;
1022 uints_all_zero (const unsigned int *x, unsigned int size)
1040 uints_set (unsigned int *x, unsigned int v, unsigned int size)
1057 uints_equal (const unsigned int *x, const unsigned int *y,
1069 return x[0] == y [0];
1076 #define UINTS_ALL_ZERO(x) \
1077 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
1078 #define UINTS_SET(x, v) \
1079 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
1080 #define UINTS_CLEAR(x) \
1081 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
1082 #define UINTS_EQUAL(x, y) \
1083 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
1086 cpu_flags_check_cpu64 (i386_cpu_flags f)
1088 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1089 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1092 static INLINE i386_cpu_flags
1093 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1095 switch (ARRAY_SIZE (x.array))
1098 x.array [2] &= y.array [2];
1100 x.array [1] &= y.array [1];
1102 x.array [0] &= y.array [0];
1110 static INLINE i386_cpu_flags
1111 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1113 switch (ARRAY_SIZE (x.array))
1116 x.array [2] |= y.array [2];
1118 x.array [1] |= y.array [1];
1120 x.array [0] |= y.array [0];
1128 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1129 1 if compatible with arch, 0 if there is no match. */
1132 cpu_flags_match (i386_cpu_flags x)
1134 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1136 x.bitfield.cpu64 = 0;
1137 x.bitfield.cpuno64 = 0;
1139 if (UINTS_ALL_ZERO (x))
1143 i386_cpu_flags cpu = cpu_arch_flags;
1145 cpu.bitfield.cpu64 = 0;
1146 cpu.bitfield.cpuno64 = 0;
1147 cpu = cpu_flags_and (x, cpu);
1148 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1153 static INLINE i386_operand_type
1154 operand_type_and (i386_operand_type x, i386_operand_type y)
1156 switch (ARRAY_SIZE (x.array))
1159 x.array [2] &= y.array [2];
1161 x.array [1] &= y.array [1];
1163 x.array [0] &= y.array [0];
1171 static INLINE i386_operand_type
1172 operand_type_or (i386_operand_type x, i386_operand_type y)
1174 switch (ARRAY_SIZE (x.array))
1177 x.array [2] |= y.array [2];
1179 x.array [1] |= y.array [1];
1181 x.array [0] |= y.array [0];
1189 static INLINE i386_operand_type
1190 operand_type_xor (i386_operand_type x, i386_operand_type y)
1192 switch (ARRAY_SIZE (x.array))
1195 x.array [2] ^= y.array [2];
1197 x.array [1] ^= y.array [1];
1199 x.array [0] ^= y.array [0];
1207 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1208 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1209 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1210 static const i386_operand_type reg16_inoutportreg
1211 = OPERAND_TYPE_REG16_INOUTPORTREG;
1212 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1213 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1214 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1215 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1216 static const i386_operand_type anydisp
1217 = OPERAND_TYPE_ANYDISP;
1218 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1219 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1220 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1221 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1222 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1223 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1224 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1225 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1226 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1227 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1238 operand_type_check (i386_operand_type t, enum operand_type c)
1243 return (t.bitfield.reg8
1246 || t.bitfield.reg64);
1249 return (t.bitfield.imm8
1253 || t.bitfield.imm32s
1254 || t.bitfield.imm64);
1257 return (t.bitfield.disp8
1258 || t.bitfield.disp16
1259 || t.bitfield.disp32
1260 || t.bitfield.disp32s
1261 || t.bitfield.disp64);
1264 return (t.bitfield.disp8
1265 || t.bitfield.disp16
1266 || t.bitfield.disp32
1267 || t.bitfield.disp32s
1268 || t.bitfield.disp64
1269 || t.bitfield.baseindex);
1276 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1277 operand J for instruction template T. */
1280 match_reg_size (const template *t, unsigned int j)
1282 return !((i.types[j].bitfield.byte
1283 && !t->operand_types[j].bitfield.byte)
1284 || (i.types[j].bitfield.word
1285 && !t->operand_types[j].bitfield.word)
1286 || (i.types[j].bitfield.dword
1287 && !t->operand_types[j].bitfield.dword)
1288 || (i.types[j].bitfield.qword
1289 && !t->operand_types[j].bitfield.qword));
1292 /* Return 1 if there is no conflict in any size on operand J for
1293 instruction template T. */
1296 match_mem_size (const template *t, unsigned int j)
1298 return (match_reg_size (t, j)
1299 && !((i.types[j].bitfield.unspecified
1300 && !t->operand_types[j].bitfield.unspecified)
1301 || (i.types[j].bitfield.fword
1302 && !t->operand_types[j].bitfield.fword)
1303 || (i.types[j].bitfield.tbyte
1304 && !t->operand_types[j].bitfield.tbyte)
1305 || (i.types[j].bitfield.xmmword
1306 && !t->operand_types[j].bitfield.xmmword)));
1309 /* Return 1 if there is no size conflict on any operands for
1310 instruction template T. */
1313 operand_size_match (const template *t)
1318 /* Don't check jump instructions. */
1319 if (t->opcode_modifier.jump
1320 || t->opcode_modifier.jumpbyte
1321 || t->opcode_modifier.jumpdword
1322 || t->opcode_modifier.jumpintersegment)
1325 /* Check memory and accumulator operand size. */
1326 for (j = 0; j < i.operands; j++)
1328 if (t->operand_types[j].bitfield.anysize)
1331 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1337 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1345 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1348 /* Check reverse. */
1349 assert (i.operands == 2);
1352 for (j = 0; j < 2; j++)
1354 if (t->operand_types[j].bitfield.acc
1355 && !match_reg_size (t, j ? 0 : 1))
1361 if (i.types[j].bitfield.mem
1362 && !match_mem_size (t, j ? 0 : 1))
1373 operand_type_match (i386_operand_type overlap,
1374 i386_operand_type given)
1376 i386_operand_type temp = overlap;
1378 temp.bitfield.jumpabsolute = 0;
1379 temp.bitfield.unspecified = 0;
1380 temp.bitfield.byte = 0;
1381 temp.bitfield.word = 0;
1382 temp.bitfield.dword = 0;
1383 temp.bitfield.fword = 0;
1384 temp.bitfield.qword = 0;
1385 temp.bitfield.tbyte = 0;
1386 temp.bitfield.xmmword = 0;
1387 if (UINTS_ALL_ZERO (temp))
1390 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1391 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1394 /* If given types g0 and g1 are registers they must be of the same type
1395 unless the expected operand type register overlap is null.
1396 Note that Acc in a template matches every size of reg. */
1399 operand_type_register_match (i386_operand_type m0,
1400 i386_operand_type g0,
1401 i386_operand_type t0,
1402 i386_operand_type m1,
1403 i386_operand_type g1,
1404 i386_operand_type t1)
1406 if (!operand_type_check (g0, reg))
1409 if (!operand_type_check (g1, reg))
1412 if (g0.bitfield.reg8 == g1.bitfield.reg8
1413 && g0.bitfield.reg16 == g1.bitfield.reg16
1414 && g0.bitfield.reg32 == g1.bitfield.reg32
1415 && g0.bitfield.reg64 == g1.bitfield.reg64)
1418 if (m0.bitfield.acc)
1420 t0.bitfield.reg8 = 1;
1421 t0.bitfield.reg16 = 1;
1422 t0.bitfield.reg32 = 1;
1423 t0.bitfield.reg64 = 1;
1426 if (m1.bitfield.acc)
1428 t1.bitfield.reg8 = 1;
1429 t1.bitfield.reg16 = 1;
1430 t1.bitfield.reg32 = 1;
1431 t1.bitfield.reg64 = 1;
1434 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1435 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1436 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1437 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1440 static INLINE unsigned int
1441 mode_from_disp_size (i386_operand_type t)
1443 if (t.bitfield.disp8)
1445 else if (t.bitfield.disp16
1446 || t.bitfield.disp32
1447 || t.bitfield.disp32s)
1454 fits_in_signed_byte (offsetT num)
1456 return (num >= -128) && (num <= 127);
1460 fits_in_unsigned_byte (offsetT num)
1462 return (num & 0xff) == num;
1466 fits_in_unsigned_word (offsetT num)
1468 return (num & 0xffff) == num;
1472 fits_in_signed_word (offsetT num)
1474 return (-32768 <= num) && (num <= 32767);
1478 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1483 return (!(((offsetT) -1 << 31) & num)
1484 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1486 } /* fits_in_signed_long() */
1489 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1494 return (num & (((offsetT) 2 << 31) - 1)) == num;
1496 } /* fits_in_unsigned_long() */
1498 static i386_operand_type
1499 smallest_imm_type (offsetT num)
1501 i386_operand_type t;
1504 t.bitfield.imm64 = 1;
1506 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1508 /* This code is disabled on the 486 because all the Imm1 forms
1509 in the opcode table are slower on the i486. They're the
1510 versions with the implicitly specified single-position
1511 displacement, which has another syntax if you really want to
1513 t.bitfield.imm1 = 1;
1514 t.bitfield.imm8 = 1;
1515 t.bitfield.imm8s = 1;
1516 t.bitfield.imm16 = 1;
1517 t.bitfield.imm32 = 1;
1518 t.bitfield.imm32s = 1;
1520 else if (fits_in_signed_byte (num))
1522 t.bitfield.imm8 = 1;
1523 t.bitfield.imm8s = 1;
1524 t.bitfield.imm16 = 1;
1525 t.bitfield.imm32 = 1;
1526 t.bitfield.imm32s = 1;
1528 else if (fits_in_unsigned_byte (num))
1530 t.bitfield.imm8 = 1;
1531 t.bitfield.imm16 = 1;
1532 t.bitfield.imm32 = 1;
1533 t.bitfield.imm32s = 1;
1535 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1537 t.bitfield.imm16 = 1;
1538 t.bitfield.imm32 = 1;
1539 t.bitfield.imm32s = 1;
1541 else if (fits_in_signed_long (num))
1543 t.bitfield.imm32 = 1;
1544 t.bitfield.imm32s = 1;
1546 else if (fits_in_unsigned_long (num))
1547 t.bitfield.imm32 = 1;
1553 offset_in_range (offsetT val, int size)
1559 case 1: mask = ((addressT) 1 << 8) - 1; break;
1560 case 2: mask = ((addressT) 1 << 16) - 1; break;
1561 case 4: mask = ((addressT) 2 << 31) - 1; break;
1563 case 8: mask = ((addressT) 2 << 63) - 1; break;
1568 /* If BFD64, sign extend val. */
1569 if (!use_rela_relocations)
1570 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1571 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1573 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1575 char buf1[40], buf2[40];
1577 sprint_value (buf1, val);
1578 sprint_value (buf2, val & mask);
1579 as_warn (_("%s shortened to %s"), buf1, buf2);
1584 /* Returns 0 if attempting to add a prefix where one from the same
1585 class already exists, 1 if non rep/repne added, 2 if rep/repne
1588 add_prefix (unsigned int prefix)
1593 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1594 && flag_code == CODE_64BIT)
1596 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1597 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1598 && (prefix & (REX_R | REX_X | REX_B))))
1609 case CS_PREFIX_OPCODE:
1610 case DS_PREFIX_OPCODE:
1611 case ES_PREFIX_OPCODE:
1612 case FS_PREFIX_OPCODE:
1613 case GS_PREFIX_OPCODE:
1614 case SS_PREFIX_OPCODE:
1618 case REPNE_PREFIX_OPCODE:
1619 case REPE_PREFIX_OPCODE:
1622 case LOCK_PREFIX_OPCODE:
1630 case ADDR_PREFIX_OPCODE:
1634 case DATA_PREFIX_OPCODE:
1638 if (i.prefix[q] != 0)
1646 i.prefix[q] |= prefix;
1649 as_bad (_("same type of prefix used twice"));
1655 set_code_flag (int value)
1658 if (flag_code == CODE_64BIT)
1660 cpu_arch_flags.bitfield.cpu64 = 1;
1661 cpu_arch_flags.bitfield.cpuno64 = 0;
1665 cpu_arch_flags.bitfield.cpu64 = 0;
1666 cpu_arch_flags.bitfield.cpuno64 = 1;
1668 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1670 as_bad (_("64bit mode not supported on this CPU."));
1672 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1674 as_bad (_("32bit mode not supported on this CPU."));
1676 stackop_size = '\0';
1680 set_16bit_gcc_code_flag (int new_code_flag)
1682 flag_code = new_code_flag;
1683 if (flag_code != CODE_16BIT)
1685 cpu_arch_flags.bitfield.cpu64 = 0;
1686 cpu_arch_flags.bitfield.cpuno64 = 1;
1687 stackop_size = LONG_MNEM_SUFFIX;
1691 set_intel_syntax (int syntax_flag)
1693 /* Find out if register prefixing is specified. */
1694 int ask_naked_reg = 0;
1697 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1699 char *string = input_line_pointer;
1700 int e = get_symbol_end ();
1702 if (strcmp (string, "prefix") == 0)
1704 else if (strcmp (string, "noprefix") == 0)
1707 as_bad (_("bad argument to syntax directive."));
1708 *input_line_pointer = e;
1710 demand_empty_rest_of_line ();
1712 intel_syntax = syntax_flag;
1714 if (ask_naked_reg == 0)
1715 allow_naked_reg = (intel_syntax
1716 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1718 allow_naked_reg = (ask_naked_reg < 0);
1720 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1721 identifier_chars['$'] = intel_syntax ? '$' : 0;
1722 register_prefix = allow_naked_reg ? "" : "%";
1726 set_intel_mnemonic (int mnemonic_flag)
1728 intel_mnemonic = mnemonic_flag;
1732 set_allow_index_reg (int flag)
1734 allow_index_reg = flag;
1738 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1742 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1744 char *string = input_line_pointer;
1745 int e = get_symbol_end ();
1747 i386_cpu_flags flags;
1749 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1751 if (strcmp (string, cpu_arch[i].name) == 0)
1755 cpu_arch_name = cpu_arch[i].name;
1756 cpu_sub_arch_name = NULL;
1757 cpu_arch_flags = cpu_arch[i].flags;
1758 if (flag_code == CODE_64BIT)
1760 cpu_arch_flags.bitfield.cpu64 = 1;
1761 cpu_arch_flags.bitfield.cpuno64 = 0;
1765 cpu_arch_flags.bitfield.cpu64 = 0;
1766 cpu_arch_flags.bitfield.cpuno64 = 1;
1768 cpu_arch_isa = cpu_arch[i].type;
1769 cpu_arch_isa_flags = cpu_arch[i].flags;
1770 if (!cpu_arch_tune_set)
1772 cpu_arch_tune = cpu_arch_isa;
1773 cpu_arch_tune_flags = cpu_arch_isa_flags;
1778 flags = cpu_flags_or (cpu_arch_flags,
1780 if (!UINTS_EQUAL (flags, cpu_arch_flags))
1782 if (cpu_sub_arch_name)
1784 char *name = cpu_sub_arch_name;
1785 cpu_sub_arch_name = concat (name,
1791 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1792 cpu_arch_flags = flags;
1794 *input_line_pointer = e;
1795 demand_empty_rest_of_line ();
1799 if (i >= ARRAY_SIZE (cpu_arch))
1800 as_bad (_("no such architecture: `%s'"), string);
1802 *input_line_pointer = e;
1805 as_bad (_("missing cpu architecture"));
1807 no_cond_jump_promotion = 0;
1808 if (*input_line_pointer == ','
1809 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1811 char *string = ++input_line_pointer;
1812 int e = get_symbol_end ();
1814 if (strcmp (string, "nojumps") == 0)
1815 no_cond_jump_promotion = 1;
1816 else if (strcmp (string, "jumps") == 0)
1819 as_bad (_("no such architecture modifier: `%s'"), string);
1821 *input_line_pointer = e;
1824 demand_empty_rest_of_line ();
1830 if (!strcmp (default_arch, "x86_64"))
1831 return bfd_mach_x86_64;
1832 else if (!strcmp (default_arch, "i386"))
1833 return bfd_mach_i386_i386;
1835 as_fatal (_("Unknown architecture"));
1841 const char *hash_err;
1843 /* Initialize op_hash hash table. */
1844 op_hash = hash_new ();
1847 const template *optab;
1848 templates *core_optab;
1850 /* Setup for loop. */
1852 core_optab = (templates *) xmalloc (sizeof (templates));
1853 core_optab->start = optab;
1858 if (optab->name == NULL
1859 || strcmp (optab->name, (optab - 1)->name) != 0)
1861 /* different name --> ship out current template list;
1862 add to hash table; & begin anew. */
1863 core_optab->end = optab;
1864 hash_err = hash_insert (op_hash,
1869 as_fatal (_("Internal Error: Can't hash %s: %s"),
1873 if (optab->name == NULL)
1875 core_optab = (templates *) xmalloc (sizeof (templates));
1876 core_optab->start = optab;
1881 /* Initialize reg_hash hash table. */
1882 reg_hash = hash_new ();
1884 const reg_entry *regtab;
1885 unsigned int regtab_size = i386_regtab_size;
1887 for (regtab = i386_regtab; regtab_size--; regtab++)
1889 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1891 as_fatal (_("Internal Error: Can't hash %s: %s"),
1897 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1902 for (c = 0; c < 256; c++)
1907 mnemonic_chars[c] = c;
1908 register_chars[c] = c;
1909 operand_chars[c] = c;
1911 else if (ISLOWER (c))
1913 mnemonic_chars[c] = c;
1914 register_chars[c] = c;
1915 operand_chars[c] = c;
1917 else if (ISUPPER (c))
1919 mnemonic_chars[c] = TOLOWER (c);
1920 register_chars[c] = mnemonic_chars[c];
1921 operand_chars[c] = c;
1924 if (ISALPHA (c) || ISDIGIT (c))
1925 identifier_chars[c] = c;
1928 identifier_chars[c] = c;
1929 operand_chars[c] = c;
1934 identifier_chars['@'] = '@';
1937 identifier_chars['?'] = '?';
1938 operand_chars['?'] = '?';
1940 digit_chars['-'] = '-';
1941 mnemonic_chars['-'] = '-';
1942 mnemonic_chars['.'] = '.';
1943 identifier_chars['_'] = '_';
1944 identifier_chars['.'] = '.';
1946 for (p = operand_special_chars; *p != '\0'; p++)
1947 operand_chars[(unsigned char) *p] = *p;
1950 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1953 record_alignment (text_section, 2);
1954 record_alignment (data_section, 2);
1955 record_alignment (bss_section, 2);
1959 if (flag_code == CODE_64BIT)
1961 x86_dwarf2_return_column = 16;
1962 x86_cie_data_alignment = -8;
1966 x86_dwarf2_return_column = 8;
1967 x86_cie_data_alignment = -4;
1972 i386_print_statistics (FILE *file)
1974 hash_print_statistics (file, "i386 opcode", op_hash);
1975 hash_print_statistics (file, "i386 register", reg_hash);
1980 /* Debugging routines for md_assemble. */
1981 static void pte (template *);
1982 static void pt (i386_operand_type);
1983 static void pe (expressionS *);
1984 static void ps (symbolS *);
1987 pi (char *line, i386_insn *x)
1991 fprintf (stdout, "%s: template ", line);
1993 fprintf (stdout, " address: base %s index %s scale %x\n",
1994 x->base_reg ? x->base_reg->reg_name : "none",
1995 x->index_reg ? x->index_reg->reg_name : "none",
1996 x->log2_scale_factor);
1997 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1998 x->rm.mode, x->rm.reg, x->rm.regmem);
1999 fprintf (stdout, " sib: base %x index %x scale %x\n",
2000 x->sib.base, x->sib.index, x->sib.scale);
2001 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2002 (x->rex & REX_W) != 0,
2003 (x->rex & REX_R) != 0,
2004 (x->rex & REX_X) != 0,
2005 (x->rex & REX_B) != 0);
2006 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2007 x->drex.reg, x->drex.rex);
2008 for (i = 0; i < x->operands; i++)
2010 fprintf (stdout, " #%d: ", i + 1);
2012 fprintf (stdout, "\n");
2013 if (x->types[i].bitfield.reg8
2014 || x->types[i].bitfield.reg16
2015 || x->types[i].bitfield.reg32
2016 || x->types[i].bitfield.reg64
2017 || x->types[i].bitfield.regmmx
2018 || x->types[i].bitfield.regxmm
2019 || x->types[i].bitfield.sreg2
2020 || x->types[i].bitfield.sreg3
2021 || x->types[i].bitfield.control
2022 || x->types[i].bitfield.debug
2023 || x->types[i].bitfield.test)
2024 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2025 if (operand_type_check (x->types[i], imm))
2027 if (operand_type_check (x->types[i], disp))
2028 pe (x->op[i].disps);
2036 fprintf (stdout, " %d operands ", t->operands);
2037 fprintf (stdout, "opcode %x ", t->base_opcode);
2038 if (t->extension_opcode != None)
2039 fprintf (stdout, "ext %x ", t->extension_opcode);
2040 if (t->opcode_modifier.d)
2041 fprintf (stdout, "D");
2042 if (t->opcode_modifier.w)
2043 fprintf (stdout, "W");
2044 fprintf (stdout, "\n");
2045 for (i = 0; i < t->operands; i++)
2047 fprintf (stdout, " #%d type ", i + 1);
2048 pt (t->operand_types[i]);
2049 fprintf (stdout, "\n");
2056 fprintf (stdout, " operation %d\n", e->X_op);
2057 fprintf (stdout, " add_number %ld (%lx)\n",
2058 (long) e->X_add_number, (long) e->X_add_number);
2059 if (e->X_add_symbol)
2061 fprintf (stdout, " add_symbol ");
2062 ps (e->X_add_symbol);
2063 fprintf (stdout, "\n");
2067 fprintf (stdout, " op_symbol ");
2068 ps (e->X_op_symbol);
2069 fprintf (stdout, "\n");
2076 fprintf (stdout, "%s type %s%s",
2078 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2079 segment_name (S_GET_SEGMENT (s)));
2082 static struct type_name
2084 i386_operand_type mask;
2087 const type_names[] =
2089 { OPERAND_TYPE_REG8, "r8" },
2090 { OPERAND_TYPE_REG16, "r16" },
2091 { OPERAND_TYPE_REG32, "r32" },
2092 { OPERAND_TYPE_REG64, "r64" },
2093 { OPERAND_TYPE_IMM8, "i8" },
2094 { OPERAND_TYPE_IMM8, "i8s" },
2095 { OPERAND_TYPE_IMM16, "i16" },
2096 { OPERAND_TYPE_IMM32, "i32" },
2097 { OPERAND_TYPE_IMM32S, "i32s" },
2098 { OPERAND_TYPE_IMM64, "i64" },
2099 { OPERAND_TYPE_IMM1, "i1" },
2100 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2101 { OPERAND_TYPE_DISP8, "d8" },
2102 { OPERAND_TYPE_DISP16, "d16" },
2103 { OPERAND_TYPE_DISP32, "d32" },
2104 { OPERAND_TYPE_DISP32S, "d32s" },
2105 { OPERAND_TYPE_DISP64, "d64" },
2106 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2107 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2108 { OPERAND_TYPE_CONTROL, "control reg" },
2109 { OPERAND_TYPE_TEST, "test reg" },
2110 { OPERAND_TYPE_DEBUG, "debug reg" },
2111 { OPERAND_TYPE_FLOATREG, "FReg" },
2112 { OPERAND_TYPE_FLOATACC, "FAcc" },
2113 { OPERAND_TYPE_SREG2, "SReg2" },
2114 { OPERAND_TYPE_SREG3, "SReg3" },
2115 { OPERAND_TYPE_ACC, "Acc" },
2116 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2117 { OPERAND_TYPE_REGMMX, "rMMX" },
2118 { OPERAND_TYPE_REGXMM, "rXMM" },
2119 { OPERAND_TYPE_ESSEG, "es" },
2123 pt (i386_operand_type t)
2126 i386_operand_type a;
2128 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2130 a = operand_type_and (t, type_names[j].mask);
2131 if (!UINTS_ALL_ZERO (a))
2132 fprintf (stdout, "%s, ", type_names[j].name);
2137 #endif /* DEBUG386 */
2139 static bfd_reloc_code_real_type
2140 reloc (unsigned int size,
2143 bfd_reloc_code_real_type other)
2145 if (other != NO_RELOC)
2147 reloc_howto_type *reloc;
2152 case BFD_RELOC_X86_64_GOT32:
2153 return BFD_RELOC_X86_64_GOT64;
2155 case BFD_RELOC_X86_64_PLTOFF64:
2156 return BFD_RELOC_X86_64_PLTOFF64;
2158 case BFD_RELOC_X86_64_GOTPC32:
2159 other = BFD_RELOC_X86_64_GOTPC64;
2161 case BFD_RELOC_X86_64_GOTPCREL:
2162 other = BFD_RELOC_X86_64_GOTPCREL64;
2164 case BFD_RELOC_X86_64_TPOFF32:
2165 other = BFD_RELOC_X86_64_TPOFF64;
2167 case BFD_RELOC_X86_64_DTPOFF32:
2168 other = BFD_RELOC_X86_64_DTPOFF64;
2174 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2175 if (size == 4 && flag_code != CODE_64BIT)
2178 reloc = bfd_reloc_type_lookup (stdoutput, other);
2180 as_bad (_("unknown relocation (%u)"), other);
2181 else if (size != bfd_get_reloc_size (reloc))
2182 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2183 bfd_get_reloc_size (reloc),
2185 else if (pcrel && !reloc->pc_relative)
2186 as_bad (_("non-pc-relative relocation for pc-relative field"));
2187 else if ((reloc->complain_on_overflow == complain_overflow_signed
2189 || (reloc->complain_on_overflow == complain_overflow_unsigned
2191 as_bad (_("relocated field and relocation type differ in signedness"));
2200 as_bad (_("there are no unsigned pc-relative relocations"));
2203 case 1: return BFD_RELOC_8_PCREL;
2204 case 2: return BFD_RELOC_16_PCREL;
2205 case 4: return BFD_RELOC_32_PCREL;
2206 case 8: return BFD_RELOC_64_PCREL;
2208 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2215 case 4: return BFD_RELOC_X86_64_32S;
2220 case 1: return BFD_RELOC_8;
2221 case 2: return BFD_RELOC_16;
2222 case 4: return BFD_RELOC_32;
2223 case 8: return BFD_RELOC_64;
2225 as_bad (_("cannot do %s %u byte relocation"),
2226 sign > 0 ? "signed" : "unsigned", size);
2230 return BFD_RELOC_NONE;
2233 /* Here we decide which fixups can be adjusted to make them relative to
2234 the beginning of the section instead of the symbol. Basically we need
2235 to make sure that the dynamic relocations are done correctly, so in
2236 some cases we force the original symbol to be used. */
2239 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2241 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2245 /* Don't adjust pc-relative references to merge sections in 64-bit
2247 if (use_rela_relocations
2248 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2252 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2253 and changed later by validate_fix. */
2254 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2255 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2258 /* adjust_reloc_syms doesn't know about the GOT. */
2259 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2260 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2261 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2262 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2263 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2264 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2265 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2266 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2267 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2268 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2269 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2270 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2271 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2272 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2273 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2274 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2275 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2276 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2277 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2278 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2279 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2280 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2281 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2282 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2283 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2284 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2285 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2286 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2293 intel_float_operand (const char *mnemonic)
2295 /* Note that the value returned is meaningful only for opcodes with (memory)
2296 operands, hence the code here is free to improperly handle opcodes that
2297 have no operands (for better performance and smaller code). */
2299 if (mnemonic[0] != 'f')
2300 return 0; /* non-math */
2302 switch (mnemonic[1])
2304 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2305 the fs segment override prefix not currently handled because no
2306 call path can make opcodes without operands get here */
2308 return 2 /* integer op */;
2310 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2311 return 3; /* fldcw/fldenv */
2314 if (mnemonic[2] != 'o' /* fnop */)
2315 return 3; /* non-waiting control op */
2318 if (mnemonic[2] == 's')
2319 return 3; /* frstor/frstpm */
2322 if (mnemonic[2] == 'a')
2323 return 3; /* fsave */
2324 if (mnemonic[2] == 't')
2326 switch (mnemonic[3])
2328 case 'c': /* fstcw */
2329 case 'd': /* fstdw */
2330 case 'e': /* fstenv */
2331 case 's': /* fsts[gw] */
2337 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2338 return 0; /* fxsave/fxrstor are not really math ops */
2345 /* This is the guts of the machine-dependent assembler. LINE points to a
2346 machine dependent instruction. This function is supposed to emit
2347 the frags/bytes it assembles to. */
2354 char mnemonic[MAX_MNEM_SIZE];
2356 /* Initialize globals. */
2357 memset (&i, '\0', sizeof (i));
2358 for (j = 0; j < MAX_OPERANDS; j++)
2359 i.reloc[j] = NO_RELOC;
2360 memset (disp_expressions, '\0', sizeof (disp_expressions));
2361 memset (im_expressions, '\0', sizeof (im_expressions));
2362 save_stack_p = save_stack;
2364 /* First parse an instruction mnemonic & call i386_operand for the operands.
2365 We assume that the scrubber has arranged it so that line[0] is the valid
2366 start of a (possibly prefixed) mnemonic. */
2368 line = parse_insn (line, mnemonic);
2372 line = parse_operands (line, mnemonic);
2376 /* Now we've parsed the mnemonic into a set of templates, and have the
2377 operands at hand. */
2379 /* All intel opcodes have reversed operands except for "bound" and
2380 "enter". We also don't reverse intersegment "jmp" and "call"
2381 instructions with 2 immediate operands so that the immediate segment
2382 precedes the offset, as it does when in AT&T mode. */
2385 && (strcmp (mnemonic, "bound") != 0)
2386 && (strcmp (mnemonic, "invlpga") != 0)
2387 && !(operand_type_check (i.types[0], imm)
2388 && operand_type_check (i.types[1], imm)))
2391 /* The order of the immediates should be reversed
2392 for 2 immediates extrq and insertq instructions */
2393 if (i.imm_operands == 2
2394 && (strcmp (mnemonic, "extrq") == 0
2395 || strcmp (mnemonic, "insertq") == 0))
2396 swap_2_operands (0, 1);
2401 /* Don't optimize displacement for movabs since it only takes 64bit
2404 && (flag_code != CODE_64BIT
2405 || strcmp (mnemonic, "movabs") != 0))
2408 /* Next, we find a template that matches the given insn,
2409 making sure the overlap of the given operands types is consistent
2410 with the template operand types. */
2412 if (!match_template ())
2415 /* Zap movzx and movsx suffix. The suffix has been set from
2416 "word ptr" or "byte ptr" on the source operand in Intel syntax
2417 or extracted from mnemonic in AT&T syntax. But we'll use
2418 the destination register to choose the suffix for encoding. */
2419 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2421 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2422 there is no suffix, the default will be byte extension. */
2423 if (i.reg_operands != 2
2426 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2431 if (i.tm.opcode_modifier.fwait)
2432 if (!add_prefix (FWAIT_OPCODE))
2435 /* Check string instruction segment overrides. */
2436 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2438 if (!check_string ())
2442 if (!process_suffix ())
2445 /* Make still unresolved immediate matches conform to size of immediate
2446 given in i.suffix. */
2447 if (!finalize_imm ())
2450 if (i.types[0].bitfield.imm1)
2451 i.imm_operands = 0; /* kludge for shift insns. */
2453 for (j = 0; j < 3; j++)
2454 if (i.types[j].bitfield.inoutportreg
2455 || i.types[j].bitfield.shiftcount
2456 || i.types[j].bitfield.acc
2457 || i.types[j].bitfield.floatacc)
2460 if (i.tm.opcode_modifier.immext)
2464 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2466 /* Streaming SIMD extensions 3 Instructions have the fixed
2467 operands with an opcode suffix which is coded in the same
2468 place as an 8-bit immediate field would be. Here we check
2469 those operands and remove them afterwards. */
2472 for (x = 0; x < i.operands; x++)
2473 if (i.op[x].regs->reg_num != x)
2474 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2476 i.op[x].regs->reg_name,
2482 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2483 opcode suffix which is coded in the same place as an 8-bit
2484 immediate field would be. Here we fake an 8-bit immediate
2485 operand from the opcode suffix stored in tm.extension_opcode.
2486 SSE5 also uses this encoding, for some of its 3 argument
2489 assert (i.imm_operands == 0
2491 || (i.tm.cpu_flags.bitfield.cpusse5
2492 && i.operands <= 3)));
2494 exp = &im_expressions[i.imm_operands++];
2495 i.op[i.operands].imms = exp;
2496 UINTS_CLEAR (i.types[i.operands]);
2497 i.types[i.operands].bitfield.imm8 = 1;
2499 exp->X_op = O_constant;
2500 exp->X_add_number = i.tm.extension_opcode;
2501 i.tm.extension_opcode = None;
2504 /* For insns with operands there are more diddles to do to the opcode. */
2507 if (!process_operands ())
2510 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2512 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2513 as_warn (_("translating to `%sp'"), i.tm.name);
2516 /* Handle conversion of 'int $3' --> special int3 insn. */
2517 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2519 i.tm.base_opcode = INT3_OPCODE;
2523 if ((i.tm.opcode_modifier.jump
2524 || i.tm.opcode_modifier.jumpbyte
2525 || i.tm.opcode_modifier.jumpdword)
2526 && i.op[0].disps->X_op == O_constant)
2528 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2529 the absolute address given by the constant. Since ix86 jumps and
2530 calls are pc relative, we need to generate a reloc. */
2531 i.op[0].disps->X_add_symbol = &abs_symbol;
2532 i.op[0].disps->X_op = O_symbol;
2535 if (i.tm.opcode_modifier.rex64)
2538 /* For 8 bit registers we need an empty rex prefix. Also if the
2539 instruction already has a prefix, we need to convert old
2540 registers to new ones. */
2542 if ((i.types[0].bitfield.reg8
2543 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2544 || (i.types[1].bitfield.reg8
2545 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2546 || ((i.types[0].bitfield.reg8
2547 || i.types[1].bitfield.reg8)
2552 i.rex |= REX_OPCODE;
2553 for (x = 0; x < 2; x++)
2555 /* Look for 8 bit operand that uses old registers. */
2556 if (i.types[x].bitfield.reg8
2557 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2559 /* In case it is "hi" register, give up. */
2560 if (i.op[x].regs->reg_num > 3)
2561 as_bad (_("can't encode register '%s%s' in an "
2562 "instruction requiring REX prefix."),
2563 register_prefix, i.op[x].regs->reg_name);
2565 /* Otherwise it is equivalent to the extended register.
2566 Since the encoding doesn't change this is merely
2567 cosmetic cleanup for debug output. */
2569 i.op[x].regs = i.op[x].regs + 8;
2574 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2576 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2581 else if (i.rex != 0)
2582 add_prefix (REX_OPCODE | i.rex);
2584 /* We are ready to output the insn. */
2589 parse_insn (char *line, char *mnemonic)
2592 char *token_start = l;
2597 /* Non-zero if we found a prefix only acceptable with string insns. */
2598 const char *expecting_string_instruction = NULL;
2603 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2606 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2608 as_bad (_("no such instruction: `%s'"), token_start);
2613 if (!is_space_char (*l)
2614 && *l != END_OF_INSN
2616 || (*l != PREFIX_SEPARATOR
2619 as_bad (_("invalid character %s in mnemonic"),
2620 output_invalid (*l));
2623 if (token_start == l)
2625 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2626 as_bad (_("expecting prefix; got nothing"));
2628 as_bad (_("expecting mnemonic; got nothing"));
2632 /* Look up instruction (or prefix) via hash table. */
2633 current_templates = hash_find (op_hash, mnemonic);
2635 if (*l != END_OF_INSN
2636 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2637 && current_templates
2638 && current_templates->start->opcode_modifier.isprefix)
2640 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2642 as_bad ((flag_code != CODE_64BIT
2643 ? _("`%s' is only supported in 64-bit mode")
2644 : _("`%s' is not supported in 64-bit mode")),
2645 current_templates->start->name);
2648 /* If we are in 16-bit mode, do not allow addr16 or data16.
2649 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2650 if ((current_templates->start->opcode_modifier.size16
2651 || current_templates->start->opcode_modifier.size32)
2652 && flag_code != CODE_64BIT
2653 && (current_templates->start->opcode_modifier.size32
2654 ^ (flag_code == CODE_16BIT)))
2656 as_bad (_("redundant %s prefix"),
2657 current_templates->start->name);
2660 /* Add prefix, checking for repeated prefixes. */
2661 switch (add_prefix (current_templates->start->base_opcode))
2666 expecting_string_instruction = current_templates->start->name;
2669 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2676 if (!current_templates)
2678 /* See if we can get a match by trimming off a suffix. */
2681 case WORD_MNEM_SUFFIX:
2682 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2683 i.suffix = SHORT_MNEM_SUFFIX;
2685 case BYTE_MNEM_SUFFIX:
2686 case QWORD_MNEM_SUFFIX:
2687 i.suffix = mnem_p[-1];
2689 current_templates = hash_find (op_hash, mnemonic);
2691 case SHORT_MNEM_SUFFIX:
2692 case LONG_MNEM_SUFFIX:
2695 i.suffix = mnem_p[-1];
2697 current_templates = hash_find (op_hash, mnemonic);
2705 if (intel_float_operand (mnemonic) == 1)
2706 i.suffix = SHORT_MNEM_SUFFIX;
2708 i.suffix = LONG_MNEM_SUFFIX;
2710 current_templates = hash_find (op_hash, mnemonic);
2714 if (!current_templates)
2716 as_bad (_("no such instruction: `%s'"), token_start);
2721 if (current_templates->start->opcode_modifier.jump
2722 || current_templates->start->opcode_modifier.jumpbyte)
2724 /* Check for a branch hint. We allow ",pt" and ",pn" for
2725 predict taken and predict not taken respectively.
2726 I'm not sure that branch hints actually do anything on loop
2727 and jcxz insns (JumpByte) for current Pentium4 chips. They
2728 may work in the future and it doesn't hurt to accept them
2730 if (l[0] == ',' && l[1] == 'p')
2734 if (!add_prefix (DS_PREFIX_OPCODE))
2738 else if (l[2] == 'n')
2740 if (!add_prefix (CS_PREFIX_OPCODE))
2746 /* Any other comma loses. */
2749 as_bad (_("invalid character %s in mnemonic"),
2750 output_invalid (*l));
2754 /* Check if instruction is supported on specified architecture. */
2756 for (t = current_templates->start; t < current_templates->end; ++t)
2758 supported |= cpu_flags_match (t->cpu_flags);
2763 if (!(supported & 2))
2765 as_bad (flag_code == CODE_64BIT
2766 ? _("`%s' is not supported in 64-bit mode")
2767 : _("`%s' is only supported in 64-bit mode"),
2768 current_templates->start->name);
2771 if (!(supported & 1))
2773 as_bad (_("`%s' is not supported on `%s%s'"),
2774 current_templates->start->name, cpu_arch_name,
2775 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2780 if (!cpu_arch_flags.bitfield.cpui386
2781 && (flag_code != CODE_16BIT))
2783 as_warn (_("use .code16 to ensure correct addressing mode"));
2786 /* Check for rep/repne without a string instruction. */
2787 if (expecting_string_instruction)
2789 static templates override;
2791 for (t = current_templates->start; t < current_templates->end; ++t)
2792 if (t->opcode_modifier.isstring)
2794 if (t >= current_templates->end)
2796 as_bad (_("expecting string instruction after `%s'"),
2797 expecting_string_instruction);
2800 for (override.start = t; t < current_templates->end; ++t)
2801 if (!t->opcode_modifier.isstring)
2804 current_templates = &override;
2811 parse_operands (char *l, const char *mnemonic)
2815 /* 1 if operand is pending after ','. */
2816 unsigned int expecting_operand = 0;
2818 /* Non-zero if operand parens not balanced. */
2819 unsigned int paren_not_balanced;
2821 while (*l != END_OF_INSN)
2823 /* Skip optional white space before operand. */
2824 if (is_space_char (*l))
2826 if (!is_operand_char (*l) && *l != END_OF_INSN)
2828 as_bad (_("invalid character %s before operand %d"),
2829 output_invalid (*l),
2833 token_start = l; /* after white space */
2834 paren_not_balanced = 0;
2835 while (paren_not_balanced || *l != ',')
2837 if (*l == END_OF_INSN)
2839 if (paren_not_balanced)
2842 as_bad (_("unbalanced parenthesis in operand %d."),
2845 as_bad (_("unbalanced brackets in operand %d."),
2850 break; /* we are done */
2852 else if (!is_operand_char (*l) && !is_space_char (*l))
2854 as_bad (_("invalid character %s in operand %d"),
2855 output_invalid (*l),
2862 ++paren_not_balanced;
2864 --paren_not_balanced;
2869 ++paren_not_balanced;
2871 --paren_not_balanced;
2875 if (l != token_start)
2876 { /* Yes, we've read in another operand. */
2877 unsigned int operand_ok;
2878 this_operand = i.operands++;
2879 i.types[this_operand].bitfield.unspecified = 1;
2880 if (i.operands > MAX_OPERANDS)
2882 as_bad (_("spurious operands; (%d operands/instruction max)"),
2886 /* Now parse operand adding info to 'i' as we go along. */
2887 END_STRING_AND_SAVE (l);
2891 i386_intel_operand (token_start,
2892 intel_float_operand (mnemonic));
2894 operand_ok = i386_att_operand (token_start);
2896 RESTORE_END_STRING (l);
2902 if (expecting_operand)
2904 expecting_operand_after_comma:
2905 as_bad (_("expecting operand after ','; got nothing"));
2910 as_bad (_("expecting operand before ','; got nothing"));
2915 /* Now *l must be either ',' or END_OF_INSN. */
2918 if (*++l == END_OF_INSN)
2920 /* Just skip it, if it's \n complain. */
2921 goto expecting_operand_after_comma;
2923 expecting_operand = 1;
2930 swap_2_operands (int xchg1, int xchg2)
2932 union i386_op temp_op;
2933 i386_operand_type temp_type;
2934 enum bfd_reloc_code_real temp_reloc;
2936 temp_type = i.types[xchg2];
2937 i.types[xchg2] = i.types[xchg1];
2938 i.types[xchg1] = temp_type;
2939 temp_op = i.op[xchg2];
2940 i.op[xchg2] = i.op[xchg1];
2941 i.op[xchg1] = temp_op;
2942 temp_reloc = i.reloc[xchg2];
2943 i.reloc[xchg2] = i.reloc[xchg1];
2944 i.reloc[xchg1] = temp_reloc;
2948 swap_operands (void)
2953 swap_2_operands (1, i.operands - 2);
2956 swap_2_operands (0, i.operands - 1);
2962 if (i.mem_operands == 2)
2964 const seg_entry *temp_seg;
2965 temp_seg = i.seg[0];
2966 i.seg[0] = i.seg[1];
2967 i.seg[1] = temp_seg;
2971 /* Try to ensure constant immediates are represented in the smallest
2976 char guess_suffix = 0;
2980 guess_suffix = i.suffix;
2981 else if (i.reg_operands)
2983 /* Figure out a suffix from the last register operand specified.
2984 We can't do this properly yet, ie. excluding InOutPortReg,
2985 but the following works for instructions with immediates.
2986 In any case, we can't set i.suffix yet. */
2987 for (op = i.operands; --op >= 0;)
2988 if (i.types[op].bitfield.reg8)
2990 guess_suffix = BYTE_MNEM_SUFFIX;
2993 else if (i.types[op].bitfield.reg16)
2995 guess_suffix = WORD_MNEM_SUFFIX;
2998 else if (i.types[op].bitfield.reg32)
3000 guess_suffix = LONG_MNEM_SUFFIX;
3003 else if (i.types[op].bitfield.reg64)
3005 guess_suffix = QWORD_MNEM_SUFFIX;
3009 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3010 guess_suffix = WORD_MNEM_SUFFIX;
3012 for (op = i.operands; --op >= 0;)
3013 if (operand_type_check (i.types[op], imm))
3015 switch (i.op[op].imms->X_op)
3018 /* If a suffix is given, this operand may be shortened. */
3019 switch (guess_suffix)
3021 case LONG_MNEM_SUFFIX:
3022 i.types[op].bitfield.imm32 = 1;
3023 i.types[op].bitfield.imm64 = 1;
3025 case WORD_MNEM_SUFFIX:
3026 i.types[op].bitfield.imm16 = 1;
3027 i.types[op].bitfield.imm32 = 1;
3028 i.types[op].bitfield.imm32s = 1;
3029 i.types[op].bitfield.imm64 = 1;
3031 case BYTE_MNEM_SUFFIX:
3032 i.types[op].bitfield.imm8 = 1;
3033 i.types[op].bitfield.imm8s = 1;
3034 i.types[op].bitfield.imm16 = 1;
3035 i.types[op].bitfield.imm32 = 1;
3036 i.types[op].bitfield.imm32s = 1;
3037 i.types[op].bitfield.imm64 = 1;
3041 /* If this operand is at most 16 bits, convert it
3042 to a signed 16 bit number before trying to see
3043 whether it will fit in an even smaller size.
3044 This allows a 16-bit operand such as $0xffe0 to
3045 be recognised as within Imm8S range. */
3046 if ((i.types[op].bitfield.imm16)
3047 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3049 i.op[op].imms->X_add_number =
3050 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3052 if ((i.types[op].bitfield.imm32)
3053 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3056 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3057 ^ ((offsetT) 1 << 31))
3058 - ((offsetT) 1 << 31));
3061 = operand_type_or (i.types[op],
3062 smallest_imm_type (i.op[op].imms->X_add_number));
3064 /* We must avoid matching of Imm32 templates when 64bit
3065 only immediate is available. */
3066 if (guess_suffix == QWORD_MNEM_SUFFIX)
3067 i.types[op].bitfield.imm32 = 0;
3074 /* Symbols and expressions. */
3076 /* Convert symbolic operand to proper sizes for matching, but don't
3077 prevent matching a set of insns that only supports sizes other
3078 than those matching the insn suffix. */
3080 i386_operand_type mask, allowed;
3084 UINTS_CLEAR (allowed);
3086 for (t = current_templates->start;
3087 t < current_templates->end;
3089 allowed = operand_type_or (allowed,
3090 t->operand_types[op]);
3091 switch (guess_suffix)
3093 case QWORD_MNEM_SUFFIX:
3094 mask.bitfield.imm64 = 1;
3095 mask.bitfield.imm32s = 1;
3097 case LONG_MNEM_SUFFIX:
3098 mask.bitfield.imm32 = 1;
3100 case WORD_MNEM_SUFFIX:
3101 mask.bitfield.imm16 = 1;
3103 case BYTE_MNEM_SUFFIX:
3104 mask.bitfield.imm8 = 1;
3109 allowed = operand_type_and (mask, allowed);
3110 if (!UINTS_ALL_ZERO (allowed))
3111 i.types[op] = operand_type_and (i.types[op], mask);
3118 /* Try to use the smallest displacement type too. */
3120 optimize_disp (void)
3124 for (op = i.operands; --op >= 0;)
3125 if (operand_type_check (i.types[op], disp))
3127 if (i.op[op].disps->X_op == O_constant)
3129 offsetT disp = i.op[op].disps->X_add_number;
3131 if (i.types[op].bitfield.disp16
3132 && (disp & ~(offsetT) 0xffff) == 0)
3134 /* If this operand is at most 16 bits, convert
3135 to a signed 16 bit number and don't use 64bit
3137 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3138 i.types[op].bitfield.disp64 = 0;
3140 if (i.types[op].bitfield.disp32
3141 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3143 /* If this operand is at most 32 bits, convert
3144 to a signed 32 bit number and don't use 64bit
3146 disp &= (((offsetT) 2 << 31) - 1);
3147 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3148 i.types[op].bitfield.disp64 = 0;
3150 if (!disp && i.types[op].bitfield.baseindex)
3152 i.types[op].bitfield.disp8 = 0;
3153 i.types[op].bitfield.disp16 = 0;
3154 i.types[op].bitfield.disp32 = 0;
3155 i.types[op].bitfield.disp32s = 0;
3156 i.types[op].bitfield.disp64 = 0;
3160 else if (flag_code == CODE_64BIT)
3162 if (fits_in_signed_long (disp))
3164 i.types[op].bitfield.disp64 = 0;
3165 i.types[op].bitfield.disp32s = 1;
3167 if (fits_in_unsigned_long (disp))
3168 i.types[op].bitfield.disp32 = 1;
3170 if ((i.types[op].bitfield.disp32
3171 || i.types[op].bitfield.disp32s
3172 || i.types[op].bitfield.disp16)
3173 && fits_in_signed_byte (disp))
3174 i.types[op].bitfield.disp8 = 1;
3176 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3177 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3179 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3180 i.op[op].disps, 0, i.reloc[op]);
3181 i.types[op].bitfield.disp8 = 0;
3182 i.types[op].bitfield.disp16 = 0;
3183 i.types[op].bitfield.disp32 = 0;
3184 i.types[op].bitfield.disp32s = 0;
3185 i.types[op].bitfield.disp64 = 0;
3188 /* We only support 64bit displacement on constants. */
3189 i.types[op].bitfield.disp64 = 0;
3194 match_template (void)
3196 /* Points to template once we've found it. */
3198 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3199 unsigned int found_reverse_match;
3200 i386_opcode_modifier suffix_check;
3201 i386_operand_type operand_types [MAX_OPERANDS];
3202 int addr_prefix_disp;
3204 unsigned int found_cpu_match;
3205 unsigned int check_register;
3207 #if MAX_OPERANDS != 4
3208 # error "MAX_OPERANDS must be 4."
3211 found_reverse_match = 0;
3212 addr_prefix_disp = -1;
3214 memset (&suffix_check, 0, sizeof (suffix_check));
3215 if (i.suffix == BYTE_MNEM_SUFFIX)
3216 suffix_check.no_bsuf = 1;
3217 else if (i.suffix == WORD_MNEM_SUFFIX)
3218 suffix_check.no_wsuf = 1;
3219 else if (i.suffix == SHORT_MNEM_SUFFIX)
3220 suffix_check.no_ssuf = 1;
3221 else if (i.suffix == LONG_MNEM_SUFFIX)
3222 suffix_check.no_lsuf = 1;
3223 else if (i.suffix == QWORD_MNEM_SUFFIX)
3224 suffix_check.no_qsuf = 1;
3225 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3226 suffix_check.no_ldsuf = 1;
3228 for (t = current_templates->start; t < current_templates->end; t++)
3230 addr_prefix_disp = -1;
3232 /* Must have right number of operands. */
3233 if (i.operands != t->operands)
3236 /* Check processor support. */
3237 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3238 if (!found_cpu_match)
3241 /* Check old gcc support. */
3242 if (!old_gcc && t->opcode_modifier.oldgcc)
3245 /* Check AT&T mnemonic. */
3246 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3249 /* Check AT&T syntax Intel syntax. */
3250 if ((intel_syntax && t->opcode_modifier.attsyntax)
3251 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3254 /* Check the suffix, except for some instructions in intel mode. */
3255 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3256 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3257 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3258 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3259 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3260 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3261 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3264 if (!operand_size_match (t))
3267 for (j = 0; j < MAX_OPERANDS; j++)
3268 operand_types[j] = t->operand_types[j];
3270 /* In general, don't allow 64-bit operands in 32-bit mode. */
3271 if (i.suffix == QWORD_MNEM_SUFFIX
3272 && flag_code != CODE_64BIT
3274 ? (!t->opcode_modifier.ignoresize
3275 && !intel_float_operand (t->name))
3276 : intel_float_operand (t->name) != 2)
3277 && ((!operand_types[0].bitfield.regmmx
3278 && !operand_types[0].bitfield.regxmm)
3279 || (!operand_types[t->operands > 1].bitfield.regmmx
3280 && !!operand_types[t->operands > 1].bitfield.regxmm))
3281 && (t->base_opcode != 0x0fc7
3282 || t->extension_opcode != 1 /* cmpxchg8b */))
3285 /* Do not verify operands when there are none. */
3289 /* We've found a match; break out of loop. */
3293 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3294 into Disp32/Disp16/Disp32 operand. */
3295 if (i.prefix[ADDR_PREFIX] != 0)
3297 /* There should be only one Disp operand. */
3301 for (j = 0; j < MAX_OPERANDS; j++)
3303 if (operand_types[j].bitfield.disp16)
3305 addr_prefix_disp = j;
3306 operand_types[j].bitfield.disp32 = 1;
3307 operand_types[j].bitfield.disp16 = 0;
3313 for (j = 0; j < MAX_OPERANDS; j++)
3315 if (operand_types[j].bitfield.disp32)
3317 addr_prefix_disp = j;
3318 operand_types[j].bitfield.disp32 = 0;
3319 operand_types[j].bitfield.disp16 = 1;
3325 for (j = 0; j < MAX_OPERANDS; j++)
3327 if (operand_types[j].bitfield.disp64)
3329 addr_prefix_disp = j;
3330 operand_types[j].bitfield.disp64 = 0;
3331 operand_types[j].bitfield.disp32 = 1;
3339 /* We check register size only if size of operands can be
3340 encoded the canonical way. */
3341 check_register = t->opcode_modifier.w;
3342 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3343 switch (t->operands)
3346 if (!operand_type_match (overlap0, i.types[0]))
3350 /* xchg %eax, %eax is a special case. It is an aliase for nop
3351 only in 32bit mode and we can use opcode 0x90. In 64bit
3352 mode, we can't use 0x90 for xchg %eax, %eax since it should
3353 zero-extend %eax to %rax. */
3354 if (flag_code == CODE_64BIT
3355 && t->base_opcode == 0x90
3356 && UINTS_EQUAL (i.types [0], acc32)
3357 && UINTS_EQUAL (i.types [1], acc32))
3361 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3362 if (!operand_type_match (overlap0, i.types[0])
3363 || !operand_type_match (overlap1, i.types[1])
3365 && !operand_type_register_match (overlap0, i.types[0],
3367 overlap1, i.types[1],
3370 /* Check if other direction is valid ... */
3371 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3374 /* Try reversing direction of operands. */
3375 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3376 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3377 if (!operand_type_match (overlap0, i.types[0])
3378 || !operand_type_match (overlap1, i.types[1])
3380 && !operand_type_register_match (overlap0,
3387 /* Does not match either direction. */
3390 /* found_reverse_match holds which of D or FloatDR
3392 if (t->opcode_modifier.d)
3393 found_reverse_match = Opcode_D;
3394 else if (t->opcode_modifier.floatd)
3395 found_reverse_match = Opcode_FloatD;
3397 found_reverse_match = 0;
3398 if (t->opcode_modifier.floatr)
3399 found_reverse_match |= Opcode_FloatR;
3403 /* Found a forward 2 operand match here. */
3404 switch (t->operands)
3407 overlap3 = operand_type_and (i.types[3],
3410 overlap2 = operand_type_and (i.types[2],
3415 switch (t->operands)
3418 if (!operand_type_match (overlap3, i.types[3])
3420 && !operand_type_register_match (overlap2,
3428 /* Here we make use of the fact that there are no
3429 reverse match 3 operand instructions, and all 3
3430 operand instructions only need to be checked for
3431 register consistency between operands 2 and 3. */
3432 if (!operand_type_match (overlap2, i.types[2])
3434 && !operand_type_register_match (overlap1,
3444 /* Found either forward/reverse 2, 3 or 4 operand match here:
3445 slip through to break. */
3447 if (!found_cpu_match)
3449 found_reverse_match = 0;
3452 /* We've found a match; break out of loop. */
3456 if (t == current_templates->end)
3458 /* We found no match. */
3459 as_bad (_("suffix or operands invalid for `%s'"),
3460 current_templates->start->name);
3464 if (!quiet_warnings)
3467 && (i.types[0].bitfield.jumpabsolute
3468 != operand_types[0].bitfield.jumpabsolute))
3470 as_warn (_("indirect %s without `*'"), t->name);
3473 if (t->opcode_modifier.isprefix
3474 && t->opcode_modifier.ignoresize)
3476 /* Warn them that a data or address size prefix doesn't
3477 affect assembly of the next line of code. */
3478 as_warn (_("stand-alone `%s' prefix"), t->name);
3482 /* Copy the template we found. */
3485 if (addr_prefix_disp != -1)
3486 i.tm.operand_types[addr_prefix_disp]
3487 = operand_types[addr_prefix_disp];
3489 if (found_reverse_match)
3491 /* If we found a reverse match we must alter the opcode
3492 direction bit. found_reverse_match holds bits to change
3493 (different for int & float insns). */
3495 i.tm.base_opcode ^= found_reverse_match;
3497 i.tm.operand_types[0] = operand_types[1];
3498 i.tm.operand_types[1] = operand_types[0];
3507 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3508 if (i.tm.operand_types[mem_op].bitfield.esseg)
3510 if (i.seg[0] != NULL && i.seg[0] != &es)
3512 as_bad (_("`%s' operand %d must use `%%es' segment"),
3517 /* There's only ever one segment override allowed per instruction.
3518 This instruction possibly has a legal segment override on the
3519 second operand, so copy the segment to where non-string
3520 instructions store it, allowing common code. */
3521 i.seg[0] = i.seg[1];
3523 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3525 if (i.seg[1] != NULL && i.seg[1] != &es)
3527 as_bad (_("`%s' operand %d must use `%%es' segment"),
3537 process_suffix (void)
3539 /* If matched instruction specifies an explicit instruction mnemonic
3541 if (i.tm.opcode_modifier.size16)
3542 i.suffix = WORD_MNEM_SUFFIX;
3543 else if (i.tm.opcode_modifier.size32)
3544 i.suffix = LONG_MNEM_SUFFIX;
3545 else if (i.tm.opcode_modifier.size64)
3546 i.suffix = QWORD_MNEM_SUFFIX;
3547 else if (i.reg_operands)
3549 /* If there's no instruction mnemonic suffix we try to invent one
3550 based on register operands. */
3553 /* We take i.suffix from the last register operand specified,
3554 Destination register type is more significant than source
3555 register type. crc32 in SSE4.2 prefers source register
3557 if (i.tm.base_opcode == 0xf20f38f1)
3559 if (i.types[0].bitfield.reg16)
3560 i.suffix = WORD_MNEM_SUFFIX;
3561 else if (i.types[0].bitfield.reg32)
3562 i.suffix = LONG_MNEM_SUFFIX;
3563 else if (i.types[0].bitfield.reg64)
3564 i.suffix = QWORD_MNEM_SUFFIX;
3566 else if (i.tm.base_opcode == 0xf20f38f0)
3568 if (i.types[0].bitfield.reg8)
3569 i.suffix = BYTE_MNEM_SUFFIX;
3576 if (i.tm.base_opcode == 0xf20f38f1
3577 || i.tm.base_opcode == 0xf20f38f0)
3579 /* We have to know the operand size for crc32. */
3580 as_bad (_("ambiguous memory operand size for `%s`"),
3585 for (op = i.operands; --op >= 0;)
3586 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3588 if (i.types[op].bitfield.reg8)
3590 i.suffix = BYTE_MNEM_SUFFIX;
3593 else if (i.types[op].bitfield.reg16)
3595 i.suffix = WORD_MNEM_SUFFIX;
3598 else if (i.types[op].bitfield.reg32)
3600 i.suffix = LONG_MNEM_SUFFIX;
3603 else if (i.types[op].bitfield.reg64)
3605 i.suffix = QWORD_MNEM_SUFFIX;
3611 else if (i.suffix == BYTE_MNEM_SUFFIX)
3613 if (!check_byte_reg ())
3616 else if (i.suffix == LONG_MNEM_SUFFIX)
3618 if (!check_long_reg ())
3621 else if (i.suffix == QWORD_MNEM_SUFFIX)
3624 && i.tm.opcode_modifier.ignoresize
3625 && i.tm.opcode_modifier.no_qsuf)
3627 else if (!check_qword_reg ())
3630 else if (i.suffix == WORD_MNEM_SUFFIX)
3632 if (!check_word_reg ())
3635 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3637 /* Skip if the instruction has x suffix. match_template
3638 should check if it is a valid suffix. */
3640 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3641 /* Do nothing if the instruction is going to ignore the prefix. */
3646 else if (i.tm.opcode_modifier.defaultsize
3648 /* exclude fldenv/frstor/fsave/fstenv */
3649 && i.tm.opcode_modifier.no_ssuf)
3651 i.suffix = stackop_size;
3653 else if (intel_syntax
3655 && (i.tm.operand_types[0].bitfield.jumpabsolute
3656 || i.tm.opcode_modifier.jumpbyte
3657 || i.tm.opcode_modifier.jumpintersegment
3658 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3659 && i.tm.extension_opcode <= 3)))
3664 if (!i.tm.opcode_modifier.no_qsuf)
3666 i.suffix = QWORD_MNEM_SUFFIX;
3670 if (!i.tm.opcode_modifier.no_lsuf)
3671 i.suffix = LONG_MNEM_SUFFIX;
3674 if (!i.tm.opcode_modifier.no_wsuf)
3675 i.suffix = WORD_MNEM_SUFFIX;
3684 if (i.tm.opcode_modifier.w)
3686 as_bad (_("no instruction mnemonic suffix given and "
3687 "no register operands; can't size instruction"));
3693 unsigned int suffixes;
3695 suffixes = !i.tm.opcode_modifier.no_bsuf;
3696 if (!i.tm.opcode_modifier.no_wsuf)
3698 if (!i.tm.opcode_modifier.no_lsuf)
3700 if (!i.tm.opcode_modifier.no_ldsuf)
3702 if (!i.tm.opcode_modifier.no_ssuf)
3704 if (!i.tm.opcode_modifier.no_qsuf)
3707 /* There are more than suffix matches. */
3708 if (i.tm.opcode_modifier.w
3709 || ((suffixes & (suffixes - 1))
3710 && !i.tm.opcode_modifier.defaultsize
3711 && !i.tm.opcode_modifier.ignoresize))
3713 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3719 /* Change the opcode based on the operand size given by i.suffix;
3720 We don't need to change things for byte insns. */
3723 && i.suffix != BYTE_MNEM_SUFFIX
3724 && i.suffix != XMMWORD_MNEM_SUFFIX)
3726 /* It's not a byte, select word/dword operation. */
3727 if (i.tm.opcode_modifier.w)
3729 if (i.tm.opcode_modifier.shortform)
3730 i.tm.base_opcode |= 8;
3732 i.tm.base_opcode |= 1;
3735 /* Now select between word & dword operations via the operand
3736 size prefix, except for instructions that will ignore this
3738 if (i.tm.opcode_modifier.addrprefixop0)
3740 /* The address size override prefix changes the size of the
3742 if ((flag_code == CODE_32BIT
3743 && i.op->regs[0].reg_type.bitfield.reg16)
3744 || (flag_code != CODE_32BIT
3745 && i.op->regs[0].reg_type.bitfield.reg32))
3746 if (!add_prefix (ADDR_PREFIX_OPCODE))
3749 else if (i.suffix != QWORD_MNEM_SUFFIX
3750 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3751 && !i.tm.opcode_modifier.ignoresize
3752 && !i.tm.opcode_modifier.floatmf
3753 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3754 || (flag_code == CODE_64BIT
3755 && i.tm.opcode_modifier.jumpbyte)))
3757 unsigned int prefix = DATA_PREFIX_OPCODE;
3759 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3760 prefix = ADDR_PREFIX_OPCODE;
3762 if (!add_prefix (prefix))
3766 /* Set mode64 for an operand. */
3767 if (i.suffix == QWORD_MNEM_SUFFIX
3768 && flag_code == CODE_64BIT
3769 && !i.tm.opcode_modifier.norex64)
3771 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3772 need rex64. cmpxchg8b is also a special case. */
3773 if (! (i.operands == 2
3774 && i.tm.base_opcode == 0x90
3775 && i.tm.extension_opcode == None
3776 && UINTS_EQUAL (i.types [0], acc64)
3777 && UINTS_EQUAL (i.types [1], acc64))
3778 && ! (i.operands == 1
3779 && i.tm.base_opcode == 0xfc7
3780 && i.tm.extension_opcode == 1
3781 && !operand_type_check (i.types [0], reg)
3782 && operand_type_check (i.types [0], anymem)))
3786 /* Size floating point instruction. */
3787 if (i.suffix == LONG_MNEM_SUFFIX)
3788 if (i.tm.opcode_modifier.floatmf)
3789 i.tm.base_opcode ^= 4;
3796 check_byte_reg (void)
3800 for (op = i.operands; --op >= 0;)
3802 /* If this is an eight bit register, it's OK. If it's the 16 or
3803 32 bit version of an eight bit register, we will just use the
3804 low portion, and that's OK too. */
3805 if (i.types[op].bitfield.reg8)
3808 /* Don't generate this warning if not needed. */
3809 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3812 /* crc32 doesn't generate this warning. */
3813 if (i.tm.base_opcode == 0xf20f38f0)
3816 if ((i.types[op].bitfield.reg16
3817 || i.types[op].bitfield.reg32
3818 || i.types[op].bitfield.reg64)
3819 && i.op[op].regs->reg_num < 4)
3821 /* Prohibit these changes in the 64bit mode, since the
3822 lowering is more complicated. */
3823 if (flag_code == CODE_64BIT
3824 && !i.tm.operand_types[op].bitfield.inoutportreg)
3826 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3827 register_prefix, i.op[op].regs->reg_name,
3831 #if REGISTER_WARNINGS
3833 && !i.tm.operand_types[op].bitfield.inoutportreg)
3834 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3836 (i.op[op].regs + (i.types[op].bitfield.reg16
3837 ? REGNAM_AL - REGNAM_AX
3838 : REGNAM_AL - REGNAM_EAX))->reg_name,
3840 i.op[op].regs->reg_name,
3845 /* Any other register is bad. */
3846 if (i.types[op].bitfield.reg16
3847 || i.types[op].bitfield.reg32
3848 || i.types[op].bitfield.reg64
3849 || i.types[op].bitfield.regmmx
3850 || i.types[op].bitfield.regxmm
3851 || i.types[op].bitfield.sreg2
3852 || i.types[op].bitfield.sreg3
3853 || i.types[op].bitfield.control
3854 || i.types[op].bitfield.debug
3855 || i.types[op].bitfield.test
3856 || i.types[op].bitfield.floatreg
3857 || i.types[op].bitfield.floatacc)
3859 as_bad (_("`%s%s' not allowed with `%s%c'"),
3861 i.op[op].regs->reg_name,
3871 check_long_reg (void)
3875 for (op = i.operands; --op >= 0;)
3876 /* Reject eight bit registers, except where the template requires
3877 them. (eg. movzb) */
3878 if (i.types[op].bitfield.reg8
3879 && (i.tm.operand_types[op].bitfield.reg16
3880 || i.tm.operand_types[op].bitfield.reg32
3881 || i.tm.operand_types[op].bitfield.acc))
3883 as_bad (_("`%s%s' not allowed with `%s%c'"),
3885 i.op[op].regs->reg_name,
3890 /* Warn if the e prefix on a general reg is missing. */
3891 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3892 && i.types[op].bitfield.reg16
3893 && (i.tm.operand_types[op].bitfield.reg32
3894 || i.tm.operand_types[op].bitfield.acc))
3896 /* Prohibit these changes in the 64bit mode, since the
3897 lowering is more complicated. */
3898 if (flag_code == CODE_64BIT)
3900 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3901 register_prefix, i.op[op].regs->reg_name,
3905 #if REGISTER_WARNINGS
3907 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3909 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3911 i.op[op].regs->reg_name,
3915 /* Warn if the r prefix on a general reg is missing. */
3916 else if (i.types[op].bitfield.reg64
3917 && (i.tm.operand_types[op].bitfield.reg32
3918 || i.tm.operand_types[op].bitfield.acc))
3921 && i.tm.opcode_modifier.toqword
3922 && !i.types[0].bitfield.regxmm)
3924 /* Convert to QWORD. We want REX byte. */
3925 i.suffix = QWORD_MNEM_SUFFIX;
3929 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3930 register_prefix, i.op[op].regs->reg_name,
3939 check_qword_reg (void)
3943 for (op = i.operands; --op >= 0; )
3944 /* Reject eight bit registers, except where the template requires
3945 them. (eg. movzb) */
3946 if (i.types[op].bitfield.reg8
3947 && (i.tm.operand_types[op].bitfield.reg16
3948 || i.tm.operand_types[op].bitfield.reg32
3949 || i.tm.operand_types[op].bitfield.acc))
3951 as_bad (_("`%s%s' not allowed with `%s%c'"),
3953 i.op[op].regs->reg_name,
3958 /* Warn if the e prefix on a general reg is missing. */
3959 else if ((i.types[op].bitfield.reg16
3960 || i.types[op].bitfield.reg32)
3961 && (i.tm.operand_types[op].bitfield.reg32
3962 || i.tm.operand_types[op].bitfield.acc))
3964 /* Prohibit these changes in the 64bit mode, since the
3965 lowering is more complicated. */
3967 && i.tm.opcode_modifier.todword
3968 && !i.types[0].bitfield.regxmm)
3970 /* Convert to DWORD. We don't want REX byte. */
3971 i.suffix = LONG_MNEM_SUFFIX;
3975 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3976 register_prefix, i.op[op].regs->reg_name,
3985 check_word_reg (void)
3988 for (op = i.operands; --op >= 0;)
3989 /* Reject eight bit registers, except where the template requires
3990 them. (eg. movzb) */
3991 if (i.types[op].bitfield.reg8
3992 && (i.tm.operand_types[op].bitfield.reg16
3993 || i.tm.operand_types[op].bitfield.reg32
3994 || i.tm.operand_types[op].bitfield.acc))
3996 as_bad (_("`%s%s' not allowed with `%s%c'"),
3998 i.op[op].regs->reg_name,
4003 /* Warn if the e prefix on a general reg is present. */
4004 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4005 && i.types[op].bitfield.reg32
4006 && (i.tm.operand_types[op].bitfield.reg16
4007 || i.tm.operand_types[op].bitfield.acc))
4009 /* Prohibit these changes in the 64bit mode, since the
4010 lowering is more complicated. */
4011 if (flag_code == CODE_64BIT)
4013 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4014 register_prefix, i.op[op].regs->reg_name,
4019 #if REGISTER_WARNINGS
4020 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4022 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4024 i.op[op].regs->reg_name,
4032 update_imm (unsigned int j)
4034 i386_operand_type overlap;
4036 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4037 if ((overlap.bitfield.imm8
4038 || overlap.bitfield.imm8s
4039 || overlap.bitfield.imm16
4040 || overlap.bitfield.imm32
4041 || overlap.bitfield.imm32s
4042 || overlap.bitfield.imm64)
4043 && !UINTS_EQUAL (overlap, imm8)
4044 && !UINTS_EQUAL (overlap, imm8s)
4045 && !UINTS_EQUAL (overlap, imm16)
4046 && !UINTS_EQUAL (overlap, imm32)
4047 && !UINTS_EQUAL (overlap, imm32s)
4048 && !UINTS_EQUAL (overlap, imm64))
4052 i386_operand_type temp;
4055 if (i.suffix == BYTE_MNEM_SUFFIX)
4057 temp.bitfield.imm8 = overlap.bitfield.imm8;
4058 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4060 else if (i.suffix == WORD_MNEM_SUFFIX)
4061 temp.bitfield.imm16 = overlap.bitfield.imm16;
4062 else if (i.suffix == QWORD_MNEM_SUFFIX)
4064 temp.bitfield.imm64 = overlap.bitfield.imm64;
4065 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4068 temp.bitfield.imm32 = overlap.bitfield.imm32;
4071 else if (UINTS_EQUAL (overlap, imm16_32_32s)
4072 || UINTS_EQUAL (overlap, imm16_32)
4073 || UINTS_EQUAL (overlap, imm16_32s))
4075 UINTS_CLEAR (overlap);
4076 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4077 overlap.bitfield.imm16 = 1;
4079 overlap.bitfield.imm32s = 1;
4081 if (!UINTS_EQUAL (overlap, imm8)
4082 && !UINTS_EQUAL (overlap, imm8s)
4083 && !UINTS_EQUAL (overlap, imm16)
4084 && !UINTS_EQUAL (overlap, imm32)
4085 && !UINTS_EQUAL (overlap, imm32s)
4086 && !UINTS_EQUAL (overlap, imm64))
4088 as_bad (_("no instruction mnemonic suffix given; "
4089 "can't determine immediate size"));
4093 i.types[j] = overlap;
4103 for (j = 0; j < 2; j++)
4104 if (update_imm (j) == 0)
4107 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4108 assert (operand_type_check (i.types[2], imm) == 0);
4116 i.drex.modrm_reg = 0;
4117 i.drex.modrm_regmem = 0;
4119 /* SSE5 4 operand instructions must have the destination the same as
4120 one of the inputs. Figure out the destination register and cache
4121 it away in the drex field, and remember which fields to use for
4123 if (i.tm.opcode_modifier.drex
4124 && i.tm.opcode_modifier.drexv
4127 i.tm.extension_opcode = None;
4129 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4130 if (i.types[0].bitfield.regxmm != 0
4131 && i.types[1].bitfield.regxmm != 0
4132 && i.types[2].bitfield.regxmm != 0
4133 && i.types[3].bitfield.regxmm != 0
4134 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4135 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4137 /* Clear the arguments that are stored in drex. */
4138 UINTS_CLEAR (i.types[0]);
4139 UINTS_CLEAR (i.types[3]);
4140 i.reg_operands -= 2;
4142 /* There are two different ways to encode a 4 operand
4143 instruction with all registers that uses OC1 set to
4144 0 or 1. Favor setting OC1 to 0 since this mimics the
4145 actions of other SSE5 assemblers. Use modrm encoding 2
4146 for register/register. Include the high order bit that
4147 is normally stored in the REX byte in the register
4149 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4150 i.drex.modrm_reg = 2;
4151 i.drex.modrm_regmem = 1;
4152 i.drex.reg = (i.op[3].regs->reg_num
4153 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4156 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4157 else if (i.types[0].bitfield.regxmm != 0
4158 && i.types[1].bitfield.regxmm != 0
4159 && (i.types[2].bitfield.regxmm
4160 || operand_type_check (i.types[2], anymem))
4161 && i.types[3].bitfield.regxmm != 0
4162 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4163 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4165 /* clear the arguments that are stored in drex */
4166 UINTS_CLEAR (i.types[0]);
4167 UINTS_CLEAR (i.types[3]);
4168 i.reg_operands -= 2;
4170 /* Specify the modrm encoding for memory addressing. Include
4171 the high order bit that is normally stored in the REX byte
4172 in the register field. */
4173 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4174 i.drex.modrm_reg = 1;
4175 i.drex.modrm_regmem = 2;
4176 i.drex.reg = (i.op[3].regs->reg_num
4177 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4180 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4181 else if (i.types[0].bitfield.regxmm != 0
4182 && operand_type_check (i.types[1], anymem) != 0
4183 && i.types[2].bitfield.regxmm != 0
4184 && i.types[3].bitfield.regxmm != 0
4185 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4186 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4188 /* Clear the arguments that are stored in drex. */
4189 UINTS_CLEAR (i.types[0]);
4190 UINTS_CLEAR (i.types[3]);
4191 i.reg_operands -= 2;
4193 /* Specify the modrm encoding for memory addressing. Include
4194 the high order bit that is normally stored in the REX byte
4195 in the register field. */
4196 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4197 i.drex.modrm_reg = 2;
4198 i.drex.modrm_regmem = 1;
4199 i.drex.reg = (i.op[3].regs->reg_num
4200 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4203 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4204 else if (i.types[0].bitfield.regxmm != 0
4205 && i.types[1].bitfield.regxmm != 0
4206 && i.types[2].bitfield.regxmm != 0
4207 && i.types[3].bitfield.regxmm != 0
4208 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4209 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4211 /* clear the arguments that are stored in drex */
4212 UINTS_CLEAR (i.types[2]);
4213 UINTS_CLEAR (i.types[3]);
4214 i.reg_operands -= 2;
4216 /* There are two different ways to encode a 4 operand
4217 instruction with all registers that uses OC1 set to
4218 0 or 1. Favor setting OC1 to 0 since this mimics the
4219 actions of other SSE5 assemblers. Use modrm encoding
4220 2 for register/register. Include the high order bit that
4221 is normally stored in the REX byte in the register
4223 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4224 i.drex.modrm_reg = 1;
4225 i.drex.modrm_regmem = 0;
4227 /* Remember the register, including the upper bits */
4228 i.drex.reg = (i.op[3].regs->reg_num
4229 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4232 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4233 else if (i.types[0].bitfield.regxmm != 0
4234 && (i.types[1].bitfield.regxmm
4235 || operand_type_check (i.types[1], anymem))
4236 && i.types[2].bitfield.regxmm != 0
4237 && i.types[3].bitfield.regxmm != 0
4238 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4239 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4241 /* Clear the arguments that are stored in drex. */
4242 UINTS_CLEAR (i.types[2]);
4243 UINTS_CLEAR (i.types[3]);
4244 i.reg_operands -= 2;
4246 /* Specify the modrm encoding and remember the register
4247 including the bits normally stored in the REX byte. */
4248 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4249 i.drex.modrm_reg = 0;
4250 i.drex.modrm_regmem = 1;
4251 i.drex.reg = (i.op[3].regs->reg_num
4252 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4255 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4256 else if (operand_type_check (i.types[0], anymem) != 0
4257 && i.types[1].bitfield.regxmm != 0
4258 && i.types[2].bitfield.regxmm != 0
4259 && i.types[3].bitfield.regxmm != 0
4260 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4261 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4263 /* clear the arguments that are stored in drex */
4264 UINTS_CLEAR (i.types[2]);
4265 UINTS_CLEAR (i.types[3]);
4266 i.reg_operands -= 2;
4268 /* Specify the modrm encoding and remember the register
4269 including the bits normally stored in the REX byte. */
4270 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4271 i.drex.modrm_reg = 1;
4272 i.drex.modrm_regmem = 0;
4273 i.drex.reg = (i.op[3].regs->reg_num
4274 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4278 as_bad (_("Incorrect operands for the '%s' instruction"),
4282 /* SSE5 instructions with the DREX byte where the only memory operand
4283 is in the 2nd argument, and the first and last xmm register must
4284 match, and is encoded in the DREX byte. */
4285 else if (i.tm.opcode_modifier.drex
4286 && !i.tm.opcode_modifier.drexv
4289 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4290 if (i.types[0].bitfield.regxmm != 0
4291 && (i.types[1].bitfield.regxmm
4292 || operand_type_check(i.types[1], anymem))
4293 && i.types[2].bitfield.regxmm != 0
4294 && i.types[3].bitfield.regxmm != 0
4295 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4296 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4298 /* clear the arguments that are stored in drex */
4299 UINTS_CLEAR (i.types[0]);
4300 UINTS_CLEAR (i.types[3]);
4301 i.reg_operands -= 2;
4303 /* Specify the modrm encoding and remember the register
4304 including the high bit normally stored in the REX
4306 i.drex.modrm_reg = 2;
4307 i.drex.modrm_regmem = 1;
4308 i.drex.reg = (i.op[3].regs->reg_num
4309 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4313 as_bad (_("Incorrect operands for the '%s' instruction"),
4317 /* SSE5 3 operand instructions that the result is a register, being
4318 either operand can be a memory operand, using OC0 to note which
4319 one is the memory. */
4320 else if (i.tm.opcode_modifier.drex
4321 && i.tm.opcode_modifier.drexv
4324 i.tm.extension_opcode = None;
4326 /* Case 1: 3 operand insn, src1 = register. */
4327 if (i.types[0].bitfield.regxmm != 0
4328 && i.types[1].bitfield.regxmm != 0
4329 && i.types[2].bitfield.regxmm != 0)
4331 /* Clear the arguments that are stored in drex. */
4332 UINTS_CLEAR (i.types[2]);
4335 /* Specify the modrm encoding and remember the register
4336 including the high bit normally stored in the REX byte. */
4337 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4338 i.drex.modrm_reg = 1;
4339 i.drex.modrm_regmem = 0;
4340 i.drex.reg = (i.op[2].regs->reg_num
4341 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4344 /* Case 2: 3 operand insn, src1 = memory. */
4345 else if (operand_type_check (i.types[0], anymem) != 0
4346 && i.types[1].bitfield.regxmm != 0
4347 && i.types[2].bitfield.regxmm != 0)
4349 /* Clear the arguments that are stored in drex. */
4350 UINTS_CLEAR (i.types[2]);
4353 /* Specify the modrm encoding and remember the register
4354 including the high bit normally stored in the REX
4356 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4357 i.drex.modrm_reg = 1;
4358 i.drex.modrm_regmem = 0;
4359 i.drex.reg = (i.op[2].regs->reg_num
4360 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4363 /* Case 3: 3 operand insn, src2 = memory. */
4364 else if (i.types[0].bitfield.regxmm != 0
4365 && operand_type_check (i.types[1], anymem) != 0
4366 && i.types[2].bitfield.regxmm != 0)
4368 /* Clear the arguments that are stored in drex. */
4369 UINTS_CLEAR (i.types[2]);
4372 /* Specify the modrm encoding and remember the register
4373 including the high bit normally stored in the REX byte. */
4374 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4375 i.drex.modrm_reg = 0;
4376 i.drex.modrm_regmem = 1;
4377 i.drex.reg = (i.op[2].regs->reg_num
4378 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4382 as_bad (_("Incorrect operands for the '%s' instruction"),
4386 /* SSE5 4 operand instructions that are the comparison instructions
4387 where the first operand is the immediate value of the comparison
4389 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4391 /* Case 1: 4 operand insn, src1 = reg/memory. */
4392 if (operand_type_check (i.types[0], imm) != 0
4393 && (i.types[1].bitfield.regxmm
4394 || operand_type_check (i.types[1], anymem))
4395 && i.types[2].bitfield.regxmm != 0
4396 && i.types[3].bitfield.regxmm != 0)
4398 /* clear the arguments that are stored in drex */
4399 UINTS_CLEAR (i.types[3]);
4402 /* Specify the modrm encoding and remember the register
4403 including the high bit normally stored in the REX byte. */
4404 i.drex.modrm_reg = 2;
4405 i.drex.modrm_regmem = 1;
4406 i.drex.reg = (i.op[3].regs->reg_num
4407 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4410 /* Case 2: 3 operand insn with ImmExt that places the
4411 opcode_extension as an immediate argument. This is used for
4412 all of the varients of comparison that supplies the appropriate
4413 value as part of the instruction. */
4414 else if ((i.types[0].bitfield.regxmm
4415 || operand_type_check (i.types[0], anymem))
4416 && i.types[1].bitfield.regxmm != 0
4417 && i.types[2].bitfield.regxmm != 0
4418 && operand_type_check (i.types[3], imm) != 0)
4420 /* clear the arguments that are stored in drex */
4421 UINTS_CLEAR (i.types[2]);
4424 /* Specify the modrm encoding and remember the register
4425 including the high bit normally stored in the REX byte. */
4426 i.drex.modrm_reg = 1;
4427 i.drex.modrm_regmem = 0;
4428 i.drex.reg = (i.op[2].regs->reg_num
4429 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4433 as_bad (_("Incorrect operands for the '%s' instruction"),
4437 else if (i.tm.opcode_modifier.drex
4438 || i.tm.opcode_modifier.drexv
4439 || i.tm.opcode_modifier.drexc)
4440 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4444 process_operands (void)
4446 /* Default segment register this instruction will use for memory
4447 accesses. 0 means unknown. This is only for optimizing out
4448 unnecessary segment overrides. */
4449 const seg_entry *default_seg = 0;
4451 /* Handle all of the DREX munging that SSE5 needs. */
4452 if (i.tm.opcode_modifier.drex
4453 || i.tm.opcode_modifier.drexv
4454 || i.tm.opcode_modifier.drexc)
4457 if (i.tm.opcode_modifier.firstxmm0)
4461 /* The first operand is implicit and must be xmm0. */
4462 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4463 if (i.op[0].regs->reg_num != 0)
4466 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4467 i.tm.name, register_prefix);
4469 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4470 i.tm.name, register_prefix);
4474 for (j = 1; j < i.operands; j++)
4476 i.op[j - 1] = i.op[j];
4477 i.types[j - 1] = i.types[j];
4479 /* We need to adjust fields in i.tm since they are used by
4480 build_modrm_byte. */
4481 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4488 else if (i.tm.opcode_modifier.regkludge)
4490 /* The imul $imm, %reg instruction is converted into
4491 imul $imm, %reg, %reg, and the clr %reg instruction
4492 is converted into xor %reg, %reg. */
4494 unsigned int first_reg_op;
4496 if (operand_type_check (i.types[0], reg))
4500 /* Pretend we saw the extra register operand. */
4501 assert (i.reg_operands == 1
4502 && i.op[first_reg_op + 1].regs == 0);
4503 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4504 i.types[first_reg_op + 1] = i.types[first_reg_op];
4509 if (i.tm.opcode_modifier.shortform)
4511 if (i.types[0].bitfield.sreg2
4512 || i.types[0].bitfield.sreg3)
4514 if (i.tm.base_opcode == POP_SEG_SHORT
4515 && i.op[0].regs->reg_num == 1)
4517 as_bad (_("you can't `pop %%cs'"));
4520 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4521 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4526 /* The register or float register operand is in operand
4530 if (i.types[0].bitfield.floatreg
4531 || operand_type_check (i.types[0], reg))
4535 /* Register goes in low 3 bits of opcode. */
4536 i.tm.base_opcode |= i.op[op].regs->reg_num;
4537 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4539 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4541 /* Warn about some common errors, but press on regardless.
4542 The first case can be generated by gcc (<= 2.8.1). */
4543 if (i.operands == 2)
4545 /* Reversed arguments on faddp, fsubp, etc. */
4546 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4547 register_prefix, i.op[1].regs->reg_name,
4548 register_prefix, i.op[0].regs->reg_name);
4552 /* Extraneous `l' suffix on fp insn. */
4553 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4554 register_prefix, i.op[0].regs->reg_name);
4559 else if (i.tm.opcode_modifier.modrm)
4561 /* The opcode is completed (modulo i.tm.extension_opcode which
4562 must be put into the modrm byte). Now, we make the modrm and
4563 index base bytes based on all the info we've collected. */
4565 default_seg = build_modrm_byte ();
4567 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4571 else if (i.tm.opcode_modifier.isstring)
4573 /* For the string instructions that allow a segment override
4574 on one of their operands, the default segment is ds. */
4578 if (i.tm.base_opcode == 0x8d /* lea */
4581 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4583 /* If a segment was explicitly specified, and the specified segment
4584 is not the default, use an opcode prefix to select it. If we
4585 never figured out what the default segment is, then default_seg
4586 will be zero at this point, and the specified segment prefix will
4588 if ((i.seg[0]) && (i.seg[0] != default_seg))
4590 if (!add_prefix (i.seg[0]->seg_prefix))
4596 static const seg_entry *
4597 build_modrm_byte (void)
4599 const seg_entry *default_seg = 0;
4601 /* SSE5 4 operand instructions are encoded in such a way that one of
4602 the inputs must match the destination register. Process_drex hides
4603 the 3rd argument in the drex field, so that by the time we get
4604 here, it looks to GAS as if this is a 2 operand instruction. */
4605 if ((i.tm.opcode_modifier.drex
4606 || i.tm.opcode_modifier.drexv
4607 || i.tm.opcode_modifier.drexc)
4608 && i.reg_operands == 2)
4610 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4611 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4613 i.rm.reg = reg->reg_num;
4614 i.rm.regmem = regmem->reg_num;
4616 if ((reg->reg_flags & RegRex) != 0)
4618 if ((regmem->reg_flags & RegRex) != 0)
4622 /* i.reg_operands MUST be the number of real register operands;
4623 implicit registers do not count. */
4624 else if (i.reg_operands == 2)
4626 unsigned int source, dest;
4634 /* When there are 3 operands, one of them may be immediate,
4635 which may be the first or the last operand. Otherwise,
4636 the first operand must be shift count register (cl). */
4637 assert (i.imm_operands == 1
4638 || (i.imm_operands == 0
4639 && i.types[0].bitfield.shiftcount));
4640 if (operand_type_check (i.types[0], imm)
4641 || i.types[0].bitfield.shiftcount)
4647 /* When there are 4 operands, the first two must be 8bit
4648 immediate operands. The source operand will be the 3rd
4650 assert (i.imm_operands == 2
4651 && i.types[0].bitfield.imm8
4652 && i.types[1].bitfield.imm8);
4662 /* One of the register operands will be encoded in the i.tm.reg
4663 field, the other in the combined i.tm.mode and i.tm.regmem
4664 fields. If no form of this instruction supports a memory
4665 destination operand, then we assume the source operand may
4666 sometimes be a memory operand and so we need to store the
4667 destination in the i.rm.reg field. */
4668 if (!i.tm.operand_types[dest].bitfield.regmem
4669 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4671 i.rm.reg = i.op[dest].regs->reg_num;
4672 i.rm.regmem = i.op[source].regs->reg_num;
4673 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4675 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4680 i.rm.reg = i.op[source].regs->reg_num;
4681 i.rm.regmem = i.op[dest].regs->reg_num;
4682 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4684 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4687 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4689 if (!i.types[0].bitfield.control
4690 && !i.types[1].bitfield.control)
4692 i.rex &= ~(REX_R | REX_B);
4693 add_prefix (LOCK_PREFIX_OPCODE);
4697 { /* If it's not 2 reg operands... */
4700 unsigned int fake_zero_displacement = 0;
4703 /* This has been precalculated for SSE5 instructions
4704 that have a DREX field earlier in process_drex. */
4705 if (i.tm.opcode_modifier.drex
4706 || i.tm.opcode_modifier.drexv
4707 || i.tm.opcode_modifier.drexc)
4708 op = i.drex.modrm_regmem;
4711 for (op = 0; op < i.operands; op++)
4712 if (operand_type_check (i.types[op], anymem))
4714 assert (op < i.operands);
4719 if (i.base_reg == 0)
4722 if (!i.disp_operands)
4723 fake_zero_displacement = 1;
4724 if (i.index_reg == 0)
4726 /* Operand is just <disp> */
4727 if (flag_code == CODE_64BIT)
4729 /* 64bit mode overwrites the 32bit absolute
4730 addressing by RIP relative addressing and
4731 absolute addressing is encoded by one of the
4732 redundant SIB forms. */
4733 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4734 i.sib.base = NO_BASE_REGISTER;
4735 i.sib.index = NO_INDEX_REGISTER;
4736 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4737 ? disp32s : disp32);
4739 else if ((flag_code == CODE_16BIT)
4740 ^ (i.prefix[ADDR_PREFIX] != 0))
4742 i.rm.regmem = NO_BASE_REGISTER_16;
4743 i.types[op] = disp16;
4747 i.rm.regmem = NO_BASE_REGISTER;
4748 i.types[op] = disp32;
4751 else /* !i.base_reg && i.index_reg */
4753 if (i.index_reg->reg_num == RegEiz
4754 || i.index_reg->reg_num == RegRiz)
4755 i.sib.index = NO_INDEX_REGISTER;
4757 i.sib.index = i.index_reg->reg_num;
4758 i.sib.base = NO_BASE_REGISTER;
4759 i.sib.scale = i.log2_scale_factor;
4760 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4761 i.types[op].bitfield.disp8 = 0;
4762 i.types[op].bitfield.disp16 = 0;
4763 i.types[op].bitfield.disp64 = 0;
4764 if (flag_code != CODE_64BIT)
4766 /* Must be 32 bit */
4767 i.types[op].bitfield.disp32 = 1;
4768 i.types[op].bitfield.disp32s = 0;
4772 i.types[op].bitfield.disp32 = 0;
4773 i.types[op].bitfield.disp32s = 1;
4775 if ((i.index_reg->reg_flags & RegRex) != 0)
4779 /* RIP addressing for 64bit mode. */
4780 else if (i.base_reg->reg_num == RegRip ||
4781 i.base_reg->reg_num == RegEip)
4783 i.rm.regmem = NO_BASE_REGISTER;
4784 i.types[op].bitfield.disp8 = 0;
4785 i.types[op].bitfield.disp16 = 0;
4786 i.types[op].bitfield.disp32 = 0;
4787 i.types[op].bitfield.disp32s = 1;
4788 i.types[op].bitfield.disp64 = 0;
4789 i.flags[op] |= Operand_PCrel;
4790 if (! i.disp_operands)
4791 fake_zero_displacement = 1;
4793 else if (i.base_reg->reg_type.bitfield.reg16)
4795 switch (i.base_reg->reg_num)
4798 if (i.index_reg == 0)
4800 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4801 i.rm.regmem = i.index_reg->reg_num - 6;
4805 if (i.index_reg == 0)
4808 if (operand_type_check (i.types[op], disp) == 0)
4810 /* fake (%bp) into 0(%bp) */
4811 i.types[op].bitfield.disp8 = 1;
4812 fake_zero_displacement = 1;
4815 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4816 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4818 default: /* (%si) -> 4 or (%di) -> 5 */
4819 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4821 i.rm.mode = mode_from_disp_size (i.types[op]);
4823 else /* i.base_reg and 32/64 bit mode */
4825 if (flag_code == CODE_64BIT
4826 && operand_type_check (i.types[op], disp))
4828 i386_operand_type temp;
4830 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4832 if (i.prefix[ADDR_PREFIX] == 0)
4833 i.types[op].bitfield.disp32s = 1;
4835 i.types[op].bitfield.disp32 = 1;
4838 i.rm.regmem = i.base_reg->reg_num;
4839 if ((i.base_reg->reg_flags & RegRex) != 0)
4841 i.sib.base = i.base_reg->reg_num;
4842 /* x86-64 ignores REX prefix bit here to avoid decoder
4844 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4847 if (i.disp_operands == 0)
4849 fake_zero_displacement = 1;
4850 i.types[op].bitfield.disp8 = 1;
4853 else if (i.base_reg->reg_num == ESP_REG_NUM)
4857 i.sib.scale = i.log2_scale_factor;
4858 if (i.index_reg == 0)
4860 /* <disp>(%esp) becomes two byte modrm with no index
4861 register. We've already stored the code for esp
4862 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4863 Any base register besides %esp will not use the
4864 extra modrm byte. */
4865 i.sib.index = NO_INDEX_REGISTER;
4869 if (i.index_reg->reg_num == RegEiz
4870 || i.index_reg->reg_num == RegRiz)
4871 i.sib.index = NO_INDEX_REGISTER;
4873 i.sib.index = i.index_reg->reg_num;
4874 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4875 if ((i.index_reg->reg_flags & RegRex) != 0)
4880 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4881 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4884 i.rm.mode = mode_from_disp_size (i.types[op]);
4887 if (fake_zero_displacement)
4889 /* Fakes a zero displacement assuming that i.types[op]
4890 holds the correct displacement size. */
4893 assert (i.op[op].disps == 0);
4894 exp = &disp_expressions[i.disp_operands++];
4895 i.op[op].disps = exp;
4896 exp->X_op = O_constant;
4897 exp->X_add_number = 0;
4898 exp->X_add_symbol = (symbolS *) 0;
4899 exp->X_op_symbol = (symbolS *) 0;
4903 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4904 (if any) based on i.tm.extension_opcode. Again, we must be
4905 careful to make sure that segment/control/debug/test/MMX
4906 registers are coded into the i.rm.reg field. */
4911 /* This has been precalculated for SSE5 instructions
4912 that have a DREX field earlier in process_drex. */
4913 if (i.tm.opcode_modifier.drex
4914 || i.tm.opcode_modifier.drexv
4915 || i.tm.opcode_modifier.drexc)
4917 op = i.drex.modrm_reg;
4918 i.rm.reg = i.op[op].regs->reg_num;
4919 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4924 for (op = 0; op < i.operands; op++)
4925 if (i.types[op].bitfield.reg8
4926 || i.types[op].bitfield.reg16
4927 || i.types[op].bitfield.reg32
4928 || i.types[op].bitfield.reg64
4929 || i.types[op].bitfield.regmmx
4930 || i.types[op].bitfield.regxmm
4931 || i.types[op].bitfield.sreg2
4932 || i.types[op].bitfield.sreg3
4933 || i.types[op].bitfield.control
4934 || i.types[op].bitfield.debug
4935 || i.types[op].bitfield.test)
4938 assert (op < i.operands);
4940 /* If there is an extension opcode to put here, the
4941 register number must be put into the regmem field. */
4942 if (i.tm.extension_opcode != None)
4944 i.rm.regmem = i.op[op].regs->reg_num;
4945 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4950 i.rm.reg = i.op[op].regs->reg_num;
4951 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4956 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4957 must set it to 3 to indicate this is a register operand
4958 in the regmem field. */
4959 if (!i.mem_operands)
4963 /* Fill in i.rm.reg field with extension opcode (if any). */
4964 if (i.tm.extension_opcode != None
4965 && !(i.tm.opcode_modifier.drex
4966 || i.tm.opcode_modifier.drexv
4967 || i.tm.opcode_modifier.drexc))
4968 i.rm.reg = i.tm.extension_opcode;
4974 output_branch (void)
4979 relax_substateT subtype;
4984 if (flag_code == CODE_16BIT)
4988 if (i.prefix[DATA_PREFIX] != 0)
4994 /* Pentium4 branch hints. */
4995 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4996 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5001 if (i.prefix[REX_PREFIX] != 0)
5007 if (i.prefixes != 0 && !intel_syntax)
5008 as_warn (_("skipping prefixes on this instruction"));
5010 /* It's always a symbol; End frag & setup for relax.
5011 Make sure there is enough room in this frag for the largest
5012 instruction we may generate in md_convert_frag. This is 2
5013 bytes for the opcode and room for the prefix and largest
5015 frag_grow (prefix + 2 + 4);
5016 /* Prefix and 1 opcode byte go in fr_fix. */
5017 p = frag_more (prefix + 1);
5018 if (i.prefix[DATA_PREFIX] != 0)
5019 *p++ = DATA_PREFIX_OPCODE;
5020 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5021 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5022 *p++ = i.prefix[SEG_PREFIX];
5023 if (i.prefix[REX_PREFIX] != 0)
5024 *p++ = i.prefix[REX_PREFIX];
5025 *p = i.tm.base_opcode;
5027 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5028 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5029 else if (cpu_arch_flags.bitfield.cpui386)
5030 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5032 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5035 sym = i.op[0].disps->X_add_symbol;
5036 off = i.op[0].disps->X_add_number;
5038 if (i.op[0].disps->X_op != O_constant
5039 && i.op[0].disps->X_op != O_symbol)
5041 /* Handle complex expressions. */
5042 sym = make_expr_symbol (i.op[0].disps);
5046 /* 1 possible extra opcode + 4 byte displacement go in var part.
5047 Pass reloc in fr_var. */
5048 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5058 if (i.tm.opcode_modifier.jumpbyte)
5060 /* This is a loop or jecxz type instruction. */
5062 if (i.prefix[ADDR_PREFIX] != 0)
5064 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5067 /* Pentium4 branch hints. */
5068 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5069 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5071 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5080 if (flag_code == CODE_16BIT)
5083 if (i.prefix[DATA_PREFIX] != 0)
5085 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5095 if (i.prefix[REX_PREFIX] != 0)
5097 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5101 if (i.prefixes != 0 && !intel_syntax)
5102 as_warn (_("skipping prefixes on this instruction"));
5104 p = frag_more (1 + size);
5105 *p++ = i.tm.base_opcode;
5107 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5108 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5110 /* All jumps handled here are signed, but don't use a signed limit
5111 check for 32 and 16 bit jumps as we want to allow wrap around at
5112 4G and 64k respectively. */
5114 fixP->fx_signed = 1;
5118 output_interseg_jump (void)
5126 if (flag_code == CODE_16BIT)
5130 if (i.prefix[DATA_PREFIX] != 0)
5136 if (i.prefix[REX_PREFIX] != 0)
5146 if (i.prefixes != 0 && !intel_syntax)
5147 as_warn (_("skipping prefixes on this instruction"));
5149 /* 1 opcode; 2 segment; offset */
5150 p = frag_more (prefix + 1 + 2 + size);
5152 if (i.prefix[DATA_PREFIX] != 0)
5153 *p++ = DATA_PREFIX_OPCODE;
5155 if (i.prefix[REX_PREFIX] != 0)
5156 *p++ = i.prefix[REX_PREFIX];
5158 *p++ = i.tm.base_opcode;
5159 if (i.op[1].imms->X_op == O_constant)
5161 offsetT n = i.op[1].imms->X_add_number;
5164 && !fits_in_unsigned_word (n)
5165 && !fits_in_signed_word (n))
5167 as_bad (_("16-bit jump out of range"));
5170 md_number_to_chars (p, n, size);
5173 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5174 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5175 if (i.op[0].imms->X_op != O_constant)
5176 as_bad (_("can't handle non absolute segment in `%s'"),
5178 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5184 fragS *insn_start_frag;
5185 offsetT insn_start_off;
5187 /* Tie dwarf2 debug info to the address at the start of the insn.
5188 We can't do this after the insn has been output as the current
5189 frag may have been closed off. eg. by frag_var. */
5190 dwarf2_emit_insn (0);
5192 insn_start_frag = frag_now;
5193 insn_start_off = frag_now_fix ();
5196 if (i.tm.opcode_modifier.jump)
5198 else if (i.tm.opcode_modifier.jumpbyte
5199 || i.tm.opcode_modifier.jumpdword)
5201 else if (i.tm.opcode_modifier.jumpintersegment)
5202 output_interseg_jump ();
5205 /* Output normal instructions here. */
5209 unsigned int prefix;
5211 switch (i.tm.opcode_length)
5214 if (i.tm.base_opcode & 0xff000000)
5216 prefix = (i.tm.base_opcode >> 24) & 0xff;
5221 if ((i.tm.base_opcode & 0xff0000) != 0)
5223 prefix = (i.tm.base_opcode >> 16) & 0xff;
5224 if (i.tm.cpu_flags.bitfield.cpupadlock)
5227 if (prefix != REPE_PREFIX_OPCODE
5228 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5229 add_prefix (prefix);
5232 add_prefix (prefix);
5241 /* The prefix bytes. */
5242 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5244 FRAG_APPEND_1_CHAR (*q);
5246 /* Now the opcode; be careful about word order here! */
5247 if (i.tm.opcode_length == 1)
5249 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5253 switch (i.tm.opcode_length)
5257 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5267 /* Put out high byte first: can't use md_number_to_chars! */
5268 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5269 *p = i.tm.base_opcode & 0xff;
5271 /* On SSE5, encode the OC1 bit in the DREX field if this
5272 encoding has multiple formats. */
5273 if (i.tm.opcode_modifier.drex
5274 && i.tm.opcode_modifier.drexv
5275 && DREX_OC1 (i.tm.extension_opcode))
5276 *p |= DREX_OC1_MASK;
5279 /* Now the modrm byte and sib byte (if present). */
5280 if (i.tm.opcode_modifier.modrm)
5282 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5285 /* If i.rm.regmem == ESP (4)
5286 && i.rm.mode != (Register mode)
5288 ==> need second modrm byte. */
5289 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5291 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5292 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5294 | i.sib.scale << 6));
5297 /* Write the DREX byte if needed. */
5298 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5301 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5303 /* Encode the OC0 bit if this encoding has multiple
5305 if ((i.tm.opcode_modifier.drex
5306 || i.tm.opcode_modifier.drexv)
5307 && DREX_OC0 (i.tm.extension_opcode))
5308 *p |= DREX_OC0_MASK;
5311 if (i.disp_operands)
5312 output_disp (insn_start_frag, insn_start_off);
5315 output_imm (insn_start_frag, insn_start_off);
5321 pi ("" /*line*/, &i);
5323 #endif /* DEBUG386 */
5326 /* Return the size of the displacement operand N. */
5329 disp_size (unsigned int n)
5332 if (i.types[n].bitfield.disp64)
5334 else if (i.types[n].bitfield.disp8)
5336 else if (i.types[n].bitfield.disp16)
5341 /* Return the size of the immediate operand N. */
5344 imm_size (unsigned int n)
5347 if (i.types[n].bitfield.imm64)
5349 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5351 else if (i.types[n].bitfield.imm16)
5357 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5362 for (n = 0; n < i.operands; n++)
5364 if (operand_type_check (i.types[n], disp))
5366 if (i.op[n].disps->X_op == O_constant)
5368 int size = disp_size (n);
5371 val = offset_in_range (i.op[n].disps->X_add_number,
5373 p = frag_more (size);
5374 md_number_to_chars (p, val, size);
5378 enum bfd_reloc_code_real reloc_type;
5379 int size = disp_size (n);
5380 int sign = i.types[n].bitfield.disp32s;
5381 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5383 /* We can't have 8 bit displacement here. */
5384 assert (!i.types[n].bitfield.disp8);
5386 /* The PC relative address is computed relative
5387 to the instruction boundary, so in case immediate
5388 fields follows, we need to adjust the value. */
5389 if (pcrel && i.imm_operands)
5394 for (n1 = 0; n1 < i.operands; n1++)
5395 if (operand_type_check (i.types[n1], imm))
5397 /* Only one immediate is allowed for PC
5398 relative address. */
5401 i.op[n].disps->X_add_number -= sz;
5403 /* We should find the immediate. */
5407 p = frag_more (size);
5408 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5410 && GOT_symbol == i.op[n].disps->X_add_symbol
5411 && (((reloc_type == BFD_RELOC_32
5412 || reloc_type == BFD_RELOC_X86_64_32S
5413 || (reloc_type == BFD_RELOC_64
5415 && (i.op[n].disps->X_op == O_symbol
5416 || (i.op[n].disps->X_op == O_add
5417 && ((symbol_get_value_expression
5418 (i.op[n].disps->X_op_symbol)->X_op)
5420 || reloc_type == BFD_RELOC_32_PCREL))
5424 if (insn_start_frag == frag_now)
5425 add = (p - frag_now->fr_literal) - insn_start_off;
5430 add = insn_start_frag->fr_fix - insn_start_off;
5431 for (fr = insn_start_frag->fr_next;
5432 fr && fr != frag_now; fr = fr->fr_next)
5434 add += p - frag_now->fr_literal;
5439 reloc_type = BFD_RELOC_386_GOTPC;
5440 i.op[n].imms->X_add_number += add;
5442 else if (reloc_type == BFD_RELOC_64)
5443 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5445 /* Don't do the adjustment for x86-64, as there
5446 the pcrel addressing is relative to the _next_
5447 insn, and that is taken care of in other code. */
5448 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5450 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5451 i.op[n].disps, pcrel, reloc_type);
5458 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5463 for (n = 0; n < i.operands; n++)
5465 if (operand_type_check (i.types[n], imm))
5467 if (i.op[n].imms->X_op == O_constant)
5469 int size = imm_size (n);
5472 val = offset_in_range (i.op[n].imms->X_add_number,
5474 p = frag_more (size);
5475 md_number_to_chars (p, val, size);
5479 /* Not absolute_section.
5480 Need a 32-bit fixup (don't support 8bit
5481 non-absolute imms). Try to support other
5483 enum bfd_reloc_code_real reloc_type;
5484 int size = imm_size (n);
5487 if (i.types[n].bitfield.imm32s
5488 && (i.suffix == QWORD_MNEM_SUFFIX
5489 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5494 p = frag_more (size);
5495 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5497 /* This is tough to explain. We end up with this one if we
5498 * have operands that look like
5499 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5500 * obtain the absolute address of the GOT, and it is strongly
5501 * preferable from a performance point of view to avoid using
5502 * a runtime relocation for this. The actual sequence of
5503 * instructions often look something like:
5508 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5510 * The call and pop essentially return the absolute address
5511 * of the label .L66 and store it in %ebx. The linker itself
5512 * will ultimately change the first operand of the addl so
5513 * that %ebx points to the GOT, but to keep things simple, the
5514 * .o file must have this operand set so that it generates not
5515 * the absolute address of .L66, but the absolute address of
5516 * itself. This allows the linker itself simply treat a GOTPC
5517 * relocation as asking for a pcrel offset to the GOT to be
5518 * added in, and the addend of the relocation is stored in the
5519 * operand field for the instruction itself.
5521 * Our job here is to fix the operand so that it would add
5522 * the correct offset so that %ebx would point to itself. The
5523 * thing that is tricky is that .-.L66 will point to the
5524 * beginning of the instruction, so we need to further modify
5525 * the operand so that it will point to itself. There are
5526 * other cases where you have something like:
5528 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5530 * and here no correction would be required. Internally in
5531 * the assembler we treat operands of this form as not being
5532 * pcrel since the '.' is explicitly mentioned, and I wonder
5533 * whether it would simplify matters to do it this way. Who
5534 * knows. In earlier versions of the PIC patches, the
5535 * pcrel_adjust field was used to store the correction, but
5536 * since the expression is not pcrel, I felt it would be
5537 * confusing to do it this way. */
5539 if ((reloc_type == BFD_RELOC_32
5540 || reloc_type == BFD_RELOC_X86_64_32S
5541 || reloc_type == BFD_RELOC_64)
5543 && GOT_symbol == i.op[n].imms->X_add_symbol
5544 && (i.op[n].imms->X_op == O_symbol
5545 || (i.op[n].imms->X_op == O_add
5546 && ((symbol_get_value_expression
5547 (i.op[n].imms->X_op_symbol)->X_op)
5552 if (insn_start_frag == frag_now)
5553 add = (p - frag_now->fr_literal) - insn_start_off;
5558 add = insn_start_frag->fr_fix - insn_start_off;
5559 for (fr = insn_start_frag->fr_next;
5560 fr && fr != frag_now; fr = fr->fr_next)
5562 add += p - frag_now->fr_literal;
5566 reloc_type = BFD_RELOC_386_GOTPC;
5568 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5570 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5571 i.op[n].imms->X_add_number += add;
5573 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5574 i.op[n].imms, 0, reloc_type);
5580 /* x86_cons_fix_new is called via the expression parsing code when a
5581 reloc is needed. We use this hook to get the correct .got reloc. */
5582 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5583 static int cons_sign = -1;
5586 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5589 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5591 got_reloc = NO_RELOC;
5594 if (exp->X_op == O_secrel)
5596 exp->X_op = O_symbol;
5597 r = BFD_RELOC_32_SECREL;
5601 fix_new_exp (frag, off, len, exp, 0, r);
5604 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5605 # define lex_got(reloc, adjust, types) NULL
5607 /* Parse operands of the form
5608 <symbol>@GOTOFF+<nnn>
5609 and similar .plt or .got references.
5611 If we find one, set up the correct relocation in RELOC and copy the
5612 input string, minus the `@GOTOFF' into a malloc'd buffer for
5613 parsing by the calling routine. Return this buffer, and if ADJUST
5614 is non-null set it to the length of the string we removed from the
5615 input line. Otherwise return NULL. */
5617 lex_got (enum bfd_reloc_code_real *reloc,
5619 i386_operand_type *types)
5621 /* Some of the relocations depend on the size of what field is to
5622 be relocated. But in our callers i386_immediate and i386_displacement
5623 we don't yet know the operand size (this will be set by insn
5624 matching). Hence we record the word32 relocation here,
5625 and adjust the reloc according to the real size in reloc(). */
5626 static const struct {
5628 const enum bfd_reloc_code_real rel[2];
5629 const i386_operand_type types64;
5632 BFD_RELOC_X86_64_PLTOFF64 },
5633 OPERAND_TYPE_IMM64 },
5634 { "PLT", { BFD_RELOC_386_PLT32,
5635 BFD_RELOC_X86_64_PLT32 },
5636 OPERAND_TYPE_IMM32_32S_DISP32 },
5638 BFD_RELOC_X86_64_GOTPLT64 },
5639 OPERAND_TYPE_IMM64_DISP64 },
5640 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5641 BFD_RELOC_X86_64_GOTOFF64 },
5642 OPERAND_TYPE_IMM64_DISP64 },
5644 BFD_RELOC_X86_64_GOTPCREL },
5645 OPERAND_TYPE_IMM32_32S_DISP32 },
5646 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5647 BFD_RELOC_X86_64_TLSGD },
5648 OPERAND_TYPE_IMM32_32S_DISP32 },
5649 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5651 OPERAND_TYPE_NONE },
5653 BFD_RELOC_X86_64_TLSLD },
5654 OPERAND_TYPE_IMM32_32S_DISP32 },
5655 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5656 BFD_RELOC_X86_64_GOTTPOFF },
5657 OPERAND_TYPE_IMM32_32S_DISP32 },
5658 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5659 BFD_RELOC_X86_64_TPOFF32 },
5660 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5661 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5663 OPERAND_TYPE_NONE },
5664 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5665 BFD_RELOC_X86_64_DTPOFF32 },
5667 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5668 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5670 OPERAND_TYPE_NONE },
5671 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5673 OPERAND_TYPE_NONE },
5674 { "GOT", { BFD_RELOC_386_GOT32,
5675 BFD_RELOC_X86_64_GOT32 },
5676 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5677 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5678 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5679 OPERAND_TYPE_IMM32_32S_DISP32 },
5680 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5681 BFD_RELOC_X86_64_TLSDESC_CALL },
5682 OPERAND_TYPE_IMM32_32S_DISP32 },
5690 for (cp = input_line_pointer; *cp != '@'; cp++)
5691 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5694 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5698 len = strlen (gotrel[j].str);
5699 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5701 if (gotrel[j].rel[object_64bit] != 0)
5704 char *tmpbuf, *past_reloc;
5706 *reloc = gotrel[j].rel[object_64bit];
5712 if (flag_code != CODE_64BIT)
5714 types->bitfield.imm32 = 1;
5715 types->bitfield.disp32 = 1;
5718 *types = gotrel[j].types64;
5721 if (GOT_symbol == NULL)
5722 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5724 /* The length of the first part of our input line. */
5725 first = cp - input_line_pointer;
5727 /* The second part goes from after the reloc token until
5728 (and including) an end_of_line char or comma. */
5729 past_reloc = cp + 1 + len;
5731 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5733 second = cp + 1 - past_reloc;
5735 /* Allocate and copy string. The trailing NUL shouldn't
5736 be necessary, but be safe. */
5737 tmpbuf = xmalloc (first + second + 2);
5738 memcpy (tmpbuf, input_line_pointer, first);
5739 if (second != 0 && *past_reloc != ' ')
5740 /* Replace the relocation token with ' ', so that
5741 errors like foo@GOTOFF1 will be detected. */
5742 tmpbuf[first++] = ' ';
5743 memcpy (tmpbuf + first, past_reloc, second);
5744 tmpbuf[first + second] = '\0';
5748 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5749 gotrel[j].str, 1 << (5 + object_64bit));
5754 /* Might be a symbol version string. Don't as_bad here. */
5759 x86_cons (expressionS *exp, int size)
5761 if (size == 4 || (object_64bit && size == 8))
5763 /* Handle @GOTOFF and the like in an expression. */
5765 char *gotfree_input_line;
5768 save = input_line_pointer;
5769 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5770 if (gotfree_input_line)
5771 input_line_pointer = gotfree_input_line;
5775 if (gotfree_input_line)
5777 /* expression () has merrily parsed up to the end of line,
5778 or a comma - in the wrong buffer. Transfer how far
5779 input_line_pointer has moved to the right buffer. */
5780 input_line_pointer = (save
5781 + (input_line_pointer - gotfree_input_line)
5783 free (gotfree_input_line);
5784 if (exp->X_op == O_constant
5785 || exp->X_op == O_absent
5786 || exp->X_op == O_illegal
5787 || exp->X_op == O_register
5788 || exp->X_op == O_big)
5790 char c = *input_line_pointer;
5791 *input_line_pointer = 0;
5792 as_bad (_("missing or invalid expression `%s'"), save);
5793 *input_line_pointer = c;
5802 static void signed_cons (int size)
5804 if (flag_code == CODE_64BIT)
5812 pe_directive_secrel (dummy)
5813 int dummy ATTRIBUTE_UNUSED;
5820 if (exp.X_op == O_symbol)
5821 exp.X_op = O_secrel;
5823 emit_expr (&exp, 4);
5825 while (*input_line_pointer++ == ',');
5827 input_line_pointer--;
5828 demand_empty_rest_of_line ();
5833 i386_immediate (char *imm_start)
5835 char *save_input_line_pointer;
5836 char *gotfree_input_line;
5839 i386_operand_type types;
5841 UINTS_SET (types, ~0);
5843 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5845 as_bad (_("at most %d immediate operands are allowed"),
5846 MAX_IMMEDIATE_OPERANDS);
5850 exp = &im_expressions[i.imm_operands++];
5851 i.op[this_operand].imms = exp;
5853 if (is_space_char (*imm_start))
5856 save_input_line_pointer = input_line_pointer;
5857 input_line_pointer = imm_start;
5859 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5860 if (gotfree_input_line)
5861 input_line_pointer = gotfree_input_line;
5863 exp_seg = expression (exp);
5866 if (*input_line_pointer)
5867 as_bad (_("junk `%s' after expression"), input_line_pointer);
5869 input_line_pointer = save_input_line_pointer;
5870 if (gotfree_input_line)
5871 free (gotfree_input_line);
5873 if (exp->X_op == O_absent
5874 || exp->X_op == O_illegal
5875 || exp->X_op == O_big
5876 || (gotfree_input_line
5877 && (exp->X_op == O_constant
5878 || exp->X_op == O_register)))
5880 as_bad (_("missing or invalid immediate expression `%s'"),
5884 else if (exp->X_op == O_constant)
5886 /* Size it properly later. */
5887 i.types[this_operand].bitfield.imm64 = 1;
5888 /* If BFD64, sign extend val. */
5889 if (!use_rela_relocations
5890 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5892 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5894 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5895 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5896 && exp_seg != absolute_section
5897 && exp_seg != text_section
5898 && exp_seg != data_section
5899 && exp_seg != bss_section
5900 && exp_seg != undefined_section
5901 && !bfd_is_com_section (exp_seg))
5903 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5907 else if (!intel_syntax && exp->X_op == O_register)
5909 as_bad (_("illegal immediate register operand %s"), imm_start);
5914 /* This is an address. The size of the address will be
5915 determined later, depending on destination register,
5916 suffix, or the default for the section. */
5917 i.types[this_operand].bitfield.imm8 = 1;
5918 i.types[this_operand].bitfield.imm16 = 1;
5919 i.types[this_operand].bitfield.imm32 = 1;
5920 i.types[this_operand].bitfield.imm32s = 1;
5921 i.types[this_operand].bitfield.imm64 = 1;
5922 i.types[this_operand] = operand_type_and (i.types[this_operand],
5930 i386_scale (char *scale)
5933 char *save = input_line_pointer;
5935 input_line_pointer = scale;
5936 val = get_absolute_expression ();
5941 i.log2_scale_factor = 0;
5944 i.log2_scale_factor = 1;
5947 i.log2_scale_factor = 2;
5950 i.log2_scale_factor = 3;
5954 char sep = *input_line_pointer;
5956 *input_line_pointer = '\0';
5957 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5959 *input_line_pointer = sep;
5960 input_line_pointer = save;
5964 if (i.log2_scale_factor != 0 && i.index_reg == 0)
5966 as_warn (_("scale factor of %d without an index register"),
5967 1 << i.log2_scale_factor);
5968 i.log2_scale_factor = 0;
5970 scale = input_line_pointer;
5971 input_line_pointer = save;
5976 i386_displacement (char *disp_start, char *disp_end)
5980 char *save_input_line_pointer;
5981 char *gotfree_input_line;
5983 i386_operand_type bigdisp, types = anydisp;
5986 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5988 as_bad (_("at most %d displacement operands are allowed"),
5989 MAX_MEMORY_OPERANDS);
5993 UINTS_CLEAR (bigdisp);
5994 if ((i.types[this_operand].bitfield.jumpabsolute)
5995 || (!current_templates->start->opcode_modifier.jump
5996 && !current_templates->start->opcode_modifier.jumpdword))
5998 bigdisp.bitfield.disp32 = 1;
5999 override = (i.prefix[ADDR_PREFIX] != 0);
6000 if (flag_code == CODE_64BIT)
6004 bigdisp.bitfield.disp32s = 1;
6005 bigdisp.bitfield.disp64 = 1;
6008 else if ((flag_code == CODE_16BIT) ^ override)
6010 bigdisp.bitfield.disp32 = 0;
6011 bigdisp.bitfield.disp16 = 1;
6016 /* For PC-relative branches, the width of the displacement
6017 is dependent upon data size, not address size. */
6018 override = (i.prefix[DATA_PREFIX] != 0);
6019 if (flag_code == CODE_64BIT)
6021 if (override || i.suffix == WORD_MNEM_SUFFIX)
6022 bigdisp.bitfield.disp16 = 1;
6025 bigdisp.bitfield.disp32 = 1;
6026 bigdisp.bitfield.disp32s = 1;
6032 override = (i.suffix == (flag_code != CODE_16BIT
6034 : LONG_MNEM_SUFFIX));
6035 bigdisp.bitfield.disp32 = 1;
6036 if ((flag_code == CODE_16BIT) ^ override)
6038 bigdisp.bitfield.disp32 = 0;
6039 bigdisp.bitfield.disp16 = 1;
6043 i.types[this_operand] = operand_type_or (i.types[this_operand],
6046 exp = &disp_expressions[i.disp_operands];
6047 i.op[this_operand].disps = exp;
6049 save_input_line_pointer = input_line_pointer;
6050 input_line_pointer = disp_start;
6051 END_STRING_AND_SAVE (disp_end);
6053 #ifndef GCC_ASM_O_HACK
6054 #define GCC_ASM_O_HACK 0
6057 END_STRING_AND_SAVE (disp_end + 1);
6058 if (i.types[this_operand].bitfield.baseIndex
6059 && displacement_string_end[-1] == '+')
6061 /* This hack is to avoid a warning when using the "o"
6062 constraint within gcc asm statements.
6065 #define _set_tssldt_desc(n,addr,limit,type) \
6066 __asm__ __volatile__ ( \
6068 "movw %w1,2+%0\n\t" \
6070 "movb %b1,4+%0\n\t" \
6071 "movb %4,5+%0\n\t" \
6072 "movb $0,6+%0\n\t" \
6073 "movb %h1,7+%0\n\t" \
6075 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6077 This works great except that the output assembler ends
6078 up looking a bit weird if it turns out that there is
6079 no offset. You end up producing code that looks like:
6092 So here we provide the missing zero. */
6094 *displacement_string_end = '0';
6097 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6098 if (gotfree_input_line)
6099 input_line_pointer = gotfree_input_line;
6101 exp_seg = expression (exp);
6104 if (*input_line_pointer)
6105 as_bad (_("junk `%s' after expression"), input_line_pointer);
6107 RESTORE_END_STRING (disp_end + 1);
6109 input_line_pointer = save_input_line_pointer;
6110 if (gotfree_input_line)
6111 free (gotfree_input_line);
6114 /* We do this to make sure that the section symbol is in
6115 the symbol table. We will ultimately change the relocation
6116 to be relative to the beginning of the section. */
6117 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6118 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6119 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6121 if (exp->X_op != O_symbol)
6124 if (S_IS_LOCAL (exp->X_add_symbol)
6125 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6126 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6127 exp->X_op = O_subtract;
6128 exp->X_op_symbol = GOT_symbol;
6129 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6130 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6131 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6132 i.reloc[this_operand] = BFD_RELOC_64;
6134 i.reloc[this_operand] = BFD_RELOC_32;
6137 else if (exp->X_op == O_absent
6138 || exp->X_op == O_illegal
6139 || exp->X_op == O_big
6140 || (gotfree_input_line
6141 && (exp->X_op == O_constant
6142 || exp->X_op == O_register)))
6145 as_bad (_("missing or invalid displacement expression `%s'"),
6150 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6151 else if (exp->X_op != O_constant
6152 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6153 && exp_seg != absolute_section
6154 && exp_seg != text_section
6155 && exp_seg != data_section
6156 && exp_seg != bss_section
6157 && exp_seg != undefined_section
6158 && !bfd_is_com_section (exp_seg))
6160 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6165 RESTORE_END_STRING (disp_end);
6167 /* Check if this is a displacement only operand. */
6168 bigdisp = i.types[this_operand];
6169 bigdisp.bitfield.disp8 = 0;
6170 bigdisp.bitfield.disp16 = 0;
6171 bigdisp.bitfield.disp32 = 0;
6172 bigdisp.bitfield.disp32s = 0;
6173 bigdisp.bitfield.disp64 = 0;
6174 if (UINTS_ALL_ZERO (bigdisp))
6175 i.types[this_operand] = operand_type_and (i.types[this_operand],
6181 /* Make sure the memory operand we've been dealt is valid.
6182 Return 1 on success, 0 on a failure. */
6185 i386_index_check (const char *operand_string)
6188 #if INFER_ADDR_PREFIX
6194 if (flag_code == CODE_64BIT)
6197 && ((i.prefix[ADDR_PREFIX] == 0
6198 && !i.base_reg->reg_type.bitfield.reg64)
6199 || (i.prefix[ADDR_PREFIX]
6200 && !i.base_reg->reg_type.bitfield.reg32))
6202 || i.base_reg->reg_num !=
6203 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6205 && (!i.index_reg->reg_type.bitfield.baseindex
6206 || (i.prefix[ADDR_PREFIX] == 0
6207 && i.index_reg->reg_num != RegRiz
6208 && !i.index_reg->reg_type.bitfield.reg64
6210 || (i.prefix[ADDR_PREFIX]
6211 && i.index_reg->reg_num != RegEiz
6212 && !i.index_reg->reg_type.bitfield.reg32))))
6217 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6221 && (!i.base_reg->reg_type.bitfield.reg16
6222 || !i.base_reg->reg_type.bitfield.baseindex))
6224 && (!i.index_reg->reg_type.bitfield.reg16
6225 || !i.index_reg->reg_type.bitfield.baseindex
6227 && i.base_reg->reg_num < 6
6228 && i.index_reg->reg_num >= 6
6229 && i.log2_scale_factor == 0))))
6236 && !i.base_reg->reg_type.bitfield.reg32)
6238 && ((!i.index_reg->reg_type.bitfield.reg32
6239 && i.index_reg->reg_num != RegEiz)
6240 || !i.index_reg->reg_type.bitfield.baseindex)))
6246 #if INFER_ADDR_PREFIX
6247 if (i.prefix[ADDR_PREFIX] == 0)
6249 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6251 /* Change the size of any displacement too. At most one of
6252 Disp16 or Disp32 is set.
6253 FIXME. There doesn't seem to be any real need for separate
6254 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6255 Removing them would probably clean up the code quite a lot. */
6256 if (flag_code != CODE_64BIT
6257 && (i.types[this_operand].bitfield.disp16
6258 || i.types[this_operand].bitfield.disp32))
6259 i.types[this_operand]
6260 = operand_type_xor (i.types[this_operand], disp16_32);
6265 as_bad (_("`%s' is not a valid base/index expression"),
6269 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6271 flag_code_names[flag_code]);
6276 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6280 i386_att_operand (char *operand_string)
6284 char *op_string = operand_string;
6286 if (is_space_char (*op_string))
6289 /* We check for an absolute prefix (differentiating,
6290 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6291 if (*op_string == ABSOLUTE_PREFIX)
6294 if (is_space_char (*op_string))
6296 i.types[this_operand].bitfield.jumpabsolute = 1;
6299 /* Check if operand is a register. */
6300 if ((r = parse_register (op_string, &end_op)) != NULL)
6302 i386_operand_type temp;
6304 /* Check for a segment override by searching for ':' after a
6305 segment register. */
6307 if (is_space_char (*op_string))
6309 if (*op_string == ':'
6310 && (r->reg_type.bitfield.sreg2
6311 || r->reg_type.bitfield.sreg3))
6316 i.seg[i.mem_operands] = &es;
6319 i.seg[i.mem_operands] = &cs;
6322 i.seg[i.mem_operands] = &ss;
6325 i.seg[i.mem_operands] = &ds;
6328 i.seg[i.mem_operands] = &fs;
6331 i.seg[i.mem_operands] = &gs;
6335 /* Skip the ':' and whitespace. */
6337 if (is_space_char (*op_string))
6340 if (!is_digit_char (*op_string)
6341 && !is_identifier_char (*op_string)
6342 && *op_string != '('
6343 && *op_string != ABSOLUTE_PREFIX)
6345 as_bad (_("bad memory operand `%s'"), op_string);
6348 /* Handle case of %es:*foo. */
6349 if (*op_string == ABSOLUTE_PREFIX)
6352 if (is_space_char (*op_string))
6354 i.types[this_operand].bitfield.jumpabsolute = 1;
6356 goto do_memory_reference;
6360 as_bad (_("junk `%s' after register"), op_string);
6364 temp.bitfield.baseindex = 0;
6365 i.types[this_operand] = operand_type_or (i.types[this_operand],
6367 i.types[this_operand].bitfield.unspecified = 0;
6368 i.op[this_operand].regs = r;
6371 else if (*op_string == REGISTER_PREFIX)
6373 as_bad (_("bad register name `%s'"), op_string);
6376 else if (*op_string == IMMEDIATE_PREFIX)
6379 if (i.types[this_operand].bitfield.jumpabsolute)
6381 as_bad (_("immediate operand illegal with absolute jump"));
6384 if (!i386_immediate (op_string))
6387 else if (is_digit_char (*op_string)
6388 || is_identifier_char (*op_string)
6389 || *op_string == '(')
6391 /* This is a memory reference of some sort. */
6394 /* Start and end of displacement string expression (if found). */
6395 char *displacement_string_start;
6396 char *displacement_string_end;
6398 do_memory_reference:
6399 if ((i.mem_operands == 1
6400 && !current_templates->start->opcode_modifier.isstring)
6401 || i.mem_operands == 2)
6403 as_bad (_("too many memory references for `%s'"),
6404 current_templates->start->name);
6408 /* Check for base index form. We detect the base index form by
6409 looking for an ')' at the end of the operand, searching
6410 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6412 base_string = op_string + strlen (op_string);
6415 if (is_space_char (*base_string))
6418 /* If we only have a displacement, set-up for it to be parsed later. */
6419 displacement_string_start = op_string;
6420 displacement_string_end = base_string + 1;
6422 if (*base_string == ')')
6425 unsigned int parens_balanced = 1;
6426 /* We've already checked that the number of left & right ()'s are
6427 equal, so this loop will not be infinite. */
6431 if (*base_string == ')')
6433 if (*base_string == '(')
6436 while (parens_balanced);
6438 temp_string = base_string;
6440 /* Skip past '(' and whitespace. */
6442 if (is_space_char (*base_string))
6445 if (*base_string == ','
6446 || ((i.base_reg = parse_register (base_string, &end_op))
6449 displacement_string_end = temp_string;
6451 i.types[this_operand].bitfield.baseindex = 1;
6455 base_string = end_op;
6456 if (is_space_char (*base_string))
6460 /* There may be an index reg or scale factor here. */
6461 if (*base_string == ',')
6464 if (is_space_char (*base_string))
6467 if ((i.index_reg = parse_register (base_string, &end_op))
6470 base_string = end_op;
6471 if (is_space_char (*base_string))
6473 if (*base_string == ',')
6476 if (is_space_char (*base_string))
6479 else if (*base_string != ')')
6481 as_bad (_("expecting `,' or `)' "
6482 "after index register in `%s'"),
6487 else if (*base_string == REGISTER_PREFIX)
6489 as_bad (_("bad register name `%s'"), base_string);
6493 /* Check for scale factor. */
6494 if (*base_string != ')')
6496 char *end_scale = i386_scale (base_string);
6501 base_string = end_scale;
6502 if (is_space_char (*base_string))
6504 if (*base_string != ')')
6506 as_bad (_("expecting `)' "
6507 "after scale factor in `%s'"),
6512 else if (!i.index_reg)
6514 as_bad (_("expecting index register or scale factor "
6515 "after `,'; got '%c'"),
6520 else if (*base_string != ')')
6522 as_bad (_("expecting `,' or `)' "
6523 "after base register in `%s'"),
6528 else if (*base_string == REGISTER_PREFIX)
6530 as_bad (_("bad register name `%s'"), base_string);
6535 /* If there's an expression beginning the operand, parse it,
6536 assuming displacement_string_start and
6537 displacement_string_end are meaningful. */
6538 if (displacement_string_start != displacement_string_end)
6540 if (!i386_displacement (displacement_string_start,
6541 displacement_string_end))
6545 /* Special case for (%dx) while doing input/output op. */
6547 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
6549 && i.log2_scale_factor == 0
6550 && i.seg[i.mem_operands] == 0
6551 && !operand_type_check (i.types[this_operand], disp))
6553 UINTS_CLEAR (i.types[this_operand]);
6554 i.types[this_operand].bitfield.inoutportreg = 1;
6558 if (i386_index_check (operand_string) == 0)
6560 i.types[this_operand].bitfield.mem = 1;
6565 /* It's not a memory operand; argh! */
6566 as_bad (_("invalid char %s beginning operand %d `%s'"),
6567 output_invalid (*op_string),
6572 return 1; /* Normal return. */
6575 /* md_estimate_size_before_relax()
6577 Called just before relax() for rs_machine_dependent frags. The x86
6578 assembler uses these frags to handle variable size jump
6581 Any symbol that is now undefined will not become defined.
6582 Return the correct fr_subtype in the frag.
6583 Return the initial "guess for variable size of frag" to caller.
6584 The guess is actually the growth beyond the fixed part. Whatever
6585 we do to grow the fixed or variable part contributes to our
6589 md_estimate_size_before_relax (fragP, segment)
6593 /* We've already got fragP->fr_subtype right; all we have to do is
6594 check for un-relaxable symbols. On an ELF system, we can't relax
6595 an externally visible symbol, because it may be overridden by a
6597 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6598 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6600 && (S_IS_EXTERNAL (fragP->fr_symbol)
6601 || S_IS_WEAK (fragP->fr_symbol)))
6605 /* Symbol is undefined in this segment, or we need to keep a
6606 reloc so that weak symbols can be overridden. */
6607 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6608 enum bfd_reloc_code_real reloc_type;
6609 unsigned char *opcode;
6612 if (fragP->fr_var != NO_RELOC)
6613 reloc_type = fragP->fr_var;
6615 reloc_type = BFD_RELOC_16_PCREL;
6617 reloc_type = BFD_RELOC_32_PCREL;
6619 old_fr_fix = fragP->fr_fix;
6620 opcode = (unsigned char *) fragP->fr_opcode;
6622 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6625 /* Make jmp (0xeb) a (d)word displacement jump. */
6627 fragP->fr_fix += size;
6628 fix_new (fragP, old_fr_fix, size,
6630 fragP->fr_offset, 1,
6636 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6638 /* Negate the condition, and branch past an
6639 unconditional jump. */
6642 /* Insert an unconditional jump. */
6644 /* We added two extra opcode bytes, and have a two byte
6646 fragP->fr_fix += 2 + 2;
6647 fix_new (fragP, old_fr_fix + 2, 2,
6649 fragP->fr_offset, 1,
6656 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6661 fixP = fix_new (fragP, old_fr_fix, 1,
6663 fragP->fr_offset, 1,
6665 fixP->fx_signed = 1;
6669 /* This changes the byte-displacement jump 0x7N
6670 to the (d)word-displacement jump 0x0f,0x8N. */
6671 opcode[1] = opcode[0] + 0x10;
6672 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6673 /* We've added an opcode byte. */
6674 fragP->fr_fix += 1 + size;
6675 fix_new (fragP, old_fr_fix + 1, size,
6677 fragP->fr_offset, 1,
6682 BAD_CASE (fragP->fr_subtype);
6686 return fragP->fr_fix - old_fr_fix;
6689 /* Guess size depending on current relax state. Initially the relax
6690 state will correspond to a short jump and we return 1, because
6691 the variable part of the frag (the branch offset) is one byte
6692 long. However, we can relax a section more than once and in that
6693 case we must either set fr_subtype back to the unrelaxed state,
6694 or return the value for the appropriate branch. */
6695 return md_relax_table[fragP->fr_subtype].rlx_length;
6698 /* Called after relax() is finished.
6700 In: Address of frag.
6701 fr_type == rs_machine_dependent.
6702 fr_subtype is what the address relaxed to.
6704 Out: Any fixSs and constants are set up.
6705 Caller will turn frag into a ".space 0". */
6708 md_convert_frag (abfd, sec, fragP)
6709 bfd *abfd ATTRIBUTE_UNUSED;
6710 segT sec ATTRIBUTE_UNUSED;
6713 unsigned char *opcode;
6714 unsigned char *where_to_put_displacement = NULL;
6715 offsetT target_address;
6716 offsetT opcode_address;
6717 unsigned int extension = 0;
6718 offsetT displacement_from_opcode_start;
6720 opcode = (unsigned char *) fragP->fr_opcode;
6722 /* Address we want to reach in file space. */
6723 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6725 /* Address opcode resides at in file space. */
6726 opcode_address = fragP->fr_address + fragP->fr_fix;
6728 /* Displacement from opcode start to fill into instruction. */
6729 displacement_from_opcode_start = target_address - opcode_address;
6731 if ((fragP->fr_subtype & BIG) == 0)
6733 /* Don't have to change opcode. */
6734 extension = 1; /* 1 opcode + 1 displacement */
6735 where_to_put_displacement = &opcode[1];
6739 if (no_cond_jump_promotion
6740 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6741 as_warn_where (fragP->fr_file, fragP->fr_line,
6742 _("long jump required"));
6744 switch (fragP->fr_subtype)
6746 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6747 extension = 4; /* 1 opcode + 4 displacement */
6749 where_to_put_displacement = &opcode[1];
6752 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6753 extension = 2; /* 1 opcode + 2 displacement */
6755 where_to_put_displacement = &opcode[1];
6758 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6759 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6760 extension = 5; /* 2 opcode + 4 displacement */
6761 opcode[1] = opcode[0] + 0x10;
6762 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6763 where_to_put_displacement = &opcode[2];
6766 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6767 extension = 3; /* 2 opcode + 2 displacement */
6768 opcode[1] = opcode[0] + 0x10;
6769 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6770 where_to_put_displacement = &opcode[2];
6773 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6778 where_to_put_displacement = &opcode[3];
6782 BAD_CASE (fragP->fr_subtype);
6787 /* If size if less then four we are sure that the operand fits,
6788 but if it's 4, then it could be that the displacement is larger
6790 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6792 && ((addressT) (displacement_from_opcode_start - extension
6793 + ((addressT) 1 << 31))
6794 > (((addressT) 2 << 31) - 1)))
6796 as_bad_where (fragP->fr_file, fragP->fr_line,
6797 _("jump target out of range"));
6798 /* Make us emit 0. */
6799 displacement_from_opcode_start = extension;
6801 /* Now put displacement after opcode. */
6802 md_number_to_chars ((char *) where_to_put_displacement,
6803 (valueT) (displacement_from_opcode_start - extension),
6804 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6805 fragP->fr_fix += extension;
6808 /* Apply a fixup (fixS) to segment data, once it has been determined
6809 by our caller that we have all the info we need to fix it up.
6811 On the 386, immediates, displacements, and data pointers are all in
6812 the same (little-endian) format, so we don't need to care about which
6816 md_apply_fix (fixP, valP, seg)
6817 /* The fix we're to put in. */
6819 /* Pointer to the value of the bits. */
6821 /* Segment fix is from. */
6822 segT seg ATTRIBUTE_UNUSED;
6824 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6825 valueT value = *valP;
6827 #if !defined (TE_Mach)
6830 switch (fixP->fx_r_type)
6836 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6839 case BFD_RELOC_X86_64_32S:
6840 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6843 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6846 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6851 if (fixP->fx_addsy != NULL
6852 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6853 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6854 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6855 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6856 && !use_rela_relocations)
6858 /* This is a hack. There should be a better way to handle this.
6859 This covers for the fact that bfd_install_relocation will
6860 subtract the current location (for partial_inplace, PC relative
6861 relocations); see more below. */
6865 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6868 value += fixP->fx_where + fixP->fx_frag->fr_address;
6870 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6873 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6876 || (symbol_section_p (fixP->fx_addsy)
6877 && sym_seg != absolute_section))
6878 && !generic_force_reloc (fixP))
6880 /* Yes, we add the values in twice. This is because
6881 bfd_install_relocation subtracts them out again. I think
6882 bfd_install_relocation is broken, but I don't dare change
6884 value += fixP->fx_where + fixP->fx_frag->fr_address;
6888 #if defined (OBJ_COFF) && defined (TE_PE)
6889 /* For some reason, the PE format does not store a
6890 section address offset for a PC relative symbol. */
6891 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6892 || S_IS_WEAK (fixP->fx_addsy))
6893 value += md_pcrel_from (fixP);
6897 /* Fix a few things - the dynamic linker expects certain values here,
6898 and we must not disappoint it. */
6899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6900 if (IS_ELF && fixP->fx_addsy)
6901 switch (fixP->fx_r_type)
6903 case BFD_RELOC_386_PLT32:
6904 case BFD_RELOC_X86_64_PLT32:
6905 /* Make the jump instruction point to the address of the operand. At
6906 runtime we merely add the offset to the actual PLT entry. */
6910 case BFD_RELOC_386_TLS_GD:
6911 case BFD_RELOC_386_TLS_LDM:
6912 case BFD_RELOC_386_TLS_IE_32:
6913 case BFD_RELOC_386_TLS_IE:
6914 case BFD_RELOC_386_TLS_GOTIE:
6915 case BFD_RELOC_386_TLS_GOTDESC:
6916 case BFD_RELOC_X86_64_TLSGD:
6917 case BFD_RELOC_X86_64_TLSLD:
6918 case BFD_RELOC_X86_64_GOTTPOFF:
6919 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6920 value = 0; /* Fully resolved at runtime. No addend. */
6922 case BFD_RELOC_386_TLS_LE:
6923 case BFD_RELOC_386_TLS_LDO_32:
6924 case BFD_RELOC_386_TLS_LE_32:
6925 case BFD_RELOC_X86_64_DTPOFF32:
6926 case BFD_RELOC_X86_64_DTPOFF64:
6927 case BFD_RELOC_X86_64_TPOFF32:
6928 case BFD_RELOC_X86_64_TPOFF64:
6929 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6932 case BFD_RELOC_386_TLS_DESC_CALL:
6933 case BFD_RELOC_X86_64_TLSDESC_CALL:
6934 value = 0; /* Fully resolved at runtime. No addend. */
6935 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6939 case BFD_RELOC_386_GOT32:
6940 case BFD_RELOC_X86_64_GOT32:
6941 value = 0; /* Fully resolved at runtime. No addend. */
6944 case BFD_RELOC_VTABLE_INHERIT:
6945 case BFD_RELOC_VTABLE_ENTRY:
6952 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
6954 #endif /* !defined (TE_Mach) */
6956 /* Are we finished with this relocation now? */
6957 if (fixP->fx_addsy == NULL)
6959 else if (use_rela_relocations)
6961 fixP->fx_no_overflow = 1;
6962 /* Remember value for tc_gen_reloc. */
6963 fixP->fx_addnumber = value;
6967 md_number_to_chars (p, value, fixP->fx_size);
6971 md_atof (int type, char *litP, int *sizeP)
6973 /* This outputs the LITTLENUMs in REVERSE order;
6974 in accord with the bigendian 386. */
6975 return ieee_md_atof (type, litP, sizeP, FALSE);
6978 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
6981 output_invalid (int c)
6984 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6987 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6988 "(0x%x)", (unsigned char) c);
6989 return output_invalid_buf;
6992 /* REG_STRING starts *before* REGISTER_PREFIX. */
6994 static const reg_entry *
6995 parse_real_register (char *reg_string, char **end_op)
6997 char *s = reg_string;
6999 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7002 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7003 if (*s == REGISTER_PREFIX)
7006 if (is_space_char (*s))
7010 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7012 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7013 return (const reg_entry *) NULL;
7017 /* For naked regs, make sure that we are not dealing with an identifier.
7018 This prevents confusing an identifier like `eax_var' with register
7020 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7021 return (const reg_entry *) NULL;
7025 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7027 /* Handle floating point regs, allowing spaces in the (i) part. */
7028 if (r == i386_regtab /* %st is first entry of table */)
7030 if (is_space_char (*s))
7035 if (is_space_char (*s))
7037 if (*s >= '0' && *s <= '7')
7041 if (is_space_char (*s))
7046 r = hash_find (reg_hash, "st(0)");
7051 /* We have "%st(" then garbage. */
7052 return (const reg_entry *) NULL;
7056 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7059 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7060 return (const reg_entry *) NULL;
7063 && ((r->reg_flags & (RegRex64 | RegRex))
7064 || r->reg_type.bitfield.reg64)
7065 && (!cpu_arch_flags.bitfield.cpulm
7066 || !UINTS_EQUAL (r->reg_type, control))
7067 && flag_code != CODE_64BIT)
7068 return (const reg_entry *) NULL;
7073 /* REG_STRING starts *before* REGISTER_PREFIX. */
7075 static const reg_entry *
7076 parse_register (char *reg_string, char **end_op)
7080 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7081 r = parse_real_register (reg_string, end_op);
7086 char *save = input_line_pointer;
7090 input_line_pointer = reg_string;
7091 c = get_symbol_end ();
7092 symbolP = symbol_find (reg_string);
7093 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7095 const expressionS *e = symbol_get_value_expression (symbolP);
7097 know (e->X_op == O_register);
7098 know (e->X_add_number >= 0
7099 && (valueT) e->X_add_number < i386_regtab_size);
7100 r = i386_regtab + e->X_add_number;
7101 *end_op = input_line_pointer;
7103 *input_line_pointer = c;
7104 input_line_pointer = save;
7110 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7113 char *end = input_line_pointer;
7116 r = parse_register (name, &input_line_pointer);
7117 if (r && end <= input_line_pointer)
7119 *nextcharP = *input_line_pointer;
7120 *input_line_pointer = 0;
7121 e->X_op = O_register;
7122 e->X_add_number = r - i386_regtab;
7125 input_line_pointer = end;
7131 md_operand (expressionS *e)
7133 if (*input_line_pointer == REGISTER_PREFIX)
7136 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7140 e->X_op = O_register;
7141 e->X_add_number = r - i386_regtab;
7142 input_line_pointer = end;
7148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7149 const char *md_shortopts = "kVQ:sqn";
7151 const char *md_shortopts = "qn";
7154 #define OPTION_32 (OPTION_MD_BASE + 0)
7155 #define OPTION_64 (OPTION_MD_BASE + 1)
7156 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7157 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7158 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7159 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7160 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7161 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7162 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7163 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7165 struct option md_longopts[] =
7167 {"32", no_argument, NULL, OPTION_32},
7168 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7169 {"64", no_argument, NULL, OPTION_64},
7171 {"divide", no_argument, NULL, OPTION_DIVIDE},
7172 {"march", required_argument, NULL, OPTION_MARCH},
7173 {"mtune", required_argument, NULL, OPTION_MTUNE},
7174 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7175 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7176 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7177 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7178 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7179 {NULL, no_argument, NULL, 0}
7181 size_t md_longopts_size = sizeof (md_longopts);
7184 md_parse_option (int c, char *arg)
7192 optimize_align_code = 0;
7199 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7200 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7201 should be emitted or not. FIXME: Not implemented. */
7205 /* -V: SVR4 argument to print version ID. */
7207 print_version_id ();
7210 /* -k: Ignore for FreeBSD compatibility. */
7215 /* -s: On i386 Solaris, this tells the native assembler to use
7216 .stab instead of .stab.excl. We always use .stab anyhow. */
7219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7222 const char **list, **l;
7224 list = bfd_target_list ();
7225 for (l = list; *l != NULL; l++)
7226 if (CONST_STRNEQ (*l, "elf64-x86-64")
7227 || strcmp (*l, "coff-x86-64") == 0
7228 || strcmp (*l, "pe-x86-64") == 0
7229 || strcmp (*l, "pei-x86-64") == 0)
7231 default_arch = "x86_64";
7235 as_fatal (_("No compiled in support for x86_64"));
7242 default_arch = "i386";
7246 #ifdef SVR4_COMMENT_CHARS
7251 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7253 for (s = i386_comment_chars; *s != '\0'; s++)
7257 i386_comment_chars = n;
7263 arch = xstrdup (arg);
7267 as_fatal (_("Invalid -march= option: `%s'"), arg);
7268 next = strchr (arch, '+');
7271 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7273 if (strcmp (arch, cpu_arch [i].name) == 0)
7276 cpu_arch_name = cpu_arch[i].name;
7277 cpu_sub_arch_name = NULL;
7278 cpu_arch_flags = cpu_arch[i].flags;
7279 cpu_arch_isa = cpu_arch[i].type;
7280 cpu_arch_isa_flags = cpu_arch[i].flags;
7281 if (!cpu_arch_tune_set)
7283 cpu_arch_tune = cpu_arch_isa;
7284 cpu_arch_tune_flags = cpu_arch_isa_flags;
7288 else if (*cpu_arch [i].name == '.'
7289 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7291 /* ISA entension. */
7292 i386_cpu_flags flags;
7293 flags = cpu_flags_or (cpu_arch_flags,
7295 if (!UINTS_EQUAL (flags, cpu_arch_flags))
7297 if (cpu_sub_arch_name)
7299 char *name = cpu_sub_arch_name;
7300 cpu_sub_arch_name = concat (name,
7306 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7307 cpu_arch_flags = flags;
7313 if (i >= ARRAY_SIZE (cpu_arch))
7314 as_fatal (_("Invalid -march= option: `%s'"), arg);
7318 while (next != NULL );
7323 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7324 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7326 if (strcmp (arg, cpu_arch [i].name) == 0)
7328 cpu_arch_tune_set = 1;
7329 cpu_arch_tune = cpu_arch [i].type;
7330 cpu_arch_tune_flags = cpu_arch[i].flags;
7334 if (i >= ARRAY_SIZE (cpu_arch))
7335 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7338 case OPTION_MMNEMONIC:
7339 if (strcasecmp (arg, "att") == 0)
7341 else if (strcasecmp (arg, "intel") == 0)
7344 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7347 case OPTION_MSYNTAX:
7348 if (strcasecmp (arg, "att") == 0)
7350 else if (strcasecmp (arg, "intel") == 0)
7353 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7356 case OPTION_MINDEX_REG:
7357 allow_index_reg = 1;
7360 case OPTION_MNAKED_REG:
7361 allow_naked_reg = 1;
7364 case OPTION_MOLD_GCC:
7375 md_show_usage (stream)
7378 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7379 fprintf (stream, _("\
7381 -V print assembler version number\n\
7384 fprintf (stream, _("\
7385 -n Do not optimize code alignment\n\
7386 -q quieten some warnings\n"));
7387 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7388 fprintf (stream, _("\
7391 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7392 fprintf (stream, _("\
7393 --32/--64 generate 32bit/64bit code\n"));
7395 #ifdef SVR4_COMMENT_CHARS
7396 fprintf (stream, _("\
7397 --divide do not treat `/' as a comment character\n"));
7399 fprintf (stream, _("\
7400 --divide ignored\n"));
7402 fprintf (stream, _("\
7403 -march=CPU[,+EXTENSION...]\n\
7404 generate code for CPU and EXTENSION, CPU is one of:\n\
7405 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7406 core, core2, k6, athlon, k8, generic32, generic64\n\
7407 EXTENSION is combination of:\n\
7408 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7409 vmx, smx, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\
7411 fprintf (stream, _("\
7412 -mtune=CPU optimize for CPU, where CPU is one of:\n\
7413 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
7414 core, core2, k6, athlon, k8, generic32, generic64\n"));
7415 fprintf (stream, _("\
7416 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7417 fprintf (stream, _("\
7418 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7419 fprintf (stream, _("\
7420 -mindex-reg support pseudo index registers\n"));
7421 fprintf (stream, _("\
7422 -mnaked-reg don't require `%%' prefix for registers\n"));
7423 fprintf (stream, _("\
7424 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7427 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7428 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7430 /* Pick the target format to use. */
7433 i386_target_format (void)
7435 if (!strcmp (default_arch, "x86_64"))
7437 set_code_flag (CODE_64BIT);
7438 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7440 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7441 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7442 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7443 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7444 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7445 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7446 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7447 cpu_arch_isa_flags.bitfield.cpummx= 1;
7448 cpu_arch_isa_flags.bitfield.cpusse = 1;
7449 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7451 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7453 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7454 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7455 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7456 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7457 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7458 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7459 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7460 cpu_arch_tune_flags.bitfield.cpummx= 1;
7461 cpu_arch_tune_flags.bitfield.cpusse = 1;
7462 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7465 else if (!strcmp (default_arch, "i386"))
7467 set_code_flag (CODE_32BIT);
7468 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
7470 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7471 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7472 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7474 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
7476 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7477 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7478 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7482 as_fatal (_("Unknown architecture"));
7483 switch (OUTPUT_FLAVOR)
7486 case bfd_target_coff_flavour:
7487 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7490 #ifdef OBJ_MAYBE_AOUT
7491 case bfd_target_aout_flavour:
7492 return AOUT_TARGET_FORMAT;
7494 #ifdef OBJ_MAYBE_COFF
7495 case bfd_target_coff_flavour:
7498 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7499 case bfd_target_elf_flavour:
7501 if (flag_code == CODE_64BIT)
7504 use_rela_relocations = 1;
7506 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7515 #endif /* OBJ_MAYBE_ more than one */
7517 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7519 i386_elf_emit_arch_note (void)
7521 if (IS_ELF && cpu_arch_name != NULL)
7524 asection *seg = now_seg;
7525 subsegT subseg = now_subseg;
7526 Elf_Internal_Note i_note;
7527 Elf_External_Note e_note;
7528 asection *note_secp;
7531 /* Create the .note section. */
7532 note_secp = subseg_new (".note", 0);
7533 bfd_set_section_flags (stdoutput,
7535 SEC_HAS_CONTENTS | SEC_READONLY);
7537 /* Process the arch string. */
7538 len = strlen (cpu_arch_name);
7540 i_note.namesz = len + 1;
7542 i_note.type = NT_ARCH;
7543 p = frag_more (sizeof (e_note.namesz));
7544 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7545 p = frag_more (sizeof (e_note.descsz));
7546 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7547 p = frag_more (sizeof (e_note.type));
7548 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7549 p = frag_more (len + 1);
7550 strcpy (p, cpu_arch_name);
7552 frag_align (2, 0, 0);
7554 subseg_set (seg, subseg);
7560 md_undefined_symbol (name)
7563 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7564 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7565 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7566 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7570 if (symbol_find (name))
7571 as_bad (_("GOT already in symbol table"));
7572 GOT_symbol = symbol_new (name, undefined_section,
7573 (valueT) 0, &zero_address_frag);
7580 /* Round up a section size to the appropriate boundary. */
7583 md_section_align (segment, size)
7584 segT segment ATTRIBUTE_UNUSED;
7587 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7588 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7590 /* For a.out, force the section size to be aligned. If we don't do
7591 this, BFD will align it for us, but it will not write out the
7592 final bytes of the section. This may be a bug in BFD, but it is
7593 easier to fix it here since that is how the other a.out targets
7597 align = bfd_get_section_alignment (stdoutput, segment);
7598 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7605 /* On the i386, PC-relative offsets are relative to the start of the
7606 next instruction. That is, the address of the offset, plus its
7607 size, since the offset is always the last part of the insn. */
7610 md_pcrel_from (fixS *fixP)
7612 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7618 s_bss (int ignore ATTRIBUTE_UNUSED)
7622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7624 obj_elf_section_change_hook ();
7626 temp = get_absolute_expression ();
7627 subseg_set (bss_section, (subsegT) temp);
7628 demand_empty_rest_of_line ();
7634 i386_validate_fix (fixS *fixp)
7636 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7638 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7642 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7647 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7649 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7656 tc_gen_reloc (section, fixp)
7657 asection *section ATTRIBUTE_UNUSED;
7661 bfd_reloc_code_real_type code;
7663 switch (fixp->fx_r_type)
7665 case BFD_RELOC_X86_64_PLT32:
7666 case BFD_RELOC_X86_64_GOT32:
7667 case BFD_RELOC_X86_64_GOTPCREL:
7668 case BFD_RELOC_386_PLT32:
7669 case BFD_RELOC_386_GOT32:
7670 case BFD_RELOC_386_GOTOFF:
7671 case BFD_RELOC_386_GOTPC:
7672 case BFD_RELOC_386_TLS_GD:
7673 case BFD_RELOC_386_TLS_LDM:
7674 case BFD_RELOC_386_TLS_LDO_32:
7675 case BFD_RELOC_386_TLS_IE_32:
7676 case BFD_RELOC_386_TLS_IE:
7677 case BFD_RELOC_386_TLS_GOTIE:
7678 case BFD_RELOC_386_TLS_LE_32:
7679 case BFD_RELOC_386_TLS_LE:
7680 case BFD_RELOC_386_TLS_GOTDESC:
7681 case BFD_RELOC_386_TLS_DESC_CALL:
7682 case BFD_RELOC_X86_64_TLSGD:
7683 case BFD_RELOC_X86_64_TLSLD:
7684 case BFD_RELOC_X86_64_DTPOFF32:
7685 case BFD_RELOC_X86_64_DTPOFF64:
7686 case BFD_RELOC_X86_64_GOTTPOFF:
7687 case BFD_RELOC_X86_64_TPOFF32:
7688 case BFD_RELOC_X86_64_TPOFF64:
7689 case BFD_RELOC_X86_64_GOTOFF64:
7690 case BFD_RELOC_X86_64_GOTPC32:
7691 case BFD_RELOC_X86_64_GOT64:
7692 case BFD_RELOC_X86_64_GOTPCREL64:
7693 case BFD_RELOC_X86_64_GOTPC64:
7694 case BFD_RELOC_X86_64_GOTPLT64:
7695 case BFD_RELOC_X86_64_PLTOFF64:
7696 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7697 case BFD_RELOC_X86_64_TLSDESC_CALL:
7699 case BFD_RELOC_VTABLE_ENTRY:
7700 case BFD_RELOC_VTABLE_INHERIT:
7702 case BFD_RELOC_32_SECREL:
7704 code = fixp->fx_r_type;
7706 case BFD_RELOC_X86_64_32S:
7707 if (!fixp->fx_pcrel)
7709 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7710 code = fixp->fx_r_type;
7716 switch (fixp->fx_size)
7719 as_bad_where (fixp->fx_file, fixp->fx_line,
7720 _("can not do %d byte pc-relative relocation"),
7722 code = BFD_RELOC_32_PCREL;
7724 case 1: code = BFD_RELOC_8_PCREL; break;
7725 case 2: code = BFD_RELOC_16_PCREL; break;
7726 case 4: code = BFD_RELOC_32_PCREL; break;
7728 case 8: code = BFD_RELOC_64_PCREL; break;
7734 switch (fixp->fx_size)
7737 as_bad_where (fixp->fx_file, fixp->fx_line,
7738 _("can not do %d byte relocation"),
7740 code = BFD_RELOC_32;
7742 case 1: code = BFD_RELOC_8; break;
7743 case 2: code = BFD_RELOC_16; break;
7744 case 4: code = BFD_RELOC_32; break;
7746 case 8: code = BFD_RELOC_64; break;
7753 if ((code == BFD_RELOC_32
7754 || code == BFD_RELOC_32_PCREL
7755 || code == BFD_RELOC_X86_64_32S)
7757 && fixp->fx_addsy == GOT_symbol)
7760 code = BFD_RELOC_386_GOTPC;
7762 code = BFD_RELOC_X86_64_GOTPC32;
7764 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7766 && fixp->fx_addsy == GOT_symbol)
7768 code = BFD_RELOC_X86_64_GOTPC64;
7771 rel = (arelent *) xmalloc (sizeof (arelent));
7772 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7773 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7775 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7777 if (!use_rela_relocations)
7779 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7780 vtable entry to be used in the relocation's section offset. */
7781 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7782 rel->address = fixp->fx_offset;
7786 /* Use the rela in 64bit mode. */
7789 if (!fixp->fx_pcrel)
7790 rel->addend = fixp->fx_offset;
7794 case BFD_RELOC_X86_64_PLT32:
7795 case BFD_RELOC_X86_64_GOT32:
7796 case BFD_RELOC_X86_64_GOTPCREL:
7797 case BFD_RELOC_X86_64_TLSGD:
7798 case BFD_RELOC_X86_64_TLSLD:
7799 case BFD_RELOC_X86_64_GOTTPOFF:
7800 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7801 case BFD_RELOC_X86_64_TLSDESC_CALL:
7802 rel->addend = fixp->fx_offset - fixp->fx_size;
7805 rel->addend = (section->vma
7807 + fixp->fx_addnumber
7808 + md_pcrel_from (fixp));
7813 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7814 if (rel->howto == NULL)
7816 as_bad_where (fixp->fx_file, fixp->fx_line,
7817 _("cannot represent relocation type %s"),
7818 bfd_get_reloc_code_name (code));
7819 /* Set howto to a garbage value so that we can keep going. */
7820 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7821 assert (rel->howto != NULL);
7828 /* Parse operands using Intel syntax. This implements a recursive descent
7829 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7832 FIXME: We do not recognize the full operand grammar defined in the MASM
7833 documentation. In particular, all the structure/union and
7834 high-level macro operands are missing.
7836 Uppercase words are terminals, lower case words are non-terminals.
7837 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7838 bars '|' denote choices. Most grammar productions are implemented in
7839 functions called 'intel_<production>'.
7841 Initial production is 'expr'.
7847 binOp & | AND | \| | OR | ^ | XOR
7849 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7851 constant digits [[ radixOverride ]]
7853 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7891 => expr expr cmpOp e04
7894 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7895 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7897 hexdigit a | b | c | d | e | f
7898 | A | B | C | D | E | F
7904 mulOp * | / | % | MOD | << | SHL | >> | SHR
7908 register specialRegister
7912 segmentRegister CS | DS | ES | FS | GS | SS
7914 specialRegister CR0 | CR2 | CR3 | CR4
7915 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7916 | TR3 | TR4 | TR5 | TR6 | TR7
7918 We simplify the grammar in obvious places (e.g., register parsing is
7919 done by calling parse_register) and eliminate immediate left recursion
7920 to implement a recursive-descent parser.
7924 expr' cmpOp e04 expr'
7975 /* Parsing structure for the intel syntax parser. Used to implement the
7976 semantic actions for the operand grammar. */
7977 struct intel_parser_s
7979 char *op_string; /* The string being parsed. */
7980 int got_a_float; /* Whether the operand is a float. */
7981 int op_modifier; /* Operand modifier. */
7982 int is_mem; /* 1 if operand is memory reference. */
7983 int in_offset; /* >=1 if parsing operand of offset. */
7984 int in_bracket; /* >=1 if parsing operand in brackets. */
7985 const reg_entry *reg; /* Last register reference found. */
7986 char *disp; /* Displacement string being built. */
7987 char *next_operand; /* Resume point when splitting operands. */
7990 static struct intel_parser_s intel_parser;
7992 /* Token structure for parsing intel syntax. */
7995 int code; /* Token code. */
7996 const reg_entry *reg; /* Register entry for register tokens. */
7997 char *str; /* String representation. */
8000 static struct intel_token cur_token, prev_token;
8002 /* Token codes for the intel parser. Since T_SHORT is already used
8003 by COFF, undefine it first to prevent a warning. */
8022 /* Prototypes for intel parser functions. */
8023 static int intel_match_token (int);
8024 static void intel_putback_token (void);
8025 static void intel_get_token (void);
8026 static int intel_expr (void);
8027 static int intel_e04 (void);
8028 static int intel_e05 (void);
8029 static int intel_e06 (void);
8030 static int intel_e09 (void);
8031 static int intel_e10 (void);
8032 static int intel_e11 (void);
8035 i386_intel_operand (char *operand_string, int got_a_float)
8040 p = intel_parser.op_string = xstrdup (operand_string);
8041 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8045 /* Initialize token holders. */
8046 cur_token.code = prev_token.code = T_NIL;
8047 cur_token.reg = prev_token.reg = NULL;
8048 cur_token.str = prev_token.str = NULL;
8050 /* Initialize parser structure. */
8051 intel_parser.got_a_float = got_a_float;
8052 intel_parser.op_modifier = 0;
8053 intel_parser.is_mem = 0;
8054 intel_parser.in_offset = 0;
8055 intel_parser.in_bracket = 0;
8056 intel_parser.reg = NULL;
8057 intel_parser.disp[0] = '\0';
8058 intel_parser.next_operand = NULL;
8060 /* Read the first token and start the parser. */
8062 ret = intel_expr ();
8067 if (cur_token.code != T_NIL)
8069 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8070 current_templates->start->name, cur_token.str);
8073 /* If we found a memory reference, hand it over to i386_displacement
8074 to fill in the rest of the operand fields. */
8075 else if (intel_parser.is_mem)
8077 if ((i.mem_operands == 1
8078 && !current_templates->start->opcode_modifier.isstring)
8079 || i.mem_operands == 2)
8081 as_bad (_("too many memory references for '%s'"),
8082 current_templates->start->name);
8087 char *s = intel_parser.disp;
8088 i.types[this_operand].bitfield.mem = 1;
8091 if (!quiet_warnings && intel_parser.is_mem < 0)
8092 /* See the comments in intel_bracket_expr. */
8093 as_warn (_("Treating `%s' as memory reference"), operand_string);
8095 /* Add the displacement expression. */
8097 ret = i386_displacement (s, s + strlen (s));
8100 /* Swap base and index in 16-bit memory operands like
8101 [si+bx]. Since i386_index_check is also used in AT&T
8102 mode we have to do that here. */
8105 && i.base_reg->reg_type.bitfield.reg16
8106 && i.index_reg->reg_type.bitfield.reg16
8107 && i.base_reg->reg_num >= 6
8108 && i.index_reg->reg_num < 6)
8110 const reg_entry *base = i.index_reg;
8112 i.index_reg = i.base_reg;
8115 ret = i386_index_check (operand_string);
8120 /* Constant and OFFSET expressions are handled by i386_immediate. */
8121 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8122 || intel_parser.reg == NULL)
8123 ret = i386_immediate (intel_parser.disp);
8125 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8127 if (!ret || !intel_parser.next_operand)
8129 intel_parser.op_string = intel_parser.next_operand;
8130 this_operand = i.operands++;
8131 i.types[this_operand].bitfield.unspecified = 1;
8135 free (intel_parser.disp);
8140 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8144 expr' cmpOp e04 expr'
8149 /* XXX Implement the comparison operators. */
8150 return intel_e04 ();
8167 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8168 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8170 if (cur_token.code == '+')
8172 else if (cur_token.code == '-')
8173 nregs = NUM_ADDRESS_REGS;
8177 strcat (intel_parser.disp, cur_token.str);
8178 intel_match_token (cur_token.code);
8189 int nregs = ~NUM_ADDRESS_REGS;
8196 if (cur_token.code == '&'
8197 || cur_token.code == '|'
8198 || cur_token.code == '^')
8202 str[0] = cur_token.code;
8204 strcat (intel_parser.disp, str);
8209 intel_match_token (cur_token.code);
8214 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8215 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8226 int nregs = ~NUM_ADDRESS_REGS;
8233 if (cur_token.code == '*'
8234 || cur_token.code == '/'
8235 || cur_token.code == '%')
8239 str[0] = cur_token.code;
8241 strcat (intel_parser.disp, str);
8243 else if (cur_token.code == T_SHL)
8244 strcat (intel_parser.disp, "<<");
8245 else if (cur_token.code == T_SHR)
8246 strcat (intel_parser.disp, ">>");
8250 intel_match_token (cur_token.code);
8255 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8256 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8274 int nregs = ~NUM_ADDRESS_REGS;
8279 /* Don't consume constants here. */
8280 if (cur_token.code == '+' || cur_token.code == '-')
8282 /* Need to look one token ahead - if the next token
8283 is a constant, the current token is its sign. */
8286 intel_match_token (cur_token.code);
8287 next_code = cur_token.code;
8288 intel_putback_token ();
8289 if (next_code == T_CONST)
8293 /* e09 OFFSET e09 */
8294 if (cur_token.code == T_OFFSET)
8297 ++intel_parser.in_offset;
8301 else if (cur_token.code == T_SHORT)
8302 intel_parser.op_modifier |= 1 << T_SHORT;
8305 else if (cur_token.code == '+')
8306 strcat (intel_parser.disp, "+");
8311 else if (cur_token.code == '-' || cur_token.code == '~')
8317 str[0] = cur_token.code;
8319 strcat (intel_parser.disp, str);
8326 intel_match_token (cur_token.code);
8334 /* e09' PTR e10 e09' */
8335 if (cur_token.code == T_PTR)
8339 if (prev_token.code == T_BYTE)
8341 suffix = BYTE_MNEM_SUFFIX;
8342 i.types[this_operand].bitfield.byte = 1;
8345 else if (prev_token.code == T_WORD)
8347 if (current_templates->start->name[0] == 'l'
8348 && current_templates->start->name[2] == 's'
8349 && current_templates->start->name[3] == 0)
8350 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8351 else if (intel_parser.got_a_float == 2) /* "fi..." */
8352 suffix = SHORT_MNEM_SUFFIX;
8354 suffix = WORD_MNEM_SUFFIX;
8355 i.types[this_operand].bitfield.word = 1;
8358 else if (prev_token.code == T_DWORD)
8360 if (current_templates->start->name[0] == 'l'
8361 && current_templates->start->name[2] == 's'
8362 && current_templates->start->name[3] == 0)
8363 suffix = WORD_MNEM_SUFFIX;
8364 else if (flag_code == CODE_16BIT
8365 && (current_templates->start->opcode_modifier.jump
8366 || current_templates->start->opcode_modifier.jumpdword))
8367 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8368 else if (intel_parser.got_a_float == 1) /* "f..." */
8369 suffix = SHORT_MNEM_SUFFIX;
8371 suffix = LONG_MNEM_SUFFIX;
8372 i.types[this_operand].bitfield.dword = 1;
8375 else if (prev_token.code == T_FWORD)
8377 if (current_templates->start->name[0] == 'l'
8378 && current_templates->start->name[2] == 's'
8379 && current_templates->start->name[3] == 0)
8380 suffix = LONG_MNEM_SUFFIX;
8381 else if (!intel_parser.got_a_float)
8383 if (flag_code == CODE_16BIT)
8384 add_prefix (DATA_PREFIX_OPCODE);
8385 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8388 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8389 i.types[this_operand].bitfield.fword = 1;
8392 else if (prev_token.code == T_QWORD)
8394 if (intel_parser.got_a_float == 1) /* "f..." */
8395 suffix = LONG_MNEM_SUFFIX;
8397 suffix = QWORD_MNEM_SUFFIX;
8398 i.types[this_operand].bitfield.qword = 1;
8401 else if (prev_token.code == T_TBYTE)
8403 if (intel_parser.got_a_float == 1)
8404 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8406 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8409 else if (prev_token.code == T_XMMWORD)
8411 suffix = XMMWORD_MNEM_SUFFIX;
8412 i.types[this_operand].bitfield.xmmword = 1;
8417 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8421 i.types[this_operand].bitfield.unspecified = 0;
8423 /* Operands for jump/call using 'ptr' notation denote absolute
8425 if (current_templates->start->opcode_modifier.jump
8426 || current_templates->start->opcode_modifier.jumpdword)
8427 i.types[this_operand].bitfield.jumpabsolute = 1;
8429 if (current_templates->start->base_opcode == 0x8d /* lea */)
8433 else if (i.suffix != suffix)
8435 as_bad (_("Conflicting operand modifiers"));
8441 /* e09' : e10 e09' */
8442 else if (cur_token.code == ':')
8444 if (prev_token.code != T_REG)
8446 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8447 segment/group identifier (which we don't have), using comma
8448 as the operand separator there is even less consistent, since
8449 there all branches only have a single operand. */
8450 if (this_operand != 0
8451 || intel_parser.in_offset
8452 || intel_parser.in_bracket
8453 || (!current_templates->start->opcode_modifier.jump
8454 && !current_templates->start->opcode_modifier.jumpdword
8455 && !current_templates->start->opcode_modifier.jumpintersegment
8456 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8457 return intel_match_token (T_NIL);
8458 /* Remember the start of the 2nd operand and terminate 1st
8460 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8461 another expression), but it gets at least the simplest case
8462 (a plain number or symbol on the left side) right. */
8463 intel_parser.next_operand = intel_parser.op_string;
8464 *--intel_parser.op_string = '\0';
8465 return intel_match_token (':');
8473 intel_match_token (cur_token.code);
8479 --intel_parser.in_offset;
8482 if (NUM_ADDRESS_REGS > nregs)
8484 as_bad (_("Invalid operand to `OFFSET'"));
8487 intel_parser.op_modifier |= 1 << T_OFFSET;
8490 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8491 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8496 intel_bracket_expr (void)
8498 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8499 const char *start = intel_parser.op_string;
8502 if (i.op[this_operand].regs)
8503 return intel_match_token (T_NIL);
8505 intel_match_token ('[');
8507 /* Mark as a memory operand only if it's not already known to be an
8508 offset expression. If it's an offset expression, we need to keep
8510 if (!intel_parser.in_offset)
8512 ++intel_parser.in_bracket;
8514 /* Operands for jump/call inside brackets denote absolute addresses. */
8515 if (current_templates->start->opcode_modifier.jump
8516 || current_templates->start->opcode_modifier.jumpdword)
8517 i.types[this_operand].bitfield.jumpabsolute = 1;
8519 /* Unfortunately gas always diverged from MASM in a respect that can't
8520 be easily fixed without risking to break code sequences likely to be
8521 encountered (the testsuite even check for this): MASM doesn't consider
8522 an expression inside brackets unconditionally as a memory reference.
8523 When that is e.g. a constant, an offset expression, or the sum of the
8524 two, this is still taken as a constant load. gas, however, always
8525 treated these as memory references. As a compromise, we'll try to make
8526 offset expressions inside brackets work the MASM way (since that's
8527 less likely to be found in real world code), but make constants alone
8528 continue to work the traditional gas way. In either case, issue a
8530 intel_parser.op_modifier &= ~was_offset;
8533 strcat (intel_parser.disp, "[");
8535 /* Add a '+' to the displacement string if necessary. */
8536 if (*intel_parser.disp != '\0'
8537 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8538 strcat (intel_parser.disp, "+");
8541 && (len = intel_parser.op_string - start - 1,
8542 intel_match_token (']')))
8544 /* Preserve brackets when the operand is an offset expression. */
8545 if (intel_parser.in_offset)
8546 strcat (intel_parser.disp, "]");
8549 --intel_parser.in_bracket;
8550 if (i.base_reg || i.index_reg)
8551 intel_parser.is_mem = 1;
8552 if (!intel_parser.is_mem)
8554 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8555 /* Defer the warning until all of the operand was parsed. */
8556 intel_parser.is_mem = -1;
8557 else if (!quiet_warnings)
8558 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8559 len, start, len, start);
8562 intel_parser.op_modifier |= was_offset;
8579 while (cur_token.code == '[')
8581 if (!intel_bracket_expr ())
8606 switch (cur_token.code)
8610 intel_match_token ('(');
8611 strcat (intel_parser.disp, "(");
8613 if (intel_expr () && intel_match_token (')'))
8615 strcat (intel_parser.disp, ")");
8622 return intel_bracket_expr ();
8627 strcat (intel_parser.disp, cur_token.str);
8628 intel_match_token (cur_token.code);
8630 /* Mark as a memory operand only if it's not already known to be an
8631 offset expression. */
8632 if (!intel_parser.in_offset)
8633 intel_parser.is_mem = 1;
8640 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8642 intel_match_token (T_REG);
8644 /* Check for segment change. */
8645 if (cur_token.code == ':')
8647 if (!reg->reg_type.bitfield.sreg2
8648 && !reg->reg_type.bitfield.sreg3)
8650 as_bad (_("`%s' is not a valid segment register"),
8654 else if (i.seg[i.mem_operands])
8655 as_warn (_("Extra segment override ignored"));
8658 if (!intel_parser.in_offset)
8659 intel_parser.is_mem = 1;
8660 switch (reg->reg_num)
8663 i.seg[i.mem_operands] = &es;
8666 i.seg[i.mem_operands] = &cs;
8669 i.seg[i.mem_operands] = &ss;
8672 i.seg[i.mem_operands] = &ds;
8675 i.seg[i.mem_operands] = &fs;
8678 i.seg[i.mem_operands] = &gs;
8684 /* Not a segment register. Check for register scaling. */
8685 else if (cur_token.code == '*')
8687 if (!intel_parser.in_bracket)
8689 as_bad (_("Register scaling only allowed in memory operands"));
8693 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8694 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8695 else if (i.index_reg)
8696 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8698 /* What follows must be a valid scale. */
8699 intel_match_token ('*');
8701 i.types[this_operand].bitfield.baseindex = 1;
8703 /* Set the scale after setting the register (otherwise,
8704 i386_scale will complain) */
8705 if (cur_token.code == '+' || cur_token.code == '-')
8707 char *str, sign = cur_token.code;
8708 intel_match_token (cur_token.code);
8709 if (cur_token.code != T_CONST)
8711 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8715 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8716 strcpy (str + 1, cur_token.str);
8718 if (!i386_scale (str))
8722 else if (!i386_scale (cur_token.str))
8724 intel_match_token (cur_token.code);
8727 /* No scaling. If this is a memory operand, the register is either a
8728 base register (first occurrence) or an index register (second
8730 else if (intel_parser.in_bracket)
8735 else if (!i.index_reg)
8739 as_bad (_("Too many register references in memory operand"));
8743 i.types[this_operand].bitfield.baseindex = 1;
8746 /* It's neither base nor index. */
8747 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8749 i386_operand_type temp = reg->reg_type;
8750 temp.bitfield.baseindex = 0;
8751 i.types[this_operand] = operand_type_or (i.types[this_operand],
8753 i.types[this_operand].bitfield.unspecified = 0;
8754 i.op[this_operand].regs = reg;
8759 as_bad (_("Invalid use of register"));
8763 /* Since registers are not part of the displacement string (except
8764 when we're parsing offset operands), we may need to remove any
8765 preceding '+' from the displacement string. */
8766 if (*intel_parser.disp != '\0'
8767 && !intel_parser.in_offset)
8769 char *s = intel_parser.disp;
8770 s += strlen (s) - 1;
8793 intel_match_token (cur_token.code);
8795 if (cur_token.code == T_PTR)
8798 /* It must have been an identifier. */
8799 intel_putback_token ();
8800 cur_token.code = T_ID;
8806 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8810 /* The identifier represents a memory reference only if it's not
8811 preceded by an offset modifier and if it's not an equate. */
8812 symbolP = symbol_find(cur_token.str);
8813 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8814 intel_parser.is_mem = 1;
8822 char *save_str, sign = 0;
8824 /* Allow constants that start with `+' or `-'. */
8825 if (cur_token.code == '-' || cur_token.code == '+')
8827 sign = cur_token.code;
8828 intel_match_token (cur_token.code);
8829 if (cur_token.code != T_CONST)
8831 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8837 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8838 strcpy (save_str + !!sign, cur_token.str);
8842 /* Get the next token to check for register scaling. */
8843 intel_match_token (cur_token.code);
8845 /* Check if this constant is a scaling factor for an
8847 if (cur_token.code == '*')
8849 if (intel_match_token ('*') && cur_token.code == T_REG)
8851 const reg_entry *reg = cur_token.reg;
8853 if (!intel_parser.in_bracket)
8855 as_bad (_("Register scaling only allowed "
8856 "in memory operands"));
8860 /* Disallow things like [1*si].
8861 sp and esp are invalid as index. */
8862 if (reg->reg_type.bitfield.reg16)
8863 reg = i386_regtab + REGNAM_AX + 4;
8864 else if (i.index_reg)
8865 reg = i386_regtab + REGNAM_EAX + 4;
8867 /* The constant is followed by `* reg', so it must be
8870 i.types[this_operand].bitfield.baseindex = 1;
8872 /* Set the scale after setting the register (otherwise,
8873 i386_scale will complain) */
8874 if (!i386_scale (save_str))
8876 intel_match_token (T_REG);
8878 /* Since registers are not part of the displacement
8879 string, we may need to remove any preceding '+' from
8880 the displacement string. */
8881 if (*intel_parser.disp != '\0')
8883 char *s = intel_parser.disp;
8884 s += strlen (s) - 1;
8894 /* The constant was not used for register scaling. Since we have
8895 already consumed the token following `*' we now need to put it
8896 back in the stream. */
8897 intel_putback_token ();
8900 /* Add the constant to the displacement string. */
8901 strcat (intel_parser.disp, save_str);
8908 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8912 /* Match the given token against cur_token. If they match, read the next
8913 token from the operand string. */
8915 intel_match_token (int code)
8917 if (cur_token.code == code)
8924 as_bad (_("Unexpected token `%s'"), cur_token.str);
8929 /* Read a new token from intel_parser.op_string and store it in cur_token. */
8931 intel_get_token (void)
8934 const reg_entry *reg;
8935 struct intel_token new_token;
8937 new_token.code = T_NIL;
8938 new_token.reg = NULL;
8939 new_token.str = NULL;
8941 /* Free the memory allocated to the previous token and move
8942 cur_token to prev_token. */
8944 free (prev_token.str);
8946 prev_token = cur_token;
8948 /* Skip whitespace. */
8949 while (is_space_char (*intel_parser.op_string))
8950 intel_parser.op_string++;
8952 /* Return an empty token if we find nothing else on the line. */
8953 if (*intel_parser.op_string == '\0')
8955 cur_token = new_token;
8959 /* The new token cannot be larger than the remainder of the operand
8961 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
8962 new_token.str[0] = '\0';
8964 if (strchr ("0123456789", *intel_parser.op_string))
8966 char *p = new_token.str;
8967 char *q = intel_parser.op_string;
8968 new_token.code = T_CONST;
8970 /* Allow any kind of identifier char to encompass floating point and
8971 hexadecimal numbers. */
8972 while (is_identifier_char (*q))
8976 /* Recognize special symbol names [0-9][bf]. */
8977 if (strlen (intel_parser.op_string) == 2
8978 && (intel_parser.op_string[1] == 'b'
8979 || intel_parser.op_string[1] == 'f'))
8980 new_token.code = T_ID;
8983 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
8985 size_t len = end_op - intel_parser.op_string;
8987 new_token.code = T_REG;
8988 new_token.reg = reg;
8990 memcpy (new_token.str, intel_parser.op_string, len);
8991 new_token.str[len] = '\0';
8994 else if (is_identifier_char (*intel_parser.op_string))
8996 char *p = new_token.str;
8997 char *q = intel_parser.op_string;
8999 /* A '.' or '$' followed by an identifier char is an identifier.
9000 Otherwise, it's operator '.' followed by an expression. */
9001 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9003 new_token.code = '.';
9004 new_token.str[0] = '.';
9005 new_token.str[1] = '\0';
9009 while (is_identifier_char (*q) || *q == '@')
9013 if (strcasecmp (new_token.str, "NOT") == 0)
9014 new_token.code = '~';
9016 else if (strcasecmp (new_token.str, "MOD") == 0)
9017 new_token.code = '%';
9019 else if (strcasecmp (new_token.str, "AND") == 0)
9020 new_token.code = '&';
9022 else if (strcasecmp (new_token.str, "OR") == 0)
9023 new_token.code = '|';
9025 else if (strcasecmp (new_token.str, "XOR") == 0)
9026 new_token.code = '^';
9028 else if (strcasecmp (new_token.str, "SHL") == 0)
9029 new_token.code = T_SHL;
9031 else if (strcasecmp (new_token.str, "SHR") == 0)
9032 new_token.code = T_SHR;
9034 else if (strcasecmp (new_token.str, "BYTE") == 0)
9035 new_token.code = T_BYTE;
9037 else if (strcasecmp (new_token.str, "WORD") == 0)
9038 new_token.code = T_WORD;
9040 else if (strcasecmp (new_token.str, "DWORD") == 0)
9041 new_token.code = T_DWORD;
9043 else if (strcasecmp (new_token.str, "FWORD") == 0)
9044 new_token.code = T_FWORD;
9046 else if (strcasecmp (new_token.str, "QWORD") == 0)
9047 new_token.code = T_QWORD;
9049 else if (strcasecmp (new_token.str, "TBYTE") == 0
9050 /* XXX remove (gcc still uses it) */
9051 || strcasecmp (new_token.str, "XWORD") == 0)
9052 new_token.code = T_TBYTE;
9054 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9055 || strcasecmp (new_token.str, "OWORD") == 0)
9056 new_token.code = T_XMMWORD;
9058 else if (strcasecmp (new_token.str, "PTR") == 0)
9059 new_token.code = T_PTR;
9061 else if (strcasecmp (new_token.str, "SHORT") == 0)
9062 new_token.code = T_SHORT;
9064 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9066 new_token.code = T_OFFSET;
9068 /* ??? This is not mentioned in the MASM grammar but gcc
9069 makes use of it with -mintel-syntax. OFFSET may be
9070 followed by FLAT: */
9071 if (strncasecmp (q, " FLAT:", 6) == 0)
9072 strcat (new_token.str, " FLAT:");
9075 /* ??? This is not mentioned in the MASM grammar. */
9076 else if (strcasecmp (new_token.str, "FLAT") == 0)
9078 new_token.code = T_OFFSET;
9080 strcat (new_token.str, ":");
9082 as_bad (_("`:' expected"));
9086 new_token.code = T_ID;
9090 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9092 new_token.code = *intel_parser.op_string;
9093 new_token.str[0] = *intel_parser.op_string;
9094 new_token.str[1] = '\0';
9097 else if (strchr ("<>", *intel_parser.op_string)
9098 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9100 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9101 new_token.str[0] = *intel_parser.op_string;
9102 new_token.str[1] = *intel_parser.op_string;
9103 new_token.str[2] = '\0';
9107 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9109 intel_parser.op_string += strlen (new_token.str);
9110 cur_token = new_token;
9113 /* Put cur_token back into the token stream and make cur_token point to
9116 intel_putback_token (void)
9118 if (cur_token.code != T_NIL)
9120 intel_parser.op_string -= strlen (cur_token.str);
9121 free (cur_token.str);
9123 cur_token = prev_token;
9125 /* Forget prev_token. */
9126 prev_token.code = T_NIL;
9127 prev_token.reg = NULL;
9128 prev_token.str = NULL;
9132 tc_x86_regname_to_dw2regnum (char *regname)
9134 unsigned int regnum;
9135 unsigned int regnames_count;
9136 static const char *const regnames_32[] =
9138 "eax", "ecx", "edx", "ebx",
9139 "esp", "ebp", "esi", "edi",
9140 "eip", "eflags", NULL,
9141 "st0", "st1", "st2", "st3",
9142 "st4", "st5", "st6", "st7",
9144 "xmm0", "xmm1", "xmm2", "xmm3",
9145 "xmm4", "xmm5", "xmm6", "xmm7",
9146 "mm0", "mm1", "mm2", "mm3",
9147 "mm4", "mm5", "mm6", "mm7",
9148 "fcw", "fsw", "mxcsr",
9149 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9152 static const char *const regnames_64[] =
9154 "rax", "rdx", "rcx", "rbx",
9155 "rsi", "rdi", "rbp", "rsp",
9156 "r8", "r9", "r10", "r11",
9157 "r12", "r13", "r14", "r15",
9159 "xmm0", "xmm1", "xmm2", "xmm3",
9160 "xmm4", "xmm5", "xmm6", "xmm7",
9161 "xmm8", "xmm9", "xmm10", "xmm11",
9162 "xmm12", "xmm13", "xmm14", "xmm15",
9163 "st0", "st1", "st2", "st3",
9164 "st4", "st5", "st6", "st7",
9165 "mm0", "mm1", "mm2", "mm3",
9166 "mm4", "mm5", "mm6", "mm7",
9168 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
9169 "fs.base", "gs.base", NULL, NULL,
9171 "mxcsr", "fcw", "fsw"
9173 const char *const *regnames;
9175 if (flag_code == CODE_64BIT)
9177 regnames = regnames_64;
9178 regnames_count = ARRAY_SIZE (regnames_64);
9182 regnames = regnames_32;
9183 regnames_count = ARRAY_SIZE (regnames_32);
9186 for (regnum = 0; regnum < regnames_count; regnum++)
9187 if (regnames[regnum] != NULL
9188 && strcmp (regname, regnames[regnum]) == 0)
9195 tc_x86_frame_initial_instructions (void)
9197 static unsigned int sp_regno;
9200 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9203 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9204 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9208 i386_elf_section_type (const char *str, size_t len)
9210 if (flag_code == CODE_64BIT
9211 && len == sizeof ("unwind") - 1
9212 && strncmp (str, "unwind", 6) == 0)
9213 return SHT_X86_64_UNWIND;
9220 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9224 expr.X_op = O_secrel;
9225 expr.X_add_symbol = symbol;
9226 expr.X_add_number = 0;
9227 emit_expr (&expr, size);
9231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9232 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9235 x86_64_section_letter (int letter, char **ptr_msg)
9237 if (flag_code == CODE_64BIT)
9240 return SHF_X86_64_LARGE;
9242 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9245 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9250 x86_64_section_word (char *str, size_t len)
9252 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9253 return SHF_X86_64_LARGE;
9259 handle_large_common (int small ATTRIBUTE_UNUSED)
9261 if (flag_code != CODE_64BIT)
9263 s_comm_internal (0, elf_common_parse);
9264 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9268 static segT lbss_section;
9269 asection *saved_com_section_ptr = elf_com_section_ptr;
9270 asection *saved_bss_section = bss_section;
9272 if (lbss_section == NULL)
9274 flagword applicable;
9276 subsegT subseg = now_subseg;
9278 /* The .lbss section is for local .largecomm symbols. */
9279 lbss_section = subseg_new (".lbss", 0);
9280 applicable = bfd_applicable_section_flags (stdoutput);
9281 bfd_set_section_flags (stdoutput, lbss_section,
9282 applicable & SEC_ALLOC);
9283 seg_info (lbss_section)->bss = 1;
9285 subseg_set (seg, subseg);
9288 elf_com_section_ptr = &_bfd_elf_large_com_section;
9289 bss_section = lbss_section;
9291 s_comm_internal (0, elf_common_parse);
9293 elf_com_section_ptr = saved_com_section_ptr;
9294 bss_section = saved_bss_section;
9297 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */