1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const template *start;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* The SSE5 instructions have a two bit instruction modifier (OC) that
117 is stored in two separate bytes in the instruction. Pick apart OC
118 into the 2 separate bits for instruction. */
119 #define DREX_OC0(x) (((x) & 1) != 0)
120 #define DREX_OC1(x) (((x) & 2) != 0)
122 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
123 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
126 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
127 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
128 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
129 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
132 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134 /* Information needed to create the DREX byte in SSE5 instructions. */
137 unsigned int reg; /* register */
138 unsigned int rex; /* REX flags */
139 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
140 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
143 /* 386 opcode byte to code indirect addressing. */
158 PROCESSOR_PENTIUMPRO,
171 /* x86 arch names, types and features */
174 const char *name; /* arch name */
175 enum processor_type type; /* arch type */
176 i386_cpu_flags flags; /* cpu feature flags */
180 static void set_code_flag (int);
181 static void set_16bit_gcc_code_flag (int);
182 static void set_intel_syntax (int);
183 static void set_intel_mnemonic (int);
184 static void set_allow_index_reg (int);
185 static void set_cpu_arch (int);
187 static void pe_directive_secrel (int);
189 static void signed_cons (int);
190 static char *output_invalid (int c);
191 static int i386_att_operand (char *);
192 static int i386_intel_operand (char *, int);
193 static const reg_entry *parse_register (char *, char **);
194 static char *parse_insn (char *, char *);
195 static char *parse_operands (char *, const char *);
196 static void swap_operands (void);
197 static void swap_2_operands (int, int);
198 static void optimize_imm (void);
199 static void optimize_disp (void);
200 static int match_template (void);
201 static int check_string (void);
202 static int process_suffix (void);
203 static int check_byte_reg (void);
204 static int check_long_reg (void);
205 static int check_qword_reg (void);
206 static int check_word_reg (void);
207 static int finalize_imm (void);
208 static void process_drex (void);
209 static int process_operands (void);
210 static const seg_entry *build_modrm_byte (void);
211 static void output_insn (void);
212 static void output_imm (fragS *, offsetT);
213 static void output_disp (fragS *, offsetT);
215 static void s_bss (int);
217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
218 static void handle_large_common (int small ATTRIBUTE_UNUSED);
221 static const char *default_arch = DEFAULT_ARCH;
223 /* 'md_assemble ()' gathers together information and puts it into a
230 const reg_entry *regs;
235 /* TM holds the template for the insn were currently assembling. */
238 /* SUFFIX holds the instruction size suffix for byte, word, dword
239 or qword, if given. */
242 /* OPERANDS gives the number of given operands. */
243 unsigned int operands;
245 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
246 of given register, displacement, memory operands and immediate
248 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
250 /* TYPES [i] is the type (see above #defines) which tells us how to
251 use OP[i] for the corresponding operand. */
252 i386_operand_type types[MAX_OPERANDS];
254 /* Displacement expression, immediate expression, or register for each
256 union i386_op op[MAX_OPERANDS];
258 /* Flags for operands. */
259 unsigned int flags[MAX_OPERANDS];
260 #define Operand_PCrel 1
262 /* Relocation type for operand */
263 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
265 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
266 the base index byte below. */
267 const reg_entry *base_reg;
268 const reg_entry *index_reg;
269 unsigned int log2_scale_factor;
271 /* SEG gives the seg_entries of this insn. They are zero unless
272 explicit segment overrides are given. */
273 const seg_entry *seg[2];
275 /* PREFIX holds all the given prefix opcodes (usually null).
276 PREFIXES is the number of prefix opcodes. */
277 unsigned int prefixes;
278 unsigned char prefix[MAX_PREFIXES];
280 /* RM and SIB are the modrm byte and the sib byte where the
281 addressing modes of this insn are encoded. DREX is the byte
282 added by the SSE5 instructions. */
290 typedef struct _i386_insn i386_insn;
292 /* List of chars besides those in app.c:symbol_chars that can start an
293 operand. Used to prevent the scrubber eating vital white-space. */
294 const char extra_symbol_chars[] = "*%-(["
303 #if (defined (TE_I386AIX) \
304 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
305 && !defined (TE_GNU) \
306 && !defined (TE_LINUX) \
307 && !defined (TE_NETWARE) \
308 && !defined (TE_FreeBSD) \
309 && !defined (TE_NetBSD)))
310 /* This array holds the chars that always start a comment. If the
311 pre-processor is disabled, these aren't very useful. The option
312 --divide will remove '/' from this list. */
313 const char *i386_comment_chars = "#/";
314 #define SVR4_COMMENT_CHARS 1
315 #define PREFIX_SEPARATOR '\\'
318 const char *i386_comment_chars = "#";
319 #define PREFIX_SEPARATOR '/'
322 /* This array holds the chars that only start a comment at the beginning of
323 a line. If the line seems to have the form '# 123 filename'
324 .line and .file directives will appear in the pre-processed output.
325 Note that input_file.c hand checks for '#' at the beginning of the
326 first line of the input file. This is because the compiler outputs
327 #NO_APP at the beginning of its output.
328 Also note that comments started like this one will always work if
329 '/' isn't otherwise defined. */
330 const char line_comment_chars[] = "#/";
332 const char line_separator_chars[] = ";";
334 /* Chars that can be used to separate mant from exp in floating point
336 const char EXP_CHARS[] = "eE";
338 /* Chars that mean this number is a floating point constant
341 const char FLT_CHARS[] = "fFdDxX";
343 /* Tables for lexical analysis. */
344 static char mnemonic_chars[256];
345 static char register_chars[256];
346 static char operand_chars[256];
347 static char identifier_chars[256];
348 static char digit_chars[256];
350 /* Lexical macros. */
351 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
352 #define is_operand_char(x) (operand_chars[(unsigned char) x])
353 #define is_register_char(x) (register_chars[(unsigned char) x])
354 #define is_space_char(x) ((x) == ' ')
355 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
356 #define is_digit_char(x) (digit_chars[(unsigned char) x])
358 /* All non-digit non-letter characters that may occur in an operand. */
359 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
361 /* md_assemble() always leaves the strings it's passed unaltered. To
362 effect this we maintain a stack of saved characters that we've smashed
363 with '\0's (indicating end of strings for various sub-fields of the
364 assembler instruction). */
365 static char save_stack[32];
366 static char *save_stack_p;
367 #define END_STRING_AND_SAVE(s) \
368 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
369 #define RESTORE_END_STRING(s) \
370 do { *(s) = *--save_stack_p; } while (0)
372 /* The instruction we're assembling. */
375 /* Possible templates for current insn. */
376 static const templates *current_templates;
378 /* Per instruction expressionS buffers: max displacements & immediates. */
379 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
380 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
382 /* Current operand we are working on. */
383 static int this_operand;
385 /* We support four different modes. FLAG_CODE variable is used to distinguish
393 static enum flag_code flag_code;
394 static unsigned int object_64bit;
395 static int use_rela_relocations = 0;
397 /* The names used to print error messages. */
398 static const char *flag_code_names[] =
405 /* 1 for intel syntax,
407 static int intel_syntax = 0;
409 /* 1 for intel mnemonic,
410 0 if att mnemonic. */
411 static int intel_mnemonic = !SYSV386_COMPAT;
413 /* 1 if support old (<= 2.8.1) versions of gcc. */
414 static int old_gcc = OLDGCC_COMPAT;
416 /* 1 if pseudo registers are permitted. */
417 static int allow_pseudo_reg = 0;
419 /* 1 if register prefix % not required. */
420 static int allow_naked_reg = 0;
422 /* 1 if pseudo index register, eiz/riz, is allowed . */
423 static int allow_index_reg = 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix = "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size = '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code = 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings = 0;
440 static const char *cpu_arch_name = NULL;
441 static char *cpu_sub_arch_name = NULL;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set = 0;
449 /* Cpu we are generating instructions for. */
450 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags;
455 /* CPU instruction set architecture used. */
456 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
458 /* CPU feature flags of instruction set architecture used. */
459 static i386_cpu_flags cpu_arch_isa_flags;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion = 0;
465 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
466 static symbolS *GOT_symbol;
468 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
469 unsigned int x86_dwarf2_return_column;
471 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
472 int x86_cie_data_alignment;
474 /* Interface to relax_segment.
475 There are 3 major relax states for 386 jump insns because the
476 different types of jumps add different sizes to frags when we're
477 figuring out what sort of jump to choose to reach a given label. */
480 #define UNCOND_JUMP 0
482 #define COND_JUMP86 2
487 #define SMALL16 (SMALL | CODE16)
489 #define BIG16 (BIG | CODE16)
493 #define INLINE __inline__
499 #define ENCODE_RELAX_STATE(type, size) \
500 ((relax_substateT) (((type) << 2) | (size)))
501 #define TYPE_FROM_RELAX_STATE(s) \
503 #define DISP_SIZE_FROM_RELAX_STATE(s) \
504 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
506 /* This table is used by relax_frag to promote short jumps to long
507 ones where necessary. SMALL (short) jumps may be promoted to BIG
508 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
509 don't allow a short jump in a 32 bit code segment to be promoted to
510 a 16 bit offset jump because it's slower (requires data size
511 prefix), and doesn't work, unless the destination is in the bottom
512 64k of the code segment (The top 16 bits of eip are zeroed). */
514 const relax_typeS md_relax_table[] =
517 1) most positive reach of this state,
518 2) most negative reach of this state,
519 3) how many bytes this mode will have in the variable part of the frag
520 4) which index into the table to try if we can't fit into this one. */
522 /* UNCOND_JUMP states. */
523 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
524 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
525 /* dword jmp adds 4 bytes to frag:
526 0 extra opcode bytes, 4 displacement bytes. */
528 /* word jmp adds 2 byte2 to frag:
529 0 extra opcode bytes, 2 displacement bytes. */
532 /* COND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
535 /* dword conditionals adds 5 bytes to frag:
536 1 extra opcode byte, 4 displacement bytes. */
538 /* word conditionals add 3 bytes to frag:
539 1 extra opcode byte, 2 displacement bytes. */
542 /* COND_JUMP86 states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 4 bytes to frag:
549 1 displacement byte and a 3 byte long branch insn. */
553 static const arch_entry cpu_arch[] =
555 { "generic32", PROCESSOR_GENERIC32,
556 CPU_GENERIC32_FLAGS },
557 { "generic64", PROCESSOR_GENERIC64,
558 CPU_GENERIC64_FLAGS },
559 { "i8086", PROCESSOR_UNKNOWN,
561 { "i186", PROCESSOR_UNKNOWN,
563 { "i286", PROCESSOR_UNKNOWN,
565 { "i386", PROCESSOR_I386,
567 { "i486", PROCESSOR_I486,
569 { "i586", PROCESSOR_PENTIUM,
571 { "i686", PROCESSOR_PENTIUMPRO,
573 { "pentium", PROCESSOR_PENTIUM,
575 { "pentiumpro", PROCESSOR_PENTIUMPRO,
577 { "pentiumii", PROCESSOR_PENTIUMPRO,
579 { "pentiumiii",PROCESSOR_PENTIUMPRO,
581 { "pentium4", PROCESSOR_PENTIUM4,
583 { "prescott", PROCESSOR_NOCONA,
585 { "nocona", PROCESSOR_NOCONA,
587 { "yonah", PROCESSOR_CORE,
589 { "core", PROCESSOR_CORE,
591 { "merom", PROCESSOR_CORE2,
593 { "core2", PROCESSOR_CORE2,
595 { "k6", PROCESSOR_K6,
597 { "k6_2", PROCESSOR_K6,
599 { "athlon", PROCESSOR_ATHLON,
601 { "sledgehammer", PROCESSOR_K8,
603 { "opteron", PROCESSOR_K8,
605 { "k8", PROCESSOR_K8,
607 { "amdfam10", PROCESSOR_AMDFAM10,
608 CPU_AMDFAM10_FLAGS },
609 { ".mmx", PROCESSOR_UNKNOWN,
611 { ".sse", PROCESSOR_UNKNOWN,
613 { ".sse2", PROCESSOR_UNKNOWN,
615 { ".sse3", PROCESSOR_UNKNOWN,
617 { ".ssse3", PROCESSOR_UNKNOWN,
619 { ".sse4.1", PROCESSOR_UNKNOWN,
621 { ".sse4.2", PROCESSOR_UNKNOWN,
623 { ".sse4", PROCESSOR_UNKNOWN,
625 { ".vmx", PROCESSOR_UNKNOWN,
627 { ".smx", PROCESSOR_UNKNOWN,
629 { ".xsave", PROCESSOR_UNKNOWN,
631 { ".3dnow", PROCESSOR_UNKNOWN,
633 { ".3dnowa", PROCESSOR_UNKNOWN,
635 { ".padlock", PROCESSOR_UNKNOWN,
637 { ".pacifica", PROCESSOR_UNKNOWN,
639 { ".svme", PROCESSOR_UNKNOWN,
641 { ".sse4a", PROCESSOR_UNKNOWN,
643 { ".abm", PROCESSOR_UNKNOWN,
645 { ".sse5", PROCESSOR_UNKNOWN,
649 const pseudo_typeS md_pseudo_table[] =
651 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
652 {"align", s_align_bytes, 0},
654 {"align", s_align_ptwo, 0},
656 {"arch", set_cpu_arch, 0},
660 {"ffloat", float_cons, 'f'},
661 {"dfloat", float_cons, 'd'},
662 {"tfloat", float_cons, 'x'},
664 {"slong", signed_cons, 4},
665 {"noopt", s_ignore, 0},
666 {"optim", s_ignore, 0},
667 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
668 {"code16", set_code_flag, CODE_16BIT},
669 {"code32", set_code_flag, CODE_32BIT},
670 {"code64", set_code_flag, CODE_64BIT},
671 {"intel_syntax", set_intel_syntax, 1},
672 {"att_syntax", set_intel_syntax, 0},
673 {"intel_mnemonic", set_intel_mnemonic, 1},
674 {"att_mnemonic", set_intel_mnemonic, 0},
675 {"allow_index_reg", set_allow_index_reg, 1},
676 {"disallow_index_reg", set_allow_index_reg, 0},
677 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
678 {"largecomm", handle_large_common, 0},
680 {"file", (void (*) (int)) dwarf2_directive_file, 0},
681 {"loc", dwarf2_directive_loc, 0},
682 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
685 {"secrel32", pe_directive_secrel, 0},
690 /* For interface with expression (). */
691 extern char *input_line_pointer;
693 /* Hash table for instruction mnemonic lookup. */
694 static struct hash_control *op_hash;
696 /* Hash table for register lookup. */
697 static struct hash_control *reg_hash;
700 i386_align_code (fragS *fragP, int count)
702 /* Various efficient no-op patterns for aligning code labels.
703 Note: Don't try to assemble the instructions in the comments.
704 0L and 0w are not legal. */
705 static const char f32_1[] =
707 static const char f32_2[] =
708 {0x66,0x90}; /* xchg %ax,%ax */
709 static const char f32_3[] =
710 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
711 static const char f32_4[] =
712 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
713 static const char f32_5[] =
715 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
716 static const char f32_6[] =
717 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
718 static const char f32_7[] =
719 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
720 static const char f32_8[] =
722 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
723 static const char f32_9[] =
724 {0x89,0xf6, /* movl %esi,%esi */
725 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
726 static const char f32_10[] =
727 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
728 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
729 static const char f32_11[] =
730 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
731 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
732 static const char f32_12[] =
733 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
734 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
735 static const char f32_13[] =
736 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
737 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
738 static const char f32_14[] =
739 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
740 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
741 static const char f16_3[] =
742 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
743 static const char f16_4[] =
744 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
745 static const char f16_5[] =
747 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
748 static const char f16_6[] =
749 {0x89,0xf6, /* mov %si,%si */
750 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
751 static const char f16_7[] =
752 {0x8d,0x74,0x00, /* lea 0(%si),%si */
753 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
754 static const char f16_8[] =
755 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
756 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
757 static const char jump_31[] =
758 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
759 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
760 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
761 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
762 static const char *const f32_patt[] = {
763 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
764 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
766 static const char *const f16_patt[] = {
767 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
770 static const char alt_3[] =
772 /* nopl 0(%[re]ax) */
773 static const char alt_4[] =
774 {0x0f,0x1f,0x40,0x00};
775 /* nopl 0(%[re]ax,%[re]ax,1) */
776 static const char alt_5[] =
777 {0x0f,0x1f,0x44,0x00,0x00};
778 /* nopw 0(%[re]ax,%[re]ax,1) */
779 static const char alt_6[] =
780 {0x66,0x0f,0x1f,0x44,0x00,0x00};
781 /* nopl 0L(%[re]ax) */
782 static const char alt_7[] =
783 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
784 /* nopl 0L(%[re]ax,%[re]ax,1) */
785 static const char alt_8[] =
786 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
787 /* nopw 0L(%[re]ax,%[re]ax,1) */
788 static const char alt_9[] =
789 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
790 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
791 static const char alt_10[] =
792 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
794 nopw %cs:0L(%[re]ax,%[re]ax,1) */
795 static const char alt_long_11[] =
797 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
800 nopw %cs:0L(%[re]ax,%[re]ax,1) */
801 static const char alt_long_12[] =
804 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
808 nopw %cs:0L(%[re]ax,%[re]ax,1) */
809 static const char alt_long_13[] =
813 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
818 nopw %cs:0L(%[re]ax,%[re]ax,1) */
819 static const char alt_long_14[] =
824 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
830 nopw %cs:0L(%[re]ax,%[re]ax,1) */
831 static const char alt_long_15[] =
837 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopl 0(%[re]ax,%[re]ax,1)
839 nopw 0(%[re]ax,%[re]ax,1) */
840 static const char alt_short_11[] =
841 {0x0f,0x1f,0x44,0x00,0x00,
842 0x66,0x0f,0x1f,0x44,0x00,0x00};
843 /* nopw 0(%[re]ax,%[re]ax,1)
844 nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_short_12[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00,
847 0x66,0x0f,0x1f,0x44,0x00,0x00};
848 /* nopw 0(%[re]ax,%[re]ax,1)
850 static const char alt_short_13[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00,
852 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 static const char alt_short_14[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
857 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_short_15[] =
861 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
862 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 static const char *const alt_short_patt[] = {
864 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
865 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
866 alt_short_14, alt_short_15
868 static const char *const alt_long_patt[] = {
869 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
870 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
871 alt_long_14, alt_long_15
874 /* Only align for at least a positive non-zero boundary. */
875 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
878 /* We need to decide which NOP sequence to use for 32bit and
879 64bit. When -mtune= is used:
881 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
882 PROCESSOR_GENERIC32, f32_patt will be used.
883 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
884 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
885 alt_long_patt will be used.
886 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
887 PROCESSOR_AMDFAM10, alt_short_patt will be used.
889 When -mtune= isn't used, alt_long_patt will be used if
890 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
893 When -march= or .arch is used, we can't use anything beyond
894 cpu_arch_isa_flags. */
896 if (flag_code == CODE_16BIT)
900 memcpy (fragP->fr_literal + fragP->fr_fix,
902 /* Adjust jump offset. */
903 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
906 memcpy (fragP->fr_literal + fragP->fr_fix,
907 f16_patt[count - 1], count);
911 const char *const *patt = NULL;
913 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
915 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
916 switch (cpu_arch_tune)
918 case PROCESSOR_UNKNOWN:
919 /* We use cpu_arch_isa_flags to check if we SHOULD
920 optimize for Cpu686. */
921 if (cpu_arch_isa_flags.bitfield.cpui686)
922 patt = alt_long_patt;
926 case PROCESSOR_PENTIUMPRO:
927 case PROCESSOR_PENTIUM4:
928 case PROCESSOR_NOCONA:
930 case PROCESSOR_CORE2:
931 case PROCESSOR_GENERIC64:
932 patt = alt_long_patt;
935 case PROCESSOR_ATHLON:
937 case PROCESSOR_AMDFAM10:
938 patt = alt_short_patt;
942 case PROCESSOR_PENTIUM:
943 case PROCESSOR_GENERIC32:
950 switch (cpu_arch_tune)
952 case PROCESSOR_UNKNOWN:
953 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
954 PROCESSOR_UNKNOWN. */
960 case PROCESSOR_PENTIUM:
962 case PROCESSOR_ATHLON:
964 case PROCESSOR_AMDFAM10:
965 case PROCESSOR_GENERIC32:
966 /* We use cpu_arch_isa_flags to check if we CAN optimize
968 if (cpu_arch_isa_flags.bitfield.cpui686)
969 patt = alt_short_patt;
973 case PROCESSOR_PENTIUMPRO:
974 case PROCESSOR_PENTIUM4:
975 case PROCESSOR_NOCONA:
977 case PROCESSOR_CORE2:
978 if (cpu_arch_isa_flags.bitfield.cpui686)
979 patt = alt_long_patt;
983 case PROCESSOR_GENERIC64:
984 patt = alt_long_patt;
989 if (patt == f32_patt)
991 /* If the padding is less than 15 bytes, we use the normal
992 ones. Otherwise, we use a jump instruction and adjust
995 memcpy (fragP->fr_literal + fragP->fr_fix,
996 patt[count - 1], count);
999 memcpy (fragP->fr_literal + fragP->fr_fix,
1001 /* Adjust jump offset. */
1002 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1007 /* Maximum length of an instruction is 15 byte. If the
1008 padding is greater than 15 bytes and we don't use jump,
1009 we have to break it into smaller pieces. */
1010 int padding = count;
1011 while (padding > 15)
1014 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1019 memcpy (fragP->fr_literal + fragP->fr_fix,
1020 patt [padding - 1], padding);
1023 fragP->fr_var = count;
1027 operand_type_all_zero (const union i386_operand_type *x)
1029 switch (ARRAY_SIZE(x->array))
1038 return !x->array[0];
1045 operand_type_set (union i386_operand_type *x, unsigned int v)
1047 switch (ARRAY_SIZE(x->array))
1062 operand_type_equal (const union i386_operand_type *x,
1063 const union i386_operand_type *y)
1065 switch (ARRAY_SIZE(x->array))
1068 if (x->array[2] != y->array[2])
1071 if (x->array[1] != y->array[1])
1074 return x->array[0] == y->array[0];
1082 cpu_flags_all_zero (const union i386_cpu_flags *x)
1084 switch (ARRAY_SIZE(x->array))
1093 return !x->array[0];
1100 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1102 switch (ARRAY_SIZE(x->array))
1117 cpu_flags_equal (const union i386_cpu_flags *x,
1118 const union i386_cpu_flags *y)
1120 switch (ARRAY_SIZE(x->array))
1123 if (x->array[2] != y->array[2])
1126 if (x->array[1] != y->array[1])
1129 return x->array[0] == y->array[0];
1137 cpu_flags_check_cpu64 (i386_cpu_flags f)
1139 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1140 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1143 static INLINE i386_cpu_flags
1144 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1146 switch (ARRAY_SIZE (x.array))
1149 x.array [2] &= y.array [2];
1151 x.array [1] &= y.array [1];
1153 x.array [0] &= y.array [0];
1161 static INLINE i386_cpu_flags
1162 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1164 switch (ARRAY_SIZE (x.array))
1167 x.array [2] |= y.array [2];
1169 x.array [1] |= y.array [1];
1171 x.array [0] |= y.array [0];
1179 /* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1180 1 if compatible with arch, 0 if there is no match. */
1183 cpu_flags_match (i386_cpu_flags x)
1185 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
1187 x.bitfield.cpu64 = 0;
1188 x.bitfield.cpuno64 = 0;
1190 if (cpu_flags_all_zero (&x))
1194 i386_cpu_flags cpu = cpu_arch_flags;
1196 cpu.bitfield.cpu64 = 0;
1197 cpu.bitfield.cpuno64 = 0;
1198 cpu = cpu_flags_and (x, cpu);
1199 overlap |= cpu_flags_all_zero (&cpu) ? 0 : 1;
1204 static INLINE i386_operand_type
1205 operand_type_and (i386_operand_type x, i386_operand_type y)
1207 switch (ARRAY_SIZE (x.array))
1210 x.array [2] &= y.array [2];
1212 x.array [1] &= y.array [1];
1214 x.array [0] &= y.array [0];
1222 static INLINE i386_operand_type
1223 operand_type_or (i386_operand_type x, i386_operand_type y)
1225 switch (ARRAY_SIZE (x.array))
1228 x.array [2] |= y.array [2];
1230 x.array [1] |= y.array [1];
1232 x.array [0] |= y.array [0];
1240 static INLINE i386_operand_type
1241 operand_type_xor (i386_operand_type x, i386_operand_type y)
1243 switch (ARRAY_SIZE (x.array))
1246 x.array [2] ^= y.array [2];
1248 x.array [1] ^= y.array [1];
1250 x.array [0] ^= y.array [0];
1258 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1259 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1260 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1261 static const i386_operand_type reg16_inoutportreg
1262 = OPERAND_TYPE_REG16_INOUTPORTREG;
1263 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1264 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1265 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1266 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1267 static const i386_operand_type anydisp
1268 = OPERAND_TYPE_ANYDISP;
1269 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1270 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1271 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1272 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1273 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1274 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1275 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1276 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1277 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1278 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1289 operand_type_check (i386_operand_type t, enum operand_type c)
1294 return (t.bitfield.reg8
1297 || t.bitfield.reg64);
1300 return (t.bitfield.imm8
1304 || t.bitfield.imm32s
1305 || t.bitfield.imm64);
1308 return (t.bitfield.disp8
1309 || t.bitfield.disp16
1310 || t.bitfield.disp32
1311 || t.bitfield.disp32s
1312 || t.bitfield.disp64);
1315 return (t.bitfield.disp8
1316 || t.bitfield.disp16
1317 || t.bitfield.disp32
1318 || t.bitfield.disp32s
1319 || t.bitfield.disp64
1320 || t.bitfield.baseindex);
1327 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1328 operand J for instruction template T. */
1331 match_reg_size (const template *t, unsigned int j)
1333 return !((i.types[j].bitfield.byte
1334 && !t->operand_types[j].bitfield.byte)
1335 || (i.types[j].bitfield.word
1336 && !t->operand_types[j].bitfield.word)
1337 || (i.types[j].bitfield.dword
1338 && !t->operand_types[j].bitfield.dword)
1339 || (i.types[j].bitfield.qword
1340 && !t->operand_types[j].bitfield.qword));
1343 /* Return 1 if there is no conflict in any size on operand J for
1344 instruction template T. */
1347 match_mem_size (const template *t, unsigned int j)
1349 return (match_reg_size (t, j)
1350 && !((i.types[j].bitfield.unspecified
1351 && !t->operand_types[j].bitfield.unspecified)
1352 || (i.types[j].bitfield.fword
1353 && !t->operand_types[j].bitfield.fword)
1354 || (i.types[j].bitfield.tbyte
1355 && !t->operand_types[j].bitfield.tbyte)
1356 || (i.types[j].bitfield.xmmword
1357 && !t->operand_types[j].bitfield.xmmword)));
1360 /* Return 1 if there is no size conflict on any operands for
1361 instruction template T. */
1364 operand_size_match (const template *t)
1369 /* Don't check jump instructions. */
1370 if (t->opcode_modifier.jump
1371 || t->opcode_modifier.jumpbyte
1372 || t->opcode_modifier.jumpdword
1373 || t->opcode_modifier.jumpintersegment)
1376 /* Check memory and accumulator operand size. */
1377 for (j = 0; j < i.operands; j++)
1379 if (t->operand_types[j].bitfield.anysize)
1382 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1388 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1396 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1399 /* Check reverse. */
1400 assert (i.operands == 2);
1403 for (j = 0; j < 2; j++)
1405 if (t->operand_types[j].bitfield.acc
1406 && !match_reg_size (t, j ? 0 : 1))
1412 if (i.types[j].bitfield.mem
1413 && !match_mem_size (t, j ? 0 : 1))
1424 operand_type_match (i386_operand_type overlap,
1425 i386_operand_type given)
1427 i386_operand_type temp = overlap;
1429 temp.bitfield.jumpabsolute = 0;
1430 temp.bitfield.unspecified = 0;
1431 temp.bitfield.byte = 0;
1432 temp.bitfield.word = 0;
1433 temp.bitfield.dword = 0;
1434 temp.bitfield.fword = 0;
1435 temp.bitfield.qword = 0;
1436 temp.bitfield.tbyte = 0;
1437 temp.bitfield.xmmword = 0;
1438 if (operand_type_all_zero (&temp))
1441 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1442 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1445 /* If given types g0 and g1 are registers they must be of the same type
1446 unless the expected operand type register overlap is null.
1447 Note that Acc in a template matches every size of reg. */
1450 operand_type_register_match (i386_operand_type m0,
1451 i386_operand_type g0,
1452 i386_operand_type t0,
1453 i386_operand_type m1,
1454 i386_operand_type g1,
1455 i386_operand_type t1)
1457 if (!operand_type_check (g0, reg))
1460 if (!operand_type_check (g1, reg))
1463 if (g0.bitfield.reg8 == g1.bitfield.reg8
1464 && g0.bitfield.reg16 == g1.bitfield.reg16
1465 && g0.bitfield.reg32 == g1.bitfield.reg32
1466 && g0.bitfield.reg64 == g1.bitfield.reg64)
1469 if (m0.bitfield.acc)
1471 t0.bitfield.reg8 = 1;
1472 t0.bitfield.reg16 = 1;
1473 t0.bitfield.reg32 = 1;
1474 t0.bitfield.reg64 = 1;
1477 if (m1.bitfield.acc)
1479 t1.bitfield.reg8 = 1;
1480 t1.bitfield.reg16 = 1;
1481 t1.bitfield.reg32 = 1;
1482 t1.bitfield.reg64 = 1;
1485 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1486 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1487 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1488 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1491 static INLINE unsigned int
1492 mode_from_disp_size (i386_operand_type t)
1494 if (t.bitfield.disp8)
1496 else if (t.bitfield.disp16
1497 || t.bitfield.disp32
1498 || t.bitfield.disp32s)
1505 fits_in_signed_byte (offsetT num)
1507 return (num >= -128) && (num <= 127);
1511 fits_in_unsigned_byte (offsetT num)
1513 return (num & 0xff) == num;
1517 fits_in_unsigned_word (offsetT num)
1519 return (num & 0xffff) == num;
1523 fits_in_signed_word (offsetT num)
1525 return (-32768 <= num) && (num <= 32767);
1529 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1534 return (!(((offsetT) -1 << 31) & num)
1535 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1537 } /* fits_in_signed_long() */
1540 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1545 return (num & (((offsetT) 2 << 31) - 1)) == num;
1547 } /* fits_in_unsigned_long() */
1549 static i386_operand_type
1550 smallest_imm_type (offsetT num)
1552 i386_operand_type t;
1554 operand_type_set (&t, 0);
1555 t.bitfield.imm64 = 1;
1557 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1559 /* This code is disabled on the 486 because all the Imm1 forms
1560 in the opcode table are slower on the i486. They're the
1561 versions with the implicitly specified single-position
1562 displacement, which has another syntax if you really want to
1564 t.bitfield.imm1 = 1;
1565 t.bitfield.imm8 = 1;
1566 t.bitfield.imm8s = 1;
1567 t.bitfield.imm16 = 1;
1568 t.bitfield.imm32 = 1;
1569 t.bitfield.imm32s = 1;
1571 else if (fits_in_signed_byte (num))
1573 t.bitfield.imm8 = 1;
1574 t.bitfield.imm8s = 1;
1575 t.bitfield.imm16 = 1;
1576 t.bitfield.imm32 = 1;
1577 t.bitfield.imm32s = 1;
1579 else if (fits_in_unsigned_byte (num))
1581 t.bitfield.imm8 = 1;
1582 t.bitfield.imm16 = 1;
1583 t.bitfield.imm32 = 1;
1584 t.bitfield.imm32s = 1;
1586 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1588 t.bitfield.imm16 = 1;
1589 t.bitfield.imm32 = 1;
1590 t.bitfield.imm32s = 1;
1592 else if (fits_in_signed_long (num))
1594 t.bitfield.imm32 = 1;
1595 t.bitfield.imm32s = 1;
1597 else if (fits_in_unsigned_long (num))
1598 t.bitfield.imm32 = 1;
1604 offset_in_range (offsetT val, int size)
1610 case 1: mask = ((addressT) 1 << 8) - 1; break;
1611 case 2: mask = ((addressT) 1 << 16) - 1; break;
1612 case 4: mask = ((addressT) 2 << 31) - 1; break;
1614 case 8: mask = ((addressT) 2 << 63) - 1; break;
1619 /* If BFD64, sign extend val. */
1620 if (!use_rela_relocations)
1621 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1622 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1624 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1626 char buf1[40], buf2[40];
1628 sprint_value (buf1, val);
1629 sprint_value (buf2, val & mask);
1630 as_warn (_("%s shortened to %s"), buf1, buf2);
1635 /* Returns 0 if attempting to add a prefix where one from the same
1636 class already exists, 1 if non rep/repne added, 2 if rep/repne
1639 add_prefix (unsigned int prefix)
1644 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1645 && flag_code == CODE_64BIT)
1647 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1648 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1649 && (prefix & (REX_R | REX_X | REX_B))))
1660 case CS_PREFIX_OPCODE:
1661 case DS_PREFIX_OPCODE:
1662 case ES_PREFIX_OPCODE:
1663 case FS_PREFIX_OPCODE:
1664 case GS_PREFIX_OPCODE:
1665 case SS_PREFIX_OPCODE:
1669 case REPNE_PREFIX_OPCODE:
1670 case REPE_PREFIX_OPCODE:
1673 case LOCK_PREFIX_OPCODE:
1681 case ADDR_PREFIX_OPCODE:
1685 case DATA_PREFIX_OPCODE:
1689 if (i.prefix[q] != 0)
1697 i.prefix[q] |= prefix;
1700 as_bad (_("same type of prefix used twice"));
1706 set_code_flag (int value)
1709 if (flag_code == CODE_64BIT)
1711 cpu_arch_flags.bitfield.cpu64 = 1;
1712 cpu_arch_flags.bitfield.cpuno64 = 0;
1716 cpu_arch_flags.bitfield.cpu64 = 0;
1717 cpu_arch_flags.bitfield.cpuno64 = 1;
1719 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1721 as_bad (_("64bit mode not supported on this CPU."));
1723 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1725 as_bad (_("32bit mode not supported on this CPU."));
1727 stackop_size = '\0';
1731 set_16bit_gcc_code_flag (int new_code_flag)
1733 flag_code = new_code_flag;
1734 if (flag_code != CODE_16BIT)
1736 cpu_arch_flags.bitfield.cpu64 = 0;
1737 cpu_arch_flags.bitfield.cpuno64 = 1;
1738 stackop_size = LONG_MNEM_SUFFIX;
1742 set_intel_syntax (int syntax_flag)
1744 /* Find out if register prefixing is specified. */
1745 int ask_naked_reg = 0;
1748 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1750 char *string = input_line_pointer;
1751 int e = get_symbol_end ();
1753 if (strcmp (string, "prefix") == 0)
1755 else if (strcmp (string, "noprefix") == 0)
1758 as_bad (_("bad argument to syntax directive."));
1759 *input_line_pointer = e;
1761 demand_empty_rest_of_line ();
1763 intel_syntax = syntax_flag;
1765 if (ask_naked_reg == 0)
1766 allow_naked_reg = (intel_syntax
1767 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1769 allow_naked_reg = (ask_naked_reg < 0);
1771 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1772 identifier_chars['$'] = intel_syntax ? '$' : 0;
1773 register_prefix = allow_naked_reg ? "" : "%";
1777 set_intel_mnemonic (int mnemonic_flag)
1779 intel_mnemonic = mnemonic_flag;
1783 set_allow_index_reg (int flag)
1785 allow_index_reg = flag;
1789 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1793 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1795 char *string = input_line_pointer;
1796 int e = get_symbol_end ();
1798 i386_cpu_flags flags;
1800 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1802 if (strcmp (string, cpu_arch[i].name) == 0)
1806 cpu_arch_name = cpu_arch[i].name;
1807 cpu_sub_arch_name = NULL;
1808 cpu_arch_flags = cpu_arch[i].flags;
1809 if (flag_code == CODE_64BIT)
1811 cpu_arch_flags.bitfield.cpu64 = 1;
1812 cpu_arch_flags.bitfield.cpuno64 = 0;
1816 cpu_arch_flags.bitfield.cpu64 = 0;
1817 cpu_arch_flags.bitfield.cpuno64 = 1;
1819 cpu_arch_isa = cpu_arch[i].type;
1820 cpu_arch_isa_flags = cpu_arch[i].flags;
1821 if (!cpu_arch_tune_set)
1823 cpu_arch_tune = cpu_arch_isa;
1824 cpu_arch_tune_flags = cpu_arch_isa_flags;
1829 flags = cpu_flags_or (cpu_arch_flags,
1831 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1833 if (cpu_sub_arch_name)
1835 char *name = cpu_sub_arch_name;
1836 cpu_sub_arch_name = concat (name,
1838 (const char *) NULL);
1842 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1843 cpu_arch_flags = flags;
1845 *input_line_pointer = e;
1846 demand_empty_rest_of_line ();
1850 if (i >= ARRAY_SIZE (cpu_arch))
1851 as_bad (_("no such architecture: `%s'"), string);
1853 *input_line_pointer = e;
1856 as_bad (_("missing cpu architecture"));
1858 no_cond_jump_promotion = 0;
1859 if (*input_line_pointer == ','
1860 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1862 char *string = ++input_line_pointer;
1863 int e = get_symbol_end ();
1865 if (strcmp (string, "nojumps") == 0)
1866 no_cond_jump_promotion = 1;
1867 else if (strcmp (string, "jumps") == 0)
1870 as_bad (_("no such architecture modifier: `%s'"), string);
1872 *input_line_pointer = e;
1875 demand_empty_rest_of_line ();
1881 if (!strcmp (default_arch, "x86_64"))
1882 return bfd_mach_x86_64;
1883 else if (!strcmp (default_arch, "i386"))
1884 return bfd_mach_i386_i386;
1886 as_fatal (_("Unknown architecture"));
1892 const char *hash_err;
1894 /* Initialize op_hash hash table. */
1895 op_hash = hash_new ();
1898 const template *optab;
1899 templates *core_optab;
1901 /* Setup for loop. */
1903 core_optab = (templates *) xmalloc (sizeof (templates));
1904 core_optab->start = optab;
1909 if (optab->name == NULL
1910 || strcmp (optab->name, (optab - 1)->name) != 0)
1912 /* different name --> ship out current template list;
1913 add to hash table; & begin anew. */
1914 core_optab->end = optab;
1915 hash_err = hash_insert (op_hash,
1920 as_fatal (_("Internal Error: Can't hash %s: %s"),
1924 if (optab->name == NULL)
1926 core_optab = (templates *) xmalloc (sizeof (templates));
1927 core_optab->start = optab;
1932 /* Initialize reg_hash hash table. */
1933 reg_hash = hash_new ();
1935 const reg_entry *regtab;
1936 unsigned int regtab_size = i386_regtab_size;
1938 for (regtab = i386_regtab; regtab_size--; regtab++)
1940 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1942 as_fatal (_("Internal Error: Can't hash %s: %s"),
1948 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1953 for (c = 0; c < 256; c++)
1958 mnemonic_chars[c] = c;
1959 register_chars[c] = c;
1960 operand_chars[c] = c;
1962 else if (ISLOWER (c))
1964 mnemonic_chars[c] = c;
1965 register_chars[c] = c;
1966 operand_chars[c] = c;
1968 else if (ISUPPER (c))
1970 mnemonic_chars[c] = TOLOWER (c);
1971 register_chars[c] = mnemonic_chars[c];
1972 operand_chars[c] = c;
1975 if (ISALPHA (c) || ISDIGIT (c))
1976 identifier_chars[c] = c;
1979 identifier_chars[c] = c;
1980 operand_chars[c] = c;
1985 identifier_chars['@'] = '@';
1988 identifier_chars['?'] = '?';
1989 operand_chars['?'] = '?';
1991 digit_chars['-'] = '-';
1992 mnemonic_chars['-'] = '-';
1993 mnemonic_chars['.'] = '.';
1994 identifier_chars['_'] = '_';
1995 identifier_chars['.'] = '.';
1997 for (p = operand_special_chars; *p != '\0'; p++)
1998 operand_chars[(unsigned char) *p] = *p;
2001 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2004 record_alignment (text_section, 2);
2005 record_alignment (data_section, 2);
2006 record_alignment (bss_section, 2);
2010 if (flag_code == CODE_64BIT)
2012 x86_dwarf2_return_column = 16;
2013 x86_cie_data_alignment = -8;
2017 x86_dwarf2_return_column = 8;
2018 x86_cie_data_alignment = -4;
2023 i386_print_statistics (FILE *file)
2025 hash_print_statistics (file, "i386 opcode", op_hash);
2026 hash_print_statistics (file, "i386 register", reg_hash);
2031 /* Debugging routines for md_assemble. */
2032 static void pte (template *);
2033 static void pt (i386_operand_type);
2034 static void pe (expressionS *);
2035 static void ps (symbolS *);
2038 pi (char *line, i386_insn *x)
2042 fprintf (stdout, "%s: template ", line);
2044 fprintf (stdout, " address: base %s index %s scale %x\n",
2045 x->base_reg ? x->base_reg->reg_name : "none",
2046 x->index_reg ? x->index_reg->reg_name : "none",
2047 x->log2_scale_factor);
2048 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2049 x->rm.mode, x->rm.reg, x->rm.regmem);
2050 fprintf (stdout, " sib: base %x index %x scale %x\n",
2051 x->sib.base, x->sib.index, x->sib.scale);
2052 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2053 (x->rex & REX_W) != 0,
2054 (x->rex & REX_R) != 0,
2055 (x->rex & REX_X) != 0,
2056 (x->rex & REX_B) != 0);
2057 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2058 x->drex.reg, x->drex.rex);
2059 for (i = 0; i < x->operands; i++)
2061 fprintf (stdout, " #%d: ", i + 1);
2063 fprintf (stdout, "\n");
2064 if (x->types[i].bitfield.reg8
2065 || x->types[i].bitfield.reg16
2066 || x->types[i].bitfield.reg32
2067 || x->types[i].bitfield.reg64
2068 || x->types[i].bitfield.regmmx
2069 || x->types[i].bitfield.regxmm
2070 || x->types[i].bitfield.sreg2
2071 || x->types[i].bitfield.sreg3
2072 || x->types[i].bitfield.control
2073 || x->types[i].bitfield.debug
2074 || x->types[i].bitfield.test)
2075 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2076 if (operand_type_check (x->types[i], imm))
2078 if (operand_type_check (x->types[i], disp))
2079 pe (x->op[i].disps);
2087 fprintf (stdout, " %d operands ", t->operands);
2088 fprintf (stdout, "opcode %x ", t->base_opcode);
2089 if (t->extension_opcode != None)
2090 fprintf (stdout, "ext %x ", t->extension_opcode);
2091 if (t->opcode_modifier.d)
2092 fprintf (stdout, "D");
2093 if (t->opcode_modifier.w)
2094 fprintf (stdout, "W");
2095 fprintf (stdout, "\n");
2096 for (i = 0; i < t->operands; i++)
2098 fprintf (stdout, " #%d type ", i + 1);
2099 pt (t->operand_types[i]);
2100 fprintf (stdout, "\n");
2107 fprintf (stdout, " operation %d\n", e->X_op);
2108 fprintf (stdout, " add_number %ld (%lx)\n",
2109 (long) e->X_add_number, (long) e->X_add_number);
2110 if (e->X_add_symbol)
2112 fprintf (stdout, " add_symbol ");
2113 ps (e->X_add_symbol);
2114 fprintf (stdout, "\n");
2118 fprintf (stdout, " op_symbol ");
2119 ps (e->X_op_symbol);
2120 fprintf (stdout, "\n");
2127 fprintf (stdout, "%s type %s%s",
2129 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2130 segment_name (S_GET_SEGMENT (s)));
2133 static struct type_name
2135 i386_operand_type mask;
2138 const type_names[] =
2140 { OPERAND_TYPE_REG8, "r8" },
2141 { OPERAND_TYPE_REG16, "r16" },
2142 { OPERAND_TYPE_REG32, "r32" },
2143 { OPERAND_TYPE_REG64, "r64" },
2144 { OPERAND_TYPE_IMM8, "i8" },
2145 { OPERAND_TYPE_IMM8, "i8s" },
2146 { OPERAND_TYPE_IMM16, "i16" },
2147 { OPERAND_TYPE_IMM32, "i32" },
2148 { OPERAND_TYPE_IMM32S, "i32s" },
2149 { OPERAND_TYPE_IMM64, "i64" },
2150 { OPERAND_TYPE_IMM1, "i1" },
2151 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2152 { OPERAND_TYPE_DISP8, "d8" },
2153 { OPERAND_TYPE_DISP16, "d16" },
2154 { OPERAND_TYPE_DISP32, "d32" },
2155 { OPERAND_TYPE_DISP32S, "d32s" },
2156 { OPERAND_TYPE_DISP64, "d64" },
2157 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2158 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2159 { OPERAND_TYPE_CONTROL, "control reg" },
2160 { OPERAND_TYPE_TEST, "test reg" },
2161 { OPERAND_TYPE_DEBUG, "debug reg" },
2162 { OPERAND_TYPE_FLOATREG, "FReg" },
2163 { OPERAND_TYPE_FLOATACC, "FAcc" },
2164 { OPERAND_TYPE_SREG2, "SReg2" },
2165 { OPERAND_TYPE_SREG3, "SReg3" },
2166 { OPERAND_TYPE_ACC, "Acc" },
2167 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2168 { OPERAND_TYPE_REGMMX, "rMMX" },
2169 { OPERAND_TYPE_REGXMM, "rXMM" },
2170 { OPERAND_TYPE_ESSEG, "es" },
2174 pt (i386_operand_type t)
2177 i386_operand_type a;
2179 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2181 a = operand_type_and (t, type_names[j].mask);
2182 if (!UINTS_ALL_ZERO (a))
2183 fprintf (stdout, "%s, ", type_names[j].name);
2188 #endif /* DEBUG386 */
2190 static bfd_reloc_code_real_type
2191 reloc (unsigned int size,
2194 bfd_reloc_code_real_type other)
2196 if (other != NO_RELOC)
2198 reloc_howto_type *reloc;
2203 case BFD_RELOC_X86_64_GOT32:
2204 return BFD_RELOC_X86_64_GOT64;
2206 case BFD_RELOC_X86_64_PLTOFF64:
2207 return BFD_RELOC_X86_64_PLTOFF64;
2209 case BFD_RELOC_X86_64_GOTPC32:
2210 other = BFD_RELOC_X86_64_GOTPC64;
2212 case BFD_RELOC_X86_64_GOTPCREL:
2213 other = BFD_RELOC_X86_64_GOTPCREL64;
2215 case BFD_RELOC_X86_64_TPOFF32:
2216 other = BFD_RELOC_X86_64_TPOFF64;
2218 case BFD_RELOC_X86_64_DTPOFF32:
2219 other = BFD_RELOC_X86_64_DTPOFF64;
2225 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2226 if (size == 4 && flag_code != CODE_64BIT)
2229 reloc = bfd_reloc_type_lookup (stdoutput, other);
2231 as_bad (_("unknown relocation (%u)"), other);
2232 else if (size != bfd_get_reloc_size (reloc))
2233 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2234 bfd_get_reloc_size (reloc),
2236 else if (pcrel && !reloc->pc_relative)
2237 as_bad (_("non-pc-relative relocation for pc-relative field"));
2238 else if ((reloc->complain_on_overflow == complain_overflow_signed
2240 || (reloc->complain_on_overflow == complain_overflow_unsigned
2242 as_bad (_("relocated field and relocation type differ in signedness"));
2251 as_bad (_("there are no unsigned pc-relative relocations"));
2254 case 1: return BFD_RELOC_8_PCREL;
2255 case 2: return BFD_RELOC_16_PCREL;
2256 case 4: return BFD_RELOC_32_PCREL;
2257 case 8: return BFD_RELOC_64_PCREL;
2259 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2266 case 4: return BFD_RELOC_X86_64_32S;
2271 case 1: return BFD_RELOC_8;
2272 case 2: return BFD_RELOC_16;
2273 case 4: return BFD_RELOC_32;
2274 case 8: return BFD_RELOC_64;
2276 as_bad (_("cannot do %s %u byte relocation"),
2277 sign > 0 ? "signed" : "unsigned", size);
2281 return BFD_RELOC_NONE;
2284 /* Here we decide which fixups can be adjusted to make them relative to
2285 the beginning of the section instead of the symbol. Basically we need
2286 to make sure that the dynamic relocations are done correctly, so in
2287 some cases we force the original symbol to be used. */
2290 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2292 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2296 /* Don't adjust pc-relative references to merge sections in 64-bit
2298 if (use_rela_relocations
2299 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2303 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2304 and changed later by validate_fix. */
2305 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2306 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2309 /* adjust_reloc_syms doesn't know about the GOT. */
2310 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2311 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2312 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2313 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2314 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2315 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2316 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2317 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2318 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2319 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2320 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2321 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2322 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2323 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2324 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2325 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2326 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2327 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2328 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2329 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2330 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2331 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2332 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2333 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2334 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2335 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2336 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2337 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2344 intel_float_operand (const char *mnemonic)
2346 /* Note that the value returned is meaningful only for opcodes with (memory)
2347 operands, hence the code here is free to improperly handle opcodes that
2348 have no operands (for better performance and smaller code). */
2350 if (mnemonic[0] != 'f')
2351 return 0; /* non-math */
2353 switch (mnemonic[1])
2355 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2356 the fs segment override prefix not currently handled because no
2357 call path can make opcodes without operands get here */
2359 return 2 /* integer op */;
2361 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2362 return 3; /* fldcw/fldenv */
2365 if (mnemonic[2] != 'o' /* fnop */)
2366 return 3; /* non-waiting control op */
2369 if (mnemonic[2] == 's')
2370 return 3; /* frstor/frstpm */
2373 if (mnemonic[2] == 'a')
2374 return 3; /* fsave */
2375 if (mnemonic[2] == 't')
2377 switch (mnemonic[3])
2379 case 'c': /* fstcw */
2380 case 'd': /* fstdw */
2381 case 'e': /* fstenv */
2382 case 's': /* fsts[gw] */
2388 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2389 return 0; /* fxsave/fxrstor are not really math ops */
2396 /* This is the guts of the machine-dependent assembler. LINE points to a
2397 machine dependent instruction. This function is supposed to emit
2398 the frags/bytes it assembles to. */
2405 char mnemonic[MAX_MNEM_SIZE];
2407 /* Initialize globals. */
2408 memset (&i, '\0', sizeof (i));
2409 for (j = 0; j < MAX_OPERANDS; j++)
2410 i.reloc[j] = NO_RELOC;
2411 memset (disp_expressions, '\0', sizeof (disp_expressions));
2412 memset (im_expressions, '\0', sizeof (im_expressions));
2413 save_stack_p = save_stack;
2415 /* First parse an instruction mnemonic & call i386_operand for the operands.
2416 We assume that the scrubber has arranged it so that line[0] is the valid
2417 start of a (possibly prefixed) mnemonic. */
2419 line = parse_insn (line, mnemonic);
2423 line = parse_operands (line, mnemonic);
2427 /* Now we've parsed the mnemonic into a set of templates, and have the
2428 operands at hand. */
2430 /* All intel opcodes have reversed operands except for "bound" and
2431 "enter". We also don't reverse intersegment "jmp" and "call"
2432 instructions with 2 immediate operands so that the immediate segment
2433 precedes the offset, as it does when in AT&T mode. */
2436 && (strcmp (mnemonic, "bound") != 0)
2437 && (strcmp (mnemonic, "invlpga") != 0)
2438 && !(operand_type_check (i.types[0], imm)
2439 && operand_type_check (i.types[1], imm)))
2442 /* The order of the immediates should be reversed
2443 for 2 immediates extrq and insertq instructions */
2444 if (i.imm_operands == 2
2445 && (strcmp (mnemonic, "extrq") == 0
2446 || strcmp (mnemonic, "insertq") == 0))
2447 swap_2_operands (0, 1);
2452 /* Don't optimize displacement for movabs since it only takes 64bit
2455 && (flag_code != CODE_64BIT
2456 || strcmp (mnemonic, "movabs") != 0))
2459 /* Next, we find a template that matches the given insn,
2460 making sure the overlap of the given operands types is consistent
2461 with the template operand types. */
2463 if (!match_template ())
2466 /* Zap movzx and movsx suffix. The suffix has been set from
2467 "word ptr" or "byte ptr" on the source operand in Intel syntax
2468 or extracted from mnemonic in AT&T syntax. But we'll use
2469 the destination register to choose the suffix for encoding. */
2470 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2472 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2473 there is no suffix, the default will be byte extension. */
2474 if (i.reg_operands != 2
2477 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2482 if (i.tm.opcode_modifier.fwait)
2483 if (!add_prefix (FWAIT_OPCODE))
2486 /* Check string instruction segment overrides. */
2487 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2489 if (!check_string ())
2493 if (!process_suffix ())
2496 /* Make still unresolved immediate matches conform to size of immediate
2497 given in i.suffix. */
2498 if (!finalize_imm ())
2501 if (i.types[0].bitfield.imm1)
2502 i.imm_operands = 0; /* kludge for shift insns. */
2504 for (j = 0; j < 3; j++)
2505 if (i.types[j].bitfield.inoutportreg
2506 || i.types[j].bitfield.shiftcount
2507 || i.types[j].bitfield.acc
2508 || i.types[j].bitfield.floatacc)
2511 if (i.tm.opcode_modifier.immext)
2515 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2517 /* Streaming SIMD extensions 3 Instructions have the fixed
2518 operands with an opcode suffix which is coded in the same
2519 place as an 8-bit immediate field would be. Here we check
2520 those operands and remove them afterwards. */
2523 for (x = 0; x < i.operands; x++)
2524 if (i.op[x].regs->reg_num != x)
2525 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2527 i.op[x].regs->reg_name,
2533 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2534 opcode suffix which is coded in the same place as an 8-bit
2535 immediate field would be. Here we fake an 8-bit immediate
2536 operand from the opcode suffix stored in tm.extension_opcode.
2537 SSE5 also uses this encoding, for some of its 3 argument
2540 assert (i.imm_operands == 0
2542 || (i.tm.cpu_flags.bitfield.cpusse5
2543 && i.operands <= 3)));
2545 exp = &im_expressions[i.imm_operands++];
2546 i.op[i.operands].imms = exp;
2547 operand_type_set (&i.types[i.operands], 0);
2548 i.types[i.operands].bitfield.imm8 = 1;
2550 exp->X_op = O_constant;
2551 exp->X_add_number = i.tm.extension_opcode;
2552 i.tm.extension_opcode = None;
2555 /* For insns with operands there are more diddles to do to the opcode. */
2558 if (!process_operands ())
2561 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2563 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2564 as_warn (_("translating to `%sp'"), i.tm.name);
2567 /* Handle conversion of 'int $3' --> special int3 insn. */
2568 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2570 i.tm.base_opcode = INT3_OPCODE;
2574 if ((i.tm.opcode_modifier.jump
2575 || i.tm.opcode_modifier.jumpbyte
2576 || i.tm.opcode_modifier.jumpdword)
2577 && i.op[0].disps->X_op == O_constant)
2579 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2580 the absolute address given by the constant. Since ix86 jumps and
2581 calls are pc relative, we need to generate a reloc. */
2582 i.op[0].disps->X_add_symbol = &abs_symbol;
2583 i.op[0].disps->X_op = O_symbol;
2586 if (i.tm.opcode_modifier.rex64)
2589 /* For 8 bit registers we need an empty rex prefix. Also if the
2590 instruction already has a prefix, we need to convert old
2591 registers to new ones. */
2593 if ((i.types[0].bitfield.reg8
2594 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2595 || (i.types[1].bitfield.reg8
2596 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2597 || ((i.types[0].bitfield.reg8
2598 || i.types[1].bitfield.reg8)
2603 i.rex |= REX_OPCODE;
2604 for (x = 0; x < 2; x++)
2606 /* Look for 8 bit operand that uses old registers. */
2607 if (i.types[x].bitfield.reg8
2608 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2610 /* In case it is "hi" register, give up. */
2611 if (i.op[x].regs->reg_num > 3)
2612 as_bad (_("can't encode register '%s%s' in an "
2613 "instruction requiring REX prefix."),
2614 register_prefix, i.op[x].regs->reg_name);
2616 /* Otherwise it is equivalent to the extended register.
2617 Since the encoding doesn't change this is merely
2618 cosmetic cleanup for debug output. */
2620 i.op[x].regs = i.op[x].regs + 8;
2625 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2627 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2632 else if (i.rex != 0)
2633 add_prefix (REX_OPCODE | i.rex);
2635 /* We are ready to output the insn. */
2640 parse_insn (char *line, char *mnemonic)
2643 char *token_start = l;
2648 /* Non-zero if we found a prefix only acceptable with string insns. */
2649 const char *expecting_string_instruction = NULL;
2654 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2657 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2659 as_bad (_("no such instruction: `%s'"), token_start);
2664 if (!is_space_char (*l)
2665 && *l != END_OF_INSN
2667 || (*l != PREFIX_SEPARATOR
2670 as_bad (_("invalid character %s in mnemonic"),
2671 output_invalid (*l));
2674 if (token_start == l)
2676 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2677 as_bad (_("expecting prefix; got nothing"));
2679 as_bad (_("expecting mnemonic; got nothing"));
2683 /* Look up instruction (or prefix) via hash table. */
2684 current_templates = hash_find (op_hash, mnemonic);
2686 if (*l != END_OF_INSN
2687 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2688 && current_templates
2689 && current_templates->start->opcode_modifier.isprefix)
2691 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2693 as_bad ((flag_code != CODE_64BIT
2694 ? _("`%s' is only supported in 64-bit mode")
2695 : _("`%s' is not supported in 64-bit mode")),
2696 current_templates->start->name);
2699 /* If we are in 16-bit mode, do not allow addr16 or data16.
2700 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2701 if ((current_templates->start->opcode_modifier.size16
2702 || current_templates->start->opcode_modifier.size32)
2703 && flag_code != CODE_64BIT
2704 && (current_templates->start->opcode_modifier.size32
2705 ^ (flag_code == CODE_16BIT)))
2707 as_bad (_("redundant %s prefix"),
2708 current_templates->start->name);
2711 /* Add prefix, checking for repeated prefixes. */
2712 switch (add_prefix (current_templates->start->base_opcode))
2717 expecting_string_instruction = current_templates->start->name;
2720 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2727 if (!current_templates)
2729 /* See if we can get a match by trimming off a suffix. */
2732 case WORD_MNEM_SUFFIX:
2733 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2734 i.suffix = SHORT_MNEM_SUFFIX;
2736 case BYTE_MNEM_SUFFIX:
2737 case QWORD_MNEM_SUFFIX:
2738 i.suffix = mnem_p[-1];
2740 current_templates = hash_find (op_hash, mnemonic);
2742 case SHORT_MNEM_SUFFIX:
2743 case LONG_MNEM_SUFFIX:
2746 i.suffix = mnem_p[-1];
2748 current_templates = hash_find (op_hash, mnemonic);
2756 if (intel_float_operand (mnemonic) == 1)
2757 i.suffix = SHORT_MNEM_SUFFIX;
2759 i.suffix = LONG_MNEM_SUFFIX;
2761 current_templates = hash_find (op_hash, mnemonic);
2765 if (!current_templates)
2767 as_bad (_("no such instruction: `%s'"), token_start);
2772 if (current_templates->start->opcode_modifier.jump
2773 || current_templates->start->opcode_modifier.jumpbyte)
2775 /* Check for a branch hint. We allow ",pt" and ",pn" for
2776 predict taken and predict not taken respectively.
2777 I'm not sure that branch hints actually do anything on loop
2778 and jcxz insns (JumpByte) for current Pentium4 chips. They
2779 may work in the future and it doesn't hurt to accept them
2781 if (l[0] == ',' && l[1] == 'p')
2785 if (!add_prefix (DS_PREFIX_OPCODE))
2789 else if (l[2] == 'n')
2791 if (!add_prefix (CS_PREFIX_OPCODE))
2797 /* Any other comma loses. */
2800 as_bad (_("invalid character %s in mnemonic"),
2801 output_invalid (*l));
2805 /* Check if instruction is supported on specified architecture. */
2807 for (t = current_templates->start; t < current_templates->end; ++t)
2809 supported |= cpu_flags_match (t->cpu_flags);
2814 if (!(supported & 2))
2816 as_bad (flag_code == CODE_64BIT
2817 ? _("`%s' is not supported in 64-bit mode")
2818 : _("`%s' is only supported in 64-bit mode"),
2819 current_templates->start->name);
2822 if (!(supported & 1))
2824 as_bad (_("`%s' is not supported on `%s%s'"),
2825 current_templates->start->name, cpu_arch_name,
2826 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2831 if (!cpu_arch_flags.bitfield.cpui386
2832 && (flag_code != CODE_16BIT))
2834 as_warn (_("use .code16 to ensure correct addressing mode"));
2837 /* Check for rep/repne without a string instruction. */
2838 if (expecting_string_instruction)
2840 static templates override;
2842 for (t = current_templates->start; t < current_templates->end; ++t)
2843 if (t->opcode_modifier.isstring)
2845 if (t >= current_templates->end)
2847 as_bad (_("expecting string instruction after `%s'"),
2848 expecting_string_instruction);
2851 for (override.start = t; t < current_templates->end; ++t)
2852 if (!t->opcode_modifier.isstring)
2855 current_templates = &override;
2862 parse_operands (char *l, const char *mnemonic)
2866 /* 1 if operand is pending after ','. */
2867 unsigned int expecting_operand = 0;
2869 /* Non-zero if operand parens not balanced. */
2870 unsigned int paren_not_balanced;
2872 while (*l != END_OF_INSN)
2874 /* Skip optional white space before operand. */
2875 if (is_space_char (*l))
2877 if (!is_operand_char (*l) && *l != END_OF_INSN)
2879 as_bad (_("invalid character %s before operand %d"),
2880 output_invalid (*l),
2884 token_start = l; /* after white space */
2885 paren_not_balanced = 0;
2886 while (paren_not_balanced || *l != ',')
2888 if (*l == END_OF_INSN)
2890 if (paren_not_balanced)
2893 as_bad (_("unbalanced parenthesis in operand %d."),
2896 as_bad (_("unbalanced brackets in operand %d."),
2901 break; /* we are done */
2903 else if (!is_operand_char (*l) && !is_space_char (*l))
2905 as_bad (_("invalid character %s in operand %d"),
2906 output_invalid (*l),
2913 ++paren_not_balanced;
2915 --paren_not_balanced;
2920 ++paren_not_balanced;
2922 --paren_not_balanced;
2926 if (l != token_start)
2927 { /* Yes, we've read in another operand. */
2928 unsigned int operand_ok;
2929 this_operand = i.operands++;
2930 i.types[this_operand].bitfield.unspecified = 1;
2931 if (i.operands > MAX_OPERANDS)
2933 as_bad (_("spurious operands; (%d operands/instruction max)"),
2937 /* Now parse operand adding info to 'i' as we go along. */
2938 END_STRING_AND_SAVE (l);
2942 i386_intel_operand (token_start,
2943 intel_float_operand (mnemonic));
2945 operand_ok = i386_att_operand (token_start);
2947 RESTORE_END_STRING (l);
2953 if (expecting_operand)
2955 expecting_operand_after_comma:
2956 as_bad (_("expecting operand after ','; got nothing"));
2961 as_bad (_("expecting operand before ','; got nothing"));
2966 /* Now *l must be either ',' or END_OF_INSN. */
2969 if (*++l == END_OF_INSN)
2971 /* Just skip it, if it's \n complain. */
2972 goto expecting_operand_after_comma;
2974 expecting_operand = 1;
2981 swap_2_operands (int xchg1, int xchg2)
2983 union i386_op temp_op;
2984 i386_operand_type temp_type;
2985 enum bfd_reloc_code_real temp_reloc;
2987 temp_type = i.types[xchg2];
2988 i.types[xchg2] = i.types[xchg1];
2989 i.types[xchg1] = temp_type;
2990 temp_op = i.op[xchg2];
2991 i.op[xchg2] = i.op[xchg1];
2992 i.op[xchg1] = temp_op;
2993 temp_reloc = i.reloc[xchg2];
2994 i.reloc[xchg2] = i.reloc[xchg1];
2995 i.reloc[xchg1] = temp_reloc;
2999 swap_operands (void)
3004 swap_2_operands (1, i.operands - 2);
3007 swap_2_operands (0, i.operands - 1);
3013 if (i.mem_operands == 2)
3015 const seg_entry *temp_seg;
3016 temp_seg = i.seg[0];
3017 i.seg[0] = i.seg[1];
3018 i.seg[1] = temp_seg;
3022 /* Try to ensure constant immediates are represented in the smallest
3027 char guess_suffix = 0;
3031 guess_suffix = i.suffix;
3032 else if (i.reg_operands)
3034 /* Figure out a suffix from the last register operand specified.
3035 We can't do this properly yet, ie. excluding InOutPortReg,
3036 but the following works for instructions with immediates.
3037 In any case, we can't set i.suffix yet. */
3038 for (op = i.operands; --op >= 0;)
3039 if (i.types[op].bitfield.reg8)
3041 guess_suffix = BYTE_MNEM_SUFFIX;
3044 else if (i.types[op].bitfield.reg16)
3046 guess_suffix = WORD_MNEM_SUFFIX;
3049 else if (i.types[op].bitfield.reg32)
3051 guess_suffix = LONG_MNEM_SUFFIX;
3054 else if (i.types[op].bitfield.reg64)
3056 guess_suffix = QWORD_MNEM_SUFFIX;
3060 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3061 guess_suffix = WORD_MNEM_SUFFIX;
3063 for (op = i.operands; --op >= 0;)
3064 if (operand_type_check (i.types[op], imm))
3066 switch (i.op[op].imms->X_op)
3069 /* If a suffix is given, this operand may be shortened. */
3070 switch (guess_suffix)
3072 case LONG_MNEM_SUFFIX:
3073 i.types[op].bitfield.imm32 = 1;
3074 i.types[op].bitfield.imm64 = 1;
3076 case WORD_MNEM_SUFFIX:
3077 i.types[op].bitfield.imm16 = 1;
3078 i.types[op].bitfield.imm32 = 1;
3079 i.types[op].bitfield.imm32s = 1;
3080 i.types[op].bitfield.imm64 = 1;
3082 case BYTE_MNEM_SUFFIX:
3083 i.types[op].bitfield.imm8 = 1;
3084 i.types[op].bitfield.imm8s = 1;
3085 i.types[op].bitfield.imm16 = 1;
3086 i.types[op].bitfield.imm32 = 1;
3087 i.types[op].bitfield.imm32s = 1;
3088 i.types[op].bitfield.imm64 = 1;
3092 /* If this operand is at most 16 bits, convert it
3093 to a signed 16 bit number before trying to see
3094 whether it will fit in an even smaller size.
3095 This allows a 16-bit operand such as $0xffe0 to
3096 be recognised as within Imm8S range. */
3097 if ((i.types[op].bitfield.imm16)
3098 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3100 i.op[op].imms->X_add_number =
3101 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3103 if ((i.types[op].bitfield.imm32)
3104 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3107 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3108 ^ ((offsetT) 1 << 31))
3109 - ((offsetT) 1 << 31));
3112 = operand_type_or (i.types[op],
3113 smallest_imm_type (i.op[op].imms->X_add_number));
3115 /* We must avoid matching of Imm32 templates when 64bit
3116 only immediate is available. */
3117 if (guess_suffix == QWORD_MNEM_SUFFIX)
3118 i.types[op].bitfield.imm32 = 0;
3125 /* Symbols and expressions. */
3127 /* Convert symbolic operand to proper sizes for matching, but don't
3128 prevent matching a set of insns that only supports sizes other
3129 than those matching the insn suffix. */
3131 i386_operand_type mask, allowed;
3134 operand_type_set (&mask, 0);
3135 operand_type_set (&allowed, 0);
3137 for (t = current_templates->start;
3138 t < current_templates->end;
3140 allowed = operand_type_or (allowed,
3141 t->operand_types[op]);
3142 switch (guess_suffix)
3144 case QWORD_MNEM_SUFFIX:
3145 mask.bitfield.imm64 = 1;
3146 mask.bitfield.imm32s = 1;
3148 case LONG_MNEM_SUFFIX:
3149 mask.bitfield.imm32 = 1;
3151 case WORD_MNEM_SUFFIX:
3152 mask.bitfield.imm16 = 1;
3154 case BYTE_MNEM_SUFFIX:
3155 mask.bitfield.imm8 = 1;
3160 allowed = operand_type_and (mask, allowed);
3161 if (!operand_type_all_zero (&allowed))
3162 i.types[op] = operand_type_and (i.types[op], mask);
3169 /* Try to use the smallest displacement type too. */
3171 optimize_disp (void)
3175 for (op = i.operands; --op >= 0;)
3176 if (operand_type_check (i.types[op], disp))
3178 if (i.op[op].disps->X_op == O_constant)
3180 offsetT disp = i.op[op].disps->X_add_number;
3182 if (i.types[op].bitfield.disp16
3183 && (disp & ~(offsetT) 0xffff) == 0)
3185 /* If this operand is at most 16 bits, convert
3186 to a signed 16 bit number and don't use 64bit
3188 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3189 i.types[op].bitfield.disp64 = 0;
3191 if (i.types[op].bitfield.disp32
3192 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3194 /* If this operand is at most 32 bits, convert
3195 to a signed 32 bit number and don't use 64bit
3197 disp &= (((offsetT) 2 << 31) - 1);
3198 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3199 i.types[op].bitfield.disp64 = 0;
3201 if (!disp && i.types[op].bitfield.baseindex)
3203 i.types[op].bitfield.disp8 = 0;
3204 i.types[op].bitfield.disp16 = 0;
3205 i.types[op].bitfield.disp32 = 0;
3206 i.types[op].bitfield.disp32s = 0;
3207 i.types[op].bitfield.disp64 = 0;
3211 else if (flag_code == CODE_64BIT)
3213 if (fits_in_signed_long (disp))
3215 i.types[op].bitfield.disp64 = 0;
3216 i.types[op].bitfield.disp32s = 1;
3218 if (fits_in_unsigned_long (disp))
3219 i.types[op].bitfield.disp32 = 1;
3221 if ((i.types[op].bitfield.disp32
3222 || i.types[op].bitfield.disp32s
3223 || i.types[op].bitfield.disp16)
3224 && fits_in_signed_byte (disp))
3225 i.types[op].bitfield.disp8 = 1;
3227 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3228 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3230 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3231 i.op[op].disps, 0, i.reloc[op]);
3232 i.types[op].bitfield.disp8 = 0;
3233 i.types[op].bitfield.disp16 = 0;
3234 i.types[op].bitfield.disp32 = 0;
3235 i.types[op].bitfield.disp32s = 0;
3236 i.types[op].bitfield.disp64 = 0;
3239 /* We only support 64bit displacement on constants. */
3240 i.types[op].bitfield.disp64 = 0;
3245 match_template (void)
3247 /* Points to template once we've found it. */
3249 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3250 unsigned int found_reverse_match;
3251 i386_opcode_modifier suffix_check;
3252 i386_operand_type operand_types [MAX_OPERANDS];
3253 int addr_prefix_disp;
3255 unsigned int found_cpu_match;
3256 unsigned int check_register;
3258 #if MAX_OPERANDS != 4
3259 # error "MAX_OPERANDS must be 4."
3262 found_reverse_match = 0;
3263 addr_prefix_disp = -1;
3265 memset (&suffix_check, 0, sizeof (suffix_check));
3266 if (i.suffix == BYTE_MNEM_SUFFIX)
3267 suffix_check.no_bsuf = 1;
3268 else if (i.suffix == WORD_MNEM_SUFFIX)
3269 suffix_check.no_wsuf = 1;
3270 else if (i.suffix == SHORT_MNEM_SUFFIX)
3271 suffix_check.no_ssuf = 1;
3272 else if (i.suffix == LONG_MNEM_SUFFIX)
3273 suffix_check.no_lsuf = 1;
3274 else if (i.suffix == QWORD_MNEM_SUFFIX)
3275 suffix_check.no_qsuf = 1;
3276 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3277 suffix_check.no_ldsuf = 1;
3279 for (t = current_templates->start; t < current_templates->end; t++)
3281 addr_prefix_disp = -1;
3283 /* Must have right number of operands. */
3284 if (i.operands != t->operands)
3287 /* Check processor support. */
3288 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3289 if (!found_cpu_match)
3292 /* Check old gcc support. */
3293 if (!old_gcc && t->opcode_modifier.oldgcc)
3296 /* Check AT&T mnemonic. */
3297 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3300 /* Check AT&T syntax Intel syntax. */
3301 if ((intel_syntax && t->opcode_modifier.attsyntax)
3302 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3305 /* Check the suffix, except for some instructions in intel mode. */
3306 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3307 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3308 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3309 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3310 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3311 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3312 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3315 if (!operand_size_match (t))
3318 for (j = 0; j < MAX_OPERANDS; j++)
3319 operand_types[j] = t->operand_types[j];
3321 /* In general, don't allow 64-bit operands in 32-bit mode. */
3322 if (i.suffix == QWORD_MNEM_SUFFIX
3323 && flag_code != CODE_64BIT
3325 ? (!t->opcode_modifier.ignoresize
3326 && !intel_float_operand (t->name))
3327 : intel_float_operand (t->name) != 2)
3328 && ((!operand_types[0].bitfield.regmmx
3329 && !operand_types[0].bitfield.regxmm)
3330 || (!operand_types[t->operands > 1].bitfield.regmmx
3331 && !!operand_types[t->operands > 1].bitfield.regxmm))
3332 && (t->base_opcode != 0x0fc7
3333 || t->extension_opcode != 1 /* cmpxchg8b */))
3336 /* Do not verify operands when there are none. */
3340 /* We've found a match; break out of loop. */
3344 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3345 into Disp32/Disp16/Disp32 operand. */
3346 if (i.prefix[ADDR_PREFIX] != 0)
3348 /* There should be only one Disp operand. */
3352 for (j = 0; j < MAX_OPERANDS; j++)
3354 if (operand_types[j].bitfield.disp16)
3356 addr_prefix_disp = j;
3357 operand_types[j].bitfield.disp32 = 1;
3358 operand_types[j].bitfield.disp16 = 0;
3364 for (j = 0; j < MAX_OPERANDS; j++)
3366 if (operand_types[j].bitfield.disp32)
3368 addr_prefix_disp = j;
3369 operand_types[j].bitfield.disp32 = 0;
3370 operand_types[j].bitfield.disp16 = 1;
3376 for (j = 0; j < MAX_OPERANDS; j++)
3378 if (operand_types[j].bitfield.disp64)
3380 addr_prefix_disp = j;
3381 operand_types[j].bitfield.disp64 = 0;
3382 operand_types[j].bitfield.disp32 = 1;
3390 /* We check register size only if size of operands can be
3391 encoded the canonical way. */
3392 check_register = t->opcode_modifier.w;
3393 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3394 switch (t->operands)
3397 if (!operand_type_match (overlap0, i.types[0]))
3401 /* xchg %eax, %eax is a special case. It is an aliase for nop
3402 only in 32bit mode and we can use opcode 0x90. In 64bit
3403 mode, we can't use 0x90 for xchg %eax, %eax since it should
3404 zero-extend %eax to %rax. */
3405 if (flag_code == CODE_64BIT
3406 && t->base_opcode == 0x90
3407 && operand_type_equal (&i.types [0], &acc32)
3408 && operand_type_equal (&i.types [1], &acc32))
3412 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3413 if (!operand_type_match (overlap0, i.types[0])
3414 || !operand_type_match (overlap1, i.types[1])
3416 && !operand_type_register_match (overlap0, i.types[0],
3418 overlap1, i.types[1],
3421 /* Check if other direction is valid ... */
3422 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3425 /* Try reversing direction of operands. */
3426 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3427 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3428 if (!operand_type_match (overlap0, i.types[0])
3429 || !operand_type_match (overlap1, i.types[1])
3431 && !operand_type_register_match (overlap0,
3438 /* Does not match either direction. */
3441 /* found_reverse_match holds which of D or FloatDR
3443 if (t->opcode_modifier.d)
3444 found_reverse_match = Opcode_D;
3445 else if (t->opcode_modifier.floatd)
3446 found_reverse_match = Opcode_FloatD;
3448 found_reverse_match = 0;
3449 if (t->opcode_modifier.floatr)
3450 found_reverse_match |= Opcode_FloatR;
3454 /* Found a forward 2 operand match here. */
3455 switch (t->operands)
3458 overlap3 = operand_type_and (i.types[3],
3461 overlap2 = operand_type_and (i.types[2],
3466 switch (t->operands)
3469 if (!operand_type_match (overlap3, i.types[3])
3471 && !operand_type_register_match (overlap2,
3479 /* Here we make use of the fact that there are no
3480 reverse match 3 operand instructions, and all 3
3481 operand instructions only need to be checked for
3482 register consistency between operands 2 and 3. */
3483 if (!operand_type_match (overlap2, i.types[2])
3485 && !operand_type_register_match (overlap1,
3495 /* Found either forward/reverse 2, 3 or 4 operand match here:
3496 slip through to break. */
3498 if (!found_cpu_match)
3500 found_reverse_match = 0;
3503 /* We've found a match; break out of loop. */
3507 if (t == current_templates->end)
3509 /* We found no match. */
3510 as_bad (_("suffix or operands invalid for `%s'"),
3511 current_templates->start->name);
3515 if (!quiet_warnings)
3518 && (i.types[0].bitfield.jumpabsolute
3519 != operand_types[0].bitfield.jumpabsolute))
3521 as_warn (_("indirect %s without `*'"), t->name);
3524 if (t->opcode_modifier.isprefix
3525 && t->opcode_modifier.ignoresize)
3527 /* Warn them that a data or address size prefix doesn't
3528 affect assembly of the next line of code. */
3529 as_warn (_("stand-alone `%s' prefix"), t->name);
3533 /* Copy the template we found. */
3536 if (addr_prefix_disp != -1)
3537 i.tm.operand_types[addr_prefix_disp]
3538 = operand_types[addr_prefix_disp];
3540 if (found_reverse_match)
3542 /* If we found a reverse match we must alter the opcode
3543 direction bit. found_reverse_match holds bits to change
3544 (different for int & float insns). */
3546 i.tm.base_opcode ^= found_reverse_match;
3548 i.tm.operand_types[0] = operand_types[1];
3549 i.tm.operand_types[1] = operand_types[0];
3558 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3559 if (i.tm.operand_types[mem_op].bitfield.esseg)
3561 if (i.seg[0] != NULL && i.seg[0] != &es)
3563 as_bad (_("`%s' operand %d must use `%%es' segment"),
3568 /* There's only ever one segment override allowed per instruction.
3569 This instruction possibly has a legal segment override on the
3570 second operand, so copy the segment to where non-string
3571 instructions store it, allowing common code. */
3572 i.seg[0] = i.seg[1];
3574 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3576 if (i.seg[1] != NULL && i.seg[1] != &es)
3578 as_bad (_("`%s' operand %d must use `%%es' segment"),
3588 process_suffix (void)
3590 /* If matched instruction specifies an explicit instruction mnemonic
3592 if (i.tm.opcode_modifier.size16)
3593 i.suffix = WORD_MNEM_SUFFIX;
3594 else if (i.tm.opcode_modifier.size32)
3595 i.suffix = LONG_MNEM_SUFFIX;
3596 else if (i.tm.opcode_modifier.size64)
3597 i.suffix = QWORD_MNEM_SUFFIX;
3598 else if (i.reg_operands)
3600 /* If there's no instruction mnemonic suffix we try to invent one
3601 based on register operands. */
3604 /* We take i.suffix from the last register operand specified,
3605 Destination register type is more significant than source
3606 register type. crc32 in SSE4.2 prefers source register
3608 if (i.tm.base_opcode == 0xf20f38f1)
3610 if (i.types[0].bitfield.reg16)
3611 i.suffix = WORD_MNEM_SUFFIX;
3612 else if (i.types[0].bitfield.reg32)
3613 i.suffix = LONG_MNEM_SUFFIX;
3614 else if (i.types[0].bitfield.reg64)
3615 i.suffix = QWORD_MNEM_SUFFIX;
3617 else if (i.tm.base_opcode == 0xf20f38f0)
3619 if (i.types[0].bitfield.reg8)
3620 i.suffix = BYTE_MNEM_SUFFIX;
3627 if (i.tm.base_opcode == 0xf20f38f1
3628 || i.tm.base_opcode == 0xf20f38f0)
3630 /* We have to know the operand size for crc32. */
3631 as_bad (_("ambiguous memory operand size for `%s`"),
3636 for (op = i.operands; --op >= 0;)
3637 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3639 if (i.types[op].bitfield.reg8)
3641 i.suffix = BYTE_MNEM_SUFFIX;
3644 else if (i.types[op].bitfield.reg16)
3646 i.suffix = WORD_MNEM_SUFFIX;
3649 else if (i.types[op].bitfield.reg32)
3651 i.suffix = LONG_MNEM_SUFFIX;
3654 else if (i.types[op].bitfield.reg64)
3656 i.suffix = QWORD_MNEM_SUFFIX;
3662 else if (i.suffix == BYTE_MNEM_SUFFIX)
3664 if (!check_byte_reg ())
3667 else if (i.suffix == LONG_MNEM_SUFFIX)
3669 if (!check_long_reg ())
3672 else if (i.suffix == QWORD_MNEM_SUFFIX)
3675 && i.tm.opcode_modifier.ignoresize
3676 && i.tm.opcode_modifier.no_qsuf)
3678 else if (!check_qword_reg ())
3681 else if (i.suffix == WORD_MNEM_SUFFIX)
3683 if (!check_word_reg ())
3686 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3688 /* Skip if the instruction has x suffix. match_template
3689 should check if it is a valid suffix. */
3691 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3692 /* Do nothing if the instruction is going to ignore the prefix. */
3697 else if (i.tm.opcode_modifier.defaultsize
3699 /* exclude fldenv/frstor/fsave/fstenv */
3700 && i.tm.opcode_modifier.no_ssuf)
3702 i.suffix = stackop_size;
3704 else if (intel_syntax
3706 && (i.tm.operand_types[0].bitfield.jumpabsolute
3707 || i.tm.opcode_modifier.jumpbyte
3708 || i.tm.opcode_modifier.jumpintersegment
3709 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3710 && i.tm.extension_opcode <= 3)))
3715 if (!i.tm.opcode_modifier.no_qsuf)
3717 i.suffix = QWORD_MNEM_SUFFIX;
3721 if (!i.tm.opcode_modifier.no_lsuf)
3722 i.suffix = LONG_MNEM_SUFFIX;
3725 if (!i.tm.opcode_modifier.no_wsuf)
3726 i.suffix = WORD_MNEM_SUFFIX;
3735 if (i.tm.opcode_modifier.w)
3737 as_bad (_("no instruction mnemonic suffix given and "
3738 "no register operands; can't size instruction"));
3744 unsigned int suffixes;
3746 suffixes = !i.tm.opcode_modifier.no_bsuf;
3747 if (!i.tm.opcode_modifier.no_wsuf)
3749 if (!i.tm.opcode_modifier.no_lsuf)
3751 if (!i.tm.opcode_modifier.no_ldsuf)
3753 if (!i.tm.opcode_modifier.no_ssuf)
3755 if (!i.tm.opcode_modifier.no_qsuf)
3758 /* There are more than suffix matches. */
3759 if (i.tm.opcode_modifier.w
3760 || ((suffixes & (suffixes - 1))
3761 && !i.tm.opcode_modifier.defaultsize
3762 && !i.tm.opcode_modifier.ignoresize))
3764 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3770 /* Change the opcode based on the operand size given by i.suffix;
3771 We don't need to change things for byte insns. */
3774 && i.suffix != BYTE_MNEM_SUFFIX
3775 && i.suffix != XMMWORD_MNEM_SUFFIX)
3777 /* It's not a byte, select word/dword operation. */
3778 if (i.tm.opcode_modifier.w)
3780 if (i.tm.opcode_modifier.shortform)
3781 i.tm.base_opcode |= 8;
3783 i.tm.base_opcode |= 1;
3786 /* Now select between word & dword operations via the operand
3787 size prefix, except for instructions that will ignore this
3789 if (i.tm.opcode_modifier.addrprefixop0)
3791 /* The address size override prefix changes the size of the
3793 if ((flag_code == CODE_32BIT
3794 && i.op->regs[0].reg_type.bitfield.reg16)
3795 || (flag_code != CODE_32BIT
3796 && i.op->regs[0].reg_type.bitfield.reg32))
3797 if (!add_prefix (ADDR_PREFIX_OPCODE))
3800 else if (i.suffix != QWORD_MNEM_SUFFIX
3801 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
3802 && !i.tm.opcode_modifier.ignoresize
3803 && !i.tm.opcode_modifier.floatmf
3804 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3805 || (flag_code == CODE_64BIT
3806 && i.tm.opcode_modifier.jumpbyte)))
3808 unsigned int prefix = DATA_PREFIX_OPCODE;
3810 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
3811 prefix = ADDR_PREFIX_OPCODE;
3813 if (!add_prefix (prefix))
3817 /* Set mode64 for an operand. */
3818 if (i.suffix == QWORD_MNEM_SUFFIX
3819 && flag_code == CODE_64BIT
3820 && !i.tm.opcode_modifier.norex64)
3822 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3823 need rex64. cmpxchg8b is also a special case. */
3824 if (! (i.operands == 2
3825 && i.tm.base_opcode == 0x90
3826 && i.tm.extension_opcode == None
3827 && operand_type_equal (&i.types [0], &acc64)
3828 && operand_type_equal (&i.types [1], &acc64))
3829 && ! (i.operands == 1
3830 && i.tm.base_opcode == 0xfc7
3831 && i.tm.extension_opcode == 1
3832 && !operand_type_check (i.types [0], reg)
3833 && operand_type_check (i.types [0], anymem)))
3837 /* Size floating point instruction. */
3838 if (i.suffix == LONG_MNEM_SUFFIX)
3839 if (i.tm.opcode_modifier.floatmf)
3840 i.tm.base_opcode ^= 4;
3847 check_byte_reg (void)
3851 for (op = i.operands; --op >= 0;)
3853 /* If this is an eight bit register, it's OK. If it's the 16 or
3854 32 bit version of an eight bit register, we will just use the
3855 low portion, and that's OK too. */
3856 if (i.types[op].bitfield.reg8)
3859 /* Don't generate this warning if not needed. */
3860 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
3863 /* crc32 doesn't generate this warning. */
3864 if (i.tm.base_opcode == 0xf20f38f0)
3867 if ((i.types[op].bitfield.reg16
3868 || i.types[op].bitfield.reg32
3869 || i.types[op].bitfield.reg64)
3870 && i.op[op].regs->reg_num < 4)
3872 /* Prohibit these changes in the 64bit mode, since the
3873 lowering is more complicated. */
3874 if (flag_code == CODE_64BIT
3875 && !i.tm.operand_types[op].bitfield.inoutportreg)
3877 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3878 register_prefix, i.op[op].regs->reg_name,
3882 #if REGISTER_WARNINGS
3884 && !i.tm.operand_types[op].bitfield.inoutportreg)
3885 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3887 (i.op[op].regs + (i.types[op].bitfield.reg16
3888 ? REGNAM_AL - REGNAM_AX
3889 : REGNAM_AL - REGNAM_EAX))->reg_name,
3891 i.op[op].regs->reg_name,
3896 /* Any other register is bad. */
3897 if (i.types[op].bitfield.reg16
3898 || i.types[op].bitfield.reg32
3899 || i.types[op].bitfield.reg64
3900 || i.types[op].bitfield.regmmx
3901 || i.types[op].bitfield.regxmm
3902 || i.types[op].bitfield.sreg2
3903 || i.types[op].bitfield.sreg3
3904 || i.types[op].bitfield.control
3905 || i.types[op].bitfield.debug
3906 || i.types[op].bitfield.test
3907 || i.types[op].bitfield.floatreg
3908 || i.types[op].bitfield.floatacc)
3910 as_bad (_("`%s%s' not allowed with `%s%c'"),
3912 i.op[op].regs->reg_name,
3922 check_long_reg (void)
3926 for (op = i.operands; --op >= 0;)
3927 /* Reject eight bit registers, except where the template requires
3928 them. (eg. movzb) */
3929 if (i.types[op].bitfield.reg8
3930 && (i.tm.operand_types[op].bitfield.reg16
3931 || i.tm.operand_types[op].bitfield.reg32
3932 || i.tm.operand_types[op].bitfield.acc))
3934 as_bad (_("`%s%s' not allowed with `%s%c'"),
3936 i.op[op].regs->reg_name,
3941 /* Warn if the e prefix on a general reg is missing. */
3942 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3943 && i.types[op].bitfield.reg16
3944 && (i.tm.operand_types[op].bitfield.reg32
3945 || i.tm.operand_types[op].bitfield.acc))
3947 /* Prohibit these changes in the 64bit mode, since the
3948 lowering is more complicated. */
3949 if (flag_code == CODE_64BIT)
3951 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3952 register_prefix, i.op[op].regs->reg_name,
3956 #if REGISTER_WARNINGS
3958 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3960 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3962 i.op[op].regs->reg_name,
3966 /* Warn if the r prefix on a general reg is missing. */
3967 else if (i.types[op].bitfield.reg64
3968 && (i.tm.operand_types[op].bitfield.reg32
3969 || i.tm.operand_types[op].bitfield.acc))
3972 && i.tm.opcode_modifier.toqword
3973 && !i.types[0].bitfield.regxmm)
3975 /* Convert to QWORD. We want REX byte. */
3976 i.suffix = QWORD_MNEM_SUFFIX;
3980 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3981 register_prefix, i.op[op].regs->reg_name,
3990 check_qword_reg (void)
3994 for (op = i.operands; --op >= 0; )
3995 /* Reject eight bit registers, except where the template requires
3996 them. (eg. movzb) */
3997 if (i.types[op].bitfield.reg8
3998 && (i.tm.operand_types[op].bitfield.reg16
3999 || i.tm.operand_types[op].bitfield.reg32
4000 || i.tm.operand_types[op].bitfield.acc))
4002 as_bad (_("`%s%s' not allowed with `%s%c'"),
4004 i.op[op].regs->reg_name,
4009 /* Warn if the e prefix on a general reg is missing. */
4010 else if ((i.types[op].bitfield.reg16
4011 || i.types[op].bitfield.reg32)
4012 && (i.tm.operand_types[op].bitfield.reg32
4013 || i.tm.operand_types[op].bitfield.acc))
4015 /* Prohibit these changes in the 64bit mode, since the
4016 lowering is more complicated. */
4018 && i.tm.opcode_modifier.todword
4019 && !i.types[0].bitfield.regxmm)
4021 /* Convert to DWORD. We don't want REX byte. */
4022 i.suffix = LONG_MNEM_SUFFIX;
4026 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4027 register_prefix, i.op[op].regs->reg_name,
4036 check_word_reg (void)
4039 for (op = i.operands; --op >= 0;)
4040 /* Reject eight bit registers, except where the template requires
4041 them. (eg. movzb) */
4042 if (i.types[op].bitfield.reg8
4043 && (i.tm.operand_types[op].bitfield.reg16
4044 || i.tm.operand_types[op].bitfield.reg32
4045 || i.tm.operand_types[op].bitfield.acc))
4047 as_bad (_("`%s%s' not allowed with `%s%c'"),
4049 i.op[op].regs->reg_name,
4054 /* Warn if the e prefix on a general reg is present. */
4055 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4056 && i.types[op].bitfield.reg32
4057 && (i.tm.operand_types[op].bitfield.reg16
4058 || i.tm.operand_types[op].bitfield.acc))
4060 /* Prohibit these changes in the 64bit mode, since the
4061 lowering is more complicated. */
4062 if (flag_code == CODE_64BIT)
4064 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4065 register_prefix, i.op[op].regs->reg_name,
4070 #if REGISTER_WARNINGS
4071 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4073 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4075 i.op[op].regs->reg_name,
4083 update_imm (unsigned int j)
4085 i386_operand_type overlap;
4087 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4088 if ((overlap.bitfield.imm8
4089 || overlap.bitfield.imm8s
4090 || overlap.bitfield.imm16
4091 || overlap.bitfield.imm32
4092 || overlap.bitfield.imm32s
4093 || overlap.bitfield.imm64)
4094 && !operand_type_equal (&overlap, &imm8)
4095 && !operand_type_equal (&overlap, &imm8s)
4096 && !operand_type_equal (&overlap, &imm16)
4097 && !operand_type_equal (&overlap, &imm32)
4098 && !operand_type_equal (&overlap, &imm32s)
4099 && !operand_type_equal (&overlap, &imm64))
4103 i386_operand_type temp;
4105 operand_type_set (&temp, 0);
4106 if (i.suffix == BYTE_MNEM_SUFFIX)
4108 temp.bitfield.imm8 = overlap.bitfield.imm8;
4109 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4111 else if (i.suffix == WORD_MNEM_SUFFIX)
4112 temp.bitfield.imm16 = overlap.bitfield.imm16;
4113 else if (i.suffix == QWORD_MNEM_SUFFIX)
4115 temp.bitfield.imm64 = overlap.bitfield.imm64;
4116 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4119 temp.bitfield.imm32 = overlap.bitfield.imm32;
4122 else if (operand_type_equal (&overlap, &imm16_32_32s)
4123 || operand_type_equal (&overlap, &imm16_32)
4124 || operand_type_equal (&overlap, &imm16_32s))
4126 operand_type_set (&overlap, 0);
4127 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4128 overlap.bitfield.imm16 = 1;
4130 overlap.bitfield.imm32s = 1;
4132 if (!operand_type_equal (&overlap, &imm8)
4133 && !operand_type_equal (&overlap, &imm8s)
4134 && !operand_type_equal (&overlap, &imm16)
4135 && !operand_type_equal (&overlap, &imm32)
4136 && !operand_type_equal (&overlap, &imm32s)
4137 && !operand_type_equal (&overlap, &imm64))
4139 as_bad (_("no instruction mnemonic suffix given; "
4140 "can't determine immediate size"));
4144 i.types[j] = overlap;
4154 for (j = 0; j < 2; j++)
4155 if (update_imm (j) == 0)
4158 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4159 assert (operand_type_check (i.types[2], imm) == 0);
4167 i.drex.modrm_reg = 0;
4168 i.drex.modrm_regmem = 0;
4170 /* SSE5 4 operand instructions must have the destination the same as
4171 one of the inputs. Figure out the destination register and cache
4172 it away in the drex field, and remember which fields to use for
4174 if (i.tm.opcode_modifier.drex
4175 && i.tm.opcode_modifier.drexv
4178 i.tm.extension_opcode = None;
4180 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4181 if (i.types[0].bitfield.regxmm != 0
4182 && i.types[1].bitfield.regxmm != 0
4183 && i.types[2].bitfield.regxmm != 0
4184 && i.types[3].bitfield.regxmm != 0
4185 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4186 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4188 /* Clear the arguments that are stored in drex. */
4189 operand_type_set (&i.types[0], 0);
4190 operand_type_set (&i.types[3], 0);
4191 i.reg_operands -= 2;
4193 /* There are two different ways to encode a 4 operand
4194 instruction with all registers that uses OC1 set to
4195 0 or 1. Favor setting OC1 to 0 since this mimics the
4196 actions of other SSE5 assemblers. Use modrm encoding 2
4197 for register/register. Include the high order bit that
4198 is normally stored in the REX byte in the register
4200 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4201 i.drex.modrm_reg = 2;
4202 i.drex.modrm_regmem = 1;
4203 i.drex.reg = (i.op[3].regs->reg_num
4204 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4207 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4208 else if (i.types[0].bitfield.regxmm != 0
4209 && i.types[1].bitfield.regxmm != 0
4210 && (i.types[2].bitfield.regxmm
4211 || operand_type_check (i.types[2], anymem))
4212 && i.types[3].bitfield.regxmm != 0
4213 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4214 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4216 /* clear the arguments that are stored in drex */
4217 operand_type_set (&i.types[0], 0);
4218 operand_type_set (&i.types[3], 0);
4219 i.reg_operands -= 2;
4221 /* Specify the modrm encoding for memory addressing. Include
4222 the high order bit that is normally stored in the REX byte
4223 in the register field. */
4224 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4225 i.drex.modrm_reg = 1;
4226 i.drex.modrm_regmem = 2;
4227 i.drex.reg = (i.op[3].regs->reg_num
4228 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4231 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4232 else if (i.types[0].bitfield.regxmm != 0
4233 && operand_type_check (i.types[1], anymem) != 0
4234 && i.types[2].bitfield.regxmm != 0
4235 && i.types[3].bitfield.regxmm != 0
4236 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4237 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4239 /* Clear the arguments that are stored in drex. */
4240 operand_type_set (&i.types[0], 0);
4241 operand_type_set (&i.types[3], 0);
4242 i.reg_operands -= 2;
4244 /* Specify the modrm encoding for memory addressing. Include
4245 the high order bit that is normally stored in the REX byte
4246 in the register field. */
4247 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4248 i.drex.modrm_reg = 2;
4249 i.drex.modrm_regmem = 1;
4250 i.drex.reg = (i.op[3].regs->reg_num
4251 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4254 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4255 else if (i.types[0].bitfield.regxmm != 0
4256 && i.types[1].bitfield.regxmm != 0
4257 && i.types[2].bitfield.regxmm != 0
4258 && i.types[3].bitfield.regxmm != 0
4259 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4260 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4262 /* clear the arguments that are stored in drex */
4263 operand_type_set (&i.types[2], 0);
4264 operand_type_set (&i.types[3], 0);
4265 i.reg_operands -= 2;
4267 /* There are two different ways to encode a 4 operand
4268 instruction with all registers that uses OC1 set to
4269 0 or 1. Favor setting OC1 to 0 since this mimics the
4270 actions of other SSE5 assemblers. Use modrm encoding
4271 2 for register/register. Include the high order bit that
4272 is normally stored in the REX byte in the register
4274 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4275 i.drex.modrm_reg = 1;
4276 i.drex.modrm_regmem = 0;
4278 /* Remember the register, including the upper bits */
4279 i.drex.reg = (i.op[3].regs->reg_num
4280 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4283 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4284 else if (i.types[0].bitfield.regxmm != 0
4285 && (i.types[1].bitfield.regxmm
4286 || operand_type_check (i.types[1], anymem))
4287 && i.types[2].bitfield.regxmm != 0
4288 && i.types[3].bitfield.regxmm != 0
4289 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4290 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4292 /* Clear the arguments that are stored in drex. */
4293 operand_type_set (&i.types[2], 0);
4294 operand_type_set (&i.types[3], 0);
4295 i.reg_operands -= 2;
4297 /* Specify the modrm encoding and remember the register
4298 including the bits normally stored in the REX byte. */
4299 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4300 i.drex.modrm_reg = 0;
4301 i.drex.modrm_regmem = 1;
4302 i.drex.reg = (i.op[3].regs->reg_num
4303 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4306 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4307 else if (operand_type_check (i.types[0], anymem) != 0
4308 && i.types[1].bitfield.regxmm != 0
4309 && i.types[2].bitfield.regxmm != 0
4310 && i.types[3].bitfield.regxmm != 0
4311 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4312 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4314 /* clear the arguments that are stored in drex */
4315 operand_type_set (&i.types[2], 0);
4316 operand_type_set (&i.types[3], 0);
4317 i.reg_operands -= 2;
4319 /* Specify the modrm encoding and remember the register
4320 including the bits normally stored in the REX byte. */
4321 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4322 i.drex.modrm_reg = 1;
4323 i.drex.modrm_regmem = 0;
4324 i.drex.reg = (i.op[3].regs->reg_num
4325 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4329 as_bad (_("Incorrect operands for the '%s' instruction"),
4333 /* SSE5 instructions with the DREX byte where the only memory operand
4334 is in the 2nd argument, and the first and last xmm register must
4335 match, and is encoded in the DREX byte. */
4336 else if (i.tm.opcode_modifier.drex
4337 && !i.tm.opcode_modifier.drexv
4340 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4341 if (i.types[0].bitfield.regxmm != 0
4342 && (i.types[1].bitfield.regxmm
4343 || operand_type_check(i.types[1], anymem))
4344 && i.types[2].bitfield.regxmm != 0
4345 && i.types[3].bitfield.regxmm != 0
4346 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4347 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4349 /* clear the arguments that are stored in drex */
4350 operand_type_set (&i.types[0], 0);
4351 operand_type_set (&i.types[3], 0);
4352 i.reg_operands -= 2;
4354 /* Specify the modrm encoding and remember the register
4355 including the high bit normally stored in the REX
4357 i.drex.modrm_reg = 2;
4358 i.drex.modrm_regmem = 1;
4359 i.drex.reg = (i.op[3].regs->reg_num
4360 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4364 as_bad (_("Incorrect operands for the '%s' instruction"),
4368 /* SSE5 3 operand instructions that the result is a register, being
4369 either operand can be a memory operand, using OC0 to note which
4370 one is the memory. */
4371 else if (i.tm.opcode_modifier.drex
4372 && i.tm.opcode_modifier.drexv
4375 i.tm.extension_opcode = None;
4377 /* Case 1: 3 operand insn, src1 = register. */
4378 if (i.types[0].bitfield.regxmm != 0
4379 && i.types[1].bitfield.regxmm != 0
4380 && i.types[2].bitfield.regxmm != 0)
4382 /* Clear the arguments that are stored in drex. */
4383 operand_type_set (&i.types[2], 0);
4386 /* Specify the modrm encoding and remember the register
4387 including the high bit normally stored in the REX byte. */
4388 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4389 i.drex.modrm_reg = 1;
4390 i.drex.modrm_regmem = 0;
4391 i.drex.reg = (i.op[2].regs->reg_num
4392 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4395 /* Case 2: 3 operand insn, src1 = memory. */
4396 else if (operand_type_check (i.types[0], anymem) != 0
4397 && i.types[1].bitfield.regxmm != 0
4398 && i.types[2].bitfield.regxmm != 0)
4400 /* Clear the arguments that are stored in drex. */
4401 operand_type_set (&i.types[2], 0);
4404 /* Specify the modrm encoding and remember the register
4405 including the high bit normally stored in the REX
4407 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4408 i.drex.modrm_reg = 1;
4409 i.drex.modrm_regmem = 0;
4410 i.drex.reg = (i.op[2].regs->reg_num
4411 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4414 /* Case 3: 3 operand insn, src2 = memory. */
4415 else if (i.types[0].bitfield.regxmm != 0
4416 && operand_type_check (i.types[1], anymem) != 0
4417 && i.types[2].bitfield.regxmm != 0)
4419 /* Clear the arguments that are stored in drex. */
4420 operand_type_set (&i.types[2], 0);
4423 /* Specify the modrm encoding and remember the register
4424 including the high bit normally stored in the REX byte. */
4425 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4426 i.drex.modrm_reg = 0;
4427 i.drex.modrm_regmem = 1;
4428 i.drex.reg = (i.op[2].regs->reg_num
4429 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4433 as_bad (_("Incorrect operands for the '%s' instruction"),
4437 /* SSE5 4 operand instructions that are the comparison instructions
4438 where the first operand is the immediate value of the comparison
4440 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4442 /* Case 1: 4 operand insn, src1 = reg/memory. */
4443 if (operand_type_check (i.types[0], imm) != 0
4444 && (i.types[1].bitfield.regxmm
4445 || operand_type_check (i.types[1], anymem))
4446 && i.types[2].bitfield.regxmm != 0
4447 && i.types[3].bitfield.regxmm != 0)
4449 /* clear the arguments that are stored in drex */
4450 operand_type_set (&i.types[3], 0);
4453 /* Specify the modrm encoding and remember the register
4454 including the high bit normally stored in the REX byte. */
4455 i.drex.modrm_reg = 2;
4456 i.drex.modrm_regmem = 1;
4457 i.drex.reg = (i.op[3].regs->reg_num
4458 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4461 /* Case 2: 3 operand insn with ImmExt that places the
4462 opcode_extension as an immediate argument. This is used for
4463 all of the varients of comparison that supplies the appropriate
4464 value as part of the instruction. */
4465 else if ((i.types[0].bitfield.regxmm
4466 || operand_type_check (i.types[0], anymem))
4467 && i.types[1].bitfield.regxmm != 0
4468 && i.types[2].bitfield.regxmm != 0
4469 && operand_type_check (i.types[3], imm) != 0)
4471 /* clear the arguments that are stored in drex */
4472 operand_type_set (&i.types[2], 0);
4475 /* Specify the modrm encoding and remember the register
4476 including the high bit normally stored in the REX byte. */
4477 i.drex.modrm_reg = 1;
4478 i.drex.modrm_regmem = 0;
4479 i.drex.reg = (i.op[2].regs->reg_num
4480 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4484 as_bad (_("Incorrect operands for the '%s' instruction"),
4488 else if (i.tm.opcode_modifier.drex
4489 || i.tm.opcode_modifier.drexv
4490 || i.tm.opcode_modifier.drexc)
4491 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4495 process_operands (void)
4497 /* Default segment register this instruction will use for memory
4498 accesses. 0 means unknown. This is only for optimizing out
4499 unnecessary segment overrides. */
4500 const seg_entry *default_seg = 0;
4502 /* Handle all of the DREX munging that SSE5 needs. */
4503 if (i.tm.opcode_modifier.drex
4504 || i.tm.opcode_modifier.drexv
4505 || i.tm.opcode_modifier.drexc)
4508 if (i.tm.opcode_modifier.firstxmm0)
4512 /* The first operand is implicit and must be xmm0. */
4513 assert (i.reg_operands
4514 && operand_type_equal (&i.types[0], ®xmm));
4515 if (i.op[0].regs->reg_num != 0)
4518 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4519 i.tm.name, register_prefix);
4521 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4522 i.tm.name, register_prefix);
4526 for (j = 1; j < i.operands; j++)
4528 i.op[j - 1] = i.op[j];
4529 i.types[j - 1] = i.types[j];
4531 /* We need to adjust fields in i.tm since they are used by
4532 build_modrm_byte. */
4533 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4540 else if (i.tm.opcode_modifier.regkludge)
4542 /* The imul $imm, %reg instruction is converted into
4543 imul $imm, %reg, %reg, and the clr %reg instruction
4544 is converted into xor %reg, %reg. */
4546 unsigned int first_reg_op;
4548 if (operand_type_check (i.types[0], reg))
4552 /* Pretend we saw the extra register operand. */
4553 assert (i.reg_operands == 1
4554 && i.op[first_reg_op + 1].regs == 0);
4555 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4556 i.types[first_reg_op + 1] = i.types[first_reg_op];
4561 if (i.tm.opcode_modifier.shortform)
4563 if (i.types[0].bitfield.sreg2
4564 || i.types[0].bitfield.sreg3)
4566 if (i.tm.base_opcode == POP_SEG_SHORT
4567 && i.op[0].regs->reg_num == 1)
4569 as_bad (_("you can't `pop %%cs'"));
4572 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4573 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4578 /* The register or float register operand is in operand
4582 if (i.types[0].bitfield.floatreg
4583 || operand_type_check (i.types[0], reg))
4587 /* Register goes in low 3 bits of opcode. */
4588 i.tm.base_opcode |= i.op[op].regs->reg_num;
4589 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4591 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4593 /* Warn about some common errors, but press on regardless.
4594 The first case can be generated by gcc (<= 2.8.1). */
4595 if (i.operands == 2)
4597 /* Reversed arguments on faddp, fsubp, etc. */
4598 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4599 register_prefix, i.op[1].regs->reg_name,
4600 register_prefix, i.op[0].regs->reg_name);
4604 /* Extraneous `l' suffix on fp insn. */
4605 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4606 register_prefix, i.op[0].regs->reg_name);
4611 else if (i.tm.opcode_modifier.modrm)
4613 /* The opcode is completed (modulo i.tm.extension_opcode which
4614 must be put into the modrm byte). Now, we make the modrm and
4615 index base bytes based on all the info we've collected. */
4617 default_seg = build_modrm_byte ();
4619 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4623 else if (i.tm.opcode_modifier.isstring)
4625 /* For the string instructions that allow a segment override
4626 on one of their operands, the default segment is ds. */
4630 if (i.tm.base_opcode == 0x8d /* lea */
4633 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4635 /* If a segment was explicitly specified, and the specified segment
4636 is not the default, use an opcode prefix to select it. If we
4637 never figured out what the default segment is, then default_seg
4638 will be zero at this point, and the specified segment prefix will
4640 if ((i.seg[0]) && (i.seg[0] != default_seg))
4642 if (!add_prefix (i.seg[0]->seg_prefix))
4648 static const seg_entry *
4649 build_modrm_byte (void)
4651 const seg_entry *default_seg = 0;
4653 /* SSE5 4 operand instructions are encoded in such a way that one of
4654 the inputs must match the destination register. Process_drex hides
4655 the 3rd argument in the drex field, so that by the time we get
4656 here, it looks to GAS as if this is a 2 operand instruction. */
4657 if ((i.tm.opcode_modifier.drex
4658 || i.tm.opcode_modifier.drexv
4659 || i.tm.opcode_modifier.drexc)
4660 && i.reg_operands == 2)
4662 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4663 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4665 i.rm.reg = reg->reg_num;
4666 i.rm.regmem = regmem->reg_num;
4668 if ((reg->reg_flags & RegRex) != 0)
4670 if ((regmem->reg_flags & RegRex) != 0)
4674 /* i.reg_operands MUST be the number of real register operands;
4675 implicit registers do not count. */
4676 else if (i.reg_operands == 2)
4678 unsigned int source, dest;
4686 /* When there are 3 operands, one of them may be immediate,
4687 which may be the first or the last operand. Otherwise,
4688 the first operand must be shift count register (cl). */
4689 assert (i.imm_operands == 1
4690 || (i.imm_operands == 0
4691 && i.types[0].bitfield.shiftcount));
4692 if (operand_type_check (i.types[0], imm)
4693 || i.types[0].bitfield.shiftcount)
4699 /* When there are 4 operands, the first two must be 8bit
4700 immediate operands. The source operand will be the 3rd
4702 assert (i.imm_operands == 2
4703 && i.types[0].bitfield.imm8
4704 && i.types[1].bitfield.imm8);
4714 /* One of the register operands will be encoded in the i.tm.reg
4715 field, the other in the combined i.tm.mode and i.tm.regmem
4716 fields. If no form of this instruction supports a memory
4717 destination operand, then we assume the source operand may
4718 sometimes be a memory operand and so we need to store the
4719 destination in the i.rm.reg field. */
4720 if (!i.tm.operand_types[dest].bitfield.regmem
4721 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4723 i.rm.reg = i.op[dest].regs->reg_num;
4724 i.rm.regmem = i.op[source].regs->reg_num;
4725 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4727 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4732 i.rm.reg = i.op[source].regs->reg_num;
4733 i.rm.regmem = i.op[dest].regs->reg_num;
4734 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4736 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4739 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4741 if (!i.types[0].bitfield.control
4742 && !i.types[1].bitfield.control)
4744 i.rex &= ~(REX_R | REX_B);
4745 add_prefix (LOCK_PREFIX_OPCODE);
4749 { /* If it's not 2 reg operands... */
4752 unsigned int fake_zero_displacement = 0;
4755 /* This has been precalculated for SSE5 instructions
4756 that have a DREX field earlier in process_drex. */
4757 if (i.tm.opcode_modifier.drex
4758 || i.tm.opcode_modifier.drexv
4759 || i.tm.opcode_modifier.drexc)
4760 op = i.drex.modrm_regmem;
4763 for (op = 0; op < i.operands; op++)
4764 if (operand_type_check (i.types[op], anymem))
4766 assert (op < i.operands);
4771 if (i.base_reg == 0)
4774 if (!i.disp_operands)
4775 fake_zero_displacement = 1;
4776 if (i.index_reg == 0)
4778 /* Operand is just <disp> */
4779 if (flag_code == CODE_64BIT)
4781 /* 64bit mode overwrites the 32bit absolute
4782 addressing by RIP relative addressing and
4783 absolute addressing is encoded by one of the
4784 redundant SIB forms. */
4785 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4786 i.sib.base = NO_BASE_REGISTER;
4787 i.sib.index = NO_INDEX_REGISTER;
4788 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4789 ? disp32s : disp32);
4791 else if ((flag_code == CODE_16BIT)
4792 ^ (i.prefix[ADDR_PREFIX] != 0))
4794 i.rm.regmem = NO_BASE_REGISTER_16;
4795 i.types[op] = disp16;
4799 i.rm.regmem = NO_BASE_REGISTER;
4800 i.types[op] = disp32;
4803 else /* !i.base_reg && i.index_reg */
4805 if (i.index_reg->reg_num == RegEiz
4806 || i.index_reg->reg_num == RegRiz)
4807 i.sib.index = NO_INDEX_REGISTER;
4809 i.sib.index = i.index_reg->reg_num;
4810 i.sib.base = NO_BASE_REGISTER;
4811 i.sib.scale = i.log2_scale_factor;
4812 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4813 i.types[op].bitfield.disp8 = 0;
4814 i.types[op].bitfield.disp16 = 0;
4815 i.types[op].bitfield.disp64 = 0;
4816 if (flag_code != CODE_64BIT)
4818 /* Must be 32 bit */
4819 i.types[op].bitfield.disp32 = 1;
4820 i.types[op].bitfield.disp32s = 0;
4824 i.types[op].bitfield.disp32 = 0;
4825 i.types[op].bitfield.disp32s = 1;
4827 if ((i.index_reg->reg_flags & RegRex) != 0)
4831 /* RIP addressing for 64bit mode. */
4832 else if (i.base_reg->reg_num == RegRip ||
4833 i.base_reg->reg_num == RegEip)
4835 i.rm.regmem = NO_BASE_REGISTER;
4836 i.types[op].bitfield.disp8 = 0;
4837 i.types[op].bitfield.disp16 = 0;
4838 i.types[op].bitfield.disp32 = 0;
4839 i.types[op].bitfield.disp32s = 1;
4840 i.types[op].bitfield.disp64 = 0;
4841 i.flags[op] |= Operand_PCrel;
4842 if (! i.disp_operands)
4843 fake_zero_displacement = 1;
4845 else if (i.base_reg->reg_type.bitfield.reg16)
4847 switch (i.base_reg->reg_num)
4850 if (i.index_reg == 0)
4852 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4853 i.rm.regmem = i.index_reg->reg_num - 6;
4857 if (i.index_reg == 0)
4860 if (operand_type_check (i.types[op], disp) == 0)
4862 /* fake (%bp) into 0(%bp) */
4863 i.types[op].bitfield.disp8 = 1;
4864 fake_zero_displacement = 1;
4867 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4868 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4870 default: /* (%si) -> 4 or (%di) -> 5 */
4871 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4873 i.rm.mode = mode_from_disp_size (i.types[op]);
4875 else /* i.base_reg and 32/64 bit mode */
4877 if (flag_code == CODE_64BIT
4878 && operand_type_check (i.types[op], disp))
4880 i386_operand_type temp;
4881 operand_type_set (&temp, 0);
4882 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4884 if (i.prefix[ADDR_PREFIX] == 0)
4885 i.types[op].bitfield.disp32s = 1;
4887 i.types[op].bitfield.disp32 = 1;
4890 i.rm.regmem = i.base_reg->reg_num;
4891 if ((i.base_reg->reg_flags & RegRex) != 0)
4893 i.sib.base = i.base_reg->reg_num;
4894 /* x86-64 ignores REX prefix bit here to avoid decoder
4896 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4899 if (i.disp_operands == 0)
4901 fake_zero_displacement = 1;
4902 i.types[op].bitfield.disp8 = 1;
4905 else if (i.base_reg->reg_num == ESP_REG_NUM)
4909 i.sib.scale = i.log2_scale_factor;
4910 if (i.index_reg == 0)
4912 /* <disp>(%esp) becomes two byte modrm with no index
4913 register. We've already stored the code for esp
4914 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4915 Any base register besides %esp will not use the
4916 extra modrm byte. */
4917 i.sib.index = NO_INDEX_REGISTER;
4921 if (i.index_reg->reg_num == RegEiz
4922 || i.index_reg->reg_num == RegRiz)
4923 i.sib.index = NO_INDEX_REGISTER;
4925 i.sib.index = i.index_reg->reg_num;
4926 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4927 if ((i.index_reg->reg_flags & RegRex) != 0)
4932 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4933 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4936 i.rm.mode = mode_from_disp_size (i.types[op]);
4939 if (fake_zero_displacement)
4941 /* Fakes a zero displacement assuming that i.types[op]
4942 holds the correct displacement size. */
4945 assert (i.op[op].disps == 0);
4946 exp = &disp_expressions[i.disp_operands++];
4947 i.op[op].disps = exp;
4948 exp->X_op = O_constant;
4949 exp->X_add_number = 0;
4950 exp->X_add_symbol = (symbolS *) 0;
4951 exp->X_op_symbol = (symbolS *) 0;
4955 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4956 (if any) based on i.tm.extension_opcode. Again, we must be
4957 careful to make sure that segment/control/debug/test/MMX
4958 registers are coded into the i.rm.reg field. */
4963 /* This has been precalculated for SSE5 instructions
4964 that have a DREX field earlier in process_drex. */
4965 if (i.tm.opcode_modifier.drex
4966 || i.tm.opcode_modifier.drexv
4967 || i.tm.opcode_modifier.drexc)
4969 op = i.drex.modrm_reg;
4970 i.rm.reg = i.op[op].regs->reg_num;
4971 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4976 for (op = 0; op < i.operands; op++)
4977 if (i.types[op].bitfield.reg8
4978 || i.types[op].bitfield.reg16
4979 || i.types[op].bitfield.reg32
4980 || i.types[op].bitfield.reg64
4981 || i.types[op].bitfield.regmmx
4982 || i.types[op].bitfield.regxmm
4983 || i.types[op].bitfield.sreg2
4984 || i.types[op].bitfield.sreg3
4985 || i.types[op].bitfield.control
4986 || i.types[op].bitfield.debug
4987 || i.types[op].bitfield.test)
4990 assert (op < i.operands);
4992 /* If there is an extension opcode to put here, the
4993 register number must be put into the regmem field. */
4994 if (i.tm.extension_opcode != None)
4996 i.rm.regmem = i.op[op].regs->reg_num;
4997 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5002 i.rm.reg = i.op[op].regs->reg_num;
5003 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5008 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5009 must set it to 3 to indicate this is a register operand
5010 in the regmem field. */
5011 if (!i.mem_operands)
5015 /* Fill in i.rm.reg field with extension opcode (if any). */
5016 if (i.tm.extension_opcode != None
5017 && !(i.tm.opcode_modifier.drex
5018 || i.tm.opcode_modifier.drexv
5019 || i.tm.opcode_modifier.drexc))
5020 i.rm.reg = i.tm.extension_opcode;
5026 output_branch (void)
5031 relax_substateT subtype;
5036 if (flag_code == CODE_16BIT)
5040 if (i.prefix[DATA_PREFIX] != 0)
5046 /* Pentium4 branch hints. */
5047 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5048 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5053 if (i.prefix[REX_PREFIX] != 0)
5059 if (i.prefixes != 0 && !intel_syntax)
5060 as_warn (_("skipping prefixes on this instruction"));
5062 /* It's always a symbol; End frag & setup for relax.
5063 Make sure there is enough room in this frag for the largest
5064 instruction we may generate in md_convert_frag. This is 2
5065 bytes for the opcode and room for the prefix and largest
5067 frag_grow (prefix + 2 + 4);
5068 /* Prefix and 1 opcode byte go in fr_fix. */
5069 p = frag_more (prefix + 1);
5070 if (i.prefix[DATA_PREFIX] != 0)
5071 *p++ = DATA_PREFIX_OPCODE;
5072 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5073 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5074 *p++ = i.prefix[SEG_PREFIX];
5075 if (i.prefix[REX_PREFIX] != 0)
5076 *p++ = i.prefix[REX_PREFIX];
5077 *p = i.tm.base_opcode;
5079 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5080 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5081 else if (cpu_arch_flags.bitfield.cpui386)
5082 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5084 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5087 sym = i.op[0].disps->X_add_symbol;
5088 off = i.op[0].disps->X_add_number;
5090 if (i.op[0].disps->X_op != O_constant
5091 && i.op[0].disps->X_op != O_symbol)
5093 /* Handle complex expressions. */
5094 sym = make_expr_symbol (i.op[0].disps);
5098 /* 1 possible extra opcode + 4 byte displacement go in var part.
5099 Pass reloc in fr_var. */
5100 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5110 if (i.tm.opcode_modifier.jumpbyte)
5112 /* This is a loop or jecxz type instruction. */
5114 if (i.prefix[ADDR_PREFIX] != 0)
5116 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5119 /* Pentium4 branch hints. */
5120 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5121 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5123 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5132 if (flag_code == CODE_16BIT)
5135 if (i.prefix[DATA_PREFIX] != 0)
5137 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5147 if (i.prefix[REX_PREFIX] != 0)
5149 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5153 if (i.prefixes != 0 && !intel_syntax)
5154 as_warn (_("skipping prefixes on this instruction"));
5156 p = frag_more (1 + size);
5157 *p++ = i.tm.base_opcode;
5159 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5160 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5162 /* All jumps handled here are signed, but don't use a signed limit
5163 check for 32 and 16 bit jumps as we want to allow wrap around at
5164 4G and 64k respectively. */
5166 fixP->fx_signed = 1;
5170 output_interseg_jump (void)
5178 if (flag_code == CODE_16BIT)
5182 if (i.prefix[DATA_PREFIX] != 0)
5188 if (i.prefix[REX_PREFIX] != 0)
5198 if (i.prefixes != 0 && !intel_syntax)
5199 as_warn (_("skipping prefixes on this instruction"));
5201 /* 1 opcode; 2 segment; offset */
5202 p = frag_more (prefix + 1 + 2 + size);
5204 if (i.prefix[DATA_PREFIX] != 0)
5205 *p++ = DATA_PREFIX_OPCODE;
5207 if (i.prefix[REX_PREFIX] != 0)
5208 *p++ = i.prefix[REX_PREFIX];
5210 *p++ = i.tm.base_opcode;
5211 if (i.op[1].imms->X_op == O_constant)
5213 offsetT n = i.op[1].imms->X_add_number;
5216 && !fits_in_unsigned_word (n)
5217 && !fits_in_signed_word (n))
5219 as_bad (_("16-bit jump out of range"));
5222 md_number_to_chars (p, n, size);
5225 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5226 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5227 if (i.op[0].imms->X_op != O_constant)
5228 as_bad (_("can't handle non absolute segment in `%s'"),
5230 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5236 fragS *insn_start_frag;
5237 offsetT insn_start_off;
5239 /* Tie dwarf2 debug info to the address at the start of the insn.
5240 We can't do this after the insn has been output as the current
5241 frag may have been closed off. eg. by frag_var. */
5242 dwarf2_emit_insn (0);
5244 insn_start_frag = frag_now;
5245 insn_start_off = frag_now_fix ();
5248 if (i.tm.opcode_modifier.jump)
5250 else if (i.tm.opcode_modifier.jumpbyte
5251 || i.tm.opcode_modifier.jumpdword)
5253 else if (i.tm.opcode_modifier.jumpintersegment)
5254 output_interseg_jump ();
5257 /* Output normal instructions here. */
5261 unsigned int prefix;
5263 switch (i.tm.opcode_length)
5266 if (i.tm.base_opcode & 0xff000000)
5268 prefix = (i.tm.base_opcode >> 24) & 0xff;
5273 if ((i.tm.base_opcode & 0xff0000) != 0)
5275 prefix = (i.tm.base_opcode >> 16) & 0xff;
5276 if (i.tm.cpu_flags.bitfield.cpupadlock)
5279 if (prefix != REPE_PREFIX_OPCODE
5280 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5281 add_prefix (prefix);
5284 add_prefix (prefix);
5293 /* The prefix bytes. */
5294 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5296 FRAG_APPEND_1_CHAR (*q);
5298 /* Now the opcode; be careful about word order here! */
5299 if (i.tm.opcode_length == 1)
5301 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5305 switch (i.tm.opcode_length)
5309 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5319 /* Put out high byte first: can't use md_number_to_chars! */
5320 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5321 *p = i.tm.base_opcode & 0xff;
5323 /* On SSE5, encode the OC1 bit in the DREX field if this
5324 encoding has multiple formats. */
5325 if (i.tm.opcode_modifier.drex
5326 && i.tm.opcode_modifier.drexv
5327 && DREX_OC1 (i.tm.extension_opcode))
5328 *p |= DREX_OC1_MASK;
5331 /* Now the modrm byte and sib byte (if present). */
5332 if (i.tm.opcode_modifier.modrm)
5334 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5337 /* If i.rm.regmem == ESP (4)
5338 && i.rm.mode != (Register mode)
5340 ==> need second modrm byte. */
5341 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5343 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5344 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5346 | i.sib.scale << 6));
5349 /* Write the DREX byte if needed. */
5350 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5353 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5355 /* Encode the OC0 bit if this encoding has multiple
5357 if ((i.tm.opcode_modifier.drex
5358 || i.tm.opcode_modifier.drexv)
5359 && DREX_OC0 (i.tm.extension_opcode))
5360 *p |= DREX_OC0_MASK;
5363 if (i.disp_operands)
5364 output_disp (insn_start_frag, insn_start_off);
5367 output_imm (insn_start_frag, insn_start_off);
5373 pi ("" /*line*/, &i);
5375 #endif /* DEBUG386 */
5378 /* Return the size of the displacement operand N. */
5381 disp_size (unsigned int n)
5384 if (i.types[n].bitfield.disp64)
5386 else if (i.types[n].bitfield.disp8)
5388 else if (i.types[n].bitfield.disp16)
5393 /* Return the size of the immediate operand N. */
5396 imm_size (unsigned int n)
5399 if (i.types[n].bitfield.imm64)
5401 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5403 else if (i.types[n].bitfield.imm16)
5409 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5414 for (n = 0; n < i.operands; n++)
5416 if (operand_type_check (i.types[n], disp))
5418 if (i.op[n].disps->X_op == O_constant)
5420 int size = disp_size (n);
5423 val = offset_in_range (i.op[n].disps->X_add_number,
5425 p = frag_more (size);
5426 md_number_to_chars (p, val, size);
5430 enum bfd_reloc_code_real reloc_type;
5431 int size = disp_size (n);
5432 int sign = i.types[n].bitfield.disp32s;
5433 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5435 /* We can't have 8 bit displacement here. */
5436 assert (!i.types[n].bitfield.disp8);
5438 /* The PC relative address is computed relative
5439 to the instruction boundary, so in case immediate
5440 fields follows, we need to adjust the value. */
5441 if (pcrel && i.imm_operands)
5446 for (n1 = 0; n1 < i.operands; n1++)
5447 if (operand_type_check (i.types[n1], imm))
5449 /* Only one immediate is allowed for PC
5450 relative address. */
5453 i.op[n].disps->X_add_number -= sz;
5455 /* We should find the immediate. */
5459 p = frag_more (size);
5460 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5462 && GOT_symbol == i.op[n].disps->X_add_symbol
5463 && (((reloc_type == BFD_RELOC_32
5464 || reloc_type == BFD_RELOC_X86_64_32S
5465 || (reloc_type == BFD_RELOC_64
5467 && (i.op[n].disps->X_op == O_symbol
5468 || (i.op[n].disps->X_op == O_add
5469 && ((symbol_get_value_expression
5470 (i.op[n].disps->X_op_symbol)->X_op)
5472 || reloc_type == BFD_RELOC_32_PCREL))
5476 if (insn_start_frag == frag_now)
5477 add = (p - frag_now->fr_literal) - insn_start_off;
5482 add = insn_start_frag->fr_fix - insn_start_off;
5483 for (fr = insn_start_frag->fr_next;
5484 fr && fr != frag_now; fr = fr->fr_next)
5486 add += p - frag_now->fr_literal;
5491 reloc_type = BFD_RELOC_386_GOTPC;
5492 i.op[n].imms->X_add_number += add;
5494 else if (reloc_type == BFD_RELOC_64)
5495 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5497 /* Don't do the adjustment for x86-64, as there
5498 the pcrel addressing is relative to the _next_
5499 insn, and that is taken care of in other code. */
5500 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5502 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5503 i.op[n].disps, pcrel, reloc_type);
5510 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5515 for (n = 0; n < i.operands; n++)
5517 if (operand_type_check (i.types[n], imm))
5519 if (i.op[n].imms->X_op == O_constant)
5521 int size = imm_size (n);
5524 val = offset_in_range (i.op[n].imms->X_add_number,
5526 p = frag_more (size);
5527 md_number_to_chars (p, val, size);
5531 /* Not absolute_section.
5532 Need a 32-bit fixup (don't support 8bit
5533 non-absolute imms). Try to support other
5535 enum bfd_reloc_code_real reloc_type;
5536 int size = imm_size (n);
5539 if (i.types[n].bitfield.imm32s
5540 && (i.suffix == QWORD_MNEM_SUFFIX
5541 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5546 p = frag_more (size);
5547 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5549 /* This is tough to explain. We end up with this one if we
5550 * have operands that look like
5551 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5552 * obtain the absolute address of the GOT, and it is strongly
5553 * preferable from a performance point of view to avoid using
5554 * a runtime relocation for this. The actual sequence of
5555 * instructions often look something like:
5560 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5562 * The call and pop essentially return the absolute address
5563 * of the label .L66 and store it in %ebx. The linker itself
5564 * will ultimately change the first operand of the addl so
5565 * that %ebx points to the GOT, but to keep things simple, the
5566 * .o file must have this operand set so that it generates not
5567 * the absolute address of .L66, but the absolute address of
5568 * itself. This allows the linker itself simply treat a GOTPC
5569 * relocation as asking for a pcrel offset to the GOT to be
5570 * added in, and the addend of the relocation is stored in the
5571 * operand field for the instruction itself.
5573 * Our job here is to fix the operand so that it would add
5574 * the correct offset so that %ebx would point to itself. The
5575 * thing that is tricky is that .-.L66 will point to the
5576 * beginning of the instruction, so we need to further modify
5577 * the operand so that it will point to itself. There are
5578 * other cases where you have something like:
5580 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5582 * and here no correction would be required. Internally in
5583 * the assembler we treat operands of this form as not being
5584 * pcrel since the '.' is explicitly mentioned, and I wonder
5585 * whether it would simplify matters to do it this way. Who
5586 * knows. In earlier versions of the PIC patches, the
5587 * pcrel_adjust field was used to store the correction, but
5588 * since the expression is not pcrel, I felt it would be
5589 * confusing to do it this way. */
5591 if ((reloc_type == BFD_RELOC_32
5592 || reloc_type == BFD_RELOC_X86_64_32S
5593 || reloc_type == BFD_RELOC_64)
5595 && GOT_symbol == i.op[n].imms->X_add_symbol
5596 && (i.op[n].imms->X_op == O_symbol
5597 || (i.op[n].imms->X_op == O_add
5598 && ((symbol_get_value_expression
5599 (i.op[n].imms->X_op_symbol)->X_op)
5604 if (insn_start_frag == frag_now)
5605 add = (p - frag_now->fr_literal) - insn_start_off;
5610 add = insn_start_frag->fr_fix - insn_start_off;
5611 for (fr = insn_start_frag->fr_next;
5612 fr && fr != frag_now; fr = fr->fr_next)
5614 add += p - frag_now->fr_literal;
5618 reloc_type = BFD_RELOC_386_GOTPC;
5620 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5622 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5623 i.op[n].imms->X_add_number += add;
5625 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5626 i.op[n].imms, 0, reloc_type);
5632 /* x86_cons_fix_new is called via the expression parsing code when a
5633 reloc is needed. We use this hook to get the correct .got reloc. */
5634 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5635 static int cons_sign = -1;
5638 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5641 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5643 got_reloc = NO_RELOC;
5646 if (exp->X_op == O_secrel)
5648 exp->X_op = O_symbol;
5649 r = BFD_RELOC_32_SECREL;
5653 fix_new_exp (frag, off, len, exp, 0, r);
5656 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5657 # define lex_got(reloc, adjust, types) NULL
5659 /* Parse operands of the form
5660 <symbol>@GOTOFF+<nnn>
5661 and similar .plt or .got references.
5663 If we find one, set up the correct relocation in RELOC and copy the
5664 input string, minus the `@GOTOFF' into a malloc'd buffer for
5665 parsing by the calling routine. Return this buffer, and if ADJUST
5666 is non-null set it to the length of the string we removed from the
5667 input line. Otherwise return NULL. */
5669 lex_got (enum bfd_reloc_code_real *reloc,
5671 i386_operand_type *types)
5673 /* Some of the relocations depend on the size of what field is to
5674 be relocated. But in our callers i386_immediate and i386_displacement
5675 we don't yet know the operand size (this will be set by insn
5676 matching). Hence we record the word32 relocation here,
5677 and adjust the reloc according to the real size in reloc(). */
5678 static const struct {
5680 const enum bfd_reloc_code_real rel[2];
5681 const i386_operand_type types64;
5684 BFD_RELOC_X86_64_PLTOFF64 },
5685 OPERAND_TYPE_IMM64 },
5686 { "PLT", { BFD_RELOC_386_PLT32,
5687 BFD_RELOC_X86_64_PLT32 },
5688 OPERAND_TYPE_IMM32_32S_DISP32 },
5690 BFD_RELOC_X86_64_GOTPLT64 },
5691 OPERAND_TYPE_IMM64_DISP64 },
5692 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5693 BFD_RELOC_X86_64_GOTOFF64 },
5694 OPERAND_TYPE_IMM64_DISP64 },
5696 BFD_RELOC_X86_64_GOTPCREL },
5697 OPERAND_TYPE_IMM32_32S_DISP32 },
5698 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5699 BFD_RELOC_X86_64_TLSGD },
5700 OPERAND_TYPE_IMM32_32S_DISP32 },
5701 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5703 OPERAND_TYPE_NONE },
5705 BFD_RELOC_X86_64_TLSLD },
5706 OPERAND_TYPE_IMM32_32S_DISP32 },
5707 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5708 BFD_RELOC_X86_64_GOTTPOFF },
5709 OPERAND_TYPE_IMM32_32S_DISP32 },
5710 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5711 BFD_RELOC_X86_64_TPOFF32 },
5712 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5713 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5715 OPERAND_TYPE_NONE },
5716 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5717 BFD_RELOC_X86_64_DTPOFF32 },
5719 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5720 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5722 OPERAND_TYPE_NONE },
5723 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5725 OPERAND_TYPE_NONE },
5726 { "GOT", { BFD_RELOC_386_GOT32,
5727 BFD_RELOC_X86_64_GOT32 },
5728 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5729 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5730 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5731 OPERAND_TYPE_IMM32_32S_DISP32 },
5732 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5733 BFD_RELOC_X86_64_TLSDESC_CALL },
5734 OPERAND_TYPE_IMM32_32S_DISP32 },
5742 for (cp = input_line_pointer; *cp != '@'; cp++)
5743 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5746 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5750 len = strlen (gotrel[j].str);
5751 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5753 if (gotrel[j].rel[object_64bit] != 0)
5756 char *tmpbuf, *past_reloc;
5758 *reloc = gotrel[j].rel[object_64bit];
5764 if (flag_code != CODE_64BIT)
5766 types->bitfield.imm32 = 1;
5767 types->bitfield.disp32 = 1;
5770 *types = gotrel[j].types64;
5773 if (GOT_symbol == NULL)
5774 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5776 /* The length of the first part of our input line. */
5777 first = cp - input_line_pointer;
5779 /* The second part goes from after the reloc token until
5780 (and including) an end_of_line char or comma. */
5781 past_reloc = cp + 1 + len;
5783 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5785 second = cp + 1 - past_reloc;
5787 /* Allocate and copy string. The trailing NUL shouldn't
5788 be necessary, but be safe. */
5789 tmpbuf = xmalloc (first + second + 2);
5790 memcpy (tmpbuf, input_line_pointer, first);
5791 if (second != 0 && *past_reloc != ' ')
5792 /* Replace the relocation token with ' ', so that
5793 errors like foo@GOTOFF1 will be detected. */
5794 tmpbuf[first++] = ' ';
5795 memcpy (tmpbuf + first, past_reloc, second);
5796 tmpbuf[first + second] = '\0';
5800 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5801 gotrel[j].str, 1 << (5 + object_64bit));
5806 /* Might be a symbol version string. Don't as_bad here. */
5811 x86_cons (expressionS *exp, int size)
5813 if (size == 4 || (object_64bit && size == 8))
5815 /* Handle @GOTOFF and the like in an expression. */
5817 char *gotfree_input_line;
5820 save = input_line_pointer;
5821 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
5822 if (gotfree_input_line)
5823 input_line_pointer = gotfree_input_line;
5827 if (gotfree_input_line)
5829 /* expression () has merrily parsed up to the end of line,
5830 or a comma - in the wrong buffer. Transfer how far
5831 input_line_pointer has moved to the right buffer. */
5832 input_line_pointer = (save
5833 + (input_line_pointer - gotfree_input_line)
5835 free (gotfree_input_line);
5836 if (exp->X_op == O_constant
5837 || exp->X_op == O_absent
5838 || exp->X_op == O_illegal
5839 || exp->X_op == O_register
5840 || exp->X_op == O_big)
5842 char c = *input_line_pointer;
5843 *input_line_pointer = 0;
5844 as_bad (_("missing or invalid expression `%s'"), save);
5845 *input_line_pointer = c;
5854 static void signed_cons (int size)
5856 if (flag_code == CODE_64BIT)
5864 pe_directive_secrel (dummy)
5865 int dummy ATTRIBUTE_UNUSED;
5872 if (exp.X_op == O_symbol)
5873 exp.X_op = O_secrel;
5875 emit_expr (&exp, 4);
5877 while (*input_line_pointer++ == ',');
5879 input_line_pointer--;
5880 demand_empty_rest_of_line ();
5885 i386_immediate (char *imm_start)
5887 char *save_input_line_pointer;
5888 char *gotfree_input_line;
5891 i386_operand_type types;
5893 operand_type_set (&types, ~0);
5895 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5897 as_bad (_("at most %d immediate operands are allowed"),
5898 MAX_IMMEDIATE_OPERANDS);
5902 exp = &im_expressions[i.imm_operands++];
5903 i.op[this_operand].imms = exp;
5905 if (is_space_char (*imm_start))
5908 save_input_line_pointer = input_line_pointer;
5909 input_line_pointer = imm_start;
5911 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
5912 if (gotfree_input_line)
5913 input_line_pointer = gotfree_input_line;
5915 exp_seg = expression (exp);
5918 if (*input_line_pointer)
5919 as_bad (_("junk `%s' after expression"), input_line_pointer);
5921 input_line_pointer = save_input_line_pointer;
5922 if (gotfree_input_line)
5923 free (gotfree_input_line);
5925 if (exp->X_op == O_absent
5926 || exp->X_op == O_illegal
5927 || exp->X_op == O_big
5928 || (gotfree_input_line
5929 && (exp->X_op == O_constant
5930 || exp->X_op == O_register)))
5932 as_bad (_("missing or invalid immediate expression `%s'"),
5936 else if (exp->X_op == O_constant)
5938 /* Size it properly later. */
5939 i.types[this_operand].bitfield.imm64 = 1;
5940 /* If BFD64, sign extend val. */
5941 if (!use_rela_relocations
5942 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5944 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
5946 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5947 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
5948 && exp_seg != absolute_section
5949 && exp_seg != text_section
5950 && exp_seg != data_section
5951 && exp_seg != bss_section
5952 && exp_seg != undefined_section
5953 && !bfd_is_com_section (exp_seg))
5955 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
5959 else if (!intel_syntax && exp->X_op == O_register)
5961 as_bad (_("illegal immediate register operand %s"), imm_start);
5966 /* This is an address. The size of the address will be
5967 determined later, depending on destination register,
5968 suffix, or the default for the section. */
5969 i.types[this_operand].bitfield.imm8 = 1;
5970 i.types[this_operand].bitfield.imm16 = 1;
5971 i.types[this_operand].bitfield.imm32 = 1;
5972 i.types[this_operand].bitfield.imm32s = 1;
5973 i.types[this_operand].bitfield.imm64 = 1;
5974 i.types[this_operand] = operand_type_and (i.types[this_operand],
5982 i386_scale (char *scale)
5985 char *save = input_line_pointer;
5987 input_line_pointer = scale;
5988 val = get_absolute_expression ();
5993 i.log2_scale_factor = 0;
5996 i.log2_scale_factor = 1;
5999 i.log2_scale_factor = 2;
6002 i.log2_scale_factor = 3;
6006 char sep = *input_line_pointer;
6008 *input_line_pointer = '\0';
6009 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6011 *input_line_pointer = sep;
6012 input_line_pointer = save;
6016 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6018 as_warn (_("scale factor of %d without an index register"),
6019 1 << i.log2_scale_factor);
6020 i.log2_scale_factor = 0;
6022 scale = input_line_pointer;
6023 input_line_pointer = save;
6028 i386_displacement (char *disp_start, char *disp_end)
6032 char *save_input_line_pointer;
6033 char *gotfree_input_line;
6035 i386_operand_type bigdisp, types = anydisp;
6038 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6040 as_bad (_("at most %d displacement operands are allowed"),
6041 MAX_MEMORY_OPERANDS);
6045 operand_type_set (&bigdisp, 0);
6046 if ((i.types[this_operand].bitfield.jumpabsolute)
6047 || (!current_templates->start->opcode_modifier.jump
6048 && !current_templates->start->opcode_modifier.jumpdword))
6050 bigdisp.bitfield.disp32 = 1;
6051 override = (i.prefix[ADDR_PREFIX] != 0);
6052 if (flag_code == CODE_64BIT)
6056 bigdisp.bitfield.disp32s = 1;
6057 bigdisp.bitfield.disp64 = 1;
6060 else if ((flag_code == CODE_16BIT) ^ override)
6062 bigdisp.bitfield.disp32 = 0;
6063 bigdisp.bitfield.disp16 = 1;
6068 /* For PC-relative branches, the width of the displacement
6069 is dependent upon data size, not address size. */
6070 override = (i.prefix[DATA_PREFIX] != 0);
6071 if (flag_code == CODE_64BIT)
6073 if (override || i.suffix == WORD_MNEM_SUFFIX)
6074 bigdisp.bitfield.disp16 = 1;
6077 bigdisp.bitfield.disp32 = 1;
6078 bigdisp.bitfield.disp32s = 1;
6084 override = (i.suffix == (flag_code != CODE_16BIT
6086 : LONG_MNEM_SUFFIX));
6087 bigdisp.bitfield.disp32 = 1;
6088 if ((flag_code == CODE_16BIT) ^ override)
6090 bigdisp.bitfield.disp32 = 0;
6091 bigdisp.bitfield.disp16 = 1;
6095 i.types[this_operand] = operand_type_or (i.types[this_operand],
6098 exp = &disp_expressions[i.disp_operands];
6099 i.op[this_operand].disps = exp;
6101 save_input_line_pointer = input_line_pointer;
6102 input_line_pointer = disp_start;
6103 END_STRING_AND_SAVE (disp_end);
6105 #ifndef GCC_ASM_O_HACK
6106 #define GCC_ASM_O_HACK 0
6109 END_STRING_AND_SAVE (disp_end + 1);
6110 if (i.types[this_operand].bitfield.baseIndex
6111 && displacement_string_end[-1] == '+')
6113 /* This hack is to avoid a warning when using the "o"
6114 constraint within gcc asm statements.
6117 #define _set_tssldt_desc(n,addr,limit,type) \
6118 __asm__ __volatile__ ( \
6120 "movw %w1,2+%0\n\t" \
6122 "movb %b1,4+%0\n\t" \
6123 "movb %4,5+%0\n\t" \
6124 "movb $0,6+%0\n\t" \
6125 "movb %h1,7+%0\n\t" \
6127 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6129 This works great except that the output assembler ends
6130 up looking a bit weird if it turns out that there is
6131 no offset. You end up producing code that looks like:
6144 So here we provide the missing zero. */
6146 *displacement_string_end = '0';
6149 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6150 if (gotfree_input_line)
6151 input_line_pointer = gotfree_input_line;
6153 exp_seg = expression (exp);
6156 if (*input_line_pointer)
6157 as_bad (_("junk `%s' after expression"), input_line_pointer);
6159 RESTORE_END_STRING (disp_end + 1);
6161 input_line_pointer = save_input_line_pointer;
6162 if (gotfree_input_line)
6163 free (gotfree_input_line);
6166 /* We do this to make sure that the section symbol is in
6167 the symbol table. We will ultimately change the relocation
6168 to be relative to the beginning of the section. */
6169 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6170 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6171 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6173 if (exp->X_op != O_symbol)
6176 if (S_IS_LOCAL (exp->X_add_symbol)
6177 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6178 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6179 exp->X_op = O_subtract;
6180 exp->X_op_symbol = GOT_symbol;
6181 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6182 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6183 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6184 i.reloc[this_operand] = BFD_RELOC_64;
6186 i.reloc[this_operand] = BFD_RELOC_32;
6189 else if (exp->X_op == O_absent
6190 || exp->X_op == O_illegal
6191 || exp->X_op == O_big
6192 || (gotfree_input_line
6193 && (exp->X_op == O_constant
6194 || exp->X_op == O_register)))
6197 as_bad (_("missing or invalid displacement expression `%s'"),
6202 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6203 else if (exp->X_op != O_constant
6204 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6205 && exp_seg != absolute_section
6206 && exp_seg != text_section
6207 && exp_seg != data_section
6208 && exp_seg != bss_section
6209 && exp_seg != undefined_section
6210 && !bfd_is_com_section (exp_seg))
6212 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6217 RESTORE_END_STRING (disp_end);
6219 /* Check if this is a displacement only operand. */
6220 bigdisp = i.types[this_operand];
6221 bigdisp.bitfield.disp8 = 0;
6222 bigdisp.bitfield.disp16 = 0;
6223 bigdisp.bitfield.disp32 = 0;
6224 bigdisp.bitfield.disp32s = 0;
6225 bigdisp.bitfield.disp64 = 0;
6226 if (operand_type_all_zero (&bigdisp))
6227 i.types[this_operand] = operand_type_and (i.types[this_operand],
6233 /* Make sure the memory operand we've been dealt is valid.
6234 Return 1 on success, 0 on a failure. */
6237 i386_index_check (const char *operand_string)
6240 #if INFER_ADDR_PREFIX
6246 if (flag_code == CODE_64BIT)
6249 && ((i.prefix[ADDR_PREFIX] == 0
6250 && !i.base_reg->reg_type.bitfield.reg64)
6251 || (i.prefix[ADDR_PREFIX]
6252 && !i.base_reg->reg_type.bitfield.reg32))
6254 || i.base_reg->reg_num !=
6255 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6257 && (!i.index_reg->reg_type.bitfield.baseindex
6258 || (i.prefix[ADDR_PREFIX] == 0
6259 && i.index_reg->reg_num != RegRiz
6260 && !i.index_reg->reg_type.bitfield.reg64
6262 || (i.prefix[ADDR_PREFIX]
6263 && i.index_reg->reg_num != RegEiz
6264 && !i.index_reg->reg_type.bitfield.reg32))))
6269 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6273 && (!i.base_reg->reg_type.bitfield.reg16
6274 || !i.base_reg->reg_type.bitfield.baseindex))
6276 && (!i.index_reg->reg_type.bitfield.reg16
6277 || !i.index_reg->reg_type.bitfield.baseindex
6279 && i.base_reg->reg_num < 6
6280 && i.index_reg->reg_num >= 6
6281 && i.log2_scale_factor == 0))))
6288 && !i.base_reg->reg_type.bitfield.reg32)
6290 && ((!i.index_reg->reg_type.bitfield.reg32
6291 && i.index_reg->reg_num != RegEiz)
6292 || !i.index_reg->reg_type.bitfield.baseindex)))
6298 #if INFER_ADDR_PREFIX
6299 if (i.prefix[ADDR_PREFIX] == 0)
6301 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6303 /* Change the size of any displacement too. At most one of
6304 Disp16 or Disp32 is set.
6305 FIXME. There doesn't seem to be any real need for separate
6306 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6307 Removing them would probably clean up the code quite a lot. */
6308 if (flag_code != CODE_64BIT
6309 && (i.types[this_operand].bitfield.disp16
6310 || i.types[this_operand].bitfield.disp32))
6311 i.types[this_operand]
6312 = operand_type_xor (i.types[this_operand], disp16_32);
6317 as_bad (_("`%s' is not a valid base/index expression"),
6321 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6323 flag_code_names[flag_code]);
6328 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6332 i386_att_operand (char *operand_string)
6336 char *op_string = operand_string;
6338 if (is_space_char (*op_string))
6341 /* We check for an absolute prefix (differentiating,
6342 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6343 if (*op_string == ABSOLUTE_PREFIX)
6346 if (is_space_char (*op_string))
6348 i.types[this_operand].bitfield.jumpabsolute = 1;
6351 /* Check if operand is a register. */
6352 if ((r = parse_register (op_string, &end_op)) != NULL)
6354 i386_operand_type temp;
6356 /* Check for a segment override by searching for ':' after a
6357 segment register. */
6359 if (is_space_char (*op_string))
6361 if (*op_string == ':'
6362 && (r->reg_type.bitfield.sreg2
6363 || r->reg_type.bitfield.sreg3))
6368 i.seg[i.mem_operands] = &es;
6371 i.seg[i.mem_operands] = &cs;
6374 i.seg[i.mem_operands] = &ss;
6377 i.seg[i.mem_operands] = &ds;
6380 i.seg[i.mem_operands] = &fs;
6383 i.seg[i.mem_operands] = &gs;
6387 /* Skip the ':' and whitespace. */
6389 if (is_space_char (*op_string))
6392 if (!is_digit_char (*op_string)
6393 && !is_identifier_char (*op_string)
6394 && *op_string != '('
6395 && *op_string != ABSOLUTE_PREFIX)
6397 as_bad (_("bad memory operand `%s'"), op_string);
6400 /* Handle case of %es:*foo. */
6401 if (*op_string == ABSOLUTE_PREFIX)
6404 if (is_space_char (*op_string))
6406 i.types[this_operand].bitfield.jumpabsolute = 1;
6408 goto do_memory_reference;
6412 as_bad (_("junk `%s' after register"), op_string);
6416 temp.bitfield.baseindex = 0;
6417 i.types[this_operand] = operand_type_or (i.types[this_operand],
6419 i.types[this_operand].bitfield.unspecified = 0;
6420 i.op[this_operand].regs = r;
6423 else if (*op_string == REGISTER_PREFIX)
6425 as_bad (_("bad register name `%s'"), op_string);
6428 else if (*op_string == IMMEDIATE_PREFIX)
6431 if (i.types[this_operand].bitfield.jumpabsolute)
6433 as_bad (_("immediate operand illegal with absolute jump"));
6436 if (!i386_immediate (op_string))
6439 else if (is_digit_char (*op_string)
6440 || is_identifier_char (*op_string)
6441 || *op_string == '(')
6443 /* This is a memory reference of some sort. */
6446 /* Start and end of displacement string expression (if found). */
6447 char *displacement_string_start;
6448 char *displacement_string_end;
6450 do_memory_reference:
6451 if ((i.mem_operands == 1
6452 && !current_templates->start->opcode_modifier.isstring)
6453 || i.mem_operands == 2)
6455 as_bad (_("too many memory references for `%s'"),
6456 current_templates->start->name);
6460 /* Check for base index form. We detect the base index form by
6461 looking for an ')' at the end of the operand, searching
6462 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6464 base_string = op_string + strlen (op_string);
6467 if (is_space_char (*base_string))
6470 /* If we only have a displacement, set-up for it to be parsed later. */
6471 displacement_string_start = op_string;
6472 displacement_string_end = base_string + 1;
6474 if (*base_string == ')')
6477 unsigned int parens_balanced = 1;
6478 /* We've already checked that the number of left & right ()'s are
6479 equal, so this loop will not be infinite. */
6483 if (*base_string == ')')
6485 if (*base_string == '(')
6488 while (parens_balanced);
6490 temp_string = base_string;
6492 /* Skip past '(' and whitespace. */
6494 if (is_space_char (*base_string))
6497 if (*base_string == ','
6498 || ((i.base_reg = parse_register (base_string, &end_op))
6501 displacement_string_end = temp_string;
6503 i.types[this_operand].bitfield.baseindex = 1;
6507 base_string = end_op;
6508 if (is_space_char (*base_string))
6512 /* There may be an index reg or scale factor here. */
6513 if (*base_string == ',')
6516 if (is_space_char (*base_string))
6519 if ((i.index_reg = parse_register (base_string, &end_op))
6522 base_string = end_op;
6523 if (is_space_char (*base_string))
6525 if (*base_string == ',')
6528 if (is_space_char (*base_string))
6531 else if (*base_string != ')')
6533 as_bad (_("expecting `,' or `)' "
6534 "after index register in `%s'"),
6539 else if (*base_string == REGISTER_PREFIX)
6541 as_bad (_("bad register name `%s'"), base_string);
6545 /* Check for scale factor. */
6546 if (*base_string != ')')
6548 char *end_scale = i386_scale (base_string);
6553 base_string = end_scale;
6554 if (is_space_char (*base_string))
6556 if (*base_string != ')')
6558 as_bad (_("expecting `)' "
6559 "after scale factor in `%s'"),
6564 else if (!i.index_reg)
6566 as_bad (_("expecting index register or scale factor "
6567 "after `,'; got '%c'"),
6572 else if (*base_string != ')')
6574 as_bad (_("expecting `,' or `)' "
6575 "after base register in `%s'"),
6580 else if (*base_string == REGISTER_PREFIX)
6582 as_bad (_("bad register name `%s'"), base_string);
6587 /* If there's an expression beginning the operand, parse it,
6588 assuming displacement_string_start and
6589 displacement_string_end are meaningful. */
6590 if (displacement_string_start != displacement_string_end)
6592 if (!i386_displacement (displacement_string_start,
6593 displacement_string_end))
6597 /* Special case for (%dx) while doing input/output op. */
6599 && operand_type_equal (&i.base_reg->reg_type,
6600 ®16_inoutportreg)
6602 && i.log2_scale_factor == 0
6603 && i.seg[i.mem_operands] == 0
6604 && !operand_type_check (i.types[this_operand], disp))
6606 operand_type_set (&i.types[this_operand], 0);
6607 i.types[this_operand].bitfield.inoutportreg = 1;
6611 if (i386_index_check (operand_string) == 0)
6613 i.types[this_operand].bitfield.mem = 1;
6618 /* It's not a memory operand; argh! */
6619 as_bad (_("invalid char %s beginning operand %d `%s'"),
6620 output_invalid (*op_string),
6625 return 1; /* Normal return. */
6628 /* md_estimate_size_before_relax()
6630 Called just before relax() for rs_machine_dependent frags. The x86
6631 assembler uses these frags to handle variable size jump
6634 Any symbol that is now undefined will not become defined.
6635 Return the correct fr_subtype in the frag.
6636 Return the initial "guess for variable size of frag" to caller.
6637 The guess is actually the growth beyond the fixed part. Whatever
6638 we do to grow the fixed or variable part contributes to our
6642 md_estimate_size_before_relax (fragP, segment)
6646 /* We've already got fragP->fr_subtype right; all we have to do is
6647 check for un-relaxable symbols. On an ELF system, we can't relax
6648 an externally visible symbol, because it may be overridden by a
6650 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6651 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6653 && (S_IS_EXTERNAL (fragP->fr_symbol)
6654 || S_IS_WEAK (fragP->fr_symbol)))
6658 /* Symbol is undefined in this segment, or we need to keep a
6659 reloc so that weak symbols can be overridden. */
6660 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6661 enum bfd_reloc_code_real reloc_type;
6662 unsigned char *opcode;
6665 if (fragP->fr_var != NO_RELOC)
6666 reloc_type = fragP->fr_var;
6668 reloc_type = BFD_RELOC_16_PCREL;
6670 reloc_type = BFD_RELOC_32_PCREL;
6672 old_fr_fix = fragP->fr_fix;
6673 opcode = (unsigned char *) fragP->fr_opcode;
6675 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
6678 /* Make jmp (0xeb) a (d)word displacement jump. */
6680 fragP->fr_fix += size;
6681 fix_new (fragP, old_fr_fix, size,
6683 fragP->fr_offset, 1,
6689 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
6691 /* Negate the condition, and branch past an
6692 unconditional jump. */
6695 /* Insert an unconditional jump. */
6697 /* We added two extra opcode bytes, and have a two byte
6699 fragP->fr_fix += 2 + 2;
6700 fix_new (fragP, old_fr_fix + 2, 2,
6702 fragP->fr_offset, 1,
6709 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6714 fixP = fix_new (fragP, old_fr_fix, 1,
6716 fragP->fr_offset, 1,
6718 fixP->fx_signed = 1;
6722 /* This changes the byte-displacement jump 0x7N
6723 to the (d)word-displacement jump 0x0f,0x8N. */
6724 opcode[1] = opcode[0] + 0x10;
6725 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6726 /* We've added an opcode byte. */
6727 fragP->fr_fix += 1 + size;
6728 fix_new (fragP, old_fr_fix + 1, size,
6730 fragP->fr_offset, 1,
6735 BAD_CASE (fragP->fr_subtype);
6739 return fragP->fr_fix - old_fr_fix;
6742 /* Guess size depending on current relax state. Initially the relax
6743 state will correspond to a short jump and we return 1, because
6744 the variable part of the frag (the branch offset) is one byte
6745 long. However, we can relax a section more than once and in that
6746 case we must either set fr_subtype back to the unrelaxed state,
6747 or return the value for the appropriate branch. */
6748 return md_relax_table[fragP->fr_subtype].rlx_length;
6751 /* Called after relax() is finished.
6753 In: Address of frag.
6754 fr_type == rs_machine_dependent.
6755 fr_subtype is what the address relaxed to.
6757 Out: Any fixSs and constants are set up.
6758 Caller will turn frag into a ".space 0". */
6761 md_convert_frag (abfd, sec, fragP)
6762 bfd *abfd ATTRIBUTE_UNUSED;
6763 segT sec ATTRIBUTE_UNUSED;
6766 unsigned char *opcode;
6767 unsigned char *where_to_put_displacement = NULL;
6768 offsetT target_address;
6769 offsetT opcode_address;
6770 unsigned int extension = 0;
6771 offsetT displacement_from_opcode_start;
6773 opcode = (unsigned char *) fragP->fr_opcode;
6775 /* Address we want to reach in file space. */
6776 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
6778 /* Address opcode resides at in file space. */
6779 opcode_address = fragP->fr_address + fragP->fr_fix;
6781 /* Displacement from opcode start to fill into instruction. */
6782 displacement_from_opcode_start = target_address - opcode_address;
6784 if ((fragP->fr_subtype & BIG) == 0)
6786 /* Don't have to change opcode. */
6787 extension = 1; /* 1 opcode + 1 displacement */
6788 where_to_put_displacement = &opcode[1];
6792 if (no_cond_jump_promotion
6793 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
6794 as_warn_where (fragP->fr_file, fragP->fr_line,
6795 _("long jump required"));
6797 switch (fragP->fr_subtype)
6799 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6800 extension = 4; /* 1 opcode + 4 displacement */
6802 where_to_put_displacement = &opcode[1];
6805 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6806 extension = 2; /* 1 opcode + 2 displacement */
6808 where_to_put_displacement = &opcode[1];
6811 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6812 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6813 extension = 5; /* 2 opcode + 4 displacement */
6814 opcode[1] = opcode[0] + 0x10;
6815 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6816 where_to_put_displacement = &opcode[2];
6819 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6820 extension = 3; /* 2 opcode + 2 displacement */
6821 opcode[1] = opcode[0] + 0x10;
6822 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6823 where_to_put_displacement = &opcode[2];
6826 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6831 where_to_put_displacement = &opcode[3];
6835 BAD_CASE (fragP->fr_subtype);
6840 /* If size if less then four we are sure that the operand fits,
6841 but if it's 4, then it could be that the displacement is larger
6843 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6845 && ((addressT) (displacement_from_opcode_start - extension
6846 + ((addressT) 1 << 31))
6847 > (((addressT) 2 << 31) - 1)))
6849 as_bad_where (fragP->fr_file, fragP->fr_line,
6850 _("jump target out of range"));
6851 /* Make us emit 0. */
6852 displacement_from_opcode_start = extension;
6854 /* Now put displacement after opcode. */
6855 md_number_to_chars ((char *) where_to_put_displacement,
6856 (valueT) (displacement_from_opcode_start - extension),
6857 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
6858 fragP->fr_fix += extension;
6861 /* Apply a fixup (fixS) to segment data, once it has been determined
6862 by our caller that we have all the info we need to fix it up.
6864 On the 386, immediates, displacements, and data pointers are all in
6865 the same (little-endian) format, so we don't need to care about which
6869 md_apply_fix (fixP, valP, seg)
6870 /* The fix we're to put in. */
6872 /* Pointer to the value of the bits. */
6874 /* Segment fix is from. */
6875 segT seg ATTRIBUTE_UNUSED;
6877 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
6878 valueT value = *valP;
6880 #if !defined (TE_Mach)
6883 switch (fixP->fx_r_type)
6889 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6892 case BFD_RELOC_X86_64_32S:
6893 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6896 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6899 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6904 if (fixP->fx_addsy != NULL
6905 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
6906 || fixP->fx_r_type == BFD_RELOC_64_PCREL
6907 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6908 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6909 && !use_rela_relocations)
6911 /* This is a hack. There should be a better way to handle this.
6912 This covers for the fact that bfd_install_relocation will
6913 subtract the current location (for partial_inplace, PC relative
6914 relocations); see more below. */
6918 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6921 value += fixP->fx_where + fixP->fx_frag->fr_address;
6923 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6926 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
6929 || (symbol_section_p (fixP->fx_addsy)
6930 && sym_seg != absolute_section))
6931 && !generic_force_reloc (fixP))
6933 /* Yes, we add the values in twice. This is because
6934 bfd_install_relocation subtracts them out again. I think
6935 bfd_install_relocation is broken, but I don't dare change
6937 value += fixP->fx_where + fixP->fx_frag->fr_address;
6941 #if defined (OBJ_COFF) && defined (TE_PE)
6942 /* For some reason, the PE format does not store a
6943 section address offset for a PC relative symbol. */
6944 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
6945 || S_IS_WEAK (fixP->fx_addsy))
6946 value += md_pcrel_from (fixP);
6950 /* Fix a few things - the dynamic linker expects certain values here,
6951 and we must not disappoint it. */
6952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6953 if (IS_ELF && fixP->fx_addsy)
6954 switch (fixP->fx_r_type)
6956 case BFD_RELOC_386_PLT32:
6957 case BFD_RELOC_X86_64_PLT32:
6958 /* Make the jump instruction point to the address of the operand. At
6959 runtime we merely add the offset to the actual PLT entry. */
6963 case BFD_RELOC_386_TLS_GD:
6964 case BFD_RELOC_386_TLS_LDM:
6965 case BFD_RELOC_386_TLS_IE_32:
6966 case BFD_RELOC_386_TLS_IE:
6967 case BFD_RELOC_386_TLS_GOTIE:
6968 case BFD_RELOC_386_TLS_GOTDESC:
6969 case BFD_RELOC_X86_64_TLSGD:
6970 case BFD_RELOC_X86_64_TLSLD:
6971 case BFD_RELOC_X86_64_GOTTPOFF:
6972 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6973 value = 0; /* Fully resolved at runtime. No addend. */
6975 case BFD_RELOC_386_TLS_LE:
6976 case BFD_RELOC_386_TLS_LDO_32:
6977 case BFD_RELOC_386_TLS_LE_32:
6978 case BFD_RELOC_X86_64_DTPOFF32:
6979 case BFD_RELOC_X86_64_DTPOFF64:
6980 case BFD_RELOC_X86_64_TPOFF32:
6981 case BFD_RELOC_X86_64_TPOFF64:
6982 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6985 case BFD_RELOC_386_TLS_DESC_CALL:
6986 case BFD_RELOC_X86_64_TLSDESC_CALL:
6987 value = 0; /* Fully resolved at runtime. No addend. */
6988 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6992 case BFD_RELOC_386_GOT32:
6993 case BFD_RELOC_X86_64_GOT32:
6994 value = 0; /* Fully resolved at runtime. No addend. */
6997 case BFD_RELOC_VTABLE_INHERIT:
6998 case BFD_RELOC_VTABLE_ENTRY:
7005 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7007 #endif /* !defined (TE_Mach) */
7009 /* Are we finished with this relocation now? */
7010 if (fixP->fx_addsy == NULL)
7012 else if (use_rela_relocations)
7014 fixP->fx_no_overflow = 1;
7015 /* Remember value for tc_gen_reloc. */
7016 fixP->fx_addnumber = value;
7020 md_number_to_chars (p, value, fixP->fx_size);
7024 md_atof (int type, char *litP, int *sizeP)
7026 /* This outputs the LITTLENUMs in REVERSE order;
7027 in accord with the bigendian 386. */
7028 return ieee_md_atof (type, litP, sizeP, FALSE);
7031 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7034 output_invalid (int c)
7037 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7040 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7041 "(0x%x)", (unsigned char) c);
7042 return output_invalid_buf;
7045 /* REG_STRING starts *before* REGISTER_PREFIX. */
7047 static const reg_entry *
7048 parse_real_register (char *reg_string, char **end_op)
7050 char *s = reg_string;
7052 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7055 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7056 if (*s == REGISTER_PREFIX)
7059 if (is_space_char (*s))
7063 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7065 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7066 return (const reg_entry *) NULL;
7070 /* For naked regs, make sure that we are not dealing with an identifier.
7071 This prevents confusing an identifier like `eax_var' with register
7073 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7074 return (const reg_entry *) NULL;
7078 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7080 /* Handle floating point regs, allowing spaces in the (i) part. */
7081 if (r == i386_regtab /* %st is first entry of table */)
7083 if (is_space_char (*s))
7088 if (is_space_char (*s))
7090 if (*s >= '0' && *s <= '7')
7094 if (is_space_char (*s))
7099 r = hash_find (reg_hash, "st(0)");
7104 /* We have "%st(" then garbage. */
7105 return (const reg_entry *) NULL;
7109 if (r == NULL || allow_pseudo_reg)
7112 if (operand_type_all_zero (&r->reg_type))
7113 return (const reg_entry *) NULL;
7115 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7116 if (!allow_index_reg
7117 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7118 return (const reg_entry *) NULL;
7120 if (((r->reg_flags & (RegRex64 | RegRex))
7121 || r->reg_type.bitfield.reg64)
7122 && (!cpu_arch_flags.bitfield.cpulm
7123 || !operand_type_equal (&r->reg_type, &control))
7124 && flag_code != CODE_64BIT)
7125 return (const reg_entry *) NULL;
7127 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7128 return (const reg_entry *) NULL;
7133 /* REG_STRING starts *before* REGISTER_PREFIX. */
7135 static const reg_entry *
7136 parse_register (char *reg_string, char **end_op)
7140 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7141 r = parse_real_register (reg_string, end_op);
7146 char *save = input_line_pointer;
7150 input_line_pointer = reg_string;
7151 c = get_symbol_end ();
7152 symbolP = symbol_find (reg_string);
7153 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7155 const expressionS *e = symbol_get_value_expression (symbolP);
7157 know (e->X_op == O_register);
7158 know (e->X_add_number >= 0
7159 && (valueT) e->X_add_number < i386_regtab_size);
7160 r = i386_regtab + e->X_add_number;
7161 *end_op = input_line_pointer;
7163 *input_line_pointer = c;
7164 input_line_pointer = save;
7170 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7173 char *end = input_line_pointer;
7176 r = parse_register (name, &input_line_pointer);
7177 if (r && end <= input_line_pointer)
7179 *nextcharP = *input_line_pointer;
7180 *input_line_pointer = 0;
7181 e->X_op = O_register;
7182 e->X_add_number = r - i386_regtab;
7185 input_line_pointer = end;
7191 md_operand (expressionS *e)
7193 if (*input_line_pointer == REGISTER_PREFIX)
7196 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7200 e->X_op = O_register;
7201 e->X_add_number = r - i386_regtab;
7202 input_line_pointer = end;
7208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7209 const char *md_shortopts = "kVQ:sqn";
7211 const char *md_shortopts = "qn";
7214 #define OPTION_32 (OPTION_MD_BASE + 0)
7215 #define OPTION_64 (OPTION_MD_BASE + 1)
7216 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7217 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7218 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7219 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7220 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7221 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7222 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7223 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7225 struct option md_longopts[] =
7227 {"32", no_argument, NULL, OPTION_32},
7228 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7229 {"64", no_argument, NULL, OPTION_64},
7231 {"divide", no_argument, NULL, OPTION_DIVIDE},
7232 {"march", required_argument, NULL, OPTION_MARCH},
7233 {"mtune", required_argument, NULL, OPTION_MTUNE},
7234 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7235 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7236 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7237 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7238 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7239 {NULL, no_argument, NULL, 0}
7241 size_t md_longopts_size = sizeof (md_longopts);
7244 md_parse_option (int c, char *arg)
7252 optimize_align_code = 0;
7259 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7260 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7261 should be emitted or not. FIXME: Not implemented. */
7265 /* -V: SVR4 argument to print version ID. */
7267 print_version_id ();
7270 /* -k: Ignore for FreeBSD compatibility. */
7275 /* -s: On i386 Solaris, this tells the native assembler to use
7276 .stab instead of .stab.excl. We always use .stab anyhow. */
7279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7282 const char **list, **l;
7284 list = bfd_target_list ();
7285 for (l = list; *l != NULL; l++)
7286 if (CONST_STRNEQ (*l, "elf64-x86-64")
7287 || strcmp (*l, "coff-x86-64") == 0
7288 || strcmp (*l, "pe-x86-64") == 0
7289 || strcmp (*l, "pei-x86-64") == 0)
7291 default_arch = "x86_64";
7295 as_fatal (_("No compiled in support for x86_64"));
7302 default_arch = "i386";
7306 #ifdef SVR4_COMMENT_CHARS
7311 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7313 for (s = i386_comment_chars; *s != '\0'; s++)
7317 i386_comment_chars = n;
7323 arch = xstrdup (arg);
7327 as_fatal (_("Invalid -march= option: `%s'"), arg);
7328 next = strchr (arch, '+');
7331 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7333 if (strcmp (arch, cpu_arch [i].name) == 0)
7336 cpu_arch_name = cpu_arch[i].name;
7337 cpu_sub_arch_name = NULL;
7338 cpu_arch_flags = cpu_arch[i].flags;
7339 cpu_arch_isa = cpu_arch[i].type;
7340 cpu_arch_isa_flags = cpu_arch[i].flags;
7341 if (!cpu_arch_tune_set)
7343 cpu_arch_tune = cpu_arch_isa;
7344 cpu_arch_tune_flags = cpu_arch_isa_flags;
7348 else if (*cpu_arch [i].name == '.'
7349 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7351 /* ISA entension. */
7352 i386_cpu_flags flags;
7353 flags = cpu_flags_or (cpu_arch_flags,
7355 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7357 if (cpu_sub_arch_name)
7359 char *name = cpu_sub_arch_name;
7360 cpu_sub_arch_name = concat (name,
7362 (const char *) NULL);
7366 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7367 cpu_arch_flags = flags;
7373 if (i >= ARRAY_SIZE (cpu_arch))
7374 as_fatal (_("Invalid -march= option: `%s'"), arg);
7378 while (next != NULL );
7383 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7384 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7386 if (strcmp (arg, cpu_arch [i].name) == 0)
7388 cpu_arch_tune_set = 1;
7389 cpu_arch_tune = cpu_arch [i].type;
7390 cpu_arch_tune_flags = cpu_arch[i].flags;
7394 if (i >= ARRAY_SIZE (cpu_arch))
7395 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7398 case OPTION_MMNEMONIC:
7399 if (strcasecmp (arg, "att") == 0)
7401 else if (strcasecmp (arg, "intel") == 0)
7404 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7407 case OPTION_MSYNTAX:
7408 if (strcasecmp (arg, "att") == 0)
7410 else if (strcasecmp (arg, "intel") == 0)
7413 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7416 case OPTION_MINDEX_REG:
7417 allow_index_reg = 1;
7420 case OPTION_MNAKED_REG:
7421 allow_naked_reg = 1;
7424 case OPTION_MOLD_GCC:
7435 md_show_usage (stream)
7438 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7439 fprintf (stream, _("\
7441 -V print assembler version number\n\
7444 fprintf (stream, _("\
7445 -n Do not optimize code alignment\n\
7446 -q quieten some warnings\n"));
7447 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7448 fprintf (stream, _("\
7451 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7452 fprintf (stream, _("\
7453 --32/--64 generate 32bit/64bit code\n"));
7455 #ifdef SVR4_COMMENT_CHARS
7456 fprintf (stream, _("\
7457 --divide do not treat `/' as a comment character\n"));
7459 fprintf (stream, _("\
7460 --divide ignored\n"));
7462 fprintf (stream, _("\
7463 -march=CPU[,+EXTENSION...]\n\
7464 generate code for CPU and EXTENSION, CPU is one of:\n\
7465 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7466 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7467 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7468 generic32, generic64\n\
7469 EXTENSION is combination of:\n\
7470 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7471 vmx, smx, xsave, 3dnow, 3dnowa, sse4a, sse5, svme,\n\
7473 fprintf (stream, _("\
7474 -mtune=CPU optimize for CPU, CPU is one of:\n\
7475 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7476 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7477 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
7478 generic32, generic64\n"));
7479 fprintf (stream, _("\
7480 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7481 fprintf (stream, _("\
7482 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7483 fprintf (stream, _("\
7484 -mindex-reg support pseudo index registers\n"));
7485 fprintf (stream, _("\
7486 -mnaked-reg don't require `%%' prefix for registers\n"));
7487 fprintf (stream, _("\
7488 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7491 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7492 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
7494 /* Pick the target format to use. */
7497 i386_target_format (void)
7499 if (!strcmp (default_arch, "x86_64"))
7501 set_code_flag (CODE_64BIT);
7502 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7504 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7505 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7506 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7507 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7508 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7509 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7510 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7511 cpu_arch_isa_flags.bitfield.cpummx= 1;
7512 cpu_arch_isa_flags.bitfield.cpusse = 1;
7513 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7515 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7517 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7518 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7519 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7520 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7521 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7522 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7523 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7524 cpu_arch_tune_flags.bitfield.cpummx= 1;
7525 cpu_arch_tune_flags.bitfield.cpusse = 1;
7526 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7529 else if (!strcmp (default_arch, "i386"))
7531 set_code_flag (CODE_32BIT);
7532 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7534 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7535 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7536 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7538 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7540 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7541 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7542 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7546 as_fatal (_("Unknown architecture"));
7547 switch (OUTPUT_FLAVOR)
7550 case bfd_target_coff_flavour:
7551 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7554 #ifdef OBJ_MAYBE_AOUT
7555 case bfd_target_aout_flavour:
7556 return AOUT_TARGET_FORMAT;
7558 #ifdef OBJ_MAYBE_COFF
7559 case bfd_target_coff_flavour:
7562 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7563 case bfd_target_elf_flavour:
7565 if (flag_code == CODE_64BIT)
7568 use_rela_relocations = 1;
7570 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7579 #endif /* OBJ_MAYBE_ more than one */
7581 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7583 i386_elf_emit_arch_note (void)
7585 if (IS_ELF && cpu_arch_name != NULL)
7588 asection *seg = now_seg;
7589 subsegT subseg = now_subseg;
7590 Elf_Internal_Note i_note;
7591 Elf_External_Note e_note;
7592 asection *note_secp;
7595 /* Create the .note section. */
7596 note_secp = subseg_new (".note", 0);
7597 bfd_set_section_flags (stdoutput,
7599 SEC_HAS_CONTENTS | SEC_READONLY);
7601 /* Process the arch string. */
7602 len = strlen (cpu_arch_name);
7604 i_note.namesz = len + 1;
7606 i_note.type = NT_ARCH;
7607 p = frag_more (sizeof (e_note.namesz));
7608 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7609 p = frag_more (sizeof (e_note.descsz));
7610 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7611 p = frag_more (sizeof (e_note.type));
7612 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7613 p = frag_more (len + 1);
7614 strcpy (p, cpu_arch_name);
7616 frag_align (2, 0, 0);
7618 subseg_set (seg, subseg);
7624 md_undefined_symbol (name)
7627 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7628 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7629 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7630 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
7634 if (symbol_find (name))
7635 as_bad (_("GOT already in symbol table"));
7636 GOT_symbol = symbol_new (name, undefined_section,
7637 (valueT) 0, &zero_address_frag);
7644 /* Round up a section size to the appropriate boundary. */
7647 md_section_align (segment, size)
7648 segT segment ATTRIBUTE_UNUSED;
7651 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7652 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7654 /* For a.out, force the section size to be aligned. If we don't do
7655 this, BFD will align it for us, but it will not write out the
7656 final bytes of the section. This may be a bug in BFD, but it is
7657 easier to fix it here since that is how the other a.out targets
7661 align = bfd_get_section_alignment (stdoutput, segment);
7662 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7669 /* On the i386, PC-relative offsets are relative to the start of the
7670 next instruction. That is, the address of the offset, plus its
7671 size, since the offset is always the last part of the insn. */
7674 md_pcrel_from (fixS *fixP)
7676 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7682 s_bss (int ignore ATTRIBUTE_UNUSED)
7686 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7688 obj_elf_section_change_hook ();
7690 temp = get_absolute_expression ();
7691 subseg_set (bss_section, (subsegT) temp);
7692 demand_empty_rest_of_line ();
7698 i386_validate_fix (fixS *fixp)
7700 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7702 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7706 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7711 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7713 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
7720 tc_gen_reloc (section, fixp)
7721 asection *section ATTRIBUTE_UNUSED;
7725 bfd_reloc_code_real_type code;
7727 switch (fixp->fx_r_type)
7729 case BFD_RELOC_X86_64_PLT32:
7730 case BFD_RELOC_X86_64_GOT32:
7731 case BFD_RELOC_X86_64_GOTPCREL:
7732 case BFD_RELOC_386_PLT32:
7733 case BFD_RELOC_386_GOT32:
7734 case BFD_RELOC_386_GOTOFF:
7735 case BFD_RELOC_386_GOTPC:
7736 case BFD_RELOC_386_TLS_GD:
7737 case BFD_RELOC_386_TLS_LDM:
7738 case BFD_RELOC_386_TLS_LDO_32:
7739 case BFD_RELOC_386_TLS_IE_32:
7740 case BFD_RELOC_386_TLS_IE:
7741 case BFD_RELOC_386_TLS_GOTIE:
7742 case BFD_RELOC_386_TLS_LE_32:
7743 case BFD_RELOC_386_TLS_LE:
7744 case BFD_RELOC_386_TLS_GOTDESC:
7745 case BFD_RELOC_386_TLS_DESC_CALL:
7746 case BFD_RELOC_X86_64_TLSGD:
7747 case BFD_RELOC_X86_64_TLSLD:
7748 case BFD_RELOC_X86_64_DTPOFF32:
7749 case BFD_RELOC_X86_64_DTPOFF64:
7750 case BFD_RELOC_X86_64_GOTTPOFF:
7751 case BFD_RELOC_X86_64_TPOFF32:
7752 case BFD_RELOC_X86_64_TPOFF64:
7753 case BFD_RELOC_X86_64_GOTOFF64:
7754 case BFD_RELOC_X86_64_GOTPC32:
7755 case BFD_RELOC_X86_64_GOT64:
7756 case BFD_RELOC_X86_64_GOTPCREL64:
7757 case BFD_RELOC_X86_64_GOTPC64:
7758 case BFD_RELOC_X86_64_GOTPLT64:
7759 case BFD_RELOC_X86_64_PLTOFF64:
7760 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7761 case BFD_RELOC_X86_64_TLSDESC_CALL:
7763 case BFD_RELOC_VTABLE_ENTRY:
7764 case BFD_RELOC_VTABLE_INHERIT:
7766 case BFD_RELOC_32_SECREL:
7768 code = fixp->fx_r_type;
7770 case BFD_RELOC_X86_64_32S:
7771 if (!fixp->fx_pcrel)
7773 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7774 code = fixp->fx_r_type;
7780 switch (fixp->fx_size)
7783 as_bad_where (fixp->fx_file, fixp->fx_line,
7784 _("can not do %d byte pc-relative relocation"),
7786 code = BFD_RELOC_32_PCREL;
7788 case 1: code = BFD_RELOC_8_PCREL; break;
7789 case 2: code = BFD_RELOC_16_PCREL; break;
7790 case 4: code = BFD_RELOC_32_PCREL; break;
7792 case 8: code = BFD_RELOC_64_PCREL; break;
7798 switch (fixp->fx_size)
7801 as_bad_where (fixp->fx_file, fixp->fx_line,
7802 _("can not do %d byte relocation"),
7804 code = BFD_RELOC_32;
7806 case 1: code = BFD_RELOC_8; break;
7807 case 2: code = BFD_RELOC_16; break;
7808 case 4: code = BFD_RELOC_32; break;
7810 case 8: code = BFD_RELOC_64; break;
7817 if ((code == BFD_RELOC_32
7818 || code == BFD_RELOC_32_PCREL
7819 || code == BFD_RELOC_X86_64_32S)
7821 && fixp->fx_addsy == GOT_symbol)
7824 code = BFD_RELOC_386_GOTPC;
7826 code = BFD_RELOC_X86_64_GOTPC32;
7828 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7830 && fixp->fx_addsy == GOT_symbol)
7832 code = BFD_RELOC_X86_64_GOTPC64;
7835 rel = (arelent *) xmalloc (sizeof (arelent));
7836 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7837 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
7839 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
7841 if (!use_rela_relocations)
7843 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7844 vtable entry to be used in the relocation's section offset. */
7845 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7846 rel->address = fixp->fx_offset;
7850 /* Use the rela in 64bit mode. */
7853 if (!fixp->fx_pcrel)
7854 rel->addend = fixp->fx_offset;
7858 case BFD_RELOC_X86_64_PLT32:
7859 case BFD_RELOC_X86_64_GOT32:
7860 case BFD_RELOC_X86_64_GOTPCREL:
7861 case BFD_RELOC_X86_64_TLSGD:
7862 case BFD_RELOC_X86_64_TLSLD:
7863 case BFD_RELOC_X86_64_GOTTPOFF:
7864 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7865 case BFD_RELOC_X86_64_TLSDESC_CALL:
7866 rel->addend = fixp->fx_offset - fixp->fx_size;
7869 rel->addend = (section->vma
7871 + fixp->fx_addnumber
7872 + md_pcrel_from (fixp));
7877 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7878 if (rel->howto == NULL)
7880 as_bad_where (fixp->fx_file, fixp->fx_line,
7881 _("cannot represent relocation type %s"),
7882 bfd_get_reloc_code_name (code));
7883 /* Set howto to a garbage value so that we can keep going. */
7884 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7885 assert (rel->howto != NULL);
7892 /* Parse operands using Intel syntax. This implements a recursive descent
7893 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7896 FIXME: We do not recognize the full operand grammar defined in the MASM
7897 documentation. In particular, all the structure/union and
7898 high-level macro operands are missing.
7900 Uppercase words are terminals, lower case words are non-terminals.
7901 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7902 bars '|' denote choices. Most grammar productions are implemented in
7903 functions called 'intel_<production>'.
7905 Initial production is 'expr'.
7911 binOp & | AND | \| | OR | ^ | XOR
7913 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7915 constant digits [[ radixOverride ]]
7917 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
7955 => expr expr cmpOp e04
7958 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
7959 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
7961 hexdigit a | b | c | d | e | f
7962 | A | B | C | D | E | F
7968 mulOp * | / | % | MOD | << | SHL | >> | SHR
7972 register specialRegister
7976 segmentRegister CS | DS | ES | FS | GS | SS
7978 specialRegister CR0 | CR2 | CR3 | CR4
7979 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
7980 | TR3 | TR4 | TR5 | TR6 | TR7
7982 We simplify the grammar in obvious places (e.g., register parsing is
7983 done by calling parse_register) and eliminate immediate left recursion
7984 to implement a recursive-descent parser.
7988 expr' cmpOp e04 expr'
8039 /* Parsing structure for the intel syntax parser. Used to implement the
8040 semantic actions for the operand grammar. */
8041 struct intel_parser_s
8043 char *op_string; /* The string being parsed. */
8044 int got_a_float; /* Whether the operand is a float. */
8045 int op_modifier; /* Operand modifier. */
8046 int is_mem; /* 1 if operand is memory reference. */
8047 int in_offset; /* >=1 if parsing operand of offset. */
8048 int in_bracket; /* >=1 if parsing operand in brackets. */
8049 const reg_entry *reg; /* Last register reference found. */
8050 char *disp; /* Displacement string being built. */
8051 char *next_operand; /* Resume point when splitting operands. */
8054 static struct intel_parser_s intel_parser;
8056 /* Token structure for parsing intel syntax. */
8059 int code; /* Token code. */
8060 const reg_entry *reg; /* Register entry for register tokens. */
8061 char *str; /* String representation. */
8064 static struct intel_token cur_token, prev_token;
8066 /* Token codes for the intel parser. Since T_SHORT is already used
8067 by COFF, undefine it first to prevent a warning. */
8086 /* Prototypes for intel parser functions. */
8087 static int intel_match_token (int);
8088 static void intel_putback_token (void);
8089 static void intel_get_token (void);
8090 static int intel_expr (void);
8091 static int intel_e04 (void);
8092 static int intel_e05 (void);
8093 static int intel_e06 (void);
8094 static int intel_e09 (void);
8095 static int intel_e10 (void);
8096 static int intel_e11 (void);
8099 i386_intel_operand (char *operand_string, int got_a_float)
8104 p = intel_parser.op_string = xstrdup (operand_string);
8105 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8109 /* Initialize token holders. */
8110 cur_token.code = prev_token.code = T_NIL;
8111 cur_token.reg = prev_token.reg = NULL;
8112 cur_token.str = prev_token.str = NULL;
8114 /* Initialize parser structure. */
8115 intel_parser.got_a_float = got_a_float;
8116 intel_parser.op_modifier = 0;
8117 intel_parser.is_mem = 0;
8118 intel_parser.in_offset = 0;
8119 intel_parser.in_bracket = 0;
8120 intel_parser.reg = NULL;
8121 intel_parser.disp[0] = '\0';
8122 intel_parser.next_operand = NULL;
8124 /* Read the first token and start the parser. */
8126 ret = intel_expr ();
8131 if (cur_token.code != T_NIL)
8133 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8134 current_templates->start->name, cur_token.str);
8137 /* If we found a memory reference, hand it over to i386_displacement
8138 to fill in the rest of the operand fields. */
8139 else if (intel_parser.is_mem)
8141 if ((i.mem_operands == 1
8142 && !current_templates->start->opcode_modifier.isstring)
8143 || i.mem_operands == 2)
8145 as_bad (_("too many memory references for '%s'"),
8146 current_templates->start->name);
8151 char *s = intel_parser.disp;
8152 i.types[this_operand].bitfield.mem = 1;
8155 if (!quiet_warnings && intel_parser.is_mem < 0)
8156 /* See the comments in intel_bracket_expr. */
8157 as_warn (_("Treating `%s' as memory reference"), operand_string);
8159 /* Add the displacement expression. */
8161 ret = i386_displacement (s, s + strlen (s));
8164 /* Swap base and index in 16-bit memory operands like
8165 [si+bx]. Since i386_index_check is also used in AT&T
8166 mode we have to do that here. */
8169 && i.base_reg->reg_type.bitfield.reg16
8170 && i.index_reg->reg_type.bitfield.reg16
8171 && i.base_reg->reg_num >= 6
8172 && i.index_reg->reg_num < 6)
8174 const reg_entry *base = i.index_reg;
8176 i.index_reg = i.base_reg;
8179 ret = i386_index_check (operand_string);
8184 /* Constant and OFFSET expressions are handled by i386_immediate. */
8185 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8186 || intel_parser.reg == NULL)
8188 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8190 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8191 as_warn (_("Segment override ignored"));
8192 i.seg[i.mem_operands] = NULL;
8194 ret = i386_immediate (intel_parser.disp);
8197 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8199 if (!ret || !intel_parser.next_operand)
8201 intel_parser.op_string = intel_parser.next_operand;
8202 this_operand = i.operands++;
8203 i.types[this_operand].bitfield.unspecified = 1;
8207 free (intel_parser.disp);
8212 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8216 expr' cmpOp e04 expr'
8221 /* XXX Implement the comparison operators. */
8222 return intel_e04 ();
8239 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8240 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8242 if (cur_token.code == '+')
8244 else if (cur_token.code == '-')
8245 nregs = NUM_ADDRESS_REGS;
8249 strcat (intel_parser.disp, cur_token.str);
8250 intel_match_token (cur_token.code);
8261 int nregs = ~NUM_ADDRESS_REGS;
8268 if (cur_token.code == '&'
8269 || cur_token.code == '|'
8270 || cur_token.code == '^')
8274 str[0] = cur_token.code;
8276 strcat (intel_parser.disp, str);
8281 intel_match_token (cur_token.code);
8286 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8287 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8298 int nregs = ~NUM_ADDRESS_REGS;
8305 if (cur_token.code == '*'
8306 || cur_token.code == '/'
8307 || cur_token.code == '%')
8311 str[0] = cur_token.code;
8313 strcat (intel_parser.disp, str);
8315 else if (cur_token.code == T_SHL)
8316 strcat (intel_parser.disp, "<<");
8317 else if (cur_token.code == T_SHR)
8318 strcat (intel_parser.disp, ">>");
8322 intel_match_token (cur_token.code);
8327 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8328 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8346 int nregs = ~NUM_ADDRESS_REGS;
8351 /* Don't consume constants here. */
8352 if (cur_token.code == '+' || cur_token.code == '-')
8354 /* Need to look one token ahead - if the next token
8355 is a constant, the current token is its sign. */
8358 intel_match_token (cur_token.code);
8359 next_code = cur_token.code;
8360 intel_putback_token ();
8361 if (next_code == T_CONST)
8365 /* e09 OFFSET e09 */
8366 if (cur_token.code == T_OFFSET)
8369 ++intel_parser.in_offset;
8373 else if (cur_token.code == T_SHORT)
8374 intel_parser.op_modifier |= 1 << T_SHORT;
8377 else if (cur_token.code == '+')
8378 strcat (intel_parser.disp, "+");
8383 else if (cur_token.code == '-' || cur_token.code == '~')
8389 str[0] = cur_token.code;
8391 strcat (intel_parser.disp, str);
8398 intel_match_token (cur_token.code);
8406 /* e09' PTR e10 e09' */
8407 if (cur_token.code == T_PTR)
8411 if (prev_token.code == T_BYTE)
8413 suffix = BYTE_MNEM_SUFFIX;
8414 i.types[this_operand].bitfield.byte = 1;
8417 else if (prev_token.code == T_WORD)
8419 if ((current_templates->start->name[0] == 'l'
8420 && current_templates->start->name[2] == 's'
8421 && current_templates->start->name[3] == 0)
8422 || current_templates->start->base_opcode == 0x62 /* bound */)
8423 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8424 else if (intel_parser.got_a_float == 2) /* "fi..." */
8425 suffix = SHORT_MNEM_SUFFIX;
8427 suffix = WORD_MNEM_SUFFIX;
8428 i.types[this_operand].bitfield.word = 1;
8431 else if (prev_token.code == T_DWORD)
8433 if ((current_templates->start->name[0] == 'l'
8434 && current_templates->start->name[2] == 's'
8435 && current_templates->start->name[3] == 0)
8436 || current_templates->start->base_opcode == 0x62 /* bound */)
8437 suffix = WORD_MNEM_SUFFIX;
8438 else if (flag_code == CODE_16BIT
8439 && (current_templates->start->opcode_modifier.jump
8440 || current_templates->start->opcode_modifier.jumpdword))
8441 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8442 else if (intel_parser.got_a_float == 1) /* "f..." */
8443 suffix = SHORT_MNEM_SUFFIX;
8445 suffix = LONG_MNEM_SUFFIX;
8446 i.types[this_operand].bitfield.dword = 1;
8449 else if (prev_token.code == T_FWORD)
8451 if (current_templates->start->name[0] == 'l'
8452 && current_templates->start->name[2] == 's'
8453 && current_templates->start->name[3] == 0)
8454 suffix = LONG_MNEM_SUFFIX;
8455 else if (!intel_parser.got_a_float)
8457 if (flag_code == CODE_16BIT)
8458 add_prefix (DATA_PREFIX_OPCODE);
8459 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8462 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8463 i.types[this_operand].bitfield.fword = 1;
8466 else if (prev_token.code == T_QWORD)
8468 if (current_templates->start->base_opcode == 0x62 /* bound */
8469 || intel_parser.got_a_float == 1) /* "f..." */
8470 suffix = LONG_MNEM_SUFFIX;
8472 suffix = QWORD_MNEM_SUFFIX;
8473 i.types[this_operand].bitfield.qword = 1;
8476 else if (prev_token.code == T_TBYTE)
8478 if (intel_parser.got_a_float == 1)
8479 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8481 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8484 else if (prev_token.code == T_XMMWORD)
8486 suffix = XMMWORD_MNEM_SUFFIX;
8487 i.types[this_operand].bitfield.xmmword = 1;
8492 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8496 i.types[this_operand].bitfield.unspecified = 0;
8498 /* Operands for jump/call using 'ptr' notation denote absolute
8500 if (current_templates->start->opcode_modifier.jump
8501 || current_templates->start->opcode_modifier.jumpdword)
8502 i.types[this_operand].bitfield.jumpabsolute = 1;
8504 if (current_templates->start->base_opcode == 0x8d /* lea */)
8508 else if (i.suffix != suffix)
8510 as_bad (_("Conflicting operand modifiers"));
8516 /* e09' : e10 e09' */
8517 else if (cur_token.code == ':')
8519 if (prev_token.code != T_REG)
8521 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8522 segment/group identifier (which we don't have), using comma
8523 as the operand separator there is even less consistent, since
8524 there all branches only have a single operand. */
8525 if (this_operand != 0
8526 || intel_parser.in_offset
8527 || intel_parser.in_bracket
8528 || (!current_templates->start->opcode_modifier.jump
8529 && !current_templates->start->opcode_modifier.jumpdword
8530 && !current_templates->start->opcode_modifier.jumpintersegment
8531 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
8532 return intel_match_token (T_NIL);
8533 /* Remember the start of the 2nd operand and terminate 1st
8535 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8536 another expression), but it gets at least the simplest case
8537 (a plain number or symbol on the left side) right. */
8538 intel_parser.next_operand = intel_parser.op_string;
8539 *--intel_parser.op_string = '\0';
8540 return intel_match_token (':');
8548 intel_match_token (cur_token.code);
8554 --intel_parser.in_offset;
8557 if (NUM_ADDRESS_REGS > nregs)
8559 as_bad (_("Invalid operand to `OFFSET'"));
8562 intel_parser.op_modifier |= 1 << T_OFFSET;
8565 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8566 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8571 intel_bracket_expr (void)
8573 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8574 const char *start = intel_parser.op_string;
8577 if (i.op[this_operand].regs)
8578 return intel_match_token (T_NIL);
8580 intel_match_token ('[');
8582 /* Mark as a memory operand only if it's not already known to be an
8583 offset expression. If it's an offset expression, we need to keep
8585 if (!intel_parser.in_offset)
8587 ++intel_parser.in_bracket;
8589 /* Operands for jump/call inside brackets denote absolute addresses. */
8590 if (current_templates->start->opcode_modifier.jump
8591 || current_templates->start->opcode_modifier.jumpdword)
8592 i.types[this_operand].bitfield.jumpabsolute = 1;
8594 /* Unfortunately gas always diverged from MASM in a respect that can't
8595 be easily fixed without risking to break code sequences likely to be
8596 encountered (the testsuite even check for this): MASM doesn't consider
8597 an expression inside brackets unconditionally as a memory reference.
8598 When that is e.g. a constant, an offset expression, or the sum of the
8599 two, this is still taken as a constant load. gas, however, always
8600 treated these as memory references. As a compromise, we'll try to make
8601 offset expressions inside brackets work the MASM way (since that's
8602 less likely to be found in real world code), but make constants alone
8603 continue to work the traditional gas way. In either case, issue a
8605 intel_parser.op_modifier &= ~was_offset;
8608 strcat (intel_parser.disp, "[");
8610 /* Add a '+' to the displacement string if necessary. */
8611 if (*intel_parser.disp != '\0'
8612 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8613 strcat (intel_parser.disp, "+");
8616 && (len = intel_parser.op_string - start - 1,
8617 intel_match_token (']')))
8619 /* Preserve brackets when the operand is an offset expression. */
8620 if (intel_parser.in_offset)
8621 strcat (intel_parser.disp, "]");
8624 --intel_parser.in_bracket;
8625 if (i.base_reg || i.index_reg)
8626 intel_parser.is_mem = 1;
8627 if (!intel_parser.is_mem)
8629 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8630 /* Defer the warning until all of the operand was parsed. */
8631 intel_parser.is_mem = -1;
8632 else if (!quiet_warnings)
8633 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8634 len, start, len, start);
8637 intel_parser.op_modifier |= was_offset;
8654 while (cur_token.code == '[')
8656 if (!intel_bracket_expr ())
8681 switch (cur_token.code)
8685 intel_match_token ('(');
8686 strcat (intel_parser.disp, "(");
8688 if (intel_expr () && intel_match_token (')'))
8690 strcat (intel_parser.disp, ")");
8697 return intel_bracket_expr ();
8702 strcat (intel_parser.disp, cur_token.str);
8703 intel_match_token (cur_token.code);
8705 /* Mark as a memory operand only if it's not already known to be an
8706 offset expression. */
8707 if (!intel_parser.in_offset)
8708 intel_parser.is_mem = 1;
8715 const reg_entry *reg = intel_parser.reg = cur_token.reg;
8717 intel_match_token (T_REG);
8719 /* Check for segment change. */
8720 if (cur_token.code == ':')
8722 if (!reg->reg_type.bitfield.sreg2
8723 && !reg->reg_type.bitfield.sreg3)
8725 as_bad (_("`%s' is not a valid segment register"),
8729 else if (i.mem_operands >= 2)
8730 as_warn (_("Segment override ignored"));
8731 else if (i.seg[i.mem_operands])
8732 as_warn (_("Extra segment override ignored"));
8735 if (!intel_parser.in_offset)
8736 intel_parser.is_mem = 1;
8737 switch (reg->reg_num)
8740 i.seg[i.mem_operands] = &es;
8743 i.seg[i.mem_operands] = &cs;
8746 i.seg[i.mem_operands] = &ss;
8749 i.seg[i.mem_operands] = &ds;
8752 i.seg[i.mem_operands] = &fs;
8755 i.seg[i.mem_operands] = &gs;
8761 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
8763 as_bad (_("cannot use `FLAT' here"));
8767 /* Not a segment register. Check for register scaling. */
8768 else if (cur_token.code == '*')
8770 if (!intel_parser.in_bracket)
8772 as_bad (_("Register scaling only allowed in memory operands"));
8776 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
8777 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8778 else if (i.index_reg)
8779 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
8781 /* What follows must be a valid scale. */
8782 intel_match_token ('*');
8784 i.types[this_operand].bitfield.baseindex = 1;
8786 /* Set the scale after setting the register (otherwise,
8787 i386_scale will complain) */
8788 if (cur_token.code == '+' || cur_token.code == '-')
8790 char *str, sign = cur_token.code;
8791 intel_match_token (cur_token.code);
8792 if (cur_token.code != T_CONST)
8794 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8798 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8799 strcpy (str + 1, cur_token.str);
8801 if (!i386_scale (str))
8805 else if (!i386_scale (cur_token.str))
8807 intel_match_token (cur_token.code);
8810 /* No scaling. If this is a memory operand, the register is either a
8811 base register (first occurrence) or an index register (second
8813 else if (intel_parser.in_bracket)
8818 else if (!i.index_reg)
8822 as_bad (_("Too many register references in memory operand"));
8826 i.types[this_operand].bitfield.baseindex = 1;
8829 /* It's neither base nor index. */
8830 else if (!intel_parser.in_offset && !intel_parser.is_mem)
8832 i386_operand_type temp = reg->reg_type;
8833 temp.bitfield.baseindex = 0;
8834 i.types[this_operand] = operand_type_or (i.types[this_operand],
8836 i.types[this_operand].bitfield.unspecified = 0;
8837 i.op[this_operand].regs = reg;
8842 as_bad (_("Invalid use of register"));
8846 /* Since registers are not part of the displacement string (except
8847 when we're parsing offset operands), we may need to remove any
8848 preceding '+' from the displacement string. */
8849 if (*intel_parser.disp != '\0'
8850 && !intel_parser.in_offset)
8852 char *s = intel_parser.disp;
8853 s += strlen (s) - 1;
8876 intel_match_token (cur_token.code);
8878 if (cur_token.code == T_PTR)
8881 /* It must have been an identifier. */
8882 intel_putback_token ();
8883 cur_token.code = T_ID;
8889 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
8893 /* The identifier represents a memory reference only if it's not
8894 preceded by an offset modifier and if it's not an equate. */
8895 symbolP = symbol_find(cur_token.str);
8896 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8897 intel_parser.is_mem = 1;
8905 char *save_str, sign = 0;
8907 /* Allow constants that start with `+' or `-'. */
8908 if (cur_token.code == '-' || cur_token.code == '+')
8910 sign = cur_token.code;
8911 intel_match_token (cur_token.code);
8912 if (cur_token.code != T_CONST)
8914 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8920 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8921 strcpy (save_str + !!sign, cur_token.str);
8925 /* Get the next token to check for register scaling. */
8926 intel_match_token (cur_token.code);
8928 /* Check if this constant is a scaling factor for an
8930 if (cur_token.code == '*')
8932 if (intel_match_token ('*') && cur_token.code == T_REG)
8934 const reg_entry *reg = cur_token.reg;
8936 if (!intel_parser.in_bracket)
8938 as_bad (_("Register scaling only allowed "
8939 "in memory operands"));
8943 /* Disallow things like [1*si].
8944 sp and esp are invalid as index. */
8945 if (reg->reg_type.bitfield.reg16)
8946 reg = i386_regtab + REGNAM_AX + 4;
8947 else if (i.index_reg)
8948 reg = i386_regtab + REGNAM_EAX + 4;
8950 /* The constant is followed by `* reg', so it must be
8953 i.types[this_operand].bitfield.baseindex = 1;
8955 /* Set the scale after setting the register (otherwise,
8956 i386_scale will complain) */
8957 if (!i386_scale (save_str))
8959 intel_match_token (T_REG);
8961 /* Since registers are not part of the displacement
8962 string, we may need to remove any preceding '+' from
8963 the displacement string. */
8964 if (*intel_parser.disp != '\0')
8966 char *s = intel_parser.disp;
8967 s += strlen (s) - 1;
8977 /* The constant was not used for register scaling. Since we have
8978 already consumed the token following `*' we now need to put it
8979 back in the stream. */
8980 intel_putback_token ();
8983 /* Add the constant to the displacement string. */
8984 strcat (intel_parser.disp, save_str);
8991 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8995 /* Match the given token against cur_token. If they match, read the next
8996 token from the operand string. */
8998 intel_match_token (int code)
9000 if (cur_token.code == code)
9007 as_bad (_("Unexpected token `%s'"), cur_token.str);
9012 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9014 intel_get_token (void)
9017 const reg_entry *reg;
9018 struct intel_token new_token;
9020 new_token.code = T_NIL;
9021 new_token.reg = NULL;
9022 new_token.str = NULL;
9024 /* Free the memory allocated to the previous token and move
9025 cur_token to prev_token. */
9027 free (prev_token.str);
9029 prev_token = cur_token;
9031 /* Skip whitespace. */
9032 while (is_space_char (*intel_parser.op_string))
9033 intel_parser.op_string++;
9035 /* Return an empty token if we find nothing else on the line. */
9036 if (*intel_parser.op_string == '\0')
9038 cur_token = new_token;
9042 /* The new token cannot be larger than the remainder of the operand
9044 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
9045 new_token.str[0] = '\0';
9047 if (strchr ("0123456789", *intel_parser.op_string))
9049 char *p = new_token.str;
9050 char *q = intel_parser.op_string;
9051 new_token.code = T_CONST;
9053 /* Allow any kind of identifier char to encompass floating point and
9054 hexadecimal numbers. */
9055 while (is_identifier_char (*q))
9059 /* Recognize special symbol names [0-9][bf]. */
9060 if (strlen (intel_parser.op_string) == 2
9061 && (intel_parser.op_string[1] == 'b'
9062 || intel_parser.op_string[1] == 'f'))
9063 new_token.code = T_ID;
9066 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9068 size_t len = end_op - intel_parser.op_string;
9070 new_token.code = T_REG;
9071 new_token.reg = reg;
9073 memcpy (new_token.str, intel_parser.op_string, len);
9074 new_token.str[len] = '\0';
9077 else if (is_identifier_char (*intel_parser.op_string))
9079 char *p = new_token.str;
9080 char *q = intel_parser.op_string;
9082 /* A '.' or '$' followed by an identifier char is an identifier.
9083 Otherwise, it's operator '.' followed by an expression. */
9084 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9086 new_token.code = '.';
9087 new_token.str[0] = '.';
9088 new_token.str[1] = '\0';
9092 while (is_identifier_char (*q) || *q == '@')
9096 if (strcasecmp (new_token.str, "NOT") == 0)
9097 new_token.code = '~';
9099 else if (strcasecmp (new_token.str, "MOD") == 0)
9100 new_token.code = '%';
9102 else if (strcasecmp (new_token.str, "AND") == 0)
9103 new_token.code = '&';
9105 else if (strcasecmp (new_token.str, "OR") == 0)
9106 new_token.code = '|';
9108 else if (strcasecmp (new_token.str, "XOR") == 0)
9109 new_token.code = '^';
9111 else if (strcasecmp (new_token.str, "SHL") == 0)
9112 new_token.code = T_SHL;
9114 else if (strcasecmp (new_token.str, "SHR") == 0)
9115 new_token.code = T_SHR;
9117 else if (strcasecmp (new_token.str, "BYTE") == 0)
9118 new_token.code = T_BYTE;
9120 else if (strcasecmp (new_token.str, "WORD") == 0)
9121 new_token.code = T_WORD;
9123 else if (strcasecmp (new_token.str, "DWORD") == 0)
9124 new_token.code = T_DWORD;
9126 else if (strcasecmp (new_token.str, "FWORD") == 0)
9127 new_token.code = T_FWORD;
9129 else if (strcasecmp (new_token.str, "QWORD") == 0)
9130 new_token.code = T_QWORD;
9132 else if (strcasecmp (new_token.str, "TBYTE") == 0
9133 /* XXX remove (gcc still uses it) */
9134 || strcasecmp (new_token.str, "XWORD") == 0)
9135 new_token.code = T_TBYTE;
9137 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9138 || strcasecmp (new_token.str, "OWORD") == 0)
9139 new_token.code = T_XMMWORD;
9141 else if (strcasecmp (new_token.str, "PTR") == 0)
9142 new_token.code = T_PTR;
9144 else if (strcasecmp (new_token.str, "SHORT") == 0)
9145 new_token.code = T_SHORT;
9147 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9149 new_token.code = T_OFFSET;
9151 /* ??? This is not mentioned in the MASM grammar but gcc
9152 makes use of it with -mintel-syntax. OFFSET may be
9153 followed by FLAT: */
9154 if (strncasecmp (q, " FLAT:", 6) == 0)
9155 strcat (new_token.str, " FLAT:");
9159 new_token.code = T_ID;
9163 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9165 new_token.code = *intel_parser.op_string;
9166 new_token.str[0] = *intel_parser.op_string;
9167 new_token.str[1] = '\0';
9170 else if (strchr ("<>", *intel_parser.op_string)
9171 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9173 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9174 new_token.str[0] = *intel_parser.op_string;
9175 new_token.str[1] = *intel_parser.op_string;
9176 new_token.str[2] = '\0';
9180 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9182 intel_parser.op_string += strlen (new_token.str);
9183 cur_token = new_token;
9186 /* Put cur_token back into the token stream and make cur_token point to
9189 intel_putback_token (void)
9191 if (cur_token.code != T_NIL)
9193 intel_parser.op_string -= strlen (cur_token.str);
9194 free (cur_token.str);
9196 cur_token = prev_token;
9198 /* Forget prev_token. */
9199 prev_token.code = T_NIL;
9200 prev_token.reg = NULL;
9201 prev_token.str = NULL;
9205 tc_x86_parse_to_dw2regnum (expressionS *exp)
9207 int saved_naked_reg;
9208 char saved_register_dot;
9210 saved_naked_reg = allow_naked_reg;
9211 allow_naked_reg = 1;
9212 saved_register_dot = register_chars['.'];
9213 register_chars['.'] = '.';
9214 allow_pseudo_reg = 1;
9215 expression_and_evaluate (exp);
9216 allow_pseudo_reg = 0;
9217 register_chars['.'] = saved_register_dot;
9218 allow_naked_reg = saved_naked_reg;
9220 if (exp->X_op == O_register && exp->X_add_number >= 0)
9222 if ((addressT) exp->X_add_number < i386_regtab_size)
9224 exp->X_op = O_constant;
9225 exp->X_add_number = i386_regtab[exp->X_add_number]
9226 .dw2_regnum[flag_code >> 1];
9229 exp->X_op = O_illegal;
9234 tc_x86_frame_initial_instructions (void)
9236 static unsigned int sp_regno[2];
9238 if (!sp_regno[flag_code >> 1])
9240 char *saved_input = input_line_pointer;
9241 char sp[][4] = {"esp", "rsp"};
9244 input_line_pointer = sp[flag_code >> 1];
9245 tc_x86_parse_to_dw2regnum (&exp);
9246 assert (exp.X_op == O_constant);
9247 sp_regno[flag_code >> 1] = exp.X_add_number;
9248 input_line_pointer = saved_input;
9251 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9252 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9256 i386_elf_section_type (const char *str, size_t len)
9258 if (flag_code == CODE_64BIT
9259 && len == sizeof ("unwind") - 1
9260 && strncmp (str, "unwind", 6) == 0)
9261 return SHT_X86_64_UNWIND;
9268 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9272 expr.X_op = O_secrel;
9273 expr.X_add_symbol = symbol;
9274 expr.X_add_number = 0;
9275 emit_expr (&expr, size);
9279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9280 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9283 x86_64_section_letter (int letter, char **ptr_msg)
9285 if (flag_code == CODE_64BIT)
9288 return SHF_X86_64_LARGE;
9290 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
9293 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
9298 x86_64_section_word (char *str, size_t len)
9300 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
9301 return SHF_X86_64_LARGE;
9307 handle_large_common (int small ATTRIBUTE_UNUSED)
9309 if (flag_code != CODE_64BIT)
9311 s_comm_internal (0, elf_common_parse);
9312 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9316 static segT lbss_section;
9317 asection *saved_com_section_ptr = elf_com_section_ptr;
9318 asection *saved_bss_section = bss_section;
9320 if (lbss_section == NULL)
9322 flagword applicable;
9324 subsegT subseg = now_subseg;
9326 /* The .lbss section is for local .largecomm symbols. */
9327 lbss_section = subseg_new (".lbss", 0);
9328 applicable = bfd_applicable_section_flags (stdoutput);
9329 bfd_set_section_flags (stdoutput, lbss_section,
9330 applicable & SEC_ALLOC);
9331 seg_info (lbss_section)->bss = 1;
9333 subseg_set (seg, subseg);
9336 elf_com_section_ptr = &_bfd_elf_large_com_section;
9337 bss_section = lbss_section;
9339 s_comm_internal (0, elf_common_parse);
9341 elf_com_section_ptr = saved_com_section_ptr;
9342 bss_section = saved_bss_section;
9345 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */