1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
200 static const char *default_arch = DEFAULT_ARCH;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry *mask;
224 unsigned int zeroing;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes[4];
253 /* Destination or source register specifier. */
254 const reg_entry *register_specifier;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry *regs;
269 operand_size_mismatch,
270 operand_type_mismatch,
271 register_type_mismatch,
272 number_of_operands_mismatch,
273 invalid_instruction_suffix,
275 unsupported_with_intel_mnemonic,
278 invalid_vsib_address,
279 invalid_vector_register_set,
280 unsupported_vector_index_register,
281 unsupported_broadcast,
284 mask_not_on_destination,
287 rc_sae_operand_not_last_imm,
288 invalid_register_operand,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types[MAX_OPERANDS];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op[MAX_OPERANDS];
316 /* Flags for operands. */
317 unsigned int flags[MAX_OPERANDS];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry *base_reg;
327 const reg_entry *index_reg;
328 unsigned int log2_scale_factor;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry *seg[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes;
340 unsigned char prefix[MAX_PREFIXES];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation *mask;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation *rounding;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation *broadcast;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default = 0,
382 /* Prefer 8bit or 32bit displacement in encoding. */
385 disp_encoding_default = 0,
390 /* Prefer the REX byte in encoding. */
391 bfd_boolean rex_encoding;
393 /* Disable instruction size optimization. */
394 bfd_boolean no_optimize;
396 /* How to encode vector instructions. */
399 vex_encoding_default = 0,
406 const char *rep_prefix;
409 const char *hle_prefix;
411 /* Have BND prefix. */
412 const char *bnd_prefix;
414 /* Have NOTRACK prefix. */
415 const char *notrack_prefix;
418 enum i386_error error;
421 typedef struct _i386_insn i386_insn;
423 /* Link RC type with corresponding string, that'll be looked for in
432 static const struct RC_name RC_NamesTable[] =
434 { rne, STRING_COMMA_LEN ("rn-sae") },
435 { rd, STRING_COMMA_LEN ("rd-sae") },
436 { ru, STRING_COMMA_LEN ("ru-sae") },
437 { rz, STRING_COMMA_LEN ("rz-sae") },
438 { saeonly, STRING_COMMA_LEN ("sae") },
441 /* List of chars besides those in app.c:symbol_chars that can start an
442 operand. Used to prevent the scrubber eating vital white-space. */
443 const char extra_symbol_chars[] = "*%-([{}"
452 #if (defined (TE_I386AIX) \
453 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
454 && !defined (TE_GNU) \
455 && !defined (TE_LINUX) \
456 && !defined (TE_NACL) \
457 && !defined (TE_FreeBSD) \
458 && !defined (TE_DragonFly) \
459 && !defined (TE_NetBSD)))
460 /* This array holds the chars that always start a comment. If the
461 pre-processor is disabled, these aren't very useful. The option
462 --divide will remove '/' from this list. */
463 const char *i386_comment_chars = "#/";
464 #define SVR4_COMMENT_CHARS 1
465 #define PREFIX_SEPARATOR '\\'
468 const char *i386_comment_chars = "#";
469 #define PREFIX_SEPARATOR '/'
472 /* This array holds the chars that only start a comment at the beginning of
473 a line. If the line seems to have the form '# 123 filename'
474 .line and .file directives will appear in the pre-processed output.
475 Note that input_file.c hand checks for '#' at the beginning of the
476 first line of the input file. This is because the compiler outputs
477 #NO_APP at the beginning of its output.
478 Also note that comments started like this one will always work if
479 '/' isn't otherwise defined. */
480 const char line_comment_chars[] = "#/";
482 const char line_separator_chars[] = ";";
484 /* Chars that can be used to separate mant from exp in floating point
486 const char EXP_CHARS[] = "eE";
488 /* Chars that mean this number is a floating point constant
491 const char FLT_CHARS[] = "fFdDxX";
493 /* Tables for lexical analysis. */
494 static char mnemonic_chars[256];
495 static char register_chars[256];
496 static char operand_chars[256];
497 static char identifier_chars[256];
498 static char digit_chars[256];
500 /* Lexical macros. */
501 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
502 #define is_operand_char(x) (operand_chars[(unsigned char) x])
503 #define is_register_char(x) (register_chars[(unsigned char) x])
504 #define is_space_char(x) ((x) == ' ')
505 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
506 #define is_digit_char(x) (digit_chars[(unsigned char) x])
508 /* All non-digit non-letter characters that may occur in an operand. */
509 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
511 /* md_assemble() always leaves the strings it's passed unaltered. To
512 effect this we maintain a stack of saved characters that we've smashed
513 with '\0's (indicating end of strings for various sub-fields of the
514 assembler instruction). */
515 static char save_stack[32];
516 static char *save_stack_p;
517 #define END_STRING_AND_SAVE(s) \
518 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
519 #define RESTORE_END_STRING(s) \
520 do { *(s) = *--save_stack_p; } while (0)
522 /* The instruction we're assembling. */
525 /* Possible templates for current insn. */
526 static const templates *current_templates;
528 /* Per instruction expressionS buffers: max displacements & immediates. */
529 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
530 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
532 /* Current operand we are working on. */
533 static int this_operand = -1;
535 /* We support four different modes. FLAG_CODE variable is used to distinguish
543 static enum flag_code flag_code;
544 static unsigned int object_64bit;
545 static unsigned int disallow_64bit_reloc;
546 static int use_rela_relocations = 0;
548 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
549 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
550 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
552 /* The ELF ABI to use. */
560 static enum x86_elf_abi x86_elf_abi = I386_ABI;
563 #if defined (TE_PE) || defined (TE_PEP)
564 /* Use big object file format. */
565 static int use_big_obj = 0;
568 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
569 /* 1 if generating code for a shared library. */
570 static int shared = 0;
573 /* 1 for intel syntax,
575 static int intel_syntax = 0;
577 /* 1 for Intel64 ISA,
581 /* 1 for intel mnemonic,
582 0 if att mnemonic. */
583 static int intel_mnemonic = !SYSV386_COMPAT;
585 /* 1 if pseudo registers are permitted. */
586 static int allow_pseudo_reg = 0;
588 /* 1 if register prefix % not required. */
589 static int allow_naked_reg = 0;
591 /* 1 if the assembler should add BND prefix for all control-transferring
592 instructions supporting it, even if this prefix wasn't specified
594 static int add_bnd_prefix = 0;
596 /* 1 if pseudo index register, eiz/riz, is allowed . */
597 static int allow_index_reg = 0;
599 /* 1 if the assembler should ignore LOCK prefix, even if it was
600 specified explicitly. */
601 static int omit_lock_prefix = 0;
603 /* 1 if the assembler should encode lfence, mfence, and sfence as
604 "lock addl $0, (%{re}sp)". */
605 static int avoid_fence = 0;
607 /* 1 if the assembler should generate relax relocations. */
609 static int generate_relax_relocations
610 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
612 static enum check_kind
618 sse_check, operand_check = check_warning;
621 1. Clear the REX_W bit with register operand if possible.
622 2. Above plus use 128bit vector instruction to clear the full vector
625 static int optimize = 0;
628 1. Clear the REX_W bit with register operand if possible.
629 2. Above plus use 128bit vector instruction to clear the full vector
631 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
634 static int optimize_for_space = 0;
636 /* Register prefix used for error message. */
637 static const char *register_prefix = "%";
639 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
640 leave, push, and pop instructions so that gcc has the same stack
641 frame as in 32 bit mode. */
642 static char stackop_size = '\0';
644 /* Non-zero to optimize code alignment. */
645 int optimize_align_code = 1;
647 /* Non-zero to quieten some warnings. */
648 static int quiet_warnings = 0;
651 static const char *cpu_arch_name = NULL;
652 static char *cpu_sub_arch_name = NULL;
654 /* CPU feature flags. */
655 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
657 /* If we have selected a cpu we are generating instructions for. */
658 static int cpu_arch_tune_set = 0;
660 /* Cpu we are generating instructions for. */
661 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
663 /* CPU feature flags of cpu we are generating instructions for. */
664 static i386_cpu_flags cpu_arch_tune_flags;
666 /* CPU instruction set architecture used. */
667 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
669 /* CPU feature flags of instruction set architecture used. */
670 i386_cpu_flags cpu_arch_isa_flags;
672 /* If set, conditional jumps are not automatically promoted to handle
673 larger than a byte offset. */
674 static unsigned int no_cond_jump_promotion = 0;
676 /* Encode SSE instructions with VEX prefix. */
677 static unsigned int sse2avx;
679 /* Encode scalar AVX instructions with specific vector length. */
686 /* Encode scalar EVEX LIG instructions with specific vector length. */
694 /* Encode EVEX WIG instructions with specific evex.w. */
701 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
702 static enum rc_type evexrcig = rne;
704 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
705 static symbolS *GOT_symbol;
707 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
708 unsigned int x86_dwarf2_return_column;
710 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
711 int x86_cie_data_alignment;
713 /* Interface to relax_segment.
714 There are 3 major relax states for 386 jump insns because the
715 different types of jumps add different sizes to frags when we're
716 figuring out what sort of jump to choose to reach a given label. */
719 #define UNCOND_JUMP 0
721 #define COND_JUMP86 2
726 #define SMALL16 (SMALL | CODE16)
728 #define BIG16 (BIG | CODE16)
732 #define INLINE __inline__
738 #define ENCODE_RELAX_STATE(type, size) \
739 ((relax_substateT) (((type) << 2) | (size)))
740 #define TYPE_FROM_RELAX_STATE(s) \
742 #define DISP_SIZE_FROM_RELAX_STATE(s) \
743 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
745 /* This table is used by relax_frag to promote short jumps to long
746 ones where necessary. SMALL (short) jumps may be promoted to BIG
747 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
748 don't allow a short jump in a 32 bit code segment to be promoted to
749 a 16 bit offset jump because it's slower (requires data size
750 prefix), and doesn't work, unless the destination is in the bottom
751 64k of the code segment (The top 16 bits of eip are zeroed). */
753 const relax_typeS md_relax_table[] =
756 1) most positive reach of this state,
757 2) most negative reach of this state,
758 3) how many bytes this mode will have in the variable part of the frag
759 4) which index into the table to try if we can't fit into this one. */
761 /* UNCOND_JUMP states. */
762 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
763 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
764 /* dword jmp adds 4 bytes to frag:
765 0 extra opcode bytes, 4 displacement bytes. */
767 /* word jmp adds 2 byte2 to frag:
768 0 extra opcode bytes, 2 displacement bytes. */
771 /* COND_JUMP states. */
772 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
773 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
774 /* dword conditionals adds 5 bytes to frag:
775 1 extra opcode byte, 4 displacement bytes. */
777 /* word conditionals add 3 bytes to frag:
778 1 extra opcode byte, 2 displacement bytes. */
781 /* COND_JUMP86 states. */
782 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
783 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
784 /* dword conditionals adds 5 bytes to frag:
785 1 extra opcode byte, 4 displacement bytes. */
787 /* word conditionals add 4 bytes to frag:
788 1 displacement byte and a 3 byte long branch insn. */
792 static const arch_entry cpu_arch[] =
794 /* Do not replace the first two entries - i386_target_format()
795 relies on them being there in this order. */
796 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
797 CPU_GENERIC32_FLAGS, 0 },
798 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
799 CPU_GENERIC64_FLAGS, 0 },
800 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
802 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
804 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
806 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
808 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
810 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
812 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
814 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
816 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
817 CPU_PENTIUMPRO_FLAGS, 0 },
818 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
820 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
822 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
824 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
826 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
827 CPU_NOCONA_FLAGS, 0 },
828 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
830 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
832 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
833 CPU_CORE2_FLAGS, 1 },
834 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
835 CPU_CORE2_FLAGS, 0 },
836 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
837 CPU_COREI7_FLAGS, 0 },
838 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
840 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
842 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
843 CPU_IAMCU_FLAGS, 0 },
844 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
846 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
848 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
849 CPU_ATHLON_FLAGS, 0 },
850 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
852 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
854 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
856 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
857 CPU_AMDFAM10_FLAGS, 0 },
858 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
859 CPU_BDVER1_FLAGS, 0 },
860 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
861 CPU_BDVER2_FLAGS, 0 },
862 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
863 CPU_BDVER3_FLAGS, 0 },
864 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
865 CPU_BDVER4_FLAGS, 0 },
866 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
867 CPU_ZNVER1_FLAGS, 0 },
868 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
869 CPU_ZNVER2_FLAGS, 0 },
870 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
871 CPU_BTVER1_FLAGS, 0 },
872 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
873 CPU_BTVER2_FLAGS, 0 },
874 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
876 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
878 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
882 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
886 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
888 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
890 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
892 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
894 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
895 CPU_SSSE3_FLAGS, 0 },
896 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
897 CPU_SSE4_1_FLAGS, 0 },
898 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
899 CPU_SSE4_2_FLAGS, 0 },
900 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
901 CPU_SSE4_2_FLAGS, 0 },
902 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
904 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
907 CPU_AVX512F_FLAGS, 0 },
908 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
909 CPU_AVX512CD_FLAGS, 0 },
910 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
911 CPU_AVX512ER_FLAGS, 0 },
912 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
913 CPU_AVX512PF_FLAGS, 0 },
914 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
915 CPU_AVX512DQ_FLAGS, 0 },
916 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
917 CPU_AVX512BW_FLAGS, 0 },
918 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
919 CPU_AVX512VL_FLAGS, 0 },
920 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
922 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
923 CPU_VMFUNC_FLAGS, 0 },
924 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
927 CPU_XSAVE_FLAGS, 0 },
928 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
929 CPU_XSAVEOPT_FLAGS, 0 },
930 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
931 CPU_XSAVEC_FLAGS, 0 },
932 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
933 CPU_XSAVES_FLAGS, 0 },
934 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
936 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
937 CPU_PCLMUL_FLAGS, 0 },
938 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
939 CPU_PCLMUL_FLAGS, 1 },
940 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
941 CPU_FSGSBASE_FLAGS, 0 },
942 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
943 CPU_RDRND_FLAGS, 0 },
944 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
950 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
952 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
956 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
957 CPU_MOVBE_FLAGS, 0 },
958 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
963 CPU_LZCNT_FLAGS, 0 },
964 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
969 CPU_INVPCID_FLAGS, 0 },
970 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
971 CPU_CLFLUSH_FLAGS, 0 },
972 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
975 CPU_SYSCALL_FLAGS, 0 },
976 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
977 CPU_RDTSCP_FLAGS, 0 },
978 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
979 CPU_3DNOW_FLAGS, 0 },
980 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
981 CPU_3DNOWA_FLAGS, 0 },
982 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
983 CPU_PADLOCK_FLAGS, 0 },
984 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
986 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
989 CPU_SSE4A_FLAGS, 0 },
990 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
992 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
994 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
998 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
999 CPU_RDSEED_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1001 CPU_PRFCHW_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1003 CPU_SMAP_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1006 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1008 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1009 CPU_CLFLUSHOPT_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1011 CPU_PREFETCHWT1_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1014 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1015 CPU_CLWB_FLAGS, 0 },
1016 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1017 CPU_AVX512IFMA_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1019 CPU_AVX512VBMI_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1021 CPU_AVX512_4FMAPS_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1023 CPU_AVX512_4VNNIW_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1025 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1027 CPU_AVX512_VBMI2_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1029 CPU_AVX512_VNNI_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1031 CPU_AVX512_BITALG_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1033 CPU_CLZERO_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1035 CPU_MWAITX_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1037 CPU_OSPKE_FLAGS, 0 },
1038 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1039 CPU_RDPID_FLAGS, 0 },
1040 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1041 CPU_PTWRITE_FLAGS, 0 },
1042 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1044 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1045 CPU_SHSTK_FLAGS, 0 },
1046 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1047 CPU_GFNI_FLAGS, 0 },
1048 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1049 CPU_VAES_FLAGS, 0 },
1050 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1051 CPU_VPCLMULQDQ_FLAGS, 0 },
1052 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1053 CPU_WBNOINVD_FLAGS, 0 },
1054 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1055 CPU_PCONFIG_FLAGS, 0 },
1056 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1057 CPU_WAITPKG_FLAGS, 0 },
1058 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1059 CPU_CLDEMOTE_FLAGS, 0 },
1060 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1061 CPU_MOVDIRI_FLAGS, 0 },
1062 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1063 CPU_MOVDIR64B_FLAGS, 0 },
1066 static const noarch_entry cpu_noarch[] =
1068 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1069 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1070 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1071 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1072 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1073 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1074 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1075 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1076 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1077 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1078 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1079 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1080 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1081 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1082 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1083 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1084 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1085 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1086 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1087 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1088 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1089 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1090 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1091 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1092 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1093 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1094 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1095 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1096 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1097 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1098 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1099 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1100 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1101 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1102 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1106 /* Like s_lcomm_internal in gas/read.c but the alignment string
1107 is allowed to be optional. */
1110 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1117 && *input_line_pointer == ',')
1119 align = parse_align (needs_align - 1);
1121 if (align == (addressT) -1)
1136 bss_alloc (symbolP, size, align);
1141 pe_lcomm (int needs_align)
1143 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1147 const pseudo_typeS md_pseudo_table[] =
1149 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1150 {"align", s_align_bytes, 0},
1152 {"align", s_align_ptwo, 0},
1154 {"arch", set_cpu_arch, 0},
1158 {"lcomm", pe_lcomm, 1},
1160 {"ffloat", float_cons, 'f'},
1161 {"dfloat", float_cons, 'd'},
1162 {"tfloat", float_cons, 'x'},
1164 {"slong", signed_cons, 4},
1165 {"noopt", s_ignore, 0},
1166 {"optim", s_ignore, 0},
1167 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1168 {"code16", set_code_flag, CODE_16BIT},
1169 {"code32", set_code_flag, CODE_32BIT},
1171 {"code64", set_code_flag, CODE_64BIT},
1173 {"intel_syntax", set_intel_syntax, 1},
1174 {"att_syntax", set_intel_syntax, 0},
1175 {"intel_mnemonic", set_intel_mnemonic, 1},
1176 {"att_mnemonic", set_intel_mnemonic, 0},
1177 {"allow_index_reg", set_allow_index_reg, 1},
1178 {"disallow_index_reg", set_allow_index_reg, 0},
1179 {"sse_check", set_check, 0},
1180 {"operand_check", set_check, 1},
1181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1182 {"largecomm", handle_large_common, 0},
1184 {"file", dwarf2_directive_file, 0},
1185 {"loc", dwarf2_directive_loc, 0},
1186 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1189 {"secrel32", pe_directive_secrel, 0},
1194 /* For interface with expression (). */
1195 extern char *input_line_pointer;
1197 /* Hash table for instruction mnemonic lookup. */
1198 static struct hash_control *op_hash;
1200 /* Hash table for register lookup. */
1201 static struct hash_control *reg_hash;
1203 /* Various efficient no-op patterns for aligning code labels.
1204 Note: Don't try to assemble the instructions in the comments.
1205 0L and 0w are not legal. */
1206 static const unsigned char f32_1[] =
1208 static const unsigned char f32_2[] =
1209 {0x66,0x90}; /* xchg %ax,%ax */
1210 static const unsigned char f32_3[] =
1211 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1212 static const unsigned char f32_4[] =
1213 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1214 static const unsigned char f32_6[] =
1215 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1216 static const unsigned char f32_7[] =
1217 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1218 static const unsigned char f16_3[] =
1219 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1220 static const unsigned char f16_4[] =
1221 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1222 static const unsigned char jump_disp8[] =
1223 {0xeb}; /* jmp disp8 */
1224 static const unsigned char jump32_disp32[] =
1225 {0xe9}; /* jmp disp32 */
1226 static const unsigned char jump16_disp32[] =
1227 {0x66,0xe9}; /* jmp disp32 */
1228 /* 32-bit NOPs patterns. */
1229 static const unsigned char *const f32_patt[] = {
1230 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1232 /* 16-bit NOPs patterns. */
1233 static const unsigned char *const f16_patt[] = {
1234 f32_1, f32_2, f16_3, f16_4
1236 /* nopl (%[re]ax) */
1237 static const unsigned char alt_3[] =
1239 /* nopl 0(%[re]ax) */
1240 static const unsigned char alt_4[] =
1241 {0x0f,0x1f,0x40,0x00};
1242 /* nopl 0(%[re]ax,%[re]ax,1) */
1243 static const unsigned char alt_5[] =
1244 {0x0f,0x1f,0x44,0x00,0x00};
1245 /* nopw 0(%[re]ax,%[re]ax,1) */
1246 static const unsigned char alt_6[] =
1247 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1248 /* nopl 0L(%[re]ax) */
1249 static const unsigned char alt_7[] =
1250 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1251 /* nopl 0L(%[re]ax,%[re]ax,1) */
1252 static const unsigned char alt_8[] =
1253 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1254 /* nopw 0L(%[re]ax,%[re]ax,1) */
1255 static const unsigned char alt_9[] =
1256 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1257 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1258 static const unsigned char alt_10[] =
1259 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1260 /* data16 nopw %cs:0L(%eax,%eax,1) */
1261 static const unsigned char alt_11[] =
1262 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1263 /* 32-bit and 64-bit NOPs patterns. */
1264 static const unsigned char *const alt_patt[] = {
1265 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1266 alt_9, alt_10, alt_11
1269 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1270 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1273 i386_output_nops (char *where, const unsigned char *const *patt,
1274 int count, int max_single_nop_size)
1277 /* Place the longer NOP first. */
1280 const unsigned char *nops = patt[max_single_nop_size - 1];
1282 /* Use the smaller one if the requsted one isn't available. */
1285 max_single_nop_size--;
1286 nops = patt[max_single_nop_size - 1];
1289 last = count % max_single_nop_size;
1292 for (offset = 0; offset < count; offset += max_single_nop_size)
1293 memcpy (where + offset, nops, max_single_nop_size);
1297 nops = patt[last - 1];
1300 /* Use the smaller one plus one-byte NOP if the needed one
1303 nops = patt[last - 1];
1304 memcpy (where + offset, nops, last);
1305 where[offset + last] = *patt[0];
1308 memcpy (where + offset, nops, last);
1313 fits_in_imm7 (offsetT num)
1315 return (num & 0x7f) == num;
1319 fits_in_imm31 (offsetT num)
1321 return (num & 0x7fffffff) == num;
1324 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1325 single NOP instruction LIMIT. */
1328 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1330 const unsigned char *const *patt = NULL;
1331 int max_single_nop_size;
1332 /* Maximum number of NOPs before switching to jump over NOPs. */
1333 int max_number_of_nops;
1335 switch (fragP->fr_type)
1344 /* We need to decide which NOP sequence to use for 32bit and
1345 64bit. When -mtune= is used:
1347 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1348 PROCESSOR_GENERIC32, f32_patt will be used.
1349 2. For the rest, alt_patt will be used.
1351 When -mtune= isn't used, alt_patt will be used if
1352 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1355 When -march= or .arch is used, we can't use anything beyond
1356 cpu_arch_isa_flags. */
1358 if (flag_code == CODE_16BIT)
1361 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1362 /* Limit number of NOPs to 2 in 16-bit mode. */
1363 max_number_of_nops = 2;
1367 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1369 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1370 switch (cpu_arch_tune)
1372 case PROCESSOR_UNKNOWN:
1373 /* We use cpu_arch_isa_flags to check if we SHOULD
1374 optimize with nops. */
1375 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1380 case PROCESSOR_PENTIUM4:
1381 case PROCESSOR_NOCONA:
1382 case PROCESSOR_CORE:
1383 case PROCESSOR_CORE2:
1384 case PROCESSOR_COREI7:
1385 case PROCESSOR_L1OM:
1386 case PROCESSOR_K1OM:
1387 case PROCESSOR_GENERIC64:
1389 case PROCESSOR_ATHLON:
1391 case PROCESSOR_AMDFAM10:
1393 case PROCESSOR_ZNVER:
1397 case PROCESSOR_I386:
1398 case PROCESSOR_I486:
1399 case PROCESSOR_PENTIUM:
1400 case PROCESSOR_PENTIUMPRO:
1401 case PROCESSOR_IAMCU:
1402 case PROCESSOR_GENERIC32:
1409 switch (fragP->tc_frag_data.tune)
1411 case PROCESSOR_UNKNOWN:
1412 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1413 PROCESSOR_UNKNOWN. */
1417 case PROCESSOR_I386:
1418 case PROCESSOR_I486:
1419 case PROCESSOR_PENTIUM:
1420 case PROCESSOR_IAMCU:
1422 case PROCESSOR_ATHLON:
1424 case PROCESSOR_AMDFAM10:
1426 case PROCESSOR_ZNVER:
1428 case PROCESSOR_GENERIC32:
1429 /* We use cpu_arch_isa_flags to check if we CAN optimize
1431 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1436 case PROCESSOR_PENTIUMPRO:
1437 case PROCESSOR_PENTIUM4:
1438 case PROCESSOR_NOCONA:
1439 case PROCESSOR_CORE:
1440 case PROCESSOR_CORE2:
1441 case PROCESSOR_COREI7:
1442 case PROCESSOR_L1OM:
1443 case PROCESSOR_K1OM:
1444 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1449 case PROCESSOR_GENERIC64:
1455 if (patt == f32_patt)
1457 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1458 /* Limit number of NOPs to 2 for older processors. */
1459 max_number_of_nops = 2;
1463 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1464 /* Limit number of NOPs to 7 for newer processors. */
1465 max_number_of_nops = 7;
1470 limit = max_single_nop_size;
1472 if (fragP->fr_type == rs_fill_nop)
1474 /* Output NOPs for .nop directive. */
1475 if (limit > max_single_nop_size)
1477 as_bad_where (fragP->fr_file, fragP->fr_line,
1478 _("invalid single nop size: %d "
1479 "(expect within [0, %d])"),
1480 limit, max_single_nop_size);
1485 fragP->fr_var = count;
1487 if ((count / max_single_nop_size) > max_number_of_nops)
1489 /* Generate jump over NOPs. */
1490 offsetT disp = count - 2;
1491 if (fits_in_imm7 (disp))
1493 /* Use "jmp disp8" if possible. */
1495 where[0] = jump_disp8[0];
1501 unsigned int size_of_jump;
1503 if (flag_code == CODE_16BIT)
1505 where[0] = jump16_disp32[0];
1506 where[1] = jump16_disp32[1];
1511 where[0] = jump32_disp32[0];
1515 count -= size_of_jump + 4;
1516 if (!fits_in_imm31 (count))
1518 as_bad_where (fragP->fr_file, fragP->fr_line,
1519 _("jump over nop padding out of range"));
1523 md_number_to_chars (where + size_of_jump, count, 4);
1524 where += size_of_jump + 4;
1528 /* Generate multiple NOPs. */
1529 i386_output_nops (where, patt, count, limit);
1533 operand_type_all_zero (const union i386_operand_type *x)
1535 switch (ARRAY_SIZE(x->array))
1546 return !x->array[0];
1553 operand_type_set (union i386_operand_type *x, unsigned int v)
1555 switch (ARRAY_SIZE(x->array))
1573 operand_type_equal (const union i386_operand_type *x,
1574 const union i386_operand_type *y)
1576 switch (ARRAY_SIZE(x->array))
1579 if (x->array[2] != y->array[2])
1583 if (x->array[1] != y->array[1])
1587 return x->array[0] == y->array[0];
1595 cpu_flags_all_zero (const union i386_cpu_flags *x)
1597 switch (ARRAY_SIZE(x->array))
1612 return !x->array[0];
1619 cpu_flags_equal (const union i386_cpu_flags *x,
1620 const union i386_cpu_flags *y)
1622 switch (ARRAY_SIZE(x->array))
1625 if (x->array[3] != y->array[3])
1629 if (x->array[2] != y->array[2])
1633 if (x->array[1] != y->array[1])
1637 return x->array[0] == y->array[0];
1645 cpu_flags_check_cpu64 (i386_cpu_flags f)
1647 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1648 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1651 static INLINE i386_cpu_flags
1652 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1654 switch (ARRAY_SIZE (x.array))
1657 x.array [3] &= y.array [3];
1660 x.array [2] &= y.array [2];
1663 x.array [1] &= y.array [1];
1666 x.array [0] &= y.array [0];
1674 static INLINE i386_cpu_flags
1675 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1677 switch (ARRAY_SIZE (x.array))
1680 x.array [3] |= y.array [3];
1683 x.array [2] |= y.array [2];
1686 x.array [1] |= y.array [1];
1689 x.array [0] |= y.array [0];
1697 static INLINE i386_cpu_flags
1698 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1700 switch (ARRAY_SIZE (x.array))
1703 x.array [3] &= ~y.array [3];
1706 x.array [2] &= ~y.array [2];
1709 x.array [1] &= ~y.array [1];
1712 x.array [0] &= ~y.array [0];
1720 #define CPU_FLAGS_ARCH_MATCH 0x1
1721 #define CPU_FLAGS_64BIT_MATCH 0x2
1723 #define CPU_FLAGS_PERFECT_MATCH \
1724 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1726 /* Return CPU flags match bits. */
1729 cpu_flags_match (const insn_template *t)
1731 i386_cpu_flags x = t->cpu_flags;
1732 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1734 x.bitfield.cpu64 = 0;
1735 x.bitfield.cpuno64 = 0;
1737 if (cpu_flags_all_zero (&x))
1739 /* This instruction is available on all archs. */
1740 match |= CPU_FLAGS_ARCH_MATCH;
1744 /* This instruction is available only on some archs. */
1745 i386_cpu_flags cpu = cpu_arch_flags;
1747 /* AVX512VL is no standalone feature - match it and then strip it. */
1748 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1750 x.bitfield.cpuavx512vl = 0;
1752 cpu = cpu_flags_and (x, cpu);
1753 if (!cpu_flags_all_zero (&cpu))
1755 if (x.bitfield.cpuavx)
1757 /* We need to check a few extra flags with AVX. */
1758 if (cpu.bitfield.cpuavx
1759 && (!t->opcode_modifier.sse2avx || sse2avx)
1760 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1761 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1762 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1763 match |= CPU_FLAGS_ARCH_MATCH;
1765 else if (x.bitfield.cpuavx512f)
1767 /* We need to check a few extra flags with AVX512F. */
1768 if (cpu.bitfield.cpuavx512f
1769 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1770 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1771 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1772 match |= CPU_FLAGS_ARCH_MATCH;
1775 match |= CPU_FLAGS_ARCH_MATCH;
1781 static INLINE i386_operand_type
1782 operand_type_and (i386_operand_type x, i386_operand_type y)
1784 switch (ARRAY_SIZE (x.array))
1787 x.array [2] &= y.array [2];
1790 x.array [1] &= y.array [1];
1793 x.array [0] &= y.array [0];
1801 static INLINE i386_operand_type
1802 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1804 switch (ARRAY_SIZE (x.array))
1807 x.array [2] &= ~y.array [2];
1810 x.array [1] &= ~y.array [1];
1813 x.array [0] &= ~y.array [0];
1821 static INLINE i386_operand_type
1822 operand_type_or (i386_operand_type x, i386_operand_type y)
1824 switch (ARRAY_SIZE (x.array))
1827 x.array [2] |= y.array [2];
1830 x.array [1] |= y.array [1];
1833 x.array [0] |= y.array [0];
1841 static INLINE i386_operand_type
1842 operand_type_xor (i386_operand_type x, i386_operand_type y)
1844 switch (ARRAY_SIZE (x.array))
1847 x.array [2] ^= y.array [2];
1850 x.array [1] ^= y.array [1];
1853 x.array [0] ^= y.array [0];
1861 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1862 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1863 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1864 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1865 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1866 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1867 static const i386_operand_type anydisp
1868 = OPERAND_TYPE_ANYDISP;
1869 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1870 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1871 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1872 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1873 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1874 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1875 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1876 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1877 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1878 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1879 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1880 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1891 operand_type_check (i386_operand_type t, enum operand_type c)
1896 return t.bitfield.reg;
1899 return (t.bitfield.imm8
1903 || t.bitfield.imm32s
1904 || t.bitfield.imm64);
1907 return (t.bitfield.disp8
1908 || t.bitfield.disp16
1909 || t.bitfield.disp32
1910 || t.bitfield.disp32s
1911 || t.bitfield.disp64);
1914 return (t.bitfield.disp8
1915 || t.bitfield.disp16
1916 || t.bitfield.disp32
1917 || t.bitfield.disp32s
1918 || t.bitfield.disp64
1919 || t.bitfield.baseindex);
1928 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1929 between operand GIVEN and opeand WANTED for instruction template T. */
1932 match_operand_size (const insn_template *t, unsigned int wanted,
1935 return !((i.types[given].bitfield.byte
1936 && !t->operand_types[wanted].bitfield.byte)
1937 || (i.types[given].bitfield.word
1938 && !t->operand_types[wanted].bitfield.word)
1939 || (i.types[given].bitfield.dword
1940 && !t->operand_types[wanted].bitfield.dword)
1941 || (i.types[given].bitfield.qword
1942 && !t->operand_types[wanted].bitfield.qword)
1943 || (i.types[given].bitfield.tbyte
1944 && !t->operand_types[wanted].bitfield.tbyte));
1947 /* Return 1 if there is no conflict in SIMD register between operand
1948 GIVEN and opeand WANTED for instruction template T. */
1951 match_simd_size (const insn_template *t, unsigned int wanted,
1954 return !((i.types[given].bitfield.xmmword
1955 && !t->operand_types[wanted].bitfield.xmmword)
1956 || (i.types[given].bitfield.ymmword
1957 && !t->operand_types[wanted].bitfield.ymmword)
1958 || (i.types[given].bitfield.zmmword
1959 && !t->operand_types[wanted].bitfield.zmmword));
1962 /* Return 1 if there is no conflict in any size between operand GIVEN
1963 and opeand WANTED for instruction template T. */
1966 match_mem_size (const insn_template *t, unsigned int wanted,
1969 return (match_operand_size (t, wanted, given)
1970 && !((i.types[given].bitfield.unspecified
1972 && !t->operand_types[wanted].bitfield.unspecified)
1973 || (i.types[given].bitfield.fword
1974 && !t->operand_types[wanted].bitfield.fword)
1975 /* For scalar opcode templates to allow register and memory
1976 operands at the same time, some special casing is needed
1977 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1978 down-conversion vpmov*. */
1979 || ((t->operand_types[wanted].bitfield.regsimd
1980 && !t->opcode_modifier.broadcast
1981 && (t->operand_types[wanted].bitfield.byte
1982 || t->operand_types[wanted].bitfield.word
1983 || t->operand_types[wanted].bitfield.dword
1984 || t->operand_types[wanted].bitfield.qword))
1985 ? (i.types[given].bitfield.xmmword
1986 || i.types[given].bitfield.ymmword
1987 || i.types[given].bitfield.zmmword)
1988 : !match_simd_size(t, wanted, given))));
1991 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1992 operands for instruction template T, and it has MATCH_REVERSE set if there
1993 is no size conflict on any operands for the template with operands reversed
1994 (and the template allows for reversing in the first place). */
1996 #define MATCH_STRAIGHT 1
1997 #define MATCH_REVERSE 2
1999 static INLINE unsigned int
2000 operand_size_match (const insn_template *t)
2002 unsigned int j, match = MATCH_STRAIGHT;
2004 /* Don't check jump instructions. */
2005 if (t->opcode_modifier.jump
2006 || t->opcode_modifier.jumpbyte
2007 || t->opcode_modifier.jumpdword
2008 || t->opcode_modifier.jumpintersegment)
2011 /* Check memory and accumulator operand size. */
2012 for (j = 0; j < i.operands; j++)
2014 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2015 && t->operand_types[j].bitfield.anysize)
2018 if (t->operand_types[j].bitfield.reg
2019 && !match_operand_size (t, j, j))
2025 if (t->operand_types[j].bitfield.regsimd
2026 && !match_simd_size (t, j, j))
2032 if (t->operand_types[j].bitfield.acc
2033 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2039 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2046 if (!t->opcode_modifier.d)
2050 i.error = operand_size_mismatch;
2054 /* Check reverse. */
2055 gas_assert (i.operands == 2);
2057 for (j = 0; j < 2; j++)
2059 if ((t->operand_types[j].bitfield.reg
2060 || t->operand_types[j].bitfield.acc)
2061 && !match_operand_size (t, j, !j))
2064 if ((i.flags[!j] & Operand_Mem) && !match_mem_size (t, j, !j))
2068 return match | MATCH_REVERSE;
2072 operand_type_match (i386_operand_type overlap,
2073 i386_operand_type given)
2075 i386_operand_type temp = overlap;
2077 temp.bitfield.jumpabsolute = 0;
2078 temp.bitfield.unspecified = 0;
2079 temp.bitfield.byte = 0;
2080 temp.bitfield.word = 0;
2081 temp.bitfield.dword = 0;
2082 temp.bitfield.fword = 0;
2083 temp.bitfield.qword = 0;
2084 temp.bitfield.tbyte = 0;
2085 temp.bitfield.xmmword = 0;
2086 temp.bitfield.ymmword = 0;
2087 temp.bitfield.zmmword = 0;
2088 if (operand_type_all_zero (&temp))
2091 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2092 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2096 i.error = operand_type_mismatch;
2100 /* If given types g0 and g1 are registers they must be of the same type
2101 unless the expected operand type register overlap is null.
2102 Memory operand size of certain SIMD instructions is also being checked
2106 operand_type_register_match (i386_operand_type g0,
2107 i386_operand_type t0,
2108 i386_operand_type g1,
2109 i386_operand_type t1)
2111 if (!g0.bitfield.reg
2112 && !g0.bitfield.regsimd
2113 && (!operand_type_check (g0, anymem)
2114 || g0.bitfield.unspecified
2115 || !t0.bitfield.regsimd))
2118 if (!g1.bitfield.reg
2119 && !g1.bitfield.regsimd
2120 && (!operand_type_check (g1, anymem)
2121 || g1.bitfield.unspecified
2122 || !t1.bitfield.regsimd))
2125 if (g0.bitfield.byte == g1.bitfield.byte
2126 && g0.bitfield.word == g1.bitfield.word
2127 && g0.bitfield.dword == g1.bitfield.dword
2128 && g0.bitfield.qword == g1.bitfield.qword
2129 && g0.bitfield.xmmword == g1.bitfield.xmmword
2130 && g0.bitfield.ymmword == g1.bitfield.ymmword
2131 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2134 if (!(t0.bitfield.byte & t1.bitfield.byte)
2135 && !(t0.bitfield.word & t1.bitfield.word)
2136 && !(t0.bitfield.dword & t1.bitfield.dword)
2137 && !(t0.bitfield.qword & t1.bitfield.qword)
2138 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2139 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2140 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2143 i.error = register_type_mismatch;
2148 static INLINE unsigned int
2149 register_number (const reg_entry *r)
2151 unsigned int nr = r->reg_num;
2153 if (r->reg_flags & RegRex)
2156 if (r->reg_flags & RegVRex)
2162 static INLINE unsigned int
2163 mode_from_disp_size (i386_operand_type t)
2165 if (t.bitfield.disp8)
2167 else if (t.bitfield.disp16
2168 || t.bitfield.disp32
2169 || t.bitfield.disp32s)
2176 fits_in_signed_byte (addressT num)
2178 return num + 0x80 <= 0xff;
2182 fits_in_unsigned_byte (addressT num)
2188 fits_in_unsigned_word (addressT num)
2190 return num <= 0xffff;
2194 fits_in_signed_word (addressT num)
2196 return num + 0x8000 <= 0xffff;
2200 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2205 return num + 0x80000000 <= 0xffffffff;
2207 } /* fits_in_signed_long() */
2210 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2215 return num <= 0xffffffff;
2217 } /* fits_in_unsigned_long() */
2220 fits_in_disp8 (offsetT num)
2222 int shift = i.memshift;
2228 mask = (1 << shift) - 1;
2230 /* Return 0 if NUM isn't properly aligned. */
2234 /* Check if NUM will fit in 8bit after shift. */
2235 return fits_in_signed_byte (num >> shift);
2239 fits_in_imm4 (offsetT num)
2241 return (num & 0xf) == num;
2244 static i386_operand_type
2245 smallest_imm_type (offsetT num)
2247 i386_operand_type t;
2249 operand_type_set (&t, 0);
2250 t.bitfield.imm64 = 1;
2252 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2254 /* This code is disabled on the 486 because all the Imm1 forms
2255 in the opcode table are slower on the i486. They're the
2256 versions with the implicitly specified single-position
2257 displacement, which has another syntax if you really want to
2259 t.bitfield.imm1 = 1;
2260 t.bitfield.imm8 = 1;
2261 t.bitfield.imm8s = 1;
2262 t.bitfield.imm16 = 1;
2263 t.bitfield.imm32 = 1;
2264 t.bitfield.imm32s = 1;
2266 else if (fits_in_signed_byte (num))
2268 t.bitfield.imm8 = 1;
2269 t.bitfield.imm8s = 1;
2270 t.bitfield.imm16 = 1;
2271 t.bitfield.imm32 = 1;
2272 t.bitfield.imm32s = 1;
2274 else if (fits_in_unsigned_byte (num))
2276 t.bitfield.imm8 = 1;
2277 t.bitfield.imm16 = 1;
2278 t.bitfield.imm32 = 1;
2279 t.bitfield.imm32s = 1;
2281 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2283 t.bitfield.imm16 = 1;
2284 t.bitfield.imm32 = 1;
2285 t.bitfield.imm32s = 1;
2287 else if (fits_in_signed_long (num))
2289 t.bitfield.imm32 = 1;
2290 t.bitfield.imm32s = 1;
2292 else if (fits_in_unsigned_long (num))
2293 t.bitfield.imm32 = 1;
2299 offset_in_range (offsetT val, int size)
2305 case 1: mask = ((addressT) 1 << 8) - 1; break;
2306 case 2: mask = ((addressT) 1 << 16) - 1; break;
2307 case 4: mask = ((addressT) 2 << 31) - 1; break;
2309 case 8: mask = ((addressT) 2 << 63) - 1; break;
2315 /* If BFD64, sign extend val for 32bit address mode. */
2316 if (flag_code != CODE_64BIT
2317 || i.prefix[ADDR_PREFIX])
2318 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2319 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2322 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2324 char buf1[40], buf2[40];
2326 sprint_value (buf1, val);
2327 sprint_value (buf2, val & mask);
2328 as_warn (_("%s shortened to %s"), buf1, buf2);
2343 a. PREFIX_EXIST if attempting to add a prefix where one from the
2344 same class already exists.
2345 b. PREFIX_LOCK if lock prefix is added.
2346 c. PREFIX_REP if rep/repne prefix is added.
2347 d. PREFIX_DS if ds prefix is added.
2348 e. PREFIX_OTHER if other prefix is added.
2351 static enum PREFIX_GROUP
2352 add_prefix (unsigned int prefix)
2354 enum PREFIX_GROUP ret = PREFIX_OTHER;
2357 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2358 && flag_code == CODE_64BIT)
2360 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2361 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2362 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2363 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2374 case DS_PREFIX_OPCODE:
2377 case CS_PREFIX_OPCODE:
2378 case ES_PREFIX_OPCODE:
2379 case FS_PREFIX_OPCODE:
2380 case GS_PREFIX_OPCODE:
2381 case SS_PREFIX_OPCODE:
2385 case REPNE_PREFIX_OPCODE:
2386 case REPE_PREFIX_OPCODE:
2391 case LOCK_PREFIX_OPCODE:
2400 case ADDR_PREFIX_OPCODE:
2404 case DATA_PREFIX_OPCODE:
2408 if (i.prefix[q] != 0)
2416 i.prefix[q] |= prefix;
2419 as_bad (_("same type of prefix used twice"));
2425 update_code_flag (int value, int check)
2427 PRINTF_LIKE ((*as_error));
2429 flag_code = (enum flag_code) value;
2430 if (flag_code == CODE_64BIT)
2432 cpu_arch_flags.bitfield.cpu64 = 1;
2433 cpu_arch_flags.bitfield.cpuno64 = 0;
2437 cpu_arch_flags.bitfield.cpu64 = 0;
2438 cpu_arch_flags.bitfield.cpuno64 = 1;
2440 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2443 as_error = as_fatal;
2446 (*as_error) (_("64bit mode not supported on `%s'."),
2447 cpu_arch_name ? cpu_arch_name : default_arch);
2449 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2452 as_error = as_fatal;
2455 (*as_error) (_("32bit mode not supported on `%s'."),
2456 cpu_arch_name ? cpu_arch_name : default_arch);
2458 stackop_size = '\0';
2462 set_code_flag (int value)
2464 update_code_flag (value, 0);
2468 set_16bit_gcc_code_flag (int new_code_flag)
2470 flag_code = (enum flag_code) new_code_flag;
2471 if (flag_code != CODE_16BIT)
2473 cpu_arch_flags.bitfield.cpu64 = 0;
2474 cpu_arch_flags.bitfield.cpuno64 = 1;
2475 stackop_size = LONG_MNEM_SUFFIX;
2479 set_intel_syntax (int syntax_flag)
2481 /* Find out if register prefixing is specified. */
2482 int ask_naked_reg = 0;
2485 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2488 int e = get_symbol_name (&string);
2490 if (strcmp (string, "prefix") == 0)
2492 else if (strcmp (string, "noprefix") == 0)
2495 as_bad (_("bad argument to syntax directive."));
2496 (void) restore_line_pointer (e);
2498 demand_empty_rest_of_line ();
2500 intel_syntax = syntax_flag;
2502 if (ask_naked_reg == 0)
2503 allow_naked_reg = (intel_syntax
2504 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2506 allow_naked_reg = (ask_naked_reg < 0);
2508 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2510 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2511 identifier_chars['$'] = intel_syntax ? '$' : 0;
2512 register_prefix = allow_naked_reg ? "" : "%";
2516 set_intel_mnemonic (int mnemonic_flag)
2518 intel_mnemonic = mnemonic_flag;
2522 set_allow_index_reg (int flag)
2524 allow_index_reg = flag;
2528 set_check (int what)
2530 enum check_kind *kind;
2535 kind = &operand_check;
2546 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2549 int e = get_symbol_name (&string);
2551 if (strcmp (string, "none") == 0)
2553 else if (strcmp (string, "warning") == 0)
2554 *kind = check_warning;
2555 else if (strcmp (string, "error") == 0)
2556 *kind = check_error;
2558 as_bad (_("bad argument to %s_check directive."), str);
2559 (void) restore_line_pointer (e);
2562 as_bad (_("missing argument for %s_check directive"), str);
2564 demand_empty_rest_of_line ();
2568 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2569 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2572 static const char *arch;
2574 /* Intel LIOM is only supported on ELF. */
2580 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2581 use default_arch. */
2582 arch = cpu_arch_name;
2584 arch = default_arch;
2587 /* If we are targeting Intel MCU, we must enable it. */
2588 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2589 || new_flag.bitfield.cpuiamcu)
2592 /* If we are targeting Intel L1OM, we must enable it. */
2593 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2594 || new_flag.bitfield.cpul1om)
2597 /* If we are targeting Intel K1OM, we must enable it. */
2598 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2599 || new_flag.bitfield.cpuk1om)
2602 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2607 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2611 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2614 int e = get_symbol_name (&string);
2616 i386_cpu_flags flags;
2618 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2620 if (strcmp (string, cpu_arch[j].name) == 0)
2622 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2626 cpu_arch_name = cpu_arch[j].name;
2627 cpu_sub_arch_name = NULL;
2628 cpu_arch_flags = cpu_arch[j].flags;
2629 if (flag_code == CODE_64BIT)
2631 cpu_arch_flags.bitfield.cpu64 = 1;
2632 cpu_arch_flags.bitfield.cpuno64 = 0;
2636 cpu_arch_flags.bitfield.cpu64 = 0;
2637 cpu_arch_flags.bitfield.cpuno64 = 1;
2639 cpu_arch_isa = cpu_arch[j].type;
2640 cpu_arch_isa_flags = cpu_arch[j].flags;
2641 if (!cpu_arch_tune_set)
2643 cpu_arch_tune = cpu_arch_isa;
2644 cpu_arch_tune_flags = cpu_arch_isa_flags;
2649 flags = cpu_flags_or (cpu_arch_flags,
2652 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2654 if (cpu_sub_arch_name)
2656 char *name = cpu_sub_arch_name;
2657 cpu_sub_arch_name = concat (name,
2659 (const char *) NULL);
2663 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2664 cpu_arch_flags = flags;
2665 cpu_arch_isa_flags = flags;
2669 = cpu_flags_or (cpu_arch_isa_flags,
2671 (void) restore_line_pointer (e);
2672 demand_empty_rest_of_line ();
2677 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2679 /* Disable an ISA extension. */
2680 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2681 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2683 flags = cpu_flags_and_not (cpu_arch_flags,
2684 cpu_noarch[j].flags);
2685 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2687 if (cpu_sub_arch_name)
2689 char *name = cpu_sub_arch_name;
2690 cpu_sub_arch_name = concat (name, string,
2691 (const char *) NULL);
2695 cpu_sub_arch_name = xstrdup (string);
2696 cpu_arch_flags = flags;
2697 cpu_arch_isa_flags = flags;
2699 (void) restore_line_pointer (e);
2700 demand_empty_rest_of_line ();
2704 j = ARRAY_SIZE (cpu_arch);
2707 if (j >= ARRAY_SIZE (cpu_arch))
2708 as_bad (_("no such architecture: `%s'"), string);
2710 *input_line_pointer = e;
2713 as_bad (_("missing cpu architecture"));
2715 no_cond_jump_promotion = 0;
2716 if (*input_line_pointer == ','
2717 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2722 ++input_line_pointer;
2723 e = get_symbol_name (&string);
2725 if (strcmp (string, "nojumps") == 0)
2726 no_cond_jump_promotion = 1;
2727 else if (strcmp (string, "jumps") == 0)
2730 as_bad (_("no such architecture modifier: `%s'"), string);
2732 (void) restore_line_pointer (e);
2735 demand_empty_rest_of_line ();
2738 enum bfd_architecture
2741 if (cpu_arch_isa == PROCESSOR_L1OM)
2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || flag_code != CODE_64BIT)
2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_arch_l1om;
2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || flag_code != CODE_64BIT)
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_arch_k1om;
2755 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2757 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2758 || flag_code == CODE_64BIT)
2759 as_fatal (_("Intel MCU is 32bit ELF only"));
2760 return bfd_arch_iamcu;
2763 return bfd_arch_i386;
2769 if (!strncmp (default_arch, "x86_64", 6))
2771 if (cpu_arch_isa == PROCESSOR_L1OM)
2773 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2774 || default_arch[6] != '\0')
2775 as_fatal (_("Intel L1OM is 64bit ELF only"));
2776 return bfd_mach_l1om;
2778 else if (cpu_arch_isa == PROCESSOR_K1OM)
2780 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2781 || default_arch[6] != '\0')
2782 as_fatal (_("Intel K1OM is 64bit ELF only"));
2783 return bfd_mach_k1om;
2785 else if (default_arch[6] == '\0')
2786 return bfd_mach_x86_64;
2788 return bfd_mach_x64_32;
2790 else if (!strcmp (default_arch, "i386")
2791 || !strcmp (default_arch, "iamcu"))
2793 if (cpu_arch_isa == PROCESSOR_IAMCU)
2795 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2796 as_fatal (_("Intel MCU is 32bit ELF only"));
2797 return bfd_mach_i386_iamcu;
2800 return bfd_mach_i386_i386;
2803 as_fatal (_("unknown architecture"));
2809 const char *hash_err;
2811 /* Support pseudo prefixes like {disp32}. */
2812 lex_type ['{'] = LEX_BEGIN_NAME;
2814 /* Initialize op_hash hash table. */
2815 op_hash = hash_new ();
2818 const insn_template *optab;
2819 templates *core_optab;
2821 /* Setup for loop. */
2823 core_optab = XNEW (templates);
2824 core_optab->start = optab;
2829 if (optab->name == NULL
2830 || strcmp (optab->name, (optab - 1)->name) != 0)
2832 /* different name --> ship out current template list;
2833 add to hash table; & begin anew. */
2834 core_optab->end = optab;
2835 hash_err = hash_insert (op_hash,
2837 (void *) core_optab);
2840 as_fatal (_("can't hash %s: %s"),
2844 if (optab->name == NULL)
2846 core_optab = XNEW (templates);
2847 core_optab->start = optab;
2852 /* Initialize reg_hash hash table. */
2853 reg_hash = hash_new ();
2855 const reg_entry *regtab;
2856 unsigned int regtab_size = i386_regtab_size;
2858 for (regtab = i386_regtab; regtab_size--; regtab++)
2860 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2862 as_fatal (_("can't hash %s: %s"),
2868 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2873 for (c = 0; c < 256; c++)
2878 mnemonic_chars[c] = c;
2879 register_chars[c] = c;
2880 operand_chars[c] = c;
2882 else if (ISLOWER (c))
2884 mnemonic_chars[c] = c;
2885 register_chars[c] = c;
2886 operand_chars[c] = c;
2888 else if (ISUPPER (c))
2890 mnemonic_chars[c] = TOLOWER (c);
2891 register_chars[c] = mnemonic_chars[c];
2892 operand_chars[c] = c;
2894 else if (c == '{' || c == '}')
2896 mnemonic_chars[c] = c;
2897 operand_chars[c] = c;
2900 if (ISALPHA (c) || ISDIGIT (c))
2901 identifier_chars[c] = c;
2904 identifier_chars[c] = c;
2905 operand_chars[c] = c;
2910 identifier_chars['@'] = '@';
2913 identifier_chars['?'] = '?';
2914 operand_chars['?'] = '?';
2916 digit_chars['-'] = '-';
2917 mnemonic_chars['_'] = '_';
2918 mnemonic_chars['-'] = '-';
2919 mnemonic_chars['.'] = '.';
2920 identifier_chars['_'] = '_';
2921 identifier_chars['.'] = '.';
2923 for (p = operand_special_chars; *p != '\0'; p++)
2924 operand_chars[(unsigned char) *p] = *p;
2927 if (flag_code == CODE_64BIT)
2929 #if defined (OBJ_COFF) && defined (TE_PE)
2930 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2933 x86_dwarf2_return_column = 16;
2935 x86_cie_data_alignment = -8;
2939 x86_dwarf2_return_column = 8;
2940 x86_cie_data_alignment = -4;
2945 i386_print_statistics (FILE *file)
2947 hash_print_statistics (file, "i386 opcode", op_hash);
2948 hash_print_statistics (file, "i386 register", reg_hash);
2953 /* Debugging routines for md_assemble. */
2954 static void pte (insn_template *);
2955 static void pt (i386_operand_type);
2956 static void pe (expressionS *);
2957 static void ps (symbolS *);
2960 pi (char *line, i386_insn *x)
2964 fprintf (stdout, "%s: template ", line);
2966 fprintf (stdout, " address: base %s index %s scale %x\n",
2967 x->base_reg ? x->base_reg->reg_name : "none",
2968 x->index_reg ? x->index_reg->reg_name : "none",
2969 x->log2_scale_factor);
2970 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2971 x->rm.mode, x->rm.reg, x->rm.regmem);
2972 fprintf (stdout, " sib: base %x index %x scale %x\n",
2973 x->sib.base, x->sib.index, x->sib.scale);
2974 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2975 (x->rex & REX_W) != 0,
2976 (x->rex & REX_R) != 0,
2977 (x->rex & REX_X) != 0,
2978 (x->rex & REX_B) != 0);
2979 for (j = 0; j < x->operands; j++)
2981 fprintf (stdout, " #%d: ", j + 1);
2983 fprintf (stdout, "\n");
2984 if (x->types[j].bitfield.reg
2985 || x->types[j].bitfield.regmmx
2986 || x->types[j].bitfield.regsimd
2987 || x->types[j].bitfield.sreg2
2988 || x->types[j].bitfield.sreg3
2989 || x->types[j].bitfield.control
2990 || x->types[j].bitfield.debug
2991 || x->types[j].bitfield.test)
2992 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2993 if (operand_type_check (x->types[j], imm))
2995 if (operand_type_check (x->types[j], disp))
2996 pe (x->op[j].disps);
3001 pte (insn_template *t)
3004 fprintf (stdout, " %d operands ", t->operands);
3005 fprintf (stdout, "opcode %x ", t->base_opcode);
3006 if (t->extension_opcode != None)
3007 fprintf (stdout, "ext %x ", t->extension_opcode);
3008 if (t->opcode_modifier.d)
3009 fprintf (stdout, "D");
3010 if (t->opcode_modifier.w)
3011 fprintf (stdout, "W");
3012 fprintf (stdout, "\n");
3013 for (j = 0; j < t->operands; j++)
3015 fprintf (stdout, " #%d type ", j + 1);
3016 pt (t->operand_types[j]);
3017 fprintf (stdout, "\n");
3024 fprintf (stdout, " operation %d\n", e->X_op);
3025 fprintf (stdout, " add_number %ld (%lx)\n",
3026 (long) e->X_add_number, (long) e->X_add_number);
3027 if (e->X_add_symbol)
3029 fprintf (stdout, " add_symbol ");
3030 ps (e->X_add_symbol);
3031 fprintf (stdout, "\n");
3035 fprintf (stdout, " op_symbol ");
3036 ps (e->X_op_symbol);
3037 fprintf (stdout, "\n");
3044 fprintf (stdout, "%s type %s%s",
3046 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3047 segment_name (S_GET_SEGMENT (s)));
3050 static struct type_name
3052 i386_operand_type mask;
3055 const type_names[] =
3057 { OPERAND_TYPE_REG8, "r8" },
3058 { OPERAND_TYPE_REG16, "r16" },
3059 { OPERAND_TYPE_REG32, "r32" },
3060 { OPERAND_TYPE_REG64, "r64" },
3061 { OPERAND_TYPE_IMM8, "i8" },
3062 { OPERAND_TYPE_IMM8, "i8s" },
3063 { OPERAND_TYPE_IMM16, "i16" },
3064 { OPERAND_TYPE_IMM32, "i32" },
3065 { OPERAND_TYPE_IMM32S, "i32s" },
3066 { OPERAND_TYPE_IMM64, "i64" },
3067 { OPERAND_TYPE_IMM1, "i1" },
3068 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3069 { OPERAND_TYPE_DISP8, "d8" },
3070 { OPERAND_TYPE_DISP16, "d16" },
3071 { OPERAND_TYPE_DISP32, "d32" },
3072 { OPERAND_TYPE_DISP32S, "d32s" },
3073 { OPERAND_TYPE_DISP64, "d64" },
3074 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3075 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3076 { OPERAND_TYPE_CONTROL, "control reg" },
3077 { OPERAND_TYPE_TEST, "test reg" },
3078 { OPERAND_TYPE_DEBUG, "debug reg" },
3079 { OPERAND_TYPE_FLOATREG, "FReg" },
3080 { OPERAND_TYPE_FLOATACC, "FAcc" },
3081 { OPERAND_TYPE_SREG2, "SReg2" },
3082 { OPERAND_TYPE_SREG3, "SReg3" },
3083 { OPERAND_TYPE_ACC, "Acc" },
3084 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3085 { OPERAND_TYPE_REGMMX, "rMMX" },
3086 { OPERAND_TYPE_REGXMM, "rXMM" },
3087 { OPERAND_TYPE_REGYMM, "rYMM" },
3088 { OPERAND_TYPE_REGZMM, "rZMM" },
3089 { OPERAND_TYPE_REGMASK, "Mask reg" },
3090 { OPERAND_TYPE_ESSEG, "es" },
3094 pt (i386_operand_type t)
3097 i386_operand_type a;
3099 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3101 a = operand_type_and (t, type_names[j].mask);
3102 if (!operand_type_all_zero (&a))
3103 fprintf (stdout, "%s, ", type_names[j].name);
3108 #endif /* DEBUG386 */
3110 static bfd_reloc_code_real_type
3111 reloc (unsigned int size,
3114 bfd_reloc_code_real_type other)
3116 if (other != NO_RELOC)
3118 reloc_howto_type *rel;
3123 case BFD_RELOC_X86_64_GOT32:
3124 return BFD_RELOC_X86_64_GOT64;
3126 case BFD_RELOC_X86_64_GOTPLT64:
3127 return BFD_RELOC_X86_64_GOTPLT64;
3129 case BFD_RELOC_X86_64_PLTOFF64:
3130 return BFD_RELOC_X86_64_PLTOFF64;
3132 case BFD_RELOC_X86_64_GOTPC32:
3133 other = BFD_RELOC_X86_64_GOTPC64;
3135 case BFD_RELOC_X86_64_GOTPCREL:
3136 other = BFD_RELOC_X86_64_GOTPCREL64;
3138 case BFD_RELOC_X86_64_TPOFF32:
3139 other = BFD_RELOC_X86_64_TPOFF64;
3141 case BFD_RELOC_X86_64_DTPOFF32:
3142 other = BFD_RELOC_X86_64_DTPOFF64;
3148 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3149 if (other == BFD_RELOC_SIZE32)
3152 other = BFD_RELOC_SIZE64;
3155 as_bad (_("there are no pc-relative size relocations"));
3161 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3162 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3165 rel = bfd_reloc_type_lookup (stdoutput, other);
3167 as_bad (_("unknown relocation (%u)"), other);
3168 else if (size != bfd_get_reloc_size (rel))
3169 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3170 bfd_get_reloc_size (rel),
3172 else if (pcrel && !rel->pc_relative)
3173 as_bad (_("non-pc-relative relocation for pc-relative field"));
3174 else if ((rel->complain_on_overflow == complain_overflow_signed
3176 || (rel->complain_on_overflow == complain_overflow_unsigned
3178 as_bad (_("relocated field and relocation type differ in signedness"));
3187 as_bad (_("there are no unsigned pc-relative relocations"));
3190 case 1: return BFD_RELOC_8_PCREL;
3191 case 2: return BFD_RELOC_16_PCREL;
3192 case 4: return BFD_RELOC_32_PCREL;
3193 case 8: return BFD_RELOC_64_PCREL;
3195 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3202 case 4: return BFD_RELOC_X86_64_32S;
3207 case 1: return BFD_RELOC_8;
3208 case 2: return BFD_RELOC_16;
3209 case 4: return BFD_RELOC_32;
3210 case 8: return BFD_RELOC_64;
3212 as_bad (_("cannot do %s %u byte relocation"),
3213 sign > 0 ? "signed" : "unsigned", size);
3219 /* Here we decide which fixups can be adjusted to make them relative to
3220 the beginning of the section instead of the symbol. Basically we need
3221 to make sure that the dynamic relocations are done correctly, so in
3222 some cases we force the original symbol to be used. */
3225 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3227 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3231 /* Don't adjust pc-relative references to merge sections in 64-bit
3233 if (use_rela_relocations
3234 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3238 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3239 and changed later by validate_fix. */
3240 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3241 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3244 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3245 for size relocations. */
3246 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3247 || fixP->fx_r_type == BFD_RELOC_SIZE64
3248 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3249 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3250 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3251 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3252 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3253 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3254 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3255 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3256 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3257 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3258 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3259 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3260 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3261 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3262 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3263 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3264 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3265 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3266 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3267 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3268 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3269 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3270 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3271 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3272 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3273 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3274 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3275 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3276 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3277 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3278 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3285 intel_float_operand (const char *mnemonic)
3287 /* Note that the value returned is meaningful only for opcodes with (memory)
3288 operands, hence the code here is free to improperly handle opcodes that
3289 have no operands (for better performance and smaller code). */
3291 if (mnemonic[0] != 'f')
3292 return 0; /* non-math */
3294 switch (mnemonic[1])
3296 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3297 the fs segment override prefix not currently handled because no
3298 call path can make opcodes without operands get here */
3300 return 2 /* integer op */;
3302 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3303 return 3; /* fldcw/fldenv */
3306 if (mnemonic[2] != 'o' /* fnop */)
3307 return 3; /* non-waiting control op */
3310 if (mnemonic[2] == 's')
3311 return 3; /* frstor/frstpm */
3314 if (mnemonic[2] == 'a')
3315 return 3; /* fsave */
3316 if (mnemonic[2] == 't')
3318 switch (mnemonic[3])
3320 case 'c': /* fstcw */
3321 case 'd': /* fstdw */
3322 case 'e': /* fstenv */
3323 case 's': /* fsts[gw] */
3329 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3330 return 0; /* fxsave/fxrstor are not really math ops */
3337 /* Build the VEX prefix. */
3340 build_vex_prefix (const insn_template *t)
3342 unsigned int register_specifier;
3343 unsigned int implied_prefix;
3344 unsigned int vector_length;
3346 /* Check register specifier. */
3347 if (i.vex.register_specifier)
3349 register_specifier =
3350 ~register_number (i.vex.register_specifier) & 0xf;
3351 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3354 register_specifier = 0xf;
3356 /* Use 2-byte VEX prefix by swapping destination and source
3358 if (i.vec_encoding != vex_encoding_vex3
3359 && i.dir_encoding == dir_encoding_default
3360 && i.operands == i.reg_operands
3361 && i.tm.opcode_modifier.vexopcode == VEX0F
3362 && i.tm.opcode_modifier.load
3365 unsigned int xchg = i.operands - 1;
3366 union i386_op temp_op;
3367 i386_operand_type temp_type;
3369 temp_type = i.types[xchg];
3370 i.types[xchg] = i.types[0];
3371 i.types[0] = temp_type;
3372 temp_op = i.op[xchg];
3373 i.op[xchg] = i.op[0];
3376 gas_assert (i.rm.mode == 3);
3380 i.rm.regmem = i.rm.reg;
3383 /* Use the next insn. */
3387 if (i.tm.opcode_modifier.vex == VEXScalar)
3388 vector_length = avxscalar;
3389 else if (i.tm.opcode_modifier.vex == VEX256)
3395 /* Determine vector length from the last multi-length vector
3398 for (op = t->operands; op--;)
3399 if (t->operand_types[op].bitfield.xmmword
3400 && t->operand_types[op].bitfield.ymmword
3401 && i.types[op].bitfield.ymmword)
3408 switch ((i.tm.base_opcode >> 8) & 0xff)
3413 case DATA_PREFIX_OPCODE:
3416 case REPE_PREFIX_OPCODE:
3419 case REPNE_PREFIX_OPCODE:
3426 /* Use 2-byte VEX prefix if possible. */
3427 if (i.vec_encoding != vex_encoding_vex3
3428 && i.tm.opcode_modifier.vexopcode == VEX0F
3429 && i.tm.opcode_modifier.vexw != VEXW1
3430 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3432 /* 2-byte VEX prefix. */
3436 i.vex.bytes[0] = 0xc5;
3438 /* Check the REX.R bit. */
3439 r = (i.rex & REX_R) ? 0 : 1;
3440 i.vex.bytes[1] = (r << 7
3441 | register_specifier << 3
3442 | vector_length << 2
3447 /* 3-byte VEX prefix. */
3452 switch (i.tm.opcode_modifier.vexopcode)
3456 i.vex.bytes[0] = 0xc4;
3460 i.vex.bytes[0] = 0xc4;
3464 i.vex.bytes[0] = 0xc4;
3468 i.vex.bytes[0] = 0x8f;
3472 i.vex.bytes[0] = 0x8f;
3476 i.vex.bytes[0] = 0x8f;
3482 /* The high 3 bits of the second VEX byte are 1's compliment
3483 of RXB bits from REX. */
3484 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3486 /* Check the REX.W bit. */
3487 w = (i.rex & REX_W) ? 1 : 0;
3488 if (i.tm.opcode_modifier.vexw == VEXW1)
3491 i.vex.bytes[2] = (w << 7
3492 | register_specifier << 3
3493 | vector_length << 2
3498 static INLINE bfd_boolean
3499 is_evex_encoding (const insn_template *t)
3501 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3502 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3503 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3506 static INLINE bfd_boolean
3507 is_any_vex_encoding (const insn_template *t)
3509 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3510 || is_evex_encoding (t);
3513 /* Build the EVEX prefix. */
3516 build_evex_prefix (void)
3518 unsigned int register_specifier;
3519 unsigned int implied_prefix;
3521 rex_byte vrex_used = 0;
3523 /* Check register specifier. */
3524 if (i.vex.register_specifier)
3526 gas_assert ((i.vrex & REX_X) == 0);
3528 register_specifier = i.vex.register_specifier->reg_num;
3529 if ((i.vex.register_specifier->reg_flags & RegRex))
3530 register_specifier += 8;
3531 /* The upper 16 registers are encoded in the fourth byte of the
3533 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3534 i.vex.bytes[3] = 0x8;
3535 register_specifier = ~register_specifier & 0xf;
3539 register_specifier = 0xf;
3541 /* Encode upper 16 vector index register in the fourth byte of
3543 if (!(i.vrex & REX_X))
3544 i.vex.bytes[3] = 0x8;
3549 switch ((i.tm.base_opcode >> 8) & 0xff)
3554 case DATA_PREFIX_OPCODE:
3557 case REPE_PREFIX_OPCODE:
3560 case REPNE_PREFIX_OPCODE:
3567 /* 4 byte EVEX prefix. */
3569 i.vex.bytes[0] = 0x62;
3572 switch (i.tm.opcode_modifier.vexopcode)
3588 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3590 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3592 /* The fifth bit of the second EVEX byte is 1's compliment of the
3593 REX_R bit in VREX. */
3594 if (!(i.vrex & REX_R))
3595 i.vex.bytes[1] |= 0x10;
3599 if ((i.reg_operands + i.imm_operands) == i.operands)
3601 /* When all operands are registers, the REX_X bit in REX is not
3602 used. We reuse it to encode the upper 16 registers, which is
3603 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3604 as 1's compliment. */
3605 if ((i.vrex & REX_B))
3608 i.vex.bytes[1] &= ~0x40;
3612 /* EVEX instructions shouldn't need the REX prefix. */
3613 i.vrex &= ~vrex_used;
3614 gas_assert (i.vrex == 0);
3616 /* Check the REX.W bit. */
3617 w = (i.rex & REX_W) ? 1 : 0;
3618 if (i.tm.opcode_modifier.vexw)
3620 if (i.tm.opcode_modifier.vexw == VEXW1)
3623 /* If w is not set it means we are dealing with WIG instruction. */
3626 if (evexwig == evexw1)
3630 /* Encode the U bit. */
3631 implied_prefix |= 0x4;
3633 /* The third byte of the EVEX prefix. */
3634 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3636 /* The fourth byte of the EVEX prefix. */
3637 /* The zeroing-masking bit. */
3638 if (i.mask && i.mask->zeroing)
3639 i.vex.bytes[3] |= 0x80;
3641 /* Don't always set the broadcast bit if there is no RC. */
3644 /* Encode the vector length. */
3645 unsigned int vec_length;
3647 if (!i.tm.opcode_modifier.evex
3648 || i.tm.opcode_modifier.evex == EVEXDYN)
3652 /* Determine vector length from the last multi-length vector
3655 for (op = i.operands; op--;)
3656 if (i.tm.operand_types[op].bitfield.xmmword
3657 + i.tm.operand_types[op].bitfield.ymmword
3658 + i.tm.operand_types[op].bitfield.zmmword > 1)
3660 if (i.types[op].bitfield.zmmword)
3662 i.tm.opcode_modifier.evex = EVEX512;
3665 else if (i.types[op].bitfield.ymmword)
3667 i.tm.opcode_modifier.evex = EVEX256;
3670 else if (i.types[op].bitfield.xmmword)
3672 i.tm.opcode_modifier.evex = EVEX128;
3675 else if (i.broadcast && (int) op == i.broadcast->operand)
3677 switch (i.broadcast->bytes)
3680 i.tm.opcode_modifier.evex = EVEX512;
3683 i.tm.opcode_modifier.evex = EVEX256;
3686 i.tm.opcode_modifier.evex = EVEX128;
3695 if (op >= MAX_OPERANDS)
3699 switch (i.tm.opcode_modifier.evex)
3701 case EVEXLIG: /* LL' is ignored */
3702 vec_length = evexlig << 5;
3705 vec_length = 0 << 5;
3708 vec_length = 1 << 5;
3711 vec_length = 2 << 5;
3717 i.vex.bytes[3] |= vec_length;
3718 /* Encode the broadcast bit. */
3720 i.vex.bytes[3] |= 0x10;
3724 if (i.rounding->type != saeonly)
3725 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3727 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3730 if (i.mask && i.mask->mask)
3731 i.vex.bytes[3] |= i.mask->mask->reg_num;
3735 process_immext (void)
3739 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3742 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3743 with an opcode suffix which is coded in the same place as an
3744 8-bit immediate field would be.
3745 Here we check those operands and remove them afterwards. */
3748 for (x = 0; x < i.operands; x++)
3749 if (register_number (i.op[x].regs) != x)
3750 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3751 register_prefix, i.op[x].regs->reg_name, x + 1,
3757 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3759 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3760 suffix which is coded in the same place as an 8-bit immediate
3762 Here we check those operands and remove them afterwards. */
3765 if (i.operands != 3)
3768 for (x = 0; x < 2; x++)
3769 if (register_number (i.op[x].regs) != x)
3770 goto bad_register_operand;
3772 /* Check for third operand for mwaitx/monitorx insn. */
3773 if (register_number (i.op[x].regs)
3774 != (x + (i.tm.extension_opcode == 0xfb)))
3776 bad_register_operand:
3777 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3778 register_prefix, i.op[x].regs->reg_name, x+1,
3785 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3786 which is coded in the same place as an 8-bit immediate field
3787 would be. Here we fake an 8-bit immediate operand from the
3788 opcode suffix stored in tm.extension_opcode.
3790 AVX instructions also use this encoding, for some of
3791 3 argument instructions. */
3793 gas_assert (i.imm_operands <= 1
3795 || (is_any_vex_encoding (&i.tm)
3796 && i.operands <= 4)));
3798 exp = &im_expressions[i.imm_operands++];
3799 i.op[i.operands].imms = exp;
3800 i.types[i.operands] = imm8;
3802 exp->X_op = O_constant;
3803 exp->X_add_number = i.tm.extension_opcode;
3804 i.tm.extension_opcode = None;
3811 switch (i.tm.opcode_modifier.hleprefixok)
3816 as_bad (_("invalid instruction `%s' after `%s'"),
3817 i.tm.name, i.hle_prefix);
3820 if (i.prefix[LOCK_PREFIX])
3822 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3826 case HLEPrefixRelease:
3827 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3829 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3833 if (i.mem_operands == 0
3834 || !operand_type_check (i.types[i.operands - 1], anymem))
3836 as_bad (_("memory destination needed for instruction `%s'"
3837 " after `xrelease'"), i.tm.name);
3844 /* Try the shortest encoding by shortening operand size. */
3847 optimize_encoding (void)
3851 if (optimize_for_space
3852 && i.reg_operands == 1
3853 && i.imm_operands == 1
3854 && !i.types[1].bitfield.byte
3855 && i.op[0].imms->X_op == O_constant
3856 && fits_in_imm7 (i.op[0].imms->X_add_number)
3857 && ((i.tm.base_opcode == 0xa8
3858 && i.tm.extension_opcode == None)
3859 || (i.tm.base_opcode == 0xf6
3860 && i.tm.extension_opcode == 0x0)))
3863 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3865 unsigned int base_regnum = i.op[1].regs->reg_num;
3866 if (flag_code == CODE_64BIT || base_regnum < 4)
3868 i.types[1].bitfield.byte = 1;
3869 /* Ignore the suffix. */
3871 if (base_regnum >= 4
3872 && !(i.op[1].regs->reg_flags & RegRex))
3874 /* Handle SP, BP, SI and DI registers. */
3875 if (i.types[1].bitfield.word)
3877 else if (i.types[1].bitfield.dword)
3885 else if (flag_code == CODE_64BIT
3886 && ((i.types[1].bitfield.qword
3887 && i.reg_operands == 1
3888 && i.imm_operands == 1
3889 && i.op[0].imms->X_op == O_constant
3890 && ((i.tm.base_opcode == 0xb0
3891 && i.tm.extension_opcode == None
3892 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3893 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3894 && (((i.tm.base_opcode == 0x24
3895 || i.tm.base_opcode == 0xa8)
3896 && i.tm.extension_opcode == None)
3897 || (i.tm.base_opcode == 0x80
3898 && i.tm.extension_opcode == 0x4)
3899 || ((i.tm.base_opcode == 0xf6
3900 || i.tm.base_opcode == 0xc6)
3901 && i.tm.extension_opcode == 0x0)))))
3902 || (i.types[0].bitfield.qword
3903 && ((i.reg_operands == 2
3904 && i.op[0].regs == i.op[1].regs
3905 && ((i.tm.base_opcode == 0x30
3906 || i.tm.base_opcode == 0x28)
3907 && i.tm.extension_opcode == None))
3908 || (i.reg_operands == 1
3910 && i.tm.base_opcode == 0x30
3911 && i.tm.extension_opcode == None)))))
3914 andq $imm31, %r64 -> andl $imm31, %r32
3915 testq $imm31, %r64 -> testl $imm31, %r32
3916 xorq %r64, %r64 -> xorl %r32, %r32
3917 subq %r64, %r64 -> subl %r32, %r32
3918 movq $imm31, %r64 -> movl $imm31, %r32
3919 movq $imm32, %r64 -> movl $imm32, %r32
3921 i.tm.opcode_modifier.norex64 = 1;
3922 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3925 movq $imm31, %r64 -> movl $imm31, %r32
3926 movq $imm32, %r64 -> movl $imm32, %r32
3928 i.tm.operand_types[0].bitfield.imm32 = 1;
3929 i.tm.operand_types[0].bitfield.imm32s = 0;
3930 i.tm.operand_types[0].bitfield.imm64 = 0;
3931 i.types[0].bitfield.imm32 = 1;
3932 i.types[0].bitfield.imm32s = 0;
3933 i.types[0].bitfield.imm64 = 0;
3934 i.types[1].bitfield.dword = 1;
3935 i.types[1].bitfield.qword = 0;
3936 if (i.tm.base_opcode == 0xc6)
3939 movq $imm31, %r64 -> movl $imm31, %r32
3941 i.tm.base_opcode = 0xb0;
3942 i.tm.extension_opcode = None;
3943 i.tm.opcode_modifier.shortform = 1;
3944 i.tm.opcode_modifier.modrm = 0;
3948 else if (optimize > 1
3949 && i.reg_operands == 3
3950 && i.op[0].regs == i.op[1].regs
3951 && !i.types[2].bitfield.xmmword
3952 && (i.tm.opcode_modifier.vex
3953 || ((!i.mask || i.mask->zeroing)
3955 && is_evex_encoding (&i.tm)
3956 && (i.vec_encoding != vex_encoding_evex
3957 || i.tm.cpu_flags.bitfield.cpuavx512vl
3958 || (i.tm.operand_types[2].bitfield.zmmword
3959 && i.types[2].bitfield.ymmword)
3960 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
3961 && ((i.tm.base_opcode == 0x55
3962 || i.tm.base_opcode == 0x6655
3963 || i.tm.base_opcode == 0x66df
3964 || i.tm.base_opcode == 0x57
3965 || i.tm.base_opcode == 0x6657
3966 || i.tm.base_opcode == 0x66ef
3967 || i.tm.base_opcode == 0x66f8
3968 || i.tm.base_opcode == 0x66f9
3969 || i.tm.base_opcode == 0x66fa
3970 || i.tm.base_opcode == 0x66fb
3971 || i.tm.base_opcode == 0x42
3972 || i.tm.base_opcode == 0x6642
3973 || i.tm.base_opcode == 0x47
3974 || i.tm.base_opcode == 0x6647)
3975 && i.tm.extension_opcode == None))
3978 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3980 EVEX VOP %zmmM, %zmmM, %zmmN
3981 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3982 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3983 EVEX VOP %ymmM, %ymmM, %ymmN
3984 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3985 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3986 VEX VOP %ymmM, %ymmM, %ymmN
3987 -> VEX VOP %xmmM, %xmmM, %xmmN
3988 VOP, one of vpandn and vpxor:
3989 VEX VOP %ymmM, %ymmM, %ymmN
3990 -> VEX VOP %xmmM, %xmmM, %xmmN
3991 VOP, one of vpandnd and vpandnq:
3992 EVEX VOP %zmmM, %zmmM, %zmmN
3993 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3994 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3995 EVEX VOP %ymmM, %ymmM, %ymmN
3996 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3997 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3998 VOP, one of vpxord and vpxorq:
3999 EVEX VOP %zmmM, %zmmM, %zmmN
4000 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4001 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4002 EVEX VOP %ymmM, %ymmM, %ymmN
4003 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4004 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4005 VOP, one of kxord and kxorq:
4006 VEX VOP %kM, %kM, %kN
4007 -> VEX kxorw %kM, %kM, %kN
4008 VOP, one of kandnd and kandnq:
4009 VEX VOP %kM, %kM, %kN
4010 -> VEX kandnw %kM, %kM, %kN
4012 if (is_evex_encoding (&i.tm))
4014 if (i.vec_encoding == vex_encoding_evex)
4015 i.tm.opcode_modifier.evex = EVEX128;
4018 i.tm.opcode_modifier.vex = VEX128;
4019 i.tm.opcode_modifier.vexw = VEXW0;
4020 i.tm.opcode_modifier.evex = 0;
4023 else if (i.tm.operand_types[0].bitfield.regmask)
4025 i.tm.base_opcode &= 0xff;
4026 i.tm.opcode_modifier.vexw = VEXW0;
4029 i.tm.opcode_modifier.vex = VEX128;
4031 if (i.tm.opcode_modifier.vex)
4032 for (j = 0; j < 3; j++)
4034 i.types[j].bitfield.xmmword = 1;
4035 i.types[j].bitfield.ymmword = 0;
4040 /* This is the guts of the machine-dependent assembler. LINE points to a
4041 machine dependent instruction. This function is supposed to emit
4042 the frags/bytes it assembles to. */
4045 md_assemble (char *line)
4048 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4049 const insn_template *t;
4051 /* Initialize globals. */
4052 memset (&i, '\0', sizeof (i));
4053 for (j = 0; j < MAX_OPERANDS; j++)
4054 i.reloc[j] = NO_RELOC;
4055 memset (disp_expressions, '\0', sizeof (disp_expressions));
4056 memset (im_expressions, '\0', sizeof (im_expressions));
4057 save_stack_p = save_stack;
4059 /* First parse an instruction mnemonic & call i386_operand for the operands.
4060 We assume that the scrubber has arranged it so that line[0] is the valid
4061 start of a (possibly prefixed) mnemonic. */
4063 line = parse_insn (line, mnemonic);
4066 mnem_suffix = i.suffix;
4068 line = parse_operands (line, mnemonic);
4070 xfree (i.memop1_string);
4071 i.memop1_string = NULL;
4075 /* Now we've parsed the mnemonic into a set of templates, and have the
4076 operands at hand. */
4078 /* All intel opcodes have reversed operands except for "bound" and
4079 "enter". We also don't reverse intersegment "jmp" and "call"
4080 instructions with 2 immediate operands so that the immediate segment
4081 precedes the offset, as it does when in AT&T mode. */
4084 && (strcmp (mnemonic, "bound") != 0)
4085 && (strcmp (mnemonic, "invlpga") != 0)
4086 && !(operand_type_check (i.types[0], imm)
4087 && operand_type_check (i.types[1], imm)))
4090 /* The order of the immediates should be reversed
4091 for 2 immediates extrq and insertq instructions */
4092 if (i.imm_operands == 2
4093 && (strcmp (mnemonic, "extrq") == 0
4094 || strcmp (mnemonic, "insertq") == 0))
4095 swap_2_operands (0, 1);
4100 /* Don't optimize displacement for movabs since it only takes 64bit
4103 && i.disp_encoding != disp_encoding_32bit
4104 && (flag_code != CODE_64BIT
4105 || strcmp (mnemonic, "movabs") != 0))
4108 /* Next, we find a template that matches the given insn,
4109 making sure the overlap of the given operands types is consistent
4110 with the template operand types. */
4112 if (!(t = match_template (mnem_suffix)))
4115 if (sse_check != check_none
4116 && !i.tm.opcode_modifier.noavx
4117 && !i.tm.cpu_flags.bitfield.cpuavx
4118 && (i.tm.cpu_flags.bitfield.cpusse
4119 || i.tm.cpu_flags.bitfield.cpusse2
4120 || i.tm.cpu_flags.bitfield.cpusse3
4121 || i.tm.cpu_flags.bitfield.cpussse3
4122 || i.tm.cpu_flags.bitfield.cpusse4_1
4123 || i.tm.cpu_flags.bitfield.cpusse4_2
4124 || i.tm.cpu_flags.bitfield.cpupclmul
4125 || i.tm.cpu_flags.bitfield.cpuaes
4126 || i.tm.cpu_flags.bitfield.cpugfni))
4128 (sse_check == check_warning
4130 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4133 /* Zap movzx and movsx suffix. The suffix has been set from
4134 "word ptr" or "byte ptr" on the source operand in Intel syntax
4135 or extracted from mnemonic in AT&T syntax. But we'll use
4136 the destination register to choose the suffix for encoding. */
4137 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4139 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4140 there is no suffix, the default will be byte extension. */
4141 if (i.reg_operands != 2
4144 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4149 if (i.tm.opcode_modifier.fwait)
4150 if (!add_prefix (FWAIT_OPCODE))
4153 /* Check if REP prefix is OK. */
4154 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4156 as_bad (_("invalid instruction `%s' after `%s'"),
4157 i.tm.name, i.rep_prefix);
4161 /* Check for lock without a lockable instruction. Destination operand
4162 must be memory unless it is xchg (0x86). */
4163 if (i.prefix[LOCK_PREFIX]
4164 && (!i.tm.opcode_modifier.islockable
4165 || i.mem_operands == 0
4166 || (i.tm.base_opcode != 0x86
4167 && !operand_type_check (i.types[i.operands - 1], anymem))))
4169 as_bad (_("expecting lockable instruction after `lock'"));
4173 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4174 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4176 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4180 /* Check if HLE prefix is OK. */
4181 if (i.hle_prefix && !check_hle ())
4184 /* Check BND prefix. */
4185 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4186 as_bad (_("expecting valid branch instruction after `bnd'"));
4188 /* Check NOTRACK prefix. */
4189 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4190 as_bad (_("expecting indirect branch instruction after `notrack'"));
4192 if (i.tm.cpu_flags.bitfield.cpumpx)
4194 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4195 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4196 else if (flag_code != CODE_16BIT
4197 ? i.prefix[ADDR_PREFIX]
4198 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4199 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4202 /* Insert BND prefix. */
4203 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4205 if (!i.prefix[BND_PREFIX])
4206 add_prefix (BND_PREFIX_OPCODE);
4207 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4209 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4210 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4214 /* Check string instruction segment overrides. */
4215 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4217 if (!check_string ())
4219 i.disp_operands = 0;
4222 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4223 optimize_encoding ();
4225 if (!process_suffix ())
4228 /* Update operand types. */
4229 for (j = 0; j < i.operands; j++)
4230 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4232 /* Make still unresolved immediate matches conform to size of immediate
4233 given in i.suffix. */
4234 if (!finalize_imm ())
4237 if (i.types[0].bitfield.imm1)
4238 i.imm_operands = 0; /* kludge for shift insns. */
4240 /* We only need to check those implicit registers for instructions
4241 with 3 operands or less. */
4242 if (i.operands <= 3)
4243 for (j = 0; j < i.operands; j++)
4244 if (i.types[j].bitfield.inoutportreg
4245 || i.types[j].bitfield.shiftcount
4246 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4249 /* ImmExt should be processed after SSE2AVX. */
4250 if (!i.tm.opcode_modifier.sse2avx
4251 && i.tm.opcode_modifier.immext)
4254 /* For insns with operands there are more diddles to do to the opcode. */
4257 if (!process_operands ())
4260 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4262 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4263 as_warn (_("translating to `%sp'"), i.tm.name);
4266 if (is_any_vex_encoding (&i.tm))
4268 if (flag_code == CODE_16BIT)
4270 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4275 if (i.tm.opcode_modifier.vex)
4276 build_vex_prefix (t);
4278 build_evex_prefix ();
4281 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4282 instructions may define INT_OPCODE as well, so avoid this corner
4283 case for those instructions that use MODRM. */
4284 if (i.tm.base_opcode == INT_OPCODE
4285 && !i.tm.opcode_modifier.modrm
4286 && i.op[0].imms->X_add_number == 3)
4288 i.tm.base_opcode = INT3_OPCODE;
4292 if ((i.tm.opcode_modifier.jump
4293 || i.tm.opcode_modifier.jumpbyte
4294 || i.tm.opcode_modifier.jumpdword)
4295 && i.op[0].disps->X_op == O_constant)
4297 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4298 the absolute address given by the constant. Since ix86 jumps and
4299 calls are pc relative, we need to generate a reloc. */
4300 i.op[0].disps->X_add_symbol = &abs_symbol;
4301 i.op[0].disps->X_op = O_symbol;
4304 if (i.tm.opcode_modifier.rex64)
4307 /* For 8 bit registers we need an empty rex prefix. Also if the
4308 instruction already has a prefix, we need to convert old
4309 registers to new ones. */
4311 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4312 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4313 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4314 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4315 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4316 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4321 i.rex |= REX_OPCODE;
4322 for (x = 0; x < 2; x++)
4324 /* Look for 8 bit operand that uses old registers. */
4325 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4326 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4328 /* In case it is "hi" register, give up. */
4329 if (i.op[x].regs->reg_num > 3)
4330 as_bad (_("can't encode register '%s%s' in an "
4331 "instruction requiring REX prefix."),
4332 register_prefix, i.op[x].regs->reg_name);
4334 /* Otherwise it is equivalent to the extended register.
4335 Since the encoding doesn't change this is merely
4336 cosmetic cleanup for debug output. */
4338 i.op[x].regs = i.op[x].regs + 8;
4343 if (i.rex == 0 && i.rex_encoding)
4345 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4346 that uses legacy register. If it is "hi" register, don't add
4347 the REX_OPCODE byte. */
4349 for (x = 0; x < 2; x++)
4350 if (i.types[x].bitfield.reg
4351 && i.types[x].bitfield.byte
4352 && (i.op[x].regs->reg_flags & RegRex64) == 0
4353 && i.op[x].regs->reg_num > 3)
4355 i.rex_encoding = FALSE;
4364 add_prefix (REX_OPCODE | i.rex);
4366 /* We are ready to output the insn. */
4371 parse_insn (char *line, char *mnemonic)
4374 char *token_start = l;
4377 const insn_template *t;
4383 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4388 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4390 as_bad (_("no such instruction: `%s'"), token_start);
4395 if (!is_space_char (*l)
4396 && *l != END_OF_INSN
4398 || (*l != PREFIX_SEPARATOR
4401 as_bad (_("invalid character %s in mnemonic"),
4402 output_invalid (*l));
4405 if (token_start == l)
4407 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4408 as_bad (_("expecting prefix; got nothing"));
4410 as_bad (_("expecting mnemonic; got nothing"));
4414 /* Look up instruction (or prefix) via hash table. */
4415 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4417 if (*l != END_OF_INSN
4418 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4419 && current_templates
4420 && current_templates->start->opcode_modifier.isprefix)
4422 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4424 as_bad ((flag_code != CODE_64BIT
4425 ? _("`%s' is only supported in 64-bit mode")
4426 : _("`%s' is not supported in 64-bit mode")),
4427 current_templates->start->name);
4430 /* If we are in 16-bit mode, do not allow addr16 or data16.
4431 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4432 if ((current_templates->start->opcode_modifier.size16
4433 || current_templates->start->opcode_modifier.size32)
4434 && flag_code != CODE_64BIT
4435 && (current_templates->start->opcode_modifier.size32
4436 ^ (flag_code == CODE_16BIT)))
4438 as_bad (_("redundant %s prefix"),
4439 current_templates->start->name);
4442 if (current_templates->start->opcode_length == 0)
4444 /* Handle pseudo prefixes. */
4445 switch (current_templates->start->base_opcode)
4449 i.disp_encoding = disp_encoding_8bit;
4453 i.disp_encoding = disp_encoding_32bit;
4457 i.dir_encoding = dir_encoding_load;
4461 i.dir_encoding = dir_encoding_store;
4465 i.vec_encoding = vex_encoding_vex2;
4469 i.vec_encoding = vex_encoding_vex3;
4473 i.vec_encoding = vex_encoding_evex;
4477 i.rex_encoding = TRUE;
4481 i.no_optimize = TRUE;
4489 /* Add prefix, checking for repeated prefixes. */
4490 switch (add_prefix (current_templates->start->base_opcode))
4495 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4496 i.notrack_prefix = current_templates->start->name;
4499 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4500 i.hle_prefix = current_templates->start->name;
4501 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4502 i.bnd_prefix = current_templates->start->name;
4504 i.rep_prefix = current_templates->start->name;
4510 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4517 if (!current_templates)
4519 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4520 Check if we should swap operand or force 32bit displacement in
4522 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4523 i.dir_encoding = dir_encoding_store;
4524 else if (mnem_p - 3 == dot_p
4527 i.disp_encoding = disp_encoding_8bit;
4528 else if (mnem_p - 4 == dot_p
4532 i.disp_encoding = disp_encoding_32bit;
4537 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4540 if (!current_templates)
4543 /* See if we can get a match by trimming off a suffix. */
4546 case WORD_MNEM_SUFFIX:
4547 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4548 i.suffix = SHORT_MNEM_SUFFIX;
4551 case BYTE_MNEM_SUFFIX:
4552 case QWORD_MNEM_SUFFIX:
4553 i.suffix = mnem_p[-1];
4555 current_templates = (const templates *) hash_find (op_hash,
4558 case SHORT_MNEM_SUFFIX:
4559 case LONG_MNEM_SUFFIX:
4562 i.suffix = mnem_p[-1];
4564 current_templates = (const templates *) hash_find (op_hash,
4573 if (intel_float_operand (mnemonic) == 1)
4574 i.suffix = SHORT_MNEM_SUFFIX;
4576 i.suffix = LONG_MNEM_SUFFIX;
4578 current_templates = (const templates *) hash_find (op_hash,
4583 if (!current_templates)
4585 as_bad (_("no such instruction: `%s'"), token_start);
4590 if (current_templates->start->opcode_modifier.jump
4591 || current_templates->start->opcode_modifier.jumpbyte)
4593 /* Check for a branch hint. We allow ",pt" and ",pn" for
4594 predict taken and predict not taken respectively.
4595 I'm not sure that branch hints actually do anything on loop
4596 and jcxz insns (JumpByte) for current Pentium4 chips. They
4597 may work in the future and it doesn't hurt to accept them
4599 if (l[0] == ',' && l[1] == 'p')
4603 if (!add_prefix (DS_PREFIX_OPCODE))
4607 else if (l[2] == 'n')
4609 if (!add_prefix (CS_PREFIX_OPCODE))
4615 /* Any other comma loses. */
4618 as_bad (_("invalid character %s in mnemonic"),
4619 output_invalid (*l));
4623 /* Check if instruction is supported on specified architecture. */
4625 for (t = current_templates->start; t < current_templates->end; ++t)
4627 supported |= cpu_flags_match (t);
4628 if (supported == CPU_FLAGS_PERFECT_MATCH)
4630 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4631 as_warn (_("use .code16 to ensure correct addressing mode"));
4637 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4638 as_bad (flag_code == CODE_64BIT
4639 ? _("`%s' is not supported in 64-bit mode")
4640 : _("`%s' is only supported in 64-bit mode"),
4641 current_templates->start->name);
4643 as_bad (_("`%s' is not supported on `%s%s'"),
4644 current_templates->start->name,
4645 cpu_arch_name ? cpu_arch_name : default_arch,
4646 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4652 parse_operands (char *l, const char *mnemonic)
4656 /* 1 if operand is pending after ','. */
4657 unsigned int expecting_operand = 0;
4659 /* Non-zero if operand parens not balanced. */
4660 unsigned int paren_not_balanced;
4662 while (*l != END_OF_INSN)
4664 /* Skip optional white space before operand. */
4665 if (is_space_char (*l))
4667 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4669 as_bad (_("invalid character %s before operand %d"),
4670 output_invalid (*l),
4674 token_start = l; /* After white space. */
4675 paren_not_balanced = 0;
4676 while (paren_not_balanced || *l != ',')
4678 if (*l == END_OF_INSN)
4680 if (paren_not_balanced)
4683 as_bad (_("unbalanced parenthesis in operand %d."),
4686 as_bad (_("unbalanced brackets in operand %d."),
4691 break; /* we are done */
4693 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4695 as_bad (_("invalid character %s in operand %d"),
4696 output_invalid (*l),
4703 ++paren_not_balanced;
4705 --paren_not_balanced;
4710 ++paren_not_balanced;
4712 --paren_not_balanced;
4716 if (l != token_start)
4717 { /* Yes, we've read in another operand. */
4718 unsigned int operand_ok;
4719 this_operand = i.operands++;
4720 if (i.operands > MAX_OPERANDS)
4722 as_bad (_("spurious operands; (%d operands/instruction max)"),
4726 i.types[this_operand].bitfield.unspecified = 1;
4727 /* Now parse operand adding info to 'i' as we go along. */
4728 END_STRING_AND_SAVE (l);
4730 if (i.mem_operands > 1)
4732 as_bad (_("too many memory references for `%s'"),
4739 i386_intel_operand (token_start,
4740 intel_float_operand (mnemonic));
4742 operand_ok = i386_att_operand (token_start);
4744 RESTORE_END_STRING (l);
4750 if (expecting_operand)
4752 expecting_operand_after_comma:
4753 as_bad (_("expecting operand after ','; got nothing"));
4758 as_bad (_("expecting operand before ','; got nothing"));
4763 /* Now *l must be either ',' or END_OF_INSN. */
4766 if (*++l == END_OF_INSN)
4768 /* Just skip it, if it's \n complain. */
4769 goto expecting_operand_after_comma;
4771 expecting_operand = 1;
4778 swap_2_operands (int xchg1, int xchg2)
4780 union i386_op temp_op;
4781 i386_operand_type temp_type;
4782 unsigned int temp_flags;
4783 enum bfd_reloc_code_real temp_reloc;
4785 temp_type = i.types[xchg2];
4786 i.types[xchg2] = i.types[xchg1];
4787 i.types[xchg1] = temp_type;
4789 temp_flags = i.flags[xchg2];
4790 i.flags[xchg2] = i.flags[xchg1];
4791 i.flags[xchg1] = temp_flags;
4793 temp_op = i.op[xchg2];
4794 i.op[xchg2] = i.op[xchg1];
4795 i.op[xchg1] = temp_op;
4797 temp_reloc = i.reloc[xchg2];
4798 i.reloc[xchg2] = i.reloc[xchg1];
4799 i.reloc[xchg1] = temp_reloc;
4803 if (i.mask->operand == xchg1)
4804 i.mask->operand = xchg2;
4805 else if (i.mask->operand == xchg2)
4806 i.mask->operand = xchg1;
4810 if (i.broadcast->operand == xchg1)
4811 i.broadcast->operand = xchg2;
4812 else if (i.broadcast->operand == xchg2)
4813 i.broadcast->operand = xchg1;
4817 if (i.rounding->operand == xchg1)
4818 i.rounding->operand = xchg2;
4819 else if (i.rounding->operand == xchg2)
4820 i.rounding->operand = xchg1;
4825 swap_operands (void)
4831 swap_2_operands (1, i.operands - 2);
4835 swap_2_operands (0, i.operands - 1);
4841 if (i.mem_operands == 2)
4843 const seg_entry *temp_seg;
4844 temp_seg = i.seg[0];
4845 i.seg[0] = i.seg[1];
4846 i.seg[1] = temp_seg;
4850 /* Try to ensure constant immediates are represented in the smallest
4855 char guess_suffix = 0;
4859 guess_suffix = i.suffix;
4860 else if (i.reg_operands)
4862 /* Figure out a suffix from the last register operand specified.
4863 We can't do this properly yet, ie. excluding InOutPortReg,
4864 but the following works for instructions with immediates.
4865 In any case, we can't set i.suffix yet. */
4866 for (op = i.operands; --op >= 0;)
4867 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4869 guess_suffix = BYTE_MNEM_SUFFIX;
4872 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4874 guess_suffix = WORD_MNEM_SUFFIX;
4877 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4879 guess_suffix = LONG_MNEM_SUFFIX;
4882 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4884 guess_suffix = QWORD_MNEM_SUFFIX;
4888 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4889 guess_suffix = WORD_MNEM_SUFFIX;
4891 for (op = i.operands; --op >= 0;)
4892 if (operand_type_check (i.types[op], imm))
4894 switch (i.op[op].imms->X_op)
4897 /* If a suffix is given, this operand may be shortened. */
4898 switch (guess_suffix)
4900 case LONG_MNEM_SUFFIX:
4901 i.types[op].bitfield.imm32 = 1;
4902 i.types[op].bitfield.imm64 = 1;
4904 case WORD_MNEM_SUFFIX:
4905 i.types[op].bitfield.imm16 = 1;
4906 i.types[op].bitfield.imm32 = 1;
4907 i.types[op].bitfield.imm32s = 1;
4908 i.types[op].bitfield.imm64 = 1;
4910 case BYTE_MNEM_SUFFIX:
4911 i.types[op].bitfield.imm8 = 1;
4912 i.types[op].bitfield.imm8s = 1;
4913 i.types[op].bitfield.imm16 = 1;
4914 i.types[op].bitfield.imm32 = 1;
4915 i.types[op].bitfield.imm32s = 1;
4916 i.types[op].bitfield.imm64 = 1;
4920 /* If this operand is at most 16 bits, convert it
4921 to a signed 16 bit number before trying to see
4922 whether it will fit in an even smaller size.
4923 This allows a 16-bit operand such as $0xffe0 to
4924 be recognised as within Imm8S range. */
4925 if ((i.types[op].bitfield.imm16)
4926 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4928 i.op[op].imms->X_add_number =
4929 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4932 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4933 if ((i.types[op].bitfield.imm32)
4934 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4937 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4938 ^ ((offsetT) 1 << 31))
4939 - ((offsetT) 1 << 31));
4943 = operand_type_or (i.types[op],
4944 smallest_imm_type (i.op[op].imms->X_add_number));
4946 /* We must avoid matching of Imm32 templates when 64bit
4947 only immediate is available. */
4948 if (guess_suffix == QWORD_MNEM_SUFFIX)
4949 i.types[op].bitfield.imm32 = 0;
4956 /* Symbols and expressions. */
4958 /* Convert symbolic operand to proper sizes for matching, but don't
4959 prevent matching a set of insns that only supports sizes other
4960 than those matching the insn suffix. */
4962 i386_operand_type mask, allowed;
4963 const insn_template *t;
4965 operand_type_set (&mask, 0);
4966 operand_type_set (&allowed, 0);
4968 for (t = current_templates->start;
4969 t < current_templates->end;
4971 allowed = operand_type_or (allowed,
4972 t->operand_types[op]);
4973 switch (guess_suffix)
4975 case QWORD_MNEM_SUFFIX:
4976 mask.bitfield.imm64 = 1;
4977 mask.bitfield.imm32s = 1;
4979 case LONG_MNEM_SUFFIX:
4980 mask.bitfield.imm32 = 1;
4982 case WORD_MNEM_SUFFIX:
4983 mask.bitfield.imm16 = 1;
4985 case BYTE_MNEM_SUFFIX:
4986 mask.bitfield.imm8 = 1;
4991 allowed = operand_type_and (mask, allowed);
4992 if (!operand_type_all_zero (&allowed))
4993 i.types[op] = operand_type_and (i.types[op], mask);
5000 /* Try to use the smallest displacement type too. */
5002 optimize_disp (void)
5006 for (op = i.operands; --op >= 0;)
5007 if (operand_type_check (i.types[op], disp))
5009 if (i.op[op].disps->X_op == O_constant)
5011 offsetT op_disp = i.op[op].disps->X_add_number;
5013 if (i.types[op].bitfield.disp16
5014 && (op_disp & ~(offsetT) 0xffff) == 0)
5016 /* If this operand is at most 16 bits, convert
5017 to a signed 16 bit number and don't use 64bit
5019 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5020 i.types[op].bitfield.disp64 = 0;
5023 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5024 if (i.types[op].bitfield.disp32
5025 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5027 /* If this operand is at most 32 bits, convert
5028 to a signed 32 bit number and don't use 64bit
5030 op_disp &= (((offsetT) 2 << 31) - 1);
5031 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5032 i.types[op].bitfield.disp64 = 0;
5035 if (!op_disp && i.types[op].bitfield.baseindex)
5037 i.types[op].bitfield.disp8 = 0;
5038 i.types[op].bitfield.disp16 = 0;
5039 i.types[op].bitfield.disp32 = 0;
5040 i.types[op].bitfield.disp32s = 0;
5041 i.types[op].bitfield.disp64 = 0;
5045 else if (flag_code == CODE_64BIT)
5047 if (fits_in_signed_long (op_disp))
5049 i.types[op].bitfield.disp64 = 0;
5050 i.types[op].bitfield.disp32s = 1;
5052 if (i.prefix[ADDR_PREFIX]
5053 && fits_in_unsigned_long (op_disp))
5054 i.types[op].bitfield.disp32 = 1;
5056 if ((i.types[op].bitfield.disp32
5057 || i.types[op].bitfield.disp32s
5058 || i.types[op].bitfield.disp16)
5059 && fits_in_disp8 (op_disp))
5060 i.types[op].bitfield.disp8 = 1;
5062 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5063 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5065 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5066 i.op[op].disps, 0, i.reloc[op]);
5067 i.types[op].bitfield.disp8 = 0;
5068 i.types[op].bitfield.disp16 = 0;
5069 i.types[op].bitfield.disp32 = 0;
5070 i.types[op].bitfield.disp32s = 0;
5071 i.types[op].bitfield.disp64 = 0;
5074 /* We only support 64bit displacement on constants. */
5075 i.types[op].bitfield.disp64 = 0;
5079 /* Return 1 if there is a match in broadcast bytes between operand
5080 GIVEN and instruction template T. */
5083 match_broadcast_size (const insn_template *t, unsigned int given)
5085 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5086 && i.types[given].bitfield.byte)
5087 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5088 && i.types[given].bitfield.word)
5089 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5090 && i.types[given].bitfield.dword)
5091 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5092 && i.types[given].bitfield.qword));
5095 /* Check if operands are valid for the instruction. */
5098 check_VecOperands (const insn_template *t)
5102 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5104 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5105 any one operand are implicity requiring AVX512VL support if the actual
5106 operand size is YMMword or XMMword. Since this function runs after
5107 template matching, there's no need to check for YMMword/XMMword in
5109 cpu = cpu_flags_and (t->cpu_flags, avx512);
5110 if (!cpu_flags_all_zero (&cpu)
5111 && !t->cpu_flags.bitfield.cpuavx512vl
5112 && !cpu_arch_flags.bitfield.cpuavx512vl)
5114 for (op = 0; op < t->operands; ++op)
5116 if (t->operand_types[op].bitfield.zmmword
5117 && (i.types[op].bitfield.ymmword
5118 || i.types[op].bitfield.xmmword))
5120 i.error = unsupported;
5126 /* Without VSIB byte, we can't have a vector register for index. */
5127 if (!t->opcode_modifier.vecsib
5129 && (i.index_reg->reg_type.bitfield.xmmword
5130 || i.index_reg->reg_type.bitfield.ymmword
5131 || i.index_reg->reg_type.bitfield.zmmword))
5133 i.error = unsupported_vector_index_register;
5137 /* Check if default mask is allowed. */
5138 if (t->opcode_modifier.nodefmask
5139 && (!i.mask || i.mask->mask->reg_num == 0))
5141 i.error = no_default_mask;
5145 /* For VSIB byte, we need a vector register for index, and all vector
5146 registers must be distinct. */
5147 if (t->opcode_modifier.vecsib)
5150 || !((t->opcode_modifier.vecsib == VecSIB128
5151 && i.index_reg->reg_type.bitfield.xmmword)
5152 || (t->opcode_modifier.vecsib == VecSIB256
5153 && i.index_reg->reg_type.bitfield.ymmword)
5154 || (t->opcode_modifier.vecsib == VecSIB512
5155 && i.index_reg->reg_type.bitfield.zmmword)))
5157 i.error = invalid_vsib_address;
5161 gas_assert (i.reg_operands == 2 || i.mask);
5162 if (i.reg_operands == 2 && !i.mask)
5164 gas_assert (i.types[0].bitfield.regsimd);
5165 gas_assert (i.types[0].bitfield.xmmword
5166 || i.types[0].bitfield.ymmword);
5167 gas_assert (i.types[2].bitfield.regsimd);
5168 gas_assert (i.types[2].bitfield.xmmword
5169 || i.types[2].bitfield.ymmword);
5170 if (operand_check == check_none)
5172 if (register_number (i.op[0].regs)
5173 != register_number (i.index_reg)
5174 && register_number (i.op[2].regs)
5175 != register_number (i.index_reg)
5176 && register_number (i.op[0].regs)
5177 != register_number (i.op[2].regs))
5179 if (operand_check == check_error)
5181 i.error = invalid_vector_register_set;
5184 as_warn (_("mask, index, and destination registers should be distinct"));
5186 else if (i.reg_operands == 1 && i.mask)
5188 if (i.types[1].bitfield.regsimd
5189 && (i.types[1].bitfield.xmmword
5190 || i.types[1].bitfield.ymmword
5191 || i.types[1].bitfield.zmmword)
5192 && (register_number (i.op[1].regs)
5193 == register_number (i.index_reg)))
5195 if (operand_check == check_error)
5197 i.error = invalid_vector_register_set;
5200 if (operand_check != check_none)
5201 as_warn (_("index and destination registers should be distinct"));
5206 /* Check if broadcast is supported by the instruction and is applied
5207 to the memory operand. */
5210 i386_operand_type type, overlap;
5212 /* Check if specified broadcast is supported in this instruction,
5213 and its broadcast bytes match the memory operand. */
5214 op = i.broadcast->operand;
5215 if (!t->opcode_modifier.broadcast
5216 || !(i.flags[op] & Operand_Mem)
5217 || (!i.types[op].bitfield.unspecified
5218 && !match_broadcast_size (t, op)))
5221 i.error = unsupported_broadcast;
5225 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5226 * i.broadcast->type);
5227 operand_type_set (&type, 0);
5228 switch (i.broadcast->bytes)
5231 type.bitfield.word = 1;
5234 type.bitfield.dword = 1;
5237 type.bitfield.qword = 1;
5240 type.bitfield.xmmword = 1;
5243 type.bitfield.ymmword = 1;
5246 type.bitfield.zmmword = 1;
5252 overlap = operand_type_and (type, t->operand_types[op]);
5253 if (operand_type_all_zero (&overlap))
5256 if (t->opcode_modifier.checkregsize)
5260 type.bitfield.baseindex = 1;
5261 for (j = 0; j < i.operands; ++j)
5264 && !operand_type_register_match(i.types[j],
5265 t->operand_types[j],
5267 t->operand_types[op]))
5272 /* If broadcast is supported in this instruction, we need to check if
5273 operand of one-element size isn't specified without broadcast. */
5274 else if (t->opcode_modifier.broadcast && i.mem_operands)
5276 /* Find memory operand. */
5277 for (op = 0; op < i.operands; op++)
5278 if (operand_type_check (i.types[op], anymem))
5280 gas_assert (op < i.operands);
5281 /* Check size of the memory operand. */
5282 if (match_broadcast_size (t, op))
5284 i.error = broadcast_needed;
5289 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5291 /* Check if requested masking is supported. */
5294 switch (t->opcode_modifier.masking)
5298 case MERGING_MASKING:
5299 if (i.mask->zeroing)
5302 i.error = unsupported_masking;
5306 case DYNAMIC_MASKING:
5307 /* Memory destinations allow only merging masking. */
5308 if (i.mask->zeroing && i.mem_operands)
5310 /* Find memory operand. */
5311 for (op = 0; op < i.operands; op++)
5312 if (i.flags[op] & Operand_Mem)
5314 gas_assert (op < i.operands);
5315 if (op == i.operands - 1)
5317 i.error = unsupported_masking;
5327 /* Check if masking is applied to dest operand. */
5328 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5330 i.error = mask_not_on_destination;
5337 if ((i.rounding->type != saeonly
5338 && !t->opcode_modifier.staticrounding)
5339 || (i.rounding->type == saeonly
5340 && (t->opcode_modifier.staticrounding
5341 || !t->opcode_modifier.sae)))
5343 i.error = unsupported_rc_sae;
5346 /* If the instruction has several immediate operands and one of
5347 them is rounding, the rounding operand should be the last
5348 immediate operand. */
5349 if (i.imm_operands > 1
5350 && i.rounding->operand != (int) (i.imm_operands - 1))
5352 i.error = rc_sae_operand_not_last_imm;
5357 /* Check vector Disp8 operand. */
5358 if (t->opcode_modifier.disp8memshift
5359 && i.disp_encoding != disp_encoding_32bit)
5362 i.memshift = t->opcode_modifier.broadcast - 1;
5363 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5364 i.memshift = t->opcode_modifier.disp8memshift;
5367 const i386_operand_type *type = NULL;
5370 for (op = 0; op < i.operands; op++)
5371 if (operand_type_check (i.types[op], anymem))
5373 if (t->opcode_modifier.evex == EVEXLIG)
5374 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5375 else if (t->operand_types[op].bitfield.xmmword
5376 + t->operand_types[op].bitfield.ymmword
5377 + t->operand_types[op].bitfield.zmmword <= 1)
5378 type = &t->operand_types[op];
5379 else if (!i.types[op].bitfield.unspecified)
5380 type = &i.types[op];
5382 else if (i.types[op].bitfield.regsimd
5383 && t->opcode_modifier.evex != EVEXLIG)
5385 if (i.types[op].bitfield.zmmword)
5387 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5389 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5395 if (type->bitfield.zmmword)
5397 else if (type->bitfield.ymmword)
5399 else if (type->bitfield.xmmword)
5403 /* For the check in fits_in_disp8(). */
5404 if (i.memshift == 0)
5408 for (op = 0; op < i.operands; op++)
5409 if (operand_type_check (i.types[op], disp)
5410 && i.op[op].disps->X_op == O_constant)
5412 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5414 i.types[op].bitfield.disp8 = 1;
5417 i.types[op].bitfield.disp8 = 0;
5426 /* Check if operands are valid for the instruction. Update VEX
5430 VEX_check_operands (const insn_template *t)
5432 if (i.vec_encoding == vex_encoding_evex)
5434 /* This instruction must be encoded with EVEX prefix. */
5435 if (!is_evex_encoding (t))
5437 i.error = unsupported;
5443 if (!t->opcode_modifier.vex)
5445 /* This instruction template doesn't have VEX prefix. */
5446 if (i.vec_encoding != vex_encoding_default)
5448 i.error = unsupported;
5454 /* Only check VEX_Imm4, which must be the first operand. */
5455 if (t->operand_types[0].bitfield.vec_imm4)
5457 if (i.op[0].imms->X_op != O_constant
5458 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5464 /* Turn off Imm8 so that update_imm won't complain. */
5465 i.types[0] = vec_imm4;
5471 static const insn_template *
5472 match_template (char mnem_suffix)
5474 /* Points to template once we've found it. */
5475 const insn_template *t;
5476 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5477 i386_operand_type overlap4;
5478 unsigned int found_reverse_match;
5479 i386_opcode_modifier suffix_check, mnemsuf_check;
5480 i386_operand_type operand_types [MAX_OPERANDS];
5481 int addr_prefix_disp;
5483 unsigned int found_cpu_match, size_match;
5484 unsigned int check_register;
5485 enum i386_error specific_error = 0;
5487 #if MAX_OPERANDS != 5
5488 # error "MAX_OPERANDS must be 5."
5491 found_reverse_match = 0;
5492 addr_prefix_disp = -1;
5494 memset (&suffix_check, 0, sizeof (suffix_check));
5495 if (intel_syntax && i.broadcast)
5497 else if (i.suffix == BYTE_MNEM_SUFFIX)
5498 suffix_check.no_bsuf = 1;
5499 else if (i.suffix == WORD_MNEM_SUFFIX)
5500 suffix_check.no_wsuf = 1;
5501 else if (i.suffix == SHORT_MNEM_SUFFIX)
5502 suffix_check.no_ssuf = 1;
5503 else if (i.suffix == LONG_MNEM_SUFFIX)
5504 suffix_check.no_lsuf = 1;
5505 else if (i.suffix == QWORD_MNEM_SUFFIX)
5506 suffix_check.no_qsuf = 1;
5507 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5508 suffix_check.no_ldsuf = 1;
5510 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5513 switch (mnem_suffix)
5515 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5516 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5517 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5518 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5519 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5523 /* Must have right number of operands. */
5524 i.error = number_of_operands_mismatch;
5526 for (t = current_templates->start; t < current_templates->end; t++)
5528 addr_prefix_disp = -1;
5530 if (i.operands != t->operands)
5533 /* Check processor support. */
5534 i.error = unsupported;
5535 found_cpu_match = (cpu_flags_match (t)
5536 == CPU_FLAGS_PERFECT_MATCH);
5537 if (!found_cpu_match)
5540 /* Check AT&T mnemonic. */
5541 i.error = unsupported_with_intel_mnemonic;
5542 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5545 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5546 i.error = unsupported_syntax;
5547 if ((intel_syntax && t->opcode_modifier.attsyntax)
5548 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5549 || (intel64 && t->opcode_modifier.amd64)
5550 || (!intel64 && t->opcode_modifier.intel64))
5553 /* Check the suffix, except for some instructions in intel mode. */
5554 i.error = invalid_instruction_suffix;
5555 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5556 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5557 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5558 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5559 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5560 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5561 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5563 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5564 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5565 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5566 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5567 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5568 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5569 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5572 size_match = operand_size_match (t);
5576 for (j = 0; j < MAX_OPERANDS; j++)
5577 operand_types[j] = t->operand_types[j];
5579 /* In general, don't allow 64-bit operands in 32-bit mode. */
5580 if (i.suffix == QWORD_MNEM_SUFFIX
5581 && flag_code != CODE_64BIT
5583 ? (!t->opcode_modifier.ignoresize
5584 && !t->opcode_modifier.broadcast
5585 && !intel_float_operand (t->name))
5586 : intel_float_operand (t->name) != 2)
5587 && ((!operand_types[0].bitfield.regmmx
5588 && !operand_types[0].bitfield.regsimd)
5589 || (!operand_types[t->operands > 1].bitfield.regmmx
5590 && !operand_types[t->operands > 1].bitfield.regsimd))
5591 && (t->base_opcode != 0x0fc7
5592 || t->extension_opcode != 1 /* cmpxchg8b */))
5595 /* In general, don't allow 32-bit operands on pre-386. */
5596 else if (i.suffix == LONG_MNEM_SUFFIX
5597 && !cpu_arch_flags.bitfield.cpui386
5599 ? (!t->opcode_modifier.ignoresize
5600 && !intel_float_operand (t->name))
5601 : intel_float_operand (t->name) != 2)
5602 && ((!operand_types[0].bitfield.regmmx
5603 && !operand_types[0].bitfield.regsimd)
5604 || (!operand_types[t->operands > 1].bitfield.regmmx
5605 && !operand_types[t->operands > 1].bitfield.regsimd)))
5608 /* Do not verify operands when there are none. */
5612 /* We've found a match; break out of loop. */
5616 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5617 into Disp32/Disp16/Disp32 operand. */
5618 if (i.prefix[ADDR_PREFIX] != 0)
5620 /* There should be only one Disp operand. */
5624 for (j = 0; j < MAX_OPERANDS; j++)
5626 if (operand_types[j].bitfield.disp16)
5628 addr_prefix_disp = j;
5629 operand_types[j].bitfield.disp32 = 1;
5630 operand_types[j].bitfield.disp16 = 0;
5636 for (j = 0; j < MAX_OPERANDS; j++)
5638 if (operand_types[j].bitfield.disp32)
5640 addr_prefix_disp = j;
5641 operand_types[j].bitfield.disp32 = 0;
5642 operand_types[j].bitfield.disp16 = 1;
5648 for (j = 0; j < MAX_OPERANDS; j++)
5650 if (operand_types[j].bitfield.disp64)
5652 addr_prefix_disp = j;
5653 operand_types[j].bitfield.disp64 = 0;
5654 operand_types[j].bitfield.disp32 = 1;
5662 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5663 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5666 /* We check register size if needed. */
5667 if (t->opcode_modifier.checkregsize)
5669 check_register = (1 << t->operands) - 1;
5671 check_register &= ~(1 << i.broadcast->operand);
5676 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5677 switch (t->operands)
5680 if (!operand_type_match (overlap0, i.types[0]))
5684 /* xchg %eax, %eax is a special case. It is an alias for nop
5685 only in 32bit mode and we can use opcode 0x90. In 64bit
5686 mode, we can't use 0x90 for xchg %eax, %eax since it should
5687 zero-extend %eax to %rax. */
5688 if (flag_code == CODE_64BIT
5689 && t->base_opcode == 0x90
5690 && operand_type_equal (&i.types [0], &acc32)
5691 && operand_type_equal (&i.types [1], &acc32))
5693 /* xrelease mov %eax, <disp> is another special case. It must not
5694 match the accumulator-only encoding of mov. */
5695 if (flag_code != CODE_64BIT
5697 && t->base_opcode == 0xa0
5698 && i.types[0].bitfield.acc
5699 && operand_type_check (i.types[1], anymem))
5701 if (!(size_match & MATCH_STRAIGHT))
5703 /* If we want store form, we reverse direction of operands. */
5704 if (i.dir_encoding == dir_encoding_store
5705 && t->opcode_modifier.d)
5710 /* If we want store form, we skip the current load. */
5711 if (i.dir_encoding == dir_encoding_store
5712 && i.mem_operands == 0
5713 && t->opcode_modifier.load)
5718 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5719 if (!operand_type_match (overlap0, i.types[0])
5720 || !operand_type_match (overlap1, i.types[1])
5721 || ((check_register & 3) == 3
5722 && !operand_type_register_match (i.types[0],
5727 /* Check if other direction is valid ... */
5728 if (!t->opcode_modifier.d)
5732 if (!(size_match & MATCH_REVERSE))
5734 /* Try reversing direction of operands. */
5735 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5736 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5737 if (!operand_type_match (overlap0, i.types[0])
5738 || !operand_type_match (overlap1, i.types[1])
5740 && !operand_type_register_match (i.types[0],
5745 /* Does not match either direction. */
5748 /* found_reverse_match holds which of D or FloatR
5750 if (!t->opcode_modifier.d)
5751 found_reverse_match = 0;
5752 else if (operand_types[0].bitfield.tbyte)
5753 found_reverse_match = Opcode_FloatD;
5755 found_reverse_match = Opcode_D;
5756 if (t->opcode_modifier.floatr)
5757 found_reverse_match |= Opcode_FloatR;
5761 /* Found a forward 2 operand match here. */
5762 switch (t->operands)
5765 overlap4 = operand_type_and (i.types[4],
5769 overlap3 = operand_type_and (i.types[3],
5773 overlap2 = operand_type_and (i.types[2],
5778 switch (t->operands)
5781 if (!operand_type_match (overlap4, i.types[4])
5782 || !operand_type_register_match (i.types[3],
5789 if (!operand_type_match (overlap3, i.types[3])
5790 || ((check_register & 0xa) == 0xa
5791 && !operand_type_register_match (i.types[1],
5795 || ((check_register & 0xc) == 0xc
5796 && !operand_type_register_match (i.types[2],
5803 /* Here we make use of the fact that there are no
5804 reverse match 3 operand instructions. */
5805 if (!operand_type_match (overlap2, i.types[2])
5806 || ((check_register & 5) == 5
5807 && !operand_type_register_match (i.types[0],
5811 || ((check_register & 6) == 6
5812 && !operand_type_register_match (i.types[1],
5820 /* Found either forward/reverse 2, 3 or 4 operand match here:
5821 slip through to break. */
5823 if (!found_cpu_match)
5825 found_reverse_match = 0;
5829 /* Check if vector and VEX operands are valid. */
5830 if (check_VecOperands (t) || VEX_check_operands (t))
5832 specific_error = i.error;
5836 /* We've found a match; break out of loop. */
5840 if (t == current_templates->end)
5842 /* We found no match. */
5843 const char *err_msg;
5844 switch (specific_error ? specific_error : i.error)
5848 case operand_size_mismatch:
5849 err_msg = _("operand size mismatch");
5851 case operand_type_mismatch:
5852 err_msg = _("operand type mismatch");
5854 case register_type_mismatch:
5855 err_msg = _("register type mismatch");
5857 case number_of_operands_mismatch:
5858 err_msg = _("number of operands mismatch");
5860 case invalid_instruction_suffix:
5861 err_msg = _("invalid instruction suffix");
5864 err_msg = _("constant doesn't fit in 4 bits");
5866 case unsupported_with_intel_mnemonic:
5867 err_msg = _("unsupported with Intel mnemonic");
5869 case unsupported_syntax:
5870 err_msg = _("unsupported syntax");
5873 as_bad (_("unsupported instruction `%s'"),
5874 current_templates->start->name);
5876 case invalid_vsib_address:
5877 err_msg = _("invalid VSIB address");
5879 case invalid_vector_register_set:
5880 err_msg = _("mask, index, and destination registers must be distinct");
5882 case unsupported_vector_index_register:
5883 err_msg = _("unsupported vector index register");
5885 case unsupported_broadcast:
5886 err_msg = _("unsupported broadcast");
5888 case broadcast_needed:
5889 err_msg = _("broadcast is needed for operand of such type");
5891 case unsupported_masking:
5892 err_msg = _("unsupported masking");
5894 case mask_not_on_destination:
5895 err_msg = _("mask not on destination operand");
5897 case no_default_mask:
5898 err_msg = _("default mask isn't allowed");
5900 case unsupported_rc_sae:
5901 err_msg = _("unsupported static rounding/sae");
5903 case rc_sae_operand_not_last_imm:
5905 err_msg = _("RC/SAE operand must precede immediate operands");
5907 err_msg = _("RC/SAE operand must follow immediate operands");
5909 case invalid_register_operand:
5910 err_msg = _("invalid register operand");
5913 as_bad (_("%s for `%s'"), err_msg,
5914 current_templates->start->name);
5918 if (!quiet_warnings)
5921 && (i.types[0].bitfield.jumpabsolute
5922 != operand_types[0].bitfield.jumpabsolute))
5924 as_warn (_("indirect %s without `*'"), t->name);
5927 if (t->opcode_modifier.isprefix
5928 && t->opcode_modifier.ignoresize)
5930 /* Warn them that a data or address size prefix doesn't
5931 affect assembly of the next line of code. */
5932 as_warn (_("stand-alone `%s' prefix"), t->name);
5936 /* Copy the template we found. */
5939 if (addr_prefix_disp != -1)
5940 i.tm.operand_types[addr_prefix_disp]
5941 = operand_types[addr_prefix_disp];
5943 if (found_reverse_match)
5945 /* If we found a reverse match we must alter the opcode
5946 direction bit. found_reverse_match holds bits to change
5947 (different for int & float insns). */
5949 i.tm.base_opcode ^= found_reverse_match;
5951 i.tm.operand_types[0] = operand_types[1];
5952 i.tm.operand_types[1] = operand_types[0];
5961 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5962 if (i.tm.operand_types[mem_op].bitfield.esseg)
5964 if (i.seg[0] != NULL && i.seg[0] != &es)
5966 as_bad (_("`%s' operand %d must use `%ses' segment"),
5972 /* There's only ever one segment override allowed per instruction.
5973 This instruction possibly has a legal segment override on the
5974 second operand, so copy the segment to where non-string
5975 instructions store it, allowing common code. */
5976 i.seg[0] = i.seg[1];
5978 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5980 if (i.seg[1] != NULL && i.seg[1] != &es)
5982 as_bad (_("`%s' operand %d must use `%ses' segment"),
5993 process_suffix (void)
5995 /* If matched instruction specifies an explicit instruction mnemonic
5997 if (i.tm.opcode_modifier.size16)
5998 i.suffix = WORD_MNEM_SUFFIX;
5999 else if (i.tm.opcode_modifier.size32)
6000 i.suffix = LONG_MNEM_SUFFIX;
6001 else if (i.tm.opcode_modifier.size64)
6002 i.suffix = QWORD_MNEM_SUFFIX;
6003 else if (i.reg_operands)
6005 /* If there's no instruction mnemonic suffix we try to invent one
6006 based on register operands. */
6009 /* We take i.suffix from the last register operand specified,
6010 Destination register type is more significant than source
6011 register type. crc32 in SSE4.2 prefers source register
6013 if (i.tm.base_opcode == 0xf20f38f1)
6015 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
6016 i.suffix = WORD_MNEM_SUFFIX;
6017 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
6018 i.suffix = LONG_MNEM_SUFFIX;
6019 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
6020 i.suffix = QWORD_MNEM_SUFFIX;
6022 else if (i.tm.base_opcode == 0xf20f38f0)
6024 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
6025 i.suffix = BYTE_MNEM_SUFFIX;
6032 if (i.tm.base_opcode == 0xf20f38f1
6033 || i.tm.base_opcode == 0xf20f38f0)
6035 /* We have to know the operand size for crc32. */
6036 as_bad (_("ambiguous memory operand size for `%s`"),
6041 for (op = i.operands; --op >= 0;)
6042 if (!i.tm.operand_types[op].bitfield.inoutportreg
6043 && !i.tm.operand_types[op].bitfield.shiftcount)
6045 if (!i.types[op].bitfield.reg)
6047 if (i.types[op].bitfield.byte)
6048 i.suffix = BYTE_MNEM_SUFFIX;
6049 else if (i.types[op].bitfield.word)
6050 i.suffix = WORD_MNEM_SUFFIX;
6051 else if (i.types[op].bitfield.dword)
6052 i.suffix = LONG_MNEM_SUFFIX;
6053 else if (i.types[op].bitfield.qword)
6054 i.suffix = QWORD_MNEM_SUFFIX;
6061 else if (i.suffix == BYTE_MNEM_SUFFIX)
6064 && i.tm.opcode_modifier.ignoresize
6065 && i.tm.opcode_modifier.no_bsuf)
6067 else if (!check_byte_reg ())
6070 else if (i.suffix == LONG_MNEM_SUFFIX)
6073 && i.tm.opcode_modifier.ignoresize
6074 && i.tm.opcode_modifier.no_lsuf
6075 && !i.tm.opcode_modifier.todword
6076 && !i.tm.opcode_modifier.toqword)
6078 else if (!check_long_reg ())
6081 else if (i.suffix == QWORD_MNEM_SUFFIX)
6084 && i.tm.opcode_modifier.ignoresize
6085 && i.tm.opcode_modifier.no_qsuf
6086 && !i.tm.opcode_modifier.todword
6087 && !i.tm.opcode_modifier.toqword)
6089 else if (!check_qword_reg ())
6092 else if (i.suffix == WORD_MNEM_SUFFIX)
6095 && i.tm.opcode_modifier.ignoresize
6096 && i.tm.opcode_modifier.no_wsuf)
6098 else if (!check_word_reg ())
6101 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6102 /* Do nothing if the instruction is going to ignore the prefix. */
6107 else if (i.tm.opcode_modifier.defaultsize
6109 /* exclude fldenv/frstor/fsave/fstenv */
6110 && i.tm.opcode_modifier.no_ssuf)
6112 i.suffix = stackop_size;
6114 else if (intel_syntax
6116 && (i.tm.operand_types[0].bitfield.jumpabsolute
6117 || i.tm.opcode_modifier.jumpbyte
6118 || i.tm.opcode_modifier.jumpintersegment
6119 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6120 && i.tm.extension_opcode <= 3)))
6125 if (!i.tm.opcode_modifier.no_qsuf)
6127 i.suffix = QWORD_MNEM_SUFFIX;
6132 if (!i.tm.opcode_modifier.no_lsuf)
6133 i.suffix = LONG_MNEM_SUFFIX;
6136 if (!i.tm.opcode_modifier.no_wsuf)
6137 i.suffix = WORD_MNEM_SUFFIX;
6146 if (i.tm.opcode_modifier.w)
6148 as_bad (_("no instruction mnemonic suffix given and "
6149 "no register operands; can't size instruction"));
6155 unsigned int suffixes;
6157 suffixes = !i.tm.opcode_modifier.no_bsuf;
6158 if (!i.tm.opcode_modifier.no_wsuf)
6160 if (!i.tm.opcode_modifier.no_lsuf)
6162 if (!i.tm.opcode_modifier.no_ldsuf)
6164 if (!i.tm.opcode_modifier.no_ssuf)
6166 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6169 /* There are more than suffix matches. */
6170 if (i.tm.opcode_modifier.w
6171 || ((suffixes & (suffixes - 1))
6172 && !i.tm.opcode_modifier.defaultsize
6173 && !i.tm.opcode_modifier.ignoresize))
6175 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6181 /* Change the opcode based on the operand size given by i.suffix. */
6184 /* Size floating point instruction. */
6185 case LONG_MNEM_SUFFIX:
6186 if (i.tm.opcode_modifier.floatmf)
6188 i.tm.base_opcode ^= 4;
6192 case WORD_MNEM_SUFFIX:
6193 case QWORD_MNEM_SUFFIX:
6194 /* It's not a byte, select word/dword operation. */
6195 if (i.tm.opcode_modifier.w)
6197 if (i.tm.opcode_modifier.shortform)
6198 i.tm.base_opcode |= 8;
6200 i.tm.base_opcode |= 1;
6203 case SHORT_MNEM_SUFFIX:
6204 /* Now select between word & dword operations via the operand
6205 size prefix, except for instructions that will ignore this
6207 if (i.reg_operands > 0
6208 && i.types[0].bitfield.reg
6209 && i.tm.opcode_modifier.addrprefixopreg
6210 && (i.tm.opcode_modifier.immext
6211 || i.operands == 1))
6213 /* The address size override prefix changes the size of the
6215 if ((flag_code == CODE_32BIT
6216 && i.op[0].regs->reg_type.bitfield.word)
6217 || (flag_code != CODE_32BIT
6218 && i.op[0].regs->reg_type.bitfield.dword))
6219 if (!add_prefix (ADDR_PREFIX_OPCODE))
6222 else if (i.suffix != QWORD_MNEM_SUFFIX
6223 && !i.tm.opcode_modifier.ignoresize
6224 && !i.tm.opcode_modifier.floatmf
6225 && !i.tm.opcode_modifier.vex
6226 && !i.tm.opcode_modifier.vexopcode
6227 && !is_evex_encoding (&i.tm)
6228 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6229 || (flag_code == CODE_64BIT
6230 && i.tm.opcode_modifier.jumpbyte)))
6232 unsigned int prefix = DATA_PREFIX_OPCODE;
6234 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6235 prefix = ADDR_PREFIX_OPCODE;
6237 if (!add_prefix (prefix))
6241 /* Set mode64 for an operand. */
6242 if (i.suffix == QWORD_MNEM_SUFFIX
6243 && flag_code == CODE_64BIT
6244 && !i.tm.opcode_modifier.norex64
6245 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6247 && ! (i.operands == 2
6248 && i.tm.base_opcode == 0x90
6249 && i.tm.extension_opcode == None
6250 && operand_type_equal (&i.types [0], &acc64)
6251 && operand_type_equal (&i.types [1], &acc64)))
6257 if (i.reg_operands != 0
6259 && i.tm.opcode_modifier.addrprefixopreg
6260 && !i.tm.opcode_modifier.immext)
6262 /* Check invalid register operand when the address size override
6263 prefix changes the size of register operands. */
6265 enum { need_word, need_dword, need_qword } need;
6267 if (flag_code == CODE_32BIT)
6268 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6271 if (i.prefix[ADDR_PREFIX])
6274 need = flag_code == CODE_64BIT ? need_qword : need_word;
6277 for (op = 0; op < i.operands; op++)
6278 if (i.types[op].bitfield.reg
6279 && ((need == need_word
6280 && !i.op[op].regs->reg_type.bitfield.word)
6281 || (need == need_dword
6282 && !i.op[op].regs->reg_type.bitfield.dword)
6283 || (need == need_qword
6284 && !i.op[op].regs->reg_type.bitfield.qword)))
6286 as_bad (_("invalid register operand size for `%s'"),
6296 check_byte_reg (void)
6300 for (op = i.operands; --op >= 0;)
6302 /* Skip non-register operands. */
6303 if (!i.types[op].bitfield.reg)
6306 /* If this is an eight bit register, it's OK. If it's the 16 or
6307 32 bit version of an eight bit register, we will just use the
6308 low portion, and that's OK too. */
6309 if (i.types[op].bitfield.byte)
6312 /* I/O port address operands are OK too. */
6313 if (i.tm.operand_types[op].bitfield.inoutportreg)
6316 /* crc32 doesn't generate this warning. */
6317 if (i.tm.base_opcode == 0xf20f38f0)
6320 if ((i.types[op].bitfield.word
6321 || i.types[op].bitfield.dword
6322 || i.types[op].bitfield.qword)
6323 && i.op[op].regs->reg_num < 4
6324 /* Prohibit these changes in 64bit mode, since the lowering
6325 would be more complicated. */
6326 && flag_code != CODE_64BIT)
6328 #if REGISTER_WARNINGS
6329 if (!quiet_warnings)
6330 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6332 (i.op[op].regs + (i.types[op].bitfield.word
6333 ? REGNAM_AL - REGNAM_AX
6334 : REGNAM_AL - REGNAM_EAX))->reg_name,
6336 i.op[op].regs->reg_name,
6341 /* Any other register is bad. */
6342 if (i.types[op].bitfield.reg
6343 || i.types[op].bitfield.regmmx
6344 || i.types[op].bitfield.regsimd
6345 || i.types[op].bitfield.sreg2
6346 || i.types[op].bitfield.sreg3
6347 || i.types[op].bitfield.control
6348 || i.types[op].bitfield.debug
6349 || i.types[op].bitfield.test)
6351 as_bad (_("`%s%s' not allowed with `%s%c'"),
6353 i.op[op].regs->reg_name,
6363 check_long_reg (void)
6367 for (op = i.operands; --op >= 0;)
6368 /* Skip non-register operands. */
6369 if (!i.types[op].bitfield.reg)
6371 /* Reject eight bit registers, except where the template requires
6372 them. (eg. movzb) */
6373 else if (i.types[op].bitfield.byte
6374 && (i.tm.operand_types[op].bitfield.reg
6375 || i.tm.operand_types[op].bitfield.acc)
6376 && (i.tm.operand_types[op].bitfield.word
6377 || i.tm.operand_types[op].bitfield.dword))
6379 as_bad (_("`%s%s' not allowed with `%s%c'"),
6381 i.op[op].regs->reg_name,
6386 /* Warn if the e prefix on a general reg is missing. */
6387 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6388 && i.types[op].bitfield.word
6389 && (i.tm.operand_types[op].bitfield.reg
6390 || i.tm.operand_types[op].bitfield.acc)
6391 && i.tm.operand_types[op].bitfield.dword)
6393 /* Prohibit these changes in the 64bit mode, since the
6394 lowering is more complicated. */
6395 if (flag_code == CODE_64BIT)
6397 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6398 register_prefix, i.op[op].regs->reg_name,
6402 #if REGISTER_WARNINGS
6403 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6405 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6406 register_prefix, i.op[op].regs->reg_name, i.suffix);
6409 /* Warn if the r prefix on a general reg is present. */
6410 else if (i.types[op].bitfield.qword
6411 && (i.tm.operand_types[op].bitfield.reg
6412 || i.tm.operand_types[op].bitfield.acc)
6413 && i.tm.operand_types[op].bitfield.dword)
6416 && i.tm.opcode_modifier.toqword
6417 && !i.types[0].bitfield.regsimd)
6419 /* Convert to QWORD. We want REX byte. */
6420 i.suffix = QWORD_MNEM_SUFFIX;
6424 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6425 register_prefix, i.op[op].regs->reg_name,
6434 check_qword_reg (void)
6438 for (op = i.operands; --op >= 0; )
6439 /* Skip non-register operands. */
6440 if (!i.types[op].bitfield.reg)
6442 /* Reject eight bit registers, except where the template requires
6443 them. (eg. movzb) */
6444 else if (i.types[op].bitfield.byte
6445 && (i.tm.operand_types[op].bitfield.reg
6446 || i.tm.operand_types[op].bitfield.acc)
6447 && (i.tm.operand_types[op].bitfield.word
6448 || i.tm.operand_types[op].bitfield.dword))
6450 as_bad (_("`%s%s' not allowed with `%s%c'"),
6452 i.op[op].regs->reg_name,
6457 /* Warn if the r prefix on a general reg is missing. */
6458 else if ((i.types[op].bitfield.word
6459 || i.types[op].bitfield.dword)
6460 && (i.tm.operand_types[op].bitfield.reg
6461 || i.tm.operand_types[op].bitfield.acc)
6462 && i.tm.operand_types[op].bitfield.qword)
6464 /* Prohibit these changes in the 64bit mode, since the
6465 lowering is more complicated. */
6467 && i.tm.opcode_modifier.todword
6468 && !i.types[0].bitfield.regsimd)
6470 /* Convert to DWORD. We don't want REX byte. */
6471 i.suffix = LONG_MNEM_SUFFIX;
6475 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6476 register_prefix, i.op[op].regs->reg_name,
6485 check_word_reg (void)
6488 for (op = i.operands; --op >= 0;)
6489 /* Skip non-register operands. */
6490 if (!i.types[op].bitfield.reg)
6492 /* Reject eight bit registers, except where the template requires
6493 them. (eg. movzb) */
6494 else if (i.types[op].bitfield.byte
6495 && (i.tm.operand_types[op].bitfield.reg
6496 || i.tm.operand_types[op].bitfield.acc)
6497 && (i.tm.operand_types[op].bitfield.word
6498 || i.tm.operand_types[op].bitfield.dword))
6500 as_bad (_("`%s%s' not allowed with `%s%c'"),
6502 i.op[op].regs->reg_name,
6507 /* Warn if the e or r prefix on a general reg is present. */
6508 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6509 && (i.types[op].bitfield.dword
6510 || i.types[op].bitfield.qword)
6511 && (i.tm.operand_types[op].bitfield.reg
6512 || i.tm.operand_types[op].bitfield.acc)
6513 && i.tm.operand_types[op].bitfield.word)
6515 /* Prohibit these changes in the 64bit mode, since the
6516 lowering is more complicated. */
6517 if (flag_code == CODE_64BIT)
6519 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6520 register_prefix, i.op[op].regs->reg_name,
6524 #if REGISTER_WARNINGS
6525 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6527 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6528 register_prefix, i.op[op].regs->reg_name, i.suffix);
6535 update_imm (unsigned int j)
6537 i386_operand_type overlap = i.types[j];
6538 if ((overlap.bitfield.imm8
6539 || overlap.bitfield.imm8s
6540 || overlap.bitfield.imm16
6541 || overlap.bitfield.imm32
6542 || overlap.bitfield.imm32s
6543 || overlap.bitfield.imm64)
6544 && !operand_type_equal (&overlap, &imm8)
6545 && !operand_type_equal (&overlap, &imm8s)
6546 && !operand_type_equal (&overlap, &imm16)
6547 && !operand_type_equal (&overlap, &imm32)
6548 && !operand_type_equal (&overlap, &imm32s)
6549 && !operand_type_equal (&overlap, &imm64))
6553 i386_operand_type temp;
6555 operand_type_set (&temp, 0);
6556 if (i.suffix == BYTE_MNEM_SUFFIX)
6558 temp.bitfield.imm8 = overlap.bitfield.imm8;
6559 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6561 else if (i.suffix == WORD_MNEM_SUFFIX)
6562 temp.bitfield.imm16 = overlap.bitfield.imm16;
6563 else if (i.suffix == QWORD_MNEM_SUFFIX)
6565 temp.bitfield.imm64 = overlap.bitfield.imm64;
6566 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6569 temp.bitfield.imm32 = overlap.bitfield.imm32;
6572 else if (operand_type_equal (&overlap, &imm16_32_32s)
6573 || operand_type_equal (&overlap, &imm16_32)
6574 || operand_type_equal (&overlap, &imm16_32s))
6576 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6581 if (!operand_type_equal (&overlap, &imm8)
6582 && !operand_type_equal (&overlap, &imm8s)
6583 && !operand_type_equal (&overlap, &imm16)
6584 && !operand_type_equal (&overlap, &imm32)
6585 && !operand_type_equal (&overlap, &imm32s)
6586 && !operand_type_equal (&overlap, &imm64))
6588 as_bad (_("no instruction mnemonic suffix given; "
6589 "can't determine immediate size"));
6593 i.types[j] = overlap;
6603 /* Update the first 2 immediate operands. */
6604 n = i.operands > 2 ? 2 : i.operands;
6607 for (j = 0; j < n; j++)
6608 if (update_imm (j) == 0)
6611 /* The 3rd operand can't be immediate operand. */
6612 gas_assert (operand_type_check (i.types[2], imm) == 0);
6619 process_operands (void)
6621 /* Default segment register this instruction will use for memory
6622 accesses. 0 means unknown. This is only for optimizing out
6623 unnecessary segment overrides. */
6624 const seg_entry *default_seg = 0;
6626 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6628 unsigned int dupl = i.operands;
6629 unsigned int dest = dupl - 1;
6632 /* The destination must be an xmm register. */
6633 gas_assert (i.reg_operands
6634 && MAX_OPERANDS > dupl
6635 && operand_type_equal (&i.types[dest], ®xmm));
6637 if (i.tm.operand_types[0].bitfield.acc
6638 && i.tm.operand_types[0].bitfield.xmmword)
6640 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6642 /* Keep xmm0 for instructions with VEX prefix and 3
6644 i.tm.operand_types[0].bitfield.acc = 0;
6645 i.tm.operand_types[0].bitfield.regsimd = 1;
6650 /* We remove the first xmm0 and keep the number of
6651 operands unchanged, which in fact duplicates the
6653 for (j = 1; j < i.operands; j++)
6655 i.op[j - 1] = i.op[j];
6656 i.types[j - 1] = i.types[j];
6657 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6661 else if (i.tm.opcode_modifier.implicit1stxmm0)
6663 gas_assert ((MAX_OPERANDS - 1) > dupl
6664 && (i.tm.opcode_modifier.vexsources
6667 /* Add the implicit xmm0 for instructions with VEX prefix
6669 for (j = i.operands; j > 0; j--)
6671 i.op[j] = i.op[j - 1];
6672 i.types[j] = i.types[j - 1];
6673 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6676 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6677 i.types[0] = regxmm;
6678 i.tm.operand_types[0] = regxmm;
6681 i.reg_operands += 2;
6686 i.op[dupl] = i.op[dest];
6687 i.types[dupl] = i.types[dest];
6688 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6697 i.op[dupl] = i.op[dest];
6698 i.types[dupl] = i.types[dest];
6699 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6702 if (i.tm.opcode_modifier.immext)
6705 else if (i.tm.operand_types[0].bitfield.acc
6706 && i.tm.operand_types[0].bitfield.xmmword)
6710 for (j = 1; j < i.operands; j++)
6712 i.op[j - 1] = i.op[j];
6713 i.types[j - 1] = i.types[j];
6715 /* We need to adjust fields in i.tm since they are used by
6716 build_modrm_byte. */
6717 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6724 else if (i.tm.opcode_modifier.implicitquadgroup)
6726 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6728 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6729 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6730 regnum = register_number (i.op[1].regs);
6731 first_reg_in_group = regnum & ~3;
6732 last_reg_in_group = first_reg_in_group + 3;
6733 if (regnum != first_reg_in_group)
6734 as_warn (_("source register `%s%s' implicitly denotes"
6735 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6736 register_prefix, i.op[1].regs->reg_name,
6737 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6738 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6741 else if (i.tm.opcode_modifier.regkludge)
6743 /* The imul $imm, %reg instruction is converted into
6744 imul $imm, %reg, %reg, and the clr %reg instruction
6745 is converted into xor %reg, %reg. */
6747 unsigned int first_reg_op;
6749 if (operand_type_check (i.types[0], reg))
6753 /* Pretend we saw the extra register operand. */
6754 gas_assert (i.reg_operands == 1
6755 && i.op[first_reg_op + 1].regs == 0);
6756 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6757 i.types[first_reg_op + 1] = i.types[first_reg_op];
6762 if (i.tm.opcode_modifier.shortform)
6764 if (i.types[0].bitfield.sreg2
6765 || i.types[0].bitfield.sreg3)
6767 if (i.tm.base_opcode == POP_SEG_SHORT
6768 && i.op[0].regs->reg_num == 1)
6770 as_bad (_("you can't `pop %scs'"), register_prefix);
6773 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6774 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6779 /* The register or float register operand is in operand
6783 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6784 || operand_type_check (i.types[0], reg))
6788 /* Register goes in low 3 bits of opcode. */
6789 i.tm.base_opcode |= i.op[op].regs->reg_num;
6790 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6792 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6794 /* Warn about some common errors, but press on regardless.
6795 The first case can be generated by gcc (<= 2.8.1). */
6796 if (i.operands == 2)
6798 /* Reversed arguments on faddp, fsubp, etc. */
6799 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6800 register_prefix, i.op[!intel_syntax].regs->reg_name,
6801 register_prefix, i.op[intel_syntax].regs->reg_name);
6805 /* Extraneous `l' suffix on fp insn. */
6806 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6807 register_prefix, i.op[0].regs->reg_name);
6812 else if (i.tm.opcode_modifier.modrm)
6814 /* The opcode is completed (modulo i.tm.extension_opcode which
6815 must be put into the modrm byte). Now, we make the modrm and
6816 index base bytes based on all the info we've collected. */
6818 default_seg = build_modrm_byte ();
6820 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6824 else if (i.tm.opcode_modifier.isstring)
6826 /* For the string instructions that allow a segment override
6827 on one of their operands, the default segment is ds. */
6831 if (i.tm.base_opcode == 0x8d /* lea */
6834 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6836 /* If a segment was explicitly specified, and the specified segment
6837 is not the default, use an opcode prefix to select it. If we
6838 never figured out what the default segment is, then default_seg
6839 will be zero at this point, and the specified segment prefix will
6841 if ((i.seg[0]) && (i.seg[0] != default_seg))
6843 if (!add_prefix (i.seg[0]->seg_prefix))
6849 static const seg_entry *
6850 build_modrm_byte (void)
6852 const seg_entry *default_seg = 0;
6853 unsigned int source, dest;
6856 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6859 unsigned int nds, reg_slot;
6862 dest = i.operands - 1;
6865 /* There are 2 kinds of instructions:
6866 1. 5 operands: 4 register operands or 3 register operands
6867 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6868 VexW0 or VexW1. The destination must be either XMM, YMM or
6870 2. 4 operands: 4 register operands or 3 register operands
6871 plus 1 memory operand, with VexXDS. */
6872 gas_assert ((i.reg_operands == 4
6873 || (i.reg_operands == 3 && i.mem_operands == 1))
6874 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6875 && i.tm.opcode_modifier.vexw
6876 && i.tm.operand_types[dest].bitfield.regsimd);
6878 /* If VexW1 is set, the first non-immediate operand is the source and
6879 the second non-immediate one is encoded in the immediate operand. */
6880 if (i.tm.opcode_modifier.vexw == VEXW1)
6882 source = i.imm_operands;
6883 reg_slot = i.imm_operands + 1;
6887 source = i.imm_operands + 1;
6888 reg_slot = i.imm_operands;
6891 if (i.imm_operands == 0)
6893 /* When there is no immediate operand, generate an 8bit
6894 immediate operand to encode the first operand. */
6895 exp = &im_expressions[i.imm_operands++];
6896 i.op[i.operands].imms = exp;
6897 i.types[i.operands] = imm8;
6900 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6901 exp->X_op = O_constant;
6902 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6903 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6907 unsigned int imm_slot;
6909 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6911 if (i.tm.opcode_modifier.immext)
6913 /* When ImmExt is set, the immediate byte is the last
6915 imm_slot = i.operands - 1;
6923 /* Turn on Imm8 so that output_imm will generate it. */
6924 i.types[imm_slot].bitfield.imm8 = 1;
6927 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6928 i.op[imm_slot].imms->X_add_number
6929 |= register_number (i.op[reg_slot].regs) << 4;
6930 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6933 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6934 i.vex.register_specifier = i.op[nds].regs;
6939 /* i.reg_operands MUST be the number of real register operands;
6940 implicit registers do not count. If there are 3 register
6941 operands, it must be a instruction with VexNDS. For a
6942 instruction with VexNDD, the destination register is encoded
6943 in VEX prefix. If there are 4 register operands, it must be
6944 a instruction with VEX prefix and 3 sources. */
6945 if (i.mem_operands == 0
6946 && ((i.reg_operands == 2
6947 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6948 || (i.reg_operands == 3
6949 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6950 || (i.reg_operands == 4 && vex_3_sources)))
6958 /* When there are 3 operands, one of them may be immediate,
6959 which may be the first or the last operand. Otherwise,
6960 the first operand must be shift count register (cl) or it
6961 is an instruction with VexNDS. */
6962 gas_assert (i.imm_operands == 1
6963 || (i.imm_operands == 0
6964 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6965 || i.types[0].bitfield.shiftcount)));
6966 if (operand_type_check (i.types[0], imm)
6967 || i.types[0].bitfield.shiftcount)
6973 /* When there are 4 operands, the first two must be 8bit
6974 immediate operands. The source operand will be the 3rd
6977 For instructions with VexNDS, if the first operand
6978 an imm8, the source operand is the 2nd one. If the last
6979 operand is imm8, the source operand is the first one. */
6980 gas_assert ((i.imm_operands == 2
6981 && i.types[0].bitfield.imm8
6982 && i.types[1].bitfield.imm8)
6983 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6984 && i.imm_operands == 1
6985 && (i.types[0].bitfield.imm8
6986 || i.types[i.operands - 1].bitfield.imm8
6988 if (i.imm_operands == 2)
6992 if (i.types[0].bitfield.imm8)
6999 if (is_evex_encoding (&i.tm))
7001 /* For EVEX instructions, when there are 5 operands, the
7002 first one must be immediate operand. If the second one
7003 is immediate operand, the source operand is the 3th
7004 one. If the last one is immediate operand, the source
7005 operand is the 2nd one. */
7006 gas_assert (i.imm_operands == 2
7007 && i.tm.opcode_modifier.sae
7008 && operand_type_check (i.types[0], imm));
7009 if (operand_type_check (i.types[1], imm))
7011 else if (operand_type_check (i.types[4], imm))
7025 /* RC/SAE operand could be between DEST and SRC. That happens
7026 when one operand is GPR and the other one is XMM/YMM/ZMM
7028 if (i.rounding && i.rounding->operand == (int) dest)
7031 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7033 /* For instructions with VexNDS, the register-only source
7034 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7035 register. It is encoded in VEX prefix. We need to
7036 clear RegMem bit before calling operand_type_equal. */
7038 i386_operand_type op;
7041 /* Check register-only source operand when two source
7042 operands are swapped. */
7043 if (!i.tm.operand_types[source].bitfield.baseindex
7044 && i.tm.operand_types[dest].bitfield.baseindex)
7052 op = i.tm.operand_types[vvvv];
7053 op.bitfield.regmem = 0;
7054 if ((dest + 1) >= i.operands
7055 || ((!op.bitfield.reg
7056 || (!op.bitfield.dword && !op.bitfield.qword))
7057 && !op.bitfield.regsimd
7058 && !operand_type_equal (&op, ®mask)))
7060 i.vex.register_specifier = i.op[vvvv].regs;
7066 /* One of the register operands will be encoded in the i.tm.reg
7067 field, the other in the combined i.tm.mode and i.tm.regmem
7068 fields. If no form of this instruction supports a memory
7069 destination operand, then we assume the source operand may
7070 sometimes be a memory operand and so we need to store the
7071 destination in the i.rm.reg field. */
7072 if (!i.tm.operand_types[dest].bitfield.regmem
7073 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7075 i.rm.reg = i.op[dest].regs->reg_num;
7076 i.rm.regmem = i.op[source].regs->reg_num;
7077 if (i.op[dest].regs->reg_type.bitfield.regmmx
7078 || i.op[source].regs->reg_type.bitfield.regmmx)
7079 i.has_regmmx = TRUE;
7080 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7081 || i.op[source].regs->reg_type.bitfield.regsimd)
7083 if (i.types[dest].bitfield.zmmword
7084 || i.types[source].bitfield.zmmword)
7085 i.has_regzmm = TRUE;
7086 else if (i.types[dest].bitfield.ymmword
7087 || i.types[source].bitfield.ymmword)
7088 i.has_regymm = TRUE;
7090 i.has_regxmm = TRUE;
7092 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7094 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7096 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7098 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7103 i.rm.reg = i.op[source].regs->reg_num;
7104 i.rm.regmem = i.op[dest].regs->reg_num;
7105 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7107 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7109 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7111 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7114 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7116 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7119 add_prefix (LOCK_PREFIX_OPCODE);
7123 { /* If it's not 2 reg operands... */
7128 unsigned int fake_zero_displacement = 0;
7131 for (op = 0; op < i.operands; op++)
7132 if (operand_type_check (i.types[op], anymem))
7134 gas_assert (op < i.operands);
7136 if (i.tm.opcode_modifier.vecsib)
7138 if (i.index_reg->reg_num == RegIZ)
7141 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7144 i.sib.base = NO_BASE_REGISTER;
7145 i.sib.scale = i.log2_scale_factor;
7146 i.types[op].bitfield.disp8 = 0;
7147 i.types[op].bitfield.disp16 = 0;
7148 i.types[op].bitfield.disp64 = 0;
7149 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7151 /* Must be 32 bit */
7152 i.types[op].bitfield.disp32 = 1;
7153 i.types[op].bitfield.disp32s = 0;
7157 i.types[op].bitfield.disp32 = 0;
7158 i.types[op].bitfield.disp32s = 1;
7161 i.sib.index = i.index_reg->reg_num;
7162 if ((i.index_reg->reg_flags & RegRex) != 0)
7164 if ((i.index_reg->reg_flags & RegVRex) != 0)
7170 if (i.base_reg == 0)
7173 if (!i.disp_operands)
7174 fake_zero_displacement = 1;
7175 if (i.index_reg == 0)
7177 i386_operand_type newdisp;
7179 gas_assert (!i.tm.opcode_modifier.vecsib);
7180 /* Operand is just <disp> */
7181 if (flag_code == CODE_64BIT)
7183 /* 64bit mode overwrites the 32bit absolute
7184 addressing by RIP relative addressing and
7185 absolute addressing is encoded by one of the
7186 redundant SIB forms. */
7187 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7188 i.sib.base = NO_BASE_REGISTER;
7189 i.sib.index = NO_INDEX_REGISTER;
7190 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7192 else if ((flag_code == CODE_16BIT)
7193 ^ (i.prefix[ADDR_PREFIX] != 0))
7195 i.rm.regmem = NO_BASE_REGISTER_16;
7200 i.rm.regmem = NO_BASE_REGISTER;
7203 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7204 i.types[op] = operand_type_or (i.types[op], newdisp);
7206 else if (!i.tm.opcode_modifier.vecsib)
7208 /* !i.base_reg && i.index_reg */
7209 if (i.index_reg->reg_num == RegIZ)
7210 i.sib.index = NO_INDEX_REGISTER;
7212 i.sib.index = i.index_reg->reg_num;
7213 i.sib.base = NO_BASE_REGISTER;
7214 i.sib.scale = i.log2_scale_factor;
7215 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7216 i.types[op].bitfield.disp8 = 0;
7217 i.types[op].bitfield.disp16 = 0;
7218 i.types[op].bitfield.disp64 = 0;
7219 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7221 /* Must be 32 bit */
7222 i.types[op].bitfield.disp32 = 1;
7223 i.types[op].bitfield.disp32s = 0;
7227 i.types[op].bitfield.disp32 = 0;
7228 i.types[op].bitfield.disp32s = 1;
7230 if ((i.index_reg->reg_flags & RegRex) != 0)
7234 /* RIP addressing for 64bit mode. */
7235 else if (i.base_reg->reg_num == RegIP)
7237 gas_assert (!i.tm.opcode_modifier.vecsib);
7238 i.rm.regmem = NO_BASE_REGISTER;
7239 i.types[op].bitfield.disp8 = 0;
7240 i.types[op].bitfield.disp16 = 0;
7241 i.types[op].bitfield.disp32 = 0;
7242 i.types[op].bitfield.disp32s = 1;
7243 i.types[op].bitfield.disp64 = 0;
7244 i.flags[op] |= Operand_PCrel;
7245 if (! i.disp_operands)
7246 fake_zero_displacement = 1;
7248 else if (i.base_reg->reg_type.bitfield.word)
7250 gas_assert (!i.tm.opcode_modifier.vecsib);
7251 switch (i.base_reg->reg_num)
7254 if (i.index_reg == 0)
7256 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7257 i.rm.regmem = i.index_reg->reg_num - 6;
7261 if (i.index_reg == 0)
7264 if (operand_type_check (i.types[op], disp) == 0)
7266 /* fake (%bp) into 0(%bp) */
7267 i.types[op].bitfield.disp8 = 1;
7268 fake_zero_displacement = 1;
7271 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7272 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7274 default: /* (%si) -> 4 or (%di) -> 5 */
7275 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7277 i.rm.mode = mode_from_disp_size (i.types[op]);
7279 else /* i.base_reg and 32/64 bit mode */
7281 if (flag_code == CODE_64BIT
7282 && operand_type_check (i.types[op], disp))
7284 i.types[op].bitfield.disp16 = 0;
7285 i.types[op].bitfield.disp64 = 0;
7286 if (i.prefix[ADDR_PREFIX] == 0)
7288 i.types[op].bitfield.disp32 = 0;
7289 i.types[op].bitfield.disp32s = 1;
7293 i.types[op].bitfield.disp32 = 1;
7294 i.types[op].bitfield.disp32s = 0;
7298 if (!i.tm.opcode_modifier.vecsib)
7299 i.rm.regmem = i.base_reg->reg_num;
7300 if ((i.base_reg->reg_flags & RegRex) != 0)
7302 i.sib.base = i.base_reg->reg_num;
7303 /* x86-64 ignores REX prefix bit here to avoid decoder
7305 if (!(i.base_reg->reg_flags & RegRex)
7306 && (i.base_reg->reg_num == EBP_REG_NUM
7307 || i.base_reg->reg_num == ESP_REG_NUM))
7309 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7311 fake_zero_displacement = 1;
7312 i.types[op].bitfield.disp8 = 1;
7314 i.sib.scale = i.log2_scale_factor;
7315 if (i.index_reg == 0)
7317 gas_assert (!i.tm.opcode_modifier.vecsib);
7318 /* <disp>(%esp) becomes two byte modrm with no index
7319 register. We've already stored the code for esp
7320 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7321 Any base register besides %esp will not use the
7322 extra modrm byte. */
7323 i.sib.index = NO_INDEX_REGISTER;
7325 else if (!i.tm.opcode_modifier.vecsib)
7327 if (i.index_reg->reg_num == RegIZ)
7328 i.sib.index = NO_INDEX_REGISTER;
7330 i.sib.index = i.index_reg->reg_num;
7331 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7332 if ((i.index_reg->reg_flags & RegRex) != 0)
7337 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7338 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7342 if (!fake_zero_displacement
7346 fake_zero_displacement = 1;
7347 if (i.disp_encoding == disp_encoding_8bit)
7348 i.types[op].bitfield.disp8 = 1;
7350 i.types[op].bitfield.disp32 = 1;
7352 i.rm.mode = mode_from_disp_size (i.types[op]);
7356 if (fake_zero_displacement)
7358 /* Fakes a zero displacement assuming that i.types[op]
7359 holds the correct displacement size. */
7362 gas_assert (i.op[op].disps == 0);
7363 exp = &disp_expressions[i.disp_operands++];
7364 i.op[op].disps = exp;
7365 exp->X_op = O_constant;
7366 exp->X_add_number = 0;
7367 exp->X_add_symbol = (symbolS *) 0;
7368 exp->X_op_symbol = (symbolS *) 0;
7376 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7378 if (operand_type_check (i.types[0], imm))
7379 i.vex.register_specifier = NULL;
7382 /* VEX.vvvv encodes one of the sources when the first
7383 operand is not an immediate. */
7384 if (i.tm.opcode_modifier.vexw == VEXW0)
7385 i.vex.register_specifier = i.op[0].regs;
7387 i.vex.register_specifier = i.op[1].regs;
7390 /* Destination is a XMM register encoded in the ModRM.reg
7392 i.rm.reg = i.op[2].regs->reg_num;
7393 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7396 /* ModRM.rm and VEX.B encodes the other source. */
7397 if (!i.mem_operands)
7401 if (i.tm.opcode_modifier.vexw == VEXW0)
7402 i.rm.regmem = i.op[1].regs->reg_num;
7404 i.rm.regmem = i.op[0].regs->reg_num;
7406 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7410 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7412 i.vex.register_specifier = i.op[2].regs;
7413 if (!i.mem_operands)
7416 i.rm.regmem = i.op[1].regs->reg_num;
7417 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7421 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7422 (if any) based on i.tm.extension_opcode. Again, we must be
7423 careful to make sure that segment/control/debug/test/MMX
7424 registers are coded into the i.rm.reg field. */
7425 else if (i.reg_operands)
7428 unsigned int vex_reg = ~0;
7430 for (op = 0; op < i.operands; op++)
7432 if (i.types[op].bitfield.reg
7433 || i.types[op].bitfield.regbnd
7434 || i.types[op].bitfield.regmask
7435 || i.types[op].bitfield.sreg2
7436 || i.types[op].bitfield.sreg3
7437 || i.types[op].bitfield.control
7438 || i.types[op].bitfield.debug
7439 || i.types[op].bitfield.test)
7441 if (i.types[op].bitfield.regsimd)
7443 if (i.types[op].bitfield.zmmword)
7444 i.has_regzmm = TRUE;
7445 else if (i.types[op].bitfield.ymmword)
7446 i.has_regymm = TRUE;
7448 i.has_regxmm = TRUE;
7451 if (i.types[op].bitfield.regmmx)
7453 i.has_regmmx = TRUE;
7460 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7462 /* For instructions with VexNDS, the register-only
7463 source operand is encoded in VEX prefix. */
7464 gas_assert (mem != (unsigned int) ~0);
7469 gas_assert (op < i.operands);
7473 /* Check register-only source operand when two source
7474 operands are swapped. */
7475 if (!i.tm.operand_types[op].bitfield.baseindex
7476 && i.tm.operand_types[op + 1].bitfield.baseindex)
7480 gas_assert (mem == (vex_reg + 1)
7481 && op < i.operands);
7486 gas_assert (vex_reg < i.operands);
7490 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7492 /* For instructions with VexNDD, the register destination
7493 is encoded in VEX prefix. */
7494 if (i.mem_operands == 0)
7496 /* There is no memory operand. */
7497 gas_assert ((op + 2) == i.operands);
7502 /* There are only 2 non-immediate operands. */
7503 gas_assert (op < i.imm_operands + 2
7504 && i.operands == i.imm_operands + 2);
7505 vex_reg = i.imm_operands + 1;
7509 gas_assert (op < i.operands);
7511 if (vex_reg != (unsigned int) ~0)
7513 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7515 if ((!type->bitfield.reg
7516 || (!type->bitfield.dword && !type->bitfield.qword))
7517 && !type->bitfield.regsimd
7518 && !operand_type_equal (type, ®mask))
7521 i.vex.register_specifier = i.op[vex_reg].regs;
7524 /* Don't set OP operand twice. */
7527 /* If there is an extension opcode to put here, the
7528 register number must be put into the regmem field. */
7529 if (i.tm.extension_opcode != None)
7531 i.rm.regmem = i.op[op].regs->reg_num;
7532 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7534 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7539 i.rm.reg = i.op[op].regs->reg_num;
7540 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7542 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7547 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7548 must set it to 3 to indicate this is a register operand
7549 in the regmem field. */
7550 if (!i.mem_operands)
7554 /* Fill in i.rm.reg field with extension opcode (if any). */
7555 if (i.tm.extension_opcode != None)
7556 i.rm.reg = i.tm.extension_opcode;
7562 output_branch (void)
7568 relax_substateT subtype;
7572 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7573 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7576 if (i.prefix[DATA_PREFIX] != 0)
7582 /* Pentium4 branch hints. */
7583 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7584 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7589 if (i.prefix[REX_PREFIX] != 0)
7595 /* BND prefixed jump. */
7596 if (i.prefix[BND_PREFIX] != 0)
7598 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7602 if (i.prefixes != 0 && !intel_syntax)
7603 as_warn (_("skipping prefixes on this instruction"));
7605 /* It's always a symbol; End frag & setup for relax.
7606 Make sure there is enough room in this frag for the largest
7607 instruction we may generate in md_convert_frag. This is 2
7608 bytes for the opcode and room for the prefix and largest
7610 frag_grow (prefix + 2 + 4);
7611 /* Prefix and 1 opcode byte go in fr_fix. */
7612 p = frag_more (prefix + 1);
7613 if (i.prefix[DATA_PREFIX] != 0)
7614 *p++ = DATA_PREFIX_OPCODE;
7615 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7616 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7617 *p++ = i.prefix[SEG_PREFIX];
7618 if (i.prefix[REX_PREFIX] != 0)
7619 *p++ = i.prefix[REX_PREFIX];
7620 *p = i.tm.base_opcode;
7622 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7623 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7624 else if (cpu_arch_flags.bitfield.cpui386)
7625 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7627 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7630 sym = i.op[0].disps->X_add_symbol;
7631 off = i.op[0].disps->X_add_number;
7633 if (i.op[0].disps->X_op != O_constant
7634 && i.op[0].disps->X_op != O_symbol)
7636 /* Handle complex expressions. */
7637 sym = make_expr_symbol (i.op[0].disps);
7641 /* 1 possible extra opcode + 4 byte displacement go in var part.
7642 Pass reloc in fr_var. */
7643 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7646 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7647 /* Return TRUE iff PLT32 relocation should be used for branching to
7651 need_plt32_p (symbolS *s)
7653 /* PLT32 relocation is ELF only. */
7657 /* Since there is no need to prepare for PLT branch on x86-64, we
7658 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7659 be used as a marker for 32-bit PC-relative branches. */
7663 /* Weak or undefined symbol need PLT32 relocation. */
7664 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7667 /* Non-global symbol doesn't need PLT32 relocation. */
7668 if (! S_IS_EXTERNAL (s))
7671 /* Other global symbols need PLT32 relocation. NB: Symbol with
7672 non-default visibilities are treated as normal global symbol
7673 so that PLT32 relocation can be used as a marker for 32-bit
7674 PC-relative branches. It is useful for linker relaxation. */
7685 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7687 if (i.tm.opcode_modifier.jumpbyte)
7689 /* This is a loop or jecxz type instruction. */
7691 if (i.prefix[ADDR_PREFIX] != 0)
7693 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7696 /* Pentium4 branch hints. */
7697 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7698 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7700 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7709 if (flag_code == CODE_16BIT)
7712 if (i.prefix[DATA_PREFIX] != 0)
7714 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7724 if (i.prefix[REX_PREFIX] != 0)
7726 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7730 /* BND prefixed jump. */
7731 if (i.prefix[BND_PREFIX] != 0)
7733 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7737 if (i.prefixes != 0 && !intel_syntax)
7738 as_warn (_("skipping prefixes on this instruction"));
7740 p = frag_more (i.tm.opcode_length + size);
7741 switch (i.tm.opcode_length)
7744 *p++ = i.tm.base_opcode >> 8;
7747 *p++ = i.tm.base_opcode;
7753 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7755 && jump_reloc == NO_RELOC
7756 && need_plt32_p (i.op[0].disps->X_add_symbol))
7757 jump_reloc = BFD_RELOC_X86_64_PLT32;
7760 jump_reloc = reloc (size, 1, 1, jump_reloc);
7762 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7763 i.op[0].disps, 1, jump_reloc);
7765 /* All jumps handled here are signed, but don't use a signed limit
7766 check for 32 and 16 bit jumps as we want to allow wrap around at
7767 4G and 64k respectively. */
7769 fixP->fx_signed = 1;
7773 output_interseg_jump (void)
7781 if (flag_code == CODE_16BIT)
7785 if (i.prefix[DATA_PREFIX] != 0)
7791 if (i.prefix[REX_PREFIX] != 0)
7801 if (i.prefixes != 0 && !intel_syntax)
7802 as_warn (_("skipping prefixes on this instruction"));
7804 /* 1 opcode; 2 segment; offset */
7805 p = frag_more (prefix + 1 + 2 + size);
7807 if (i.prefix[DATA_PREFIX] != 0)
7808 *p++ = DATA_PREFIX_OPCODE;
7810 if (i.prefix[REX_PREFIX] != 0)
7811 *p++ = i.prefix[REX_PREFIX];
7813 *p++ = i.tm.base_opcode;
7814 if (i.op[1].imms->X_op == O_constant)
7816 offsetT n = i.op[1].imms->X_add_number;
7819 && !fits_in_unsigned_word (n)
7820 && !fits_in_signed_word (n))
7822 as_bad (_("16-bit jump out of range"));
7825 md_number_to_chars (p, n, size);
7828 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7829 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7830 if (i.op[0].imms->X_op != O_constant)
7831 as_bad (_("can't handle non absolute segment in `%s'"),
7833 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7836 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7841 asection *seg = now_seg;
7842 subsegT subseg = now_subseg;
7844 unsigned int alignment, align_size_1;
7845 unsigned int isa_1_descsz, feature_2_descsz, descsz;
7846 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
7847 unsigned int padding;
7849 if (!IS_ELF || !x86_used_note)
7852 x86_isa_1_used |= GNU_PROPERTY_X86_UINT32_VALID;
7853 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
7855 /* The .note.gnu.property section layout:
7857 Field Length Contents
7860 n_descsz 4 The note descriptor size
7861 n_type 4 NT_GNU_PROPERTY_TYPE_0
7863 n_desc n_descsz The program property array
7867 /* Create the .note.gnu.property section. */
7868 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
7869 bfd_set_section_flags (stdoutput, sec,
7876 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
7887 bfd_set_section_alignment (stdoutput, sec, alignment);
7888 elf_section_type (sec) = SHT_NOTE;
7890 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7892 isa_1_descsz_raw = 4 + 4 + 4;
7893 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7894 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
7896 feature_2_descsz_raw = isa_1_descsz;
7897 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7899 feature_2_descsz_raw += 4 + 4 + 4;
7900 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7901 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
7904 descsz = feature_2_descsz;
7905 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7906 p = frag_more (4 + 4 + 4 + 4 + descsz);
7908 /* Write n_namsz. */
7909 md_number_to_chars (p, (valueT) 4, 4);
7911 /* Write n_descsz. */
7912 md_number_to_chars (p + 4, (valueT) descsz, 4);
7915 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
7918 memcpy (p + 4 * 3, "GNU", 4);
7920 /* Write 4-byte type. */
7921 md_number_to_chars (p + 4 * 4,
7922 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
7924 /* Write 4-byte data size. */
7925 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
7927 /* Write 4-byte data. */
7928 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
7930 /* Zero out paddings. */
7931 padding = isa_1_descsz - isa_1_descsz_raw;
7933 memset (p + 4 * 7, 0, padding);
7935 /* Write 4-byte type. */
7936 md_number_to_chars (p + isa_1_descsz + 4 * 4,
7937 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
7939 /* Write 4-byte data size. */
7940 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
7942 /* Write 4-byte data. */
7943 md_number_to_chars (p + isa_1_descsz + 4 * 6,
7944 (valueT) x86_feature_2_used, 4);
7946 /* Zero out paddings. */
7947 padding = feature_2_descsz - feature_2_descsz_raw;
7949 memset (p + isa_1_descsz + 4 * 7, 0, padding);
7951 /* We probably can't restore the current segment, for there likely
7954 subseg_set (seg, subseg);
7961 fragS *insn_start_frag;
7962 offsetT insn_start_off;
7964 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7965 if (IS_ELF && x86_used_note)
7967 if (i.tm.cpu_flags.bitfield.cpucmov)
7968 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
7969 if (i.tm.cpu_flags.bitfield.cpusse)
7970 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
7971 if (i.tm.cpu_flags.bitfield.cpusse2)
7972 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
7973 if (i.tm.cpu_flags.bitfield.cpusse3)
7974 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
7975 if (i.tm.cpu_flags.bitfield.cpussse3)
7976 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
7977 if (i.tm.cpu_flags.bitfield.cpusse4_1)
7978 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
7979 if (i.tm.cpu_flags.bitfield.cpusse4_2)
7980 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
7981 if (i.tm.cpu_flags.bitfield.cpuavx)
7982 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
7983 if (i.tm.cpu_flags.bitfield.cpuavx2)
7984 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
7985 if (i.tm.cpu_flags.bitfield.cpufma)
7986 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
7987 if (i.tm.cpu_flags.bitfield.cpuavx512f)
7988 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
7989 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
7990 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
7991 if (i.tm.cpu_flags.bitfield.cpuavx512er)
7992 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
7993 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
7994 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
7995 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
7996 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
7997 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
7998 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
7999 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8000 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8001 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8002 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8003 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8004 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8005 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8006 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8007 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8008 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8009 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8010 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8011 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8012 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8013 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8014 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
8016 if (i.tm.cpu_flags.bitfield.cpu8087
8017 || i.tm.cpu_flags.bitfield.cpu287
8018 || i.tm.cpu_flags.bitfield.cpu387
8019 || i.tm.cpu_flags.bitfield.cpu687
8020 || i.tm.cpu_flags.bitfield.cpufisttp)
8021 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8022 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8023 Xfence instructions. */
8024 if (i.tm.base_opcode != 0xf18
8025 && i.tm.base_opcode != 0xf0d
8026 && i.tm.base_opcode != 0xfae
8028 || i.tm.cpu_flags.bitfield.cpummx
8029 || i.tm.cpu_flags.bitfield.cpua3dnow
8030 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8031 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8033 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8035 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8037 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8038 if (i.tm.cpu_flags.bitfield.cpufxsr)
8039 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8040 if (i.tm.cpu_flags.bitfield.cpuxsave)
8041 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8042 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8043 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8044 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8045 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8049 /* Tie dwarf2 debug info to the address at the start of the insn.
8050 We can't do this after the insn has been output as the current
8051 frag may have been closed off. eg. by frag_var. */
8052 dwarf2_emit_insn (0);
8054 insn_start_frag = frag_now;
8055 insn_start_off = frag_now_fix ();
8058 if (i.tm.opcode_modifier.jump)
8060 else if (i.tm.opcode_modifier.jumpbyte
8061 || i.tm.opcode_modifier.jumpdword)
8063 else if (i.tm.opcode_modifier.jumpintersegment)
8064 output_interseg_jump ();
8067 /* Output normal instructions here. */
8071 unsigned int prefix;
8074 && i.tm.base_opcode == 0xfae
8076 && i.imm_operands == 1
8077 && (i.op[0].imms->X_add_number == 0xe8
8078 || i.op[0].imms->X_add_number == 0xf0
8079 || i.op[0].imms->X_add_number == 0xf8))
8081 /* Encode lfence, mfence, and sfence as
8082 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8083 offsetT val = 0x240483f0ULL;
8085 md_number_to_chars (p, val, 5);
8089 /* Some processors fail on LOCK prefix. This options makes
8090 assembler ignore LOCK prefix and serves as a workaround. */
8091 if (omit_lock_prefix)
8093 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8095 i.prefix[LOCK_PREFIX] = 0;
8098 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8099 don't need the explicit prefix. */
8100 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
8102 switch (i.tm.opcode_length)
8105 if (i.tm.base_opcode & 0xff000000)
8107 prefix = (i.tm.base_opcode >> 24) & 0xff;
8108 add_prefix (prefix);
8112 if ((i.tm.base_opcode & 0xff0000) != 0)
8114 prefix = (i.tm.base_opcode >> 16) & 0xff;
8115 if (!i.tm.cpu_flags.bitfield.cpupadlock
8116 || prefix != REPE_PREFIX_OPCODE
8117 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
8118 add_prefix (prefix);
8124 /* Check for pseudo prefixes. */
8125 as_bad_where (insn_start_frag->fr_file,
8126 insn_start_frag->fr_line,
8127 _("pseudo prefix without instruction"));
8133 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8134 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8135 R_X86_64_GOTTPOFF relocation so that linker can safely
8136 perform IE->LE optimization. */
8137 if (x86_elf_abi == X86_64_X32_ABI
8139 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8140 && i.prefix[REX_PREFIX] == 0)
8141 add_prefix (REX_OPCODE);
8144 /* The prefix bytes. */
8145 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8147 FRAG_APPEND_1_CHAR (*q);
8151 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8156 /* REX byte is encoded in VEX prefix. */
8160 FRAG_APPEND_1_CHAR (*q);
8163 /* There should be no other prefixes for instructions
8168 /* For EVEX instructions i.vrex should become 0 after
8169 build_evex_prefix. For VEX instructions upper 16 registers
8170 aren't available, so VREX should be 0. */
8173 /* Now the VEX prefix. */
8174 p = frag_more (i.vex.length);
8175 for (j = 0; j < i.vex.length; j++)
8176 p[j] = i.vex.bytes[j];
8179 /* Now the opcode; be careful about word order here! */
8180 if (i.tm.opcode_length == 1)
8182 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8186 switch (i.tm.opcode_length)
8190 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8191 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8195 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8205 /* Put out high byte first: can't use md_number_to_chars! */
8206 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8207 *p = i.tm.base_opcode & 0xff;
8210 /* Now the modrm byte and sib byte (if present). */
8211 if (i.tm.opcode_modifier.modrm)
8213 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8216 /* If i.rm.regmem == ESP (4)
8217 && i.rm.mode != (Register mode)
8219 ==> need second modrm byte. */
8220 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8222 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
8223 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8225 | i.sib.scale << 6));
8228 if (i.disp_operands)
8229 output_disp (insn_start_frag, insn_start_off);
8232 output_imm (insn_start_frag, insn_start_off);
8238 pi ("" /*line*/, &i);
8240 #endif /* DEBUG386 */
8243 /* Return the size of the displacement operand N. */
8246 disp_size (unsigned int n)
8250 if (i.types[n].bitfield.disp64)
8252 else if (i.types[n].bitfield.disp8)
8254 else if (i.types[n].bitfield.disp16)
8259 /* Return the size of the immediate operand N. */
8262 imm_size (unsigned int n)
8265 if (i.types[n].bitfield.imm64)
8267 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8269 else if (i.types[n].bitfield.imm16)
8275 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
8280 for (n = 0; n < i.operands; n++)
8282 if (operand_type_check (i.types[n], disp))
8284 if (i.op[n].disps->X_op == O_constant)
8286 int size = disp_size (n);
8287 offsetT val = i.op[n].disps->X_add_number;
8289 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8291 p = frag_more (size);
8292 md_number_to_chars (p, val, size);
8296 enum bfd_reloc_code_real reloc_type;
8297 int size = disp_size (n);
8298 int sign = i.types[n].bitfield.disp32s;
8299 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8302 /* We can't have 8 bit displacement here. */
8303 gas_assert (!i.types[n].bitfield.disp8);
8305 /* The PC relative address is computed relative
8306 to the instruction boundary, so in case immediate
8307 fields follows, we need to adjust the value. */
8308 if (pcrel && i.imm_operands)
8313 for (n1 = 0; n1 < i.operands; n1++)
8314 if (operand_type_check (i.types[n1], imm))
8316 /* Only one immediate is allowed for PC
8317 relative address. */
8318 gas_assert (sz == 0);
8320 i.op[n].disps->X_add_number -= sz;
8322 /* We should find the immediate. */
8323 gas_assert (sz != 0);
8326 p = frag_more (size);
8327 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8329 && GOT_symbol == i.op[n].disps->X_add_symbol
8330 && (((reloc_type == BFD_RELOC_32
8331 || reloc_type == BFD_RELOC_X86_64_32S
8332 || (reloc_type == BFD_RELOC_64
8334 && (i.op[n].disps->X_op == O_symbol
8335 || (i.op[n].disps->X_op == O_add
8336 && ((symbol_get_value_expression
8337 (i.op[n].disps->X_op_symbol)->X_op)
8339 || reloc_type == BFD_RELOC_32_PCREL))
8343 if (insn_start_frag == frag_now)
8344 add = (p - frag_now->fr_literal) - insn_start_off;
8349 add = insn_start_frag->fr_fix - insn_start_off;
8350 for (fr = insn_start_frag->fr_next;
8351 fr && fr != frag_now; fr = fr->fr_next)
8353 add += p - frag_now->fr_literal;
8358 reloc_type = BFD_RELOC_386_GOTPC;
8359 i.op[n].imms->X_add_number += add;
8361 else if (reloc_type == BFD_RELOC_64)
8362 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8364 /* Don't do the adjustment for x86-64, as there
8365 the pcrel addressing is relative to the _next_
8366 insn, and that is taken care of in other code. */
8367 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8369 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8370 size, i.op[n].disps, pcrel,
8372 /* Check for "call/jmp *mem", "mov mem, %reg",
8373 "test %reg, mem" and "binop mem, %reg" where binop
8374 is one of adc, add, and, cmp, or, sbb, sub, xor
8375 instructions. Always generate R_386_GOT32X for
8376 "sym*GOT" operand in 32-bit mode. */
8377 if ((generate_relax_relocations
8380 && i.rm.regmem == 5))
8382 || (i.rm.mode == 0 && i.rm.regmem == 5))
8383 && ((i.operands == 1
8384 && i.tm.base_opcode == 0xff
8385 && (i.rm.reg == 2 || i.rm.reg == 4))
8387 && (i.tm.base_opcode == 0x8b
8388 || i.tm.base_opcode == 0x85
8389 || (i.tm.base_opcode & 0xc7) == 0x03))))
8393 fixP->fx_tcbit = i.rex != 0;
8395 && (i.base_reg->reg_num == RegIP))
8396 fixP->fx_tcbit2 = 1;
8399 fixP->fx_tcbit2 = 1;
8407 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8412 for (n = 0; n < i.operands; n++)
8414 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8415 if (i.rounding && (int) n == i.rounding->operand)
8418 if (operand_type_check (i.types[n], imm))
8420 if (i.op[n].imms->X_op == O_constant)
8422 int size = imm_size (n);
8425 val = offset_in_range (i.op[n].imms->X_add_number,
8427 p = frag_more (size);
8428 md_number_to_chars (p, val, size);
8432 /* Not absolute_section.
8433 Need a 32-bit fixup (don't support 8bit
8434 non-absolute imms). Try to support other
8436 enum bfd_reloc_code_real reloc_type;
8437 int size = imm_size (n);
8440 if (i.types[n].bitfield.imm32s
8441 && (i.suffix == QWORD_MNEM_SUFFIX
8442 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8447 p = frag_more (size);
8448 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8450 /* This is tough to explain. We end up with this one if we
8451 * have operands that look like
8452 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8453 * obtain the absolute address of the GOT, and it is strongly
8454 * preferable from a performance point of view to avoid using
8455 * a runtime relocation for this. The actual sequence of
8456 * instructions often look something like:
8461 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8463 * The call and pop essentially return the absolute address
8464 * of the label .L66 and store it in %ebx. The linker itself
8465 * will ultimately change the first operand of the addl so
8466 * that %ebx points to the GOT, but to keep things simple, the
8467 * .o file must have this operand set so that it generates not
8468 * the absolute address of .L66, but the absolute address of
8469 * itself. This allows the linker itself simply treat a GOTPC
8470 * relocation as asking for a pcrel offset to the GOT to be
8471 * added in, and the addend of the relocation is stored in the
8472 * operand field for the instruction itself.
8474 * Our job here is to fix the operand so that it would add
8475 * the correct offset so that %ebx would point to itself. The
8476 * thing that is tricky is that .-.L66 will point to the
8477 * beginning of the instruction, so we need to further modify
8478 * the operand so that it will point to itself. There are
8479 * other cases where you have something like:
8481 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8483 * and here no correction would be required. Internally in
8484 * the assembler we treat operands of this form as not being
8485 * pcrel since the '.' is explicitly mentioned, and I wonder
8486 * whether it would simplify matters to do it this way. Who
8487 * knows. In earlier versions of the PIC patches, the
8488 * pcrel_adjust field was used to store the correction, but
8489 * since the expression is not pcrel, I felt it would be
8490 * confusing to do it this way. */
8492 if ((reloc_type == BFD_RELOC_32
8493 || reloc_type == BFD_RELOC_X86_64_32S
8494 || reloc_type == BFD_RELOC_64)
8496 && GOT_symbol == i.op[n].imms->X_add_symbol
8497 && (i.op[n].imms->X_op == O_symbol
8498 || (i.op[n].imms->X_op == O_add
8499 && ((symbol_get_value_expression
8500 (i.op[n].imms->X_op_symbol)->X_op)
8505 if (insn_start_frag == frag_now)
8506 add = (p - frag_now->fr_literal) - insn_start_off;
8511 add = insn_start_frag->fr_fix - insn_start_off;
8512 for (fr = insn_start_frag->fr_next;
8513 fr && fr != frag_now; fr = fr->fr_next)
8515 add += p - frag_now->fr_literal;
8519 reloc_type = BFD_RELOC_386_GOTPC;
8521 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8523 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8524 i.op[n].imms->X_add_number += add;
8526 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8527 i.op[n].imms, 0, reloc_type);
8533 /* x86_cons_fix_new is called via the expression parsing code when a
8534 reloc is needed. We use this hook to get the correct .got reloc. */
8535 static int cons_sign = -1;
8538 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8539 expressionS *exp, bfd_reloc_code_real_type r)
8541 r = reloc (len, 0, cons_sign, r);
8544 if (exp->X_op == O_secrel)
8546 exp->X_op = O_symbol;
8547 r = BFD_RELOC_32_SECREL;
8551 fix_new_exp (frag, off, len, exp, 0, r);
8554 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8555 purpose of the `.dc.a' internal pseudo-op. */
8558 x86_address_bytes (void)
8560 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8562 return stdoutput->arch_info->bits_per_address / 8;
8565 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8567 # define lex_got(reloc, adjust, types) NULL
8569 /* Parse operands of the form
8570 <symbol>@GOTOFF+<nnn>
8571 and similar .plt or .got references.
8573 If we find one, set up the correct relocation in RELOC and copy the
8574 input string, minus the `@GOTOFF' into a malloc'd buffer for
8575 parsing by the calling routine. Return this buffer, and if ADJUST
8576 is non-null set it to the length of the string we removed from the
8577 input line. Otherwise return NULL. */
8579 lex_got (enum bfd_reloc_code_real *rel,
8581 i386_operand_type *types)
8583 /* Some of the relocations depend on the size of what field is to
8584 be relocated. But in our callers i386_immediate and i386_displacement
8585 we don't yet know the operand size (this will be set by insn
8586 matching). Hence we record the word32 relocation here,
8587 and adjust the reloc according to the real size in reloc(). */
8588 static const struct {
8591 const enum bfd_reloc_code_real rel[2];
8592 const i386_operand_type types64;
8594 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8595 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8597 OPERAND_TYPE_IMM32_64 },
8599 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8600 BFD_RELOC_X86_64_PLTOFF64 },
8601 OPERAND_TYPE_IMM64 },
8602 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8603 BFD_RELOC_X86_64_PLT32 },
8604 OPERAND_TYPE_IMM32_32S_DISP32 },
8605 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8606 BFD_RELOC_X86_64_GOTPLT64 },
8607 OPERAND_TYPE_IMM64_DISP64 },
8608 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8609 BFD_RELOC_X86_64_GOTOFF64 },
8610 OPERAND_TYPE_IMM64_DISP64 },
8611 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8612 BFD_RELOC_X86_64_GOTPCREL },
8613 OPERAND_TYPE_IMM32_32S_DISP32 },
8614 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8615 BFD_RELOC_X86_64_TLSGD },
8616 OPERAND_TYPE_IMM32_32S_DISP32 },
8617 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8618 _dummy_first_bfd_reloc_code_real },
8619 OPERAND_TYPE_NONE },
8620 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8621 BFD_RELOC_X86_64_TLSLD },
8622 OPERAND_TYPE_IMM32_32S_DISP32 },
8623 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8624 BFD_RELOC_X86_64_GOTTPOFF },
8625 OPERAND_TYPE_IMM32_32S_DISP32 },
8626 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8627 BFD_RELOC_X86_64_TPOFF32 },
8628 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8629 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8630 _dummy_first_bfd_reloc_code_real },
8631 OPERAND_TYPE_NONE },
8632 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8633 BFD_RELOC_X86_64_DTPOFF32 },
8634 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8635 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8636 _dummy_first_bfd_reloc_code_real },
8637 OPERAND_TYPE_NONE },
8638 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8639 _dummy_first_bfd_reloc_code_real },
8640 OPERAND_TYPE_NONE },
8641 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8642 BFD_RELOC_X86_64_GOT32 },
8643 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8644 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8645 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8646 OPERAND_TYPE_IMM32_32S_DISP32 },
8647 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8648 BFD_RELOC_X86_64_TLSDESC_CALL },
8649 OPERAND_TYPE_IMM32_32S_DISP32 },
8654 #if defined (OBJ_MAYBE_ELF)
8659 for (cp = input_line_pointer; *cp != '@'; cp++)
8660 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8663 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8665 int len = gotrel[j].len;
8666 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8668 if (gotrel[j].rel[object_64bit] != 0)
8671 char *tmpbuf, *past_reloc;
8673 *rel = gotrel[j].rel[object_64bit];
8677 if (flag_code != CODE_64BIT)
8679 types->bitfield.imm32 = 1;
8680 types->bitfield.disp32 = 1;
8683 *types = gotrel[j].types64;
8686 if (j != 0 && GOT_symbol == NULL)
8687 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8689 /* The length of the first part of our input line. */
8690 first = cp - input_line_pointer;
8692 /* The second part goes from after the reloc token until
8693 (and including) an end_of_line char or comma. */
8694 past_reloc = cp + 1 + len;
8696 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8698 second = cp + 1 - past_reloc;
8700 /* Allocate and copy string. The trailing NUL shouldn't
8701 be necessary, but be safe. */
8702 tmpbuf = XNEWVEC (char, first + second + 2);
8703 memcpy (tmpbuf, input_line_pointer, first);
8704 if (second != 0 && *past_reloc != ' ')
8705 /* Replace the relocation token with ' ', so that
8706 errors like foo@GOTOFF1 will be detected. */
8707 tmpbuf[first++] = ' ';
8709 /* Increment length by 1 if the relocation token is
8714 memcpy (tmpbuf + first, past_reloc, second);
8715 tmpbuf[first + second] = '\0';
8719 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8720 gotrel[j].str, 1 << (5 + object_64bit));
8725 /* Might be a symbol version string. Don't as_bad here. */
8734 /* Parse operands of the form
8735 <symbol>@SECREL32+<nnn>
8737 If we find one, set up the correct relocation in RELOC and copy the
8738 input string, minus the `@SECREL32' into a malloc'd buffer for
8739 parsing by the calling routine. Return this buffer, and if ADJUST
8740 is non-null set it to the length of the string we removed from the
8741 input line. Otherwise return NULL.
8743 This function is copied from the ELF version above adjusted for PE targets. */
8746 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8747 int *adjust ATTRIBUTE_UNUSED,
8748 i386_operand_type *types)
8754 const enum bfd_reloc_code_real rel[2];
8755 const i386_operand_type types64;
8759 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8760 BFD_RELOC_32_SECREL },
8761 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8767 for (cp = input_line_pointer; *cp != '@'; cp++)
8768 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8771 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8773 int len = gotrel[j].len;
8775 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8777 if (gotrel[j].rel[object_64bit] != 0)
8780 char *tmpbuf, *past_reloc;
8782 *rel = gotrel[j].rel[object_64bit];
8788 if (flag_code != CODE_64BIT)
8790 types->bitfield.imm32 = 1;
8791 types->bitfield.disp32 = 1;
8794 *types = gotrel[j].types64;
8797 /* The length of the first part of our input line. */
8798 first = cp - input_line_pointer;
8800 /* The second part goes from after the reloc token until
8801 (and including) an end_of_line char or comma. */
8802 past_reloc = cp + 1 + len;
8804 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8806 second = cp + 1 - past_reloc;
8808 /* Allocate and copy string. The trailing NUL shouldn't
8809 be necessary, but be safe. */
8810 tmpbuf = XNEWVEC (char, first + second + 2);
8811 memcpy (tmpbuf, input_line_pointer, first);
8812 if (second != 0 && *past_reloc != ' ')
8813 /* Replace the relocation token with ' ', so that
8814 errors like foo@SECLREL321 will be detected. */
8815 tmpbuf[first++] = ' ';
8816 memcpy (tmpbuf + first, past_reloc, second);
8817 tmpbuf[first + second] = '\0';
8821 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8822 gotrel[j].str, 1 << (5 + object_64bit));
8827 /* Might be a symbol version string. Don't as_bad here. */
8833 bfd_reloc_code_real_type
8834 x86_cons (expressionS *exp, int size)
8836 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8838 intel_syntax = -intel_syntax;
8841 if (size == 4 || (object_64bit && size == 8))
8843 /* Handle @GOTOFF and the like in an expression. */
8845 char *gotfree_input_line;
8848 save = input_line_pointer;
8849 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8850 if (gotfree_input_line)
8851 input_line_pointer = gotfree_input_line;
8855 if (gotfree_input_line)
8857 /* expression () has merrily parsed up to the end of line,
8858 or a comma - in the wrong buffer. Transfer how far
8859 input_line_pointer has moved to the right buffer. */
8860 input_line_pointer = (save
8861 + (input_line_pointer - gotfree_input_line)
8863 free (gotfree_input_line);
8864 if (exp->X_op == O_constant
8865 || exp->X_op == O_absent
8866 || exp->X_op == O_illegal
8867 || exp->X_op == O_register
8868 || exp->X_op == O_big)
8870 char c = *input_line_pointer;
8871 *input_line_pointer = 0;
8872 as_bad (_("missing or invalid expression `%s'"), save);
8873 *input_line_pointer = c;
8880 intel_syntax = -intel_syntax;
8883 i386_intel_simplify (exp);
8889 signed_cons (int size)
8891 if (flag_code == CODE_64BIT)
8899 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8906 if (exp.X_op == O_symbol)
8907 exp.X_op = O_secrel;
8909 emit_expr (&exp, 4);
8911 while (*input_line_pointer++ == ',');
8913 input_line_pointer--;
8914 demand_empty_rest_of_line ();
8918 /* Handle Vector operations. */
8921 check_VecOperations (char *op_string, char *op_end)
8923 const reg_entry *mask;
8928 && (op_end == NULL || op_string < op_end))
8931 if (*op_string == '{')
8935 /* Check broadcasts. */
8936 if (strncmp (op_string, "1to", 3) == 0)
8941 goto duplicated_vec_op;
8944 if (*op_string == '8')
8946 else if (*op_string == '4')
8948 else if (*op_string == '2')
8950 else if (*op_string == '1'
8951 && *(op_string+1) == '6')
8958 as_bad (_("Unsupported broadcast: `%s'"), saved);
8963 broadcast_op.type = bcst_type;
8964 broadcast_op.operand = this_operand;
8965 broadcast_op.bytes = 0;
8966 i.broadcast = &broadcast_op;
8968 /* Check masking operation. */
8969 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8971 /* k0 can't be used for write mask. */
8972 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8974 as_bad (_("`%s%s' can't be used for write mask"),
8975 register_prefix, mask->reg_name);
8981 mask_op.mask = mask;
8982 mask_op.zeroing = 0;
8983 mask_op.operand = this_operand;
8989 goto duplicated_vec_op;
8991 i.mask->mask = mask;
8993 /* Only "{z}" is allowed here. No need to check
8994 zeroing mask explicitly. */
8995 if (i.mask->operand != this_operand)
8997 as_bad (_("invalid write mask `%s'"), saved);
9004 /* Check zeroing-flag for masking operation. */
9005 else if (*op_string == 'z')
9009 mask_op.mask = NULL;
9010 mask_op.zeroing = 1;
9011 mask_op.operand = this_operand;
9016 if (i.mask->zeroing)
9019 as_bad (_("duplicated `%s'"), saved);
9023 i.mask->zeroing = 1;
9025 /* Only "{%k}" is allowed here. No need to check mask
9026 register explicitly. */
9027 if (i.mask->operand != this_operand)
9029 as_bad (_("invalid zeroing-masking `%s'"),
9038 goto unknown_vec_op;
9040 if (*op_string != '}')
9042 as_bad (_("missing `}' in `%s'"), saved);
9047 /* Strip whitespace since the addition of pseudo prefixes
9048 changed how the scrubber treats '{'. */
9049 if (is_space_char (*op_string))
9055 /* We don't know this one. */
9056 as_bad (_("unknown vector operation: `%s'"), saved);
9060 if (i.mask && i.mask->zeroing && !i.mask->mask)
9062 as_bad (_("zeroing-masking only allowed with write mask"));
9070 i386_immediate (char *imm_start)
9072 char *save_input_line_pointer;
9073 char *gotfree_input_line;
9076 i386_operand_type types;
9078 operand_type_set (&types, ~0);
9080 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9082 as_bad (_("at most %d immediate operands are allowed"),
9083 MAX_IMMEDIATE_OPERANDS);
9087 exp = &im_expressions[i.imm_operands++];
9088 i.op[this_operand].imms = exp;
9090 if (is_space_char (*imm_start))
9093 save_input_line_pointer = input_line_pointer;
9094 input_line_pointer = imm_start;
9096 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9097 if (gotfree_input_line)
9098 input_line_pointer = gotfree_input_line;
9100 exp_seg = expression (exp);
9104 /* Handle vector operations. */
9105 if (*input_line_pointer == '{')
9107 input_line_pointer = check_VecOperations (input_line_pointer,
9109 if (input_line_pointer == NULL)
9113 if (*input_line_pointer)
9114 as_bad (_("junk `%s' after expression"), input_line_pointer);
9116 input_line_pointer = save_input_line_pointer;
9117 if (gotfree_input_line)
9119 free (gotfree_input_line);
9121 if (exp->X_op == O_constant || exp->X_op == O_register)
9122 exp->X_op = O_illegal;
9125 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9129 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9130 i386_operand_type types, const char *imm_start)
9132 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
9135 as_bad (_("missing or invalid immediate expression `%s'"),
9139 else if (exp->X_op == O_constant)
9141 /* Size it properly later. */
9142 i.types[this_operand].bitfield.imm64 = 1;
9143 /* If not 64bit, sign extend val. */
9144 if (flag_code != CODE_64BIT
9145 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9147 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
9149 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9150 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
9151 && exp_seg != absolute_section
9152 && exp_seg != text_section
9153 && exp_seg != data_section
9154 && exp_seg != bss_section
9155 && exp_seg != undefined_section
9156 && !bfd_is_com_section (exp_seg))
9158 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9162 else if (!intel_syntax && exp_seg == reg_section)
9165 as_bad (_("illegal immediate register operand %s"), imm_start);
9170 /* This is an address. The size of the address will be
9171 determined later, depending on destination register,
9172 suffix, or the default for the section. */
9173 i.types[this_operand].bitfield.imm8 = 1;
9174 i.types[this_operand].bitfield.imm16 = 1;
9175 i.types[this_operand].bitfield.imm32 = 1;
9176 i.types[this_operand].bitfield.imm32s = 1;
9177 i.types[this_operand].bitfield.imm64 = 1;
9178 i.types[this_operand] = operand_type_and (i.types[this_operand],
9186 i386_scale (char *scale)
9189 char *save = input_line_pointer;
9191 input_line_pointer = scale;
9192 val = get_absolute_expression ();
9197 i.log2_scale_factor = 0;
9200 i.log2_scale_factor = 1;
9203 i.log2_scale_factor = 2;
9206 i.log2_scale_factor = 3;
9210 char sep = *input_line_pointer;
9212 *input_line_pointer = '\0';
9213 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9215 *input_line_pointer = sep;
9216 input_line_pointer = save;
9220 if (i.log2_scale_factor != 0 && i.index_reg == 0)
9222 as_warn (_("scale factor of %d without an index register"),
9223 1 << i.log2_scale_factor);
9224 i.log2_scale_factor = 0;
9226 scale = input_line_pointer;
9227 input_line_pointer = save;
9232 i386_displacement (char *disp_start, char *disp_end)
9236 char *save_input_line_pointer;
9237 char *gotfree_input_line;
9239 i386_operand_type bigdisp, types = anydisp;
9242 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9244 as_bad (_("at most %d displacement operands are allowed"),
9245 MAX_MEMORY_OPERANDS);
9249 operand_type_set (&bigdisp, 0);
9250 if ((i.types[this_operand].bitfield.jumpabsolute)
9251 || (!current_templates->start->opcode_modifier.jump
9252 && !current_templates->start->opcode_modifier.jumpdword))
9254 bigdisp.bitfield.disp32 = 1;
9255 override = (i.prefix[ADDR_PREFIX] != 0);
9256 if (flag_code == CODE_64BIT)
9260 bigdisp.bitfield.disp32s = 1;
9261 bigdisp.bitfield.disp64 = 1;
9264 else if ((flag_code == CODE_16BIT) ^ override)
9266 bigdisp.bitfield.disp32 = 0;
9267 bigdisp.bitfield.disp16 = 1;
9272 /* For PC-relative branches, the width of the displacement
9273 is dependent upon data size, not address size. */
9274 override = (i.prefix[DATA_PREFIX] != 0);
9275 if (flag_code == CODE_64BIT)
9277 if (override || i.suffix == WORD_MNEM_SUFFIX)
9278 bigdisp.bitfield.disp16 = 1;
9281 bigdisp.bitfield.disp32 = 1;
9282 bigdisp.bitfield.disp32s = 1;
9288 override = (i.suffix == (flag_code != CODE_16BIT
9290 : LONG_MNEM_SUFFIX));
9291 bigdisp.bitfield.disp32 = 1;
9292 if ((flag_code == CODE_16BIT) ^ override)
9294 bigdisp.bitfield.disp32 = 0;
9295 bigdisp.bitfield.disp16 = 1;
9299 i.types[this_operand] = operand_type_or (i.types[this_operand],
9302 exp = &disp_expressions[i.disp_operands];
9303 i.op[this_operand].disps = exp;
9305 save_input_line_pointer = input_line_pointer;
9306 input_line_pointer = disp_start;
9307 END_STRING_AND_SAVE (disp_end);
9309 #ifndef GCC_ASM_O_HACK
9310 #define GCC_ASM_O_HACK 0
9313 END_STRING_AND_SAVE (disp_end + 1);
9314 if (i.types[this_operand].bitfield.baseIndex
9315 && displacement_string_end[-1] == '+')
9317 /* This hack is to avoid a warning when using the "o"
9318 constraint within gcc asm statements.
9321 #define _set_tssldt_desc(n,addr,limit,type) \
9322 __asm__ __volatile__ ( \
9324 "movw %w1,2+%0\n\t" \
9326 "movb %b1,4+%0\n\t" \
9327 "movb %4,5+%0\n\t" \
9328 "movb $0,6+%0\n\t" \
9329 "movb %h1,7+%0\n\t" \
9331 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9333 This works great except that the output assembler ends
9334 up looking a bit weird if it turns out that there is
9335 no offset. You end up producing code that looks like:
9348 So here we provide the missing zero. */
9350 *displacement_string_end = '0';
9353 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9354 if (gotfree_input_line)
9355 input_line_pointer = gotfree_input_line;
9357 exp_seg = expression (exp);
9360 if (*input_line_pointer)
9361 as_bad (_("junk `%s' after expression"), input_line_pointer);
9363 RESTORE_END_STRING (disp_end + 1);
9365 input_line_pointer = save_input_line_pointer;
9366 if (gotfree_input_line)
9368 free (gotfree_input_line);
9370 if (exp->X_op == O_constant || exp->X_op == O_register)
9371 exp->X_op = O_illegal;
9374 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9376 RESTORE_END_STRING (disp_end);
9382 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9383 i386_operand_type types, const char *disp_start)
9385 i386_operand_type bigdisp;
9388 /* We do this to make sure that the section symbol is in
9389 the symbol table. We will ultimately change the relocation
9390 to be relative to the beginning of the section. */
9391 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9392 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9393 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9395 if (exp->X_op != O_symbol)
9398 if (S_IS_LOCAL (exp->X_add_symbol)
9399 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9400 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9401 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9402 exp->X_op = O_subtract;
9403 exp->X_op_symbol = GOT_symbol;
9404 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9405 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9406 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9407 i.reloc[this_operand] = BFD_RELOC_64;
9409 i.reloc[this_operand] = BFD_RELOC_32;
9412 else if (exp->X_op == O_absent
9413 || exp->X_op == O_illegal
9414 || exp->X_op == O_big)
9417 as_bad (_("missing or invalid displacement expression `%s'"),
9422 else if (flag_code == CODE_64BIT
9423 && !i.prefix[ADDR_PREFIX]
9424 && exp->X_op == O_constant)
9426 /* Since displacement is signed extended to 64bit, don't allow
9427 disp32 and turn off disp32s if they are out of range. */
9428 i.types[this_operand].bitfield.disp32 = 0;
9429 if (!fits_in_signed_long (exp->X_add_number))
9431 i.types[this_operand].bitfield.disp32s = 0;
9432 if (i.types[this_operand].bitfield.baseindex)
9434 as_bad (_("0x%lx out range of signed 32bit displacement"),
9435 (long) exp->X_add_number);
9441 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9442 else if (exp->X_op != O_constant
9443 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9444 && exp_seg != absolute_section
9445 && exp_seg != text_section
9446 && exp_seg != data_section
9447 && exp_seg != bss_section
9448 && exp_seg != undefined_section
9449 && !bfd_is_com_section (exp_seg))
9451 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9456 /* Check if this is a displacement only operand. */
9457 bigdisp = i.types[this_operand];
9458 bigdisp.bitfield.disp8 = 0;
9459 bigdisp.bitfield.disp16 = 0;
9460 bigdisp.bitfield.disp32 = 0;
9461 bigdisp.bitfield.disp32s = 0;
9462 bigdisp.bitfield.disp64 = 0;
9463 if (operand_type_all_zero (&bigdisp))
9464 i.types[this_operand] = operand_type_and (i.types[this_operand],
9470 /* Return the active addressing mode, taking address override and
9471 registers forming the address into consideration. Update the
9472 address override prefix if necessary. */
9474 static enum flag_code
9475 i386_addressing_mode (void)
9477 enum flag_code addr_mode;
9479 if (i.prefix[ADDR_PREFIX])
9480 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9483 addr_mode = flag_code;
9485 #if INFER_ADDR_PREFIX
9486 if (i.mem_operands == 0)
9488 /* Infer address prefix from the first memory operand. */
9489 const reg_entry *addr_reg = i.base_reg;
9491 if (addr_reg == NULL)
9492 addr_reg = i.index_reg;
9496 if (addr_reg->reg_type.bitfield.dword)
9497 addr_mode = CODE_32BIT;
9498 else if (flag_code != CODE_64BIT
9499 && addr_reg->reg_type.bitfield.word)
9500 addr_mode = CODE_16BIT;
9502 if (addr_mode != flag_code)
9504 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9506 /* Change the size of any displacement too. At most one
9507 of Disp16 or Disp32 is set.
9508 FIXME. There doesn't seem to be any real need for
9509 separate Disp16 and Disp32 flags. The same goes for
9510 Imm16 and Imm32. Removing them would probably clean
9511 up the code quite a lot. */
9512 if (flag_code != CODE_64BIT
9513 && (i.types[this_operand].bitfield.disp16
9514 || i.types[this_operand].bitfield.disp32))
9515 i.types[this_operand]
9516 = operand_type_xor (i.types[this_operand], disp16_32);
9526 /* Make sure the memory operand we've been dealt is valid.
9527 Return 1 on success, 0 on a failure. */
9530 i386_index_check (const char *operand_string)
9532 const char *kind = "base/index";
9533 enum flag_code addr_mode = i386_addressing_mode ();
9535 if (current_templates->start->opcode_modifier.isstring
9536 && !current_templates->start->opcode_modifier.immext
9537 && (current_templates->end[-1].opcode_modifier.isstring
9540 /* Memory operands of string insns are special in that they only allow
9541 a single register (rDI, rSI, or rBX) as their memory address. */
9542 const reg_entry *expected_reg;
9543 static const char *di_si[][2] =
9549 static const char *bx[] = { "ebx", "bx", "rbx" };
9551 kind = "string address";
9553 if (current_templates->start->opcode_modifier.repprefixok)
9555 i386_operand_type type = current_templates->end[-1].operand_types[0];
9557 if (!type.bitfield.baseindex
9558 || ((!i.mem_operands != !intel_syntax)
9559 && current_templates->end[-1].operand_types[1]
9560 .bitfield.baseindex))
9561 type = current_templates->end[-1].operand_types[1];
9562 expected_reg = hash_find (reg_hash,
9563 di_si[addr_mode][type.bitfield.esseg]);
9567 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9569 if (i.base_reg != expected_reg
9571 || operand_type_check (i.types[this_operand], disp))
9573 /* The second memory operand must have the same size as
9577 && !((addr_mode == CODE_64BIT
9578 && i.base_reg->reg_type.bitfield.qword)
9579 || (addr_mode == CODE_32BIT
9580 ? i.base_reg->reg_type.bitfield.dword
9581 : i.base_reg->reg_type.bitfield.word)))
9584 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9586 intel_syntax ? '[' : '(',
9588 expected_reg->reg_name,
9589 intel_syntax ? ']' : ')');
9596 as_bad (_("`%s' is not a valid %s expression"),
9597 operand_string, kind);
9602 if (addr_mode != CODE_16BIT)
9604 /* 32-bit/64-bit checks. */
9606 && ((addr_mode == CODE_64BIT
9607 ? !i.base_reg->reg_type.bitfield.qword
9608 : !i.base_reg->reg_type.bitfield.dword)
9609 || (i.index_reg && i.base_reg->reg_num == RegIP)
9610 || i.base_reg->reg_num == RegIZ))
9612 && !i.index_reg->reg_type.bitfield.xmmword
9613 && !i.index_reg->reg_type.bitfield.ymmword
9614 && !i.index_reg->reg_type.bitfield.zmmword
9615 && ((addr_mode == CODE_64BIT
9616 ? !i.index_reg->reg_type.bitfield.qword
9617 : !i.index_reg->reg_type.bitfield.dword)
9618 || !i.index_reg->reg_type.bitfield.baseindex)))
9621 /* bndmk, bndldx, and bndstx have special restrictions. */
9622 if (current_templates->start->base_opcode == 0xf30f1b
9623 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9625 /* They cannot use RIP-relative addressing. */
9626 if (i.base_reg && i.base_reg->reg_num == RegIP)
9628 as_bad (_("`%s' cannot be used here"), operand_string);
9632 /* bndldx and bndstx ignore their scale factor. */
9633 if (current_templates->start->base_opcode != 0xf30f1b
9634 && i.log2_scale_factor)
9635 as_warn (_("register scaling is being ignored here"));
9640 /* 16-bit checks. */
9642 && (!i.base_reg->reg_type.bitfield.word
9643 || !i.base_reg->reg_type.bitfield.baseindex))
9645 && (!i.index_reg->reg_type.bitfield.word
9646 || !i.index_reg->reg_type.bitfield.baseindex
9648 && i.base_reg->reg_num < 6
9649 && i.index_reg->reg_num >= 6
9650 && i.log2_scale_factor == 0))))
9657 /* Handle vector immediates. */
9660 RC_SAE_immediate (const char *imm_start)
9662 unsigned int match_found, j;
9663 const char *pstr = imm_start;
9671 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9673 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9677 rc_op.type = RC_NamesTable[j].type;
9678 rc_op.operand = this_operand;
9679 i.rounding = &rc_op;
9683 as_bad (_("duplicated `%s'"), imm_start);
9686 pstr += RC_NamesTable[j].len;
9696 as_bad (_("Missing '}': '%s'"), imm_start);
9699 /* RC/SAE immediate string should contain nothing more. */;
9702 as_bad (_("Junk after '}': '%s'"), imm_start);
9706 exp = &im_expressions[i.imm_operands++];
9707 i.op[this_operand].imms = exp;
9709 exp->X_op = O_constant;
9710 exp->X_add_number = 0;
9711 exp->X_add_symbol = (symbolS *) 0;
9712 exp->X_op_symbol = (symbolS *) 0;
9714 i.types[this_operand].bitfield.imm8 = 1;
9718 /* Only string instructions can have a second memory operand, so
9719 reduce current_templates to just those if it contains any. */
9721 maybe_adjust_templates (void)
9723 const insn_template *t;
9725 gas_assert (i.mem_operands == 1);
9727 for (t = current_templates->start; t < current_templates->end; ++t)
9728 if (t->opcode_modifier.isstring)
9731 if (t < current_templates->end)
9733 static templates aux_templates;
9734 bfd_boolean recheck;
9736 aux_templates.start = t;
9737 for (; t < current_templates->end; ++t)
9738 if (!t->opcode_modifier.isstring)
9740 aux_templates.end = t;
9742 /* Determine whether to re-check the first memory operand. */
9743 recheck = (aux_templates.start != current_templates->start
9744 || t != current_templates->end);
9746 current_templates = &aux_templates;
9751 if (i.memop1_string != NULL
9752 && i386_index_check (i.memop1_string) == 0)
9761 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9765 i386_att_operand (char *operand_string)
9769 char *op_string = operand_string;
9771 if (is_space_char (*op_string))
9774 /* We check for an absolute prefix (differentiating,
9775 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9776 if (*op_string == ABSOLUTE_PREFIX)
9779 if (is_space_char (*op_string))
9781 i.types[this_operand].bitfield.jumpabsolute = 1;
9784 /* Check if operand is a register. */
9785 if ((r = parse_register (op_string, &end_op)) != NULL)
9787 i386_operand_type temp;
9789 /* Check for a segment override by searching for ':' after a
9790 segment register. */
9792 if (is_space_char (*op_string))
9794 if (*op_string == ':'
9795 && (r->reg_type.bitfield.sreg2
9796 || r->reg_type.bitfield.sreg3))
9801 i.seg[i.mem_operands] = &es;
9804 i.seg[i.mem_operands] = &cs;
9807 i.seg[i.mem_operands] = &ss;
9810 i.seg[i.mem_operands] = &ds;
9813 i.seg[i.mem_operands] = &fs;
9816 i.seg[i.mem_operands] = &gs;
9820 /* Skip the ':' and whitespace. */
9822 if (is_space_char (*op_string))
9825 if (!is_digit_char (*op_string)
9826 && !is_identifier_char (*op_string)
9827 && *op_string != '('
9828 && *op_string != ABSOLUTE_PREFIX)
9830 as_bad (_("bad memory operand `%s'"), op_string);
9833 /* Handle case of %es:*foo. */
9834 if (*op_string == ABSOLUTE_PREFIX)
9837 if (is_space_char (*op_string))
9839 i.types[this_operand].bitfield.jumpabsolute = 1;
9841 goto do_memory_reference;
9844 /* Handle vector operations. */
9845 if (*op_string == '{')
9847 op_string = check_VecOperations (op_string, NULL);
9848 if (op_string == NULL)
9854 as_bad (_("junk `%s' after register"), op_string);
9858 temp.bitfield.baseindex = 0;
9859 i.types[this_operand] = operand_type_or (i.types[this_operand],
9861 i.types[this_operand].bitfield.unspecified = 0;
9862 i.op[this_operand].regs = r;
9865 else if (*op_string == REGISTER_PREFIX)
9867 as_bad (_("bad register name `%s'"), op_string);
9870 else if (*op_string == IMMEDIATE_PREFIX)
9873 if (i.types[this_operand].bitfield.jumpabsolute)
9875 as_bad (_("immediate operand illegal with absolute jump"));
9878 if (!i386_immediate (op_string))
9881 else if (RC_SAE_immediate (operand_string))
9883 /* If it is a RC or SAE immediate, do nothing. */
9886 else if (is_digit_char (*op_string)
9887 || is_identifier_char (*op_string)
9888 || *op_string == '"'
9889 || *op_string == '(')
9891 /* This is a memory reference of some sort. */
9894 /* Start and end of displacement string expression (if found). */
9895 char *displacement_string_start;
9896 char *displacement_string_end;
9899 do_memory_reference:
9900 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9902 if ((i.mem_operands == 1
9903 && !current_templates->start->opcode_modifier.isstring)
9904 || i.mem_operands == 2)
9906 as_bad (_("too many memory references for `%s'"),
9907 current_templates->start->name);
9911 /* Check for base index form. We detect the base index form by
9912 looking for an ')' at the end of the operand, searching
9913 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9915 base_string = op_string + strlen (op_string);
9917 /* Handle vector operations. */
9918 vop_start = strchr (op_string, '{');
9919 if (vop_start && vop_start < base_string)
9921 if (check_VecOperations (vop_start, base_string) == NULL)
9923 base_string = vop_start;
9927 if (is_space_char (*base_string))
9930 /* If we only have a displacement, set-up for it to be parsed later. */
9931 displacement_string_start = op_string;
9932 displacement_string_end = base_string + 1;
9934 if (*base_string == ')')
9937 unsigned int parens_balanced = 1;
9938 /* We've already checked that the number of left & right ()'s are
9939 equal, so this loop will not be infinite. */
9943 if (*base_string == ')')
9945 if (*base_string == '(')
9948 while (parens_balanced);
9950 temp_string = base_string;
9952 /* Skip past '(' and whitespace. */
9954 if (is_space_char (*base_string))
9957 if (*base_string == ','
9958 || ((i.base_reg = parse_register (base_string, &end_op))
9961 displacement_string_end = temp_string;
9963 i.types[this_operand].bitfield.baseindex = 1;
9967 base_string = end_op;
9968 if (is_space_char (*base_string))
9972 /* There may be an index reg or scale factor here. */
9973 if (*base_string == ',')
9976 if (is_space_char (*base_string))
9979 if ((i.index_reg = parse_register (base_string, &end_op))
9982 base_string = end_op;
9983 if (is_space_char (*base_string))
9985 if (*base_string == ',')
9988 if (is_space_char (*base_string))
9991 else if (*base_string != ')')
9993 as_bad (_("expecting `,' or `)' "
9994 "after index register in `%s'"),
9999 else if (*base_string == REGISTER_PREFIX)
10001 end_op = strchr (base_string, ',');
10004 as_bad (_("bad register name `%s'"), base_string);
10008 /* Check for scale factor. */
10009 if (*base_string != ')')
10011 char *end_scale = i386_scale (base_string);
10016 base_string = end_scale;
10017 if (is_space_char (*base_string))
10019 if (*base_string != ')')
10021 as_bad (_("expecting `)' "
10022 "after scale factor in `%s'"),
10027 else if (!i.index_reg)
10029 as_bad (_("expecting index register or scale factor "
10030 "after `,'; got '%c'"),
10035 else if (*base_string != ')')
10037 as_bad (_("expecting `,' or `)' "
10038 "after base register in `%s'"),
10043 else if (*base_string == REGISTER_PREFIX)
10045 end_op = strchr (base_string, ',');
10048 as_bad (_("bad register name `%s'"), base_string);
10053 /* If there's an expression beginning the operand, parse it,
10054 assuming displacement_string_start and
10055 displacement_string_end are meaningful. */
10056 if (displacement_string_start != displacement_string_end)
10058 if (!i386_displacement (displacement_string_start,
10059 displacement_string_end))
10063 /* Special case for (%dx) while doing input/output op. */
10065 && i.base_reg->reg_type.bitfield.inoutportreg
10066 && i.index_reg == 0
10067 && i.log2_scale_factor == 0
10068 && i.seg[i.mem_operands] == 0
10069 && !operand_type_check (i.types[this_operand], disp))
10071 i.types[this_operand] = i.base_reg->reg_type;
10075 if (i386_index_check (operand_string) == 0)
10077 i.flags[this_operand] |= Operand_Mem;
10078 if (i.mem_operands == 0)
10079 i.memop1_string = xstrdup (operand_string);
10084 /* It's not a memory operand; argh! */
10085 as_bad (_("invalid char %s beginning operand %d `%s'"),
10086 output_invalid (*op_string),
10091 return 1; /* Normal return. */
10094 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10095 that an rs_machine_dependent frag may reach. */
10098 i386_frag_max_var (fragS *frag)
10100 /* The only relaxable frags are for jumps.
10101 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10102 gas_assert (frag->fr_type == rs_machine_dependent);
10103 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10108 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
10110 /* STT_GNU_IFUNC symbol must go through PLT. */
10111 if ((symbol_get_bfdsym (fr_symbol)->flags
10112 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10115 if (!S_IS_EXTERNAL (fr_symbol))
10116 /* Symbol may be weak or local. */
10117 return !S_IS_WEAK (fr_symbol);
10119 /* Global symbols with non-default visibility can't be preempted. */
10120 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10123 if (fr_var != NO_RELOC)
10124 switch ((enum bfd_reloc_code_real) fr_var)
10126 case BFD_RELOC_386_PLT32:
10127 case BFD_RELOC_X86_64_PLT32:
10128 /* Symbol with PLT relocation may be preempted. */
10134 /* Global symbols with default visibility in a shared library may be
10135 preempted by another definition. */
10140 /* md_estimate_size_before_relax()
10142 Called just before relax() for rs_machine_dependent frags. The x86
10143 assembler uses these frags to handle variable size jump
10146 Any symbol that is now undefined will not become defined.
10147 Return the correct fr_subtype in the frag.
10148 Return the initial "guess for variable size of frag" to caller.
10149 The guess is actually the growth beyond the fixed part. Whatever
10150 we do to grow the fixed or variable part contributes to our
10154 md_estimate_size_before_relax (fragS *fragP, segT segment)
10156 /* We've already got fragP->fr_subtype right; all we have to do is
10157 check for un-relaxable symbols. On an ELF system, we can't relax
10158 an externally visible symbol, because it may be overridden by a
10160 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
10161 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10163 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10166 #if defined (OBJ_COFF) && defined (TE_PE)
10167 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
10168 && S_IS_WEAK (fragP->fr_symbol))
10172 /* Symbol is undefined in this segment, or we need to keep a
10173 reloc so that weak symbols can be overridden. */
10174 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
10175 enum bfd_reloc_code_real reloc_type;
10176 unsigned char *opcode;
10179 if (fragP->fr_var != NO_RELOC)
10180 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
10181 else if (size == 2)
10182 reloc_type = BFD_RELOC_16_PCREL;
10183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10184 else if (need_plt32_p (fragP->fr_symbol))
10185 reloc_type = BFD_RELOC_X86_64_PLT32;
10188 reloc_type = BFD_RELOC_32_PCREL;
10190 old_fr_fix = fragP->fr_fix;
10191 opcode = (unsigned char *) fragP->fr_opcode;
10193 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
10196 /* Make jmp (0xeb) a (d)word displacement jump. */
10198 fragP->fr_fix += size;
10199 fix_new (fragP, old_fr_fix, size,
10201 fragP->fr_offset, 1,
10207 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
10209 /* Negate the condition, and branch past an
10210 unconditional jump. */
10213 /* Insert an unconditional jump. */
10215 /* We added two extra opcode bytes, and have a two byte
10217 fragP->fr_fix += 2 + 2;
10218 fix_new (fragP, old_fr_fix + 2, 2,
10220 fragP->fr_offset, 1,
10224 /* Fall through. */
10227 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10231 fragP->fr_fix += 1;
10232 fixP = fix_new (fragP, old_fr_fix, 1,
10234 fragP->fr_offset, 1,
10235 BFD_RELOC_8_PCREL);
10236 fixP->fx_signed = 1;
10240 /* This changes the byte-displacement jump 0x7N
10241 to the (d)word-displacement jump 0x0f,0x8N. */
10242 opcode[1] = opcode[0] + 0x10;
10243 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10244 /* We've added an opcode byte. */
10245 fragP->fr_fix += 1 + size;
10246 fix_new (fragP, old_fr_fix + 1, size,
10248 fragP->fr_offset, 1,
10253 BAD_CASE (fragP->fr_subtype);
10257 return fragP->fr_fix - old_fr_fix;
10260 /* Guess size depending on current relax state. Initially the relax
10261 state will correspond to a short jump and we return 1, because
10262 the variable part of the frag (the branch offset) is one byte
10263 long. However, we can relax a section more than once and in that
10264 case we must either set fr_subtype back to the unrelaxed state,
10265 or return the value for the appropriate branch. */
10266 return md_relax_table[fragP->fr_subtype].rlx_length;
10269 /* Called after relax() is finished.
10271 In: Address of frag.
10272 fr_type == rs_machine_dependent.
10273 fr_subtype is what the address relaxed to.
10275 Out: Any fixSs and constants are set up.
10276 Caller will turn frag into a ".space 0". */
10279 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10282 unsigned char *opcode;
10283 unsigned char *where_to_put_displacement = NULL;
10284 offsetT target_address;
10285 offsetT opcode_address;
10286 unsigned int extension = 0;
10287 offsetT displacement_from_opcode_start;
10289 opcode = (unsigned char *) fragP->fr_opcode;
10291 /* Address we want to reach in file space. */
10292 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10294 /* Address opcode resides at in file space. */
10295 opcode_address = fragP->fr_address + fragP->fr_fix;
10297 /* Displacement from opcode start to fill into instruction. */
10298 displacement_from_opcode_start = target_address - opcode_address;
10300 if ((fragP->fr_subtype & BIG) == 0)
10302 /* Don't have to change opcode. */
10303 extension = 1; /* 1 opcode + 1 displacement */
10304 where_to_put_displacement = &opcode[1];
10308 if (no_cond_jump_promotion
10309 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10310 as_warn_where (fragP->fr_file, fragP->fr_line,
10311 _("long jump required"));
10313 switch (fragP->fr_subtype)
10315 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10316 extension = 4; /* 1 opcode + 4 displacement */
10318 where_to_put_displacement = &opcode[1];
10321 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10322 extension = 2; /* 1 opcode + 2 displacement */
10324 where_to_put_displacement = &opcode[1];
10327 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10328 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10329 extension = 5; /* 2 opcode + 4 displacement */
10330 opcode[1] = opcode[0] + 0x10;
10331 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10332 where_to_put_displacement = &opcode[2];
10335 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10336 extension = 3; /* 2 opcode + 2 displacement */
10337 opcode[1] = opcode[0] + 0x10;
10338 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10339 where_to_put_displacement = &opcode[2];
10342 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10347 where_to_put_displacement = &opcode[3];
10351 BAD_CASE (fragP->fr_subtype);
10356 /* If size if less then four we are sure that the operand fits,
10357 but if it's 4, then it could be that the displacement is larger
10359 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10361 && ((addressT) (displacement_from_opcode_start - extension
10362 + ((addressT) 1 << 31))
10363 > (((addressT) 2 << 31) - 1)))
10365 as_bad_where (fragP->fr_file, fragP->fr_line,
10366 _("jump target out of range"));
10367 /* Make us emit 0. */
10368 displacement_from_opcode_start = extension;
10370 /* Now put displacement after opcode. */
10371 md_number_to_chars ((char *) where_to_put_displacement,
10372 (valueT) (displacement_from_opcode_start - extension),
10373 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10374 fragP->fr_fix += extension;
10377 /* Apply a fixup (fixP) to segment data, once it has been determined
10378 by our caller that we have all the info we need to fix it up.
10380 Parameter valP is the pointer to the value of the bits.
10382 On the 386, immediates, displacements, and data pointers are all in
10383 the same (little-endian) format, so we don't need to care about which
10384 we are handling. */
10387 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10389 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10390 valueT value = *valP;
10392 #if !defined (TE_Mach)
10393 if (fixP->fx_pcrel)
10395 switch (fixP->fx_r_type)
10401 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10404 case BFD_RELOC_X86_64_32S:
10405 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10408 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10411 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10416 if (fixP->fx_addsy != NULL
10417 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10418 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10419 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10420 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10421 && !use_rela_relocations)
10423 /* This is a hack. There should be a better way to handle this.
10424 This covers for the fact that bfd_install_relocation will
10425 subtract the current location (for partial_inplace, PC relative
10426 relocations); see more below. */
10430 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10433 value += fixP->fx_where + fixP->fx_frag->fr_address;
10435 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10438 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10440 if ((sym_seg == seg
10441 || (symbol_section_p (fixP->fx_addsy)
10442 && sym_seg != absolute_section))
10443 && !generic_force_reloc (fixP))
10445 /* Yes, we add the values in twice. This is because
10446 bfd_install_relocation subtracts them out again. I think
10447 bfd_install_relocation is broken, but I don't dare change
10449 value += fixP->fx_where + fixP->fx_frag->fr_address;
10453 #if defined (OBJ_COFF) && defined (TE_PE)
10454 /* For some reason, the PE format does not store a
10455 section address offset for a PC relative symbol. */
10456 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10457 || S_IS_WEAK (fixP->fx_addsy))
10458 value += md_pcrel_from (fixP);
10461 #if defined (OBJ_COFF) && defined (TE_PE)
10462 if (fixP->fx_addsy != NULL
10463 && S_IS_WEAK (fixP->fx_addsy)
10464 /* PR 16858: Do not modify weak function references. */
10465 && ! fixP->fx_pcrel)
10467 #if !defined (TE_PEP)
10468 /* For x86 PE weak function symbols are neither PC-relative
10469 nor do they set S_IS_FUNCTION. So the only reliable way
10470 to detect them is to check the flags of their containing
10472 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10473 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10477 value -= S_GET_VALUE (fixP->fx_addsy);
10481 /* Fix a few things - the dynamic linker expects certain values here,
10482 and we must not disappoint it. */
10483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10484 if (IS_ELF && fixP->fx_addsy)
10485 switch (fixP->fx_r_type)
10487 case BFD_RELOC_386_PLT32:
10488 case BFD_RELOC_X86_64_PLT32:
10489 /* Make the jump instruction point to the address of the operand. At
10490 runtime we merely add the offset to the actual PLT entry. */
10494 case BFD_RELOC_386_TLS_GD:
10495 case BFD_RELOC_386_TLS_LDM:
10496 case BFD_RELOC_386_TLS_IE_32:
10497 case BFD_RELOC_386_TLS_IE:
10498 case BFD_RELOC_386_TLS_GOTIE:
10499 case BFD_RELOC_386_TLS_GOTDESC:
10500 case BFD_RELOC_X86_64_TLSGD:
10501 case BFD_RELOC_X86_64_TLSLD:
10502 case BFD_RELOC_X86_64_GOTTPOFF:
10503 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10504 value = 0; /* Fully resolved at runtime. No addend. */
10506 case BFD_RELOC_386_TLS_LE:
10507 case BFD_RELOC_386_TLS_LDO_32:
10508 case BFD_RELOC_386_TLS_LE_32:
10509 case BFD_RELOC_X86_64_DTPOFF32:
10510 case BFD_RELOC_X86_64_DTPOFF64:
10511 case BFD_RELOC_X86_64_TPOFF32:
10512 case BFD_RELOC_X86_64_TPOFF64:
10513 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10516 case BFD_RELOC_386_TLS_DESC_CALL:
10517 case BFD_RELOC_X86_64_TLSDESC_CALL:
10518 value = 0; /* Fully resolved at runtime. No addend. */
10519 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10523 case BFD_RELOC_VTABLE_INHERIT:
10524 case BFD_RELOC_VTABLE_ENTRY:
10531 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10533 #endif /* !defined (TE_Mach) */
10535 /* Are we finished with this relocation now? */
10536 if (fixP->fx_addsy == NULL)
10538 #if defined (OBJ_COFF) && defined (TE_PE)
10539 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10542 /* Remember value for tc_gen_reloc. */
10543 fixP->fx_addnumber = value;
10544 /* Clear out the frag for now. */
10548 else if (use_rela_relocations)
10550 fixP->fx_no_overflow = 1;
10551 /* Remember value for tc_gen_reloc. */
10552 fixP->fx_addnumber = value;
10556 md_number_to_chars (p, value, fixP->fx_size);
10560 md_atof (int type, char *litP, int *sizeP)
10562 /* This outputs the LITTLENUMs in REVERSE order;
10563 in accord with the bigendian 386. */
10564 return ieee_md_atof (type, litP, sizeP, FALSE);
10567 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10570 output_invalid (int c)
10573 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10576 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10577 "(0x%x)", (unsigned char) c);
10578 return output_invalid_buf;
10581 /* REG_STRING starts *before* REGISTER_PREFIX. */
10583 static const reg_entry *
10584 parse_real_register (char *reg_string, char **end_op)
10586 char *s = reg_string;
10588 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10589 const reg_entry *r;
10591 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10592 if (*s == REGISTER_PREFIX)
10595 if (is_space_char (*s))
10598 p = reg_name_given;
10599 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10601 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10602 return (const reg_entry *) NULL;
10606 /* For naked regs, make sure that we are not dealing with an identifier.
10607 This prevents confusing an identifier like `eax_var' with register
10609 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10610 return (const reg_entry *) NULL;
10614 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10616 /* Handle floating point regs, allowing spaces in the (i) part. */
10617 if (r == i386_regtab /* %st is first entry of table */)
10619 if (!cpu_arch_flags.bitfield.cpu8087
10620 && !cpu_arch_flags.bitfield.cpu287
10621 && !cpu_arch_flags.bitfield.cpu387)
10622 return (const reg_entry *) NULL;
10624 if (is_space_char (*s))
10629 if (is_space_char (*s))
10631 if (*s >= '0' && *s <= '7')
10633 int fpr = *s - '0';
10635 if (is_space_char (*s))
10640 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10645 /* We have "%st(" then garbage. */
10646 return (const reg_entry *) NULL;
10650 if (r == NULL || allow_pseudo_reg)
10653 if (operand_type_all_zero (&r->reg_type))
10654 return (const reg_entry *) NULL;
10656 if ((r->reg_type.bitfield.dword
10657 || r->reg_type.bitfield.sreg3
10658 || r->reg_type.bitfield.control
10659 || r->reg_type.bitfield.debug
10660 || r->reg_type.bitfield.test)
10661 && !cpu_arch_flags.bitfield.cpui386)
10662 return (const reg_entry *) NULL;
10664 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10665 return (const reg_entry *) NULL;
10667 if (!cpu_arch_flags.bitfield.cpuavx512f)
10669 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10670 return (const reg_entry *) NULL;
10672 if (!cpu_arch_flags.bitfield.cpuavx)
10674 if (r->reg_type.bitfield.ymmword)
10675 return (const reg_entry *) NULL;
10677 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10678 return (const reg_entry *) NULL;
10682 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10683 return (const reg_entry *) NULL;
10685 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10686 if (!allow_index_reg && r->reg_num == RegIZ)
10687 return (const reg_entry *) NULL;
10689 /* Upper 16 vector registers are only available with VREX in 64bit
10690 mode, and require EVEX encoding. */
10691 if (r->reg_flags & RegVRex)
10693 if (!cpu_arch_flags.bitfield.cpuavx512f
10694 || flag_code != CODE_64BIT)
10695 return (const reg_entry *) NULL;
10697 i.vec_encoding = vex_encoding_evex;
10700 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10701 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10702 && flag_code != CODE_64BIT)
10703 return (const reg_entry *) NULL;
10705 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10706 return (const reg_entry *) NULL;
10711 /* REG_STRING starts *before* REGISTER_PREFIX. */
10713 static const reg_entry *
10714 parse_register (char *reg_string, char **end_op)
10716 const reg_entry *r;
10718 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10719 r = parse_real_register (reg_string, end_op);
10724 char *save = input_line_pointer;
10728 input_line_pointer = reg_string;
10729 c = get_symbol_name (®_string);
10730 symbolP = symbol_find (reg_string);
10731 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10733 const expressionS *e = symbol_get_value_expression (symbolP);
10735 know (e->X_op == O_register);
10736 know (e->X_add_number >= 0
10737 && (valueT) e->X_add_number < i386_regtab_size);
10738 r = i386_regtab + e->X_add_number;
10739 if ((r->reg_flags & RegVRex))
10740 i.vec_encoding = vex_encoding_evex;
10741 *end_op = input_line_pointer;
10743 *input_line_pointer = c;
10744 input_line_pointer = save;
10750 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10752 const reg_entry *r;
10753 char *end = input_line_pointer;
10756 r = parse_register (name, &input_line_pointer);
10757 if (r && end <= input_line_pointer)
10759 *nextcharP = *input_line_pointer;
10760 *input_line_pointer = 0;
10761 e->X_op = O_register;
10762 e->X_add_number = r - i386_regtab;
10765 input_line_pointer = end;
10767 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10771 md_operand (expressionS *e)
10774 const reg_entry *r;
10776 switch (*input_line_pointer)
10778 case REGISTER_PREFIX:
10779 r = parse_real_register (input_line_pointer, &end);
10782 e->X_op = O_register;
10783 e->X_add_number = r - i386_regtab;
10784 input_line_pointer = end;
10789 gas_assert (intel_syntax);
10790 end = input_line_pointer++;
10792 if (*input_line_pointer == ']')
10794 ++input_line_pointer;
10795 e->X_op_symbol = make_expr_symbol (e);
10796 e->X_add_symbol = NULL;
10797 e->X_add_number = 0;
10802 e->X_op = O_absent;
10803 input_line_pointer = end;
10810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10811 const char *md_shortopts = "kVQ:sqnO::";
10813 const char *md_shortopts = "qnO::";
10816 #define OPTION_32 (OPTION_MD_BASE + 0)
10817 #define OPTION_64 (OPTION_MD_BASE + 1)
10818 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10819 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10820 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10821 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10822 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10823 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10824 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10825 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10826 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10827 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10828 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10829 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10830 #define OPTION_X32 (OPTION_MD_BASE + 14)
10831 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10832 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10833 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10834 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10835 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10836 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10837 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10838 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10839 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10840 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10841 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10843 struct option md_longopts[] =
10845 {"32", no_argument, NULL, OPTION_32},
10846 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10847 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10848 {"64", no_argument, NULL, OPTION_64},
10850 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10851 {"x32", no_argument, NULL, OPTION_X32},
10852 {"mshared", no_argument, NULL, OPTION_MSHARED},
10853 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
10855 {"divide", no_argument, NULL, OPTION_DIVIDE},
10856 {"march", required_argument, NULL, OPTION_MARCH},
10857 {"mtune", required_argument, NULL, OPTION_MTUNE},
10858 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10859 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10860 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10861 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10862 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10863 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10864 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10865 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10866 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10867 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10868 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10869 # if defined (TE_PE) || defined (TE_PEP)
10870 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10872 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10873 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10874 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10875 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10876 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10877 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10878 {NULL, no_argument, NULL, 0}
10880 size_t md_longopts_size = sizeof (md_longopts);
10883 md_parse_option (int c, const char *arg)
10886 char *arch, *next, *saved;
10891 optimize_align_code = 0;
10895 quiet_warnings = 1;
10898 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10899 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10900 should be emitted or not. FIXME: Not implemented. */
10904 /* -V: SVR4 argument to print version ID. */
10906 print_version_id ();
10909 /* -k: Ignore for FreeBSD compatibility. */
10914 /* -s: On i386 Solaris, this tells the native assembler to use
10915 .stab instead of .stab.excl. We always use .stab anyhow. */
10918 case OPTION_MSHARED:
10922 case OPTION_X86_USED_NOTE:
10923 if (strcasecmp (arg, "yes") == 0)
10925 else if (strcasecmp (arg, "no") == 0)
10928 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
10933 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10934 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10937 const char **list, **l;
10939 list = bfd_target_list ();
10940 for (l = list; *l != NULL; l++)
10941 if (CONST_STRNEQ (*l, "elf64-x86-64")
10942 || strcmp (*l, "coff-x86-64") == 0
10943 || strcmp (*l, "pe-x86-64") == 0
10944 || strcmp (*l, "pei-x86-64") == 0
10945 || strcmp (*l, "mach-o-x86-64") == 0)
10947 default_arch = "x86_64";
10951 as_fatal (_("no compiled in support for x86_64"));
10957 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10961 const char **list, **l;
10963 list = bfd_target_list ();
10964 for (l = list; *l != NULL; l++)
10965 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10967 default_arch = "x86_64:32";
10971 as_fatal (_("no compiled in support for 32bit x86_64"));
10975 as_fatal (_("32bit x86_64 is only supported for ELF"));
10980 default_arch = "i386";
10983 case OPTION_DIVIDE:
10984 #ifdef SVR4_COMMENT_CHARS
10989 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10991 for (s = i386_comment_chars; *s != '\0'; s++)
10995 i386_comment_chars = n;
11001 saved = xstrdup (arg);
11003 /* Allow -march=+nosse. */
11009 as_fatal (_("invalid -march= option: `%s'"), arg);
11010 next = strchr (arch, '+');
11013 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11015 if (strcmp (arch, cpu_arch [j].name) == 0)
11018 if (! cpu_arch[j].flags.bitfield.cpui386)
11021 cpu_arch_name = cpu_arch[j].name;
11022 cpu_sub_arch_name = NULL;
11023 cpu_arch_flags = cpu_arch[j].flags;
11024 cpu_arch_isa = cpu_arch[j].type;
11025 cpu_arch_isa_flags = cpu_arch[j].flags;
11026 if (!cpu_arch_tune_set)
11028 cpu_arch_tune = cpu_arch_isa;
11029 cpu_arch_tune_flags = cpu_arch_isa_flags;
11033 else if (*cpu_arch [j].name == '.'
11034 && strcmp (arch, cpu_arch [j].name + 1) == 0)
11036 /* ISA extension. */
11037 i386_cpu_flags flags;
11039 flags = cpu_flags_or (cpu_arch_flags,
11040 cpu_arch[j].flags);
11042 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11044 if (cpu_sub_arch_name)
11046 char *name = cpu_sub_arch_name;
11047 cpu_sub_arch_name = concat (name,
11049 (const char *) NULL);
11053 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
11054 cpu_arch_flags = flags;
11055 cpu_arch_isa_flags = flags;
11059 = cpu_flags_or (cpu_arch_isa_flags,
11060 cpu_arch[j].flags);
11065 if (j >= ARRAY_SIZE (cpu_arch))
11067 /* Disable an ISA extension. */
11068 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11069 if (strcmp (arch, cpu_noarch [j].name) == 0)
11071 i386_cpu_flags flags;
11073 flags = cpu_flags_and_not (cpu_arch_flags,
11074 cpu_noarch[j].flags);
11075 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11077 if (cpu_sub_arch_name)
11079 char *name = cpu_sub_arch_name;
11080 cpu_sub_arch_name = concat (arch,
11081 (const char *) NULL);
11085 cpu_sub_arch_name = xstrdup (arch);
11086 cpu_arch_flags = flags;
11087 cpu_arch_isa_flags = flags;
11092 if (j >= ARRAY_SIZE (cpu_noarch))
11093 j = ARRAY_SIZE (cpu_arch);
11096 if (j >= ARRAY_SIZE (cpu_arch))
11097 as_fatal (_("invalid -march= option: `%s'"), arg);
11101 while (next != NULL);
11107 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11108 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11110 if (strcmp (arg, cpu_arch [j].name) == 0)
11112 cpu_arch_tune_set = 1;
11113 cpu_arch_tune = cpu_arch [j].type;
11114 cpu_arch_tune_flags = cpu_arch[j].flags;
11118 if (j >= ARRAY_SIZE (cpu_arch))
11119 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11122 case OPTION_MMNEMONIC:
11123 if (strcasecmp (arg, "att") == 0)
11124 intel_mnemonic = 0;
11125 else if (strcasecmp (arg, "intel") == 0)
11126 intel_mnemonic = 1;
11128 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
11131 case OPTION_MSYNTAX:
11132 if (strcasecmp (arg, "att") == 0)
11134 else if (strcasecmp (arg, "intel") == 0)
11137 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
11140 case OPTION_MINDEX_REG:
11141 allow_index_reg = 1;
11144 case OPTION_MNAKED_REG:
11145 allow_naked_reg = 1;
11148 case OPTION_MSSE2AVX:
11152 case OPTION_MSSE_CHECK:
11153 if (strcasecmp (arg, "error") == 0)
11154 sse_check = check_error;
11155 else if (strcasecmp (arg, "warning") == 0)
11156 sse_check = check_warning;
11157 else if (strcasecmp (arg, "none") == 0)
11158 sse_check = check_none;
11160 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
11163 case OPTION_MOPERAND_CHECK:
11164 if (strcasecmp (arg, "error") == 0)
11165 operand_check = check_error;
11166 else if (strcasecmp (arg, "warning") == 0)
11167 operand_check = check_warning;
11168 else if (strcasecmp (arg, "none") == 0)
11169 operand_check = check_none;
11171 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11174 case OPTION_MAVXSCALAR:
11175 if (strcasecmp (arg, "128") == 0)
11176 avxscalar = vex128;
11177 else if (strcasecmp (arg, "256") == 0)
11178 avxscalar = vex256;
11180 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
11183 case OPTION_MADD_BND_PREFIX:
11184 add_bnd_prefix = 1;
11187 case OPTION_MEVEXLIG:
11188 if (strcmp (arg, "128") == 0)
11189 evexlig = evexl128;
11190 else if (strcmp (arg, "256") == 0)
11191 evexlig = evexl256;
11192 else if (strcmp (arg, "512") == 0)
11193 evexlig = evexl512;
11195 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11198 case OPTION_MEVEXRCIG:
11199 if (strcmp (arg, "rne") == 0)
11201 else if (strcmp (arg, "rd") == 0)
11203 else if (strcmp (arg, "ru") == 0)
11205 else if (strcmp (arg, "rz") == 0)
11208 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11211 case OPTION_MEVEXWIG:
11212 if (strcmp (arg, "0") == 0)
11214 else if (strcmp (arg, "1") == 0)
11217 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11220 # if defined (TE_PE) || defined (TE_PEP)
11221 case OPTION_MBIG_OBJ:
11226 case OPTION_MOMIT_LOCK_PREFIX:
11227 if (strcasecmp (arg, "yes") == 0)
11228 omit_lock_prefix = 1;
11229 else if (strcasecmp (arg, "no") == 0)
11230 omit_lock_prefix = 0;
11232 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11235 case OPTION_MFENCE_AS_LOCK_ADD:
11236 if (strcasecmp (arg, "yes") == 0)
11238 else if (strcasecmp (arg, "no") == 0)
11241 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11244 case OPTION_MRELAX_RELOCATIONS:
11245 if (strcasecmp (arg, "yes") == 0)
11246 generate_relax_relocations = 1;
11247 else if (strcasecmp (arg, "no") == 0)
11248 generate_relax_relocations = 0;
11250 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11253 case OPTION_MAMD64:
11257 case OPTION_MINTEL64:
11265 /* Turn off -Os. */
11266 optimize_for_space = 0;
11268 else if (*arg == 's')
11270 optimize_for_space = 1;
11271 /* Turn on all encoding optimizations. */
11276 optimize = atoi (arg);
11277 /* Turn off -Os. */
11278 optimize_for_space = 0;
11288 #define MESSAGE_TEMPLATE \
11292 output_message (FILE *stream, char *p, char *message, char *start,
11293 int *left_p, const char *name, int len)
11295 int size = sizeof (MESSAGE_TEMPLATE);
11296 int left = *left_p;
11298 /* Reserve 2 spaces for ", " or ",\0" */
11301 /* Check if there is any room. */
11309 p = mempcpy (p, name, len);
11313 /* Output the current message now and start a new one. */
11316 fprintf (stream, "%s\n", message);
11318 left = size - (start - message) - len - 2;
11320 gas_assert (left >= 0);
11322 p = mempcpy (p, name, len);
11330 show_arch (FILE *stream, int ext, int check)
11332 static char message[] = MESSAGE_TEMPLATE;
11333 char *start = message + 27;
11335 int size = sizeof (MESSAGE_TEMPLATE);
11342 left = size - (start - message);
11343 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11345 /* Should it be skipped? */
11346 if (cpu_arch [j].skip)
11349 name = cpu_arch [j].name;
11350 len = cpu_arch [j].len;
11353 /* It is an extension. Skip if we aren't asked to show it. */
11364 /* It is an processor. Skip if we show only extension. */
11367 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11369 /* It is an impossible processor - skip. */
11373 p = output_message (stream, p, message, start, &left, name, len);
11376 /* Display disabled extensions. */
11378 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11380 name = cpu_noarch [j].name;
11381 len = cpu_noarch [j].len;
11382 p = output_message (stream, p, message, start, &left, name,
11387 fprintf (stream, "%s\n", message);
11391 md_show_usage (FILE *stream)
11393 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11394 fprintf (stream, _("\
11396 -V print assembler version number\n\
11399 fprintf (stream, _("\
11400 -n Do not optimize code alignment\n\
11401 -q quieten some warnings\n"));
11402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11403 fprintf (stream, _("\
11406 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11407 || defined (TE_PE) || defined (TE_PEP))
11408 fprintf (stream, _("\
11409 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11411 #ifdef SVR4_COMMENT_CHARS
11412 fprintf (stream, _("\
11413 --divide do not treat `/' as a comment character\n"));
11415 fprintf (stream, _("\
11416 --divide ignored\n"));
11418 fprintf (stream, _("\
11419 -march=CPU[,+EXTENSION...]\n\
11420 generate code for CPU and EXTENSION, CPU is one of:\n"));
11421 show_arch (stream, 0, 1);
11422 fprintf (stream, _("\
11423 EXTENSION is combination of:\n"));
11424 show_arch (stream, 1, 0);
11425 fprintf (stream, _("\
11426 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11427 show_arch (stream, 0, 0);
11428 fprintf (stream, _("\
11429 -msse2avx encode SSE instructions with VEX prefix\n"));
11430 fprintf (stream, _("\
11431 -msse-check=[none|error|warning] (default: warning)\n\
11432 check SSE instructions\n"));
11433 fprintf (stream, _("\
11434 -moperand-check=[none|error|warning] (default: warning)\n\
11435 check operand combinations for validity\n"));
11436 fprintf (stream, _("\
11437 -mavxscalar=[128|256] (default: 128)\n\
11438 encode scalar AVX instructions with specific vector\n\
11440 fprintf (stream, _("\
11441 -mevexlig=[128|256|512] (default: 128)\n\
11442 encode scalar EVEX instructions with specific vector\n\
11444 fprintf (stream, _("\
11445 -mevexwig=[0|1] (default: 0)\n\
11446 encode EVEX instructions with specific EVEX.W value\n\
11447 for EVEX.W bit ignored instructions\n"));
11448 fprintf (stream, _("\
11449 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11450 encode EVEX instructions with specific EVEX.RC value\n\
11451 for SAE-only ignored instructions\n"));
11452 fprintf (stream, _("\
11453 -mmnemonic=[att|intel] "));
11454 if (SYSV386_COMPAT)
11455 fprintf (stream, _("(default: att)\n"));
11457 fprintf (stream, _("(default: intel)\n"));
11458 fprintf (stream, _("\
11459 use AT&T/Intel mnemonic\n"));
11460 fprintf (stream, _("\
11461 -msyntax=[att|intel] (default: att)\n\
11462 use AT&T/Intel syntax\n"));
11463 fprintf (stream, _("\
11464 -mindex-reg support pseudo index registers\n"));
11465 fprintf (stream, _("\
11466 -mnaked-reg don't require `%%' prefix for registers\n"));
11467 fprintf (stream, _("\
11468 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11469 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11470 fprintf (stream, _("\
11471 -mshared disable branch optimization for shared code\n"));
11472 fprintf (stream, _("\
11473 -mx86-used-note=[no|yes] "));
11474 if (DEFAULT_X86_USED_NOTE)
11475 fprintf (stream, _("(default: yes)\n"));
11477 fprintf (stream, _("(default: no)\n"));
11478 fprintf (stream, _("\
11479 generate x86 used ISA and feature properties\n"));
11481 #if defined (TE_PE) || defined (TE_PEP)
11482 fprintf (stream, _("\
11483 -mbig-obj generate big object files\n"));
11485 fprintf (stream, _("\
11486 -momit-lock-prefix=[no|yes] (default: no)\n\
11487 strip all lock prefixes\n"));
11488 fprintf (stream, _("\
11489 -mfence-as-lock-add=[no|yes] (default: no)\n\
11490 encode lfence, mfence and sfence as\n\
11491 lock addl $0x0, (%%{re}sp)\n"));
11492 fprintf (stream, _("\
11493 -mrelax-relocations=[no|yes] "));
11494 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11495 fprintf (stream, _("(default: yes)\n"));
11497 fprintf (stream, _("(default: no)\n"));
11498 fprintf (stream, _("\
11499 generate relax relocations\n"));
11500 fprintf (stream, _("\
11501 -mamd64 accept only AMD64 ISA [default]\n"));
11502 fprintf (stream, _("\
11503 -mintel64 accept only Intel64 ISA\n"));
11506 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11507 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11508 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11510 /* Pick the target format to use. */
11513 i386_target_format (void)
11515 if (!strncmp (default_arch, "x86_64", 6))
11517 update_code_flag (CODE_64BIT, 1);
11518 if (default_arch[6] == '\0')
11519 x86_elf_abi = X86_64_ABI;
11521 x86_elf_abi = X86_64_X32_ABI;
11523 else if (!strcmp (default_arch, "i386"))
11524 update_code_flag (CODE_32BIT, 1);
11525 else if (!strcmp (default_arch, "iamcu"))
11527 update_code_flag (CODE_32BIT, 1);
11528 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11530 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11531 cpu_arch_name = "iamcu";
11532 cpu_sub_arch_name = NULL;
11533 cpu_arch_flags = iamcu_flags;
11534 cpu_arch_isa = PROCESSOR_IAMCU;
11535 cpu_arch_isa_flags = iamcu_flags;
11536 if (!cpu_arch_tune_set)
11538 cpu_arch_tune = cpu_arch_isa;
11539 cpu_arch_tune_flags = cpu_arch_isa_flags;
11542 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11543 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11547 as_fatal (_("unknown architecture"));
11549 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11550 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11551 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11552 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11554 switch (OUTPUT_FLAVOR)
11556 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11557 case bfd_target_aout_flavour:
11558 return AOUT_TARGET_FORMAT;
11560 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11561 # if defined (TE_PE) || defined (TE_PEP)
11562 case bfd_target_coff_flavour:
11563 if (flag_code == CODE_64BIT)
11564 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11567 # elif defined (TE_GO32)
11568 case bfd_target_coff_flavour:
11569 return "coff-go32";
11571 case bfd_target_coff_flavour:
11572 return "coff-i386";
11575 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11576 case bfd_target_elf_flavour:
11578 const char *format;
11580 switch (x86_elf_abi)
11583 format = ELF_TARGET_FORMAT;
11586 use_rela_relocations = 1;
11588 format = ELF_TARGET_FORMAT64;
11590 case X86_64_X32_ABI:
11591 use_rela_relocations = 1;
11593 disallow_64bit_reloc = 1;
11594 format = ELF_TARGET_FORMAT32;
11597 if (cpu_arch_isa == PROCESSOR_L1OM)
11599 if (x86_elf_abi != X86_64_ABI)
11600 as_fatal (_("Intel L1OM is 64bit only"));
11601 return ELF_TARGET_L1OM_FORMAT;
11603 else if (cpu_arch_isa == PROCESSOR_K1OM)
11605 if (x86_elf_abi != X86_64_ABI)
11606 as_fatal (_("Intel K1OM is 64bit only"));
11607 return ELF_TARGET_K1OM_FORMAT;
11609 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11611 if (x86_elf_abi != I386_ABI)
11612 as_fatal (_("Intel MCU is 32bit only"));
11613 return ELF_TARGET_IAMCU_FORMAT;
11619 #if defined (OBJ_MACH_O)
11620 case bfd_target_mach_o_flavour:
11621 if (flag_code == CODE_64BIT)
11623 use_rela_relocations = 1;
11625 return "mach-o-x86-64";
11628 return "mach-o-i386";
11636 #endif /* OBJ_MAYBE_ more than one */
11639 md_undefined_symbol (char *name)
11641 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11642 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11643 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11644 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11648 if (symbol_find (name))
11649 as_bad (_("GOT already in symbol table"));
11650 GOT_symbol = symbol_new (name, undefined_section,
11651 (valueT) 0, &zero_address_frag);
11658 /* Round up a section size to the appropriate boundary. */
11661 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11663 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11664 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11666 /* For a.out, force the section size to be aligned. If we don't do
11667 this, BFD will align it for us, but it will not write out the
11668 final bytes of the section. This may be a bug in BFD, but it is
11669 easier to fix it here since that is how the other a.out targets
11673 align = bfd_get_section_alignment (stdoutput, segment);
11674 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11681 /* On the i386, PC-relative offsets are relative to the start of the
11682 next instruction. That is, the address of the offset, plus its
11683 size, since the offset is always the last part of the insn. */
11686 md_pcrel_from (fixS *fixP)
11688 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11694 s_bss (int ignore ATTRIBUTE_UNUSED)
11698 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11700 obj_elf_section_change_hook ();
11702 temp = get_absolute_expression ();
11703 subseg_set (bss_section, (subsegT) temp);
11704 demand_empty_rest_of_line ();
11710 i386_validate_fix (fixS *fixp)
11712 if (fixp->fx_subsy)
11714 if (fixp->fx_subsy == GOT_symbol)
11716 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11720 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11721 if (fixp->fx_tcbit2)
11722 fixp->fx_r_type = (fixp->fx_tcbit
11723 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11724 : BFD_RELOC_X86_64_GOTPCRELX);
11727 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11732 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11734 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11736 fixp->fx_subsy = 0;
11739 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11740 else if (!object_64bit)
11742 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11743 && fixp->fx_tcbit2)
11744 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11750 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11753 bfd_reloc_code_real_type code;
11755 switch (fixp->fx_r_type)
11757 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11758 case BFD_RELOC_SIZE32:
11759 case BFD_RELOC_SIZE64:
11760 if (S_IS_DEFINED (fixp->fx_addsy)
11761 && !S_IS_EXTERNAL (fixp->fx_addsy))
11763 /* Resolve size relocation against local symbol to size of
11764 the symbol plus addend. */
11765 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11766 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11767 && !fits_in_unsigned_long (value))
11768 as_bad_where (fixp->fx_file, fixp->fx_line,
11769 _("symbol size computation overflow"));
11770 fixp->fx_addsy = NULL;
11771 fixp->fx_subsy = NULL;
11772 md_apply_fix (fixp, (valueT *) &value, NULL);
11776 /* Fall through. */
11778 case BFD_RELOC_X86_64_PLT32:
11779 case BFD_RELOC_X86_64_GOT32:
11780 case BFD_RELOC_X86_64_GOTPCREL:
11781 case BFD_RELOC_X86_64_GOTPCRELX:
11782 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11783 case BFD_RELOC_386_PLT32:
11784 case BFD_RELOC_386_GOT32:
11785 case BFD_RELOC_386_GOT32X:
11786 case BFD_RELOC_386_GOTOFF:
11787 case BFD_RELOC_386_GOTPC:
11788 case BFD_RELOC_386_TLS_GD:
11789 case BFD_RELOC_386_TLS_LDM:
11790 case BFD_RELOC_386_TLS_LDO_32:
11791 case BFD_RELOC_386_TLS_IE_32:
11792 case BFD_RELOC_386_TLS_IE:
11793 case BFD_RELOC_386_TLS_GOTIE:
11794 case BFD_RELOC_386_TLS_LE_32:
11795 case BFD_RELOC_386_TLS_LE:
11796 case BFD_RELOC_386_TLS_GOTDESC:
11797 case BFD_RELOC_386_TLS_DESC_CALL:
11798 case BFD_RELOC_X86_64_TLSGD:
11799 case BFD_RELOC_X86_64_TLSLD:
11800 case BFD_RELOC_X86_64_DTPOFF32:
11801 case BFD_RELOC_X86_64_DTPOFF64:
11802 case BFD_RELOC_X86_64_GOTTPOFF:
11803 case BFD_RELOC_X86_64_TPOFF32:
11804 case BFD_RELOC_X86_64_TPOFF64:
11805 case BFD_RELOC_X86_64_GOTOFF64:
11806 case BFD_RELOC_X86_64_GOTPC32:
11807 case BFD_RELOC_X86_64_GOT64:
11808 case BFD_RELOC_X86_64_GOTPCREL64:
11809 case BFD_RELOC_X86_64_GOTPC64:
11810 case BFD_RELOC_X86_64_GOTPLT64:
11811 case BFD_RELOC_X86_64_PLTOFF64:
11812 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11813 case BFD_RELOC_X86_64_TLSDESC_CALL:
11814 case BFD_RELOC_RVA:
11815 case BFD_RELOC_VTABLE_ENTRY:
11816 case BFD_RELOC_VTABLE_INHERIT:
11818 case BFD_RELOC_32_SECREL:
11820 code = fixp->fx_r_type;
11822 case BFD_RELOC_X86_64_32S:
11823 if (!fixp->fx_pcrel)
11825 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11826 code = fixp->fx_r_type;
11829 /* Fall through. */
11831 if (fixp->fx_pcrel)
11833 switch (fixp->fx_size)
11836 as_bad_where (fixp->fx_file, fixp->fx_line,
11837 _("can not do %d byte pc-relative relocation"),
11839 code = BFD_RELOC_32_PCREL;
11841 case 1: code = BFD_RELOC_8_PCREL; break;
11842 case 2: code = BFD_RELOC_16_PCREL; break;
11843 case 4: code = BFD_RELOC_32_PCREL; break;
11845 case 8: code = BFD_RELOC_64_PCREL; break;
11851 switch (fixp->fx_size)
11854 as_bad_where (fixp->fx_file, fixp->fx_line,
11855 _("can not do %d byte relocation"),
11857 code = BFD_RELOC_32;
11859 case 1: code = BFD_RELOC_8; break;
11860 case 2: code = BFD_RELOC_16; break;
11861 case 4: code = BFD_RELOC_32; break;
11863 case 8: code = BFD_RELOC_64; break;
11870 if ((code == BFD_RELOC_32
11871 || code == BFD_RELOC_32_PCREL
11872 || code == BFD_RELOC_X86_64_32S)
11874 && fixp->fx_addsy == GOT_symbol)
11877 code = BFD_RELOC_386_GOTPC;
11879 code = BFD_RELOC_X86_64_GOTPC32;
11881 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11883 && fixp->fx_addsy == GOT_symbol)
11885 code = BFD_RELOC_X86_64_GOTPC64;
11888 rel = XNEW (arelent);
11889 rel->sym_ptr_ptr = XNEW (asymbol *);
11890 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11892 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11894 if (!use_rela_relocations)
11896 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11897 vtable entry to be used in the relocation's section offset. */
11898 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11899 rel->address = fixp->fx_offset;
11900 #if defined (OBJ_COFF) && defined (TE_PE)
11901 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11902 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11907 /* Use the rela in 64bit mode. */
11910 if (disallow_64bit_reloc)
11913 case BFD_RELOC_X86_64_DTPOFF64:
11914 case BFD_RELOC_X86_64_TPOFF64:
11915 case BFD_RELOC_64_PCREL:
11916 case BFD_RELOC_X86_64_GOTOFF64:
11917 case BFD_RELOC_X86_64_GOT64:
11918 case BFD_RELOC_X86_64_GOTPCREL64:
11919 case BFD_RELOC_X86_64_GOTPC64:
11920 case BFD_RELOC_X86_64_GOTPLT64:
11921 case BFD_RELOC_X86_64_PLTOFF64:
11922 as_bad_where (fixp->fx_file, fixp->fx_line,
11923 _("cannot represent relocation type %s in x32 mode"),
11924 bfd_get_reloc_code_name (code));
11930 if (!fixp->fx_pcrel)
11931 rel->addend = fixp->fx_offset;
11935 case BFD_RELOC_X86_64_PLT32:
11936 case BFD_RELOC_X86_64_GOT32:
11937 case BFD_RELOC_X86_64_GOTPCREL:
11938 case BFD_RELOC_X86_64_GOTPCRELX:
11939 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11940 case BFD_RELOC_X86_64_TLSGD:
11941 case BFD_RELOC_X86_64_TLSLD:
11942 case BFD_RELOC_X86_64_GOTTPOFF:
11943 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11944 case BFD_RELOC_X86_64_TLSDESC_CALL:
11945 rel->addend = fixp->fx_offset - fixp->fx_size;
11948 rel->addend = (section->vma
11950 + fixp->fx_addnumber
11951 + md_pcrel_from (fixp));
11956 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11957 if (rel->howto == NULL)
11959 as_bad_where (fixp->fx_file, fixp->fx_line,
11960 _("cannot represent relocation type %s"),
11961 bfd_get_reloc_code_name (code));
11962 /* Set howto to a garbage value so that we can keep going. */
11963 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11964 gas_assert (rel->howto != NULL);
11970 #include "tc-i386-intel.c"
11973 tc_x86_parse_to_dw2regnum (expressionS *exp)
11975 int saved_naked_reg;
11976 char saved_register_dot;
11978 saved_naked_reg = allow_naked_reg;
11979 allow_naked_reg = 1;
11980 saved_register_dot = register_chars['.'];
11981 register_chars['.'] = '.';
11982 allow_pseudo_reg = 1;
11983 expression_and_evaluate (exp);
11984 allow_pseudo_reg = 0;
11985 register_chars['.'] = saved_register_dot;
11986 allow_naked_reg = saved_naked_reg;
11988 if (exp->X_op == O_register && exp->X_add_number >= 0)
11990 if ((addressT) exp->X_add_number < i386_regtab_size)
11992 exp->X_op = O_constant;
11993 exp->X_add_number = i386_regtab[exp->X_add_number]
11994 .dw2_regnum[flag_code >> 1];
11997 exp->X_op = O_illegal;
12002 tc_x86_frame_initial_instructions (void)
12004 static unsigned int sp_regno[2];
12006 if (!sp_regno[flag_code >> 1])
12008 char *saved_input = input_line_pointer;
12009 char sp[][4] = {"esp", "rsp"};
12012 input_line_pointer = sp[flag_code >> 1];
12013 tc_x86_parse_to_dw2regnum (&exp);
12014 gas_assert (exp.X_op == O_constant);
12015 sp_regno[flag_code >> 1] = exp.X_add_number;
12016 input_line_pointer = saved_input;
12019 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12020 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
12024 x86_dwarf2_addr_size (void)
12026 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12027 if (x86_elf_abi == X86_64_X32_ABI)
12030 return bfd_arch_bits_per_address (stdoutput) / 8;
12034 i386_elf_section_type (const char *str, size_t len)
12036 if (flag_code == CODE_64BIT
12037 && len == sizeof ("unwind") - 1
12038 && strncmp (str, "unwind", 6) == 0)
12039 return SHT_X86_64_UNWIND;
12046 i386_solaris_fix_up_eh_frame (segT sec)
12048 if (flag_code == CODE_64BIT)
12049 elf_section_type (sec) = SHT_X86_64_UNWIND;
12055 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12059 exp.X_op = O_secrel;
12060 exp.X_add_symbol = symbol;
12061 exp.X_add_number = 0;
12062 emit_expr (&exp, size);
12066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12067 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12070 x86_64_section_letter (int letter, const char **ptr_msg)
12072 if (flag_code == CODE_64BIT)
12075 return SHF_X86_64_LARGE;
12077 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12080 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
12085 x86_64_section_word (char *str, size_t len)
12087 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
12088 return SHF_X86_64_LARGE;
12094 handle_large_common (int small ATTRIBUTE_UNUSED)
12096 if (flag_code != CODE_64BIT)
12098 s_comm_internal (0, elf_common_parse);
12099 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12103 static segT lbss_section;
12104 asection *saved_com_section_ptr = elf_com_section_ptr;
12105 asection *saved_bss_section = bss_section;
12107 if (lbss_section == NULL)
12109 flagword applicable;
12110 segT seg = now_seg;
12111 subsegT subseg = now_subseg;
12113 /* The .lbss section is for local .largecomm symbols. */
12114 lbss_section = subseg_new (".lbss", 0);
12115 applicable = bfd_applicable_section_flags (stdoutput);
12116 bfd_set_section_flags (stdoutput, lbss_section,
12117 applicable & SEC_ALLOC);
12118 seg_info (lbss_section)->bss = 1;
12120 subseg_set (seg, subseg);
12123 elf_com_section_ptr = &_bfd_elf_large_com_section;
12124 bss_section = lbss_section;
12126 s_comm_internal (0, elf_common_parse);
12128 elf_com_section_ptr = saved_com_section_ptr;
12129 bss_section = saved_bss_section;
12132 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */