1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void swap_imm_operands PARAMS ((void));
93 static void optimize_imm PARAMS ((void));
94 static void optimize_disp PARAMS ((void));
95 static int match_template PARAMS ((void));
96 static int check_string PARAMS ((void));
97 static int process_suffix PARAMS ((void));
98 static int check_byte_reg PARAMS ((void));
99 static int check_long_reg PARAMS ((void));
100 static int check_qword_reg PARAMS ((void));
101 static int check_word_reg PARAMS ((void));
102 static int finalize_imm PARAMS ((void));
103 static int process_operands PARAMS ((void));
104 static const seg_entry *build_modrm_byte PARAMS ((void));
105 static void output_insn PARAMS ((void));
106 static void output_branch PARAMS ((void));
107 static void output_jump PARAMS ((void));
108 static void output_interseg_jump PARAMS ((void));
109 static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111 static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
114 static void s_bss PARAMS ((int));
116 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117 static void handle_large_common (int small ATTRIBUTE_UNUSED);
120 static const char *default_arch = DEFAULT_ARCH;
122 /* 'md_assemble ()' gathers together information and puts it into a
129 const reg_entry *regs;
134 /* TM holds the template for the insn were currently assembling. */
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
141 /* OPERANDS gives the number of given operands. */
142 unsigned int operands;
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
149 /* TYPES [i] is the type (see above #defines) which tells us how to
150 use OP[i] for the corresponding operand. */
151 unsigned int types[MAX_OPERANDS];
153 /* Displacement expression, immediate expression, or register for each
155 union i386_op op[MAX_OPERANDS];
157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159 #define Operand_PCrel 1
161 /* Relocation type for operand */
162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
170 /* SEG gives the seg_entries of this insn. They are zero unless
171 explicit segment overrides are given. */
172 const seg_entry *seg[2];
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
187 typedef struct _i386_insn i386_insn;
189 /* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
191 const char extra_symbol_chars[] = "*%-(["
200 #if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
202 && !defined (TE_GNU) \
203 && !defined (TE_LINUX) \
204 && !defined (TE_NETWARE) \
205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
207 /* This array holds the chars that always start a comment. If the
208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210 const char *i386_comment_chars = "#/";
211 #define SVR4_COMMENT_CHARS 1
212 #define PREFIX_SEPARATOR '\\'
215 const char *i386_comment_chars = "#";
216 #define PREFIX_SEPARATOR '/'
219 /* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
223 first line of the input file. This is because the compiler outputs
224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
226 '/' isn't otherwise defined. */
227 const char line_comment_chars[] = "#/";
229 const char line_separator_chars[] = ";";
231 /* Chars that can be used to separate mant from exp in floating point
233 const char EXP_CHARS[] = "eE";
235 /* Chars that mean this number is a floating point constant
238 const char FLT_CHARS[] = "fFdDxX";
240 /* Tables for lexical analysis. */
241 static char mnemonic_chars[256];
242 static char register_chars[256];
243 static char operand_chars[256];
244 static char identifier_chars[256];
245 static char digit_chars[256];
247 /* Lexical macros. */
248 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249 #define is_operand_char(x) (operand_chars[(unsigned char) x])
250 #define is_register_char(x) (register_chars[(unsigned char) x])
251 #define is_space_char(x) ((x) == ' ')
252 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253 #define is_digit_char(x) (digit_chars[(unsigned char) x])
255 /* All non-digit non-letter characters that may occur in an operand. */
256 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
258 /* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
261 assembler instruction). */
262 static char save_stack[32];
263 static char *save_stack_p;
264 #define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266 #define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
269 /* The instruction we're assembling. */
272 /* Possible templates for current insn. */
273 static const templates *current_templates;
275 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
276 static expressionS disp_expressions[2], im_expressions[2];
278 /* Current operand we are working on. */
279 static int this_operand;
281 /* We support four different modes. FLAG_CODE variable is used to distinguish
288 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
290 static enum flag_code flag_code;
291 static unsigned int object_64bit;
292 static int use_rela_relocations = 0;
294 /* The names used to print error messages. */
295 static const char *flag_code_names[] =
302 /* 1 for intel syntax,
304 static int intel_syntax = 0;
306 /* 1 if register prefix % not required. */
307 static int allow_naked_reg = 0;
309 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312 static char stackop_size = '\0';
314 /* Non-zero to optimize code alignment. */
315 int optimize_align_code = 1;
317 /* Non-zero to quieten some warnings. */
318 static int quiet_warnings = 0;
321 static const char *cpu_arch_name = NULL;
322 static const char *cpu_sub_arch_name = NULL;
324 /* CPU feature flags. */
325 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
327 /* If we have selected a cpu we are generating instructions for. */
328 static int cpu_arch_tune_set = 0;
330 /* Cpu we are generating instructions for. */
331 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
333 /* CPU feature flags of cpu we are generating instructions for. */
334 static unsigned int cpu_arch_tune_flags = 0;
336 /* CPU instruction set architecture used. */
337 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
339 /* CPU feature flags of instruction set architecture used. */
340 static unsigned int cpu_arch_isa_flags = 0;
342 /* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344 static unsigned int no_cond_jump_promotion = 0;
346 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
347 static symbolS *GOT_symbol;
349 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
350 unsigned int x86_dwarf2_return_column;
352 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353 int x86_cie_data_alignment;
355 /* Interface to relax_segment.
356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
361 #define UNCOND_JUMP 0
363 #define COND_JUMP86 2
368 #define SMALL16 (SMALL | CODE16)
370 #define BIG16 (BIG | CODE16)
374 #define INLINE __inline__
380 #define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382 #define TYPE_FROM_RELAX_STATE(s) \
384 #define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
387 /* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
395 const relax_typeS md_relax_table[] =
398 1) most positive reach of this state,
399 2) most negative reach of this state,
400 3) how many bytes this mode will have in the variable part of the frag
401 4) which index into the table to try if we can't fit into this one. */
403 /* UNCOND_JUMP states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
419 /* word conditionals add 3 bytes to frag:
420 1 extra opcode byte, 2 displacement bytes. */
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
434 static const arch_entry cpu_arch[] =
436 {"generic32", PROCESSOR_GENERIC32,
437 Cpu086|Cpu186|Cpu286|Cpu386},
438 {"generic64", PROCESSOR_GENERIC64,
439 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
443 {"i186", PROCESSOR_UNKNOWN,
445 {"i286", PROCESSOR_UNKNOWN,
446 Cpu086|Cpu186|Cpu286},
447 {"i386", PROCESSOR_GENERIC32,
448 Cpu086|Cpu186|Cpu286|Cpu386},
449 {"i486", PROCESSOR_I486,
450 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
451 {"i586", PROCESSOR_PENTIUM,
452 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
453 {"i686", PROCESSOR_PENTIUMPRO,
454 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
455 {"pentium", PROCESSOR_PENTIUM,
456 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
458 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
459 {"pentiumii", PROCESSOR_PENTIUMPRO,
460 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
462 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
464 {"pentium4", PROCESSOR_PENTIUM4,
465 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
466 |CpuMMX2|CpuSSE|CpuSSE2},
467 {"prescott", PROCESSOR_NOCONA,
468 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
469 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
470 {"nocona", PROCESSOR_NOCONA,
471 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
472 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
473 {"yonah", PROCESSOR_YONAH,
474 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
475 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
476 {"merom", PROCESSOR_MEROM,
477 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
478 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
480 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
481 {"k6_2", PROCESSOR_K6,
482 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
483 {"athlon", PROCESSOR_ATHLON,
484 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
485 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
486 {"sledgehammer", PROCESSOR_K8,
487 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
488 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
489 {"opteron", PROCESSOR_K8,
490 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
491 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
493 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
494 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
495 {"amdfam10", PROCESSOR_AMDFAM10,
496 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
497 |CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM},
498 {".mmx", PROCESSOR_UNKNOWN,
500 {".sse", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE},
502 {".sse2", PROCESSOR_UNKNOWN,
503 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
504 {".sse3", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
506 {".3dnow", PROCESSOR_UNKNOWN,
508 {".3dnowa", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
510 {".padlock", PROCESSOR_UNKNOWN,
512 {".pacifica", PROCESSOR_UNKNOWN,
514 {".svme", PROCESSOR_UNKNOWN,
516 {".sse4a", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
518 {".abm", PROCESSOR_UNKNOWN,
522 const pseudo_typeS md_pseudo_table[] =
524 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes, 0},
527 {"align", s_align_ptwo, 0},
529 {"arch", set_cpu_arch, 0},
533 {"ffloat", float_cons, 'f'},
534 {"dfloat", float_cons, 'd'},
535 {"tfloat", float_cons, 'x'},
537 {"slong", signed_cons, 4},
538 {"noopt", s_ignore, 0},
539 {"optim", s_ignore, 0},
540 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
541 {"code16", set_code_flag, CODE_16BIT},
542 {"code32", set_code_flag, CODE_32BIT},
543 {"code64", set_code_flag, CODE_64BIT},
544 {"intel_syntax", set_intel_syntax, 1},
545 {"att_syntax", set_intel_syntax, 0},
546 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
554 {"secrel32", pe_directive_secrel, 0},
559 /* For interface with expression (). */
560 extern char *input_line_pointer;
562 /* Hash table for instruction mnemonic lookup. */
563 static struct hash_control *op_hash;
565 /* Hash table for register lookup. */
566 static struct hash_control *reg_hash;
569 i386_align_code (fragP, count)
573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
576 static const char f32_1[] =
578 static const char f32_2[] =
579 {0x66,0x90}; /* xchg %ax,%ax */
580 static const char f32_3[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5[] =
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8[] =
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
615 static const char f16_3[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
617 static const char f16_4[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5[] =
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
635 static const char *const f16_patt[] = {
636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
637 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
640 static const char alt_3[] =
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
744 if (count <= 0 || count > 15)
747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
764 if (flag_code == CODE_16BIT)
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
782 for (i = 0; i < remains; i++)
784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
788 for (; i < nnops; i++)
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
797 const char *const *patt = NULL;
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
812 case PROCESSOR_MEROM:
813 patt = alt_long_patt;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
818 case PROCESSOR_YONAH:
820 case PROCESSOR_ATHLON:
822 case PROCESSOR_GENERIC64:
823 case PROCESSOR_AMDFAM10:
824 patt = alt_short_patt;
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
835 switch (cpu_arch_tune)
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_YONAH:
850 case PROCESSOR_ATHLON:
852 case PROCESSOR_AMDFAM10:
853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
861 case PROCESSOR_MEROM:
862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
873 memcpy (fragP->fr_literal + fragP->fr_fix,
874 patt[count - 1], count);
876 fragP->fr_var = count;
879 static INLINE unsigned int
880 mode_from_disp_size (t)
883 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
887 fits_in_signed_byte (num)
890 return (num >= -128) && (num <= 127);
894 fits_in_unsigned_byte (num)
897 return (num & 0xff) == num;
901 fits_in_unsigned_word (num)
904 return (num & 0xffff) == num;
908 fits_in_signed_word (num)
911 return (-32768 <= num) && (num <= 32767);
914 fits_in_signed_long (num)
915 offsetT num ATTRIBUTE_UNUSED;
920 return (!(((offsetT) -1 << 31) & num)
921 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
923 } /* fits_in_signed_long() */
925 fits_in_unsigned_long (num)
926 offsetT num ATTRIBUTE_UNUSED;
931 return (num & (((offsetT) 2 << 31) - 1)) == num;
933 } /* fits_in_unsigned_long() */
936 smallest_imm_type (num)
939 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
947 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
949 return (fits_in_signed_byte (num)
950 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_byte (num)
952 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
953 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
954 ? (Imm16 | Imm32 | Imm32S | Imm64)
955 : fits_in_signed_long (num)
956 ? (Imm32 | Imm32S | Imm64)
957 : fits_in_unsigned_long (num)
963 offset_in_range (val, size)
971 case 1: mask = ((addressT) 1 << 8) - 1; break;
972 case 2: mask = ((addressT) 1 << 16) - 1; break;
973 case 4: mask = ((addressT) 2 << 31) - 1; break;
975 case 8: mask = ((addressT) 2 << 63) - 1; break;
980 /* If BFD64, sign extend val. */
981 if (!use_rela_relocations)
982 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
983 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
985 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
987 char buf1[40], buf2[40];
989 sprint_value (buf1, val);
990 sprint_value (buf2, val & mask);
991 as_warn (_("%s shortened to %s"), buf1, buf2);
996 /* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
1001 unsigned int prefix;
1006 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1007 && flag_code == CODE_64BIT)
1009 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1010 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1011 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1022 case CS_PREFIX_OPCODE:
1023 case DS_PREFIX_OPCODE:
1024 case ES_PREFIX_OPCODE:
1025 case FS_PREFIX_OPCODE:
1026 case GS_PREFIX_OPCODE:
1027 case SS_PREFIX_OPCODE:
1031 case REPNE_PREFIX_OPCODE:
1032 case REPE_PREFIX_OPCODE:
1035 case LOCK_PREFIX_OPCODE:
1043 case ADDR_PREFIX_OPCODE:
1047 case DATA_PREFIX_OPCODE:
1051 if (i.prefix[q] != 0)
1059 i.prefix[q] |= prefix;
1062 as_bad (_("same type of prefix used twice"));
1068 set_code_flag (value)
1072 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1073 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1074 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1076 as_bad (_("64bit mode not supported on this CPU."));
1078 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1080 as_bad (_("32bit mode not supported on this CPU."));
1082 stackop_size = '\0';
1086 set_16bit_gcc_code_flag (new_code_flag)
1089 flag_code = new_code_flag;
1090 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1091 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1092 stackop_size = LONG_MNEM_SUFFIX;
1096 set_intel_syntax (syntax_flag)
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg = 0;
1103 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1105 char *string = input_line_pointer;
1106 int e = get_symbol_end ();
1108 if (strcmp (string, "prefix") == 0)
1110 else if (strcmp (string, "noprefix") == 0)
1113 as_bad (_("bad argument to syntax directive."));
1114 *input_line_pointer = e;
1116 demand_empty_rest_of_line ();
1118 intel_syntax = syntax_flag;
1120 if (ask_naked_reg == 0)
1121 allow_naked_reg = (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1124 allow_naked_reg = (ask_naked_reg < 0);
1126 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1127 identifier_chars['$'] = intel_syntax ? '$' : 0;
1131 set_cpu_arch (dummy)
1132 int dummy ATTRIBUTE_UNUSED;
1136 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1138 char *string = input_line_pointer;
1139 int e = get_symbol_end ();
1142 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1144 if (strcmp (string, cpu_arch[i].name) == 0)
1148 cpu_arch_name = cpu_arch[i].name;
1149 cpu_sub_arch_name = NULL;
1150 cpu_arch_flags = (cpu_arch[i].flags
1151 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
1152 cpu_arch_isa = cpu_arch[i].type;
1153 cpu_arch_isa_flags = cpu_arch[i].flags;
1154 if (!cpu_arch_tune_set)
1156 cpu_arch_tune = cpu_arch_isa;
1157 cpu_arch_tune_flags = cpu_arch_isa_flags;
1161 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1163 cpu_sub_arch_name = cpu_arch[i].name;
1164 cpu_arch_flags |= cpu_arch[i].flags;
1166 *input_line_pointer = e;
1167 demand_empty_rest_of_line ();
1171 if (i >= ARRAY_SIZE (cpu_arch))
1172 as_bad (_("no such architecture: `%s'"), string);
1174 *input_line_pointer = e;
1177 as_bad (_("missing cpu architecture"));
1179 no_cond_jump_promotion = 0;
1180 if (*input_line_pointer == ','
1181 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1183 char *string = ++input_line_pointer;
1184 int e = get_symbol_end ();
1186 if (strcmp (string, "nojumps") == 0)
1187 no_cond_jump_promotion = 1;
1188 else if (strcmp (string, "jumps") == 0)
1191 as_bad (_("no such architecture modifier: `%s'"), string);
1193 *input_line_pointer = e;
1196 demand_empty_rest_of_line ();
1202 if (!strcmp (default_arch, "x86_64"))
1203 return bfd_mach_x86_64;
1204 else if (!strcmp (default_arch, "i386"))
1205 return bfd_mach_i386_i386;
1207 as_fatal (_("Unknown architecture"));
1213 const char *hash_err;
1215 /* Initialize op_hash hash table. */
1216 op_hash = hash_new ();
1219 const template *optab;
1220 templates *core_optab;
1222 /* Setup for loop. */
1224 core_optab = (templates *) xmalloc (sizeof (templates));
1225 core_optab->start = optab;
1230 if (optab->name == NULL
1231 || strcmp (optab->name, (optab - 1)->name) != 0)
1233 /* different name --> ship out current template list;
1234 add to hash table; & begin anew. */
1235 core_optab->end = optab;
1236 hash_err = hash_insert (op_hash,
1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1245 if (optab->name == NULL)
1247 core_optab = (templates *) xmalloc (sizeof (templates));
1248 core_optab->start = optab;
1253 /* Initialize reg_hash hash table. */
1254 reg_hash = hash_new ();
1256 const reg_entry *regtab;
1258 for (regtab = i386_regtab;
1259 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1262 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
1275 for (c = 0; c < 256; c++)
1280 mnemonic_chars[c] = c;
1281 register_chars[c] = c;
1282 operand_chars[c] = c;
1284 else if (ISLOWER (c))
1286 mnemonic_chars[c] = c;
1287 register_chars[c] = c;
1288 operand_chars[c] = c;
1290 else if (ISUPPER (c))
1292 mnemonic_chars[c] = TOLOWER (c);
1293 register_chars[c] = mnemonic_chars[c];
1294 operand_chars[c] = c;
1297 if (ISALPHA (c) || ISDIGIT (c))
1298 identifier_chars[c] = c;
1301 identifier_chars[c] = c;
1302 operand_chars[c] = c;
1307 identifier_chars['@'] = '@';
1310 identifier_chars['?'] = '?';
1311 operand_chars['?'] = '?';
1313 digit_chars['-'] = '-';
1314 mnemonic_chars['-'] = '-';
1315 identifier_chars['_'] = '_';
1316 identifier_chars['.'] = '.';
1318 for (p = operand_special_chars; *p != '\0'; p++)
1319 operand_chars[(unsigned char) *p] = *p;
1322 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1325 record_alignment (text_section, 2);
1326 record_alignment (data_section, 2);
1327 record_alignment (bss_section, 2);
1331 if (flag_code == CODE_64BIT)
1333 x86_dwarf2_return_column = 16;
1334 x86_cie_data_alignment = -8;
1338 x86_dwarf2_return_column = 8;
1339 x86_cie_data_alignment = -4;
1344 i386_print_statistics (file)
1347 hash_print_statistics (file, "i386 opcode", op_hash);
1348 hash_print_statistics (file, "i386 register", reg_hash);
1353 /* Debugging routines for md_assemble. */
1354 static void pi PARAMS ((char *, i386_insn *));
1355 static void pte PARAMS ((template *));
1356 static void pt PARAMS ((unsigned int));
1357 static void pe PARAMS ((expressionS *));
1358 static void ps PARAMS ((symbolS *));
1367 fprintf (stdout, "%s: template ", line);
1369 fprintf (stdout, " address: base %s index %s scale %x\n",
1370 x->base_reg ? x->base_reg->reg_name : "none",
1371 x->index_reg ? x->index_reg->reg_name : "none",
1372 x->log2_scale_factor);
1373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1374 x->rm.mode, x->rm.reg, x->rm.regmem);
1375 fprintf (stdout, " sib: base %x index %x scale %x\n",
1376 x->sib.base, x->sib.index, x->sib.scale);
1377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1378 (x->rex & REX_MODE64) != 0,
1379 (x->rex & REX_EXTX) != 0,
1380 (x->rex & REX_EXTY) != 0,
1381 (x->rex & REX_EXTZ) != 0);
1382 for (i = 0; i < x->operands; i++)
1384 fprintf (stdout, " #%d: ", i + 1);
1386 fprintf (stdout, "\n");
1388 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1389 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1390 if (x->types[i] & Imm)
1392 if (x->types[i] & Disp)
1393 pe (x->op[i].disps);
1402 fprintf (stdout, " %d operands ", t->operands);
1403 fprintf (stdout, "opcode %x ", t->base_opcode);
1404 if (t->extension_opcode != None)
1405 fprintf (stdout, "ext %x ", t->extension_opcode);
1406 if (t->opcode_modifier & D)
1407 fprintf (stdout, "D");
1408 if (t->opcode_modifier & W)
1409 fprintf (stdout, "W");
1410 fprintf (stdout, "\n");
1411 for (i = 0; i < t->operands; i++)
1413 fprintf (stdout, " #%d type ", i + 1);
1414 pt (t->operand_types[i]);
1415 fprintf (stdout, "\n");
1423 fprintf (stdout, " operation %d\n", e->X_op);
1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
1426 if (e->X_add_symbol)
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1444 fprintf (stdout, "%s type %s%s",
1446 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s)));
1450 static struct type_name
1455 const type_names[] =
1468 { BaseIndex, "BaseIndex" },
1472 { Disp32S, "d32s" },
1474 { InOutPortReg, "InOutPortReg" },
1475 { ShiftCount, "ShiftCount" },
1476 { Control, "control reg" },
1477 { Test, "test reg" },
1478 { Debug, "debug reg" },
1479 { FloatReg, "FReg" },
1480 { FloatAcc, "FAcc" },
1484 { JumpAbsolute, "Jump Absolute" },
1495 const struct type_name *ty;
1497 for (ty = type_names; ty->mask; ty++)
1499 fprintf (stdout, "%s, ", ty->tname);
1503 #endif /* DEBUG386 */
1505 static bfd_reloc_code_real_type
1506 reloc (unsigned int size,
1509 bfd_reloc_code_real_type other)
1511 if (other != NO_RELOC)
1513 reloc_howto_type *reloc;
1518 case BFD_RELOC_X86_64_GOT32:
1519 return BFD_RELOC_X86_64_GOT64;
1521 case BFD_RELOC_X86_64_PLTOFF64:
1522 return BFD_RELOC_X86_64_PLTOFF64;
1524 case BFD_RELOC_X86_64_GOTPC32:
1525 other = BFD_RELOC_X86_64_GOTPC64;
1527 case BFD_RELOC_X86_64_GOTPCREL:
1528 other = BFD_RELOC_X86_64_GOTPCREL64;
1530 case BFD_RELOC_X86_64_TPOFF32:
1531 other = BFD_RELOC_X86_64_TPOFF64;
1533 case BFD_RELOC_X86_64_DTPOFF32:
1534 other = BFD_RELOC_X86_64_DTPOFF64;
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size == 4 && flag_code != CODE_64BIT)
1544 reloc = bfd_reloc_type_lookup (stdoutput, other);
1546 as_bad (_("unknown relocation (%u)"), other);
1547 else if (size != bfd_get_reloc_size (reloc))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc),
1551 else if (pcrel && !reloc->pc_relative)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc->complain_on_overflow == complain_overflow_signed
1555 || (reloc->complain_on_overflow == complain_overflow_unsigned
1557 as_bad (_("relocated field and relocation type differ in signedness"));
1566 as_bad (_("there are no unsigned pc-relative relocations"));
1569 case 1: return BFD_RELOC_8_PCREL;
1570 case 2: return BFD_RELOC_16_PCREL;
1571 case 4: return BFD_RELOC_32_PCREL;
1572 case 8: return BFD_RELOC_64_PCREL;
1574 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1581 case 4: return BFD_RELOC_X86_64_32S;
1586 case 1: return BFD_RELOC_8;
1587 case 2: return BFD_RELOC_16;
1588 case 4: return BFD_RELOC_32;
1589 case 8: return BFD_RELOC_64;
1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign > 0 ? "signed" : "unsigned", size);
1596 return BFD_RELOC_NONE;
1599 /* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1605 tc_i386_fix_adjustable (fixP)
1606 fixS *fixP ATTRIBUTE_UNUSED;
1608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1622 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1625 /* adjust_reloc_syms doesn't know about the GOT. */
1626 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1627 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1628 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
1639 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1641 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1642 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1643 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1644 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1645 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1648 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
1652 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1653 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1659 static int intel_float_operand PARAMS ((const char *mnemonic));
1662 intel_float_operand (mnemonic)
1663 const char *mnemonic;
1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1669 if (mnemonic[0] != 'f')
1670 return 0; /* non-math */
1672 switch (mnemonic[1])
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1678 return 2 /* integer op */;
1680 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1684 if (mnemonic[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1688 if (mnemonic[2] == 's')
1689 return 3; /* frstor/frstpm */
1692 if (mnemonic[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic[2] == 't')
1696 switch (mnemonic[3])
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1707 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1715 /* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1724 char mnemonic[MAX_MNEM_SIZE];
1726 /* Initialize globals. */
1727 memset (&i, '\0', sizeof (i));
1728 for (j = 0; j < MAX_OPERANDS; j++)
1729 i.reloc[j] = NO_RELOC;
1730 memset (disp_expressions, '\0', sizeof (disp_expressions));
1731 memset (im_expressions, '\0', sizeof (im_expressions));
1732 save_stack_p = save_stack;
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
1736 start of a (possibly prefixed) mnemonic. */
1738 line = parse_insn (line, mnemonic);
1742 line = parse_operands (line, mnemonic);
1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i.imm_operands == 2) &&
1749 ((strcmp (mnemonic, "extrq") == 0)
1750 || (strcmp (mnemonic, "insertq") == 0)))
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
1766 precedes the offset, as it does when in AT&T mode. */
1767 if (intel_syntax && i.operands > 1
1768 && (strcmp (mnemonic, "bound") != 0)
1769 && (strcmp (mnemonic, "invlpga") != 0)
1770 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1776 /* Don't optimize displacement for movabs since it only takes 64bit
1779 && (flag_code != CODE_64BIT
1780 || strcmp (mnemonic, "movabs") != 0))
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
1787 if (!match_template ())
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1794 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1795 i.tm.base_opcode ^= FloatR;
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1802 if (i.reg_operands < 2
1804 && (~i.tm.opcode_modifier
1811 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1817 if (i.tm.opcode_modifier & FWait)
1818 if (!add_prefix (FWAIT_OPCODE))
1821 /* Check string instruction segment overrides. */
1822 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1824 if (!check_string ())
1828 if (!process_suffix ())
1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1836 if (i.types[0] & Imm1)
1837 i.imm_operands = 0; /* kludge for shift insns. */
1838 if (i.types[0] & ImplicitRegister)
1840 if (i.types[1] & ImplicitRegister)
1842 if (i.types[2] & ImplicitRegister)
1845 if (i.tm.opcode_modifier & ImmExt)
1849 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1851 /* These Intel Prescott New Instructions have the fixed
1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1857 for (x = 0; x < i.operands; x++)
1858 if (i.op[x].regs->reg_num != x)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1860 i.op[x].regs->reg_name, x + 1, i.tm.name);
1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
1869 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1871 exp = &im_expressions[i.imm_operands++];
1872 i.op[i.operands].imms = exp;
1873 i.types[i.operands++] = Imm8;
1874 exp->X_op = O_constant;
1875 exp->X_add_number = i.tm.extension_opcode;
1876 i.tm.extension_opcode = None;
1879 /* For insns with operands there are more diddles to do to the opcode. */
1882 if (!process_operands ())
1885 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i.tm.name);
1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1894 i.tm.base_opcode = INT3_OPCODE;
1898 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1899 && i.op[0].disps->X_op == O_constant)
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i.op[0].disps->X_add_symbol = &abs_symbol;
1905 i.op[0].disps->X_op = O_symbol;
1908 if ((i.tm.opcode_modifier & Rex64) != 0)
1909 i.rex |= REX_MODE64;
1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
1915 if (((i.types[0] & Reg8) != 0
1916 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1917 || ((i.types[1] & Reg8) != 0
1918 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1919 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1924 i.rex |= REX_OPCODE;
1925 for (x = 0; x < 2; x++)
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i.types[x] & Reg8) != 0
1929 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1931 /* In case it is "hi" register, give up. */
1932 if (i.op[x].regs->reg_num > 3)
1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1934 i.op[x].regs->reg_name);
1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1940 i.op[x].regs = i.op[x].regs + 8;
1946 add_prefix (REX_OPCODE | i.rex);
1948 /* Record what ISA we have generated so far. */
1949 cpu_arch_isa_flags |= i.tm.cpu_flags;
1951 /* We are ready to output the insn. */
1956 parse_insn (line, mnemonic)
1961 char *token_start = l;
1966 /* Non-zero if we found a prefix only acceptable with string insns. */
1967 const char *expecting_string_instruction = NULL;
1972 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1975 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1977 as_bad (_("no such instruction: `%s'"), token_start);
1982 if (!is_space_char (*l)
1983 && *l != END_OF_INSN
1985 || (*l != PREFIX_SEPARATOR
1988 as_bad (_("invalid character %s in mnemonic"),
1989 output_invalid (*l));
1992 if (token_start == l)
1994 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1995 as_bad (_("expecting prefix; got nothing"));
1997 as_bad (_("expecting mnemonic; got nothing"));
2001 /* Look up instruction (or prefix) via hash table. */
2002 current_templates = hash_find (op_hash, mnemonic);
2004 if (*l != END_OF_INSN
2005 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2006 && current_templates
2007 && (current_templates->start->opcode_modifier & IsPrefix))
2009 if (current_templates->start->cpu_flags
2010 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2012 as_bad ((flag_code != CODE_64BIT
2013 ? _("`%s' is only supported in 64-bit mode")
2014 : _("`%s' is not supported in 64-bit mode")),
2015 current_templates->start->name);
2018 /* If we are in 16-bit mode, do not allow addr16 or data16.
2019 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2020 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2021 && flag_code != CODE_64BIT
2022 && (((current_templates->start->opcode_modifier & Size32) != 0)
2023 ^ (flag_code == CODE_16BIT)))
2025 as_bad (_("redundant %s prefix"),
2026 current_templates->start->name);
2029 /* Add prefix, checking for repeated prefixes. */
2030 switch (add_prefix (current_templates->start->base_opcode))
2035 expecting_string_instruction = current_templates->start->name;
2038 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2045 if (!current_templates)
2047 /* See if we can get a match by trimming off a suffix. */
2050 case WORD_MNEM_SUFFIX:
2051 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2052 i.suffix = SHORT_MNEM_SUFFIX;
2054 case BYTE_MNEM_SUFFIX:
2055 case QWORD_MNEM_SUFFIX:
2056 i.suffix = mnem_p[-1];
2058 current_templates = hash_find (op_hash, mnemonic);
2060 case SHORT_MNEM_SUFFIX:
2061 case LONG_MNEM_SUFFIX:
2064 i.suffix = mnem_p[-1];
2066 current_templates = hash_find (op_hash, mnemonic);
2074 if (intel_float_operand (mnemonic) == 1)
2075 i.suffix = SHORT_MNEM_SUFFIX;
2077 i.suffix = LONG_MNEM_SUFFIX;
2079 current_templates = hash_find (op_hash, mnemonic);
2083 if (!current_templates)
2085 as_bad (_("no such instruction: `%s'"), token_start);
2090 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2092 /* Check for a branch hint. We allow ",pt" and ",pn" for
2093 predict taken and predict not taken respectively.
2094 I'm not sure that branch hints actually do anything on loop
2095 and jcxz insns (JumpByte) for current Pentium4 chips. They
2096 may work in the future and it doesn't hurt to accept them
2098 if (l[0] == ',' && l[1] == 'p')
2102 if (!add_prefix (DS_PREFIX_OPCODE))
2106 else if (l[2] == 'n')
2108 if (!add_prefix (CS_PREFIX_OPCODE))
2114 /* Any other comma loses. */
2117 as_bad (_("invalid character %s in mnemonic"),
2118 output_invalid (*l));
2122 /* Check if instruction is supported on specified architecture. */
2124 for (t = current_templates->start; t < current_templates->end; ++t)
2126 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2127 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
2129 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
2132 if (!(supported & 2))
2134 as_bad (flag_code == CODE_64BIT
2135 ? _("`%s' is not supported in 64-bit mode")
2136 : _("`%s' is only supported in 64-bit mode"),
2137 current_templates->start->name);
2140 if (!(supported & 1))
2142 as_warn (_("`%s' is not supported on `%s%s'"),
2143 current_templates->start->name,
2145 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2147 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2149 as_warn (_("use .code16 to ensure correct addressing mode"));
2152 /* Check for rep/repne without a string instruction. */
2153 if (expecting_string_instruction)
2155 static templates override;
2157 for (t = current_templates->start; t < current_templates->end; ++t)
2158 if (t->opcode_modifier & IsString)
2160 if (t >= current_templates->end)
2162 as_bad (_("expecting string instruction after `%s'"),
2163 expecting_string_instruction);
2166 for (override.start = t; t < current_templates->end; ++t)
2167 if (!(t->opcode_modifier & IsString))
2170 current_templates = &override;
2177 parse_operands (l, mnemonic)
2179 const char *mnemonic;
2183 /* 1 if operand is pending after ','. */
2184 unsigned int expecting_operand = 0;
2186 /* Non-zero if operand parens not balanced. */
2187 unsigned int paren_not_balanced;
2189 while (*l != END_OF_INSN)
2191 /* Skip optional white space before operand. */
2192 if (is_space_char (*l))
2194 if (!is_operand_char (*l) && *l != END_OF_INSN)
2196 as_bad (_("invalid character %s before operand %d"),
2197 output_invalid (*l),
2201 token_start = l; /* after white space */
2202 paren_not_balanced = 0;
2203 while (paren_not_balanced || *l != ',')
2205 if (*l == END_OF_INSN)
2207 if (paren_not_balanced)
2210 as_bad (_("unbalanced parenthesis in operand %d."),
2213 as_bad (_("unbalanced brackets in operand %d."),
2218 break; /* we are done */
2220 else if (!is_operand_char (*l) && !is_space_char (*l))
2222 as_bad (_("invalid character %s in operand %d"),
2223 output_invalid (*l),
2230 ++paren_not_balanced;
2232 --paren_not_balanced;
2237 ++paren_not_balanced;
2239 --paren_not_balanced;
2243 if (l != token_start)
2244 { /* Yes, we've read in another operand. */
2245 unsigned int operand_ok;
2246 this_operand = i.operands++;
2247 if (i.operands > MAX_OPERANDS)
2249 as_bad (_("spurious operands; (%d operands/instruction max)"),
2253 /* Now parse operand adding info to 'i' as we go along. */
2254 END_STRING_AND_SAVE (l);
2258 i386_intel_operand (token_start,
2259 intel_float_operand (mnemonic));
2261 operand_ok = i386_operand (token_start);
2263 RESTORE_END_STRING (l);
2269 if (expecting_operand)
2271 expecting_operand_after_comma:
2272 as_bad (_("expecting operand after ','; got nothing"));
2277 as_bad (_("expecting operand before ','; got nothing"));
2282 /* Now *l must be either ',' or END_OF_INSN. */
2285 if (*++l == END_OF_INSN)
2287 /* Just skip it, if it's \n complain. */
2288 goto expecting_operand_after_comma;
2290 expecting_operand = 1;
2297 swap_imm_operands ()
2299 union i386_op temp_op;
2300 unsigned int temp_type;
2301 enum bfd_reloc_code_real temp_reloc;
2305 temp_type = i.types[xchg2];
2306 i.types[xchg2] = i.types[xchg1];
2307 i.types[xchg1] = temp_type;
2308 temp_op = i.op[xchg2];
2309 i.op[xchg2] = i.op[xchg1];
2310 i.op[xchg1] = temp_op;
2311 temp_reloc = i.reloc[xchg2];
2312 i.reloc[xchg2] = i.reloc[xchg1];
2313 i.reloc[xchg1] = temp_reloc;
2320 union i386_op temp_op;
2321 unsigned int temp_type;
2322 enum bfd_reloc_code_real temp_reloc;
2326 if (i.operands == 4)
2327 /* There will be two exchanges in a 4 operand instruction.
2328 First exchange is the done inside this block.(1st and 4rth operand)
2329 The next exchange is done outside this block.(2nd and 3rd operand) */
2333 temp_type = i.types[xchg2];
2334 i.types[xchg2] = i.types[xchg1];
2335 i.types[xchg1] = temp_type;
2336 temp_op = i.op[xchg2];
2337 i.op[xchg2] = i.op[xchg1];
2338 i.op[xchg1] = temp_op;
2339 temp_reloc = i.reloc[xchg2];
2340 i.reloc[xchg2] = i.reloc[xchg1];
2341 i.reloc[xchg1] = temp_reloc;
2346 if (i.operands == 2)
2351 else if (i.operands == 3)
2356 temp_type = i.types[xchg2];
2357 i.types[xchg2] = i.types[xchg1];
2358 i.types[xchg1] = temp_type;
2359 temp_op = i.op[xchg2];
2360 i.op[xchg2] = i.op[xchg1];
2361 i.op[xchg1] = temp_op;
2362 temp_reloc = i.reloc[xchg2];
2363 i.reloc[xchg2] = i.reloc[xchg1];
2364 i.reloc[xchg1] = temp_reloc;
2366 if (i.mem_operands == 2)
2368 const seg_entry *temp_seg;
2369 temp_seg = i.seg[0];
2370 i.seg[0] = i.seg[1];
2371 i.seg[1] = temp_seg;
2375 /* Try to ensure constant immediates are represented in the smallest
2380 char guess_suffix = 0;
2384 guess_suffix = i.suffix;
2385 else if (i.reg_operands)
2387 /* Figure out a suffix from the last register operand specified.
2388 We can't do this properly yet, ie. excluding InOutPortReg,
2389 but the following works for instructions with immediates.
2390 In any case, we can't set i.suffix yet. */
2391 for (op = i.operands; --op >= 0;)
2392 if (i.types[op] & Reg)
2394 if (i.types[op] & Reg8)
2395 guess_suffix = BYTE_MNEM_SUFFIX;
2396 else if (i.types[op] & Reg16)
2397 guess_suffix = WORD_MNEM_SUFFIX;
2398 else if (i.types[op] & Reg32)
2399 guess_suffix = LONG_MNEM_SUFFIX;
2400 else if (i.types[op] & Reg64)
2401 guess_suffix = QWORD_MNEM_SUFFIX;
2405 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2406 guess_suffix = WORD_MNEM_SUFFIX;
2408 for (op = i.operands; --op >= 0;)
2409 if (i.types[op] & Imm)
2411 switch (i.op[op].imms->X_op)
2414 /* If a suffix is given, this operand may be shortened. */
2415 switch (guess_suffix)
2417 case LONG_MNEM_SUFFIX:
2418 i.types[op] |= Imm32 | Imm64;
2420 case WORD_MNEM_SUFFIX:
2421 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2423 case BYTE_MNEM_SUFFIX:
2424 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2428 /* If this operand is at most 16 bits, convert it
2429 to a signed 16 bit number before trying to see
2430 whether it will fit in an even smaller size.
2431 This allows a 16-bit operand such as $0xffe0 to
2432 be recognised as within Imm8S range. */
2433 if ((i.types[op] & Imm16)
2434 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2436 i.op[op].imms->X_add_number =
2437 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2439 if ((i.types[op] & Imm32)
2440 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2443 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2444 ^ ((offsetT) 1 << 31))
2445 - ((offsetT) 1 << 31));
2447 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2449 /* We must avoid matching of Imm32 templates when 64bit
2450 only immediate is available. */
2451 if (guess_suffix == QWORD_MNEM_SUFFIX)
2452 i.types[op] &= ~Imm32;
2459 /* Symbols and expressions. */
2461 /* Convert symbolic operand to proper sizes for matching, but don't
2462 prevent matching a set of insns that only supports sizes other
2463 than those matching the insn suffix. */
2465 unsigned int mask, allowed = 0;
2468 for (t = current_templates->start; t < current_templates->end; ++t)
2469 allowed |= t->operand_types[op];
2470 switch (guess_suffix)
2472 case QWORD_MNEM_SUFFIX:
2473 mask = Imm64 | Imm32S;
2475 case LONG_MNEM_SUFFIX:
2478 case WORD_MNEM_SUFFIX:
2481 case BYTE_MNEM_SUFFIX:
2489 i.types[op] &= mask;
2496 /* Try to use the smallest displacement type too. */
2502 for (op = i.operands; --op >= 0;)
2503 if (i.types[op] & Disp)
2505 if (i.op[op].disps->X_op == O_constant)
2507 offsetT disp = i.op[op].disps->X_add_number;
2509 if ((i.types[op] & Disp16)
2510 && (disp & ~(offsetT) 0xffff) == 0)
2512 /* If this operand is at most 16 bits, convert
2513 to a signed 16 bit number and don't use 64bit
2515 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2516 i.types[op] &= ~Disp64;
2518 if ((i.types[op] & Disp32)
2519 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2521 /* If this operand is at most 32 bits, convert
2522 to a signed 32 bit number and don't use 64bit
2524 disp &= (((offsetT) 2 << 31) - 1);
2525 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2526 i.types[op] &= ~Disp64;
2528 if (!disp && (i.types[op] & BaseIndex))
2530 i.types[op] &= ~Disp;
2534 else if (flag_code == CODE_64BIT)
2536 if (fits_in_signed_long (disp))
2538 i.types[op] &= ~Disp64;
2539 i.types[op] |= Disp32S;
2541 if (fits_in_unsigned_long (disp))
2542 i.types[op] |= Disp32;
2544 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2545 && fits_in_signed_byte (disp))
2546 i.types[op] |= Disp8;
2548 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2549 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2551 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2552 i.op[op].disps, 0, i.reloc[op]);
2553 i.types[op] &= ~Disp;
2556 /* We only support 64bit displacement on constants. */
2557 i.types[op] &= ~Disp64;
2564 /* Points to template once we've found it. */
2566 unsigned int overlap0, overlap1, overlap2;
2567 unsigned int found_reverse_match;
2570 #define MATCH(overlap, given, template) \
2571 ((overlap & ~JumpAbsolute) \
2572 && (((given) & (BaseIndex | JumpAbsolute)) \
2573 == ((overlap) & (BaseIndex | JumpAbsolute))))
2575 /* If given types r0 and r1 are registers they must be of the same type
2576 unless the expected operand type register overlap is null.
2577 Note that Acc in a template matches every size of reg. */
2578 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2579 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2580 || ((g0) & Reg) == ((g1) & Reg) \
2581 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2586 found_reverse_match = 0;
2587 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2589 : (i.suffix == WORD_MNEM_SUFFIX
2591 : (i.suffix == SHORT_MNEM_SUFFIX
2593 : (i.suffix == LONG_MNEM_SUFFIX
2595 : (i.suffix == QWORD_MNEM_SUFFIX
2597 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2598 ? No_xSuf : 0))))));
2600 for (t = current_templates->start; t < current_templates->end; t++)
2602 /* Must have right number of operands. */
2603 if (i.operands != t->operands)
2606 /* Check the suffix, except for some instructions in intel mode. */
2607 if ((t->opcode_modifier & suffix_check)
2609 && (t->opcode_modifier & IgnoreSize)))
2612 /* In general, don't allow 64-bit operands in 32-bit mode. */
2613 if (i.suffix == QWORD_MNEM_SUFFIX
2614 && flag_code != CODE_64BIT
2616 ? (!(t->opcode_modifier & IgnoreSize)
2617 && !intel_float_operand (t->name))
2618 : intel_float_operand (t->name) != 2)
2619 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2620 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2621 && (t->base_opcode != 0x0fc7
2622 || t->extension_opcode != 1 /* cmpxchg8b */))
2625 /* Do not verify operands when there are none. */
2626 else if (!t->operands)
2628 if (t->cpu_flags & ~cpu_arch_flags)
2630 /* We've found a match; break out of loop. */
2634 overlap0 = i.types[0] & t->operand_types[0];
2635 switch (t->operands)
2638 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2643 overlap1 = i.types[1] & t->operand_types[1];
2644 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2645 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2646 /* monitor in SSE3 is a very special case. The first
2647 register and the second register may have different
2649 || !((t->base_opcode == 0x0f01
2650 && t->extension_opcode == 0xc8)
2651 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2652 t->operand_types[0],
2653 overlap1, i.types[1],
2654 t->operand_types[1])))
2656 /* Check if other direction is valid ... */
2657 if ((t->opcode_modifier & (D | FloatD)) == 0)
2660 /* Try reversing direction of operands. */
2661 overlap0 = i.types[0] & t->operand_types[1];
2662 overlap1 = i.types[1] & t->operand_types[0];
2663 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2664 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2665 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2666 t->operand_types[1],
2667 overlap1, i.types[1],
2668 t->operand_types[0]))
2670 /* Does not match either direction. */
2673 /* found_reverse_match holds which of D or FloatDR
2675 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2677 /* Found a forward 2 operand match here. */
2678 else if (t->operands == 3)
2680 /* Here we make use of the fact that there are no
2681 reverse match 3 operand instructions, and all 3
2682 operand instructions only need to be checked for
2683 register consistency between operands 2 and 3. */
2684 overlap2 = i.types[2] & t->operand_types[2];
2685 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2686 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2687 t->operand_types[1],
2688 overlap2, i.types[2],
2689 t->operand_types[2]))
2693 /* Found either forward/reverse 2 or 3 operand match here:
2694 slip through to break. */
2696 if (t->cpu_flags & ~cpu_arch_flags)
2698 found_reverse_match = 0;
2701 /* We've found a match; break out of loop. */
2705 if (t == current_templates->end)
2707 /* We found no match. */
2708 as_bad (_("suffix or operands invalid for `%s'"),
2709 current_templates->start->name);
2713 if (!quiet_warnings)
2716 && ((i.types[0] & JumpAbsolute)
2717 != (t->operand_types[0] & JumpAbsolute)))
2719 as_warn (_("indirect %s without `*'"), t->name);
2722 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2723 == (IsPrefix | IgnoreSize))
2725 /* Warn them that a data or address size prefix doesn't
2726 affect assembly of the next line of code. */
2727 as_warn (_("stand-alone `%s' prefix"), t->name);
2731 /* Copy the template we found. */
2733 if (found_reverse_match)
2735 /* If we found a reverse match we must alter the opcode
2736 direction bit. found_reverse_match holds bits to change
2737 (different for int & float insns). */
2739 i.tm.base_opcode ^= found_reverse_match;
2741 i.tm.operand_types[0] = t->operand_types[1];
2742 i.tm.operand_types[1] = t->operand_types[0];
2751 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2752 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2754 if (i.seg[0] != NULL && i.seg[0] != &es)
2756 as_bad (_("`%s' operand %d must use `%%es' segment"),
2761 /* There's only ever one segment override allowed per instruction.
2762 This instruction possibly has a legal segment override on the
2763 second operand, so copy the segment to where non-string
2764 instructions store it, allowing common code. */
2765 i.seg[0] = i.seg[1];
2767 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2769 if (i.seg[1] != NULL && i.seg[1] != &es)
2771 as_bad (_("`%s' operand %d must use `%%es' segment"),
2781 process_suffix (void)
2783 /* If matched instruction specifies an explicit instruction mnemonic
2785 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2787 if (i.tm.opcode_modifier & Size16)
2788 i.suffix = WORD_MNEM_SUFFIX;
2789 else if (i.tm.opcode_modifier & Size64)
2790 i.suffix = QWORD_MNEM_SUFFIX;
2792 i.suffix = LONG_MNEM_SUFFIX;
2794 else if (i.reg_operands)
2796 /* If there's no instruction mnemonic suffix we try to invent one
2797 based on register operands. */
2800 /* We take i.suffix from the last register operand specified,
2801 Destination register type is more significant than source
2805 for (op = i.operands; --op >= 0;)
2806 if ((i.types[op] & Reg)
2807 && !(i.tm.operand_types[op] & InOutPortReg))
2809 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2810 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2811 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2816 else if (i.suffix == BYTE_MNEM_SUFFIX)
2818 if (!check_byte_reg ())
2821 else if (i.suffix == LONG_MNEM_SUFFIX)
2823 if (!check_long_reg ())
2826 else if (i.suffix == QWORD_MNEM_SUFFIX)
2828 if (!check_qword_reg ())
2831 else if (i.suffix == WORD_MNEM_SUFFIX)
2833 if (!check_word_reg ())
2836 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2837 /* Do nothing if the instruction is going to ignore the prefix. */
2842 else if ((i.tm.opcode_modifier & DefaultSize)
2844 /* exclude fldenv/frstor/fsave/fstenv */
2845 && (i.tm.opcode_modifier & No_sSuf))
2847 i.suffix = stackop_size;
2849 else if (intel_syntax
2851 && ((i.tm.operand_types[0] & JumpAbsolute)
2852 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2853 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2854 && i.tm.extension_opcode <= 3)))
2859 if (!(i.tm.opcode_modifier & No_qSuf))
2861 i.suffix = QWORD_MNEM_SUFFIX;
2865 if (!(i.tm.opcode_modifier & No_lSuf))
2866 i.suffix = LONG_MNEM_SUFFIX;
2869 if (!(i.tm.opcode_modifier & No_wSuf))
2870 i.suffix = WORD_MNEM_SUFFIX;
2879 if (i.tm.opcode_modifier & W)
2881 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2887 unsigned int suffixes = (~i.tm.opcode_modifier
2895 if ((i.tm.opcode_modifier & W)
2896 || ((suffixes & (suffixes - 1))
2897 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2899 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2905 /* Change the opcode based on the operand size given by i.suffix;
2906 We don't need to change things for byte insns. */
2908 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2910 /* It's not a byte, select word/dword operation. */
2911 if (i.tm.opcode_modifier & W)
2913 if (i.tm.opcode_modifier & ShortForm)
2914 i.tm.base_opcode |= 8;
2916 i.tm.base_opcode |= 1;
2919 /* Now select between word & dword operations via the operand
2920 size prefix, except for instructions that will ignore this
2922 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2924 /* monitor in SSE3 is a very special case. The default size
2925 of AX is the size of mode. The address size override
2926 prefix will change the size of AX. */
2927 if (i.op->regs[0].reg_type &
2928 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2929 if (!add_prefix (ADDR_PREFIX_OPCODE))
2932 else if (i.suffix != QWORD_MNEM_SUFFIX
2933 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2934 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2935 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2936 || (flag_code == CODE_64BIT
2937 && (i.tm.opcode_modifier & JumpByte))))
2939 unsigned int prefix = DATA_PREFIX_OPCODE;
2941 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2942 prefix = ADDR_PREFIX_OPCODE;
2944 if (!add_prefix (prefix))
2948 /* Set mode64 for an operand. */
2949 if (i.suffix == QWORD_MNEM_SUFFIX
2950 && flag_code == CODE_64BIT
2951 && (i.tm.opcode_modifier & NoRex64) == 0)
2953 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2956 || i.types [0] != (Acc | Reg64)
2957 || i.types [1] != (Acc | Reg64)
2958 || strcmp (i.tm.name, "xchg") != 0)
2959 i.rex |= REX_MODE64;
2962 /* Size floating point instruction. */
2963 if (i.suffix == LONG_MNEM_SUFFIX)
2964 if (i.tm.opcode_modifier & FloatMF)
2965 i.tm.base_opcode ^= 4;
2972 check_byte_reg (void)
2976 for (op = i.operands; --op >= 0;)
2978 /* If this is an eight bit register, it's OK. If it's the 16 or
2979 32 bit version of an eight bit register, we will just use the
2980 low portion, and that's OK too. */
2981 if (i.types[op] & Reg8)
2984 /* movzx and movsx should not generate this warning. */
2986 && (i.tm.base_opcode == 0xfb7
2987 || i.tm.base_opcode == 0xfb6
2988 || i.tm.base_opcode == 0x63
2989 || i.tm.base_opcode == 0xfbe
2990 || i.tm.base_opcode == 0xfbf))
2993 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2995 /* Prohibit these changes in the 64bit mode, since the
2996 lowering is more complicated. */
2997 if (flag_code == CODE_64BIT
2998 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3000 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3001 i.op[op].regs->reg_name,
3005 #if REGISTER_WARNINGS
3007 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3008 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3009 (i.op[op].regs + (i.types[op] & Reg16
3010 ? REGNAM_AL - REGNAM_AX
3011 : REGNAM_AL - REGNAM_EAX))->reg_name,
3012 i.op[op].regs->reg_name,
3017 /* Any other register is bad. */
3018 if (i.types[op] & (Reg | RegMMX | RegXMM
3020 | Control | Debug | Test
3021 | FloatReg | FloatAcc))
3023 as_bad (_("`%%%s' not allowed with `%s%c'"),
3024 i.op[op].regs->reg_name,
3038 for (op = i.operands; --op >= 0;)
3039 /* Reject eight bit registers, except where the template requires
3040 them. (eg. movzb) */
3041 if ((i.types[op] & Reg8) != 0
3042 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3044 as_bad (_("`%%%s' not allowed with `%s%c'"),
3045 i.op[op].regs->reg_name,
3050 /* Warn if the e prefix on a general reg is missing. */
3051 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3052 && (i.types[op] & Reg16) != 0
3053 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3055 /* Prohibit these changes in the 64bit mode, since the
3056 lowering is more complicated. */
3057 if (flag_code == CODE_64BIT)
3059 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3060 i.op[op].regs->reg_name,
3064 #if REGISTER_WARNINGS
3066 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3067 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3068 i.op[op].regs->reg_name,
3072 /* Warn if the r prefix on a general reg is missing. */
3073 else if ((i.types[op] & Reg64) != 0
3074 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3076 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3077 i.op[op].regs->reg_name,
3089 for (op = i.operands; --op >= 0; )
3090 /* Reject eight bit registers, except where the template requires
3091 them. (eg. movzb) */
3092 if ((i.types[op] & Reg8) != 0
3093 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3095 as_bad (_("`%%%s' not allowed with `%s%c'"),
3096 i.op[op].regs->reg_name,
3101 /* Warn if the e prefix on a general reg is missing. */
3102 else if (((i.types[op] & Reg16) != 0
3103 || (i.types[op] & Reg32) != 0)
3104 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3106 /* Prohibit these changes in the 64bit mode, since the
3107 lowering is more complicated. */
3108 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3109 i.op[op].regs->reg_name,
3120 for (op = i.operands; --op >= 0;)
3121 /* Reject eight bit registers, except where the template requires
3122 them. (eg. movzb) */
3123 if ((i.types[op] & Reg8) != 0
3124 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3126 as_bad (_("`%%%s' not allowed with `%s%c'"),
3127 i.op[op].regs->reg_name,
3132 /* Warn if the e prefix on a general reg is present. */
3133 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3134 && (i.types[op] & Reg32) != 0
3135 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
3137 /* Prohibit these changes in the 64bit mode, since the
3138 lowering is more complicated. */
3139 if (flag_code == CODE_64BIT)
3141 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
3142 i.op[op].regs->reg_name,
3147 #if REGISTER_WARNINGS
3148 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3149 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3150 i.op[op].regs->reg_name,
3160 unsigned int overlap0, overlap1, overlap2;
3162 overlap0 = i.types[0] & i.tm.operand_types[0];
3163 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
3164 && overlap0 != Imm8 && overlap0 != Imm8S
3165 && overlap0 != Imm16 && overlap0 != Imm32S
3166 && overlap0 != Imm32 && overlap0 != Imm64)
3170 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3172 : (i.suffix == WORD_MNEM_SUFFIX
3174 : (i.suffix == QWORD_MNEM_SUFFIX
3178 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3179 || overlap0 == (Imm16 | Imm32)
3180 || overlap0 == (Imm16 | Imm32S))
3182 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3185 if (overlap0 != Imm8 && overlap0 != Imm8S
3186 && overlap0 != Imm16 && overlap0 != Imm32S
3187 && overlap0 != Imm32 && overlap0 != Imm64)
3189 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3193 i.types[0] = overlap0;
3195 overlap1 = i.types[1] & i.tm.operand_types[1];
3196 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
3197 && overlap1 != Imm8 && overlap1 != Imm8S
3198 && overlap1 != Imm16 && overlap1 != Imm32S
3199 && overlap1 != Imm32 && overlap1 != Imm64)
3203 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3205 : (i.suffix == WORD_MNEM_SUFFIX
3207 : (i.suffix == QWORD_MNEM_SUFFIX
3211 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3212 || overlap1 == (Imm16 | Imm32)
3213 || overlap1 == (Imm16 | Imm32S))
3215 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3218 if (overlap1 != Imm8 && overlap1 != Imm8S
3219 && overlap1 != Imm16 && overlap1 != Imm32S
3220 && overlap1 != Imm32 && overlap1 != Imm64)
3222 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3226 i.types[1] = overlap1;
3228 overlap2 = i.types[2] & i.tm.operand_types[2];
3229 assert ((overlap2 & Imm) == 0);
3230 i.types[2] = overlap2;
3238 /* Default segment register this instruction will use for memory
3239 accesses. 0 means unknown. This is only for optimizing out
3240 unnecessary segment overrides. */
3241 const seg_entry *default_seg = 0;
3243 /* The imul $imm, %reg instruction is converted into
3244 imul $imm, %reg, %reg, and the clr %reg instruction
3245 is converted into xor %reg, %reg. */
3246 if (i.tm.opcode_modifier & regKludge)
3248 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3249 /* Pretend we saw the extra register operand. */
3250 assert (i.op[first_reg_op + 1].regs == 0);
3251 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3252 i.types[first_reg_op + 1] = i.types[first_reg_op];
3256 if (i.tm.opcode_modifier & ShortForm)
3258 /* The register or float register operand is in operand 0 or 1. */
3259 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3260 /* Register goes in low 3 bits of opcode. */
3261 i.tm.base_opcode |= i.op[op].regs->reg_num;
3262 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3264 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3266 /* Warn about some common errors, but press on regardless.
3267 The first case can be generated by gcc (<= 2.8.1). */
3268 if (i.operands == 2)
3270 /* Reversed arguments on faddp, fsubp, etc. */
3271 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3272 i.op[1].regs->reg_name,
3273 i.op[0].regs->reg_name);
3277 /* Extraneous `l' suffix on fp insn. */
3278 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3279 i.op[0].regs->reg_name);
3283 else if (i.tm.opcode_modifier & Modrm)
3285 /* The opcode is completed (modulo i.tm.extension_opcode which
3286 must be put into the modrm byte). Now, we make the modrm and
3287 index base bytes based on all the info we've collected. */
3289 default_seg = build_modrm_byte ();
3291 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3293 if (i.tm.base_opcode == POP_SEG_SHORT
3294 && i.op[0].regs->reg_num == 1)
3296 as_bad (_("you can't `pop %%cs'"));
3299 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3300 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3303 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3307 else if ((i.tm.opcode_modifier & IsString) != 0)
3309 /* For the string instructions that allow a segment override
3310 on one of their operands, the default segment is ds. */
3314 if ((i.tm.base_opcode == 0x8d /* lea */
3315 || (i.tm.cpu_flags & CpuSVME))
3316 && i.seg[0] && !quiet_warnings)
3317 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
3319 /* If a segment was explicitly specified, and the specified segment
3320 is not the default, use an opcode prefix to select it. If we
3321 never figured out what the default segment is, then default_seg
3322 will be zero at this point, and the specified segment prefix will
3324 if ((i.seg[0]) && (i.seg[0] != default_seg))
3326 if (!add_prefix (i.seg[0]->seg_prefix))
3332 static const seg_entry *
3335 const seg_entry *default_seg = 0;
3337 /* i.reg_operands MUST be the number of real register operands;
3338 implicit registers do not count. */
3339 if (i.reg_operands == 2)
3341 unsigned int source, dest;
3342 source = ((i.types[0]
3343 & (Reg | RegMMX | RegXMM
3345 | Control | Debug | Test))
3348 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3349 bytes and hence source operand will be in the next byte after the immediates */
3350 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
3354 /* One of the register operands will be encoded in the i.tm.reg
3355 field, the other in the combined i.tm.mode and i.tm.regmem
3356 fields. If no form of this instruction supports a memory
3357 destination operand, then we assume the source operand may
3358 sometimes be a memory operand and so we need to store the
3359 destination in the i.rm.reg field. */
3360 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3362 i.rm.reg = i.op[dest].regs->reg_num;
3363 i.rm.regmem = i.op[source].regs->reg_num;
3364 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3366 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3371 i.rm.reg = i.op[source].regs->reg_num;
3372 i.rm.regmem = i.op[dest].regs->reg_num;
3373 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3375 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3378 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3380 if (!((i.types[0] | i.types[1]) & Control))
3382 i.rex &= ~(REX_EXTX | REX_EXTZ);
3383 add_prefix (LOCK_PREFIX_OPCODE);
3387 { /* If it's not 2 reg operands... */
3390 unsigned int fake_zero_displacement = 0;
3391 unsigned int op = ((i.types[0] & AnyMem)
3393 : (i.types[1] & AnyMem) ? 1 : 2);
3397 if (i.base_reg == 0)
3400 if (!i.disp_operands)
3401 fake_zero_displacement = 1;
3402 if (i.index_reg == 0)
3404 /* Operand is just <disp> */
3405 if (flag_code == CODE_64BIT)
3407 /* 64bit mode overwrites the 32bit absolute
3408 addressing by RIP relative addressing and
3409 absolute addressing is encoded by one of the
3410 redundant SIB forms. */
3411 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3412 i.sib.base = NO_BASE_REGISTER;
3413 i.sib.index = NO_INDEX_REGISTER;
3414 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3416 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3418 i.rm.regmem = NO_BASE_REGISTER_16;
3419 i.types[op] = Disp16;
3423 i.rm.regmem = NO_BASE_REGISTER;
3424 i.types[op] = Disp32;
3427 else /* !i.base_reg && i.index_reg */
3429 i.sib.index = i.index_reg->reg_num;
3430 i.sib.base = NO_BASE_REGISTER;
3431 i.sib.scale = i.log2_scale_factor;
3432 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3433 i.types[op] &= ~Disp;
3434 if (flag_code != CODE_64BIT)
3435 i.types[op] |= Disp32; /* Must be 32 bit */
3437 i.types[op] |= Disp32S;
3438 if ((i.index_reg->reg_flags & RegRex) != 0)
3442 /* RIP addressing for 64bit mode. */
3443 else if (i.base_reg->reg_type == BaseIndex)
3445 i.rm.regmem = NO_BASE_REGISTER;
3446 i.types[op] &= ~ Disp;
3447 i.types[op] |= Disp32S;
3448 i.flags[op] = Operand_PCrel;
3449 if (! i.disp_operands)
3450 fake_zero_displacement = 1;
3452 else if (i.base_reg->reg_type & Reg16)
3454 switch (i.base_reg->reg_num)
3457 if (i.index_reg == 0)
3459 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3460 i.rm.regmem = i.index_reg->reg_num - 6;
3464 if (i.index_reg == 0)
3467 if ((i.types[op] & Disp) == 0)
3469 /* fake (%bp) into 0(%bp) */
3470 i.types[op] |= Disp8;
3471 fake_zero_displacement = 1;
3474 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3475 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3477 default: /* (%si) -> 4 or (%di) -> 5 */
3478 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3480 i.rm.mode = mode_from_disp_size (i.types[op]);
3482 else /* i.base_reg and 32/64 bit mode */
3484 if (flag_code == CODE_64BIT
3485 && (i.types[op] & Disp))
3486 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3488 i.rm.regmem = i.base_reg->reg_num;
3489 if ((i.base_reg->reg_flags & RegRex) != 0)
3491 i.sib.base = i.base_reg->reg_num;
3492 /* x86-64 ignores REX prefix bit here to avoid decoder
3494 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3497 if (i.disp_operands == 0)
3499 fake_zero_displacement = 1;
3500 i.types[op] |= Disp8;
3503 else if (i.base_reg->reg_num == ESP_REG_NUM)
3507 i.sib.scale = i.log2_scale_factor;
3508 if (i.index_reg == 0)
3510 /* <disp>(%esp) becomes two byte modrm with no index
3511 register. We've already stored the code for esp
3512 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3513 Any base register besides %esp will not use the
3514 extra modrm byte. */
3515 i.sib.index = NO_INDEX_REGISTER;
3516 #if !SCALE1_WHEN_NO_INDEX
3517 /* Another case where we force the second modrm byte. */
3518 if (i.log2_scale_factor)
3519 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3524 i.sib.index = i.index_reg->reg_num;
3525 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3526 if ((i.index_reg->reg_flags & RegRex) != 0)
3531 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3532 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3535 i.rm.mode = mode_from_disp_size (i.types[op]);
3538 if (fake_zero_displacement)
3540 /* Fakes a zero displacement assuming that i.types[op]
3541 holds the correct displacement size. */
3544 assert (i.op[op].disps == 0);
3545 exp = &disp_expressions[i.disp_operands++];
3546 i.op[op].disps = exp;
3547 exp->X_op = O_constant;
3548 exp->X_add_number = 0;
3549 exp->X_add_symbol = (symbolS *) 0;
3550 exp->X_op_symbol = (symbolS *) 0;
3554 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3555 (if any) based on i.tm.extension_opcode. Again, we must be
3556 careful to make sure that segment/control/debug/test/MMX
3557 registers are coded into the i.rm.reg field. */
3562 & (Reg | RegMMX | RegXMM
3564 | Control | Debug | Test))
3567 & (Reg | RegMMX | RegXMM
3569 | Control | Debug | Test))
3572 /* If there is an extension opcode to put here, the register
3573 number must be put into the regmem field. */
3574 if (i.tm.extension_opcode != None)
3576 i.rm.regmem = i.op[op].regs->reg_num;
3577 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3582 i.rm.reg = i.op[op].regs->reg_num;
3583 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3587 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3588 must set it to 3 to indicate this is a register operand
3589 in the regmem field. */
3590 if (!i.mem_operands)
3594 /* Fill in i.rm.reg field with extension opcode (if any). */
3595 if (i.tm.extension_opcode != None)
3596 i.rm.reg = i.tm.extension_opcode;
3607 relax_substateT subtype;
3612 if (flag_code == CODE_16BIT)
3616 if (i.prefix[DATA_PREFIX] != 0)
3622 /* Pentium4 branch hints. */
3623 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3624 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3629 if (i.prefix[REX_PREFIX] != 0)
3635 if (i.prefixes != 0 && !intel_syntax)
3636 as_warn (_("skipping prefixes on this instruction"));
3638 /* It's always a symbol; End frag & setup for relax.
3639 Make sure there is enough room in this frag for the largest
3640 instruction we may generate in md_convert_frag. This is 2
3641 bytes for the opcode and room for the prefix and largest
3643 frag_grow (prefix + 2 + 4);
3644 /* Prefix and 1 opcode byte go in fr_fix. */
3645 p = frag_more (prefix + 1);
3646 if (i.prefix[DATA_PREFIX] != 0)
3647 *p++ = DATA_PREFIX_OPCODE;
3648 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3649 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3650 *p++ = i.prefix[SEG_PREFIX];
3651 if (i.prefix[REX_PREFIX] != 0)
3652 *p++ = i.prefix[REX_PREFIX];
3653 *p = i.tm.base_opcode;
3655 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3656 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3657 else if ((cpu_arch_flags & Cpu386) != 0)
3658 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3660 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3663 sym = i.op[0].disps->X_add_symbol;
3664 off = i.op[0].disps->X_add_number;
3666 if (i.op[0].disps->X_op != O_constant
3667 && i.op[0].disps->X_op != O_symbol)
3669 /* Handle complex expressions. */
3670 sym = make_expr_symbol (i.op[0].disps);
3674 /* 1 possible extra opcode + 4 byte displacement go in var part.
3675 Pass reloc in fr_var. */
3676 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3686 if (i.tm.opcode_modifier & JumpByte)
3688 /* This is a loop or jecxz type instruction. */
3690 if (i.prefix[ADDR_PREFIX] != 0)
3692 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3695 /* Pentium4 branch hints. */
3696 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3697 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3699 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3708 if (flag_code == CODE_16BIT)
3711 if (i.prefix[DATA_PREFIX] != 0)
3713 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3723 if (i.prefix[REX_PREFIX] != 0)
3725 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3729 if (i.prefixes != 0 && !intel_syntax)
3730 as_warn (_("skipping prefixes on this instruction"));
3732 p = frag_more (1 + size);
3733 *p++ = i.tm.base_opcode;
3735 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3736 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3738 /* All jumps handled here are signed, but don't use a signed limit
3739 check for 32 and 16 bit jumps as we want to allow wrap around at
3740 4G and 64k respectively. */
3742 fixP->fx_signed = 1;
3746 output_interseg_jump ()
3754 if (flag_code == CODE_16BIT)
3758 if (i.prefix[DATA_PREFIX] != 0)
3764 if (i.prefix[REX_PREFIX] != 0)
3774 if (i.prefixes != 0 && !intel_syntax)
3775 as_warn (_("skipping prefixes on this instruction"));
3777 /* 1 opcode; 2 segment; offset */
3778 p = frag_more (prefix + 1 + 2 + size);
3780 if (i.prefix[DATA_PREFIX] != 0)
3781 *p++ = DATA_PREFIX_OPCODE;
3783 if (i.prefix[REX_PREFIX] != 0)
3784 *p++ = i.prefix[REX_PREFIX];
3786 *p++ = i.tm.base_opcode;
3787 if (i.op[1].imms->X_op == O_constant)
3789 offsetT n = i.op[1].imms->X_add_number;
3792 && !fits_in_unsigned_word (n)
3793 && !fits_in_signed_word (n))
3795 as_bad (_("16-bit jump out of range"));
3798 md_number_to_chars (p, n, size);
3801 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3802 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3803 if (i.op[0].imms->X_op != O_constant)
3804 as_bad (_("can't handle non absolute segment in `%s'"),
3806 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3812 fragS *insn_start_frag;
3813 offsetT insn_start_off;
3815 /* Tie dwarf2 debug info to the address at the start of the insn.
3816 We can't do this after the insn has been output as the current
3817 frag may have been closed off. eg. by frag_var. */
3818 dwarf2_emit_insn (0);
3820 insn_start_frag = frag_now;
3821 insn_start_off = frag_now_fix ();
3824 if (i.tm.opcode_modifier & Jump)
3826 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3828 else if (i.tm.opcode_modifier & JumpInterSegment)
3829 output_interseg_jump ();
3832 /* Output normal instructions here. */
3835 unsigned int prefix;
3837 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3838 Instructions have 3 bytes. We may use one more higher byte
3839 to specify a prefix the instruction requires. */
3840 if ((i.tm.cpu_flags & CpuMNI) != 0)
3842 if (i.tm.base_opcode & 0xff000000)
3844 prefix = (i.tm.base_opcode >> 24) & 0xff;
3848 else if ((i.tm.base_opcode & 0xff0000) != 0)
3850 prefix = (i.tm.base_opcode >> 16) & 0xff;
3851 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3854 if (prefix != REPE_PREFIX_OPCODE
3855 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3856 add_prefix (prefix);
3859 add_prefix (prefix);
3862 /* The prefix bytes. */
3864 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3870 md_number_to_chars (p, (valueT) *q, 1);
3874 /* Now the opcode; be careful about word order here! */
3875 if (fits_in_unsigned_byte (i.tm.base_opcode))
3877 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3881 if ((i.tm.cpu_flags & CpuMNI) != 0)
3884 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3889 /* Put out high byte first: can't use md_number_to_chars! */
3890 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3891 *p = i.tm.base_opcode & 0xff;
3894 /* Now the modrm byte and sib byte (if present). */
3895 if (i.tm.opcode_modifier & Modrm)
3898 md_number_to_chars (p,
3899 (valueT) (i.rm.regmem << 0
3903 /* If i.rm.regmem == ESP (4)
3904 && i.rm.mode != (Register mode)
3906 ==> need second modrm byte. */
3907 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3909 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3912 md_number_to_chars (p,
3913 (valueT) (i.sib.base << 0
3915 | i.sib.scale << 6),
3920 if (i.disp_operands)
3921 output_disp (insn_start_frag, insn_start_off);
3924 output_imm (insn_start_frag, insn_start_off);
3930 pi ("" /*line*/, &i);
3932 #endif /* DEBUG386 */
3936 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
3941 for (n = 0; n < i.operands; n++)
3943 if (i.types[n] & Disp)
3945 if (i.op[n].disps->X_op == O_constant)
3951 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3954 if (i.types[n] & Disp8)
3956 if (i.types[n] & Disp64)
3959 val = offset_in_range (i.op[n].disps->X_add_number,
3961 p = frag_more (size);
3962 md_number_to_chars (p, val, size);
3966 enum bfd_reloc_code_real reloc_type;
3969 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3971 /* The PC relative address is computed relative
3972 to the instruction boundary, so in case immediate
3973 fields follows, we need to adjust the value. */
3974 if (pcrel && i.imm_operands)
3979 for (n1 = 0; n1 < i.operands; n1++)
3980 if (i.types[n1] & Imm)
3982 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3985 if (i.types[n1] & (Imm8 | Imm8S))
3987 if (i.types[n1] & Imm64)
3992 /* We should find the immediate. */
3993 if (n1 == i.operands)
3995 i.op[n].disps->X_add_number -= imm_size;
3998 if (i.types[n] & Disp32S)
4001 if (i.types[n] & (Disp16 | Disp64))
4004 if (i.types[n] & Disp64)
4008 p = frag_more (size);
4009 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
4011 && GOT_symbol == i.op[n].disps->X_add_symbol
4012 && (((reloc_type == BFD_RELOC_32
4013 || reloc_type == BFD_RELOC_X86_64_32S
4014 || (reloc_type == BFD_RELOC_64
4016 && (i.op[n].disps->X_op == O_symbol
4017 || (i.op[n].disps->X_op == O_add
4018 && ((symbol_get_value_expression
4019 (i.op[n].disps->X_op_symbol)->X_op)
4021 || reloc_type == BFD_RELOC_32_PCREL))
4025 if (insn_start_frag == frag_now)
4026 add = (p - frag_now->fr_literal) - insn_start_off;
4031 add = insn_start_frag->fr_fix - insn_start_off;
4032 for (fr = insn_start_frag->fr_next;
4033 fr && fr != frag_now; fr = fr->fr_next)
4035 add += p - frag_now->fr_literal;
4040 reloc_type = BFD_RELOC_386_GOTPC;
4041 i.op[n].imms->X_add_number += add;
4043 else if (reloc_type == BFD_RELOC_64)
4044 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4046 /* Don't do the adjustment for x86-64, as there
4047 the pcrel addressing is relative to the _next_
4048 insn, and that is taken care of in other code. */
4049 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4051 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4052 i.op[n].disps, pcrel, reloc_type);
4059 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
4064 for (n = 0; n < i.operands; n++)
4066 if (i.types[n] & Imm)
4068 if (i.op[n].imms->X_op == O_constant)
4074 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4077 if (i.types[n] & (Imm8 | Imm8S))
4079 else if (i.types[n] & Imm64)
4082 val = offset_in_range (i.op[n].imms->X_add_number,
4084 p = frag_more (size);
4085 md_number_to_chars (p, val, size);
4089 /* Not absolute_section.
4090 Need a 32-bit fixup (don't support 8bit
4091 non-absolute imms). Try to support other
4093 enum bfd_reloc_code_real reloc_type;
4097 if ((i.types[n] & (Imm32S))
4098 && (i.suffix == QWORD_MNEM_SUFFIX
4099 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
4101 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4104 if (i.types[n] & (Imm8 | Imm8S))
4106 if (i.types[n] & Imm64)
4110 p = frag_more (size);
4111 reloc_type = reloc (size, 0, sign, i.reloc[n]);
4113 /* This is tough to explain. We end up with this one if we
4114 * have operands that look like
4115 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4116 * obtain the absolute address of the GOT, and it is strongly
4117 * preferable from a performance point of view to avoid using
4118 * a runtime relocation for this. The actual sequence of
4119 * instructions often look something like:
4124 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4126 * The call and pop essentially return the absolute address
4127 * of the label .L66 and store it in %ebx. The linker itself
4128 * will ultimately change the first operand of the addl so
4129 * that %ebx points to the GOT, but to keep things simple, the
4130 * .o file must have this operand set so that it generates not
4131 * the absolute address of .L66, but the absolute address of
4132 * itself. This allows the linker itself simply treat a GOTPC
4133 * relocation as asking for a pcrel offset to the GOT to be
4134 * added in, and the addend of the relocation is stored in the
4135 * operand field for the instruction itself.
4137 * Our job here is to fix the operand so that it would add
4138 * the correct offset so that %ebx would point to itself. The
4139 * thing that is tricky is that .-.L66 will point to the
4140 * beginning of the instruction, so we need to further modify
4141 * the operand so that it will point to itself. There are
4142 * other cases where you have something like:
4144 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4146 * and here no correction would be required. Internally in
4147 * the assembler we treat operands of this form as not being
4148 * pcrel since the '.' is explicitly mentioned, and I wonder
4149 * whether it would simplify matters to do it this way. Who
4150 * knows. In earlier versions of the PIC patches, the
4151 * pcrel_adjust field was used to store the correction, but
4152 * since the expression is not pcrel, I felt it would be
4153 * confusing to do it this way. */
4155 if ((reloc_type == BFD_RELOC_32
4156 || reloc_type == BFD_RELOC_X86_64_32S
4157 || reloc_type == BFD_RELOC_64)
4159 && GOT_symbol == i.op[n].imms->X_add_symbol
4160 && (i.op[n].imms->X_op == O_symbol
4161 || (i.op[n].imms->X_op == O_add
4162 && ((symbol_get_value_expression
4163 (i.op[n].imms->X_op_symbol)->X_op)
4168 if (insn_start_frag == frag_now)
4169 add = (p - frag_now->fr_literal) - insn_start_off;
4174 add = insn_start_frag->fr_fix - insn_start_off;
4175 for (fr = insn_start_frag->fr_next;
4176 fr && fr != frag_now; fr = fr->fr_next)
4178 add += p - frag_now->fr_literal;
4182 reloc_type = BFD_RELOC_386_GOTPC;
4184 reloc_type = BFD_RELOC_X86_64_GOTPC32;
4186 reloc_type = BFD_RELOC_X86_64_GOTPC64;
4187 i.op[n].imms->X_add_number += add;
4189 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4190 i.op[n].imms, 0, reloc_type);
4196 /* x86_cons_fix_new is called via the expression parsing code when a
4197 reloc is needed. We use this hook to get the correct .got reloc. */
4198 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4199 static int cons_sign = -1;
4202 x86_cons_fix_new (fragS *frag,
4207 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4209 got_reloc = NO_RELOC;
4212 if (exp->X_op == O_secrel)
4214 exp->X_op = O_symbol;
4215 r = BFD_RELOC_32_SECREL;
4219 fix_new_exp (frag, off, len, exp, 0, r);
4222 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4223 # define lex_got(reloc, adjust, types) NULL
4225 /* Parse operands of the form
4226 <symbol>@GOTOFF+<nnn>
4227 and similar .plt or .got references.
4229 If we find one, set up the correct relocation in RELOC and copy the
4230 input string, minus the `@GOTOFF' into a malloc'd buffer for
4231 parsing by the calling routine. Return this buffer, and if ADJUST
4232 is non-null set it to the length of the string we removed from the
4233 input line. Otherwise return NULL. */
4235 lex_got (enum bfd_reloc_code_real *reloc,
4237 unsigned int *types)
4239 /* Some of the relocations depend on the size of what field is to
4240 be relocated. But in our callers i386_immediate and i386_displacement
4241 we don't yet know the operand size (this will be set by insn
4242 matching). Hence we record the word32 relocation here,
4243 and adjust the reloc according to the real size in reloc(). */
4244 static const struct {
4246 const enum bfd_reloc_code_real rel[2];
4247 const unsigned int types64;
4249 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4250 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
4251 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4252 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4253 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4254 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4255 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4256 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4257 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4258 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4259 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4260 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4261 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4262 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
4263 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
4264 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4265 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
4273 for (cp = input_line_pointer; *cp != '@'; cp++)
4274 if (is_end_of_line[(unsigned char) *cp])
4277 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4281 len = strlen (gotrel[j].str);
4282 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
4284 if (gotrel[j].rel[object_64bit] != 0)
4287 char *tmpbuf, *past_reloc;
4289 *reloc = gotrel[j].rel[object_64bit];
4295 if (flag_code != CODE_64BIT)
4296 *types = Imm32|Disp32;
4298 *types = gotrel[j].types64;
4301 if (GOT_symbol == NULL)
4302 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4304 /* Replace the relocation token with ' ', so that
4305 errors like foo@GOTOFF1 will be detected. */
4307 /* The length of the first part of our input line. */
4308 first = cp - input_line_pointer;
4310 /* The second part goes from after the reloc token until
4311 (and including) an end_of_line char. Don't use strlen
4312 here as the end_of_line char may not be a NUL. */
4313 past_reloc = cp + 1 + len;
4314 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4316 second = cp - past_reloc;
4318 /* Allocate and copy string. The trailing NUL shouldn't
4319 be necessary, but be safe. */
4320 tmpbuf = xmalloc (first + second + 2);
4321 memcpy (tmpbuf, input_line_pointer, first);
4322 tmpbuf[first] = ' ';
4323 memcpy (tmpbuf + first + 1, past_reloc, second);
4324 tmpbuf[first + second + 1] = '\0';
4328 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4329 gotrel[j].str, 1 << (5 + object_64bit));
4334 /* Might be a symbol version string. Don't as_bad here. */
4339 x86_cons (exp, size)
4343 if (size == 4 || (object_64bit && size == 8))
4345 /* Handle @GOTOFF and the like in an expression. */
4347 char *gotfree_input_line;
4350 save = input_line_pointer;
4351 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
4352 if (gotfree_input_line)
4353 input_line_pointer = gotfree_input_line;
4357 if (gotfree_input_line)
4359 /* expression () has merrily parsed up to the end of line,
4360 or a comma - in the wrong buffer. Transfer how far
4361 input_line_pointer has moved to the right buffer. */
4362 input_line_pointer = (save
4363 + (input_line_pointer - gotfree_input_line)
4365 free (gotfree_input_line);
4373 static void signed_cons (int size)
4375 if (flag_code == CODE_64BIT)
4383 pe_directive_secrel (dummy)
4384 int dummy ATTRIBUTE_UNUSED;
4391 if (exp.X_op == O_symbol)
4392 exp.X_op = O_secrel;
4394 emit_expr (&exp, 4);
4396 while (*input_line_pointer++ == ',');
4398 input_line_pointer--;
4399 demand_empty_rest_of_line ();
4403 static int i386_immediate PARAMS ((char *));
4406 i386_immediate (imm_start)
4409 char *save_input_line_pointer;
4410 char *gotfree_input_line;
4413 unsigned int types = ~0U;
4415 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4417 as_bad (_("only 1 or 2 immediate operands are allowed"));
4421 exp = &im_expressions[i.imm_operands++];
4422 i.op[this_operand].imms = exp;
4424 if (is_space_char (*imm_start))
4427 save_input_line_pointer = input_line_pointer;
4428 input_line_pointer = imm_start;
4430 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4431 if (gotfree_input_line)
4432 input_line_pointer = gotfree_input_line;
4434 exp_seg = expression (exp);
4437 if (*input_line_pointer)
4438 as_bad (_("junk `%s' after expression"), input_line_pointer);
4440 input_line_pointer = save_input_line_pointer;
4441 if (gotfree_input_line)
4442 free (gotfree_input_line);
4444 if (exp->X_op == O_absent || exp->X_op == O_big)
4446 /* Missing or bad expr becomes absolute 0. */
4447 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4449 exp->X_op = O_constant;
4450 exp->X_add_number = 0;
4451 exp->X_add_symbol = (symbolS *) 0;
4452 exp->X_op_symbol = (symbolS *) 0;
4454 else if (exp->X_op == O_constant)
4456 /* Size it properly later. */
4457 i.types[this_operand] |= Imm64;
4458 /* If BFD64, sign extend val. */
4459 if (!use_rela_relocations)
4460 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4461 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4463 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4464 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4465 && exp_seg != absolute_section
4466 && exp_seg != text_section
4467 && exp_seg != data_section
4468 && exp_seg != bss_section
4469 && exp_seg != undefined_section
4470 && !bfd_is_com_section (exp_seg))
4472 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4476 else if (!intel_syntax && exp->X_op == O_register)
4478 as_bad (_("illegal immediate register operand %s"), imm_start);
4483 /* This is an address. The size of the address will be
4484 determined later, depending on destination register,
4485 suffix, or the default for the section. */
4486 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4487 i.types[this_operand] &= types;
4493 static char *i386_scale PARAMS ((char *));
4500 char *save = input_line_pointer;
4502 input_line_pointer = scale;
4503 val = get_absolute_expression ();
4508 i.log2_scale_factor = 0;
4511 i.log2_scale_factor = 1;
4514 i.log2_scale_factor = 2;
4517 i.log2_scale_factor = 3;
4521 char sep = *input_line_pointer;
4523 *input_line_pointer = '\0';
4524 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4526 *input_line_pointer = sep;
4527 input_line_pointer = save;
4531 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4533 as_warn (_("scale factor of %d without an index register"),
4534 1 << i.log2_scale_factor);
4535 #if SCALE1_WHEN_NO_INDEX
4536 i.log2_scale_factor = 0;
4539 scale = input_line_pointer;
4540 input_line_pointer = save;
4544 static int i386_displacement PARAMS ((char *, char *));
4547 i386_displacement (disp_start, disp_end)
4553 char *save_input_line_pointer;
4554 char *gotfree_input_line;
4555 int bigdisp, override;
4556 unsigned int types = Disp;
4558 if ((i.types[this_operand] & JumpAbsolute)
4559 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4562 override = (i.prefix[ADDR_PREFIX] != 0);
4566 /* For PC-relative branches, the width of the displacement
4567 is dependent upon data size, not address size. */
4569 override = (i.prefix[DATA_PREFIX] != 0);
4571 if (flag_code == CODE_64BIT)
4574 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4576 : Disp32S | Disp32);
4578 bigdisp = Disp64 | Disp32S | Disp32;
4585 override = (i.suffix == (flag_code != CODE_16BIT
4587 : LONG_MNEM_SUFFIX));
4590 if ((flag_code == CODE_16BIT) ^ override)
4593 i.types[this_operand] |= bigdisp;
4595 exp = &disp_expressions[i.disp_operands];
4596 i.op[this_operand].disps = exp;
4598 save_input_line_pointer = input_line_pointer;
4599 input_line_pointer = disp_start;
4600 END_STRING_AND_SAVE (disp_end);
4602 #ifndef GCC_ASM_O_HACK
4603 #define GCC_ASM_O_HACK 0
4606 END_STRING_AND_SAVE (disp_end + 1);
4607 if ((i.types[this_operand] & BaseIndex) != 0
4608 && displacement_string_end[-1] == '+')
4610 /* This hack is to avoid a warning when using the "o"
4611 constraint within gcc asm statements.
4614 #define _set_tssldt_desc(n,addr,limit,type) \
4615 __asm__ __volatile__ ( \
4617 "movw %w1,2+%0\n\t" \
4619 "movb %b1,4+%0\n\t" \
4620 "movb %4,5+%0\n\t" \
4621 "movb $0,6+%0\n\t" \
4622 "movb %h1,7+%0\n\t" \
4624 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4626 This works great except that the output assembler ends
4627 up looking a bit weird if it turns out that there is
4628 no offset. You end up producing code that looks like:
4641 So here we provide the missing zero. */
4643 *displacement_string_end = '0';
4646 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4647 if (gotfree_input_line)
4648 input_line_pointer = gotfree_input_line;
4650 exp_seg = expression (exp);
4653 if (*input_line_pointer)
4654 as_bad (_("junk `%s' after expression"), input_line_pointer);
4656 RESTORE_END_STRING (disp_end + 1);
4658 RESTORE_END_STRING (disp_end);
4659 input_line_pointer = save_input_line_pointer;
4660 if (gotfree_input_line)
4661 free (gotfree_input_line);
4663 /* We do this to make sure that the section symbol is in
4664 the symbol table. We will ultimately change the relocation
4665 to be relative to the beginning of the section. */
4666 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4667 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4668 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4670 if (exp->X_op != O_symbol)
4672 as_bad (_("bad expression used with @%s"),
4673 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4679 if (S_IS_LOCAL (exp->X_add_symbol)
4680 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4681 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4682 exp->X_op = O_subtract;
4683 exp->X_op_symbol = GOT_symbol;
4684 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4685 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4686 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4687 i.reloc[this_operand] = BFD_RELOC_64;
4689 i.reloc[this_operand] = BFD_RELOC_32;
4692 if (exp->X_op == O_absent || exp->X_op == O_big)
4694 /* Missing or bad expr becomes absolute 0. */
4695 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4697 exp->X_op = O_constant;
4698 exp->X_add_number = 0;
4699 exp->X_add_symbol = (symbolS *) 0;
4700 exp->X_op_symbol = (symbolS *) 0;
4703 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4704 if (exp->X_op != O_constant
4705 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4706 && exp_seg != absolute_section
4707 && exp_seg != text_section
4708 && exp_seg != data_section
4709 && exp_seg != bss_section
4710 && exp_seg != undefined_section
4711 && !bfd_is_com_section (exp_seg))
4713 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4718 if (!(i.types[this_operand] & ~Disp))
4719 i.types[this_operand] &= types;
4724 static int i386_index_check PARAMS ((const char *));
4726 /* Make sure the memory operand we've been dealt is valid.
4727 Return 1 on success, 0 on a failure. */
4730 i386_index_check (operand_string)
4731 const char *operand_string;
4734 #if INFER_ADDR_PREFIX
4740 if ((current_templates->start->cpu_flags & CpuSVME)
4741 && current_templates->end[-1].operand_types[0] == AnyMem)
4743 /* Memory operands of SVME insns are special in that they only allow
4744 rAX as their memory address and ignore any segment override. */
4747 /* SKINIT is even more restrictive: it always requires EAX. */
4748 if (strcmp (current_templates->start->name, "skinit") == 0)
4750 else if (flag_code == CODE_64BIT)
4751 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4753 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4757 || !(i.base_reg->reg_type & Acc)
4758 || !(i.base_reg->reg_type & RegXX)
4760 || (i.types[0] & Disp))
4763 else if (flag_code == CODE_64BIT)
4765 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4768 && ((i.base_reg->reg_type & RegXX) == 0)
4769 && (i.base_reg->reg_type != BaseIndex
4772 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4773 != (RegXX | BaseIndex))))
4778 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4782 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4783 != (Reg16 | BaseIndex)))
4785 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4786 != (Reg16 | BaseIndex))
4788 && i.base_reg->reg_num < 6
4789 && i.index_reg->reg_num >= 6
4790 && i.log2_scale_factor == 0))))
4797 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4799 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4800 != (Reg32 | BaseIndex))))
4806 #if INFER_ADDR_PREFIX
4807 if (i.prefix[ADDR_PREFIX] == 0)
4809 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4811 /* Change the size of any displacement too. At most one of
4812 Disp16 or Disp32 is set.
4813 FIXME. There doesn't seem to be any real need for separate
4814 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4815 Removing them would probably clean up the code quite a lot. */
4816 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4817 i.types[this_operand] ^= (Disp16 | Disp32);
4822 as_bad (_("`%s' is not a valid base/index expression"),
4826 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4828 flag_code_names[flag_code]);
4833 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4837 i386_operand (operand_string)
4838 char *operand_string;
4842 char *op_string = operand_string;
4844 if (is_space_char (*op_string))
4847 /* We check for an absolute prefix (differentiating,
4848 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4849 if (*op_string == ABSOLUTE_PREFIX)
4852 if (is_space_char (*op_string))
4854 i.types[this_operand] |= JumpAbsolute;
4857 /* Check if operand is a register. */
4858 if ((r = parse_register (op_string, &end_op)) != NULL)
4860 /* Check for a segment override by searching for ':' after a
4861 segment register. */
4863 if (is_space_char (*op_string))
4865 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4870 i.seg[i.mem_operands] = &es;
4873 i.seg[i.mem_operands] = &cs;
4876 i.seg[i.mem_operands] = &ss;
4879 i.seg[i.mem_operands] = &ds;
4882 i.seg[i.mem_operands] = &fs;
4885 i.seg[i.mem_operands] = &gs;
4889 /* Skip the ':' and whitespace. */
4891 if (is_space_char (*op_string))
4894 if (!is_digit_char (*op_string)
4895 && !is_identifier_char (*op_string)
4896 && *op_string != '('
4897 && *op_string != ABSOLUTE_PREFIX)
4899 as_bad (_("bad memory operand `%s'"), op_string);
4902 /* Handle case of %es:*foo. */
4903 if (*op_string == ABSOLUTE_PREFIX)
4906 if (is_space_char (*op_string))
4908 i.types[this_operand] |= JumpAbsolute;
4910 goto do_memory_reference;
4914 as_bad (_("junk `%s' after register"), op_string);
4917 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4918 i.op[this_operand].regs = r;
4921 else if (*op_string == REGISTER_PREFIX)
4923 as_bad (_("bad register name `%s'"), op_string);
4926 else if (*op_string == IMMEDIATE_PREFIX)
4929 if (i.types[this_operand] & JumpAbsolute)
4931 as_bad (_("immediate operand illegal with absolute jump"));
4934 if (!i386_immediate (op_string))
4937 else if (is_digit_char (*op_string)
4938 || is_identifier_char (*op_string)
4939 || *op_string == '(')
4941 /* This is a memory reference of some sort. */
4944 /* Start and end of displacement string expression (if found). */
4945 char *displacement_string_start;
4946 char *displacement_string_end;
4948 do_memory_reference:
4949 if ((i.mem_operands == 1
4950 && (current_templates->start->opcode_modifier & IsString) == 0)
4951 || i.mem_operands == 2)
4953 as_bad (_("too many memory references for `%s'"),
4954 current_templates->start->name);
4958 /* Check for base index form. We detect the base index form by
4959 looking for an ')' at the end of the operand, searching
4960 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4962 base_string = op_string + strlen (op_string);
4965 if (is_space_char (*base_string))
4968 /* If we only have a displacement, set-up for it to be parsed later. */
4969 displacement_string_start = op_string;
4970 displacement_string_end = base_string + 1;
4972 if (*base_string == ')')
4975 unsigned int parens_balanced = 1;
4976 /* We've already checked that the number of left & right ()'s are
4977 equal, so this loop will not be infinite. */
4981 if (*base_string == ')')
4983 if (*base_string == '(')
4986 while (parens_balanced);
4988 temp_string = base_string;
4990 /* Skip past '(' and whitespace. */
4992 if (is_space_char (*base_string))
4995 if (*base_string == ','
4996 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
4998 displacement_string_end = temp_string;
5000 i.types[this_operand] |= BaseIndex;
5004 base_string = end_op;
5005 if (is_space_char (*base_string))
5009 /* There may be an index reg or scale factor here. */
5010 if (*base_string == ',')
5013 if (is_space_char (*base_string))
5016 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
5018 base_string = end_op;
5019 if (is_space_char (*base_string))
5021 if (*base_string == ',')
5024 if (is_space_char (*base_string))
5027 else if (*base_string != ')')
5029 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5034 else if (*base_string == REGISTER_PREFIX)
5036 as_bad (_("bad register name `%s'"), base_string);
5040 /* Check for scale factor. */
5041 if (*base_string != ')')
5043 char *end_scale = i386_scale (base_string);
5048 base_string = end_scale;
5049 if (is_space_char (*base_string))
5051 if (*base_string != ')')
5053 as_bad (_("expecting `)' after scale factor in `%s'"),
5058 else if (!i.index_reg)
5060 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5065 else if (*base_string != ')')
5067 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5072 else if (*base_string == REGISTER_PREFIX)
5074 as_bad (_("bad register name `%s'"), base_string);
5079 /* If there's an expression beginning the operand, parse it,
5080 assuming displacement_string_start and
5081 displacement_string_end are meaningful. */
5082 if (displacement_string_start != displacement_string_end)
5084 if (!i386_displacement (displacement_string_start,
5085 displacement_string_end))
5089 /* Special case for (%dx) while doing input/output op. */
5091 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5093 && i.log2_scale_factor == 0
5094 && i.seg[i.mem_operands] == 0
5095 && (i.types[this_operand] & Disp) == 0)
5097 i.types[this_operand] = InOutPortReg;
5101 if (i386_index_check (operand_string) == 0)
5107 /* It's not a memory operand; argh! */
5108 as_bad (_("invalid char %s beginning operand %d `%s'"),
5109 output_invalid (*op_string),
5114 return 1; /* Normal return. */
5117 /* md_estimate_size_before_relax()
5119 Called just before relax() for rs_machine_dependent frags. The x86
5120 assembler uses these frags to handle variable size jump
5123 Any symbol that is now undefined will not become defined.
5124 Return the correct fr_subtype in the frag.
5125 Return the initial "guess for variable size of frag" to caller.
5126 The guess is actually the growth beyond the fixed part. Whatever
5127 we do to grow the fixed or variable part contributes to our
5131 md_estimate_size_before_relax (fragP, segment)
5135 /* We've already got fragP->fr_subtype right; all we have to do is
5136 check for un-relaxable symbols. On an ELF system, we can't relax
5137 an externally visible symbol, because it may be overridden by a
5139 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
5140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5142 && (S_IS_EXTERNAL (fragP->fr_symbol)
5143 || S_IS_WEAK (fragP->fr_symbol)))
5147 /* Symbol is undefined in this segment, or we need to keep a
5148 reloc so that weak symbols can be overridden. */
5149 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
5150 enum bfd_reloc_code_real reloc_type;
5151 unsigned char *opcode;
5154 if (fragP->fr_var != NO_RELOC)
5155 reloc_type = fragP->fr_var;
5157 reloc_type = BFD_RELOC_16_PCREL;
5159 reloc_type = BFD_RELOC_32_PCREL;
5161 old_fr_fix = fragP->fr_fix;
5162 opcode = (unsigned char *) fragP->fr_opcode;
5164 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
5167 /* Make jmp (0xeb) a (d)word displacement jump. */
5169 fragP->fr_fix += size;
5170 fix_new (fragP, old_fr_fix, size,
5172 fragP->fr_offset, 1,
5178 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
5180 /* Negate the condition, and branch past an
5181 unconditional jump. */
5184 /* Insert an unconditional jump. */
5186 /* We added two extra opcode bytes, and have a two byte
5188 fragP->fr_fix += 2 + 2;
5189 fix_new (fragP, old_fr_fix + 2, 2,
5191 fragP->fr_offset, 1,
5198 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5203 fixP = fix_new (fragP, old_fr_fix, 1,
5205 fragP->fr_offset, 1,
5207 fixP->fx_signed = 1;
5211 /* This changes the byte-displacement jump 0x7N
5212 to the (d)word-displacement jump 0x0f,0x8N. */
5213 opcode[1] = opcode[0] + 0x10;
5214 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5215 /* We've added an opcode byte. */
5216 fragP->fr_fix += 1 + size;
5217 fix_new (fragP, old_fr_fix + 1, size,
5219 fragP->fr_offset, 1,
5224 BAD_CASE (fragP->fr_subtype);
5228 return fragP->fr_fix - old_fr_fix;
5231 /* Guess size depending on current relax state. Initially the relax
5232 state will correspond to a short jump and we return 1, because
5233 the variable part of the frag (the branch offset) is one byte
5234 long. However, we can relax a section more than once and in that
5235 case we must either set fr_subtype back to the unrelaxed state,
5236 or return the value for the appropriate branch. */
5237 return md_relax_table[fragP->fr_subtype].rlx_length;
5240 /* Called after relax() is finished.
5242 In: Address of frag.
5243 fr_type == rs_machine_dependent.
5244 fr_subtype is what the address relaxed to.
5246 Out: Any fixSs and constants are set up.
5247 Caller will turn frag into a ".space 0". */
5250 md_convert_frag (abfd, sec, fragP)
5251 bfd *abfd ATTRIBUTE_UNUSED;
5252 segT sec ATTRIBUTE_UNUSED;
5255 unsigned char *opcode;
5256 unsigned char *where_to_put_displacement = NULL;
5257 offsetT target_address;
5258 offsetT opcode_address;
5259 unsigned int extension = 0;
5260 offsetT displacement_from_opcode_start;
5262 opcode = (unsigned char *) fragP->fr_opcode;
5264 /* Address we want to reach in file space. */
5265 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
5267 /* Address opcode resides at in file space. */
5268 opcode_address = fragP->fr_address + fragP->fr_fix;
5270 /* Displacement from opcode start to fill into instruction. */
5271 displacement_from_opcode_start = target_address - opcode_address;
5273 if ((fragP->fr_subtype & BIG) == 0)
5275 /* Don't have to change opcode. */
5276 extension = 1; /* 1 opcode + 1 displacement */
5277 where_to_put_displacement = &opcode[1];
5281 if (no_cond_jump_promotion
5282 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5283 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
5285 switch (fragP->fr_subtype)
5287 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5288 extension = 4; /* 1 opcode + 4 displacement */
5290 where_to_put_displacement = &opcode[1];
5293 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5294 extension = 2; /* 1 opcode + 2 displacement */
5296 where_to_put_displacement = &opcode[1];
5299 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5300 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5301 extension = 5; /* 2 opcode + 4 displacement */
5302 opcode[1] = opcode[0] + 0x10;
5303 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5304 where_to_put_displacement = &opcode[2];
5307 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5308 extension = 3; /* 2 opcode + 2 displacement */
5309 opcode[1] = opcode[0] + 0x10;
5310 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5311 where_to_put_displacement = &opcode[2];
5314 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5319 where_to_put_displacement = &opcode[3];
5323 BAD_CASE (fragP->fr_subtype);
5328 /* If size if less then four we are sure that the operand fits,
5329 but if it's 4, then it could be that the displacement is larger
5331 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5333 && ((addressT) (displacement_from_opcode_start - extension
5334 + ((addressT) 1 << 31))
5335 > (((addressT) 2 << 31) - 1)))
5337 as_bad_where (fragP->fr_file, fragP->fr_line,
5338 _("jump target out of range"));
5339 /* Make us emit 0. */
5340 displacement_from_opcode_start = extension;
5342 /* Now put displacement after opcode. */
5343 md_number_to_chars ((char *) where_to_put_displacement,
5344 (valueT) (displacement_from_opcode_start - extension),
5345 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
5346 fragP->fr_fix += extension;
5349 /* Size of byte displacement jmp. */
5350 int md_short_jump_size = 2;
5352 /* Size of dword displacement jmp. */
5353 int md_long_jump_size = 5;
5356 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5358 addressT from_addr, to_addr;
5359 fragS *frag ATTRIBUTE_UNUSED;
5360 symbolS *to_symbol ATTRIBUTE_UNUSED;
5364 offset = to_addr - (from_addr + 2);
5365 /* Opcode for byte-disp jump. */
5366 md_number_to_chars (ptr, (valueT) 0xeb, 1);
5367 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5371 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5373 addressT from_addr, to_addr;
5374 fragS *frag ATTRIBUTE_UNUSED;
5375 symbolS *to_symbol ATTRIBUTE_UNUSED;
5379 offset = to_addr - (from_addr + 5);
5380 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5381 md_number_to_chars (ptr + 1, (valueT) offset, 4);
5384 /* Apply a fixup (fixS) to segment data, once it has been determined
5385 by our caller that we have all the info we need to fix it up.
5387 On the 386, immediates, displacements, and data pointers are all in
5388 the same (little-endian) format, so we don't need to care about which
5392 md_apply_fix (fixP, valP, seg)
5393 /* The fix we're to put in. */
5395 /* Pointer to the value of the bits. */
5397 /* Segment fix is from. */
5398 segT seg ATTRIBUTE_UNUSED;
5400 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
5401 valueT value = *valP;
5403 #if !defined (TE_Mach)
5406 switch (fixP->fx_r_type)
5412 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5415 case BFD_RELOC_X86_64_32S:
5416 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5419 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5422 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5427 if (fixP->fx_addsy != NULL
5428 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
5429 || fixP->fx_r_type == BFD_RELOC_64_PCREL
5430 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5431 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5432 && !use_rela_relocations)
5434 /* This is a hack. There should be a better way to handle this.
5435 This covers for the fact that bfd_install_relocation will
5436 subtract the current location (for partial_inplace, PC relative
5437 relocations); see more below. */
5441 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5444 value += fixP->fx_where + fixP->fx_frag->fr_address;
5446 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5449 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5452 || (symbol_section_p (fixP->fx_addsy)
5453 && sym_seg != absolute_section))
5454 && !generic_force_reloc (fixP))
5456 /* Yes, we add the values in twice. This is because
5457 bfd_install_relocation subtracts them out again. I think
5458 bfd_install_relocation is broken, but I don't dare change
5460 value += fixP->fx_where + fixP->fx_frag->fr_address;
5464 #if defined (OBJ_COFF) && defined (TE_PE)
5465 /* For some reason, the PE format does not store a
5466 section address offset for a PC relative symbol. */
5467 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5468 || S_IS_WEAK (fixP->fx_addsy))
5469 value += md_pcrel_from (fixP);
5473 /* Fix a few things - the dynamic linker expects certain values here,
5474 and we must not disappoint it. */
5475 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5476 if (IS_ELF && fixP->fx_addsy)
5477 switch (fixP->fx_r_type)
5479 case BFD_RELOC_386_PLT32:
5480 case BFD_RELOC_X86_64_PLT32:
5481 /* Make the jump instruction point to the address of the operand. At
5482 runtime we merely add the offset to the actual PLT entry. */
5486 case BFD_RELOC_386_TLS_GD:
5487 case BFD_RELOC_386_TLS_LDM:
5488 case BFD_RELOC_386_TLS_IE_32:
5489 case BFD_RELOC_386_TLS_IE:
5490 case BFD_RELOC_386_TLS_GOTIE:
5491 case BFD_RELOC_386_TLS_GOTDESC:
5492 case BFD_RELOC_X86_64_TLSGD:
5493 case BFD_RELOC_X86_64_TLSLD:
5494 case BFD_RELOC_X86_64_GOTTPOFF:
5495 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5496 value = 0; /* Fully resolved at runtime. No addend. */
5498 case BFD_RELOC_386_TLS_LE:
5499 case BFD_RELOC_386_TLS_LDO_32:
5500 case BFD_RELOC_386_TLS_LE_32:
5501 case BFD_RELOC_X86_64_DTPOFF32:
5502 case BFD_RELOC_X86_64_DTPOFF64:
5503 case BFD_RELOC_X86_64_TPOFF32:
5504 case BFD_RELOC_X86_64_TPOFF64:
5505 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5508 case BFD_RELOC_386_TLS_DESC_CALL:
5509 case BFD_RELOC_X86_64_TLSDESC_CALL:
5510 value = 0; /* Fully resolved at runtime. No addend. */
5511 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5515 case BFD_RELOC_386_GOT32:
5516 case BFD_RELOC_X86_64_GOT32:
5517 value = 0; /* Fully resolved at runtime. No addend. */
5520 case BFD_RELOC_VTABLE_INHERIT:
5521 case BFD_RELOC_VTABLE_ENTRY:
5528 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5530 #endif /* !defined (TE_Mach) */
5532 /* Are we finished with this relocation now? */
5533 if (fixP->fx_addsy == NULL)
5535 else if (use_rela_relocations)
5537 fixP->fx_no_overflow = 1;
5538 /* Remember value for tc_gen_reloc. */
5539 fixP->fx_addnumber = value;
5543 md_number_to_chars (p, value, fixP->fx_size);
5546 #define MAX_LITTLENUMS 6
5548 /* Turn the string pointed to by litP into a floating point constant
5549 of type TYPE, and emit the appropriate bytes. The number of
5550 LITTLENUMS emitted is stored in *SIZEP. An error message is
5551 returned, or NULL on OK. */
5554 md_atof (type, litP, sizeP)
5560 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5561 LITTLENUM_TYPE *wordP;
5583 return _("Bad call to md_atof ()");
5585 t = atof_ieee (input_line_pointer, type, words);
5587 input_line_pointer = t;
5589 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5590 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5591 the bigendian 386. */
5592 for (wordP = words + prec - 1; prec--;)
5594 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5595 litP += sizeof (LITTLENUM_TYPE);
5600 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
5607 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5610 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5611 "(0x%x)", (unsigned char) c);
5612 return output_invalid_buf;
5615 /* REG_STRING starts *before* REGISTER_PREFIX. */
5617 static const reg_entry *
5618 parse_real_register (char *reg_string, char **end_op)
5620 char *s = reg_string;
5622 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5625 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5626 if (*s == REGISTER_PREFIX)
5629 if (is_space_char (*s))
5633 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5635 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5636 return (const reg_entry *) NULL;
5640 /* For naked regs, make sure that we are not dealing with an identifier.
5641 This prevents confusing an identifier like `eax_var' with register
5643 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5644 return (const reg_entry *) NULL;
5648 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5650 /* Handle floating point regs, allowing spaces in the (i) part. */
5651 if (r == i386_regtab /* %st is first entry of table */)
5653 if (is_space_char (*s))
5658 if (is_space_char (*s))
5660 if (*s >= '0' && *s <= '7')
5662 r = &i386_float_regtab[*s - '0'];
5664 if (is_space_char (*s))
5672 /* We have "%st(" then garbage. */
5673 return (const reg_entry *) NULL;
5678 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5679 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5680 && flag_code != CODE_64BIT)
5681 return (const reg_entry *) NULL;
5686 /* REG_STRING starts *before* REGISTER_PREFIX. */
5688 static const reg_entry *
5689 parse_register (char *reg_string, char **end_op)
5693 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5694 r = parse_real_register (reg_string, end_op);
5699 char *save = input_line_pointer;
5703 input_line_pointer = reg_string;
5704 c = get_symbol_end ();
5705 symbolP = symbol_find (reg_string);
5706 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5708 const expressionS *e = symbol_get_value_expression (symbolP);
5710 know (e->X_op == O_register);
5711 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5712 r = i386_regtab + e->X_add_number;
5713 *end_op = input_line_pointer;
5715 *input_line_pointer = c;
5716 input_line_pointer = save;
5722 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5725 char *end = input_line_pointer;
5728 r = parse_register (name, &input_line_pointer);
5729 if (r && end <= input_line_pointer)
5731 *nextcharP = *input_line_pointer;
5732 *input_line_pointer = 0;
5733 e->X_op = O_register;
5734 e->X_add_number = r - i386_regtab;
5737 input_line_pointer = end;
5743 md_operand (expressionS *e)
5745 if (*input_line_pointer == REGISTER_PREFIX)
5748 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5752 e->X_op = O_register;
5753 e->X_add_number = r - i386_regtab;
5754 input_line_pointer = end;
5760 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5761 const char *md_shortopts = "kVQ:sqn";
5763 const char *md_shortopts = "qn";
5766 #define OPTION_32 (OPTION_MD_BASE + 0)
5767 #define OPTION_64 (OPTION_MD_BASE + 1)
5768 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5769 #define OPTION_MARCH (OPTION_MD_BASE + 3)
5770 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
5772 struct option md_longopts[] = {
5773 {"32", no_argument, NULL, OPTION_32},
5774 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5775 {"64", no_argument, NULL, OPTION_64},
5777 {"divide", no_argument, NULL, OPTION_DIVIDE},
5778 {"march", required_argument, NULL, OPTION_MARCH},
5779 {"mtune", required_argument, NULL, OPTION_MTUNE},
5780 {NULL, no_argument, NULL, 0}
5782 size_t md_longopts_size = sizeof (md_longopts);
5785 md_parse_option (int c, char *arg)
5792 optimize_align_code = 0;
5799 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5800 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5801 should be emitted or not. FIXME: Not implemented. */
5805 /* -V: SVR4 argument to print version ID. */
5807 print_version_id ();
5810 /* -k: Ignore for FreeBSD compatibility. */
5815 /* -s: On i386 Solaris, this tells the native assembler to use
5816 .stab instead of .stab.excl. We always use .stab anyhow. */
5821 const char **list, **l;
5823 list = bfd_target_list ();
5824 for (l = list; *l != NULL; l++)
5825 if (strcmp (*l, "elf64-x86-64") == 0)
5827 default_arch = "x86_64";
5831 as_fatal (_("No compiled in support for x86_64"));
5838 default_arch = "i386";
5842 #ifdef SVR4_COMMENT_CHARS
5847 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5849 for (s = i386_comment_chars; *s != '\0'; s++)
5853 i386_comment_chars = n;
5860 as_fatal (_("Invalid -march= option: `%s'"), arg);
5861 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5863 if (strcmp (arg, cpu_arch [i].name) == 0)
5865 cpu_arch_isa = cpu_arch[i].type;
5866 cpu_arch_isa_flags = cpu_arch[i].flags;
5867 if (!cpu_arch_tune_set)
5869 cpu_arch_tune = cpu_arch_isa;
5870 cpu_arch_tune_flags = cpu_arch_isa_flags;
5875 if (i >= ARRAY_SIZE (cpu_arch))
5876 as_fatal (_("Invalid -march= option: `%s'"), arg);
5881 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5882 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5884 if (strcmp (arg, cpu_arch [i].name) == 0)
5886 cpu_arch_tune_set = 1;
5887 cpu_arch_tune = cpu_arch [i].type;
5888 cpu_arch_tune_flags = cpu_arch[i].flags;
5892 if (i >= ARRAY_SIZE (cpu_arch))
5893 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5903 md_show_usage (stream)
5906 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5907 fprintf (stream, _("\
5909 -V print assembler version number\n\
5912 fprintf (stream, _("\
5913 -n Do not optimize code alignment\n\
5914 -q quieten some warnings\n"));
5915 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5916 fprintf (stream, _("\
5919 #ifdef SVR4_COMMENT_CHARS
5920 fprintf (stream, _("\
5921 --divide do not treat `/' as a comment character\n"));
5923 fprintf (stream, _("\
5924 --divide ignored\n"));
5926 fprintf (stream, _("\
5927 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5928 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5929 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5933 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5934 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5936 /* Pick the target format to use. */
5939 i386_target_format ()
5941 if (!strcmp (default_arch, "x86_64"))
5943 set_code_flag (CODE_64BIT);
5944 if (cpu_arch_isa_flags == 0)
5945 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5946 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5948 if (cpu_arch_tune_flags == 0)
5949 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5950 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5953 else if (!strcmp (default_arch, "i386"))
5955 set_code_flag (CODE_32BIT);
5956 if (cpu_arch_isa_flags == 0)
5957 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5958 if (cpu_arch_tune_flags == 0)
5959 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5962 as_fatal (_("Unknown architecture"));
5963 switch (OUTPUT_FLAVOR)
5965 #ifdef OBJ_MAYBE_AOUT
5966 case bfd_target_aout_flavour:
5967 return AOUT_TARGET_FORMAT;
5969 #ifdef OBJ_MAYBE_COFF
5970 case bfd_target_coff_flavour:
5973 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5974 case bfd_target_elf_flavour:
5976 if (flag_code == CODE_64BIT)
5979 use_rela_relocations = 1;
5981 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5990 #endif /* OBJ_MAYBE_ more than one */
5992 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5993 void i386_elf_emit_arch_note ()
5995 if (IS_ELF && cpu_arch_name != NULL)
5998 asection *seg = now_seg;
5999 subsegT subseg = now_subseg;
6000 Elf_Internal_Note i_note;
6001 Elf_External_Note e_note;
6002 asection *note_secp;
6005 /* Create the .note section. */
6006 note_secp = subseg_new (".note", 0);
6007 bfd_set_section_flags (stdoutput,
6009 SEC_HAS_CONTENTS | SEC_READONLY);
6011 /* Process the arch string. */
6012 len = strlen (cpu_arch_name);
6014 i_note.namesz = len + 1;
6016 i_note.type = NT_ARCH;
6017 p = frag_more (sizeof (e_note.namesz));
6018 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6019 p = frag_more (sizeof (e_note.descsz));
6020 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6021 p = frag_more (sizeof (e_note.type));
6022 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6023 p = frag_more (len + 1);
6024 strcpy (p, cpu_arch_name);
6026 frag_align (2, 0, 0);
6028 subseg_set (seg, subseg);
6034 md_undefined_symbol (name)
6037 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6038 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6039 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6040 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
6044 if (symbol_find (name))
6045 as_bad (_("GOT already in symbol table"));
6046 GOT_symbol = symbol_new (name, undefined_section,
6047 (valueT) 0, &zero_address_frag);
6054 /* Round up a section size to the appropriate boundary. */
6057 md_section_align (segment, size)
6058 segT segment ATTRIBUTE_UNUSED;
6061 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6062 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6064 /* For a.out, force the section size to be aligned. If we don't do
6065 this, BFD will align it for us, but it will not write out the
6066 final bytes of the section. This may be a bug in BFD, but it is
6067 easier to fix it here since that is how the other a.out targets
6071 align = bfd_get_section_alignment (stdoutput, segment);
6072 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6079 /* On the i386, PC-relative offsets are relative to the start of the
6080 next instruction. That is, the address of the offset, plus its
6081 size, since the offset is always the last part of the insn. */
6084 md_pcrel_from (fixP)
6087 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6094 int ignore ATTRIBUTE_UNUSED;
6098 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6100 obj_elf_section_change_hook ();
6102 temp = get_absolute_expression ();
6103 subseg_set (bss_section, (subsegT) temp);
6104 demand_empty_rest_of_line ();
6110 i386_validate_fix (fixp)
6113 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6115 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6119 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6124 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6126 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
6133 tc_gen_reloc (section, fixp)
6134 asection *section ATTRIBUTE_UNUSED;
6138 bfd_reloc_code_real_type code;
6140 switch (fixp->fx_r_type)
6142 case BFD_RELOC_X86_64_PLT32:
6143 case BFD_RELOC_X86_64_GOT32:
6144 case BFD_RELOC_X86_64_GOTPCREL:
6145 case BFD_RELOC_386_PLT32:
6146 case BFD_RELOC_386_GOT32:
6147 case BFD_RELOC_386_GOTOFF:
6148 case BFD_RELOC_386_GOTPC:
6149 case BFD_RELOC_386_TLS_GD:
6150 case BFD_RELOC_386_TLS_LDM:
6151 case BFD_RELOC_386_TLS_LDO_32:
6152 case BFD_RELOC_386_TLS_IE_32:
6153 case BFD_RELOC_386_TLS_IE:
6154 case BFD_RELOC_386_TLS_GOTIE:
6155 case BFD_RELOC_386_TLS_LE_32:
6156 case BFD_RELOC_386_TLS_LE:
6157 case BFD_RELOC_386_TLS_GOTDESC:
6158 case BFD_RELOC_386_TLS_DESC_CALL:
6159 case BFD_RELOC_X86_64_TLSGD:
6160 case BFD_RELOC_X86_64_TLSLD:
6161 case BFD_RELOC_X86_64_DTPOFF32:
6162 case BFD_RELOC_X86_64_DTPOFF64:
6163 case BFD_RELOC_X86_64_GOTTPOFF:
6164 case BFD_RELOC_X86_64_TPOFF32:
6165 case BFD_RELOC_X86_64_TPOFF64:
6166 case BFD_RELOC_X86_64_GOTOFF64:
6167 case BFD_RELOC_X86_64_GOTPC32:
6168 case BFD_RELOC_X86_64_GOT64:
6169 case BFD_RELOC_X86_64_GOTPCREL64:
6170 case BFD_RELOC_X86_64_GOTPC64:
6171 case BFD_RELOC_X86_64_GOTPLT64:
6172 case BFD_RELOC_X86_64_PLTOFF64:
6173 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6174 case BFD_RELOC_X86_64_TLSDESC_CALL:
6176 case BFD_RELOC_VTABLE_ENTRY:
6177 case BFD_RELOC_VTABLE_INHERIT:
6179 case BFD_RELOC_32_SECREL:
6181 code = fixp->fx_r_type;
6183 case BFD_RELOC_X86_64_32S:
6184 if (!fixp->fx_pcrel)
6186 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6187 code = fixp->fx_r_type;
6193 switch (fixp->fx_size)
6196 as_bad_where (fixp->fx_file, fixp->fx_line,
6197 _("can not do %d byte pc-relative relocation"),
6199 code = BFD_RELOC_32_PCREL;
6201 case 1: code = BFD_RELOC_8_PCREL; break;
6202 case 2: code = BFD_RELOC_16_PCREL; break;
6203 case 4: code = BFD_RELOC_32_PCREL; break;
6205 case 8: code = BFD_RELOC_64_PCREL; break;
6211 switch (fixp->fx_size)
6214 as_bad_where (fixp->fx_file, fixp->fx_line,
6215 _("can not do %d byte relocation"),
6217 code = BFD_RELOC_32;
6219 case 1: code = BFD_RELOC_8; break;
6220 case 2: code = BFD_RELOC_16; break;
6221 case 4: code = BFD_RELOC_32; break;
6223 case 8: code = BFD_RELOC_64; break;
6230 if ((code == BFD_RELOC_32
6231 || code == BFD_RELOC_32_PCREL
6232 || code == BFD_RELOC_X86_64_32S)
6234 && fixp->fx_addsy == GOT_symbol)
6237 code = BFD_RELOC_386_GOTPC;
6239 code = BFD_RELOC_X86_64_GOTPC32;
6241 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6243 && fixp->fx_addsy == GOT_symbol)
6245 code = BFD_RELOC_X86_64_GOTPC64;
6248 rel = (arelent *) xmalloc (sizeof (arelent));
6249 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6250 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6252 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
6254 if (!use_rela_relocations)
6256 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6257 vtable entry to be used in the relocation's section offset. */
6258 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6259 rel->address = fixp->fx_offset;
6263 /* Use the rela in 64bit mode. */
6266 if (!fixp->fx_pcrel)
6267 rel->addend = fixp->fx_offset;
6271 case BFD_RELOC_X86_64_PLT32:
6272 case BFD_RELOC_X86_64_GOT32:
6273 case BFD_RELOC_X86_64_GOTPCREL:
6274 case BFD_RELOC_X86_64_TLSGD:
6275 case BFD_RELOC_X86_64_TLSLD:
6276 case BFD_RELOC_X86_64_GOTTPOFF:
6277 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6278 case BFD_RELOC_X86_64_TLSDESC_CALL:
6279 rel->addend = fixp->fx_offset - fixp->fx_size;
6282 rel->addend = (section->vma
6284 + fixp->fx_addnumber
6285 + md_pcrel_from (fixp));
6290 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6291 if (rel->howto == NULL)
6293 as_bad_where (fixp->fx_file, fixp->fx_line,
6294 _("cannot represent relocation type %s"),
6295 bfd_get_reloc_code_name (code));
6296 /* Set howto to a garbage value so that we can keep going. */
6297 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6298 assert (rel->howto != NULL);
6305 /* Parse operands using Intel syntax. This implements a recursive descent
6306 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6309 FIXME: We do not recognize the full operand grammar defined in the MASM
6310 documentation. In particular, all the structure/union and
6311 high-level macro operands are missing.
6313 Uppercase words are terminals, lower case words are non-terminals.
6314 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6315 bars '|' denote choices. Most grammar productions are implemented in
6316 functions called 'intel_<production>'.
6318 Initial production is 'expr'.
6324 binOp & | AND | \| | OR | ^ | XOR
6326 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6328 constant digits [[ radixOverride ]]
6330 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
6368 => expr expr cmpOp e04
6371 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
6372 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
6374 hexdigit a | b | c | d | e | f
6375 | A | B | C | D | E | F
6381 mulOp * | / | % | MOD | << | SHL | >> | SHR
6385 register specialRegister
6389 segmentRegister CS | DS | ES | FS | GS | SS
6391 specialRegister CR0 | CR2 | CR3 | CR4
6392 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
6393 | TR3 | TR4 | TR5 | TR6 | TR7
6395 We simplify the grammar in obvious places (e.g., register parsing is
6396 done by calling parse_register) and eliminate immediate left recursion
6397 to implement a recursive-descent parser.
6401 expr' cmpOp e04 expr'
6452 /* Parsing structure for the intel syntax parser. Used to implement the
6453 semantic actions for the operand grammar. */
6454 struct intel_parser_s
6456 char *op_string; /* The string being parsed. */
6457 int got_a_float; /* Whether the operand is a float. */
6458 int op_modifier; /* Operand modifier. */
6459 int is_mem; /* 1 if operand is memory reference. */
6460 int in_offset; /* >=1 if parsing operand of offset. */
6461 int in_bracket; /* >=1 if parsing operand in brackets. */
6462 const reg_entry *reg; /* Last register reference found. */
6463 char *disp; /* Displacement string being built. */
6464 char *next_operand; /* Resume point when splitting operands. */
6467 static struct intel_parser_s intel_parser;
6469 /* Token structure for parsing intel syntax. */
6472 int code; /* Token code. */
6473 const reg_entry *reg; /* Register entry for register tokens. */
6474 char *str; /* String representation. */
6477 static struct intel_token cur_token, prev_token;
6479 /* Token codes for the intel parser. Since T_SHORT is already used
6480 by COFF, undefine it first to prevent a warning. */
6499 /* Prototypes for intel parser functions. */
6500 static int intel_match_token PARAMS ((int code));
6501 static void intel_get_token PARAMS ((void));
6502 static void intel_putback_token PARAMS ((void));
6503 static int intel_expr PARAMS ((void));
6504 static int intel_e04 PARAMS ((void));
6505 static int intel_e05 PARAMS ((void));
6506 static int intel_e06 PARAMS ((void));
6507 static int intel_e09 PARAMS ((void));
6508 static int intel_bracket_expr PARAMS ((void));
6509 static int intel_e10 PARAMS ((void));
6510 static int intel_e11 PARAMS ((void));
6513 i386_intel_operand (operand_string, got_a_float)
6514 char *operand_string;
6520 p = intel_parser.op_string = xstrdup (operand_string);
6521 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6525 /* Initialize token holders. */
6526 cur_token.code = prev_token.code = T_NIL;
6527 cur_token.reg = prev_token.reg = NULL;
6528 cur_token.str = prev_token.str = NULL;
6530 /* Initialize parser structure. */
6531 intel_parser.got_a_float = got_a_float;
6532 intel_parser.op_modifier = 0;
6533 intel_parser.is_mem = 0;
6534 intel_parser.in_offset = 0;
6535 intel_parser.in_bracket = 0;
6536 intel_parser.reg = NULL;
6537 intel_parser.disp[0] = '\0';
6538 intel_parser.next_operand = NULL;
6540 /* Read the first token and start the parser. */
6542 ret = intel_expr ();
6547 if (cur_token.code != T_NIL)
6549 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6550 current_templates->start->name, cur_token.str);
6553 /* If we found a memory reference, hand it over to i386_displacement
6554 to fill in the rest of the operand fields. */
6555 else if (intel_parser.is_mem)
6557 if ((i.mem_operands == 1
6558 && (current_templates->start->opcode_modifier & IsString) == 0)
6559 || i.mem_operands == 2)
6561 as_bad (_("too many memory references for '%s'"),
6562 current_templates->start->name);
6567 char *s = intel_parser.disp;
6570 if (!quiet_warnings && intel_parser.is_mem < 0)
6571 /* See the comments in intel_bracket_expr. */
6572 as_warn (_("Treating `%s' as memory reference"), operand_string);
6574 /* Add the displacement expression. */
6576 ret = i386_displacement (s, s + strlen (s));
6579 /* Swap base and index in 16-bit memory operands like
6580 [si+bx]. Since i386_index_check is also used in AT&T
6581 mode we have to do that here. */
6584 && (i.base_reg->reg_type & Reg16)
6585 && (i.index_reg->reg_type & Reg16)
6586 && i.base_reg->reg_num >= 6
6587 && i.index_reg->reg_num < 6)
6589 const reg_entry *base = i.index_reg;
6591 i.index_reg = i.base_reg;
6594 ret = i386_index_check (operand_string);
6599 /* Constant and OFFSET expressions are handled by i386_immediate. */
6600 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6601 || intel_parser.reg == NULL)
6602 ret = i386_immediate (intel_parser.disp);
6604 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6606 if (!ret || !intel_parser.next_operand)
6608 intel_parser.op_string = intel_parser.next_operand;
6609 this_operand = i.operands++;
6613 free (intel_parser.disp);
6618 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6622 expr' cmpOp e04 expr'
6627 /* XXX Implement the comparison operators. */
6628 return intel_e04 ();
6645 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6646 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6648 if (cur_token.code == '+')
6650 else if (cur_token.code == '-')
6651 nregs = NUM_ADDRESS_REGS;
6655 strcat (intel_parser.disp, cur_token.str);
6656 intel_match_token (cur_token.code);
6667 int nregs = ~NUM_ADDRESS_REGS;
6674 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6678 str[0] = cur_token.code;
6680 strcat (intel_parser.disp, str);
6685 intel_match_token (cur_token.code);
6690 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6691 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6702 int nregs = ~NUM_ADDRESS_REGS;
6709 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6713 str[0] = cur_token.code;
6715 strcat (intel_parser.disp, str);
6717 else if (cur_token.code == T_SHL)
6718 strcat (intel_parser.disp, "<<");
6719 else if (cur_token.code == T_SHR)
6720 strcat (intel_parser.disp, ">>");
6724 intel_match_token (cur_token.code);
6729 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6730 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6748 int nregs = ~NUM_ADDRESS_REGS;
6753 /* Don't consume constants here. */
6754 if (cur_token.code == '+' || cur_token.code == '-')
6756 /* Need to look one token ahead - if the next token
6757 is a constant, the current token is its sign. */
6760 intel_match_token (cur_token.code);
6761 next_code = cur_token.code;
6762 intel_putback_token ();
6763 if (next_code == T_CONST)
6767 /* e09 OFFSET e09 */
6768 if (cur_token.code == T_OFFSET)
6771 ++intel_parser.in_offset;
6775 else if (cur_token.code == T_SHORT)
6776 intel_parser.op_modifier |= 1 << T_SHORT;
6779 else if (cur_token.code == '+')
6780 strcat (intel_parser.disp, "+");
6785 else if (cur_token.code == '-' || cur_token.code == '~')
6791 str[0] = cur_token.code;
6793 strcat (intel_parser.disp, str);
6800 intel_match_token (cur_token.code);
6808 /* e09' PTR e10 e09' */
6809 if (cur_token.code == T_PTR)
6813 if (prev_token.code == T_BYTE)
6814 suffix = BYTE_MNEM_SUFFIX;
6816 else if (prev_token.code == T_WORD)
6818 if (current_templates->start->name[0] == 'l'
6819 && current_templates->start->name[2] == 's'
6820 && current_templates->start->name[3] == 0)
6821 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6822 else if (intel_parser.got_a_float == 2) /* "fi..." */
6823 suffix = SHORT_MNEM_SUFFIX;
6825 suffix = WORD_MNEM_SUFFIX;
6828 else if (prev_token.code == T_DWORD)
6830 if (current_templates->start->name[0] == 'l'
6831 && current_templates->start->name[2] == 's'
6832 && current_templates->start->name[3] == 0)
6833 suffix = WORD_MNEM_SUFFIX;
6834 else if (flag_code == CODE_16BIT
6835 && (current_templates->start->opcode_modifier
6836 & (Jump | JumpDword)))
6837 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6838 else if (intel_parser.got_a_float == 1) /* "f..." */
6839 suffix = SHORT_MNEM_SUFFIX;
6841 suffix = LONG_MNEM_SUFFIX;
6844 else if (prev_token.code == T_FWORD)
6846 if (current_templates->start->name[0] == 'l'
6847 && current_templates->start->name[2] == 's'
6848 && current_templates->start->name[3] == 0)
6849 suffix = LONG_MNEM_SUFFIX;
6850 else if (!intel_parser.got_a_float)
6852 if (flag_code == CODE_16BIT)
6853 add_prefix (DATA_PREFIX_OPCODE);
6854 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6857 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6860 else if (prev_token.code == T_QWORD)
6862 if (intel_parser.got_a_float == 1) /* "f..." */
6863 suffix = LONG_MNEM_SUFFIX;
6865 suffix = QWORD_MNEM_SUFFIX;
6868 else if (prev_token.code == T_TBYTE)
6870 if (intel_parser.got_a_float == 1)
6871 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6873 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6876 else if (prev_token.code == T_XMMWORD)
6878 /* XXX ignored for now, but accepted since gcc uses it */
6884 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6888 /* Operands for jump/call using 'ptr' notation denote absolute
6890 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6891 i.types[this_operand] |= JumpAbsolute;
6893 if (current_templates->start->base_opcode == 0x8d /* lea */)
6897 else if (i.suffix != suffix)
6899 as_bad (_("Conflicting operand modifiers"));
6905 /* e09' : e10 e09' */
6906 else if (cur_token.code == ':')
6908 if (prev_token.code != T_REG)
6910 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6911 segment/group identifier (which we don't have), using comma
6912 as the operand separator there is even less consistent, since
6913 there all branches only have a single operand. */
6914 if (this_operand != 0
6915 || intel_parser.in_offset
6916 || intel_parser.in_bracket
6917 || (!(current_templates->start->opcode_modifier
6918 & (Jump|JumpDword|JumpInterSegment))
6919 && !(current_templates->start->operand_types[0]
6921 return intel_match_token (T_NIL);
6922 /* Remember the start of the 2nd operand and terminate 1st
6924 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6925 another expression), but it gets at least the simplest case
6926 (a plain number or symbol on the left side) right. */
6927 intel_parser.next_operand = intel_parser.op_string;
6928 *--intel_parser.op_string = '\0';
6929 return intel_match_token (':');
6937 intel_match_token (cur_token.code);
6943 --intel_parser.in_offset;
6946 if (NUM_ADDRESS_REGS > nregs)
6948 as_bad (_("Invalid operand to `OFFSET'"));
6951 intel_parser.op_modifier |= 1 << T_OFFSET;
6954 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6955 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6960 intel_bracket_expr ()
6962 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6963 const char *start = intel_parser.op_string;
6966 if (i.op[this_operand].regs)
6967 return intel_match_token (T_NIL);
6969 intel_match_token ('[');
6971 /* Mark as a memory operand only if it's not already known to be an
6972 offset expression. If it's an offset expression, we need to keep
6974 if (!intel_parser.in_offset)
6976 ++intel_parser.in_bracket;
6978 /* Operands for jump/call inside brackets denote absolute addresses. */
6979 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6980 i.types[this_operand] |= JumpAbsolute;
6982 /* Unfortunately gas always diverged from MASM in a respect that can't
6983 be easily fixed without risking to break code sequences likely to be
6984 encountered (the testsuite even check for this): MASM doesn't consider
6985 an expression inside brackets unconditionally as a memory reference.
6986 When that is e.g. a constant, an offset expression, or the sum of the
6987 two, this is still taken as a constant load. gas, however, always
6988 treated these as memory references. As a compromise, we'll try to make
6989 offset expressions inside brackets work the MASM way (since that's
6990 less likely to be found in real world code), but make constants alone
6991 continue to work the traditional gas way. In either case, issue a
6993 intel_parser.op_modifier &= ~was_offset;
6996 strcat (intel_parser.disp, "[");
6998 /* Add a '+' to the displacement string if necessary. */
6999 if (*intel_parser.disp != '\0'
7000 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7001 strcat (intel_parser.disp, "+");
7004 && (len = intel_parser.op_string - start - 1,
7005 intel_match_token (']')))
7007 /* Preserve brackets when the operand is an offset expression. */
7008 if (intel_parser.in_offset)
7009 strcat (intel_parser.disp, "]");
7012 --intel_parser.in_bracket;
7013 if (i.base_reg || i.index_reg)
7014 intel_parser.is_mem = 1;
7015 if (!intel_parser.is_mem)
7017 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7018 /* Defer the warning until all of the operand was parsed. */
7019 intel_parser.is_mem = -1;
7020 else if (!quiet_warnings)
7021 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7024 intel_parser.op_modifier |= was_offset;
7041 while (cur_token.code == '[')
7043 if (!intel_bracket_expr ())
7068 switch (cur_token.code)
7072 intel_match_token ('(');
7073 strcat (intel_parser.disp, "(");
7075 if (intel_expr () && intel_match_token (')'))
7077 strcat (intel_parser.disp, ")");
7084 return intel_bracket_expr ();
7089 strcat (intel_parser.disp, cur_token.str);
7090 intel_match_token (cur_token.code);
7092 /* Mark as a memory operand only if it's not already known to be an
7093 offset expression. */
7094 if (!intel_parser.in_offset)
7095 intel_parser.is_mem = 1;
7102 const reg_entry *reg = intel_parser.reg = cur_token.reg;
7104 intel_match_token (T_REG);
7106 /* Check for segment change. */
7107 if (cur_token.code == ':')
7109 if (!(reg->reg_type & (SReg2 | SReg3)))
7111 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7114 else if (i.seg[i.mem_operands])
7115 as_warn (_("Extra segment override ignored"));
7118 if (!intel_parser.in_offset)
7119 intel_parser.is_mem = 1;
7120 switch (reg->reg_num)
7123 i.seg[i.mem_operands] = &es;
7126 i.seg[i.mem_operands] = &cs;
7129 i.seg[i.mem_operands] = &ss;
7132 i.seg[i.mem_operands] = &ds;
7135 i.seg[i.mem_operands] = &fs;
7138 i.seg[i.mem_operands] = &gs;
7144 /* Not a segment register. Check for register scaling. */
7145 else if (cur_token.code == '*')
7147 if (!intel_parser.in_bracket)
7149 as_bad (_("Register scaling only allowed in memory operands"));
7153 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7154 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7155 else if (i.index_reg)
7156 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7158 /* What follows must be a valid scale. */
7159 intel_match_token ('*');
7161 i.types[this_operand] |= BaseIndex;
7163 /* Set the scale after setting the register (otherwise,
7164 i386_scale will complain) */
7165 if (cur_token.code == '+' || cur_token.code == '-')
7167 char *str, sign = cur_token.code;
7168 intel_match_token (cur_token.code);
7169 if (cur_token.code != T_CONST)
7171 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7175 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7176 strcpy (str + 1, cur_token.str);
7178 if (!i386_scale (str))
7182 else if (!i386_scale (cur_token.str))
7184 intel_match_token (cur_token.code);
7187 /* No scaling. If this is a memory operand, the register is either a
7188 base register (first occurrence) or an index register (second
7190 else if (intel_parser.in_bracket)
7195 else if (!i.index_reg)
7199 as_bad (_("Too many register references in memory operand"));
7203 i.types[this_operand] |= BaseIndex;
7206 /* It's neither base nor index. */
7207 else if (!intel_parser.in_offset && !intel_parser.is_mem)
7209 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7210 i.op[this_operand].regs = reg;
7215 as_bad (_("Invalid use of register"));
7219 /* Since registers are not part of the displacement string (except
7220 when we're parsing offset operands), we may need to remove any
7221 preceding '+' from the displacement string. */
7222 if (*intel_parser.disp != '\0'
7223 && !intel_parser.in_offset)
7225 char *s = intel_parser.disp;
7226 s += strlen (s) - 1;
7249 intel_match_token (cur_token.code);
7251 if (cur_token.code == T_PTR)
7254 /* It must have been an identifier. */
7255 intel_putback_token ();
7256 cur_token.code = T_ID;
7262 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
7266 /* The identifier represents a memory reference only if it's not
7267 preceded by an offset modifier and if it's not an equate. */
7268 symbolP = symbol_find(cur_token.str);
7269 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7270 intel_parser.is_mem = 1;
7278 char *save_str, sign = 0;
7280 /* Allow constants that start with `+' or `-'. */
7281 if (cur_token.code == '-' || cur_token.code == '+')
7283 sign = cur_token.code;
7284 intel_match_token (cur_token.code);
7285 if (cur_token.code != T_CONST)
7287 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7293 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7294 strcpy (save_str + !!sign, cur_token.str);
7298 /* Get the next token to check for register scaling. */
7299 intel_match_token (cur_token.code);
7301 /* Check if this constant is a scaling factor for an index register. */
7302 if (cur_token.code == '*')
7304 if (intel_match_token ('*') && cur_token.code == T_REG)
7306 const reg_entry *reg = cur_token.reg;
7308 if (!intel_parser.in_bracket)
7310 as_bad (_("Register scaling only allowed in memory operands"));
7314 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7315 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7316 else if (i.index_reg)
7317 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7319 /* The constant is followed by `* reg', so it must be
7322 i.types[this_operand] |= BaseIndex;
7324 /* Set the scale after setting the register (otherwise,
7325 i386_scale will complain) */
7326 if (!i386_scale (save_str))
7328 intel_match_token (T_REG);
7330 /* Since registers are not part of the displacement
7331 string, we may need to remove any preceding '+' from
7332 the displacement string. */
7333 if (*intel_parser.disp != '\0')
7335 char *s = intel_parser.disp;
7336 s += strlen (s) - 1;
7346 /* The constant was not used for register scaling. Since we have
7347 already consumed the token following `*' we now need to put it
7348 back in the stream. */
7349 intel_putback_token ();
7352 /* Add the constant to the displacement string. */
7353 strcat (intel_parser.disp, save_str);
7360 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7364 /* Match the given token against cur_token. If they match, read the next
7365 token from the operand string. */
7367 intel_match_token (code)
7370 if (cur_token.code == code)
7377 as_bad (_("Unexpected token `%s'"), cur_token.str);
7382 /* Read a new token from intel_parser.op_string and store it in cur_token. */
7387 const reg_entry *reg;
7388 struct intel_token new_token;
7390 new_token.code = T_NIL;
7391 new_token.reg = NULL;
7392 new_token.str = NULL;
7394 /* Free the memory allocated to the previous token and move
7395 cur_token to prev_token. */
7397 free (prev_token.str);
7399 prev_token = cur_token;
7401 /* Skip whitespace. */
7402 while (is_space_char (*intel_parser.op_string))
7403 intel_parser.op_string++;
7405 /* Return an empty token if we find nothing else on the line. */
7406 if (*intel_parser.op_string == '\0')
7408 cur_token = new_token;
7412 /* The new token cannot be larger than the remainder of the operand
7414 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
7415 new_token.str[0] = '\0';
7417 if (strchr ("0123456789", *intel_parser.op_string))
7419 char *p = new_token.str;
7420 char *q = intel_parser.op_string;
7421 new_token.code = T_CONST;
7423 /* Allow any kind of identifier char to encompass floating point and
7424 hexadecimal numbers. */
7425 while (is_identifier_char (*q))
7429 /* Recognize special symbol names [0-9][bf]. */
7430 if (strlen (intel_parser.op_string) == 2
7431 && (intel_parser.op_string[1] == 'b'
7432 || intel_parser.op_string[1] == 'f'))
7433 new_token.code = T_ID;
7436 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
7438 size_t len = end_op - intel_parser.op_string;
7440 new_token.code = T_REG;
7441 new_token.reg = reg;
7443 memcpy (new_token.str, intel_parser.op_string, len);
7444 new_token.str[len] = '\0';
7447 else if (is_identifier_char (*intel_parser.op_string))
7449 char *p = new_token.str;
7450 char *q = intel_parser.op_string;
7452 /* A '.' or '$' followed by an identifier char is an identifier.
7453 Otherwise, it's operator '.' followed by an expression. */
7454 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7456 new_token.code = '.';
7457 new_token.str[0] = '.';
7458 new_token.str[1] = '\0';
7462 while (is_identifier_char (*q) || *q == '@')
7466 if (strcasecmp (new_token.str, "NOT") == 0)
7467 new_token.code = '~';
7469 else if (strcasecmp (new_token.str, "MOD") == 0)
7470 new_token.code = '%';
7472 else if (strcasecmp (new_token.str, "AND") == 0)
7473 new_token.code = '&';
7475 else if (strcasecmp (new_token.str, "OR") == 0)
7476 new_token.code = '|';
7478 else if (strcasecmp (new_token.str, "XOR") == 0)
7479 new_token.code = '^';
7481 else if (strcasecmp (new_token.str, "SHL") == 0)
7482 new_token.code = T_SHL;
7484 else if (strcasecmp (new_token.str, "SHR") == 0)
7485 new_token.code = T_SHR;
7487 else if (strcasecmp (new_token.str, "BYTE") == 0)
7488 new_token.code = T_BYTE;
7490 else if (strcasecmp (new_token.str, "WORD") == 0)
7491 new_token.code = T_WORD;
7493 else if (strcasecmp (new_token.str, "DWORD") == 0)
7494 new_token.code = T_DWORD;
7496 else if (strcasecmp (new_token.str, "FWORD") == 0)
7497 new_token.code = T_FWORD;
7499 else if (strcasecmp (new_token.str, "QWORD") == 0)
7500 new_token.code = T_QWORD;
7502 else if (strcasecmp (new_token.str, "TBYTE") == 0
7503 /* XXX remove (gcc still uses it) */
7504 || strcasecmp (new_token.str, "XWORD") == 0)
7505 new_token.code = T_TBYTE;
7507 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7508 || strcasecmp (new_token.str, "OWORD") == 0)
7509 new_token.code = T_XMMWORD;
7511 else if (strcasecmp (new_token.str, "PTR") == 0)
7512 new_token.code = T_PTR;
7514 else if (strcasecmp (new_token.str, "SHORT") == 0)
7515 new_token.code = T_SHORT;
7517 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7519 new_token.code = T_OFFSET;
7521 /* ??? This is not mentioned in the MASM grammar but gcc
7522 makes use of it with -mintel-syntax. OFFSET may be
7523 followed by FLAT: */
7524 if (strncasecmp (q, " FLAT:", 6) == 0)
7525 strcat (new_token.str, " FLAT:");
7528 /* ??? This is not mentioned in the MASM grammar. */
7529 else if (strcasecmp (new_token.str, "FLAT") == 0)
7531 new_token.code = T_OFFSET;
7533 strcat (new_token.str, ":");
7535 as_bad (_("`:' expected"));
7539 new_token.code = T_ID;
7543 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7545 new_token.code = *intel_parser.op_string;
7546 new_token.str[0] = *intel_parser.op_string;
7547 new_token.str[1] = '\0';
7550 else if (strchr ("<>", *intel_parser.op_string)
7551 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7553 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7554 new_token.str[0] = *intel_parser.op_string;
7555 new_token.str[1] = *intel_parser.op_string;
7556 new_token.str[2] = '\0';
7560 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7562 intel_parser.op_string += strlen (new_token.str);
7563 cur_token = new_token;
7566 /* Put cur_token back into the token stream and make cur_token point to
7569 intel_putback_token ()
7571 if (cur_token.code != T_NIL)
7573 intel_parser.op_string -= strlen (cur_token.str);
7574 free (cur_token.str);
7576 cur_token = prev_token;
7578 /* Forget prev_token. */
7579 prev_token.code = T_NIL;
7580 prev_token.reg = NULL;
7581 prev_token.str = NULL;
7585 tc_x86_regname_to_dw2regnum (char *regname)
7587 unsigned int regnum;
7588 unsigned int regnames_count;
7589 static const char *const regnames_32[] =
7591 "eax", "ecx", "edx", "ebx",
7592 "esp", "ebp", "esi", "edi",
7593 "eip", "eflags", NULL,
7594 "st0", "st1", "st2", "st3",
7595 "st4", "st5", "st6", "st7",
7597 "xmm0", "xmm1", "xmm2", "xmm3",
7598 "xmm4", "xmm5", "xmm6", "xmm7",
7599 "mm0", "mm1", "mm2", "mm3",
7600 "mm4", "mm5", "mm6", "mm7",
7601 "fcw", "fsw", "mxcsr",
7602 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7605 static const char *const regnames_64[] =
7607 "rax", "rdx", "rcx", "rbx",
7608 "rsi", "rdi", "rbp", "rsp",
7609 "r8", "r9", "r10", "r11",
7610 "r12", "r13", "r14", "r15",
7612 "xmm0", "xmm1", "xmm2", "xmm3",
7613 "xmm4", "xmm5", "xmm6", "xmm7",
7614 "xmm8", "xmm9", "xmm10", "xmm11",
7615 "xmm12", "xmm13", "xmm14", "xmm15",
7616 "st0", "st1", "st2", "st3",
7617 "st4", "st5", "st6", "st7",
7618 "mm0", "mm1", "mm2", "mm3",
7619 "mm4", "mm5", "mm6", "mm7",
7621 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7622 "fs.base", "gs.base", NULL, NULL,
7624 "mxcsr", "fcw", "fsw"
7626 const char *const *regnames;
7628 if (flag_code == CODE_64BIT)
7630 regnames = regnames_64;
7631 regnames_count = ARRAY_SIZE (regnames_64);
7635 regnames = regnames_32;
7636 regnames_count = ARRAY_SIZE (regnames_32);
7639 for (regnum = 0; regnum < regnames_count; regnum++)
7640 if (regnames[regnum] != NULL
7641 && strcmp (regname, regnames[regnum]) == 0)
7648 tc_x86_frame_initial_instructions (void)
7650 static unsigned int sp_regno;
7653 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7656 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7657 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7661 i386_elf_section_type (const char *str, size_t len)
7663 if (flag_code == CODE_64BIT
7664 && len == sizeof ("unwind") - 1
7665 && strncmp (str, "unwind", 6) == 0)
7666 return SHT_X86_64_UNWIND;
7673 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7677 expr.X_op = O_secrel;
7678 expr.X_add_symbol = symbol;
7679 expr.X_add_number = 0;
7680 emit_expr (&expr, size);
7684 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7685 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7688 x86_64_section_letter (int letter, char **ptr_msg)
7690 if (flag_code == CODE_64BIT)
7693 return SHF_X86_64_LARGE;
7695 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7698 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7703 x86_64_section_word (char *str, size_t len)
7705 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7706 return SHF_X86_64_LARGE;
7712 handle_large_common (int small ATTRIBUTE_UNUSED)
7714 if (flag_code != CODE_64BIT)
7716 s_comm_internal (0, elf_common_parse);
7717 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7721 static segT lbss_section;
7722 asection *saved_com_section_ptr = elf_com_section_ptr;
7723 asection *saved_bss_section = bss_section;
7725 if (lbss_section == NULL)
7727 flagword applicable;
7729 subsegT subseg = now_subseg;
7731 /* The .lbss section is for local .largecomm symbols. */
7732 lbss_section = subseg_new (".lbss", 0);
7733 applicable = bfd_applicable_section_flags (stdoutput);
7734 bfd_set_section_flags (stdoutput, lbss_section,
7735 applicable & SEC_ALLOC);
7736 seg_info (lbss_section)->bss = 1;
7738 subseg_set (seg, subseg);
7741 elf_com_section_ptr = &_bfd_elf_large_com_section;
7742 bss_section = lbss_section;
7744 s_comm_internal (0, elf_common_parse);
7746 elf_com_section_ptr = saved_com_section_ptr;
7747 bss_section = saved_bss_section;
7750 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */