1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void optimize_imm PARAMS ((void));
93 static void optimize_disp PARAMS ((void));
94 static int match_template PARAMS ((void));
95 static int check_string PARAMS ((void));
96 static int process_suffix PARAMS ((void));
97 static int check_byte_reg PARAMS ((void));
98 static int check_long_reg PARAMS ((void));
99 static int check_qword_reg PARAMS ((void));
100 static int check_word_reg PARAMS ((void));
101 static int finalize_imm PARAMS ((void));
102 static int process_operands PARAMS ((void));
103 static const seg_entry *build_modrm_byte PARAMS ((void));
104 static void output_insn PARAMS ((void));
105 static void output_branch PARAMS ((void));
106 static void output_jump PARAMS ((void));
107 static void output_interseg_jump PARAMS ((void));
108 static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110 static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
113 static void s_bss PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED);
119 static const char *default_arch = DEFAULT_ARCH;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry *regs;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types[MAX_OPERANDS];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op[MAX_OPERANDS];
156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry *seg[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_LINUX) \
202 && !defined (TE_NETWARE) \
203 && !defined (TE_FreeBSD) \
204 && !defined (TE_NetBSD)))
205 /* This array holds the chars that always start a comment. If the
206 pre-processor is disabled, these aren't very useful. The option
207 --divide will remove '/' from this list. */
208 const char *i386_comment_chars = "#/";
209 #define SVR4_COMMENT_CHARS 1
210 #define PREFIX_SEPARATOR '\\'
213 const char *i386_comment_chars = "#";
214 #define PREFIX_SEPARATOR '/'
217 /* This array holds the chars that only start a comment at the beginning of
218 a line. If the line seems to have the form '# 123 filename'
219 .line and .file directives will appear in the pre-processed output.
220 Note that input_file.c hand checks for '#' at the beginning of the
221 first line of the input file. This is because the compiler outputs
222 #NO_APP at the beginning of its output.
223 Also note that comments started like this one will always work if
224 '/' isn't otherwise defined. */
225 const char line_comment_chars[] = "#/";
227 const char line_separator_chars[] = ";";
229 /* Chars that can be used to separate mant from exp in floating point
231 const char EXP_CHARS[] = "eE";
233 /* Chars that mean this number is a floating point constant
236 const char FLT_CHARS[] = "fFdDxX";
238 /* Tables for lexical analysis. */
239 static char mnemonic_chars[256];
240 static char register_chars[256];
241 static char operand_chars[256];
242 static char identifier_chars[256];
243 static char digit_chars[256];
245 /* Lexical macros. */
246 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
247 #define is_operand_char(x) (operand_chars[(unsigned char) x])
248 #define is_register_char(x) (register_chars[(unsigned char) x])
249 #define is_space_char(x) ((x) == ' ')
250 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
251 #define is_digit_char(x) (digit_chars[(unsigned char) x])
253 /* All non-digit non-letter characters that may occur in an operand. */
254 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256 /* md_assemble() always leaves the strings it's passed unaltered. To
257 effect this we maintain a stack of saved characters that we've smashed
258 with '\0's (indicating end of strings for various sub-fields of the
259 assembler instruction). */
260 static char save_stack[32];
261 static char *save_stack_p;
262 #define END_STRING_AND_SAVE(s) \
263 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
264 #define RESTORE_END_STRING(s) \
265 do { *(s) = *--save_stack_p; } while (0)
267 /* The instruction we're assembling. */
270 /* Possible templates for current insn. */
271 static const templates *current_templates;
273 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
274 static expressionS disp_expressions[2], im_expressions[2];
276 /* Current operand we are working on. */
277 static int this_operand;
279 /* We support four different modes. FLAG_CODE variable is used to distinguish
286 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
288 static enum flag_code flag_code;
289 static unsigned int object_64bit;
290 static int use_rela_relocations = 0;
292 /* The names used to print error messages. */
293 static const char *flag_code_names[] =
300 /* 1 for intel syntax,
302 static int intel_syntax = 0;
304 /* 1 if register prefix % not required. */
305 static int allow_naked_reg = 0;
307 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
308 leave, push, and pop instructions so that gcc has the same stack
309 frame as in 32 bit mode. */
310 static char stackop_size = '\0';
312 /* Non-zero to optimize code alignment. */
313 int optimize_align_code = 1;
315 /* Non-zero to quieten some warnings. */
316 static int quiet_warnings = 0;
319 static const char *cpu_arch_name = NULL;
320 static const char *cpu_sub_arch_name = NULL;
322 /* CPU feature flags. */
323 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
325 /* If set, conditional jumps are not automatically promoted to handle
326 larger than a byte offset. */
327 static unsigned int no_cond_jump_promotion = 0;
329 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
330 static symbolS *GOT_symbol;
332 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
333 unsigned int x86_dwarf2_return_column;
335 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
336 int x86_cie_data_alignment;
338 /* Interface to relax_segment.
339 There are 3 major relax states for 386 jump insns because the
340 different types of jumps add different sizes to frags when we're
341 figuring out what sort of jump to choose to reach a given label. */
344 #define UNCOND_JUMP 0
346 #define COND_JUMP86 2
351 #define SMALL16 (SMALL | CODE16)
353 #define BIG16 (BIG | CODE16)
357 #define INLINE __inline__
363 #define ENCODE_RELAX_STATE(type, size) \
364 ((relax_substateT) (((type) << 2) | (size)))
365 #define TYPE_FROM_RELAX_STATE(s) \
367 #define DISP_SIZE_FROM_RELAX_STATE(s) \
368 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
370 /* This table is used by relax_frag to promote short jumps to long
371 ones where necessary. SMALL (short) jumps may be promoted to BIG
372 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
373 don't allow a short jump in a 32 bit code segment to be promoted to
374 a 16 bit offset jump because it's slower (requires data size
375 prefix), and doesn't work, unless the destination is in the bottom
376 64k of the code segment (The top 16 bits of eip are zeroed). */
378 const relax_typeS md_relax_table[] =
381 1) most positive reach of this state,
382 2) most negative reach of this state,
383 3) how many bytes this mode will have in the variable part of the frag
384 4) which index into the table to try if we can't fit into this one. */
386 /* UNCOND_JUMP states. */
387 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
389 /* dword jmp adds 4 bytes to frag:
390 0 extra opcode bytes, 4 displacement bytes. */
392 /* word jmp adds 2 byte2 to frag:
393 0 extra opcode bytes, 2 displacement bytes. */
396 /* COND_JUMP states. */
397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
399 /* dword conditionals adds 5 bytes to frag:
400 1 extra opcode byte, 4 displacement bytes. */
402 /* word conditionals add 3 bytes to frag:
403 1 extra opcode byte, 2 displacement bytes. */
406 /* COND_JUMP86 states. */
407 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
409 /* dword conditionals adds 5 bytes to frag:
410 1 extra opcode byte, 4 displacement bytes. */
412 /* word conditionals add 4 bytes to frag:
413 1 displacement byte and a 3 byte long branch insn. */
417 static const arch_entry cpu_arch[] = {
419 {"i186", Cpu086|Cpu186 },
420 {"i286", Cpu086|Cpu186|Cpu286 },
421 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
422 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
423 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
424 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
425 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
426 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
427 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
428 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
429 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
430 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
431 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
432 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
433 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
434 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
435 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
437 {".sse", CpuMMX|CpuMMX2|CpuSSE },
438 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
439 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
440 {".3dnow", CpuMMX|Cpu3dnow },
441 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
442 {".padlock", CpuPadLock },
443 {".pacifica", CpuSVME },
448 const pseudo_typeS md_pseudo_table[] =
450 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
451 {"align", s_align_bytes, 0},
453 {"align", s_align_ptwo, 0},
455 {"arch", set_cpu_arch, 0},
459 {"ffloat", float_cons, 'f'},
460 {"dfloat", float_cons, 'd'},
461 {"tfloat", float_cons, 'x'},
463 {"slong", signed_cons, 4},
464 {"noopt", s_ignore, 0},
465 {"optim", s_ignore, 0},
466 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
467 {"code16", set_code_flag, CODE_16BIT},
468 {"code32", set_code_flag, CODE_32BIT},
469 {"code64", set_code_flag, CODE_64BIT},
470 {"intel_syntax", set_intel_syntax, 1},
471 {"att_syntax", set_intel_syntax, 0},
472 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
473 {"largecomm", handle_large_common, 0},
475 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
476 {"loc", dwarf2_directive_loc, 0},
477 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
480 {"secrel32", pe_directive_secrel, 0},
485 /* For interface with expression (). */
486 extern char *input_line_pointer;
488 /* Hash table for instruction mnemonic lookup. */
489 static struct hash_control *op_hash;
491 /* Hash table for register lookup. */
492 static struct hash_control *reg_hash;
495 i386_align_code (fragP, count)
499 /* Various efficient no-op patterns for aligning code labels.
500 Note: Don't try to assemble the instructions in the comments.
501 0L and 0w are not legal. */
502 static const char f32_1[] =
504 static const char f32_2[] =
505 {0x89,0xf6}; /* movl %esi,%esi */
506 static const char f32_3[] =
507 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
508 static const char f32_4[] =
509 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
510 static const char f32_5[] =
512 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
513 static const char f32_6[] =
514 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
515 static const char f32_7[] =
516 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
517 static const char f32_8[] =
519 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
520 static const char f32_9[] =
521 {0x89,0xf6, /* movl %esi,%esi */
522 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
523 static const char f32_10[] =
524 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_11[] =
527 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_12[] =
530 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
531 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
532 static const char f32_13[] =
533 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
534 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
535 static const char f32_14[] =
536 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
537 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
538 static const char f32_15[] =
539 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
540 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
541 static const char f16_3[] =
542 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
543 static const char f16_4[] =
544 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
545 static const char f16_5[] =
547 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
548 static const char f16_6[] =
549 {0x89,0xf6, /* mov %si,%si */
550 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
551 static const char f16_7[] =
552 {0x8d,0x74,0x00, /* lea 0(%si),%si */
553 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
554 static const char f16_8[] =
555 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
556 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
557 static const char *const f32_patt[] = {
558 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
559 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
561 static const char *const f16_patt[] = {
562 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
563 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
566 if (count <= 0 || count > 15)
569 /* The recommended way to pad 64bit code is to use NOPs preceded by
570 maximally four 0x66 prefixes. Balance the size of nops. */
571 if (flag_code == CODE_64BIT)
574 int nnops = (count + 3) / 4;
575 int len = count / nnops;
576 int remains = count - nnops * len;
579 for (i = 0; i < remains; i++)
581 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
582 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
585 for (; i < nnops; i++)
587 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
588 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
593 if (flag_code == CODE_16BIT)
595 memcpy (fragP->fr_literal + fragP->fr_fix,
596 f16_patt[count - 1], count);
598 /* Adjust jump offset. */
599 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
602 memcpy (fragP->fr_literal + fragP->fr_fix,
603 f32_patt[count - 1], count);
604 fragP->fr_var = count;
607 static INLINE unsigned int
608 mode_from_disp_size (t)
611 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
615 fits_in_signed_byte (num)
618 return (num >= -128) && (num <= 127);
622 fits_in_unsigned_byte (num)
625 return (num & 0xff) == num;
629 fits_in_unsigned_word (num)
632 return (num & 0xffff) == num;
636 fits_in_signed_word (num)
639 return (-32768 <= num) && (num <= 32767);
642 fits_in_signed_long (num)
643 offsetT num ATTRIBUTE_UNUSED;
648 return (!(((offsetT) -1 << 31) & num)
649 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
651 } /* fits_in_signed_long() */
653 fits_in_unsigned_long (num)
654 offsetT num ATTRIBUTE_UNUSED;
659 return (num & (((offsetT) 2 << 31) - 1)) == num;
661 } /* fits_in_unsigned_long() */
664 smallest_imm_type (num)
667 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
669 /* This code is disabled on the 486 because all the Imm1 forms
670 in the opcode table are slower on the i486. They're the
671 versions with the implicitly specified single-position
672 displacement, which has another syntax if you really want to
675 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
677 return (fits_in_signed_byte (num)
678 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
679 : fits_in_unsigned_byte (num)
680 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
681 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
682 ? (Imm16 | Imm32 | Imm32S | Imm64)
683 : fits_in_signed_long (num)
684 ? (Imm32 | Imm32S | Imm64)
685 : fits_in_unsigned_long (num)
691 offset_in_range (val, size)
699 case 1: mask = ((addressT) 1 << 8) - 1; break;
700 case 2: mask = ((addressT) 1 << 16) - 1; break;
701 case 4: mask = ((addressT) 2 << 31) - 1; break;
703 case 8: mask = ((addressT) 2 << 63) - 1; break;
708 /* If BFD64, sign extend val. */
709 if (!use_rela_relocations)
710 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
711 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
713 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
715 char buf1[40], buf2[40];
717 sprint_value (buf1, val);
718 sprint_value (buf2, val & mask);
719 as_warn (_("%s shortened to %s"), buf1, buf2);
724 /* Returns 0 if attempting to add a prefix where one from the same
725 class already exists, 1 if non rep/repne added, 2 if rep/repne
734 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
735 && flag_code == CODE_64BIT)
743 case CS_PREFIX_OPCODE:
744 case DS_PREFIX_OPCODE:
745 case ES_PREFIX_OPCODE:
746 case FS_PREFIX_OPCODE:
747 case GS_PREFIX_OPCODE:
748 case SS_PREFIX_OPCODE:
752 case REPNE_PREFIX_OPCODE:
753 case REPE_PREFIX_OPCODE:
756 case LOCK_PREFIX_OPCODE:
764 case ADDR_PREFIX_OPCODE:
768 case DATA_PREFIX_OPCODE:
773 if (i.prefix[q] != 0)
775 as_bad (_("same type of prefix used twice"));
780 i.prefix[q] = prefix;
785 set_code_flag (value)
789 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
790 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
791 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
793 as_bad (_("64bit mode not supported on this CPU."));
795 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
797 as_bad (_("32bit mode not supported on this CPU."));
803 set_16bit_gcc_code_flag (new_code_flag)
806 flag_code = new_code_flag;
807 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
808 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
809 stackop_size = LONG_MNEM_SUFFIX;
813 set_intel_syntax (syntax_flag)
816 /* Find out if register prefixing is specified. */
817 int ask_naked_reg = 0;
820 if (!is_end_of_line[(unsigned char) *input_line_pointer])
822 char *string = input_line_pointer;
823 int e = get_symbol_end ();
825 if (strcmp (string, "prefix") == 0)
827 else if (strcmp (string, "noprefix") == 0)
830 as_bad (_("bad argument to syntax directive."));
831 *input_line_pointer = e;
833 demand_empty_rest_of_line ();
835 intel_syntax = syntax_flag;
837 if (ask_naked_reg == 0)
838 allow_naked_reg = (intel_syntax
839 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
841 allow_naked_reg = (ask_naked_reg < 0);
843 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
844 identifier_chars['$'] = intel_syntax ? '$' : 0;
849 int dummy ATTRIBUTE_UNUSED;
853 if (!is_end_of_line[(unsigned char) *input_line_pointer])
855 char *string = input_line_pointer;
856 int e = get_symbol_end ();
859 for (i = 0; cpu_arch[i].name; i++)
861 if (strcmp (string, cpu_arch[i].name) == 0)
865 cpu_arch_name = cpu_arch[i].name;
866 cpu_sub_arch_name = NULL;
867 cpu_arch_flags = (cpu_arch[i].flags
868 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
871 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
873 cpu_sub_arch_name = cpu_arch[i].name;
874 cpu_arch_flags |= cpu_arch[i].flags;
876 *input_line_pointer = e;
877 demand_empty_rest_of_line ();
881 if (!cpu_arch[i].name)
882 as_bad (_("no such architecture: `%s'"), string);
884 *input_line_pointer = e;
887 as_bad (_("missing cpu architecture"));
889 no_cond_jump_promotion = 0;
890 if (*input_line_pointer == ','
891 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
893 char *string = ++input_line_pointer;
894 int e = get_symbol_end ();
896 if (strcmp (string, "nojumps") == 0)
897 no_cond_jump_promotion = 1;
898 else if (strcmp (string, "jumps") == 0)
901 as_bad (_("no such architecture modifier: `%s'"), string);
903 *input_line_pointer = e;
906 demand_empty_rest_of_line ();
912 if (!strcmp (default_arch, "x86_64"))
913 return bfd_mach_x86_64;
914 else if (!strcmp (default_arch, "i386"))
915 return bfd_mach_i386_i386;
917 as_fatal (_("Unknown architecture"));
923 const char *hash_err;
925 /* Initialize op_hash hash table. */
926 op_hash = hash_new ();
929 const template *optab;
930 templates *core_optab;
932 /* Setup for loop. */
934 core_optab = (templates *) xmalloc (sizeof (templates));
935 core_optab->start = optab;
940 if (optab->name == NULL
941 || strcmp (optab->name, (optab - 1)->name) != 0)
943 /* different name --> ship out current template list;
944 add to hash table; & begin anew. */
945 core_optab->end = optab;
946 hash_err = hash_insert (op_hash,
951 as_fatal (_("Internal Error: Can't hash %s: %s"),
955 if (optab->name == NULL)
957 core_optab = (templates *) xmalloc (sizeof (templates));
958 core_optab->start = optab;
963 /* Initialize reg_hash hash table. */
964 reg_hash = hash_new ();
966 const reg_entry *regtab;
968 for (regtab = i386_regtab;
969 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
972 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
974 as_fatal (_("Internal Error: Can't hash %s: %s"),
980 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
985 for (c = 0; c < 256; c++)
990 mnemonic_chars[c] = c;
991 register_chars[c] = c;
992 operand_chars[c] = c;
994 else if (ISLOWER (c))
996 mnemonic_chars[c] = c;
997 register_chars[c] = c;
998 operand_chars[c] = c;
1000 else if (ISUPPER (c))
1002 mnemonic_chars[c] = TOLOWER (c);
1003 register_chars[c] = mnemonic_chars[c];
1004 operand_chars[c] = c;
1007 if (ISALPHA (c) || ISDIGIT (c))
1008 identifier_chars[c] = c;
1011 identifier_chars[c] = c;
1012 operand_chars[c] = c;
1017 identifier_chars['@'] = '@';
1020 identifier_chars['?'] = '?';
1021 operand_chars['?'] = '?';
1023 digit_chars['-'] = '-';
1024 mnemonic_chars['-'] = '-';
1025 identifier_chars['_'] = '_';
1026 identifier_chars['.'] = '.';
1028 for (p = operand_special_chars; *p != '\0'; p++)
1029 operand_chars[(unsigned char) *p] = *p;
1032 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1035 record_alignment (text_section, 2);
1036 record_alignment (data_section, 2);
1037 record_alignment (bss_section, 2);
1041 if (flag_code == CODE_64BIT)
1043 x86_dwarf2_return_column = 16;
1044 x86_cie_data_alignment = -8;
1048 x86_dwarf2_return_column = 8;
1049 x86_cie_data_alignment = -4;
1054 i386_print_statistics (file)
1057 hash_print_statistics (file, "i386 opcode", op_hash);
1058 hash_print_statistics (file, "i386 register", reg_hash);
1063 /* Debugging routines for md_assemble. */
1064 static void pi PARAMS ((char *, i386_insn *));
1065 static void pte PARAMS ((template *));
1066 static void pt PARAMS ((unsigned int));
1067 static void pe PARAMS ((expressionS *));
1068 static void ps PARAMS ((symbolS *));
1077 fprintf (stdout, "%s: template ", line);
1079 fprintf (stdout, " address: base %s index %s scale %x\n",
1080 x->base_reg ? x->base_reg->reg_name : "none",
1081 x->index_reg ? x->index_reg->reg_name : "none",
1082 x->log2_scale_factor);
1083 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1084 x->rm.mode, x->rm.reg, x->rm.regmem);
1085 fprintf (stdout, " sib: base %x index %x scale %x\n",
1086 x->sib.base, x->sib.index, x->sib.scale);
1087 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1088 (x->rex & REX_MODE64) != 0,
1089 (x->rex & REX_EXTX) != 0,
1090 (x->rex & REX_EXTY) != 0,
1091 (x->rex & REX_EXTZ) != 0);
1092 for (i = 0; i < x->operands; i++)
1094 fprintf (stdout, " #%d: ", i + 1);
1096 fprintf (stdout, "\n");
1098 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1099 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1100 if (x->types[i] & Imm)
1102 if (x->types[i] & Disp)
1103 pe (x->op[i].disps);
1112 fprintf (stdout, " %d operands ", t->operands);
1113 fprintf (stdout, "opcode %x ", t->base_opcode);
1114 if (t->extension_opcode != None)
1115 fprintf (stdout, "ext %x ", t->extension_opcode);
1116 if (t->opcode_modifier & D)
1117 fprintf (stdout, "D");
1118 if (t->opcode_modifier & W)
1119 fprintf (stdout, "W");
1120 fprintf (stdout, "\n");
1121 for (i = 0; i < t->operands; i++)
1123 fprintf (stdout, " #%d type ", i + 1);
1124 pt (t->operand_types[i]);
1125 fprintf (stdout, "\n");
1133 fprintf (stdout, " operation %d\n", e->X_op);
1134 fprintf (stdout, " add_number %ld (%lx)\n",
1135 (long) e->X_add_number, (long) e->X_add_number);
1136 if (e->X_add_symbol)
1138 fprintf (stdout, " add_symbol ");
1139 ps (e->X_add_symbol);
1140 fprintf (stdout, "\n");
1144 fprintf (stdout, " op_symbol ");
1145 ps (e->X_op_symbol);
1146 fprintf (stdout, "\n");
1154 fprintf (stdout, "%s type %s%s",
1156 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1157 segment_name (S_GET_SEGMENT (s)));
1166 static const type_names[] =
1179 { BaseIndex, "BaseIndex" },
1183 { Disp32S, "d32s" },
1185 { InOutPortReg, "InOutPortReg" },
1186 { ShiftCount, "ShiftCount" },
1187 { Control, "control reg" },
1188 { Test, "test reg" },
1189 { Debug, "debug reg" },
1190 { FloatReg, "FReg" },
1191 { FloatAcc, "FAcc" },
1195 { JumpAbsolute, "Jump Absolute" },
1206 const struct type_name *ty;
1208 for (ty = type_names; ty->mask; ty++)
1210 fprintf (stdout, "%s, ", ty->tname);
1214 #endif /* DEBUG386 */
1216 static bfd_reloc_code_real_type
1217 reloc (unsigned int size,
1220 bfd_reloc_code_real_type other)
1222 if (other != NO_RELOC)
1224 reloc_howto_type *reloc;
1229 case BFD_RELOC_X86_64_TPOFF32:
1230 other = BFD_RELOC_X86_64_TPOFF64;
1232 case BFD_RELOC_X86_64_DTPOFF32:
1233 other = BFD_RELOC_X86_64_DTPOFF64;
1239 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1240 if (size == 4 && flag_code != CODE_64BIT)
1243 reloc = bfd_reloc_type_lookup (stdoutput, other);
1245 as_bad (_("unknown relocation (%u)"), other);
1246 else if (size != bfd_get_reloc_size (reloc))
1247 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1248 bfd_get_reloc_size (reloc),
1250 else if (pcrel && !reloc->pc_relative)
1251 as_bad (_("non-pc-relative relocation for pc-relative field"));
1252 else if ((reloc->complain_on_overflow == complain_overflow_signed
1254 || (reloc->complain_on_overflow == complain_overflow_unsigned
1256 as_bad (_("relocated field and relocation type differ in signedness"));
1265 as_bad (_("there are no unsigned pc-relative relocations"));
1268 case 1: return BFD_RELOC_8_PCREL;
1269 case 2: return BFD_RELOC_16_PCREL;
1270 case 4: return BFD_RELOC_32_PCREL;
1271 case 8: return BFD_RELOC_64_PCREL;
1273 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1280 case 4: return BFD_RELOC_X86_64_32S;
1285 case 1: return BFD_RELOC_8;
1286 case 2: return BFD_RELOC_16;
1287 case 4: return BFD_RELOC_32;
1288 case 8: return BFD_RELOC_64;
1290 as_bad (_("cannot do %s %u byte relocation"),
1291 sign > 0 ? "signed" : "unsigned", size);
1295 return BFD_RELOC_NONE;
1298 /* Here we decide which fixups can be adjusted to make them relative to
1299 the beginning of the section instead of the symbol. Basically we need
1300 to make sure that the dynamic relocations are done correctly, so in
1301 some cases we force the original symbol to be used. */
1304 tc_i386_fix_adjustable (fixP)
1305 fixS *fixP ATTRIBUTE_UNUSED;
1307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1311 /* Don't adjust pc-relative references to merge sections in 64-bit
1313 if (use_rela_relocations
1314 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1318 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1319 and changed later by validate_fix. */
1320 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1321 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1324 /* adjust_reloc_syms doesn't know about the GOT. */
1325 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1326 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1327 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1328 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1333 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1334 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1335 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1336 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1337 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1339 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1340 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1342 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1343 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1344 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1345 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1346 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1347 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1348 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1354 static int intel_float_operand PARAMS ((const char *mnemonic));
1357 intel_float_operand (mnemonic)
1358 const char *mnemonic;
1360 /* Note that the value returned is meaningful only for opcodes with (memory)
1361 operands, hence the code here is free to improperly handle opcodes that
1362 have no operands (for better performance and smaller code). */
1364 if (mnemonic[0] != 'f')
1365 return 0; /* non-math */
1367 switch (mnemonic[1])
1369 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1370 the fs segment override prefix not currently handled because no
1371 call path can make opcodes without operands get here */
1373 return 2 /* integer op */;
1375 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1376 return 3; /* fldcw/fldenv */
1379 if (mnemonic[2] != 'o' /* fnop */)
1380 return 3; /* non-waiting control op */
1383 if (mnemonic[2] == 's')
1384 return 3; /* frstor/frstpm */
1387 if (mnemonic[2] == 'a')
1388 return 3; /* fsave */
1389 if (mnemonic[2] == 't')
1391 switch (mnemonic[3])
1393 case 'c': /* fstcw */
1394 case 'd': /* fstdw */
1395 case 'e': /* fstenv */
1396 case 's': /* fsts[gw] */
1402 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1403 return 0; /* fxsave/fxrstor are not really math ops */
1410 /* This is the guts of the machine-dependent assembler. LINE points to a
1411 machine dependent instruction. This function is supposed to emit
1412 the frags/bytes it assembles to. */
1419 char mnemonic[MAX_MNEM_SIZE];
1421 /* Initialize globals. */
1422 memset (&i, '\0', sizeof (i));
1423 for (j = 0; j < MAX_OPERANDS; j++)
1424 i.reloc[j] = NO_RELOC;
1425 memset (disp_expressions, '\0', sizeof (disp_expressions));
1426 memset (im_expressions, '\0', sizeof (im_expressions));
1427 save_stack_p = save_stack;
1429 /* First parse an instruction mnemonic & call i386_operand for the operands.
1430 We assume that the scrubber has arranged it so that line[0] is the valid
1431 start of a (possibly prefixed) mnemonic. */
1433 line = parse_insn (line, mnemonic);
1437 line = parse_operands (line, mnemonic);
1441 /* Now we've parsed the mnemonic into a set of templates, and have the
1442 operands at hand. */
1444 /* All intel opcodes have reversed operands except for "bound" and
1445 "enter". We also don't reverse intersegment "jmp" and "call"
1446 instructions with 2 immediate operands so that the immediate segment
1447 precedes the offset, as it does when in AT&T mode. "enter" and the
1448 intersegment "jmp" and "call" instructions are the only ones that
1449 have two immediate operands. */
1450 if (intel_syntax && i.operands > 1
1451 && (strcmp (mnemonic, "bound") != 0)
1452 && (strcmp (mnemonic, "invlpga") != 0)
1453 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1459 /* Don't optimize displacement for movabs since it only takes 64bit
1462 && (flag_code != CODE_64BIT
1463 || strcmp (mnemonic, "movabs") != 0))
1466 /* Next, we find a template that matches the given insn,
1467 making sure the overlap of the given operands types is consistent
1468 with the template operand types. */
1470 if (!match_template ())
1475 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1477 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1478 i.tm.base_opcode ^= FloatR;
1480 /* Zap movzx and movsx suffix. The suffix may have been set from
1481 "word ptr" or "byte ptr" on the source operand, but we'll use
1482 the suffix later to choose the destination register. */
1483 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1485 if (i.reg_operands < 2
1487 && (~i.tm.opcode_modifier
1494 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1500 if (i.tm.opcode_modifier & FWait)
1501 if (!add_prefix (FWAIT_OPCODE))
1504 /* Check string instruction segment overrides. */
1505 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1507 if (!check_string ())
1511 if (!process_suffix ())
1514 /* Make still unresolved immediate matches conform to size of immediate
1515 given in i.suffix. */
1516 if (!finalize_imm ())
1519 if (i.types[0] & Imm1)
1520 i.imm_operands = 0; /* kludge for shift insns. */
1521 if (i.types[0] & ImplicitRegister)
1523 if (i.types[1] & ImplicitRegister)
1525 if (i.types[2] & ImplicitRegister)
1528 if (i.tm.opcode_modifier & ImmExt)
1532 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1534 /* These Intel Prescott New Instructions have the fixed
1535 operands with an opcode suffix which is coded in the same
1536 place as an 8-bit immediate field would be. Here we check
1537 those operands and remove them afterwards. */
1540 for (x = 0; x < i.operands; x++)
1541 if (i.op[x].regs->reg_num != x)
1542 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1543 i.op[x].regs->reg_name, x + 1, i.tm.name);
1547 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1548 opcode suffix which is coded in the same place as an 8-bit
1549 immediate field would be. Here we fake an 8-bit immediate
1550 operand from the opcode suffix stored in tm.extension_opcode. */
1552 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1554 exp = &im_expressions[i.imm_operands++];
1555 i.op[i.operands].imms = exp;
1556 i.types[i.operands++] = Imm8;
1557 exp->X_op = O_constant;
1558 exp->X_add_number = i.tm.extension_opcode;
1559 i.tm.extension_opcode = None;
1562 /* For insns with operands there are more diddles to do to the opcode. */
1565 if (!process_operands ())
1568 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1570 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1571 as_warn (_("translating to `%sp'"), i.tm.name);
1574 /* Handle conversion of 'int $3' --> special int3 insn. */
1575 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1577 i.tm.base_opcode = INT3_OPCODE;
1581 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1582 && i.op[0].disps->X_op == O_constant)
1584 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1585 the absolute address given by the constant. Since ix86 jumps and
1586 calls are pc relative, we need to generate a reloc. */
1587 i.op[0].disps->X_add_symbol = &abs_symbol;
1588 i.op[0].disps->X_op = O_symbol;
1591 if ((i.tm.opcode_modifier & Rex64) != 0)
1592 i.rex |= REX_MODE64;
1594 /* For 8 bit registers we need an empty rex prefix. Also if the
1595 instruction already has a prefix, we need to convert old
1596 registers to new ones. */
1598 if (((i.types[0] & Reg8) != 0
1599 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1600 || ((i.types[1] & Reg8) != 0
1601 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1602 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1607 i.rex |= REX_OPCODE;
1608 for (x = 0; x < 2; x++)
1610 /* Look for 8 bit operand that uses old registers. */
1611 if ((i.types[x] & Reg8) != 0
1612 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1614 /* In case it is "hi" register, give up. */
1615 if (i.op[x].regs->reg_num > 3)
1616 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1617 i.op[x].regs->reg_name);
1619 /* Otherwise it is equivalent to the extended register.
1620 Since the encoding doesn't change this is merely
1621 cosmetic cleanup for debug output. */
1623 i.op[x].regs = i.op[x].regs + 8;
1629 add_prefix (REX_OPCODE | i.rex);
1631 /* We are ready to output the insn. */
1636 parse_insn (line, mnemonic)
1641 char *token_start = l;
1646 /* Non-zero if we found a prefix only acceptable with string insns. */
1647 const char *expecting_string_instruction = NULL;
1652 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1655 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1657 as_bad (_("no such instruction: `%s'"), token_start);
1662 if (!is_space_char (*l)
1663 && *l != END_OF_INSN
1665 || (*l != PREFIX_SEPARATOR
1668 as_bad (_("invalid character %s in mnemonic"),
1669 output_invalid (*l));
1672 if (token_start == l)
1674 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1675 as_bad (_("expecting prefix; got nothing"));
1677 as_bad (_("expecting mnemonic; got nothing"));
1681 /* Look up instruction (or prefix) via hash table. */
1682 current_templates = hash_find (op_hash, mnemonic);
1684 if (*l != END_OF_INSN
1685 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1686 && current_templates
1687 && (current_templates->start->opcode_modifier & IsPrefix))
1689 if (current_templates->start->cpu_flags
1690 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1692 as_bad ((flag_code != CODE_64BIT
1693 ? _("`%s' is only supported in 64-bit mode")
1694 : _("`%s' is not supported in 64-bit mode")),
1695 current_templates->start->name);
1698 /* If we are in 16-bit mode, do not allow addr16 or data16.
1699 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1700 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1701 && flag_code != CODE_64BIT
1702 && (((current_templates->start->opcode_modifier & Size32) != 0)
1703 ^ (flag_code == CODE_16BIT)))
1705 as_bad (_("redundant %s prefix"),
1706 current_templates->start->name);
1709 /* Add prefix, checking for repeated prefixes. */
1710 switch (add_prefix (current_templates->start->base_opcode))
1715 expecting_string_instruction = current_templates->start->name;
1718 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1725 if (!current_templates)
1727 /* See if we can get a match by trimming off a suffix. */
1730 case WORD_MNEM_SUFFIX:
1731 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1732 i.suffix = SHORT_MNEM_SUFFIX;
1734 case BYTE_MNEM_SUFFIX:
1735 case QWORD_MNEM_SUFFIX:
1736 i.suffix = mnem_p[-1];
1738 current_templates = hash_find (op_hash, mnemonic);
1740 case SHORT_MNEM_SUFFIX:
1741 case LONG_MNEM_SUFFIX:
1744 i.suffix = mnem_p[-1];
1746 current_templates = hash_find (op_hash, mnemonic);
1754 if (intel_float_operand (mnemonic) == 1)
1755 i.suffix = SHORT_MNEM_SUFFIX;
1757 i.suffix = LONG_MNEM_SUFFIX;
1759 current_templates = hash_find (op_hash, mnemonic);
1763 if (!current_templates)
1765 as_bad (_("no such instruction: `%s'"), token_start);
1770 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1772 /* Check for a branch hint. We allow ",pt" and ",pn" for
1773 predict taken and predict not taken respectively.
1774 I'm not sure that branch hints actually do anything on loop
1775 and jcxz insns (JumpByte) for current Pentium4 chips. They
1776 may work in the future and it doesn't hurt to accept them
1778 if (l[0] == ',' && l[1] == 'p')
1782 if (!add_prefix (DS_PREFIX_OPCODE))
1786 else if (l[2] == 'n')
1788 if (!add_prefix (CS_PREFIX_OPCODE))
1794 /* Any other comma loses. */
1797 as_bad (_("invalid character %s in mnemonic"),
1798 output_invalid (*l));
1802 /* Check if instruction is supported on specified architecture. */
1804 for (t = current_templates->start; t < current_templates->end; ++t)
1806 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1807 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1809 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1812 if (!(supported & 2))
1814 as_bad (flag_code == CODE_64BIT
1815 ? _("`%s' is not supported in 64-bit mode")
1816 : _("`%s' is only supported in 64-bit mode"),
1817 current_templates->start->name);
1820 if (!(supported & 1))
1822 as_warn (_("`%s' is not supported on `%s%s'"),
1823 current_templates->start->name,
1825 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1827 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1829 as_warn (_("use .code16 to ensure correct addressing mode"));
1832 /* Check for rep/repne without a string instruction. */
1833 if (expecting_string_instruction)
1835 static templates override;
1837 for (t = current_templates->start; t < current_templates->end; ++t)
1838 if (t->opcode_modifier & IsString)
1840 if (t >= current_templates->end)
1842 as_bad (_("expecting string instruction after `%s'"),
1843 expecting_string_instruction);
1846 for (override.start = t; t < current_templates->end; ++t)
1847 if (!(t->opcode_modifier & IsString))
1850 current_templates = &override;
1857 parse_operands (l, mnemonic)
1859 const char *mnemonic;
1863 /* 1 if operand is pending after ','. */
1864 unsigned int expecting_operand = 0;
1866 /* Non-zero if operand parens not balanced. */
1867 unsigned int paren_not_balanced;
1869 while (*l != END_OF_INSN)
1871 /* Skip optional white space before operand. */
1872 if (is_space_char (*l))
1874 if (!is_operand_char (*l) && *l != END_OF_INSN)
1876 as_bad (_("invalid character %s before operand %d"),
1877 output_invalid (*l),
1881 token_start = l; /* after white space */
1882 paren_not_balanced = 0;
1883 while (paren_not_balanced || *l != ',')
1885 if (*l == END_OF_INSN)
1887 if (paren_not_balanced)
1890 as_bad (_("unbalanced parenthesis in operand %d."),
1893 as_bad (_("unbalanced brackets in operand %d."),
1898 break; /* we are done */
1900 else if (!is_operand_char (*l) && !is_space_char (*l))
1902 as_bad (_("invalid character %s in operand %d"),
1903 output_invalid (*l),
1910 ++paren_not_balanced;
1912 --paren_not_balanced;
1917 ++paren_not_balanced;
1919 --paren_not_balanced;
1923 if (l != token_start)
1924 { /* Yes, we've read in another operand. */
1925 unsigned int operand_ok;
1926 this_operand = i.operands++;
1927 if (i.operands > MAX_OPERANDS)
1929 as_bad (_("spurious operands; (%d operands/instruction max)"),
1933 /* Now parse operand adding info to 'i' as we go along. */
1934 END_STRING_AND_SAVE (l);
1938 i386_intel_operand (token_start,
1939 intel_float_operand (mnemonic));
1941 operand_ok = i386_operand (token_start);
1943 RESTORE_END_STRING (l);
1949 if (expecting_operand)
1951 expecting_operand_after_comma:
1952 as_bad (_("expecting operand after ','; got nothing"));
1957 as_bad (_("expecting operand before ','; got nothing"));
1962 /* Now *l must be either ',' or END_OF_INSN. */
1965 if (*++l == END_OF_INSN)
1967 /* Just skip it, if it's \n complain. */
1968 goto expecting_operand_after_comma;
1970 expecting_operand = 1;
1979 union i386_op temp_op;
1980 unsigned int temp_type;
1981 enum bfd_reloc_code_real temp_reloc;
1985 if (i.operands == 2)
1990 else if (i.operands == 3)
1995 temp_type = i.types[xchg2];
1996 i.types[xchg2] = i.types[xchg1];
1997 i.types[xchg1] = temp_type;
1998 temp_op = i.op[xchg2];
1999 i.op[xchg2] = i.op[xchg1];
2000 i.op[xchg1] = temp_op;
2001 temp_reloc = i.reloc[xchg2];
2002 i.reloc[xchg2] = i.reloc[xchg1];
2003 i.reloc[xchg1] = temp_reloc;
2005 if (i.mem_operands == 2)
2007 const seg_entry *temp_seg;
2008 temp_seg = i.seg[0];
2009 i.seg[0] = i.seg[1];
2010 i.seg[1] = temp_seg;
2014 /* Try to ensure constant immediates are represented in the smallest
2019 char guess_suffix = 0;
2023 guess_suffix = i.suffix;
2024 else if (i.reg_operands)
2026 /* Figure out a suffix from the last register operand specified.
2027 We can't do this properly yet, ie. excluding InOutPortReg,
2028 but the following works for instructions with immediates.
2029 In any case, we can't set i.suffix yet. */
2030 for (op = i.operands; --op >= 0;)
2031 if (i.types[op] & Reg)
2033 if (i.types[op] & Reg8)
2034 guess_suffix = BYTE_MNEM_SUFFIX;
2035 else if (i.types[op] & Reg16)
2036 guess_suffix = WORD_MNEM_SUFFIX;
2037 else if (i.types[op] & Reg32)
2038 guess_suffix = LONG_MNEM_SUFFIX;
2039 else if (i.types[op] & Reg64)
2040 guess_suffix = QWORD_MNEM_SUFFIX;
2044 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2045 guess_suffix = WORD_MNEM_SUFFIX;
2047 for (op = i.operands; --op >= 0;)
2048 if (i.types[op] & Imm)
2050 switch (i.op[op].imms->X_op)
2053 /* If a suffix is given, this operand may be shortened. */
2054 switch (guess_suffix)
2056 case LONG_MNEM_SUFFIX:
2057 i.types[op] |= Imm32 | Imm64;
2059 case WORD_MNEM_SUFFIX:
2060 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2062 case BYTE_MNEM_SUFFIX:
2063 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2067 /* If this operand is at most 16 bits, convert it
2068 to a signed 16 bit number before trying to see
2069 whether it will fit in an even smaller size.
2070 This allows a 16-bit operand such as $0xffe0 to
2071 be recognised as within Imm8S range. */
2072 if ((i.types[op] & Imm16)
2073 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2075 i.op[op].imms->X_add_number =
2076 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2078 if ((i.types[op] & Imm32)
2079 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2082 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2083 ^ ((offsetT) 1 << 31))
2084 - ((offsetT) 1 << 31));
2086 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2088 /* We must avoid matching of Imm32 templates when 64bit
2089 only immediate is available. */
2090 if (guess_suffix == QWORD_MNEM_SUFFIX)
2091 i.types[op] &= ~Imm32;
2098 /* Symbols and expressions. */
2100 /* Convert symbolic operand to proper sizes for matching, but don't
2101 prevent matching a set of insns that only supports sizes other
2102 than those matching the insn suffix. */
2104 unsigned int mask, allowed = 0;
2107 for (t = current_templates->start; t < current_templates->end; ++t)
2108 allowed |= t->operand_types[op];
2109 switch (guess_suffix)
2111 case QWORD_MNEM_SUFFIX:
2112 mask = Imm64 | Imm32S;
2114 case LONG_MNEM_SUFFIX:
2117 case WORD_MNEM_SUFFIX:
2120 case BYTE_MNEM_SUFFIX:
2128 i.types[op] &= mask;
2135 /* Try to use the smallest displacement type too. */
2141 for (op = i.operands; --op >= 0;)
2142 if (i.types[op] & Disp)
2144 if (i.op[op].disps->X_op == O_constant)
2146 offsetT disp = i.op[op].disps->X_add_number;
2148 if ((i.types[op] & Disp16)
2149 && (disp & ~(offsetT) 0xffff) == 0)
2151 /* If this operand is at most 16 bits, convert
2152 to a signed 16 bit number and don't use 64bit
2154 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2155 i.types[op] &= ~Disp64;
2157 if ((i.types[op] & Disp32)
2158 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2160 /* If this operand is at most 32 bits, convert
2161 to a signed 32 bit number and don't use 64bit
2163 disp &= (((offsetT) 2 << 31) - 1);
2164 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2165 i.types[op] &= ~Disp64;
2167 if (!disp && (i.types[op] & BaseIndex))
2169 i.types[op] &= ~Disp;
2173 else if (flag_code == CODE_64BIT)
2175 if (fits_in_signed_long (disp))
2177 i.types[op] &= ~Disp64;
2178 i.types[op] |= Disp32S;
2180 if (fits_in_unsigned_long (disp))
2181 i.types[op] |= Disp32;
2183 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2184 && fits_in_signed_byte (disp))
2185 i.types[op] |= Disp8;
2188 /* We only support 64bit displacement on constants. */
2189 i.types[op] &= ~Disp64;
2196 /* Points to template once we've found it. */
2198 unsigned int overlap0, overlap1, overlap2;
2199 unsigned int found_reverse_match;
2202 #define MATCH(overlap, given, template) \
2203 ((overlap & ~JumpAbsolute) \
2204 && (((given) & (BaseIndex | JumpAbsolute)) \
2205 == ((overlap) & (BaseIndex | JumpAbsolute))))
2207 /* If given types r0 and r1 are registers they must be of the same type
2208 unless the expected operand type register overlap is null.
2209 Note that Acc in a template matches every size of reg. */
2210 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2211 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2212 || ((g0) & Reg) == ((g1) & Reg) \
2213 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2218 found_reverse_match = 0;
2219 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2221 : (i.suffix == WORD_MNEM_SUFFIX
2223 : (i.suffix == SHORT_MNEM_SUFFIX
2225 : (i.suffix == LONG_MNEM_SUFFIX
2227 : (i.suffix == QWORD_MNEM_SUFFIX
2229 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2230 ? No_xSuf : 0))))));
2232 t = current_templates->start;
2233 if (i.suffix == QWORD_MNEM_SUFFIX
2234 && flag_code != CODE_64BIT
2236 ? !(t->opcode_modifier & IgnoreSize)
2237 && !intel_float_operand (t->name)
2238 : intel_float_operand (t->name) != 2)
2239 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2240 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2241 && (t->base_opcode != 0x0fc7
2242 || t->extension_opcode != 1 /* cmpxchg8b */))
2243 t = current_templates->end;
2244 for (; t < current_templates->end; t++)
2246 /* Must have right number of operands. */
2247 if (i.operands != t->operands)
2250 /* Check the suffix, except for some instructions in intel mode. */
2251 if ((t->opcode_modifier & suffix_check)
2253 && (t->opcode_modifier & IgnoreSize)))
2256 /* Do not verify operands when there are none. */
2257 else if (!t->operands)
2259 if (t->cpu_flags & ~cpu_arch_flags)
2261 /* We've found a match; break out of loop. */
2265 overlap0 = i.types[0] & t->operand_types[0];
2266 switch (t->operands)
2269 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2274 overlap1 = i.types[1] & t->operand_types[1];
2275 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2276 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2277 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2278 t->operand_types[0],
2279 overlap1, i.types[1],
2280 t->operand_types[1]))
2282 /* Check if other direction is valid ... */
2283 if ((t->opcode_modifier & (D | FloatD)) == 0)
2286 /* Try reversing direction of operands. */
2287 overlap0 = i.types[0] & t->operand_types[1];
2288 overlap1 = i.types[1] & t->operand_types[0];
2289 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2290 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2291 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2292 t->operand_types[1],
2293 overlap1, i.types[1],
2294 t->operand_types[0]))
2296 /* Does not match either direction. */
2299 /* found_reverse_match holds which of D or FloatDR
2301 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2303 /* Found a forward 2 operand match here. */
2304 else if (t->operands == 3)
2306 /* Here we make use of the fact that there are no
2307 reverse match 3 operand instructions, and all 3
2308 operand instructions only need to be checked for
2309 register consistency between operands 2 and 3. */
2310 overlap2 = i.types[2] & t->operand_types[2];
2311 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2312 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2313 t->operand_types[1],
2314 overlap2, i.types[2],
2315 t->operand_types[2]))
2319 /* Found either forward/reverse 2 or 3 operand match here:
2320 slip through to break. */
2322 if (t->cpu_flags & ~cpu_arch_flags)
2324 found_reverse_match = 0;
2327 /* We've found a match; break out of loop. */
2331 if (t == current_templates->end)
2333 /* We found no match. */
2334 as_bad (_("suffix or operands invalid for `%s'"),
2335 current_templates->start->name);
2339 if (!quiet_warnings)
2342 && ((i.types[0] & JumpAbsolute)
2343 != (t->operand_types[0] & JumpAbsolute)))
2345 as_warn (_("indirect %s without `*'"), t->name);
2348 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2349 == (IsPrefix | IgnoreSize))
2351 /* Warn them that a data or address size prefix doesn't
2352 affect assembly of the next line of code. */
2353 as_warn (_("stand-alone `%s' prefix"), t->name);
2357 /* Copy the template we found. */
2359 if (found_reverse_match)
2361 /* If we found a reverse match we must alter the opcode
2362 direction bit. found_reverse_match holds bits to change
2363 (different for int & float insns). */
2365 i.tm.base_opcode ^= found_reverse_match;
2367 i.tm.operand_types[0] = t->operand_types[1];
2368 i.tm.operand_types[1] = t->operand_types[0];
2377 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2378 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2380 if (i.seg[0] != NULL && i.seg[0] != &es)
2382 as_bad (_("`%s' operand %d must use `%%es' segment"),
2387 /* There's only ever one segment override allowed per instruction.
2388 This instruction possibly has a legal segment override on the
2389 second operand, so copy the segment to where non-string
2390 instructions store it, allowing common code. */
2391 i.seg[0] = i.seg[1];
2393 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2395 if (i.seg[1] != NULL && i.seg[1] != &es)
2397 as_bad (_("`%s' operand %d must use `%%es' segment"),
2407 process_suffix (void)
2409 /* If matched instruction specifies an explicit instruction mnemonic
2411 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2413 if (i.tm.opcode_modifier & Size16)
2414 i.suffix = WORD_MNEM_SUFFIX;
2415 else if (i.tm.opcode_modifier & Size64)
2416 i.suffix = QWORD_MNEM_SUFFIX;
2418 i.suffix = LONG_MNEM_SUFFIX;
2420 else if (i.reg_operands)
2422 /* If there's no instruction mnemonic suffix we try to invent one
2423 based on register operands. */
2426 /* We take i.suffix from the last register operand specified,
2427 Destination register type is more significant than source
2431 for (op = i.operands; --op >= 0;)
2432 if ((i.types[op] & Reg)
2433 && !(i.tm.operand_types[op] & InOutPortReg))
2435 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2436 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2437 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2442 else if (i.suffix == BYTE_MNEM_SUFFIX)
2444 if (!check_byte_reg ())
2447 else if (i.suffix == LONG_MNEM_SUFFIX)
2449 if (!check_long_reg ())
2452 else if (i.suffix == QWORD_MNEM_SUFFIX)
2454 if (!check_qword_reg ())
2457 else if (i.suffix == WORD_MNEM_SUFFIX)
2459 if (!check_word_reg ())
2462 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2463 /* Do nothing if the instruction is going to ignore the prefix. */
2468 else if ((i.tm.opcode_modifier & DefaultSize)
2470 /* exclude fldenv/frstor/fsave/fstenv */
2471 && (i.tm.opcode_modifier & No_sSuf))
2473 i.suffix = stackop_size;
2475 else if (intel_syntax
2477 && ((i.tm.operand_types[0] & JumpAbsolute)
2478 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2479 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2480 && i.tm.extension_opcode <= 3)))
2485 if (!(i.tm.opcode_modifier & No_qSuf))
2487 i.suffix = QWORD_MNEM_SUFFIX;
2491 if (!(i.tm.opcode_modifier & No_lSuf))
2492 i.suffix = LONG_MNEM_SUFFIX;
2495 if (!(i.tm.opcode_modifier & No_wSuf))
2496 i.suffix = WORD_MNEM_SUFFIX;
2505 if (i.tm.opcode_modifier & W)
2507 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2513 unsigned int suffixes = ~i.tm.opcode_modifier
2521 if ((i.tm.opcode_modifier & W)
2522 || ((suffixes & (suffixes - 1))
2523 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2525 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2531 /* Change the opcode based on the operand size given by i.suffix;
2532 We don't need to change things for byte insns. */
2534 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2536 /* It's not a byte, select word/dword operation. */
2537 if (i.tm.opcode_modifier & W)
2539 if (i.tm.opcode_modifier & ShortForm)
2540 i.tm.base_opcode |= 8;
2542 i.tm.base_opcode |= 1;
2545 /* Now select between word & dword operations via the operand
2546 size prefix, except for instructions that will ignore this
2548 if (i.suffix != QWORD_MNEM_SUFFIX
2549 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2550 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2551 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2552 || (flag_code == CODE_64BIT
2553 && (i.tm.opcode_modifier & JumpByte))))
2555 unsigned int prefix = DATA_PREFIX_OPCODE;
2557 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2558 prefix = ADDR_PREFIX_OPCODE;
2560 if (!add_prefix (prefix))
2564 /* Set mode64 for an operand. */
2565 if (i.suffix == QWORD_MNEM_SUFFIX
2566 && flag_code == CODE_64BIT
2567 && (i.tm.opcode_modifier & NoRex64) == 0)
2568 i.rex |= REX_MODE64;
2570 /* Size floating point instruction. */
2571 if (i.suffix == LONG_MNEM_SUFFIX)
2572 if (i.tm.opcode_modifier & FloatMF)
2573 i.tm.base_opcode ^= 4;
2580 check_byte_reg (void)
2584 for (op = i.operands; --op >= 0;)
2586 /* If this is an eight bit register, it's OK. If it's the 16 or
2587 32 bit version of an eight bit register, we will just use the
2588 low portion, and that's OK too. */
2589 if (i.types[op] & Reg8)
2592 /* movzx and movsx should not generate this warning. */
2594 && (i.tm.base_opcode == 0xfb7
2595 || i.tm.base_opcode == 0xfb6
2596 || i.tm.base_opcode == 0x63
2597 || i.tm.base_opcode == 0xfbe
2598 || i.tm.base_opcode == 0xfbf))
2601 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2603 /* Prohibit these changes in the 64bit mode, since the
2604 lowering is more complicated. */
2605 if (flag_code == CODE_64BIT
2606 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2608 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2609 i.op[op].regs->reg_name,
2613 #if REGISTER_WARNINGS
2615 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2616 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2617 (i.op[op].regs + (i.types[op] & Reg16
2618 ? REGNAM_AL - REGNAM_AX
2619 : REGNAM_AL - REGNAM_EAX))->reg_name,
2620 i.op[op].regs->reg_name,
2625 /* Any other register is bad. */
2626 if (i.types[op] & (Reg | RegMMX | RegXMM
2628 | Control | Debug | Test
2629 | FloatReg | FloatAcc))
2631 as_bad (_("`%%%s' not allowed with `%s%c'"),
2632 i.op[op].regs->reg_name,
2646 for (op = i.operands; --op >= 0;)
2647 /* Reject eight bit registers, except where the template requires
2648 them. (eg. movzb) */
2649 if ((i.types[op] & Reg8) != 0
2650 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2652 as_bad (_("`%%%s' not allowed with `%s%c'"),
2653 i.op[op].regs->reg_name,
2658 /* Warn if the e prefix on a general reg is missing. */
2659 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2660 && (i.types[op] & Reg16) != 0
2661 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2663 /* Prohibit these changes in the 64bit mode, since the
2664 lowering is more complicated. */
2665 if (flag_code == CODE_64BIT)
2667 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2668 i.op[op].regs->reg_name,
2672 #if REGISTER_WARNINGS
2674 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2675 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2676 i.op[op].regs->reg_name,
2680 /* Warn if the r prefix on a general reg is missing. */
2681 else if ((i.types[op] & Reg64) != 0
2682 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2684 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2685 i.op[op].regs->reg_name,
2697 for (op = i.operands; --op >= 0; )
2698 /* Reject eight bit registers, except where the template requires
2699 them. (eg. movzb) */
2700 if ((i.types[op] & Reg8) != 0
2701 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2703 as_bad (_("`%%%s' not allowed with `%s%c'"),
2704 i.op[op].regs->reg_name,
2709 /* Warn if the e prefix on a general reg is missing. */
2710 else if (((i.types[op] & Reg16) != 0
2711 || (i.types[op] & Reg32) != 0)
2712 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2714 /* Prohibit these changes in the 64bit mode, since the
2715 lowering is more complicated. */
2716 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2717 i.op[op].regs->reg_name,
2728 for (op = i.operands; --op >= 0;)
2729 /* Reject eight bit registers, except where the template requires
2730 them. (eg. movzb) */
2731 if ((i.types[op] & Reg8) != 0
2732 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2734 as_bad (_("`%%%s' not allowed with `%s%c'"),
2735 i.op[op].regs->reg_name,
2740 /* Warn if the e prefix on a general reg is present. */
2741 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2742 && (i.types[op] & Reg32) != 0
2743 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2745 /* Prohibit these changes in the 64bit mode, since the
2746 lowering is more complicated. */
2747 if (flag_code == CODE_64BIT)
2749 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2750 i.op[op].regs->reg_name,
2755 #if REGISTER_WARNINGS
2756 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2757 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2758 i.op[op].regs->reg_name,
2768 unsigned int overlap0, overlap1, overlap2;
2770 overlap0 = i.types[0] & i.tm.operand_types[0];
2771 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2772 && overlap0 != Imm8 && overlap0 != Imm8S
2773 && overlap0 != Imm16 && overlap0 != Imm32S
2774 && overlap0 != Imm32 && overlap0 != Imm64)
2778 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2780 : (i.suffix == WORD_MNEM_SUFFIX
2782 : (i.suffix == QWORD_MNEM_SUFFIX
2786 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2787 || overlap0 == (Imm16 | Imm32)
2788 || overlap0 == (Imm16 | Imm32S))
2790 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2793 if (overlap0 != Imm8 && overlap0 != Imm8S
2794 && overlap0 != Imm16 && overlap0 != Imm32S
2795 && overlap0 != Imm32 && overlap0 != Imm64)
2797 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2801 i.types[0] = overlap0;
2803 overlap1 = i.types[1] & i.tm.operand_types[1];
2804 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2805 && overlap1 != Imm8 && overlap1 != Imm8S
2806 && overlap1 != Imm16 && overlap1 != Imm32S
2807 && overlap1 != Imm32 && overlap1 != Imm64)
2811 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2813 : (i.suffix == WORD_MNEM_SUFFIX
2815 : (i.suffix == QWORD_MNEM_SUFFIX
2819 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2820 || overlap1 == (Imm16 | Imm32)
2821 || overlap1 == (Imm16 | Imm32S))
2823 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2826 if (overlap1 != Imm8 && overlap1 != Imm8S
2827 && overlap1 != Imm16 && overlap1 != Imm32S
2828 && overlap1 != Imm32 && overlap1 != Imm64)
2830 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2834 i.types[1] = overlap1;
2836 overlap2 = i.types[2] & i.tm.operand_types[2];
2837 assert ((overlap2 & Imm) == 0);
2838 i.types[2] = overlap2;
2846 /* Default segment register this instruction will use for memory
2847 accesses. 0 means unknown. This is only for optimizing out
2848 unnecessary segment overrides. */
2849 const seg_entry *default_seg = 0;
2851 /* The imul $imm, %reg instruction is converted into
2852 imul $imm, %reg, %reg, and the clr %reg instruction
2853 is converted into xor %reg, %reg. */
2854 if (i.tm.opcode_modifier & regKludge)
2856 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2857 /* Pretend we saw the extra register operand. */
2858 assert (i.op[first_reg_op + 1].regs == 0);
2859 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2860 i.types[first_reg_op + 1] = i.types[first_reg_op];
2864 if (i.tm.opcode_modifier & ShortForm)
2866 /* The register or float register operand is in operand 0 or 1. */
2867 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2868 /* Register goes in low 3 bits of opcode. */
2869 i.tm.base_opcode |= i.op[op].regs->reg_num;
2870 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2872 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2874 /* Warn about some common errors, but press on regardless.
2875 The first case can be generated by gcc (<= 2.8.1). */
2876 if (i.operands == 2)
2878 /* Reversed arguments on faddp, fsubp, etc. */
2879 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2880 i.op[1].regs->reg_name,
2881 i.op[0].regs->reg_name);
2885 /* Extraneous `l' suffix on fp insn. */
2886 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2887 i.op[0].regs->reg_name);
2891 else if (i.tm.opcode_modifier & Modrm)
2893 /* The opcode is completed (modulo i.tm.extension_opcode which
2894 must be put into the modrm byte). Now, we make the modrm and
2895 index base bytes based on all the info we've collected. */
2897 default_seg = build_modrm_byte ();
2899 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2901 if (i.tm.base_opcode == POP_SEG_SHORT
2902 && i.op[0].regs->reg_num == 1)
2904 as_bad (_("you can't `pop %%cs'"));
2907 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2908 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2911 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2915 else if ((i.tm.opcode_modifier & IsString) != 0)
2917 /* For the string instructions that allow a segment override
2918 on one of their operands, the default segment is ds. */
2922 if ((i.tm.base_opcode == 0x8d /* lea */
2923 || (i.tm.cpu_flags & CpuSVME))
2924 && i.seg[0] && !quiet_warnings)
2925 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
2927 /* If a segment was explicitly specified, and the specified segment
2928 is not the default, use an opcode prefix to select it. If we
2929 never figured out what the default segment is, then default_seg
2930 will be zero at this point, and the specified segment prefix will
2932 if ((i.seg[0]) && (i.seg[0] != default_seg))
2934 if (!add_prefix (i.seg[0]->seg_prefix))
2940 static const seg_entry *
2943 const seg_entry *default_seg = 0;
2945 /* i.reg_operands MUST be the number of real register operands;
2946 implicit registers do not count. */
2947 if (i.reg_operands == 2)
2949 unsigned int source, dest;
2950 source = ((i.types[0]
2951 & (Reg | RegMMX | RegXMM
2953 | Control | Debug | Test))
2958 /* One of the register operands will be encoded in the i.tm.reg
2959 field, the other in the combined i.tm.mode and i.tm.regmem
2960 fields. If no form of this instruction supports a memory
2961 destination operand, then we assume the source operand may
2962 sometimes be a memory operand and so we need to store the
2963 destination in the i.rm.reg field. */
2964 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2966 i.rm.reg = i.op[dest].regs->reg_num;
2967 i.rm.regmem = i.op[source].regs->reg_num;
2968 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2970 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2975 i.rm.reg = i.op[source].regs->reg_num;
2976 i.rm.regmem = i.op[dest].regs->reg_num;
2977 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2979 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2982 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2984 if (!((i.types[0] | i.types[1]) & Control))
2986 i.rex &= ~(REX_EXTX | REX_EXTZ);
2987 add_prefix (LOCK_PREFIX_OPCODE);
2991 { /* If it's not 2 reg operands... */
2994 unsigned int fake_zero_displacement = 0;
2995 unsigned int op = ((i.types[0] & AnyMem)
2997 : (i.types[1] & AnyMem) ? 1 : 2);
3001 if (i.base_reg == 0)
3004 if (!i.disp_operands)
3005 fake_zero_displacement = 1;
3006 if (i.index_reg == 0)
3008 /* Operand is just <disp> */
3009 if (flag_code == CODE_64BIT)
3011 /* 64bit mode overwrites the 32bit absolute
3012 addressing by RIP relative addressing and
3013 absolute addressing is encoded by one of the
3014 redundant SIB forms. */
3015 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3016 i.sib.base = NO_BASE_REGISTER;
3017 i.sib.index = NO_INDEX_REGISTER;
3018 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3020 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3022 i.rm.regmem = NO_BASE_REGISTER_16;
3023 i.types[op] = Disp16;
3027 i.rm.regmem = NO_BASE_REGISTER;
3028 i.types[op] = Disp32;
3031 else /* !i.base_reg && i.index_reg */
3033 i.sib.index = i.index_reg->reg_num;
3034 i.sib.base = NO_BASE_REGISTER;
3035 i.sib.scale = i.log2_scale_factor;
3036 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3037 i.types[op] &= ~Disp;
3038 if (flag_code != CODE_64BIT)
3039 i.types[op] |= Disp32; /* Must be 32 bit */
3041 i.types[op] |= Disp32S;
3042 if ((i.index_reg->reg_flags & RegRex) != 0)
3046 /* RIP addressing for 64bit mode. */
3047 else if (i.base_reg->reg_type == BaseIndex)
3049 i.rm.regmem = NO_BASE_REGISTER;
3050 i.types[op] &= ~ Disp;
3051 i.types[op] |= Disp32S;
3052 i.flags[op] = Operand_PCrel;
3053 if (! i.disp_operands)
3054 fake_zero_displacement = 1;
3056 else if (i.base_reg->reg_type & Reg16)
3058 switch (i.base_reg->reg_num)
3061 if (i.index_reg == 0)
3063 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3064 i.rm.regmem = i.index_reg->reg_num - 6;
3068 if (i.index_reg == 0)
3071 if ((i.types[op] & Disp) == 0)
3073 /* fake (%bp) into 0(%bp) */
3074 i.types[op] |= Disp8;
3075 fake_zero_displacement = 1;
3078 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3079 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3081 default: /* (%si) -> 4 or (%di) -> 5 */
3082 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3084 i.rm.mode = mode_from_disp_size (i.types[op]);
3086 else /* i.base_reg and 32/64 bit mode */
3088 if (flag_code == CODE_64BIT
3089 && (i.types[op] & Disp))
3090 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3092 i.rm.regmem = i.base_reg->reg_num;
3093 if ((i.base_reg->reg_flags & RegRex) != 0)
3095 i.sib.base = i.base_reg->reg_num;
3096 /* x86-64 ignores REX prefix bit here to avoid decoder
3098 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3101 if (i.disp_operands == 0)
3103 fake_zero_displacement = 1;
3104 i.types[op] |= Disp8;
3107 else if (i.base_reg->reg_num == ESP_REG_NUM)
3111 i.sib.scale = i.log2_scale_factor;
3112 if (i.index_reg == 0)
3114 /* <disp>(%esp) becomes two byte modrm with no index
3115 register. We've already stored the code for esp
3116 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3117 Any base register besides %esp will not use the
3118 extra modrm byte. */
3119 i.sib.index = NO_INDEX_REGISTER;
3120 #if !SCALE1_WHEN_NO_INDEX
3121 /* Another case where we force the second modrm byte. */
3122 if (i.log2_scale_factor)
3123 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3128 i.sib.index = i.index_reg->reg_num;
3129 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3130 if ((i.index_reg->reg_flags & RegRex) != 0)
3133 i.rm.mode = mode_from_disp_size (i.types[op]);
3136 if (fake_zero_displacement)
3138 /* Fakes a zero displacement assuming that i.types[op]
3139 holds the correct displacement size. */
3142 assert (i.op[op].disps == 0);
3143 exp = &disp_expressions[i.disp_operands++];
3144 i.op[op].disps = exp;
3145 exp->X_op = O_constant;
3146 exp->X_add_number = 0;
3147 exp->X_add_symbol = (symbolS *) 0;
3148 exp->X_op_symbol = (symbolS *) 0;
3152 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3153 (if any) based on i.tm.extension_opcode. Again, we must be
3154 careful to make sure that segment/control/debug/test/MMX
3155 registers are coded into the i.rm.reg field. */
3160 & (Reg | RegMMX | RegXMM
3162 | Control | Debug | Test))
3165 & (Reg | RegMMX | RegXMM
3167 | Control | Debug | Test))
3170 /* If there is an extension opcode to put here, the register
3171 number must be put into the regmem field. */
3172 if (i.tm.extension_opcode != None)
3174 i.rm.regmem = i.op[op].regs->reg_num;
3175 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3180 i.rm.reg = i.op[op].regs->reg_num;
3181 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3185 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3186 must set it to 3 to indicate this is a register operand
3187 in the regmem field. */
3188 if (!i.mem_operands)
3192 /* Fill in i.rm.reg field with extension opcode (if any). */
3193 if (i.tm.extension_opcode != None)
3194 i.rm.reg = i.tm.extension_opcode;
3205 relax_substateT subtype;
3210 if (flag_code == CODE_16BIT)
3214 if (i.prefix[DATA_PREFIX] != 0)
3220 /* Pentium4 branch hints. */
3221 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3222 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3227 if (i.prefix[REX_PREFIX] != 0)
3233 if (i.prefixes != 0 && !intel_syntax)
3234 as_warn (_("skipping prefixes on this instruction"));
3236 /* It's always a symbol; End frag & setup for relax.
3237 Make sure there is enough room in this frag for the largest
3238 instruction we may generate in md_convert_frag. This is 2
3239 bytes for the opcode and room for the prefix and largest
3241 frag_grow (prefix + 2 + 4);
3242 /* Prefix and 1 opcode byte go in fr_fix. */
3243 p = frag_more (prefix + 1);
3244 if (i.prefix[DATA_PREFIX] != 0)
3245 *p++ = DATA_PREFIX_OPCODE;
3246 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3247 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3248 *p++ = i.prefix[SEG_PREFIX];
3249 if (i.prefix[REX_PREFIX] != 0)
3250 *p++ = i.prefix[REX_PREFIX];
3251 *p = i.tm.base_opcode;
3253 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3254 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3255 else if ((cpu_arch_flags & Cpu386) != 0)
3256 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3258 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3261 sym = i.op[0].disps->X_add_symbol;
3262 off = i.op[0].disps->X_add_number;
3264 if (i.op[0].disps->X_op != O_constant
3265 && i.op[0].disps->X_op != O_symbol)
3267 /* Handle complex expressions. */
3268 sym = make_expr_symbol (i.op[0].disps);
3272 /* 1 possible extra opcode + 4 byte displacement go in var part.
3273 Pass reloc in fr_var. */
3274 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3284 if (i.tm.opcode_modifier & JumpByte)
3286 /* This is a loop or jecxz type instruction. */
3288 if (i.prefix[ADDR_PREFIX] != 0)
3290 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3293 /* Pentium4 branch hints. */
3294 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3295 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3297 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3306 if (flag_code == CODE_16BIT)
3309 if (i.prefix[DATA_PREFIX] != 0)
3311 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3321 if (i.prefix[REX_PREFIX] != 0)
3323 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3327 if (i.prefixes != 0 && !intel_syntax)
3328 as_warn (_("skipping prefixes on this instruction"));
3330 p = frag_more (1 + size);
3331 *p++ = i.tm.base_opcode;
3333 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3334 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3336 /* All jumps handled here are signed, but don't use a signed limit
3337 check for 32 and 16 bit jumps as we want to allow wrap around at
3338 4G and 64k respectively. */
3340 fixP->fx_signed = 1;
3344 output_interseg_jump ()
3352 if (flag_code == CODE_16BIT)
3356 if (i.prefix[DATA_PREFIX] != 0)
3362 if (i.prefix[REX_PREFIX] != 0)
3372 if (i.prefixes != 0 && !intel_syntax)
3373 as_warn (_("skipping prefixes on this instruction"));
3375 /* 1 opcode; 2 segment; offset */
3376 p = frag_more (prefix + 1 + 2 + size);
3378 if (i.prefix[DATA_PREFIX] != 0)
3379 *p++ = DATA_PREFIX_OPCODE;
3381 if (i.prefix[REX_PREFIX] != 0)
3382 *p++ = i.prefix[REX_PREFIX];
3384 *p++ = i.tm.base_opcode;
3385 if (i.op[1].imms->X_op == O_constant)
3387 offsetT n = i.op[1].imms->X_add_number;
3390 && !fits_in_unsigned_word (n)
3391 && !fits_in_signed_word (n))
3393 as_bad (_("16-bit jump out of range"));
3396 md_number_to_chars (p, n, size);
3399 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3400 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3401 if (i.op[0].imms->X_op != O_constant)
3402 as_bad (_("can't handle non absolute segment in `%s'"),
3404 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3410 fragS *insn_start_frag;
3411 offsetT insn_start_off;
3413 /* Tie dwarf2 debug info to the address at the start of the insn.
3414 We can't do this after the insn has been output as the current
3415 frag may have been closed off. eg. by frag_var. */
3416 dwarf2_emit_insn (0);
3418 insn_start_frag = frag_now;
3419 insn_start_off = frag_now_fix ();
3422 if (i.tm.opcode_modifier & Jump)
3424 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3426 else if (i.tm.opcode_modifier & JumpInterSegment)
3427 output_interseg_jump ();
3430 /* Output normal instructions here. */
3434 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3435 more higher byte to specify a prefix the instruction
3437 if ((i.tm.base_opcode & 0xff0000) != 0)
3439 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3441 unsigned int prefix;
3442 prefix = (i.tm.base_opcode >> 16) & 0xff;
3444 if (prefix != REPE_PREFIX_OPCODE
3445 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3446 add_prefix (prefix);
3449 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3452 /* The prefix bytes. */
3454 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3460 md_number_to_chars (p, (valueT) *q, 1);
3464 /* Now the opcode; be careful about word order here! */
3465 if (fits_in_unsigned_byte (i.tm.base_opcode))
3467 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3473 /* Put out high byte first: can't use md_number_to_chars! */
3474 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3475 *p = i.tm.base_opcode & 0xff;
3478 /* Now the modrm byte and sib byte (if present). */
3479 if (i.tm.opcode_modifier & Modrm)
3482 md_number_to_chars (p,
3483 (valueT) (i.rm.regmem << 0
3487 /* If i.rm.regmem == ESP (4)
3488 && i.rm.mode != (Register mode)
3490 ==> need second modrm byte. */
3491 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3493 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3496 md_number_to_chars (p,
3497 (valueT) (i.sib.base << 0
3499 | i.sib.scale << 6),
3504 if (i.disp_operands)
3505 output_disp (insn_start_frag, insn_start_off);
3508 output_imm (insn_start_frag, insn_start_off);
3516 #endif /* DEBUG386 */
3520 output_disp (insn_start_frag, insn_start_off)
3521 fragS *insn_start_frag;
3522 offsetT insn_start_off;
3527 for (n = 0; n < i.operands; n++)
3529 if (i.types[n] & Disp)
3531 if (i.op[n].disps->X_op == O_constant)
3537 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3540 if (i.types[n] & Disp8)
3542 if (i.types[n] & Disp64)
3545 val = offset_in_range (i.op[n].disps->X_add_number,
3547 p = frag_more (size);
3548 md_number_to_chars (p, val, size);
3552 enum bfd_reloc_code_real reloc_type;
3555 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3557 /* The PC relative address is computed relative
3558 to the instruction boundary, so in case immediate
3559 fields follows, we need to adjust the value. */
3560 if (pcrel && i.imm_operands)
3565 for (n1 = 0; n1 < i.operands; n1++)
3566 if (i.types[n1] & Imm)
3568 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3571 if (i.types[n1] & (Imm8 | Imm8S))
3573 if (i.types[n1] & Imm64)
3578 /* We should find the immediate. */
3579 if (n1 == i.operands)
3581 i.op[n].disps->X_add_number -= imm_size;
3584 if (i.types[n] & Disp32S)
3587 if (i.types[n] & (Disp16 | Disp64))
3590 if (i.types[n] & Disp64)
3594 p = frag_more (size);
3595 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3597 && GOT_symbol == i.op[n].disps->X_add_symbol
3598 && (((reloc_type == BFD_RELOC_32
3599 || reloc_type == BFD_RELOC_X86_64_32S)
3600 && (i.op[n].disps->X_op == O_symbol
3601 || (i.op[n].disps->X_op == O_add
3602 && ((symbol_get_value_expression
3603 (i.op[n].disps->X_op_symbol)->X_op)
3605 || reloc_type == BFD_RELOC_32_PCREL))
3609 if (insn_start_frag == frag_now)
3610 add = (p - frag_now->fr_literal) - insn_start_off;
3615 add = insn_start_frag->fr_fix - insn_start_off;
3616 for (fr = insn_start_frag->fr_next;
3617 fr && fr != frag_now; fr = fr->fr_next)
3619 add += p - frag_now->fr_literal;
3623 reloc_type = BFD_RELOC_386_GOTPC;
3625 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3626 i.op[n].disps->X_add_number += add;
3628 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3629 i.op[n].disps, pcrel, reloc_type);
3636 output_imm (insn_start_frag, insn_start_off)
3637 fragS *insn_start_frag;
3638 offsetT insn_start_off;
3643 for (n = 0; n < i.operands; n++)
3645 if (i.types[n] & Imm)
3647 if (i.op[n].imms->X_op == O_constant)
3653 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3656 if (i.types[n] & (Imm8 | Imm8S))
3658 else if (i.types[n] & Imm64)
3661 val = offset_in_range (i.op[n].imms->X_add_number,
3663 p = frag_more (size);
3664 md_number_to_chars (p, val, size);
3668 /* Not absolute_section.
3669 Need a 32-bit fixup (don't support 8bit
3670 non-absolute imms). Try to support other
3672 enum bfd_reloc_code_real reloc_type;
3676 if ((i.types[n] & (Imm32S))
3677 && (i.suffix == QWORD_MNEM_SUFFIX
3678 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
3680 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3683 if (i.types[n] & (Imm8 | Imm8S))
3685 if (i.types[n] & Imm64)
3689 p = frag_more (size);
3690 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3692 /* This is tough to explain. We end up with this one if we
3693 * have operands that look like
3694 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3695 * obtain the absolute address of the GOT, and it is strongly
3696 * preferable from a performance point of view to avoid using
3697 * a runtime relocation for this. The actual sequence of
3698 * instructions often look something like:
3703 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3705 * The call and pop essentially return the absolute address
3706 * of the label .L66 and store it in %ebx. The linker itself
3707 * will ultimately change the first operand of the addl so
3708 * that %ebx points to the GOT, but to keep things simple, the
3709 * .o file must have this operand set so that it generates not
3710 * the absolute address of .L66, but the absolute address of
3711 * itself. This allows the linker itself simply treat a GOTPC
3712 * relocation as asking for a pcrel offset to the GOT to be
3713 * added in, and the addend of the relocation is stored in the
3714 * operand field for the instruction itself.
3716 * Our job here is to fix the operand so that it would add
3717 * the correct offset so that %ebx would point to itself. The
3718 * thing that is tricky is that .-.L66 will point to the
3719 * beginning of the instruction, so we need to further modify
3720 * the operand so that it will point to itself. There are
3721 * other cases where you have something like:
3723 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3725 * and here no correction would be required. Internally in
3726 * the assembler we treat operands of this form as not being
3727 * pcrel since the '.' is explicitly mentioned, and I wonder
3728 * whether it would simplify matters to do it this way. Who
3729 * knows. In earlier versions of the PIC patches, the
3730 * pcrel_adjust field was used to store the correction, but
3731 * since the expression is not pcrel, I felt it would be
3732 * confusing to do it this way. */
3734 if ((reloc_type == BFD_RELOC_32
3735 || reloc_type == BFD_RELOC_X86_64_32S)
3737 && GOT_symbol == i.op[n].imms->X_add_symbol
3738 && (i.op[n].imms->X_op == O_symbol
3739 || (i.op[n].imms->X_op == O_add
3740 && ((symbol_get_value_expression
3741 (i.op[n].imms->X_op_symbol)->X_op)
3746 if (insn_start_frag == frag_now)
3747 add = (p - frag_now->fr_literal) - insn_start_off;
3752 add = insn_start_frag->fr_fix - insn_start_off;
3753 for (fr = insn_start_frag->fr_next;
3754 fr && fr != frag_now; fr = fr->fr_next)
3756 add += p - frag_now->fr_literal;
3760 reloc_type = BFD_RELOC_386_GOTPC;
3762 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3763 i.op[n].imms->X_add_number += add;
3765 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3766 i.op[n].imms, 0, reloc_type);
3772 /* x86_cons_fix_new is called via the expression parsing code when a
3773 reloc is needed. We use this hook to get the correct .got reloc. */
3774 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3775 static int cons_sign = -1;
3778 x86_cons_fix_new (fragS *frag,
3783 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3785 got_reloc = NO_RELOC;
3788 if (exp->X_op == O_secrel)
3790 exp->X_op = O_symbol;
3791 r = BFD_RELOC_32_SECREL;
3795 fix_new_exp (frag, off, len, exp, 0, r);
3798 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3799 # define lex_got(reloc, adjust, types) NULL
3801 /* Parse operands of the form
3802 <symbol>@GOTOFF+<nnn>
3803 and similar .plt or .got references.
3805 If we find one, set up the correct relocation in RELOC and copy the
3806 input string, minus the `@GOTOFF' into a malloc'd buffer for
3807 parsing by the calling routine. Return this buffer, and if ADJUST
3808 is non-null set it to the length of the string we removed from the
3809 input line. Otherwise return NULL. */
3811 lex_got (enum bfd_reloc_code_real *reloc,
3813 unsigned int *types)
3815 static const struct {
3817 const enum bfd_reloc_code_real rel[2];
3818 const unsigned int types64;
3820 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3821 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3822 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3823 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3824 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3825 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3826 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3827 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3828 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3829 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3830 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3831 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3832 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
3840 for (cp = input_line_pointer; *cp != '@'; cp++)
3841 if (is_end_of_line[(unsigned char) *cp])
3844 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3848 len = strlen (gotrel[j].str);
3849 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3851 if (gotrel[j].rel[object_64bit] != 0)
3854 char *tmpbuf, *past_reloc;
3856 *reloc = gotrel[j].rel[object_64bit];
3862 if (flag_code != CODE_64BIT)
3863 *types = Imm32|Disp32;
3865 *types = gotrel[j].types64;
3868 if (GOT_symbol == NULL)
3869 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3871 /* Replace the relocation token with ' ', so that
3872 errors like foo@GOTOFF1 will be detected. */
3874 /* The length of the first part of our input line. */
3875 first = cp - input_line_pointer;
3877 /* The second part goes from after the reloc token until
3878 (and including) an end_of_line char. Don't use strlen
3879 here as the end_of_line char may not be a NUL. */
3880 past_reloc = cp + 1 + len;
3881 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3883 second = cp - past_reloc;
3885 /* Allocate and copy string. The trailing NUL shouldn't
3886 be necessary, but be safe. */
3887 tmpbuf = xmalloc (first + second + 2);
3888 memcpy (tmpbuf, input_line_pointer, first);
3889 tmpbuf[first] = ' ';
3890 memcpy (tmpbuf + first + 1, past_reloc, second);
3891 tmpbuf[first + second + 1] = '\0';
3895 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3896 gotrel[j].str, 1 << (5 + object_64bit));
3901 /* Might be a symbol version string. Don't as_bad here. */
3906 x86_cons (exp, size)
3910 if (size == 4 || (object_64bit && size == 8))
3912 /* Handle @GOTOFF and the like in an expression. */
3914 char *gotfree_input_line;
3917 save = input_line_pointer;
3918 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
3919 if (gotfree_input_line)
3920 input_line_pointer = gotfree_input_line;
3924 if (gotfree_input_line)
3926 /* expression () has merrily parsed up to the end of line,
3927 or a comma - in the wrong buffer. Transfer how far
3928 input_line_pointer has moved to the right buffer. */
3929 input_line_pointer = (save
3930 + (input_line_pointer - gotfree_input_line)
3932 free (gotfree_input_line);
3940 static void signed_cons (int size)
3942 if (flag_code == CODE_64BIT)
3950 pe_directive_secrel (dummy)
3951 int dummy ATTRIBUTE_UNUSED;
3958 if (exp.X_op == O_symbol)
3959 exp.X_op = O_secrel;
3961 emit_expr (&exp, 4);
3963 while (*input_line_pointer++ == ',');
3965 input_line_pointer--;
3966 demand_empty_rest_of_line ();
3970 static int i386_immediate PARAMS ((char *));
3973 i386_immediate (imm_start)
3976 char *save_input_line_pointer;
3977 char *gotfree_input_line;
3980 unsigned int types = ~0U;
3982 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3984 as_bad (_("only 1 or 2 immediate operands are allowed"));
3988 exp = &im_expressions[i.imm_operands++];
3989 i.op[this_operand].imms = exp;
3991 if (is_space_char (*imm_start))
3994 save_input_line_pointer = input_line_pointer;
3995 input_line_pointer = imm_start;
3997 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
3998 if (gotfree_input_line)
3999 input_line_pointer = gotfree_input_line;
4001 exp_seg = expression (exp);
4004 if (*input_line_pointer)
4005 as_bad (_("junk `%s' after expression"), input_line_pointer);
4007 input_line_pointer = save_input_line_pointer;
4008 if (gotfree_input_line)
4009 free (gotfree_input_line);
4011 if (exp->X_op == O_absent || exp->X_op == O_big)
4013 /* Missing or bad expr becomes absolute 0. */
4014 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4016 exp->X_op = O_constant;
4017 exp->X_add_number = 0;
4018 exp->X_add_symbol = (symbolS *) 0;
4019 exp->X_op_symbol = (symbolS *) 0;
4021 else if (exp->X_op == O_constant)
4023 /* Size it properly later. */
4024 i.types[this_operand] |= Imm64;
4025 /* If BFD64, sign extend val. */
4026 if (!use_rela_relocations)
4027 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4028 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4030 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4031 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4032 && exp_seg != absolute_section
4033 && exp_seg != text_section
4034 && exp_seg != data_section
4035 && exp_seg != bss_section
4036 && exp_seg != undefined_section
4037 && !bfd_is_com_section (exp_seg))
4039 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4045 /* This is an address. The size of the address will be
4046 determined later, depending on destination register,
4047 suffix, or the default for the section. */
4048 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4049 i.types[this_operand] &= types;
4055 static char *i386_scale PARAMS ((char *));
4062 char *save = input_line_pointer;
4064 input_line_pointer = scale;
4065 val = get_absolute_expression ();
4070 i.log2_scale_factor = 0;
4073 i.log2_scale_factor = 1;
4076 i.log2_scale_factor = 2;
4079 i.log2_scale_factor = 3;
4083 char sep = *input_line_pointer;
4085 *input_line_pointer = '\0';
4086 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4088 *input_line_pointer = sep;
4089 input_line_pointer = save;
4093 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4095 as_warn (_("scale factor of %d without an index register"),
4096 1 << i.log2_scale_factor);
4097 #if SCALE1_WHEN_NO_INDEX
4098 i.log2_scale_factor = 0;
4101 scale = input_line_pointer;
4102 input_line_pointer = save;
4106 static int i386_displacement PARAMS ((char *, char *));
4109 i386_displacement (disp_start, disp_end)
4115 char *save_input_line_pointer;
4116 char *gotfree_input_line;
4117 int bigdisp, override;
4118 unsigned int types = Disp;
4120 if ((i.types[this_operand] & JumpAbsolute)
4121 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4124 override = (i.prefix[ADDR_PREFIX] != 0);
4128 /* For PC-relative branches, the width of the displacement
4129 is dependent upon data size, not address size. */
4131 override = (i.prefix[DATA_PREFIX] != 0);
4133 if (flag_code == CODE_64BIT)
4136 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4140 bigdisp = Disp64 | Disp32S | Disp32;
4147 override = (i.suffix == (flag_code != CODE_16BIT
4149 : LONG_MNEM_SUFFIX));
4152 if ((flag_code == CODE_16BIT) ^ override)
4155 i.types[this_operand] |= bigdisp;
4157 exp = &disp_expressions[i.disp_operands];
4158 i.op[this_operand].disps = exp;
4160 save_input_line_pointer = input_line_pointer;
4161 input_line_pointer = disp_start;
4162 END_STRING_AND_SAVE (disp_end);
4164 #ifndef GCC_ASM_O_HACK
4165 #define GCC_ASM_O_HACK 0
4168 END_STRING_AND_SAVE (disp_end + 1);
4169 if ((i.types[this_operand] & BaseIndex) != 0
4170 && displacement_string_end[-1] == '+')
4172 /* This hack is to avoid a warning when using the "o"
4173 constraint within gcc asm statements.
4176 #define _set_tssldt_desc(n,addr,limit,type) \
4177 __asm__ __volatile__ ( \
4179 "movw %w1,2+%0\n\t" \
4181 "movb %b1,4+%0\n\t" \
4182 "movb %4,5+%0\n\t" \
4183 "movb $0,6+%0\n\t" \
4184 "movb %h1,7+%0\n\t" \
4186 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4188 This works great except that the output assembler ends
4189 up looking a bit weird if it turns out that there is
4190 no offset. You end up producing code that looks like:
4203 So here we provide the missing zero. */
4205 *displacement_string_end = '0';
4208 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4209 if (gotfree_input_line)
4210 input_line_pointer = gotfree_input_line;
4212 exp_seg = expression (exp);
4215 if (*input_line_pointer)
4216 as_bad (_("junk `%s' after expression"), input_line_pointer);
4218 RESTORE_END_STRING (disp_end + 1);
4220 RESTORE_END_STRING (disp_end);
4221 input_line_pointer = save_input_line_pointer;
4222 if (gotfree_input_line)
4223 free (gotfree_input_line);
4225 /* We do this to make sure that the section symbol is in
4226 the symbol table. We will ultimately change the relocation
4227 to be relative to the beginning of the section. */
4228 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4229 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4230 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4232 if (exp->X_op != O_symbol)
4234 as_bad (_("bad expression used with @%s"),
4235 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4241 if (S_IS_LOCAL (exp->X_add_symbol)
4242 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4243 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4244 exp->X_op = O_subtract;
4245 exp->X_op_symbol = GOT_symbol;
4246 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4247 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4248 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4249 i.reloc[this_operand] = BFD_RELOC_64;
4251 i.reloc[this_operand] = BFD_RELOC_32;
4254 if (exp->X_op == O_absent || exp->X_op == O_big)
4256 /* Missing or bad expr becomes absolute 0. */
4257 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4259 exp->X_op = O_constant;
4260 exp->X_add_number = 0;
4261 exp->X_add_symbol = (symbolS *) 0;
4262 exp->X_op_symbol = (symbolS *) 0;
4265 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4266 if (exp->X_op != O_constant
4267 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4268 && exp_seg != absolute_section
4269 && exp_seg != text_section
4270 && exp_seg != data_section
4271 && exp_seg != bss_section
4272 && exp_seg != undefined_section
4273 && !bfd_is_com_section (exp_seg))
4275 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4280 if (!(i.types[this_operand] & ~Disp))
4281 i.types[this_operand] &= types;
4286 static int i386_index_check PARAMS ((const char *));
4288 /* Make sure the memory operand we've been dealt is valid.
4289 Return 1 on success, 0 on a failure. */
4292 i386_index_check (operand_string)
4293 const char *operand_string;
4296 #if INFER_ADDR_PREFIX
4302 if ((current_templates->start->cpu_flags & CpuSVME)
4303 && current_templates->end[-1].operand_types[0] == AnyMem)
4305 /* Memory operands of SVME insns are special in that they only allow
4306 rAX as their memory address and ignore any segment override. */
4309 /* SKINIT is even more restrictive: it always requires EAX. */
4310 if (strcmp (current_templates->start->name, "skinit") == 0)
4312 else if (flag_code == CODE_64BIT)
4313 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4315 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4319 || !(i.base_reg->reg_type & Acc)
4320 || !(i.base_reg->reg_type & RegXX)
4322 || (i.types[0] & Disp))
4325 else if (flag_code == CODE_64BIT)
4327 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4330 && ((i.base_reg->reg_type & RegXX) == 0)
4331 && (i.base_reg->reg_type != BaseIndex
4334 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4335 != (RegXX | BaseIndex))))
4340 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4344 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4345 != (Reg16 | BaseIndex)))
4347 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4348 != (Reg16 | BaseIndex))
4350 && i.base_reg->reg_num < 6
4351 && i.index_reg->reg_num >= 6
4352 && i.log2_scale_factor == 0))))
4359 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4361 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4362 != (Reg32 | BaseIndex))))
4368 #if INFER_ADDR_PREFIX
4369 if (i.prefix[ADDR_PREFIX] == 0)
4371 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4373 /* Change the size of any displacement too. At most one of
4374 Disp16 or Disp32 is set.
4375 FIXME. There doesn't seem to be any real need for separate
4376 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4377 Removing them would probably clean up the code quite a lot. */
4378 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4379 i.types[this_operand] ^= (Disp16 | Disp32);
4384 as_bad (_("`%s' is not a valid base/index expression"),
4388 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4390 flag_code_names[flag_code]);
4395 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4399 i386_operand (operand_string)
4400 char *operand_string;
4404 char *op_string = operand_string;
4406 if (is_space_char (*op_string))
4409 /* We check for an absolute prefix (differentiating,
4410 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4411 if (*op_string == ABSOLUTE_PREFIX)
4414 if (is_space_char (*op_string))
4416 i.types[this_operand] |= JumpAbsolute;
4419 /* Check if operand is a register. */
4420 if ((r = parse_register (op_string, &end_op)) != NULL)
4422 /* Check for a segment override by searching for ':' after a
4423 segment register. */
4425 if (is_space_char (*op_string))
4427 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4432 i.seg[i.mem_operands] = &es;
4435 i.seg[i.mem_operands] = &cs;
4438 i.seg[i.mem_operands] = &ss;
4441 i.seg[i.mem_operands] = &ds;
4444 i.seg[i.mem_operands] = &fs;
4447 i.seg[i.mem_operands] = &gs;
4451 /* Skip the ':' and whitespace. */
4453 if (is_space_char (*op_string))
4456 if (!is_digit_char (*op_string)
4457 && !is_identifier_char (*op_string)
4458 && *op_string != '('
4459 && *op_string != ABSOLUTE_PREFIX)
4461 as_bad (_("bad memory operand `%s'"), op_string);
4464 /* Handle case of %es:*foo. */
4465 if (*op_string == ABSOLUTE_PREFIX)
4468 if (is_space_char (*op_string))
4470 i.types[this_operand] |= JumpAbsolute;
4472 goto do_memory_reference;
4476 as_bad (_("junk `%s' after register"), op_string);
4479 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4480 i.op[this_operand].regs = r;
4483 else if (*op_string == REGISTER_PREFIX)
4485 as_bad (_("bad register name `%s'"), op_string);
4488 else if (*op_string == IMMEDIATE_PREFIX)
4491 if (i.types[this_operand] & JumpAbsolute)
4493 as_bad (_("immediate operand illegal with absolute jump"));
4496 if (!i386_immediate (op_string))
4499 else if (is_digit_char (*op_string)
4500 || is_identifier_char (*op_string)
4501 || *op_string == '(')
4503 /* This is a memory reference of some sort. */
4506 /* Start and end of displacement string expression (if found). */
4507 char *displacement_string_start;
4508 char *displacement_string_end;
4510 do_memory_reference:
4511 if ((i.mem_operands == 1
4512 && (current_templates->start->opcode_modifier & IsString) == 0)
4513 || i.mem_operands == 2)
4515 as_bad (_("too many memory references for `%s'"),
4516 current_templates->start->name);
4520 /* Check for base index form. We detect the base index form by
4521 looking for an ')' at the end of the operand, searching
4522 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4524 base_string = op_string + strlen (op_string);
4527 if (is_space_char (*base_string))
4530 /* If we only have a displacement, set-up for it to be parsed later. */
4531 displacement_string_start = op_string;
4532 displacement_string_end = base_string + 1;
4534 if (*base_string == ')')
4537 unsigned int parens_balanced = 1;
4538 /* We've already checked that the number of left & right ()'s are
4539 equal, so this loop will not be infinite. */
4543 if (*base_string == ')')
4545 if (*base_string == '(')
4548 while (parens_balanced);
4550 temp_string = base_string;
4552 /* Skip past '(' and whitespace. */
4554 if (is_space_char (*base_string))
4557 if (*base_string == ','
4558 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
4560 displacement_string_end = temp_string;
4562 i.types[this_operand] |= BaseIndex;
4566 base_string = end_op;
4567 if (is_space_char (*base_string))
4571 /* There may be an index reg or scale factor here. */
4572 if (*base_string == ',')
4575 if (is_space_char (*base_string))
4578 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
4580 base_string = end_op;
4581 if (is_space_char (*base_string))
4583 if (*base_string == ',')
4586 if (is_space_char (*base_string))
4589 else if (*base_string != ')')
4591 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4596 else if (*base_string == REGISTER_PREFIX)
4598 as_bad (_("bad register name `%s'"), base_string);
4602 /* Check for scale factor. */
4603 if (*base_string != ')')
4605 char *end_scale = i386_scale (base_string);
4610 base_string = end_scale;
4611 if (is_space_char (*base_string))
4613 if (*base_string != ')')
4615 as_bad (_("expecting `)' after scale factor in `%s'"),
4620 else if (!i.index_reg)
4622 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4627 else if (*base_string != ')')
4629 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4634 else if (*base_string == REGISTER_PREFIX)
4636 as_bad (_("bad register name `%s'"), base_string);
4641 /* If there's an expression beginning the operand, parse it,
4642 assuming displacement_string_start and
4643 displacement_string_end are meaningful. */
4644 if (displacement_string_start != displacement_string_end)
4646 if (!i386_displacement (displacement_string_start,
4647 displacement_string_end))
4651 /* Special case for (%dx) while doing input/output op. */
4653 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4655 && i.log2_scale_factor == 0
4656 && i.seg[i.mem_operands] == 0
4657 && (i.types[this_operand] & Disp) == 0)
4659 i.types[this_operand] = InOutPortReg;
4663 if (i386_index_check (operand_string) == 0)
4669 /* It's not a memory operand; argh! */
4670 as_bad (_("invalid char %s beginning operand %d `%s'"),
4671 output_invalid (*op_string),
4676 return 1; /* Normal return. */
4679 /* md_estimate_size_before_relax()
4681 Called just before relax() for rs_machine_dependent frags. The x86
4682 assembler uses these frags to handle variable size jump
4685 Any symbol that is now undefined will not become defined.
4686 Return the correct fr_subtype in the frag.
4687 Return the initial "guess for variable size of frag" to caller.
4688 The guess is actually the growth beyond the fixed part. Whatever
4689 we do to grow the fixed or variable part contributes to our
4693 md_estimate_size_before_relax (fragP, segment)
4697 /* We've already got fragP->fr_subtype right; all we have to do is
4698 check for un-relaxable symbols. On an ELF system, we can't relax
4699 an externally visible symbol, because it may be overridden by a
4701 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4704 && (S_IS_EXTERNAL (fragP->fr_symbol)
4705 || S_IS_WEAK (fragP->fr_symbol)))
4709 /* Symbol is undefined in this segment, or we need to keep a
4710 reloc so that weak symbols can be overridden. */
4711 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4712 enum bfd_reloc_code_real reloc_type;
4713 unsigned char *opcode;
4716 if (fragP->fr_var != NO_RELOC)
4717 reloc_type = fragP->fr_var;
4719 reloc_type = BFD_RELOC_16_PCREL;
4721 reloc_type = BFD_RELOC_32_PCREL;
4723 old_fr_fix = fragP->fr_fix;
4724 opcode = (unsigned char *) fragP->fr_opcode;
4726 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4729 /* Make jmp (0xeb) a (d)word displacement jump. */
4731 fragP->fr_fix += size;
4732 fix_new (fragP, old_fr_fix, size,
4734 fragP->fr_offset, 1,
4740 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4742 /* Negate the condition, and branch past an
4743 unconditional jump. */
4746 /* Insert an unconditional jump. */
4748 /* We added two extra opcode bytes, and have a two byte
4750 fragP->fr_fix += 2 + 2;
4751 fix_new (fragP, old_fr_fix + 2, 2,
4753 fragP->fr_offset, 1,
4760 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4765 fixP = fix_new (fragP, old_fr_fix, 1,
4767 fragP->fr_offset, 1,
4769 fixP->fx_signed = 1;
4773 /* This changes the byte-displacement jump 0x7N
4774 to the (d)word-displacement jump 0x0f,0x8N. */
4775 opcode[1] = opcode[0] + 0x10;
4776 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4777 /* We've added an opcode byte. */
4778 fragP->fr_fix += 1 + size;
4779 fix_new (fragP, old_fr_fix + 1, size,
4781 fragP->fr_offset, 1,
4786 BAD_CASE (fragP->fr_subtype);
4790 return fragP->fr_fix - old_fr_fix;
4793 /* Guess size depending on current relax state. Initially the relax
4794 state will correspond to a short jump and we return 1, because
4795 the variable part of the frag (the branch offset) is one byte
4796 long. However, we can relax a section more than once and in that
4797 case we must either set fr_subtype back to the unrelaxed state,
4798 or return the value for the appropriate branch. */
4799 return md_relax_table[fragP->fr_subtype].rlx_length;
4802 /* Called after relax() is finished.
4804 In: Address of frag.
4805 fr_type == rs_machine_dependent.
4806 fr_subtype is what the address relaxed to.
4808 Out: Any fixSs and constants are set up.
4809 Caller will turn frag into a ".space 0". */
4812 md_convert_frag (abfd, sec, fragP)
4813 bfd *abfd ATTRIBUTE_UNUSED;
4814 segT sec ATTRIBUTE_UNUSED;
4817 unsigned char *opcode;
4818 unsigned char *where_to_put_displacement = NULL;
4819 offsetT target_address;
4820 offsetT opcode_address;
4821 unsigned int extension = 0;
4822 offsetT displacement_from_opcode_start;
4824 opcode = (unsigned char *) fragP->fr_opcode;
4826 /* Address we want to reach in file space. */
4827 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4829 /* Address opcode resides at in file space. */
4830 opcode_address = fragP->fr_address + fragP->fr_fix;
4832 /* Displacement from opcode start to fill into instruction. */
4833 displacement_from_opcode_start = target_address - opcode_address;
4835 if ((fragP->fr_subtype & BIG) == 0)
4837 /* Don't have to change opcode. */
4838 extension = 1; /* 1 opcode + 1 displacement */
4839 where_to_put_displacement = &opcode[1];
4843 if (no_cond_jump_promotion
4844 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4845 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4847 switch (fragP->fr_subtype)
4849 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4850 extension = 4; /* 1 opcode + 4 displacement */
4852 where_to_put_displacement = &opcode[1];
4855 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4856 extension = 2; /* 1 opcode + 2 displacement */
4858 where_to_put_displacement = &opcode[1];
4861 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4862 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4863 extension = 5; /* 2 opcode + 4 displacement */
4864 opcode[1] = opcode[0] + 0x10;
4865 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4866 where_to_put_displacement = &opcode[2];
4869 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4870 extension = 3; /* 2 opcode + 2 displacement */
4871 opcode[1] = opcode[0] + 0x10;
4872 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4873 where_to_put_displacement = &opcode[2];
4876 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4881 where_to_put_displacement = &opcode[3];
4885 BAD_CASE (fragP->fr_subtype);
4890 /* Now put displacement after opcode. */
4891 md_number_to_chars ((char *) where_to_put_displacement,
4892 (valueT) (displacement_from_opcode_start - extension),
4893 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4894 fragP->fr_fix += extension;
4897 /* Size of byte displacement jmp. */
4898 int md_short_jump_size = 2;
4900 /* Size of dword displacement jmp. */
4901 int md_long_jump_size = 5;
4904 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4906 addressT from_addr, to_addr;
4907 fragS *frag ATTRIBUTE_UNUSED;
4908 symbolS *to_symbol ATTRIBUTE_UNUSED;
4912 offset = to_addr - (from_addr + 2);
4913 /* Opcode for byte-disp jump. */
4914 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4915 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4919 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4921 addressT from_addr, to_addr;
4922 fragS *frag ATTRIBUTE_UNUSED;
4923 symbolS *to_symbol ATTRIBUTE_UNUSED;
4927 offset = to_addr - (from_addr + 5);
4928 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4929 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4932 /* Apply a fixup (fixS) to segment data, once it has been determined
4933 by our caller that we have all the info we need to fix it up.
4935 On the 386, immediates, displacements, and data pointers are all in
4936 the same (little-endian) format, so we don't need to care about which
4940 md_apply_fix (fixP, valP, seg)
4941 /* The fix we're to put in. */
4943 /* Pointer to the value of the bits. */
4945 /* Segment fix is from. */
4946 segT seg ATTRIBUTE_UNUSED;
4948 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4949 valueT value = *valP;
4951 #if !defined (TE_Mach)
4954 switch (fixP->fx_r_type)
4960 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4963 case BFD_RELOC_X86_64_32S:
4964 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4967 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4970 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4975 if (fixP->fx_addsy != NULL
4976 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4977 || fixP->fx_r_type == BFD_RELOC_64_PCREL
4978 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4979 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4980 && !use_rela_relocations)
4982 /* This is a hack. There should be a better way to handle this.
4983 This covers for the fact that bfd_install_relocation will
4984 subtract the current location (for partial_inplace, PC relative
4985 relocations); see more below. */
4989 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4992 value += fixP->fx_where + fixP->fx_frag->fr_address;
4994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4997 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5000 || (symbol_section_p (fixP->fx_addsy)
5001 && sym_seg != absolute_section))
5002 && !generic_force_reloc (fixP))
5004 /* Yes, we add the values in twice. This is because
5005 bfd_install_relocation subtracts them out again. I think
5006 bfd_install_relocation is broken, but I don't dare change
5008 value += fixP->fx_where + fixP->fx_frag->fr_address;
5012 #if defined (OBJ_COFF) && defined (TE_PE)
5013 /* For some reason, the PE format does not store a
5014 section address offset for a PC relative symbol. */
5015 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5016 || S_IS_WEAK (fixP->fx_addsy))
5017 value += md_pcrel_from (fixP);
5021 /* Fix a few things - the dynamic linker expects certain values here,
5022 and we must not disappoint it. */
5023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5024 if (IS_ELF && fixP->fx_addsy)
5025 switch (fixP->fx_r_type)
5027 case BFD_RELOC_386_PLT32:
5028 case BFD_RELOC_X86_64_PLT32:
5029 /* Make the jump instruction point to the address of the operand. At
5030 runtime we merely add the offset to the actual PLT entry. */
5034 case BFD_RELOC_386_TLS_GD:
5035 case BFD_RELOC_386_TLS_LDM:
5036 case BFD_RELOC_386_TLS_IE_32:
5037 case BFD_RELOC_386_TLS_IE:
5038 case BFD_RELOC_386_TLS_GOTIE:
5039 case BFD_RELOC_X86_64_TLSGD:
5040 case BFD_RELOC_X86_64_TLSLD:
5041 case BFD_RELOC_X86_64_GOTTPOFF:
5042 value = 0; /* Fully resolved at runtime. No addend. */
5044 case BFD_RELOC_386_TLS_LE:
5045 case BFD_RELOC_386_TLS_LDO_32:
5046 case BFD_RELOC_386_TLS_LE_32:
5047 case BFD_RELOC_X86_64_DTPOFF32:
5048 case BFD_RELOC_X86_64_DTPOFF64:
5049 case BFD_RELOC_X86_64_TPOFF32:
5050 case BFD_RELOC_X86_64_TPOFF64:
5051 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5054 case BFD_RELOC_386_GOT32:
5055 case BFD_RELOC_X86_64_GOT32:
5056 value = 0; /* Fully resolved at runtime. No addend. */
5059 case BFD_RELOC_VTABLE_INHERIT:
5060 case BFD_RELOC_VTABLE_ENTRY:
5067 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5069 #endif /* !defined (TE_Mach) */
5071 /* Are we finished with this relocation now? */
5072 if (fixP->fx_addsy == NULL)
5074 else if (use_rela_relocations)
5076 fixP->fx_no_overflow = 1;
5077 /* Remember value for tc_gen_reloc. */
5078 fixP->fx_addnumber = value;
5082 md_number_to_chars (p, value, fixP->fx_size);
5085 #define MAX_LITTLENUMS 6
5087 /* Turn the string pointed to by litP into a floating point constant
5088 of type TYPE, and emit the appropriate bytes. The number of
5089 LITTLENUMS emitted is stored in *SIZEP. An error message is
5090 returned, or NULL on OK. */
5093 md_atof (type, litP, sizeP)
5099 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5100 LITTLENUM_TYPE *wordP;
5122 return _("Bad call to md_atof ()");
5124 t = atof_ieee (input_line_pointer, type, words);
5126 input_line_pointer = t;
5128 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5129 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5130 the bigendian 386. */
5131 for (wordP = words + prec - 1; prec--;)
5133 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5134 litP += sizeof (LITTLENUM_TYPE);
5139 static char output_invalid_buf[8];
5146 sprintf (output_invalid_buf, "'%c'", c);
5148 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5149 return output_invalid_buf;
5152 /* REG_STRING starts *before* REGISTER_PREFIX. */
5154 static const reg_entry *
5155 parse_real_register (char *reg_string, char **end_op)
5157 char *s = reg_string;
5159 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5162 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5163 if (*s == REGISTER_PREFIX)
5166 if (is_space_char (*s))
5170 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5172 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5173 return (const reg_entry *) NULL;
5177 /* For naked regs, make sure that we are not dealing with an identifier.
5178 This prevents confusing an identifier like `eax_var' with register
5180 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5181 return (const reg_entry *) NULL;
5185 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5187 /* Handle floating point regs, allowing spaces in the (i) part. */
5188 if (r == i386_regtab /* %st is first entry of table */)
5190 if (is_space_char (*s))
5195 if (is_space_char (*s))
5197 if (*s >= '0' && *s <= '7')
5199 r = &i386_float_regtab[*s - '0'];
5201 if (is_space_char (*s))
5209 /* We have "%st(" then garbage. */
5210 return (const reg_entry *) NULL;
5215 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5216 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5217 && flag_code != CODE_64BIT)
5218 return (const reg_entry *) NULL;
5223 /* REG_STRING starts *before* REGISTER_PREFIX. */
5225 static const reg_entry *
5226 parse_register (char *reg_string, char **end_op)
5230 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5231 r = parse_real_register (reg_string, end_op);
5236 char *save = input_line_pointer;
5240 input_line_pointer = reg_string;
5241 c = get_symbol_end ();
5242 symbolP = symbol_find (reg_string);
5243 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5245 const expressionS *e = symbol_get_value_expression (symbolP);
5247 know (e->X_op == O_register);
5248 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5249 r = i386_regtab + e->X_add_number;
5250 *end_op = input_line_pointer;
5252 *input_line_pointer = c;
5253 input_line_pointer = save;
5259 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5262 char *end = input_line_pointer;
5265 r = parse_register (name, &input_line_pointer);
5266 if (r && end <= input_line_pointer)
5268 *nextcharP = *input_line_pointer;
5269 *input_line_pointer = 0;
5270 e->X_op = O_register;
5271 e->X_add_number = r - i386_regtab;
5274 input_line_pointer = end;
5280 md_operand (expressionS *e)
5282 if (*input_line_pointer == REGISTER_PREFIX)
5285 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5289 e->X_op = O_register;
5290 e->X_add_number = r - i386_regtab;
5291 input_line_pointer = end;
5297 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5298 const char *md_shortopts = "kVQ:sqn";
5300 const char *md_shortopts = "qn";
5303 #define OPTION_32 (OPTION_MD_BASE + 0)
5304 #define OPTION_64 (OPTION_MD_BASE + 1)
5305 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5307 struct option md_longopts[] = {
5308 {"32", no_argument, NULL, OPTION_32},
5309 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5310 {"64", no_argument, NULL, OPTION_64},
5312 {"divide", no_argument, NULL, OPTION_DIVIDE},
5313 {NULL, no_argument, NULL, 0}
5315 size_t md_longopts_size = sizeof (md_longopts);
5318 md_parse_option (c, arg)
5320 char *arg ATTRIBUTE_UNUSED;
5325 optimize_align_code = 0;
5332 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5333 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5334 should be emitted or not. FIXME: Not implemented. */
5338 /* -V: SVR4 argument to print version ID. */
5340 print_version_id ();
5343 /* -k: Ignore for FreeBSD compatibility. */
5348 /* -s: On i386 Solaris, this tells the native assembler to use
5349 .stab instead of .stab.excl. We always use .stab anyhow. */
5354 const char **list, **l;
5356 list = bfd_target_list ();
5357 for (l = list; *l != NULL; l++)
5358 if (strcmp (*l, "elf64-x86-64") == 0)
5360 default_arch = "x86_64";
5364 as_fatal (_("No compiled in support for x86_64"));
5371 default_arch = "i386";
5375 #ifdef SVR4_COMMENT_CHARS
5380 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5382 for (s = i386_comment_chars; *s != '\0'; s++)
5386 i386_comment_chars = n;
5398 md_show_usage (stream)
5401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5402 fprintf (stream, _("\
5404 -V print assembler version number\n\
5407 fprintf (stream, _("\
5408 -n Do not optimize code alignment\n\
5409 -q quieten some warnings\n"));
5410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5411 fprintf (stream, _("\
5414 #ifdef SVR4_COMMENT_CHARS
5415 fprintf (stream, _("\
5416 --divide do not treat `/' as a comment character\n"));
5418 fprintf (stream, _("\
5419 --divide ignored\n"));
5423 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5424 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5426 /* Pick the target format to use. */
5429 i386_target_format ()
5431 if (!strcmp (default_arch, "x86_64"))
5432 set_code_flag (CODE_64BIT);
5433 else if (!strcmp (default_arch, "i386"))
5434 set_code_flag (CODE_32BIT);
5436 as_fatal (_("Unknown architecture"));
5437 switch (OUTPUT_FLAVOR)
5439 #ifdef OBJ_MAYBE_AOUT
5440 case bfd_target_aout_flavour:
5441 return AOUT_TARGET_FORMAT;
5443 #ifdef OBJ_MAYBE_COFF
5444 case bfd_target_coff_flavour:
5447 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5448 case bfd_target_elf_flavour:
5450 if (flag_code == CODE_64BIT)
5453 use_rela_relocations = 1;
5455 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5464 #endif /* OBJ_MAYBE_ more than one */
5466 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5467 void i386_elf_emit_arch_note ()
5469 if (IS_ELF && cpu_arch_name != NULL)
5472 asection *seg = now_seg;
5473 subsegT subseg = now_subseg;
5474 Elf_Internal_Note i_note;
5475 Elf_External_Note e_note;
5476 asection *note_secp;
5479 /* Create the .note section. */
5480 note_secp = subseg_new (".note", 0);
5481 bfd_set_section_flags (stdoutput,
5483 SEC_HAS_CONTENTS | SEC_READONLY);
5485 /* Process the arch string. */
5486 len = strlen (cpu_arch_name);
5488 i_note.namesz = len + 1;
5490 i_note.type = NT_ARCH;
5491 p = frag_more (sizeof (e_note.namesz));
5492 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5493 p = frag_more (sizeof (e_note.descsz));
5494 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5495 p = frag_more (sizeof (e_note.type));
5496 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5497 p = frag_more (len + 1);
5498 strcpy (p, cpu_arch_name);
5500 frag_align (2, 0, 0);
5502 subseg_set (seg, subseg);
5508 md_undefined_symbol (name)
5511 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5512 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5513 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5514 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5518 if (symbol_find (name))
5519 as_bad (_("GOT already in symbol table"));
5520 GOT_symbol = symbol_new (name, undefined_section,
5521 (valueT) 0, &zero_address_frag);
5528 /* Round up a section size to the appropriate boundary. */
5531 md_section_align (segment, size)
5532 segT segment ATTRIBUTE_UNUSED;
5535 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5536 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5538 /* For a.out, force the section size to be aligned. If we don't do
5539 this, BFD will align it for us, but it will not write out the
5540 final bytes of the section. This may be a bug in BFD, but it is
5541 easier to fix it here since that is how the other a.out targets
5545 align = bfd_get_section_alignment (stdoutput, segment);
5546 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5553 /* On the i386, PC-relative offsets are relative to the start of the
5554 next instruction. That is, the address of the offset, plus its
5555 size, since the offset is always the last part of the insn. */
5558 md_pcrel_from (fixP)
5561 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5568 int ignore ATTRIBUTE_UNUSED;
5572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5574 obj_elf_section_change_hook ();
5576 temp = get_absolute_expression ();
5577 subseg_set (bss_section, (subsegT) temp);
5578 demand_empty_rest_of_line ();
5584 i386_validate_fix (fixp)
5587 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5589 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5593 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5598 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5600 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
5607 tc_gen_reloc (section, fixp)
5608 asection *section ATTRIBUTE_UNUSED;
5612 bfd_reloc_code_real_type code;
5614 switch (fixp->fx_r_type)
5616 case BFD_RELOC_X86_64_PLT32:
5617 case BFD_RELOC_X86_64_GOT32:
5618 case BFD_RELOC_X86_64_GOTPCREL:
5619 case BFD_RELOC_386_PLT32:
5620 case BFD_RELOC_386_GOT32:
5621 case BFD_RELOC_386_GOTOFF:
5622 case BFD_RELOC_386_GOTPC:
5623 case BFD_RELOC_386_TLS_GD:
5624 case BFD_RELOC_386_TLS_LDM:
5625 case BFD_RELOC_386_TLS_LDO_32:
5626 case BFD_RELOC_386_TLS_IE_32:
5627 case BFD_RELOC_386_TLS_IE:
5628 case BFD_RELOC_386_TLS_GOTIE:
5629 case BFD_RELOC_386_TLS_LE_32:
5630 case BFD_RELOC_386_TLS_LE:
5631 case BFD_RELOC_X86_64_TLSGD:
5632 case BFD_RELOC_X86_64_TLSLD:
5633 case BFD_RELOC_X86_64_DTPOFF32:
5634 case BFD_RELOC_X86_64_DTPOFF64:
5635 case BFD_RELOC_X86_64_GOTTPOFF:
5636 case BFD_RELOC_X86_64_TPOFF32:
5637 case BFD_RELOC_X86_64_TPOFF64:
5638 case BFD_RELOC_X86_64_GOTOFF64:
5639 case BFD_RELOC_X86_64_GOTPC32:
5641 case BFD_RELOC_VTABLE_ENTRY:
5642 case BFD_RELOC_VTABLE_INHERIT:
5644 case BFD_RELOC_32_SECREL:
5646 code = fixp->fx_r_type;
5648 case BFD_RELOC_X86_64_32S:
5649 if (!fixp->fx_pcrel)
5651 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5652 code = fixp->fx_r_type;
5658 switch (fixp->fx_size)
5661 as_bad_where (fixp->fx_file, fixp->fx_line,
5662 _("can not do %d byte pc-relative relocation"),
5664 code = BFD_RELOC_32_PCREL;
5666 case 1: code = BFD_RELOC_8_PCREL; break;
5667 case 2: code = BFD_RELOC_16_PCREL; break;
5668 case 4: code = BFD_RELOC_32_PCREL; break;
5670 case 8: code = BFD_RELOC_64_PCREL; break;
5676 switch (fixp->fx_size)
5679 as_bad_where (fixp->fx_file, fixp->fx_line,
5680 _("can not do %d byte relocation"),
5682 code = BFD_RELOC_32;
5684 case 1: code = BFD_RELOC_8; break;
5685 case 2: code = BFD_RELOC_16; break;
5686 case 4: code = BFD_RELOC_32; break;
5688 case 8: code = BFD_RELOC_64; break;
5695 if ((code == BFD_RELOC_32
5696 || code == BFD_RELOC_32_PCREL
5697 || code == BFD_RELOC_X86_64_32S)
5699 && fixp->fx_addsy == GOT_symbol)
5702 code = BFD_RELOC_386_GOTPC;
5704 code = BFD_RELOC_X86_64_GOTPC32;
5707 rel = (arelent *) xmalloc (sizeof (arelent));
5708 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5709 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5711 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5713 if (!use_rela_relocations)
5715 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5716 vtable entry to be used in the relocation's section offset. */
5717 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5718 rel->address = fixp->fx_offset;
5722 /* Use the rela in 64bit mode. */
5725 if (!fixp->fx_pcrel)
5726 rel->addend = fixp->fx_offset;
5730 case BFD_RELOC_X86_64_PLT32:
5731 case BFD_RELOC_X86_64_GOT32:
5732 case BFD_RELOC_X86_64_GOTPCREL:
5733 case BFD_RELOC_X86_64_TLSGD:
5734 case BFD_RELOC_X86_64_TLSLD:
5735 case BFD_RELOC_X86_64_GOTTPOFF:
5736 rel->addend = fixp->fx_offset - fixp->fx_size;
5739 rel->addend = (section->vma
5741 + fixp->fx_addnumber
5742 + md_pcrel_from (fixp));
5747 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5748 if (rel->howto == NULL)
5750 as_bad_where (fixp->fx_file, fixp->fx_line,
5751 _("cannot represent relocation type %s"),
5752 bfd_get_reloc_code_name (code));
5753 /* Set howto to a garbage value so that we can keep going. */
5754 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5755 assert (rel->howto != NULL);
5762 /* Parse operands using Intel syntax. This implements a recursive descent
5763 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5766 FIXME: We do not recognize the full operand grammar defined in the MASM
5767 documentation. In particular, all the structure/union and
5768 high-level macro operands are missing.
5770 Uppercase words are terminals, lower case words are non-terminals.
5771 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5772 bars '|' denote choices. Most grammar productions are implemented in
5773 functions called 'intel_<production>'.
5775 Initial production is 'expr'.
5781 binOp & | AND | \| | OR | ^ | XOR
5783 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5785 constant digits [[ radixOverride ]]
5787 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5825 => expr expr cmpOp e04
5828 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5829 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5831 hexdigit a | b | c | d | e | f
5832 | A | B | C | D | E | F
5838 mulOp * | / | % | MOD | << | SHL | >> | SHR
5842 register specialRegister
5846 segmentRegister CS | DS | ES | FS | GS | SS
5848 specialRegister CR0 | CR2 | CR3 | CR4
5849 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5850 | TR3 | TR4 | TR5 | TR6 | TR7
5852 We simplify the grammar in obvious places (e.g., register parsing is
5853 done by calling parse_register) and eliminate immediate left recursion
5854 to implement a recursive-descent parser.
5858 expr' cmpOp e04 expr'
5909 /* Parsing structure for the intel syntax parser. Used to implement the
5910 semantic actions for the operand grammar. */
5911 struct intel_parser_s
5913 char *op_string; /* The string being parsed. */
5914 int got_a_float; /* Whether the operand is a float. */
5915 int op_modifier; /* Operand modifier. */
5916 int is_mem; /* 1 if operand is memory reference. */
5917 int in_offset; /* >=1 if parsing operand of offset. */
5918 int in_bracket; /* >=1 if parsing operand in brackets. */
5919 const reg_entry *reg; /* Last register reference found. */
5920 char *disp; /* Displacement string being built. */
5921 char *next_operand; /* Resume point when splitting operands. */
5924 static struct intel_parser_s intel_parser;
5926 /* Token structure for parsing intel syntax. */
5929 int code; /* Token code. */
5930 const reg_entry *reg; /* Register entry for register tokens. */
5931 char *str; /* String representation. */
5934 static struct intel_token cur_token, prev_token;
5936 /* Token codes for the intel parser. Since T_SHORT is already used
5937 by COFF, undefine it first to prevent a warning. */
5956 /* Prototypes for intel parser functions. */
5957 static int intel_match_token PARAMS ((int code));
5958 static void intel_get_token PARAMS ((void));
5959 static void intel_putback_token PARAMS ((void));
5960 static int intel_expr PARAMS ((void));
5961 static int intel_e04 PARAMS ((void));
5962 static int intel_e05 PARAMS ((void));
5963 static int intel_e06 PARAMS ((void));
5964 static int intel_e09 PARAMS ((void));
5965 static int intel_bracket_expr PARAMS ((void));
5966 static int intel_e10 PARAMS ((void));
5967 static int intel_e11 PARAMS ((void));
5970 i386_intel_operand (operand_string, got_a_float)
5971 char *operand_string;
5977 p = intel_parser.op_string = xstrdup (operand_string);
5978 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5982 /* Initialize token holders. */
5983 cur_token.code = prev_token.code = T_NIL;
5984 cur_token.reg = prev_token.reg = NULL;
5985 cur_token.str = prev_token.str = NULL;
5987 /* Initialize parser structure. */
5988 intel_parser.got_a_float = got_a_float;
5989 intel_parser.op_modifier = 0;
5990 intel_parser.is_mem = 0;
5991 intel_parser.in_offset = 0;
5992 intel_parser.in_bracket = 0;
5993 intel_parser.reg = NULL;
5994 intel_parser.disp[0] = '\0';
5995 intel_parser.next_operand = NULL;
5997 /* Read the first token and start the parser. */
5999 ret = intel_expr ();
6004 if (cur_token.code != T_NIL)
6006 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6007 current_templates->start->name, cur_token.str);
6010 /* If we found a memory reference, hand it over to i386_displacement
6011 to fill in the rest of the operand fields. */
6012 else if (intel_parser.is_mem)
6014 if ((i.mem_operands == 1
6015 && (current_templates->start->opcode_modifier & IsString) == 0)
6016 || i.mem_operands == 2)
6018 as_bad (_("too many memory references for '%s'"),
6019 current_templates->start->name);
6024 char *s = intel_parser.disp;
6027 if (!quiet_warnings && intel_parser.is_mem < 0)
6028 /* See the comments in intel_bracket_expr. */
6029 as_warn (_("Treating `%s' as memory reference"), operand_string);
6031 /* Add the displacement expression. */
6033 ret = i386_displacement (s, s + strlen (s));
6036 /* Swap base and index in 16-bit memory operands like
6037 [si+bx]. Since i386_index_check is also used in AT&T
6038 mode we have to do that here. */
6041 && (i.base_reg->reg_type & Reg16)
6042 && (i.index_reg->reg_type & Reg16)
6043 && i.base_reg->reg_num >= 6
6044 && i.index_reg->reg_num < 6)
6046 const reg_entry *base = i.index_reg;
6048 i.index_reg = i.base_reg;
6051 ret = i386_index_check (operand_string);
6056 /* Constant and OFFSET expressions are handled by i386_immediate. */
6057 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6058 || intel_parser.reg == NULL)
6059 ret = i386_immediate (intel_parser.disp);
6061 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6063 if (!ret || !intel_parser.next_operand)
6065 intel_parser.op_string = intel_parser.next_operand;
6066 this_operand = i.operands++;
6070 free (intel_parser.disp);
6075 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6079 expr' cmpOp e04 expr'
6084 /* XXX Implement the comparison operators. */
6085 return intel_e04 ();
6102 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6103 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6105 if (cur_token.code == '+')
6107 else if (cur_token.code == '-')
6108 nregs = NUM_ADDRESS_REGS;
6112 strcat (intel_parser.disp, cur_token.str);
6113 intel_match_token (cur_token.code);
6124 int nregs = ~NUM_ADDRESS_REGS;
6131 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6135 str[0] = cur_token.code;
6137 strcat (intel_parser.disp, str);
6142 intel_match_token (cur_token.code);
6147 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6148 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6159 int nregs = ~NUM_ADDRESS_REGS;
6166 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6170 str[0] = cur_token.code;
6172 strcat (intel_parser.disp, str);
6174 else if (cur_token.code == T_SHL)
6175 strcat (intel_parser.disp, "<<");
6176 else if (cur_token.code == T_SHR)
6177 strcat (intel_parser.disp, ">>");
6181 intel_match_token (cur_token.code);
6186 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6187 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6205 int nregs = ~NUM_ADDRESS_REGS;
6210 /* Don't consume constants here. */
6211 if (cur_token.code == '+' || cur_token.code == '-')
6213 /* Need to look one token ahead - if the next token
6214 is a constant, the current token is its sign. */
6217 intel_match_token (cur_token.code);
6218 next_code = cur_token.code;
6219 intel_putback_token ();
6220 if (next_code == T_CONST)
6224 /* e09 OFFSET e09 */
6225 if (cur_token.code == T_OFFSET)
6228 ++intel_parser.in_offset;
6232 else if (cur_token.code == T_SHORT)
6233 intel_parser.op_modifier |= 1 << T_SHORT;
6236 else if (cur_token.code == '+')
6237 strcat (intel_parser.disp, "+");
6242 else if (cur_token.code == '-' || cur_token.code == '~')
6248 str[0] = cur_token.code;
6250 strcat (intel_parser.disp, str);
6257 intel_match_token (cur_token.code);
6265 /* e09' PTR e10 e09' */
6266 if (cur_token.code == T_PTR)
6270 if (prev_token.code == T_BYTE)
6271 suffix = BYTE_MNEM_SUFFIX;
6273 else if (prev_token.code == T_WORD)
6275 if (current_templates->start->name[0] == 'l'
6276 && current_templates->start->name[2] == 's'
6277 && current_templates->start->name[3] == 0)
6278 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6279 else if (intel_parser.got_a_float == 2) /* "fi..." */
6280 suffix = SHORT_MNEM_SUFFIX;
6282 suffix = WORD_MNEM_SUFFIX;
6285 else if (prev_token.code == T_DWORD)
6287 if (current_templates->start->name[0] == 'l'
6288 && current_templates->start->name[2] == 's'
6289 && current_templates->start->name[3] == 0)
6290 suffix = WORD_MNEM_SUFFIX;
6291 else if (flag_code == CODE_16BIT
6292 && (current_templates->start->opcode_modifier
6293 & (Jump | JumpDword)))
6294 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6295 else if (intel_parser.got_a_float == 1) /* "f..." */
6296 suffix = SHORT_MNEM_SUFFIX;
6298 suffix = LONG_MNEM_SUFFIX;
6301 else if (prev_token.code == T_FWORD)
6303 if (current_templates->start->name[0] == 'l'
6304 && current_templates->start->name[2] == 's'
6305 && current_templates->start->name[3] == 0)
6306 suffix = LONG_MNEM_SUFFIX;
6307 else if (!intel_parser.got_a_float)
6309 if (flag_code == CODE_16BIT)
6310 add_prefix (DATA_PREFIX_OPCODE);
6311 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6314 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6317 else if (prev_token.code == T_QWORD)
6319 if (intel_parser.got_a_float == 1) /* "f..." */
6320 suffix = LONG_MNEM_SUFFIX;
6322 suffix = QWORD_MNEM_SUFFIX;
6325 else if (prev_token.code == T_TBYTE)
6327 if (intel_parser.got_a_float == 1)
6328 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6330 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6333 else if (prev_token.code == T_XMMWORD)
6335 /* XXX ignored for now, but accepted since gcc uses it */
6341 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6345 /* Operands for jump/call using 'ptr' notation denote absolute
6347 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6348 i.types[this_operand] |= JumpAbsolute;
6350 if (current_templates->start->base_opcode == 0x8d /* lea */)
6354 else if (i.suffix != suffix)
6356 as_bad (_("Conflicting operand modifiers"));
6362 /* e09' : e10 e09' */
6363 else if (cur_token.code == ':')
6365 if (prev_token.code != T_REG)
6367 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6368 segment/group identifier (which we don't have), using comma
6369 as the operand separator there is even less consistent, since
6370 there all branches only have a single operand. */
6371 if (this_operand != 0
6372 || intel_parser.in_offset
6373 || intel_parser.in_bracket
6374 || (!(current_templates->start->opcode_modifier
6375 & (Jump|JumpDword|JumpInterSegment))
6376 && !(current_templates->start->operand_types[0]
6378 return intel_match_token (T_NIL);
6379 /* Remember the start of the 2nd operand and terminate 1st
6381 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6382 another expression), but it gets at least the simplest case
6383 (a plain number or symbol on the left side) right. */
6384 intel_parser.next_operand = intel_parser.op_string;
6385 *--intel_parser.op_string = '\0';
6386 return intel_match_token (':');
6394 intel_match_token (cur_token.code);
6400 --intel_parser.in_offset;
6403 if (NUM_ADDRESS_REGS > nregs)
6405 as_bad (_("Invalid operand to `OFFSET'"));
6408 intel_parser.op_modifier |= 1 << T_OFFSET;
6411 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6412 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6417 intel_bracket_expr ()
6419 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6420 const char *start = intel_parser.op_string;
6423 if (i.op[this_operand].regs)
6424 return intel_match_token (T_NIL);
6426 intel_match_token ('[');
6428 /* Mark as a memory operand only if it's not already known to be an
6429 offset expression. If it's an offset expression, we need to keep
6431 if (!intel_parser.in_offset)
6433 ++intel_parser.in_bracket;
6435 /* Operands for jump/call inside brackets denote absolute addresses. */
6436 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6437 i.types[this_operand] |= JumpAbsolute;
6439 /* Unfortunately gas always diverged from MASM in a respect that can't
6440 be easily fixed without risking to break code sequences likely to be
6441 encountered (the testsuite even check for this): MASM doesn't consider
6442 an expression inside brackets unconditionally as a memory reference.
6443 When that is e.g. a constant, an offset expression, or the sum of the
6444 two, this is still taken as a constant load. gas, however, always
6445 treated these as memory references. As a compromise, we'll try to make
6446 offset expressions inside brackets work the MASM way (since that's
6447 less likely to be found in real world code), but make constants alone
6448 continue to work the traditional gas way. In either case, issue a
6450 intel_parser.op_modifier &= ~was_offset;
6453 strcat (intel_parser.disp, "[");
6455 /* Add a '+' to the displacement string if necessary. */
6456 if (*intel_parser.disp != '\0'
6457 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6458 strcat (intel_parser.disp, "+");
6461 && (len = intel_parser.op_string - start - 1,
6462 intel_match_token (']')))
6464 /* Preserve brackets when the operand is an offset expression. */
6465 if (intel_parser.in_offset)
6466 strcat (intel_parser.disp, "]");
6469 --intel_parser.in_bracket;
6470 if (i.base_reg || i.index_reg)
6471 intel_parser.is_mem = 1;
6472 if (!intel_parser.is_mem)
6474 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6475 /* Defer the warning until all of the operand was parsed. */
6476 intel_parser.is_mem = -1;
6477 else if (!quiet_warnings)
6478 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6481 intel_parser.op_modifier |= was_offset;
6498 while (cur_token.code == '[')
6500 if (!intel_bracket_expr ())
6525 switch (cur_token.code)
6529 intel_match_token ('(');
6530 strcat (intel_parser.disp, "(");
6532 if (intel_expr () && intel_match_token (')'))
6534 strcat (intel_parser.disp, ")");
6541 return intel_bracket_expr ();
6546 strcat (intel_parser.disp, cur_token.str);
6547 intel_match_token (cur_token.code);
6549 /* Mark as a memory operand only if it's not already known to be an
6550 offset expression. */
6551 if (!intel_parser.in_offset)
6552 intel_parser.is_mem = 1;
6559 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6561 intel_match_token (T_REG);
6563 /* Check for segment change. */
6564 if (cur_token.code == ':')
6566 if (!(reg->reg_type & (SReg2 | SReg3)))
6568 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6571 else if (i.seg[i.mem_operands])
6572 as_warn (_("Extra segment override ignored"));
6575 if (!intel_parser.in_offset)
6576 intel_parser.is_mem = 1;
6577 switch (reg->reg_num)
6580 i.seg[i.mem_operands] = &es;
6583 i.seg[i.mem_operands] = &cs;
6586 i.seg[i.mem_operands] = &ss;
6589 i.seg[i.mem_operands] = &ds;
6592 i.seg[i.mem_operands] = &fs;
6595 i.seg[i.mem_operands] = &gs;
6601 /* Not a segment register. Check for register scaling. */
6602 else if (cur_token.code == '*')
6604 if (!intel_parser.in_bracket)
6606 as_bad (_("Register scaling only allowed in memory operands"));
6610 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6611 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6612 else if (i.index_reg)
6613 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6615 /* What follows must be a valid scale. */
6616 intel_match_token ('*');
6618 i.types[this_operand] |= BaseIndex;
6620 /* Set the scale after setting the register (otherwise,
6621 i386_scale will complain) */
6622 if (cur_token.code == '+' || cur_token.code == '-')
6624 char *str, sign = cur_token.code;
6625 intel_match_token (cur_token.code);
6626 if (cur_token.code != T_CONST)
6628 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6632 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6633 strcpy (str + 1, cur_token.str);
6635 if (!i386_scale (str))
6639 else if (!i386_scale (cur_token.str))
6641 intel_match_token (cur_token.code);
6644 /* No scaling. If this is a memory operand, the register is either a
6645 base register (first occurrence) or an index register (second
6647 else if (intel_parser.in_bracket)
6652 else if (!i.index_reg)
6656 as_bad (_("Too many register references in memory operand"));
6660 i.types[this_operand] |= BaseIndex;
6663 /* It's neither base nor index. */
6664 else if (!intel_parser.in_offset && !intel_parser.is_mem)
6666 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6667 i.op[this_operand].regs = reg;
6672 as_bad (_("Invalid use of register"));
6676 /* Since registers are not part of the displacement string (except
6677 when we're parsing offset operands), we may need to remove any
6678 preceding '+' from the displacement string. */
6679 if (*intel_parser.disp != '\0'
6680 && !intel_parser.in_offset)
6682 char *s = intel_parser.disp;
6683 s += strlen (s) - 1;
6706 intel_match_token (cur_token.code);
6708 if (cur_token.code == T_PTR)
6711 /* It must have been an identifier. */
6712 intel_putback_token ();
6713 cur_token.code = T_ID;
6719 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
6723 /* The identifier represents a memory reference only if it's not
6724 preceded by an offset modifier and if it's not an equate. */
6725 symbolP = symbol_find(cur_token.str);
6726 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6727 intel_parser.is_mem = 1;
6735 char *save_str, sign = 0;
6737 /* Allow constants that start with `+' or `-'. */
6738 if (cur_token.code == '-' || cur_token.code == '+')
6740 sign = cur_token.code;
6741 intel_match_token (cur_token.code);
6742 if (cur_token.code != T_CONST)
6744 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6750 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6751 strcpy (save_str + !!sign, cur_token.str);
6755 /* Get the next token to check for register scaling. */
6756 intel_match_token (cur_token.code);
6758 /* Check if this constant is a scaling factor for an index register. */
6759 if (cur_token.code == '*')
6761 if (intel_match_token ('*') && cur_token.code == T_REG)
6763 const reg_entry *reg = cur_token.reg;
6765 if (!intel_parser.in_bracket)
6767 as_bad (_("Register scaling only allowed in memory operands"));
6771 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6772 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6773 else if (i.index_reg)
6774 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6776 /* The constant is followed by `* reg', so it must be
6779 i.types[this_operand] |= BaseIndex;
6781 /* Set the scale after setting the register (otherwise,
6782 i386_scale will complain) */
6783 if (!i386_scale (save_str))
6785 intel_match_token (T_REG);
6787 /* Since registers are not part of the displacement
6788 string, we may need to remove any preceding '+' from
6789 the displacement string. */
6790 if (*intel_parser.disp != '\0')
6792 char *s = intel_parser.disp;
6793 s += strlen (s) - 1;
6803 /* The constant was not used for register scaling. Since we have
6804 already consumed the token following `*' we now need to put it
6805 back in the stream. */
6806 intel_putback_token ();
6809 /* Add the constant to the displacement string. */
6810 strcat (intel_parser.disp, save_str);
6817 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6821 /* Match the given token against cur_token. If they match, read the next
6822 token from the operand string. */
6824 intel_match_token (code)
6827 if (cur_token.code == code)
6834 as_bad (_("Unexpected token `%s'"), cur_token.str);
6839 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6844 const reg_entry *reg;
6845 struct intel_token new_token;
6847 new_token.code = T_NIL;
6848 new_token.reg = NULL;
6849 new_token.str = NULL;
6851 /* Free the memory allocated to the previous token and move
6852 cur_token to prev_token. */
6854 free (prev_token.str);
6856 prev_token = cur_token;
6858 /* Skip whitespace. */
6859 while (is_space_char (*intel_parser.op_string))
6860 intel_parser.op_string++;
6862 /* Return an empty token if we find nothing else on the line. */
6863 if (*intel_parser.op_string == '\0')
6865 cur_token = new_token;
6869 /* The new token cannot be larger than the remainder of the operand
6871 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
6872 new_token.str[0] = '\0';
6874 if (strchr ("0123456789", *intel_parser.op_string))
6876 char *p = new_token.str;
6877 char *q = intel_parser.op_string;
6878 new_token.code = T_CONST;
6880 /* Allow any kind of identifier char to encompass floating point and
6881 hexadecimal numbers. */
6882 while (is_identifier_char (*q))
6886 /* Recognize special symbol names [0-9][bf]. */
6887 if (strlen (intel_parser.op_string) == 2
6888 && (intel_parser.op_string[1] == 'b'
6889 || intel_parser.op_string[1] == 'f'))
6890 new_token.code = T_ID;
6893 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
6895 size_t len = end_op - intel_parser.op_string;
6897 new_token.code = T_REG;
6898 new_token.reg = reg;
6900 memcpy (new_token.str, intel_parser.op_string, len);
6901 new_token.str[len] = '\0';
6904 else if (is_identifier_char (*intel_parser.op_string))
6906 char *p = new_token.str;
6907 char *q = intel_parser.op_string;
6909 /* A '.' or '$' followed by an identifier char is an identifier.
6910 Otherwise, it's operator '.' followed by an expression. */
6911 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6913 new_token.code = '.';
6914 new_token.str[0] = '.';
6915 new_token.str[1] = '\0';
6919 while (is_identifier_char (*q) || *q == '@')
6923 if (strcasecmp (new_token.str, "NOT") == 0)
6924 new_token.code = '~';
6926 else if (strcasecmp (new_token.str, "MOD") == 0)
6927 new_token.code = '%';
6929 else if (strcasecmp (new_token.str, "AND") == 0)
6930 new_token.code = '&';
6932 else if (strcasecmp (new_token.str, "OR") == 0)
6933 new_token.code = '|';
6935 else if (strcasecmp (new_token.str, "XOR") == 0)
6936 new_token.code = '^';
6938 else if (strcasecmp (new_token.str, "SHL") == 0)
6939 new_token.code = T_SHL;
6941 else if (strcasecmp (new_token.str, "SHR") == 0)
6942 new_token.code = T_SHR;
6944 else if (strcasecmp (new_token.str, "BYTE") == 0)
6945 new_token.code = T_BYTE;
6947 else if (strcasecmp (new_token.str, "WORD") == 0)
6948 new_token.code = T_WORD;
6950 else if (strcasecmp (new_token.str, "DWORD") == 0)
6951 new_token.code = T_DWORD;
6953 else if (strcasecmp (new_token.str, "FWORD") == 0)
6954 new_token.code = T_FWORD;
6956 else if (strcasecmp (new_token.str, "QWORD") == 0)
6957 new_token.code = T_QWORD;
6959 else if (strcasecmp (new_token.str, "TBYTE") == 0
6960 /* XXX remove (gcc still uses it) */
6961 || strcasecmp (new_token.str, "XWORD") == 0)
6962 new_token.code = T_TBYTE;
6964 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6965 || strcasecmp (new_token.str, "OWORD") == 0)
6966 new_token.code = T_XMMWORD;
6968 else if (strcasecmp (new_token.str, "PTR") == 0)
6969 new_token.code = T_PTR;
6971 else if (strcasecmp (new_token.str, "SHORT") == 0)
6972 new_token.code = T_SHORT;
6974 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6976 new_token.code = T_OFFSET;
6978 /* ??? This is not mentioned in the MASM grammar but gcc
6979 makes use of it with -mintel-syntax. OFFSET may be
6980 followed by FLAT: */
6981 if (strncasecmp (q, " FLAT:", 6) == 0)
6982 strcat (new_token.str, " FLAT:");
6985 /* ??? This is not mentioned in the MASM grammar. */
6986 else if (strcasecmp (new_token.str, "FLAT") == 0)
6988 new_token.code = T_OFFSET;
6990 strcat (new_token.str, ":");
6992 as_bad (_("`:' expected"));
6996 new_token.code = T_ID;
7000 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7002 new_token.code = *intel_parser.op_string;
7003 new_token.str[0] = *intel_parser.op_string;
7004 new_token.str[1] = '\0';
7007 else if (strchr ("<>", *intel_parser.op_string)
7008 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7010 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7011 new_token.str[0] = *intel_parser.op_string;
7012 new_token.str[1] = *intel_parser.op_string;
7013 new_token.str[2] = '\0';
7017 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7019 intel_parser.op_string += strlen (new_token.str);
7020 cur_token = new_token;
7023 /* Put cur_token back into the token stream and make cur_token point to
7026 intel_putback_token ()
7028 if (cur_token.code != T_NIL)
7030 intel_parser.op_string -= strlen (cur_token.str);
7031 free (cur_token.str);
7033 cur_token = prev_token;
7035 /* Forget prev_token. */
7036 prev_token.code = T_NIL;
7037 prev_token.reg = NULL;
7038 prev_token.str = NULL;
7042 tc_x86_regname_to_dw2regnum (const char *regname)
7044 unsigned int regnum;
7045 unsigned int regnames_count;
7046 static const char *const regnames_32[] =
7048 "eax", "ecx", "edx", "ebx",
7049 "esp", "ebp", "esi", "edi",
7050 "eip", "eflags", NULL,
7051 "st0", "st1", "st2", "st3",
7052 "st4", "st5", "st6", "st7",
7054 "xmm0", "xmm1", "xmm2", "xmm3",
7055 "xmm4", "xmm5", "xmm6", "xmm7",
7056 "mm0", "mm1", "mm2", "mm3",
7057 "mm4", "mm5", "mm6", "mm7",
7058 "fcw", "fsw", "mxcsr",
7059 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7062 static const char *const regnames_64[] =
7064 "rax", "rdx", "rcx", "rbx",
7065 "rsi", "rdi", "rbp", "rsp",
7066 "r8", "r9", "r10", "r11",
7067 "r12", "r13", "r14", "r15",
7069 "xmm0", "xmm1", "xmm2", "xmm3",
7070 "xmm4", "xmm5", "xmm6", "xmm7",
7071 "xmm8", "xmm9", "xmm10", "xmm11",
7072 "xmm12", "xmm13", "xmm14", "xmm15",
7073 "st0", "st1", "st2", "st3",
7074 "st4", "st5", "st6", "st7",
7075 "mm0", "mm1", "mm2", "mm3",
7076 "mm4", "mm5", "mm6", "mm7",
7078 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7079 "fs.base", "gs.base", NULL, NULL,
7081 "mxcsr", "fcw", "fsw"
7083 const char *const *regnames;
7085 if (flag_code == CODE_64BIT)
7087 regnames = regnames_64;
7088 regnames_count = ARRAY_SIZE (regnames_64);
7092 regnames = regnames_32;
7093 regnames_count = ARRAY_SIZE (regnames_32);
7096 for (regnum = 0; regnum < regnames_count; regnum++)
7097 if (regnames[regnum] != NULL
7098 && strcmp (regname, regnames[regnum]) == 0)
7105 tc_x86_frame_initial_instructions (void)
7107 static unsigned int sp_regno;
7110 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7113 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7114 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7118 i386_elf_section_type (const char *str, size_t len)
7120 if (flag_code == CODE_64BIT
7121 && len == sizeof ("unwind") - 1
7122 && strncmp (str, "unwind", 6) == 0)
7123 return SHT_X86_64_UNWIND;
7130 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7134 expr.X_op = O_secrel;
7135 expr.X_add_symbol = symbol;
7136 expr.X_add_number = 0;
7137 emit_expr (&expr, size);
7141 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7142 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7145 x86_64_section_letter (int letter, char **ptr_msg)
7147 if (flag_code == CODE_64BIT)
7150 return SHF_X86_64_LARGE;
7152 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7155 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7160 x86_64_section_word (char *str, size_t len)
7162 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7163 return SHF_X86_64_LARGE;
7169 handle_large_common (int small ATTRIBUTE_UNUSED)
7171 if (flag_code != CODE_64BIT)
7173 s_comm_internal (0, elf_common_parse);
7174 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7178 static segT lbss_section;
7179 asection *saved_com_section_ptr = elf_com_section_ptr;
7180 asection *saved_bss_section = bss_section;
7182 if (lbss_section == NULL)
7184 flagword applicable;
7186 subsegT subseg = now_subseg;
7188 /* The .lbss section is for local .largecomm symbols. */
7189 lbss_section = subseg_new (".lbss", 0);
7190 applicable = bfd_applicable_section_flags (stdoutput);
7191 bfd_set_section_flags (stdoutput, lbss_section,
7192 applicable & SEC_ALLOC);
7193 seg_info (lbss_section)->bss = 1;
7195 subseg_set (seg, subseg);
7198 elf_com_section_ptr = &_bfd_elf_large_com_section;
7199 bss_section = lbss_section;
7201 s_comm_internal (0, elf_common_parse);
7203 elf_com_section_ptr = saved_com_section_ptr;
7204 bss_section = saved_bss_section;
7207 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */