1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 unsigned int negated; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c);
153 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS *);
160 static int i386_intel_parse_name (const char *, expressionS *);
161 static const reg_entry *parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template *match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry *build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS *, offsetT);
180 static void output_disp (fragS *, offsetT);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED);
188 static const char *default_arch = DEFAULT_ARCH;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry *regs;
254 operand_size_mismatch,
255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
261 unsupported_with_intel_mnemonic,
264 invalid_vsib_address,
265 invalid_vector_register_set,
266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
271 mask_not_on_destination,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types[MAX_OPERANDS];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op[MAX_OPERANDS];
304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry *seg[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation *mask;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default = 0,
358 const char *rep_prefix;
361 const char *hle_prefix;
363 /* Have BND prefix. */
364 const char *bnd_prefix;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error;
373 typedef struct _i386_insn i386_insn;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable[] =
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars = "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars = "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars[] = "#/";
435 const char line_separator_chars[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars[256];
448 static char register_chars[256];
449 static char operand_chars[256];
450 static char identifier_chars[256];
451 static char digit_chars[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack[32];
469 static char *save_stack_p;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates *current_templates;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
485 /* Current operand we are working on. */
486 static int this_operand = -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code;
497 static unsigned int object_64bit;
498 static unsigned int disallow_64bit_reloc;
499 static int use_rela_relocations = 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi = I386_ABI;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj = 0;
521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
522 /* 1 if generating code for a shared library. */
523 static int shared = 0;
526 /* 1 for intel syntax,
528 static int intel_syntax = 0;
530 /* 1 for intel mnemonic,
531 0 if att mnemonic. */
532 static int intel_mnemonic = !SYSV386_COMPAT;
534 /* 1 if support old (<= 2.8.1) versions of gcc. */
535 static int old_gcc = OLDGCC_COMPAT;
537 /* 1 if pseudo registers are permitted. */
538 static int allow_pseudo_reg = 0;
540 /* 1 if register prefix % not required. */
541 static int allow_naked_reg = 0;
543 /* 1 if the assembler should add BND prefix for all control-tranferring
544 instructions supporting it, even if this prefix wasn't specified
546 static int add_bnd_prefix = 0;
548 /* 1 if pseudo index register, eiz/riz, is allowed . */
549 static int allow_index_reg = 0;
551 /* 1 if the assembler should ignore LOCK prefix, even if it was
552 specified explicitly. */
553 static int omit_lock_prefix = 0;
555 static enum check_kind
561 sse_check, operand_check = check_warning;
563 /* Register prefix used for error message. */
564 static const char *register_prefix = "%";
566 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
567 leave, push, and pop instructions so that gcc has the same stack
568 frame as in 32 bit mode. */
569 static char stackop_size = '\0';
571 /* Non-zero to optimize code alignment. */
572 int optimize_align_code = 1;
574 /* Non-zero to quieten some warnings. */
575 static int quiet_warnings = 0;
578 static const char *cpu_arch_name = NULL;
579 static char *cpu_sub_arch_name = NULL;
581 /* CPU feature flags. */
582 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
584 /* If we have selected a cpu we are generating instructions for. */
585 static int cpu_arch_tune_set = 0;
587 /* Cpu we are generating instructions for. */
588 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
590 /* CPU feature flags of cpu we are generating instructions for. */
591 static i386_cpu_flags cpu_arch_tune_flags;
593 /* CPU instruction set architecture used. */
594 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
596 /* CPU feature flags of instruction set architecture used. */
597 i386_cpu_flags cpu_arch_isa_flags;
599 /* If set, conditional jumps are not automatically promoted to handle
600 larger than a byte offset. */
601 static unsigned int no_cond_jump_promotion = 0;
603 /* Encode SSE instructions with VEX prefix. */
604 static unsigned int sse2avx;
606 /* Encode scalar AVX instructions with specific vector length. */
613 /* Encode scalar EVEX LIG instructions with specific vector length. */
621 /* Encode EVEX WIG instructions with specific evex.w. */
628 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
629 static enum rc_type evexrcig = rne;
631 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
632 static symbolS *GOT_symbol;
634 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
635 unsigned int x86_dwarf2_return_column;
637 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
638 int x86_cie_data_alignment;
640 /* Interface to relax_segment.
641 There are 3 major relax states for 386 jump insns because the
642 different types of jumps add different sizes to frags when we're
643 figuring out what sort of jump to choose to reach a given label. */
646 #define UNCOND_JUMP 0
648 #define COND_JUMP86 2
653 #define SMALL16 (SMALL | CODE16)
655 #define BIG16 (BIG | CODE16)
659 #define INLINE __inline__
665 #define ENCODE_RELAX_STATE(type, size) \
666 ((relax_substateT) (((type) << 2) | (size)))
667 #define TYPE_FROM_RELAX_STATE(s) \
669 #define DISP_SIZE_FROM_RELAX_STATE(s) \
670 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
672 /* This table is used by relax_frag to promote short jumps to long
673 ones where necessary. SMALL (short) jumps may be promoted to BIG
674 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
675 don't allow a short jump in a 32 bit code segment to be promoted to
676 a 16 bit offset jump because it's slower (requires data size
677 prefix), and doesn't work, unless the destination is in the bottom
678 64k of the code segment (The top 16 bits of eip are zeroed). */
680 const relax_typeS md_relax_table[] =
683 1) most positive reach of this state,
684 2) most negative reach of this state,
685 3) how many bytes this mode will have in the variable part of the frag
686 4) which index into the table to try if we can't fit into this one. */
688 /* UNCOND_JUMP states. */
689 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
691 /* dword jmp adds 4 bytes to frag:
692 0 extra opcode bytes, 4 displacement bytes. */
694 /* word jmp adds 2 byte2 to frag:
695 0 extra opcode bytes, 2 displacement bytes. */
698 /* COND_JUMP states. */
699 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
701 /* dword conditionals adds 5 bytes to frag:
702 1 extra opcode byte, 4 displacement bytes. */
704 /* word conditionals add 3 bytes to frag:
705 1 extra opcode byte, 2 displacement bytes. */
708 /* COND_JUMP86 states. */
709 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
711 /* dword conditionals adds 5 bytes to frag:
712 1 extra opcode byte, 4 displacement bytes. */
714 /* word conditionals add 4 bytes to frag:
715 1 displacement byte and a 3 byte long branch insn. */
719 static const arch_entry cpu_arch[] =
721 /* Do not replace the first two entries - i386_target_format()
722 relies on them being there in this order. */
723 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
724 CPU_GENERIC32_FLAGS, 0, 0 },
725 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
726 CPU_GENERIC64_FLAGS, 0, 0 },
727 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
728 CPU_NONE_FLAGS, 0, 0 },
729 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
730 CPU_I186_FLAGS, 0, 0 },
731 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
732 CPU_I286_FLAGS, 0, 0 },
733 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
734 CPU_I386_FLAGS, 0, 0 },
735 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
736 CPU_I486_FLAGS, 0, 0 },
737 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
738 CPU_I586_FLAGS, 0, 0 },
739 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
740 CPU_I686_FLAGS, 0, 0 },
741 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
742 CPU_I586_FLAGS, 0, 0 },
743 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
744 CPU_PENTIUMPRO_FLAGS, 0, 0 },
745 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
746 CPU_P2_FLAGS, 0, 0 },
747 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
748 CPU_P3_FLAGS, 0, 0 },
749 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
750 CPU_P4_FLAGS, 0, 0 },
751 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
752 CPU_CORE_FLAGS, 0, 0 },
753 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
754 CPU_NOCONA_FLAGS, 0, 0 },
755 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
756 CPU_CORE_FLAGS, 1, 0 },
757 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
758 CPU_CORE_FLAGS, 0, 0 },
759 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
760 CPU_CORE2_FLAGS, 1, 0 },
761 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
762 CPU_CORE2_FLAGS, 0, 0 },
763 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
764 CPU_COREI7_FLAGS, 0, 0 },
765 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
766 CPU_L1OM_FLAGS, 0, 0 },
767 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
768 CPU_K1OM_FLAGS, 0, 0 },
769 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
770 CPU_IAMCU_FLAGS, 0, 0 },
771 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
772 CPU_K6_FLAGS, 0, 0 },
773 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
774 CPU_K6_2_FLAGS, 0, 0 },
775 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
776 CPU_ATHLON_FLAGS, 0, 0 },
777 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
778 CPU_K8_FLAGS, 1, 0 },
779 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
780 CPU_K8_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
782 CPU_K8_FLAGS, 0, 0 },
783 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
784 CPU_AMDFAM10_FLAGS, 0, 0 },
785 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
786 CPU_BDVER1_FLAGS, 0, 0 },
787 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
788 CPU_BDVER2_FLAGS, 0, 0 },
789 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
790 CPU_BDVER3_FLAGS, 0, 0 },
791 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
792 CPU_BDVER4_FLAGS, 0, 0 },
793 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
794 CPU_ZNVER1_FLAGS, 0, 0 },
795 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
796 CPU_BTVER1_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
798 CPU_BTVER2_FLAGS, 0, 0 },
799 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
800 CPU_8087_FLAGS, 0, 0 },
801 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
802 CPU_287_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
804 CPU_387_FLAGS, 0, 0 },
805 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
806 CPU_ANY87_FLAGS, 0, 1 },
807 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
808 CPU_MMX_FLAGS, 0, 0 },
809 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
810 CPU_3DNOWA_FLAGS, 0, 1 },
811 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
812 CPU_SSE_FLAGS, 0, 0 },
813 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
814 CPU_SSE2_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
816 CPU_SSE3_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
818 CPU_SSSE3_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
820 CPU_SSE4_1_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
822 CPU_SSE4_2_FLAGS, 0, 0 },
823 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
824 CPU_SSE4_2_FLAGS, 0, 0 },
825 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
826 CPU_ANY_SSE_FLAGS, 0, 1 },
827 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
828 CPU_AVX_FLAGS, 0, 0 },
829 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
830 CPU_AVX2_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
832 CPU_AVX512F_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
834 CPU_AVX512CD_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
836 CPU_AVX512ER_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
838 CPU_AVX512PF_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
840 CPU_AVX512DQ_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
842 CPU_AVX512BW_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
844 CPU_AVX512VL_FLAGS, 0, 0 },
845 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
846 CPU_ANY_AVX_FLAGS, 0, 1 },
847 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
848 CPU_VMX_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
850 CPU_VMFUNC_FLAGS, 0, 0 },
851 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
852 CPU_SMX_FLAGS, 0, 0 },
853 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
854 CPU_XSAVE_FLAGS, 0, 0 },
855 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
856 CPU_XSAVEOPT_FLAGS, 0, 0 },
857 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
858 CPU_XSAVEC_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
860 CPU_XSAVES_FLAGS, 0, 0 },
861 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
862 CPU_AES_FLAGS, 0, 0 },
863 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
864 CPU_PCLMUL_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
866 CPU_PCLMUL_FLAGS, 1, 0 },
867 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
868 CPU_FSGSBASE_FLAGS, 0, 0 },
869 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
870 CPU_RDRND_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
872 CPU_F16C_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
874 CPU_BMI2_FLAGS, 0, 0 },
875 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
876 CPU_FMA_FLAGS, 0, 0 },
877 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
878 CPU_FMA4_FLAGS, 0, 0 },
879 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
880 CPU_XOP_FLAGS, 0, 0 },
881 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
882 CPU_LWP_FLAGS, 0, 0 },
883 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
884 CPU_MOVBE_FLAGS, 0, 0 },
885 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
886 CPU_CX16_FLAGS, 0, 0 },
887 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
888 CPU_EPT_FLAGS, 0, 0 },
889 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
890 CPU_LZCNT_FLAGS, 0, 0 },
891 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
892 CPU_HLE_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
894 CPU_RTM_FLAGS, 0, 0 },
895 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
896 CPU_INVPCID_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
898 CPU_CLFLUSH_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
900 CPU_NOP_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
902 CPU_SYSCALL_FLAGS, 0, 0 },
903 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
904 CPU_RDTSCP_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
906 CPU_3DNOW_FLAGS, 0, 0 },
907 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
908 CPU_3DNOWA_FLAGS, 0, 0 },
909 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
910 CPU_PADLOCK_FLAGS, 0, 0 },
911 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
912 CPU_SVME_FLAGS, 1, 0 },
913 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
914 CPU_SVME_FLAGS, 0, 0 },
915 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
916 CPU_SSE4A_FLAGS, 0, 0 },
917 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
918 CPU_ABM_FLAGS, 0, 0 },
919 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
920 CPU_BMI_FLAGS, 0, 0 },
921 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
922 CPU_TBM_FLAGS, 0, 0 },
923 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
924 CPU_ADX_FLAGS, 0, 0 },
925 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
926 CPU_RDSEED_FLAGS, 0, 0 },
927 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
928 CPU_PRFCHW_FLAGS, 0, 0 },
929 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
930 CPU_SMAP_FLAGS, 0, 0 },
931 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
932 CPU_MPX_FLAGS, 0, 0 },
933 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
934 CPU_SHA_FLAGS, 0, 0 },
935 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
936 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
937 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
938 CPU_PREFETCHWT1_FLAGS, 0, 0 },
939 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
940 CPU_SE1_FLAGS, 0, 0 },
941 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
942 CPU_CLWB_FLAGS, 0, 0 },
943 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
944 CPU_PCOMMIT_FLAGS, 0, 0 },
945 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
946 CPU_AVX512IFMA_FLAGS, 0, 0 },
947 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
948 CPU_AVX512VBMI_FLAGS, 0, 0 },
949 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
950 CPU_CLZERO_FLAGS, 0, 0 },
951 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
952 CPU_MWAITX_FLAGS, 0, 0 },
956 /* Like s_lcomm_internal in gas/read.c but the alignment string
957 is allowed to be optional. */
960 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
967 && *input_line_pointer == ',')
969 align = parse_align (needs_align - 1);
971 if (align == (addressT) -1)
986 bss_alloc (symbolP, size, align);
991 pe_lcomm (int needs_align)
993 s_comm_internal (needs_align * 2, pe_lcomm_internal);
997 const pseudo_typeS md_pseudo_table[] =
999 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1000 {"align", s_align_bytes, 0},
1002 {"align", s_align_ptwo, 0},
1004 {"arch", set_cpu_arch, 0},
1008 {"lcomm", pe_lcomm, 1},
1010 {"ffloat", float_cons, 'f'},
1011 {"dfloat", float_cons, 'd'},
1012 {"tfloat", float_cons, 'x'},
1014 {"slong", signed_cons, 4},
1015 {"noopt", s_ignore, 0},
1016 {"optim", s_ignore, 0},
1017 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1018 {"code16", set_code_flag, CODE_16BIT},
1019 {"code32", set_code_flag, CODE_32BIT},
1020 {"code64", set_code_flag, CODE_64BIT},
1021 {"intel_syntax", set_intel_syntax, 1},
1022 {"att_syntax", set_intel_syntax, 0},
1023 {"intel_mnemonic", set_intel_mnemonic, 1},
1024 {"att_mnemonic", set_intel_mnemonic, 0},
1025 {"allow_index_reg", set_allow_index_reg, 1},
1026 {"disallow_index_reg", set_allow_index_reg, 0},
1027 {"sse_check", set_check, 0},
1028 {"operand_check", set_check, 1},
1029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1030 {"largecomm", handle_large_common, 0},
1032 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1033 {"loc", dwarf2_directive_loc, 0},
1034 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1037 {"secrel32", pe_directive_secrel, 0},
1042 /* For interface with expression (). */
1043 extern char *input_line_pointer;
1045 /* Hash table for instruction mnemonic lookup. */
1046 static struct hash_control *op_hash;
1048 /* Hash table for register lookup. */
1049 static struct hash_control *reg_hash;
1052 i386_align_code (fragS *fragP, int count)
1054 /* Various efficient no-op patterns for aligning code labels.
1055 Note: Don't try to assemble the instructions in the comments.
1056 0L and 0w are not legal. */
1057 static const char f32_1[] =
1059 static const char f32_2[] =
1060 {0x66,0x90}; /* xchg %ax,%ax */
1061 static const char f32_3[] =
1062 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1063 static const char f32_4[] =
1064 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_5[] =
1067 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1068 static const char f32_6[] =
1069 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1070 static const char f32_7[] =
1071 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_8[] =
1074 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1075 static const char f32_9[] =
1076 {0x89,0xf6, /* movl %esi,%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_10[] =
1079 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_11[] =
1082 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_12[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1087 static const char f32_13[] =
1088 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_14[] =
1091 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1092 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1093 static const char f16_3[] =
1094 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1095 static const char f16_4[] =
1096 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_5[] =
1099 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1100 static const char f16_6[] =
1101 {0x89,0xf6, /* mov %si,%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_7[] =
1104 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1106 static const char f16_8[] =
1107 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char jump_31[] =
1110 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1111 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1112 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1113 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1114 static const char *const f32_patt[] = {
1115 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1116 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1118 static const char *const f16_patt[] = {
1119 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1121 /* nopl (%[re]ax) */
1122 static const char alt_3[] =
1124 /* nopl 0(%[re]ax) */
1125 static const char alt_4[] =
1126 {0x0f,0x1f,0x40,0x00};
1127 /* nopl 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_5[] =
1129 {0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopw 0(%[re]ax,%[re]ax,1) */
1131 static const char alt_6[] =
1132 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1133 /* nopl 0L(%[re]ax) */
1134 static const char alt_7[] =
1135 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1136 /* nopl 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_8[] =
1138 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw 0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_9[] =
1141 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1142 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_10[] =
1144 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 static const char *const alt_patt[] = {
1146 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1150 /* Only align for at least a positive non-zero boundary. */
1151 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1154 /* We need to decide which NOP sequence to use for 32bit and
1155 64bit. When -mtune= is used:
1157 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1158 PROCESSOR_GENERIC32, f32_patt will be used.
1159 2. For the rest, alt_patt will be used.
1161 When -mtune= isn't used, alt_patt will be used if
1162 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1165 When -march= or .arch is used, we can't use anything beyond
1166 cpu_arch_isa_flags. */
1168 if (flag_code == CODE_16BIT)
1172 memcpy (fragP->fr_literal + fragP->fr_fix,
1174 /* Adjust jump offset. */
1175 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 f16_patt[count - 1], count);
1183 const char *const *patt = NULL;
1185 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1187 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1188 switch (cpu_arch_tune)
1190 case PROCESSOR_UNKNOWN:
1191 /* We use cpu_arch_isa_flags to check if we SHOULD
1192 optimize with nops. */
1193 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1198 case PROCESSOR_PENTIUM4:
1199 case PROCESSOR_NOCONA:
1200 case PROCESSOR_CORE:
1201 case PROCESSOR_CORE2:
1202 case PROCESSOR_COREI7:
1203 case PROCESSOR_L1OM:
1204 case PROCESSOR_K1OM:
1205 case PROCESSOR_GENERIC64:
1207 case PROCESSOR_ATHLON:
1209 case PROCESSOR_AMDFAM10:
1211 case PROCESSOR_ZNVER:
1215 case PROCESSOR_I386:
1216 case PROCESSOR_I486:
1217 case PROCESSOR_PENTIUM:
1218 case PROCESSOR_PENTIUMPRO:
1219 case PROCESSOR_IAMCU:
1220 case PROCESSOR_GENERIC32:
1227 switch (fragP->tc_frag_data.tune)
1229 case PROCESSOR_UNKNOWN:
1230 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1231 PROCESSOR_UNKNOWN. */
1235 case PROCESSOR_I386:
1236 case PROCESSOR_I486:
1237 case PROCESSOR_PENTIUM:
1238 case PROCESSOR_IAMCU:
1240 case PROCESSOR_ATHLON:
1242 case PROCESSOR_AMDFAM10:
1244 case PROCESSOR_ZNVER:
1246 case PROCESSOR_GENERIC32:
1247 /* We use cpu_arch_isa_flags to check if we CAN optimize
1249 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_PENTIUM4:
1256 case PROCESSOR_NOCONA:
1257 case PROCESSOR_CORE:
1258 case PROCESSOR_CORE2:
1259 case PROCESSOR_COREI7:
1260 case PROCESSOR_L1OM:
1261 case PROCESSOR_K1OM:
1262 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1267 case PROCESSOR_GENERIC64:
1273 if (patt == f32_patt)
1275 /* If the padding is less than 15 bytes, we use the normal
1276 ones. Otherwise, we use a jump instruction and adjust
1280 /* For 64bit, the limit is 3 bytes. */
1281 if (flag_code == CODE_64BIT
1282 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1287 memcpy (fragP->fr_literal + fragP->fr_fix,
1288 patt[count - 1], count);
1291 memcpy (fragP->fr_literal + fragP->fr_fix,
1293 /* Adjust jump offset. */
1294 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1299 /* Maximum length of an instruction is 10 byte. If the
1300 padding is greater than 10 bytes and we don't use jump,
1301 we have to break it into smaller pieces. */
1302 int padding = count;
1303 while (padding > 10)
1306 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1311 memcpy (fragP->fr_literal + fragP->fr_fix,
1312 patt [padding - 1], padding);
1315 fragP->fr_var = count;
1319 operand_type_all_zero (const union i386_operand_type *x)
1321 switch (ARRAY_SIZE(x->array))
1330 return !x->array[0];
1337 operand_type_set (union i386_operand_type *x, unsigned int v)
1339 switch (ARRAY_SIZE(x->array))
1354 operand_type_equal (const union i386_operand_type *x,
1355 const union i386_operand_type *y)
1357 switch (ARRAY_SIZE(x->array))
1360 if (x->array[2] != y->array[2])
1363 if (x->array[1] != y->array[1])
1366 return x->array[0] == y->array[0];
1374 cpu_flags_all_zero (const union i386_cpu_flags *x)
1376 switch (ARRAY_SIZE(x->array))
1385 return !x->array[0];
1392 cpu_flags_equal (const union i386_cpu_flags *x,
1393 const union i386_cpu_flags *y)
1395 switch (ARRAY_SIZE(x->array))
1398 if (x->array[2] != y->array[2])
1401 if (x->array[1] != y->array[1])
1404 return x->array[0] == y->array[0];
1412 cpu_flags_check_cpu64 (i386_cpu_flags f)
1414 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1415 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1418 static INLINE i386_cpu_flags
1419 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1421 switch (ARRAY_SIZE (x.array))
1424 x.array [2] &= y.array [2];
1426 x.array [1] &= y.array [1];
1428 x.array [0] &= y.array [0];
1436 static INLINE i386_cpu_flags
1437 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1439 switch (ARRAY_SIZE (x.array))
1442 x.array [2] |= y.array [2];
1444 x.array [1] |= y.array [1];
1446 x.array [0] |= y.array [0];
1454 static INLINE i386_cpu_flags
1455 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1457 switch (ARRAY_SIZE (x.array))
1460 x.array [2] &= ~y.array [2];
1462 x.array [1] &= ~y.array [1];
1464 x.array [0] &= ~y.array [0];
1473 valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1475 if (cpu_arch_isa == PROCESSOR_IAMCU)
1477 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1478 i386_cpu_flags compat_flags;
1479 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1480 return cpu_flags_all_zero (&compat_flags);
1486 #define CPU_FLAGS_ARCH_MATCH 0x1
1487 #define CPU_FLAGS_64BIT_MATCH 0x2
1488 #define CPU_FLAGS_AES_MATCH 0x4
1489 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1490 #define CPU_FLAGS_AVX_MATCH 0x10
1492 #define CPU_FLAGS_32BIT_MATCH \
1493 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1494 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1495 #define CPU_FLAGS_PERFECT_MATCH \
1496 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1498 /* Return CPU flags match bits. */
1501 cpu_flags_match (const insn_template *t)
1503 i386_cpu_flags x = t->cpu_flags;
1504 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1506 x.bitfield.cpu64 = 0;
1507 x.bitfield.cpuno64 = 0;
1509 if (cpu_flags_all_zero (&x))
1511 /* This instruction is available on all archs. */
1512 match |= CPU_FLAGS_32BIT_MATCH;
1516 /* This instruction is available only on some archs. */
1517 i386_cpu_flags cpu = cpu_arch_flags;
1519 cpu.bitfield.cpu64 = 0;
1520 cpu.bitfield.cpuno64 = 0;
1521 cpu = cpu_flags_and (x, cpu);
1522 if (!cpu_flags_all_zero (&cpu))
1524 if (x.bitfield.cpuavx)
1526 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1527 if (cpu.bitfield.cpuavx)
1529 /* Check SSE2AVX. */
1530 if (!t->opcode_modifier.sse2avx|| sse2avx)
1532 match |= (CPU_FLAGS_ARCH_MATCH
1533 | CPU_FLAGS_AVX_MATCH);
1535 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1536 match |= CPU_FLAGS_AES_MATCH;
1538 if (!x.bitfield.cpupclmul
1539 || cpu.bitfield.cpupclmul)
1540 match |= CPU_FLAGS_PCLMUL_MATCH;
1544 match |= CPU_FLAGS_ARCH_MATCH;
1547 match |= CPU_FLAGS_32BIT_MATCH;
1553 static INLINE i386_operand_type
1554 operand_type_and (i386_operand_type x, i386_operand_type y)
1556 switch (ARRAY_SIZE (x.array))
1559 x.array [2] &= y.array [2];
1561 x.array [1] &= y.array [1];
1563 x.array [0] &= y.array [0];
1571 static INLINE i386_operand_type
1572 operand_type_or (i386_operand_type x, i386_operand_type y)
1574 switch (ARRAY_SIZE (x.array))
1577 x.array [2] |= y.array [2];
1579 x.array [1] |= y.array [1];
1581 x.array [0] |= y.array [0];
1589 static INLINE i386_operand_type
1590 operand_type_xor (i386_operand_type x, i386_operand_type y)
1592 switch (ARRAY_SIZE (x.array))
1595 x.array [2] ^= y.array [2];
1597 x.array [1] ^= y.array [1];
1599 x.array [0] ^= y.array [0];
1607 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1608 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1609 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1610 static const i386_operand_type inoutportreg
1611 = OPERAND_TYPE_INOUTPORTREG;
1612 static const i386_operand_type reg16_inoutportreg
1613 = OPERAND_TYPE_REG16_INOUTPORTREG;
1614 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1615 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1616 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1617 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1618 static const i386_operand_type anydisp
1619 = OPERAND_TYPE_ANYDISP;
1620 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1621 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1622 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1623 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1624 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1625 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1626 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1627 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1628 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1629 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1630 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1631 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1632 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1633 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1644 operand_type_check (i386_operand_type t, enum operand_type c)
1649 return (t.bitfield.reg8
1652 || t.bitfield.reg64);
1655 return (t.bitfield.imm8
1659 || t.bitfield.imm32s
1660 || t.bitfield.imm64);
1663 return (t.bitfield.disp8
1664 || t.bitfield.disp16
1665 || t.bitfield.disp32
1666 || t.bitfield.disp32s
1667 || t.bitfield.disp64);
1670 return (t.bitfield.disp8
1671 || t.bitfield.disp16
1672 || t.bitfield.disp32
1673 || t.bitfield.disp32s
1674 || t.bitfield.disp64
1675 || t.bitfield.baseindex);
1684 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1685 operand J for instruction template T. */
1688 match_reg_size (const insn_template *t, unsigned int j)
1690 return !((i.types[j].bitfield.byte
1691 && !t->operand_types[j].bitfield.byte)
1692 || (i.types[j].bitfield.word
1693 && !t->operand_types[j].bitfield.word)
1694 || (i.types[j].bitfield.dword
1695 && !t->operand_types[j].bitfield.dword)
1696 || (i.types[j].bitfield.qword
1697 && !t->operand_types[j].bitfield.qword));
1700 /* Return 1 if there is no conflict in any size on operand J for
1701 instruction template T. */
1704 match_mem_size (const insn_template *t, unsigned int j)
1706 return (match_reg_size (t, j)
1707 && !((i.types[j].bitfield.unspecified
1709 && !t->operand_types[j].bitfield.unspecified)
1710 || (i.types[j].bitfield.fword
1711 && !t->operand_types[j].bitfield.fword)
1712 || (i.types[j].bitfield.tbyte
1713 && !t->operand_types[j].bitfield.tbyte)
1714 || (i.types[j].bitfield.xmmword
1715 && !t->operand_types[j].bitfield.xmmword)
1716 || (i.types[j].bitfield.ymmword
1717 && !t->operand_types[j].bitfield.ymmword)
1718 || (i.types[j].bitfield.zmmword
1719 && !t->operand_types[j].bitfield.zmmword)));
1722 /* Return 1 if there is no size conflict on any operands for
1723 instruction template T. */
1726 operand_size_match (const insn_template *t)
1731 /* Don't check jump instructions. */
1732 if (t->opcode_modifier.jump
1733 || t->opcode_modifier.jumpbyte
1734 || t->opcode_modifier.jumpdword
1735 || t->opcode_modifier.jumpintersegment)
1738 /* Check memory and accumulator operand size. */
1739 for (j = 0; j < i.operands; j++)
1741 if (t->operand_types[j].bitfield.anysize)
1744 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1750 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1759 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1762 i.error = operand_size_mismatch;
1766 /* Check reverse. */
1767 gas_assert (i.operands == 2);
1770 for (j = 0; j < 2; j++)
1772 if (t->operand_types[j].bitfield.acc
1773 && !match_reg_size (t, j ? 0 : 1))
1776 if (i.types[j].bitfield.mem
1777 && !match_mem_size (t, j ? 0 : 1))
1785 operand_type_match (i386_operand_type overlap,
1786 i386_operand_type given)
1788 i386_operand_type temp = overlap;
1790 temp.bitfield.jumpabsolute = 0;
1791 temp.bitfield.unspecified = 0;
1792 temp.bitfield.byte = 0;
1793 temp.bitfield.word = 0;
1794 temp.bitfield.dword = 0;
1795 temp.bitfield.fword = 0;
1796 temp.bitfield.qword = 0;
1797 temp.bitfield.tbyte = 0;
1798 temp.bitfield.xmmword = 0;
1799 temp.bitfield.ymmword = 0;
1800 temp.bitfield.zmmword = 0;
1801 if (operand_type_all_zero (&temp))
1804 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1805 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1809 i.error = operand_type_mismatch;
1813 /* If given types g0 and g1 are registers they must be of the same type
1814 unless the expected operand type register overlap is null.
1815 Note that Acc in a template matches every size of reg. */
1818 operand_type_register_match (i386_operand_type m0,
1819 i386_operand_type g0,
1820 i386_operand_type t0,
1821 i386_operand_type m1,
1822 i386_operand_type g1,
1823 i386_operand_type t1)
1825 if (!operand_type_check (g0, reg))
1828 if (!operand_type_check (g1, reg))
1831 if (g0.bitfield.reg8 == g1.bitfield.reg8
1832 && g0.bitfield.reg16 == g1.bitfield.reg16
1833 && g0.bitfield.reg32 == g1.bitfield.reg32
1834 && g0.bitfield.reg64 == g1.bitfield.reg64)
1837 if (m0.bitfield.acc)
1839 t0.bitfield.reg8 = 1;
1840 t0.bitfield.reg16 = 1;
1841 t0.bitfield.reg32 = 1;
1842 t0.bitfield.reg64 = 1;
1845 if (m1.bitfield.acc)
1847 t1.bitfield.reg8 = 1;
1848 t1.bitfield.reg16 = 1;
1849 t1.bitfield.reg32 = 1;
1850 t1.bitfield.reg64 = 1;
1853 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1854 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1855 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1856 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1859 i.error = register_type_mismatch;
1864 static INLINE unsigned int
1865 register_number (const reg_entry *r)
1867 unsigned int nr = r->reg_num;
1869 if (r->reg_flags & RegRex)
1875 static INLINE unsigned int
1876 mode_from_disp_size (i386_operand_type t)
1878 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1880 else if (t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s)
1889 fits_in_signed_byte (addressT num)
1891 return num + 0x80 <= 0xff;
1895 fits_in_unsigned_byte (addressT num)
1901 fits_in_unsigned_word (addressT num)
1903 return num <= 0xffff;
1907 fits_in_signed_word (addressT num)
1909 return num + 0x8000 <= 0xffff;
1913 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
1918 return num + 0x80000000 <= 0xffffffff;
1920 } /* fits_in_signed_long() */
1923 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
1928 return num <= 0xffffffff;
1930 } /* fits_in_unsigned_long() */
1933 fits_in_vec_disp8 (offsetT num)
1935 int shift = i.memshift;
1941 mask = (1 << shift) - 1;
1943 /* Return 0 if NUM isn't properly aligned. */
1947 /* Check if NUM will fit in 8bit after shift. */
1948 return fits_in_signed_byte (num >> shift);
1952 fits_in_imm4 (offsetT num)
1954 return (num & 0xf) == num;
1957 static i386_operand_type
1958 smallest_imm_type (offsetT num)
1960 i386_operand_type t;
1962 operand_type_set (&t, 0);
1963 t.bitfield.imm64 = 1;
1965 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1967 /* This code is disabled on the 486 because all the Imm1 forms
1968 in the opcode table are slower on the i486. They're the
1969 versions with the implicitly specified single-position
1970 displacement, which has another syntax if you really want to
1972 t.bitfield.imm1 = 1;
1973 t.bitfield.imm8 = 1;
1974 t.bitfield.imm8s = 1;
1975 t.bitfield.imm16 = 1;
1976 t.bitfield.imm32 = 1;
1977 t.bitfield.imm32s = 1;
1979 else if (fits_in_signed_byte (num))
1981 t.bitfield.imm8 = 1;
1982 t.bitfield.imm8s = 1;
1983 t.bitfield.imm16 = 1;
1984 t.bitfield.imm32 = 1;
1985 t.bitfield.imm32s = 1;
1987 else if (fits_in_unsigned_byte (num))
1989 t.bitfield.imm8 = 1;
1990 t.bitfield.imm16 = 1;
1991 t.bitfield.imm32 = 1;
1992 t.bitfield.imm32s = 1;
1994 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
2000 else if (fits_in_signed_long (num))
2002 t.bitfield.imm32 = 1;
2003 t.bitfield.imm32s = 1;
2005 else if (fits_in_unsigned_long (num))
2006 t.bitfield.imm32 = 1;
2012 offset_in_range (offsetT val, int size)
2018 case 1: mask = ((addressT) 1 << 8) - 1; break;
2019 case 2: mask = ((addressT) 1 << 16) - 1; break;
2020 case 4: mask = ((addressT) 2 << 31) - 1; break;
2022 case 8: mask = ((addressT) 2 << 63) - 1; break;
2028 /* If BFD64, sign extend val for 32bit address mode. */
2029 if (flag_code != CODE_64BIT
2030 || i.prefix[ADDR_PREFIX])
2031 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2032 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2035 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2037 char buf1[40], buf2[40];
2039 sprint_value (buf1, val);
2040 sprint_value (buf2, val & mask);
2041 as_warn (_("%s shortened to %s"), buf1, buf2);
2055 a. PREFIX_EXIST if attempting to add a prefix where one from the
2056 same class already exists.
2057 b. PREFIX_LOCK if lock prefix is added.
2058 c. PREFIX_REP if rep/repne prefix is added.
2059 d. PREFIX_OTHER if other prefix is added.
2062 static enum PREFIX_GROUP
2063 add_prefix (unsigned int prefix)
2065 enum PREFIX_GROUP ret = PREFIX_OTHER;
2068 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2069 && flag_code == CODE_64BIT)
2071 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2072 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2073 && (prefix & (REX_R | REX_X | REX_B))))
2084 case CS_PREFIX_OPCODE:
2085 case DS_PREFIX_OPCODE:
2086 case ES_PREFIX_OPCODE:
2087 case FS_PREFIX_OPCODE:
2088 case GS_PREFIX_OPCODE:
2089 case SS_PREFIX_OPCODE:
2093 case REPNE_PREFIX_OPCODE:
2094 case REPE_PREFIX_OPCODE:
2099 case LOCK_PREFIX_OPCODE:
2108 case ADDR_PREFIX_OPCODE:
2112 case DATA_PREFIX_OPCODE:
2116 if (i.prefix[q] != 0)
2124 i.prefix[q] |= prefix;
2127 as_bad (_("same type of prefix used twice"));
2133 update_code_flag (int value, int check)
2135 PRINTF_LIKE ((*as_error));
2137 flag_code = (enum flag_code) value;
2138 if (flag_code == CODE_64BIT)
2140 cpu_arch_flags.bitfield.cpu64 = 1;
2141 cpu_arch_flags.bitfield.cpuno64 = 0;
2145 cpu_arch_flags.bitfield.cpu64 = 0;
2146 cpu_arch_flags.bitfield.cpuno64 = 1;
2148 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2151 as_error = as_fatal;
2154 (*as_error) (_("64bit mode not supported on `%s'."),
2155 cpu_arch_name ? cpu_arch_name : default_arch);
2157 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2160 as_error = as_fatal;
2163 (*as_error) (_("32bit mode not supported on `%s'."),
2164 cpu_arch_name ? cpu_arch_name : default_arch);
2166 stackop_size = '\0';
2170 set_code_flag (int value)
2172 update_code_flag (value, 0);
2176 set_16bit_gcc_code_flag (int new_code_flag)
2178 flag_code = (enum flag_code) new_code_flag;
2179 if (flag_code != CODE_16BIT)
2181 cpu_arch_flags.bitfield.cpu64 = 0;
2182 cpu_arch_flags.bitfield.cpuno64 = 1;
2183 stackop_size = LONG_MNEM_SUFFIX;
2187 set_intel_syntax (int syntax_flag)
2189 /* Find out if register prefixing is specified. */
2190 int ask_naked_reg = 0;
2193 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2196 int e = get_symbol_name (&string);
2198 if (strcmp (string, "prefix") == 0)
2200 else if (strcmp (string, "noprefix") == 0)
2203 as_bad (_("bad argument to syntax directive."));
2204 (void) restore_line_pointer (e);
2206 demand_empty_rest_of_line ();
2208 intel_syntax = syntax_flag;
2210 if (ask_naked_reg == 0)
2211 allow_naked_reg = (intel_syntax
2212 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2214 allow_naked_reg = (ask_naked_reg < 0);
2216 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2218 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2219 identifier_chars['$'] = intel_syntax ? '$' : 0;
2220 register_prefix = allow_naked_reg ? "" : "%";
2224 set_intel_mnemonic (int mnemonic_flag)
2226 intel_mnemonic = mnemonic_flag;
2230 set_allow_index_reg (int flag)
2232 allow_index_reg = flag;
2236 set_check (int what)
2238 enum check_kind *kind;
2243 kind = &operand_check;
2254 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2257 int e = get_symbol_name (&string);
2259 if (strcmp (string, "none") == 0)
2261 else if (strcmp (string, "warning") == 0)
2262 *kind = check_warning;
2263 else if (strcmp (string, "error") == 0)
2264 *kind = check_error;
2266 as_bad (_("bad argument to %s_check directive."), str);
2267 (void) restore_line_pointer (e);
2270 as_bad (_("missing argument for %s_check directive"), str);
2272 demand_empty_rest_of_line ();
2276 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2277 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2280 static const char *arch;
2282 /* Intel LIOM is only supported on ELF. */
2288 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2289 use default_arch. */
2290 arch = cpu_arch_name;
2292 arch = default_arch;
2295 /* If we are targeting Intel MCU, we must enable it. */
2296 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2297 || new_flag.bitfield.cpuiamcu)
2300 /* If we are targeting Intel L1OM, we must enable it. */
2301 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2302 || new_flag.bitfield.cpul1om)
2305 /* If we are targeting Intel K1OM, we must enable it. */
2306 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2307 || new_flag.bitfield.cpuk1om)
2310 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2315 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2319 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2322 int e = get_symbol_name (&string);
2324 i386_cpu_flags flags;
2326 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2328 if (strcmp (string, cpu_arch[j].name) == 0)
2330 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2334 cpu_arch_name = cpu_arch[j].name;
2335 cpu_sub_arch_name = NULL;
2336 cpu_arch_flags = cpu_arch[j].flags;
2337 if (flag_code == CODE_64BIT)
2339 cpu_arch_flags.bitfield.cpu64 = 1;
2340 cpu_arch_flags.bitfield.cpuno64 = 0;
2344 cpu_arch_flags.bitfield.cpu64 = 0;
2345 cpu_arch_flags.bitfield.cpuno64 = 1;
2347 cpu_arch_isa = cpu_arch[j].type;
2348 cpu_arch_isa_flags = cpu_arch[j].flags;
2349 if (!cpu_arch_tune_set)
2351 cpu_arch_tune = cpu_arch_isa;
2352 cpu_arch_tune_flags = cpu_arch_isa_flags;
2357 if (!cpu_arch[j].negated)
2358 flags = cpu_flags_or (cpu_arch_flags,
2361 flags = cpu_flags_and_not (cpu_arch_flags,
2364 if (!valid_iamcu_cpu_flags (&flags))
2365 as_fatal (_("`%s' isn't valid for Intel MCU"),
2367 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2369 if (cpu_sub_arch_name)
2371 char *name = cpu_sub_arch_name;
2372 cpu_sub_arch_name = concat (name,
2374 (const char *) NULL);
2378 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2379 cpu_arch_flags = flags;
2380 cpu_arch_isa_flags = flags;
2382 (void) restore_line_pointer (e);
2383 demand_empty_rest_of_line ();
2387 if (j >= ARRAY_SIZE (cpu_arch))
2388 as_bad (_("no such architecture: `%s'"), string);
2390 *input_line_pointer = e;
2393 as_bad (_("missing cpu architecture"));
2395 no_cond_jump_promotion = 0;
2396 if (*input_line_pointer == ','
2397 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2402 ++input_line_pointer;
2403 e = get_symbol_name (&string);
2405 if (strcmp (string, "nojumps") == 0)
2406 no_cond_jump_promotion = 1;
2407 else if (strcmp (string, "jumps") == 0)
2410 as_bad (_("no such architecture modifier: `%s'"), string);
2412 (void) restore_line_pointer (e);
2415 demand_empty_rest_of_line ();
2418 enum bfd_architecture
2421 if (cpu_arch_isa == PROCESSOR_L1OM)
2423 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2424 || flag_code != CODE_64BIT)
2425 as_fatal (_("Intel L1OM is 64bit ELF only"));
2426 return bfd_arch_l1om;
2428 else if (cpu_arch_isa == PROCESSOR_K1OM)
2430 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2431 || flag_code != CODE_64BIT)
2432 as_fatal (_("Intel K1OM is 64bit ELF only"));
2433 return bfd_arch_k1om;
2435 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2437 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2438 || flag_code == CODE_64BIT)
2439 as_fatal (_("Intel MCU is 32bit ELF only"));
2440 return bfd_arch_iamcu;
2443 return bfd_arch_i386;
2449 if (!strncmp (default_arch, "x86_64", 6))
2451 if (cpu_arch_isa == PROCESSOR_L1OM)
2453 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2454 || default_arch[6] != '\0')
2455 as_fatal (_("Intel L1OM is 64bit ELF only"));
2456 return bfd_mach_l1om;
2458 else if (cpu_arch_isa == PROCESSOR_K1OM)
2460 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2461 || default_arch[6] != '\0')
2462 as_fatal (_("Intel K1OM is 64bit ELF only"));
2463 return bfd_mach_k1om;
2465 else if (default_arch[6] == '\0')
2466 return bfd_mach_x86_64;
2468 return bfd_mach_x64_32;
2470 else if (!strcmp (default_arch, "i386")
2471 || !strcmp (default_arch, "iamcu"))
2473 if (cpu_arch_isa == PROCESSOR_IAMCU)
2475 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2476 as_fatal (_("Intel MCU is 32bit ELF only"));
2477 return bfd_mach_i386_iamcu;
2480 return bfd_mach_i386_i386;
2483 as_fatal (_("unknown architecture"));
2489 const char *hash_err;
2491 /* Initialize op_hash hash table. */
2492 op_hash = hash_new ();
2495 const insn_template *optab;
2496 templates *core_optab;
2498 /* Setup for loop. */
2500 core_optab = (templates *) xmalloc (sizeof (templates));
2501 core_optab->start = optab;
2506 if (optab->name == NULL
2507 || strcmp (optab->name, (optab - 1)->name) != 0)
2509 /* different name --> ship out current template list;
2510 add to hash table; & begin anew. */
2511 core_optab->end = optab;
2512 hash_err = hash_insert (op_hash,
2514 (void *) core_optab);
2517 as_fatal (_("can't hash %s: %s"),
2521 if (optab->name == NULL)
2523 core_optab = (templates *) xmalloc (sizeof (templates));
2524 core_optab->start = optab;
2529 /* Initialize reg_hash hash table. */
2530 reg_hash = hash_new ();
2532 const reg_entry *regtab;
2533 unsigned int regtab_size = i386_regtab_size;
2535 for (regtab = i386_regtab; regtab_size--; regtab++)
2537 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2539 as_fatal (_("can't hash %s: %s"),
2545 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2550 for (c = 0; c < 256; c++)
2555 mnemonic_chars[c] = c;
2556 register_chars[c] = c;
2557 operand_chars[c] = c;
2559 else if (ISLOWER (c))
2561 mnemonic_chars[c] = c;
2562 register_chars[c] = c;
2563 operand_chars[c] = c;
2565 else if (ISUPPER (c))
2567 mnemonic_chars[c] = TOLOWER (c);
2568 register_chars[c] = mnemonic_chars[c];
2569 operand_chars[c] = c;
2571 else if (c == '{' || c == '}')
2572 operand_chars[c] = c;
2574 if (ISALPHA (c) || ISDIGIT (c))
2575 identifier_chars[c] = c;
2578 identifier_chars[c] = c;
2579 operand_chars[c] = c;
2584 identifier_chars['@'] = '@';
2587 identifier_chars['?'] = '?';
2588 operand_chars['?'] = '?';
2590 digit_chars['-'] = '-';
2591 mnemonic_chars['_'] = '_';
2592 mnemonic_chars['-'] = '-';
2593 mnemonic_chars['.'] = '.';
2594 identifier_chars['_'] = '_';
2595 identifier_chars['.'] = '.';
2597 for (p = operand_special_chars; *p != '\0'; p++)
2598 operand_chars[(unsigned char) *p] = *p;
2601 if (flag_code == CODE_64BIT)
2603 #if defined (OBJ_COFF) && defined (TE_PE)
2604 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2607 x86_dwarf2_return_column = 16;
2609 x86_cie_data_alignment = -8;
2613 x86_dwarf2_return_column = 8;
2614 x86_cie_data_alignment = -4;
2619 i386_print_statistics (FILE *file)
2621 hash_print_statistics (file, "i386 opcode", op_hash);
2622 hash_print_statistics (file, "i386 register", reg_hash);
2627 /* Debugging routines for md_assemble. */
2628 static void pte (insn_template *);
2629 static void pt (i386_operand_type);
2630 static void pe (expressionS *);
2631 static void ps (symbolS *);
2634 pi (char *line, i386_insn *x)
2638 fprintf (stdout, "%s: template ", line);
2640 fprintf (stdout, " address: base %s index %s scale %x\n",
2641 x->base_reg ? x->base_reg->reg_name : "none",
2642 x->index_reg ? x->index_reg->reg_name : "none",
2643 x->log2_scale_factor);
2644 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2645 x->rm.mode, x->rm.reg, x->rm.regmem);
2646 fprintf (stdout, " sib: base %x index %x scale %x\n",
2647 x->sib.base, x->sib.index, x->sib.scale);
2648 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2649 (x->rex & REX_W) != 0,
2650 (x->rex & REX_R) != 0,
2651 (x->rex & REX_X) != 0,
2652 (x->rex & REX_B) != 0);
2653 for (j = 0; j < x->operands; j++)
2655 fprintf (stdout, " #%d: ", j + 1);
2657 fprintf (stdout, "\n");
2658 if (x->types[j].bitfield.reg8
2659 || x->types[j].bitfield.reg16
2660 || x->types[j].bitfield.reg32
2661 || x->types[j].bitfield.reg64
2662 || x->types[j].bitfield.regmmx
2663 || x->types[j].bitfield.regxmm
2664 || x->types[j].bitfield.regymm
2665 || x->types[j].bitfield.regzmm
2666 || x->types[j].bitfield.sreg2
2667 || x->types[j].bitfield.sreg3
2668 || x->types[j].bitfield.control
2669 || x->types[j].bitfield.debug
2670 || x->types[j].bitfield.test)
2671 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2672 if (operand_type_check (x->types[j], imm))
2674 if (operand_type_check (x->types[j], disp))
2675 pe (x->op[j].disps);
2680 pte (insn_template *t)
2683 fprintf (stdout, " %d operands ", t->operands);
2684 fprintf (stdout, "opcode %x ", t->base_opcode);
2685 if (t->extension_opcode != None)
2686 fprintf (stdout, "ext %x ", t->extension_opcode);
2687 if (t->opcode_modifier.d)
2688 fprintf (stdout, "D");
2689 if (t->opcode_modifier.w)
2690 fprintf (stdout, "W");
2691 fprintf (stdout, "\n");
2692 for (j = 0; j < t->operands; j++)
2694 fprintf (stdout, " #%d type ", j + 1);
2695 pt (t->operand_types[j]);
2696 fprintf (stdout, "\n");
2703 fprintf (stdout, " operation %d\n", e->X_op);
2704 fprintf (stdout, " add_number %ld (%lx)\n",
2705 (long) e->X_add_number, (long) e->X_add_number);
2706 if (e->X_add_symbol)
2708 fprintf (stdout, " add_symbol ");
2709 ps (e->X_add_symbol);
2710 fprintf (stdout, "\n");
2714 fprintf (stdout, " op_symbol ");
2715 ps (e->X_op_symbol);
2716 fprintf (stdout, "\n");
2723 fprintf (stdout, "%s type %s%s",
2725 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2726 segment_name (S_GET_SEGMENT (s)));
2729 static struct type_name
2731 i386_operand_type mask;
2734 const type_names[] =
2736 { OPERAND_TYPE_REG8, "r8" },
2737 { OPERAND_TYPE_REG16, "r16" },
2738 { OPERAND_TYPE_REG32, "r32" },
2739 { OPERAND_TYPE_REG64, "r64" },
2740 { OPERAND_TYPE_IMM8, "i8" },
2741 { OPERAND_TYPE_IMM8, "i8s" },
2742 { OPERAND_TYPE_IMM16, "i16" },
2743 { OPERAND_TYPE_IMM32, "i32" },
2744 { OPERAND_TYPE_IMM32S, "i32s" },
2745 { OPERAND_TYPE_IMM64, "i64" },
2746 { OPERAND_TYPE_IMM1, "i1" },
2747 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2748 { OPERAND_TYPE_DISP8, "d8" },
2749 { OPERAND_TYPE_DISP16, "d16" },
2750 { OPERAND_TYPE_DISP32, "d32" },
2751 { OPERAND_TYPE_DISP32S, "d32s" },
2752 { OPERAND_TYPE_DISP64, "d64" },
2753 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2754 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2755 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2756 { OPERAND_TYPE_CONTROL, "control reg" },
2757 { OPERAND_TYPE_TEST, "test reg" },
2758 { OPERAND_TYPE_DEBUG, "debug reg" },
2759 { OPERAND_TYPE_FLOATREG, "FReg" },
2760 { OPERAND_TYPE_FLOATACC, "FAcc" },
2761 { OPERAND_TYPE_SREG2, "SReg2" },
2762 { OPERAND_TYPE_SREG3, "SReg3" },
2763 { OPERAND_TYPE_ACC, "Acc" },
2764 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2765 { OPERAND_TYPE_REGMMX, "rMMX" },
2766 { OPERAND_TYPE_REGXMM, "rXMM" },
2767 { OPERAND_TYPE_REGYMM, "rYMM" },
2768 { OPERAND_TYPE_REGZMM, "rZMM" },
2769 { OPERAND_TYPE_REGMASK, "Mask reg" },
2770 { OPERAND_TYPE_ESSEG, "es" },
2774 pt (i386_operand_type t)
2777 i386_operand_type a;
2779 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2781 a = operand_type_and (t, type_names[j].mask);
2782 if (!operand_type_all_zero (&a))
2783 fprintf (stdout, "%s, ", type_names[j].name);
2788 #endif /* DEBUG386 */
2790 static bfd_reloc_code_real_type
2791 reloc (unsigned int size,
2794 bfd_reloc_code_real_type other)
2796 if (other != NO_RELOC)
2798 reloc_howto_type *rel;
2803 case BFD_RELOC_X86_64_GOT32:
2804 return BFD_RELOC_X86_64_GOT64;
2806 case BFD_RELOC_X86_64_GOTPLT64:
2807 return BFD_RELOC_X86_64_GOTPLT64;
2809 case BFD_RELOC_X86_64_PLTOFF64:
2810 return BFD_RELOC_X86_64_PLTOFF64;
2812 case BFD_RELOC_X86_64_GOTPC32:
2813 other = BFD_RELOC_X86_64_GOTPC64;
2815 case BFD_RELOC_X86_64_GOTPCREL:
2816 other = BFD_RELOC_X86_64_GOTPCREL64;
2818 case BFD_RELOC_X86_64_TPOFF32:
2819 other = BFD_RELOC_X86_64_TPOFF64;
2821 case BFD_RELOC_X86_64_DTPOFF32:
2822 other = BFD_RELOC_X86_64_DTPOFF64;
2828 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2829 if (other == BFD_RELOC_SIZE32)
2832 other = BFD_RELOC_SIZE64;
2835 as_bad (_("there are no pc-relative size relocations"));
2841 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2842 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2845 rel = bfd_reloc_type_lookup (stdoutput, other);
2847 as_bad (_("unknown relocation (%u)"), other);
2848 else if (size != bfd_get_reloc_size (rel))
2849 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2850 bfd_get_reloc_size (rel),
2852 else if (pcrel && !rel->pc_relative)
2853 as_bad (_("non-pc-relative relocation for pc-relative field"));
2854 else if ((rel->complain_on_overflow == complain_overflow_signed
2856 || (rel->complain_on_overflow == complain_overflow_unsigned
2858 as_bad (_("relocated field and relocation type differ in signedness"));
2867 as_bad (_("there are no unsigned pc-relative relocations"));
2870 case 1: return BFD_RELOC_8_PCREL;
2871 case 2: return BFD_RELOC_16_PCREL;
2872 case 4: return BFD_RELOC_32_PCREL;
2873 case 8: return BFD_RELOC_64_PCREL;
2875 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2882 case 4: return BFD_RELOC_X86_64_32S;
2887 case 1: return BFD_RELOC_8;
2888 case 2: return BFD_RELOC_16;
2889 case 4: return BFD_RELOC_32;
2890 case 8: return BFD_RELOC_64;
2892 as_bad (_("cannot do %s %u byte relocation"),
2893 sign > 0 ? "signed" : "unsigned", size);
2899 /* Here we decide which fixups can be adjusted to make them relative to
2900 the beginning of the section instead of the symbol. Basically we need
2901 to make sure that the dynamic relocations are done correctly, so in
2902 some cases we force the original symbol to be used. */
2905 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2911 /* Don't adjust pc-relative references to merge sections in 64-bit
2913 if (use_rela_relocations
2914 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2918 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2919 and changed later by validate_fix. */
2920 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2921 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2924 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2925 for size relocations. */
2926 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2927 || fixP->fx_r_type == BFD_RELOC_SIZE64
2928 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2929 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2930 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2931 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2932 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2933 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2941 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2942 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2943 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2944 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2946 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2947 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2954 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2955 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2962 intel_float_operand (const char *mnemonic)
2964 /* Note that the value returned is meaningful only for opcodes with (memory)
2965 operands, hence the code here is free to improperly handle opcodes that
2966 have no operands (for better performance and smaller code). */
2968 if (mnemonic[0] != 'f')
2969 return 0; /* non-math */
2971 switch (mnemonic[1])
2973 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2974 the fs segment override prefix not currently handled because no
2975 call path can make opcodes without operands get here */
2977 return 2 /* integer op */;
2979 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2980 return 3; /* fldcw/fldenv */
2983 if (mnemonic[2] != 'o' /* fnop */)
2984 return 3; /* non-waiting control op */
2987 if (mnemonic[2] == 's')
2988 return 3; /* frstor/frstpm */
2991 if (mnemonic[2] == 'a')
2992 return 3; /* fsave */
2993 if (mnemonic[2] == 't')
2995 switch (mnemonic[3])
2997 case 'c': /* fstcw */
2998 case 'd': /* fstdw */
2999 case 'e': /* fstenv */
3000 case 's': /* fsts[gw] */
3006 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3007 return 0; /* fxsave/fxrstor are not really math ops */
3014 /* Build the VEX prefix. */
3017 build_vex_prefix (const insn_template *t)
3019 unsigned int register_specifier;
3020 unsigned int implied_prefix;
3021 unsigned int vector_length;
3023 /* Check register specifier. */
3024 if (i.vex.register_specifier)
3026 register_specifier =
3027 ~register_number (i.vex.register_specifier) & 0xf;
3028 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3031 register_specifier = 0xf;
3033 /* Use 2-byte VEX prefix by swappping destination and source
3036 && i.operands == i.reg_operands
3037 && i.tm.opcode_modifier.vexopcode == VEX0F
3038 && i.tm.opcode_modifier.s
3041 unsigned int xchg = i.operands - 1;
3042 union i386_op temp_op;
3043 i386_operand_type temp_type;
3045 temp_type = i.types[xchg];
3046 i.types[xchg] = i.types[0];
3047 i.types[0] = temp_type;
3048 temp_op = i.op[xchg];
3049 i.op[xchg] = i.op[0];
3052 gas_assert (i.rm.mode == 3);
3056 i.rm.regmem = i.rm.reg;
3059 /* Use the next insn. */
3063 if (i.tm.opcode_modifier.vex == VEXScalar)
3064 vector_length = avxscalar;
3066 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3068 switch ((i.tm.base_opcode >> 8) & 0xff)
3073 case DATA_PREFIX_OPCODE:
3076 case REPE_PREFIX_OPCODE:
3079 case REPNE_PREFIX_OPCODE:
3086 /* Use 2-byte VEX prefix if possible. */
3087 if (i.tm.opcode_modifier.vexopcode == VEX0F
3088 && i.tm.opcode_modifier.vexw != VEXW1
3089 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3091 /* 2-byte VEX prefix. */
3095 i.vex.bytes[0] = 0xc5;
3097 /* Check the REX.R bit. */
3098 r = (i.rex & REX_R) ? 0 : 1;
3099 i.vex.bytes[1] = (r << 7
3100 | register_specifier << 3
3101 | vector_length << 2
3106 /* 3-byte VEX prefix. */
3111 switch (i.tm.opcode_modifier.vexopcode)
3115 i.vex.bytes[0] = 0xc4;
3119 i.vex.bytes[0] = 0xc4;
3123 i.vex.bytes[0] = 0xc4;
3127 i.vex.bytes[0] = 0x8f;
3131 i.vex.bytes[0] = 0x8f;
3135 i.vex.bytes[0] = 0x8f;
3141 /* The high 3 bits of the second VEX byte are 1's compliment
3142 of RXB bits from REX. */
3143 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3145 /* Check the REX.W bit. */
3146 w = (i.rex & REX_W) ? 1 : 0;
3147 if (i.tm.opcode_modifier.vexw == VEXW1)
3150 i.vex.bytes[2] = (w << 7
3151 | register_specifier << 3
3152 | vector_length << 2
3157 /* Build the EVEX prefix. */
3160 build_evex_prefix (void)
3162 unsigned int register_specifier;
3163 unsigned int implied_prefix;
3165 rex_byte vrex_used = 0;
3167 /* Check register specifier. */
3168 if (i.vex.register_specifier)
3170 gas_assert ((i.vrex & REX_X) == 0);
3172 register_specifier = i.vex.register_specifier->reg_num;
3173 if ((i.vex.register_specifier->reg_flags & RegRex))
3174 register_specifier += 8;
3175 /* The upper 16 registers are encoded in the fourth byte of the
3177 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3178 i.vex.bytes[3] = 0x8;
3179 register_specifier = ~register_specifier & 0xf;
3183 register_specifier = 0xf;
3185 /* Encode upper 16 vector index register in the fourth byte of
3187 if (!(i.vrex & REX_X))
3188 i.vex.bytes[3] = 0x8;
3193 switch ((i.tm.base_opcode >> 8) & 0xff)
3198 case DATA_PREFIX_OPCODE:
3201 case REPE_PREFIX_OPCODE:
3204 case REPNE_PREFIX_OPCODE:
3211 /* 4 byte EVEX prefix. */
3213 i.vex.bytes[0] = 0x62;
3216 switch (i.tm.opcode_modifier.vexopcode)
3232 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3234 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3236 /* The fifth bit of the second EVEX byte is 1's compliment of the
3237 REX_R bit in VREX. */
3238 if (!(i.vrex & REX_R))
3239 i.vex.bytes[1] |= 0x10;
3243 if ((i.reg_operands + i.imm_operands) == i.operands)
3245 /* When all operands are registers, the REX_X bit in REX is not
3246 used. We reuse it to encode the upper 16 registers, which is
3247 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3248 as 1's compliment. */
3249 if ((i.vrex & REX_B))
3252 i.vex.bytes[1] &= ~0x40;
3256 /* EVEX instructions shouldn't need the REX prefix. */
3257 i.vrex &= ~vrex_used;
3258 gas_assert (i.vrex == 0);
3260 /* Check the REX.W bit. */
3261 w = (i.rex & REX_W) ? 1 : 0;
3262 if (i.tm.opcode_modifier.vexw)
3264 if (i.tm.opcode_modifier.vexw == VEXW1)
3267 /* If w is not set it means we are dealing with WIG instruction. */
3270 if (evexwig == evexw1)
3274 /* Encode the U bit. */
3275 implied_prefix |= 0x4;
3277 /* The third byte of the EVEX prefix. */
3278 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3280 /* The fourth byte of the EVEX prefix. */
3281 /* The zeroing-masking bit. */
3282 if (i.mask && i.mask->zeroing)
3283 i.vex.bytes[3] |= 0x80;
3285 /* Don't always set the broadcast bit if there is no RC. */
3288 /* Encode the vector length. */
3289 unsigned int vec_length;
3291 switch (i.tm.opcode_modifier.evex)
3293 case EVEXLIG: /* LL' is ignored */
3294 vec_length = evexlig << 5;
3297 vec_length = 0 << 5;
3300 vec_length = 1 << 5;
3303 vec_length = 2 << 5;
3309 i.vex.bytes[3] |= vec_length;
3310 /* Encode the broadcast bit. */
3312 i.vex.bytes[3] |= 0x10;
3316 if (i.rounding->type != saeonly)
3317 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3319 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3322 if (i.mask && i.mask->mask)
3323 i.vex.bytes[3] |= i.mask->mask->reg_num;
3327 process_immext (void)
3331 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3334 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3335 with an opcode suffix which is coded in the same place as an
3336 8-bit immediate field would be.
3337 Here we check those operands and remove them afterwards. */
3340 for (x = 0; x < i.operands; x++)
3341 if (register_number (i.op[x].regs) != x)
3342 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3343 register_prefix, i.op[x].regs->reg_name, x + 1,
3349 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3351 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3352 suffix which is coded in the same place as an 8-bit immediate
3354 Here we check those operands and remove them afterwards. */
3357 if (i.operands != 3)
3360 for (x = 0; x < 2; x++)
3361 if (register_number (i.op[x].regs) != x)
3362 goto bad_register_operand;
3364 /* Check for third operand for mwaitx/monitorx insn. */
3365 if (register_number (i.op[x].regs)
3366 != (x + (i.tm.extension_opcode == 0xfb)))
3368 bad_register_operand:
3369 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3370 register_prefix, i.op[x].regs->reg_name, x+1,
3377 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3378 which is coded in the same place as an 8-bit immediate field
3379 would be. Here we fake an 8-bit immediate operand from the
3380 opcode suffix stored in tm.extension_opcode.
3382 AVX instructions also use this encoding, for some of
3383 3 argument instructions. */
3385 gas_assert (i.imm_operands <= 1
3387 || ((i.tm.opcode_modifier.vex
3388 || i.tm.opcode_modifier.evex)
3389 && i.operands <= 4)));
3391 exp = &im_expressions[i.imm_operands++];
3392 i.op[i.operands].imms = exp;
3393 i.types[i.operands] = imm8;
3395 exp->X_op = O_constant;
3396 exp->X_add_number = i.tm.extension_opcode;
3397 i.tm.extension_opcode = None;
3404 switch (i.tm.opcode_modifier.hleprefixok)
3409 as_bad (_("invalid instruction `%s' after `%s'"),
3410 i.tm.name, i.hle_prefix);
3413 if (i.prefix[LOCK_PREFIX])
3415 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3419 case HLEPrefixRelease:
3420 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3422 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3426 if (i.mem_operands == 0
3427 || !operand_type_check (i.types[i.operands - 1], anymem))
3429 as_bad (_("memory destination needed for instruction `%s'"
3430 " after `xrelease'"), i.tm.name);
3437 /* This is the guts of the machine-dependent assembler. LINE points to a
3438 machine dependent instruction. This function is supposed to emit
3439 the frags/bytes it assembles to. */
3442 md_assemble (char *line)
3445 char mnemonic[MAX_MNEM_SIZE];
3446 const insn_template *t;
3448 /* Initialize globals. */
3449 memset (&i, '\0', sizeof (i));
3450 for (j = 0; j < MAX_OPERANDS; j++)
3451 i.reloc[j] = NO_RELOC;
3452 memset (disp_expressions, '\0', sizeof (disp_expressions));
3453 memset (im_expressions, '\0', sizeof (im_expressions));
3454 save_stack_p = save_stack;
3456 /* First parse an instruction mnemonic & call i386_operand for the operands.
3457 We assume that the scrubber has arranged it so that line[0] is the valid
3458 start of a (possibly prefixed) mnemonic. */
3460 line = parse_insn (line, mnemonic);
3464 line = parse_operands (line, mnemonic);
3469 /* Now we've parsed the mnemonic into a set of templates, and have the
3470 operands at hand. */
3472 /* All intel opcodes have reversed operands except for "bound" and
3473 "enter". We also don't reverse intersegment "jmp" and "call"
3474 instructions with 2 immediate operands so that the immediate segment
3475 precedes the offset, as it does when in AT&T mode. */
3478 && (strcmp (mnemonic, "bound") != 0)
3479 && (strcmp (mnemonic, "invlpga") != 0)
3480 && !(operand_type_check (i.types[0], imm)
3481 && operand_type_check (i.types[1], imm)))
3484 /* The order of the immediates should be reversed
3485 for 2 immediates extrq and insertq instructions */
3486 if (i.imm_operands == 2
3487 && (strcmp (mnemonic, "extrq") == 0
3488 || strcmp (mnemonic, "insertq") == 0))
3489 swap_2_operands (0, 1);
3494 /* Don't optimize displacement for movabs since it only takes 64bit
3497 && i.disp_encoding != disp_encoding_32bit
3498 && (flag_code != CODE_64BIT
3499 || strcmp (mnemonic, "movabs") != 0))
3502 /* Next, we find a template that matches the given insn,
3503 making sure the overlap of the given operands types is consistent
3504 with the template operand types. */
3506 if (!(t = match_template ()))
3509 if (sse_check != check_none
3510 && !i.tm.opcode_modifier.noavx
3511 && (i.tm.cpu_flags.bitfield.cpusse
3512 || i.tm.cpu_flags.bitfield.cpusse2
3513 || i.tm.cpu_flags.bitfield.cpusse3
3514 || i.tm.cpu_flags.bitfield.cpussse3
3515 || i.tm.cpu_flags.bitfield.cpusse4_1
3516 || i.tm.cpu_flags.bitfield.cpusse4_2))
3518 (sse_check == check_warning
3520 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3523 /* Zap movzx and movsx suffix. The suffix has been set from
3524 "word ptr" or "byte ptr" on the source operand in Intel syntax
3525 or extracted from mnemonic in AT&T syntax. But we'll use
3526 the destination register to choose the suffix for encoding. */
3527 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3529 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3530 there is no suffix, the default will be byte extension. */
3531 if (i.reg_operands != 2
3534 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3539 if (i.tm.opcode_modifier.fwait)
3540 if (!add_prefix (FWAIT_OPCODE))
3543 /* Check if REP prefix is OK. */
3544 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3546 as_bad (_("invalid instruction `%s' after `%s'"),
3547 i.tm.name, i.rep_prefix);
3551 /* Check for lock without a lockable instruction. Destination operand
3552 must be memory unless it is xchg (0x86). */
3553 if (i.prefix[LOCK_PREFIX]
3554 && (!i.tm.opcode_modifier.islockable
3555 || i.mem_operands == 0
3556 || (i.tm.base_opcode != 0x86
3557 && !operand_type_check (i.types[i.operands - 1], anymem))))
3559 as_bad (_("expecting lockable instruction after `lock'"));
3563 /* Check if HLE prefix is OK. */
3564 if (i.hle_prefix && !check_hle ())
3567 /* Check BND prefix. */
3568 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3569 as_bad (_("expecting valid branch instruction after `bnd'"));
3571 if (i.tm.cpu_flags.bitfield.cpumpx
3572 && flag_code == CODE_64BIT
3573 && i.prefix[ADDR_PREFIX])
3574 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3576 /* Insert BND prefix. */
3578 && i.tm.opcode_modifier.bndprefixok
3579 && !i.prefix[BND_PREFIX])
3580 add_prefix (BND_PREFIX_OPCODE);
3582 /* Check string instruction segment overrides. */
3583 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3585 if (!check_string ())
3587 i.disp_operands = 0;
3590 if (!process_suffix ())
3593 /* Update operand types. */
3594 for (j = 0; j < i.operands; j++)
3595 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3597 /* Make still unresolved immediate matches conform to size of immediate
3598 given in i.suffix. */
3599 if (!finalize_imm ())
3602 if (i.types[0].bitfield.imm1)
3603 i.imm_operands = 0; /* kludge for shift insns. */
3605 /* We only need to check those implicit registers for instructions
3606 with 3 operands or less. */
3607 if (i.operands <= 3)
3608 for (j = 0; j < i.operands; j++)
3609 if (i.types[j].bitfield.inoutportreg
3610 || i.types[j].bitfield.shiftcount
3611 || i.types[j].bitfield.acc
3612 || i.types[j].bitfield.floatacc)
3615 /* ImmExt should be processed after SSE2AVX. */
3616 if (!i.tm.opcode_modifier.sse2avx
3617 && i.tm.opcode_modifier.immext)
3620 /* For insns with operands there are more diddles to do to the opcode. */
3623 if (!process_operands ())
3626 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3628 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3629 as_warn (_("translating to `%sp'"), i.tm.name);
3632 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3634 if (flag_code == CODE_16BIT)
3636 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3641 if (i.tm.opcode_modifier.vex)
3642 build_vex_prefix (t);
3644 build_evex_prefix ();
3647 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3648 instructions may define INT_OPCODE as well, so avoid this corner
3649 case for those instructions that use MODRM. */
3650 if (i.tm.base_opcode == INT_OPCODE
3651 && !i.tm.opcode_modifier.modrm
3652 && i.op[0].imms->X_add_number == 3)
3654 i.tm.base_opcode = INT3_OPCODE;
3658 if ((i.tm.opcode_modifier.jump
3659 || i.tm.opcode_modifier.jumpbyte
3660 || i.tm.opcode_modifier.jumpdword)
3661 && i.op[0].disps->X_op == O_constant)
3663 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3664 the absolute address given by the constant. Since ix86 jumps and
3665 calls are pc relative, we need to generate a reloc. */
3666 i.op[0].disps->X_add_symbol = &abs_symbol;
3667 i.op[0].disps->X_op = O_symbol;
3670 if (i.tm.opcode_modifier.rex64)
3673 /* For 8 bit registers we need an empty rex prefix. Also if the
3674 instruction already has a prefix, we need to convert old
3675 registers to new ones. */
3677 if ((i.types[0].bitfield.reg8
3678 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3679 || (i.types[1].bitfield.reg8
3680 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3681 || ((i.types[0].bitfield.reg8
3682 || i.types[1].bitfield.reg8)
3687 i.rex |= REX_OPCODE;
3688 for (x = 0; x < 2; x++)
3690 /* Look for 8 bit operand that uses old registers. */
3691 if (i.types[x].bitfield.reg8
3692 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3694 /* In case it is "hi" register, give up. */
3695 if (i.op[x].regs->reg_num > 3)
3696 as_bad (_("can't encode register '%s%s' in an "
3697 "instruction requiring REX prefix."),
3698 register_prefix, i.op[x].regs->reg_name);
3700 /* Otherwise it is equivalent to the extended register.
3701 Since the encoding doesn't change this is merely
3702 cosmetic cleanup for debug output. */
3704 i.op[x].regs = i.op[x].regs + 8;
3710 add_prefix (REX_OPCODE | i.rex);
3712 /* We are ready to output the insn. */
3717 parse_insn (char *line, char *mnemonic)
3720 char *token_start = l;
3723 const insn_template *t;
3729 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3734 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3736 as_bad (_("no such instruction: `%s'"), token_start);
3741 if (!is_space_char (*l)
3742 && *l != END_OF_INSN
3744 || (*l != PREFIX_SEPARATOR
3747 as_bad (_("invalid character %s in mnemonic"),
3748 output_invalid (*l));
3751 if (token_start == l)
3753 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3754 as_bad (_("expecting prefix; got nothing"));
3756 as_bad (_("expecting mnemonic; got nothing"));
3760 /* Look up instruction (or prefix) via hash table. */
3761 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3763 if (*l != END_OF_INSN
3764 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3765 && current_templates
3766 && current_templates->start->opcode_modifier.isprefix)
3768 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3770 as_bad ((flag_code != CODE_64BIT
3771 ? _("`%s' is only supported in 64-bit mode")
3772 : _("`%s' is not supported in 64-bit mode")),
3773 current_templates->start->name);
3776 /* If we are in 16-bit mode, do not allow addr16 or data16.
3777 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3778 if ((current_templates->start->opcode_modifier.size16
3779 || current_templates->start->opcode_modifier.size32)
3780 && flag_code != CODE_64BIT
3781 && (current_templates->start->opcode_modifier.size32
3782 ^ (flag_code == CODE_16BIT)))
3784 as_bad (_("redundant %s prefix"),
3785 current_templates->start->name);
3788 /* Add prefix, checking for repeated prefixes. */
3789 switch (add_prefix (current_templates->start->base_opcode))
3794 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3795 i.hle_prefix = current_templates->start->name;
3796 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3797 i.bnd_prefix = current_templates->start->name;
3799 i.rep_prefix = current_templates->start->name;
3804 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3811 if (!current_templates)
3813 /* Check if we should swap operand or force 32bit displacement in
3815 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3817 else if (mnem_p - 3 == dot_p
3820 i.disp_encoding = disp_encoding_8bit;
3821 else if (mnem_p - 4 == dot_p
3825 i.disp_encoding = disp_encoding_32bit;
3830 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3833 if (!current_templates)
3836 /* See if we can get a match by trimming off a suffix. */
3839 case WORD_MNEM_SUFFIX:
3840 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3841 i.suffix = SHORT_MNEM_SUFFIX;
3843 case BYTE_MNEM_SUFFIX:
3844 case QWORD_MNEM_SUFFIX:
3845 i.suffix = mnem_p[-1];
3847 current_templates = (const templates *) hash_find (op_hash,
3850 case SHORT_MNEM_SUFFIX:
3851 case LONG_MNEM_SUFFIX:
3854 i.suffix = mnem_p[-1];
3856 current_templates = (const templates *) hash_find (op_hash,
3865 if (intel_float_operand (mnemonic) == 1)
3866 i.suffix = SHORT_MNEM_SUFFIX;
3868 i.suffix = LONG_MNEM_SUFFIX;
3870 current_templates = (const templates *) hash_find (op_hash,
3875 if (!current_templates)
3877 as_bad (_("no such instruction: `%s'"), token_start);
3882 if (current_templates->start->opcode_modifier.jump
3883 || current_templates->start->opcode_modifier.jumpbyte)
3885 /* Check for a branch hint. We allow ",pt" and ",pn" for
3886 predict taken and predict not taken respectively.
3887 I'm not sure that branch hints actually do anything on loop
3888 and jcxz insns (JumpByte) for current Pentium4 chips. They
3889 may work in the future and it doesn't hurt to accept them
3891 if (l[0] == ',' && l[1] == 'p')
3895 if (!add_prefix (DS_PREFIX_OPCODE))
3899 else if (l[2] == 'n')
3901 if (!add_prefix (CS_PREFIX_OPCODE))
3907 /* Any other comma loses. */
3910 as_bad (_("invalid character %s in mnemonic"),
3911 output_invalid (*l));
3915 /* Check if instruction is supported on specified architecture. */
3917 for (t = current_templates->start; t < current_templates->end; ++t)
3919 supported |= cpu_flags_match (t);
3920 if (supported == CPU_FLAGS_PERFECT_MATCH)
3924 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3926 as_bad (flag_code == CODE_64BIT
3927 ? _("`%s' is not supported in 64-bit mode")
3928 : _("`%s' is only supported in 64-bit mode"),
3929 current_templates->start->name);
3932 if (supported != CPU_FLAGS_PERFECT_MATCH)
3934 as_bad (_("`%s' is not supported on `%s%s'"),
3935 current_templates->start->name,
3936 cpu_arch_name ? cpu_arch_name : default_arch,
3937 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3942 if (!cpu_arch_flags.bitfield.cpui386
3943 && (flag_code != CODE_16BIT))
3945 as_warn (_("use .code16 to ensure correct addressing mode"));
3952 parse_operands (char *l, const char *mnemonic)
3956 /* 1 if operand is pending after ','. */
3957 unsigned int expecting_operand = 0;
3959 /* Non-zero if operand parens not balanced. */
3960 unsigned int paren_not_balanced;
3962 while (*l != END_OF_INSN)
3964 /* Skip optional white space before operand. */
3965 if (is_space_char (*l))
3967 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
3969 as_bad (_("invalid character %s before operand %d"),
3970 output_invalid (*l),
3974 token_start = l; /* After white space. */
3975 paren_not_balanced = 0;
3976 while (paren_not_balanced || *l != ',')
3978 if (*l == END_OF_INSN)
3980 if (paren_not_balanced)
3983 as_bad (_("unbalanced parenthesis in operand %d."),
3986 as_bad (_("unbalanced brackets in operand %d."),
3991 break; /* we are done */
3993 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
3995 as_bad (_("invalid character %s in operand %d"),
3996 output_invalid (*l),
4003 ++paren_not_balanced;
4005 --paren_not_balanced;
4010 ++paren_not_balanced;
4012 --paren_not_balanced;
4016 if (l != token_start)
4017 { /* Yes, we've read in another operand. */
4018 unsigned int operand_ok;
4019 this_operand = i.operands++;
4020 i.types[this_operand].bitfield.unspecified = 1;
4021 if (i.operands > MAX_OPERANDS)
4023 as_bad (_("spurious operands; (%d operands/instruction max)"),
4027 /* Now parse operand adding info to 'i' as we go along. */
4028 END_STRING_AND_SAVE (l);
4032 i386_intel_operand (token_start,
4033 intel_float_operand (mnemonic));
4035 operand_ok = i386_att_operand (token_start);
4037 RESTORE_END_STRING (l);
4043 if (expecting_operand)
4045 expecting_operand_after_comma:
4046 as_bad (_("expecting operand after ','; got nothing"));
4051 as_bad (_("expecting operand before ','; got nothing"));
4056 /* Now *l must be either ',' or END_OF_INSN. */
4059 if (*++l == END_OF_INSN)
4061 /* Just skip it, if it's \n complain. */
4062 goto expecting_operand_after_comma;
4064 expecting_operand = 1;
4071 swap_2_operands (int xchg1, int xchg2)
4073 union i386_op temp_op;
4074 i386_operand_type temp_type;
4075 enum bfd_reloc_code_real temp_reloc;
4077 temp_type = i.types[xchg2];
4078 i.types[xchg2] = i.types[xchg1];
4079 i.types[xchg1] = temp_type;
4080 temp_op = i.op[xchg2];
4081 i.op[xchg2] = i.op[xchg1];
4082 i.op[xchg1] = temp_op;
4083 temp_reloc = i.reloc[xchg2];
4084 i.reloc[xchg2] = i.reloc[xchg1];
4085 i.reloc[xchg1] = temp_reloc;
4089 if (i.mask->operand == xchg1)
4090 i.mask->operand = xchg2;
4091 else if (i.mask->operand == xchg2)
4092 i.mask->operand = xchg1;
4096 if (i.broadcast->operand == xchg1)
4097 i.broadcast->operand = xchg2;
4098 else if (i.broadcast->operand == xchg2)
4099 i.broadcast->operand = xchg1;
4103 if (i.rounding->operand == xchg1)
4104 i.rounding->operand = xchg2;
4105 else if (i.rounding->operand == xchg2)
4106 i.rounding->operand = xchg1;
4111 swap_operands (void)
4117 swap_2_operands (1, i.operands - 2);
4120 swap_2_operands (0, i.operands - 1);
4126 if (i.mem_operands == 2)
4128 const seg_entry *temp_seg;
4129 temp_seg = i.seg[0];
4130 i.seg[0] = i.seg[1];
4131 i.seg[1] = temp_seg;
4135 /* Try to ensure constant immediates are represented in the smallest
4140 char guess_suffix = 0;
4144 guess_suffix = i.suffix;
4145 else if (i.reg_operands)
4147 /* Figure out a suffix from the last register operand specified.
4148 We can't do this properly yet, ie. excluding InOutPortReg,
4149 but the following works for instructions with immediates.
4150 In any case, we can't set i.suffix yet. */
4151 for (op = i.operands; --op >= 0;)
4152 if (i.types[op].bitfield.reg8)
4154 guess_suffix = BYTE_MNEM_SUFFIX;
4157 else if (i.types[op].bitfield.reg16)
4159 guess_suffix = WORD_MNEM_SUFFIX;
4162 else if (i.types[op].bitfield.reg32)
4164 guess_suffix = LONG_MNEM_SUFFIX;
4167 else if (i.types[op].bitfield.reg64)
4169 guess_suffix = QWORD_MNEM_SUFFIX;
4173 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4174 guess_suffix = WORD_MNEM_SUFFIX;
4176 for (op = i.operands; --op >= 0;)
4177 if (operand_type_check (i.types[op], imm))
4179 switch (i.op[op].imms->X_op)
4182 /* If a suffix is given, this operand may be shortened. */
4183 switch (guess_suffix)
4185 case LONG_MNEM_SUFFIX:
4186 i.types[op].bitfield.imm32 = 1;
4187 i.types[op].bitfield.imm64 = 1;
4189 case WORD_MNEM_SUFFIX:
4190 i.types[op].bitfield.imm16 = 1;
4191 i.types[op].bitfield.imm32 = 1;
4192 i.types[op].bitfield.imm32s = 1;
4193 i.types[op].bitfield.imm64 = 1;
4195 case BYTE_MNEM_SUFFIX:
4196 i.types[op].bitfield.imm8 = 1;
4197 i.types[op].bitfield.imm8s = 1;
4198 i.types[op].bitfield.imm16 = 1;
4199 i.types[op].bitfield.imm32 = 1;
4200 i.types[op].bitfield.imm32s = 1;
4201 i.types[op].bitfield.imm64 = 1;
4205 /* If this operand is at most 16 bits, convert it
4206 to a signed 16 bit number before trying to see
4207 whether it will fit in an even smaller size.
4208 This allows a 16-bit operand such as $0xffe0 to
4209 be recognised as within Imm8S range. */
4210 if ((i.types[op].bitfield.imm16)
4211 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4213 i.op[op].imms->X_add_number =
4214 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4216 if ((i.types[op].bitfield.imm32)
4217 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4220 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4221 ^ ((offsetT) 1 << 31))
4222 - ((offsetT) 1 << 31));
4225 = operand_type_or (i.types[op],
4226 smallest_imm_type (i.op[op].imms->X_add_number));
4228 /* We must avoid matching of Imm32 templates when 64bit
4229 only immediate is available. */
4230 if (guess_suffix == QWORD_MNEM_SUFFIX)
4231 i.types[op].bitfield.imm32 = 0;
4238 /* Symbols and expressions. */
4240 /* Convert symbolic operand to proper sizes for matching, but don't
4241 prevent matching a set of insns that only supports sizes other
4242 than those matching the insn suffix. */
4244 i386_operand_type mask, allowed;
4245 const insn_template *t;
4247 operand_type_set (&mask, 0);
4248 operand_type_set (&allowed, 0);
4250 for (t = current_templates->start;
4251 t < current_templates->end;
4253 allowed = operand_type_or (allowed,
4254 t->operand_types[op]);
4255 switch (guess_suffix)
4257 case QWORD_MNEM_SUFFIX:
4258 mask.bitfield.imm64 = 1;
4259 mask.bitfield.imm32s = 1;
4261 case LONG_MNEM_SUFFIX:
4262 mask.bitfield.imm32 = 1;
4264 case WORD_MNEM_SUFFIX:
4265 mask.bitfield.imm16 = 1;
4267 case BYTE_MNEM_SUFFIX:
4268 mask.bitfield.imm8 = 1;
4273 allowed = operand_type_and (mask, allowed);
4274 if (!operand_type_all_zero (&allowed))
4275 i.types[op] = operand_type_and (i.types[op], mask);
4282 /* Try to use the smallest displacement type too. */
4284 optimize_disp (void)
4288 for (op = i.operands; --op >= 0;)
4289 if (operand_type_check (i.types[op], disp))
4291 if (i.op[op].disps->X_op == O_constant)
4293 offsetT op_disp = i.op[op].disps->X_add_number;
4295 if (i.types[op].bitfield.disp16
4296 && (op_disp & ~(offsetT) 0xffff) == 0)
4298 /* If this operand is at most 16 bits, convert
4299 to a signed 16 bit number and don't use 64bit
4301 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4302 i.types[op].bitfield.disp64 = 0;
4304 if (i.types[op].bitfield.disp32
4305 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4307 /* If this operand is at most 32 bits, convert
4308 to a signed 32 bit number and don't use 64bit
4310 op_disp &= (((offsetT) 2 << 31) - 1);
4311 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4312 i.types[op].bitfield.disp64 = 0;
4314 if (!op_disp && i.types[op].bitfield.baseindex)
4316 i.types[op].bitfield.disp8 = 0;
4317 i.types[op].bitfield.disp16 = 0;
4318 i.types[op].bitfield.disp32 = 0;
4319 i.types[op].bitfield.disp32s = 0;
4320 i.types[op].bitfield.disp64 = 0;
4324 else if (flag_code == CODE_64BIT)
4326 if (fits_in_signed_long (op_disp))
4328 i.types[op].bitfield.disp64 = 0;
4329 i.types[op].bitfield.disp32s = 1;
4331 if (i.prefix[ADDR_PREFIX]
4332 && fits_in_unsigned_long (op_disp))
4333 i.types[op].bitfield.disp32 = 1;
4335 if ((i.types[op].bitfield.disp32
4336 || i.types[op].bitfield.disp32s
4337 || i.types[op].bitfield.disp16)
4338 && fits_in_signed_byte (op_disp))
4339 i.types[op].bitfield.disp8 = 1;
4341 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4342 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4344 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4345 i.op[op].disps, 0, i.reloc[op]);
4346 i.types[op].bitfield.disp8 = 0;
4347 i.types[op].bitfield.disp16 = 0;
4348 i.types[op].bitfield.disp32 = 0;
4349 i.types[op].bitfield.disp32s = 0;
4350 i.types[op].bitfield.disp64 = 0;
4353 /* We only support 64bit displacement on constants. */
4354 i.types[op].bitfield.disp64 = 0;
4358 /* Check if operands are valid for the instruction. */
4361 check_VecOperands (const insn_template *t)
4365 /* Without VSIB byte, we can't have a vector register for index. */
4366 if (!t->opcode_modifier.vecsib
4368 && (i.index_reg->reg_type.bitfield.regxmm
4369 || i.index_reg->reg_type.bitfield.regymm
4370 || i.index_reg->reg_type.bitfield.regzmm))
4372 i.error = unsupported_vector_index_register;
4376 /* Check if default mask is allowed. */
4377 if (t->opcode_modifier.nodefmask
4378 && (!i.mask || i.mask->mask->reg_num == 0))
4380 i.error = no_default_mask;
4384 /* For VSIB byte, we need a vector register for index, and all vector
4385 registers must be distinct. */
4386 if (t->opcode_modifier.vecsib)
4389 || !((t->opcode_modifier.vecsib == VecSIB128
4390 && i.index_reg->reg_type.bitfield.regxmm)
4391 || (t->opcode_modifier.vecsib == VecSIB256
4392 && i.index_reg->reg_type.bitfield.regymm)
4393 || (t->opcode_modifier.vecsib == VecSIB512
4394 && i.index_reg->reg_type.bitfield.regzmm)))
4396 i.error = invalid_vsib_address;
4400 gas_assert (i.reg_operands == 2 || i.mask);
4401 if (i.reg_operands == 2 && !i.mask)
4403 gas_assert (i.types[0].bitfield.regxmm
4404 || i.types[0].bitfield.regymm);
4405 gas_assert (i.types[2].bitfield.regxmm
4406 || i.types[2].bitfield.regymm);
4407 if (operand_check == check_none)
4409 if (register_number (i.op[0].regs)
4410 != register_number (i.index_reg)
4411 && register_number (i.op[2].regs)
4412 != register_number (i.index_reg)
4413 && register_number (i.op[0].regs)
4414 != register_number (i.op[2].regs))
4416 if (operand_check == check_error)
4418 i.error = invalid_vector_register_set;
4421 as_warn (_("mask, index, and destination registers should be distinct"));
4423 else if (i.reg_operands == 1 && i.mask)
4425 if ((i.types[1].bitfield.regymm
4426 || i.types[1].bitfield.regzmm)
4427 && (register_number (i.op[1].regs)
4428 == register_number (i.index_reg)))
4430 if (operand_check == check_error)
4432 i.error = invalid_vector_register_set;
4435 if (operand_check != check_none)
4436 as_warn (_("index and destination registers should be distinct"));
4441 /* Check if broadcast is supported by the instruction and is applied
4442 to the memory operand. */
4445 int broadcasted_opnd_size;
4447 /* Check if specified broadcast is supported in this instruction,
4448 and it's applied to memory operand of DWORD or QWORD type,
4449 depending on VecESize. */
4450 if (i.broadcast->type != t->opcode_modifier.broadcast
4451 || !i.types[i.broadcast->operand].bitfield.mem
4452 || (t->opcode_modifier.vecesize == 0
4453 && !i.types[i.broadcast->operand].bitfield.dword
4454 && !i.types[i.broadcast->operand].bitfield.unspecified)
4455 || (t->opcode_modifier.vecesize == 1
4456 && !i.types[i.broadcast->operand].bitfield.qword
4457 && !i.types[i.broadcast->operand].bitfield.unspecified))
4460 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4461 if (i.broadcast->type == BROADCAST_1TO16)
4462 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4463 else if (i.broadcast->type == BROADCAST_1TO8)
4464 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4465 else if (i.broadcast->type == BROADCAST_1TO4)
4466 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4467 else if (i.broadcast->type == BROADCAST_1TO2)
4468 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4472 if ((broadcasted_opnd_size == 256
4473 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4474 || (broadcasted_opnd_size == 512
4475 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4478 i.error = unsupported_broadcast;
4482 /* If broadcast is supported in this instruction, we need to check if
4483 operand of one-element size isn't specified without broadcast. */
4484 else if (t->opcode_modifier.broadcast && i.mem_operands)
4486 /* Find memory operand. */
4487 for (op = 0; op < i.operands; op++)
4488 if (operand_type_check (i.types[op], anymem))
4490 gas_assert (op < i.operands);
4491 /* Check size of the memory operand. */
4492 if ((t->opcode_modifier.vecesize == 0
4493 && i.types[op].bitfield.dword)
4494 || (t->opcode_modifier.vecesize == 1
4495 && i.types[op].bitfield.qword))
4497 i.error = broadcast_needed;
4502 /* Check if requested masking is supported. */
4504 && (!t->opcode_modifier.masking
4506 && t->opcode_modifier.masking == MERGING_MASKING)))
4508 i.error = unsupported_masking;
4512 /* Check if masking is applied to dest operand. */
4513 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4515 i.error = mask_not_on_destination;
4522 if ((i.rounding->type != saeonly
4523 && !t->opcode_modifier.staticrounding)
4524 || (i.rounding->type == saeonly
4525 && (t->opcode_modifier.staticrounding
4526 || !t->opcode_modifier.sae)))
4528 i.error = unsupported_rc_sae;
4531 /* If the instruction has several immediate operands and one of
4532 them is rounding, the rounding operand should be the last
4533 immediate operand. */
4534 if (i.imm_operands > 1
4535 && i.rounding->operand != (int) (i.imm_operands - 1))
4537 i.error = rc_sae_operand_not_last_imm;
4542 /* Check vector Disp8 operand. */
4543 if (t->opcode_modifier.disp8memshift)
4546 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4548 i.memshift = t->opcode_modifier.disp8memshift;
4550 for (op = 0; op < i.operands; op++)
4551 if (operand_type_check (i.types[op], disp)
4552 && i.op[op].disps->X_op == O_constant)
4554 offsetT value = i.op[op].disps->X_add_number;
4555 int vec_disp8_ok = fits_in_vec_disp8 (value);
4556 if (t->operand_types [op].bitfield.vec_disp8)
4559 i.types[op].bitfield.vec_disp8 = 1;
4562 /* Vector insn can only have Vec_Disp8/Disp32 in
4563 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4565 i.types[op].bitfield.disp8 = 0;
4566 if (flag_code != CODE_16BIT)
4567 i.types[op].bitfield.disp16 = 0;
4570 else if (flag_code != CODE_16BIT)
4572 /* One form of this instruction supports vector Disp8.
4573 Try vector Disp8 if we need to use Disp32. */
4574 if (vec_disp8_ok && !fits_in_signed_byte (value))
4576 i.error = try_vector_disp8;
4588 /* Check if operands are valid for the instruction. Update VEX
4592 VEX_check_operands (const insn_template *t)
4594 /* VREX is only valid with EVEX prefix. */
4595 if (i.need_vrex && !t->opcode_modifier.evex)
4597 i.error = invalid_register_operand;
4601 if (!t->opcode_modifier.vex)
4604 /* Only check VEX_Imm4, which must be the first operand. */
4605 if (t->operand_types[0].bitfield.vec_imm4)
4607 if (i.op[0].imms->X_op != O_constant
4608 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4614 /* Turn off Imm8 so that update_imm won't complain. */
4615 i.types[0] = vec_imm4;
4621 static const insn_template *
4622 match_template (void)
4624 /* Points to template once we've found it. */
4625 const insn_template *t;
4626 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4627 i386_operand_type overlap4;
4628 unsigned int found_reverse_match;
4629 i386_opcode_modifier suffix_check;
4630 i386_operand_type operand_types [MAX_OPERANDS];
4631 int addr_prefix_disp;
4633 unsigned int found_cpu_match;
4634 unsigned int check_register;
4635 enum i386_error specific_error = 0;
4637 #if MAX_OPERANDS != 5
4638 # error "MAX_OPERANDS must be 5."
4641 found_reverse_match = 0;
4642 addr_prefix_disp = -1;
4644 memset (&suffix_check, 0, sizeof (suffix_check));
4645 if (i.suffix == BYTE_MNEM_SUFFIX)
4646 suffix_check.no_bsuf = 1;
4647 else if (i.suffix == WORD_MNEM_SUFFIX)
4648 suffix_check.no_wsuf = 1;
4649 else if (i.suffix == SHORT_MNEM_SUFFIX)
4650 suffix_check.no_ssuf = 1;
4651 else if (i.suffix == LONG_MNEM_SUFFIX)
4652 suffix_check.no_lsuf = 1;
4653 else if (i.suffix == QWORD_MNEM_SUFFIX)
4654 suffix_check.no_qsuf = 1;
4655 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4656 suffix_check.no_ldsuf = 1;
4658 /* Must have right number of operands. */
4659 i.error = number_of_operands_mismatch;
4661 for (t = current_templates->start; t < current_templates->end; t++)
4663 addr_prefix_disp = -1;
4665 if (i.operands != t->operands)
4668 /* Check processor support. */
4669 i.error = unsupported;
4670 found_cpu_match = (cpu_flags_match (t)
4671 == CPU_FLAGS_PERFECT_MATCH);
4672 if (!found_cpu_match)
4675 /* Check old gcc support. */
4676 i.error = old_gcc_only;
4677 if (!old_gcc && t->opcode_modifier.oldgcc)
4680 /* Check AT&T mnemonic. */
4681 i.error = unsupported_with_intel_mnemonic;
4682 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4685 /* Check AT&T/Intel syntax. */
4686 i.error = unsupported_syntax;
4687 if ((intel_syntax && t->opcode_modifier.attsyntax)
4688 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4691 /* Check the suffix, except for some instructions in intel mode. */
4692 i.error = invalid_instruction_suffix;
4693 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4694 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4695 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4696 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4697 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4698 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4699 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4702 if (!operand_size_match (t))
4705 for (j = 0; j < MAX_OPERANDS; j++)
4706 operand_types[j] = t->operand_types[j];
4708 /* In general, don't allow 64-bit operands in 32-bit mode. */
4709 if (i.suffix == QWORD_MNEM_SUFFIX
4710 && flag_code != CODE_64BIT
4712 ? (!t->opcode_modifier.ignoresize
4713 && !intel_float_operand (t->name))
4714 : intel_float_operand (t->name) != 2)
4715 && ((!operand_types[0].bitfield.regmmx
4716 && !operand_types[0].bitfield.regxmm
4717 && !operand_types[0].bitfield.regymm
4718 && !operand_types[0].bitfield.regzmm)
4719 || (!operand_types[t->operands > 1].bitfield.regmmx
4720 && operand_types[t->operands > 1].bitfield.regxmm
4721 && operand_types[t->operands > 1].bitfield.regymm
4722 && operand_types[t->operands > 1].bitfield.regzmm))
4723 && (t->base_opcode != 0x0fc7
4724 || t->extension_opcode != 1 /* cmpxchg8b */))
4727 /* In general, don't allow 32-bit operands on pre-386. */
4728 else if (i.suffix == LONG_MNEM_SUFFIX
4729 && !cpu_arch_flags.bitfield.cpui386
4731 ? (!t->opcode_modifier.ignoresize
4732 && !intel_float_operand (t->name))
4733 : intel_float_operand (t->name) != 2)
4734 && ((!operand_types[0].bitfield.regmmx
4735 && !operand_types[0].bitfield.regxmm)
4736 || (!operand_types[t->operands > 1].bitfield.regmmx
4737 && operand_types[t->operands > 1].bitfield.regxmm)))
4740 /* Do not verify operands when there are none. */
4744 /* We've found a match; break out of loop. */
4748 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4749 into Disp32/Disp16/Disp32 operand. */
4750 if (i.prefix[ADDR_PREFIX] != 0)
4752 /* There should be only one Disp operand. */
4756 for (j = 0; j < MAX_OPERANDS; j++)
4758 if (operand_types[j].bitfield.disp16)
4760 addr_prefix_disp = j;
4761 operand_types[j].bitfield.disp32 = 1;
4762 operand_types[j].bitfield.disp16 = 0;
4768 for (j = 0; j < MAX_OPERANDS; j++)
4770 if (operand_types[j].bitfield.disp32)
4772 addr_prefix_disp = j;
4773 operand_types[j].bitfield.disp32 = 0;
4774 operand_types[j].bitfield.disp16 = 1;
4780 for (j = 0; j < MAX_OPERANDS; j++)
4782 if (operand_types[j].bitfield.disp64)
4784 addr_prefix_disp = j;
4785 operand_types[j].bitfield.disp64 = 0;
4786 operand_types[j].bitfield.disp32 = 1;
4794 /* We check register size if needed. */
4795 check_register = t->opcode_modifier.checkregsize;
4796 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4797 switch (t->operands)
4800 if (!operand_type_match (overlap0, i.types[0]))
4804 /* xchg %eax, %eax is a special case. It is an aliase for nop
4805 only in 32bit mode and we can use opcode 0x90. In 64bit
4806 mode, we can't use 0x90 for xchg %eax, %eax since it should
4807 zero-extend %eax to %rax. */
4808 if (flag_code == CODE_64BIT
4809 && t->base_opcode == 0x90
4810 && operand_type_equal (&i.types [0], &acc32)
4811 && operand_type_equal (&i.types [1], &acc32))
4815 /* If we swap operand in encoding, we either match
4816 the next one or reverse direction of operands. */
4817 if (t->opcode_modifier.s)
4819 else if (t->opcode_modifier.d)
4824 /* If we swap operand in encoding, we match the next one. */
4825 if (i.swap_operand && t->opcode_modifier.s)
4829 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4830 if (!operand_type_match (overlap0, i.types[0])
4831 || !operand_type_match (overlap1, i.types[1])
4833 && !operand_type_register_match (overlap0, i.types[0],
4835 overlap1, i.types[1],
4838 /* Check if other direction is valid ... */
4839 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4843 /* Try reversing direction of operands. */
4844 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4845 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4846 if (!operand_type_match (overlap0, i.types[0])
4847 || !operand_type_match (overlap1, i.types[1])
4849 && !operand_type_register_match (overlap0,
4856 /* Does not match either direction. */
4859 /* found_reverse_match holds which of D or FloatDR
4861 if (t->opcode_modifier.d)
4862 found_reverse_match = Opcode_D;
4863 else if (t->opcode_modifier.floatd)
4864 found_reverse_match = Opcode_FloatD;
4866 found_reverse_match = 0;
4867 if (t->opcode_modifier.floatr)
4868 found_reverse_match |= Opcode_FloatR;
4872 /* Found a forward 2 operand match here. */
4873 switch (t->operands)
4876 overlap4 = operand_type_and (i.types[4],
4879 overlap3 = operand_type_and (i.types[3],
4882 overlap2 = operand_type_and (i.types[2],
4887 switch (t->operands)
4890 if (!operand_type_match (overlap4, i.types[4])
4891 || !operand_type_register_match (overlap3,
4899 if (!operand_type_match (overlap3, i.types[3])
4901 && !operand_type_register_match (overlap2,
4909 /* Here we make use of the fact that there are no
4910 reverse match 3 operand instructions, and all 3
4911 operand instructions only need to be checked for
4912 register consistency between operands 2 and 3. */
4913 if (!operand_type_match (overlap2, i.types[2])
4915 && !operand_type_register_match (overlap1,
4925 /* Found either forward/reverse 2, 3 or 4 operand match here:
4926 slip through to break. */
4928 if (!found_cpu_match)
4930 found_reverse_match = 0;
4934 /* Check if vector and VEX operands are valid. */
4935 if (check_VecOperands (t) || VEX_check_operands (t))
4937 specific_error = i.error;
4941 /* We've found a match; break out of loop. */
4945 if (t == current_templates->end)
4947 /* We found no match. */
4948 const char *err_msg;
4949 switch (specific_error ? specific_error : i.error)
4953 case operand_size_mismatch:
4954 err_msg = _("operand size mismatch");
4956 case operand_type_mismatch:
4957 err_msg = _("operand type mismatch");
4959 case register_type_mismatch:
4960 err_msg = _("register type mismatch");
4962 case number_of_operands_mismatch:
4963 err_msg = _("number of operands mismatch");
4965 case invalid_instruction_suffix:
4966 err_msg = _("invalid instruction suffix");
4969 err_msg = _("constant doesn't fit in 4 bits");
4972 err_msg = _("only supported with old gcc");
4974 case unsupported_with_intel_mnemonic:
4975 err_msg = _("unsupported with Intel mnemonic");
4977 case unsupported_syntax:
4978 err_msg = _("unsupported syntax");
4981 as_bad (_("unsupported instruction `%s'"),
4982 current_templates->start->name);
4984 case invalid_vsib_address:
4985 err_msg = _("invalid VSIB address");
4987 case invalid_vector_register_set:
4988 err_msg = _("mask, index, and destination registers must be distinct");
4990 case unsupported_vector_index_register:
4991 err_msg = _("unsupported vector index register");
4993 case unsupported_broadcast:
4994 err_msg = _("unsupported broadcast");
4996 case broadcast_not_on_src_operand:
4997 err_msg = _("broadcast not on source memory operand");
4999 case broadcast_needed:
5000 err_msg = _("broadcast is needed for operand of such type");
5002 case unsupported_masking:
5003 err_msg = _("unsupported masking");
5005 case mask_not_on_destination:
5006 err_msg = _("mask not on destination operand");
5008 case no_default_mask:
5009 err_msg = _("default mask isn't allowed");
5011 case unsupported_rc_sae:
5012 err_msg = _("unsupported static rounding/sae");
5014 case rc_sae_operand_not_last_imm:
5016 err_msg = _("RC/SAE operand must precede immediate operands");
5018 err_msg = _("RC/SAE operand must follow immediate operands");
5020 case invalid_register_operand:
5021 err_msg = _("invalid register operand");
5024 as_bad (_("%s for `%s'"), err_msg,
5025 current_templates->start->name);
5029 if (!quiet_warnings)
5032 && (i.types[0].bitfield.jumpabsolute
5033 != operand_types[0].bitfield.jumpabsolute))
5035 as_warn (_("indirect %s without `*'"), t->name);
5038 if (t->opcode_modifier.isprefix
5039 && t->opcode_modifier.ignoresize)
5041 /* Warn them that a data or address size prefix doesn't
5042 affect assembly of the next line of code. */
5043 as_warn (_("stand-alone `%s' prefix"), t->name);
5047 /* Copy the template we found. */
5050 if (addr_prefix_disp != -1)
5051 i.tm.operand_types[addr_prefix_disp]
5052 = operand_types[addr_prefix_disp];
5054 if (found_reverse_match)
5056 /* If we found a reverse match we must alter the opcode
5057 direction bit. found_reverse_match holds bits to change
5058 (different for int & float insns). */
5060 i.tm.base_opcode ^= found_reverse_match;
5062 i.tm.operand_types[0] = operand_types[1];
5063 i.tm.operand_types[1] = operand_types[0];
5072 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5073 if (i.tm.operand_types[mem_op].bitfield.esseg)
5075 if (i.seg[0] != NULL && i.seg[0] != &es)
5077 as_bad (_("`%s' operand %d must use `%ses' segment"),
5083 /* There's only ever one segment override allowed per instruction.
5084 This instruction possibly has a legal segment override on the
5085 second operand, so copy the segment to where non-string
5086 instructions store it, allowing common code. */
5087 i.seg[0] = i.seg[1];
5089 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5091 if (i.seg[1] != NULL && i.seg[1] != &es)
5093 as_bad (_("`%s' operand %d must use `%ses' segment"),
5104 process_suffix (void)
5106 /* If matched instruction specifies an explicit instruction mnemonic
5108 if (i.tm.opcode_modifier.size16)
5109 i.suffix = WORD_MNEM_SUFFIX;
5110 else if (i.tm.opcode_modifier.size32)
5111 i.suffix = LONG_MNEM_SUFFIX;
5112 else if (i.tm.opcode_modifier.size64)
5113 i.suffix = QWORD_MNEM_SUFFIX;
5114 else if (i.reg_operands)
5116 /* If there's no instruction mnemonic suffix we try to invent one
5117 based on register operands. */
5120 /* We take i.suffix from the last register operand specified,
5121 Destination register type is more significant than source
5122 register type. crc32 in SSE4.2 prefers source register
5124 if (i.tm.base_opcode == 0xf20f38f1)
5126 if (i.types[0].bitfield.reg16)
5127 i.suffix = WORD_MNEM_SUFFIX;
5128 else if (i.types[0].bitfield.reg32)
5129 i.suffix = LONG_MNEM_SUFFIX;
5130 else if (i.types[0].bitfield.reg64)
5131 i.suffix = QWORD_MNEM_SUFFIX;
5133 else if (i.tm.base_opcode == 0xf20f38f0)
5135 if (i.types[0].bitfield.reg8)
5136 i.suffix = BYTE_MNEM_SUFFIX;
5143 if (i.tm.base_opcode == 0xf20f38f1
5144 || i.tm.base_opcode == 0xf20f38f0)
5146 /* We have to know the operand size for crc32. */
5147 as_bad (_("ambiguous memory operand size for `%s`"),
5152 for (op = i.operands; --op >= 0;)
5153 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5155 if (i.types[op].bitfield.reg8)
5157 i.suffix = BYTE_MNEM_SUFFIX;
5160 else if (i.types[op].bitfield.reg16)
5162 i.suffix = WORD_MNEM_SUFFIX;
5165 else if (i.types[op].bitfield.reg32)
5167 i.suffix = LONG_MNEM_SUFFIX;
5170 else if (i.types[op].bitfield.reg64)
5172 i.suffix = QWORD_MNEM_SUFFIX;
5178 else if (i.suffix == BYTE_MNEM_SUFFIX)
5181 && i.tm.opcode_modifier.ignoresize
5182 && i.tm.opcode_modifier.no_bsuf)
5184 else if (!check_byte_reg ())
5187 else if (i.suffix == LONG_MNEM_SUFFIX)
5190 && i.tm.opcode_modifier.ignoresize
5191 && i.tm.opcode_modifier.no_lsuf)
5193 else if (!check_long_reg ())
5196 else if (i.suffix == QWORD_MNEM_SUFFIX)
5199 && i.tm.opcode_modifier.ignoresize
5200 && i.tm.opcode_modifier.no_qsuf)
5202 else if (!check_qword_reg ())
5205 else if (i.suffix == WORD_MNEM_SUFFIX)
5208 && i.tm.opcode_modifier.ignoresize
5209 && i.tm.opcode_modifier.no_wsuf)
5211 else if (!check_word_reg ())
5214 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5215 || i.suffix == YMMWORD_MNEM_SUFFIX
5216 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5218 /* Skip if the instruction has x/y/z suffix. match_template
5219 should check if it is a valid suffix. */
5221 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5222 /* Do nothing if the instruction is going to ignore the prefix. */
5227 else if (i.tm.opcode_modifier.defaultsize
5229 /* exclude fldenv/frstor/fsave/fstenv */
5230 && i.tm.opcode_modifier.no_ssuf)
5232 i.suffix = stackop_size;
5234 else if (intel_syntax
5236 && (i.tm.operand_types[0].bitfield.jumpabsolute
5237 || i.tm.opcode_modifier.jumpbyte
5238 || i.tm.opcode_modifier.jumpintersegment
5239 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5240 && i.tm.extension_opcode <= 3)))
5245 if (!i.tm.opcode_modifier.no_qsuf)
5247 i.suffix = QWORD_MNEM_SUFFIX;
5251 if (!i.tm.opcode_modifier.no_lsuf)
5252 i.suffix = LONG_MNEM_SUFFIX;
5255 if (!i.tm.opcode_modifier.no_wsuf)
5256 i.suffix = WORD_MNEM_SUFFIX;
5265 if (i.tm.opcode_modifier.w)
5267 as_bad (_("no instruction mnemonic suffix given and "
5268 "no register operands; can't size instruction"));
5274 unsigned int suffixes;
5276 suffixes = !i.tm.opcode_modifier.no_bsuf;
5277 if (!i.tm.opcode_modifier.no_wsuf)
5279 if (!i.tm.opcode_modifier.no_lsuf)
5281 if (!i.tm.opcode_modifier.no_ldsuf)
5283 if (!i.tm.opcode_modifier.no_ssuf)
5285 if (!i.tm.opcode_modifier.no_qsuf)
5288 /* There are more than suffix matches. */
5289 if (i.tm.opcode_modifier.w
5290 || ((suffixes & (suffixes - 1))
5291 && !i.tm.opcode_modifier.defaultsize
5292 && !i.tm.opcode_modifier.ignoresize))
5294 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5300 /* Change the opcode based on the operand size given by i.suffix;
5301 We don't need to change things for byte insns. */
5304 && i.suffix != BYTE_MNEM_SUFFIX
5305 && i.suffix != XMMWORD_MNEM_SUFFIX
5306 && i.suffix != YMMWORD_MNEM_SUFFIX
5307 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5309 /* It's not a byte, select word/dword operation. */
5310 if (i.tm.opcode_modifier.w)
5312 if (i.tm.opcode_modifier.shortform)
5313 i.tm.base_opcode |= 8;
5315 i.tm.base_opcode |= 1;
5318 /* Now select between word & dword operations via the operand
5319 size prefix, except for instructions that will ignore this
5321 if (i.tm.opcode_modifier.addrprefixop0)
5323 /* The address size override prefix changes the size of the
5325 if ((flag_code == CODE_32BIT
5326 && i.op->regs[0].reg_type.bitfield.reg16)
5327 || (flag_code != CODE_32BIT
5328 && i.op->regs[0].reg_type.bitfield.reg32))
5329 if (!add_prefix (ADDR_PREFIX_OPCODE))
5332 else if (i.suffix != QWORD_MNEM_SUFFIX
5333 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5334 && !i.tm.opcode_modifier.ignoresize
5335 && !i.tm.opcode_modifier.floatmf
5336 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5337 || (flag_code == CODE_64BIT
5338 && i.tm.opcode_modifier.jumpbyte)))
5340 unsigned int prefix = DATA_PREFIX_OPCODE;
5342 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5343 prefix = ADDR_PREFIX_OPCODE;
5345 if (!add_prefix (prefix))
5349 /* Set mode64 for an operand. */
5350 if (i.suffix == QWORD_MNEM_SUFFIX
5351 && flag_code == CODE_64BIT
5352 && !i.tm.opcode_modifier.norex64)
5354 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5355 need rex64. cmpxchg8b is also a special case. */
5356 if (! (i.operands == 2
5357 && i.tm.base_opcode == 0x90
5358 && i.tm.extension_opcode == None
5359 && operand_type_equal (&i.types [0], &acc64)
5360 && operand_type_equal (&i.types [1], &acc64))
5361 && ! (i.operands == 1
5362 && i.tm.base_opcode == 0xfc7
5363 && i.tm.extension_opcode == 1
5364 && !operand_type_check (i.types [0], reg)
5365 && operand_type_check (i.types [0], anymem)))
5369 /* Size floating point instruction. */
5370 if (i.suffix == LONG_MNEM_SUFFIX)
5371 if (i.tm.opcode_modifier.floatmf)
5372 i.tm.base_opcode ^= 4;
5379 check_byte_reg (void)
5383 for (op = i.operands; --op >= 0;)
5385 /* If this is an eight bit register, it's OK. If it's the 16 or
5386 32 bit version of an eight bit register, we will just use the
5387 low portion, and that's OK too. */
5388 if (i.types[op].bitfield.reg8)
5391 /* I/O port address operands are OK too. */
5392 if (i.tm.operand_types[op].bitfield.inoutportreg)
5395 /* crc32 doesn't generate this warning. */
5396 if (i.tm.base_opcode == 0xf20f38f0)
5399 if ((i.types[op].bitfield.reg16
5400 || i.types[op].bitfield.reg32
5401 || i.types[op].bitfield.reg64)
5402 && i.op[op].regs->reg_num < 4
5403 /* Prohibit these changes in 64bit mode, since the lowering
5404 would be more complicated. */
5405 && flag_code != CODE_64BIT)
5407 #if REGISTER_WARNINGS
5408 if (!quiet_warnings)
5409 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5411 (i.op[op].regs + (i.types[op].bitfield.reg16
5412 ? REGNAM_AL - REGNAM_AX
5413 : REGNAM_AL - REGNAM_EAX))->reg_name,
5415 i.op[op].regs->reg_name,
5420 /* Any other register is bad. */
5421 if (i.types[op].bitfield.reg16
5422 || i.types[op].bitfield.reg32
5423 || i.types[op].bitfield.reg64
5424 || i.types[op].bitfield.regmmx
5425 || i.types[op].bitfield.regxmm
5426 || i.types[op].bitfield.regymm
5427 || i.types[op].bitfield.regzmm
5428 || i.types[op].bitfield.sreg2
5429 || i.types[op].bitfield.sreg3
5430 || i.types[op].bitfield.control
5431 || i.types[op].bitfield.debug
5432 || i.types[op].bitfield.test
5433 || i.types[op].bitfield.floatreg
5434 || i.types[op].bitfield.floatacc)
5436 as_bad (_("`%s%s' not allowed with `%s%c'"),
5438 i.op[op].regs->reg_name,
5448 check_long_reg (void)
5452 for (op = i.operands; --op >= 0;)
5453 /* Reject eight bit registers, except where the template requires
5454 them. (eg. movzb) */
5455 if (i.types[op].bitfield.reg8
5456 && (i.tm.operand_types[op].bitfield.reg16
5457 || i.tm.operand_types[op].bitfield.reg32
5458 || i.tm.operand_types[op].bitfield.acc))
5460 as_bad (_("`%s%s' not allowed with `%s%c'"),
5462 i.op[op].regs->reg_name,
5467 /* Warn if the e prefix on a general reg is missing. */
5468 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5469 && i.types[op].bitfield.reg16
5470 && (i.tm.operand_types[op].bitfield.reg32
5471 || i.tm.operand_types[op].bitfield.acc))
5473 /* Prohibit these changes in the 64bit mode, since the
5474 lowering is more complicated. */
5475 if (flag_code == CODE_64BIT)
5477 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5478 register_prefix, i.op[op].regs->reg_name,
5482 #if REGISTER_WARNINGS
5483 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5485 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5486 register_prefix, i.op[op].regs->reg_name, i.suffix);
5489 /* Warn if the r prefix on a general reg is present. */
5490 else if (i.types[op].bitfield.reg64
5491 && (i.tm.operand_types[op].bitfield.reg32
5492 || i.tm.operand_types[op].bitfield.acc))
5495 && i.tm.opcode_modifier.toqword
5496 && !i.types[0].bitfield.regxmm)
5498 /* Convert to QWORD. We want REX byte. */
5499 i.suffix = QWORD_MNEM_SUFFIX;
5503 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5504 register_prefix, i.op[op].regs->reg_name,
5513 check_qword_reg (void)
5517 for (op = i.operands; --op >= 0; )
5518 /* Reject eight bit registers, except where the template requires
5519 them. (eg. movzb) */
5520 if (i.types[op].bitfield.reg8
5521 && (i.tm.operand_types[op].bitfield.reg16
5522 || i.tm.operand_types[op].bitfield.reg32
5523 || i.tm.operand_types[op].bitfield.acc))
5525 as_bad (_("`%s%s' not allowed with `%s%c'"),
5527 i.op[op].regs->reg_name,
5532 /* Warn if the r prefix on a general reg is missing. */
5533 else if ((i.types[op].bitfield.reg16
5534 || i.types[op].bitfield.reg32)
5535 && (i.tm.operand_types[op].bitfield.reg32
5536 || i.tm.operand_types[op].bitfield.acc))
5538 /* Prohibit these changes in the 64bit mode, since the
5539 lowering is more complicated. */
5541 && i.tm.opcode_modifier.todword
5542 && !i.types[0].bitfield.regxmm)
5544 /* Convert to DWORD. We don't want REX byte. */
5545 i.suffix = LONG_MNEM_SUFFIX;
5549 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5550 register_prefix, i.op[op].regs->reg_name,
5559 check_word_reg (void)
5562 for (op = i.operands; --op >= 0;)
5563 /* Reject eight bit registers, except where the template requires
5564 them. (eg. movzb) */
5565 if (i.types[op].bitfield.reg8
5566 && (i.tm.operand_types[op].bitfield.reg16
5567 || i.tm.operand_types[op].bitfield.reg32
5568 || i.tm.operand_types[op].bitfield.acc))
5570 as_bad (_("`%s%s' not allowed with `%s%c'"),
5572 i.op[op].regs->reg_name,
5577 /* Warn if the e or r prefix on a general reg is present. */
5578 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5579 && (i.types[op].bitfield.reg32
5580 || i.types[op].bitfield.reg64)
5581 && (i.tm.operand_types[op].bitfield.reg16
5582 || i.tm.operand_types[op].bitfield.acc))
5584 /* Prohibit these changes in the 64bit mode, since the
5585 lowering is more complicated. */
5586 if (flag_code == CODE_64BIT)
5588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5589 register_prefix, i.op[op].regs->reg_name,
5593 #if REGISTER_WARNINGS
5594 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5596 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5597 register_prefix, i.op[op].regs->reg_name, i.suffix);
5604 update_imm (unsigned int j)
5606 i386_operand_type overlap = i.types[j];
5607 if ((overlap.bitfield.imm8
5608 || overlap.bitfield.imm8s
5609 || overlap.bitfield.imm16
5610 || overlap.bitfield.imm32
5611 || overlap.bitfield.imm32s
5612 || overlap.bitfield.imm64)
5613 && !operand_type_equal (&overlap, &imm8)
5614 && !operand_type_equal (&overlap, &imm8s)
5615 && !operand_type_equal (&overlap, &imm16)
5616 && !operand_type_equal (&overlap, &imm32)
5617 && !operand_type_equal (&overlap, &imm32s)
5618 && !operand_type_equal (&overlap, &imm64))
5622 i386_operand_type temp;
5624 operand_type_set (&temp, 0);
5625 if (i.suffix == BYTE_MNEM_SUFFIX)
5627 temp.bitfield.imm8 = overlap.bitfield.imm8;
5628 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5630 else if (i.suffix == WORD_MNEM_SUFFIX)
5631 temp.bitfield.imm16 = overlap.bitfield.imm16;
5632 else if (i.suffix == QWORD_MNEM_SUFFIX)
5634 temp.bitfield.imm64 = overlap.bitfield.imm64;
5635 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5638 temp.bitfield.imm32 = overlap.bitfield.imm32;
5641 else if (operand_type_equal (&overlap, &imm16_32_32s)
5642 || operand_type_equal (&overlap, &imm16_32)
5643 || operand_type_equal (&overlap, &imm16_32s))
5645 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5650 if (!operand_type_equal (&overlap, &imm8)
5651 && !operand_type_equal (&overlap, &imm8s)
5652 && !operand_type_equal (&overlap, &imm16)
5653 && !operand_type_equal (&overlap, &imm32)
5654 && !operand_type_equal (&overlap, &imm32s)
5655 && !operand_type_equal (&overlap, &imm64))
5657 as_bad (_("no instruction mnemonic suffix given; "
5658 "can't determine immediate size"));
5662 i.types[j] = overlap;
5672 /* Update the first 2 immediate operands. */
5673 n = i.operands > 2 ? 2 : i.operands;
5676 for (j = 0; j < n; j++)
5677 if (update_imm (j) == 0)
5680 /* The 3rd operand can't be immediate operand. */
5681 gas_assert (operand_type_check (i.types[2], imm) == 0);
5688 bad_implicit_operand (int xmm)
5690 const char *ireg = xmm ? "xmm0" : "ymm0";
5693 as_bad (_("the last operand of `%s' must be `%s%s'"),
5694 i.tm.name, register_prefix, ireg);
5696 as_bad (_("the first operand of `%s' must be `%s%s'"),
5697 i.tm.name, register_prefix, ireg);
5702 process_operands (void)
5704 /* Default segment register this instruction will use for memory
5705 accesses. 0 means unknown. This is only for optimizing out
5706 unnecessary segment overrides. */
5707 const seg_entry *default_seg = 0;
5709 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5711 unsigned int dupl = i.operands;
5712 unsigned int dest = dupl - 1;
5715 /* The destination must be an xmm register. */
5716 gas_assert (i.reg_operands
5717 && MAX_OPERANDS > dupl
5718 && operand_type_equal (&i.types[dest], ®xmm));
5720 if (i.tm.opcode_modifier.firstxmm0)
5722 /* The first operand is implicit and must be xmm0. */
5723 gas_assert (operand_type_equal (&i.types[0], ®xmm));
5724 if (register_number (i.op[0].regs) != 0)
5725 return bad_implicit_operand (1);
5727 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5729 /* Keep xmm0 for instructions with VEX prefix and 3
5735 /* We remove the first xmm0 and keep the number of
5736 operands unchanged, which in fact duplicates the
5738 for (j = 1; j < i.operands; j++)
5740 i.op[j - 1] = i.op[j];
5741 i.types[j - 1] = i.types[j];
5742 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5746 else if (i.tm.opcode_modifier.implicit1stxmm0)
5748 gas_assert ((MAX_OPERANDS - 1) > dupl
5749 && (i.tm.opcode_modifier.vexsources
5752 /* Add the implicit xmm0 for instructions with VEX prefix
5754 for (j = i.operands; j > 0; j--)
5756 i.op[j] = i.op[j - 1];
5757 i.types[j] = i.types[j - 1];
5758 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5761 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5762 i.types[0] = regxmm;
5763 i.tm.operand_types[0] = regxmm;
5766 i.reg_operands += 2;
5771 i.op[dupl] = i.op[dest];
5772 i.types[dupl] = i.types[dest];
5773 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5782 i.op[dupl] = i.op[dest];
5783 i.types[dupl] = i.types[dest];
5784 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5787 if (i.tm.opcode_modifier.immext)
5790 else if (i.tm.opcode_modifier.firstxmm0)
5794 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5795 gas_assert (i.reg_operands
5796 && (operand_type_equal (&i.types[0], ®xmm)
5797 || operand_type_equal (&i.types[0], ®ymm)
5798 || operand_type_equal (&i.types[0], ®zmm)));
5799 if (register_number (i.op[0].regs) != 0)
5800 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5802 for (j = 1; j < i.operands; j++)
5804 i.op[j - 1] = i.op[j];
5805 i.types[j - 1] = i.types[j];
5807 /* We need to adjust fields in i.tm since they are used by
5808 build_modrm_byte. */
5809 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5816 else if (i.tm.opcode_modifier.regkludge)
5818 /* The imul $imm, %reg instruction is converted into
5819 imul $imm, %reg, %reg, and the clr %reg instruction
5820 is converted into xor %reg, %reg. */
5822 unsigned int first_reg_op;
5824 if (operand_type_check (i.types[0], reg))
5828 /* Pretend we saw the extra register operand. */
5829 gas_assert (i.reg_operands == 1
5830 && i.op[first_reg_op + 1].regs == 0);
5831 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5832 i.types[first_reg_op + 1] = i.types[first_reg_op];
5837 if (i.tm.opcode_modifier.shortform)
5839 if (i.types[0].bitfield.sreg2
5840 || i.types[0].bitfield.sreg3)
5842 if (i.tm.base_opcode == POP_SEG_SHORT
5843 && i.op[0].regs->reg_num == 1)
5845 as_bad (_("you can't `pop %scs'"), register_prefix);
5848 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5849 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5854 /* The register or float register operand is in operand
5858 if (i.types[0].bitfield.floatreg
5859 || operand_type_check (i.types[0], reg))
5863 /* Register goes in low 3 bits of opcode. */
5864 i.tm.base_opcode |= i.op[op].regs->reg_num;
5865 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5867 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5869 /* Warn about some common errors, but press on regardless.
5870 The first case can be generated by gcc (<= 2.8.1). */
5871 if (i.operands == 2)
5873 /* Reversed arguments on faddp, fsubp, etc. */
5874 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5875 register_prefix, i.op[!intel_syntax].regs->reg_name,
5876 register_prefix, i.op[intel_syntax].regs->reg_name);
5880 /* Extraneous `l' suffix on fp insn. */
5881 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5882 register_prefix, i.op[0].regs->reg_name);
5887 else if (i.tm.opcode_modifier.modrm)
5889 /* The opcode is completed (modulo i.tm.extension_opcode which
5890 must be put into the modrm byte). Now, we make the modrm and
5891 index base bytes based on all the info we've collected. */
5893 default_seg = build_modrm_byte ();
5895 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5899 else if (i.tm.opcode_modifier.isstring)
5901 /* For the string instructions that allow a segment override
5902 on one of their operands, the default segment is ds. */
5906 if (i.tm.base_opcode == 0x8d /* lea */
5909 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5911 /* If a segment was explicitly specified, and the specified segment
5912 is not the default, use an opcode prefix to select it. If we
5913 never figured out what the default segment is, then default_seg
5914 will be zero at this point, and the specified segment prefix will
5916 if ((i.seg[0]) && (i.seg[0] != default_seg))
5918 if (!add_prefix (i.seg[0]->seg_prefix))
5924 static const seg_entry *
5925 build_modrm_byte (void)
5927 const seg_entry *default_seg = 0;
5928 unsigned int source, dest;
5931 /* The first operand of instructions with VEX prefix and 3 sources
5932 must be VEX_Imm4. */
5933 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5936 unsigned int nds, reg_slot;
5939 if (i.tm.opcode_modifier.veximmext
5940 && i.tm.opcode_modifier.immext)
5942 dest = i.operands - 2;
5943 gas_assert (dest == 3);
5946 dest = i.operands - 1;
5949 /* There are 2 kinds of instructions:
5950 1. 5 operands: 4 register operands or 3 register operands
5951 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5952 VexW0 or VexW1. The destination must be either XMM, YMM or
5954 2. 4 operands: 4 register operands or 3 register operands
5955 plus 1 memory operand, VexXDS, and VexImmExt */
5956 gas_assert ((i.reg_operands == 4
5957 || (i.reg_operands == 3 && i.mem_operands == 1))
5958 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5959 && (i.tm.opcode_modifier.veximmext
5960 || (i.imm_operands == 1
5961 && i.types[0].bitfield.vec_imm4
5962 && (i.tm.opcode_modifier.vexw == VEXW0
5963 || i.tm.opcode_modifier.vexw == VEXW1)
5964 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5965 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)
5966 || operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
5968 if (i.imm_operands == 0)
5970 /* When there is no immediate operand, generate an 8bit
5971 immediate operand to encode the first operand. */
5972 exp = &im_expressions[i.imm_operands++];
5973 i.op[i.operands].imms = exp;
5974 i.types[i.operands] = imm8;
5976 /* If VexW1 is set, the first operand is the source and
5977 the second operand is encoded in the immediate operand. */
5978 if (i.tm.opcode_modifier.vexw == VEXW1)
5989 /* FMA swaps REG and NDS. */
5990 if (i.tm.cpu_flags.bitfield.cpufma)
5998 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6000 || operand_type_equal (&i.tm.operand_types[reg_slot],
6002 || operand_type_equal (&i.tm.operand_types[reg_slot],
6004 exp->X_op = O_constant;
6005 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6006 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6010 unsigned int imm_slot;
6012 if (i.tm.opcode_modifier.vexw == VEXW0)
6014 /* If VexW0 is set, the third operand is the source and
6015 the second operand is encoded in the immediate
6022 /* VexW1 is set, the second operand is the source and
6023 the third operand is encoded in the immediate
6029 if (i.tm.opcode_modifier.immext)
6031 /* When ImmExt is set, the immdiate byte is the last
6033 imm_slot = i.operands - 1;
6041 /* Turn on Imm8 so that output_imm will generate it. */
6042 i.types[imm_slot].bitfield.imm8 = 1;
6045 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6047 || operand_type_equal (&i.tm.operand_types[reg_slot],
6049 || operand_type_equal (&i.tm.operand_types[reg_slot],
6051 i.op[imm_slot].imms->X_add_number
6052 |= register_number (i.op[reg_slot].regs) << 4;
6053 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6056 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
6057 || operand_type_equal (&i.tm.operand_types[nds],
6059 || operand_type_equal (&i.tm.operand_types[nds],
6061 i.vex.register_specifier = i.op[nds].regs;
6066 /* i.reg_operands MUST be the number of real register operands;
6067 implicit registers do not count. If there are 3 register
6068 operands, it must be a instruction with VexNDS. For a
6069 instruction with VexNDD, the destination register is encoded
6070 in VEX prefix. If there are 4 register operands, it must be
6071 a instruction with VEX prefix and 3 sources. */
6072 if (i.mem_operands == 0
6073 && ((i.reg_operands == 2
6074 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6075 || (i.reg_operands == 3
6076 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6077 || (i.reg_operands == 4 && vex_3_sources)))
6085 /* When there are 3 operands, one of them may be immediate,
6086 which may be the first or the last operand. Otherwise,
6087 the first operand must be shift count register (cl) or it
6088 is an instruction with VexNDS. */
6089 gas_assert (i.imm_operands == 1
6090 || (i.imm_operands == 0
6091 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6092 || i.types[0].bitfield.shiftcount)));
6093 if (operand_type_check (i.types[0], imm)
6094 || i.types[0].bitfield.shiftcount)
6100 /* When there are 4 operands, the first two must be 8bit
6101 immediate operands. The source operand will be the 3rd
6104 For instructions with VexNDS, if the first operand
6105 an imm8, the source operand is the 2nd one. If the last
6106 operand is imm8, the source operand is the first one. */
6107 gas_assert ((i.imm_operands == 2
6108 && i.types[0].bitfield.imm8
6109 && i.types[1].bitfield.imm8)
6110 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6111 && i.imm_operands == 1
6112 && (i.types[0].bitfield.imm8
6113 || i.types[i.operands - 1].bitfield.imm8
6115 if (i.imm_operands == 2)
6119 if (i.types[0].bitfield.imm8)
6126 if (i.tm.opcode_modifier.evex)
6128 /* For EVEX instructions, when there are 5 operands, the
6129 first one must be immediate operand. If the second one
6130 is immediate operand, the source operand is the 3th
6131 one. If the last one is immediate operand, the source
6132 operand is the 2nd one. */
6133 gas_assert (i.imm_operands == 2
6134 && i.tm.opcode_modifier.sae
6135 && operand_type_check (i.types[0], imm));
6136 if (operand_type_check (i.types[1], imm))
6138 else if (operand_type_check (i.types[4], imm))
6152 /* RC/SAE operand could be between DEST and SRC. That happens
6153 when one operand is GPR and the other one is XMM/YMM/ZMM
6155 if (i.rounding && i.rounding->operand == (int) dest)
6158 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6160 /* For instructions with VexNDS, the register-only source
6161 operand must be 32/64bit integer, XMM, YMM or ZMM
6162 register. It is encoded in VEX prefix. We need to
6163 clear RegMem bit before calling operand_type_equal. */
6165 i386_operand_type op;
6168 /* Check register-only source operand when two source
6169 operands are swapped. */
6170 if (!i.tm.operand_types[source].bitfield.baseindex
6171 && i.tm.operand_types[dest].bitfield.baseindex)
6179 op = i.tm.operand_types[vvvv];
6180 op.bitfield.regmem = 0;
6181 if ((dest + 1) >= i.operands
6182 || (!op.bitfield.reg32
6183 && op.bitfield.reg64
6184 && !operand_type_equal (&op, ®xmm)
6185 && !operand_type_equal (&op, ®ymm)
6186 && !operand_type_equal (&op, ®zmm)
6187 && !operand_type_equal (&op, ®mask)))
6189 i.vex.register_specifier = i.op[vvvv].regs;
6195 /* One of the register operands will be encoded in the i.tm.reg
6196 field, the other in the combined i.tm.mode and i.tm.regmem
6197 fields. If no form of this instruction supports a memory
6198 destination operand, then we assume the source operand may
6199 sometimes be a memory operand and so we need to store the
6200 destination in the i.rm.reg field. */
6201 if (!i.tm.operand_types[dest].bitfield.regmem
6202 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6204 i.rm.reg = i.op[dest].regs->reg_num;
6205 i.rm.regmem = i.op[source].regs->reg_num;
6206 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6208 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6210 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6212 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6217 i.rm.reg = i.op[source].regs->reg_num;
6218 i.rm.regmem = i.op[dest].regs->reg_num;
6219 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6221 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6223 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6225 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6228 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6230 if (!i.types[0].bitfield.control
6231 && !i.types[1].bitfield.control)
6233 i.rex &= ~(REX_R | REX_B);
6234 add_prefix (LOCK_PREFIX_OPCODE);
6238 { /* If it's not 2 reg operands... */
6243 unsigned int fake_zero_displacement = 0;
6246 for (op = 0; op < i.operands; op++)
6247 if (operand_type_check (i.types[op], anymem))
6249 gas_assert (op < i.operands);
6251 if (i.tm.opcode_modifier.vecsib)
6253 if (i.index_reg->reg_num == RegEiz
6254 || i.index_reg->reg_num == RegRiz)
6257 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6260 i.sib.base = NO_BASE_REGISTER;
6261 i.sib.scale = i.log2_scale_factor;
6262 /* No Vec_Disp8 if there is no base. */
6263 i.types[op].bitfield.vec_disp8 = 0;
6264 i.types[op].bitfield.disp8 = 0;
6265 i.types[op].bitfield.disp16 = 0;
6266 i.types[op].bitfield.disp64 = 0;
6267 if (flag_code != CODE_64BIT)
6269 /* Must be 32 bit */
6270 i.types[op].bitfield.disp32 = 1;
6271 i.types[op].bitfield.disp32s = 0;
6275 i.types[op].bitfield.disp32 = 0;
6276 i.types[op].bitfield.disp32s = 1;
6279 i.sib.index = i.index_reg->reg_num;
6280 if ((i.index_reg->reg_flags & RegRex) != 0)
6282 if ((i.index_reg->reg_flags & RegVRex) != 0)
6288 if (i.base_reg == 0)
6291 if (!i.disp_operands)
6293 fake_zero_displacement = 1;
6294 /* Instructions with VSIB byte need 32bit displacement
6295 if there is no base register. */
6296 if (i.tm.opcode_modifier.vecsib)
6297 i.types[op].bitfield.disp32 = 1;
6299 if (i.index_reg == 0)
6301 gas_assert (!i.tm.opcode_modifier.vecsib);
6302 /* Operand is just <disp> */
6303 if (flag_code == CODE_64BIT)
6305 /* 64bit mode overwrites the 32bit absolute
6306 addressing by RIP relative addressing and
6307 absolute addressing is encoded by one of the
6308 redundant SIB forms. */
6309 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6310 i.sib.base = NO_BASE_REGISTER;
6311 i.sib.index = NO_INDEX_REGISTER;
6312 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6313 ? disp32s : disp32);
6315 else if ((flag_code == CODE_16BIT)
6316 ^ (i.prefix[ADDR_PREFIX] != 0))
6318 i.rm.regmem = NO_BASE_REGISTER_16;
6319 i.types[op] = disp16;
6323 i.rm.regmem = NO_BASE_REGISTER;
6324 i.types[op] = disp32;
6327 else if (!i.tm.opcode_modifier.vecsib)
6329 /* !i.base_reg && i.index_reg */
6330 if (i.index_reg->reg_num == RegEiz
6331 || i.index_reg->reg_num == RegRiz)
6332 i.sib.index = NO_INDEX_REGISTER;
6334 i.sib.index = i.index_reg->reg_num;
6335 i.sib.base = NO_BASE_REGISTER;
6336 i.sib.scale = i.log2_scale_factor;
6337 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6338 /* No Vec_Disp8 if there is no base. */
6339 i.types[op].bitfield.vec_disp8 = 0;
6340 i.types[op].bitfield.disp8 = 0;
6341 i.types[op].bitfield.disp16 = 0;
6342 i.types[op].bitfield.disp64 = 0;
6343 if (flag_code != CODE_64BIT)
6345 /* Must be 32 bit */
6346 i.types[op].bitfield.disp32 = 1;
6347 i.types[op].bitfield.disp32s = 0;
6351 i.types[op].bitfield.disp32 = 0;
6352 i.types[op].bitfield.disp32s = 1;
6354 if ((i.index_reg->reg_flags & RegRex) != 0)
6358 /* RIP addressing for 64bit mode. */
6359 else if (i.base_reg->reg_num == RegRip ||
6360 i.base_reg->reg_num == RegEip)
6362 gas_assert (!i.tm.opcode_modifier.vecsib);
6363 i.rm.regmem = NO_BASE_REGISTER;
6364 i.types[op].bitfield.disp8 = 0;
6365 i.types[op].bitfield.disp16 = 0;
6366 i.types[op].bitfield.disp32 = 0;
6367 i.types[op].bitfield.disp32s = 1;
6368 i.types[op].bitfield.disp64 = 0;
6369 i.types[op].bitfield.vec_disp8 = 0;
6370 i.flags[op] |= Operand_PCrel;
6371 if (! i.disp_operands)
6372 fake_zero_displacement = 1;
6374 else if (i.base_reg->reg_type.bitfield.reg16)
6376 gas_assert (!i.tm.opcode_modifier.vecsib);
6377 switch (i.base_reg->reg_num)
6380 if (i.index_reg == 0)
6382 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6383 i.rm.regmem = i.index_reg->reg_num - 6;
6387 if (i.index_reg == 0)
6390 if (operand_type_check (i.types[op], disp) == 0)
6392 /* fake (%bp) into 0(%bp) */
6393 if (i.tm.operand_types[op].bitfield.vec_disp8)
6394 i.types[op].bitfield.vec_disp8 = 1;
6396 i.types[op].bitfield.disp8 = 1;
6397 fake_zero_displacement = 1;
6400 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6401 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6403 default: /* (%si) -> 4 or (%di) -> 5 */
6404 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6406 i.rm.mode = mode_from_disp_size (i.types[op]);
6408 else /* i.base_reg and 32/64 bit mode */
6410 if (flag_code == CODE_64BIT
6411 && operand_type_check (i.types[op], disp))
6413 i386_operand_type temp;
6414 operand_type_set (&temp, 0);
6415 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6416 temp.bitfield.vec_disp8
6417 = i.types[op].bitfield.vec_disp8;
6419 if (i.prefix[ADDR_PREFIX] == 0)
6420 i.types[op].bitfield.disp32s = 1;
6422 i.types[op].bitfield.disp32 = 1;
6425 if (!i.tm.opcode_modifier.vecsib)
6426 i.rm.regmem = i.base_reg->reg_num;
6427 if ((i.base_reg->reg_flags & RegRex) != 0)
6429 i.sib.base = i.base_reg->reg_num;
6430 /* x86-64 ignores REX prefix bit here to avoid decoder
6432 if (!(i.base_reg->reg_flags & RegRex)
6433 && (i.base_reg->reg_num == EBP_REG_NUM
6434 || i.base_reg->reg_num == ESP_REG_NUM))
6436 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6438 fake_zero_displacement = 1;
6439 if (i.tm.operand_types [op].bitfield.vec_disp8)
6440 i.types[op].bitfield.vec_disp8 = 1;
6442 i.types[op].bitfield.disp8 = 1;
6444 i.sib.scale = i.log2_scale_factor;
6445 if (i.index_reg == 0)
6447 gas_assert (!i.tm.opcode_modifier.vecsib);
6448 /* <disp>(%esp) becomes two byte modrm with no index
6449 register. We've already stored the code for esp
6450 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6451 Any base register besides %esp will not use the
6452 extra modrm byte. */
6453 i.sib.index = NO_INDEX_REGISTER;
6455 else if (!i.tm.opcode_modifier.vecsib)
6457 if (i.index_reg->reg_num == RegEiz
6458 || i.index_reg->reg_num == RegRiz)
6459 i.sib.index = NO_INDEX_REGISTER;
6461 i.sib.index = i.index_reg->reg_num;
6462 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6463 if ((i.index_reg->reg_flags & RegRex) != 0)
6468 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6469 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6473 if (!fake_zero_displacement
6477 fake_zero_displacement = 1;
6478 if (i.disp_encoding == disp_encoding_8bit)
6479 i.types[op].bitfield.disp8 = 1;
6481 i.types[op].bitfield.disp32 = 1;
6483 i.rm.mode = mode_from_disp_size (i.types[op]);
6487 if (fake_zero_displacement)
6489 /* Fakes a zero displacement assuming that i.types[op]
6490 holds the correct displacement size. */
6493 gas_assert (i.op[op].disps == 0);
6494 exp = &disp_expressions[i.disp_operands++];
6495 i.op[op].disps = exp;
6496 exp->X_op = O_constant;
6497 exp->X_add_number = 0;
6498 exp->X_add_symbol = (symbolS *) 0;
6499 exp->X_op_symbol = (symbolS *) 0;
6507 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6509 if (operand_type_check (i.types[0], imm))
6510 i.vex.register_specifier = NULL;
6513 /* VEX.vvvv encodes one of the sources when the first
6514 operand is not an immediate. */
6515 if (i.tm.opcode_modifier.vexw == VEXW0)
6516 i.vex.register_specifier = i.op[0].regs;
6518 i.vex.register_specifier = i.op[1].regs;
6521 /* Destination is a XMM register encoded in the ModRM.reg
6523 i.rm.reg = i.op[2].regs->reg_num;
6524 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6527 /* ModRM.rm and VEX.B encodes the other source. */
6528 if (!i.mem_operands)
6532 if (i.tm.opcode_modifier.vexw == VEXW0)
6533 i.rm.regmem = i.op[1].regs->reg_num;
6535 i.rm.regmem = i.op[0].regs->reg_num;
6537 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6541 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6543 i.vex.register_specifier = i.op[2].regs;
6544 if (!i.mem_operands)
6547 i.rm.regmem = i.op[1].regs->reg_num;
6548 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6552 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6553 (if any) based on i.tm.extension_opcode. Again, we must be
6554 careful to make sure that segment/control/debug/test/MMX
6555 registers are coded into the i.rm.reg field. */
6556 else if (i.reg_operands)
6559 unsigned int vex_reg = ~0;
6561 for (op = 0; op < i.operands; op++)
6562 if (i.types[op].bitfield.reg8
6563 || i.types[op].bitfield.reg16
6564 || i.types[op].bitfield.reg32
6565 || i.types[op].bitfield.reg64
6566 || i.types[op].bitfield.regmmx
6567 || i.types[op].bitfield.regxmm
6568 || i.types[op].bitfield.regymm
6569 || i.types[op].bitfield.regbnd
6570 || i.types[op].bitfield.regzmm
6571 || i.types[op].bitfield.regmask
6572 || i.types[op].bitfield.sreg2
6573 || i.types[op].bitfield.sreg3
6574 || i.types[op].bitfield.control
6575 || i.types[op].bitfield.debug
6576 || i.types[op].bitfield.test)
6581 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6583 /* For instructions with VexNDS, the register-only
6584 source operand is encoded in VEX prefix. */
6585 gas_assert (mem != (unsigned int) ~0);
6590 gas_assert (op < i.operands);
6594 /* Check register-only source operand when two source
6595 operands are swapped. */
6596 if (!i.tm.operand_types[op].bitfield.baseindex
6597 && i.tm.operand_types[op + 1].bitfield.baseindex)
6601 gas_assert (mem == (vex_reg + 1)
6602 && op < i.operands);
6607 gas_assert (vex_reg < i.operands);
6611 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6613 /* For instructions with VexNDD, the register destination
6614 is encoded in VEX prefix. */
6615 if (i.mem_operands == 0)
6617 /* There is no memory operand. */
6618 gas_assert ((op + 2) == i.operands);
6623 /* There are only 2 operands. */
6624 gas_assert (op < 2 && i.operands == 2);
6629 gas_assert (op < i.operands);
6631 if (vex_reg != (unsigned int) ~0)
6633 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6635 if (type->bitfield.reg32 != 1
6636 && type->bitfield.reg64 != 1
6637 && !operand_type_equal (type, ®xmm)
6638 && !operand_type_equal (type, ®ymm)
6639 && !operand_type_equal (type, ®zmm)
6640 && !operand_type_equal (type, ®mask))
6643 i.vex.register_specifier = i.op[vex_reg].regs;
6646 /* Don't set OP operand twice. */
6649 /* If there is an extension opcode to put here, the
6650 register number must be put into the regmem field. */
6651 if (i.tm.extension_opcode != None)
6653 i.rm.regmem = i.op[op].regs->reg_num;
6654 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6656 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6661 i.rm.reg = i.op[op].regs->reg_num;
6662 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6664 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6669 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6670 must set it to 3 to indicate this is a register operand
6671 in the regmem field. */
6672 if (!i.mem_operands)
6676 /* Fill in i.rm.reg field with extension opcode (if any). */
6677 if (i.tm.extension_opcode != None)
6678 i.rm.reg = i.tm.extension_opcode;
6684 output_branch (void)
6690 relax_substateT subtype;
6694 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6695 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6698 if (i.prefix[DATA_PREFIX] != 0)
6704 /* Pentium4 branch hints. */
6705 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6706 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6711 if (i.prefix[REX_PREFIX] != 0)
6717 /* BND prefixed jump. */
6718 if (i.prefix[BND_PREFIX] != 0)
6720 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6724 if (i.prefixes != 0 && !intel_syntax)
6725 as_warn (_("skipping prefixes on this instruction"));
6727 /* It's always a symbol; End frag & setup for relax.
6728 Make sure there is enough room in this frag for the largest
6729 instruction we may generate in md_convert_frag. This is 2
6730 bytes for the opcode and room for the prefix and largest
6732 frag_grow (prefix + 2 + 4);
6733 /* Prefix and 1 opcode byte go in fr_fix. */
6734 p = frag_more (prefix + 1);
6735 if (i.prefix[DATA_PREFIX] != 0)
6736 *p++ = DATA_PREFIX_OPCODE;
6737 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6738 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6739 *p++ = i.prefix[SEG_PREFIX];
6740 if (i.prefix[REX_PREFIX] != 0)
6741 *p++ = i.prefix[REX_PREFIX];
6742 *p = i.tm.base_opcode;
6744 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6745 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6746 else if (cpu_arch_flags.bitfield.cpui386)
6747 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6749 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6752 sym = i.op[0].disps->X_add_symbol;
6753 off = i.op[0].disps->X_add_number;
6755 if (i.op[0].disps->X_op != O_constant
6756 && i.op[0].disps->X_op != O_symbol)
6758 /* Handle complex expressions. */
6759 sym = make_expr_symbol (i.op[0].disps);
6763 /* 1 possible extra opcode + 4 byte displacement go in var part.
6764 Pass reloc in fr_var. */
6765 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
6775 if (i.tm.opcode_modifier.jumpbyte)
6777 /* This is a loop or jecxz type instruction. */
6779 if (i.prefix[ADDR_PREFIX] != 0)
6781 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6784 /* Pentium4 branch hints. */
6785 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6786 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6788 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6797 if (flag_code == CODE_16BIT)
6800 if (i.prefix[DATA_PREFIX] != 0)
6802 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6812 if (i.prefix[REX_PREFIX] != 0)
6814 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6818 /* BND prefixed jump. */
6819 if (i.prefix[BND_PREFIX] != 0)
6821 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6825 if (i.prefixes != 0 && !intel_syntax)
6826 as_warn (_("skipping prefixes on this instruction"));
6828 p = frag_more (i.tm.opcode_length + size);
6829 switch (i.tm.opcode_length)
6832 *p++ = i.tm.base_opcode >> 8;
6834 *p++ = i.tm.base_opcode;
6840 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6841 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
6843 /* All jumps handled here are signed, but don't use a signed limit
6844 check for 32 and 16 bit jumps as we want to allow wrap around at
6845 4G and 64k respectively. */
6847 fixP->fx_signed = 1;
6851 output_interseg_jump (void)
6859 if (flag_code == CODE_16BIT)
6863 if (i.prefix[DATA_PREFIX] != 0)
6869 if (i.prefix[REX_PREFIX] != 0)
6879 if (i.prefixes != 0 && !intel_syntax)
6880 as_warn (_("skipping prefixes on this instruction"));
6882 /* 1 opcode; 2 segment; offset */
6883 p = frag_more (prefix + 1 + 2 + size);
6885 if (i.prefix[DATA_PREFIX] != 0)
6886 *p++ = DATA_PREFIX_OPCODE;
6888 if (i.prefix[REX_PREFIX] != 0)
6889 *p++ = i.prefix[REX_PREFIX];
6891 *p++ = i.tm.base_opcode;
6892 if (i.op[1].imms->X_op == O_constant)
6894 offsetT n = i.op[1].imms->X_add_number;
6897 && !fits_in_unsigned_word (n)
6898 && !fits_in_signed_word (n))
6900 as_bad (_("16-bit jump out of range"));
6903 md_number_to_chars (p, n, size);
6906 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6907 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
6908 if (i.op[0].imms->X_op != O_constant)
6909 as_bad (_("can't handle non absolute segment in `%s'"),
6911 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6917 fragS *insn_start_frag;
6918 offsetT insn_start_off;
6920 /* Tie dwarf2 debug info to the address at the start of the insn.
6921 We can't do this after the insn has been output as the current
6922 frag may have been closed off. eg. by frag_var. */
6923 dwarf2_emit_insn (0);
6925 insn_start_frag = frag_now;
6926 insn_start_off = frag_now_fix ();
6929 if (i.tm.opcode_modifier.jump)
6931 else if (i.tm.opcode_modifier.jumpbyte
6932 || i.tm.opcode_modifier.jumpdword)
6934 else if (i.tm.opcode_modifier.jumpintersegment)
6935 output_interseg_jump ();
6938 /* Output normal instructions here. */
6942 unsigned int prefix;
6944 /* Some processors fail on LOCK prefix. This options makes
6945 assembler ignore LOCK prefix and serves as a workaround. */
6946 if (omit_lock_prefix)
6948 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6950 i.prefix[LOCK_PREFIX] = 0;
6953 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6954 don't need the explicit prefix. */
6955 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6957 switch (i.tm.opcode_length)
6960 if (i.tm.base_opcode & 0xff000000)
6962 prefix = (i.tm.base_opcode >> 24) & 0xff;
6967 if ((i.tm.base_opcode & 0xff0000) != 0)
6969 prefix = (i.tm.base_opcode >> 16) & 0xff;
6970 if (i.tm.cpu_flags.bitfield.cpupadlock)
6973 if (prefix != REPE_PREFIX_OPCODE
6974 || (i.prefix[REP_PREFIX]
6975 != REPE_PREFIX_OPCODE))
6976 add_prefix (prefix);
6979 add_prefix (prefix);
6988 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6989 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6990 R_X86_64_GOTTPOFF relocation so that linker can safely
6991 perform IE->LE optimization. */
6992 if (x86_elf_abi == X86_64_X32_ABI
6994 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6995 && i.prefix[REX_PREFIX] == 0)
6996 add_prefix (REX_OPCODE);
6999 /* The prefix bytes. */
7000 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7002 FRAG_APPEND_1_CHAR (*q);
7006 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7011 /* REX byte is encoded in VEX prefix. */
7015 FRAG_APPEND_1_CHAR (*q);
7018 /* There should be no other prefixes for instructions
7023 /* For EVEX instructions i.vrex should become 0 after
7024 build_evex_prefix. For VEX instructions upper 16 registers
7025 aren't available, so VREX should be 0. */
7028 /* Now the VEX prefix. */
7029 p = frag_more (i.vex.length);
7030 for (j = 0; j < i.vex.length; j++)
7031 p[j] = i.vex.bytes[j];
7034 /* Now the opcode; be careful about word order here! */
7035 if (i.tm.opcode_length == 1)
7037 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7041 switch (i.tm.opcode_length)
7045 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7046 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7050 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7060 /* Put out high byte first: can't use md_number_to_chars! */
7061 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7062 *p = i.tm.base_opcode & 0xff;
7065 /* Now the modrm byte and sib byte (if present). */
7066 if (i.tm.opcode_modifier.modrm)
7068 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7071 /* If i.rm.regmem == ESP (4)
7072 && i.rm.mode != (Register mode)
7074 ==> need second modrm byte. */
7075 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7077 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7078 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7080 | i.sib.scale << 6));
7083 if (i.disp_operands)
7084 output_disp (insn_start_frag, insn_start_off);
7087 output_imm (insn_start_frag, insn_start_off);
7093 pi ("" /*line*/, &i);
7095 #endif /* DEBUG386 */
7098 /* Return the size of the displacement operand N. */
7101 disp_size (unsigned int n)
7105 /* Vec_Disp8 has to be 8bit. */
7106 if (i.types[n].bitfield.vec_disp8)
7108 else if (i.types[n].bitfield.disp64)
7110 else if (i.types[n].bitfield.disp8)
7112 else if (i.types[n].bitfield.disp16)
7117 /* Return the size of the immediate operand N. */
7120 imm_size (unsigned int n)
7123 if (i.types[n].bitfield.imm64)
7125 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7127 else if (i.types[n].bitfield.imm16)
7133 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7138 for (n = 0; n < i.operands; n++)
7140 if (i.types[n].bitfield.vec_disp8
7141 || operand_type_check (i.types[n], disp))
7143 if (i.op[n].disps->X_op == O_constant)
7145 int size = disp_size (n);
7146 offsetT val = i.op[n].disps->X_add_number;
7148 if (i.types[n].bitfield.vec_disp8)
7150 val = offset_in_range (val, size);
7151 p = frag_more (size);
7152 md_number_to_chars (p, val, size);
7156 enum bfd_reloc_code_real reloc_type;
7157 int size = disp_size (n);
7158 int sign = i.types[n].bitfield.disp32s;
7159 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7161 /* We can't have 8 bit displacement here. */
7162 gas_assert (!i.types[n].bitfield.disp8);
7164 /* The PC relative address is computed relative
7165 to the instruction boundary, so in case immediate
7166 fields follows, we need to adjust the value. */
7167 if (pcrel && i.imm_operands)
7172 for (n1 = 0; n1 < i.operands; n1++)
7173 if (operand_type_check (i.types[n1], imm))
7175 /* Only one immediate is allowed for PC
7176 relative address. */
7177 gas_assert (sz == 0);
7179 i.op[n].disps->X_add_number -= sz;
7181 /* We should find the immediate. */
7182 gas_assert (sz != 0);
7185 p = frag_more (size);
7186 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7188 && GOT_symbol == i.op[n].disps->X_add_symbol
7189 && (((reloc_type == BFD_RELOC_32
7190 || reloc_type == BFD_RELOC_X86_64_32S
7191 || (reloc_type == BFD_RELOC_64
7193 && (i.op[n].disps->X_op == O_symbol
7194 || (i.op[n].disps->X_op == O_add
7195 && ((symbol_get_value_expression
7196 (i.op[n].disps->X_op_symbol)->X_op)
7198 || reloc_type == BFD_RELOC_32_PCREL))
7202 if (insn_start_frag == frag_now)
7203 add = (p - frag_now->fr_literal) - insn_start_off;
7208 add = insn_start_frag->fr_fix - insn_start_off;
7209 for (fr = insn_start_frag->fr_next;
7210 fr && fr != frag_now; fr = fr->fr_next)
7212 add += p - frag_now->fr_literal;
7217 reloc_type = BFD_RELOC_386_GOTPC;
7218 i.op[n].imms->X_add_number += add;
7220 else if (reloc_type == BFD_RELOC_64)
7221 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7223 /* Don't do the adjustment for x86-64, as there
7224 the pcrel addressing is relative to the _next_
7225 insn, and that is taken care of in other code. */
7226 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7228 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7229 i.op[n].disps, pcrel, reloc_type);
7236 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7241 for (n = 0; n < i.operands; n++)
7243 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7244 if (i.rounding && (int) n == i.rounding->operand)
7247 if (operand_type_check (i.types[n], imm))
7249 if (i.op[n].imms->X_op == O_constant)
7251 int size = imm_size (n);
7254 val = offset_in_range (i.op[n].imms->X_add_number,
7256 p = frag_more (size);
7257 md_number_to_chars (p, val, size);
7261 /* Not absolute_section.
7262 Need a 32-bit fixup (don't support 8bit
7263 non-absolute imms). Try to support other
7265 enum bfd_reloc_code_real reloc_type;
7266 int size = imm_size (n);
7269 if (i.types[n].bitfield.imm32s
7270 && (i.suffix == QWORD_MNEM_SUFFIX
7271 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7276 p = frag_more (size);
7277 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7279 /* This is tough to explain. We end up with this one if we
7280 * have operands that look like
7281 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7282 * obtain the absolute address of the GOT, and it is strongly
7283 * preferable from a performance point of view to avoid using
7284 * a runtime relocation for this. The actual sequence of
7285 * instructions often look something like:
7290 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7292 * The call and pop essentially return the absolute address
7293 * of the label .L66 and store it in %ebx. The linker itself
7294 * will ultimately change the first operand of the addl so
7295 * that %ebx points to the GOT, but to keep things simple, the
7296 * .o file must have this operand set so that it generates not
7297 * the absolute address of .L66, but the absolute address of
7298 * itself. This allows the linker itself simply treat a GOTPC
7299 * relocation as asking for a pcrel offset to the GOT to be
7300 * added in, and the addend of the relocation is stored in the
7301 * operand field for the instruction itself.
7303 * Our job here is to fix the operand so that it would add
7304 * the correct offset so that %ebx would point to itself. The
7305 * thing that is tricky is that .-.L66 will point to the
7306 * beginning of the instruction, so we need to further modify
7307 * the operand so that it will point to itself. There are
7308 * other cases where you have something like:
7310 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7312 * and here no correction would be required. Internally in
7313 * the assembler we treat operands of this form as not being
7314 * pcrel since the '.' is explicitly mentioned, and I wonder
7315 * whether it would simplify matters to do it this way. Who
7316 * knows. In earlier versions of the PIC patches, the
7317 * pcrel_adjust field was used to store the correction, but
7318 * since the expression is not pcrel, I felt it would be
7319 * confusing to do it this way. */
7321 if ((reloc_type == BFD_RELOC_32
7322 || reloc_type == BFD_RELOC_X86_64_32S
7323 || reloc_type == BFD_RELOC_64)
7325 && GOT_symbol == i.op[n].imms->X_add_symbol
7326 && (i.op[n].imms->X_op == O_symbol
7327 || (i.op[n].imms->X_op == O_add
7328 && ((symbol_get_value_expression
7329 (i.op[n].imms->X_op_symbol)->X_op)
7334 if (insn_start_frag == frag_now)
7335 add = (p - frag_now->fr_literal) - insn_start_off;
7340 add = insn_start_frag->fr_fix - insn_start_off;
7341 for (fr = insn_start_frag->fr_next;
7342 fr && fr != frag_now; fr = fr->fr_next)
7344 add += p - frag_now->fr_literal;
7348 reloc_type = BFD_RELOC_386_GOTPC;
7350 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7352 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7353 i.op[n].imms->X_add_number += add;
7355 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7356 i.op[n].imms, 0, reloc_type);
7362 /* x86_cons_fix_new is called via the expression parsing code when a
7363 reloc is needed. We use this hook to get the correct .got reloc. */
7364 static int cons_sign = -1;
7367 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7368 expressionS *exp, bfd_reloc_code_real_type r)
7370 r = reloc (len, 0, cons_sign, r);
7373 if (exp->X_op == O_secrel)
7375 exp->X_op = O_symbol;
7376 r = BFD_RELOC_32_SECREL;
7380 fix_new_exp (frag, off, len, exp, 0, r);
7383 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7384 purpose of the `.dc.a' internal pseudo-op. */
7387 x86_address_bytes (void)
7389 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7391 return stdoutput->arch_info->bits_per_address / 8;
7394 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7396 # define lex_got(reloc, adjust, types) NULL
7398 /* Parse operands of the form
7399 <symbol>@GOTOFF+<nnn>
7400 and similar .plt or .got references.
7402 If we find one, set up the correct relocation in RELOC and copy the
7403 input string, minus the `@GOTOFF' into a malloc'd buffer for
7404 parsing by the calling routine. Return this buffer, and if ADJUST
7405 is non-null set it to the length of the string we removed from the
7406 input line. Otherwise return NULL. */
7408 lex_got (enum bfd_reloc_code_real *rel,
7410 i386_operand_type *types)
7412 /* Some of the relocations depend on the size of what field is to
7413 be relocated. But in our callers i386_immediate and i386_displacement
7414 we don't yet know the operand size (this will be set by insn
7415 matching). Hence we record the word32 relocation here,
7416 and adjust the reloc according to the real size in reloc(). */
7417 static const struct {
7420 const enum bfd_reloc_code_real rel[2];
7421 const i386_operand_type types64;
7423 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7424 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7426 OPERAND_TYPE_IMM32_64 },
7428 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7429 BFD_RELOC_X86_64_PLTOFF64 },
7430 OPERAND_TYPE_IMM64 },
7431 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7432 BFD_RELOC_X86_64_PLT32 },
7433 OPERAND_TYPE_IMM32_32S_DISP32 },
7434 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7435 BFD_RELOC_X86_64_GOTPLT64 },
7436 OPERAND_TYPE_IMM64_DISP64 },
7437 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7438 BFD_RELOC_X86_64_GOTOFF64 },
7439 OPERAND_TYPE_IMM64_DISP64 },
7440 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7441 BFD_RELOC_X86_64_GOTPCREL },
7442 OPERAND_TYPE_IMM32_32S_DISP32 },
7443 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7444 BFD_RELOC_X86_64_TLSGD },
7445 OPERAND_TYPE_IMM32_32S_DISP32 },
7446 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7447 _dummy_first_bfd_reloc_code_real },
7448 OPERAND_TYPE_NONE },
7449 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7450 BFD_RELOC_X86_64_TLSLD },
7451 OPERAND_TYPE_IMM32_32S_DISP32 },
7452 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7453 BFD_RELOC_X86_64_GOTTPOFF },
7454 OPERAND_TYPE_IMM32_32S_DISP32 },
7455 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7456 BFD_RELOC_X86_64_TPOFF32 },
7457 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7458 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7459 _dummy_first_bfd_reloc_code_real },
7460 OPERAND_TYPE_NONE },
7461 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7462 BFD_RELOC_X86_64_DTPOFF32 },
7463 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7464 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7465 _dummy_first_bfd_reloc_code_real },
7466 OPERAND_TYPE_NONE },
7467 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7468 _dummy_first_bfd_reloc_code_real },
7469 OPERAND_TYPE_NONE },
7470 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7471 BFD_RELOC_X86_64_GOT32 },
7472 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7473 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7474 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7475 OPERAND_TYPE_IMM32_32S_DISP32 },
7476 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7477 BFD_RELOC_X86_64_TLSDESC_CALL },
7478 OPERAND_TYPE_IMM32_32S_DISP32 },
7483 #if defined (OBJ_MAYBE_ELF)
7488 for (cp = input_line_pointer; *cp != '@'; cp++)
7489 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7492 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7494 int len = gotrel[j].len;
7495 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7497 if (gotrel[j].rel[object_64bit] != 0)
7500 char *tmpbuf, *past_reloc;
7502 *rel = gotrel[j].rel[object_64bit];
7506 if (flag_code != CODE_64BIT)
7508 types->bitfield.imm32 = 1;
7509 types->bitfield.disp32 = 1;
7512 *types = gotrel[j].types64;
7515 if (j != 0 && GOT_symbol == NULL)
7516 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7518 /* The length of the first part of our input line. */
7519 first = cp - input_line_pointer;
7521 /* The second part goes from after the reloc token until
7522 (and including) an end_of_line char or comma. */
7523 past_reloc = cp + 1 + len;
7525 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7527 second = cp + 1 - past_reloc;
7529 /* Allocate and copy string. The trailing NUL shouldn't
7530 be necessary, but be safe. */
7531 tmpbuf = (char *) xmalloc (first + second + 2);
7532 memcpy (tmpbuf, input_line_pointer, first);
7533 if (second != 0 && *past_reloc != ' ')
7534 /* Replace the relocation token with ' ', so that
7535 errors like foo@GOTOFF1 will be detected. */
7536 tmpbuf[first++] = ' ';
7538 /* Increment length by 1 if the relocation token is
7543 memcpy (tmpbuf + first, past_reloc, second);
7544 tmpbuf[first + second] = '\0';
7548 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7549 gotrel[j].str, 1 << (5 + object_64bit));
7554 /* Might be a symbol version string. Don't as_bad here. */
7563 /* Parse operands of the form
7564 <symbol>@SECREL32+<nnn>
7566 If we find one, set up the correct relocation in RELOC and copy the
7567 input string, minus the `@SECREL32' into a malloc'd buffer for
7568 parsing by the calling routine. Return this buffer, and if ADJUST
7569 is non-null set it to the length of the string we removed from the
7570 input line. Otherwise return NULL.
7572 This function is copied from the ELF version above adjusted for PE targets. */
7575 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7576 int *adjust ATTRIBUTE_UNUSED,
7577 i386_operand_type *types)
7583 const enum bfd_reloc_code_real rel[2];
7584 const i386_operand_type types64;
7588 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7589 BFD_RELOC_32_SECREL },
7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7596 for (cp = input_line_pointer; *cp != '@'; cp++)
7597 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7600 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7602 int len = gotrel[j].len;
7604 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7606 if (gotrel[j].rel[object_64bit] != 0)
7609 char *tmpbuf, *past_reloc;
7611 *rel = gotrel[j].rel[object_64bit];
7617 if (flag_code != CODE_64BIT)
7619 types->bitfield.imm32 = 1;
7620 types->bitfield.disp32 = 1;
7623 *types = gotrel[j].types64;
7626 /* The length of the first part of our input line. */
7627 first = cp - input_line_pointer;
7629 /* The second part goes from after the reloc token until
7630 (and including) an end_of_line char or comma. */
7631 past_reloc = cp + 1 + len;
7633 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7635 second = cp + 1 - past_reloc;
7637 /* Allocate and copy string. The trailing NUL shouldn't
7638 be necessary, but be safe. */
7639 tmpbuf = (char *) xmalloc (first + second + 2);
7640 memcpy (tmpbuf, input_line_pointer, first);
7641 if (second != 0 && *past_reloc != ' ')
7642 /* Replace the relocation token with ' ', so that
7643 errors like foo@SECLREL321 will be detected. */
7644 tmpbuf[first++] = ' ';
7645 memcpy (tmpbuf + first, past_reloc, second);
7646 tmpbuf[first + second] = '\0';
7650 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7651 gotrel[j].str, 1 << (5 + object_64bit));
7656 /* Might be a symbol version string. Don't as_bad here. */
7662 bfd_reloc_code_real_type
7663 x86_cons (expressionS *exp, int size)
7665 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7667 intel_syntax = -intel_syntax;
7670 if (size == 4 || (object_64bit && size == 8))
7672 /* Handle @GOTOFF and the like in an expression. */
7674 char *gotfree_input_line;
7677 save = input_line_pointer;
7678 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
7679 if (gotfree_input_line)
7680 input_line_pointer = gotfree_input_line;
7684 if (gotfree_input_line)
7686 /* expression () has merrily parsed up to the end of line,
7687 or a comma - in the wrong buffer. Transfer how far
7688 input_line_pointer has moved to the right buffer. */
7689 input_line_pointer = (save
7690 + (input_line_pointer - gotfree_input_line)
7692 free (gotfree_input_line);
7693 if (exp->X_op == O_constant
7694 || exp->X_op == O_absent
7695 || exp->X_op == O_illegal
7696 || exp->X_op == O_register
7697 || exp->X_op == O_big)
7699 char c = *input_line_pointer;
7700 *input_line_pointer = 0;
7701 as_bad (_("missing or invalid expression `%s'"), save);
7702 *input_line_pointer = c;
7709 intel_syntax = -intel_syntax;
7712 i386_intel_simplify (exp);
7718 signed_cons (int size)
7720 if (flag_code == CODE_64BIT)
7728 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7735 if (exp.X_op == O_symbol)
7736 exp.X_op = O_secrel;
7738 emit_expr (&exp, 4);
7740 while (*input_line_pointer++ == ',');
7742 input_line_pointer--;
7743 demand_empty_rest_of_line ();
7747 /* Handle Vector operations. */
7750 check_VecOperations (char *op_string, char *op_end)
7752 const reg_entry *mask;
7757 && (op_end == NULL || op_string < op_end))
7760 if (*op_string == '{')
7764 /* Check broadcasts. */
7765 if (strncmp (op_string, "1to", 3) == 0)
7770 goto duplicated_vec_op;
7773 if (*op_string == '8')
7774 bcst_type = BROADCAST_1TO8;
7775 else if (*op_string == '4')
7776 bcst_type = BROADCAST_1TO4;
7777 else if (*op_string == '2')
7778 bcst_type = BROADCAST_1TO2;
7779 else if (*op_string == '1'
7780 && *(op_string+1) == '6')
7782 bcst_type = BROADCAST_1TO16;
7787 as_bad (_("Unsupported broadcast: `%s'"), saved);
7792 broadcast_op.type = bcst_type;
7793 broadcast_op.operand = this_operand;
7794 i.broadcast = &broadcast_op;
7796 /* Check masking operation. */
7797 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7799 /* k0 can't be used for write mask. */
7800 if (mask->reg_num == 0)
7802 as_bad (_("`%s' can't be used for write mask"),
7809 mask_op.mask = mask;
7810 mask_op.zeroing = 0;
7811 mask_op.operand = this_operand;
7817 goto duplicated_vec_op;
7819 i.mask->mask = mask;
7821 /* Only "{z}" is allowed here. No need to check
7822 zeroing mask explicitly. */
7823 if (i.mask->operand != this_operand)
7825 as_bad (_("invalid write mask `%s'"), saved);
7832 /* Check zeroing-flag for masking operation. */
7833 else if (*op_string == 'z')
7837 mask_op.mask = NULL;
7838 mask_op.zeroing = 1;
7839 mask_op.operand = this_operand;
7844 if (i.mask->zeroing)
7847 as_bad (_("duplicated `%s'"), saved);
7851 i.mask->zeroing = 1;
7853 /* Only "{%k}" is allowed here. No need to check mask
7854 register explicitly. */
7855 if (i.mask->operand != this_operand)
7857 as_bad (_("invalid zeroing-masking `%s'"),
7866 goto unknown_vec_op;
7868 if (*op_string != '}')
7870 as_bad (_("missing `}' in `%s'"), saved);
7877 /* We don't know this one. */
7878 as_bad (_("unknown vector operation: `%s'"), saved);
7886 i386_immediate (char *imm_start)
7888 char *save_input_line_pointer;
7889 char *gotfree_input_line;
7892 i386_operand_type types;
7894 operand_type_set (&types, ~0);
7896 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7898 as_bad (_("at most %d immediate operands are allowed"),
7899 MAX_IMMEDIATE_OPERANDS);
7903 exp = &im_expressions[i.imm_operands++];
7904 i.op[this_operand].imms = exp;
7906 if (is_space_char (*imm_start))
7909 save_input_line_pointer = input_line_pointer;
7910 input_line_pointer = imm_start;
7912 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
7913 if (gotfree_input_line)
7914 input_line_pointer = gotfree_input_line;
7916 exp_seg = expression (exp);
7920 /* Handle vector operations. */
7921 if (*input_line_pointer == '{')
7923 input_line_pointer = check_VecOperations (input_line_pointer,
7925 if (input_line_pointer == NULL)
7929 if (*input_line_pointer)
7930 as_bad (_("junk `%s' after expression"), input_line_pointer);
7932 input_line_pointer = save_input_line_pointer;
7933 if (gotfree_input_line)
7935 free (gotfree_input_line);
7937 if (exp->X_op == O_constant || exp->X_op == O_register)
7938 exp->X_op = O_illegal;
7941 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7945 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7946 i386_operand_type types, const char *imm_start)
7948 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7951 as_bad (_("missing or invalid immediate expression `%s'"),
7955 else if (exp->X_op == O_constant)
7957 /* Size it properly later. */
7958 i.types[this_operand].bitfield.imm64 = 1;
7959 /* If not 64bit, sign extend val. */
7960 if (flag_code != CODE_64BIT
7961 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7963 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7965 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7966 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7967 && exp_seg != absolute_section
7968 && exp_seg != text_section
7969 && exp_seg != data_section
7970 && exp_seg != bss_section
7971 && exp_seg != undefined_section
7972 && !bfd_is_com_section (exp_seg))
7974 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
7978 else if (!intel_syntax && exp_seg == reg_section)
7981 as_bad (_("illegal immediate register operand %s"), imm_start);
7986 /* This is an address. The size of the address will be
7987 determined later, depending on destination register,
7988 suffix, or the default for the section. */
7989 i.types[this_operand].bitfield.imm8 = 1;
7990 i.types[this_operand].bitfield.imm16 = 1;
7991 i.types[this_operand].bitfield.imm32 = 1;
7992 i.types[this_operand].bitfield.imm32s = 1;
7993 i.types[this_operand].bitfield.imm64 = 1;
7994 i.types[this_operand] = operand_type_and (i.types[this_operand],
8002 i386_scale (char *scale)
8005 char *save = input_line_pointer;
8007 input_line_pointer = scale;
8008 val = get_absolute_expression ();
8013 i.log2_scale_factor = 0;
8016 i.log2_scale_factor = 1;
8019 i.log2_scale_factor = 2;
8022 i.log2_scale_factor = 3;
8026 char sep = *input_line_pointer;
8028 *input_line_pointer = '\0';
8029 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8031 *input_line_pointer = sep;
8032 input_line_pointer = save;
8036 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8038 as_warn (_("scale factor of %d without an index register"),
8039 1 << i.log2_scale_factor);
8040 i.log2_scale_factor = 0;
8042 scale = input_line_pointer;
8043 input_line_pointer = save;
8048 i386_displacement (char *disp_start, char *disp_end)
8052 char *save_input_line_pointer;
8053 char *gotfree_input_line;
8055 i386_operand_type bigdisp, types = anydisp;
8058 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8060 as_bad (_("at most %d displacement operands are allowed"),
8061 MAX_MEMORY_OPERANDS);
8065 operand_type_set (&bigdisp, 0);
8066 if ((i.types[this_operand].bitfield.jumpabsolute)
8067 || (!current_templates->start->opcode_modifier.jump
8068 && !current_templates->start->opcode_modifier.jumpdword))
8070 bigdisp.bitfield.disp32 = 1;
8071 override = (i.prefix[ADDR_PREFIX] != 0);
8072 if (flag_code == CODE_64BIT)
8076 bigdisp.bitfield.disp32s = 1;
8077 bigdisp.bitfield.disp64 = 1;
8080 else if ((flag_code == CODE_16BIT) ^ override)
8082 bigdisp.bitfield.disp32 = 0;
8083 bigdisp.bitfield.disp16 = 1;
8088 /* For PC-relative branches, the width of the displacement
8089 is dependent upon data size, not address size. */
8090 override = (i.prefix[DATA_PREFIX] != 0);
8091 if (flag_code == CODE_64BIT)
8093 if (override || i.suffix == WORD_MNEM_SUFFIX)
8094 bigdisp.bitfield.disp16 = 1;
8097 bigdisp.bitfield.disp32 = 1;
8098 bigdisp.bitfield.disp32s = 1;
8104 override = (i.suffix == (flag_code != CODE_16BIT
8106 : LONG_MNEM_SUFFIX));
8107 bigdisp.bitfield.disp32 = 1;
8108 if ((flag_code == CODE_16BIT) ^ override)
8110 bigdisp.bitfield.disp32 = 0;
8111 bigdisp.bitfield.disp16 = 1;
8115 i.types[this_operand] = operand_type_or (i.types[this_operand],
8118 exp = &disp_expressions[i.disp_operands];
8119 i.op[this_operand].disps = exp;
8121 save_input_line_pointer = input_line_pointer;
8122 input_line_pointer = disp_start;
8123 END_STRING_AND_SAVE (disp_end);
8125 #ifndef GCC_ASM_O_HACK
8126 #define GCC_ASM_O_HACK 0
8129 END_STRING_AND_SAVE (disp_end + 1);
8130 if (i.types[this_operand].bitfield.baseIndex
8131 && displacement_string_end[-1] == '+')
8133 /* This hack is to avoid a warning when using the "o"
8134 constraint within gcc asm statements.
8137 #define _set_tssldt_desc(n,addr,limit,type) \
8138 __asm__ __volatile__ ( \
8140 "movw %w1,2+%0\n\t" \
8142 "movb %b1,4+%0\n\t" \
8143 "movb %4,5+%0\n\t" \
8144 "movb $0,6+%0\n\t" \
8145 "movb %h1,7+%0\n\t" \
8147 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8149 This works great except that the output assembler ends
8150 up looking a bit weird if it turns out that there is
8151 no offset. You end up producing code that looks like:
8164 So here we provide the missing zero. */
8166 *displacement_string_end = '0';
8169 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8170 if (gotfree_input_line)
8171 input_line_pointer = gotfree_input_line;
8173 exp_seg = expression (exp);
8176 if (*input_line_pointer)
8177 as_bad (_("junk `%s' after expression"), input_line_pointer);
8179 RESTORE_END_STRING (disp_end + 1);
8181 input_line_pointer = save_input_line_pointer;
8182 if (gotfree_input_line)
8184 free (gotfree_input_line);
8186 if (exp->X_op == O_constant || exp->X_op == O_register)
8187 exp->X_op = O_illegal;
8190 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8192 RESTORE_END_STRING (disp_end);
8198 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8199 i386_operand_type types, const char *disp_start)
8201 i386_operand_type bigdisp;
8204 /* We do this to make sure that the section symbol is in
8205 the symbol table. We will ultimately change the relocation
8206 to be relative to the beginning of the section. */
8207 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8208 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8209 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8211 if (exp->X_op != O_symbol)
8214 if (S_IS_LOCAL (exp->X_add_symbol)
8215 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8216 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8217 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8218 exp->X_op = O_subtract;
8219 exp->X_op_symbol = GOT_symbol;
8220 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8221 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8222 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8223 i.reloc[this_operand] = BFD_RELOC_64;
8225 i.reloc[this_operand] = BFD_RELOC_32;
8228 else if (exp->X_op == O_absent
8229 || exp->X_op == O_illegal
8230 || exp->X_op == O_big)
8233 as_bad (_("missing or invalid displacement expression `%s'"),
8238 else if (flag_code == CODE_64BIT
8239 && !i.prefix[ADDR_PREFIX]
8240 && exp->X_op == O_constant)
8242 /* Since displacement is signed extended to 64bit, don't allow
8243 disp32 and turn off disp32s if they are out of range. */
8244 i.types[this_operand].bitfield.disp32 = 0;
8245 if (!fits_in_signed_long (exp->X_add_number))
8247 i.types[this_operand].bitfield.disp32s = 0;
8248 if (i.types[this_operand].bitfield.baseindex)
8250 as_bad (_("0x%lx out range of signed 32bit displacement"),
8251 (long) exp->X_add_number);
8257 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8258 else if (exp->X_op != O_constant
8259 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8260 && exp_seg != absolute_section
8261 && exp_seg != text_section
8262 && exp_seg != data_section
8263 && exp_seg != bss_section
8264 && exp_seg != undefined_section
8265 && !bfd_is_com_section (exp_seg))
8267 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8272 /* Check if this is a displacement only operand. */
8273 bigdisp = i.types[this_operand];
8274 bigdisp.bitfield.disp8 = 0;
8275 bigdisp.bitfield.disp16 = 0;
8276 bigdisp.bitfield.disp32 = 0;
8277 bigdisp.bitfield.disp32s = 0;
8278 bigdisp.bitfield.disp64 = 0;
8279 if (operand_type_all_zero (&bigdisp))
8280 i.types[this_operand] = operand_type_and (i.types[this_operand],
8286 /* Make sure the memory operand we've been dealt is valid.
8287 Return 1 on success, 0 on a failure. */
8290 i386_index_check (const char *operand_string)
8292 const char *kind = "base/index";
8293 enum flag_code addr_mode;
8295 if (i.prefix[ADDR_PREFIX])
8296 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8299 addr_mode = flag_code;
8301 #if INFER_ADDR_PREFIX
8302 if (i.mem_operands == 0)
8304 /* Infer address prefix from the first memory operand. */
8305 const reg_entry *addr_reg = i.base_reg;
8307 if (addr_reg == NULL)
8308 addr_reg = i.index_reg;
8312 if (addr_reg->reg_num == RegEip
8313 || addr_reg->reg_num == RegEiz
8314 || addr_reg->reg_type.bitfield.reg32)
8315 addr_mode = CODE_32BIT;
8316 else if (flag_code != CODE_64BIT
8317 && addr_reg->reg_type.bitfield.reg16)
8318 addr_mode = CODE_16BIT;
8320 if (addr_mode != flag_code)
8322 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8324 /* Change the size of any displacement too. At most one
8325 of Disp16 or Disp32 is set.
8326 FIXME. There doesn't seem to be any real need for
8327 separate Disp16 and Disp32 flags. The same goes for
8328 Imm16 and Imm32. Removing them would probably clean
8329 up the code quite a lot. */
8330 if (flag_code != CODE_64BIT
8331 && (i.types[this_operand].bitfield.disp16
8332 || i.types[this_operand].bitfield.disp32))
8333 i.types[this_operand]
8334 = operand_type_xor (i.types[this_operand], disp16_32);
8341 if (current_templates->start->opcode_modifier.isstring
8342 && !current_templates->start->opcode_modifier.immext
8343 && (current_templates->end[-1].opcode_modifier.isstring
8346 /* Memory operands of string insns are special in that they only allow
8347 a single register (rDI, rSI, or rBX) as their memory address. */
8348 const reg_entry *expected_reg;
8349 static const char *di_si[][2] =
8355 static const char *bx[] = { "ebx", "bx", "rbx" };
8357 kind = "string address";
8359 if (current_templates->start->opcode_modifier.w)
8361 i386_operand_type type = current_templates->end[-1].operand_types[0];
8363 if (!type.bitfield.baseindex
8364 || ((!i.mem_operands != !intel_syntax)
8365 && current_templates->end[-1].operand_types[1]
8366 .bitfield.baseindex))
8367 type = current_templates->end[-1].operand_types[1];
8368 expected_reg = hash_find (reg_hash,
8369 di_si[addr_mode][type.bitfield.esseg]);
8373 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8375 if (i.base_reg != expected_reg
8377 || operand_type_check (i.types[this_operand], disp))
8379 /* The second memory operand must have the same size as
8383 && !((addr_mode == CODE_64BIT
8384 && i.base_reg->reg_type.bitfield.reg64)
8385 || (addr_mode == CODE_32BIT
8386 ? i.base_reg->reg_type.bitfield.reg32
8387 : i.base_reg->reg_type.bitfield.reg16)))
8390 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8392 intel_syntax ? '[' : '(',
8394 expected_reg->reg_name,
8395 intel_syntax ? ']' : ')');
8402 as_bad (_("`%s' is not a valid %s expression"),
8403 operand_string, kind);
8408 if (addr_mode != CODE_16BIT)
8410 /* 32-bit/64-bit checks. */
8412 && (addr_mode == CODE_64BIT
8413 ? !i.base_reg->reg_type.bitfield.reg64
8414 : !i.base_reg->reg_type.bitfield.reg32)
8416 || (i.base_reg->reg_num
8417 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8419 && !i.index_reg->reg_type.bitfield.regxmm
8420 && !i.index_reg->reg_type.bitfield.regymm
8421 && !i.index_reg->reg_type.bitfield.regzmm
8422 && ((addr_mode == CODE_64BIT
8423 ? !(i.index_reg->reg_type.bitfield.reg64
8424 || i.index_reg->reg_num == RegRiz)
8425 : !(i.index_reg->reg_type.bitfield.reg32
8426 || i.index_reg->reg_num == RegEiz))
8427 || !i.index_reg->reg_type.bitfield.baseindex)))
8432 /* 16-bit checks. */
8434 && (!i.base_reg->reg_type.bitfield.reg16
8435 || !i.base_reg->reg_type.bitfield.baseindex))
8437 && (!i.index_reg->reg_type.bitfield.reg16
8438 || !i.index_reg->reg_type.bitfield.baseindex
8440 && i.base_reg->reg_num < 6
8441 && i.index_reg->reg_num >= 6
8442 && i.log2_scale_factor == 0))))
8449 /* Handle vector immediates. */
8452 RC_SAE_immediate (const char *imm_start)
8454 unsigned int match_found, j;
8455 const char *pstr = imm_start;
8463 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8465 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8469 rc_op.type = RC_NamesTable[j].type;
8470 rc_op.operand = this_operand;
8471 i.rounding = &rc_op;
8475 as_bad (_("duplicated `%s'"), imm_start);
8478 pstr += RC_NamesTable[j].len;
8488 as_bad (_("Missing '}': '%s'"), imm_start);
8491 /* RC/SAE immediate string should contain nothing more. */;
8494 as_bad (_("Junk after '}': '%s'"), imm_start);
8498 exp = &im_expressions[i.imm_operands++];
8499 i.op[this_operand].imms = exp;
8501 exp->X_op = O_constant;
8502 exp->X_add_number = 0;
8503 exp->X_add_symbol = (symbolS *) 0;
8504 exp->X_op_symbol = (symbolS *) 0;
8506 i.types[this_operand].bitfield.imm8 = 1;
8510 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8514 i386_att_operand (char *operand_string)
8518 char *op_string = operand_string;
8520 if (is_space_char (*op_string))
8523 /* We check for an absolute prefix (differentiating,
8524 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8525 if (*op_string == ABSOLUTE_PREFIX)
8528 if (is_space_char (*op_string))
8530 i.types[this_operand].bitfield.jumpabsolute = 1;
8533 /* Check if operand is a register. */
8534 if ((r = parse_register (op_string, &end_op)) != NULL)
8536 i386_operand_type temp;
8538 /* Check for a segment override by searching for ':' after a
8539 segment register. */
8541 if (is_space_char (*op_string))
8543 if (*op_string == ':'
8544 && (r->reg_type.bitfield.sreg2
8545 || r->reg_type.bitfield.sreg3))
8550 i.seg[i.mem_operands] = &es;
8553 i.seg[i.mem_operands] = &cs;
8556 i.seg[i.mem_operands] = &ss;
8559 i.seg[i.mem_operands] = &ds;
8562 i.seg[i.mem_operands] = &fs;
8565 i.seg[i.mem_operands] = &gs;
8569 /* Skip the ':' and whitespace. */
8571 if (is_space_char (*op_string))
8574 if (!is_digit_char (*op_string)
8575 && !is_identifier_char (*op_string)
8576 && *op_string != '('
8577 && *op_string != ABSOLUTE_PREFIX)
8579 as_bad (_("bad memory operand `%s'"), op_string);
8582 /* Handle case of %es:*foo. */
8583 if (*op_string == ABSOLUTE_PREFIX)
8586 if (is_space_char (*op_string))
8588 i.types[this_operand].bitfield.jumpabsolute = 1;
8590 goto do_memory_reference;
8593 /* Handle vector operations. */
8594 if (*op_string == '{')
8596 op_string = check_VecOperations (op_string, NULL);
8597 if (op_string == NULL)
8603 as_bad (_("junk `%s' after register"), op_string);
8607 temp.bitfield.baseindex = 0;
8608 i.types[this_operand] = operand_type_or (i.types[this_operand],
8610 i.types[this_operand].bitfield.unspecified = 0;
8611 i.op[this_operand].regs = r;
8614 else if (*op_string == REGISTER_PREFIX)
8616 as_bad (_("bad register name `%s'"), op_string);
8619 else if (*op_string == IMMEDIATE_PREFIX)
8622 if (i.types[this_operand].bitfield.jumpabsolute)
8624 as_bad (_("immediate operand illegal with absolute jump"));
8627 if (!i386_immediate (op_string))
8630 else if (RC_SAE_immediate (operand_string))
8632 /* If it is a RC or SAE immediate, do nothing. */
8635 else if (is_digit_char (*op_string)
8636 || is_identifier_char (*op_string)
8637 || *op_string == '"'
8638 || *op_string == '(')
8640 /* This is a memory reference of some sort. */
8643 /* Start and end of displacement string expression (if found). */
8644 char *displacement_string_start;
8645 char *displacement_string_end;
8648 do_memory_reference:
8649 if ((i.mem_operands == 1
8650 && !current_templates->start->opcode_modifier.isstring)
8651 || i.mem_operands == 2)
8653 as_bad (_("too many memory references for `%s'"),
8654 current_templates->start->name);
8658 /* Check for base index form. We detect the base index form by
8659 looking for an ')' at the end of the operand, searching
8660 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8662 base_string = op_string + strlen (op_string);
8664 /* Handle vector operations. */
8665 vop_start = strchr (op_string, '{');
8666 if (vop_start && vop_start < base_string)
8668 if (check_VecOperations (vop_start, base_string) == NULL)
8670 base_string = vop_start;
8674 if (is_space_char (*base_string))
8677 /* If we only have a displacement, set-up for it to be parsed later. */
8678 displacement_string_start = op_string;
8679 displacement_string_end = base_string + 1;
8681 if (*base_string == ')')
8684 unsigned int parens_balanced = 1;
8685 /* We've already checked that the number of left & right ()'s are
8686 equal, so this loop will not be infinite. */
8690 if (*base_string == ')')
8692 if (*base_string == '(')
8695 while (parens_balanced);
8697 temp_string = base_string;
8699 /* Skip past '(' and whitespace. */
8701 if (is_space_char (*base_string))
8704 if (*base_string == ','
8705 || ((i.base_reg = parse_register (base_string, &end_op))
8708 displacement_string_end = temp_string;
8710 i.types[this_operand].bitfield.baseindex = 1;
8714 base_string = end_op;
8715 if (is_space_char (*base_string))
8719 /* There may be an index reg or scale factor here. */
8720 if (*base_string == ',')
8723 if (is_space_char (*base_string))
8726 if ((i.index_reg = parse_register (base_string, &end_op))
8729 base_string = end_op;
8730 if (is_space_char (*base_string))
8732 if (*base_string == ',')
8735 if (is_space_char (*base_string))
8738 else if (*base_string != ')')
8740 as_bad (_("expecting `,' or `)' "
8741 "after index register in `%s'"),
8746 else if (*base_string == REGISTER_PREFIX)
8748 end_op = strchr (base_string, ',');
8751 as_bad (_("bad register name `%s'"), base_string);
8755 /* Check for scale factor. */
8756 if (*base_string != ')')
8758 char *end_scale = i386_scale (base_string);
8763 base_string = end_scale;
8764 if (is_space_char (*base_string))
8766 if (*base_string != ')')
8768 as_bad (_("expecting `)' "
8769 "after scale factor in `%s'"),
8774 else if (!i.index_reg)
8776 as_bad (_("expecting index register or scale factor "
8777 "after `,'; got '%c'"),
8782 else if (*base_string != ')')
8784 as_bad (_("expecting `,' or `)' "
8785 "after base register in `%s'"),
8790 else if (*base_string == REGISTER_PREFIX)
8792 end_op = strchr (base_string, ',');
8795 as_bad (_("bad register name `%s'"), base_string);
8800 /* If there's an expression beginning the operand, parse it,
8801 assuming displacement_string_start and
8802 displacement_string_end are meaningful. */
8803 if (displacement_string_start != displacement_string_end)
8805 if (!i386_displacement (displacement_string_start,
8806 displacement_string_end))
8810 /* Special case for (%dx) while doing input/output op. */
8812 && operand_type_equal (&i.base_reg->reg_type,
8813 ®16_inoutportreg)
8815 && i.log2_scale_factor == 0
8816 && i.seg[i.mem_operands] == 0
8817 && !operand_type_check (i.types[this_operand], disp))
8819 i.types[this_operand] = inoutportreg;
8823 if (i386_index_check (operand_string) == 0)
8825 i.types[this_operand].bitfield.mem = 1;
8830 /* It's not a memory operand; argh! */
8831 as_bad (_("invalid char %s beginning operand %d `%s'"),
8832 output_invalid (*op_string),
8837 return 1; /* Normal return. */
8840 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8841 that an rs_machine_dependent frag may reach. */
8844 i386_frag_max_var (fragS *frag)
8846 /* The only relaxable frags are for jumps.
8847 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8848 gas_assert (frag->fr_type == rs_machine_dependent);
8849 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8852 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8854 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
8856 /* STT_GNU_IFUNC symbol must go through PLT. */
8857 if ((symbol_get_bfdsym (fr_symbol)->flags
8858 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8861 if (!S_IS_EXTERNAL (fr_symbol))
8862 /* Symbol may be weak or local. */
8863 return !S_IS_WEAK (fr_symbol);
8865 /* Global symbols with non-default visibility can't be preempted. */
8866 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8869 if (fr_var != NO_RELOC)
8870 switch ((enum bfd_reloc_code_real) fr_var)
8872 case BFD_RELOC_386_PLT32:
8873 case BFD_RELOC_X86_64_PLT32:
8874 /* Symbol with PLT relocatin may be preempted. */
8880 /* Global symbols with default visibility in a shared library may be
8881 preempted by another definition. */
8886 /* md_estimate_size_before_relax()
8888 Called just before relax() for rs_machine_dependent frags. The x86
8889 assembler uses these frags to handle variable size jump
8892 Any symbol that is now undefined will not become defined.
8893 Return the correct fr_subtype in the frag.
8894 Return the initial "guess for variable size of frag" to caller.
8895 The guess is actually the growth beyond the fixed part. Whatever
8896 we do to grow the fixed or variable part contributes to our
8900 md_estimate_size_before_relax (fragS *fragP, segT segment)
8902 /* We've already got fragP->fr_subtype right; all we have to do is
8903 check for un-relaxable symbols. On an ELF system, we can't relax
8904 an externally visible symbol, because it may be overridden by a
8906 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8907 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8909 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8912 #if defined (OBJ_COFF) && defined (TE_PE)
8913 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8914 && S_IS_WEAK (fragP->fr_symbol))
8918 /* Symbol is undefined in this segment, or we need to keep a
8919 reloc so that weak symbols can be overridden. */
8920 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8921 enum bfd_reloc_code_real reloc_type;
8922 unsigned char *opcode;
8925 if (fragP->fr_var != NO_RELOC)
8926 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8928 reloc_type = BFD_RELOC_16_PCREL;
8930 reloc_type = BFD_RELOC_32_PCREL;
8932 old_fr_fix = fragP->fr_fix;
8933 opcode = (unsigned char *) fragP->fr_opcode;
8935 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8938 /* Make jmp (0xeb) a (d)word displacement jump. */
8940 fragP->fr_fix += size;
8941 fix_new (fragP, old_fr_fix, size,
8943 fragP->fr_offset, 1,
8949 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8951 /* Negate the condition, and branch past an
8952 unconditional jump. */
8955 /* Insert an unconditional jump. */
8957 /* We added two extra opcode bytes, and have a two byte
8959 fragP->fr_fix += 2 + 2;
8960 fix_new (fragP, old_fr_fix + 2, 2,
8962 fragP->fr_offset, 1,
8969 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8974 fixP = fix_new (fragP, old_fr_fix, 1,
8976 fragP->fr_offset, 1,
8978 fixP->fx_signed = 1;
8982 /* This changes the byte-displacement jump 0x7N
8983 to the (d)word-displacement jump 0x0f,0x8N. */
8984 opcode[1] = opcode[0] + 0x10;
8985 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8986 /* We've added an opcode byte. */
8987 fragP->fr_fix += 1 + size;
8988 fix_new (fragP, old_fr_fix + 1, size,
8990 fragP->fr_offset, 1,
8995 BAD_CASE (fragP->fr_subtype);
8999 return fragP->fr_fix - old_fr_fix;
9002 /* Guess size depending on current relax state. Initially the relax
9003 state will correspond to a short jump and we return 1, because
9004 the variable part of the frag (the branch offset) is one byte
9005 long. However, we can relax a section more than once and in that
9006 case we must either set fr_subtype back to the unrelaxed state,
9007 or return the value for the appropriate branch. */
9008 return md_relax_table[fragP->fr_subtype].rlx_length;
9011 /* Called after relax() is finished.
9013 In: Address of frag.
9014 fr_type == rs_machine_dependent.
9015 fr_subtype is what the address relaxed to.
9017 Out: Any fixSs and constants are set up.
9018 Caller will turn frag into a ".space 0". */
9021 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9024 unsigned char *opcode;
9025 unsigned char *where_to_put_displacement = NULL;
9026 offsetT target_address;
9027 offsetT opcode_address;
9028 unsigned int extension = 0;
9029 offsetT displacement_from_opcode_start;
9031 opcode = (unsigned char *) fragP->fr_opcode;
9033 /* Address we want to reach in file space. */
9034 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9036 /* Address opcode resides at in file space. */
9037 opcode_address = fragP->fr_address + fragP->fr_fix;
9039 /* Displacement from opcode start to fill into instruction. */
9040 displacement_from_opcode_start = target_address - opcode_address;
9042 if ((fragP->fr_subtype & BIG) == 0)
9044 /* Don't have to change opcode. */
9045 extension = 1; /* 1 opcode + 1 displacement */
9046 where_to_put_displacement = &opcode[1];
9050 if (no_cond_jump_promotion
9051 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9052 as_warn_where (fragP->fr_file, fragP->fr_line,
9053 _("long jump required"));
9055 switch (fragP->fr_subtype)
9057 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9058 extension = 4; /* 1 opcode + 4 displacement */
9060 where_to_put_displacement = &opcode[1];
9063 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9064 extension = 2; /* 1 opcode + 2 displacement */
9066 where_to_put_displacement = &opcode[1];
9069 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9070 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9071 extension = 5; /* 2 opcode + 4 displacement */
9072 opcode[1] = opcode[0] + 0x10;
9073 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9074 where_to_put_displacement = &opcode[2];
9077 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9078 extension = 3; /* 2 opcode + 2 displacement */
9079 opcode[1] = opcode[0] + 0x10;
9080 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9081 where_to_put_displacement = &opcode[2];
9084 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9089 where_to_put_displacement = &opcode[3];
9093 BAD_CASE (fragP->fr_subtype);
9098 /* If size if less then four we are sure that the operand fits,
9099 but if it's 4, then it could be that the displacement is larger
9101 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9103 && ((addressT) (displacement_from_opcode_start - extension
9104 + ((addressT) 1 << 31))
9105 > (((addressT) 2 << 31) - 1)))
9107 as_bad_where (fragP->fr_file, fragP->fr_line,
9108 _("jump target out of range"));
9109 /* Make us emit 0. */
9110 displacement_from_opcode_start = extension;
9112 /* Now put displacement after opcode. */
9113 md_number_to_chars ((char *) where_to_put_displacement,
9114 (valueT) (displacement_from_opcode_start - extension),
9115 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9116 fragP->fr_fix += extension;
9119 /* Apply a fixup (fixP) to segment data, once it has been determined
9120 by our caller that we have all the info we need to fix it up.
9122 Parameter valP is the pointer to the value of the bits.
9124 On the 386, immediates, displacements, and data pointers are all in
9125 the same (little-endian) format, so we don't need to care about which
9129 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9131 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9132 valueT value = *valP;
9134 #if !defined (TE_Mach)
9137 switch (fixP->fx_r_type)
9143 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9146 case BFD_RELOC_X86_64_32S:
9147 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9150 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9153 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9158 if (fixP->fx_addsy != NULL
9159 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9160 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9161 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9162 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9163 && !use_rela_relocations)
9165 /* This is a hack. There should be a better way to handle this.
9166 This covers for the fact that bfd_install_relocation will
9167 subtract the current location (for partial_inplace, PC relative
9168 relocations); see more below. */
9172 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9175 value += fixP->fx_where + fixP->fx_frag->fr_address;
9177 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9180 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9183 || (symbol_section_p (fixP->fx_addsy)
9184 && sym_seg != absolute_section))
9185 && !generic_force_reloc (fixP))
9187 /* Yes, we add the values in twice. This is because
9188 bfd_install_relocation subtracts them out again. I think
9189 bfd_install_relocation is broken, but I don't dare change
9191 value += fixP->fx_where + fixP->fx_frag->fr_address;
9195 #if defined (OBJ_COFF) && defined (TE_PE)
9196 /* For some reason, the PE format does not store a
9197 section address offset for a PC relative symbol. */
9198 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9199 || S_IS_WEAK (fixP->fx_addsy))
9200 value += md_pcrel_from (fixP);
9203 #if defined (OBJ_COFF) && defined (TE_PE)
9204 if (fixP->fx_addsy != NULL
9205 && S_IS_WEAK (fixP->fx_addsy)
9206 /* PR 16858: Do not modify weak function references. */
9207 && ! fixP->fx_pcrel)
9209 #if !defined (TE_PEP)
9210 /* For x86 PE weak function symbols are neither PC-relative
9211 nor do they set S_IS_FUNCTION. So the only reliable way
9212 to detect them is to check the flags of their containing
9214 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9215 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9219 value -= S_GET_VALUE (fixP->fx_addsy);
9223 /* Fix a few things - the dynamic linker expects certain values here,
9224 and we must not disappoint it. */
9225 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9226 if (IS_ELF && fixP->fx_addsy)
9227 switch (fixP->fx_r_type)
9229 case BFD_RELOC_386_PLT32:
9230 case BFD_RELOC_X86_64_PLT32:
9231 /* Make the jump instruction point to the address of the operand. At
9232 runtime we merely add the offset to the actual PLT entry. */
9236 case BFD_RELOC_386_TLS_GD:
9237 case BFD_RELOC_386_TLS_LDM:
9238 case BFD_RELOC_386_TLS_IE_32:
9239 case BFD_RELOC_386_TLS_IE:
9240 case BFD_RELOC_386_TLS_GOTIE:
9241 case BFD_RELOC_386_TLS_GOTDESC:
9242 case BFD_RELOC_X86_64_TLSGD:
9243 case BFD_RELOC_X86_64_TLSLD:
9244 case BFD_RELOC_X86_64_GOTTPOFF:
9245 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9246 value = 0; /* Fully resolved at runtime. No addend. */
9248 case BFD_RELOC_386_TLS_LE:
9249 case BFD_RELOC_386_TLS_LDO_32:
9250 case BFD_RELOC_386_TLS_LE_32:
9251 case BFD_RELOC_X86_64_DTPOFF32:
9252 case BFD_RELOC_X86_64_DTPOFF64:
9253 case BFD_RELOC_X86_64_TPOFF32:
9254 case BFD_RELOC_X86_64_TPOFF64:
9255 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9258 case BFD_RELOC_386_TLS_DESC_CALL:
9259 case BFD_RELOC_X86_64_TLSDESC_CALL:
9260 value = 0; /* Fully resolved at runtime. No addend. */
9261 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9265 case BFD_RELOC_386_GOT32:
9266 case BFD_RELOC_X86_64_GOT32:
9267 value = 0; /* Fully resolved at runtime. No addend. */
9270 case BFD_RELOC_VTABLE_INHERIT:
9271 case BFD_RELOC_VTABLE_ENTRY:
9278 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9280 #endif /* !defined (TE_Mach) */
9282 /* Are we finished with this relocation now? */
9283 if (fixP->fx_addsy == NULL)
9285 #if defined (OBJ_COFF) && defined (TE_PE)
9286 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9289 /* Remember value for tc_gen_reloc. */
9290 fixP->fx_addnumber = value;
9291 /* Clear out the frag for now. */
9295 else if (use_rela_relocations)
9297 fixP->fx_no_overflow = 1;
9298 /* Remember value for tc_gen_reloc. */
9299 fixP->fx_addnumber = value;
9303 md_number_to_chars (p, value, fixP->fx_size);
9307 md_atof (int type, char *litP, int *sizeP)
9309 /* This outputs the LITTLENUMs in REVERSE order;
9310 in accord with the bigendian 386. */
9311 return ieee_md_atof (type, litP, sizeP, FALSE);
9314 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9317 output_invalid (int c)
9320 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9323 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9324 "(0x%x)", (unsigned char) c);
9325 return output_invalid_buf;
9328 /* REG_STRING starts *before* REGISTER_PREFIX. */
9330 static const reg_entry *
9331 parse_real_register (char *reg_string, char **end_op)
9333 char *s = reg_string;
9335 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9338 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9339 if (*s == REGISTER_PREFIX)
9342 if (is_space_char (*s))
9346 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9348 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9349 return (const reg_entry *) NULL;
9353 /* For naked regs, make sure that we are not dealing with an identifier.
9354 This prevents confusing an identifier like `eax_var' with register
9356 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9357 return (const reg_entry *) NULL;
9361 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9363 /* Handle floating point regs, allowing spaces in the (i) part. */
9364 if (r == i386_regtab /* %st is first entry of table */)
9366 if (is_space_char (*s))
9371 if (is_space_char (*s))
9373 if (*s >= '0' && *s <= '7')
9377 if (is_space_char (*s))
9382 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9387 /* We have "%st(" then garbage. */
9388 return (const reg_entry *) NULL;
9392 if (r == NULL || allow_pseudo_reg)
9395 if (operand_type_all_zero (&r->reg_type))
9396 return (const reg_entry *) NULL;
9398 if ((r->reg_type.bitfield.reg32
9399 || r->reg_type.bitfield.sreg3
9400 || r->reg_type.bitfield.control
9401 || r->reg_type.bitfield.debug
9402 || r->reg_type.bitfield.test)
9403 && !cpu_arch_flags.bitfield.cpui386)
9404 return (const reg_entry *) NULL;
9406 if (r->reg_type.bitfield.floatreg
9407 && !cpu_arch_flags.bitfield.cpu8087
9408 && !cpu_arch_flags.bitfield.cpu287
9409 && !cpu_arch_flags.bitfield.cpu387)
9410 return (const reg_entry *) NULL;
9412 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9413 return (const reg_entry *) NULL;
9415 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9416 return (const reg_entry *) NULL;
9418 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9419 return (const reg_entry *) NULL;
9421 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9422 && !cpu_arch_flags.bitfield.cpuavx512f)
9423 return (const reg_entry *) NULL;
9425 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9426 if (!allow_index_reg
9427 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9428 return (const reg_entry *) NULL;
9430 /* Upper 16 vector register is only available with VREX in 64bit
9432 if ((r->reg_flags & RegVRex))
9434 if (!cpu_arch_flags.bitfield.cpuvrex
9435 || flag_code != CODE_64BIT)
9436 return (const reg_entry *) NULL;
9441 if (((r->reg_flags & (RegRex64 | RegRex))
9442 || r->reg_type.bitfield.reg64)
9443 && (!cpu_arch_flags.bitfield.cpulm
9444 || !operand_type_equal (&r->reg_type, &control))
9445 && flag_code != CODE_64BIT)
9446 return (const reg_entry *) NULL;
9448 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9449 return (const reg_entry *) NULL;
9454 /* REG_STRING starts *before* REGISTER_PREFIX. */
9456 static const reg_entry *
9457 parse_register (char *reg_string, char **end_op)
9461 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9462 r = parse_real_register (reg_string, end_op);
9467 char *save = input_line_pointer;
9471 input_line_pointer = reg_string;
9472 c = get_symbol_name (®_string);
9473 symbolP = symbol_find (reg_string);
9474 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9476 const expressionS *e = symbol_get_value_expression (symbolP);
9478 know (e->X_op == O_register);
9479 know (e->X_add_number >= 0
9480 && (valueT) e->X_add_number < i386_regtab_size);
9481 r = i386_regtab + e->X_add_number;
9482 if ((r->reg_flags & RegVRex))
9484 *end_op = input_line_pointer;
9486 *input_line_pointer = c;
9487 input_line_pointer = save;
9493 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9496 char *end = input_line_pointer;
9499 r = parse_register (name, &input_line_pointer);
9500 if (r && end <= input_line_pointer)
9502 *nextcharP = *input_line_pointer;
9503 *input_line_pointer = 0;
9504 e->X_op = O_register;
9505 e->X_add_number = r - i386_regtab;
9508 input_line_pointer = end;
9510 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9514 md_operand (expressionS *e)
9519 switch (*input_line_pointer)
9521 case REGISTER_PREFIX:
9522 r = parse_real_register (input_line_pointer, &end);
9525 e->X_op = O_register;
9526 e->X_add_number = r - i386_regtab;
9527 input_line_pointer = end;
9532 gas_assert (intel_syntax);
9533 end = input_line_pointer++;
9535 if (*input_line_pointer == ']')
9537 ++input_line_pointer;
9538 e->X_op_symbol = make_expr_symbol (e);
9539 e->X_add_symbol = NULL;
9540 e->X_add_number = 0;
9546 input_line_pointer = end;
9553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9554 const char *md_shortopts = "kVQ:sqn";
9556 const char *md_shortopts = "qn";
9559 #define OPTION_32 (OPTION_MD_BASE + 0)
9560 #define OPTION_64 (OPTION_MD_BASE + 1)
9561 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9562 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9563 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9564 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9565 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9566 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9567 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9568 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9569 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9570 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9571 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9572 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9573 #define OPTION_X32 (OPTION_MD_BASE + 14)
9574 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9575 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9576 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9577 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9578 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9579 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9580 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
9581 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9582 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
9584 struct option md_longopts[] =
9586 {"32", no_argument, NULL, OPTION_32},
9587 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9588 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9589 {"64", no_argument, NULL, OPTION_64},
9591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9592 {"x32", no_argument, NULL, OPTION_X32},
9593 {"mshared", no_argument, NULL, OPTION_MSHARED},
9595 {"divide", no_argument, NULL, OPTION_DIVIDE},
9596 {"march", required_argument, NULL, OPTION_MARCH},
9597 {"mtune", required_argument, NULL, OPTION_MTUNE},
9598 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9599 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9600 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9601 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9602 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9603 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9604 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9605 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9606 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9607 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9608 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9609 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9610 # if defined (TE_PE) || defined (TE_PEP)
9611 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9613 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
9614 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
9615 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9616 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
9617 {NULL, no_argument, NULL, 0}
9619 size_t md_longopts_size = sizeof (md_longopts);
9622 md_parse_option (int c, char *arg)
9630 optimize_align_code = 0;
9637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9638 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9639 should be emitted or not. FIXME: Not implemented. */
9643 /* -V: SVR4 argument to print version ID. */
9645 print_version_id ();
9648 /* -k: Ignore for FreeBSD compatibility. */
9653 /* -s: On i386 Solaris, this tells the native assembler to use
9654 .stab instead of .stab.excl. We always use .stab anyhow. */
9657 case OPTION_MSHARED:
9661 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9662 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9665 const char **list, **l;
9667 list = bfd_target_list ();
9668 for (l = list; *l != NULL; l++)
9669 if (CONST_STRNEQ (*l, "elf64-x86-64")
9670 || strcmp (*l, "coff-x86-64") == 0
9671 || strcmp (*l, "pe-x86-64") == 0
9672 || strcmp (*l, "pei-x86-64") == 0
9673 || strcmp (*l, "mach-o-x86-64") == 0)
9675 default_arch = "x86_64";
9679 as_fatal (_("no compiled in support for x86_64"));
9685 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9689 const char **list, **l;
9691 list = bfd_target_list ();
9692 for (l = list; *l != NULL; l++)
9693 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9695 default_arch = "x86_64:32";
9699 as_fatal (_("no compiled in support for 32bit x86_64"));
9703 as_fatal (_("32bit x86_64 is only supported for ELF"));
9708 default_arch = "i386";
9712 #ifdef SVR4_COMMENT_CHARS
9717 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9719 for (s = i386_comment_chars; *s != '\0'; s++)
9723 i386_comment_chars = n;
9729 arch = xstrdup (arg);
9733 as_fatal (_("invalid -march= option: `%s'"), arg);
9734 next = strchr (arch, '+');
9737 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9739 if (strcmp (arch, cpu_arch [j].name) == 0)
9742 if (! cpu_arch[j].flags.bitfield.cpui386)
9745 cpu_arch_name = cpu_arch[j].name;
9746 cpu_sub_arch_name = NULL;
9747 cpu_arch_flags = cpu_arch[j].flags;
9748 cpu_arch_isa = cpu_arch[j].type;
9749 cpu_arch_isa_flags = cpu_arch[j].flags;
9750 if (!cpu_arch_tune_set)
9752 cpu_arch_tune = cpu_arch_isa;
9753 cpu_arch_tune_flags = cpu_arch_isa_flags;
9757 else if (*cpu_arch [j].name == '.'
9758 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9760 /* ISA entension. */
9761 i386_cpu_flags flags;
9763 if (!cpu_arch[j].negated)
9764 flags = cpu_flags_or (cpu_arch_flags,
9767 flags = cpu_flags_and_not (cpu_arch_flags,
9770 if (!valid_iamcu_cpu_flags (&flags))
9771 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9772 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9774 if (cpu_sub_arch_name)
9776 char *name = cpu_sub_arch_name;
9777 cpu_sub_arch_name = concat (name,
9779 (const char *) NULL);
9783 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9784 cpu_arch_flags = flags;
9785 cpu_arch_isa_flags = flags;
9791 if (j >= ARRAY_SIZE (cpu_arch))
9792 as_fatal (_("invalid -march= option: `%s'"), arg);
9796 while (next != NULL );
9801 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9802 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9804 if (strcmp (arg, cpu_arch [j].name) == 0)
9806 cpu_arch_tune_set = 1;
9807 cpu_arch_tune = cpu_arch [j].type;
9808 cpu_arch_tune_flags = cpu_arch[j].flags;
9812 if (j >= ARRAY_SIZE (cpu_arch))
9813 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9816 case OPTION_MMNEMONIC:
9817 if (strcasecmp (arg, "att") == 0)
9819 else if (strcasecmp (arg, "intel") == 0)
9822 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9825 case OPTION_MSYNTAX:
9826 if (strcasecmp (arg, "att") == 0)
9828 else if (strcasecmp (arg, "intel") == 0)
9831 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9834 case OPTION_MINDEX_REG:
9835 allow_index_reg = 1;
9838 case OPTION_MNAKED_REG:
9839 allow_naked_reg = 1;
9842 case OPTION_MOLD_GCC:
9846 case OPTION_MSSE2AVX:
9850 case OPTION_MSSE_CHECK:
9851 if (strcasecmp (arg, "error") == 0)
9852 sse_check = check_error;
9853 else if (strcasecmp (arg, "warning") == 0)
9854 sse_check = check_warning;
9855 else if (strcasecmp (arg, "none") == 0)
9856 sse_check = check_none;
9858 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9861 case OPTION_MOPERAND_CHECK:
9862 if (strcasecmp (arg, "error") == 0)
9863 operand_check = check_error;
9864 else if (strcasecmp (arg, "warning") == 0)
9865 operand_check = check_warning;
9866 else if (strcasecmp (arg, "none") == 0)
9867 operand_check = check_none;
9869 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9872 case OPTION_MAVXSCALAR:
9873 if (strcasecmp (arg, "128") == 0)
9875 else if (strcasecmp (arg, "256") == 0)
9878 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9881 case OPTION_MADD_BND_PREFIX:
9885 case OPTION_MEVEXLIG:
9886 if (strcmp (arg, "128") == 0)
9888 else if (strcmp (arg, "256") == 0)
9890 else if (strcmp (arg, "512") == 0)
9893 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9896 case OPTION_MEVEXRCIG:
9897 if (strcmp (arg, "rne") == 0)
9899 else if (strcmp (arg, "rd") == 0)
9901 else if (strcmp (arg, "ru") == 0)
9903 else if (strcmp (arg, "rz") == 0)
9906 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9909 case OPTION_MEVEXWIG:
9910 if (strcmp (arg, "0") == 0)
9912 else if (strcmp (arg, "1") == 0)
9915 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9918 # if defined (TE_PE) || defined (TE_PEP)
9919 case OPTION_MBIG_OBJ:
9924 case OPTION_OMIT_LOCK_PREFIX:
9925 if (strcasecmp (arg, "yes") == 0)
9926 omit_lock_prefix = 1;
9927 else if (strcasecmp (arg, "no") == 0)
9928 omit_lock_prefix = 0;
9930 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9934 cpu_arch_flags.bitfield.cpuamd64 = 1;
9935 cpu_arch_flags.bitfield.cpuintel64 = 0;
9936 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9937 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9940 case OPTION_MINTEL64:
9941 cpu_arch_flags.bitfield.cpuamd64 = 0;
9942 cpu_arch_flags.bitfield.cpuintel64 = 1;
9943 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9944 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9953 #define MESSAGE_TEMPLATE \
9957 show_arch (FILE *stream, int ext, int check)
9959 static char message[] = MESSAGE_TEMPLATE;
9960 char *start = message + 27;
9962 int size = sizeof (MESSAGE_TEMPLATE);
9969 left = size - (start - message);
9970 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9972 /* Should it be skipped? */
9973 if (cpu_arch [j].skip)
9976 name = cpu_arch [j].name;
9977 len = cpu_arch [j].len;
9980 /* It is an extension. Skip if we aren't asked to show it. */
9991 /* It is an processor. Skip if we show only extension. */
9994 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9996 /* It is an impossible processor - skip. */
10000 /* Reserve 2 spaces for ", " or ",\0" */
10003 /* Check if there is any room. */
10011 p = mempcpy (p, name, len);
10015 /* Output the current message now and start a new one. */
10018 fprintf (stream, "%s\n", message);
10020 left = size - (start - message) - len - 2;
10022 gas_assert (left >= 0);
10024 p = mempcpy (p, name, len);
10029 fprintf (stream, "%s\n", message);
10033 md_show_usage (FILE *stream)
10035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10036 fprintf (stream, _("\
10038 -V print assembler version number\n\
10041 fprintf (stream, _("\
10042 -n Do not optimize code alignment\n\
10043 -q quieten some warnings\n"));
10044 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10045 fprintf (stream, _("\
10048 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10049 || defined (TE_PE) || defined (TE_PEP))
10050 fprintf (stream, _("\
10051 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10053 #ifdef SVR4_COMMENT_CHARS
10054 fprintf (stream, _("\
10055 --divide do not treat `/' as a comment character\n"));
10057 fprintf (stream, _("\
10058 --divide ignored\n"));
10060 fprintf (stream, _("\
10061 -march=CPU[,+EXTENSION...]\n\
10062 generate code for CPU and EXTENSION, CPU is one of:\n"));
10063 show_arch (stream, 0, 1);
10064 fprintf (stream, _("\
10065 EXTENSION is combination of:\n"));
10066 show_arch (stream, 1, 0);
10067 fprintf (stream, _("\
10068 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10069 show_arch (stream, 0, 0);
10070 fprintf (stream, _("\
10071 -msse2avx encode SSE instructions with VEX prefix\n"));
10072 fprintf (stream, _("\
10073 -msse-check=[none|error|warning]\n\
10074 check SSE instructions\n"));
10075 fprintf (stream, _("\
10076 -moperand-check=[none|error|warning]\n\
10077 check operand combinations for validity\n"));
10078 fprintf (stream, _("\
10079 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10081 fprintf (stream, _("\
10082 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10084 fprintf (stream, _("\
10085 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10086 for EVEX.W bit ignored instructions\n"));
10087 fprintf (stream, _("\
10088 -mevexrcig=[rne|rd|ru|rz]\n\
10089 encode EVEX instructions with specific EVEX.RC value\n\
10090 for SAE-only ignored instructions\n"));
10091 fprintf (stream, _("\
10092 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10093 fprintf (stream, _("\
10094 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10095 fprintf (stream, _("\
10096 -mindex-reg support pseudo index registers\n"));
10097 fprintf (stream, _("\
10098 -mnaked-reg don't require `%%' prefix for registers\n"));
10099 fprintf (stream, _("\
10100 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10101 fprintf (stream, _("\
10102 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10103 fprintf (stream, _("\
10104 -mshared disable branch optimization for shared code\n"));
10105 # if defined (TE_PE) || defined (TE_PEP)
10106 fprintf (stream, _("\
10107 -mbig-obj generate big object files\n"));
10109 fprintf (stream, _("\
10110 -momit-lock-prefix=[no|yes]\n\
10111 strip all lock prefixes\n"));
10112 fprintf (stream, _("\
10113 -mamd64 accept only AMD64 ISA\n"));
10114 fprintf (stream, _("\
10115 -mintel64 accept only Intel64 ISA\n"));
10118 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10119 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10120 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10122 /* Pick the target format to use. */
10125 i386_target_format (void)
10127 if (!strncmp (default_arch, "x86_64", 6))
10129 update_code_flag (CODE_64BIT, 1);
10130 if (default_arch[6] == '\0')
10131 x86_elf_abi = X86_64_ABI;
10133 x86_elf_abi = X86_64_X32_ABI;
10135 else if (!strcmp (default_arch, "i386"))
10136 update_code_flag (CODE_32BIT, 1);
10137 else if (!strcmp (default_arch, "iamcu"))
10139 update_code_flag (CODE_32BIT, 1);
10140 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10142 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10143 cpu_arch_name = "iamcu";
10144 cpu_sub_arch_name = NULL;
10145 cpu_arch_flags = iamcu_flags;
10146 cpu_arch_isa = PROCESSOR_IAMCU;
10147 cpu_arch_isa_flags = iamcu_flags;
10148 if (!cpu_arch_tune_set)
10150 cpu_arch_tune = cpu_arch_isa;
10151 cpu_arch_tune_flags = cpu_arch_isa_flags;
10155 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10159 as_fatal (_("unknown architecture"));
10161 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10162 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10163 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10164 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10166 switch (OUTPUT_FLAVOR)
10168 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10169 case bfd_target_aout_flavour:
10170 return AOUT_TARGET_FORMAT;
10172 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10173 # if defined (TE_PE) || defined (TE_PEP)
10174 case bfd_target_coff_flavour:
10175 if (flag_code == CODE_64BIT)
10176 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10179 # elif defined (TE_GO32)
10180 case bfd_target_coff_flavour:
10181 return "coff-go32";
10183 case bfd_target_coff_flavour:
10184 return "coff-i386";
10187 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10188 case bfd_target_elf_flavour:
10190 const char *format;
10192 switch (x86_elf_abi)
10195 format = ELF_TARGET_FORMAT;
10198 use_rela_relocations = 1;
10200 format = ELF_TARGET_FORMAT64;
10202 case X86_64_X32_ABI:
10203 use_rela_relocations = 1;
10205 disallow_64bit_reloc = 1;
10206 format = ELF_TARGET_FORMAT32;
10209 if (cpu_arch_isa == PROCESSOR_L1OM)
10211 if (x86_elf_abi != X86_64_ABI)
10212 as_fatal (_("Intel L1OM is 64bit only"));
10213 return ELF_TARGET_L1OM_FORMAT;
10215 else if (cpu_arch_isa == PROCESSOR_K1OM)
10217 if (x86_elf_abi != X86_64_ABI)
10218 as_fatal (_("Intel K1OM is 64bit only"));
10219 return ELF_TARGET_K1OM_FORMAT;
10221 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10223 if (x86_elf_abi != I386_ABI)
10224 as_fatal (_("Intel MCU is 32bit only"));
10225 return ELF_TARGET_IAMCU_FORMAT;
10231 #if defined (OBJ_MACH_O)
10232 case bfd_target_mach_o_flavour:
10233 if (flag_code == CODE_64BIT)
10235 use_rela_relocations = 1;
10237 return "mach-o-x86-64";
10240 return "mach-o-i386";
10248 #endif /* OBJ_MAYBE_ more than one */
10251 md_undefined_symbol (char *name)
10253 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10254 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10255 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10256 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10260 if (symbol_find (name))
10261 as_bad (_("GOT already in symbol table"));
10262 GOT_symbol = symbol_new (name, undefined_section,
10263 (valueT) 0, &zero_address_frag);
10270 /* Round up a section size to the appropriate boundary. */
10273 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10275 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10276 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10278 /* For a.out, force the section size to be aligned. If we don't do
10279 this, BFD will align it for us, but it will not write out the
10280 final bytes of the section. This may be a bug in BFD, but it is
10281 easier to fix it here since that is how the other a.out targets
10285 align = bfd_get_section_alignment (stdoutput, segment);
10286 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10293 /* On the i386, PC-relative offsets are relative to the start of the
10294 next instruction. That is, the address of the offset, plus its
10295 size, since the offset is always the last part of the insn. */
10298 md_pcrel_from (fixS *fixP)
10300 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10306 s_bss (int ignore ATTRIBUTE_UNUSED)
10310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10312 obj_elf_section_change_hook ();
10314 temp = get_absolute_expression ();
10315 subseg_set (bss_section, (subsegT) temp);
10316 demand_empty_rest_of_line ();
10322 i386_validate_fix (fixS *fixp)
10324 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10326 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10330 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10335 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10337 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10339 fixp->fx_subsy = 0;
10344 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10347 bfd_reloc_code_real_type code;
10349 switch (fixp->fx_r_type)
10351 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10352 case BFD_RELOC_SIZE32:
10353 case BFD_RELOC_SIZE64:
10354 if (S_IS_DEFINED (fixp->fx_addsy)
10355 && !S_IS_EXTERNAL (fixp->fx_addsy))
10357 /* Resolve size relocation against local symbol to size of
10358 the symbol plus addend. */
10359 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10360 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10361 && !fits_in_unsigned_long (value))
10362 as_bad_where (fixp->fx_file, fixp->fx_line,
10363 _("symbol size computation overflow"));
10364 fixp->fx_addsy = NULL;
10365 fixp->fx_subsy = NULL;
10366 md_apply_fix (fixp, (valueT *) &value, NULL);
10371 case BFD_RELOC_X86_64_PLT32:
10372 case BFD_RELOC_X86_64_GOT32:
10373 case BFD_RELOC_X86_64_GOTPCREL:
10374 case BFD_RELOC_386_PLT32:
10375 case BFD_RELOC_386_GOT32:
10376 case BFD_RELOC_386_GOTOFF:
10377 case BFD_RELOC_386_GOTPC:
10378 case BFD_RELOC_386_TLS_GD:
10379 case BFD_RELOC_386_TLS_LDM:
10380 case BFD_RELOC_386_TLS_LDO_32:
10381 case BFD_RELOC_386_TLS_IE_32:
10382 case BFD_RELOC_386_TLS_IE:
10383 case BFD_RELOC_386_TLS_GOTIE:
10384 case BFD_RELOC_386_TLS_LE_32:
10385 case BFD_RELOC_386_TLS_LE:
10386 case BFD_RELOC_386_TLS_GOTDESC:
10387 case BFD_RELOC_386_TLS_DESC_CALL:
10388 case BFD_RELOC_X86_64_TLSGD:
10389 case BFD_RELOC_X86_64_TLSLD:
10390 case BFD_RELOC_X86_64_DTPOFF32:
10391 case BFD_RELOC_X86_64_DTPOFF64:
10392 case BFD_RELOC_X86_64_GOTTPOFF:
10393 case BFD_RELOC_X86_64_TPOFF32:
10394 case BFD_RELOC_X86_64_TPOFF64:
10395 case BFD_RELOC_X86_64_GOTOFF64:
10396 case BFD_RELOC_X86_64_GOTPC32:
10397 case BFD_RELOC_X86_64_GOT64:
10398 case BFD_RELOC_X86_64_GOTPCREL64:
10399 case BFD_RELOC_X86_64_GOTPC64:
10400 case BFD_RELOC_X86_64_GOTPLT64:
10401 case BFD_RELOC_X86_64_PLTOFF64:
10402 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10403 case BFD_RELOC_X86_64_TLSDESC_CALL:
10404 case BFD_RELOC_RVA:
10405 case BFD_RELOC_VTABLE_ENTRY:
10406 case BFD_RELOC_VTABLE_INHERIT:
10408 case BFD_RELOC_32_SECREL:
10410 code = fixp->fx_r_type;
10412 case BFD_RELOC_X86_64_32S:
10413 if (!fixp->fx_pcrel)
10415 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10416 code = fixp->fx_r_type;
10420 if (fixp->fx_pcrel)
10422 switch (fixp->fx_size)
10425 as_bad_where (fixp->fx_file, fixp->fx_line,
10426 _("can not do %d byte pc-relative relocation"),
10428 code = BFD_RELOC_32_PCREL;
10430 case 1: code = BFD_RELOC_8_PCREL; break;
10431 case 2: code = BFD_RELOC_16_PCREL; break;
10432 case 4: code = BFD_RELOC_32_PCREL; break;
10434 case 8: code = BFD_RELOC_64_PCREL; break;
10440 switch (fixp->fx_size)
10443 as_bad_where (fixp->fx_file, fixp->fx_line,
10444 _("can not do %d byte relocation"),
10446 code = BFD_RELOC_32;
10448 case 1: code = BFD_RELOC_8; break;
10449 case 2: code = BFD_RELOC_16; break;
10450 case 4: code = BFD_RELOC_32; break;
10452 case 8: code = BFD_RELOC_64; break;
10459 if ((code == BFD_RELOC_32
10460 || code == BFD_RELOC_32_PCREL
10461 || code == BFD_RELOC_X86_64_32S)
10463 && fixp->fx_addsy == GOT_symbol)
10466 code = BFD_RELOC_386_GOTPC;
10468 code = BFD_RELOC_X86_64_GOTPC32;
10470 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10472 && fixp->fx_addsy == GOT_symbol)
10474 code = BFD_RELOC_X86_64_GOTPC64;
10477 rel = (arelent *) xmalloc (sizeof (arelent));
10478 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10479 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10481 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10483 if (!use_rela_relocations)
10485 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10486 vtable entry to be used in the relocation's section offset. */
10487 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10488 rel->address = fixp->fx_offset;
10489 #if defined (OBJ_COFF) && defined (TE_PE)
10490 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10491 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10496 /* Use the rela in 64bit mode. */
10499 if (disallow_64bit_reloc)
10502 case BFD_RELOC_X86_64_DTPOFF64:
10503 case BFD_RELOC_X86_64_TPOFF64:
10504 case BFD_RELOC_64_PCREL:
10505 case BFD_RELOC_X86_64_GOTOFF64:
10506 case BFD_RELOC_X86_64_GOT64:
10507 case BFD_RELOC_X86_64_GOTPCREL64:
10508 case BFD_RELOC_X86_64_GOTPC64:
10509 case BFD_RELOC_X86_64_GOTPLT64:
10510 case BFD_RELOC_X86_64_PLTOFF64:
10511 as_bad_where (fixp->fx_file, fixp->fx_line,
10512 _("cannot represent relocation type %s in x32 mode"),
10513 bfd_get_reloc_code_name (code));
10519 if (!fixp->fx_pcrel)
10520 rel->addend = fixp->fx_offset;
10524 case BFD_RELOC_X86_64_PLT32:
10525 case BFD_RELOC_X86_64_GOT32:
10526 case BFD_RELOC_X86_64_GOTPCREL:
10527 case BFD_RELOC_X86_64_TLSGD:
10528 case BFD_RELOC_X86_64_TLSLD:
10529 case BFD_RELOC_X86_64_GOTTPOFF:
10530 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10531 case BFD_RELOC_X86_64_TLSDESC_CALL:
10532 rel->addend = fixp->fx_offset - fixp->fx_size;
10535 rel->addend = (section->vma
10537 + fixp->fx_addnumber
10538 + md_pcrel_from (fixp));
10543 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10544 if (rel->howto == NULL)
10546 as_bad_where (fixp->fx_file, fixp->fx_line,
10547 _("cannot represent relocation type %s"),
10548 bfd_get_reloc_code_name (code));
10549 /* Set howto to a garbage value so that we can keep going. */
10550 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10551 gas_assert (rel->howto != NULL);
10557 #include "tc-i386-intel.c"
10560 tc_x86_parse_to_dw2regnum (expressionS *exp)
10562 int saved_naked_reg;
10563 char saved_register_dot;
10565 saved_naked_reg = allow_naked_reg;
10566 allow_naked_reg = 1;
10567 saved_register_dot = register_chars['.'];
10568 register_chars['.'] = '.';
10569 allow_pseudo_reg = 1;
10570 expression_and_evaluate (exp);
10571 allow_pseudo_reg = 0;
10572 register_chars['.'] = saved_register_dot;
10573 allow_naked_reg = saved_naked_reg;
10575 if (exp->X_op == O_register && exp->X_add_number >= 0)
10577 if ((addressT) exp->X_add_number < i386_regtab_size)
10579 exp->X_op = O_constant;
10580 exp->X_add_number = i386_regtab[exp->X_add_number]
10581 .dw2_regnum[flag_code >> 1];
10584 exp->X_op = O_illegal;
10589 tc_x86_frame_initial_instructions (void)
10591 static unsigned int sp_regno[2];
10593 if (!sp_regno[flag_code >> 1])
10595 char *saved_input = input_line_pointer;
10596 char sp[][4] = {"esp", "rsp"};
10599 input_line_pointer = sp[flag_code >> 1];
10600 tc_x86_parse_to_dw2regnum (&exp);
10601 gas_assert (exp.X_op == O_constant);
10602 sp_regno[flag_code >> 1] = exp.X_add_number;
10603 input_line_pointer = saved_input;
10606 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10607 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10611 x86_dwarf2_addr_size (void)
10613 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10614 if (x86_elf_abi == X86_64_X32_ABI)
10617 return bfd_arch_bits_per_address (stdoutput) / 8;
10621 i386_elf_section_type (const char *str, size_t len)
10623 if (flag_code == CODE_64BIT
10624 && len == sizeof ("unwind") - 1
10625 && strncmp (str, "unwind", 6) == 0)
10626 return SHT_X86_64_UNWIND;
10633 i386_solaris_fix_up_eh_frame (segT sec)
10635 if (flag_code == CODE_64BIT)
10636 elf_section_type (sec) = SHT_X86_64_UNWIND;
10642 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10646 exp.X_op = O_secrel;
10647 exp.X_add_symbol = symbol;
10648 exp.X_add_number = 0;
10649 emit_expr (&exp, size);
10653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10654 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10657 x86_64_section_letter (int letter, char **ptr_msg)
10659 if (flag_code == CODE_64BIT)
10662 return SHF_X86_64_LARGE;
10664 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10667 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10672 x86_64_section_word (char *str, size_t len)
10674 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10675 return SHF_X86_64_LARGE;
10681 handle_large_common (int small ATTRIBUTE_UNUSED)
10683 if (flag_code != CODE_64BIT)
10685 s_comm_internal (0, elf_common_parse);
10686 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10690 static segT lbss_section;
10691 asection *saved_com_section_ptr = elf_com_section_ptr;
10692 asection *saved_bss_section = bss_section;
10694 if (lbss_section == NULL)
10696 flagword applicable;
10697 segT seg = now_seg;
10698 subsegT subseg = now_subseg;
10700 /* The .lbss section is for local .largecomm symbols. */
10701 lbss_section = subseg_new (".lbss", 0);
10702 applicable = bfd_applicable_section_flags (stdoutput);
10703 bfd_set_section_flags (stdoutput, lbss_section,
10704 applicable & SEC_ALLOC);
10705 seg_info (lbss_section)->bss = 1;
10707 subseg_set (seg, subseg);
10710 elf_com_section_ptr = &_bfd_elf_large_com_section;
10711 bss_section = lbss_section;
10713 s_comm_internal (0, elf_common_parse);
10715 elf_com_section_ptr = saved_com_section_ptr;
10716 bss_section = saved_bss_section;
10719 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */