1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 /* Intel Syntax. Use a non-ascii letter since since it never appears
86 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
88 #define END_OF_INSN '\0'
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
99 const insn_template *start;
100 const insn_template *end;
104 /* 386 operand encoding bytes: see 386 book for details of this. */
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
113 /* x86-64 extension prefix. */
114 typedef int rex_byte;
116 /* 386 opcode byte to code indirect addressing. */
125 /* x86 arch names, types and features */
128 const char *name; /* arch name */
129 unsigned int len; /* arch string length */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132 unsigned int skip; /* show_arch should skip this. */
136 /* Used to turn off indicated flags. */
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
145 static void update_code_flag (int, int);
146 static void set_code_flag (int);
147 static void set_16bit_gcc_code_flag (int);
148 static void set_intel_syntax (int);
149 static void set_intel_mnemonic (int);
150 static void set_allow_index_reg (int);
151 static void set_check (int);
152 static void set_cpu_arch (int);
154 static void pe_directive_secrel (int);
156 static void signed_cons (int);
157 static char *output_invalid (int c);
158 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 static int i386_att_operand (char *);
163 static int i386_intel_operand (char *, int);
164 static int i386_intel_simplify (expressionS *);
165 static int i386_intel_parse_name (const char *, expressionS *);
166 static const reg_entry *parse_register (char *, char **);
167 static char *parse_insn (char *, char *);
168 static char *parse_operands (char *, const char *);
169 static void swap_operands (void);
170 static void swap_2_operands (int, int);
171 static void optimize_imm (void);
172 static void optimize_disp (void);
173 static const insn_template *match_template (char);
174 static int check_string (void);
175 static int process_suffix (void);
176 static int check_byte_reg (void);
177 static int check_long_reg (void);
178 static int check_qword_reg (void);
179 static int check_word_reg (void);
180 static int finalize_imm (void);
181 static int process_operands (void);
182 static const seg_entry *build_modrm_byte (void);
183 static void output_insn (void);
184 static void output_imm (fragS *, offsetT);
185 static void output_disp (fragS *, offsetT);
187 static void s_bss (int);
189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190 static void handle_large_common (int small ATTRIBUTE_UNUSED);
192 /* GNU_PROPERTY_X86_ISA_1_USED. */
193 static unsigned int x86_isa_1_used;
194 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
195 static unsigned int x86_feature_2_used;
196 /* Generate x86 used ISA and feature properties. */
197 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
200 static const char *default_arch = DEFAULT_ARCH;
202 /* This struct describes rounding control and SAE in the instruction. */
216 static struct RC_Operation rc_op;
218 /* The struct describes masking, applied to OPERAND in the instruction.
219 MASK is a pointer to the corresponding mask register. ZEROING tells
220 whether merging or zeroing mask is used. */
221 struct Mask_Operation
223 const reg_entry *mask;
224 unsigned int zeroing;
225 /* The operand where this operation is associated. */
229 static struct Mask_Operation mask_op;
231 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
233 struct Broadcast_Operation
235 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
238 /* Index of broadcasted operand. */
241 /* Number of bytes to broadcast. */
245 static struct Broadcast_Operation broadcast_op;
250 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
251 unsigned char bytes[4];
253 /* Destination or source register specifier. */
254 const reg_entry *register_specifier;
257 /* 'md_assemble ()' gathers together information and puts it into a
264 const reg_entry *regs;
269 operand_size_mismatch,
270 operand_type_mismatch,
271 register_type_mismatch,
272 number_of_operands_mismatch,
273 invalid_instruction_suffix,
275 unsupported_with_intel_mnemonic,
278 invalid_vsib_address,
279 invalid_vector_register_set,
280 unsupported_vector_index_register,
281 unsupported_broadcast,
284 mask_not_on_destination,
287 rc_sae_operand_not_last_imm,
288 invalid_register_operand,
293 /* TM holds the template for the insn were currently assembling. */
296 /* SUFFIX holds the instruction size suffix for byte, word, dword
297 or qword, if given. */
300 /* OPERANDS gives the number of given operands. */
301 unsigned int operands;
303 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
304 of given register, displacement, memory operands and immediate
306 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
308 /* TYPES [i] is the type (see above #defines) which tells us how to
309 use OP[i] for the corresponding operand. */
310 i386_operand_type types[MAX_OPERANDS];
312 /* Displacement expression, immediate expression, or register for each
314 union i386_op op[MAX_OPERANDS];
316 /* Flags for operands. */
317 unsigned int flags[MAX_OPERANDS];
318 #define Operand_PCrel 1
319 #define Operand_Mem 2
321 /* Relocation type for operand */
322 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
324 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
325 the base index byte below. */
326 const reg_entry *base_reg;
327 const reg_entry *index_reg;
328 unsigned int log2_scale_factor;
330 /* SEG gives the seg_entries of this insn. They are zero unless
331 explicit segment overrides are given. */
332 const seg_entry *seg[2];
334 /* Copied first memory operand string, for re-checking. */
337 /* PREFIX holds all the given prefix opcodes (usually null).
338 PREFIXES is the number of prefix opcodes. */
339 unsigned int prefixes;
340 unsigned char prefix[MAX_PREFIXES];
342 /* Has MMX register operands. */
343 bfd_boolean has_regmmx;
345 /* Has XMM register operands. */
346 bfd_boolean has_regxmm;
348 /* Has YMM register operands. */
349 bfd_boolean has_regymm;
351 /* Has ZMM register operands. */
352 bfd_boolean has_regzmm;
354 /* RM and SIB are the modrm byte and the sib byte where the
355 addressing modes of this insn are encoded. */
362 /* Masking attributes. */
363 struct Mask_Operation *mask;
365 /* Rounding control and SAE attributes. */
366 struct RC_Operation *rounding;
368 /* Broadcasting attributes. */
369 struct Broadcast_Operation *broadcast;
371 /* Compressed disp8*N attribute. */
372 unsigned int memshift;
374 /* Prefer load or store in encoding. */
377 dir_encoding_default = 0,
383 /* Prefer 8bit or 32bit displacement in encoding. */
386 disp_encoding_default = 0,
391 /* Prefer the REX byte in encoding. */
392 bfd_boolean rex_encoding;
394 /* Disable instruction size optimization. */
395 bfd_boolean no_optimize;
397 /* How to encode vector instructions. */
400 vex_encoding_default = 0,
407 const char *rep_prefix;
410 const char *hle_prefix;
412 /* Have BND prefix. */
413 const char *bnd_prefix;
415 /* Have NOTRACK prefix. */
416 const char *notrack_prefix;
419 enum i386_error error;
422 typedef struct _i386_insn i386_insn;
424 /* Link RC type with corresponding string, that'll be looked for in
433 static const struct RC_name RC_NamesTable[] =
435 { rne, STRING_COMMA_LEN ("rn-sae") },
436 { rd, STRING_COMMA_LEN ("rd-sae") },
437 { ru, STRING_COMMA_LEN ("ru-sae") },
438 { rz, STRING_COMMA_LEN ("rz-sae") },
439 { saeonly, STRING_COMMA_LEN ("sae") },
442 /* List of chars besides those in app.c:symbol_chars that can start an
443 operand. Used to prevent the scrubber eating vital white-space. */
444 const char extra_symbol_chars[] = "*%-([{}"
453 #if (defined (TE_I386AIX) \
454 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
455 && !defined (TE_GNU) \
456 && !defined (TE_LINUX) \
457 && !defined (TE_NACL) \
458 && !defined (TE_FreeBSD) \
459 && !defined (TE_DragonFly) \
460 && !defined (TE_NetBSD)))
461 /* This array holds the chars that always start a comment. If the
462 pre-processor is disabled, these aren't very useful. The option
463 --divide will remove '/' from this list. */
464 const char *i386_comment_chars = "#/";
465 #define SVR4_COMMENT_CHARS 1
466 #define PREFIX_SEPARATOR '\\'
469 const char *i386_comment_chars = "#";
470 #define PREFIX_SEPARATOR '/'
473 /* This array holds the chars that only start a comment at the beginning of
474 a line. If the line seems to have the form '# 123 filename'
475 .line and .file directives will appear in the pre-processed output.
476 Note that input_file.c hand checks for '#' at the beginning of the
477 first line of the input file. This is because the compiler outputs
478 #NO_APP at the beginning of its output.
479 Also note that comments started like this one will always work if
480 '/' isn't otherwise defined. */
481 const char line_comment_chars[] = "#/";
483 const char line_separator_chars[] = ";";
485 /* Chars that can be used to separate mant from exp in floating point
487 const char EXP_CHARS[] = "eE";
489 /* Chars that mean this number is a floating point constant
492 const char FLT_CHARS[] = "fFdDxX";
494 /* Tables for lexical analysis. */
495 static char mnemonic_chars[256];
496 static char register_chars[256];
497 static char operand_chars[256];
498 static char identifier_chars[256];
499 static char digit_chars[256];
501 /* Lexical macros. */
502 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
503 #define is_operand_char(x) (operand_chars[(unsigned char) x])
504 #define is_register_char(x) (register_chars[(unsigned char) x])
505 #define is_space_char(x) ((x) == ' ')
506 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
507 #define is_digit_char(x) (digit_chars[(unsigned char) x])
509 /* All non-digit non-letter characters that may occur in an operand. */
510 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
512 /* md_assemble() always leaves the strings it's passed unaltered. To
513 effect this we maintain a stack of saved characters that we've smashed
514 with '\0's (indicating end of strings for various sub-fields of the
515 assembler instruction). */
516 static char save_stack[32];
517 static char *save_stack_p;
518 #define END_STRING_AND_SAVE(s) \
519 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
520 #define RESTORE_END_STRING(s) \
521 do { *(s) = *--save_stack_p; } while (0)
523 /* The instruction we're assembling. */
526 /* Possible templates for current insn. */
527 static const templates *current_templates;
529 /* Per instruction expressionS buffers: max displacements & immediates. */
530 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
531 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
533 /* Current operand we are working on. */
534 static int this_operand = -1;
536 /* We support four different modes. FLAG_CODE variable is used to distinguish
544 static enum flag_code flag_code;
545 static unsigned int object_64bit;
546 static unsigned int disallow_64bit_reloc;
547 static int use_rela_relocations = 0;
549 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
550 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
551 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
553 /* The ELF ABI to use. */
561 static enum x86_elf_abi x86_elf_abi = I386_ABI;
564 #if defined (TE_PE) || defined (TE_PEP)
565 /* Use big object file format. */
566 static int use_big_obj = 0;
569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570 /* 1 if generating code for a shared library. */
571 static int shared = 0;
574 /* 1 for intel syntax,
576 static int intel_syntax = 0;
578 /* 1 for Intel64 ISA,
582 /* 1 for intel mnemonic,
583 0 if att mnemonic. */
584 static int intel_mnemonic = !SYSV386_COMPAT;
586 /* 1 if pseudo registers are permitted. */
587 static int allow_pseudo_reg = 0;
589 /* 1 if register prefix % not required. */
590 static int allow_naked_reg = 0;
592 /* 1 if the assembler should add BND prefix for all control-transferring
593 instructions supporting it, even if this prefix wasn't specified
595 static int add_bnd_prefix = 0;
597 /* 1 if pseudo index register, eiz/riz, is allowed . */
598 static int allow_index_reg = 0;
600 /* 1 if the assembler should ignore LOCK prefix, even if it was
601 specified explicitly. */
602 static int omit_lock_prefix = 0;
604 /* 1 if the assembler should encode lfence, mfence, and sfence as
605 "lock addl $0, (%{re}sp)". */
606 static int avoid_fence = 0;
608 /* 1 if the assembler should generate relax relocations. */
610 static int generate_relax_relocations
611 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
613 static enum check_kind
619 sse_check, operand_check = check_warning;
622 1. Clear the REX_W bit with register operand if possible.
623 2. Above plus use 128bit vector instruction to clear the full vector
626 static int optimize = 0;
629 1. Clear the REX_W bit with register operand if possible.
630 2. Above plus use 128bit vector instruction to clear the full vector
632 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
635 static int optimize_for_space = 0;
637 /* Register prefix used for error message. */
638 static const char *register_prefix = "%";
640 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
641 leave, push, and pop instructions so that gcc has the same stack
642 frame as in 32 bit mode. */
643 static char stackop_size = '\0';
645 /* Non-zero to optimize code alignment. */
646 int optimize_align_code = 1;
648 /* Non-zero to quieten some warnings. */
649 static int quiet_warnings = 0;
652 static const char *cpu_arch_name = NULL;
653 static char *cpu_sub_arch_name = NULL;
655 /* CPU feature flags. */
656 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
658 /* If we have selected a cpu we are generating instructions for. */
659 static int cpu_arch_tune_set = 0;
661 /* Cpu we are generating instructions for. */
662 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
664 /* CPU feature flags of cpu we are generating instructions for. */
665 static i386_cpu_flags cpu_arch_tune_flags;
667 /* CPU instruction set architecture used. */
668 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
670 /* CPU feature flags of instruction set architecture used. */
671 i386_cpu_flags cpu_arch_isa_flags;
673 /* If set, conditional jumps are not automatically promoted to handle
674 larger than a byte offset. */
675 static unsigned int no_cond_jump_promotion = 0;
677 /* Encode SSE instructions with VEX prefix. */
678 static unsigned int sse2avx;
680 /* Encode scalar AVX instructions with specific vector length. */
687 /* Encode VEX WIG instructions with specific vex.w. */
694 /* Encode scalar EVEX LIG instructions with specific vector length. */
702 /* Encode EVEX WIG instructions with specific evex.w. */
709 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
710 static enum rc_type evexrcig = rne;
712 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
713 static symbolS *GOT_symbol;
715 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
716 unsigned int x86_dwarf2_return_column;
718 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
719 int x86_cie_data_alignment;
721 /* Interface to relax_segment.
722 There are 3 major relax states for 386 jump insns because the
723 different types of jumps add different sizes to frags when we're
724 figuring out what sort of jump to choose to reach a given label. */
727 #define UNCOND_JUMP 0
729 #define COND_JUMP86 2
734 #define SMALL16 (SMALL | CODE16)
736 #define BIG16 (BIG | CODE16)
740 #define INLINE __inline__
746 #define ENCODE_RELAX_STATE(type, size) \
747 ((relax_substateT) (((type) << 2) | (size)))
748 #define TYPE_FROM_RELAX_STATE(s) \
750 #define DISP_SIZE_FROM_RELAX_STATE(s) \
751 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
753 /* This table is used by relax_frag to promote short jumps to long
754 ones where necessary. SMALL (short) jumps may be promoted to BIG
755 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
756 don't allow a short jump in a 32 bit code segment to be promoted to
757 a 16 bit offset jump because it's slower (requires data size
758 prefix), and doesn't work, unless the destination is in the bottom
759 64k of the code segment (The top 16 bits of eip are zeroed). */
761 const relax_typeS md_relax_table[] =
764 1) most positive reach of this state,
765 2) most negative reach of this state,
766 3) how many bytes this mode will have in the variable part of the frag
767 4) which index into the table to try if we can't fit into this one. */
769 /* UNCOND_JUMP states. */
770 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
771 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
772 /* dword jmp adds 4 bytes to frag:
773 0 extra opcode bytes, 4 displacement bytes. */
775 /* word jmp adds 2 byte2 to frag:
776 0 extra opcode bytes, 2 displacement bytes. */
779 /* COND_JUMP states. */
780 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
781 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
782 /* dword conditionals adds 5 bytes to frag:
783 1 extra opcode byte, 4 displacement bytes. */
785 /* word conditionals add 3 bytes to frag:
786 1 extra opcode byte, 2 displacement bytes. */
789 /* COND_JUMP86 states. */
790 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
791 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
792 /* dword conditionals adds 5 bytes to frag:
793 1 extra opcode byte, 4 displacement bytes. */
795 /* word conditionals add 4 bytes to frag:
796 1 displacement byte and a 3 byte long branch insn. */
800 static const arch_entry cpu_arch[] =
802 /* Do not replace the first two entries - i386_target_format()
803 relies on them being there in this order. */
804 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
805 CPU_GENERIC32_FLAGS, 0 },
806 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
807 CPU_GENERIC64_FLAGS, 0 },
808 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
810 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
812 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
814 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
816 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
818 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
820 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
822 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
824 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
825 CPU_PENTIUMPRO_FLAGS, 0 },
826 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
828 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
830 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
832 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
834 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
835 CPU_NOCONA_FLAGS, 0 },
836 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
838 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
840 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
841 CPU_CORE2_FLAGS, 1 },
842 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
843 CPU_CORE2_FLAGS, 0 },
844 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
845 CPU_COREI7_FLAGS, 0 },
846 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
848 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
850 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
851 CPU_IAMCU_FLAGS, 0 },
852 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
854 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
856 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
857 CPU_ATHLON_FLAGS, 0 },
858 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
860 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
862 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
864 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
865 CPU_AMDFAM10_FLAGS, 0 },
866 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
867 CPU_BDVER1_FLAGS, 0 },
868 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
869 CPU_BDVER2_FLAGS, 0 },
870 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
871 CPU_BDVER3_FLAGS, 0 },
872 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
873 CPU_BDVER4_FLAGS, 0 },
874 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
875 CPU_ZNVER1_FLAGS, 0 },
876 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
877 CPU_ZNVER2_FLAGS, 0 },
878 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
879 CPU_BTVER1_FLAGS, 0 },
880 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
881 CPU_BTVER2_FLAGS, 0 },
882 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
886 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
888 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
890 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
892 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
894 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
896 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
903 CPU_SSSE3_FLAGS, 0 },
904 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
905 CPU_SSE4_1_FLAGS, 0 },
906 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
907 CPU_SSE4_2_FLAGS, 0 },
908 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
909 CPU_SSE4_2_FLAGS, 0 },
910 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
912 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
914 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
915 CPU_AVX512F_FLAGS, 0 },
916 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
917 CPU_AVX512CD_FLAGS, 0 },
918 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
919 CPU_AVX512ER_FLAGS, 0 },
920 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
921 CPU_AVX512PF_FLAGS, 0 },
922 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
923 CPU_AVX512DQ_FLAGS, 0 },
924 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
925 CPU_AVX512BW_FLAGS, 0 },
926 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
927 CPU_AVX512VL_FLAGS, 0 },
928 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
930 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
931 CPU_VMFUNC_FLAGS, 0 },
932 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
934 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
935 CPU_XSAVE_FLAGS, 0 },
936 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
937 CPU_XSAVEOPT_FLAGS, 0 },
938 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
939 CPU_XSAVEC_FLAGS, 0 },
940 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
941 CPU_XSAVES_FLAGS, 0 },
942 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
944 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
945 CPU_PCLMUL_FLAGS, 0 },
946 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
947 CPU_PCLMUL_FLAGS, 1 },
948 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
949 CPU_FSGSBASE_FLAGS, 0 },
950 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
951 CPU_RDRND_FLAGS, 0 },
952 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
956 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
958 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
960 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
965 CPU_MOVBE_FLAGS, 0 },
966 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
971 CPU_LZCNT_FLAGS, 0 },
972 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
977 CPU_INVPCID_FLAGS, 0 },
978 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
979 CPU_CLFLUSH_FLAGS, 0 },
980 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
983 CPU_SYSCALL_FLAGS, 0 },
984 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
985 CPU_RDTSCP_FLAGS, 0 },
986 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
987 CPU_3DNOW_FLAGS, 0 },
988 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
989 CPU_3DNOWA_FLAGS, 0 },
990 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
991 CPU_PADLOCK_FLAGS, 0 },
992 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
994 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
997 CPU_SSE4A_FLAGS, 0 },
998 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
1000 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
1002 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
1004 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
1006 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1007 CPU_RDSEED_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1009 CPU_PRFCHW_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1011 CPU_SMAP_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1014 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1016 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1017 CPU_CLFLUSHOPT_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1019 CPU_PREFETCHWT1_FLAGS, 0 },
1020 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1022 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1023 CPU_CLWB_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1025 CPU_AVX512IFMA_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1027 CPU_AVX512VBMI_FLAGS, 0 },
1028 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1029 CPU_AVX512_4FMAPS_FLAGS, 0 },
1030 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1031 CPU_AVX512_4VNNIW_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1033 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1035 CPU_AVX512_VBMI2_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1037 CPU_AVX512_VNNI_FLAGS, 0 },
1038 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1039 CPU_AVX512_BITALG_FLAGS, 0 },
1040 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1041 CPU_CLZERO_FLAGS, 0 },
1042 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1043 CPU_MWAITX_FLAGS, 0 },
1044 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1045 CPU_OSPKE_FLAGS, 0 },
1046 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1047 CPU_RDPID_FLAGS, 0 },
1048 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1049 CPU_PTWRITE_FLAGS, 0 },
1050 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1052 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1053 CPU_SHSTK_FLAGS, 0 },
1054 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1055 CPU_GFNI_FLAGS, 0 },
1056 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1057 CPU_VAES_FLAGS, 0 },
1058 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1059 CPU_VPCLMULQDQ_FLAGS, 0 },
1060 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1061 CPU_WBNOINVD_FLAGS, 0 },
1062 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1063 CPU_PCONFIG_FLAGS, 0 },
1064 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1065 CPU_WAITPKG_FLAGS, 0 },
1066 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1067 CPU_CLDEMOTE_FLAGS, 0 },
1068 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1069 CPU_MOVDIRI_FLAGS, 0 },
1070 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1071 CPU_MOVDIR64B_FLAGS, 0 },
1074 static const noarch_entry cpu_noarch[] =
1076 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1077 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1078 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1079 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1080 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1081 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1082 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1083 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1084 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1085 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1086 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1087 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1088 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1089 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1090 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1091 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1092 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1093 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1094 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1095 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1096 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1097 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1098 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1099 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1100 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1101 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1102 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1103 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1104 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1105 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1106 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1107 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1108 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1109 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1110 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1114 /* Like s_lcomm_internal in gas/read.c but the alignment string
1115 is allowed to be optional. */
1118 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1125 && *input_line_pointer == ',')
1127 align = parse_align (needs_align - 1);
1129 if (align == (addressT) -1)
1144 bss_alloc (symbolP, size, align);
1149 pe_lcomm (int needs_align)
1151 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1155 const pseudo_typeS md_pseudo_table[] =
1157 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1158 {"align", s_align_bytes, 0},
1160 {"align", s_align_ptwo, 0},
1162 {"arch", set_cpu_arch, 0},
1166 {"lcomm", pe_lcomm, 1},
1168 {"ffloat", float_cons, 'f'},
1169 {"dfloat", float_cons, 'd'},
1170 {"tfloat", float_cons, 'x'},
1172 {"slong", signed_cons, 4},
1173 {"noopt", s_ignore, 0},
1174 {"optim", s_ignore, 0},
1175 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1176 {"code16", set_code_flag, CODE_16BIT},
1177 {"code32", set_code_flag, CODE_32BIT},
1179 {"code64", set_code_flag, CODE_64BIT},
1181 {"intel_syntax", set_intel_syntax, 1},
1182 {"att_syntax", set_intel_syntax, 0},
1183 {"intel_mnemonic", set_intel_mnemonic, 1},
1184 {"att_mnemonic", set_intel_mnemonic, 0},
1185 {"allow_index_reg", set_allow_index_reg, 1},
1186 {"disallow_index_reg", set_allow_index_reg, 0},
1187 {"sse_check", set_check, 0},
1188 {"operand_check", set_check, 1},
1189 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1190 {"largecomm", handle_large_common, 0},
1192 {"file", dwarf2_directive_file, 0},
1193 {"loc", dwarf2_directive_loc, 0},
1194 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1197 {"secrel32", pe_directive_secrel, 0},
1202 /* For interface with expression (). */
1203 extern char *input_line_pointer;
1205 /* Hash table for instruction mnemonic lookup. */
1206 static struct hash_control *op_hash;
1208 /* Hash table for register lookup. */
1209 static struct hash_control *reg_hash;
1211 /* Various efficient no-op patterns for aligning code labels.
1212 Note: Don't try to assemble the instructions in the comments.
1213 0L and 0w are not legal. */
1214 static const unsigned char f32_1[] =
1216 static const unsigned char f32_2[] =
1217 {0x66,0x90}; /* xchg %ax,%ax */
1218 static const unsigned char f32_3[] =
1219 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1220 static const unsigned char f32_4[] =
1221 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1222 static const unsigned char f32_6[] =
1223 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1224 static const unsigned char f32_7[] =
1225 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1226 static const unsigned char f16_3[] =
1227 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1228 static const unsigned char f16_4[] =
1229 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1230 static const unsigned char jump_disp8[] =
1231 {0xeb}; /* jmp disp8 */
1232 static const unsigned char jump32_disp32[] =
1233 {0xe9}; /* jmp disp32 */
1234 static const unsigned char jump16_disp32[] =
1235 {0x66,0xe9}; /* jmp disp32 */
1236 /* 32-bit NOPs patterns. */
1237 static const unsigned char *const f32_patt[] = {
1238 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1240 /* 16-bit NOPs patterns. */
1241 static const unsigned char *const f16_patt[] = {
1242 f32_1, f32_2, f16_3, f16_4
1244 /* nopl (%[re]ax) */
1245 static const unsigned char alt_3[] =
1247 /* nopl 0(%[re]ax) */
1248 static const unsigned char alt_4[] =
1249 {0x0f,0x1f,0x40,0x00};
1250 /* nopl 0(%[re]ax,%[re]ax,1) */
1251 static const unsigned char alt_5[] =
1252 {0x0f,0x1f,0x44,0x00,0x00};
1253 /* nopw 0(%[re]ax,%[re]ax,1) */
1254 static const unsigned char alt_6[] =
1255 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1256 /* nopl 0L(%[re]ax) */
1257 static const unsigned char alt_7[] =
1258 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1259 /* nopl 0L(%[re]ax,%[re]ax,1) */
1260 static const unsigned char alt_8[] =
1261 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1262 /* nopw 0L(%[re]ax,%[re]ax,1) */
1263 static const unsigned char alt_9[] =
1264 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1265 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1266 static const unsigned char alt_10[] =
1267 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1268 /* data16 nopw %cs:0L(%eax,%eax,1) */
1269 static const unsigned char alt_11[] =
1270 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1271 /* 32-bit and 64-bit NOPs patterns. */
1272 static const unsigned char *const alt_patt[] = {
1273 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1274 alt_9, alt_10, alt_11
1277 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1278 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1281 i386_output_nops (char *where, const unsigned char *const *patt,
1282 int count, int max_single_nop_size)
1285 /* Place the longer NOP first. */
1288 const unsigned char *nops = patt[max_single_nop_size - 1];
1290 /* Use the smaller one if the requsted one isn't available. */
1293 max_single_nop_size--;
1294 nops = patt[max_single_nop_size - 1];
1297 last = count % max_single_nop_size;
1300 for (offset = 0; offset < count; offset += max_single_nop_size)
1301 memcpy (where + offset, nops, max_single_nop_size);
1305 nops = patt[last - 1];
1308 /* Use the smaller one plus one-byte NOP if the needed one
1311 nops = patt[last - 1];
1312 memcpy (where + offset, nops, last);
1313 where[offset + last] = *patt[0];
1316 memcpy (where + offset, nops, last);
1321 fits_in_imm7 (offsetT num)
1323 return (num & 0x7f) == num;
1327 fits_in_imm31 (offsetT num)
1329 return (num & 0x7fffffff) == num;
1332 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1333 single NOP instruction LIMIT. */
1336 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1338 const unsigned char *const *patt = NULL;
1339 int max_single_nop_size;
1340 /* Maximum number of NOPs before switching to jump over NOPs. */
1341 int max_number_of_nops;
1343 switch (fragP->fr_type)
1352 /* We need to decide which NOP sequence to use for 32bit and
1353 64bit. When -mtune= is used:
1355 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1356 PROCESSOR_GENERIC32, f32_patt will be used.
1357 2. For the rest, alt_patt will be used.
1359 When -mtune= isn't used, alt_patt will be used if
1360 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1363 When -march= or .arch is used, we can't use anything beyond
1364 cpu_arch_isa_flags. */
1366 if (flag_code == CODE_16BIT)
1369 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1370 /* Limit number of NOPs to 2 in 16-bit mode. */
1371 max_number_of_nops = 2;
1375 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1377 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1378 switch (cpu_arch_tune)
1380 case PROCESSOR_UNKNOWN:
1381 /* We use cpu_arch_isa_flags to check if we SHOULD
1382 optimize with nops. */
1383 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1388 case PROCESSOR_PENTIUM4:
1389 case PROCESSOR_NOCONA:
1390 case PROCESSOR_CORE:
1391 case PROCESSOR_CORE2:
1392 case PROCESSOR_COREI7:
1393 case PROCESSOR_L1OM:
1394 case PROCESSOR_K1OM:
1395 case PROCESSOR_GENERIC64:
1397 case PROCESSOR_ATHLON:
1399 case PROCESSOR_AMDFAM10:
1401 case PROCESSOR_ZNVER:
1405 case PROCESSOR_I386:
1406 case PROCESSOR_I486:
1407 case PROCESSOR_PENTIUM:
1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_IAMCU:
1410 case PROCESSOR_GENERIC32:
1417 switch (fragP->tc_frag_data.tune)
1419 case PROCESSOR_UNKNOWN:
1420 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1421 PROCESSOR_UNKNOWN. */
1425 case PROCESSOR_I386:
1426 case PROCESSOR_I486:
1427 case PROCESSOR_PENTIUM:
1428 case PROCESSOR_IAMCU:
1430 case PROCESSOR_ATHLON:
1432 case PROCESSOR_AMDFAM10:
1434 case PROCESSOR_ZNVER:
1436 case PROCESSOR_GENERIC32:
1437 /* We use cpu_arch_isa_flags to check if we CAN optimize
1439 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1444 case PROCESSOR_PENTIUMPRO:
1445 case PROCESSOR_PENTIUM4:
1446 case PROCESSOR_NOCONA:
1447 case PROCESSOR_CORE:
1448 case PROCESSOR_CORE2:
1449 case PROCESSOR_COREI7:
1450 case PROCESSOR_L1OM:
1451 case PROCESSOR_K1OM:
1452 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1457 case PROCESSOR_GENERIC64:
1463 if (patt == f32_patt)
1465 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1466 /* Limit number of NOPs to 2 for older processors. */
1467 max_number_of_nops = 2;
1471 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1472 /* Limit number of NOPs to 7 for newer processors. */
1473 max_number_of_nops = 7;
1478 limit = max_single_nop_size;
1480 if (fragP->fr_type == rs_fill_nop)
1482 /* Output NOPs for .nop directive. */
1483 if (limit > max_single_nop_size)
1485 as_bad_where (fragP->fr_file, fragP->fr_line,
1486 _("invalid single nop size: %d "
1487 "(expect within [0, %d])"),
1488 limit, max_single_nop_size);
1493 fragP->fr_var = count;
1495 if ((count / max_single_nop_size) > max_number_of_nops)
1497 /* Generate jump over NOPs. */
1498 offsetT disp = count - 2;
1499 if (fits_in_imm7 (disp))
1501 /* Use "jmp disp8" if possible. */
1503 where[0] = jump_disp8[0];
1509 unsigned int size_of_jump;
1511 if (flag_code == CODE_16BIT)
1513 where[0] = jump16_disp32[0];
1514 where[1] = jump16_disp32[1];
1519 where[0] = jump32_disp32[0];
1523 count -= size_of_jump + 4;
1524 if (!fits_in_imm31 (count))
1526 as_bad_where (fragP->fr_file, fragP->fr_line,
1527 _("jump over nop padding out of range"));
1531 md_number_to_chars (where + size_of_jump, count, 4);
1532 where += size_of_jump + 4;
1536 /* Generate multiple NOPs. */
1537 i386_output_nops (where, patt, count, limit);
1541 operand_type_all_zero (const union i386_operand_type *x)
1543 switch (ARRAY_SIZE(x->array))
1554 return !x->array[0];
1561 operand_type_set (union i386_operand_type *x, unsigned int v)
1563 switch (ARRAY_SIZE(x->array))
1581 operand_type_equal (const union i386_operand_type *x,
1582 const union i386_operand_type *y)
1584 switch (ARRAY_SIZE(x->array))
1587 if (x->array[2] != y->array[2])
1591 if (x->array[1] != y->array[1])
1595 return x->array[0] == y->array[0];
1603 cpu_flags_all_zero (const union i386_cpu_flags *x)
1605 switch (ARRAY_SIZE(x->array))
1620 return !x->array[0];
1627 cpu_flags_equal (const union i386_cpu_flags *x,
1628 const union i386_cpu_flags *y)
1630 switch (ARRAY_SIZE(x->array))
1633 if (x->array[3] != y->array[3])
1637 if (x->array[2] != y->array[2])
1641 if (x->array[1] != y->array[1])
1645 return x->array[0] == y->array[0];
1653 cpu_flags_check_cpu64 (i386_cpu_flags f)
1655 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1656 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1659 static INLINE i386_cpu_flags
1660 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1662 switch (ARRAY_SIZE (x.array))
1665 x.array [3] &= y.array [3];
1668 x.array [2] &= y.array [2];
1671 x.array [1] &= y.array [1];
1674 x.array [0] &= y.array [0];
1682 static INLINE i386_cpu_flags
1683 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1685 switch (ARRAY_SIZE (x.array))
1688 x.array [3] |= y.array [3];
1691 x.array [2] |= y.array [2];
1694 x.array [1] |= y.array [1];
1697 x.array [0] |= y.array [0];
1705 static INLINE i386_cpu_flags
1706 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1708 switch (ARRAY_SIZE (x.array))
1711 x.array [3] &= ~y.array [3];
1714 x.array [2] &= ~y.array [2];
1717 x.array [1] &= ~y.array [1];
1720 x.array [0] &= ~y.array [0];
1728 #define CPU_FLAGS_ARCH_MATCH 0x1
1729 #define CPU_FLAGS_64BIT_MATCH 0x2
1731 #define CPU_FLAGS_PERFECT_MATCH \
1732 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1734 /* Return CPU flags match bits. */
1737 cpu_flags_match (const insn_template *t)
1739 i386_cpu_flags x = t->cpu_flags;
1740 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1742 x.bitfield.cpu64 = 0;
1743 x.bitfield.cpuno64 = 0;
1745 if (cpu_flags_all_zero (&x))
1747 /* This instruction is available on all archs. */
1748 match |= CPU_FLAGS_ARCH_MATCH;
1752 /* This instruction is available only on some archs. */
1753 i386_cpu_flags cpu = cpu_arch_flags;
1755 /* AVX512VL is no standalone feature - match it and then strip it. */
1756 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1758 x.bitfield.cpuavx512vl = 0;
1760 cpu = cpu_flags_and (x, cpu);
1761 if (!cpu_flags_all_zero (&cpu))
1763 if (x.bitfield.cpuavx)
1765 /* We need to check a few extra flags with AVX. */
1766 if (cpu.bitfield.cpuavx
1767 && (!t->opcode_modifier.sse2avx || sse2avx)
1768 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1769 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1770 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1771 match |= CPU_FLAGS_ARCH_MATCH;
1773 else if (x.bitfield.cpuavx512f)
1775 /* We need to check a few extra flags with AVX512F. */
1776 if (cpu.bitfield.cpuavx512f
1777 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1778 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1779 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1780 match |= CPU_FLAGS_ARCH_MATCH;
1783 match |= CPU_FLAGS_ARCH_MATCH;
1789 static INLINE i386_operand_type
1790 operand_type_and (i386_operand_type x, i386_operand_type y)
1792 switch (ARRAY_SIZE (x.array))
1795 x.array [2] &= y.array [2];
1798 x.array [1] &= y.array [1];
1801 x.array [0] &= y.array [0];
1809 static INLINE i386_operand_type
1810 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1812 switch (ARRAY_SIZE (x.array))
1815 x.array [2] &= ~y.array [2];
1818 x.array [1] &= ~y.array [1];
1821 x.array [0] &= ~y.array [0];
1829 static INLINE i386_operand_type
1830 operand_type_or (i386_operand_type x, i386_operand_type y)
1832 switch (ARRAY_SIZE (x.array))
1835 x.array [2] |= y.array [2];
1838 x.array [1] |= y.array [1];
1841 x.array [0] |= y.array [0];
1849 static INLINE i386_operand_type
1850 operand_type_xor (i386_operand_type x, i386_operand_type y)
1852 switch (ARRAY_SIZE (x.array))
1855 x.array [2] ^= y.array [2];
1858 x.array [1] ^= y.array [1];
1861 x.array [0] ^= y.array [0];
1869 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1870 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1871 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1872 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1873 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1874 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1875 static const i386_operand_type anydisp
1876 = OPERAND_TYPE_ANYDISP;
1877 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1878 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1879 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1880 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1881 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1882 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1883 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1884 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1885 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1886 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1887 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1888 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1899 operand_type_check (i386_operand_type t, enum operand_type c)
1904 return t.bitfield.reg;
1907 return (t.bitfield.imm8
1911 || t.bitfield.imm32s
1912 || t.bitfield.imm64);
1915 return (t.bitfield.disp8
1916 || t.bitfield.disp16
1917 || t.bitfield.disp32
1918 || t.bitfield.disp32s
1919 || t.bitfield.disp64);
1922 return (t.bitfield.disp8
1923 || t.bitfield.disp16
1924 || t.bitfield.disp32
1925 || t.bitfield.disp32s
1926 || t.bitfield.disp64
1927 || t.bitfield.baseindex);
1936 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1937 between operand GIVEN and opeand WANTED for instruction template T. */
1940 match_operand_size (const insn_template *t, unsigned int wanted,
1943 return !((i.types[given].bitfield.byte
1944 && !t->operand_types[wanted].bitfield.byte)
1945 || (i.types[given].bitfield.word
1946 && !t->operand_types[wanted].bitfield.word)
1947 || (i.types[given].bitfield.dword
1948 && !t->operand_types[wanted].bitfield.dword)
1949 || (i.types[given].bitfield.qword
1950 && !t->operand_types[wanted].bitfield.qword)
1951 || (i.types[given].bitfield.tbyte
1952 && !t->operand_types[wanted].bitfield.tbyte));
1955 /* Return 1 if there is no conflict in SIMD register between operand
1956 GIVEN and opeand WANTED for instruction template T. */
1959 match_simd_size (const insn_template *t, unsigned int wanted,
1962 return !((i.types[given].bitfield.xmmword
1963 && !t->operand_types[wanted].bitfield.xmmword)
1964 || (i.types[given].bitfield.ymmword
1965 && !t->operand_types[wanted].bitfield.ymmword)
1966 || (i.types[given].bitfield.zmmword
1967 && !t->operand_types[wanted].bitfield.zmmword));
1970 /* Return 1 if there is no conflict in any size between operand GIVEN
1971 and opeand WANTED for instruction template T. */
1974 match_mem_size (const insn_template *t, unsigned int wanted,
1977 return (match_operand_size (t, wanted, given)
1978 && !((i.types[given].bitfield.unspecified
1980 && !t->operand_types[wanted].bitfield.unspecified)
1981 || (i.types[given].bitfield.fword
1982 && !t->operand_types[wanted].bitfield.fword)
1983 /* For scalar opcode templates to allow register and memory
1984 operands at the same time, some special casing is needed
1985 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1986 down-conversion vpmov*. */
1987 || ((t->operand_types[wanted].bitfield.regsimd
1988 && !t->opcode_modifier.broadcast
1989 && (t->operand_types[wanted].bitfield.byte
1990 || t->operand_types[wanted].bitfield.word
1991 || t->operand_types[wanted].bitfield.dword
1992 || t->operand_types[wanted].bitfield.qword))
1993 ? (i.types[given].bitfield.xmmword
1994 || i.types[given].bitfield.ymmword
1995 || i.types[given].bitfield.zmmword)
1996 : !match_simd_size(t, wanted, given))));
1999 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2000 operands for instruction template T, and it has MATCH_REVERSE set if there
2001 is no size conflict on any operands for the template with operands reversed
2002 (and the template allows for reversing in the first place). */
2004 #define MATCH_STRAIGHT 1
2005 #define MATCH_REVERSE 2
2007 static INLINE unsigned int
2008 operand_size_match (const insn_template *t)
2010 unsigned int j, match = MATCH_STRAIGHT;
2012 /* Don't check jump instructions. */
2013 if (t->opcode_modifier.jump
2014 || t->opcode_modifier.jumpbyte
2015 || t->opcode_modifier.jumpdword
2016 || t->opcode_modifier.jumpintersegment)
2019 /* Check memory and accumulator operand size. */
2020 for (j = 0; j < i.operands; j++)
2022 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2023 && t->operand_types[j].bitfield.anysize)
2026 if (t->operand_types[j].bitfield.reg
2027 && !match_operand_size (t, j, j))
2033 if (t->operand_types[j].bitfield.regsimd
2034 && !match_simd_size (t, j, j))
2040 if (t->operand_types[j].bitfield.acc
2041 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2047 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2054 if (!t->opcode_modifier.d)
2058 i.error = operand_size_mismatch;
2062 /* Check reverse. */
2063 gas_assert (i.operands >= 2 && i.operands <= 3);
2065 for (j = 0; j < i.operands; j++)
2067 unsigned int given = i.operands - j - 1;
2069 if (t->operand_types[j].bitfield.reg
2070 && !match_operand_size (t, j, given))
2073 if (t->operand_types[j].bitfield.regsimd
2074 && !match_simd_size (t, j, given))
2077 if (t->operand_types[j].bitfield.acc
2078 && (!match_operand_size (t, j, given)
2079 || !match_simd_size (t, j, given)))
2082 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2086 return match | MATCH_REVERSE;
2090 operand_type_match (i386_operand_type overlap,
2091 i386_operand_type given)
2093 i386_operand_type temp = overlap;
2095 temp.bitfield.jumpabsolute = 0;
2096 temp.bitfield.unspecified = 0;
2097 temp.bitfield.byte = 0;
2098 temp.bitfield.word = 0;
2099 temp.bitfield.dword = 0;
2100 temp.bitfield.fword = 0;
2101 temp.bitfield.qword = 0;
2102 temp.bitfield.tbyte = 0;
2103 temp.bitfield.xmmword = 0;
2104 temp.bitfield.ymmword = 0;
2105 temp.bitfield.zmmword = 0;
2106 if (operand_type_all_zero (&temp))
2109 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2110 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2114 i.error = operand_type_mismatch;
2118 /* If given types g0 and g1 are registers they must be of the same type
2119 unless the expected operand type register overlap is null.
2120 Memory operand size of certain SIMD instructions is also being checked
2124 operand_type_register_match (i386_operand_type g0,
2125 i386_operand_type t0,
2126 i386_operand_type g1,
2127 i386_operand_type t1)
2129 if (!g0.bitfield.reg
2130 && !g0.bitfield.regsimd
2131 && (!operand_type_check (g0, anymem)
2132 || g0.bitfield.unspecified
2133 || !t0.bitfield.regsimd))
2136 if (!g1.bitfield.reg
2137 && !g1.bitfield.regsimd
2138 && (!operand_type_check (g1, anymem)
2139 || g1.bitfield.unspecified
2140 || !t1.bitfield.regsimd))
2143 if (g0.bitfield.byte == g1.bitfield.byte
2144 && g0.bitfield.word == g1.bitfield.word
2145 && g0.bitfield.dword == g1.bitfield.dword
2146 && g0.bitfield.qword == g1.bitfield.qword
2147 && g0.bitfield.xmmword == g1.bitfield.xmmword
2148 && g0.bitfield.ymmword == g1.bitfield.ymmword
2149 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2152 if (!(t0.bitfield.byte & t1.bitfield.byte)
2153 && !(t0.bitfield.word & t1.bitfield.word)
2154 && !(t0.bitfield.dword & t1.bitfield.dword)
2155 && !(t0.bitfield.qword & t1.bitfield.qword)
2156 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2157 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2158 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2161 i.error = register_type_mismatch;
2166 static INLINE unsigned int
2167 register_number (const reg_entry *r)
2169 unsigned int nr = r->reg_num;
2171 if (r->reg_flags & RegRex)
2174 if (r->reg_flags & RegVRex)
2180 static INLINE unsigned int
2181 mode_from_disp_size (i386_operand_type t)
2183 if (t.bitfield.disp8)
2185 else if (t.bitfield.disp16
2186 || t.bitfield.disp32
2187 || t.bitfield.disp32s)
2194 fits_in_signed_byte (addressT num)
2196 return num + 0x80 <= 0xff;
2200 fits_in_unsigned_byte (addressT num)
2206 fits_in_unsigned_word (addressT num)
2208 return num <= 0xffff;
2212 fits_in_signed_word (addressT num)
2214 return num + 0x8000 <= 0xffff;
2218 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2223 return num + 0x80000000 <= 0xffffffff;
2225 } /* fits_in_signed_long() */
2228 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2233 return num <= 0xffffffff;
2235 } /* fits_in_unsigned_long() */
2238 fits_in_disp8 (offsetT num)
2240 int shift = i.memshift;
2246 mask = (1 << shift) - 1;
2248 /* Return 0 if NUM isn't properly aligned. */
2252 /* Check if NUM will fit in 8bit after shift. */
2253 return fits_in_signed_byte (num >> shift);
2257 fits_in_imm4 (offsetT num)
2259 return (num & 0xf) == num;
2262 static i386_operand_type
2263 smallest_imm_type (offsetT num)
2265 i386_operand_type t;
2267 operand_type_set (&t, 0);
2268 t.bitfield.imm64 = 1;
2270 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2272 /* This code is disabled on the 486 because all the Imm1 forms
2273 in the opcode table are slower on the i486. They're the
2274 versions with the implicitly specified single-position
2275 displacement, which has another syntax if you really want to
2277 t.bitfield.imm1 = 1;
2278 t.bitfield.imm8 = 1;
2279 t.bitfield.imm8s = 1;
2280 t.bitfield.imm16 = 1;
2281 t.bitfield.imm32 = 1;
2282 t.bitfield.imm32s = 1;
2284 else if (fits_in_signed_byte (num))
2286 t.bitfield.imm8 = 1;
2287 t.bitfield.imm8s = 1;
2288 t.bitfield.imm16 = 1;
2289 t.bitfield.imm32 = 1;
2290 t.bitfield.imm32s = 1;
2292 else if (fits_in_unsigned_byte (num))
2294 t.bitfield.imm8 = 1;
2295 t.bitfield.imm16 = 1;
2296 t.bitfield.imm32 = 1;
2297 t.bitfield.imm32s = 1;
2299 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2301 t.bitfield.imm16 = 1;
2302 t.bitfield.imm32 = 1;
2303 t.bitfield.imm32s = 1;
2305 else if (fits_in_signed_long (num))
2307 t.bitfield.imm32 = 1;
2308 t.bitfield.imm32s = 1;
2310 else if (fits_in_unsigned_long (num))
2311 t.bitfield.imm32 = 1;
2317 offset_in_range (offsetT val, int size)
2323 case 1: mask = ((addressT) 1 << 8) - 1; break;
2324 case 2: mask = ((addressT) 1 << 16) - 1; break;
2325 case 4: mask = ((addressT) 2 << 31) - 1; break;
2327 case 8: mask = ((addressT) 2 << 63) - 1; break;
2333 /* If BFD64, sign extend val for 32bit address mode. */
2334 if (flag_code != CODE_64BIT
2335 || i.prefix[ADDR_PREFIX])
2336 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2337 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2340 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2342 char buf1[40], buf2[40];
2344 sprint_value (buf1, val);
2345 sprint_value (buf2, val & mask);
2346 as_warn (_("%s shortened to %s"), buf1, buf2);
2361 a. PREFIX_EXIST if attempting to add a prefix where one from the
2362 same class already exists.
2363 b. PREFIX_LOCK if lock prefix is added.
2364 c. PREFIX_REP if rep/repne prefix is added.
2365 d. PREFIX_DS if ds prefix is added.
2366 e. PREFIX_OTHER if other prefix is added.
2369 static enum PREFIX_GROUP
2370 add_prefix (unsigned int prefix)
2372 enum PREFIX_GROUP ret = PREFIX_OTHER;
2375 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2376 && flag_code == CODE_64BIT)
2378 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2379 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2380 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2381 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2392 case DS_PREFIX_OPCODE:
2395 case CS_PREFIX_OPCODE:
2396 case ES_PREFIX_OPCODE:
2397 case FS_PREFIX_OPCODE:
2398 case GS_PREFIX_OPCODE:
2399 case SS_PREFIX_OPCODE:
2403 case REPNE_PREFIX_OPCODE:
2404 case REPE_PREFIX_OPCODE:
2409 case LOCK_PREFIX_OPCODE:
2418 case ADDR_PREFIX_OPCODE:
2422 case DATA_PREFIX_OPCODE:
2426 if (i.prefix[q] != 0)
2434 i.prefix[q] |= prefix;
2437 as_bad (_("same type of prefix used twice"));
2443 update_code_flag (int value, int check)
2445 PRINTF_LIKE ((*as_error));
2447 flag_code = (enum flag_code) value;
2448 if (flag_code == CODE_64BIT)
2450 cpu_arch_flags.bitfield.cpu64 = 1;
2451 cpu_arch_flags.bitfield.cpuno64 = 0;
2455 cpu_arch_flags.bitfield.cpu64 = 0;
2456 cpu_arch_flags.bitfield.cpuno64 = 1;
2458 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2461 as_error = as_fatal;
2464 (*as_error) (_("64bit mode not supported on `%s'."),
2465 cpu_arch_name ? cpu_arch_name : default_arch);
2467 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2470 as_error = as_fatal;
2473 (*as_error) (_("32bit mode not supported on `%s'."),
2474 cpu_arch_name ? cpu_arch_name : default_arch);
2476 stackop_size = '\0';
2480 set_code_flag (int value)
2482 update_code_flag (value, 0);
2486 set_16bit_gcc_code_flag (int new_code_flag)
2488 flag_code = (enum flag_code) new_code_flag;
2489 if (flag_code != CODE_16BIT)
2491 cpu_arch_flags.bitfield.cpu64 = 0;
2492 cpu_arch_flags.bitfield.cpuno64 = 1;
2493 stackop_size = LONG_MNEM_SUFFIX;
2497 set_intel_syntax (int syntax_flag)
2499 /* Find out if register prefixing is specified. */
2500 int ask_naked_reg = 0;
2503 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2506 int e = get_symbol_name (&string);
2508 if (strcmp (string, "prefix") == 0)
2510 else if (strcmp (string, "noprefix") == 0)
2513 as_bad (_("bad argument to syntax directive."));
2514 (void) restore_line_pointer (e);
2516 demand_empty_rest_of_line ();
2518 intel_syntax = syntax_flag;
2520 if (ask_naked_reg == 0)
2521 allow_naked_reg = (intel_syntax
2522 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2524 allow_naked_reg = (ask_naked_reg < 0);
2526 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2528 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2529 identifier_chars['$'] = intel_syntax ? '$' : 0;
2530 register_prefix = allow_naked_reg ? "" : "%";
2534 set_intel_mnemonic (int mnemonic_flag)
2536 intel_mnemonic = mnemonic_flag;
2540 set_allow_index_reg (int flag)
2542 allow_index_reg = flag;
2546 set_check (int what)
2548 enum check_kind *kind;
2553 kind = &operand_check;
2564 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2567 int e = get_symbol_name (&string);
2569 if (strcmp (string, "none") == 0)
2571 else if (strcmp (string, "warning") == 0)
2572 *kind = check_warning;
2573 else if (strcmp (string, "error") == 0)
2574 *kind = check_error;
2576 as_bad (_("bad argument to %s_check directive."), str);
2577 (void) restore_line_pointer (e);
2580 as_bad (_("missing argument for %s_check directive"), str);
2582 demand_empty_rest_of_line ();
2586 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2587 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2589 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2590 static const char *arch;
2592 /* Intel LIOM is only supported on ELF. */
2598 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2599 use default_arch. */
2600 arch = cpu_arch_name;
2602 arch = default_arch;
2605 /* If we are targeting Intel MCU, we must enable it. */
2606 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2607 || new_flag.bitfield.cpuiamcu)
2610 /* If we are targeting Intel L1OM, we must enable it. */
2611 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2612 || new_flag.bitfield.cpul1om)
2615 /* If we are targeting Intel K1OM, we must enable it. */
2616 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2617 || new_flag.bitfield.cpuk1om)
2620 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2625 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2629 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2632 int e = get_symbol_name (&string);
2634 i386_cpu_flags flags;
2636 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2638 if (strcmp (string, cpu_arch[j].name) == 0)
2640 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2644 cpu_arch_name = cpu_arch[j].name;
2645 cpu_sub_arch_name = NULL;
2646 cpu_arch_flags = cpu_arch[j].flags;
2647 if (flag_code == CODE_64BIT)
2649 cpu_arch_flags.bitfield.cpu64 = 1;
2650 cpu_arch_flags.bitfield.cpuno64 = 0;
2654 cpu_arch_flags.bitfield.cpu64 = 0;
2655 cpu_arch_flags.bitfield.cpuno64 = 1;
2657 cpu_arch_isa = cpu_arch[j].type;
2658 cpu_arch_isa_flags = cpu_arch[j].flags;
2659 if (!cpu_arch_tune_set)
2661 cpu_arch_tune = cpu_arch_isa;
2662 cpu_arch_tune_flags = cpu_arch_isa_flags;
2667 flags = cpu_flags_or (cpu_arch_flags,
2670 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2672 if (cpu_sub_arch_name)
2674 char *name = cpu_sub_arch_name;
2675 cpu_sub_arch_name = concat (name,
2677 (const char *) NULL);
2681 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2682 cpu_arch_flags = flags;
2683 cpu_arch_isa_flags = flags;
2687 = cpu_flags_or (cpu_arch_isa_flags,
2689 (void) restore_line_pointer (e);
2690 demand_empty_rest_of_line ();
2695 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2697 /* Disable an ISA extension. */
2698 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2699 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2701 flags = cpu_flags_and_not (cpu_arch_flags,
2702 cpu_noarch[j].flags);
2703 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2705 if (cpu_sub_arch_name)
2707 char *name = cpu_sub_arch_name;
2708 cpu_sub_arch_name = concat (name, string,
2709 (const char *) NULL);
2713 cpu_sub_arch_name = xstrdup (string);
2714 cpu_arch_flags = flags;
2715 cpu_arch_isa_flags = flags;
2717 (void) restore_line_pointer (e);
2718 demand_empty_rest_of_line ();
2722 j = ARRAY_SIZE (cpu_arch);
2725 if (j >= ARRAY_SIZE (cpu_arch))
2726 as_bad (_("no such architecture: `%s'"), string);
2728 *input_line_pointer = e;
2731 as_bad (_("missing cpu architecture"));
2733 no_cond_jump_promotion = 0;
2734 if (*input_line_pointer == ','
2735 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2740 ++input_line_pointer;
2741 e = get_symbol_name (&string);
2743 if (strcmp (string, "nojumps") == 0)
2744 no_cond_jump_promotion = 1;
2745 else if (strcmp (string, "jumps") == 0)
2748 as_bad (_("no such architecture modifier: `%s'"), string);
2750 (void) restore_line_pointer (e);
2753 demand_empty_rest_of_line ();
2756 enum bfd_architecture
2759 if (cpu_arch_isa == PROCESSOR_L1OM)
2761 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2762 || flag_code != CODE_64BIT)
2763 as_fatal (_("Intel L1OM is 64bit ELF only"));
2764 return bfd_arch_l1om;
2766 else if (cpu_arch_isa == PROCESSOR_K1OM)
2768 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2769 || flag_code != CODE_64BIT)
2770 as_fatal (_("Intel K1OM is 64bit ELF only"));
2771 return bfd_arch_k1om;
2773 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2775 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2776 || flag_code == CODE_64BIT)
2777 as_fatal (_("Intel MCU is 32bit ELF only"));
2778 return bfd_arch_iamcu;
2781 return bfd_arch_i386;
2787 if (!strncmp (default_arch, "x86_64", 6))
2789 if (cpu_arch_isa == PROCESSOR_L1OM)
2791 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2792 || default_arch[6] != '\0')
2793 as_fatal (_("Intel L1OM is 64bit ELF only"));
2794 return bfd_mach_l1om;
2796 else if (cpu_arch_isa == PROCESSOR_K1OM)
2798 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2799 || default_arch[6] != '\0')
2800 as_fatal (_("Intel K1OM is 64bit ELF only"));
2801 return bfd_mach_k1om;
2803 else if (default_arch[6] == '\0')
2804 return bfd_mach_x86_64;
2806 return bfd_mach_x64_32;
2808 else if (!strcmp (default_arch, "i386")
2809 || !strcmp (default_arch, "iamcu"))
2811 if (cpu_arch_isa == PROCESSOR_IAMCU)
2813 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2814 as_fatal (_("Intel MCU is 32bit ELF only"));
2815 return bfd_mach_i386_iamcu;
2818 return bfd_mach_i386_i386;
2821 as_fatal (_("unknown architecture"));
2827 const char *hash_err;
2829 /* Support pseudo prefixes like {disp32}. */
2830 lex_type ['{'] = LEX_BEGIN_NAME;
2832 /* Initialize op_hash hash table. */
2833 op_hash = hash_new ();
2836 const insn_template *optab;
2837 templates *core_optab;
2839 /* Setup for loop. */
2841 core_optab = XNEW (templates);
2842 core_optab->start = optab;
2847 if (optab->name == NULL
2848 || strcmp (optab->name, (optab - 1)->name) != 0)
2850 /* different name --> ship out current template list;
2851 add to hash table; & begin anew. */
2852 core_optab->end = optab;
2853 hash_err = hash_insert (op_hash,
2855 (void *) core_optab);
2858 as_fatal (_("can't hash %s: %s"),
2862 if (optab->name == NULL)
2864 core_optab = XNEW (templates);
2865 core_optab->start = optab;
2870 /* Initialize reg_hash hash table. */
2871 reg_hash = hash_new ();
2873 const reg_entry *regtab;
2874 unsigned int regtab_size = i386_regtab_size;
2876 for (regtab = i386_regtab; regtab_size--; regtab++)
2878 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2880 as_fatal (_("can't hash %s: %s"),
2886 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2891 for (c = 0; c < 256; c++)
2896 mnemonic_chars[c] = c;
2897 register_chars[c] = c;
2898 operand_chars[c] = c;
2900 else if (ISLOWER (c))
2902 mnemonic_chars[c] = c;
2903 register_chars[c] = c;
2904 operand_chars[c] = c;
2906 else if (ISUPPER (c))
2908 mnemonic_chars[c] = TOLOWER (c);
2909 register_chars[c] = mnemonic_chars[c];
2910 operand_chars[c] = c;
2912 else if (c == '{' || c == '}')
2914 mnemonic_chars[c] = c;
2915 operand_chars[c] = c;
2918 if (ISALPHA (c) || ISDIGIT (c))
2919 identifier_chars[c] = c;
2922 identifier_chars[c] = c;
2923 operand_chars[c] = c;
2928 identifier_chars['@'] = '@';
2931 identifier_chars['?'] = '?';
2932 operand_chars['?'] = '?';
2934 digit_chars['-'] = '-';
2935 mnemonic_chars['_'] = '_';
2936 mnemonic_chars['-'] = '-';
2937 mnemonic_chars['.'] = '.';
2938 identifier_chars['_'] = '_';
2939 identifier_chars['.'] = '.';
2941 for (p = operand_special_chars; *p != '\0'; p++)
2942 operand_chars[(unsigned char) *p] = *p;
2945 if (flag_code == CODE_64BIT)
2947 #if defined (OBJ_COFF) && defined (TE_PE)
2948 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2951 x86_dwarf2_return_column = 16;
2953 x86_cie_data_alignment = -8;
2957 x86_dwarf2_return_column = 8;
2958 x86_cie_data_alignment = -4;
2963 i386_print_statistics (FILE *file)
2965 hash_print_statistics (file, "i386 opcode", op_hash);
2966 hash_print_statistics (file, "i386 register", reg_hash);
2971 /* Debugging routines for md_assemble. */
2972 static void pte (insn_template *);
2973 static void pt (i386_operand_type);
2974 static void pe (expressionS *);
2975 static void ps (symbolS *);
2978 pi (char *line, i386_insn *x)
2982 fprintf (stdout, "%s: template ", line);
2984 fprintf (stdout, " address: base %s index %s scale %x\n",
2985 x->base_reg ? x->base_reg->reg_name : "none",
2986 x->index_reg ? x->index_reg->reg_name : "none",
2987 x->log2_scale_factor);
2988 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2989 x->rm.mode, x->rm.reg, x->rm.regmem);
2990 fprintf (stdout, " sib: base %x index %x scale %x\n",
2991 x->sib.base, x->sib.index, x->sib.scale);
2992 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2993 (x->rex & REX_W) != 0,
2994 (x->rex & REX_R) != 0,
2995 (x->rex & REX_X) != 0,
2996 (x->rex & REX_B) != 0);
2997 for (j = 0; j < x->operands; j++)
2999 fprintf (stdout, " #%d: ", j + 1);
3001 fprintf (stdout, "\n");
3002 if (x->types[j].bitfield.reg
3003 || x->types[j].bitfield.regmmx
3004 || x->types[j].bitfield.regsimd
3005 || x->types[j].bitfield.sreg2
3006 || x->types[j].bitfield.sreg3
3007 || x->types[j].bitfield.control
3008 || x->types[j].bitfield.debug
3009 || x->types[j].bitfield.test)
3010 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3011 if (operand_type_check (x->types[j], imm))
3013 if (operand_type_check (x->types[j], disp))
3014 pe (x->op[j].disps);
3019 pte (insn_template *t)
3022 fprintf (stdout, " %d operands ", t->operands);
3023 fprintf (stdout, "opcode %x ", t->base_opcode);
3024 if (t->extension_opcode != None)
3025 fprintf (stdout, "ext %x ", t->extension_opcode);
3026 if (t->opcode_modifier.d)
3027 fprintf (stdout, "D");
3028 if (t->opcode_modifier.w)
3029 fprintf (stdout, "W");
3030 fprintf (stdout, "\n");
3031 for (j = 0; j < t->operands; j++)
3033 fprintf (stdout, " #%d type ", j + 1);
3034 pt (t->operand_types[j]);
3035 fprintf (stdout, "\n");
3042 fprintf (stdout, " operation %d\n", e->X_op);
3043 fprintf (stdout, " add_number %ld (%lx)\n",
3044 (long) e->X_add_number, (long) e->X_add_number);
3045 if (e->X_add_symbol)
3047 fprintf (stdout, " add_symbol ");
3048 ps (e->X_add_symbol);
3049 fprintf (stdout, "\n");
3053 fprintf (stdout, " op_symbol ");
3054 ps (e->X_op_symbol);
3055 fprintf (stdout, "\n");
3062 fprintf (stdout, "%s type %s%s",
3064 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3065 segment_name (S_GET_SEGMENT (s)));
3068 static struct type_name
3070 i386_operand_type mask;
3073 const type_names[] =
3075 { OPERAND_TYPE_REG8, "r8" },
3076 { OPERAND_TYPE_REG16, "r16" },
3077 { OPERAND_TYPE_REG32, "r32" },
3078 { OPERAND_TYPE_REG64, "r64" },
3079 { OPERAND_TYPE_IMM8, "i8" },
3080 { OPERAND_TYPE_IMM8, "i8s" },
3081 { OPERAND_TYPE_IMM16, "i16" },
3082 { OPERAND_TYPE_IMM32, "i32" },
3083 { OPERAND_TYPE_IMM32S, "i32s" },
3084 { OPERAND_TYPE_IMM64, "i64" },
3085 { OPERAND_TYPE_IMM1, "i1" },
3086 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3087 { OPERAND_TYPE_DISP8, "d8" },
3088 { OPERAND_TYPE_DISP16, "d16" },
3089 { OPERAND_TYPE_DISP32, "d32" },
3090 { OPERAND_TYPE_DISP32S, "d32s" },
3091 { OPERAND_TYPE_DISP64, "d64" },
3092 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3093 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3094 { OPERAND_TYPE_CONTROL, "control reg" },
3095 { OPERAND_TYPE_TEST, "test reg" },
3096 { OPERAND_TYPE_DEBUG, "debug reg" },
3097 { OPERAND_TYPE_FLOATREG, "FReg" },
3098 { OPERAND_TYPE_FLOATACC, "FAcc" },
3099 { OPERAND_TYPE_SREG2, "SReg2" },
3100 { OPERAND_TYPE_SREG3, "SReg3" },
3101 { OPERAND_TYPE_ACC, "Acc" },
3102 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3103 { OPERAND_TYPE_REGMMX, "rMMX" },
3104 { OPERAND_TYPE_REGXMM, "rXMM" },
3105 { OPERAND_TYPE_REGYMM, "rYMM" },
3106 { OPERAND_TYPE_REGZMM, "rZMM" },
3107 { OPERAND_TYPE_REGMASK, "Mask reg" },
3108 { OPERAND_TYPE_ESSEG, "es" },
3112 pt (i386_operand_type t)
3115 i386_operand_type a;
3117 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3119 a = operand_type_and (t, type_names[j].mask);
3120 if (!operand_type_all_zero (&a))
3121 fprintf (stdout, "%s, ", type_names[j].name);
3126 #endif /* DEBUG386 */
3128 static bfd_reloc_code_real_type
3129 reloc (unsigned int size,
3132 bfd_reloc_code_real_type other)
3134 if (other != NO_RELOC)
3136 reloc_howto_type *rel;
3141 case BFD_RELOC_X86_64_GOT32:
3142 return BFD_RELOC_X86_64_GOT64;
3144 case BFD_RELOC_X86_64_GOTPLT64:
3145 return BFD_RELOC_X86_64_GOTPLT64;
3147 case BFD_RELOC_X86_64_PLTOFF64:
3148 return BFD_RELOC_X86_64_PLTOFF64;
3150 case BFD_RELOC_X86_64_GOTPC32:
3151 other = BFD_RELOC_X86_64_GOTPC64;
3153 case BFD_RELOC_X86_64_GOTPCREL:
3154 other = BFD_RELOC_X86_64_GOTPCREL64;
3156 case BFD_RELOC_X86_64_TPOFF32:
3157 other = BFD_RELOC_X86_64_TPOFF64;
3159 case BFD_RELOC_X86_64_DTPOFF32:
3160 other = BFD_RELOC_X86_64_DTPOFF64;
3166 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3167 if (other == BFD_RELOC_SIZE32)
3170 other = BFD_RELOC_SIZE64;
3173 as_bad (_("there are no pc-relative size relocations"));
3179 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3180 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3183 rel = bfd_reloc_type_lookup (stdoutput, other);
3185 as_bad (_("unknown relocation (%u)"), other);
3186 else if (size != bfd_get_reloc_size (rel))
3187 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3188 bfd_get_reloc_size (rel),
3190 else if (pcrel && !rel->pc_relative)
3191 as_bad (_("non-pc-relative relocation for pc-relative field"));
3192 else if ((rel->complain_on_overflow == complain_overflow_signed
3194 || (rel->complain_on_overflow == complain_overflow_unsigned
3196 as_bad (_("relocated field and relocation type differ in signedness"));
3205 as_bad (_("there are no unsigned pc-relative relocations"));
3208 case 1: return BFD_RELOC_8_PCREL;
3209 case 2: return BFD_RELOC_16_PCREL;
3210 case 4: return BFD_RELOC_32_PCREL;
3211 case 8: return BFD_RELOC_64_PCREL;
3213 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3220 case 4: return BFD_RELOC_X86_64_32S;
3225 case 1: return BFD_RELOC_8;
3226 case 2: return BFD_RELOC_16;
3227 case 4: return BFD_RELOC_32;
3228 case 8: return BFD_RELOC_64;
3230 as_bad (_("cannot do %s %u byte relocation"),
3231 sign > 0 ? "signed" : "unsigned", size);
3237 /* Here we decide which fixups can be adjusted to make them relative to
3238 the beginning of the section instead of the symbol. Basically we need
3239 to make sure that the dynamic relocations are done correctly, so in
3240 some cases we force the original symbol to be used. */
3243 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3245 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3249 /* Don't adjust pc-relative references to merge sections in 64-bit
3251 if (use_rela_relocations
3252 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3256 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3257 and changed later by validate_fix. */
3258 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3259 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3262 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3263 for size relocations. */
3264 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3265 || fixP->fx_r_type == BFD_RELOC_SIZE64
3266 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3267 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3268 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3269 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3270 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3271 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3272 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3273 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3274 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3275 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3276 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3277 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3278 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3279 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3280 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3281 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3282 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3283 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3284 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3285 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3286 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3287 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3288 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3289 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3290 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3291 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3292 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3293 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3294 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3295 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3296 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3303 intel_float_operand (const char *mnemonic)
3305 /* Note that the value returned is meaningful only for opcodes with (memory)
3306 operands, hence the code here is free to improperly handle opcodes that
3307 have no operands (for better performance and smaller code). */
3309 if (mnemonic[0] != 'f')
3310 return 0; /* non-math */
3312 switch (mnemonic[1])
3314 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3315 the fs segment override prefix not currently handled because no
3316 call path can make opcodes without operands get here */
3318 return 2 /* integer op */;
3320 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3321 return 3; /* fldcw/fldenv */
3324 if (mnemonic[2] != 'o' /* fnop */)
3325 return 3; /* non-waiting control op */
3328 if (mnemonic[2] == 's')
3329 return 3; /* frstor/frstpm */
3332 if (mnemonic[2] == 'a')
3333 return 3; /* fsave */
3334 if (mnemonic[2] == 't')
3336 switch (mnemonic[3])
3338 case 'c': /* fstcw */
3339 case 'd': /* fstdw */
3340 case 'e': /* fstenv */
3341 case 's': /* fsts[gw] */
3347 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3348 return 0; /* fxsave/fxrstor are not really math ops */
3355 /* Build the VEX prefix. */
3358 build_vex_prefix (const insn_template *t)
3360 unsigned int register_specifier;
3361 unsigned int implied_prefix;
3362 unsigned int vector_length;
3365 /* Check register specifier. */
3366 if (i.vex.register_specifier)
3368 register_specifier =
3369 ~register_number (i.vex.register_specifier) & 0xf;
3370 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3373 register_specifier = 0xf;
3375 /* Use 2-byte VEX prefix by swapping destination and source operand
3376 if there are more than 1 register operand. */
3377 if (i.reg_operands > 1
3378 && i.vec_encoding != vex_encoding_vex3
3379 && i.dir_encoding == dir_encoding_default
3380 && i.operands == i.reg_operands
3381 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3382 && i.tm.opcode_modifier.vexopcode == VEX0F
3383 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3386 unsigned int xchg = i.operands - 1;
3387 union i386_op temp_op;
3388 i386_operand_type temp_type;
3390 temp_type = i.types[xchg];
3391 i.types[xchg] = i.types[0];
3392 i.types[0] = temp_type;
3393 temp_op = i.op[xchg];
3394 i.op[xchg] = i.op[0];
3397 gas_assert (i.rm.mode == 3);
3401 i.rm.regmem = i.rm.reg;
3404 if (i.tm.opcode_modifier.d)
3405 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3406 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3407 else /* Use the next insn. */
3411 if (i.tm.opcode_modifier.vex == VEXScalar)
3412 vector_length = avxscalar;
3413 else if (i.tm.opcode_modifier.vex == VEX256)
3419 /* Determine vector length from the last multi-length vector
3422 for (op = t->operands; op--;)
3423 if (t->operand_types[op].bitfield.xmmword
3424 && t->operand_types[op].bitfield.ymmword
3425 && i.types[op].bitfield.ymmword)
3432 switch ((i.tm.base_opcode >> 8) & 0xff)
3437 case DATA_PREFIX_OPCODE:
3440 case REPE_PREFIX_OPCODE:
3443 case REPNE_PREFIX_OPCODE:
3450 /* Check the REX.W bit and VEXW. */
3451 if (i.tm.opcode_modifier.vexw == VEXWIG)
3452 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3453 else if (i.tm.opcode_modifier.vexw)
3454 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3456 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3458 /* Use 2-byte VEX prefix if possible. */
3460 && i.vec_encoding != vex_encoding_vex3
3461 && i.tm.opcode_modifier.vexopcode == VEX0F
3462 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3464 /* 2-byte VEX prefix. */
3468 i.vex.bytes[0] = 0xc5;
3470 /* Check the REX.R bit. */
3471 r = (i.rex & REX_R) ? 0 : 1;
3472 i.vex.bytes[1] = (r << 7
3473 | register_specifier << 3
3474 | vector_length << 2
3479 /* 3-byte VEX prefix. */
3484 switch (i.tm.opcode_modifier.vexopcode)
3488 i.vex.bytes[0] = 0xc4;
3492 i.vex.bytes[0] = 0xc4;
3496 i.vex.bytes[0] = 0xc4;
3500 i.vex.bytes[0] = 0x8f;
3504 i.vex.bytes[0] = 0x8f;
3508 i.vex.bytes[0] = 0x8f;
3514 /* The high 3 bits of the second VEX byte are 1's compliment
3515 of RXB bits from REX. */
3516 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3518 i.vex.bytes[2] = (w << 7
3519 | register_specifier << 3
3520 | vector_length << 2
3525 static INLINE bfd_boolean
3526 is_evex_encoding (const insn_template *t)
3528 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3529 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3530 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3533 static INLINE bfd_boolean
3534 is_any_vex_encoding (const insn_template *t)
3536 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3537 || is_evex_encoding (t);
3540 /* Build the EVEX prefix. */
3543 build_evex_prefix (void)
3545 unsigned int register_specifier;
3546 unsigned int implied_prefix;
3548 rex_byte vrex_used = 0;
3550 /* Check register specifier. */
3551 if (i.vex.register_specifier)
3553 gas_assert ((i.vrex & REX_X) == 0);
3555 register_specifier = i.vex.register_specifier->reg_num;
3556 if ((i.vex.register_specifier->reg_flags & RegRex))
3557 register_specifier += 8;
3558 /* The upper 16 registers are encoded in the fourth byte of the
3560 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3561 i.vex.bytes[3] = 0x8;
3562 register_specifier = ~register_specifier & 0xf;
3566 register_specifier = 0xf;
3568 /* Encode upper 16 vector index register in the fourth byte of
3570 if (!(i.vrex & REX_X))
3571 i.vex.bytes[3] = 0x8;
3576 switch ((i.tm.base_opcode >> 8) & 0xff)
3581 case DATA_PREFIX_OPCODE:
3584 case REPE_PREFIX_OPCODE:
3587 case REPNE_PREFIX_OPCODE:
3594 /* 4 byte EVEX prefix. */
3596 i.vex.bytes[0] = 0x62;
3599 switch (i.tm.opcode_modifier.vexopcode)
3615 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3617 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3619 /* The fifth bit of the second EVEX byte is 1's compliment of the
3620 REX_R bit in VREX. */
3621 if (!(i.vrex & REX_R))
3622 i.vex.bytes[1] |= 0x10;
3626 if ((i.reg_operands + i.imm_operands) == i.operands)
3628 /* When all operands are registers, the REX_X bit in REX is not
3629 used. We reuse it to encode the upper 16 registers, which is
3630 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3631 as 1's compliment. */
3632 if ((i.vrex & REX_B))
3635 i.vex.bytes[1] &= ~0x40;
3639 /* EVEX instructions shouldn't need the REX prefix. */
3640 i.vrex &= ~vrex_used;
3641 gas_assert (i.vrex == 0);
3643 /* Check the REX.W bit and VEXW. */
3644 if (i.tm.opcode_modifier.vexw == VEXWIG)
3645 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3646 else if (i.tm.opcode_modifier.vexw)
3647 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3649 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
3651 /* Encode the U bit. */
3652 implied_prefix |= 0x4;
3654 /* The third byte of the EVEX prefix. */
3655 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3657 /* The fourth byte of the EVEX prefix. */
3658 /* The zeroing-masking bit. */
3659 if (i.mask && i.mask->zeroing)
3660 i.vex.bytes[3] |= 0x80;
3662 /* Don't always set the broadcast bit if there is no RC. */
3665 /* Encode the vector length. */
3666 unsigned int vec_length;
3668 if (!i.tm.opcode_modifier.evex
3669 || i.tm.opcode_modifier.evex == EVEXDYN)
3673 /* Determine vector length from the last multi-length vector
3676 for (op = i.operands; op--;)
3677 if (i.tm.operand_types[op].bitfield.xmmword
3678 + i.tm.operand_types[op].bitfield.ymmword
3679 + i.tm.operand_types[op].bitfield.zmmword > 1)
3681 if (i.types[op].bitfield.zmmword)
3683 i.tm.opcode_modifier.evex = EVEX512;
3686 else if (i.types[op].bitfield.ymmword)
3688 i.tm.opcode_modifier.evex = EVEX256;
3691 else if (i.types[op].bitfield.xmmword)
3693 i.tm.opcode_modifier.evex = EVEX128;
3696 else if (i.broadcast && (int) op == i.broadcast->operand)
3698 switch (i.broadcast->bytes)
3701 i.tm.opcode_modifier.evex = EVEX512;
3704 i.tm.opcode_modifier.evex = EVEX256;
3707 i.tm.opcode_modifier.evex = EVEX128;
3716 if (op >= MAX_OPERANDS)
3720 switch (i.tm.opcode_modifier.evex)
3722 case EVEXLIG: /* LL' is ignored */
3723 vec_length = evexlig << 5;
3726 vec_length = 0 << 5;
3729 vec_length = 1 << 5;
3732 vec_length = 2 << 5;
3738 i.vex.bytes[3] |= vec_length;
3739 /* Encode the broadcast bit. */
3741 i.vex.bytes[3] |= 0x10;
3745 if (i.rounding->type != saeonly)
3746 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3748 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3751 if (i.mask && i.mask->mask)
3752 i.vex.bytes[3] |= i.mask->mask->reg_num;
3756 process_immext (void)
3760 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3763 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3764 with an opcode suffix which is coded in the same place as an
3765 8-bit immediate field would be.
3766 Here we check those operands and remove them afterwards. */
3769 for (x = 0; x < i.operands; x++)
3770 if (register_number (i.op[x].regs) != x)
3771 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3772 register_prefix, i.op[x].regs->reg_name, x + 1,
3778 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3780 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3781 suffix which is coded in the same place as an 8-bit immediate
3783 Here we check those operands and remove them afterwards. */
3786 if (i.operands != 3)
3789 for (x = 0; x < 2; x++)
3790 if (register_number (i.op[x].regs) != x)
3791 goto bad_register_operand;
3793 /* Check for third operand for mwaitx/monitorx insn. */
3794 if (register_number (i.op[x].regs)
3795 != (x + (i.tm.extension_opcode == 0xfb)))
3797 bad_register_operand:
3798 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3799 register_prefix, i.op[x].regs->reg_name, x+1,
3806 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3807 which is coded in the same place as an 8-bit immediate field
3808 would be. Here we fake an 8-bit immediate operand from the
3809 opcode suffix stored in tm.extension_opcode.
3811 AVX instructions also use this encoding, for some of
3812 3 argument instructions. */
3814 gas_assert (i.imm_operands <= 1
3816 || (is_any_vex_encoding (&i.tm)
3817 && i.operands <= 4)));
3819 exp = &im_expressions[i.imm_operands++];
3820 i.op[i.operands].imms = exp;
3821 i.types[i.operands] = imm8;
3823 exp->X_op = O_constant;
3824 exp->X_add_number = i.tm.extension_opcode;
3825 i.tm.extension_opcode = None;
3832 switch (i.tm.opcode_modifier.hleprefixok)
3837 as_bad (_("invalid instruction `%s' after `%s'"),
3838 i.tm.name, i.hle_prefix);
3841 if (i.prefix[LOCK_PREFIX])
3843 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3847 case HLEPrefixRelease:
3848 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3850 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3854 if (i.mem_operands == 0
3855 || !operand_type_check (i.types[i.operands - 1], anymem))
3857 as_bad (_("memory destination needed for instruction `%s'"
3858 " after `xrelease'"), i.tm.name);
3865 /* Try the shortest encoding by shortening operand size. */
3868 optimize_encoding (void)
3872 if (optimize_for_space
3873 && i.reg_operands == 1
3874 && i.imm_operands == 1
3875 && !i.types[1].bitfield.byte
3876 && i.op[0].imms->X_op == O_constant
3877 && fits_in_imm7 (i.op[0].imms->X_add_number)
3878 && ((i.tm.base_opcode == 0xa8
3879 && i.tm.extension_opcode == None)
3880 || (i.tm.base_opcode == 0xf6
3881 && i.tm.extension_opcode == 0x0)))
3884 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3886 unsigned int base_regnum = i.op[1].regs->reg_num;
3887 if (flag_code == CODE_64BIT || base_regnum < 4)
3889 i.types[1].bitfield.byte = 1;
3890 /* Ignore the suffix. */
3892 if (base_regnum >= 4
3893 && !(i.op[1].regs->reg_flags & RegRex))
3895 /* Handle SP, BP, SI and DI registers. */
3896 if (i.types[1].bitfield.word)
3898 else if (i.types[1].bitfield.dword)
3906 else if (flag_code == CODE_64BIT
3907 && ((i.types[1].bitfield.qword
3908 && i.reg_operands == 1
3909 && i.imm_operands == 1
3910 && i.op[0].imms->X_op == O_constant
3911 && ((i.tm.base_opcode == 0xb0
3912 && i.tm.extension_opcode == None
3913 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3914 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3915 && (((i.tm.base_opcode == 0x24
3916 || i.tm.base_opcode == 0xa8)
3917 && i.tm.extension_opcode == None)
3918 || (i.tm.base_opcode == 0x80
3919 && i.tm.extension_opcode == 0x4)
3920 || ((i.tm.base_opcode == 0xf6
3921 || i.tm.base_opcode == 0xc6)
3922 && i.tm.extension_opcode == 0x0)))))
3923 || (i.types[0].bitfield.qword
3924 && ((i.reg_operands == 2
3925 && i.op[0].regs == i.op[1].regs
3926 && ((i.tm.base_opcode == 0x30
3927 || i.tm.base_opcode == 0x28)
3928 && i.tm.extension_opcode == None))
3929 || (i.reg_operands == 1
3931 && i.tm.base_opcode == 0x30
3932 && i.tm.extension_opcode == None)))))
3935 andq $imm31, %r64 -> andl $imm31, %r32
3936 testq $imm31, %r64 -> testl $imm31, %r32
3937 xorq %r64, %r64 -> xorl %r32, %r32
3938 subq %r64, %r64 -> subl %r32, %r32
3939 movq $imm31, %r64 -> movl $imm31, %r32
3940 movq $imm32, %r64 -> movl $imm32, %r32
3942 i.tm.opcode_modifier.norex64 = 1;
3943 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3946 movq $imm31, %r64 -> movl $imm31, %r32
3947 movq $imm32, %r64 -> movl $imm32, %r32
3949 i.tm.operand_types[0].bitfield.imm32 = 1;
3950 i.tm.operand_types[0].bitfield.imm32s = 0;
3951 i.tm.operand_types[0].bitfield.imm64 = 0;
3952 i.types[0].bitfield.imm32 = 1;
3953 i.types[0].bitfield.imm32s = 0;
3954 i.types[0].bitfield.imm64 = 0;
3955 i.types[1].bitfield.dword = 1;
3956 i.types[1].bitfield.qword = 0;
3957 if (i.tm.base_opcode == 0xc6)
3960 movq $imm31, %r64 -> movl $imm31, %r32
3962 i.tm.base_opcode = 0xb0;
3963 i.tm.extension_opcode = None;
3964 i.tm.opcode_modifier.shortform = 1;
3965 i.tm.opcode_modifier.modrm = 0;
3969 else if (optimize > 1
3970 && i.reg_operands == 3
3971 && i.op[0].regs == i.op[1].regs
3972 && !i.types[2].bitfield.xmmword
3973 && (i.tm.opcode_modifier.vex
3974 || ((!i.mask || i.mask->zeroing)
3976 && is_evex_encoding (&i.tm)
3977 && (i.vec_encoding != vex_encoding_evex
3978 || cpu_arch_flags.bitfield.cpuavx
3979 || cpu_arch_isa_flags.bitfield.cpuavx
3980 || cpu_arch_flags.bitfield.cpuavx512vl
3981 || cpu_arch_isa_flags.bitfield.cpuavx512vl
3982 || i.tm.cpu_flags.bitfield.cpuavx512vl
3983 || (i.tm.operand_types[2].bitfield.zmmword
3984 && i.types[2].bitfield.ymmword))))
3985 && ((i.tm.base_opcode == 0x55
3986 || i.tm.base_opcode == 0x6655
3987 || i.tm.base_opcode == 0x66df
3988 || i.tm.base_opcode == 0x57
3989 || i.tm.base_opcode == 0x6657
3990 || i.tm.base_opcode == 0x66ef
3991 || i.tm.base_opcode == 0x66f8
3992 || i.tm.base_opcode == 0x66f9
3993 || i.tm.base_opcode == 0x66fa
3994 || i.tm.base_opcode == 0x66fb
3995 || i.tm.base_opcode == 0x42
3996 || i.tm.base_opcode == 0x6642
3997 || i.tm.base_opcode == 0x47
3998 || i.tm.base_opcode == 0x6647)
3999 && i.tm.extension_opcode == None))
4002 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4004 EVEX VOP %zmmM, %zmmM, %zmmN
4005 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4006 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4007 EVEX VOP %ymmM, %ymmM, %ymmN
4008 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4009 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4010 VEX VOP %ymmM, %ymmM, %ymmN
4011 -> VEX VOP %xmmM, %xmmM, %xmmN
4012 VOP, one of vpandn and vpxor:
4013 VEX VOP %ymmM, %ymmM, %ymmN
4014 -> VEX VOP %xmmM, %xmmM, %xmmN
4015 VOP, one of vpandnd and vpandnq:
4016 EVEX VOP %zmmM, %zmmM, %zmmN
4017 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4018 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4019 EVEX VOP %ymmM, %ymmM, %ymmN
4020 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4021 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4022 VOP, one of vpxord and vpxorq:
4023 EVEX VOP %zmmM, %zmmM, %zmmN
4024 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4025 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4026 EVEX VOP %ymmM, %ymmM, %ymmN
4027 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4028 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
4029 VOP, one of kxord and kxorq:
4030 VEX VOP %kM, %kM, %kN
4031 -> VEX kxorw %kM, %kM, %kN
4032 VOP, one of kandnd and kandnq:
4033 VEX VOP %kM, %kM, %kN
4034 -> VEX kandnw %kM, %kM, %kN
4036 if (is_evex_encoding (&i.tm))
4038 if (i.vec_encoding != vex_encoding_evex
4039 && (cpu_arch_flags.bitfield.cpuavx
4040 || cpu_arch_isa_flags.bitfield.cpuavx))
4042 i.tm.opcode_modifier.vex = VEX128;
4043 i.tm.opcode_modifier.vexw = VEXW0;
4044 i.tm.opcode_modifier.evex = 0;
4046 else if (cpu_arch_flags.bitfield.cpuavx512vl
4047 || cpu_arch_isa_flags.bitfield.cpuavx512vl)
4048 i.tm.opcode_modifier.evex = EVEX128;
4052 else if (i.tm.operand_types[0].bitfield.regmask)
4054 i.tm.base_opcode &= 0xff;
4055 i.tm.opcode_modifier.vexw = VEXW0;
4058 i.tm.opcode_modifier.vex = VEX128;
4060 if (i.tm.opcode_modifier.vex)
4061 for (j = 0; j < 3; j++)
4063 i.types[j].bitfield.xmmword = 1;
4064 i.types[j].bitfield.ymmword = 0;
4069 /* This is the guts of the machine-dependent assembler. LINE points to a
4070 machine dependent instruction. This function is supposed to emit
4071 the frags/bytes it assembles to. */
4074 md_assemble (char *line)
4077 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4078 const insn_template *t;
4080 /* Initialize globals. */
4081 memset (&i, '\0', sizeof (i));
4082 for (j = 0; j < MAX_OPERANDS; j++)
4083 i.reloc[j] = NO_RELOC;
4084 memset (disp_expressions, '\0', sizeof (disp_expressions));
4085 memset (im_expressions, '\0', sizeof (im_expressions));
4086 save_stack_p = save_stack;
4088 /* First parse an instruction mnemonic & call i386_operand for the operands.
4089 We assume that the scrubber has arranged it so that line[0] is the valid
4090 start of a (possibly prefixed) mnemonic. */
4092 line = parse_insn (line, mnemonic);
4095 mnem_suffix = i.suffix;
4097 line = parse_operands (line, mnemonic);
4099 xfree (i.memop1_string);
4100 i.memop1_string = NULL;
4104 /* Now we've parsed the mnemonic into a set of templates, and have the
4105 operands at hand. */
4107 /* All intel opcodes have reversed operands except for "bound" and
4108 "enter". We also don't reverse intersegment "jmp" and "call"
4109 instructions with 2 immediate operands so that the immediate segment
4110 precedes the offset, as it does when in AT&T mode. */
4113 && (strcmp (mnemonic, "bound") != 0)
4114 && (strcmp (mnemonic, "invlpga") != 0)
4115 && !(operand_type_check (i.types[0], imm)
4116 && operand_type_check (i.types[1], imm)))
4119 /* The order of the immediates should be reversed
4120 for 2 immediates extrq and insertq instructions */
4121 if (i.imm_operands == 2
4122 && (strcmp (mnemonic, "extrq") == 0
4123 || strcmp (mnemonic, "insertq") == 0))
4124 swap_2_operands (0, 1);
4129 /* Don't optimize displacement for movabs since it only takes 64bit
4132 && i.disp_encoding != disp_encoding_32bit
4133 && (flag_code != CODE_64BIT
4134 || strcmp (mnemonic, "movabs") != 0))
4137 /* Next, we find a template that matches the given insn,
4138 making sure the overlap of the given operands types is consistent
4139 with the template operand types. */
4141 if (!(t = match_template (mnem_suffix)))
4144 if (sse_check != check_none
4145 && !i.tm.opcode_modifier.noavx
4146 && !i.tm.cpu_flags.bitfield.cpuavx
4147 && (i.tm.cpu_flags.bitfield.cpusse
4148 || i.tm.cpu_flags.bitfield.cpusse2
4149 || i.tm.cpu_flags.bitfield.cpusse3
4150 || i.tm.cpu_flags.bitfield.cpussse3
4151 || i.tm.cpu_flags.bitfield.cpusse4_1
4152 || i.tm.cpu_flags.bitfield.cpusse4_2
4153 || i.tm.cpu_flags.bitfield.cpupclmul
4154 || i.tm.cpu_flags.bitfield.cpuaes
4155 || i.tm.cpu_flags.bitfield.cpugfni))
4157 (sse_check == check_warning
4159 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4162 /* Zap movzx and movsx suffix. The suffix has been set from
4163 "word ptr" or "byte ptr" on the source operand in Intel syntax
4164 or extracted from mnemonic in AT&T syntax. But we'll use
4165 the destination register to choose the suffix for encoding. */
4166 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4168 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4169 there is no suffix, the default will be byte extension. */
4170 if (i.reg_operands != 2
4173 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4178 if (i.tm.opcode_modifier.fwait)
4179 if (!add_prefix (FWAIT_OPCODE))
4182 /* Check if REP prefix is OK. */
4183 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4185 as_bad (_("invalid instruction `%s' after `%s'"),
4186 i.tm.name, i.rep_prefix);
4190 /* Check for lock without a lockable instruction. Destination operand
4191 must be memory unless it is xchg (0x86). */
4192 if (i.prefix[LOCK_PREFIX]
4193 && (!i.tm.opcode_modifier.islockable
4194 || i.mem_operands == 0
4195 || (i.tm.base_opcode != 0x86
4196 && !operand_type_check (i.types[i.operands - 1], anymem))))
4198 as_bad (_("expecting lockable instruction after `lock'"));
4202 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4203 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4205 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4209 /* Check if HLE prefix is OK. */
4210 if (i.hle_prefix && !check_hle ())
4213 /* Check BND prefix. */
4214 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4215 as_bad (_("expecting valid branch instruction after `bnd'"));
4217 /* Check NOTRACK prefix. */
4218 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4219 as_bad (_("expecting indirect branch instruction after `notrack'"));
4221 if (i.tm.cpu_flags.bitfield.cpumpx)
4223 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4224 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4225 else if (flag_code != CODE_16BIT
4226 ? i.prefix[ADDR_PREFIX]
4227 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4228 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4231 /* Insert BND prefix. */
4232 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4234 if (!i.prefix[BND_PREFIX])
4235 add_prefix (BND_PREFIX_OPCODE);
4236 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4238 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4239 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4243 /* Check string instruction segment overrides. */
4244 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4246 if (!check_string ())
4248 i.disp_operands = 0;
4251 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4252 optimize_encoding ();
4254 if (!process_suffix ())
4257 /* Update operand types. */
4258 for (j = 0; j < i.operands; j++)
4259 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4261 /* Make still unresolved immediate matches conform to size of immediate
4262 given in i.suffix. */
4263 if (!finalize_imm ())
4266 if (i.types[0].bitfield.imm1)
4267 i.imm_operands = 0; /* kludge for shift insns. */
4269 /* We only need to check those implicit registers for instructions
4270 with 3 operands or less. */
4271 if (i.operands <= 3)
4272 for (j = 0; j < i.operands; j++)
4273 if (i.types[j].bitfield.inoutportreg
4274 || i.types[j].bitfield.shiftcount
4275 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4278 /* ImmExt should be processed after SSE2AVX. */
4279 if (!i.tm.opcode_modifier.sse2avx
4280 && i.tm.opcode_modifier.immext)
4283 /* For insns with operands there are more diddles to do to the opcode. */
4286 if (!process_operands ())
4289 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4291 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4292 as_warn (_("translating to `%sp'"), i.tm.name);
4295 if (is_any_vex_encoding (&i.tm))
4297 if (flag_code == CODE_16BIT)
4299 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4304 if (i.tm.opcode_modifier.vex)
4305 build_vex_prefix (t);
4307 build_evex_prefix ();
4310 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4311 instructions may define INT_OPCODE as well, so avoid this corner
4312 case for those instructions that use MODRM. */
4313 if (i.tm.base_opcode == INT_OPCODE
4314 && !i.tm.opcode_modifier.modrm
4315 && i.op[0].imms->X_add_number == 3)
4317 i.tm.base_opcode = INT3_OPCODE;
4321 if ((i.tm.opcode_modifier.jump
4322 || i.tm.opcode_modifier.jumpbyte
4323 || i.tm.opcode_modifier.jumpdword)
4324 && i.op[0].disps->X_op == O_constant)
4326 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4327 the absolute address given by the constant. Since ix86 jumps and
4328 calls are pc relative, we need to generate a reloc. */
4329 i.op[0].disps->X_add_symbol = &abs_symbol;
4330 i.op[0].disps->X_op = O_symbol;
4333 if (i.tm.opcode_modifier.rex64)
4336 /* For 8 bit registers we need an empty rex prefix. Also if the
4337 instruction already has a prefix, we need to convert old
4338 registers to new ones. */
4340 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4341 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4342 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4343 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4344 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4345 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4350 i.rex |= REX_OPCODE;
4351 for (x = 0; x < 2; x++)
4353 /* Look for 8 bit operand that uses old registers. */
4354 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4355 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4357 /* In case it is "hi" register, give up. */
4358 if (i.op[x].regs->reg_num > 3)
4359 as_bad (_("can't encode register '%s%s' in an "
4360 "instruction requiring REX prefix."),
4361 register_prefix, i.op[x].regs->reg_name);
4363 /* Otherwise it is equivalent to the extended register.
4364 Since the encoding doesn't change this is merely
4365 cosmetic cleanup for debug output. */
4367 i.op[x].regs = i.op[x].regs + 8;
4372 if (i.rex == 0 && i.rex_encoding)
4374 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4375 that uses legacy register. If it is "hi" register, don't add
4376 the REX_OPCODE byte. */
4378 for (x = 0; x < 2; x++)
4379 if (i.types[x].bitfield.reg
4380 && i.types[x].bitfield.byte
4381 && (i.op[x].regs->reg_flags & RegRex64) == 0
4382 && i.op[x].regs->reg_num > 3)
4384 i.rex_encoding = FALSE;
4393 add_prefix (REX_OPCODE | i.rex);
4395 /* We are ready to output the insn. */
4400 parse_insn (char *line, char *mnemonic)
4403 char *token_start = l;
4406 const insn_template *t;
4412 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4417 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4419 as_bad (_("no such instruction: `%s'"), token_start);
4424 if (!is_space_char (*l)
4425 && *l != END_OF_INSN
4427 || (*l != PREFIX_SEPARATOR
4430 as_bad (_("invalid character %s in mnemonic"),
4431 output_invalid (*l));
4434 if (token_start == l)
4436 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4437 as_bad (_("expecting prefix; got nothing"));
4439 as_bad (_("expecting mnemonic; got nothing"));
4443 /* Look up instruction (or prefix) via hash table. */
4444 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4446 if (*l != END_OF_INSN
4447 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4448 && current_templates
4449 && current_templates->start->opcode_modifier.isprefix)
4451 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4453 as_bad ((flag_code != CODE_64BIT
4454 ? _("`%s' is only supported in 64-bit mode")
4455 : _("`%s' is not supported in 64-bit mode")),
4456 current_templates->start->name);
4459 /* If we are in 16-bit mode, do not allow addr16 or data16.
4460 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4461 if ((current_templates->start->opcode_modifier.size == SIZE16
4462 || current_templates->start->opcode_modifier.size == SIZE32)
4463 && flag_code != CODE_64BIT
4464 && ((current_templates->start->opcode_modifier.size == SIZE32)
4465 ^ (flag_code == CODE_16BIT)))
4467 as_bad (_("redundant %s prefix"),
4468 current_templates->start->name);
4471 if (current_templates->start->opcode_length == 0)
4473 /* Handle pseudo prefixes. */
4474 switch (current_templates->start->base_opcode)
4478 i.disp_encoding = disp_encoding_8bit;
4482 i.disp_encoding = disp_encoding_32bit;
4486 i.dir_encoding = dir_encoding_load;
4490 i.dir_encoding = dir_encoding_store;
4494 i.vec_encoding = vex_encoding_vex2;
4498 i.vec_encoding = vex_encoding_vex3;
4502 i.vec_encoding = vex_encoding_evex;
4506 i.rex_encoding = TRUE;
4510 i.no_optimize = TRUE;
4518 /* Add prefix, checking for repeated prefixes. */
4519 switch (add_prefix (current_templates->start->base_opcode))
4524 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4525 i.notrack_prefix = current_templates->start->name;
4528 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4529 i.hle_prefix = current_templates->start->name;
4530 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4531 i.bnd_prefix = current_templates->start->name;
4533 i.rep_prefix = current_templates->start->name;
4539 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4546 if (!current_templates)
4548 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4549 Check if we should swap operand or force 32bit displacement in
4551 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4552 i.dir_encoding = dir_encoding_swap;
4553 else if (mnem_p - 3 == dot_p
4556 i.disp_encoding = disp_encoding_8bit;
4557 else if (mnem_p - 4 == dot_p
4561 i.disp_encoding = disp_encoding_32bit;
4566 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4569 if (!current_templates)
4572 if (mnem_p > mnemonic)
4574 /* See if we can get a match by trimming off a suffix. */
4577 case WORD_MNEM_SUFFIX:
4578 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4579 i.suffix = SHORT_MNEM_SUFFIX;
4582 case BYTE_MNEM_SUFFIX:
4583 case QWORD_MNEM_SUFFIX:
4584 i.suffix = mnem_p[-1];
4586 current_templates = (const templates *) hash_find (op_hash,
4589 case SHORT_MNEM_SUFFIX:
4590 case LONG_MNEM_SUFFIX:
4593 i.suffix = mnem_p[-1];
4595 current_templates = (const templates *) hash_find (op_hash,
4604 if (intel_float_operand (mnemonic) == 1)
4605 i.suffix = SHORT_MNEM_SUFFIX;
4607 i.suffix = LONG_MNEM_SUFFIX;
4609 current_templates = (const templates *) hash_find (op_hash,
4616 if (!current_templates)
4618 as_bad (_("no such instruction: `%s'"), token_start);
4623 if (current_templates->start->opcode_modifier.jump
4624 || current_templates->start->opcode_modifier.jumpbyte)
4626 /* Check for a branch hint. We allow ",pt" and ",pn" for
4627 predict taken and predict not taken respectively.
4628 I'm not sure that branch hints actually do anything on loop
4629 and jcxz insns (JumpByte) for current Pentium4 chips. They
4630 may work in the future and it doesn't hurt to accept them
4632 if (l[0] == ',' && l[1] == 'p')
4636 if (!add_prefix (DS_PREFIX_OPCODE))
4640 else if (l[2] == 'n')
4642 if (!add_prefix (CS_PREFIX_OPCODE))
4648 /* Any other comma loses. */
4651 as_bad (_("invalid character %s in mnemonic"),
4652 output_invalid (*l));
4656 /* Check if instruction is supported on specified architecture. */
4658 for (t = current_templates->start; t < current_templates->end; ++t)
4660 supported |= cpu_flags_match (t);
4661 if (supported == CPU_FLAGS_PERFECT_MATCH)
4663 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4664 as_warn (_("use .code16 to ensure correct addressing mode"));
4670 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4671 as_bad (flag_code == CODE_64BIT
4672 ? _("`%s' is not supported in 64-bit mode")
4673 : _("`%s' is only supported in 64-bit mode"),
4674 current_templates->start->name);
4676 as_bad (_("`%s' is not supported on `%s%s'"),
4677 current_templates->start->name,
4678 cpu_arch_name ? cpu_arch_name : default_arch,
4679 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4685 parse_operands (char *l, const char *mnemonic)
4689 /* 1 if operand is pending after ','. */
4690 unsigned int expecting_operand = 0;
4692 /* Non-zero if operand parens not balanced. */
4693 unsigned int paren_not_balanced;
4695 while (*l != END_OF_INSN)
4697 /* Skip optional white space before operand. */
4698 if (is_space_char (*l))
4700 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4702 as_bad (_("invalid character %s before operand %d"),
4703 output_invalid (*l),
4707 token_start = l; /* After white space. */
4708 paren_not_balanced = 0;
4709 while (paren_not_balanced || *l != ',')
4711 if (*l == END_OF_INSN)
4713 if (paren_not_balanced)
4716 as_bad (_("unbalanced parenthesis in operand %d."),
4719 as_bad (_("unbalanced brackets in operand %d."),
4724 break; /* we are done */
4726 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4728 as_bad (_("invalid character %s in operand %d"),
4729 output_invalid (*l),
4736 ++paren_not_balanced;
4738 --paren_not_balanced;
4743 ++paren_not_balanced;
4745 --paren_not_balanced;
4749 if (l != token_start)
4750 { /* Yes, we've read in another operand. */
4751 unsigned int operand_ok;
4752 this_operand = i.operands++;
4753 if (i.operands > MAX_OPERANDS)
4755 as_bad (_("spurious operands; (%d operands/instruction max)"),
4759 i.types[this_operand].bitfield.unspecified = 1;
4760 /* Now parse operand adding info to 'i' as we go along. */
4761 END_STRING_AND_SAVE (l);
4763 if (i.mem_operands > 1)
4765 as_bad (_("too many memory references for `%s'"),
4772 i386_intel_operand (token_start,
4773 intel_float_operand (mnemonic));
4775 operand_ok = i386_att_operand (token_start);
4777 RESTORE_END_STRING (l);
4783 if (expecting_operand)
4785 expecting_operand_after_comma:
4786 as_bad (_("expecting operand after ','; got nothing"));
4791 as_bad (_("expecting operand before ','; got nothing"));
4796 /* Now *l must be either ',' or END_OF_INSN. */
4799 if (*++l == END_OF_INSN)
4801 /* Just skip it, if it's \n complain. */
4802 goto expecting_operand_after_comma;
4804 expecting_operand = 1;
4811 swap_2_operands (int xchg1, int xchg2)
4813 union i386_op temp_op;
4814 i386_operand_type temp_type;
4815 unsigned int temp_flags;
4816 enum bfd_reloc_code_real temp_reloc;
4818 temp_type = i.types[xchg2];
4819 i.types[xchg2] = i.types[xchg1];
4820 i.types[xchg1] = temp_type;
4822 temp_flags = i.flags[xchg2];
4823 i.flags[xchg2] = i.flags[xchg1];
4824 i.flags[xchg1] = temp_flags;
4826 temp_op = i.op[xchg2];
4827 i.op[xchg2] = i.op[xchg1];
4828 i.op[xchg1] = temp_op;
4830 temp_reloc = i.reloc[xchg2];
4831 i.reloc[xchg2] = i.reloc[xchg1];
4832 i.reloc[xchg1] = temp_reloc;
4836 if (i.mask->operand == xchg1)
4837 i.mask->operand = xchg2;
4838 else if (i.mask->operand == xchg2)
4839 i.mask->operand = xchg1;
4843 if (i.broadcast->operand == xchg1)
4844 i.broadcast->operand = xchg2;
4845 else if (i.broadcast->operand == xchg2)
4846 i.broadcast->operand = xchg1;
4850 if (i.rounding->operand == xchg1)
4851 i.rounding->operand = xchg2;
4852 else if (i.rounding->operand == xchg2)
4853 i.rounding->operand = xchg1;
4858 swap_operands (void)
4864 swap_2_operands (1, i.operands - 2);
4868 swap_2_operands (0, i.operands - 1);
4874 if (i.mem_operands == 2)
4876 const seg_entry *temp_seg;
4877 temp_seg = i.seg[0];
4878 i.seg[0] = i.seg[1];
4879 i.seg[1] = temp_seg;
4883 /* Try to ensure constant immediates are represented in the smallest
4888 char guess_suffix = 0;
4892 guess_suffix = i.suffix;
4893 else if (i.reg_operands)
4895 /* Figure out a suffix from the last register operand specified.
4896 We can't do this properly yet, ie. excluding InOutPortReg,
4897 but the following works for instructions with immediates.
4898 In any case, we can't set i.suffix yet. */
4899 for (op = i.operands; --op >= 0;)
4900 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4902 guess_suffix = BYTE_MNEM_SUFFIX;
4905 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4907 guess_suffix = WORD_MNEM_SUFFIX;
4910 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4912 guess_suffix = LONG_MNEM_SUFFIX;
4915 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4917 guess_suffix = QWORD_MNEM_SUFFIX;
4921 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4922 guess_suffix = WORD_MNEM_SUFFIX;
4924 for (op = i.operands; --op >= 0;)
4925 if (operand_type_check (i.types[op], imm))
4927 switch (i.op[op].imms->X_op)
4930 /* If a suffix is given, this operand may be shortened. */
4931 switch (guess_suffix)
4933 case LONG_MNEM_SUFFIX:
4934 i.types[op].bitfield.imm32 = 1;
4935 i.types[op].bitfield.imm64 = 1;
4937 case WORD_MNEM_SUFFIX:
4938 i.types[op].bitfield.imm16 = 1;
4939 i.types[op].bitfield.imm32 = 1;
4940 i.types[op].bitfield.imm32s = 1;
4941 i.types[op].bitfield.imm64 = 1;
4943 case BYTE_MNEM_SUFFIX:
4944 i.types[op].bitfield.imm8 = 1;
4945 i.types[op].bitfield.imm8s = 1;
4946 i.types[op].bitfield.imm16 = 1;
4947 i.types[op].bitfield.imm32 = 1;
4948 i.types[op].bitfield.imm32s = 1;
4949 i.types[op].bitfield.imm64 = 1;
4953 /* If this operand is at most 16 bits, convert it
4954 to a signed 16 bit number before trying to see
4955 whether it will fit in an even smaller size.
4956 This allows a 16-bit operand such as $0xffe0 to
4957 be recognised as within Imm8S range. */
4958 if ((i.types[op].bitfield.imm16)
4959 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4961 i.op[op].imms->X_add_number =
4962 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4965 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4966 if ((i.types[op].bitfield.imm32)
4967 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4970 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4971 ^ ((offsetT) 1 << 31))
4972 - ((offsetT) 1 << 31));
4976 = operand_type_or (i.types[op],
4977 smallest_imm_type (i.op[op].imms->X_add_number));
4979 /* We must avoid matching of Imm32 templates when 64bit
4980 only immediate is available. */
4981 if (guess_suffix == QWORD_MNEM_SUFFIX)
4982 i.types[op].bitfield.imm32 = 0;
4989 /* Symbols and expressions. */
4991 /* Convert symbolic operand to proper sizes for matching, but don't
4992 prevent matching a set of insns that only supports sizes other
4993 than those matching the insn suffix. */
4995 i386_operand_type mask, allowed;
4996 const insn_template *t;
4998 operand_type_set (&mask, 0);
4999 operand_type_set (&allowed, 0);
5001 for (t = current_templates->start;
5002 t < current_templates->end;
5004 allowed = operand_type_or (allowed,
5005 t->operand_types[op]);
5006 switch (guess_suffix)
5008 case QWORD_MNEM_SUFFIX:
5009 mask.bitfield.imm64 = 1;
5010 mask.bitfield.imm32s = 1;
5012 case LONG_MNEM_SUFFIX:
5013 mask.bitfield.imm32 = 1;
5015 case WORD_MNEM_SUFFIX:
5016 mask.bitfield.imm16 = 1;
5018 case BYTE_MNEM_SUFFIX:
5019 mask.bitfield.imm8 = 1;
5024 allowed = operand_type_and (mask, allowed);
5025 if (!operand_type_all_zero (&allowed))
5026 i.types[op] = operand_type_and (i.types[op], mask);
5033 /* Try to use the smallest displacement type too. */
5035 optimize_disp (void)
5039 for (op = i.operands; --op >= 0;)
5040 if (operand_type_check (i.types[op], disp))
5042 if (i.op[op].disps->X_op == O_constant)
5044 offsetT op_disp = i.op[op].disps->X_add_number;
5046 if (i.types[op].bitfield.disp16
5047 && (op_disp & ~(offsetT) 0xffff) == 0)
5049 /* If this operand is at most 16 bits, convert
5050 to a signed 16 bit number and don't use 64bit
5052 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5053 i.types[op].bitfield.disp64 = 0;
5056 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5057 if (i.types[op].bitfield.disp32
5058 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5060 /* If this operand is at most 32 bits, convert
5061 to a signed 32 bit number and don't use 64bit
5063 op_disp &= (((offsetT) 2 << 31) - 1);
5064 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5065 i.types[op].bitfield.disp64 = 0;
5068 if (!op_disp && i.types[op].bitfield.baseindex)
5070 i.types[op].bitfield.disp8 = 0;
5071 i.types[op].bitfield.disp16 = 0;
5072 i.types[op].bitfield.disp32 = 0;
5073 i.types[op].bitfield.disp32s = 0;
5074 i.types[op].bitfield.disp64 = 0;
5078 else if (flag_code == CODE_64BIT)
5080 if (fits_in_signed_long (op_disp))
5082 i.types[op].bitfield.disp64 = 0;
5083 i.types[op].bitfield.disp32s = 1;
5085 if (i.prefix[ADDR_PREFIX]
5086 && fits_in_unsigned_long (op_disp))
5087 i.types[op].bitfield.disp32 = 1;
5089 if ((i.types[op].bitfield.disp32
5090 || i.types[op].bitfield.disp32s
5091 || i.types[op].bitfield.disp16)
5092 && fits_in_disp8 (op_disp))
5093 i.types[op].bitfield.disp8 = 1;
5095 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5096 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5098 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5099 i.op[op].disps, 0, i.reloc[op]);
5100 i.types[op].bitfield.disp8 = 0;
5101 i.types[op].bitfield.disp16 = 0;
5102 i.types[op].bitfield.disp32 = 0;
5103 i.types[op].bitfield.disp32s = 0;
5104 i.types[op].bitfield.disp64 = 0;
5107 /* We only support 64bit displacement on constants. */
5108 i.types[op].bitfield.disp64 = 0;
5112 /* Return 1 if there is a match in broadcast bytes between operand
5113 GIVEN and instruction template T. */
5116 match_broadcast_size (const insn_template *t, unsigned int given)
5118 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5119 && i.types[given].bitfield.byte)
5120 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5121 && i.types[given].bitfield.word)
5122 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5123 && i.types[given].bitfield.dword)
5124 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5125 && i.types[given].bitfield.qword));
5128 /* Check if operands are valid for the instruction. */
5131 check_VecOperands (const insn_template *t)
5135 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5137 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5138 any one operand are implicity requiring AVX512VL support if the actual
5139 operand size is YMMword or XMMword. Since this function runs after
5140 template matching, there's no need to check for YMMword/XMMword in
5142 cpu = cpu_flags_and (t->cpu_flags, avx512);
5143 if (!cpu_flags_all_zero (&cpu)
5144 && !t->cpu_flags.bitfield.cpuavx512vl
5145 && !cpu_arch_flags.bitfield.cpuavx512vl)
5147 for (op = 0; op < t->operands; ++op)
5149 if (t->operand_types[op].bitfield.zmmword
5150 && (i.types[op].bitfield.ymmword
5151 || i.types[op].bitfield.xmmword))
5153 i.error = unsupported;
5159 /* Without VSIB byte, we can't have a vector register for index. */
5160 if (!t->opcode_modifier.vecsib
5162 && (i.index_reg->reg_type.bitfield.xmmword
5163 || i.index_reg->reg_type.bitfield.ymmword
5164 || i.index_reg->reg_type.bitfield.zmmword))
5166 i.error = unsupported_vector_index_register;
5170 /* Check if default mask is allowed. */
5171 if (t->opcode_modifier.nodefmask
5172 && (!i.mask || i.mask->mask->reg_num == 0))
5174 i.error = no_default_mask;
5178 /* For VSIB byte, we need a vector register for index, and all vector
5179 registers must be distinct. */
5180 if (t->opcode_modifier.vecsib)
5183 || !((t->opcode_modifier.vecsib == VecSIB128
5184 && i.index_reg->reg_type.bitfield.xmmword)
5185 || (t->opcode_modifier.vecsib == VecSIB256
5186 && i.index_reg->reg_type.bitfield.ymmword)
5187 || (t->opcode_modifier.vecsib == VecSIB512
5188 && i.index_reg->reg_type.bitfield.zmmword)))
5190 i.error = invalid_vsib_address;
5194 gas_assert (i.reg_operands == 2 || i.mask);
5195 if (i.reg_operands == 2 && !i.mask)
5197 gas_assert (i.types[0].bitfield.regsimd);
5198 gas_assert (i.types[0].bitfield.xmmword
5199 || i.types[0].bitfield.ymmword);
5200 gas_assert (i.types[2].bitfield.regsimd);
5201 gas_assert (i.types[2].bitfield.xmmword
5202 || i.types[2].bitfield.ymmword);
5203 if (operand_check == check_none)
5205 if (register_number (i.op[0].regs)
5206 != register_number (i.index_reg)
5207 && register_number (i.op[2].regs)
5208 != register_number (i.index_reg)
5209 && register_number (i.op[0].regs)
5210 != register_number (i.op[2].regs))
5212 if (operand_check == check_error)
5214 i.error = invalid_vector_register_set;
5217 as_warn (_("mask, index, and destination registers should be distinct"));
5219 else if (i.reg_operands == 1 && i.mask)
5221 if (i.types[1].bitfield.regsimd
5222 && (i.types[1].bitfield.xmmword
5223 || i.types[1].bitfield.ymmword
5224 || i.types[1].bitfield.zmmword)
5225 && (register_number (i.op[1].regs)
5226 == register_number (i.index_reg)))
5228 if (operand_check == check_error)
5230 i.error = invalid_vector_register_set;
5233 if (operand_check != check_none)
5234 as_warn (_("index and destination registers should be distinct"));
5239 /* Check if broadcast is supported by the instruction and is applied
5240 to the memory operand. */
5243 i386_operand_type type, overlap;
5245 /* Check if specified broadcast is supported in this instruction,
5246 and its broadcast bytes match the memory operand. */
5247 op = i.broadcast->operand;
5248 if (!t->opcode_modifier.broadcast
5249 || !(i.flags[op] & Operand_Mem)
5250 || (!i.types[op].bitfield.unspecified
5251 && !match_broadcast_size (t, op)))
5254 i.error = unsupported_broadcast;
5258 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5259 * i.broadcast->type);
5260 operand_type_set (&type, 0);
5261 switch (i.broadcast->bytes)
5264 type.bitfield.word = 1;
5267 type.bitfield.dword = 1;
5270 type.bitfield.qword = 1;
5273 type.bitfield.xmmword = 1;
5276 type.bitfield.ymmword = 1;
5279 type.bitfield.zmmword = 1;
5285 overlap = operand_type_and (type, t->operand_types[op]);
5286 if (operand_type_all_zero (&overlap))
5289 if (t->opcode_modifier.checkregsize)
5293 type.bitfield.baseindex = 1;
5294 for (j = 0; j < i.operands; ++j)
5297 && !operand_type_register_match(i.types[j],
5298 t->operand_types[j],
5300 t->operand_types[op]))
5305 /* If broadcast is supported in this instruction, we need to check if
5306 operand of one-element size isn't specified without broadcast. */
5307 else if (t->opcode_modifier.broadcast && i.mem_operands)
5309 /* Find memory operand. */
5310 for (op = 0; op < i.operands; op++)
5311 if (operand_type_check (i.types[op], anymem))
5313 gas_assert (op < i.operands);
5314 /* Check size of the memory operand. */
5315 if (match_broadcast_size (t, op))
5317 i.error = broadcast_needed;
5322 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5324 /* Check if requested masking is supported. */
5327 switch (t->opcode_modifier.masking)
5331 case MERGING_MASKING:
5332 if (i.mask->zeroing)
5335 i.error = unsupported_masking;
5339 case DYNAMIC_MASKING:
5340 /* Memory destinations allow only merging masking. */
5341 if (i.mask->zeroing && i.mem_operands)
5343 /* Find memory operand. */
5344 for (op = 0; op < i.operands; op++)
5345 if (i.flags[op] & Operand_Mem)
5347 gas_assert (op < i.operands);
5348 if (op == i.operands - 1)
5350 i.error = unsupported_masking;
5360 /* Check if masking is applied to dest operand. */
5361 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5363 i.error = mask_not_on_destination;
5370 if ((i.rounding->type != saeonly
5371 && !t->opcode_modifier.staticrounding)
5372 || (i.rounding->type == saeonly
5373 && (t->opcode_modifier.staticrounding
5374 || !t->opcode_modifier.sae)))
5376 i.error = unsupported_rc_sae;
5379 /* If the instruction has several immediate operands and one of
5380 them is rounding, the rounding operand should be the last
5381 immediate operand. */
5382 if (i.imm_operands > 1
5383 && i.rounding->operand != (int) (i.imm_operands - 1))
5385 i.error = rc_sae_operand_not_last_imm;
5390 /* Check vector Disp8 operand. */
5391 if (t->opcode_modifier.disp8memshift
5392 && i.disp_encoding != disp_encoding_32bit)
5395 i.memshift = t->opcode_modifier.broadcast - 1;
5396 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5397 i.memshift = t->opcode_modifier.disp8memshift;
5400 const i386_operand_type *type = NULL;
5403 for (op = 0; op < i.operands; op++)
5404 if (operand_type_check (i.types[op], anymem))
5406 if (t->opcode_modifier.evex == EVEXLIG)
5407 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5408 else if (t->operand_types[op].bitfield.xmmword
5409 + t->operand_types[op].bitfield.ymmword
5410 + t->operand_types[op].bitfield.zmmword <= 1)
5411 type = &t->operand_types[op];
5412 else if (!i.types[op].bitfield.unspecified)
5413 type = &i.types[op];
5415 else if (i.types[op].bitfield.regsimd
5416 && t->opcode_modifier.evex != EVEXLIG)
5418 if (i.types[op].bitfield.zmmword)
5420 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5422 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5428 if (type->bitfield.zmmword)
5430 else if (type->bitfield.ymmword)
5432 else if (type->bitfield.xmmword)
5436 /* For the check in fits_in_disp8(). */
5437 if (i.memshift == 0)
5441 for (op = 0; op < i.operands; op++)
5442 if (operand_type_check (i.types[op], disp)
5443 && i.op[op].disps->X_op == O_constant)
5445 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5447 i.types[op].bitfield.disp8 = 1;
5450 i.types[op].bitfield.disp8 = 0;
5459 /* Check if operands are valid for the instruction. Update VEX
5463 VEX_check_operands (const insn_template *t)
5465 if (i.vec_encoding == vex_encoding_evex)
5467 /* This instruction must be encoded with EVEX prefix. */
5468 if (!is_evex_encoding (t))
5470 i.error = unsupported;
5476 if (!t->opcode_modifier.vex)
5478 /* This instruction template doesn't have VEX prefix. */
5479 if (i.vec_encoding != vex_encoding_default)
5481 i.error = unsupported;
5487 /* Only check VEX_Imm4, which must be the first operand. */
5488 if (t->operand_types[0].bitfield.vec_imm4)
5490 if (i.op[0].imms->X_op != O_constant
5491 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5497 /* Turn off Imm8 so that update_imm won't complain. */
5498 i.types[0] = vec_imm4;
5504 static const insn_template *
5505 match_template (char mnem_suffix)
5507 /* Points to template once we've found it. */
5508 const insn_template *t;
5509 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5510 i386_operand_type overlap4;
5511 unsigned int found_reverse_match;
5512 i386_opcode_modifier suffix_check, mnemsuf_check;
5513 i386_operand_type operand_types [MAX_OPERANDS];
5514 int addr_prefix_disp;
5516 unsigned int found_cpu_match, size_match;
5517 unsigned int check_register;
5518 enum i386_error specific_error = 0;
5520 #if MAX_OPERANDS != 5
5521 # error "MAX_OPERANDS must be 5."
5524 found_reverse_match = 0;
5525 addr_prefix_disp = -1;
5527 memset (&suffix_check, 0, sizeof (suffix_check));
5528 if (intel_syntax && i.broadcast)
5530 else if (i.suffix == BYTE_MNEM_SUFFIX)
5531 suffix_check.no_bsuf = 1;
5532 else if (i.suffix == WORD_MNEM_SUFFIX)
5533 suffix_check.no_wsuf = 1;
5534 else if (i.suffix == SHORT_MNEM_SUFFIX)
5535 suffix_check.no_ssuf = 1;
5536 else if (i.suffix == LONG_MNEM_SUFFIX)
5537 suffix_check.no_lsuf = 1;
5538 else if (i.suffix == QWORD_MNEM_SUFFIX)
5539 suffix_check.no_qsuf = 1;
5540 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5541 suffix_check.no_ldsuf = 1;
5543 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5546 switch (mnem_suffix)
5548 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5549 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5550 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5551 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5552 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5556 /* Must have right number of operands. */
5557 i.error = number_of_operands_mismatch;
5559 for (t = current_templates->start; t < current_templates->end; t++)
5561 addr_prefix_disp = -1;
5562 found_reverse_match = 0;
5564 if (i.operands != t->operands)
5567 /* Check processor support. */
5568 i.error = unsupported;
5569 found_cpu_match = (cpu_flags_match (t)
5570 == CPU_FLAGS_PERFECT_MATCH);
5571 if (!found_cpu_match)
5574 /* Check AT&T mnemonic. */
5575 i.error = unsupported_with_intel_mnemonic;
5576 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5579 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5580 i.error = unsupported_syntax;
5581 if ((intel_syntax && t->opcode_modifier.attsyntax)
5582 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5583 || (intel64 && t->opcode_modifier.amd64)
5584 || (!intel64 && t->opcode_modifier.intel64))
5587 /* Check the suffix, except for some instructions in intel mode. */
5588 i.error = invalid_instruction_suffix;
5589 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5590 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5591 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5592 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5593 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5594 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5595 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5597 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5598 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5599 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5600 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5601 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5602 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5603 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5606 size_match = operand_size_match (t);
5610 for (j = 0; j < MAX_OPERANDS; j++)
5611 operand_types[j] = t->operand_types[j];
5613 /* In general, don't allow 64-bit operands in 32-bit mode. */
5614 if (i.suffix == QWORD_MNEM_SUFFIX
5615 && flag_code != CODE_64BIT
5617 ? (!t->opcode_modifier.ignoresize
5618 && !t->opcode_modifier.broadcast
5619 && !intel_float_operand (t->name))
5620 : intel_float_operand (t->name) != 2)
5621 && ((!operand_types[0].bitfield.regmmx
5622 && !operand_types[0].bitfield.regsimd)
5623 || (!operand_types[t->operands > 1].bitfield.regmmx
5624 && !operand_types[t->operands > 1].bitfield.regsimd))
5625 && (t->base_opcode != 0x0fc7
5626 || t->extension_opcode != 1 /* cmpxchg8b */))
5629 /* In general, don't allow 32-bit operands on pre-386. */
5630 else if (i.suffix == LONG_MNEM_SUFFIX
5631 && !cpu_arch_flags.bitfield.cpui386
5633 ? (!t->opcode_modifier.ignoresize
5634 && !intel_float_operand (t->name))
5635 : intel_float_operand (t->name) != 2)
5636 && ((!operand_types[0].bitfield.regmmx
5637 && !operand_types[0].bitfield.regsimd)
5638 || (!operand_types[t->operands > 1].bitfield.regmmx
5639 && !operand_types[t->operands > 1].bitfield.regsimd)))
5642 /* Do not verify operands when there are none. */
5646 /* We've found a match; break out of loop. */
5650 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5651 into Disp32/Disp16/Disp32 operand. */
5652 if (i.prefix[ADDR_PREFIX] != 0)
5654 /* There should be only one Disp operand. */
5658 for (j = 0; j < MAX_OPERANDS; j++)
5660 if (operand_types[j].bitfield.disp16)
5662 addr_prefix_disp = j;
5663 operand_types[j].bitfield.disp32 = 1;
5664 operand_types[j].bitfield.disp16 = 0;
5670 for (j = 0; j < MAX_OPERANDS; j++)
5672 if (operand_types[j].bitfield.disp32)
5674 addr_prefix_disp = j;
5675 operand_types[j].bitfield.disp32 = 0;
5676 operand_types[j].bitfield.disp16 = 1;
5682 for (j = 0; j < MAX_OPERANDS; j++)
5684 if (operand_types[j].bitfield.disp64)
5686 addr_prefix_disp = j;
5687 operand_types[j].bitfield.disp64 = 0;
5688 operand_types[j].bitfield.disp32 = 1;
5696 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5697 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5700 /* We check register size if needed. */
5701 if (t->opcode_modifier.checkregsize)
5703 check_register = (1 << t->operands) - 1;
5705 check_register &= ~(1 << i.broadcast->operand);
5710 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5711 switch (t->operands)
5714 if (!operand_type_match (overlap0, i.types[0]))
5718 /* xchg %eax, %eax is a special case. It is an alias for nop
5719 only in 32bit mode and we can use opcode 0x90. In 64bit
5720 mode, we can't use 0x90 for xchg %eax, %eax since it should
5721 zero-extend %eax to %rax. */
5722 if (flag_code == CODE_64BIT
5723 && t->base_opcode == 0x90
5724 && operand_type_equal (&i.types [0], &acc32)
5725 && operand_type_equal (&i.types [1], &acc32))
5727 /* xrelease mov %eax, <disp> is another special case. It must not
5728 match the accumulator-only encoding of mov. */
5729 if (flag_code != CODE_64BIT
5731 && t->base_opcode == 0xa0
5732 && i.types[0].bitfield.acc
5733 && operand_type_check (i.types[1], anymem))
5738 if (!(size_match & MATCH_STRAIGHT))
5740 /* Reverse direction of operands if swapping is possible in the first
5741 place (operands need to be symmetric) and
5742 - the load form is requested, and the template is a store form,
5743 - the store form is requested, and the template is a load form,
5744 - the non-default (swapped) form is requested. */
5745 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
5746 if (t->opcode_modifier.d && i.reg_operands == i.operands
5747 && !operand_type_all_zero (&overlap1))
5748 switch (i.dir_encoding)
5750 case dir_encoding_load:
5751 if (operand_type_check (operand_types[i.operands - 1], anymem)
5752 || operand_types[i.operands - 1].bitfield.regmem)
5756 case dir_encoding_store:
5757 if (!operand_type_check (operand_types[i.operands - 1], anymem)
5758 && !operand_types[i.operands - 1].bitfield.regmem)
5762 case dir_encoding_swap:
5765 case dir_encoding_default:
5768 /* If we want store form, we skip the current load. */
5769 if ((i.dir_encoding == dir_encoding_store
5770 || i.dir_encoding == dir_encoding_swap)
5771 && i.mem_operands == 0
5772 && t->opcode_modifier.load)
5777 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5778 if (!operand_type_match (overlap0, i.types[0])
5779 || !operand_type_match (overlap1, i.types[1])
5780 || ((check_register & 3) == 3
5781 && !operand_type_register_match (i.types[0],
5786 /* Check if other direction is valid ... */
5787 if (!t->opcode_modifier.d)
5791 if (!(size_match & MATCH_REVERSE))
5793 /* Try reversing direction of operands. */
5794 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
5795 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
5796 if (!operand_type_match (overlap0, i.types[0])
5797 || !operand_type_match (overlap1, i.types[i.operands - 1])
5799 && !operand_type_register_match (i.types[0],
5800 operand_types[i.operands - 1],
5801 i.types[i.operands - 1],
5804 /* Does not match either direction. */
5807 /* found_reverse_match holds which of D or FloatR
5809 if (!t->opcode_modifier.d)
5810 found_reverse_match = 0;
5811 else if (operand_types[0].bitfield.tbyte)
5812 found_reverse_match = Opcode_FloatD;
5813 else if (operand_types[0].bitfield.xmmword
5814 || operand_types[i.operands - 1].bitfield.xmmword
5815 || operand_types[0].bitfield.regmmx
5816 || operand_types[i.operands - 1].bitfield.regmmx
5817 || is_any_vex_encoding(t))
5818 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
5819 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
5821 found_reverse_match = Opcode_D;
5822 if (t->opcode_modifier.floatr)
5823 found_reverse_match |= Opcode_FloatR;
5827 /* Found a forward 2 operand match here. */
5828 switch (t->operands)
5831 overlap4 = operand_type_and (i.types[4],
5835 overlap3 = operand_type_and (i.types[3],
5839 overlap2 = operand_type_and (i.types[2],
5844 switch (t->operands)
5847 if (!operand_type_match (overlap4, i.types[4])
5848 || !operand_type_register_match (i.types[3],
5855 if (!operand_type_match (overlap3, i.types[3])
5856 || ((check_register & 0xa) == 0xa
5857 && !operand_type_register_match (i.types[1],
5861 || ((check_register & 0xc) == 0xc
5862 && !operand_type_register_match (i.types[2],
5869 /* Here we make use of the fact that there are no
5870 reverse match 3 operand instructions. */
5871 if (!operand_type_match (overlap2, i.types[2])
5872 || ((check_register & 5) == 5
5873 && !operand_type_register_match (i.types[0],
5877 || ((check_register & 6) == 6
5878 && !operand_type_register_match (i.types[1],
5886 /* Found either forward/reverse 2, 3 or 4 operand match here:
5887 slip through to break. */
5889 if (!found_cpu_match)
5892 /* Check if vector and VEX operands are valid. */
5893 if (check_VecOperands (t) || VEX_check_operands (t))
5895 specific_error = i.error;
5899 /* We've found a match; break out of loop. */
5903 if (t == current_templates->end)
5905 /* We found no match. */
5906 const char *err_msg;
5907 switch (specific_error ? specific_error : i.error)
5911 case operand_size_mismatch:
5912 err_msg = _("operand size mismatch");
5914 case operand_type_mismatch:
5915 err_msg = _("operand type mismatch");
5917 case register_type_mismatch:
5918 err_msg = _("register type mismatch");
5920 case number_of_operands_mismatch:
5921 err_msg = _("number of operands mismatch");
5923 case invalid_instruction_suffix:
5924 err_msg = _("invalid instruction suffix");
5927 err_msg = _("constant doesn't fit in 4 bits");
5929 case unsupported_with_intel_mnemonic:
5930 err_msg = _("unsupported with Intel mnemonic");
5932 case unsupported_syntax:
5933 err_msg = _("unsupported syntax");
5936 as_bad (_("unsupported instruction `%s'"),
5937 current_templates->start->name);
5939 case invalid_vsib_address:
5940 err_msg = _("invalid VSIB address");
5942 case invalid_vector_register_set:
5943 err_msg = _("mask, index, and destination registers must be distinct");
5945 case unsupported_vector_index_register:
5946 err_msg = _("unsupported vector index register");
5948 case unsupported_broadcast:
5949 err_msg = _("unsupported broadcast");
5951 case broadcast_needed:
5952 err_msg = _("broadcast is needed for operand of such type");
5954 case unsupported_masking:
5955 err_msg = _("unsupported masking");
5957 case mask_not_on_destination:
5958 err_msg = _("mask not on destination operand");
5960 case no_default_mask:
5961 err_msg = _("default mask isn't allowed");
5963 case unsupported_rc_sae:
5964 err_msg = _("unsupported static rounding/sae");
5966 case rc_sae_operand_not_last_imm:
5968 err_msg = _("RC/SAE operand must precede immediate operands");
5970 err_msg = _("RC/SAE operand must follow immediate operands");
5972 case invalid_register_operand:
5973 err_msg = _("invalid register operand");
5976 as_bad (_("%s for `%s'"), err_msg,
5977 current_templates->start->name);
5981 if (!quiet_warnings)
5984 && (i.types[0].bitfield.jumpabsolute
5985 != operand_types[0].bitfield.jumpabsolute))
5987 as_warn (_("indirect %s without `*'"), t->name);
5990 if (t->opcode_modifier.isprefix
5991 && t->opcode_modifier.ignoresize)
5993 /* Warn them that a data or address size prefix doesn't
5994 affect assembly of the next line of code. */
5995 as_warn (_("stand-alone `%s' prefix"), t->name);
5999 /* Copy the template we found. */
6002 if (addr_prefix_disp != -1)
6003 i.tm.operand_types[addr_prefix_disp]
6004 = operand_types[addr_prefix_disp];
6006 if (found_reverse_match)
6008 /* If we found a reverse match we must alter the opcode
6009 direction bit. found_reverse_match holds bits to change
6010 (different for int & float insns). */
6012 i.tm.base_opcode ^= found_reverse_match;
6014 i.tm.operand_types[0] = operand_types[i.operands - 1];
6015 i.tm.operand_types[i.operands - 1] = operand_types[0];
6024 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
6025 if (i.tm.operand_types[mem_op].bitfield.esseg)
6027 if (i.seg[0] != NULL && i.seg[0] != &es)
6029 as_bad (_("`%s' operand %d must use `%ses' segment"),
6035 /* There's only ever one segment override allowed per instruction.
6036 This instruction possibly has a legal segment override on the
6037 second operand, so copy the segment to where non-string
6038 instructions store it, allowing common code. */
6039 i.seg[0] = i.seg[1];
6041 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
6043 if (i.seg[1] != NULL && i.seg[1] != &es)
6045 as_bad (_("`%s' operand %d must use `%ses' segment"),
6056 process_suffix (void)
6058 /* If matched instruction specifies an explicit instruction mnemonic
6060 if (i.tm.opcode_modifier.size == SIZE16)
6061 i.suffix = WORD_MNEM_SUFFIX;
6062 else if (i.tm.opcode_modifier.size == SIZE32)
6063 i.suffix = LONG_MNEM_SUFFIX;
6064 else if (i.tm.opcode_modifier.size == SIZE64)
6065 i.suffix = QWORD_MNEM_SUFFIX;
6066 else if (i.reg_operands)
6068 /* If there's no instruction mnemonic suffix we try to invent one
6069 based on register operands. */
6072 /* We take i.suffix from the last register operand specified,
6073 Destination register type is more significant than source
6074 register type. crc32 in SSE4.2 prefers source register
6076 if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg)
6078 if (i.types[0].bitfield.byte)
6079 i.suffix = BYTE_MNEM_SUFFIX;
6080 else if (i.types[0].bitfield.word)
6081 i.suffix = WORD_MNEM_SUFFIX;
6082 else if (i.types[0].bitfield.dword)
6083 i.suffix = LONG_MNEM_SUFFIX;
6084 else if (i.types[0].bitfield.qword)
6085 i.suffix = QWORD_MNEM_SUFFIX;
6092 if (i.tm.base_opcode == 0xf20f38f0)
6094 /* We have to know the operand size for crc32. */
6095 as_bad (_("ambiguous memory operand size for `%s`"),
6100 for (op = i.operands; --op >= 0;)
6101 if (!i.tm.operand_types[op].bitfield.inoutportreg
6102 && !i.tm.operand_types[op].bitfield.shiftcount)
6104 if (!i.types[op].bitfield.reg)
6106 if (i.types[op].bitfield.byte)
6107 i.suffix = BYTE_MNEM_SUFFIX;
6108 else if (i.types[op].bitfield.word)
6109 i.suffix = WORD_MNEM_SUFFIX;
6110 else if (i.types[op].bitfield.dword)
6111 i.suffix = LONG_MNEM_SUFFIX;
6112 else if (i.types[op].bitfield.qword)
6113 i.suffix = QWORD_MNEM_SUFFIX;
6120 else if (i.suffix == BYTE_MNEM_SUFFIX)
6123 && i.tm.opcode_modifier.ignoresize
6124 && i.tm.opcode_modifier.no_bsuf)
6126 else if (!check_byte_reg ())
6129 else if (i.suffix == LONG_MNEM_SUFFIX)
6132 && i.tm.opcode_modifier.ignoresize
6133 && i.tm.opcode_modifier.no_lsuf
6134 && !i.tm.opcode_modifier.todword
6135 && !i.tm.opcode_modifier.toqword)
6137 else if (!check_long_reg ())
6140 else if (i.suffix == QWORD_MNEM_SUFFIX)
6143 && i.tm.opcode_modifier.ignoresize
6144 && i.tm.opcode_modifier.no_qsuf
6145 && !i.tm.opcode_modifier.todword
6146 && !i.tm.opcode_modifier.toqword)
6148 else if (!check_qword_reg ())
6151 else if (i.suffix == WORD_MNEM_SUFFIX)
6154 && i.tm.opcode_modifier.ignoresize
6155 && i.tm.opcode_modifier.no_wsuf)
6157 else if (!check_word_reg ())
6160 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6161 /* Do nothing if the instruction is going to ignore the prefix. */
6166 else if (i.tm.opcode_modifier.defaultsize
6168 /* exclude fldenv/frstor/fsave/fstenv */
6169 && i.tm.opcode_modifier.no_ssuf)
6171 i.suffix = stackop_size;
6173 else if (intel_syntax
6175 && (i.tm.operand_types[0].bitfield.jumpabsolute
6176 || i.tm.opcode_modifier.jumpbyte
6177 || i.tm.opcode_modifier.jumpintersegment
6178 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6179 && i.tm.extension_opcode <= 3)))
6184 if (!i.tm.opcode_modifier.no_qsuf)
6186 i.suffix = QWORD_MNEM_SUFFIX;
6191 if (!i.tm.opcode_modifier.no_lsuf)
6192 i.suffix = LONG_MNEM_SUFFIX;
6195 if (!i.tm.opcode_modifier.no_wsuf)
6196 i.suffix = WORD_MNEM_SUFFIX;
6205 if (i.tm.opcode_modifier.w)
6207 as_bad (_("no instruction mnemonic suffix given and "
6208 "no register operands; can't size instruction"));
6214 unsigned int suffixes;
6216 suffixes = !i.tm.opcode_modifier.no_bsuf;
6217 if (!i.tm.opcode_modifier.no_wsuf)
6219 if (!i.tm.opcode_modifier.no_lsuf)
6221 if (!i.tm.opcode_modifier.no_ldsuf)
6223 if (!i.tm.opcode_modifier.no_ssuf)
6225 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6228 /* There are more than suffix matches. */
6229 if (i.tm.opcode_modifier.w
6230 || ((suffixes & (suffixes - 1))
6231 && !i.tm.opcode_modifier.defaultsize
6232 && !i.tm.opcode_modifier.ignoresize))
6234 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6240 /* Change the opcode based on the operand size given by i.suffix. */
6243 /* Size floating point instruction. */
6244 case LONG_MNEM_SUFFIX:
6245 if (i.tm.opcode_modifier.floatmf)
6247 i.tm.base_opcode ^= 4;
6251 case WORD_MNEM_SUFFIX:
6252 case QWORD_MNEM_SUFFIX:
6253 /* It's not a byte, select word/dword operation. */
6254 if (i.tm.opcode_modifier.w)
6256 if (i.tm.opcode_modifier.shortform)
6257 i.tm.base_opcode |= 8;
6259 i.tm.base_opcode |= 1;
6262 case SHORT_MNEM_SUFFIX:
6263 /* Now select between word & dword operations via the operand
6264 size prefix, except for instructions that will ignore this
6266 if (i.reg_operands > 0
6267 && i.types[0].bitfield.reg
6268 && i.tm.opcode_modifier.addrprefixopreg
6269 && (i.tm.opcode_modifier.immext
6270 || i.operands == 1))
6272 /* The address size override prefix changes the size of the
6274 if ((flag_code == CODE_32BIT
6275 && i.op[0].regs->reg_type.bitfield.word)
6276 || (flag_code != CODE_32BIT
6277 && i.op[0].regs->reg_type.bitfield.dword))
6278 if (!add_prefix (ADDR_PREFIX_OPCODE))
6281 else if (i.suffix != QWORD_MNEM_SUFFIX
6282 && !i.tm.opcode_modifier.ignoresize
6283 && !i.tm.opcode_modifier.floatmf
6284 && !i.tm.opcode_modifier.vex
6285 && !i.tm.opcode_modifier.vexopcode
6286 && !is_evex_encoding (&i.tm)
6287 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6288 || (flag_code == CODE_64BIT
6289 && i.tm.opcode_modifier.jumpbyte)))
6291 unsigned int prefix = DATA_PREFIX_OPCODE;
6293 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6294 prefix = ADDR_PREFIX_OPCODE;
6296 if (!add_prefix (prefix))
6300 /* Set mode64 for an operand. */
6301 if (i.suffix == QWORD_MNEM_SUFFIX
6302 && flag_code == CODE_64BIT
6303 && !i.tm.opcode_modifier.norex64
6304 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6306 && ! (i.operands == 2
6307 && i.tm.base_opcode == 0x90
6308 && i.tm.extension_opcode == None
6309 && operand_type_equal (&i.types [0], &acc64)
6310 && operand_type_equal (&i.types [1], &acc64)))
6316 if (i.reg_operands != 0
6318 && i.tm.opcode_modifier.addrprefixopreg
6319 && !i.tm.opcode_modifier.immext)
6321 /* Check invalid register operand when the address size override
6322 prefix changes the size of register operands. */
6324 enum { need_word, need_dword, need_qword } need;
6326 if (flag_code == CODE_32BIT)
6327 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6330 if (i.prefix[ADDR_PREFIX])
6333 need = flag_code == CODE_64BIT ? need_qword : need_word;
6336 for (op = 0; op < i.operands; op++)
6337 if (i.types[op].bitfield.reg
6338 && ((need == need_word
6339 && !i.op[op].regs->reg_type.bitfield.word)
6340 || (need == need_dword
6341 && !i.op[op].regs->reg_type.bitfield.dword)
6342 || (need == need_qword
6343 && !i.op[op].regs->reg_type.bitfield.qword)))
6345 as_bad (_("invalid register operand size for `%s'"),
6355 check_byte_reg (void)
6359 for (op = i.operands; --op >= 0;)
6361 /* Skip non-register operands. */
6362 if (!i.types[op].bitfield.reg)
6365 /* If this is an eight bit register, it's OK. If it's the 16 or
6366 32 bit version of an eight bit register, we will just use the
6367 low portion, and that's OK too. */
6368 if (i.types[op].bitfield.byte)
6371 /* I/O port address operands are OK too. */
6372 if (i.tm.operand_types[op].bitfield.inoutportreg)
6375 /* crc32 doesn't generate this warning. */
6376 if (i.tm.base_opcode == 0xf20f38f0)
6379 if ((i.types[op].bitfield.word
6380 || i.types[op].bitfield.dword
6381 || i.types[op].bitfield.qword)
6382 && i.op[op].regs->reg_num < 4
6383 /* Prohibit these changes in 64bit mode, since the lowering
6384 would be more complicated. */
6385 && flag_code != CODE_64BIT)
6387 #if REGISTER_WARNINGS
6388 if (!quiet_warnings)
6389 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6391 (i.op[op].regs + (i.types[op].bitfield.word
6392 ? REGNAM_AL - REGNAM_AX
6393 : REGNAM_AL - REGNAM_EAX))->reg_name,
6395 i.op[op].regs->reg_name,
6400 /* Any other register is bad. */
6401 if (i.types[op].bitfield.reg
6402 || i.types[op].bitfield.regmmx
6403 || i.types[op].bitfield.regsimd
6404 || i.types[op].bitfield.sreg2
6405 || i.types[op].bitfield.sreg3
6406 || i.types[op].bitfield.control
6407 || i.types[op].bitfield.debug
6408 || i.types[op].bitfield.test)
6410 as_bad (_("`%s%s' not allowed with `%s%c'"),
6412 i.op[op].regs->reg_name,
6422 check_long_reg (void)
6426 for (op = i.operands; --op >= 0;)
6427 /* Skip non-register operands. */
6428 if (!i.types[op].bitfield.reg)
6430 /* Reject eight bit registers, except where the template requires
6431 them. (eg. movzb) */
6432 else if (i.types[op].bitfield.byte
6433 && (i.tm.operand_types[op].bitfield.reg
6434 || i.tm.operand_types[op].bitfield.acc)
6435 && (i.tm.operand_types[op].bitfield.word
6436 || i.tm.operand_types[op].bitfield.dword))
6438 as_bad (_("`%s%s' not allowed with `%s%c'"),
6440 i.op[op].regs->reg_name,
6445 /* Warn if the e prefix on a general reg is missing. */
6446 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6447 && i.types[op].bitfield.word
6448 && (i.tm.operand_types[op].bitfield.reg
6449 || i.tm.operand_types[op].bitfield.acc)
6450 && i.tm.operand_types[op].bitfield.dword)
6452 /* Prohibit these changes in the 64bit mode, since the
6453 lowering is more complicated. */
6454 if (flag_code == CODE_64BIT)
6456 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6457 register_prefix, i.op[op].regs->reg_name,
6461 #if REGISTER_WARNINGS
6462 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6464 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6465 register_prefix, i.op[op].regs->reg_name, i.suffix);
6468 /* Warn if the r prefix on a general reg is present. */
6469 else if (i.types[op].bitfield.qword
6470 && (i.tm.operand_types[op].bitfield.reg
6471 || i.tm.operand_types[op].bitfield.acc)
6472 && i.tm.operand_types[op].bitfield.dword)
6475 && i.tm.opcode_modifier.toqword
6476 && !i.types[0].bitfield.regsimd)
6478 /* Convert to QWORD. We want REX byte. */
6479 i.suffix = QWORD_MNEM_SUFFIX;
6483 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6484 register_prefix, i.op[op].regs->reg_name,
6493 check_qword_reg (void)
6497 for (op = i.operands; --op >= 0; )
6498 /* Skip non-register operands. */
6499 if (!i.types[op].bitfield.reg)
6501 /* Reject eight bit registers, except where the template requires
6502 them. (eg. movzb) */
6503 else if (i.types[op].bitfield.byte
6504 && (i.tm.operand_types[op].bitfield.reg
6505 || i.tm.operand_types[op].bitfield.acc)
6506 && (i.tm.operand_types[op].bitfield.word
6507 || i.tm.operand_types[op].bitfield.dword))
6509 as_bad (_("`%s%s' not allowed with `%s%c'"),
6511 i.op[op].regs->reg_name,
6516 /* Warn if the r prefix on a general reg is missing. */
6517 else if ((i.types[op].bitfield.word
6518 || i.types[op].bitfield.dword)
6519 && (i.tm.operand_types[op].bitfield.reg
6520 || i.tm.operand_types[op].bitfield.acc)
6521 && i.tm.operand_types[op].bitfield.qword)
6523 /* Prohibit these changes in the 64bit mode, since the
6524 lowering is more complicated. */
6526 && i.tm.opcode_modifier.todword
6527 && !i.types[0].bitfield.regsimd)
6529 /* Convert to DWORD. We don't want REX byte. */
6530 i.suffix = LONG_MNEM_SUFFIX;
6534 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6535 register_prefix, i.op[op].regs->reg_name,
6544 check_word_reg (void)
6547 for (op = i.operands; --op >= 0;)
6548 /* Skip non-register operands. */
6549 if (!i.types[op].bitfield.reg)
6551 /* Reject eight bit registers, except where the template requires
6552 them. (eg. movzb) */
6553 else if (i.types[op].bitfield.byte
6554 && (i.tm.operand_types[op].bitfield.reg
6555 || i.tm.operand_types[op].bitfield.acc)
6556 && (i.tm.operand_types[op].bitfield.word
6557 || i.tm.operand_types[op].bitfield.dword))
6559 as_bad (_("`%s%s' not allowed with `%s%c'"),
6561 i.op[op].regs->reg_name,
6566 /* Warn if the e or r prefix on a general reg is present. */
6567 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6568 && (i.types[op].bitfield.dword
6569 || i.types[op].bitfield.qword)
6570 && (i.tm.operand_types[op].bitfield.reg
6571 || i.tm.operand_types[op].bitfield.acc)
6572 && i.tm.operand_types[op].bitfield.word)
6574 /* Prohibit these changes in the 64bit mode, since the
6575 lowering is more complicated. */
6576 if (flag_code == CODE_64BIT)
6578 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6579 register_prefix, i.op[op].regs->reg_name,
6583 #if REGISTER_WARNINGS
6584 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6586 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6587 register_prefix, i.op[op].regs->reg_name, i.suffix);
6594 update_imm (unsigned int j)
6596 i386_operand_type overlap = i.types[j];
6597 if ((overlap.bitfield.imm8
6598 || overlap.bitfield.imm8s
6599 || overlap.bitfield.imm16
6600 || overlap.bitfield.imm32
6601 || overlap.bitfield.imm32s
6602 || overlap.bitfield.imm64)
6603 && !operand_type_equal (&overlap, &imm8)
6604 && !operand_type_equal (&overlap, &imm8s)
6605 && !operand_type_equal (&overlap, &imm16)
6606 && !operand_type_equal (&overlap, &imm32)
6607 && !operand_type_equal (&overlap, &imm32s)
6608 && !operand_type_equal (&overlap, &imm64))
6612 i386_operand_type temp;
6614 operand_type_set (&temp, 0);
6615 if (i.suffix == BYTE_MNEM_SUFFIX)
6617 temp.bitfield.imm8 = overlap.bitfield.imm8;
6618 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6620 else if (i.suffix == WORD_MNEM_SUFFIX)
6621 temp.bitfield.imm16 = overlap.bitfield.imm16;
6622 else if (i.suffix == QWORD_MNEM_SUFFIX)
6624 temp.bitfield.imm64 = overlap.bitfield.imm64;
6625 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6628 temp.bitfield.imm32 = overlap.bitfield.imm32;
6631 else if (operand_type_equal (&overlap, &imm16_32_32s)
6632 || operand_type_equal (&overlap, &imm16_32)
6633 || operand_type_equal (&overlap, &imm16_32s))
6635 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6640 if (!operand_type_equal (&overlap, &imm8)
6641 && !operand_type_equal (&overlap, &imm8s)
6642 && !operand_type_equal (&overlap, &imm16)
6643 && !operand_type_equal (&overlap, &imm32)
6644 && !operand_type_equal (&overlap, &imm32s)
6645 && !operand_type_equal (&overlap, &imm64))
6647 as_bad (_("no instruction mnemonic suffix given; "
6648 "can't determine immediate size"));
6652 i.types[j] = overlap;
6662 /* Update the first 2 immediate operands. */
6663 n = i.operands > 2 ? 2 : i.operands;
6666 for (j = 0; j < n; j++)
6667 if (update_imm (j) == 0)
6670 /* The 3rd operand can't be immediate operand. */
6671 gas_assert (operand_type_check (i.types[2], imm) == 0);
6678 process_operands (void)
6680 /* Default segment register this instruction will use for memory
6681 accesses. 0 means unknown. This is only for optimizing out
6682 unnecessary segment overrides. */
6683 const seg_entry *default_seg = 0;
6685 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6687 unsigned int dupl = i.operands;
6688 unsigned int dest = dupl - 1;
6691 /* The destination must be an xmm register. */
6692 gas_assert (i.reg_operands
6693 && MAX_OPERANDS > dupl
6694 && operand_type_equal (&i.types[dest], ®xmm));
6696 if (i.tm.operand_types[0].bitfield.acc
6697 && i.tm.operand_types[0].bitfield.xmmword)
6699 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6701 /* Keep xmm0 for instructions with VEX prefix and 3
6703 i.tm.operand_types[0].bitfield.acc = 0;
6704 i.tm.operand_types[0].bitfield.regsimd = 1;
6709 /* We remove the first xmm0 and keep the number of
6710 operands unchanged, which in fact duplicates the
6712 for (j = 1; j < i.operands; j++)
6714 i.op[j - 1] = i.op[j];
6715 i.types[j - 1] = i.types[j];
6716 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6720 else if (i.tm.opcode_modifier.implicit1stxmm0)
6722 gas_assert ((MAX_OPERANDS - 1) > dupl
6723 && (i.tm.opcode_modifier.vexsources
6726 /* Add the implicit xmm0 for instructions with VEX prefix
6728 for (j = i.operands; j > 0; j--)
6730 i.op[j] = i.op[j - 1];
6731 i.types[j] = i.types[j - 1];
6732 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6735 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6736 i.types[0] = regxmm;
6737 i.tm.operand_types[0] = regxmm;
6740 i.reg_operands += 2;
6745 i.op[dupl] = i.op[dest];
6746 i.types[dupl] = i.types[dest];
6747 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6756 i.op[dupl] = i.op[dest];
6757 i.types[dupl] = i.types[dest];
6758 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6761 if (i.tm.opcode_modifier.immext)
6764 else if (i.tm.operand_types[0].bitfield.acc
6765 && i.tm.operand_types[0].bitfield.xmmword)
6769 for (j = 1; j < i.operands; j++)
6771 i.op[j - 1] = i.op[j];
6772 i.types[j - 1] = i.types[j];
6774 /* We need to adjust fields in i.tm since they are used by
6775 build_modrm_byte. */
6776 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6783 else if (i.tm.opcode_modifier.implicitquadgroup)
6785 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6787 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6788 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6789 regnum = register_number (i.op[1].regs);
6790 first_reg_in_group = regnum & ~3;
6791 last_reg_in_group = first_reg_in_group + 3;
6792 if (regnum != first_reg_in_group)
6793 as_warn (_("source register `%s%s' implicitly denotes"
6794 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6795 register_prefix, i.op[1].regs->reg_name,
6796 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6797 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6800 else if (i.tm.opcode_modifier.regkludge)
6802 /* The imul $imm, %reg instruction is converted into
6803 imul $imm, %reg, %reg, and the clr %reg instruction
6804 is converted into xor %reg, %reg. */
6806 unsigned int first_reg_op;
6808 if (operand_type_check (i.types[0], reg))
6812 /* Pretend we saw the extra register operand. */
6813 gas_assert (i.reg_operands == 1
6814 && i.op[first_reg_op + 1].regs == 0);
6815 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6816 i.types[first_reg_op + 1] = i.types[first_reg_op];
6821 if (i.tm.opcode_modifier.shortform)
6823 if (i.types[0].bitfield.sreg2
6824 || i.types[0].bitfield.sreg3)
6826 if (i.tm.base_opcode == POP_SEG_SHORT
6827 && i.op[0].regs->reg_num == 1)
6829 as_bad (_("you can't `pop %scs'"), register_prefix);
6832 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6833 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6838 /* The register or float register operand is in operand
6842 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6843 || operand_type_check (i.types[0], reg))
6847 /* Register goes in low 3 bits of opcode. */
6848 i.tm.base_opcode |= i.op[op].regs->reg_num;
6849 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6851 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6853 /* Warn about some common errors, but press on regardless.
6854 The first case can be generated by gcc (<= 2.8.1). */
6855 if (i.operands == 2)
6857 /* Reversed arguments on faddp, fsubp, etc. */
6858 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6859 register_prefix, i.op[!intel_syntax].regs->reg_name,
6860 register_prefix, i.op[intel_syntax].regs->reg_name);
6864 /* Extraneous `l' suffix on fp insn. */
6865 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6866 register_prefix, i.op[0].regs->reg_name);
6871 else if (i.tm.opcode_modifier.modrm)
6873 /* The opcode is completed (modulo i.tm.extension_opcode which
6874 must be put into the modrm byte). Now, we make the modrm and
6875 index base bytes based on all the info we've collected. */
6877 default_seg = build_modrm_byte ();
6879 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6883 else if (i.tm.opcode_modifier.isstring)
6885 /* For the string instructions that allow a segment override
6886 on one of their operands, the default segment is ds. */
6890 if (i.tm.base_opcode == 0x8d /* lea */
6893 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6895 /* If a segment was explicitly specified, and the specified segment
6896 is not the default, use an opcode prefix to select it. If we
6897 never figured out what the default segment is, then default_seg
6898 will be zero at this point, and the specified segment prefix will
6900 if ((i.seg[0]) && (i.seg[0] != default_seg))
6902 if (!add_prefix (i.seg[0]->seg_prefix))
6908 static const seg_entry *
6909 build_modrm_byte (void)
6911 const seg_entry *default_seg = 0;
6912 unsigned int source, dest;
6915 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6918 unsigned int nds, reg_slot;
6921 dest = i.operands - 1;
6924 /* There are 2 kinds of instructions:
6925 1. 5 operands: 4 register operands or 3 register operands
6926 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6927 VexW0 or VexW1. The destination must be either XMM, YMM or
6929 2. 4 operands: 4 register operands or 3 register operands
6930 plus 1 memory operand, with VexXDS. */
6931 gas_assert ((i.reg_operands == 4
6932 || (i.reg_operands == 3 && i.mem_operands == 1))
6933 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6934 && i.tm.opcode_modifier.vexw
6935 && i.tm.operand_types[dest].bitfield.regsimd);
6937 /* If VexW1 is set, the first non-immediate operand is the source and
6938 the second non-immediate one is encoded in the immediate operand. */
6939 if (i.tm.opcode_modifier.vexw == VEXW1)
6941 source = i.imm_operands;
6942 reg_slot = i.imm_operands + 1;
6946 source = i.imm_operands + 1;
6947 reg_slot = i.imm_operands;
6950 if (i.imm_operands == 0)
6952 /* When there is no immediate operand, generate an 8bit
6953 immediate operand to encode the first operand. */
6954 exp = &im_expressions[i.imm_operands++];
6955 i.op[i.operands].imms = exp;
6956 i.types[i.operands] = imm8;
6959 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6960 exp->X_op = O_constant;
6961 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6962 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6966 unsigned int imm_slot;
6968 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6970 if (i.tm.opcode_modifier.immext)
6972 /* When ImmExt is set, the immediate byte is the last
6974 imm_slot = i.operands - 1;
6982 /* Turn on Imm8 so that output_imm will generate it. */
6983 i.types[imm_slot].bitfield.imm8 = 1;
6986 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6987 i.op[imm_slot].imms->X_add_number
6988 |= register_number (i.op[reg_slot].regs) << 4;
6989 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6992 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6993 i.vex.register_specifier = i.op[nds].regs;
6998 /* i.reg_operands MUST be the number of real register operands;
6999 implicit registers do not count. If there are 3 register
7000 operands, it must be a instruction with VexNDS. For a
7001 instruction with VexNDD, the destination register is encoded
7002 in VEX prefix. If there are 4 register operands, it must be
7003 a instruction with VEX prefix and 3 sources. */
7004 if (i.mem_operands == 0
7005 && ((i.reg_operands == 2
7006 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7007 || (i.reg_operands == 3
7008 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7009 || (i.reg_operands == 4 && vex_3_sources)))
7017 /* When there are 3 operands, one of them may be immediate,
7018 which may be the first or the last operand. Otherwise,
7019 the first operand must be shift count register (cl) or it
7020 is an instruction with VexNDS. */
7021 gas_assert (i.imm_operands == 1
7022 || (i.imm_operands == 0
7023 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7024 || i.types[0].bitfield.shiftcount)));
7025 if (operand_type_check (i.types[0], imm)
7026 || i.types[0].bitfield.shiftcount)
7032 /* When there are 4 operands, the first two must be 8bit
7033 immediate operands. The source operand will be the 3rd
7036 For instructions with VexNDS, if the first operand
7037 an imm8, the source operand is the 2nd one. If the last
7038 operand is imm8, the source operand is the first one. */
7039 gas_assert ((i.imm_operands == 2
7040 && i.types[0].bitfield.imm8
7041 && i.types[1].bitfield.imm8)
7042 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7043 && i.imm_operands == 1
7044 && (i.types[0].bitfield.imm8
7045 || i.types[i.operands - 1].bitfield.imm8
7047 if (i.imm_operands == 2)
7051 if (i.types[0].bitfield.imm8)
7058 if (is_evex_encoding (&i.tm))
7060 /* For EVEX instructions, when there are 5 operands, the
7061 first one must be immediate operand. If the second one
7062 is immediate operand, the source operand is the 3th
7063 one. If the last one is immediate operand, the source
7064 operand is the 2nd one. */
7065 gas_assert (i.imm_operands == 2
7066 && i.tm.opcode_modifier.sae
7067 && operand_type_check (i.types[0], imm));
7068 if (operand_type_check (i.types[1], imm))
7070 else if (operand_type_check (i.types[4], imm))
7084 /* RC/SAE operand could be between DEST and SRC. That happens
7085 when one operand is GPR and the other one is XMM/YMM/ZMM
7087 if (i.rounding && i.rounding->operand == (int) dest)
7090 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7092 /* For instructions with VexNDS, the register-only source
7093 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7094 register. It is encoded in VEX prefix. We need to
7095 clear RegMem bit before calling operand_type_equal. */
7097 i386_operand_type op;
7100 /* Check register-only source operand when two source
7101 operands are swapped. */
7102 if (!i.tm.operand_types[source].bitfield.baseindex
7103 && i.tm.operand_types[dest].bitfield.baseindex)
7111 op = i.tm.operand_types[vvvv];
7112 op.bitfield.regmem = 0;
7113 if ((dest + 1) >= i.operands
7114 || ((!op.bitfield.reg
7115 || (!op.bitfield.dword && !op.bitfield.qword))
7116 && !op.bitfield.regsimd
7117 && !operand_type_equal (&op, ®mask)))
7119 i.vex.register_specifier = i.op[vvvv].regs;
7125 /* One of the register operands will be encoded in the i.tm.reg
7126 field, the other in the combined i.tm.mode and i.tm.regmem
7127 fields. If no form of this instruction supports a memory
7128 destination operand, then we assume the source operand may
7129 sometimes be a memory operand and so we need to store the
7130 destination in the i.rm.reg field. */
7131 if (!i.tm.operand_types[dest].bitfield.regmem
7132 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7134 i.rm.reg = i.op[dest].regs->reg_num;
7135 i.rm.regmem = i.op[source].regs->reg_num;
7136 if (i.op[dest].regs->reg_type.bitfield.regmmx
7137 || i.op[source].regs->reg_type.bitfield.regmmx)
7138 i.has_regmmx = TRUE;
7139 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7140 || i.op[source].regs->reg_type.bitfield.regsimd)
7142 if (i.types[dest].bitfield.zmmword
7143 || i.types[source].bitfield.zmmword)
7144 i.has_regzmm = TRUE;
7145 else if (i.types[dest].bitfield.ymmword
7146 || i.types[source].bitfield.ymmword)
7147 i.has_regymm = TRUE;
7149 i.has_regxmm = TRUE;
7151 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7153 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7155 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7157 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7162 i.rm.reg = i.op[source].regs->reg_num;
7163 i.rm.regmem = i.op[dest].regs->reg_num;
7164 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7166 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7168 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7170 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7173 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7175 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7178 add_prefix (LOCK_PREFIX_OPCODE);
7182 { /* If it's not 2 reg operands... */
7187 unsigned int fake_zero_displacement = 0;
7190 for (op = 0; op < i.operands; op++)
7191 if (operand_type_check (i.types[op], anymem))
7193 gas_assert (op < i.operands);
7195 if (i.tm.opcode_modifier.vecsib)
7197 if (i.index_reg->reg_num == RegIZ)
7200 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7203 i.sib.base = NO_BASE_REGISTER;
7204 i.sib.scale = i.log2_scale_factor;
7205 i.types[op].bitfield.disp8 = 0;
7206 i.types[op].bitfield.disp16 = 0;
7207 i.types[op].bitfield.disp64 = 0;
7208 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7210 /* Must be 32 bit */
7211 i.types[op].bitfield.disp32 = 1;
7212 i.types[op].bitfield.disp32s = 0;
7216 i.types[op].bitfield.disp32 = 0;
7217 i.types[op].bitfield.disp32s = 1;
7220 i.sib.index = i.index_reg->reg_num;
7221 if ((i.index_reg->reg_flags & RegRex) != 0)
7223 if ((i.index_reg->reg_flags & RegVRex) != 0)
7229 if (i.base_reg == 0)
7232 if (!i.disp_operands)
7233 fake_zero_displacement = 1;
7234 if (i.index_reg == 0)
7236 i386_operand_type newdisp;
7238 gas_assert (!i.tm.opcode_modifier.vecsib);
7239 /* Operand is just <disp> */
7240 if (flag_code == CODE_64BIT)
7242 /* 64bit mode overwrites the 32bit absolute
7243 addressing by RIP relative addressing and
7244 absolute addressing is encoded by one of the
7245 redundant SIB forms. */
7246 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7247 i.sib.base = NO_BASE_REGISTER;
7248 i.sib.index = NO_INDEX_REGISTER;
7249 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7251 else if ((flag_code == CODE_16BIT)
7252 ^ (i.prefix[ADDR_PREFIX] != 0))
7254 i.rm.regmem = NO_BASE_REGISTER_16;
7259 i.rm.regmem = NO_BASE_REGISTER;
7262 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7263 i.types[op] = operand_type_or (i.types[op], newdisp);
7265 else if (!i.tm.opcode_modifier.vecsib)
7267 /* !i.base_reg && i.index_reg */
7268 if (i.index_reg->reg_num == RegIZ)
7269 i.sib.index = NO_INDEX_REGISTER;
7271 i.sib.index = i.index_reg->reg_num;
7272 i.sib.base = NO_BASE_REGISTER;
7273 i.sib.scale = i.log2_scale_factor;
7274 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7275 i.types[op].bitfield.disp8 = 0;
7276 i.types[op].bitfield.disp16 = 0;
7277 i.types[op].bitfield.disp64 = 0;
7278 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7280 /* Must be 32 bit */
7281 i.types[op].bitfield.disp32 = 1;
7282 i.types[op].bitfield.disp32s = 0;
7286 i.types[op].bitfield.disp32 = 0;
7287 i.types[op].bitfield.disp32s = 1;
7289 if ((i.index_reg->reg_flags & RegRex) != 0)
7293 /* RIP addressing for 64bit mode. */
7294 else if (i.base_reg->reg_num == RegIP)
7296 gas_assert (!i.tm.opcode_modifier.vecsib);
7297 i.rm.regmem = NO_BASE_REGISTER;
7298 i.types[op].bitfield.disp8 = 0;
7299 i.types[op].bitfield.disp16 = 0;
7300 i.types[op].bitfield.disp32 = 0;
7301 i.types[op].bitfield.disp32s = 1;
7302 i.types[op].bitfield.disp64 = 0;
7303 i.flags[op] |= Operand_PCrel;
7304 if (! i.disp_operands)
7305 fake_zero_displacement = 1;
7307 else if (i.base_reg->reg_type.bitfield.word)
7309 gas_assert (!i.tm.opcode_modifier.vecsib);
7310 switch (i.base_reg->reg_num)
7313 if (i.index_reg == 0)
7315 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7316 i.rm.regmem = i.index_reg->reg_num - 6;
7320 if (i.index_reg == 0)
7323 if (operand_type_check (i.types[op], disp) == 0)
7325 /* fake (%bp) into 0(%bp) */
7326 i.types[op].bitfield.disp8 = 1;
7327 fake_zero_displacement = 1;
7330 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7331 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7333 default: /* (%si) -> 4 or (%di) -> 5 */
7334 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7336 i.rm.mode = mode_from_disp_size (i.types[op]);
7338 else /* i.base_reg and 32/64 bit mode */
7340 if (flag_code == CODE_64BIT
7341 && operand_type_check (i.types[op], disp))
7343 i.types[op].bitfield.disp16 = 0;
7344 i.types[op].bitfield.disp64 = 0;
7345 if (i.prefix[ADDR_PREFIX] == 0)
7347 i.types[op].bitfield.disp32 = 0;
7348 i.types[op].bitfield.disp32s = 1;
7352 i.types[op].bitfield.disp32 = 1;
7353 i.types[op].bitfield.disp32s = 0;
7357 if (!i.tm.opcode_modifier.vecsib)
7358 i.rm.regmem = i.base_reg->reg_num;
7359 if ((i.base_reg->reg_flags & RegRex) != 0)
7361 i.sib.base = i.base_reg->reg_num;
7362 /* x86-64 ignores REX prefix bit here to avoid decoder
7364 if (!(i.base_reg->reg_flags & RegRex)
7365 && (i.base_reg->reg_num == EBP_REG_NUM
7366 || i.base_reg->reg_num == ESP_REG_NUM))
7368 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7370 fake_zero_displacement = 1;
7371 i.types[op].bitfield.disp8 = 1;
7373 i.sib.scale = i.log2_scale_factor;
7374 if (i.index_reg == 0)
7376 gas_assert (!i.tm.opcode_modifier.vecsib);
7377 /* <disp>(%esp) becomes two byte modrm with no index
7378 register. We've already stored the code for esp
7379 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7380 Any base register besides %esp will not use the
7381 extra modrm byte. */
7382 i.sib.index = NO_INDEX_REGISTER;
7384 else if (!i.tm.opcode_modifier.vecsib)
7386 if (i.index_reg->reg_num == RegIZ)
7387 i.sib.index = NO_INDEX_REGISTER;
7389 i.sib.index = i.index_reg->reg_num;
7390 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7391 if ((i.index_reg->reg_flags & RegRex) != 0)
7396 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7397 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7401 if (!fake_zero_displacement
7405 fake_zero_displacement = 1;
7406 if (i.disp_encoding == disp_encoding_8bit)
7407 i.types[op].bitfield.disp8 = 1;
7409 i.types[op].bitfield.disp32 = 1;
7411 i.rm.mode = mode_from_disp_size (i.types[op]);
7415 if (fake_zero_displacement)
7417 /* Fakes a zero displacement assuming that i.types[op]
7418 holds the correct displacement size. */
7421 gas_assert (i.op[op].disps == 0);
7422 exp = &disp_expressions[i.disp_operands++];
7423 i.op[op].disps = exp;
7424 exp->X_op = O_constant;
7425 exp->X_add_number = 0;
7426 exp->X_add_symbol = (symbolS *) 0;
7427 exp->X_op_symbol = (symbolS *) 0;
7435 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7437 if (operand_type_check (i.types[0], imm))
7438 i.vex.register_specifier = NULL;
7441 /* VEX.vvvv encodes one of the sources when the first
7442 operand is not an immediate. */
7443 if (i.tm.opcode_modifier.vexw == VEXW0)
7444 i.vex.register_specifier = i.op[0].regs;
7446 i.vex.register_specifier = i.op[1].regs;
7449 /* Destination is a XMM register encoded in the ModRM.reg
7451 i.rm.reg = i.op[2].regs->reg_num;
7452 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7455 /* ModRM.rm and VEX.B encodes the other source. */
7456 if (!i.mem_operands)
7460 if (i.tm.opcode_modifier.vexw == VEXW0)
7461 i.rm.regmem = i.op[1].regs->reg_num;
7463 i.rm.regmem = i.op[0].regs->reg_num;
7465 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7469 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7471 i.vex.register_specifier = i.op[2].regs;
7472 if (!i.mem_operands)
7475 i.rm.regmem = i.op[1].regs->reg_num;
7476 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7480 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7481 (if any) based on i.tm.extension_opcode. Again, we must be
7482 careful to make sure that segment/control/debug/test/MMX
7483 registers are coded into the i.rm.reg field. */
7484 else if (i.reg_operands)
7487 unsigned int vex_reg = ~0;
7489 for (op = 0; op < i.operands; op++)
7491 if (i.types[op].bitfield.reg
7492 || i.types[op].bitfield.regbnd
7493 || i.types[op].bitfield.regmask
7494 || i.types[op].bitfield.sreg2
7495 || i.types[op].bitfield.sreg3
7496 || i.types[op].bitfield.control
7497 || i.types[op].bitfield.debug
7498 || i.types[op].bitfield.test)
7500 if (i.types[op].bitfield.regsimd)
7502 if (i.types[op].bitfield.zmmword)
7503 i.has_regzmm = TRUE;
7504 else if (i.types[op].bitfield.ymmword)
7505 i.has_regymm = TRUE;
7507 i.has_regxmm = TRUE;
7510 if (i.types[op].bitfield.regmmx)
7512 i.has_regmmx = TRUE;
7519 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7521 /* For instructions with VexNDS, the register-only
7522 source operand is encoded in VEX prefix. */
7523 gas_assert (mem != (unsigned int) ~0);
7528 gas_assert (op < i.operands);
7532 /* Check register-only source operand when two source
7533 operands are swapped. */
7534 if (!i.tm.operand_types[op].bitfield.baseindex
7535 && i.tm.operand_types[op + 1].bitfield.baseindex)
7539 gas_assert (mem == (vex_reg + 1)
7540 && op < i.operands);
7545 gas_assert (vex_reg < i.operands);
7549 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7551 /* For instructions with VexNDD, the register destination
7552 is encoded in VEX prefix. */
7553 if (i.mem_operands == 0)
7555 /* There is no memory operand. */
7556 gas_assert ((op + 2) == i.operands);
7561 /* There are only 2 non-immediate operands. */
7562 gas_assert (op < i.imm_operands + 2
7563 && i.operands == i.imm_operands + 2);
7564 vex_reg = i.imm_operands + 1;
7568 gas_assert (op < i.operands);
7570 if (vex_reg != (unsigned int) ~0)
7572 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7574 if ((!type->bitfield.reg
7575 || (!type->bitfield.dword && !type->bitfield.qword))
7576 && !type->bitfield.regsimd
7577 && !operand_type_equal (type, ®mask))
7580 i.vex.register_specifier = i.op[vex_reg].regs;
7583 /* Don't set OP operand twice. */
7586 /* If there is an extension opcode to put here, the
7587 register number must be put into the regmem field. */
7588 if (i.tm.extension_opcode != None)
7590 i.rm.regmem = i.op[op].regs->reg_num;
7591 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7593 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7598 i.rm.reg = i.op[op].regs->reg_num;
7599 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7601 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7606 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7607 must set it to 3 to indicate this is a register operand
7608 in the regmem field. */
7609 if (!i.mem_operands)
7613 /* Fill in i.rm.reg field with extension opcode (if any). */
7614 if (i.tm.extension_opcode != None)
7615 i.rm.reg = i.tm.extension_opcode;
7621 output_branch (void)
7627 relax_substateT subtype;
7631 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7632 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7635 if (i.prefix[DATA_PREFIX] != 0)
7641 /* Pentium4 branch hints. */
7642 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7643 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7648 if (i.prefix[REX_PREFIX] != 0)
7654 /* BND prefixed jump. */
7655 if (i.prefix[BND_PREFIX] != 0)
7657 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7661 if (i.prefixes != 0 && !intel_syntax)
7662 as_warn (_("skipping prefixes on this instruction"));
7664 /* It's always a symbol; End frag & setup for relax.
7665 Make sure there is enough room in this frag for the largest
7666 instruction we may generate in md_convert_frag. This is 2
7667 bytes for the opcode and room for the prefix and largest
7669 frag_grow (prefix + 2 + 4);
7670 /* Prefix and 1 opcode byte go in fr_fix. */
7671 p = frag_more (prefix + 1);
7672 if (i.prefix[DATA_PREFIX] != 0)
7673 *p++ = DATA_PREFIX_OPCODE;
7674 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7675 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7676 *p++ = i.prefix[SEG_PREFIX];
7677 if (i.prefix[REX_PREFIX] != 0)
7678 *p++ = i.prefix[REX_PREFIX];
7679 *p = i.tm.base_opcode;
7681 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7682 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7683 else if (cpu_arch_flags.bitfield.cpui386)
7684 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7686 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7689 sym = i.op[0].disps->X_add_symbol;
7690 off = i.op[0].disps->X_add_number;
7692 if (i.op[0].disps->X_op != O_constant
7693 && i.op[0].disps->X_op != O_symbol)
7695 /* Handle complex expressions. */
7696 sym = make_expr_symbol (i.op[0].disps);
7700 /* 1 possible extra opcode + 4 byte displacement go in var part.
7701 Pass reloc in fr_var. */
7702 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7705 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7706 /* Return TRUE iff PLT32 relocation should be used for branching to
7710 need_plt32_p (symbolS *s)
7712 /* PLT32 relocation is ELF only. */
7716 /* Since there is no need to prepare for PLT branch on x86-64, we
7717 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7718 be used as a marker for 32-bit PC-relative branches. */
7722 /* Weak or undefined symbol need PLT32 relocation. */
7723 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7726 /* Non-global symbol doesn't need PLT32 relocation. */
7727 if (! S_IS_EXTERNAL (s))
7730 /* Other global symbols need PLT32 relocation. NB: Symbol with
7731 non-default visibilities are treated as normal global symbol
7732 so that PLT32 relocation can be used as a marker for 32-bit
7733 PC-relative branches. It is useful for linker relaxation. */
7744 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7746 if (i.tm.opcode_modifier.jumpbyte)
7748 /* This is a loop or jecxz type instruction. */
7750 if (i.prefix[ADDR_PREFIX] != 0)
7752 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7755 /* Pentium4 branch hints. */
7756 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7757 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7759 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7768 if (flag_code == CODE_16BIT)
7771 if (i.prefix[DATA_PREFIX] != 0)
7773 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7783 if (i.prefix[REX_PREFIX] != 0)
7785 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7789 /* BND prefixed jump. */
7790 if (i.prefix[BND_PREFIX] != 0)
7792 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7796 if (i.prefixes != 0 && !intel_syntax)
7797 as_warn (_("skipping prefixes on this instruction"));
7799 p = frag_more (i.tm.opcode_length + size);
7800 switch (i.tm.opcode_length)
7803 *p++ = i.tm.base_opcode >> 8;
7806 *p++ = i.tm.base_opcode;
7812 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7814 && jump_reloc == NO_RELOC
7815 && need_plt32_p (i.op[0].disps->X_add_symbol))
7816 jump_reloc = BFD_RELOC_X86_64_PLT32;
7819 jump_reloc = reloc (size, 1, 1, jump_reloc);
7821 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7822 i.op[0].disps, 1, jump_reloc);
7824 /* All jumps handled here are signed, but don't use a signed limit
7825 check for 32 and 16 bit jumps as we want to allow wrap around at
7826 4G and 64k respectively. */
7828 fixP->fx_signed = 1;
7832 output_interseg_jump (void)
7840 if (flag_code == CODE_16BIT)
7844 if (i.prefix[DATA_PREFIX] != 0)
7850 if (i.prefix[REX_PREFIX] != 0)
7860 if (i.prefixes != 0 && !intel_syntax)
7861 as_warn (_("skipping prefixes on this instruction"));
7863 /* 1 opcode; 2 segment; offset */
7864 p = frag_more (prefix + 1 + 2 + size);
7866 if (i.prefix[DATA_PREFIX] != 0)
7867 *p++ = DATA_PREFIX_OPCODE;
7869 if (i.prefix[REX_PREFIX] != 0)
7870 *p++ = i.prefix[REX_PREFIX];
7872 *p++ = i.tm.base_opcode;
7873 if (i.op[1].imms->X_op == O_constant)
7875 offsetT n = i.op[1].imms->X_add_number;
7878 && !fits_in_unsigned_word (n)
7879 && !fits_in_signed_word (n))
7881 as_bad (_("16-bit jump out of range"));
7884 md_number_to_chars (p, n, size);
7887 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7888 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7889 if (i.op[0].imms->X_op != O_constant)
7890 as_bad (_("can't handle non absolute segment in `%s'"),
7892 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7895 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7900 asection *seg = now_seg;
7901 subsegT subseg = now_subseg;
7903 unsigned int alignment, align_size_1;
7904 unsigned int isa_1_descsz, feature_2_descsz, descsz;
7905 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
7906 unsigned int padding;
7908 if (!IS_ELF || !x86_used_note)
7911 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
7913 /* The .note.gnu.property section layout:
7915 Field Length Contents
7918 n_descsz 4 The note descriptor size
7919 n_type 4 NT_GNU_PROPERTY_TYPE_0
7921 n_desc n_descsz The program property array
7925 /* Create the .note.gnu.property section. */
7926 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
7927 bfd_set_section_flags (stdoutput, sec,
7934 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
7945 bfd_set_section_alignment (stdoutput, sec, alignment);
7946 elf_section_type (sec) = SHT_NOTE;
7948 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
7950 isa_1_descsz_raw = 4 + 4 + 4;
7951 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
7952 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
7954 feature_2_descsz_raw = isa_1_descsz;
7955 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
7957 feature_2_descsz_raw += 4 + 4 + 4;
7958 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
7959 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
7962 descsz = feature_2_descsz;
7963 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
7964 p = frag_more (4 + 4 + 4 + 4 + descsz);
7966 /* Write n_namsz. */
7967 md_number_to_chars (p, (valueT) 4, 4);
7969 /* Write n_descsz. */
7970 md_number_to_chars (p + 4, (valueT) descsz, 4);
7973 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
7976 memcpy (p + 4 * 3, "GNU", 4);
7978 /* Write 4-byte type. */
7979 md_number_to_chars (p + 4 * 4,
7980 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
7982 /* Write 4-byte data size. */
7983 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
7985 /* Write 4-byte data. */
7986 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
7988 /* Zero out paddings. */
7989 padding = isa_1_descsz - isa_1_descsz_raw;
7991 memset (p + 4 * 7, 0, padding);
7993 /* Write 4-byte type. */
7994 md_number_to_chars (p + isa_1_descsz + 4 * 4,
7995 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
7997 /* Write 4-byte data size. */
7998 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8000 /* Write 4-byte data. */
8001 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8002 (valueT) x86_feature_2_used, 4);
8004 /* Zero out paddings. */
8005 padding = feature_2_descsz - feature_2_descsz_raw;
8007 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8009 /* We probably can't restore the current segment, for there likely
8012 subseg_set (seg, subseg);
8019 fragS *insn_start_frag;
8020 offsetT insn_start_off;
8022 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8023 if (IS_ELF && x86_used_note)
8025 if (i.tm.cpu_flags.bitfield.cpucmov)
8026 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
8027 if (i.tm.cpu_flags.bitfield.cpusse)
8028 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
8029 if (i.tm.cpu_flags.bitfield.cpusse2)
8030 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
8031 if (i.tm.cpu_flags.bitfield.cpusse3)
8032 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8033 if (i.tm.cpu_flags.bitfield.cpussse3)
8034 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8035 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8036 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8037 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8038 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8039 if (i.tm.cpu_flags.bitfield.cpuavx)
8040 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8041 if (i.tm.cpu_flags.bitfield.cpuavx2)
8042 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8043 if (i.tm.cpu_flags.bitfield.cpufma)
8044 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8045 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8046 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8047 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8048 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8049 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8050 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8051 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8052 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8053 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8054 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8055 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8056 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8057 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8058 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8059 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8060 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8061 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8062 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8063 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8064 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8065 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8066 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8067 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8068 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8069 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8070 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8071 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8072 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
8074 if (i.tm.cpu_flags.bitfield.cpu8087
8075 || i.tm.cpu_flags.bitfield.cpu287
8076 || i.tm.cpu_flags.bitfield.cpu387
8077 || i.tm.cpu_flags.bitfield.cpu687
8078 || i.tm.cpu_flags.bitfield.cpufisttp)
8079 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8080 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8081 Xfence instructions. */
8082 if (i.tm.base_opcode != 0xf18
8083 && i.tm.base_opcode != 0xf0d
8084 && i.tm.base_opcode != 0xfae
8086 || i.tm.cpu_flags.bitfield.cpummx
8087 || i.tm.cpu_flags.bitfield.cpua3dnow
8088 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8089 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8091 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8093 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8095 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8096 if (i.tm.cpu_flags.bitfield.cpufxsr)
8097 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8098 if (i.tm.cpu_flags.bitfield.cpuxsave)
8099 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8100 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8101 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8102 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8103 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8107 /* Tie dwarf2 debug info to the address at the start of the insn.
8108 We can't do this after the insn has been output as the current
8109 frag may have been closed off. eg. by frag_var. */
8110 dwarf2_emit_insn (0);
8112 insn_start_frag = frag_now;
8113 insn_start_off = frag_now_fix ();
8116 if (i.tm.opcode_modifier.jump)
8118 else if (i.tm.opcode_modifier.jumpbyte
8119 || i.tm.opcode_modifier.jumpdword)
8121 else if (i.tm.opcode_modifier.jumpintersegment)
8122 output_interseg_jump ();
8125 /* Output normal instructions here. */
8129 unsigned int prefix;
8132 && i.tm.base_opcode == 0xfae
8134 && i.imm_operands == 1
8135 && (i.op[0].imms->X_add_number == 0xe8
8136 || i.op[0].imms->X_add_number == 0xf0
8137 || i.op[0].imms->X_add_number == 0xf8))
8139 /* Encode lfence, mfence, and sfence as
8140 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8141 offsetT val = 0x240483f0ULL;
8143 md_number_to_chars (p, val, 5);
8147 /* Some processors fail on LOCK prefix. This options makes
8148 assembler ignore LOCK prefix and serves as a workaround. */
8149 if (omit_lock_prefix)
8151 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8153 i.prefix[LOCK_PREFIX] = 0;
8156 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8157 don't need the explicit prefix. */
8158 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
8160 switch (i.tm.opcode_length)
8163 if (i.tm.base_opcode & 0xff000000)
8165 prefix = (i.tm.base_opcode >> 24) & 0xff;
8166 add_prefix (prefix);
8170 if ((i.tm.base_opcode & 0xff0000) != 0)
8172 prefix = (i.tm.base_opcode >> 16) & 0xff;
8173 if (!i.tm.cpu_flags.bitfield.cpupadlock
8174 || prefix != REPE_PREFIX_OPCODE
8175 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
8176 add_prefix (prefix);
8182 /* Check for pseudo prefixes. */
8183 as_bad_where (insn_start_frag->fr_file,
8184 insn_start_frag->fr_line,
8185 _("pseudo prefix without instruction"));
8191 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8192 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8193 R_X86_64_GOTTPOFF relocation so that linker can safely
8194 perform IE->LE optimization. */
8195 if (x86_elf_abi == X86_64_X32_ABI
8197 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8198 && i.prefix[REX_PREFIX] == 0)
8199 add_prefix (REX_OPCODE);
8202 /* The prefix bytes. */
8203 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8205 FRAG_APPEND_1_CHAR (*q);
8209 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8214 /* REX byte is encoded in VEX prefix. */
8218 FRAG_APPEND_1_CHAR (*q);
8221 /* There should be no other prefixes for instructions
8226 /* For EVEX instructions i.vrex should become 0 after
8227 build_evex_prefix. For VEX instructions upper 16 registers
8228 aren't available, so VREX should be 0. */
8231 /* Now the VEX prefix. */
8232 p = frag_more (i.vex.length);
8233 for (j = 0; j < i.vex.length; j++)
8234 p[j] = i.vex.bytes[j];
8237 /* Now the opcode; be careful about word order here! */
8238 if (i.tm.opcode_length == 1)
8240 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8244 switch (i.tm.opcode_length)
8248 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8249 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8253 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8263 /* Put out high byte first: can't use md_number_to_chars! */
8264 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8265 *p = i.tm.base_opcode & 0xff;
8268 /* Now the modrm byte and sib byte (if present). */
8269 if (i.tm.opcode_modifier.modrm)
8271 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8274 /* If i.rm.regmem == ESP (4)
8275 && i.rm.mode != (Register mode)
8277 ==> need second modrm byte. */
8278 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8280 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
8281 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8283 | i.sib.scale << 6));
8286 if (i.disp_operands)
8287 output_disp (insn_start_frag, insn_start_off);
8290 output_imm (insn_start_frag, insn_start_off);
8296 pi ("" /*line*/, &i);
8298 #endif /* DEBUG386 */
8301 /* Return the size of the displacement operand N. */
8304 disp_size (unsigned int n)
8308 if (i.types[n].bitfield.disp64)
8310 else if (i.types[n].bitfield.disp8)
8312 else if (i.types[n].bitfield.disp16)
8317 /* Return the size of the immediate operand N. */
8320 imm_size (unsigned int n)
8323 if (i.types[n].bitfield.imm64)
8325 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8327 else if (i.types[n].bitfield.imm16)
8333 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
8338 for (n = 0; n < i.operands; n++)
8340 if (operand_type_check (i.types[n], disp))
8342 if (i.op[n].disps->X_op == O_constant)
8344 int size = disp_size (n);
8345 offsetT val = i.op[n].disps->X_add_number;
8347 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8349 p = frag_more (size);
8350 md_number_to_chars (p, val, size);
8354 enum bfd_reloc_code_real reloc_type;
8355 int size = disp_size (n);
8356 int sign = i.types[n].bitfield.disp32s;
8357 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8360 /* We can't have 8 bit displacement here. */
8361 gas_assert (!i.types[n].bitfield.disp8);
8363 /* The PC relative address is computed relative
8364 to the instruction boundary, so in case immediate
8365 fields follows, we need to adjust the value. */
8366 if (pcrel && i.imm_operands)
8371 for (n1 = 0; n1 < i.operands; n1++)
8372 if (operand_type_check (i.types[n1], imm))
8374 /* Only one immediate is allowed for PC
8375 relative address. */
8376 gas_assert (sz == 0);
8378 i.op[n].disps->X_add_number -= sz;
8380 /* We should find the immediate. */
8381 gas_assert (sz != 0);
8384 p = frag_more (size);
8385 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8387 && GOT_symbol == i.op[n].disps->X_add_symbol
8388 && (((reloc_type == BFD_RELOC_32
8389 || reloc_type == BFD_RELOC_X86_64_32S
8390 || (reloc_type == BFD_RELOC_64
8392 && (i.op[n].disps->X_op == O_symbol
8393 || (i.op[n].disps->X_op == O_add
8394 && ((symbol_get_value_expression
8395 (i.op[n].disps->X_op_symbol)->X_op)
8397 || reloc_type == BFD_RELOC_32_PCREL))
8401 if (insn_start_frag == frag_now)
8402 add = (p - frag_now->fr_literal) - insn_start_off;
8407 add = insn_start_frag->fr_fix - insn_start_off;
8408 for (fr = insn_start_frag->fr_next;
8409 fr && fr != frag_now; fr = fr->fr_next)
8411 add += p - frag_now->fr_literal;
8416 reloc_type = BFD_RELOC_386_GOTPC;
8417 i.op[n].imms->X_add_number += add;
8419 else if (reloc_type == BFD_RELOC_64)
8420 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8422 /* Don't do the adjustment for x86-64, as there
8423 the pcrel addressing is relative to the _next_
8424 insn, and that is taken care of in other code. */
8425 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8427 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8428 size, i.op[n].disps, pcrel,
8430 /* Check for "call/jmp *mem", "mov mem, %reg",
8431 "test %reg, mem" and "binop mem, %reg" where binop
8432 is one of adc, add, and, cmp, or, sbb, sub, xor
8433 instructions without data prefix. Always generate
8434 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8435 if (i.prefix[DATA_PREFIX] == 0
8436 && (generate_relax_relocations
8439 && i.rm.regmem == 5))
8441 || (i.rm.mode == 0 && i.rm.regmem == 5))
8442 && ((i.operands == 1
8443 && i.tm.base_opcode == 0xff
8444 && (i.rm.reg == 2 || i.rm.reg == 4))
8446 && (i.tm.base_opcode == 0x8b
8447 || i.tm.base_opcode == 0x85
8448 || (i.tm.base_opcode & 0xc7) == 0x03))))
8452 fixP->fx_tcbit = i.rex != 0;
8454 && (i.base_reg->reg_num == RegIP))
8455 fixP->fx_tcbit2 = 1;
8458 fixP->fx_tcbit2 = 1;
8466 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8471 for (n = 0; n < i.operands; n++)
8473 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8474 if (i.rounding && (int) n == i.rounding->operand)
8477 if (operand_type_check (i.types[n], imm))
8479 if (i.op[n].imms->X_op == O_constant)
8481 int size = imm_size (n);
8484 val = offset_in_range (i.op[n].imms->X_add_number,
8486 p = frag_more (size);
8487 md_number_to_chars (p, val, size);
8491 /* Not absolute_section.
8492 Need a 32-bit fixup (don't support 8bit
8493 non-absolute imms). Try to support other
8495 enum bfd_reloc_code_real reloc_type;
8496 int size = imm_size (n);
8499 if (i.types[n].bitfield.imm32s
8500 && (i.suffix == QWORD_MNEM_SUFFIX
8501 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8506 p = frag_more (size);
8507 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8509 /* This is tough to explain. We end up with this one if we
8510 * have operands that look like
8511 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8512 * obtain the absolute address of the GOT, and it is strongly
8513 * preferable from a performance point of view to avoid using
8514 * a runtime relocation for this. The actual sequence of
8515 * instructions often look something like:
8520 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8522 * The call and pop essentially return the absolute address
8523 * of the label .L66 and store it in %ebx. The linker itself
8524 * will ultimately change the first operand of the addl so
8525 * that %ebx points to the GOT, but to keep things simple, the
8526 * .o file must have this operand set so that it generates not
8527 * the absolute address of .L66, but the absolute address of
8528 * itself. This allows the linker itself simply treat a GOTPC
8529 * relocation as asking for a pcrel offset to the GOT to be
8530 * added in, and the addend of the relocation is stored in the
8531 * operand field for the instruction itself.
8533 * Our job here is to fix the operand so that it would add
8534 * the correct offset so that %ebx would point to itself. The
8535 * thing that is tricky is that .-.L66 will point to the
8536 * beginning of the instruction, so we need to further modify
8537 * the operand so that it will point to itself. There are
8538 * other cases where you have something like:
8540 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8542 * and here no correction would be required. Internally in
8543 * the assembler we treat operands of this form as not being
8544 * pcrel since the '.' is explicitly mentioned, and I wonder
8545 * whether it would simplify matters to do it this way. Who
8546 * knows. In earlier versions of the PIC patches, the
8547 * pcrel_adjust field was used to store the correction, but
8548 * since the expression is not pcrel, I felt it would be
8549 * confusing to do it this way. */
8551 if ((reloc_type == BFD_RELOC_32
8552 || reloc_type == BFD_RELOC_X86_64_32S
8553 || reloc_type == BFD_RELOC_64)
8555 && GOT_symbol == i.op[n].imms->X_add_symbol
8556 && (i.op[n].imms->X_op == O_symbol
8557 || (i.op[n].imms->X_op == O_add
8558 && ((symbol_get_value_expression
8559 (i.op[n].imms->X_op_symbol)->X_op)
8564 if (insn_start_frag == frag_now)
8565 add = (p - frag_now->fr_literal) - insn_start_off;
8570 add = insn_start_frag->fr_fix - insn_start_off;
8571 for (fr = insn_start_frag->fr_next;
8572 fr && fr != frag_now; fr = fr->fr_next)
8574 add += p - frag_now->fr_literal;
8578 reloc_type = BFD_RELOC_386_GOTPC;
8580 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8582 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8583 i.op[n].imms->X_add_number += add;
8585 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8586 i.op[n].imms, 0, reloc_type);
8592 /* x86_cons_fix_new is called via the expression parsing code when a
8593 reloc is needed. We use this hook to get the correct .got reloc. */
8594 static int cons_sign = -1;
8597 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8598 expressionS *exp, bfd_reloc_code_real_type r)
8600 r = reloc (len, 0, cons_sign, r);
8603 if (exp->X_op == O_secrel)
8605 exp->X_op = O_symbol;
8606 r = BFD_RELOC_32_SECREL;
8610 fix_new_exp (frag, off, len, exp, 0, r);
8613 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8614 purpose of the `.dc.a' internal pseudo-op. */
8617 x86_address_bytes (void)
8619 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8621 return stdoutput->arch_info->bits_per_address / 8;
8624 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8626 # define lex_got(reloc, adjust, types) NULL
8628 /* Parse operands of the form
8629 <symbol>@GOTOFF+<nnn>
8630 and similar .plt or .got references.
8632 If we find one, set up the correct relocation in RELOC and copy the
8633 input string, minus the `@GOTOFF' into a malloc'd buffer for
8634 parsing by the calling routine. Return this buffer, and if ADJUST
8635 is non-null set it to the length of the string we removed from the
8636 input line. Otherwise return NULL. */
8638 lex_got (enum bfd_reloc_code_real *rel,
8640 i386_operand_type *types)
8642 /* Some of the relocations depend on the size of what field is to
8643 be relocated. But in our callers i386_immediate and i386_displacement
8644 we don't yet know the operand size (this will be set by insn
8645 matching). Hence we record the word32 relocation here,
8646 and adjust the reloc according to the real size in reloc(). */
8647 static const struct {
8650 const enum bfd_reloc_code_real rel[2];
8651 const i386_operand_type types64;
8653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8654 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8656 OPERAND_TYPE_IMM32_64 },
8658 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8659 BFD_RELOC_X86_64_PLTOFF64 },
8660 OPERAND_TYPE_IMM64 },
8661 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8662 BFD_RELOC_X86_64_PLT32 },
8663 OPERAND_TYPE_IMM32_32S_DISP32 },
8664 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8665 BFD_RELOC_X86_64_GOTPLT64 },
8666 OPERAND_TYPE_IMM64_DISP64 },
8667 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8668 BFD_RELOC_X86_64_GOTOFF64 },
8669 OPERAND_TYPE_IMM64_DISP64 },
8670 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8671 BFD_RELOC_X86_64_GOTPCREL },
8672 OPERAND_TYPE_IMM32_32S_DISP32 },
8673 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8674 BFD_RELOC_X86_64_TLSGD },
8675 OPERAND_TYPE_IMM32_32S_DISP32 },
8676 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8677 _dummy_first_bfd_reloc_code_real },
8678 OPERAND_TYPE_NONE },
8679 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8680 BFD_RELOC_X86_64_TLSLD },
8681 OPERAND_TYPE_IMM32_32S_DISP32 },
8682 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8683 BFD_RELOC_X86_64_GOTTPOFF },
8684 OPERAND_TYPE_IMM32_32S_DISP32 },
8685 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8686 BFD_RELOC_X86_64_TPOFF32 },
8687 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8688 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8689 _dummy_first_bfd_reloc_code_real },
8690 OPERAND_TYPE_NONE },
8691 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8692 BFD_RELOC_X86_64_DTPOFF32 },
8693 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8694 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8695 _dummy_first_bfd_reloc_code_real },
8696 OPERAND_TYPE_NONE },
8697 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8698 _dummy_first_bfd_reloc_code_real },
8699 OPERAND_TYPE_NONE },
8700 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8701 BFD_RELOC_X86_64_GOT32 },
8702 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8703 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8704 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8705 OPERAND_TYPE_IMM32_32S_DISP32 },
8706 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8707 BFD_RELOC_X86_64_TLSDESC_CALL },
8708 OPERAND_TYPE_IMM32_32S_DISP32 },
8713 #if defined (OBJ_MAYBE_ELF)
8718 for (cp = input_line_pointer; *cp != '@'; cp++)
8719 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8722 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8724 int len = gotrel[j].len;
8725 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8727 if (gotrel[j].rel[object_64bit] != 0)
8730 char *tmpbuf, *past_reloc;
8732 *rel = gotrel[j].rel[object_64bit];
8736 if (flag_code != CODE_64BIT)
8738 types->bitfield.imm32 = 1;
8739 types->bitfield.disp32 = 1;
8742 *types = gotrel[j].types64;
8745 if (j != 0 && GOT_symbol == NULL)
8746 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8748 /* The length of the first part of our input line. */
8749 first = cp - input_line_pointer;
8751 /* The second part goes from after the reloc token until
8752 (and including) an end_of_line char or comma. */
8753 past_reloc = cp + 1 + len;
8755 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8757 second = cp + 1 - past_reloc;
8759 /* Allocate and copy string. The trailing NUL shouldn't
8760 be necessary, but be safe. */
8761 tmpbuf = XNEWVEC (char, first + second + 2);
8762 memcpy (tmpbuf, input_line_pointer, first);
8763 if (second != 0 && *past_reloc != ' ')
8764 /* Replace the relocation token with ' ', so that
8765 errors like foo@GOTOFF1 will be detected. */
8766 tmpbuf[first++] = ' ';
8768 /* Increment length by 1 if the relocation token is
8773 memcpy (tmpbuf + first, past_reloc, second);
8774 tmpbuf[first + second] = '\0';
8778 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8779 gotrel[j].str, 1 << (5 + object_64bit));
8784 /* Might be a symbol version string. Don't as_bad here. */
8793 /* Parse operands of the form
8794 <symbol>@SECREL32+<nnn>
8796 If we find one, set up the correct relocation in RELOC and copy the
8797 input string, minus the `@SECREL32' into a malloc'd buffer for
8798 parsing by the calling routine. Return this buffer, and if ADJUST
8799 is non-null set it to the length of the string we removed from the
8800 input line. Otherwise return NULL.
8802 This function is copied from the ELF version above adjusted for PE targets. */
8805 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8806 int *adjust ATTRIBUTE_UNUSED,
8807 i386_operand_type *types)
8813 const enum bfd_reloc_code_real rel[2];
8814 const i386_operand_type types64;
8818 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8819 BFD_RELOC_32_SECREL },
8820 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8826 for (cp = input_line_pointer; *cp != '@'; cp++)
8827 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8830 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8832 int len = gotrel[j].len;
8834 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8836 if (gotrel[j].rel[object_64bit] != 0)
8839 char *tmpbuf, *past_reloc;
8841 *rel = gotrel[j].rel[object_64bit];
8847 if (flag_code != CODE_64BIT)
8849 types->bitfield.imm32 = 1;
8850 types->bitfield.disp32 = 1;
8853 *types = gotrel[j].types64;
8856 /* The length of the first part of our input line. */
8857 first = cp - input_line_pointer;
8859 /* The second part goes from after the reloc token until
8860 (and including) an end_of_line char or comma. */
8861 past_reloc = cp + 1 + len;
8863 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8865 second = cp + 1 - past_reloc;
8867 /* Allocate and copy string. The trailing NUL shouldn't
8868 be necessary, but be safe. */
8869 tmpbuf = XNEWVEC (char, first + second + 2);
8870 memcpy (tmpbuf, input_line_pointer, first);
8871 if (second != 0 && *past_reloc != ' ')
8872 /* Replace the relocation token with ' ', so that
8873 errors like foo@SECLREL321 will be detected. */
8874 tmpbuf[first++] = ' ';
8875 memcpy (tmpbuf + first, past_reloc, second);
8876 tmpbuf[first + second] = '\0';
8880 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8881 gotrel[j].str, 1 << (5 + object_64bit));
8886 /* Might be a symbol version string. Don't as_bad here. */
8892 bfd_reloc_code_real_type
8893 x86_cons (expressionS *exp, int size)
8895 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8897 intel_syntax = -intel_syntax;
8900 if (size == 4 || (object_64bit && size == 8))
8902 /* Handle @GOTOFF and the like in an expression. */
8904 char *gotfree_input_line;
8907 save = input_line_pointer;
8908 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8909 if (gotfree_input_line)
8910 input_line_pointer = gotfree_input_line;
8914 if (gotfree_input_line)
8916 /* expression () has merrily parsed up to the end of line,
8917 or a comma - in the wrong buffer. Transfer how far
8918 input_line_pointer has moved to the right buffer. */
8919 input_line_pointer = (save
8920 + (input_line_pointer - gotfree_input_line)
8922 free (gotfree_input_line);
8923 if (exp->X_op == O_constant
8924 || exp->X_op == O_absent
8925 || exp->X_op == O_illegal
8926 || exp->X_op == O_register
8927 || exp->X_op == O_big)
8929 char c = *input_line_pointer;
8930 *input_line_pointer = 0;
8931 as_bad (_("missing or invalid expression `%s'"), save);
8932 *input_line_pointer = c;
8934 else if ((got_reloc == BFD_RELOC_386_PLT32
8935 || got_reloc == BFD_RELOC_X86_64_PLT32)
8936 && exp->X_op != O_symbol)
8938 char c = *input_line_pointer;
8939 *input_line_pointer = 0;
8940 as_bad (_("invalid PLT expression `%s'"), save);
8941 *input_line_pointer = c;
8948 intel_syntax = -intel_syntax;
8951 i386_intel_simplify (exp);
8957 signed_cons (int size)
8959 if (flag_code == CODE_64BIT)
8967 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8974 if (exp.X_op == O_symbol)
8975 exp.X_op = O_secrel;
8977 emit_expr (&exp, 4);
8979 while (*input_line_pointer++ == ',');
8981 input_line_pointer--;
8982 demand_empty_rest_of_line ();
8986 /* Handle Vector operations. */
8989 check_VecOperations (char *op_string, char *op_end)
8991 const reg_entry *mask;
8996 && (op_end == NULL || op_string < op_end))
8999 if (*op_string == '{')
9003 /* Check broadcasts. */
9004 if (strncmp (op_string, "1to", 3) == 0)
9009 goto duplicated_vec_op;
9012 if (*op_string == '8')
9014 else if (*op_string == '4')
9016 else if (*op_string == '2')
9018 else if (*op_string == '1'
9019 && *(op_string+1) == '6')
9026 as_bad (_("Unsupported broadcast: `%s'"), saved);
9031 broadcast_op.type = bcst_type;
9032 broadcast_op.operand = this_operand;
9033 broadcast_op.bytes = 0;
9034 i.broadcast = &broadcast_op;
9036 /* Check masking operation. */
9037 else if ((mask = parse_register (op_string, &end_op)) != NULL)
9039 /* k0 can't be used for write mask. */
9040 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
9042 as_bad (_("`%s%s' can't be used for write mask"),
9043 register_prefix, mask->reg_name);
9049 mask_op.mask = mask;
9050 mask_op.zeroing = 0;
9051 mask_op.operand = this_operand;
9057 goto duplicated_vec_op;
9059 i.mask->mask = mask;
9061 /* Only "{z}" is allowed here. No need to check
9062 zeroing mask explicitly. */
9063 if (i.mask->operand != this_operand)
9065 as_bad (_("invalid write mask `%s'"), saved);
9072 /* Check zeroing-flag for masking operation. */
9073 else if (*op_string == 'z')
9077 mask_op.mask = NULL;
9078 mask_op.zeroing = 1;
9079 mask_op.operand = this_operand;
9084 if (i.mask->zeroing)
9087 as_bad (_("duplicated `%s'"), saved);
9091 i.mask->zeroing = 1;
9093 /* Only "{%k}" is allowed here. No need to check mask
9094 register explicitly. */
9095 if (i.mask->operand != this_operand)
9097 as_bad (_("invalid zeroing-masking `%s'"),
9106 goto unknown_vec_op;
9108 if (*op_string != '}')
9110 as_bad (_("missing `}' in `%s'"), saved);
9115 /* Strip whitespace since the addition of pseudo prefixes
9116 changed how the scrubber treats '{'. */
9117 if (is_space_char (*op_string))
9123 /* We don't know this one. */
9124 as_bad (_("unknown vector operation: `%s'"), saved);
9128 if (i.mask && i.mask->zeroing && !i.mask->mask)
9130 as_bad (_("zeroing-masking only allowed with write mask"));
9138 i386_immediate (char *imm_start)
9140 char *save_input_line_pointer;
9141 char *gotfree_input_line;
9144 i386_operand_type types;
9146 operand_type_set (&types, ~0);
9148 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9150 as_bad (_("at most %d immediate operands are allowed"),
9151 MAX_IMMEDIATE_OPERANDS);
9155 exp = &im_expressions[i.imm_operands++];
9156 i.op[this_operand].imms = exp;
9158 if (is_space_char (*imm_start))
9161 save_input_line_pointer = input_line_pointer;
9162 input_line_pointer = imm_start;
9164 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9165 if (gotfree_input_line)
9166 input_line_pointer = gotfree_input_line;
9168 exp_seg = expression (exp);
9172 /* Handle vector operations. */
9173 if (*input_line_pointer == '{')
9175 input_line_pointer = check_VecOperations (input_line_pointer,
9177 if (input_line_pointer == NULL)
9181 if (*input_line_pointer)
9182 as_bad (_("junk `%s' after expression"), input_line_pointer);
9184 input_line_pointer = save_input_line_pointer;
9185 if (gotfree_input_line)
9187 free (gotfree_input_line);
9189 if (exp->X_op == O_constant || exp->X_op == O_register)
9190 exp->X_op = O_illegal;
9193 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9197 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9198 i386_operand_type types, const char *imm_start)
9200 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
9203 as_bad (_("missing or invalid immediate expression `%s'"),
9207 else if (exp->X_op == O_constant)
9209 /* Size it properly later. */
9210 i.types[this_operand].bitfield.imm64 = 1;
9211 /* If not 64bit, sign extend val. */
9212 if (flag_code != CODE_64BIT
9213 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9215 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
9217 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9218 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
9219 && exp_seg != absolute_section
9220 && exp_seg != text_section
9221 && exp_seg != data_section
9222 && exp_seg != bss_section
9223 && exp_seg != undefined_section
9224 && !bfd_is_com_section (exp_seg))
9226 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9230 else if (!intel_syntax && exp_seg == reg_section)
9233 as_bad (_("illegal immediate register operand %s"), imm_start);
9238 /* This is an address. The size of the address will be
9239 determined later, depending on destination register,
9240 suffix, or the default for the section. */
9241 i.types[this_operand].bitfield.imm8 = 1;
9242 i.types[this_operand].bitfield.imm16 = 1;
9243 i.types[this_operand].bitfield.imm32 = 1;
9244 i.types[this_operand].bitfield.imm32s = 1;
9245 i.types[this_operand].bitfield.imm64 = 1;
9246 i.types[this_operand] = operand_type_and (i.types[this_operand],
9254 i386_scale (char *scale)
9257 char *save = input_line_pointer;
9259 input_line_pointer = scale;
9260 val = get_absolute_expression ();
9265 i.log2_scale_factor = 0;
9268 i.log2_scale_factor = 1;
9271 i.log2_scale_factor = 2;
9274 i.log2_scale_factor = 3;
9278 char sep = *input_line_pointer;
9280 *input_line_pointer = '\0';
9281 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9283 *input_line_pointer = sep;
9284 input_line_pointer = save;
9288 if (i.log2_scale_factor != 0 && i.index_reg == 0)
9290 as_warn (_("scale factor of %d without an index register"),
9291 1 << i.log2_scale_factor);
9292 i.log2_scale_factor = 0;
9294 scale = input_line_pointer;
9295 input_line_pointer = save;
9300 i386_displacement (char *disp_start, char *disp_end)
9304 char *save_input_line_pointer;
9305 char *gotfree_input_line;
9307 i386_operand_type bigdisp, types = anydisp;
9310 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9312 as_bad (_("at most %d displacement operands are allowed"),
9313 MAX_MEMORY_OPERANDS);
9317 operand_type_set (&bigdisp, 0);
9318 if ((i.types[this_operand].bitfield.jumpabsolute)
9319 || (!current_templates->start->opcode_modifier.jump
9320 && !current_templates->start->opcode_modifier.jumpdword))
9322 bigdisp.bitfield.disp32 = 1;
9323 override = (i.prefix[ADDR_PREFIX] != 0);
9324 if (flag_code == CODE_64BIT)
9328 bigdisp.bitfield.disp32s = 1;
9329 bigdisp.bitfield.disp64 = 1;
9332 else if ((flag_code == CODE_16BIT) ^ override)
9334 bigdisp.bitfield.disp32 = 0;
9335 bigdisp.bitfield.disp16 = 1;
9340 /* For PC-relative branches, the width of the displacement
9341 is dependent upon data size, not address size. */
9342 override = (i.prefix[DATA_PREFIX] != 0);
9343 if (flag_code == CODE_64BIT)
9345 if (override || i.suffix == WORD_MNEM_SUFFIX)
9346 bigdisp.bitfield.disp16 = 1;
9349 bigdisp.bitfield.disp32 = 1;
9350 bigdisp.bitfield.disp32s = 1;
9356 override = (i.suffix == (flag_code != CODE_16BIT
9358 : LONG_MNEM_SUFFIX));
9359 bigdisp.bitfield.disp32 = 1;
9360 if ((flag_code == CODE_16BIT) ^ override)
9362 bigdisp.bitfield.disp32 = 0;
9363 bigdisp.bitfield.disp16 = 1;
9367 i.types[this_operand] = operand_type_or (i.types[this_operand],
9370 exp = &disp_expressions[i.disp_operands];
9371 i.op[this_operand].disps = exp;
9373 save_input_line_pointer = input_line_pointer;
9374 input_line_pointer = disp_start;
9375 END_STRING_AND_SAVE (disp_end);
9377 #ifndef GCC_ASM_O_HACK
9378 #define GCC_ASM_O_HACK 0
9381 END_STRING_AND_SAVE (disp_end + 1);
9382 if (i.types[this_operand].bitfield.baseIndex
9383 && displacement_string_end[-1] == '+')
9385 /* This hack is to avoid a warning when using the "o"
9386 constraint within gcc asm statements.
9389 #define _set_tssldt_desc(n,addr,limit,type) \
9390 __asm__ __volatile__ ( \
9392 "movw %w1,2+%0\n\t" \
9394 "movb %b1,4+%0\n\t" \
9395 "movb %4,5+%0\n\t" \
9396 "movb $0,6+%0\n\t" \
9397 "movb %h1,7+%0\n\t" \
9399 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9401 This works great except that the output assembler ends
9402 up looking a bit weird if it turns out that there is
9403 no offset. You end up producing code that looks like:
9416 So here we provide the missing zero. */
9418 *displacement_string_end = '0';
9421 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9422 if (gotfree_input_line)
9423 input_line_pointer = gotfree_input_line;
9425 exp_seg = expression (exp);
9428 if (*input_line_pointer)
9429 as_bad (_("junk `%s' after expression"), input_line_pointer);
9431 RESTORE_END_STRING (disp_end + 1);
9433 input_line_pointer = save_input_line_pointer;
9434 if (gotfree_input_line)
9436 free (gotfree_input_line);
9438 if (exp->X_op == O_constant || exp->X_op == O_register)
9439 exp->X_op = O_illegal;
9442 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9444 RESTORE_END_STRING (disp_end);
9450 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9451 i386_operand_type types, const char *disp_start)
9453 i386_operand_type bigdisp;
9456 /* We do this to make sure that the section symbol is in
9457 the symbol table. We will ultimately change the relocation
9458 to be relative to the beginning of the section. */
9459 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9460 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9461 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9463 if (exp->X_op != O_symbol)
9466 if (S_IS_LOCAL (exp->X_add_symbol)
9467 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9468 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9469 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9470 exp->X_op = O_subtract;
9471 exp->X_op_symbol = GOT_symbol;
9472 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9473 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9474 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9475 i.reloc[this_operand] = BFD_RELOC_64;
9477 i.reloc[this_operand] = BFD_RELOC_32;
9480 else if (exp->X_op == O_absent
9481 || exp->X_op == O_illegal
9482 || exp->X_op == O_big)
9485 as_bad (_("missing or invalid displacement expression `%s'"),
9490 else if (flag_code == CODE_64BIT
9491 && !i.prefix[ADDR_PREFIX]
9492 && exp->X_op == O_constant)
9494 /* Since displacement is signed extended to 64bit, don't allow
9495 disp32 and turn off disp32s if they are out of range. */
9496 i.types[this_operand].bitfield.disp32 = 0;
9497 if (!fits_in_signed_long (exp->X_add_number))
9499 i.types[this_operand].bitfield.disp32s = 0;
9500 if (i.types[this_operand].bitfield.baseindex)
9502 as_bad (_("0x%lx out range of signed 32bit displacement"),
9503 (long) exp->X_add_number);
9509 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9510 else if (exp->X_op != O_constant
9511 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9512 && exp_seg != absolute_section
9513 && exp_seg != text_section
9514 && exp_seg != data_section
9515 && exp_seg != bss_section
9516 && exp_seg != undefined_section
9517 && !bfd_is_com_section (exp_seg))
9519 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9524 /* Check if this is a displacement only operand. */
9525 bigdisp = i.types[this_operand];
9526 bigdisp.bitfield.disp8 = 0;
9527 bigdisp.bitfield.disp16 = 0;
9528 bigdisp.bitfield.disp32 = 0;
9529 bigdisp.bitfield.disp32s = 0;
9530 bigdisp.bitfield.disp64 = 0;
9531 if (operand_type_all_zero (&bigdisp))
9532 i.types[this_operand] = operand_type_and (i.types[this_operand],
9538 /* Return the active addressing mode, taking address override and
9539 registers forming the address into consideration. Update the
9540 address override prefix if necessary. */
9542 static enum flag_code
9543 i386_addressing_mode (void)
9545 enum flag_code addr_mode;
9547 if (i.prefix[ADDR_PREFIX])
9548 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9551 addr_mode = flag_code;
9553 #if INFER_ADDR_PREFIX
9554 if (i.mem_operands == 0)
9556 /* Infer address prefix from the first memory operand. */
9557 const reg_entry *addr_reg = i.base_reg;
9559 if (addr_reg == NULL)
9560 addr_reg = i.index_reg;
9564 if (addr_reg->reg_type.bitfield.dword)
9565 addr_mode = CODE_32BIT;
9566 else if (flag_code != CODE_64BIT
9567 && addr_reg->reg_type.bitfield.word)
9568 addr_mode = CODE_16BIT;
9570 if (addr_mode != flag_code)
9572 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9574 /* Change the size of any displacement too. At most one
9575 of Disp16 or Disp32 is set.
9576 FIXME. There doesn't seem to be any real need for
9577 separate Disp16 and Disp32 flags. The same goes for
9578 Imm16 and Imm32. Removing them would probably clean
9579 up the code quite a lot. */
9580 if (flag_code != CODE_64BIT
9581 && (i.types[this_operand].bitfield.disp16
9582 || i.types[this_operand].bitfield.disp32))
9583 i.types[this_operand]
9584 = operand_type_xor (i.types[this_operand], disp16_32);
9594 /* Make sure the memory operand we've been dealt is valid.
9595 Return 1 on success, 0 on a failure. */
9598 i386_index_check (const char *operand_string)
9600 const char *kind = "base/index";
9601 enum flag_code addr_mode = i386_addressing_mode ();
9603 if (current_templates->start->opcode_modifier.isstring
9604 && !current_templates->start->opcode_modifier.immext
9605 && (current_templates->end[-1].opcode_modifier.isstring
9608 /* Memory operands of string insns are special in that they only allow
9609 a single register (rDI, rSI, or rBX) as their memory address. */
9610 const reg_entry *expected_reg;
9611 static const char *di_si[][2] =
9617 static const char *bx[] = { "ebx", "bx", "rbx" };
9619 kind = "string address";
9621 if (current_templates->start->opcode_modifier.repprefixok)
9623 i386_operand_type type = current_templates->end[-1].operand_types[0];
9625 if (!type.bitfield.baseindex
9626 || ((!i.mem_operands != !intel_syntax)
9627 && current_templates->end[-1].operand_types[1]
9628 .bitfield.baseindex))
9629 type = current_templates->end[-1].operand_types[1];
9630 expected_reg = hash_find (reg_hash,
9631 di_si[addr_mode][type.bitfield.esseg]);
9635 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9637 if (i.base_reg != expected_reg
9639 || operand_type_check (i.types[this_operand], disp))
9641 /* The second memory operand must have the same size as
9645 && !((addr_mode == CODE_64BIT
9646 && i.base_reg->reg_type.bitfield.qword)
9647 || (addr_mode == CODE_32BIT
9648 ? i.base_reg->reg_type.bitfield.dword
9649 : i.base_reg->reg_type.bitfield.word)))
9652 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9654 intel_syntax ? '[' : '(',
9656 expected_reg->reg_name,
9657 intel_syntax ? ']' : ')');
9664 as_bad (_("`%s' is not a valid %s expression"),
9665 operand_string, kind);
9670 if (addr_mode != CODE_16BIT)
9672 /* 32-bit/64-bit checks. */
9674 && ((addr_mode == CODE_64BIT
9675 ? !i.base_reg->reg_type.bitfield.qword
9676 : !i.base_reg->reg_type.bitfield.dword)
9677 || (i.index_reg && i.base_reg->reg_num == RegIP)
9678 || i.base_reg->reg_num == RegIZ))
9680 && !i.index_reg->reg_type.bitfield.xmmword
9681 && !i.index_reg->reg_type.bitfield.ymmword
9682 && !i.index_reg->reg_type.bitfield.zmmword
9683 && ((addr_mode == CODE_64BIT
9684 ? !i.index_reg->reg_type.bitfield.qword
9685 : !i.index_reg->reg_type.bitfield.dword)
9686 || !i.index_reg->reg_type.bitfield.baseindex)))
9689 /* bndmk, bndldx, and bndstx have special restrictions. */
9690 if (current_templates->start->base_opcode == 0xf30f1b
9691 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9693 /* They cannot use RIP-relative addressing. */
9694 if (i.base_reg && i.base_reg->reg_num == RegIP)
9696 as_bad (_("`%s' cannot be used here"), operand_string);
9700 /* bndldx and bndstx ignore their scale factor. */
9701 if (current_templates->start->base_opcode != 0xf30f1b
9702 && i.log2_scale_factor)
9703 as_warn (_("register scaling is being ignored here"));
9708 /* 16-bit checks. */
9710 && (!i.base_reg->reg_type.bitfield.word
9711 || !i.base_reg->reg_type.bitfield.baseindex))
9713 && (!i.index_reg->reg_type.bitfield.word
9714 || !i.index_reg->reg_type.bitfield.baseindex
9716 && i.base_reg->reg_num < 6
9717 && i.index_reg->reg_num >= 6
9718 && i.log2_scale_factor == 0))))
9725 /* Handle vector immediates. */
9728 RC_SAE_immediate (const char *imm_start)
9730 unsigned int match_found, j;
9731 const char *pstr = imm_start;
9739 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9741 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9745 rc_op.type = RC_NamesTable[j].type;
9746 rc_op.operand = this_operand;
9747 i.rounding = &rc_op;
9751 as_bad (_("duplicated `%s'"), imm_start);
9754 pstr += RC_NamesTable[j].len;
9764 as_bad (_("Missing '}': '%s'"), imm_start);
9767 /* RC/SAE immediate string should contain nothing more. */;
9770 as_bad (_("Junk after '}': '%s'"), imm_start);
9774 exp = &im_expressions[i.imm_operands++];
9775 i.op[this_operand].imms = exp;
9777 exp->X_op = O_constant;
9778 exp->X_add_number = 0;
9779 exp->X_add_symbol = (symbolS *) 0;
9780 exp->X_op_symbol = (symbolS *) 0;
9782 i.types[this_operand].bitfield.imm8 = 1;
9786 /* Only string instructions can have a second memory operand, so
9787 reduce current_templates to just those if it contains any. */
9789 maybe_adjust_templates (void)
9791 const insn_template *t;
9793 gas_assert (i.mem_operands == 1);
9795 for (t = current_templates->start; t < current_templates->end; ++t)
9796 if (t->opcode_modifier.isstring)
9799 if (t < current_templates->end)
9801 static templates aux_templates;
9802 bfd_boolean recheck;
9804 aux_templates.start = t;
9805 for (; t < current_templates->end; ++t)
9806 if (!t->opcode_modifier.isstring)
9808 aux_templates.end = t;
9810 /* Determine whether to re-check the first memory operand. */
9811 recheck = (aux_templates.start != current_templates->start
9812 || t != current_templates->end);
9814 current_templates = &aux_templates;
9819 if (i.memop1_string != NULL
9820 && i386_index_check (i.memop1_string) == 0)
9829 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
9833 i386_att_operand (char *operand_string)
9837 char *op_string = operand_string;
9839 if (is_space_char (*op_string))
9842 /* We check for an absolute prefix (differentiating,
9843 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
9844 if (*op_string == ABSOLUTE_PREFIX)
9847 if (is_space_char (*op_string))
9849 i.types[this_operand].bitfield.jumpabsolute = 1;
9852 /* Check if operand is a register. */
9853 if ((r = parse_register (op_string, &end_op)) != NULL)
9855 i386_operand_type temp;
9857 /* Check for a segment override by searching for ':' after a
9858 segment register. */
9860 if (is_space_char (*op_string))
9862 if (*op_string == ':'
9863 && (r->reg_type.bitfield.sreg2
9864 || r->reg_type.bitfield.sreg3))
9869 i.seg[i.mem_operands] = &es;
9872 i.seg[i.mem_operands] = &cs;
9875 i.seg[i.mem_operands] = &ss;
9878 i.seg[i.mem_operands] = &ds;
9881 i.seg[i.mem_operands] = &fs;
9884 i.seg[i.mem_operands] = &gs;
9888 /* Skip the ':' and whitespace. */
9890 if (is_space_char (*op_string))
9893 if (!is_digit_char (*op_string)
9894 && !is_identifier_char (*op_string)
9895 && *op_string != '('
9896 && *op_string != ABSOLUTE_PREFIX)
9898 as_bad (_("bad memory operand `%s'"), op_string);
9901 /* Handle case of %es:*foo. */
9902 if (*op_string == ABSOLUTE_PREFIX)
9905 if (is_space_char (*op_string))
9907 i.types[this_operand].bitfield.jumpabsolute = 1;
9909 goto do_memory_reference;
9912 /* Handle vector operations. */
9913 if (*op_string == '{')
9915 op_string = check_VecOperations (op_string, NULL);
9916 if (op_string == NULL)
9922 as_bad (_("junk `%s' after register"), op_string);
9926 temp.bitfield.baseindex = 0;
9927 i.types[this_operand] = operand_type_or (i.types[this_operand],
9929 i.types[this_operand].bitfield.unspecified = 0;
9930 i.op[this_operand].regs = r;
9933 else if (*op_string == REGISTER_PREFIX)
9935 as_bad (_("bad register name `%s'"), op_string);
9938 else if (*op_string == IMMEDIATE_PREFIX)
9941 if (i.types[this_operand].bitfield.jumpabsolute)
9943 as_bad (_("immediate operand illegal with absolute jump"));
9946 if (!i386_immediate (op_string))
9949 else if (RC_SAE_immediate (operand_string))
9951 /* If it is a RC or SAE immediate, do nothing. */
9954 else if (is_digit_char (*op_string)
9955 || is_identifier_char (*op_string)
9956 || *op_string == '"'
9957 || *op_string == '(')
9959 /* This is a memory reference of some sort. */
9962 /* Start and end of displacement string expression (if found). */
9963 char *displacement_string_start;
9964 char *displacement_string_end;
9967 do_memory_reference:
9968 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9970 if ((i.mem_operands == 1
9971 && !current_templates->start->opcode_modifier.isstring)
9972 || i.mem_operands == 2)
9974 as_bad (_("too many memory references for `%s'"),
9975 current_templates->start->name);
9979 /* Check for base index form. We detect the base index form by
9980 looking for an ')' at the end of the operand, searching
9981 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9983 base_string = op_string + strlen (op_string);
9985 /* Handle vector operations. */
9986 vop_start = strchr (op_string, '{');
9987 if (vop_start && vop_start < base_string)
9989 if (check_VecOperations (vop_start, base_string) == NULL)
9991 base_string = vop_start;
9995 if (is_space_char (*base_string))
9998 /* If we only have a displacement, set-up for it to be parsed later. */
9999 displacement_string_start = op_string;
10000 displacement_string_end = base_string + 1;
10002 if (*base_string == ')')
10005 unsigned int parens_balanced = 1;
10006 /* We've already checked that the number of left & right ()'s are
10007 equal, so this loop will not be infinite. */
10011 if (*base_string == ')')
10013 if (*base_string == '(')
10016 while (parens_balanced);
10018 temp_string = base_string;
10020 /* Skip past '(' and whitespace. */
10022 if (is_space_char (*base_string))
10025 if (*base_string == ','
10026 || ((i.base_reg = parse_register (base_string, &end_op))
10029 displacement_string_end = temp_string;
10031 i.types[this_operand].bitfield.baseindex = 1;
10035 base_string = end_op;
10036 if (is_space_char (*base_string))
10040 /* There may be an index reg or scale factor here. */
10041 if (*base_string == ',')
10044 if (is_space_char (*base_string))
10047 if ((i.index_reg = parse_register (base_string, &end_op))
10050 base_string = end_op;
10051 if (is_space_char (*base_string))
10053 if (*base_string == ',')
10056 if (is_space_char (*base_string))
10059 else if (*base_string != ')')
10061 as_bad (_("expecting `,' or `)' "
10062 "after index register in `%s'"),
10067 else if (*base_string == REGISTER_PREFIX)
10069 end_op = strchr (base_string, ',');
10072 as_bad (_("bad register name `%s'"), base_string);
10076 /* Check for scale factor. */
10077 if (*base_string != ')')
10079 char *end_scale = i386_scale (base_string);
10084 base_string = end_scale;
10085 if (is_space_char (*base_string))
10087 if (*base_string != ')')
10089 as_bad (_("expecting `)' "
10090 "after scale factor in `%s'"),
10095 else if (!i.index_reg)
10097 as_bad (_("expecting index register or scale factor "
10098 "after `,'; got '%c'"),
10103 else if (*base_string != ')')
10105 as_bad (_("expecting `,' or `)' "
10106 "after base register in `%s'"),
10111 else if (*base_string == REGISTER_PREFIX)
10113 end_op = strchr (base_string, ',');
10116 as_bad (_("bad register name `%s'"), base_string);
10121 /* If there's an expression beginning the operand, parse it,
10122 assuming displacement_string_start and
10123 displacement_string_end are meaningful. */
10124 if (displacement_string_start != displacement_string_end)
10126 if (!i386_displacement (displacement_string_start,
10127 displacement_string_end))
10131 /* Special case for (%dx) while doing input/output op. */
10133 && i.base_reg->reg_type.bitfield.inoutportreg
10134 && i.index_reg == 0
10135 && i.log2_scale_factor == 0
10136 && i.seg[i.mem_operands] == 0
10137 && !operand_type_check (i.types[this_operand], disp))
10139 i.types[this_operand] = i.base_reg->reg_type;
10143 if (i386_index_check (operand_string) == 0)
10145 i.flags[this_operand] |= Operand_Mem;
10146 if (i.mem_operands == 0)
10147 i.memop1_string = xstrdup (operand_string);
10152 /* It's not a memory operand; argh! */
10153 as_bad (_("invalid char %s beginning operand %d `%s'"),
10154 output_invalid (*op_string),
10159 return 1; /* Normal return. */
10162 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10163 that an rs_machine_dependent frag may reach. */
10166 i386_frag_max_var (fragS *frag)
10168 /* The only relaxable frags are for jumps.
10169 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10170 gas_assert (frag->fr_type == rs_machine_dependent);
10171 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10176 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
10178 /* STT_GNU_IFUNC symbol must go through PLT. */
10179 if ((symbol_get_bfdsym (fr_symbol)->flags
10180 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10183 if (!S_IS_EXTERNAL (fr_symbol))
10184 /* Symbol may be weak or local. */
10185 return !S_IS_WEAK (fr_symbol);
10187 /* Global symbols with non-default visibility can't be preempted. */
10188 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10191 if (fr_var != NO_RELOC)
10192 switch ((enum bfd_reloc_code_real) fr_var)
10194 case BFD_RELOC_386_PLT32:
10195 case BFD_RELOC_X86_64_PLT32:
10196 /* Symbol with PLT relocation may be preempted. */
10202 /* Global symbols with default visibility in a shared library may be
10203 preempted by another definition. */
10208 /* md_estimate_size_before_relax()
10210 Called just before relax() for rs_machine_dependent frags. The x86
10211 assembler uses these frags to handle variable size jump
10214 Any symbol that is now undefined will not become defined.
10215 Return the correct fr_subtype in the frag.
10216 Return the initial "guess for variable size of frag" to caller.
10217 The guess is actually the growth beyond the fixed part. Whatever
10218 we do to grow the fixed or variable part contributes to our
10222 md_estimate_size_before_relax (fragS *fragP, segT segment)
10224 /* We've already got fragP->fr_subtype right; all we have to do is
10225 check for un-relaxable symbols. On an ELF system, we can't relax
10226 an externally visible symbol, because it may be overridden by a
10228 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
10229 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10231 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10234 #if defined (OBJ_COFF) && defined (TE_PE)
10235 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
10236 && S_IS_WEAK (fragP->fr_symbol))
10240 /* Symbol is undefined in this segment, or we need to keep a
10241 reloc so that weak symbols can be overridden. */
10242 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
10243 enum bfd_reloc_code_real reloc_type;
10244 unsigned char *opcode;
10247 if (fragP->fr_var != NO_RELOC)
10248 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
10249 else if (size == 2)
10250 reloc_type = BFD_RELOC_16_PCREL;
10251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10252 else if (need_plt32_p (fragP->fr_symbol))
10253 reloc_type = BFD_RELOC_X86_64_PLT32;
10256 reloc_type = BFD_RELOC_32_PCREL;
10258 old_fr_fix = fragP->fr_fix;
10259 opcode = (unsigned char *) fragP->fr_opcode;
10261 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
10264 /* Make jmp (0xeb) a (d)word displacement jump. */
10266 fragP->fr_fix += size;
10267 fix_new (fragP, old_fr_fix, size,
10269 fragP->fr_offset, 1,
10275 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
10277 /* Negate the condition, and branch past an
10278 unconditional jump. */
10281 /* Insert an unconditional jump. */
10283 /* We added two extra opcode bytes, and have a two byte
10285 fragP->fr_fix += 2 + 2;
10286 fix_new (fragP, old_fr_fix + 2, 2,
10288 fragP->fr_offset, 1,
10292 /* Fall through. */
10295 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10299 fragP->fr_fix += 1;
10300 fixP = fix_new (fragP, old_fr_fix, 1,
10302 fragP->fr_offset, 1,
10303 BFD_RELOC_8_PCREL);
10304 fixP->fx_signed = 1;
10308 /* This changes the byte-displacement jump 0x7N
10309 to the (d)word-displacement jump 0x0f,0x8N. */
10310 opcode[1] = opcode[0] + 0x10;
10311 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10312 /* We've added an opcode byte. */
10313 fragP->fr_fix += 1 + size;
10314 fix_new (fragP, old_fr_fix + 1, size,
10316 fragP->fr_offset, 1,
10321 BAD_CASE (fragP->fr_subtype);
10325 return fragP->fr_fix - old_fr_fix;
10328 /* Guess size depending on current relax state. Initially the relax
10329 state will correspond to a short jump and we return 1, because
10330 the variable part of the frag (the branch offset) is one byte
10331 long. However, we can relax a section more than once and in that
10332 case we must either set fr_subtype back to the unrelaxed state,
10333 or return the value for the appropriate branch. */
10334 return md_relax_table[fragP->fr_subtype].rlx_length;
10337 /* Called after relax() is finished.
10339 In: Address of frag.
10340 fr_type == rs_machine_dependent.
10341 fr_subtype is what the address relaxed to.
10343 Out: Any fixSs and constants are set up.
10344 Caller will turn frag into a ".space 0". */
10347 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10350 unsigned char *opcode;
10351 unsigned char *where_to_put_displacement = NULL;
10352 offsetT target_address;
10353 offsetT opcode_address;
10354 unsigned int extension = 0;
10355 offsetT displacement_from_opcode_start;
10357 opcode = (unsigned char *) fragP->fr_opcode;
10359 /* Address we want to reach in file space. */
10360 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10362 /* Address opcode resides at in file space. */
10363 opcode_address = fragP->fr_address + fragP->fr_fix;
10365 /* Displacement from opcode start to fill into instruction. */
10366 displacement_from_opcode_start = target_address - opcode_address;
10368 if ((fragP->fr_subtype & BIG) == 0)
10370 /* Don't have to change opcode. */
10371 extension = 1; /* 1 opcode + 1 displacement */
10372 where_to_put_displacement = &opcode[1];
10376 if (no_cond_jump_promotion
10377 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10378 as_warn_where (fragP->fr_file, fragP->fr_line,
10379 _("long jump required"));
10381 switch (fragP->fr_subtype)
10383 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10384 extension = 4; /* 1 opcode + 4 displacement */
10386 where_to_put_displacement = &opcode[1];
10389 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10390 extension = 2; /* 1 opcode + 2 displacement */
10392 where_to_put_displacement = &opcode[1];
10395 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10396 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10397 extension = 5; /* 2 opcode + 4 displacement */
10398 opcode[1] = opcode[0] + 0x10;
10399 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10400 where_to_put_displacement = &opcode[2];
10403 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10404 extension = 3; /* 2 opcode + 2 displacement */
10405 opcode[1] = opcode[0] + 0x10;
10406 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10407 where_to_put_displacement = &opcode[2];
10410 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10415 where_to_put_displacement = &opcode[3];
10419 BAD_CASE (fragP->fr_subtype);
10424 /* If size if less then four we are sure that the operand fits,
10425 but if it's 4, then it could be that the displacement is larger
10427 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10429 && ((addressT) (displacement_from_opcode_start - extension
10430 + ((addressT) 1 << 31))
10431 > (((addressT) 2 << 31) - 1)))
10433 as_bad_where (fragP->fr_file, fragP->fr_line,
10434 _("jump target out of range"));
10435 /* Make us emit 0. */
10436 displacement_from_opcode_start = extension;
10438 /* Now put displacement after opcode. */
10439 md_number_to_chars ((char *) where_to_put_displacement,
10440 (valueT) (displacement_from_opcode_start - extension),
10441 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10442 fragP->fr_fix += extension;
10445 /* Apply a fixup (fixP) to segment data, once it has been determined
10446 by our caller that we have all the info we need to fix it up.
10448 Parameter valP is the pointer to the value of the bits.
10450 On the 386, immediates, displacements, and data pointers are all in
10451 the same (little-endian) format, so we don't need to care about which
10452 we are handling. */
10455 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10457 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10458 valueT value = *valP;
10460 #if !defined (TE_Mach)
10461 if (fixP->fx_pcrel)
10463 switch (fixP->fx_r_type)
10469 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10472 case BFD_RELOC_X86_64_32S:
10473 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10476 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10479 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10484 if (fixP->fx_addsy != NULL
10485 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10486 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10487 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10488 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10489 && !use_rela_relocations)
10491 /* This is a hack. There should be a better way to handle this.
10492 This covers for the fact that bfd_install_relocation will
10493 subtract the current location (for partial_inplace, PC relative
10494 relocations); see more below. */
10498 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10501 value += fixP->fx_where + fixP->fx_frag->fr_address;
10503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10506 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10508 if ((sym_seg == seg
10509 || (symbol_section_p (fixP->fx_addsy)
10510 && sym_seg != absolute_section))
10511 && !generic_force_reloc (fixP))
10513 /* Yes, we add the values in twice. This is because
10514 bfd_install_relocation subtracts them out again. I think
10515 bfd_install_relocation is broken, but I don't dare change
10517 value += fixP->fx_where + fixP->fx_frag->fr_address;
10521 #if defined (OBJ_COFF) && defined (TE_PE)
10522 /* For some reason, the PE format does not store a
10523 section address offset for a PC relative symbol. */
10524 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10525 || S_IS_WEAK (fixP->fx_addsy))
10526 value += md_pcrel_from (fixP);
10529 #if defined (OBJ_COFF) && defined (TE_PE)
10530 if (fixP->fx_addsy != NULL
10531 && S_IS_WEAK (fixP->fx_addsy)
10532 /* PR 16858: Do not modify weak function references. */
10533 && ! fixP->fx_pcrel)
10535 #if !defined (TE_PEP)
10536 /* For x86 PE weak function symbols are neither PC-relative
10537 nor do they set S_IS_FUNCTION. So the only reliable way
10538 to detect them is to check the flags of their containing
10540 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10541 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10545 value -= S_GET_VALUE (fixP->fx_addsy);
10549 /* Fix a few things - the dynamic linker expects certain values here,
10550 and we must not disappoint it. */
10551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10552 if (IS_ELF && fixP->fx_addsy)
10553 switch (fixP->fx_r_type)
10555 case BFD_RELOC_386_PLT32:
10556 case BFD_RELOC_X86_64_PLT32:
10557 /* Make the jump instruction point to the address of the operand.
10558 At runtime we merely add the offset to the actual PLT entry.
10559 NB: Subtract the offset size only for jump instructions. */
10560 if (fixP->fx_pcrel)
10564 case BFD_RELOC_386_TLS_GD:
10565 case BFD_RELOC_386_TLS_LDM:
10566 case BFD_RELOC_386_TLS_IE_32:
10567 case BFD_RELOC_386_TLS_IE:
10568 case BFD_RELOC_386_TLS_GOTIE:
10569 case BFD_RELOC_386_TLS_GOTDESC:
10570 case BFD_RELOC_X86_64_TLSGD:
10571 case BFD_RELOC_X86_64_TLSLD:
10572 case BFD_RELOC_X86_64_GOTTPOFF:
10573 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10574 value = 0; /* Fully resolved at runtime. No addend. */
10576 case BFD_RELOC_386_TLS_LE:
10577 case BFD_RELOC_386_TLS_LDO_32:
10578 case BFD_RELOC_386_TLS_LE_32:
10579 case BFD_RELOC_X86_64_DTPOFF32:
10580 case BFD_RELOC_X86_64_DTPOFF64:
10581 case BFD_RELOC_X86_64_TPOFF32:
10582 case BFD_RELOC_X86_64_TPOFF64:
10583 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10586 case BFD_RELOC_386_TLS_DESC_CALL:
10587 case BFD_RELOC_X86_64_TLSDESC_CALL:
10588 value = 0; /* Fully resolved at runtime. No addend. */
10589 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10593 case BFD_RELOC_VTABLE_INHERIT:
10594 case BFD_RELOC_VTABLE_ENTRY:
10601 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10603 #endif /* !defined (TE_Mach) */
10605 /* Are we finished with this relocation now? */
10606 if (fixP->fx_addsy == NULL)
10608 #if defined (OBJ_COFF) && defined (TE_PE)
10609 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10612 /* Remember value for tc_gen_reloc. */
10613 fixP->fx_addnumber = value;
10614 /* Clear out the frag for now. */
10618 else if (use_rela_relocations)
10620 fixP->fx_no_overflow = 1;
10621 /* Remember value for tc_gen_reloc. */
10622 fixP->fx_addnumber = value;
10626 md_number_to_chars (p, value, fixP->fx_size);
10630 md_atof (int type, char *litP, int *sizeP)
10632 /* This outputs the LITTLENUMs in REVERSE order;
10633 in accord with the bigendian 386. */
10634 return ieee_md_atof (type, litP, sizeP, FALSE);
10637 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10640 output_invalid (int c)
10643 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10646 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10647 "(0x%x)", (unsigned char) c);
10648 return output_invalid_buf;
10651 /* REG_STRING starts *before* REGISTER_PREFIX. */
10653 static const reg_entry *
10654 parse_real_register (char *reg_string, char **end_op)
10656 char *s = reg_string;
10658 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10659 const reg_entry *r;
10661 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10662 if (*s == REGISTER_PREFIX)
10665 if (is_space_char (*s))
10668 p = reg_name_given;
10669 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10671 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10672 return (const reg_entry *) NULL;
10676 /* For naked regs, make sure that we are not dealing with an identifier.
10677 This prevents confusing an identifier like `eax_var' with register
10679 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10680 return (const reg_entry *) NULL;
10684 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10686 /* Handle floating point regs, allowing spaces in the (i) part. */
10687 if (r == i386_regtab /* %st is first entry of table */)
10689 if (!cpu_arch_flags.bitfield.cpu8087
10690 && !cpu_arch_flags.bitfield.cpu287
10691 && !cpu_arch_flags.bitfield.cpu387)
10692 return (const reg_entry *) NULL;
10694 if (is_space_char (*s))
10699 if (is_space_char (*s))
10701 if (*s >= '0' && *s <= '7')
10703 int fpr = *s - '0';
10705 if (is_space_char (*s))
10710 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10715 /* We have "%st(" then garbage. */
10716 return (const reg_entry *) NULL;
10720 if (r == NULL || allow_pseudo_reg)
10723 if (operand_type_all_zero (&r->reg_type))
10724 return (const reg_entry *) NULL;
10726 if ((r->reg_type.bitfield.dword
10727 || r->reg_type.bitfield.sreg3
10728 || r->reg_type.bitfield.control
10729 || r->reg_type.bitfield.debug
10730 || r->reg_type.bitfield.test)
10731 && !cpu_arch_flags.bitfield.cpui386)
10732 return (const reg_entry *) NULL;
10734 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10735 return (const reg_entry *) NULL;
10737 if (!cpu_arch_flags.bitfield.cpuavx512f)
10739 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10740 return (const reg_entry *) NULL;
10742 if (!cpu_arch_flags.bitfield.cpuavx)
10744 if (r->reg_type.bitfield.ymmword)
10745 return (const reg_entry *) NULL;
10747 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10748 return (const reg_entry *) NULL;
10752 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10753 return (const reg_entry *) NULL;
10755 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10756 if (!allow_index_reg && r->reg_num == RegIZ)
10757 return (const reg_entry *) NULL;
10759 /* Upper 16 vector registers are only available with VREX in 64bit
10760 mode, and require EVEX encoding. */
10761 if (r->reg_flags & RegVRex)
10763 if (!cpu_arch_flags.bitfield.cpuavx512f
10764 || flag_code != CODE_64BIT)
10765 return (const reg_entry *) NULL;
10767 i.vec_encoding = vex_encoding_evex;
10770 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10771 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10772 && flag_code != CODE_64BIT)
10773 return (const reg_entry *) NULL;
10775 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10776 return (const reg_entry *) NULL;
10781 /* REG_STRING starts *before* REGISTER_PREFIX. */
10783 static const reg_entry *
10784 parse_register (char *reg_string, char **end_op)
10786 const reg_entry *r;
10788 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10789 r = parse_real_register (reg_string, end_op);
10794 char *save = input_line_pointer;
10798 input_line_pointer = reg_string;
10799 c = get_symbol_name (®_string);
10800 symbolP = symbol_find (reg_string);
10801 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10803 const expressionS *e = symbol_get_value_expression (symbolP);
10805 know (e->X_op == O_register);
10806 know (e->X_add_number >= 0
10807 && (valueT) e->X_add_number < i386_regtab_size);
10808 r = i386_regtab + e->X_add_number;
10809 if ((r->reg_flags & RegVRex))
10810 i.vec_encoding = vex_encoding_evex;
10811 *end_op = input_line_pointer;
10813 *input_line_pointer = c;
10814 input_line_pointer = save;
10820 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10822 const reg_entry *r;
10823 char *end = input_line_pointer;
10826 r = parse_register (name, &input_line_pointer);
10827 if (r && end <= input_line_pointer)
10829 *nextcharP = *input_line_pointer;
10830 *input_line_pointer = 0;
10831 e->X_op = O_register;
10832 e->X_add_number = r - i386_regtab;
10835 input_line_pointer = end;
10837 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
10841 md_operand (expressionS *e)
10844 const reg_entry *r;
10846 switch (*input_line_pointer)
10848 case REGISTER_PREFIX:
10849 r = parse_real_register (input_line_pointer, &end);
10852 e->X_op = O_register;
10853 e->X_add_number = r - i386_regtab;
10854 input_line_pointer = end;
10859 gas_assert (intel_syntax);
10860 end = input_line_pointer++;
10862 if (*input_line_pointer == ']')
10864 ++input_line_pointer;
10865 e->X_op_symbol = make_expr_symbol (e);
10866 e->X_add_symbol = NULL;
10867 e->X_add_number = 0;
10872 e->X_op = O_absent;
10873 input_line_pointer = end;
10880 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10881 const char *md_shortopts = "kVQ:sqnO::";
10883 const char *md_shortopts = "qnO::";
10886 #define OPTION_32 (OPTION_MD_BASE + 0)
10887 #define OPTION_64 (OPTION_MD_BASE + 1)
10888 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
10889 #define OPTION_MARCH (OPTION_MD_BASE + 3)
10890 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10891 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10892 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10893 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10894 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10895 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
10896 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10897 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10898 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10899 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10900 #define OPTION_X32 (OPTION_MD_BASE + 14)
10901 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10902 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10903 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10904 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10905 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10906 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10907 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10908 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10909 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10910 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10911 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
10912 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
10914 struct option md_longopts[] =
10916 {"32", no_argument, NULL, OPTION_32},
10917 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10918 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10919 {"64", no_argument, NULL, OPTION_64},
10921 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10922 {"x32", no_argument, NULL, OPTION_X32},
10923 {"mshared", no_argument, NULL, OPTION_MSHARED},
10924 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
10926 {"divide", no_argument, NULL, OPTION_DIVIDE},
10927 {"march", required_argument, NULL, OPTION_MARCH},
10928 {"mtune", required_argument, NULL, OPTION_MTUNE},
10929 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10930 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10931 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10932 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10933 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10934 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10935 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10936 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10937 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
10938 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10939 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10940 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10941 # if defined (TE_PE) || defined (TE_PEP)
10942 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10944 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10945 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10946 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10947 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10948 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10949 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10950 {NULL, no_argument, NULL, 0}
10952 size_t md_longopts_size = sizeof (md_longopts);
10955 md_parse_option (int c, const char *arg)
10958 char *arch, *next, *saved;
10963 optimize_align_code = 0;
10967 quiet_warnings = 1;
10970 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10971 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10972 should be emitted or not. FIXME: Not implemented. */
10976 /* -V: SVR4 argument to print version ID. */
10978 print_version_id ();
10981 /* -k: Ignore for FreeBSD compatibility. */
10986 /* -s: On i386 Solaris, this tells the native assembler to use
10987 .stab instead of .stab.excl. We always use .stab anyhow. */
10990 case OPTION_MSHARED:
10994 case OPTION_X86_USED_NOTE:
10995 if (strcasecmp (arg, "yes") == 0)
10997 else if (strcasecmp (arg, "no") == 0)
11000 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
11005 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11006 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11009 const char **list, **l;
11011 list = bfd_target_list ();
11012 for (l = list; *l != NULL; l++)
11013 if (CONST_STRNEQ (*l, "elf64-x86-64")
11014 || strcmp (*l, "coff-x86-64") == 0
11015 || strcmp (*l, "pe-x86-64") == 0
11016 || strcmp (*l, "pei-x86-64") == 0
11017 || strcmp (*l, "mach-o-x86-64") == 0)
11019 default_arch = "x86_64";
11023 as_fatal (_("no compiled in support for x86_64"));
11029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11033 const char **list, **l;
11035 list = bfd_target_list ();
11036 for (l = list; *l != NULL; l++)
11037 if (CONST_STRNEQ (*l, "elf32-x86-64"))
11039 default_arch = "x86_64:32";
11043 as_fatal (_("no compiled in support for 32bit x86_64"));
11047 as_fatal (_("32bit x86_64 is only supported for ELF"));
11052 default_arch = "i386";
11055 case OPTION_DIVIDE:
11056 #ifdef SVR4_COMMENT_CHARS
11061 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
11063 for (s = i386_comment_chars; *s != '\0'; s++)
11067 i386_comment_chars = n;
11073 saved = xstrdup (arg);
11075 /* Allow -march=+nosse. */
11081 as_fatal (_("invalid -march= option: `%s'"), arg);
11082 next = strchr (arch, '+');
11085 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11087 if (strcmp (arch, cpu_arch [j].name) == 0)
11090 if (! cpu_arch[j].flags.bitfield.cpui386)
11093 cpu_arch_name = cpu_arch[j].name;
11094 cpu_sub_arch_name = NULL;
11095 cpu_arch_flags = cpu_arch[j].flags;
11096 cpu_arch_isa = cpu_arch[j].type;
11097 cpu_arch_isa_flags = cpu_arch[j].flags;
11098 if (!cpu_arch_tune_set)
11100 cpu_arch_tune = cpu_arch_isa;
11101 cpu_arch_tune_flags = cpu_arch_isa_flags;
11105 else if (*cpu_arch [j].name == '.'
11106 && strcmp (arch, cpu_arch [j].name + 1) == 0)
11108 /* ISA extension. */
11109 i386_cpu_flags flags;
11111 flags = cpu_flags_or (cpu_arch_flags,
11112 cpu_arch[j].flags);
11114 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11116 if (cpu_sub_arch_name)
11118 char *name = cpu_sub_arch_name;
11119 cpu_sub_arch_name = concat (name,
11121 (const char *) NULL);
11125 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
11126 cpu_arch_flags = flags;
11127 cpu_arch_isa_flags = flags;
11131 = cpu_flags_or (cpu_arch_isa_flags,
11132 cpu_arch[j].flags);
11137 if (j >= ARRAY_SIZE (cpu_arch))
11139 /* Disable an ISA extension. */
11140 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11141 if (strcmp (arch, cpu_noarch [j].name) == 0)
11143 i386_cpu_flags flags;
11145 flags = cpu_flags_and_not (cpu_arch_flags,
11146 cpu_noarch[j].flags);
11147 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11149 if (cpu_sub_arch_name)
11151 char *name = cpu_sub_arch_name;
11152 cpu_sub_arch_name = concat (arch,
11153 (const char *) NULL);
11157 cpu_sub_arch_name = xstrdup (arch);
11158 cpu_arch_flags = flags;
11159 cpu_arch_isa_flags = flags;
11164 if (j >= ARRAY_SIZE (cpu_noarch))
11165 j = ARRAY_SIZE (cpu_arch);
11168 if (j >= ARRAY_SIZE (cpu_arch))
11169 as_fatal (_("invalid -march= option: `%s'"), arg);
11173 while (next != NULL);
11179 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11180 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11182 if (strcmp (arg, cpu_arch [j].name) == 0)
11184 cpu_arch_tune_set = 1;
11185 cpu_arch_tune = cpu_arch [j].type;
11186 cpu_arch_tune_flags = cpu_arch[j].flags;
11190 if (j >= ARRAY_SIZE (cpu_arch))
11191 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11194 case OPTION_MMNEMONIC:
11195 if (strcasecmp (arg, "att") == 0)
11196 intel_mnemonic = 0;
11197 else if (strcasecmp (arg, "intel") == 0)
11198 intel_mnemonic = 1;
11200 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
11203 case OPTION_MSYNTAX:
11204 if (strcasecmp (arg, "att") == 0)
11206 else if (strcasecmp (arg, "intel") == 0)
11209 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
11212 case OPTION_MINDEX_REG:
11213 allow_index_reg = 1;
11216 case OPTION_MNAKED_REG:
11217 allow_naked_reg = 1;
11220 case OPTION_MSSE2AVX:
11224 case OPTION_MSSE_CHECK:
11225 if (strcasecmp (arg, "error") == 0)
11226 sse_check = check_error;
11227 else if (strcasecmp (arg, "warning") == 0)
11228 sse_check = check_warning;
11229 else if (strcasecmp (arg, "none") == 0)
11230 sse_check = check_none;
11232 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
11235 case OPTION_MOPERAND_CHECK:
11236 if (strcasecmp (arg, "error") == 0)
11237 operand_check = check_error;
11238 else if (strcasecmp (arg, "warning") == 0)
11239 operand_check = check_warning;
11240 else if (strcasecmp (arg, "none") == 0)
11241 operand_check = check_none;
11243 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11246 case OPTION_MAVXSCALAR:
11247 if (strcasecmp (arg, "128") == 0)
11248 avxscalar = vex128;
11249 else if (strcasecmp (arg, "256") == 0)
11250 avxscalar = vex256;
11252 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
11255 case OPTION_MVEXWIG:
11256 if (strcmp (arg, "0") == 0)
11258 else if (strcmp (arg, "1") == 0)
11261 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
11264 case OPTION_MADD_BND_PREFIX:
11265 add_bnd_prefix = 1;
11268 case OPTION_MEVEXLIG:
11269 if (strcmp (arg, "128") == 0)
11270 evexlig = evexl128;
11271 else if (strcmp (arg, "256") == 0)
11272 evexlig = evexl256;
11273 else if (strcmp (arg, "512") == 0)
11274 evexlig = evexl512;
11276 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11279 case OPTION_MEVEXRCIG:
11280 if (strcmp (arg, "rne") == 0)
11282 else if (strcmp (arg, "rd") == 0)
11284 else if (strcmp (arg, "ru") == 0)
11286 else if (strcmp (arg, "rz") == 0)
11289 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11292 case OPTION_MEVEXWIG:
11293 if (strcmp (arg, "0") == 0)
11295 else if (strcmp (arg, "1") == 0)
11298 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11301 # if defined (TE_PE) || defined (TE_PEP)
11302 case OPTION_MBIG_OBJ:
11307 case OPTION_MOMIT_LOCK_PREFIX:
11308 if (strcasecmp (arg, "yes") == 0)
11309 omit_lock_prefix = 1;
11310 else if (strcasecmp (arg, "no") == 0)
11311 omit_lock_prefix = 0;
11313 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11316 case OPTION_MFENCE_AS_LOCK_ADD:
11317 if (strcasecmp (arg, "yes") == 0)
11319 else if (strcasecmp (arg, "no") == 0)
11322 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11325 case OPTION_MRELAX_RELOCATIONS:
11326 if (strcasecmp (arg, "yes") == 0)
11327 generate_relax_relocations = 1;
11328 else if (strcasecmp (arg, "no") == 0)
11329 generate_relax_relocations = 0;
11331 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11334 case OPTION_MAMD64:
11338 case OPTION_MINTEL64:
11346 /* Turn off -Os. */
11347 optimize_for_space = 0;
11349 else if (*arg == 's')
11351 optimize_for_space = 1;
11352 /* Turn on all encoding optimizations. */
11357 optimize = atoi (arg);
11358 /* Turn off -Os. */
11359 optimize_for_space = 0;
11369 #define MESSAGE_TEMPLATE \
11373 output_message (FILE *stream, char *p, char *message, char *start,
11374 int *left_p, const char *name, int len)
11376 int size = sizeof (MESSAGE_TEMPLATE);
11377 int left = *left_p;
11379 /* Reserve 2 spaces for ", " or ",\0" */
11382 /* Check if there is any room. */
11390 p = mempcpy (p, name, len);
11394 /* Output the current message now and start a new one. */
11397 fprintf (stream, "%s\n", message);
11399 left = size - (start - message) - len - 2;
11401 gas_assert (left >= 0);
11403 p = mempcpy (p, name, len);
11411 show_arch (FILE *stream, int ext, int check)
11413 static char message[] = MESSAGE_TEMPLATE;
11414 char *start = message + 27;
11416 int size = sizeof (MESSAGE_TEMPLATE);
11423 left = size - (start - message);
11424 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11426 /* Should it be skipped? */
11427 if (cpu_arch [j].skip)
11430 name = cpu_arch [j].name;
11431 len = cpu_arch [j].len;
11434 /* It is an extension. Skip if we aren't asked to show it. */
11445 /* It is an processor. Skip if we show only extension. */
11448 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11450 /* It is an impossible processor - skip. */
11454 p = output_message (stream, p, message, start, &left, name, len);
11457 /* Display disabled extensions. */
11459 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11461 name = cpu_noarch [j].name;
11462 len = cpu_noarch [j].len;
11463 p = output_message (stream, p, message, start, &left, name,
11468 fprintf (stream, "%s\n", message);
11472 md_show_usage (FILE *stream)
11474 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11475 fprintf (stream, _("\
11477 -V print assembler version number\n\
11480 fprintf (stream, _("\
11481 -n Do not optimize code alignment\n\
11482 -q quieten some warnings\n"));
11483 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11484 fprintf (stream, _("\
11487 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11488 || defined (TE_PE) || defined (TE_PEP))
11489 fprintf (stream, _("\
11490 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11492 #ifdef SVR4_COMMENT_CHARS
11493 fprintf (stream, _("\
11494 --divide do not treat `/' as a comment character\n"));
11496 fprintf (stream, _("\
11497 --divide ignored\n"));
11499 fprintf (stream, _("\
11500 -march=CPU[,+EXTENSION...]\n\
11501 generate code for CPU and EXTENSION, CPU is one of:\n"));
11502 show_arch (stream, 0, 1);
11503 fprintf (stream, _("\
11504 EXTENSION is combination of:\n"));
11505 show_arch (stream, 1, 0);
11506 fprintf (stream, _("\
11507 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11508 show_arch (stream, 0, 0);
11509 fprintf (stream, _("\
11510 -msse2avx encode SSE instructions with VEX prefix\n"));
11511 fprintf (stream, _("\
11512 -msse-check=[none|error|warning] (default: warning)\n\
11513 check SSE instructions\n"));
11514 fprintf (stream, _("\
11515 -moperand-check=[none|error|warning] (default: warning)\n\
11516 check operand combinations for validity\n"));
11517 fprintf (stream, _("\
11518 -mavxscalar=[128|256] (default: 128)\n\
11519 encode scalar AVX instructions with specific vector\n\
11521 fprintf (stream, _("\
11522 -mvexwig=[0|1] (default: 0)\n\
11523 encode VEX instructions with specific VEX.W value\n\
11524 for VEX.W bit ignored instructions\n"));
11525 fprintf (stream, _("\
11526 -mevexlig=[128|256|512] (default: 128)\n\
11527 encode scalar EVEX instructions with specific vector\n\
11529 fprintf (stream, _("\
11530 -mevexwig=[0|1] (default: 0)\n\
11531 encode EVEX instructions with specific EVEX.W value\n\
11532 for EVEX.W bit ignored instructions\n"));
11533 fprintf (stream, _("\
11534 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11535 encode EVEX instructions with specific EVEX.RC value\n\
11536 for SAE-only ignored instructions\n"));
11537 fprintf (stream, _("\
11538 -mmnemonic=[att|intel] "));
11539 if (SYSV386_COMPAT)
11540 fprintf (stream, _("(default: att)\n"));
11542 fprintf (stream, _("(default: intel)\n"));
11543 fprintf (stream, _("\
11544 use AT&T/Intel mnemonic\n"));
11545 fprintf (stream, _("\
11546 -msyntax=[att|intel] (default: att)\n\
11547 use AT&T/Intel syntax\n"));
11548 fprintf (stream, _("\
11549 -mindex-reg support pseudo index registers\n"));
11550 fprintf (stream, _("\
11551 -mnaked-reg don't require `%%' prefix for registers\n"));
11552 fprintf (stream, _("\
11553 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11554 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11555 fprintf (stream, _("\
11556 -mshared disable branch optimization for shared code\n"));
11557 fprintf (stream, _("\
11558 -mx86-used-note=[no|yes] "));
11559 if (DEFAULT_X86_USED_NOTE)
11560 fprintf (stream, _("(default: yes)\n"));
11562 fprintf (stream, _("(default: no)\n"));
11563 fprintf (stream, _("\
11564 generate x86 used ISA and feature properties\n"));
11566 #if defined (TE_PE) || defined (TE_PEP)
11567 fprintf (stream, _("\
11568 -mbig-obj generate big object files\n"));
11570 fprintf (stream, _("\
11571 -momit-lock-prefix=[no|yes] (default: no)\n\
11572 strip all lock prefixes\n"));
11573 fprintf (stream, _("\
11574 -mfence-as-lock-add=[no|yes] (default: no)\n\
11575 encode lfence, mfence and sfence as\n\
11576 lock addl $0x0, (%%{re}sp)\n"));
11577 fprintf (stream, _("\
11578 -mrelax-relocations=[no|yes] "));
11579 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11580 fprintf (stream, _("(default: yes)\n"));
11582 fprintf (stream, _("(default: no)\n"));
11583 fprintf (stream, _("\
11584 generate relax relocations\n"));
11585 fprintf (stream, _("\
11586 -mamd64 accept only AMD64 ISA [default]\n"));
11587 fprintf (stream, _("\
11588 -mintel64 accept only Intel64 ISA\n"));
11591 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11592 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11593 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11595 /* Pick the target format to use. */
11598 i386_target_format (void)
11600 if (!strncmp (default_arch, "x86_64", 6))
11602 update_code_flag (CODE_64BIT, 1);
11603 if (default_arch[6] == '\0')
11604 x86_elf_abi = X86_64_ABI;
11606 x86_elf_abi = X86_64_X32_ABI;
11608 else if (!strcmp (default_arch, "i386"))
11609 update_code_flag (CODE_32BIT, 1);
11610 else if (!strcmp (default_arch, "iamcu"))
11612 update_code_flag (CODE_32BIT, 1);
11613 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11615 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11616 cpu_arch_name = "iamcu";
11617 cpu_sub_arch_name = NULL;
11618 cpu_arch_flags = iamcu_flags;
11619 cpu_arch_isa = PROCESSOR_IAMCU;
11620 cpu_arch_isa_flags = iamcu_flags;
11621 if (!cpu_arch_tune_set)
11623 cpu_arch_tune = cpu_arch_isa;
11624 cpu_arch_tune_flags = cpu_arch_isa_flags;
11627 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11628 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11632 as_fatal (_("unknown architecture"));
11634 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11635 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11636 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11637 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11639 switch (OUTPUT_FLAVOR)
11641 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11642 case bfd_target_aout_flavour:
11643 return AOUT_TARGET_FORMAT;
11645 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11646 # if defined (TE_PE) || defined (TE_PEP)
11647 case bfd_target_coff_flavour:
11648 if (flag_code == CODE_64BIT)
11649 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11652 # elif defined (TE_GO32)
11653 case bfd_target_coff_flavour:
11654 return "coff-go32";
11656 case bfd_target_coff_flavour:
11657 return "coff-i386";
11660 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11661 case bfd_target_elf_flavour:
11663 const char *format;
11665 switch (x86_elf_abi)
11668 format = ELF_TARGET_FORMAT;
11671 use_rela_relocations = 1;
11673 format = ELF_TARGET_FORMAT64;
11675 case X86_64_X32_ABI:
11676 use_rela_relocations = 1;
11678 disallow_64bit_reloc = 1;
11679 format = ELF_TARGET_FORMAT32;
11682 if (cpu_arch_isa == PROCESSOR_L1OM)
11684 if (x86_elf_abi != X86_64_ABI)
11685 as_fatal (_("Intel L1OM is 64bit only"));
11686 return ELF_TARGET_L1OM_FORMAT;
11688 else if (cpu_arch_isa == PROCESSOR_K1OM)
11690 if (x86_elf_abi != X86_64_ABI)
11691 as_fatal (_("Intel K1OM is 64bit only"));
11692 return ELF_TARGET_K1OM_FORMAT;
11694 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11696 if (x86_elf_abi != I386_ABI)
11697 as_fatal (_("Intel MCU is 32bit only"));
11698 return ELF_TARGET_IAMCU_FORMAT;
11704 #if defined (OBJ_MACH_O)
11705 case bfd_target_mach_o_flavour:
11706 if (flag_code == CODE_64BIT)
11708 use_rela_relocations = 1;
11710 return "mach-o-x86-64";
11713 return "mach-o-i386";
11721 #endif /* OBJ_MAYBE_ more than one */
11724 md_undefined_symbol (char *name)
11726 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11727 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11728 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11729 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11733 if (symbol_find (name))
11734 as_bad (_("GOT already in symbol table"));
11735 GOT_symbol = symbol_new (name, undefined_section,
11736 (valueT) 0, &zero_address_frag);
11743 /* Round up a section size to the appropriate boundary. */
11746 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11748 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11749 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11751 /* For a.out, force the section size to be aligned. If we don't do
11752 this, BFD will align it for us, but it will not write out the
11753 final bytes of the section. This may be a bug in BFD, but it is
11754 easier to fix it here since that is how the other a.out targets
11758 align = bfd_get_section_alignment (stdoutput, segment);
11759 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11766 /* On the i386, PC-relative offsets are relative to the start of the
11767 next instruction. That is, the address of the offset, plus its
11768 size, since the offset is always the last part of the insn. */
11771 md_pcrel_from (fixS *fixP)
11773 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11779 s_bss (int ignore ATTRIBUTE_UNUSED)
11783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11785 obj_elf_section_change_hook ();
11787 temp = get_absolute_expression ();
11788 subseg_set (bss_section, (subsegT) temp);
11789 demand_empty_rest_of_line ();
11795 i386_validate_fix (fixS *fixp)
11797 if (fixp->fx_subsy)
11799 if (fixp->fx_subsy == GOT_symbol)
11801 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11805 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11806 if (fixp->fx_tcbit2)
11807 fixp->fx_r_type = (fixp->fx_tcbit
11808 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11809 : BFD_RELOC_X86_64_GOTPCRELX);
11812 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11817 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11819 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11821 fixp->fx_subsy = 0;
11824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11825 else if (!object_64bit)
11827 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11828 && fixp->fx_tcbit2)
11829 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11835 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
11838 bfd_reloc_code_real_type code;
11840 switch (fixp->fx_r_type)
11842 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11843 case BFD_RELOC_SIZE32:
11844 case BFD_RELOC_SIZE64:
11845 if (S_IS_DEFINED (fixp->fx_addsy)
11846 && !S_IS_EXTERNAL (fixp->fx_addsy))
11848 /* Resolve size relocation against local symbol to size of
11849 the symbol plus addend. */
11850 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11851 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11852 && !fits_in_unsigned_long (value))
11853 as_bad_where (fixp->fx_file, fixp->fx_line,
11854 _("symbol size computation overflow"));
11855 fixp->fx_addsy = NULL;
11856 fixp->fx_subsy = NULL;
11857 md_apply_fix (fixp, (valueT *) &value, NULL);
11861 /* Fall through. */
11863 case BFD_RELOC_X86_64_PLT32:
11864 case BFD_RELOC_X86_64_GOT32:
11865 case BFD_RELOC_X86_64_GOTPCREL:
11866 case BFD_RELOC_X86_64_GOTPCRELX:
11867 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11868 case BFD_RELOC_386_PLT32:
11869 case BFD_RELOC_386_GOT32:
11870 case BFD_RELOC_386_GOT32X:
11871 case BFD_RELOC_386_GOTOFF:
11872 case BFD_RELOC_386_GOTPC:
11873 case BFD_RELOC_386_TLS_GD:
11874 case BFD_RELOC_386_TLS_LDM:
11875 case BFD_RELOC_386_TLS_LDO_32:
11876 case BFD_RELOC_386_TLS_IE_32:
11877 case BFD_RELOC_386_TLS_IE:
11878 case BFD_RELOC_386_TLS_GOTIE:
11879 case BFD_RELOC_386_TLS_LE_32:
11880 case BFD_RELOC_386_TLS_LE:
11881 case BFD_RELOC_386_TLS_GOTDESC:
11882 case BFD_RELOC_386_TLS_DESC_CALL:
11883 case BFD_RELOC_X86_64_TLSGD:
11884 case BFD_RELOC_X86_64_TLSLD:
11885 case BFD_RELOC_X86_64_DTPOFF32:
11886 case BFD_RELOC_X86_64_DTPOFF64:
11887 case BFD_RELOC_X86_64_GOTTPOFF:
11888 case BFD_RELOC_X86_64_TPOFF32:
11889 case BFD_RELOC_X86_64_TPOFF64:
11890 case BFD_RELOC_X86_64_GOTOFF64:
11891 case BFD_RELOC_X86_64_GOTPC32:
11892 case BFD_RELOC_X86_64_GOT64:
11893 case BFD_RELOC_X86_64_GOTPCREL64:
11894 case BFD_RELOC_X86_64_GOTPC64:
11895 case BFD_RELOC_X86_64_GOTPLT64:
11896 case BFD_RELOC_X86_64_PLTOFF64:
11897 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11898 case BFD_RELOC_X86_64_TLSDESC_CALL:
11899 case BFD_RELOC_RVA:
11900 case BFD_RELOC_VTABLE_ENTRY:
11901 case BFD_RELOC_VTABLE_INHERIT:
11903 case BFD_RELOC_32_SECREL:
11905 code = fixp->fx_r_type;
11907 case BFD_RELOC_X86_64_32S:
11908 if (!fixp->fx_pcrel)
11910 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11911 code = fixp->fx_r_type;
11914 /* Fall through. */
11916 if (fixp->fx_pcrel)
11918 switch (fixp->fx_size)
11921 as_bad_where (fixp->fx_file, fixp->fx_line,
11922 _("can not do %d byte pc-relative relocation"),
11924 code = BFD_RELOC_32_PCREL;
11926 case 1: code = BFD_RELOC_8_PCREL; break;
11927 case 2: code = BFD_RELOC_16_PCREL; break;
11928 case 4: code = BFD_RELOC_32_PCREL; break;
11930 case 8: code = BFD_RELOC_64_PCREL; break;
11936 switch (fixp->fx_size)
11939 as_bad_where (fixp->fx_file, fixp->fx_line,
11940 _("can not do %d byte relocation"),
11942 code = BFD_RELOC_32;
11944 case 1: code = BFD_RELOC_8; break;
11945 case 2: code = BFD_RELOC_16; break;
11946 case 4: code = BFD_RELOC_32; break;
11948 case 8: code = BFD_RELOC_64; break;
11955 if ((code == BFD_RELOC_32
11956 || code == BFD_RELOC_32_PCREL
11957 || code == BFD_RELOC_X86_64_32S)
11959 && fixp->fx_addsy == GOT_symbol)
11962 code = BFD_RELOC_386_GOTPC;
11964 code = BFD_RELOC_X86_64_GOTPC32;
11966 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11968 && fixp->fx_addsy == GOT_symbol)
11970 code = BFD_RELOC_X86_64_GOTPC64;
11973 rel = XNEW (arelent);
11974 rel->sym_ptr_ptr = XNEW (asymbol *);
11975 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11977 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11979 if (!use_rela_relocations)
11981 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11982 vtable entry to be used in the relocation's section offset. */
11983 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11984 rel->address = fixp->fx_offset;
11985 #if defined (OBJ_COFF) && defined (TE_PE)
11986 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11987 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11992 /* Use the rela in 64bit mode. */
11995 if (disallow_64bit_reloc)
11998 case BFD_RELOC_X86_64_DTPOFF64:
11999 case BFD_RELOC_X86_64_TPOFF64:
12000 case BFD_RELOC_64_PCREL:
12001 case BFD_RELOC_X86_64_GOTOFF64:
12002 case BFD_RELOC_X86_64_GOT64:
12003 case BFD_RELOC_X86_64_GOTPCREL64:
12004 case BFD_RELOC_X86_64_GOTPC64:
12005 case BFD_RELOC_X86_64_GOTPLT64:
12006 case BFD_RELOC_X86_64_PLTOFF64:
12007 as_bad_where (fixp->fx_file, fixp->fx_line,
12008 _("cannot represent relocation type %s in x32 mode"),
12009 bfd_get_reloc_code_name (code));
12015 if (!fixp->fx_pcrel)
12016 rel->addend = fixp->fx_offset;
12020 case BFD_RELOC_X86_64_PLT32:
12021 case BFD_RELOC_X86_64_GOT32:
12022 case BFD_RELOC_X86_64_GOTPCREL:
12023 case BFD_RELOC_X86_64_GOTPCRELX:
12024 case BFD_RELOC_X86_64_REX_GOTPCRELX:
12025 case BFD_RELOC_X86_64_TLSGD:
12026 case BFD_RELOC_X86_64_TLSLD:
12027 case BFD_RELOC_X86_64_GOTTPOFF:
12028 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12029 case BFD_RELOC_X86_64_TLSDESC_CALL:
12030 rel->addend = fixp->fx_offset - fixp->fx_size;
12033 rel->addend = (section->vma
12035 + fixp->fx_addnumber
12036 + md_pcrel_from (fixp));
12041 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
12042 if (rel->howto == NULL)
12044 as_bad_where (fixp->fx_file, fixp->fx_line,
12045 _("cannot represent relocation type %s"),
12046 bfd_get_reloc_code_name (code));
12047 /* Set howto to a garbage value so that we can keep going. */
12048 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
12049 gas_assert (rel->howto != NULL);
12055 #include "tc-i386-intel.c"
12058 tc_x86_parse_to_dw2regnum (expressionS *exp)
12060 int saved_naked_reg;
12061 char saved_register_dot;
12063 saved_naked_reg = allow_naked_reg;
12064 allow_naked_reg = 1;
12065 saved_register_dot = register_chars['.'];
12066 register_chars['.'] = '.';
12067 allow_pseudo_reg = 1;
12068 expression_and_evaluate (exp);
12069 allow_pseudo_reg = 0;
12070 register_chars['.'] = saved_register_dot;
12071 allow_naked_reg = saved_naked_reg;
12073 if (exp->X_op == O_register && exp->X_add_number >= 0)
12075 if ((addressT) exp->X_add_number < i386_regtab_size)
12077 exp->X_op = O_constant;
12078 exp->X_add_number = i386_regtab[exp->X_add_number]
12079 .dw2_regnum[flag_code >> 1];
12082 exp->X_op = O_illegal;
12087 tc_x86_frame_initial_instructions (void)
12089 static unsigned int sp_regno[2];
12091 if (!sp_regno[flag_code >> 1])
12093 char *saved_input = input_line_pointer;
12094 char sp[][4] = {"esp", "rsp"};
12097 input_line_pointer = sp[flag_code >> 1];
12098 tc_x86_parse_to_dw2regnum (&exp);
12099 gas_assert (exp.X_op == O_constant);
12100 sp_regno[flag_code >> 1] = exp.X_add_number;
12101 input_line_pointer = saved_input;
12104 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12105 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
12109 x86_dwarf2_addr_size (void)
12111 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12112 if (x86_elf_abi == X86_64_X32_ABI)
12115 return bfd_arch_bits_per_address (stdoutput) / 8;
12119 i386_elf_section_type (const char *str, size_t len)
12121 if (flag_code == CODE_64BIT
12122 && len == sizeof ("unwind") - 1
12123 && strncmp (str, "unwind", 6) == 0)
12124 return SHT_X86_64_UNWIND;
12131 i386_solaris_fix_up_eh_frame (segT sec)
12133 if (flag_code == CODE_64BIT)
12134 elf_section_type (sec) = SHT_X86_64_UNWIND;
12140 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12144 exp.X_op = O_secrel;
12145 exp.X_add_symbol = symbol;
12146 exp.X_add_number = 0;
12147 emit_expr (&exp, size);
12151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12152 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12155 x86_64_section_letter (int letter, const char **ptr_msg)
12157 if (flag_code == CODE_64BIT)
12160 return SHF_X86_64_LARGE;
12162 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12165 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
12170 x86_64_section_word (char *str, size_t len)
12172 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
12173 return SHF_X86_64_LARGE;
12179 handle_large_common (int small ATTRIBUTE_UNUSED)
12181 if (flag_code != CODE_64BIT)
12183 s_comm_internal (0, elf_common_parse);
12184 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12188 static segT lbss_section;
12189 asection *saved_com_section_ptr = elf_com_section_ptr;
12190 asection *saved_bss_section = bss_section;
12192 if (lbss_section == NULL)
12194 flagword applicable;
12195 segT seg = now_seg;
12196 subsegT subseg = now_subseg;
12198 /* The .lbss section is for local .largecomm symbols. */
12199 lbss_section = subseg_new (".lbss", 0);
12200 applicable = bfd_applicable_section_flags (stdoutput);
12201 bfd_set_section_flags (stdoutput, lbss_section,
12202 applicable & SEC_ALLOC);
12203 seg_info (lbss_section)->bss = 1;
12205 subseg_set (seg, subseg);
12208 elf_com_section_ptr = &_bfd_elf_large_com_section;
12209 bss_section = lbss_section;
12211 s_comm_internal (0, elf_common_parse);
12213 elf_com_section_ptr = saved_com_section_ptr;
12214 bss_section = saved_bss_section;
12217 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */