1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 unsigned int negated; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c);
153 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS *);
160 static int i386_intel_parse_name (const char *, expressionS *);
161 static const reg_entry *parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template *match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry *build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS *, offsetT);
180 static void output_disp (fragS *, offsetT);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED);
188 static const char *default_arch = DEFAULT_ARCH;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry *regs;
254 operand_size_mismatch,
255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
261 unsupported_with_intel_mnemonic,
264 invalid_vsib_address,
265 invalid_vector_register_set,
266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
271 mask_not_on_destination,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types[MAX_OPERANDS];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op[MAX_OPERANDS];
304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry *seg[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation *mask;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default = 0,
358 const char *rep_prefix;
361 const char *hle_prefix;
363 /* Have BND prefix. */
364 const char *bnd_prefix;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error;
373 typedef struct _i386_insn i386_insn;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable[] =
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars = "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars = "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars[] = "#/";
435 const char line_separator_chars[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars[256];
448 static char register_chars[256];
449 static char operand_chars[256];
450 static char identifier_chars[256];
451 static char digit_chars[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack[32];
469 static char *save_stack_p;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates *current_templates;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
485 /* Current operand we are working on. */
486 static int this_operand = -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code;
497 static unsigned int object_64bit;
498 static unsigned int disallow_64bit_reloc;
499 static int use_rela_relocations = 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi = I386_ABI;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj = 0;
521 /* 1 for intel syntax,
523 static int intel_syntax = 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic = !SYSV386_COMPAT;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc = OLDGCC_COMPAT;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg = 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg = 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix = 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg = 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix = 0;
550 static enum check_kind
556 sse_check, operand_check = check_warning;
558 /* Register prefix used for error message. */
559 static const char *register_prefix = "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size = '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code = 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings = 0;
573 static const char *cpu_arch_name = NULL;
574 static char *cpu_sub_arch_name = NULL;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set = 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion = 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig = rne;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS *GOT_symbol;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
719 CPU_GENERIC32_FLAGS, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
721 CPU_GENERIC64_FLAGS, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
723 CPU_NONE_FLAGS, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
725 CPU_I186_FLAGS, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
727 CPU_I286_FLAGS, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
729 CPU_I386_FLAGS, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
731 CPU_I486_FLAGS, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
733 CPU_I586_FLAGS, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
735 CPU_I686_FLAGS, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
737 CPU_I586_FLAGS, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
741 CPU_P2_FLAGS, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
743 CPU_P3_FLAGS, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
745 CPU_P4_FLAGS, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
747 CPU_CORE_FLAGS, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
749 CPU_NOCONA_FLAGS, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
751 CPU_CORE_FLAGS, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
753 CPU_CORE_FLAGS, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
755 CPU_CORE2_FLAGS, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
757 CPU_CORE2_FLAGS, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
759 CPU_COREI7_FLAGS, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
761 CPU_L1OM_FLAGS, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
765 CPU_K6_FLAGS, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
767 CPU_K6_2_FLAGS, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
769 CPU_ATHLON_FLAGS, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
771 CPU_K8_FLAGS, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
773 CPU_K8_FLAGS, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
775 CPU_K8_FLAGS, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
777 CPU_AMDFAM10_FLAGS, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
779 CPU_BDVER1_FLAGS, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
781 CPU_BDVER2_FLAGS, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
791 CPU_8087_FLAGS, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
793 CPU_287_FLAGS, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
795 CPU_387_FLAGS, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
797 CPU_ANY87_FLAGS, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
799 CPU_MMX_FLAGS, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
801 CPU_3DNOWA_FLAGS, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
803 CPU_SSE_FLAGS, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
805 CPU_SSE2_FLAGS, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
807 CPU_SSE3_FLAGS, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
809 CPU_SSSE3_FLAGS, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
811 CPU_SSE4_1_FLAGS, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
813 CPU_SSE4_2_FLAGS, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
815 CPU_SSE4_2_FLAGS, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
817 CPU_ANY_SSE_FLAGS, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
819 CPU_AVX_FLAGS, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
830 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
831 CPU_ANY_AVX_FLAGS, 0, 1 },
832 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
833 CPU_VMX_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
835 CPU_VMFUNC_FLAGS, 0, 0 },
836 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
837 CPU_SMX_FLAGS, 0, 0 },
838 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
839 CPU_XSAVE_FLAGS, 0, 0 },
840 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
841 CPU_XSAVEOPT_FLAGS, 0, 0 },
842 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
843 CPU_AES_FLAGS, 0, 0 },
844 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
845 CPU_PCLMUL_FLAGS, 0, 0 },
846 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
847 CPU_PCLMUL_FLAGS, 1, 0 },
848 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
849 CPU_FSGSBASE_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
851 CPU_RDRND_FLAGS, 0, 0 },
852 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
853 CPU_F16C_FLAGS, 0, 0 },
854 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
855 CPU_BMI2_FLAGS, 0, 0 },
856 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
857 CPU_FMA_FLAGS, 0, 0 },
858 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
859 CPU_FMA4_FLAGS, 0, 0 },
860 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
861 CPU_XOP_FLAGS, 0, 0 },
862 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
863 CPU_LWP_FLAGS, 0, 0 },
864 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
865 CPU_MOVBE_FLAGS, 0, 0 },
866 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
867 CPU_CX16_FLAGS, 0, 0 },
868 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
869 CPU_EPT_FLAGS, 0, 0 },
870 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
871 CPU_LZCNT_FLAGS, 0, 0 },
872 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
873 CPU_HLE_FLAGS, 0, 0 },
874 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
875 CPU_RTM_FLAGS, 0, 0 },
876 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
877 CPU_INVPCID_FLAGS, 0, 0 },
878 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
879 CPU_CLFLUSH_FLAGS, 0, 0 },
880 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
881 CPU_NOP_FLAGS, 0, 0 },
882 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
883 CPU_SYSCALL_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
885 CPU_RDTSCP_FLAGS, 0, 0 },
886 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
887 CPU_3DNOW_FLAGS, 0, 0 },
888 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
889 CPU_3DNOWA_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
891 CPU_PADLOCK_FLAGS, 0, 0 },
892 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
893 CPU_SVME_FLAGS, 1, 0 },
894 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
895 CPU_SVME_FLAGS, 0, 0 },
896 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
897 CPU_SSE4A_FLAGS, 0, 0 },
898 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
899 CPU_ABM_FLAGS, 0, 0 },
900 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
901 CPU_BMI_FLAGS, 0, 0 },
902 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
903 CPU_TBM_FLAGS, 0, 0 },
904 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
905 CPU_ADX_FLAGS, 0, 0 },
906 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
907 CPU_RDSEED_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
909 CPU_PRFCHW_FLAGS, 0, 0 },
910 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
911 CPU_SMAP_FLAGS, 0, 0 },
912 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
913 CPU_MPX_FLAGS, 0, 0 },
914 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
915 CPU_SHA_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
917 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
919 CPU_XSAVEC_FLAGS, 0, 0 },
920 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
921 CPU_XSAVES_FLAGS, 0, 0 },
922 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
923 CPU_PREFETCHWT1_FLAGS, 0, 0 },
924 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
925 CPU_SE1_FLAGS, 0, 0 },
926 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
927 CPU_AVX512DQ_FLAGS, 0, 0 },
928 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
929 CPU_AVX512BW_FLAGS, 0, 0 },
930 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
931 CPU_AVX512VL_FLAGS, 0, 0 },
935 /* Like s_lcomm_internal in gas/read.c but the alignment string
936 is allowed to be optional. */
939 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
946 && *input_line_pointer == ',')
948 align = parse_align (needs_align - 1);
950 if (align == (addressT) -1)
965 bss_alloc (symbolP, size, align);
970 pe_lcomm (int needs_align)
972 s_comm_internal (needs_align * 2, pe_lcomm_internal);
976 const pseudo_typeS md_pseudo_table[] =
978 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
979 {"align", s_align_bytes, 0},
981 {"align", s_align_ptwo, 0},
983 {"arch", set_cpu_arch, 0},
987 {"lcomm", pe_lcomm, 1},
989 {"ffloat", float_cons, 'f'},
990 {"dfloat", float_cons, 'd'},
991 {"tfloat", float_cons, 'x'},
993 {"slong", signed_cons, 4},
994 {"noopt", s_ignore, 0},
995 {"optim", s_ignore, 0},
996 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
997 {"code16", set_code_flag, CODE_16BIT},
998 {"code32", set_code_flag, CODE_32BIT},
999 {"code64", set_code_flag, CODE_64BIT},
1000 {"intel_syntax", set_intel_syntax, 1},
1001 {"att_syntax", set_intel_syntax, 0},
1002 {"intel_mnemonic", set_intel_mnemonic, 1},
1003 {"att_mnemonic", set_intel_mnemonic, 0},
1004 {"allow_index_reg", set_allow_index_reg, 1},
1005 {"disallow_index_reg", set_allow_index_reg, 0},
1006 {"sse_check", set_check, 0},
1007 {"operand_check", set_check, 1},
1008 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1009 {"largecomm", handle_large_common, 0},
1011 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1012 {"loc", dwarf2_directive_loc, 0},
1013 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1016 {"secrel32", pe_directive_secrel, 0},
1021 /* For interface with expression (). */
1022 extern char *input_line_pointer;
1024 /* Hash table for instruction mnemonic lookup. */
1025 static struct hash_control *op_hash;
1027 /* Hash table for register lookup. */
1028 static struct hash_control *reg_hash;
1031 i386_align_code (fragS *fragP, int count)
1033 /* Various efficient no-op patterns for aligning code labels.
1034 Note: Don't try to assemble the instructions in the comments.
1035 0L and 0w are not legal. */
1036 static const char f32_1[] =
1038 static const char f32_2[] =
1039 {0x66,0x90}; /* xchg %ax,%ax */
1040 static const char f32_3[] =
1041 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1042 static const char f32_4[] =
1043 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1044 static const char f32_5[] =
1046 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1047 static const char f32_6[] =
1048 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1049 static const char f32_7[] =
1050 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1051 static const char f32_8[] =
1053 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1054 static const char f32_9[] =
1055 {0x89,0xf6, /* movl %esi,%esi */
1056 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1057 static const char f32_10[] =
1058 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1059 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1060 static const char f32_11[] =
1061 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_12[] =
1064 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1065 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1066 static const char f32_13[] =
1067 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_14[] =
1070 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1071 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1072 static const char f16_3[] =
1073 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1074 static const char f16_4[] =
1075 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1076 static const char f16_5[] =
1078 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1079 static const char f16_6[] =
1080 {0x89,0xf6, /* mov %si,%si */
1081 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1082 static const char f16_7[] =
1083 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1084 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1085 static const char f16_8[] =
1086 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char jump_31[] =
1089 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1090 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1091 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1092 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1093 static const char *const f32_patt[] = {
1094 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1095 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1097 static const char *const f16_patt[] = {
1098 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1100 /* nopl (%[re]ax) */
1101 static const char alt_3[] =
1103 /* nopl 0(%[re]ax) */
1104 static const char alt_4[] =
1105 {0x0f,0x1f,0x40,0x00};
1106 /* nopl 0(%[re]ax,%[re]ax,1) */
1107 static const char alt_5[] =
1108 {0x0f,0x1f,0x44,0x00,0x00};
1109 /* nopw 0(%[re]ax,%[re]ax,1) */
1110 static const char alt_6[] =
1111 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1112 /* nopl 0L(%[re]ax) */
1113 static const char alt_7[] =
1114 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1115 /* nopl 0L(%[re]ax,%[re]ax,1) */
1116 static const char alt_8[] =
1117 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1118 /* nopw 0L(%[re]ax,%[re]ax,1) */
1119 static const char alt_9[] =
1120 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1121 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_10[] =
1123 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1125 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1126 static const char alt_long_11[] =
1128 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_12[] =
1135 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_long_13[] =
1144 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1149 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1150 static const char alt_long_14[] =
1155 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1161 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1162 static const char alt_long_15[] =
1168 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 /* nopl 0(%[re]ax,%[re]ax,1)
1170 nopw 0(%[re]ax,%[re]ax,1) */
1171 static const char alt_short_11[] =
1172 {0x0f,0x1f,0x44,0x00,0x00,
1173 0x66,0x0f,0x1f,0x44,0x00,0x00};
1174 /* nopw 0(%[re]ax,%[re]ax,1)
1175 nopw 0(%[re]ax,%[re]ax,1) */
1176 static const char alt_short_12[] =
1177 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1178 0x66,0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1)
1181 static const char alt_short_13[] =
1182 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1183 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1186 static const char alt_short_14[] =
1187 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1188 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1190 nopl 0L(%[re]ax,%[re]ax,1) */
1191 static const char alt_short_15[] =
1192 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1193 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1194 static const char *const alt_short_patt[] = {
1195 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1196 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1197 alt_short_14, alt_short_15
1199 static const char *const alt_long_patt[] = {
1200 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1201 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1202 alt_long_14, alt_long_15
1205 /* Only align for at least a positive non-zero boundary. */
1206 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1209 /* We need to decide which NOP sequence to use for 32bit and
1210 64bit. When -mtune= is used:
1212 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1213 PROCESSOR_GENERIC32, f32_patt will be used.
1214 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1215 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1216 PROCESSOR_GENERIC64, alt_long_patt will be used.
1217 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1218 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1221 When -mtune= isn't used, alt_long_patt will be used if
1222 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1225 When -march= or .arch is used, we can't use anything beyond
1226 cpu_arch_isa_flags. */
1228 if (flag_code == CODE_16BIT)
1232 memcpy (fragP->fr_literal + fragP->fr_fix,
1234 /* Adjust jump offset. */
1235 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1238 memcpy (fragP->fr_literal + fragP->fr_fix,
1239 f16_patt[count - 1], count);
1243 const char *const *patt = NULL;
1245 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1247 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1248 switch (cpu_arch_tune)
1250 case PROCESSOR_UNKNOWN:
1251 /* We use cpu_arch_isa_flags to check if we SHOULD
1252 optimize with nops. */
1253 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1254 patt = alt_long_patt;
1258 case PROCESSOR_PENTIUM4:
1259 case PROCESSOR_NOCONA:
1260 case PROCESSOR_CORE:
1261 case PROCESSOR_CORE2:
1262 case PROCESSOR_COREI7:
1263 case PROCESSOR_L1OM:
1264 case PROCESSOR_K1OM:
1265 case PROCESSOR_GENERIC64:
1266 patt = alt_long_patt;
1269 case PROCESSOR_ATHLON:
1271 case PROCESSOR_AMDFAM10:
1274 patt = alt_short_patt;
1276 case PROCESSOR_I386:
1277 case PROCESSOR_I486:
1278 case PROCESSOR_PENTIUM:
1279 case PROCESSOR_PENTIUMPRO:
1280 case PROCESSOR_GENERIC32:
1287 switch (fragP->tc_frag_data.tune)
1289 case PROCESSOR_UNKNOWN:
1290 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1291 PROCESSOR_UNKNOWN. */
1295 case PROCESSOR_I386:
1296 case PROCESSOR_I486:
1297 case PROCESSOR_PENTIUM:
1299 case PROCESSOR_ATHLON:
1301 case PROCESSOR_AMDFAM10:
1304 case PROCESSOR_GENERIC32:
1305 /* We use cpu_arch_isa_flags to check if we CAN optimize
1307 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1308 patt = alt_short_patt;
1312 case PROCESSOR_PENTIUMPRO:
1313 case PROCESSOR_PENTIUM4:
1314 case PROCESSOR_NOCONA:
1315 case PROCESSOR_CORE:
1316 case PROCESSOR_CORE2:
1317 case PROCESSOR_COREI7:
1318 case PROCESSOR_L1OM:
1319 case PROCESSOR_K1OM:
1320 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1321 patt = alt_long_patt;
1325 case PROCESSOR_GENERIC64:
1326 patt = alt_long_patt;
1331 if (patt == f32_patt)
1333 /* If the padding is less than 15 bytes, we use the normal
1334 ones. Otherwise, we use a jump instruction and adjust
1338 /* For 64bit, the limit is 3 bytes. */
1339 if (flag_code == CODE_64BIT
1340 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1345 memcpy (fragP->fr_literal + fragP->fr_fix,
1346 patt[count - 1], count);
1349 memcpy (fragP->fr_literal + fragP->fr_fix,
1351 /* Adjust jump offset. */
1352 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1357 /* Maximum length of an instruction is 15 byte. If the
1358 padding is greater than 15 bytes and we don't use jump,
1359 we have to break it into smaller pieces. */
1360 int padding = count;
1361 while (padding > 15)
1364 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1369 memcpy (fragP->fr_literal + fragP->fr_fix,
1370 patt [padding - 1], padding);
1373 fragP->fr_var = count;
1377 operand_type_all_zero (const union i386_operand_type *x)
1379 switch (ARRAY_SIZE(x->array))
1388 return !x->array[0];
1395 operand_type_set (union i386_operand_type *x, unsigned int v)
1397 switch (ARRAY_SIZE(x->array))
1412 operand_type_equal (const union i386_operand_type *x,
1413 const union i386_operand_type *y)
1415 switch (ARRAY_SIZE(x->array))
1418 if (x->array[2] != y->array[2])
1421 if (x->array[1] != y->array[1])
1424 return x->array[0] == y->array[0];
1432 cpu_flags_all_zero (const union i386_cpu_flags *x)
1434 switch (ARRAY_SIZE(x->array))
1443 return !x->array[0];
1450 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1452 switch (ARRAY_SIZE(x->array))
1467 cpu_flags_equal (const union i386_cpu_flags *x,
1468 const union i386_cpu_flags *y)
1470 switch (ARRAY_SIZE(x->array))
1473 if (x->array[2] != y->array[2])
1476 if (x->array[1] != y->array[1])
1479 return x->array[0] == y->array[0];
1487 cpu_flags_check_cpu64 (i386_cpu_flags f)
1489 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1490 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1493 static INLINE i386_cpu_flags
1494 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1496 switch (ARRAY_SIZE (x.array))
1499 x.array [2] &= y.array [2];
1501 x.array [1] &= y.array [1];
1503 x.array [0] &= y.array [0];
1511 static INLINE i386_cpu_flags
1512 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1514 switch (ARRAY_SIZE (x.array))
1517 x.array [2] |= y.array [2];
1519 x.array [1] |= y.array [1];
1521 x.array [0] |= y.array [0];
1529 static INLINE i386_cpu_flags
1530 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1532 switch (ARRAY_SIZE (x.array))
1535 x.array [2] &= ~y.array [2];
1537 x.array [1] &= ~y.array [1];
1539 x.array [0] &= ~y.array [0];
1547 #define CPU_FLAGS_ARCH_MATCH 0x1
1548 #define CPU_FLAGS_64BIT_MATCH 0x2
1549 #define CPU_FLAGS_AES_MATCH 0x4
1550 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1551 #define CPU_FLAGS_AVX_MATCH 0x10
1553 #define CPU_FLAGS_32BIT_MATCH \
1554 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1555 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1556 #define CPU_FLAGS_PERFECT_MATCH \
1557 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1559 /* Return CPU flags match bits. */
1562 cpu_flags_match (const insn_template *t)
1564 i386_cpu_flags x = t->cpu_flags;
1565 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1567 x.bitfield.cpu64 = 0;
1568 x.bitfield.cpuno64 = 0;
1570 if (cpu_flags_all_zero (&x))
1572 /* This instruction is available on all archs. */
1573 match |= CPU_FLAGS_32BIT_MATCH;
1577 /* This instruction is available only on some archs. */
1578 i386_cpu_flags cpu = cpu_arch_flags;
1580 cpu.bitfield.cpu64 = 0;
1581 cpu.bitfield.cpuno64 = 0;
1582 cpu = cpu_flags_and (x, cpu);
1583 if (!cpu_flags_all_zero (&cpu))
1585 if (x.bitfield.cpuavx)
1587 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1588 if (cpu.bitfield.cpuavx)
1590 /* Check SSE2AVX. */
1591 if (!t->opcode_modifier.sse2avx|| sse2avx)
1593 match |= (CPU_FLAGS_ARCH_MATCH
1594 | CPU_FLAGS_AVX_MATCH);
1596 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1597 match |= CPU_FLAGS_AES_MATCH;
1599 if (!x.bitfield.cpupclmul
1600 || cpu.bitfield.cpupclmul)
1601 match |= CPU_FLAGS_PCLMUL_MATCH;
1605 match |= CPU_FLAGS_ARCH_MATCH;
1608 match |= CPU_FLAGS_32BIT_MATCH;
1614 static INLINE i386_operand_type
1615 operand_type_and (i386_operand_type x, i386_operand_type y)
1617 switch (ARRAY_SIZE (x.array))
1620 x.array [2] &= y.array [2];
1622 x.array [1] &= y.array [1];
1624 x.array [0] &= y.array [0];
1632 static INLINE i386_operand_type
1633 operand_type_or (i386_operand_type x, i386_operand_type y)
1635 switch (ARRAY_SIZE (x.array))
1638 x.array [2] |= y.array [2];
1640 x.array [1] |= y.array [1];
1642 x.array [0] |= y.array [0];
1650 static INLINE i386_operand_type
1651 operand_type_xor (i386_operand_type x, i386_operand_type y)
1653 switch (ARRAY_SIZE (x.array))
1656 x.array [2] ^= y.array [2];
1658 x.array [1] ^= y.array [1];
1660 x.array [0] ^= y.array [0];
1668 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1669 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1670 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1671 static const i386_operand_type inoutportreg
1672 = OPERAND_TYPE_INOUTPORTREG;
1673 static const i386_operand_type reg16_inoutportreg
1674 = OPERAND_TYPE_REG16_INOUTPORTREG;
1675 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1676 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1677 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1678 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1679 static const i386_operand_type anydisp
1680 = OPERAND_TYPE_ANYDISP;
1681 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1682 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1683 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1684 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1685 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1686 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1687 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1688 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1689 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1690 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1691 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1692 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1693 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1694 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1705 operand_type_check (i386_operand_type t, enum operand_type c)
1710 return (t.bitfield.reg8
1713 || t.bitfield.reg64);
1716 return (t.bitfield.imm8
1720 || t.bitfield.imm32s
1721 || t.bitfield.imm64);
1724 return (t.bitfield.disp8
1725 || t.bitfield.disp16
1726 || t.bitfield.disp32
1727 || t.bitfield.disp32s
1728 || t.bitfield.disp64);
1731 return (t.bitfield.disp8
1732 || t.bitfield.disp16
1733 || t.bitfield.disp32
1734 || t.bitfield.disp32s
1735 || t.bitfield.disp64
1736 || t.bitfield.baseindex);
1745 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1746 operand J for instruction template T. */
1749 match_reg_size (const insn_template *t, unsigned int j)
1751 return !((i.types[j].bitfield.byte
1752 && !t->operand_types[j].bitfield.byte)
1753 || (i.types[j].bitfield.word
1754 && !t->operand_types[j].bitfield.word)
1755 || (i.types[j].bitfield.dword
1756 && !t->operand_types[j].bitfield.dword)
1757 || (i.types[j].bitfield.qword
1758 && !t->operand_types[j].bitfield.qword));
1761 /* Return 1 if there is no conflict in any size on operand J for
1762 instruction template T. */
1765 match_mem_size (const insn_template *t, unsigned int j)
1767 return (match_reg_size (t, j)
1768 && !((i.types[j].bitfield.unspecified
1769 && !t->operand_types[j].bitfield.unspecified)
1770 || (i.types[j].bitfield.fword
1771 && !t->operand_types[j].bitfield.fword)
1772 || (i.types[j].bitfield.tbyte
1773 && !t->operand_types[j].bitfield.tbyte)
1774 || (i.types[j].bitfield.xmmword
1775 && !t->operand_types[j].bitfield.xmmword)
1776 || (i.types[j].bitfield.ymmword
1777 && !t->operand_types[j].bitfield.ymmword)
1778 || (i.types[j].bitfield.zmmword
1779 && !t->operand_types[j].bitfield.zmmword)));
1782 /* Return 1 if there is no size conflict on any operands for
1783 instruction template T. */
1786 operand_size_match (const insn_template *t)
1791 /* Don't check jump instructions. */
1792 if (t->opcode_modifier.jump
1793 || t->opcode_modifier.jumpbyte
1794 || t->opcode_modifier.jumpdword
1795 || t->opcode_modifier.jumpintersegment)
1798 /* Check memory and accumulator operand size. */
1799 for (j = 0; j < i.operands; j++)
1801 if (t->operand_types[j].bitfield.anysize)
1804 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1810 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1819 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1822 i.error = operand_size_mismatch;
1826 /* Check reverse. */
1827 gas_assert (i.operands == 2);
1830 for (j = 0; j < 2; j++)
1832 if (t->operand_types[j].bitfield.acc
1833 && !match_reg_size (t, j ? 0 : 1))
1836 if (i.types[j].bitfield.mem
1837 && !match_mem_size (t, j ? 0 : 1))
1845 operand_type_match (i386_operand_type overlap,
1846 i386_operand_type given)
1848 i386_operand_type temp = overlap;
1850 temp.bitfield.jumpabsolute = 0;
1851 temp.bitfield.unspecified = 0;
1852 temp.bitfield.byte = 0;
1853 temp.bitfield.word = 0;
1854 temp.bitfield.dword = 0;
1855 temp.bitfield.fword = 0;
1856 temp.bitfield.qword = 0;
1857 temp.bitfield.tbyte = 0;
1858 temp.bitfield.xmmword = 0;
1859 temp.bitfield.ymmword = 0;
1860 temp.bitfield.zmmword = 0;
1861 if (operand_type_all_zero (&temp))
1864 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1865 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1869 i.error = operand_type_mismatch;
1873 /* If given types g0 and g1 are registers they must be of the same type
1874 unless the expected operand type register overlap is null.
1875 Note that Acc in a template matches every size of reg. */
1878 operand_type_register_match (i386_operand_type m0,
1879 i386_operand_type g0,
1880 i386_operand_type t0,
1881 i386_operand_type m1,
1882 i386_operand_type g1,
1883 i386_operand_type t1)
1885 if (!operand_type_check (g0, reg))
1888 if (!operand_type_check (g1, reg))
1891 if (g0.bitfield.reg8 == g1.bitfield.reg8
1892 && g0.bitfield.reg16 == g1.bitfield.reg16
1893 && g0.bitfield.reg32 == g1.bitfield.reg32
1894 && g0.bitfield.reg64 == g1.bitfield.reg64)
1897 if (m0.bitfield.acc)
1899 t0.bitfield.reg8 = 1;
1900 t0.bitfield.reg16 = 1;
1901 t0.bitfield.reg32 = 1;
1902 t0.bitfield.reg64 = 1;
1905 if (m1.bitfield.acc)
1907 t1.bitfield.reg8 = 1;
1908 t1.bitfield.reg16 = 1;
1909 t1.bitfield.reg32 = 1;
1910 t1.bitfield.reg64 = 1;
1913 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1914 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1915 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1916 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1919 i.error = register_type_mismatch;
1924 static INLINE unsigned int
1925 register_number (const reg_entry *r)
1927 unsigned int nr = r->reg_num;
1929 if (r->reg_flags & RegRex)
1935 static INLINE unsigned int
1936 mode_from_disp_size (i386_operand_type t)
1938 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1940 else if (t.bitfield.disp16
1941 || t.bitfield.disp32
1942 || t.bitfield.disp32s)
1949 fits_in_signed_byte (offsetT num)
1951 return (num >= -128) && (num <= 127);
1955 fits_in_unsigned_byte (offsetT num)
1957 return (num & 0xff) == num;
1961 fits_in_unsigned_word (offsetT num)
1963 return (num & 0xffff) == num;
1967 fits_in_signed_word (offsetT num)
1969 return (-32768 <= num) && (num <= 32767);
1973 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1978 return (!(((offsetT) -1 << 31) & num)
1979 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1981 } /* fits_in_signed_long() */
1984 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1989 return (num & (((offsetT) 2 << 31) - 1)) == num;
1991 } /* fits_in_unsigned_long() */
1994 fits_in_vec_disp8 (offsetT num)
1996 int shift = i.memshift;
2002 mask = (1 << shift) - 1;
2004 /* Return 0 if NUM isn't properly aligned. */
2008 /* Check if NUM will fit in 8bit after shift. */
2009 return fits_in_signed_byte (num >> shift);
2013 fits_in_imm4 (offsetT num)
2015 return (num & 0xf) == num;
2018 static i386_operand_type
2019 smallest_imm_type (offsetT num)
2021 i386_operand_type t;
2023 operand_type_set (&t, 0);
2024 t.bitfield.imm64 = 1;
2026 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2028 /* This code is disabled on the 486 because all the Imm1 forms
2029 in the opcode table are slower on the i486. They're the
2030 versions with the implicitly specified single-position
2031 displacement, which has another syntax if you really want to
2033 t.bitfield.imm1 = 1;
2034 t.bitfield.imm8 = 1;
2035 t.bitfield.imm8s = 1;
2036 t.bitfield.imm16 = 1;
2037 t.bitfield.imm32 = 1;
2038 t.bitfield.imm32s = 1;
2040 else if (fits_in_signed_byte (num))
2042 t.bitfield.imm8 = 1;
2043 t.bitfield.imm8s = 1;
2044 t.bitfield.imm16 = 1;
2045 t.bitfield.imm32 = 1;
2046 t.bitfield.imm32s = 1;
2048 else if (fits_in_unsigned_byte (num))
2050 t.bitfield.imm8 = 1;
2051 t.bitfield.imm16 = 1;
2052 t.bitfield.imm32 = 1;
2053 t.bitfield.imm32s = 1;
2055 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2057 t.bitfield.imm16 = 1;
2058 t.bitfield.imm32 = 1;
2059 t.bitfield.imm32s = 1;
2061 else if (fits_in_signed_long (num))
2063 t.bitfield.imm32 = 1;
2064 t.bitfield.imm32s = 1;
2066 else if (fits_in_unsigned_long (num))
2067 t.bitfield.imm32 = 1;
2073 offset_in_range (offsetT val, int size)
2079 case 1: mask = ((addressT) 1 << 8) - 1; break;
2080 case 2: mask = ((addressT) 1 << 16) - 1; break;
2081 case 4: mask = ((addressT) 2 << 31) - 1; break;
2083 case 8: mask = ((addressT) 2 << 63) - 1; break;
2089 /* If BFD64, sign extend val for 32bit address mode. */
2090 if (flag_code != CODE_64BIT
2091 || i.prefix[ADDR_PREFIX])
2092 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2093 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2096 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2098 char buf1[40], buf2[40];
2100 sprint_value (buf1, val);
2101 sprint_value (buf2, val & mask);
2102 as_warn (_("%s shortened to %s"), buf1, buf2);
2116 a. PREFIX_EXIST if attempting to add a prefix where one from the
2117 same class already exists.
2118 b. PREFIX_LOCK if lock prefix is added.
2119 c. PREFIX_REP if rep/repne prefix is added.
2120 d. PREFIX_OTHER if other prefix is added.
2123 static enum PREFIX_GROUP
2124 add_prefix (unsigned int prefix)
2126 enum PREFIX_GROUP ret = PREFIX_OTHER;
2129 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2130 && flag_code == CODE_64BIT)
2132 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2133 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2134 && (prefix & (REX_R | REX_X | REX_B))))
2145 case CS_PREFIX_OPCODE:
2146 case DS_PREFIX_OPCODE:
2147 case ES_PREFIX_OPCODE:
2148 case FS_PREFIX_OPCODE:
2149 case GS_PREFIX_OPCODE:
2150 case SS_PREFIX_OPCODE:
2154 case REPNE_PREFIX_OPCODE:
2155 case REPE_PREFIX_OPCODE:
2160 case LOCK_PREFIX_OPCODE:
2169 case ADDR_PREFIX_OPCODE:
2173 case DATA_PREFIX_OPCODE:
2177 if (i.prefix[q] != 0)
2185 i.prefix[q] |= prefix;
2188 as_bad (_("same type of prefix used twice"));
2194 update_code_flag (int value, int check)
2196 PRINTF_LIKE ((*as_error));
2198 flag_code = (enum flag_code) value;
2199 if (flag_code == CODE_64BIT)
2201 cpu_arch_flags.bitfield.cpu64 = 1;
2202 cpu_arch_flags.bitfield.cpuno64 = 0;
2206 cpu_arch_flags.bitfield.cpu64 = 0;
2207 cpu_arch_flags.bitfield.cpuno64 = 1;
2209 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2212 as_error = as_fatal;
2215 (*as_error) (_("64bit mode not supported on `%s'."),
2216 cpu_arch_name ? cpu_arch_name : default_arch);
2218 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2221 as_error = as_fatal;
2224 (*as_error) (_("32bit mode not supported on `%s'."),
2225 cpu_arch_name ? cpu_arch_name : default_arch);
2227 stackop_size = '\0';
2231 set_code_flag (int value)
2233 update_code_flag (value, 0);
2237 set_16bit_gcc_code_flag (int new_code_flag)
2239 flag_code = (enum flag_code) new_code_flag;
2240 if (flag_code != CODE_16BIT)
2242 cpu_arch_flags.bitfield.cpu64 = 0;
2243 cpu_arch_flags.bitfield.cpuno64 = 1;
2244 stackop_size = LONG_MNEM_SUFFIX;
2248 set_intel_syntax (int syntax_flag)
2250 /* Find out if register prefixing is specified. */
2251 int ask_naked_reg = 0;
2254 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2256 char *string = input_line_pointer;
2257 int e = get_symbol_end ();
2259 if (strcmp (string, "prefix") == 0)
2261 else if (strcmp (string, "noprefix") == 0)
2264 as_bad (_("bad argument to syntax directive."));
2265 *input_line_pointer = e;
2267 demand_empty_rest_of_line ();
2269 intel_syntax = syntax_flag;
2271 if (ask_naked_reg == 0)
2272 allow_naked_reg = (intel_syntax
2273 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2275 allow_naked_reg = (ask_naked_reg < 0);
2277 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2279 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2280 identifier_chars['$'] = intel_syntax ? '$' : 0;
2281 register_prefix = allow_naked_reg ? "" : "%";
2285 set_intel_mnemonic (int mnemonic_flag)
2287 intel_mnemonic = mnemonic_flag;
2291 set_allow_index_reg (int flag)
2293 allow_index_reg = flag;
2297 set_check (int what)
2299 enum check_kind *kind;
2304 kind = &operand_check;
2315 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2317 char *string = input_line_pointer;
2318 int e = get_symbol_end ();
2320 if (strcmp (string, "none") == 0)
2322 else if (strcmp (string, "warning") == 0)
2323 *kind = check_warning;
2324 else if (strcmp (string, "error") == 0)
2325 *kind = check_error;
2327 as_bad (_("bad argument to %s_check directive."), str);
2328 *input_line_pointer = e;
2331 as_bad (_("missing argument for %s_check directive"), str);
2333 demand_empty_rest_of_line ();
2337 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2338 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2340 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2341 static const char *arch;
2343 /* Intel LIOM is only supported on ELF. */
2349 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2350 use default_arch. */
2351 arch = cpu_arch_name;
2353 arch = default_arch;
2356 /* If we are targeting Intel L1OM, we must enable it. */
2357 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2358 || new_flag.bitfield.cpul1om)
2361 /* If we are targeting Intel K1OM, we must enable it. */
2362 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2363 || new_flag.bitfield.cpuk1om)
2366 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2371 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2375 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2377 char *string = input_line_pointer;
2378 int e = get_symbol_end ();
2380 i386_cpu_flags flags;
2382 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2384 if (strcmp (string, cpu_arch[j].name) == 0)
2386 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2390 cpu_arch_name = cpu_arch[j].name;
2391 cpu_sub_arch_name = NULL;
2392 cpu_arch_flags = cpu_arch[j].flags;
2393 if (flag_code == CODE_64BIT)
2395 cpu_arch_flags.bitfield.cpu64 = 1;
2396 cpu_arch_flags.bitfield.cpuno64 = 0;
2400 cpu_arch_flags.bitfield.cpu64 = 0;
2401 cpu_arch_flags.bitfield.cpuno64 = 1;
2403 cpu_arch_isa = cpu_arch[j].type;
2404 cpu_arch_isa_flags = cpu_arch[j].flags;
2405 if (!cpu_arch_tune_set)
2407 cpu_arch_tune = cpu_arch_isa;
2408 cpu_arch_tune_flags = cpu_arch_isa_flags;
2413 if (!cpu_arch[j].negated)
2414 flags = cpu_flags_or (cpu_arch_flags,
2417 flags = cpu_flags_and_not (cpu_arch_flags,
2419 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2421 if (cpu_sub_arch_name)
2423 char *name = cpu_sub_arch_name;
2424 cpu_sub_arch_name = concat (name,
2426 (const char *) NULL);
2430 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2431 cpu_arch_flags = flags;
2432 cpu_arch_isa_flags = flags;
2434 *input_line_pointer = e;
2435 demand_empty_rest_of_line ();
2439 if (j >= ARRAY_SIZE (cpu_arch))
2440 as_bad (_("no such architecture: `%s'"), string);
2442 *input_line_pointer = e;
2445 as_bad (_("missing cpu architecture"));
2447 no_cond_jump_promotion = 0;
2448 if (*input_line_pointer == ','
2449 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2451 char *string = ++input_line_pointer;
2452 int e = get_symbol_end ();
2454 if (strcmp (string, "nojumps") == 0)
2455 no_cond_jump_promotion = 1;
2456 else if (strcmp (string, "jumps") == 0)
2459 as_bad (_("no such architecture modifier: `%s'"), string);
2461 *input_line_pointer = e;
2464 demand_empty_rest_of_line ();
2467 enum bfd_architecture
2470 if (cpu_arch_isa == PROCESSOR_L1OM)
2472 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2473 || flag_code != CODE_64BIT)
2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_arch_l1om;
2477 else if (cpu_arch_isa == PROCESSOR_K1OM)
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || flag_code != CODE_64BIT)
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_arch_k1om;
2485 return bfd_arch_i386;
2491 if (!strncmp (default_arch, "x86_64", 6))
2493 if (cpu_arch_isa == PROCESSOR_L1OM)
2495 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2496 || default_arch[6] != '\0')
2497 as_fatal (_("Intel L1OM is 64bit ELF only"));
2498 return bfd_mach_l1om;
2500 else if (cpu_arch_isa == PROCESSOR_K1OM)
2502 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2503 || default_arch[6] != '\0')
2504 as_fatal (_("Intel K1OM is 64bit ELF only"));
2505 return bfd_mach_k1om;
2507 else if (default_arch[6] == '\0')
2508 return bfd_mach_x86_64;
2510 return bfd_mach_x64_32;
2512 else if (!strcmp (default_arch, "i386"))
2513 return bfd_mach_i386_i386;
2515 as_fatal (_("unknown architecture"));
2521 const char *hash_err;
2523 /* Initialize op_hash hash table. */
2524 op_hash = hash_new ();
2527 const insn_template *optab;
2528 templates *core_optab;
2530 /* Setup for loop. */
2532 core_optab = (templates *) xmalloc (sizeof (templates));
2533 core_optab->start = optab;
2538 if (optab->name == NULL
2539 || strcmp (optab->name, (optab - 1)->name) != 0)
2541 /* different name --> ship out current template list;
2542 add to hash table; & begin anew. */
2543 core_optab->end = optab;
2544 hash_err = hash_insert (op_hash,
2546 (void *) core_optab);
2549 as_fatal (_("can't hash %s: %s"),
2553 if (optab->name == NULL)
2555 core_optab = (templates *) xmalloc (sizeof (templates));
2556 core_optab->start = optab;
2561 /* Initialize reg_hash hash table. */
2562 reg_hash = hash_new ();
2564 const reg_entry *regtab;
2565 unsigned int regtab_size = i386_regtab_size;
2567 for (regtab = i386_regtab; regtab_size--; regtab++)
2569 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2571 as_fatal (_("can't hash %s: %s"),
2577 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2582 for (c = 0; c < 256; c++)
2587 mnemonic_chars[c] = c;
2588 register_chars[c] = c;
2589 operand_chars[c] = c;
2591 else if (ISLOWER (c))
2593 mnemonic_chars[c] = c;
2594 register_chars[c] = c;
2595 operand_chars[c] = c;
2597 else if (ISUPPER (c))
2599 mnemonic_chars[c] = TOLOWER (c);
2600 register_chars[c] = mnemonic_chars[c];
2601 operand_chars[c] = c;
2603 else if (c == '{' || c == '}')
2604 operand_chars[c] = c;
2606 if (ISALPHA (c) || ISDIGIT (c))
2607 identifier_chars[c] = c;
2610 identifier_chars[c] = c;
2611 operand_chars[c] = c;
2616 identifier_chars['@'] = '@';
2619 identifier_chars['?'] = '?';
2620 operand_chars['?'] = '?';
2622 digit_chars['-'] = '-';
2623 mnemonic_chars['_'] = '_';
2624 mnemonic_chars['-'] = '-';
2625 mnemonic_chars['.'] = '.';
2626 identifier_chars['_'] = '_';
2627 identifier_chars['.'] = '.';
2629 for (p = operand_special_chars; *p != '\0'; p++)
2630 operand_chars[(unsigned char) *p] = *p;
2633 if (flag_code == CODE_64BIT)
2635 #if defined (OBJ_COFF) && defined (TE_PE)
2636 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2639 x86_dwarf2_return_column = 16;
2641 x86_cie_data_alignment = -8;
2645 x86_dwarf2_return_column = 8;
2646 x86_cie_data_alignment = -4;
2651 i386_print_statistics (FILE *file)
2653 hash_print_statistics (file, "i386 opcode", op_hash);
2654 hash_print_statistics (file, "i386 register", reg_hash);
2659 /* Debugging routines for md_assemble. */
2660 static void pte (insn_template *);
2661 static void pt (i386_operand_type);
2662 static void pe (expressionS *);
2663 static void ps (symbolS *);
2666 pi (char *line, i386_insn *x)
2670 fprintf (stdout, "%s: template ", line);
2672 fprintf (stdout, " address: base %s index %s scale %x\n",
2673 x->base_reg ? x->base_reg->reg_name : "none",
2674 x->index_reg ? x->index_reg->reg_name : "none",
2675 x->log2_scale_factor);
2676 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2677 x->rm.mode, x->rm.reg, x->rm.regmem);
2678 fprintf (stdout, " sib: base %x index %x scale %x\n",
2679 x->sib.base, x->sib.index, x->sib.scale);
2680 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2681 (x->rex & REX_W) != 0,
2682 (x->rex & REX_R) != 0,
2683 (x->rex & REX_X) != 0,
2684 (x->rex & REX_B) != 0);
2685 for (j = 0; j < x->operands; j++)
2687 fprintf (stdout, " #%d: ", j + 1);
2689 fprintf (stdout, "\n");
2690 if (x->types[j].bitfield.reg8
2691 || x->types[j].bitfield.reg16
2692 || x->types[j].bitfield.reg32
2693 || x->types[j].bitfield.reg64
2694 || x->types[j].bitfield.regmmx
2695 || x->types[j].bitfield.regxmm
2696 || x->types[j].bitfield.regymm
2697 || x->types[j].bitfield.regzmm
2698 || x->types[j].bitfield.sreg2
2699 || x->types[j].bitfield.sreg3
2700 || x->types[j].bitfield.control
2701 || x->types[j].bitfield.debug
2702 || x->types[j].bitfield.test)
2703 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2704 if (operand_type_check (x->types[j], imm))
2706 if (operand_type_check (x->types[j], disp))
2707 pe (x->op[j].disps);
2712 pte (insn_template *t)
2715 fprintf (stdout, " %d operands ", t->operands);
2716 fprintf (stdout, "opcode %x ", t->base_opcode);
2717 if (t->extension_opcode != None)
2718 fprintf (stdout, "ext %x ", t->extension_opcode);
2719 if (t->opcode_modifier.d)
2720 fprintf (stdout, "D");
2721 if (t->opcode_modifier.w)
2722 fprintf (stdout, "W");
2723 fprintf (stdout, "\n");
2724 for (j = 0; j < t->operands; j++)
2726 fprintf (stdout, " #%d type ", j + 1);
2727 pt (t->operand_types[j]);
2728 fprintf (stdout, "\n");
2735 fprintf (stdout, " operation %d\n", e->X_op);
2736 fprintf (stdout, " add_number %ld (%lx)\n",
2737 (long) e->X_add_number, (long) e->X_add_number);
2738 if (e->X_add_symbol)
2740 fprintf (stdout, " add_symbol ");
2741 ps (e->X_add_symbol);
2742 fprintf (stdout, "\n");
2746 fprintf (stdout, " op_symbol ");
2747 ps (e->X_op_symbol);
2748 fprintf (stdout, "\n");
2755 fprintf (stdout, "%s type %s%s",
2757 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2758 segment_name (S_GET_SEGMENT (s)));
2761 static struct type_name
2763 i386_operand_type mask;
2766 const type_names[] =
2768 { OPERAND_TYPE_REG8, "r8" },
2769 { OPERAND_TYPE_REG16, "r16" },
2770 { OPERAND_TYPE_REG32, "r32" },
2771 { OPERAND_TYPE_REG64, "r64" },
2772 { OPERAND_TYPE_IMM8, "i8" },
2773 { OPERAND_TYPE_IMM8, "i8s" },
2774 { OPERAND_TYPE_IMM16, "i16" },
2775 { OPERAND_TYPE_IMM32, "i32" },
2776 { OPERAND_TYPE_IMM32S, "i32s" },
2777 { OPERAND_TYPE_IMM64, "i64" },
2778 { OPERAND_TYPE_IMM1, "i1" },
2779 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2780 { OPERAND_TYPE_DISP8, "d8" },
2781 { OPERAND_TYPE_DISP16, "d16" },
2782 { OPERAND_TYPE_DISP32, "d32" },
2783 { OPERAND_TYPE_DISP32S, "d32s" },
2784 { OPERAND_TYPE_DISP64, "d64" },
2785 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2786 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2787 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2788 { OPERAND_TYPE_CONTROL, "control reg" },
2789 { OPERAND_TYPE_TEST, "test reg" },
2790 { OPERAND_TYPE_DEBUG, "debug reg" },
2791 { OPERAND_TYPE_FLOATREG, "FReg" },
2792 { OPERAND_TYPE_FLOATACC, "FAcc" },
2793 { OPERAND_TYPE_SREG2, "SReg2" },
2794 { OPERAND_TYPE_SREG3, "SReg3" },
2795 { OPERAND_TYPE_ACC, "Acc" },
2796 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2797 { OPERAND_TYPE_REGMMX, "rMMX" },
2798 { OPERAND_TYPE_REGXMM, "rXMM" },
2799 { OPERAND_TYPE_REGYMM, "rYMM" },
2800 { OPERAND_TYPE_REGZMM, "rZMM" },
2801 { OPERAND_TYPE_REGMASK, "Mask reg" },
2802 { OPERAND_TYPE_ESSEG, "es" },
2806 pt (i386_operand_type t)
2809 i386_operand_type a;
2811 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2813 a = operand_type_and (t, type_names[j].mask);
2814 if (!operand_type_all_zero (&a))
2815 fprintf (stdout, "%s, ", type_names[j].name);
2820 #endif /* DEBUG386 */
2822 static bfd_reloc_code_real_type
2823 reloc (unsigned int size,
2827 bfd_reloc_code_real_type other)
2829 if (other != NO_RELOC)
2831 reloc_howto_type *rel;
2836 case BFD_RELOC_X86_64_GOT32:
2837 return BFD_RELOC_X86_64_GOT64;
2839 case BFD_RELOC_X86_64_PLTOFF64:
2840 return BFD_RELOC_X86_64_PLTOFF64;
2842 case BFD_RELOC_X86_64_GOTPC32:
2843 other = BFD_RELOC_X86_64_GOTPC64;
2845 case BFD_RELOC_X86_64_GOTPCREL:
2846 other = BFD_RELOC_X86_64_GOTPCREL64;
2848 case BFD_RELOC_X86_64_TPOFF32:
2849 other = BFD_RELOC_X86_64_TPOFF64;
2851 case BFD_RELOC_X86_64_DTPOFF32:
2852 other = BFD_RELOC_X86_64_DTPOFF64;
2858 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2859 if (other == BFD_RELOC_SIZE32)
2862 other = BFD_RELOC_SIZE64;
2865 as_bad (_("there are no pc-relative size relocations"));
2871 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2872 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2875 rel = bfd_reloc_type_lookup (stdoutput, other);
2877 as_bad (_("unknown relocation (%u)"), other);
2878 else if (size != bfd_get_reloc_size (rel))
2879 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2880 bfd_get_reloc_size (rel),
2882 else if (pcrel && !rel->pc_relative)
2883 as_bad (_("non-pc-relative relocation for pc-relative field"));
2884 else if ((rel->complain_on_overflow == complain_overflow_signed
2886 || (rel->complain_on_overflow == complain_overflow_unsigned
2888 as_bad (_("relocated field and relocation type differ in signedness"));
2897 as_bad (_("there are no unsigned pc-relative relocations"));
2900 case 1: return BFD_RELOC_8_PCREL;
2901 case 2: return BFD_RELOC_16_PCREL;
2902 case 4: return (bnd_prefix && object_64bit
2903 ? BFD_RELOC_X86_64_PC32_BND
2904 : BFD_RELOC_32_PCREL);
2905 case 8: return BFD_RELOC_64_PCREL;
2907 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2914 case 4: return BFD_RELOC_X86_64_32S;
2919 case 1: return BFD_RELOC_8;
2920 case 2: return BFD_RELOC_16;
2921 case 4: return BFD_RELOC_32;
2922 case 8: return BFD_RELOC_64;
2924 as_bad (_("cannot do %s %u byte relocation"),
2925 sign > 0 ? "signed" : "unsigned", size);
2931 /* Here we decide which fixups can be adjusted to make them relative to
2932 the beginning of the section instead of the symbol. Basically we need
2933 to make sure that the dynamic relocations are done correctly, so in
2934 some cases we force the original symbol to be used. */
2937 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2939 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2943 /* Don't adjust pc-relative references to merge sections in 64-bit
2945 if (use_rela_relocations
2946 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2950 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2951 and changed later by validate_fix. */
2952 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2953 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2956 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2957 for size relocations. */
2958 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2959 || fixP->fx_r_type == BFD_RELOC_SIZE64
2960 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2961 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2962 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2963 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2964 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2965 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2966 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2967 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2968 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2969 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2970 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2972 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2973 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2974 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2975 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2976 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2977 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2978 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2979 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2980 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2981 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2982 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2983 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2985 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2986 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2987 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2994 intel_float_operand (const char *mnemonic)
2996 /* Note that the value returned is meaningful only for opcodes with (memory)
2997 operands, hence the code here is free to improperly handle opcodes that
2998 have no operands (for better performance and smaller code). */
3000 if (mnemonic[0] != 'f')
3001 return 0; /* non-math */
3003 switch (mnemonic[1])
3005 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3006 the fs segment override prefix not currently handled because no
3007 call path can make opcodes without operands get here */
3009 return 2 /* integer op */;
3011 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3012 return 3; /* fldcw/fldenv */
3015 if (mnemonic[2] != 'o' /* fnop */)
3016 return 3; /* non-waiting control op */
3019 if (mnemonic[2] == 's')
3020 return 3; /* frstor/frstpm */
3023 if (mnemonic[2] == 'a')
3024 return 3; /* fsave */
3025 if (mnemonic[2] == 't')
3027 switch (mnemonic[3])
3029 case 'c': /* fstcw */
3030 case 'd': /* fstdw */
3031 case 'e': /* fstenv */
3032 case 's': /* fsts[gw] */
3038 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3039 return 0; /* fxsave/fxrstor are not really math ops */
3046 /* Build the VEX prefix. */
3049 build_vex_prefix (const insn_template *t)
3051 unsigned int register_specifier;
3052 unsigned int implied_prefix;
3053 unsigned int vector_length;
3055 /* Check register specifier. */
3056 if (i.vex.register_specifier)
3058 register_specifier =
3059 ~register_number (i.vex.register_specifier) & 0xf;
3060 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3063 register_specifier = 0xf;
3065 /* Use 2-byte VEX prefix by swappping destination and source
3068 && i.operands == i.reg_operands
3069 && i.tm.opcode_modifier.vexopcode == VEX0F
3070 && i.tm.opcode_modifier.s
3073 unsigned int xchg = i.operands - 1;
3074 union i386_op temp_op;
3075 i386_operand_type temp_type;
3077 temp_type = i.types[xchg];
3078 i.types[xchg] = i.types[0];
3079 i.types[0] = temp_type;
3080 temp_op = i.op[xchg];
3081 i.op[xchg] = i.op[0];
3084 gas_assert (i.rm.mode == 3);
3088 i.rm.regmem = i.rm.reg;
3091 /* Use the next insn. */
3095 if (i.tm.opcode_modifier.vex == VEXScalar)
3096 vector_length = avxscalar;
3098 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3100 switch ((i.tm.base_opcode >> 8) & 0xff)
3105 case DATA_PREFIX_OPCODE:
3108 case REPE_PREFIX_OPCODE:
3111 case REPNE_PREFIX_OPCODE:
3118 /* Use 2-byte VEX prefix if possible. */
3119 if (i.tm.opcode_modifier.vexopcode == VEX0F
3120 && i.tm.opcode_modifier.vexw != VEXW1
3121 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3123 /* 2-byte VEX prefix. */
3127 i.vex.bytes[0] = 0xc5;
3129 /* Check the REX.R bit. */
3130 r = (i.rex & REX_R) ? 0 : 1;
3131 i.vex.bytes[1] = (r << 7
3132 | register_specifier << 3
3133 | vector_length << 2
3138 /* 3-byte VEX prefix. */
3143 switch (i.tm.opcode_modifier.vexopcode)
3147 i.vex.bytes[0] = 0xc4;
3151 i.vex.bytes[0] = 0xc4;
3155 i.vex.bytes[0] = 0xc4;
3159 i.vex.bytes[0] = 0x8f;
3163 i.vex.bytes[0] = 0x8f;
3167 i.vex.bytes[0] = 0x8f;
3173 /* The high 3 bits of the second VEX byte are 1's compliment
3174 of RXB bits from REX. */
3175 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3177 /* Check the REX.W bit. */
3178 w = (i.rex & REX_W) ? 1 : 0;
3179 if (i.tm.opcode_modifier.vexw == VEXW1)
3182 i.vex.bytes[2] = (w << 7
3183 | register_specifier << 3
3184 | vector_length << 2
3189 /* Build the EVEX prefix. */
3192 build_evex_prefix (void)
3194 unsigned int register_specifier;
3195 unsigned int implied_prefix;
3197 rex_byte vrex_used = 0;
3199 /* Check register specifier. */
3200 if (i.vex.register_specifier)
3202 gas_assert ((i.vrex & REX_X) == 0);
3204 register_specifier = i.vex.register_specifier->reg_num;
3205 if ((i.vex.register_specifier->reg_flags & RegRex))
3206 register_specifier += 8;
3207 /* The upper 16 registers are encoded in the fourth byte of the
3209 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3210 i.vex.bytes[3] = 0x8;
3211 register_specifier = ~register_specifier & 0xf;
3215 register_specifier = 0xf;
3217 /* Encode upper 16 vector index register in the fourth byte of
3219 if (!(i.vrex & REX_X))
3220 i.vex.bytes[3] = 0x8;
3225 switch ((i.tm.base_opcode >> 8) & 0xff)
3230 case DATA_PREFIX_OPCODE:
3233 case REPE_PREFIX_OPCODE:
3236 case REPNE_PREFIX_OPCODE:
3243 /* 4 byte EVEX prefix. */
3245 i.vex.bytes[0] = 0x62;
3248 switch (i.tm.opcode_modifier.vexopcode)
3264 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3266 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3268 /* The fifth bit of the second EVEX byte is 1's compliment of the
3269 REX_R bit in VREX. */
3270 if (!(i.vrex & REX_R))
3271 i.vex.bytes[1] |= 0x10;
3275 if ((i.reg_operands + i.imm_operands) == i.operands)
3277 /* When all operands are registers, the REX_X bit in REX is not
3278 used. We reuse it to encode the upper 16 registers, which is
3279 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3280 as 1's compliment. */
3281 if ((i.vrex & REX_B))
3284 i.vex.bytes[1] &= ~0x40;
3288 /* EVEX instructions shouldn't need the REX prefix. */
3289 i.vrex &= ~vrex_used;
3290 gas_assert (i.vrex == 0);
3292 /* Check the REX.W bit. */
3293 w = (i.rex & REX_W) ? 1 : 0;
3294 if (i.tm.opcode_modifier.vexw)
3296 if (i.tm.opcode_modifier.vexw == VEXW1)
3299 /* If w is not set it means we are dealing with WIG instruction. */
3302 if (evexwig == evexw1)
3306 /* Encode the U bit. */
3307 implied_prefix |= 0x4;
3309 /* The third byte of the EVEX prefix. */
3310 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3312 /* The fourth byte of the EVEX prefix. */
3313 /* The zeroing-masking bit. */
3314 if (i.mask && i.mask->zeroing)
3315 i.vex.bytes[3] |= 0x80;
3317 /* Don't always set the broadcast bit if there is no RC. */
3320 /* Encode the vector length. */
3321 unsigned int vec_length;
3323 switch (i.tm.opcode_modifier.evex)
3325 case EVEXLIG: /* LL' is ignored */
3326 vec_length = evexlig << 5;
3329 vec_length = 0 << 5;
3332 vec_length = 1 << 5;
3335 vec_length = 2 << 5;
3341 i.vex.bytes[3] |= vec_length;
3342 /* Encode the broadcast bit. */
3344 i.vex.bytes[3] |= 0x10;
3348 if (i.rounding->type != saeonly)
3349 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3351 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3354 if (i.mask && i.mask->mask)
3355 i.vex.bytes[3] |= i.mask->mask->reg_num;
3359 process_immext (void)
3363 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3366 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3367 with an opcode suffix which is coded in the same place as an
3368 8-bit immediate field would be.
3369 Here we check those operands and remove them afterwards. */
3372 for (x = 0; x < i.operands; x++)
3373 if (register_number (i.op[x].regs) != x)
3374 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3375 register_prefix, i.op[x].regs->reg_name, x + 1,
3381 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3382 which is coded in the same place as an 8-bit immediate field
3383 would be. Here we fake an 8-bit immediate operand from the
3384 opcode suffix stored in tm.extension_opcode.
3386 AVX instructions also use this encoding, for some of
3387 3 argument instructions. */
3389 gas_assert (i.imm_operands <= 1
3391 || ((i.tm.opcode_modifier.vex
3392 || i.tm.opcode_modifier.evex)
3393 && i.operands <= 4)));
3395 exp = &im_expressions[i.imm_operands++];
3396 i.op[i.operands].imms = exp;
3397 i.types[i.operands] = imm8;
3399 exp->X_op = O_constant;
3400 exp->X_add_number = i.tm.extension_opcode;
3401 i.tm.extension_opcode = None;
3408 switch (i.tm.opcode_modifier.hleprefixok)
3413 as_bad (_("invalid instruction `%s' after `%s'"),
3414 i.tm.name, i.hle_prefix);
3417 if (i.prefix[LOCK_PREFIX])
3419 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3423 case HLEPrefixRelease:
3424 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3426 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3430 if (i.mem_operands == 0
3431 || !operand_type_check (i.types[i.operands - 1], anymem))
3433 as_bad (_("memory destination needed for instruction `%s'"
3434 " after `xrelease'"), i.tm.name);
3441 /* This is the guts of the machine-dependent assembler. LINE points to a
3442 machine dependent instruction. This function is supposed to emit
3443 the frags/bytes it assembles to. */
3446 md_assemble (char *line)
3449 char mnemonic[MAX_MNEM_SIZE];
3450 const insn_template *t;
3452 /* Initialize globals. */
3453 memset (&i, '\0', sizeof (i));
3454 for (j = 0; j < MAX_OPERANDS; j++)
3455 i.reloc[j] = NO_RELOC;
3456 memset (disp_expressions, '\0', sizeof (disp_expressions));
3457 memset (im_expressions, '\0', sizeof (im_expressions));
3458 save_stack_p = save_stack;
3460 /* First parse an instruction mnemonic & call i386_operand for the operands.
3461 We assume that the scrubber has arranged it so that line[0] is the valid
3462 start of a (possibly prefixed) mnemonic. */
3464 line = parse_insn (line, mnemonic);
3468 line = parse_operands (line, mnemonic);
3473 /* Now we've parsed the mnemonic into a set of templates, and have the
3474 operands at hand. */
3476 /* All intel opcodes have reversed operands except for "bound" and
3477 "enter". We also don't reverse intersegment "jmp" and "call"
3478 instructions with 2 immediate operands so that the immediate segment
3479 precedes the offset, as it does when in AT&T mode. */
3482 && (strcmp (mnemonic, "bound") != 0)
3483 && (strcmp (mnemonic, "invlpga") != 0)
3484 && !(operand_type_check (i.types[0], imm)
3485 && operand_type_check (i.types[1], imm)))
3488 /* The order of the immediates should be reversed
3489 for 2 immediates extrq and insertq instructions */
3490 if (i.imm_operands == 2
3491 && (strcmp (mnemonic, "extrq") == 0
3492 || strcmp (mnemonic, "insertq") == 0))
3493 swap_2_operands (0, 1);
3498 /* Don't optimize displacement for movabs since it only takes 64bit
3501 && i.disp_encoding != disp_encoding_32bit
3502 && (flag_code != CODE_64BIT
3503 || strcmp (mnemonic, "movabs") != 0))
3506 /* Next, we find a template that matches the given insn,
3507 making sure the overlap of the given operands types is consistent
3508 with the template operand types. */
3510 if (!(t = match_template ()))
3513 if (sse_check != check_none
3514 && !i.tm.opcode_modifier.noavx
3515 && (i.tm.cpu_flags.bitfield.cpusse
3516 || i.tm.cpu_flags.bitfield.cpusse2
3517 || i.tm.cpu_flags.bitfield.cpusse3
3518 || i.tm.cpu_flags.bitfield.cpussse3
3519 || i.tm.cpu_flags.bitfield.cpusse4_1
3520 || i.tm.cpu_flags.bitfield.cpusse4_2))
3522 (sse_check == check_warning
3524 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3527 /* Zap movzx and movsx suffix. The suffix has been set from
3528 "word ptr" or "byte ptr" on the source operand in Intel syntax
3529 or extracted from mnemonic in AT&T syntax. But we'll use
3530 the destination register to choose the suffix for encoding. */
3531 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3533 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3534 there is no suffix, the default will be byte extension. */
3535 if (i.reg_operands != 2
3538 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3543 if (i.tm.opcode_modifier.fwait)
3544 if (!add_prefix (FWAIT_OPCODE))
3547 /* Check if REP prefix is OK. */
3548 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3550 as_bad (_("invalid instruction `%s' after `%s'"),
3551 i.tm.name, i.rep_prefix);
3555 /* Check for lock without a lockable instruction. Destination operand
3556 must be memory unless it is xchg (0x86). */
3557 if (i.prefix[LOCK_PREFIX]
3558 && (!i.tm.opcode_modifier.islockable
3559 || i.mem_operands == 0
3560 || (i.tm.base_opcode != 0x86
3561 && !operand_type_check (i.types[i.operands - 1], anymem))))
3563 as_bad (_("expecting lockable instruction after `lock'"));
3567 /* Check if HLE prefix is OK. */
3568 if (i.hle_prefix && !check_hle ())
3571 /* Check BND prefix. */
3572 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3573 as_bad (_("expecting valid branch instruction after `bnd'"));
3575 if (i.tm.cpu_flags.bitfield.cpumpx
3576 && flag_code == CODE_64BIT
3577 && i.prefix[ADDR_PREFIX])
3578 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3580 /* Insert BND prefix. */
3582 && i.tm.opcode_modifier.bndprefixok
3583 && !i.prefix[BND_PREFIX])
3584 add_prefix (BND_PREFIX_OPCODE);
3586 /* Check string instruction segment overrides. */
3587 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3589 if (!check_string ())
3591 i.disp_operands = 0;
3594 if (!process_suffix ())
3597 /* Update operand types. */
3598 for (j = 0; j < i.operands; j++)
3599 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3601 /* Make still unresolved immediate matches conform to size of immediate
3602 given in i.suffix. */
3603 if (!finalize_imm ())
3606 if (i.types[0].bitfield.imm1)
3607 i.imm_operands = 0; /* kludge for shift insns. */
3609 /* We only need to check those implicit registers for instructions
3610 with 3 operands or less. */
3611 if (i.operands <= 3)
3612 for (j = 0; j < i.operands; j++)
3613 if (i.types[j].bitfield.inoutportreg
3614 || i.types[j].bitfield.shiftcount
3615 || i.types[j].bitfield.acc
3616 || i.types[j].bitfield.floatacc)
3619 /* ImmExt should be processed after SSE2AVX. */
3620 if (!i.tm.opcode_modifier.sse2avx
3621 && i.tm.opcode_modifier.immext)
3624 /* For insns with operands there are more diddles to do to the opcode. */
3627 if (!process_operands ())
3630 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3632 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3633 as_warn (_("translating to `%sp'"), i.tm.name);
3636 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3638 if (flag_code == CODE_16BIT)
3640 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3645 if (i.tm.opcode_modifier.vex)
3646 build_vex_prefix (t);
3648 build_evex_prefix ();
3651 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3652 instructions may define INT_OPCODE as well, so avoid this corner
3653 case for those instructions that use MODRM. */
3654 if (i.tm.base_opcode == INT_OPCODE
3655 && !i.tm.opcode_modifier.modrm
3656 && i.op[0].imms->X_add_number == 3)
3658 i.tm.base_opcode = INT3_OPCODE;
3662 if ((i.tm.opcode_modifier.jump
3663 || i.tm.opcode_modifier.jumpbyte
3664 || i.tm.opcode_modifier.jumpdword)
3665 && i.op[0].disps->X_op == O_constant)
3667 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3668 the absolute address given by the constant. Since ix86 jumps and
3669 calls are pc relative, we need to generate a reloc. */
3670 i.op[0].disps->X_add_symbol = &abs_symbol;
3671 i.op[0].disps->X_op = O_symbol;
3674 if (i.tm.opcode_modifier.rex64)
3677 /* For 8 bit registers we need an empty rex prefix. Also if the
3678 instruction already has a prefix, we need to convert old
3679 registers to new ones. */
3681 if ((i.types[0].bitfield.reg8
3682 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3683 || (i.types[1].bitfield.reg8
3684 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3685 || ((i.types[0].bitfield.reg8
3686 || i.types[1].bitfield.reg8)
3691 i.rex |= REX_OPCODE;
3692 for (x = 0; x < 2; x++)
3694 /* Look for 8 bit operand that uses old registers. */
3695 if (i.types[x].bitfield.reg8
3696 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3698 /* In case it is "hi" register, give up. */
3699 if (i.op[x].regs->reg_num > 3)
3700 as_bad (_("can't encode register '%s%s' in an "
3701 "instruction requiring REX prefix."),
3702 register_prefix, i.op[x].regs->reg_name);
3704 /* Otherwise it is equivalent to the extended register.
3705 Since the encoding doesn't change this is merely
3706 cosmetic cleanup for debug output. */
3708 i.op[x].regs = i.op[x].regs + 8;
3714 add_prefix (REX_OPCODE | i.rex);
3716 /* We are ready to output the insn. */
3721 parse_insn (char *line, char *mnemonic)
3724 char *token_start = l;
3727 const insn_template *t;
3733 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3738 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3740 as_bad (_("no such instruction: `%s'"), token_start);
3745 if (!is_space_char (*l)
3746 && *l != END_OF_INSN
3748 || (*l != PREFIX_SEPARATOR
3751 as_bad (_("invalid character %s in mnemonic"),
3752 output_invalid (*l));
3755 if (token_start == l)
3757 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3758 as_bad (_("expecting prefix; got nothing"));
3760 as_bad (_("expecting mnemonic; got nothing"));
3764 /* Look up instruction (or prefix) via hash table. */
3765 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3767 if (*l != END_OF_INSN
3768 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3769 && current_templates
3770 && current_templates->start->opcode_modifier.isprefix)
3772 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3774 as_bad ((flag_code != CODE_64BIT
3775 ? _("`%s' is only supported in 64-bit mode")
3776 : _("`%s' is not supported in 64-bit mode")),
3777 current_templates->start->name);
3780 /* If we are in 16-bit mode, do not allow addr16 or data16.
3781 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3782 if ((current_templates->start->opcode_modifier.size16
3783 || current_templates->start->opcode_modifier.size32)
3784 && flag_code != CODE_64BIT
3785 && (current_templates->start->opcode_modifier.size32
3786 ^ (flag_code == CODE_16BIT)))
3788 as_bad (_("redundant %s prefix"),
3789 current_templates->start->name);
3792 /* Add prefix, checking for repeated prefixes. */
3793 switch (add_prefix (current_templates->start->base_opcode))
3798 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3799 i.hle_prefix = current_templates->start->name;
3800 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3801 i.bnd_prefix = current_templates->start->name;
3803 i.rep_prefix = current_templates->start->name;
3808 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3815 if (!current_templates)
3817 /* Check if we should swap operand or force 32bit displacement in
3819 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3821 else if (mnem_p - 3 == dot_p
3824 i.disp_encoding = disp_encoding_8bit;
3825 else if (mnem_p - 4 == dot_p
3829 i.disp_encoding = disp_encoding_32bit;
3834 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3837 if (!current_templates)
3840 /* See if we can get a match by trimming off a suffix. */
3843 case WORD_MNEM_SUFFIX:
3844 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3845 i.suffix = SHORT_MNEM_SUFFIX;
3847 case BYTE_MNEM_SUFFIX:
3848 case QWORD_MNEM_SUFFIX:
3849 i.suffix = mnem_p[-1];
3851 current_templates = (const templates *) hash_find (op_hash,
3854 case SHORT_MNEM_SUFFIX:
3855 case LONG_MNEM_SUFFIX:
3858 i.suffix = mnem_p[-1];
3860 current_templates = (const templates *) hash_find (op_hash,
3869 if (intel_float_operand (mnemonic) == 1)
3870 i.suffix = SHORT_MNEM_SUFFIX;
3872 i.suffix = LONG_MNEM_SUFFIX;
3874 current_templates = (const templates *) hash_find (op_hash,
3879 if (!current_templates)
3881 as_bad (_("no such instruction: `%s'"), token_start);
3886 if (current_templates->start->opcode_modifier.jump
3887 || current_templates->start->opcode_modifier.jumpbyte)
3889 /* Check for a branch hint. We allow ",pt" and ",pn" for
3890 predict taken and predict not taken respectively.
3891 I'm not sure that branch hints actually do anything on loop
3892 and jcxz insns (JumpByte) for current Pentium4 chips. They
3893 may work in the future and it doesn't hurt to accept them
3895 if (l[0] == ',' && l[1] == 'p')
3899 if (!add_prefix (DS_PREFIX_OPCODE))
3903 else if (l[2] == 'n')
3905 if (!add_prefix (CS_PREFIX_OPCODE))
3911 /* Any other comma loses. */
3914 as_bad (_("invalid character %s in mnemonic"),
3915 output_invalid (*l));
3919 /* Check if instruction is supported on specified architecture. */
3921 for (t = current_templates->start; t < current_templates->end; ++t)
3923 supported |= cpu_flags_match (t);
3924 if (supported == CPU_FLAGS_PERFECT_MATCH)
3928 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3930 as_bad (flag_code == CODE_64BIT
3931 ? _("`%s' is not supported in 64-bit mode")
3932 : _("`%s' is only supported in 64-bit mode"),
3933 current_templates->start->name);
3936 if (supported != CPU_FLAGS_PERFECT_MATCH)
3938 as_bad (_("`%s' is not supported on `%s%s'"),
3939 current_templates->start->name,
3940 cpu_arch_name ? cpu_arch_name : default_arch,
3941 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3946 if (!cpu_arch_flags.bitfield.cpui386
3947 && (flag_code != CODE_16BIT))
3949 as_warn (_("use .code16 to ensure correct addressing mode"));
3956 parse_operands (char *l, const char *mnemonic)
3960 /* 1 if operand is pending after ','. */
3961 unsigned int expecting_operand = 0;
3963 /* Non-zero if operand parens not balanced. */
3964 unsigned int paren_not_balanced;
3966 while (*l != END_OF_INSN)
3968 /* Skip optional white space before operand. */
3969 if (is_space_char (*l))
3971 if (!is_operand_char (*l) && *l != END_OF_INSN)
3973 as_bad (_("invalid character %s before operand %d"),
3974 output_invalid (*l),
3978 token_start = l; /* after white space */
3979 paren_not_balanced = 0;
3980 while (paren_not_balanced || *l != ',')
3982 if (*l == END_OF_INSN)
3984 if (paren_not_balanced)
3987 as_bad (_("unbalanced parenthesis in operand %d."),
3990 as_bad (_("unbalanced brackets in operand %d."),
3995 break; /* we are done */
3997 else if (!is_operand_char (*l) && !is_space_char (*l))
3999 as_bad (_("invalid character %s in operand %d"),
4000 output_invalid (*l),
4007 ++paren_not_balanced;
4009 --paren_not_balanced;
4014 ++paren_not_balanced;
4016 --paren_not_balanced;
4020 if (l != token_start)
4021 { /* Yes, we've read in another operand. */
4022 unsigned int operand_ok;
4023 this_operand = i.operands++;
4024 i.types[this_operand].bitfield.unspecified = 1;
4025 if (i.operands > MAX_OPERANDS)
4027 as_bad (_("spurious operands; (%d operands/instruction max)"),
4031 /* Now parse operand adding info to 'i' as we go along. */
4032 END_STRING_AND_SAVE (l);
4036 i386_intel_operand (token_start,
4037 intel_float_operand (mnemonic));
4039 operand_ok = i386_att_operand (token_start);
4041 RESTORE_END_STRING (l);
4047 if (expecting_operand)
4049 expecting_operand_after_comma:
4050 as_bad (_("expecting operand after ','; got nothing"));
4055 as_bad (_("expecting operand before ','; got nothing"));
4060 /* Now *l must be either ',' or END_OF_INSN. */
4063 if (*++l == END_OF_INSN)
4065 /* Just skip it, if it's \n complain. */
4066 goto expecting_operand_after_comma;
4068 expecting_operand = 1;
4075 swap_2_operands (int xchg1, int xchg2)
4077 union i386_op temp_op;
4078 i386_operand_type temp_type;
4079 enum bfd_reloc_code_real temp_reloc;
4081 temp_type = i.types[xchg2];
4082 i.types[xchg2] = i.types[xchg1];
4083 i.types[xchg1] = temp_type;
4084 temp_op = i.op[xchg2];
4085 i.op[xchg2] = i.op[xchg1];
4086 i.op[xchg1] = temp_op;
4087 temp_reloc = i.reloc[xchg2];
4088 i.reloc[xchg2] = i.reloc[xchg1];
4089 i.reloc[xchg1] = temp_reloc;
4093 if (i.mask->operand == xchg1)
4094 i.mask->operand = xchg2;
4095 else if (i.mask->operand == xchg2)
4096 i.mask->operand = xchg1;
4100 if (i.broadcast->operand == xchg1)
4101 i.broadcast->operand = xchg2;
4102 else if (i.broadcast->operand == xchg2)
4103 i.broadcast->operand = xchg1;
4107 if (i.rounding->operand == xchg1)
4108 i.rounding->operand = xchg2;
4109 else if (i.rounding->operand == xchg2)
4110 i.rounding->operand = xchg1;
4115 swap_operands (void)
4121 swap_2_operands (1, i.operands - 2);
4124 swap_2_operands (0, i.operands - 1);
4130 if (i.mem_operands == 2)
4132 const seg_entry *temp_seg;
4133 temp_seg = i.seg[0];
4134 i.seg[0] = i.seg[1];
4135 i.seg[1] = temp_seg;
4139 /* Try to ensure constant immediates are represented in the smallest
4144 char guess_suffix = 0;
4148 guess_suffix = i.suffix;
4149 else if (i.reg_operands)
4151 /* Figure out a suffix from the last register operand specified.
4152 We can't do this properly yet, ie. excluding InOutPortReg,
4153 but the following works for instructions with immediates.
4154 In any case, we can't set i.suffix yet. */
4155 for (op = i.operands; --op >= 0;)
4156 if (i.types[op].bitfield.reg8)
4158 guess_suffix = BYTE_MNEM_SUFFIX;
4161 else if (i.types[op].bitfield.reg16)
4163 guess_suffix = WORD_MNEM_SUFFIX;
4166 else if (i.types[op].bitfield.reg32)
4168 guess_suffix = LONG_MNEM_SUFFIX;
4171 else if (i.types[op].bitfield.reg64)
4173 guess_suffix = QWORD_MNEM_SUFFIX;
4177 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4178 guess_suffix = WORD_MNEM_SUFFIX;
4180 for (op = i.operands; --op >= 0;)
4181 if (operand_type_check (i.types[op], imm))
4183 switch (i.op[op].imms->X_op)
4186 /* If a suffix is given, this operand may be shortened. */
4187 switch (guess_suffix)
4189 case LONG_MNEM_SUFFIX:
4190 i.types[op].bitfield.imm32 = 1;
4191 i.types[op].bitfield.imm64 = 1;
4193 case WORD_MNEM_SUFFIX:
4194 i.types[op].bitfield.imm16 = 1;
4195 i.types[op].bitfield.imm32 = 1;
4196 i.types[op].bitfield.imm32s = 1;
4197 i.types[op].bitfield.imm64 = 1;
4199 case BYTE_MNEM_SUFFIX:
4200 i.types[op].bitfield.imm8 = 1;
4201 i.types[op].bitfield.imm8s = 1;
4202 i.types[op].bitfield.imm16 = 1;
4203 i.types[op].bitfield.imm32 = 1;
4204 i.types[op].bitfield.imm32s = 1;
4205 i.types[op].bitfield.imm64 = 1;
4209 /* If this operand is at most 16 bits, convert it
4210 to a signed 16 bit number before trying to see
4211 whether it will fit in an even smaller size.
4212 This allows a 16-bit operand such as $0xffe0 to
4213 be recognised as within Imm8S range. */
4214 if ((i.types[op].bitfield.imm16)
4215 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4217 i.op[op].imms->X_add_number =
4218 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4220 if ((i.types[op].bitfield.imm32)
4221 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4224 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4225 ^ ((offsetT) 1 << 31))
4226 - ((offsetT) 1 << 31));
4229 = operand_type_or (i.types[op],
4230 smallest_imm_type (i.op[op].imms->X_add_number));
4232 /* We must avoid matching of Imm32 templates when 64bit
4233 only immediate is available. */
4234 if (guess_suffix == QWORD_MNEM_SUFFIX)
4235 i.types[op].bitfield.imm32 = 0;
4242 /* Symbols and expressions. */
4244 /* Convert symbolic operand to proper sizes for matching, but don't
4245 prevent matching a set of insns that only supports sizes other
4246 than those matching the insn suffix. */
4248 i386_operand_type mask, allowed;
4249 const insn_template *t;
4251 operand_type_set (&mask, 0);
4252 operand_type_set (&allowed, 0);
4254 for (t = current_templates->start;
4255 t < current_templates->end;
4257 allowed = operand_type_or (allowed,
4258 t->operand_types[op]);
4259 switch (guess_suffix)
4261 case QWORD_MNEM_SUFFIX:
4262 mask.bitfield.imm64 = 1;
4263 mask.bitfield.imm32s = 1;
4265 case LONG_MNEM_SUFFIX:
4266 mask.bitfield.imm32 = 1;
4268 case WORD_MNEM_SUFFIX:
4269 mask.bitfield.imm16 = 1;
4271 case BYTE_MNEM_SUFFIX:
4272 mask.bitfield.imm8 = 1;
4277 allowed = operand_type_and (mask, allowed);
4278 if (!operand_type_all_zero (&allowed))
4279 i.types[op] = operand_type_and (i.types[op], mask);
4286 /* Try to use the smallest displacement type too. */
4288 optimize_disp (void)
4292 for (op = i.operands; --op >= 0;)
4293 if (operand_type_check (i.types[op], disp))
4295 if (i.op[op].disps->X_op == O_constant)
4297 offsetT op_disp = i.op[op].disps->X_add_number;
4299 if (i.types[op].bitfield.disp16
4300 && (op_disp & ~(offsetT) 0xffff) == 0)
4302 /* If this operand is at most 16 bits, convert
4303 to a signed 16 bit number and don't use 64bit
4305 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4306 i.types[op].bitfield.disp64 = 0;
4308 if (i.types[op].bitfield.disp32
4309 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4311 /* If this operand is at most 32 bits, convert
4312 to a signed 32 bit number and don't use 64bit
4314 op_disp &= (((offsetT) 2 << 31) - 1);
4315 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4316 i.types[op].bitfield.disp64 = 0;
4318 if (!op_disp && i.types[op].bitfield.baseindex)
4320 i.types[op].bitfield.disp8 = 0;
4321 i.types[op].bitfield.disp16 = 0;
4322 i.types[op].bitfield.disp32 = 0;
4323 i.types[op].bitfield.disp32s = 0;
4324 i.types[op].bitfield.disp64 = 0;
4328 else if (flag_code == CODE_64BIT)
4330 if (fits_in_signed_long (op_disp))
4332 i.types[op].bitfield.disp64 = 0;
4333 i.types[op].bitfield.disp32s = 1;
4335 if (i.prefix[ADDR_PREFIX]
4336 && fits_in_unsigned_long (op_disp))
4337 i.types[op].bitfield.disp32 = 1;
4339 if ((i.types[op].bitfield.disp32
4340 || i.types[op].bitfield.disp32s
4341 || i.types[op].bitfield.disp16)
4342 && fits_in_signed_byte (op_disp))
4343 i.types[op].bitfield.disp8 = 1;
4345 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4346 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4348 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4349 i.op[op].disps, 0, i.reloc[op]);
4350 i.types[op].bitfield.disp8 = 0;
4351 i.types[op].bitfield.disp16 = 0;
4352 i.types[op].bitfield.disp32 = 0;
4353 i.types[op].bitfield.disp32s = 0;
4354 i.types[op].bitfield.disp64 = 0;
4357 /* We only support 64bit displacement on constants. */
4358 i.types[op].bitfield.disp64 = 0;
4362 /* Check if operands are valid for the instruction. */
4365 check_VecOperands (const insn_template *t)
4369 /* Without VSIB byte, we can't have a vector register for index. */
4370 if (!t->opcode_modifier.vecsib
4372 && (i.index_reg->reg_type.bitfield.regxmm
4373 || i.index_reg->reg_type.bitfield.regymm
4374 || i.index_reg->reg_type.bitfield.regzmm))
4376 i.error = unsupported_vector_index_register;
4380 /* Check if default mask is allowed. */
4381 if (t->opcode_modifier.nodefmask
4382 && (!i.mask || i.mask->mask->reg_num == 0))
4384 i.error = no_default_mask;
4388 /* For VSIB byte, we need a vector register for index, and all vector
4389 registers must be distinct. */
4390 if (t->opcode_modifier.vecsib)
4393 || !((t->opcode_modifier.vecsib == VecSIB128
4394 && i.index_reg->reg_type.bitfield.regxmm)
4395 || (t->opcode_modifier.vecsib == VecSIB256
4396 && i.index_reg->reg_type.bitfield.regymm)
4397 || (t->opcode_modifier.vecsib == VecSIB512
4398 && i.index_reg->reg_type.bitfield.regzmm)))
4400 i.error = invalid_vsib_address;
4404 gas_assert (i.reg_operands == 2 || i.mask);
4405 if (i.reg_operands == 2 && !i.mask)
4407 gas_assert (i.types[0].bitfield.regxmm
4408 || i.types[0].bitfield.regymm);
4409 gas_assert (i.types[2].bitfield.regxmm
4410 || i.types[2].bitfield.regymm);
4411 if (operand_check == check_none)
4413 if (register_number (i.op[0].regs)
4414 != register_number (i.index_reg)
4415 && register_number (i.op[2].regs)
4416 != register_number (i.index_reg)
4417 && register_number (i.op[0].regs)
4418 != register_number (i.op[2].regs))
4420 if (operand_check == check_error)
4422 i.error = invalid_vector_register_set;
4425 as_warn (_("mask, index, and destination registers should be distinct"));
4427 else if (i.reg_operands == 1 && i.mask)
4429 if ((i.types[1].bitfield.regymm
4430 || i.types[1].bitfield.regzmm)
4431 && (register_number (i.op[1].regs)
4432 == register_number (i.index_reg)))
4434 if (operand_check == check_error)
4436 i.error = invalid_vector_register_set;
4439 if (operand_check != check_none)
4440 as_warn (_("index and destination registers should be distinct"));
4445 /* Check if broadcast is supported by the instruction and is applied
4446 to the memory operand. */
4449 int broadcasted_opnd_size;
4451 /* Check if specified broadcast is supported in this instruction,
4452 and it's applied to memory operand of DWORD or QWORD type,
4453 depending on VecESize. */
4454 if (i.broadcast->type != t->opcode_modifier.broadcast
4455 || !i.types[i.broadcast->operand].bitfield.mem
4456 || (t->opcode_modifier.vecesize == 0
4457 && !i.types[i.broadcast->operand].bitfield.dword
4458 && !i.types[i.broadcast->operand].bitfield.unspecified)
4459 || (t->opcode_modifier.vecesize == 1
4460 && !i.types[i.broadcast->operand].bitfield.qword
4461 && !i.types[i.broadcast->operand].bitfield.unspecified))
4464 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4465 if (i.broadcast->type == BROADCAST_1TO16)
4466 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4467 else if (i.broadcast->type == BROADCAST_1TO8)
4468 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4469 else if (i.broadcast->type == BROADCAST_1TO4)
4470 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4471 else if (i.broadcast->type == BROADCAST_1TO2)
4472 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4476 if ((broadcasted_opnd_size == 256
4477 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4478 || (broadcasted_opnd_size == 512
4479 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4482 i.error = unsupported_broadcast;
4486 /* If broadcast is supported in this instruction, we need to check if
4487 operand of one-element size isn't specified without broadcast. */
4488 else if (t->opcode_modifier.broadcast && i.mem_operands)
4490 /* Find memory operand. */
4491 for (op = 0; op < i.operands; op++)
4492 if (operand_type_check (i.types[op], anymem))
4494 gas_assert (op < i.operands);
4495 /* Check size of the memory operand. */
4496 if ((t->opcode_modifier.vecesize == 0
4497 && i.types[op].bitfield.dword)
4498 || (t->opcode_modifier.vecesize == 1
4499 && i.types[op].bitfield.qword))
4501 i.error = broadcast_needed;
4506 /* Check if requested masking is supported. */
4508 && (!t->opcode_modifier.masking
4510 && t->opcode_modifier.masking == MERGING_MASKING)))
4512 i.error = unsupported_masking;
4516 /* Check if masking is applied to dest operand. */
4517 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4519 i.error = mask_not_on_destination;
4526 if ((i.rounding->type != saeonly
4527 && !t->opcode_modifier.staticrounding)
4528 || (i.rounding->type == saeonly
4529 && (t->opcode_modifier.staticrounding
4530 || !t->opcode_modifier.sae)))
4532 i.error = unsupported_rc_sae;
4535 /* If the instruction has several immediate operands and one of
4536 them is rounding, the rounding operand should be the last
4537 immediate operand. */
4538 if (i.imm_operands > 1
4539 && i.rounding->operand != (int) (i.imm_operands - 1))
4541 i.error = rc_sae_operand_not_last_imm;
4546 /* Check vector Disp8 operand. */
4547 if (t->opcode_modifier.disp8memshift)
4550 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4552 i.memshift = t->opcode_modifier.disp8memshift;
4554 for (op = 0; op < i.operands; op++)
4555 if (operand_type_check (i.types[op], disp)
4556 && i.op[op].disps->X_op == O_constant)
4558 offsetT value = i.op[op].disps->X_add_number;
4559 int vec_disp8_ok = fits_in_vec_disp8 (value);
4560 if (t->operand_types [op].bitfield.vec_disp8)
4563 i.types[op].bitfield.vec_disp8 = 1;
4566 /* Vector insn can only have Vec_Disp8/Disp32 in
4567 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4569 i.types[op].bitfield.disp8 = 0;
4570 if (flag_code != CODE_16BIT)
4571 i.types[op].bitfield.disp16 = 0;
4574 else if (flag_code != CODE_16BIT)
4576 /* One form of this instruction supports vector Disp8.
4577 Try vector Disp8 if we need to use Disp32. */
4578 if (vec_disp8_ok && !fits_in_signed_byte (value))
4580 i.error = try_vector_disp8;
4592 /* Check if operands are valid for the instruction. Update VEX
4596 VEX_check_operands (const insn_template *t)
4598 /* VREX is only valid with EVEX prefix. */
4599 if (i.need_vrex && !t->opcode_modifier.evex)
4601 i.error = invalid_register_operand;
4605 if (!t->opcode_modifier.vex)
4608 /* Only check VEX_Imm4, which must be the first operand. */
4609 if (t->operand_types[0].bitfield.vec_imm4)
4611 if (i.op[0].imms->X_op != O_constant
4612 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4618 /* Turn off Imm8 so that update_imm won't complain. */
4619 i.types[0] = vec_imm4;
4625 static const insn_template *
4626 match_template (void)
4628 /* Points to template once we've found it. */
4629 const insn_template *t;
4630 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4631 i386_operand_type overlap4;
4632 unsigned int found_reverse_match;
4633 i386_opcode_modifier suffix_check;
4634 i386_operand_type operand_types [MAX_OPERANDS];
4635 int addr_prefix_disp;
4637 unsigned int found_cpu_match;
4638 unsigned int check_register;
4639 enum i386_error specific_error = 0;
4641 #if MAX_OPERANDS != 5
4642 # error "MAX_OPERANDS must be 5."
4645 found_reverse_match = 0;
4646 addr_prefix_disp = -1;
4648 memset (&suffix_check, 0, sizeof (suffix_check));
4649 if (i.suffix == BYTE_MNEM_SUFFIX)
4650 suffix_check.no_bsuf = 1;
4651 else if (i.suffix == WORD_MNEM_SUFFIX)
4652 suffix_check.no_wsuf = 1;
4653 else if (i.suffix == SHORT_MNEM_SUFFIX)
4654 suffix_check.no_ssuf = 1;
4655 else if (i.suffix == LONG_MNEM_SUFFIX)
4656 suffix_check.no_lsuf = 1;
4657 else if (i.suffix == QWORD_MNEM_SUFFIX)
4658 suffix_check.no_qsuf = 1;
4659 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4660 suffix_check.no_ldsuf = 1;
4662 /* Must have right number of operands. */
4663 i.error = number_of_operands_mismatch;
4665 for (t = current_templates->start; t < current_templates->end; t++)
4667 addr_prefix_disp = -1;
4669 if (i.operands != t->operands)
4672 /* Check processor support. */
4673 i.error = unsupported;
4674 found_cpu_match = (cpu_flags_match (t)
4675 == CPU_FLAGS_PERFECT_MATCH);
4676 if (!found_cpu_match)
4679 /* Check old gcc support. */
4680 i.error = old_gcc_only;
4681 if (!old_gcc && t->opcode_modifier.oldgcc)
4684 /* Check AT&T mnemonic. */
4685 i.error = unsupported_with_intel_mnemonic;
4686 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4689 /* Check AT&T/Intel syntax. */
4690 i.error = unsupported_syntax;
4691 if ((intel_syntax && t->opcode_modifier.attsyntax)
4692 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4695 /* Check the suffix, except for some instructions in intel mode. */
4696 i.error = invalid_instruction_suffix;
4697 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4698 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4699 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4700 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4701 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4702 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4703 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4706 if (!operand_size_match (t))
4709 for (j = 0; j < MAX_OPERANDS; j++)
4710 operand_types[j] = t->operand_types[j];
4712 /* In general, don't allow 64-bit operands in 32-bit mode. */
4713 if (i.suffix == QWORD_MNEM_SUFFIX
4714 && flag_code != CODE_64BIT
4716 ? (!t->opcode_modifier.ignoresize
4717 && !intel_float_operand (t->name))
4718 : intel_float_operand (t->name) != 2)
4719 && ((!operand_types[0].bitfield.regmmx
4720 && !operand_types[0].bitfield.regxmm
4721 && !operand_types[0].bitfield.regymm
4722 && !operand_types[0].bitfield.regzmm)
4723 || (!operand_types[t->operands > 1].bitfield.regmmx
4724 && operand_types[t->operands > 1].bitfield.regxmm
4725 && operand_types[t->operands > 1].bitfield.regymm
4726 && operand_types[t->operands > 1].bitfield.regzmm))
4727 && (t->base_opcode != 0x0fc7
4728 || t->extension_opcode != 1 /* cmpxchg8b */))
4731 /* In general, don't allow 32-bit operands on pre-386. */
4732 else if (i.suffix == LONG_MNEM_SUFFIX
4733 && !cpu_arch_flags.bitfield.cpui386
4735 ? (!t->opcode_modifier.ignoresize
4736 && !intel_float_operand (t->name))
4737 : intel_float_operand (t->name) != 2)
4738 && ((!operand_types[0].bitfield.regmmx
4739 && !operand_types[0].bitfield.regxmm)
4740 || (!operand_types[t->operands > 1].bitfield.regmmx
4741 && operand_types[t->operands > 1].bitfield.regxmm)))
4744 /* Do not verify operands when there are none. */
4748 /* We've found a match; break out of loop. */
4752 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4753 into Disp32/Disp16/Disp32 operand. */
4754 if (i.prefix[ADDR_PREFIX] != 0)
4756 /* There should be only one Disp operand. */
4760 for (j = 0; j < MAX_OPERANDS; j++)
4762 if (operand_types[j].bitfield.disp16)
4764 addr_prefix_disp = j;
4765 operand_types[j].bitfield.disp32 = 1;
4766 operand_types[j].bitfield.disp16 = 0;
4772 for (j = 0; j < MAX_OPERANDS; j++)
4774 if (operand_types[j].bitfield.disp32)
4776 addr_prefix_disp = j;
4777 operand_types[j].bitfield.disp32 = 0;
4778 operand_types[j].bitfield.disp16 = 1;
4784 for (j = 0; j < MAX_OPERANDS; j++)
4786 if (operand_types[j].bitfield.disp64)
4788 addr_prefix_disp = j;
4789 operand_types[j].bitfield.disp64 = 0;
4790 operand_types[j].bitfield.disp32 = 1;
4798 /* We check register size if needed. */
4799 check_register = t->opcode_modifier.checkregsize;
4800 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4801 switch (t->operands)
4804 if (!operand_type_match (overlap0, i.types[0]))
4808 /* xchg %eax, %eax is a special case. It is an aliase for nop
4809 only in 32bit mode and we can use opcode 0x90. In 64bit
4810 mode, we can't use 0x90 for xchg %eax, %eax since it should
4811 zero-extend %eax to %rax. */
4812 if (flag_code == CODE_64BIT
4813 && t->base_opcode == 0x90
4814 && operand_type_equal (&i.types [0], &acc32)
4815 && operand_type_equal (&i.types [1], &acc32))
4819 /* If we swap operand in encoding, we either match
4820 the next one or reverse direction of operands. */
4821 if (t->opcode_modifier.s)
4823 else if (t->opcode_modifier.d)
4828 /* If we swap operand in encoding, we match the next one. */
4829 if (i.swap_operand && t->opcode_modifier.s)
4833 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4834 if (!operand_type_match (overlap0, i.types[0])
4835 || !operand_type_match (overlap1, i.types[1])
4837 && !operand_type_register_match (overlap0, i.types[0],
4839 overlap1, i.types[1],
4842 /* Check if other direction is valid ... */
4843 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4847 /* Try reversing direction of operands. */
4848 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4849 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4850 if (!operand_type_match (overlap0, i.types[0])
4851 || !operand_type_match (overlap1, i.types[1])
4853 && !operand_type_register_match (overlap0,
4860 /* Does not match either direction. */
4863 /* found_reverse_match holds which of D or FloatDR
4865 if (t->opcode_modifier.d)
4866 found_reverse_match = Opcode_D;
4867 else if (t->opcode_modifier.floatd)
4868 found_reverse_match = Opcode_FloatD;
4870 found_reverse_match = 0;
4871 if (t->opcode_modifier.floatr)
4872 found_reverse_match |= Opcode_FloatR;
4876 /* Found a forward 2 operand match here. */
4877 switch (t->operands)
4880 overlap4 = operand_type_and (i.types[4],
4883 overlap3 = operand_type_and (i.types[3],
4886 overlap2 = operand_type_and (i.types[2],
4891 switch (t->operands)
4894 if (!operand_type_match (overlap4, i.types[4])
4895 || !operand_type_register_match (overlap3,
4903 if (!operand_type_match (overlap3, i.types[3])
4905 && !operand_type_register_match (overlap2,
4913 /* Here we make use of the fact that there are no
4914 reverse match 3 operand instructions, and all 3
4915 operand instructions only need to be checked for
4916 register consistency between operands 2 and 3. */
4917 if (!operand_type_match (overlap2, i.types[2])
4919 && !operand_type_register_match (overlap1,
4929 /* Found either forward/reverse 2, 3 or 4 operand match here:
4930 slip through to break. */
4932 if (!found_cpu_match)
4934 found_reverse_match = 0;
4938 /* Check if vector and VEX operands are valid. */
4939 if (check_VecOperands (t) || VEX_check_operands (t))
4941 specific_error = i.error;
4945 /* We've found a match; break out of loop. */
4949 if (t == current_templates->end)
4951 /* We found no match. */
4952 const char *err_msg;
4953 switch (specific_error ? specific_error : i.error)
4957 case operand_size_mismatch:
4958 err_msg = _("operand size mismatch");
4960 case operand_type_mismatch:
4961 err_msg = _("operand type mismatch");
4963 case register_type_mismatch:
4964 err_msg = _("register type mismatch");
4966 case number_of_operands_mismatch:
4967 err_msg = _("number of operands mismatch");
4969 case invalid_instruction_suffix:
4970 err_msg = _("invalid instruction suffix");
4973 err_msg = _("constant doesn't fit in 4 bits");
4976 err_msg = _("only supported with old gcc");
4978 case unsupported_with_intel_mnemonic:
4979 err_msg = _("unsupported with Intel mnemonic");
4981 case unsupported_syntax:
4982 err_msg = _("unsupported syntax");
4985 as_bad (_("unsupported instruction `%s'"),
4986 current_templates->start->name);
4988 case invalid_vsib_address:
4989 err_msg = _("invalid VSIB address");
4991 case invalid_vector_register_set:
4992 err_msg = _("mask, index, and destination registers must be distinct");
4994 case unsupported_vector_index_register:
4995 err_msg = _("unsupported vector index register");
4997 case unsupported_broadcast:
4998 err_msg = _("unsupported broadcast");
5000 case broadcast_not_on_src_operand:
5001 err_msg = _("broadcast not on source memory operand");
5003 case broadcast_needed:
5004 err_msg = _("broadcast is needed for operand of such type");
5006 case unsupported_masking:
5007 err_msg = _("unsupported masking");
5009 case mask_not_on_destination:
5010 err_msg = _("mask not on destination operand");
5012 case no_default_mask:
5013 err_msg = _("default mask isn't allowed");
5015 case unsupported_rc_sae:
5016 err_msg = _("unsupported static rounding/sae");
5018 case rc_sae_operand_not_last_imm:
5020 err_msg = _("RC/SAE operand must precede immediate operands");
5022 err_msg = _("RC/SAE operand must follow immediate operands");
5024 case invalid_register_operand:
5025 err_msg = _("invalid register operand");
5028 as_bad (_("%s for `%s'"), err_msg,
5029 current_templates->start->name);
5033 if (!quiet_warnings)
5036 && (i.types[0].bitfield.jumpabsolute
5037 != operand_types[0].bitfield.jumpabsolute))
5039 as_warn (_("indirect %s without `*'"), t->name);
5042 if (t->opcode_modifier.isprefix
5043 && t->opcode_modifier.ignoresize)
5045 /* Warn them that a data or address size prefix doesn't
5046 affect assembly of the next line of code. */
5047 as_warn (_("stand-alone `%s' prefix"), t->name);
5051 /* Copy the template we found. */
5054 if (addr_prefix_disp != -1)
5055 i.tm.operand_types[addr_prefix_disp]
5056 = operand_types[addr_prefix_disp];
5058 if (found_reverse_match)
5060 /* If we found a reverse match we must alter the opcode
5061 direction bit. found_reverse_match holds bits to change
5062 (different for int & float insns). */
5064 i.tm.base_opcode ^= found_reverse_match;
5066 i.tm.operand_types[0] = operand_types[1];
5067 i.tm.operand_types[1] = operand_types[0];
5076 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5077 if (i.tm.operand_types[mem_op].bitfield.esseg)
5079 if (i.seg[0] != NULL && i.seg[0] != &es)
5081 as_bad (_("`%s' operand %d must use `%ses' segment"),
5087 /* There's only ever one segment override allowed per instruction.
5088 This instruction possibly has a legal segment override on the
5089 second operand, so copy the segment to where non-string
5090 instructions store it, allowing common code. */
5091 i.seg[0] = i.seg[1];
5093 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5095 if (i.seg[1] != NULL && i.seg[1] != &es)
5097 as_bad (_("`%s' operand %d must use `%ses' segment"),
5108 process_suffix (void)
5110 /* If matched instruction specifies an explicit instruction mnemonic
5112 if (i.tm.opcode_modifier.size16)
5113 i.suffix = WORD_MNEM_SUFFIX;
5114 else if (i.tm.opcode_modifier.size32)
5115 i.suffix = LONG_MNEM_SUFFIX;
5116 else if (i.tm.opcode_modifier.size64)
5117 i.suffix = QWORD_MNEM_SUFFIX;
5118 else if (i.reg_operands)
5120 /* If there's no instruction mnemonic suffix we try to invent one
5121 based on register operands. */
5124 /* We take i.suffix from the last register operand specified,
5125 Destination register type is more significant than source
5126 register type. crc32 in SSE4.2 prefers source register
5128 if (i.tm.base_opcode == 0xf20f38f1)
5130 if (i.types[0].bitfield.reg16)
5131 i.suffix = WORD_MNEM_SUFFIX;
5132 else if (i.types[0].bitfield.reg32)
5133 i.suffix = LONG_MNEM_SUFFIX;
5134 else if (i.types[0].bitfield.reg64)
5135 i.suffix = QWORD_MNEM_SUFFIX;
5137 else if (i.tm.base_opcode == 0xf20f38f0)
5139 if (i.types[0].bitfield.reg8)
5140 i.suffix = BYTE_MNEM_SUFFIX;
5147 if (i.tm.base_opcode == 0xf20f38f1
5148 || i.tm.base_opcode == 0xf20f38f0)
5150 /* We have to know the operand size for crc32. */
5151 as_bad (_("ambiguous memory operand size for `%s`"),
5156 for (op = i.operands; --op >= 0;)
5157 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5159 if (i.types[op].bitfield.reg8)
5161 i.suffix = BYTE_MNEM_SUFFIX;
5164 else if (i.types[op].bitfield.reg16)
5166 i.suffix = WORD_MNEM_SUFFIX;
5169 else if (i.types[op].bitfield.reg32)
5171 i.suffix = LONG_MNEM_SUFFIX;
5174 else if (i.types[op].bitfield.reg64)
5176 i.suffix = QWORD_MNEM_SUFFIX;
5182 else if (i.suffix == BYTE_MNEM_SUFFIX)
5185 && i.tm.opcode_modifier.ignoresize
5186 && i.tm.opcode_modifier.no_bsuf)
5188 else if (!check_byte_reg ())
5191 else if (i.suffix == LONG_MNEM_SUFFIX)
5194 && i.tm.opcode_modifier.ignoresize
5195 && i.tm.opcode_modifier.no_lsuf)
5197 else if (!check_long_reg ())
5200 else if (i.suffix == QWORD_MNEM_SUFFIX)
5203 && i.tm.opcode_modifier.ignoresize
5204 && i.tm.opcode_modifier.no_qsuf)
5206 else if (!check_qword_reg ())
5209 else if (i.suffix == WORD_MNEM_SUFFIX)
5212 && i.tm.opcode_modifier.ignoresize
5213 && i.tm.opcode_modifier.no_wsuf)
5215 else if (!check_word_reg ())
5218 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5219 || i.suffix == YMMWORD_MNEM_SUFFIX
5220 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5222 /* Skip if the instruction has x/y/z suffix. match_template
5223 should check if it is a valid suffix. */
5225 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5226 /* Do nothing if the instruction is going to ignore the prefix. */
5231 else if (i.tm.opcode_modifier.defaultsize
5233 /* exclude fldenv/frstor/fsave/fstenv */
5234 && i.tm.opcode_modifier.no_ssuf)
5236 i.suffix = stackop_size;
5238 else if (intel_syntax
5240 && (i.tm.operand_types[0].bitfield.jumpabsolute
5241 || i.tm.opcode_modifier.jumpbyte
5242 || i.tm.opcode_modifier.jumpintersegment
5243 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5244 && i.tm.extension_opcode <= 3)))
5249 if (!i.tm.opcode_modifier.no_qsuf)
5251 i.suffix = QWORD_MNEM_SUFFIX;
5255 if (!i.tm.opcode_modifier.no_lsuf)
5256 i.suffix = LONG_MNEM_SUFFIX;
5259 if (!i.tm.opcode_modifier.no_wsuf)
5260 i.suffix = WORD_MNEM_SUFFIX;
5269 if (i.tm.opcode_modifier.w)
5271 as_bad (_("no instruction mnemonic suffix given and "
5272 "no register operands; can't size instruction"));
5278 unsigned int suffixes;
5280 suffixes = !i.tm.opcode_modifier.no_bsuf;
5281 if (!i.tm.opcode_modifier.no_wsuf)
5283 if (!i.tm.opcode_modifier.no_lsuf)
5285 if (!i.tm.opcode_modifier.no_ldsuf)
5287 if (!i.tm.opcode_modifier.no_ssuf)
5289 if (!i.tm.opcode_modifier.no_qsuf)
5292 /* There are more than suffix matches. */
5293 if (i.tm.opcode_modifier.w
5294 || ((suffixes & (suffixes - 1))
5295 && !i.tm.opcode_modifier.defaultsize
5296 && !i.tm.opcode_modifier.ignoresize))
5298 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5304 /* Change the opcode based on the operand size given by i.suffix;
5305 We don't need to change things for byte insns. */
5308 && i.suffix != BYTE_MNEM_SUFFIX
5309 && i.suffix != XMMWORD_MNEM_SUFFIX
5310 && i.suffix != YMMWORD_MNEM_SUFFIX
5311 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5313 /* It's not a byte, select word/dword operation. */
5314 if (i.tm.opcode_modifier.w)
5316 if (i.tm.opcode_modifier.shortform)
5317 i.tm.base_opcode |= 8;
5319 i.tm.base_opcode |= 1;
5322 /* Now select between word & dword operations via the operand
5323 size prefix, except for instructions that will ignore this
5325 if (i.tm.opcode_modifier.addrprefixop0)
5327 /* The address size override prefix changes the size of the
5329 if ((flag_code == CODE_32BIT
5330 && i.op->regs[0].reg_type.bitfield.reg16)
5331 || (flag_code != CODE_32BIT
5332 && i.op->regs[0].reg_type.bitfield.reg32))
5333 if (!add_prefix (ADDR_PREFIX_OPCODE))
5336 else if (i.suffix != QWORD_MNEM_SUFFIX
5337 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5338 && !i.tm.opcode_modifier.ignoresize
5339 && !i.tm.opcode_modifier.floatmf
5340 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5341 || (flag_code == CODE_64BIT
5342 && i.tm.opcode_modifier.jumpbyte)))
5344 unsigned int prefix = DATA_PREFIX_OPCODE;
5346 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5347 prefix = ADDR_PREFIX_OPCODE;
5349 if (!add_prefix (prefix))
5353 /* Set mode64 for an operand. */
5354 if (i.suffix == QWORD_MNEM_SUFFIX
5355 && flag_code == CODE_64BIT
5356 && !i.tm.opcode_modifier.norex64)
5358 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5359 need rex64. cmpxchg8b is also a special case. */
5360 if (! (i.operands == 2
5361 && i.tm.base_opcode == 0x90
5362 && i.tm.extension_opcode == None
5363 && operand_type_equal (&i.types [0], &acc64)
5364 && operand_type_equal (&i.types [1], &acc64))
5365 && ! (i.operands == 1
5366 && i.tm.base_opcode == 0xfc7
5367 && i.tm.extension_opcode == 1
5368 && !operand_type_check (i.types [0], reg)
5369 && operand_type_check (i.types [0], anymem)))
5373 /* Size floating point instruction. */
5374 if (i.suffix == LONG_MNEM_SUFFIX)
5375 if (i.tm.opcode_modifier.floatmf)
5376 i.tm.base_opcode ^= 4;
5383 check_byte_reg (void)
5387 for (op = i.operands; --op >= 0;)
5389 /* If this is an eight bit register, it's OK. If it's the 16 or
5390 32 bit version of an eight bit register, we will just use the
5391 low portion, and that's OK too. */
5392 if (i.types[op].bitfield.reg8)
5395 /* I/O port address operands are OK too. */
5396 if (i.tm.operand_types[op].bitfield.inoutportreg)
5399 /* crc32 doesn't generate this warning. */
5400 if (i.tm.base_opcode == 0xf20f38f0)
5403 if ((i.types[op].bitfield.reg16
5404 || i.types[op].bitfield.reg32
5405 || i.types[op].bitfield.reg64)
5406 && i.op[op].regs->reg_num < 4
5407 /* Prohibit these changes in 64bit mode, since the lowering
5408 would be more complicated. */
5409 && flag_code != CODE_64BIT)
5411 #if REGISTER_WARNINGS
5412 if (!quiet_warnings)
5413 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5415 (i.op[op].regs + (i.types[op].bitfield.reg16
5416 ? REGNAM_AL - REGNAM_AX
5417 : REGNAM_AL - REGNAM_EAX))->reg_name,
5419 i.op[op].regs->reg_name,
5424 /* Any other register is bad. */
5425 if (i.types[op].bitfield.reg16
5426 || i.types[op].bitfield.reg32
5427 || i.types[op].bitfield.reg64
5428 || i.types[op].bitfield.regmmx
5429 || i.types[op].bitfield.regxmm
5430 || i.types[op].bitfield.regymm
5431 || i.types[op].bitfield.regzmm
5432 || i.types[op].bitfield.sreg2
5433 || i.types[op].bitfield.sreg3
5434 || i.types[op].bitfield.control
5435 || i.types[op].bitfield.debug
5436 || i.types[op].bitfield.test
5437 || i.types[op].bitfield.floatreg
5438 || i.types[op].bitfield.floatacc)
5440 as_bad (_("`%s%s' not allowed with `%s%c'"),
5442 i.op[op].regs->reg_name,
5452 check_long_reg (void)
5456 for (op = i.operands; --op >= 0;)
5457 /* Reject eight bit registers, except where the template requires
5458 them. (eg. movzb) */
5459 if (i.types[op].bitfield.reg8
5460 && (i.tm.operand_types[op].bitfield.reg16
5461 || i.tm.operand_types[op].bitfield.reg32
5462 || i.tm.operand_types[op].bitfield.acc))
5464 as_bad (_("`%s%s' not allowed with `%s%c'"),
5466 i.op[op].regs->reg_name,
5471 /* Warn if the e prefix on a general reg is missing. */
5472 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5473 && i.types[op].bitfield.reg16
5474 && (i.tm.operand_types[op].bitfield.reg32
5475 || i.tm.operand_types[op].bitfield.acc))
5477 /* Prohibit these changes in the 64bit mode, since the
5478 lowering is more complicated. */
5479 if (flag_code == CODE_64BIT)
5481 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5482 register_prefix, i.op[op].regs->reg_name,
5486 #if REGISTER_WARNINGS
5487 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5489 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5490 register_prefix, i.op[op].regs->reg_name, i.suffix);
5493 /* Warn if the r prefix on a general reg is present. */
5494 else if (i.types[op].bitfield.reg64
5495 && (i.tm.operand_types[op].bitfield.reg32
5496 || i.tm.operand_types[op].bitfield.acc))
5499 && i.tm.opcode_modifier.toqword
5500 && !i.types[0].bitfield.regxmm)
5502 /* Convert to QWORD. We want REX byte. */
5503 i.suffix = QWORD_MNEM_SUFFIX;
5507 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5508 register_prefix, i.op[op].regs->reg_name,
5517 check_qword_reg (void)
5521 for (op = i.operands; --op >= 0; )
5522 /* Reject eight bit registers, except where the template requires
5523 them. (eg. movzb) */
5524 if (i.types[op].bitfield.reg8
5525 && (i.tm.operand_types[op].bitfield.reg16
5526 || i.tm.operand_types[op].bitfield.reg32
5527 || i.tm.operand_types[op].bitfield.acc))
5529 as_bad (_("`%s%s' not allowed with `%s%c'"),
5531 i.op[op].regs->reg_name,
5536 /* Warn if the r prefix on a general reg is missing. */
5537 else if ((i.types[op].bitfield.reg16
5538 || i.types[op].bitfield.reg32)
5539 && (i.tm.operand_types[op].bitfield.reg32
5540 || i.tm.operand_types[op].bitfield.acc))
5542 /* Prohibit these changes in the 64bit mode, since the
5543 lowering is more complicated. */
5545 && i.tm.opcode_modifier.todword
5546 && !i.types[0].bitfield.regxmm)
5548 /* Convert to DWORD. We don't want REX byte. */
5549 i.suffix = LONG_MNEM_SUFFIX;
5553 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5554 register_prefix, i.op[op].regs->reg_name,
5563 check_word_reg (void)
5566 for (op = i.operands; --op >= 0;)
5567 /* Reject eight bit registers, except where the template requires
5568 them. (eg. movzb) */
5569 if (i.types[op].bitfield.reg8
5570 && (i.tm.operand_types[op].bitfield.reg16
5571 || i.tm.operand_types[op].bitfield.reg32
5572 || i.tm.operand_types[op].bitfield.acc))
5574 as_bad (_("`%s%s' not allowed with `%s%c'"),
5576 i.op[op].regs->reg_name,
5581 /* Warn if the e or r prefix on a general reg is present. */
5582 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5583 && (i.types[op].bitfield.reg32
5584 || i.types[op].bitfield.reg64)
5585 && (i.tm.operand_types[op].bitfield.reg16
5586 || i.tm.operand_types[op].bitfield.acc))
5588 /* Prohibit these changes in the 64bit mode, since the
5589 lowering is more complicated. */
5590 if (flag_code == CODE_64BIT)
5592 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5593 register_prefix, i.op[op].regs->reg_name,
5597 #if REGISTER_WARNINGS
5598 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5600 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5601 register_prefix, i.op[op].regs->reg_name, i.suffix);
5608 update_imm (unsigned int j)
5610 i386_operand_type overlap = i.types[j];
5611 if ((overlap.bitfield.imm8
5612 || overlap.bitfield.imm8s
5613 || overlap.bitfield.imm16
5614 || overlap.bitfield.imm32
5615 || overlap.bitfield.imm32s
5616 || overlap.bitfield.imm64)
5617 && !operand_type_equal (&overlap, &imm8)
5618 && !operand_type_equal (&overlap, &imm8s)
5619 && !operand_type_equal (&overlap, &imm16)
5620 && !operand_type_equal (&overlap, &imm32)
5621 && !operand_type_equal (&overlap, &imm32s)
5622 && !operand_type_equal (&overlap, &imm64))
5626 i386_operand_type temp;
5628 operand_type_set (&temp, 0);
5629 if (i.suffix == BYTE_MNEM_SUFFIX)
5631 temp.bitfield.imm8 = overlap.bitfield.imm8;
5632 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5634 else if (i.suffix == WORD_MNEM_SUFFIX)
5635 temp.bitfield.imm16 = overlap.bitfield.imm16;
5636 else if (i.suffix == QWORD_MNEM_SUFFIX)
5638 temp.bitfield.imm64 = overlap.bitfield.imm64;
5639 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5642 temp.bitfield.imm32 = overlap.bitfield.imm32;
5645 else if (operand_type_equal (&overlap, &imm16_32_32s)
5646 || operand_type_equal (&overlap, &imm16_32)
5647 || operand_type_equal (&overlap, &imm16_32s))
5649 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5654 if (!operand_type_equal (&overlap, &imm8)
5655 && !operand_type_equal (&overlap, &imm8s)
5656 && !operand_type_equal (&overlap, &imm16)
5657 && !operand_type_equal (&overlap, &imm32)
5658 && !operand_type_equal (&overlap, &imm32s)
5659 && !operand_type_equal (&overlap, &imm64))
5661 as_bad (_("no instruction mnemonic suffix given; "
5662 "can't determine immediate size"));
5666 i.types[j] = overlap;
5676 /* Update the first 2 immediate operands. */
5677 n = i.operands > 2 ? 2 : i.operands;
5680 for (j = 0; j < n; j++)
5681 if (update_imm (j) == 0)
5684 /* The 3rd operand can't be immediate operand. */
5685 gas_assert (operand_type_check (i.types[2], imm) == 0);
5692 bad_implicit_operand (int xmm)
5694 const char *ireg = xmm ? "xmm0" : "ymm0";
5697 as_bad (_("the last operand of `%s' must be `%s%s'"),
5698 i.tm.name, register_prefix, ireg);
5700 as_bad (_("the first operand of `%s' must be `%s%s'"),
5701 i.tm.name, register_prefix, ireg);
5706 process_operands (void)
5708 /* Default segment register this instruction will use for memory
5709 accesses. 0 means unknown. This is only for optimizing out
5710 unnecessary segment overrides. */
5711 const seg_entry *default_seg = 0;
5713 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5715 unsigned int dupl = i.operands;
5716 unsigned int dest = dupl - 1;
5719 /* The destination must be an xmm register. */
5720 gas_assert (i.reg_operands
5721 && MAX_OPERANDS > dupl
5722 && operand_type_equal (&i.types[dest], ®xmm));
5724 if (i.tm.opcode_modifier.firstxmm0)
5726 /* The first operand is implicit and must be xmm0. */
5727 gas_assert (operand_type_equal (&i.types[0], ®xmm));
5728 if (register_number (i.op[0].regs) != 0)
5729 return bad_implicit_operand (1);
5731 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5733 /* Keep xmm0 for instructions with VEX prefix and 3
5739 /* We remove the first xmm0 and keep the number of
5740 operands unchanged, which in fact duplicates the
5742 for (j = 1; j < i.operands; j++)
5744 i.op[j - 1] = i.op[j];
5745 i.types[j - 1] = i.types[j];
5746 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5750 else if (i.tm.opcode_modifier.implicit1stxmm0)
5752 gas_assert ((MAX_OPERANDS - 1) > dupl
5753 && (i.tm.opcode_modifier.vexsources
5756 /* Add the implicit xmm0 for instructions with VEX prefix
5758 for (j = i.operands; j > 0; j--)
5760 i.op[j] = i.op[j - 1];
5761 i.types[j] = i.types[j - 1];
5762 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5765 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5766 i.types[0] = regxmm;
5767 i.tm.operand_types[0] = regxmm;
5770 i.reg_operands += 2;
5775 i.op[dupl] = i.op[dest];
5776 i.types[dupl] = i.types[dest];
5777 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5786 i.op[dupl] = i.op[dest];
5787 i.types[dupl] = i.types[dest];
5788 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5791 if (i.tm.opcode_modifier.immext)
5794 else if (i.tm.opcode_modifier.firstxmm0)
5798 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5799 gas_assert (i.reg_operands
5800 && (operand_type_equal (&i.types[0], ®xmm)
5801 || operand_type_equal (&i.types[0], ®ymm)
5802 || operand_type_equal (&i.types[0], ®zmm)));
5803 if (register_number (i.op[0].regs) != 0)
5804 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5806 for (j = 1; j < i.operands; j++)
5808 i.op[j - 1] = i.op[j];
5809 i.types[j - 1] = i.types[j];
5811 /* We need to adjust fields in i.tm since they are used by
5812 build_modrm_byte. */
5813 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5820 else if (i.tm.opcode_modifier.regkludge)
5822 /* The imul $imm, %reg instruction is converted into
5823 imul $imm, %reg, %reg, and the clr %reg instruction
5824 is converted into xor %reg, %reg. */
5826 unsigned int first_reg_op;
5828 if (operand_type_check (i.types[0], reg))
5832 /* Pretend we saw the extra register operand. */
5833 gas_assert (i.reg_operands == 1
5834 && i.op[first_reg_op + 1].regs == 0);
5835 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5836 i.types[first_reg_op + 1] = i.types[first_reg_op];
5841 if (i.tm.opcode_modifier.shortform)
5843 if (i.types[0].bitfield.sreg2
5844 || i.types[0].bitfield.sreg3)
5846 if (i.tm.base_opcode == POP_SEG_SHORT
5847 && i.op[0].regs->reg_num == 1)
5849 as_bad (_("you can't `pop %scs'"), register_prefix);
5852 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5853 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5858 /* The register or float register operand is in operand
5862 if (i.types[0].bitfield.floatreg
5863 || operand_type_check (i.types[0], reg))
5867 /* Register goes in low 3 bits of opcode. */
5868 i.tm.base_opcode |= i.op[op].regs->reg_num;
5869 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5871 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5873 /* Warn about some common errors, but press on regardless.
5874 The first case can be generated by gcc (<= 2.8.1). */
5875 if (i.operands == 2)
5877 /* Reversed arguments on faddp, fsubp, etc. */
5878 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5879 register_prefix, i.op[!intel_syntax].regs->reg_name,
5880 register_prefix, i.op[intel_syntax].regs->reg_name);
5884 /* Extraneous `l' suffix on fp insn. */
5885 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5886 register_prefix, i.op[0].regs->reg_name);
5891 else if (i.tm.opcode_modifier.modrm)
5893 /* The opcode is completed (modulo i.tm.extension_opcode which
5894 must be put into the modrm byte). Now, we make the modrm and
5895 index base bytes based on all the info we've collected. */
5897 default_seg = build_modrm_byte ();
5899 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5903 else if (i.tm.opcode_modifier.isstring)
5905 /* For the string instructions that allow a segment override
5906 on one of their operands, the default segment is ds. */
5910 if (i.tm.base_opcode == 0x8d /* lea */
5913 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5915 /* If a segment was explicitly specified, and the specified segment
5916 is not the default, use an opcode prefix to select it. If we
5917 never figured out what the default segment is, then default_seg
5918 will be zero at this point, and the specified segment prefix will
5920 if ((i.seg[0]) && (i.seg[0] != default_seg))
5922 if (!add_prefix (i.seg[0]->seg_prefix))
5928 static const seg_entry *
5929 build_modrm_byte (void)
5931 const seg_entry *default_seg = 0;
5932 unsigned int source, dest;
5935 /* The first operand of instructions with VEX prefix and 3 sources
5936 must be VEX_Imm4. */
5937 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5940 unsigned int nds, reg_slot;
5943 if (i.tm.opcode_modifier.veximmext
5944 && i.tm.opcode_modifier.immext)
5946 dest = i.operands - 2;
5947 gas_assert (dest == 3);
5950 dest = i.operands - 1;
5953 /* There are 2 kinds of instructions:
5954 1. 5 operands: 4 register operands or 3 register operands
5955 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5956 VexW0 or VexW1. The destination must be either XMM, YMM or
5958 2. 4 operands: 4 register operands or 3 register operands
5959 plus 1 memory operand, VexXDS, and VexImmExt */
5960 gas_assert ((i.reg_operands == 4
5961 || (i.reg_operands == 3 && i.mem_operands == 1))
5962 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5963 && (i.tm.opcode_modifier.veximmext
5964 || (i.imm_operands == 1
5965 && i.types[0].bitfield.vec_imm4
5966 && (i.tm.opcode_modifier.vexw == VEXW0
5967 || i.tm.opcode_modifier.vexw == VEXW1)
5968 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5969 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)
5970 || operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
5972 if (i.imm_operands == 0)
5974 /* When there is no immediate operand, generate an 8bit
5975 immediate operand to encode the first operand. */
5976 exp = &im_expressions[i.imm_operands++];
5977 i.op[i.operands].imms = exp;
5978 i.types[i.operands] = imm8;
5980 /* If VexW1 is set, the first operand is the source and
5981 the second operand is encoded in the immediate operand. */
5982 if (i.tm.opcode_modifier.vexw == VEXW1)
5993 /* FMA swaps REG and NDS. */
5994 if (i.tm.cpu_flags.bitfield.cpufma)
6002 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6004 || operand_type_equal (&i.tm.operand_types[reg_slot],
6006 || operand_type_equal (&i.tm.operand_types[reg_slot],
6008 exp->X_op = O_constant;
6009 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6010 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6014 unsigned int imm_slot;
6016 if (i.tm.opcode_modifier.vexw == VEXW0)
6018 /* If VexW0 is set, the third operand is the source and
6019 the second operand is encoded in the immediate
6026 /* VexW1 is set, the second operand is the source and
6027 the third operand is encoded in the immediate
6033 if (i.tm.opcode_modifier.immext)
6035 /* When ImmExt is set, the immdiate byte is the last
6037 imm_slot = i.operands - 1;
6045 /* Turn on Imm8 so that output_imm will generate it. */
6046 i.types[imm_slot].bitfield.imm8 = 1;
6049 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6051 || operand_type_equal (&i.tm.operand_types[reg_slot],
6053 || operand_type_equal (&i.tm.operand_types[reg_slot],
6055 i.op[imm_slot].imms->X_add_number
6056 |= register_number (i.op[reg_slot].regs) << 4;
6057 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6060 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
6061 || operand_type_equal (&i.tm.operand_types[nds],
6063 || operand_type_equal (&i.tm.operand_types[nds],
6065 i.vex.register_specifier = i.op[nds].regs;
6070 /* i.reg_operands MUST be the number of real register operands;
6071 implicit registers do not count. If there are 3 register
6072 operands, it must be a instruction with VexNDS. For a
6073 instruction with VexNDD, the destination register is encoded
6074 in VEX prefix. If there are 4 register operands, it must be
6075 a instruction with VEX prefix and 3 sources. */
6076 if (i.mem_operands == 0
6077 && ((i.reg_operands == 2
6078 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6079 || (i.reg_operands == 3
6080 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6081 || (i.reg_operands == 4 && vex_3_sources)))
6089 /* When there are 3 operands, one of them may be immediate,
6090 which may be the first or the last operand. Otherwise,
6091 the first operand must be shift count register (cl) or it
6092 is an instruction with VexNDS. */
6093 gas_assert (i.imm_operands == 1
6094 || (i.imm_operands == 0
6095 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6096 || i.types[0].bitfield.shiftcount)));
6097 if (operand_type_check (i.types[0], imm)
6098 || i.types[0].bitfield.shiftcount)
6104 /* When there are 4 operands, the first two must be 8bit
6105 immediate operands. The source operand will be the 3rd
6108 For instructions with VexNDS, if the first operand
6109 an imm8, the source operand is the 2nd one. If the last
6110 operand is imm8, the source operand is the first one. */
6111 gas_assert ((i.imm_operands == 2
6112 && i.types[0].bitfield.imm8
6113 && i.types[1].bitfield.imm8)
6114 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6115 && i.imm_operands == 1
6116 && (i.types[0].bitfield.imm8
6117 || i.types[i.operands - 1].bitfield.imm8
6119 if (i.imm_operands == 2)
6123 if (i.types[0].bitfield.imm8)
6130 if (i.tm.opcode_modifier.evex)
6132 /* For EVEX instructions, when there are 5 operands, the
6133 first one must be immediate operand. If the second one
6134 is immediate operand, the source operand is the 3th
6135 one. If the last one is immediate operand, the source
6136 operand is the 2nd one. */
6137 gas_assert (i.imm_operands == 2
6138 && i.tm.opcode_modifier.sae
6139 && operand_type_check (i.types[0], imm));
6140 if (operand_type_check (i.types[1], imm))
6142 else if (operand_type_check (i.types[4], imm))
6156 /* RC/SAE operand could be between DEST and SRC. That happens
6157 when one operand is GPR and the other one is XMM/YMM/ZMM
6159 if (i.rounding && i.rounding->operand == (int) dest)
6162 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6164 /* For instructions with VexNDS, the register-only source
6165 operand must be 32/64bit integer, XMM, YMM or ZMM
6166 register. It is encoded in VEX prefix. We need to
6167 clear RegMem bit before calling operand_type_equal. */
6169 i386_operand_type op;
6172 /* Check register-only source operand when two source
6173 operands are swapped. */
6174 if (!i.tm.operand_types[source].bitfield.baseindex
6175 && i.tm.operand_types[dest].bitfield.baseindex)
6183 op = i.tm.operand_types[vvvv];
6184 op.bitfield.regmem = 0;
6185 if ((dest + 1) >= i.operands
6186 || (!op.bitfield.reg32
6187 && op.bitfield.reg64
6188 && !operand_type_equal (&op, ®xmm)
6189 && !operand_type_equal (&op, ®ymm)
6190 && !operand_type_equal (&op, ®zmm)
6191 && !operand_type_equal (&op, ®mask)))
6193 i.vex.register_specifier = i.op[vvvv].regs;
6199 /* One of the register operands will be encoded in the i.tm.reg
6200 field, the other in the combined i.tm.mode and i.tm.regmem
6201 fields. If no form of this instruction supports a memory
6202 destination operand, then we assume the source operand may
6203 sometimes be a memory operand and so we need to store the
6204 destination in the i.rm.reg field. */
6205 if (!i.tm.operand_types[dest].bitfield.regmem
6206 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6208 i.rm.reg = i.op[dest].regs->reg_num;
6209 i.rm.regmem = i.op[source].regs->reg_num;
6210 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6212 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6214 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6216 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6221 i.rm.reg = i.op[source].regs->reg_num;
6222 i.rm.regmem = i.op[dest].regs->reg_num;
6223 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6225 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6227 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6229 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6232 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6234 if (!i.types[0].bitfield.control
6235 && !i.types[1].bitfield.control)
6237 i.rex &= ~(REX_R | REX_B);
6238 add_prefix (LOCK_PREFIX_OPCODE);
6242 { /* If it's not 2 reg operands... */
6247 unsigned int fake_zero_displacement = 0;
6250 for (op = 0; op < i.operands; op++)
6251 if (operand_type_check (i.types[op], anymem))
6253 gas_assert (op < i.operands);
6255 if (i.tm.opcode_modifier.vecsib)
6257 if (i.index_reg->reg_num == RegEiz
6258 || i.index_reg->reg_num == RegRiz)
6261 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6264 i.sib.base = NO_BASE_REGISTER;
6265 i.sib.scale = i.log2_scale_factor;
6266 /* No Vec_Disp8 if there is no base. */
6267 i.types[op].bitfield.vec_disp8 = 0;
6268 i.types[op].bitfield.disp8 = 0;
6269 i.types[op].bitfield.disp16 = 0;
6270 i.types[op].bitfield.disp64 = 0;
6271 if (flag_code != CODE_64BIT)
6273 /* Must be 32 bit */
6274 i.types[op].bitfield.disp32 = 1;
6275 i.types[op].bitfield.disp32s = 0;
6279 i.types[op].bitfield.disp32 = 0;
6280 i.types[op].bitfield.disp32s = 1;
6283 i.sib.index = i.index_reg->reg_num;
6284 if ((i.index_reg->reg_flags & RegRex) != 0)
6286 if ((i.index_reg->reg_flags & RegVRex) != 0)
6292 if (i.base_reg == 0)
6295 if (!i.disp_operands)
6297 fake_zero_displacement = 1;
6298 /* Instructions with VSIB byte need 32bit displacement
6299 if there is no base register. */
6300 if (i.tm.opcode_modifier.vecsib)
6301 i.types[op].bitfield.disp32 = 1;
6303 if (i.index_reg == 0)
6305 gas_assert (!i.tm.opcode_modifier.vecsib);
6306 /* Operand is just <disp> */
6307 if (flag_code == CODE_64BIT)
6309 /* 64bit mode overwrites the 32bit absolute
6310 addressing by RIP relative addressing and
6311 absolute addressing is encoded by one of the
6312 redundant SIB forms. */
6313 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6314 i.sib.base = NO_BASE_REGISTER;
6315 i.sib.index = NO_INDEX_REGISTER;
6316 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6317 ? disp32s : disp32);
6319 else if ((flag_code == CODE_16BIT)
6320 ^ (i.prefix[ADDR_PREFIX] != 0))
6322 i.rm.regmem = NO_BASE_REGISTER_16;
6323 i.types[op] = disp16;
6327 i.rm.regmem = NO_BASE_REGISTER;
6328 i.types[op] = disp32;
6331 else if (!i.tm.opcode_modifier.vecsib)
6333 /* !i.base_reg && i.index_reg */
6334 if (i.index_reg->reg_num == RegEiz
6335 || i.index_reg->reg_num == RegRiz)
6336 i.sib.index = NO_INDEX_REGISTER;
6338 i.sib.index = i.index_reg->reg_num;
6339 i.sib.base = NO_BASE_REGISTER;
6340 i.sib.scale = i.log2_scale_factor;
6341 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6342 /* No Vec_Disp8 if there is no base. */
6343 i.types[op].bitfield.vec_disp8 = 0;
6344 i.types[op].bitfield.disp8 = 0;
6345 i.types[op].bitfield.disp16 = 0;
6346 i.types[op].bitfield.disp64 = 0;
6347 if (flag_code != CODE_64BIT)
6349 /* Must be 32 bit */
6350 i.types[op].bitfield.disp32 = 1;
6351 i.types[op].bitfield.disp32s = 0;
6355 i.types[op].bitfield.disp32 = 0;
6356 i.types[op].bitfield.disp32s = 1;
6358 if ((i.index_reg->reg_flags & RegRex) != 0)
6362 /* RIP addressing for 64bit mode. */
6363 else if (i.base_reg->reg_num == RegRip ||
6364 i.base_reg->reg_num == RegEip)
6366 gas_assert (!i.tm.opcode_modifier.vecsib);
6367 i.rm.regmem = NO_BASE_REGISTER;
6368 i.types[op].bitfield.disp8 = 0;
6369 i.types[op].bitfield.disp16 = 0;
6370 i.types[op].bitfield.disp32 = 0;
6371 i.types[op].bitfield.disp32s = 1;
6372 i.types[op].bitfield.disp64 = 0;
6373 i.types[op].bitfield.vec_disp8 = 0;
6374 i.flags[op] |= Operand_PCrel;
6375 if (! i.disp_operands)
6376 fake_zero_displacement = 1;
6378 else if (i.base_reg->reg_type.bitfield.reg16)
6380 gas_assert (!i.tm.opcode_modifier.vecsib);
6381 switch (i.base_reg->reg_num)
6384 if (i.index_reg == 0)
6386 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6387 i.rm.regmem = i.index_reg->reg_num - 6;
6391 if (i.index_reg == 0)
6394 if (operand_type_check (i.types[op], disp) == 0)
6396 /* fake (%bp) into 0(%bp) */
6397 if (i.tm.operand_types[op].bitfield.vec_disp8)
6398 i.types[op].bitfield.vec_disp8 = 1;
6400 i.types[op].bitfield.disp8 = 1;
6401 fake_zero_displacement = 1;
6404 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6405 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6407 default: /* (%si) -> 4 or (%di) -> 5 */
6408 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6410 i.rm.mode = mode_from_disp_size (i.types[op]);
6412 else /* i.base_reg and 32/64 bit mode */
6414 if (flag_code == CODE_64BIT
6415 && operand_type_check (i.types[op], disp))
6417 i386_operand_type temp;
6418 operand_type_set (&temp, 0);
6419 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6420 temp.bitfield.vec_disp8
6421 = i.types[op].bitfield.vec_disp8;
6423 if (i.prefix[ADDR_PREFIX] == 0)
6424 i.types[op].bitfield.disp32s = 1;
6426 i.types[op].bitfield.disp32 = 1;
6429 if (!i.tm.opcode_modifier.vecsib)
6430 i.rm.regmem = i.base_reg->reg_num;
6431 if ((i.base_reg->reg_flags & RegRex) != 0)
6433 i.sib.base = i.base_reg->reg_num;
6434 /* x86-64 ignores REX prefix bit here to avoid decoder
6436 if (!(i.base_reg->reg_flags & RegRex)
6437 && (i.base_reg->reg_num == EBP_REG_NUM
6438 || i.base_reg->reg_num == ESP_REG_NUM))
6440 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6442 fake_zero_displacement = 1;
6443 if (i.tm.operand_types [op].bitfield.vec_disp8)
6444 i.types[op].bitfield.vec_disp8 = 1;
6446 i.types[op].bitfield.disp8 = 1;
6448 i.sib.scale = i.log2_scale_factor;
6449 if (i.index_reg == 0)
6451 gas_assert (!i.tm.opcode_modifier.vecsib);
6452 /* <disp>(%esp) becomes two byte modrm with no index
6453 register. We've already stored the code for esp
6454 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6455 Any base register besides %esp will not use the
6456 extra modrm byte. */
6457 i.sib.index = NO_INDEX_REGISTER;
6459 else if (!i.tm.opcode_modifier.vecsib)
6461 if (i.index_reg->reg_num == RegEiz
6462 || i.index_reg->reg_num == RegRiz)
6463 i.sib.index = NO_INDEX_REGISTER;
6465 i.sib.index = i.index_reg->reg_num;
6466 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6467 if ((i.index_reg->reg_flags & RegRex) != 0)
6472 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6473 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6477 if (!fake_zero_displacement
6481 fake_zero_displacement = 1;
6482 if (i.disp_encoding == disp_encoding_8bit)
6483 i.types[op].bitfield.disp8 = 1;
6485 i.types[op].bitfield.disp32 = 1;
6487 i.rm.mode = mode_from_disp_size (i.types[op]);
6491 if (fake_zero_displacement)
6493 /* Fakes a zero displacement assuming that i.types[op]
6494 holds the correct displacement size. */
6497 gas_assert (i.op[op].disps == 0);
6498 exp = &disp_expressions[i.disp_operands++];
6499 i.op[op].disps = exp;
6500 exp->X_op = O_constant;
6501 exp->X_add_number = 0;
6502 exp->X_add_symbol = (symbolS *) 0;
6503 exp->X_op_symbol = (symbolS *) 0;
6511 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6513 if (operand_type_check (i.types[0], imm))
6514 i.vex.register_specifier = NULL;
6517 /* VEX.vvvv encodes one of the sources when the first
6518 operand is not an immediate. */
6519 if (i.tm.opcode_modifier.vexw == VEXW0)
6520 i.vex.register_specifier = i.op[0].regs;
6522 i.vex.register_specifier = i.op[1].regs;
6525 /* Destination is a XMM register encoded in the ModRM.reg
6527 i.rm.reg = i.op[2].regs->reg_num;
6528 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6531 /* ModRM.rm and VEX.B encodes the other source. */
6532 if (!i.mem_operands)
6536 if (i.tm.opcode_modifier.vexw == VEXW0)
6537 i.rm.regmem = i.op[1].regs->reg_num;
6539 i.rm.regmem = i.op[0].regs->reg_num;
6541 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6545 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6547 i.vex.register_specifier = i.op[2].regs;
6548 if (!i.mem_operands)
6551 i.rm.regmem = i.op[1].regs->reg_num;
6552 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6556 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6557 (if any) based on i.tm.extension_opcode. Again, we must be
6558 careful to make sure that segment/control/debug/test/MMX
6559 registers are coded into the i.rm.reg field. */
6560 else if (i.reg_operands)
6563 unsigned int vex_reg = ~0;
6565 for (op = 0; op < i.operands; op++)
6566 if (i.types[op].bitfield.reg8
6567 || i.types[op].bitfield.reg16
6568 || i.types[op].bitfield.reg32
6569 || i.types[op].bitfield.reg64
6570 || i.types[op].bitfield.regmmx
6571 || i.types[op].bitfield.regxmm
6572 || i.types[op].bitfield.regymm
6573 || i.types[op].bitfield.regbnd
6574 || i.types[op].bitfield.regzmm
6575 || i.types[op].bitfield.regmask
6576 || i.types[op].bitfield.sreg2
6577 || i.types[op].bitfield.sreg3
6578 || i.types[op].bitfield.control
6579 || i.types[op].bitfield.debug
6580 || i.types[op].bitfield.test)
6585 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6587 /* For instructions with VexNDS, the register-only
6588 source operand is encoded in VEX prefix. */
6589 gas_assert (mem != (unsigned int) ~0);
6594 gas_assert (op < i.operands);
6598 /* Check register-only source operand when two source
6599 operands are swapped. */
6600 if (!i.tm.operand_types[op].bitfield.baseindex
6601 && i.tm.operand_types[op + 1].bitfield.baseindex)
6605 gas_assert (mem == (vex_reg + 1)
6606 && op < i.operands);
6611 gas_assert (vex_reg < i.operands);
6615 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6617 /* For instructions with VexNDD, the register destination
6618 is encoded in VEX prefix. */
6619 if (i.mem_operands == 0)
6621 /* There is no memory operand. */
6622 gas_assert ((op + 2) == i.operands);
6627 /* There are only 2 operands. */
6628 gas_assert (op < 2 && i.operands == 2);
6633 gas_assert (op < i.operands);
6635 if (vex_reg != (unsigned int) ~0)
6637 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6639 if (type->bitfield.reg32 != 1
6640 && type->bitfield.reg64 != 1
6641 && !operand_type_equal (type, ®xmm)
6642 && !operand_type_equal (type, ®ymm)
6643 && !operand_type_equal (type, ®zmm)
6644 && !operand_type_equal (type, ®mask))
6647 i.vex.register_specifier = i.op[vex_reg].regs;
6650 /* Don't set OP operand twice. */
6653 /* If there is an extension opcode to put here, the
6654 register number must be put into the regmem field. */
6655 if (i.tm.extension_opcode != None)
6657 i.rm.regmem = i.op[op].regs->reg_num;
6658 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6660 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6665 i.rm.reg = i.op[op].regs->reg_num;
6666 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6668 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6673 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6674 must set it to 3 to indicate this is a register operand
6675 in the regmem field. */
6676 if (!i.mem_operands)
6680 /* Fill in i.rm.reg field with extension opcode (if any). */
6681 if (i.tm.extension_opcode != None)
6682 i.rm.reg = i.tm.extension_opcode;
6688 output_branch (void)
6694 relax_substateT subtype;
6698 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6699 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6702 if (i.prefix[DATA_PREFIX] != 0)
6708 /* Pentium4 branch hints. */
6709 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6710 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6715 if (i.prefix[REX_PREFIX] != 0)
6721 /* BND prefixed jump. */
6722 if (i.prefix[BND_PREFIX] != 0)
6724 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6728 if (i.prefixes != 0 && !intel_syntax)
6729 as_warn (_("skipping prefixes on this instruction"));
6731 /* It's always a symbol; End frag & setup for relax.
6732 Make sure there is enough room in this frag for the largest
6733 instruction we may generate in md_convert_frag. This is 2
6734 bytes for the opcode and room for the prefix and largest
6736 frag_grow (prefix + 2 + 4);
6737 /* Prefix and 1 opcode byte go in fr_fix. */
6738 p = frag_more (prefix + 1);
6739 if (i.prefix[DATA_PREFIX] != 0)
6740 *p++ = DATA_PREFIX_OPCODE;
6741 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6742 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6743 *p++ = i.prefix[SEG_PREFIX];
6744 if (i.prefix[REX_PREFIX] != 0)
6745 *p++ = i.prefix[REX_PREFIX];
6746 *p = i.tm.base_opcode;
6748 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6749 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6750 else if (cpu_arch_flags.bitfield.cpui386)
6751 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6753 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6756 sym = i.op[0].disps->X_add_symbol;
6757 off = i.op[0].disps->X_add_number;
6759 if (i.op[0].disps->X_op != O_constant
6760 && i.op[0].disps->X_op != O_symbol)
6762 /* Handle complex expressions. */
6763 sym = make_expr_symbol (i.op[0].disps);
6767 /* 1 possible extra opcode + 4 byte displacement go in var part.
6768 Pass reloc in fr_var. */
6769 frag_var (rs_machine_dependent, 5,
6771 || i.reloc[0] != NO_RELOC
6772 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6774 : BFD_RELOC_X86_64_PC32_BND),
6775 subtype, sym, off, p);
6785 if (i.tm.opcode_modifier.jumpbyte)
6787 /* This is a loop or jecxz type instruction. */
6789 if (i.prefix[ADDR_PREFIX] != 0)
6791 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6794 /* Pentium4 branch hints. */
6795 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6796 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6798 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6807 if (flag_code == CODE_16BIT)
6810 if (i.prefix[DATA_PREFIX] != 0)
6812 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6822 if (i.prefix[REX_PREFIX] != 0)
6824 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6828 /* BND prefixed jump. */
6829 if (i.prefix[BND_PREFIX] != 0)
6831 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6835 if (i.prefixes != 0 && !intel_syntax)
6836 as_warn (_("skipping prefixes on this instruction"));
6838 p = frag_more (i.tm.opcode_length + size);
6839 switch (i.tm.opcode_length)
6842 *p++ = i.tm.base_opcode >> 8;
6844 *p++ = i.tm.base_opcode;
6850 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6851 i.op[0].disps, 1, reloc (size, 1, 1,
6852 (i.bnd_prefix != NULL
6856 /* All jumps handled here are signed, but don't use a signed limit
6857 check for 32 and 16 bit jumps as we want to allow wrap around at
6858 4G and 64k respectively. */
6860 fixP->fx_signed = 1;
6864 output_interseg_jump (void)
6872 if (flag_code == CODE_16BIT)
6876 if (i.prefix[DATA_PREFIX] != 0)
6882 if (i.prefix[REX_PREFIX] != 0)
6892 if (i.prefixes != 0 && !intel_syntax)
6893 as_warn (_("skipping prefixes on this instruction"));
6895 /* 1 opcode; 2 segment; offset */
6896 p = frag_more (prefix + 1 + 2 + size);
6898 if (i.prefix[DATA_PREFIX] != 0)
6899 *p++ = DATA_PREFIX_OPCODE;
6901 if (i.prefix[REX_PREFIX] != 0)
6902 *p++ = i.prefix[REX_PREFIX];
6904 *p++ = i.tm.base_opcode;
6905 if (i.op[1].imms->X_op == O_constant)
6907 offsetT n = i.op[1].imms->X_add_number;
6910 && !fits_in_unsigned_word (n)
6911 && !fits_in_signed_word (n))
6913 as_bad (_("16-bit jump out of range"));
6916 md_number_to_chars (p, n, size);
6919 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6920 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
6921 if (i.op[0].imms->X_op != O_constant)
6922 as_bad (_("can't handle non absolute segment in `%s'"),
6924 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6930 fragS *insn_start_frag;
6931 offsetT insn_start_off;
6933 /* Tie dwarf2 debug info to the address at the start of the insn.
6934 We can't do this after the insn has been output as the current
6935 frag may have been closed off. eg. by frag_var. */
6936 dwarf2_emit_insn (0);
6938 insn_start_frag = frag_now;
6939 insn_start_off = frag_now_fix ();
6942 if (i.tm.opcode_modifier.jump)
6944 else if (i.tm.opcode_modifier.jumpbyte
6945 || i.tm.opcode_modifier.jumpdword)
6947 else if (i.tm.opcode_modifier.jumpintersegment)
6948 output_interseg_jump ();
6951 /* Output normal instructions here. */
6955 unsigned int prefix;
6957 /* Some processors fail on LOCK prefix. This options makes
6958 assembler ignore LOCK prefix and serves as a workaround. */
6959 if (omit_lock_prefix)
6961 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6963 i.prefix[LOCK_PREFIX] = 0;
6966 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6967 don't need the explicit prefix. */
6968 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6970 switch (i.tm.opcode_length)
6973 if (i.tm.base_opcode & 0xff000000)
6975 prefix = (i.tm.base_opcode >> 24) & 0xff;
6980 if ((i.tm.base_opcode & 0xff0000) != 0)
6982 prefix = (i.tm.base_opcode >> 16) & 0xff;
6983 if (i.tm.cpu_flags.bitfield.cpupadlock)
6986 if (prefix != REPE_PREFIX_OPCODE
6987 || (i.prefix[REP_PREFIX]
6988 != REPE_PREFIX_OPCODE))
6989 add_prefix (prefix);
6992 add_prefix (prefix);
7001 /* The prefix bytes. */
7002 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7004 FRAG_APPEND_1_CHAR (*q);
7008 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7013 /* REX byte is encoded in VEX prefix. */
7017 FRAG_APPEND_1_CHAR (*q);
7020 /* There should be no other prefixes for instructions
7025 /* For EVEX instructions i.vrex should become 0 after
7026 build_evex_prefix. For VEX instructions upper 16 registers
7027 aren't available, so VREX should be 0. */
7030 /* Now the VEX prefix. */
7031 p = frag_more (i.vex.length);
7032 for (j = 0; j < i.vex.length; j++)
7033 p[j] = i.vex.bytes[j];
7036 /* Now the opcode; be careful about word order here! */
7037 if (i.tm.opcode_length == 1)
7039 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7043 switch (i.tm.opcode_length)
7047 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7048 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7052 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7062 /* Put out high byte first: can't use md_number_to_chars! */
7063 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7064 *p = i.tm.base_opcode & 0xff;
7067 /* Now the modrm byte and sib byte (if present). */
7068 if (i.tm.opcode_modifier.modrm)
7070 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7073 /* If i.rm.regmem == ESP (4)
7074 && i.rm.mode != (Register mode)
7076 ==> need second modrm byte. */
7077 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7079 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7080 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7082 | i.sib.scale << 6));
7085 if (i.disp_operands)
7086 output_disp (insn_start_frag, insn_start_off);
7089 output_imm (insn_start_frag, insn_start_off);
7095 pi ("" /*line*/, &i);
7097 #endif /* DEBUG386 */
7100 /* Return the size of the displacement operand N. */
7103 disp_size (unsigned int n)
7107 /* Vec_Disp8 has to be 8bit. */
7108 if (i.types[n].bitfield.vec_disp8)
7110 else if (i.types[n].bitfield.disp64)
7112 else if (i.types[n].bitfield.disp8)
7114 else if (i.types[n].bitfield.disp16)
7119 /* Return the size of the immediate operand N. */
7122 imm_size (unsigned int n)
7125 if (i.types[n].bitfield.imm64)
7127 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7129 else if (i.types[n].bitfield.imm16)
7135 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7140 for (n = 0; n < i.operands; n++)
7142 if (i.types[n].bitfield.vec_disp8
7143 || operand_type_check (i.types[n], disp))
7145 if (i.op[n].disps->X_op == O_constant)
7147 int size = disp_size (n);
7148 offsetT val = i.op[n].disps->X_add_number;
7150 if (i.types[n].bitfield.vec_disp8)
7152 val = offset_in_range (val, size);
7153 p = frag_more (size);
7154 md_number_to_chars (p, val, size);
7158 enum bfd_reloc_code_real reloc_type;
7159 int size = disp_size (n);
7160 int sign = i.types[n].bitfield.disp32s;
7161 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7163 /* We can't have 8 bit displacement here. */
7164 gas_assert (!i.types[n].bitfield.disp8);
7166 /* The PC relative address is computed relative
7167 to the instruction boundary, so in case immediate
7168 fields follows, we need to adjust the value. */
7169 if (pcrel && i.imm_operands)
7174 for (n1 = 0; n1 < i.operands; n1++)
7175 if (operand_type_check (i.types[n1], imm))
7177 /* Only one immediate is allowed for PC
7178 relative address. */
7179 gas_assert (sz == 0);
7181 i.op[n].disps->X_add_number -= sz;
7183 /* We should find the immediate. */
7184 gas_assert (sz != 0);
7187 p = frag_more (size);
7188 reloc_type = reloc (size, pcrel, sign,
7189 (i.bnd_prefix != NULL
7193 && GOT_symbol == i.op[n].disps->X_add_symbol
7194 && (((reloc_type == BFD_RELOC_32
7195 || reloc_type == BFD_RELOC_X86_64_32S
7196 || (reloc_type == BFD_RELOC_64
7198 && (i.op[n].disps->X_op == O_symbol
7199 || (i.op[n].disps->X_op == O_add
7200 && ((symbol_get_value_expression
7201 (i.op[n].disps->X_op_symbol)->X_op)
7203 || reloc_type == BFD_RELOC_32_PCREL))
7207 if (insn_start_frag == frag_now)
7208 add = (p - frag_now->fr_literal) - insn_start_off;
7213 add = insn_start_frag->fr_fix - insn_start_off;
7214 for (fr = insn_start_frag->fr_next;
7215 fr && fr != frag_now; fr = fr->fr_next)
7217 add += p - frag_now->fr_literal;
7222 reloc_type = BFD_RELOC_386_GOTPC;
7223 i.op[n].imms->X_add_number += add;
7225 else if (reloc_type == BFD_RELOC_64)
7226 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7228 /* Don't do the adjustment for x86-64, as there
7229 the pcrel addressing is relative to the _next_
7230 insn, and that is taken care of in other code. */
7231 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7233 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7234 i.op[n].disps, pcrel, reloc_type);
7241 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7246 for (n = 0; n < i.operands; n++)
7248 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7249 if (i.rounding && (int) n == i.rounding->operand)
7252 if (operand_type_check (i.types[n], imm))
7254 if (i.op[n].imms->X_op == O_constant)
7256 int size = imm_size (n);
7259 val = offset_in_range (i.op[n].imms->X_add_number,
7261 p = frag_more (size);
7262 md_number_to_chars (p, val, size);
7266 /* Not absolute_section.
7267 Need a 32-bit fixup (don't support 8bit
7268 non-absolute imms). Try to support other
7270 enum bfd_reloc_code_real reloc_type;
7271 int size = imm_size (n);
7274 if (i.types[n].bitfield.imm32s
7275 && (i.suffix == QWORD_MNEM_SUFFIX
7276 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7281 p = frag_more (size);
7282 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
7284 /* This is tough to explain. We end up with this one if we
7285 * have operands that look like
7286 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7287 * obtain the absolute address of the GOT, and it is strongly
7288 * preferable from a performance point of view to avoid using
7289 * a runtime relocation for this. The actual sequence of
7290 * instructions often look something like:
7295 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7297 * The call and pop essentially return the absolute address
7298 * of the label .L66 and store it in %ebx. The linker itself
7299 * will ultimately change the first operand of the addl so
7300 * that %ebx points to the GOT, but to keep things simple, the
7301 * .o file must have this operand set so that it generates not
7302 * the absolute address of .L66, but the absolute address of
7303 * itself. This allows the linker itself simply treat a GOTPC
7304 * relocation as asking for a pcrel offset to the GOT to be
7305 * added in, and the addend of the relocation is stored in the
7306 * operand field for the instruction itself.
7308 * Our job here is to fix the operand so that it would add
7309 * the correct offset so that %ebx would point to itself. The
7310 * thing that is tricky is that .-.L66 will point to the
7311 * beginning of the instruction, so we need to further modify
7312 * the operand so that it will point to itself. There are
7313 * other cases where you have something like:
7315 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7317 * and here no correction would be required. Internally in
7318 * the assembler we treat operands of this form as not being
7319 * pcrel since the '.' is explicitly mentioned, and I wonder
7320 * whether it would simplify matters to do it this way. Who
7321 * knows. In earlier versions of the PIC patches, the
7322 * pcrel_adjust field was used to store the correction, but
7323 * since the expression is not pcrel, I felt it would be
7324 * confusing to do it this way. */
7326 if ((reloc_type == BFD_RELOC_32
7327 || reloc_type == BFD_RELOC_X86_64_32S
7328 || reloc_type == BFD_RELOC_64)
7330 && GOT_symbol == i.op[n].imms->X_add_symbol
7331 && (i.op[n].imms->X_op == O_symbol
7332 || (i.op[n].imms->X_op == O_add
7333 && ((symbol_get_value_expression
7334 (i.op[n].imms->X_op_symbol)->X_op)
7339 if (insn_start_frag == frag_now)
7340 add = (p - frag_now->fr_literal) - insn_start_off;
7345 add = insn_start_frag->fr_fix - insn_start_off;
7346 for (fr = insn_start_frag->fr_next;
7347 fr && fr != frag_now; fr = fr->fr_next)
7349 add += p - frag_now->fr_literal;
7353 reloc_type = BFD_RELOC_386_GOTPC;
7355 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7357 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7358 i.op[n].imms->X_add_number += add;
7360 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7361 i.op[n].imms, 0, reloc_type);
7367 /* x86_cons_fix_new is called via the expression parsing code when a
7368 reloc is needed. We use this hook to get the correct .got reloc. */
7369 static int cons_sign = -1;
7372 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7373 expressionS *exp, bfd_reloc_code_real_type r)
7375 r = reloc (len, 0, cons_sign, 0, r);
7378 if (exp->X_op == O_secrel)
7380 exp->X_op = O_symbol;
7381 r = BFD_RELOC_32_SECREL;
7385 fix_new_exp (frag, off, len, exp, 0, r);
7388 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7389 purpose of the `.dc.a' internal pseudo-op. */
7392 x86_address_bytes (void)
7394 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7396 return stdoutput->arch_info->bits_per_address / 8;
7399 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7401 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7403 /* Parse operands of the form
7404 <symbol>@GOTOFF+<nnn>
7405 and similar .plt or .got references.
7407 If we find one, set up the correct relocation in RELOC and copy the
7408 input string, minus the `@GOTOFF' into a malloc'd buffer for
7409 parsing by the calling routine. Return this buffer, and if ADJUST
7410 is non-null set it to the length of the string we removed from the
7411 input line. Otherwise return NULL. */
7413 lex_got (enum bfd_reloc_code_real *rel,
7415 i386_operand_type *types,
7418 /* Some of the relocations depend on the size of what field is to
7419 be relocated. But in our callers i386_immediate and i386_displacement
7420 we don't yet know the operand size (this will be set by insn
7421 matching). Hence we record the word32 relocation here,
7422 and adjust the reloc according to the real size in reloc(). */
7423 static const struct {
7426 const enum bfd_reloc_code_real rel[2];
7427 const i386_operand_type types64;
7429 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7430 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7432 OPERAND_TYPE_IMM32_64 },
7434 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7435 BFD_RELOC_X86_64_PLTOFF64 },
7436 OPERAND_TYPE_IMM64 },
7437 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7438 BFD_RELOC_X86_64_PLT32 },
7439 OPERAND_TYPE_IMM32_32S_DISP32 },
7440 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7441 BFD_RELOC_X86_64_GOTPLT64 },
7442 OPERAND_TYPE_IMM64_DISP64 },
7443 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7444 BFD_RELOC_X86_64_GOTOFF64 },
7445 OPERAND_TYPE_IMM64_DISP64 },
7446 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7447 BFD_RELOC_X86_64_GOTPCREL },
7448 OPERAND_TYPE_IMM32_32S_DISP32 },
7449 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7450 BFD_RELOC_X86_64_TLSGD },
7451 OPERAND_TYPE_IMM32_32S_DISP32 },
7452 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7453 _dummy_first_bfd_reloc_code_real },
7454 OPERAND_TYPE_NONE },
7455 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7456 BFD_RELOC_X86_64_TLSLD },
7457 OPERAND_TYPE_IMM32_32S_DISP32 },
7458 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7459 BFD_RELOC_X86_64_GOTTPOFF },
7460 OPERAND_TYPE_IMM32_32S_DISP32 },
7461 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7462 BFD_RELOC_X86_64_TPOFF32 },
7463 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7464 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7465 _dummy_first_bfd_reloc_code_real },
7466 OPERAND_TYPE_NONE },
7467 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7468 BFD_RELOC_X86_64_DTPOFF32 },
7469 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7470 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7471 _dummy_first_bfd_reloc_code_real },
7472 OPERAND_TYPE_NONE },
7473 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7474 _dummy_first_bfd_reloc_code_real },
7475 OPERAND_TYPE_NONE },
7476 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7477 BFD_RELOC_X86_64_GOT32 },
7478 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7479 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7480 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7481 OPERAND_TYPE_IMM32_32S_DISP32 },
7482 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7483 BFD_RELOC_X86_64_TLSDESC_CALL },
7484 OPERAND_TYPE_IMM32_32S_DISP32 },
7489 #if defined (OBJ_MAYBE_ELF)
7494 for (cp = input_line_pointer; *cp != '@'; cp++)
7495 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7498 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7500 int len = gotrel[j].len;
7501 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7503 if (gotrel[j].rel[object_64bit] != 0)
7506 char *tmpbuf, *past_reloc;
7508 *rel = gotrel[j].rel[object_64bit];
7512 if (flag_code != CODE_64BIT)
7514 types->bitfield.imm32 = 1;
7515 types->bitfield.disp32 = 1;
7518 *types = gotrel[j].types64;
7521 if (j != 0 && GOT_symbol == NULL)
7522 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7524 /* The length of the first part of our input line. */
7525 first = cp - input_line_pointer;
7527 /* The second part goes from after the reloc token until
7528 (and including) an end_of_line char or comma. */
7529 past_reloc = cp + 1 + len;
7531 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7533 second = cp + 1 - past_reloc;
7535 /* Allocate and copy string. The trailing NUL shouldn't
7536 be necessary, but be safe. */
7537 tmpbuf = (char *) xmalloc (first + second + 2);
7538 memcpy (tmpbuf, input_line_pointer, first);
7539 if (second != 0 && *past_reloc != ' ')
7540 /* Replace the relocation token with ' ', so that
7541 errors like foo@GOTOFF1 will be detected. */
7542 tmpbuf[first++] = ' ';
7544 /* Increment length by 1 if the relocation token is
7549 memcpy (tmpbuf + first, past_reloc, second);
7550 tmpbuf[first + second] = '\0';
7551 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7552 *rel = BFD_RELOC_X86_64_PLT32_BND;
7556 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7557 gotrel[j].str, 1 << (5 + object_64bit));
7562 /* Might be a symbol version string. Don't as_bad here. */
7571 /* Parse operands of the form
7572 <symbol>@SECREL32+<nnn>
7574 If we find one, set up the correct relocation in RELOC and copy the
7575 input string, minus the `@SECREL32' into a malloc'd buffer for
7576 parsing by the calling routine. Return this buffer, and if ADJUST
7577 is non-null set it to the length of the string we removed from the
7578 input line. Otherwise return NULL.
7580 This function is copied from the ELF version above adjusted for PE targets. */
7583 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7584 int *adjust ATTRIBUTE_UNUSED,
7585 i386_operand_type *types,
7586 int bnd_prefix ATTRIBUTE_UNUSED)
7592 const enum bfd_reloc_code_real rel[2];
7593 const i386_operand_type types64;
7597 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7598 BFD_RELOC_32_SECREL },
7599 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7605 for (cp = input_line_pointer; *cp != '@'; cp++)
7606 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7609 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7611 int len = gotrel[j].len;
7613 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7615 if (gotrel[j].rel[object_64bit] != 0)
7618 char *tmpbuf, *past_reloc;
7620 *rel = gotrel[j].rel[object_64bit];
7626 if (flag_code != CODE_64BIT)
7628 types->bitfield.imm32 = 1;
7629 types->bitfield.disp32 = 1;
7632 *types = gotrel[j].types64;
7635 /* The length of the first part of our input line. */
7636 first = cp - input_line_pointer;
7638 /* The second part goes from after the reloc token until
7639 (and including) an end_of_line char or comma. */
7640 past_reloc = cp + 1 + len;
7642 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7644 second = cp + 1 - past_reloc;
7646 /* Allocate and copy string. The trailing NUL shouldn't
7647 be necessary, but be safe. */
7648 tmpbuf = (char *) xmalloc (first + second + 2);
7649 memcpy (tmpbuf, input_line_pointer, first);
7650 if (second != 0 && *past_reloc != ' ')
7651 /* Replace the relocation token with ' ', so that
7652 errors like foo@SECLREL321 will be detected. */
7653 tmpbuf[first++] = ' ';
7654 memcpy (tmpbuf + first, past_reloc, second);
7655 tmpbuf[first + second] = '\0';
7659 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7660 gotrel[j].str, 1 << (5 + object_64bit));
7665 /* Might be a symbol version string. Don't as_bad here. */
7671 bfd_reloc_code_real_type
7672 x86_cons (expressionS *exp, int size)
7674 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7676 intel_syntax = -intel_syntax;
7679 if (size == 4 || (object_64bit && size == 8))
7681 /* Handle @GOTOFF and the like in an expression. */
7683 char *gotfree_input_line;
7686 save = input_line_pointer;
7687 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
7688 if (gotfree_input_line)
7689 input_line_pointer = gotfree_input_line;
7693 if (gotfree_input_line)
7695 /* expression () has merrily parsed up to the end of line,
7696 or a comma - in the wrong buffer. Transfer how far
7697 input_line_pointer has moved to the right buffer. */
7698 input_line_pointer = (save
7699 + (input_line_pointer - gotfree_input_line)
7701 free (gotfree_input_line);
7702 if (exp->X_op == O_constant
7703 || exp->X_op == O_absent
7704 || exp->X_op == O_illegal
7705 || exp->X_op == O_register
7706 || exp->X_op == O_big)
7708 char c = *input_line_pointer;
7709 *input_line_pointer = 0;
7710 as_bad (_("missing or invalid expression `%s'"), save);
7711 *input_line_pointer = c;
7718 intel_syntax = -intel_syntax;
7721 i386_intel_simplify (exp);
7727 signed_cons (int size)
7729 if (flag_code == CODE_64BIT)
7737 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7744 if (exp.X_op == O_symbol)
7745 exp.X_op = O_secrel;
7747 emit_expr (&exp, 4);
7749 while (*input_line_pointer++ == ',');
7751 input_line_pointer--;
7752 demand_empty_rest_of_line ();
7756 /* Handle Vector operations. */
7759 check_VecOperations (char *op_string, char *op_end)
7761 const reg_entry *mask;
7766 && (op_end == NULL || op_string < op_end))
7769 if (*op_string == '{')
7773 /* Check broadcasts. */
7774 if (strncmp (op_string, "1to", 3) == 0)
7779 goto duplicated_vec_op;
7782 if (*op_string == '8')
7783 bcst_type = BROADCAST_1TO8;
7784 else if (*op_string == '4')
7785 bcst_type = BROADCAST_1TO4;
7786 else if (*op_string == '2')
7787 bcst_type = BROADCAST_1TO2;
7788 else if (*op_string == '1'
7789 && *(op_string+1) == '6')
7791 bcst_type = BROADCAST_1TO16;
7796 as_bad (_("Unsupported broadcast: `%s'"), saved);
7801 broadcast_op.type = bcst_type;
7802 broadcast_op.operand = this_operand;
7803 i.broadcast = &broadcast_op;
7805 /* Check masking operation. */
7806 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7808 /* k0 can't be used for write mask. */
7809 if (mask->reg_num == 0)
7811 as_bad (_("`%s' can't be used for write mask"),
7818 mask_op.mask = mask;
7819 mask_op.zeroing = 0;
7820 mask_op.operand = this_operand;
7826 goto duplicated_vec_op;
7828 i.mask->mask = mask;
7830 /* Only "{z}" is allowed here. No need to check
7831 zeroing mask explicitly. */
7832 if (i.mask->operand != this_operand)
7834 as_bad (_("invalid write mask `%s'"), saved);
7841 /* Check zeroing-flag for masking operation. */
7842 else if (*op_string == 'z')
7846 mask_op.mask = NULL;
7847 mask_op.zeroing = 1;
7848 mask_op.operand = this_operand;
7853 if (i.mask->zeroing)
7856 as_bad (_("duplicated `%s'"), saved);
7860 i.mask->zeroing = 1;
7862 /* Only "{%k}" is allowed here. No need to check mask
7863 register explicitly. */
7864 if (i.mask->operand != this_operand)
7866 as_bad (_("invalid zeroing-masking `%s'"),
7875 goto unknown_vec_op;
7877 if (*op_string != '}')
7879 as_bad (_("missing `}' in `%s'"), saved);
7886 /* We don't know this one. */
7887 as_bad (_("unknown vector operation: `%s'"), saved);
7895 i386_immediate (char *imm_start)
7897 char *save_input_line_pointer;
7898 char *gotfree_input_line;
7901 i386_operand_type types;
7903 operand_type_set (&types, ~0);
7905 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7907 as_bad (_("at most %d immediate operands are allowed"),
7908 MAX_IMMEDIATE_OPERANDS);
7912 exp = &im_expressions[i.imm_operands++];
7913 i.op[this_operand].imms = exp;
7915 if (is_space_char (*imm_start))
7918 save_input_line_pointer = input_line_pointer;
7919 input_line_pointer = imm_start;
7921 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7922 (i.bnd_prefix != NULL
7923 || add_bnd_prefix));
7924 if (gotfree_input_line)
7925 input_line_pointer = gotfree_input_line;
7927 exp_seg = expression (exp);
7931 /* Handle vector operations. */
7932 if (*input_line_pointer == '{')
7934 input_line_pointer = check_VecOperations (input_line_pointer,
7936 if (input_line_pointer == NULL)
7940 if (*input_line_pointer)
7941 as_bad (_("junk `%s' after expression"), input_line_pointer);
7943 input_line_pointer = save_input_line_pointer;
7944 if (gotfree_input_line)
7946 free (gotfree_input_line);
7948 if (exp->X_op == O_constant || exp->X_op == O_register)
7949 exp->X_op = O_illegal;
7952 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7956 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7957 i386_operand_type types, const char *imm_start)
7959 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7962 as_bad (_("missing or invalid immediate expression `%s'"),
7966 else if (exp->X_op == O_constant)
7968 /* Size it properly later. */
7969 i.types[this_operand].bitfield.imm64 = 1;
7970 /* If not 64bit, sign extend val. */
7971 if (flag_code != CODE_64BIT
7972 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7974 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7976 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7977 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7978 && exp_seg != absolute_section
7979 && exp_seg != text_section
7980 && exp_seg != data_section
7981 && exp_seg != bss_section
7982 && exp_seg != undefined_section
7983 && !bfd_is_com_section (exp_seg))
7985 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
7989 else if (!intel_syntax && exp->X_op == O_register)
7992 as_bad (_("illegal immediate register operand %s"), imm_start);
7997 /* This is an address. The size of the address will be
7998 determined later, depending on destination register,
7999 suffix, or the default for the section. */
8000 i.types[this_operand].bitfield.imm8 = 1;
8001 i.types[this_operand].bitfield.imm16 = 1;
8002 i.types[this_operand].bitfield.imm32 = 1;
8003 i.types[this_operand].bitfield.imm32s = 1;
8004 i.types[this_operand].bitfield.imm64 = 1;
8005 i.types[this_operand] = operand_type_and (i.types[this_operand],
8013 i386_scale (char *scale)
8016 char *save = input_line_pointer;
8018 input_line_pointer = scale;
8019 val = get_absolute_expression ();
8024 i.log2_scale_factor = 0;
8027 i.log2_scale_factor = 1;
8030 i.log2_scale_factor = 2;
8033 i.log2_scale_factor = 3;
8037 char sep = *input_line_pointer;
8039 *input_line_pointer = '\0';
8040 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8042 *input_line_pointer = sep;
8043 input_line_pointer = save;
8047 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8049 as_warn (_("scale factor of %d without an index register"),
8050 1 << i.log2_scale_factor);
8051 i.log2_scale_factor = 0;
8053 scale = input_line_pointer;
8054 input_line_pointer = save;
8059 i386_displacement (char *disp_start, char *disp_end)
8063 char *save_input_line_pointer;
8064 char *gotfree_input_line;
8066 i386_operand_type bigdisp, types = anydisp;
8069 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8071 as_bad (_("at most %d displacement operands are allowed"),
8072 MAX_MEMORY_OPERANDS);
8076 operand_type_set (&bigdisp, 0);
8077 if ((i.types[this_operand].bitfield.jumpabsolute)
8078 || (!current_templates->start->opcode_modifier.jump
8079 && !current_templates->start->opcode_modifier.jumpdword))
8081 bigdisp.bitfield.disp32 = 1;
8082 override = (i.prefix[ADDR_PREFIX] != 0);
8083 if (flag_code == CODE_64BIT)
8087 bigdisp.bitfield.disp32s = 1;
8088 bigdisp.bitfield.disp64 = 1;
8091 else if ((flag_code == CODE_16BIT) ^ override)
8093 bigdisp.bitfield.disp32 = 0;
8094 bigdisp.bitfield.disp16 = 1;
8099 /* For PC-relative branches, the width of the displacement
8100 is dependent upon data size, not address size. */
8101 override = (i.prefix[DATA_PREFIX] != 0);
8102 if (flag_code == CODE_64BIT)
8104 if (override || i.suffix == WORD_MNEM_SUFFIX)
8105 bigdisp.bitfield.disp16 = 1;
8108 bigdisp.bitfield.disp32 = 1;
8109 bigdisp.bitfield.disp32s = 1;
8115 override = (i.suffix == (flag_code != CODE_16BIT
8117 : LONG_MNEM_SUFFIX));
8118 bigdisp.bitfield.disp32 = 1;
8119 if ((flag_code == CODE_16BIT) ^ override)
8121 bigdisp.bitfield.disp32 = 0;
8122 bigdisp.bitfield.disp16 = 1;
8126 i.types[this_operand] = operand_type_or (i.types[this_operand],
8129 exp = &disp_expressions[i.disp_operands];
8130 i.op[this_operand].disps = exp;
8132 save_input_line_pointer = input_line_pointer;
8133 input_line_pointer = disp_start;
8134 END_STRING_AND_SAVE (disp_end);
8136 #ifndef GCC_ASM_O_HACK
8137 #define GCC_ASM_O_HACK 0
8140 END_STRING_AND_SAVE (disp_end + 1);
8141 if (i.types[this_operand].bitfield.baseIndex
8142 && displacement_string_end[-1] == '+')
8144 /* This hack is to avoid a warning when using the "o"
8145 constraint within gcc asm statements.
8148 #define _set_tssldt_desc(n,addr,limit,type) \
8149 __asm__ __volatile__ ( \
8151 "movw %w1,2+%0\n\t" \
8153 "movb %b1,4+%0\n\t" \
8154 "movb %4,5+%0\n\t" \
8155 "movb $0,6+%0\n\t" \
8156 "movb %h1,7+%0\n\t" \
8158 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8160 This works great except that the output assembler ends
8161 up looking a bit weird if it turns out that there is
8162 no offset. You end up producing code that looks like:
8175 So here we provide the missing zero. */
8177 *displacement_string_end = '0';
8180 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8181 (i.bnd_prefix != NULL
8182 || add_bnd_prefix));
8183 if (gotfree_input_line)
8184 input_line_pointer = gotfree_input_line;
8186 exp_seg = expression (exp);
8189 if (*input_line_pointer)
8190 as_bad (_("junk `%s' after expression"), input_line_pointer);
8192 RESTORE_END_STRING (disp_end + 1);
8194 input_line_pointer = save_input_line_pointer;
8195 if (gotfree_input_line)
8197 free (gotfree_input_line);
8199 if (exp->X_op == O_constant || exp->X_op == O_register)
8200 exp->X_op = O_illegal;
8203 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8205 RESTORE_END_STRING (disp_end);
8211 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8212 i386_operand_type types, const char *disp_start)
8214 i386_operand_type bigdisp;
8217 /* We do this to make sure that the section symbol is in
8218 the symbol table. We will ultimately change the relocation
8219 to be relative to the beginning of the section. */
8220 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8221 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8222 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8224 if (exp->X_op != O_symbol)
8227 if (S_IS_LOCAL (exp->X_add_symbol)
8228 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8229 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8230 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8231 exp->X_op = O_subtract;
8232 exp->X_op_symbol = GOT_symbol;
8233 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8234 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8235 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8236 i.reloc[this_operand] = BFD_RELOC_64;
8238 i.reloc[this_operand] = BFD_RELOC_32;
8241 else if (exp->X_op == O_absent
8242 || exp->X_op == O_illegal
8243 || exp->X_op == O_big)
8246 as_bad (_("missing or invalid displacement expression `%s'"),
8251 else if (flag_code == CODE_64BIT
8252 && !i.prefix[ADDR_PREFIX]
8253 && exp->X_op == O_constant)
8255 /* Since displacement is signed extended to 64bit, don't allow
8256 disp32 and turn off disp32s if they are out of range. */
8257 i.types[this_operand].bitfield.disp32 = 0;
8258 if (!fits_in_signed_long (exp->X_add_number))
8260 i.types[this_operand].bitfield.disp32s = 0;
8261 if (i.types[this_operand].bitfield.baseindex)
8263 as_bad (_("0x%lx out range of signed 32bit displacement"),
8264 (long) exp->X_add_number);
8270 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8271 else if (exp->X_op != O_constant
8272 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8273 && exp_seg != absolute_section
8274 && exp_seg != text_section
8275 && exp_seg != data_section
8276 && exp_seg != bss_section
8277 && exp_seg != undefined_section
8278 && !bfd_is_com_section (exp_seg))
8280 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8285 /* Check if this is a displacement only operand. */
8286 bigdisp = i.types[this_operand];
8287 bigdisp.bitfield.disp8 = 0;
8288 bigdisp.bitfield.disp16 = 0;
8289 bigdisp.bitfield.disp32 = 0;
8290 bigdisp.bitfield.disp32s = 0;
8291 bigdisp.bitfield.disp64 = 0;
8292 if (operand_type_all_zero (&bigdisp))
8293 i.types[this_operand] = operand_type_and (i.types[this_operand],
8299 /* Make sure the memory operand we've been dealt is valid.
8300 Return 1 on success, 0 on a failure. */
8303 i386_index_check (const char *operand_string)
8305 const char *kind = "base/index";
8306 enum flag_code addr_mode;
8308 if (i.prefix[ADDR_PREFIX])
8309 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8312 addr_mode = flag_code;
8314 #if INFER_ADDR_PREFIX
8315 if (i.mem_operands == 0)
8317 /* Infer address prefix from the first memory operand. */
8318 const reg_entry *addr_reg = i.base_reg;
8320 if (addr_reg == NULL)
8321 addr_reg = i.index_reg;
8325 if (addr_reg->reg_num == RegEip
8326 || addr_reg->reg_num == RegEiz
8327 || addr_reg->reg_type.bitfield.reg32)
8328 addr_mode = CODE_32BIT;
8329 else if (flag_code != CODE_64BIT
8330 && addr_reg->reg_type.bitfield.reg16)
8331 addr_mode = CODE_16BIT;
8333 if (addr_mode != flag_code)
8335 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8337 /* Change the size of any displacement too. At most one
8338 of Disp16 or Disp32 is set.
8339 FIXME. There doesn't seem to be any real need for
8340 separate Disp16 and Disp32 flags. The same goes for
8341 Imm16 and Imm32. Removing them would probably clean
8342 up the code quite a lot. */
8343 if (flag_code != CODE_64BIT
8344 && (i.types[this_operand].bitfield.disp16
8345 || i.types[this_operand].bitfield.disp32))
8346 i.types[this_operand]
8347 = operand_type_xor (i.types[this_operand], disp16_32);
8354 if (current_templates->start->opcode_modifier.isstring
8355 && !current_templates->start->opcode_modifier.immext
8356 && (current_templates->end[-1].opcode_modifier.isstring
8359 /* Memory operands of string insns are special in that they only allow
8360 a single register (rDI, rSI, or rBX) as their memory address. */
8361 const reg_entry *expected_reg;
8362 static const char *di_si[][2] =
8368 static const char *bx[] = { "ebx", "bx", "rbx" };
8370 kind = "string address";
8372 if (current_templates->start->opcode_modifier.w)
8374 i386_operand_type type = current_templates->end[-1].operand_types[0];
8376 if (!type.bitfield.baseindex
8377 || ((!i.mem_operands != !intel_syntax)
8378 && current_templates->end[-1].operand_types[1]
8379 .bitfield.baseindex))
8380 type = current_templates->end[-1].operand_types[1];
8381 expected_reg = hash_find (reg_hash,
8382 di_si[addr_mode][type.bitfield.esseg]);
8386 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8388 if (i.base_reg != expected_reg
8390 || operand_type_check (i.types[this_operand], disp))
8392 /* The second memory operand must have the same size as
8396 && !((addr_mode == CODE_64BIT
8397 && i.base_reg->reg_type.bitfield.reg64)
8398 || (addr_mode == CODE_32BIT
8399 ? i.base_reg->reg_type.bitfield.reg32
8400 : i.base_reg->reg_type.bitfield.reg16)))
8403 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8405 intel_syntax ? '[' : '(',
8407 expected_reg->reg_name,
8408 intel_syntax ? ']' : ')');
8415 as_bad (_("`%s' is not a valid %s expression"),
8416 operand_string, kind);
8421 if (addr_mode != CODE_16BIT)
8423 /* 32-bit/64-bit checks. */
8425 && (addr_mode == CODE_64BIT
8426 ? !i.base_reg->reg_type.bitfield.reg64
8427 : !i.base_reg->reg_type.bitfield.reg32)
8429 || (i.base_reg->reg_num
8430 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8432 && !i.index_reg->reg_type.bitfield.regxmm
8433 && !i.index_reg->reg_type.bitfield.regymm
8434 && !i.index_reg->reg_type.bitfield.regzmm
8435 && ((addr_mode == CODE_64BIT
8436 ? !(i.index_reg->reg_type.bitfield.reg64
8437 || i.index_reg->reg_num == RegRiz)
8438 : !(i.index_reg->reg_type.bitfield.reg32
8439 || i.index_reg->reg_num == RegEiz))
8440 || !i.index_reg->reg_type.bitfield.baseindex)))
8445 /* 16-bit checks. */
8447 && (!i.base_reg->reg_type.bitfield.reg16
8448 || !i.base_reg->reg_type.bitfield.baseindex))
8450 && (!i.index_reg->reg_type.bitfield.reg16
8451 || !i.index_reg->reg_type.bitfield.baseindex
8453 && i.base_reg->reg_num < 6
8454 && i.index_reg->reg_num >= 6
8455 && i.log2_scale_factor == 0))))
8462 /* Handle vector immediates. */
8465 RC_SAE_immediate (const char *imm_start)
8467 unsigned int match_found, j;
8468 const char *pstr = imm_start;
8476 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8478 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8482 rc_op.type = RC_NamesTable[j].type;
8483 rc_op.operand = this_operand;
8484 i.rounding = &rc_op;
8488 as_bad (_("duplicated `%s'"), imm_start);
8491 pstr += RC_NamesTable[j].len;
8501 as_bad (_("Missing '}': '%s'"), imm_start);
8504 /* RC/SAE immediate string should contain nothing more. */;
8507 as_bad (_("Junk after '}': '%s'"), imm_start);
8511 exp = &im_expressions[i.imm_operands++];
8512 i.op[this_operand].imms = exp;
8514 exp->X_op = O_constant;
8515 exp->X_add_number = 0;
8516 exp->X_add_symbol = (symbolS *) 0;
8517 exp->X_op_symbol = (symbolS *) 0;
8519 i.types[this_operand].bitfield.imm8 = 1;
8523 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8527 i386_att_operand (char *operand_string)
8531 char *op_string = operand_string;
8533 if (is_space_char (*op_string))
8536 /* We check for an absolute prefix (differentiating,
8537 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8538 if (*op_string == ABSOLUTE_PREFIX)
8541 if (is_space_char (*op_string))
8543 i.types[this_operand].bitfield.jumpabsolute = 1;
8546 /* Check if operand is a register. */
8547 if ((r = parse_register (op_string, &end_op)) != NULL)
8549 i386_operand_type temp;
8551 /* Check for a segment override by searching for ':' after a
8552 segment register. */
8554 if (is_space_char (*op_string))
8556 if (*op_string == ':'
8557 && (r->reg_type.bitfield.sreg2
8558 || r->reg_type.bitfield.sreg3))
8563 i.seg[i.mem_operands] = &es;
8566 i.seg[i.mem_operands] = &cs;
8569 i.seg[i.mem_operands] = &ss;
8572 i.seg[i.mem_operands] = &ds;
8575 i.seg[i.mem_operands] = &fs;
8578 i.seg[i.mem_operands] = &gs;
8582 /* Skip the ':' and whitespace. */
8584 if (is_space_char (*op_string))
8587 if (!is_digit_char (*op_string)
8588 && !is_identifier_char (*op_string)
8589 && *op_string != '('
8590 && *op_string != ABSOLUTE_PREFIX)
8592 as_bad (_("bad memory operand `%s'"), op_string);
8595 /* Handle case of %es:*foo. */
8596 if (*op_string == ABSOLUTE_PREFIX)
8599 if (is_space_char (*op_string))
8601 i.types[this_operand].bitfield.jumpabsolute = 1;
8603 goto do_memory_reference;
8606 /* Handle vector operations. */
8607 if (*op_string == '{')
8609 op_string = check_VecOperations (op_string, NULL);
8610 if (op_string == NULL)
8616 as_bad (_("junk `%s' after register"), op_string);
8620 temp.bitfield.baseindex = 0;
8621 i.types[this_operand] = operand_type_or (i.types[this_operand],
8623 i.types[this_operand].bitfield.unspecified = 0;
8624 i.op[this_operand].regs = r;
8627 else if (*op_string == REGISTER_PREFIX)
8629 as_bad (_("bad register name `%s'"), op_string);
8632 else if (*op_string == IMMEDIATE_PREFIX)
8635 if (i.types[this_operand].bitfield.jumpabsolute)
8637 as_bad (_("immediate operand illegal with absolute jump"));
8640 if (!i386_immediate (op_string))
8643 else if (RC_SAE_immediate (operand_string))
8645 /* If it is a RC or SAE immediate, do nothing. */
8648 else if (is_digit_char (*op_string)
8649 || is_identifier_char (*op_string)
8650 || *op_string == '(')
8652 /* This is a memory reference of some sort. */
8655 /* Start and end of displacement string expression (if found). */
8656 char *displacement_string_start;
8657 char *displacement_string_end;
8660 do_memory_reference:
8661 if ((i.mem_operands == 1
8662 && !current_templates->start->opcode_modifier.isstring)
8663 || i.mem_operands == 2)
8665 as_bad (_("too many memory references for `%s'"),
8666 current_templates->start->name);
8670 /* Check for base index form. We detect the base index form by
8671 looking for an ')' at the end of the operand, searching
8672 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8674 base_string = op_string + strlen (op_string);
8676 /* Handle vector operations. */
8677 vop_start = strchr (op_string, '{');
8678 if (vop_start && vop_start < base_string)
8680 if (check_VecOperations (vop_start, base_string) == NULL)
8682 base_string = vop_start;
8686 if (is_space_char (*base_string))
8689 /* If we only have a displacement, set-up for it to be parsed later. */
8690 displacement_string_start = op_string;
8691 displacement_string_end = base_string + 1;
8693 if (*base_string == ')')
8696 unsigned int parens_balanced = 1;
8697 /* We've already checked that the number of left & right ()'s are
8698 equal, so this loop will not be infinite. */
8702 if (*base_string == ')')
8704 if (*base_string == '(')
8707 while (parens_balanced);
8709 temp_string = base_string;
8711 /* Skip past '(' and whitespace. */
8713 if (is_space_char (*base_string))
8716 if (*base_string == ','
8717 || ((i.base_reg = parse_register (base_string, &end_op))
8720 displacement_string_end = temp_string;
8722 i.types[this_operand].bitfield.baseindex = 1;
8726 base_string = end_op;
8727 if (is_space_char (*base_string))
8731 /* There may be an index reg or scale factor here. */
8732 if (*base_string == ',')
8735 if (is_space_char (*base_string))
8738 if ((i.index_reg = parse_register (base_string, &end_op))
8741 base_string = end_op;
8742 if (is_space_char (*base_string))
8744 if (*base_string == ',')
8747 if (is_space_char (*base_string))
8750 else if (*base_string != ')')
8752 as_bad (_("expecting `,' or `)' "
8753 "after index register in `%s'"),
8758 else if (*base_string == REGISTER_PREFIX)
8760 end_op = strchr (base_string, ',');
8763 as_bad (_("bad register name `%s'"), base_string);
8767 /* Check for scale factor. */
8768 if (*base_string != ')')
8770 char *end_scale = i386_scale (base_string);
8775 base_string = end_scale;
8776 if (is_space_char (*base_string))
8778 if (*base_string != ')')
8780 as_bad (_("expecting `)' "
8781 "after scale factor in `%s'"),
8786 else if (!i.index_reg)
8788 as_bad (_("expecting index register or scale factor "
8789 "after `,'; got '%c'"),
8794 else if (*base_string != ')')
8796 as_bad (_("expecting `,' or `)' "
8797 "after base register in `%s'"),
8802 else if (*base_string == REGISTER_PREFIX)
8804 end_op = strchr (base_string, ',');
8807 as_bad (_("bad register name `%s'"), base_string);
8812 /* If there's an expression beginning the operand, parse it,
8813 assuming displacement_string_start and
8814 displacement_string_end are meaningful. */
8815 if (displacement_string_start != displacement_string_end)
8817 if (!i386_displacement (displacement_string_start,
8818 displacement_string_end))
8822 /* Special case for (%dx) while doing input/output op. */
8824 && operand_type_equal (&i.base_reg->reg_type,
8825 ®16_inoutportreg)
8827 && i.log2_scale_factor == 0
8828 && i.seg[i.mem_operands] == 0
8829 && !operand_type_check (i.types[this_operand], disp))
8831 i.types[this_operand] = inoutportreg;
8835 if (i386_index_check (operand_string) == 0)
8837 i.types[this_operand].bitfield.mem = 1;
8842 /* It's not a memory operand; argh! */
8843 as_bad (_("invalid char %s beginning operand %d `%s'"),
8844 output_invalid (*op_string),
8849 return 1; /* Normal return. */
8852 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8853 that an rs_machine_dependent frag may reach. */
8856 i386_frag_max_var (fragS *frag)
8858 /* The only relaxable frags are for jumps.
8859 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8860 gas_assert (frag->fr_type == rs_machine_dependent);
8861 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8864 /* md_estimate_size_before_relax()
8866 Called just before relax() for rs_machine_dependent frags. The x86
8867 assembler uses these frags to handle variable size jump
8870 Any symbol that is now undefined will not become defined.
8871 Return the correct fr_subtype in the frag.
8872 Return the initial "guess for variable size of frag" to caller.
8873 The guess is actually the growth beyond the fixed part. Whatever
8874 we do to grow the fixed or variable part contributes to our
8878 md_estimate_size_before_relax (fragS *fragP, segT segment)
8880 /* We've already got fragP->fr_subtype right; all we have to do is
8881 check for un-relaxable symbols. On an ELF system, we can't relax
8882 an externally visible symbol, because it may be overridden by a
8884 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8885 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8887 && (S_IS_EXTERNAL (fragP->fr_symbol)
8888 || S_IS_WEAK (fragP->fr_symbol)
8889 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8890 & BSF_GNU_INDIRECT_FUNCTION))))
8892 #if defined (OBJ_COFF) && defined (TE_PE)
8893 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8894 && S_IS_WEAK (fragP->fr_symbol))
8898 /* Symbol is undefined in this segment, or we need to keep a
8899 reloc so that weak symbols can be overridden. */
8900 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8901 enum bfd_reloc_code_real reloc_type;
8902 unsigned char *opcode;
8905 if (fragP->fr_var != NO_RELOC)
8906 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8908 reloc_type = BFD_RELOC_16_PCREL;
8910 reloc_type = BFD_RELOC_32_PCREL;
8912 old_fr_fix = fragP->fr_fix;
8913 opcode = (unsigned char *) fragP->fr_opcode;
8915 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8918 /* Make jmp (0xeb) a (d)word displacement jump. */
8920 fragP->fr_fix += size;
8921 fix_new (fragP, old_fr_fix, size,
8923 fragP->fr_offset, 1,
8929 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8931 /* Negate the condition, and branch past an
8932 unconditional jump. */
8935 /* Insert an unconditional jump. */
8937 /* We added two extra opcode bytes, and have a two byte
8939 fragP->fr_fix += 2 + 2;
8940 fix_new (fragP, old_fr_fix + 2, 2,
8942 fragP->fr_offset, 1,
8949 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8954 fixP = fix_new (fragP, old_fr_fix, 1,
8956 fragP->fr_offset, 1,
8958 fixP->fx_signed = 1;
8962 /* This changes the byte-displacement jump 0x7N
8963 to the (d)word-displacement jump 0x0f,0x8N. */
8964 opcode[1] = opcode[0] + 0x10;
8965 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8966 /* We've added an opcode byte. */
8967 fragP->fr_fix += 1 + size;
8968 fix_new (fragP, old_fr_fix + 1, size,
8970 fragP->fr_offset, 1,
8975 BAD_CASE (fragP->fr_subtype);
8979 return fragP->fr_fix - old_fr_fix;
8982 /* Guess size depending on current relax state. Initially the relax
8983 state will correspond to a short jump and we return 1, because
8984 the variable part of the frag (the branch offset) is one byte
8985 long. However, we can relax a section more than once and in that
8986 case we must either set fr_subtype back to the unrelaxed state,
8987 or return the value for the appropriate branch. */
8988 return md_relax_table[fragP->fr_subtype].rlx_length;
8991 /* Called after relax() is finished.
8993 In: Address of frag.
8994 fr_type == rs_machine_dependent.
8995 fr_subtype is what the address relaxed to.
8997 Out: Any fixSs and constants are set up.
8998 Caller will turn frag into a ".space 0". */
9001 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9004 unsigned char *opcode;
9005 unsigned char *where_to_put_displacement = NULL;
9006 offsetT target_address;
9007 offsetT opcode_address;
9008 unsigned int extension = 0;
9009 offsetT displacement_from_opcode_start;
9011 opcode = (unsigned char *) fragP->fr_opcode;
9013 /* Address we want to reach in file space. */
9014 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9016 /* Address opcode resides at in file space. */
9017 opcode_address = fragP->fr_address + fragP->fr_fix;
9019 /* Displacement from opcode start to fill into instruction. */
9020 displacement_from_opcode_start = target_address - opcode_address;
9022 if ((fragP->fr_subtype & BIG) == 0)
9024 /* Don't have to change opcode. */
9025 extension = 1; /* 1 opcode + 1 displacement */
9026 where_to_put_displacement = &opcode[1];
9030 if (no_cond_jump_promotion
9031 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9032 as_warn_where (fragP->fr_file, fragP->fr_line,
9033 _("long jump required"));
9035 switch (fragP->fr_subtype)
9037 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9038 extension = 4; /* 1 opcode + 4 displacement */
9040 where_to_put_displacement = &opcode[1];
9043 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9044 extension = 2; /* 1 opcode + 2 displacement */
9046 where_to_put_displacement = &opcode[1];
9049 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9050 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9051 extension = 5; /* 2 opcode + 4 displacement */
9052 opcode[1] = opcode[0] + 0x10;
9053 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9054 where_to_put_displacement = &opcode[2];
9057 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9058 extension = 3; /* 2 opcode + 2 displacement */
9059 opcode[1] = opcode[0] + 0x10;
9060 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9061 where_to_put_displacement = &opcode[2];
9064 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9069 where_to_put_displacement = &opcode[3];
9073 BAD_CASE (fragP->fr_subtype);
9078 /* If size if less then four we are sure that the operand fits,
9079 but if it's 4, then it could be that the displacement is larger
9081 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9083 && ((addressT) (displacement_from_opcode_start - extension
9084 + ((addressT) 1 << 31))
9085 > (((addressT) 2 << 31) - 1)))
9087 as_bad_where (fragP->fr_file, fragP->fr_line,
9088 _("jump target out of range"));
9089 /* Make us emit 0. */
9090 displacement_from_opcode_start = extension;
9092 /* Now put displacement after opcode. */
9093 md_number_to_chars ((char *) where_to_put_displacement,
9094 (valueT) (displacement_from_opcode_start - extension),
9095 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9096 fragP->fr_fix += extension;
9099 /* Apply a fixup (fixP) to segment data, once it has been determined
9100 by our caller that we have all the info we need to fix it up.
9102 Parameter valP is the pointer to the value of the bits.
9104 On the 386, immediates, displacements, and data pointers are all in
9105 the same (little-endian) format, so we don't need to care about which
9109 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9111 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9112 valueT value = *valP;
9114 #if !defined (TE_Mach)
9117 switch (fixP->fx_r_type)
9123 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9126 case BFD_RELOC_X86_64_32S:
9127 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9130 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9133 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9138 if (fixP->fx_addsy != NULL
9139 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9140 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9141 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9142 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9143 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
9144 && !use_rela_relocations)
9146 /* This is a hack. There should be a better way to handle this.
9147 This covers for the fact that bfd_install_relocation will
9148 subtract the current location (for partial_inplace, PC relative
9149 relocations); see more below. */
9153 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9156 value += fixP->fx_where + fixP->fx_frag->fr_address;
9158 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9161 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9164 || (symbol_section_p (fixP->fx_addsy)
9165 && sym_seg != absolute_section))
9166 && !generic_force_reloc (fixP))
9168 /* Yes, we add the values in twice. This is because
9169 bfd_install_relocation subtracts them out again. I think
9170 bfd_install_relocation is broken, but I don't dare change
9172 value += fixP->fx_where + fixP->fx_frag->fr_address;
9176 #if defined (OBJ_COFF) && defined (TE_PE)
9177 /* For some reason, the PE format does not store a
9178 section address offset for a PC relative symbol. */
9179 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9180 || S_IS_WEAK (fixP->fx_addsy))
9181 value += md_pcrel_from (fixP);
9184 #if defined (OBJ_COFF) && defined (TE_PE)
9185 if (fixP->fx_addsy != NULL
9186 && S_IS_WEAK (fixP->fx_addsy)
9187 /* PR 16858: Do not modify weak function references. */
9188 && ! fixP->fx_pcrel)
9190 #if !defined (TE_PEP)
9191 /* For x86 PE weak function symbols are neither PC-relative
9192 nor do they set S_IS_FUNCTION. So the only reliable way
9193 to detect them is to check the flags of their containing
9195 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9196 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9200 value -= S_GET_VALUE (fixP->fx_addsy);
9204 /* Fix a few things - the dynamic linker expects certain values here,
9205 and we must not disappoint it. */
9206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9207 if (IS_ELF && fixP->fx_addsy)
9208 switch (fixP->fx_r_type)
9210 case BFD_RELOC_386_PLT32:
9211 case BFD_RELOC_X86_64_PLT32:
9212 case BFD_RELOC_X86_64_PLT32_BND:
9213 /* Make the jump instruction point to the address of the operand. At
9214 runtime we merely add the offset to the actual PLT entry. */
9218 case BFD_RELOC_386_TLS_GD:
9219 case BFD_RELOC_386_TLS_LDM:
9220 case BFD_RELOC_386_TLS_IE_32:
9221 case BFD_RELOC_386_TLS_IE:
9222 case BFD_RELOC_386_TLS_GOTIE:
9223 case BFD_RELOC_386_TLS_GOTDESC:
9224 case BFD_RELOC_X86_64_TLSGD:
9225 case BFD_RELOC_X86_64_TLSLD:
9226 case BFD_RELOC_X86_64_GOTTPOFF:
9227 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9228 value = 0; /* Fully resolved at runtime. No addend. */
9230 case BFD_RELOC_386_TLS_LE:
9231 case BFD_RELOC_386_TLS_LDO_32:
9232 case BFD_RELOC_386_TLS_LE_32:
9233 case BFD_RELOC_X86_64_DTPOFF32:
9234 case BFD_RELOC_X86_64_DTPOFF64:
9235 case BFD_RELOC_X86_64_TPOFF32:
9236 case BFD_RELOC_X86_64_TPOFF64:
9237 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9240 case BFD_RELOC_386_TLS_DESC_CALL:
9241 case BFD_RELOC_X86_64_TLSDESC_CALL:
9242 value = 0; /* Fully resolved at runtime. No addend. */
9243 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9247 case BFD_RELOC_386_GOT32:
9248 case BFD_RELOC_X86_64_GOT32:
9249 value = 0; /* Fully resolved at runtime. No addend. */
9252 case BFD_RELOC_VTABLE_INHERIT:
9253 case BFD_RELOC_VTABLE_ENTRY:
9260 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9262 #endif /* !defined (TE_Mach) */
9264 /* Are we finished with this relocation now? */
9265 if (fixP->fx_addsy == NULL)
9267 #if defined (OBJ_COFF) && defined (TE_PE)
9268 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9271 /* Remember value for tc_gen_reloc. */
9272 fixP->fx_addnumber = value;
9273 /* Clear out the frag for now. */
9277 else if (use_rela_relocations)
9279 fixP->fx_no_overflow = 1;
9280 /* Remember value for tc_gen_reloc. */
9281 fixP->fx_addnumber = value;
9285 md_number_to_chars (p, value, fixP->fx_size);
9289 md_atof (int type, char *litP, int *sizeP)
9291 /* This outputs the LITTLENUMs in REVERSE order;
9292 in accord with the bigendian 386. */
9293 return ieee_md_atof (type, litP, sizeP, FALSE);
9296 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9299 output_invalid (int c)
9302 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9305 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9306 "(0x%x)", (unsigned char) c);
9307 return output_invalid_buf;
9310 /* REG_STRING starts *before* REGISTER_PREFIX. */
9312 static const reg_entry *
9313 parse_real_register (char *reg_string, char **end_op)
9315 char *s = reg_string;
9317 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9320 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9321 if (*s == REGISTER_PREFIX)
9324 if (is_space_char (*s))
9328 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9330 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9331 return (const reg_entry *) NULL;
9335 /* For naked regs, make sure that we are not dealing with an identifier.
9336 This prevents confusing an identifier like `eax_var' with register
9338 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9339 return (const reg_entry *) NULL;
9343 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9345 /* Handle floating point regs, allowing spaces in the (i) part. */
9346 if (r == i386_regtab /* %st is first entry of table */)
9348 if (is_space_char (*s))
9353 if (is_space_char (*s))
9355 if (*s >= '0' && *s <= '7')
9359 if (is_space_char (*s))
9364 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9369 /* We have "%st(" then garbage. */
9370 return (const reg_entry *) NULL;
9374 if (r == NULL || allow_pseudo_reg)
9377 if (operand_type_all_zero (&r->reg_type))
9378 return (const reg_entry *) NULL;
9380 if ((r->reg_type.bitfield.reg32
9381 || r->reg_type.bitfield.sreg3
9382 || r->reg_type.bitfield.control
9383 || r->reg_type.bitfield.debug
9384 || r->reg_type.bitfield.test)
9385 && !cpu_arch_flags.bitfield.cpui386)
9386 return (const reg_entry *) NULL;
9388 if (r->reg_type.bitfield.floatreg
9389 && !cpu_arch_flags.bitfield.cpu8087
9390 && !cpu_arch_flags.bitfield.cpu287
9391 && !cpu_arch_flags.bitfield.cpu387)
9392 return (const reg_entry *) NULL;
9394 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9395 return (const reg_entry *) NULL;
9397 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9398 return (const reg_entry *) NULL;
9400 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9401 return (const reg_entry *) NULL;
9403 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9404 && !cpu_arch_flags.bitfield.cpuavx512f)
9405 return (const reg_entry *) NULL;
9407 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9408 if (!allow_index_reg
9409 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9410 return (const reg_entry *) NULL;
9412 /* Upper 16 vector register is only available with VREX in 64bit
9414 if ((r->reg_flags & RegVRex))
9416 if (!cpu_arch_flags.bitfield.cpuvrex
9417 || flag_code != CODE_64BIT)
9418 return (const reg_entry *) NULL;
9423 if (((r->reg_flags & (RegRex64 | RegRex))
9424 || r->reg_type.bitfield.reg64)
9425 && (!cpu_arch_flags.bitfield.cpulm
9426 || !operand_type_equal (&r->reg_type, &control))
9427 && flag_code != CODE_64BIT)
9428 return (const reg_entry *) NULL;
9430 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9431 return (const reg_entry *) NULL;
9436 /* REG_STRING starts *before* REGISTER_PREFIX. */
9438 static const reg_entry *
9439 parse_register (char *reg_string, char **end_op)
9443 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9444 r = parse_real_register (reg_string, end_op);
9449 char *save = input_line_pointer;
9453 input_line_pointer = reg_string;
9454 c = get_symbol_end ();
9455 symbolP = symbol_find (reg_string);
9456 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9458 const expressionS *e = symbol_get_value_expression (symbolP);
9460 know (e->X_op == O_register);
9461 know (e->X_add_number >= 0
9462 && (valueT) e->X_add_number < i386_regtab_size);
9463 r = i386_regtab + e->X_add_number;
9464 if ((r->reg_flags & RegVRex))
9466 *end_op = input_line_pointer;
9468 *input_line_pointer = c;
9469 input_line_pointer = save;
9475 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9478 char *end = input_line_pointer;
9481 r = parse_register (name, &input_line_pointer);
9482 if (r && end <= input_line_pointer)
9484 *nextcharP = *input_line_pointer;
9485 *input_line_pointer = 0;
9486 e->X_op = O_register;
9487 e->X_add_number = r - i386_regtab;
9490 input_line_pointer = end;
9492 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9496 md_operand (expressionS *e)
9501 switch (*input_line_pointer)
9503 case REGISTER_PREFIX:
9504 r = parse_real_register (input_line_pointer, &end);
9507 e->X_op = O_register;
9508 e->X_add_number = r - i386_regtab;
9509 input_line_pointer = end;
9514 gas_assert (intel_syntax);
9515 end = input_line_pointer++;
9517 if (*input_line_pointer == ']')
9519 ++input_line_pointer;
9520 e->X_op_symbol = make_expr_symbol (e);
9521 e->X_add_symbol = NULL;
9522 e->X_add_number = 0;
9528 input_line_pointer = end;
9535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9536 const char *md_shortopts = "kVQ:sqn";
9538 const char *md_shortopts = "qn";
9541 #define OPTION_32 (OPTION_MD_BASE + 0)
9542 #define OPTION_64 (OPTION_MD_BASE + 1)
9543 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9544 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9545 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9546 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9547 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9548 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9549 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9550 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9551 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9552 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9553 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9554 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9555 #define OPTION_X32 (OPTION_MD_BASE + 14)
9556 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9557 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9558 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9559 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9560 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9561 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9563 struct option md_longopts[] =
9565 {"32", no_argument, NULL, OPTION_32},
9566 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9567 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9568 {"64", no_argument, NULL, OPTION_64},
9570 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9571 {"x32", no_argument, NULL, OPTION_X32},
9573 {"divide", no_argument, NULL, OPTION_DIVIDE},
9574 {"march", required_argument, NULL, OPTION_MARCH},
9575 {"mtune", required_argument, NULL, OPTION_MTUNE},
9576 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9577 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9578 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9579 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9580 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9581 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9582 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9583 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9584 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9585 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9586 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9587 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9588 # if defined (TE_PE) || defined (TE_PEP)
9589 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9591 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
9592 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
9593 {NULL, no_argument, NULL, 0}
9595 size_t md_longopts_size = sizeof (md_longopts);
9598 md_parse_option (int c, char *arg)
9606 optimize_align_code = 0;
9613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9614 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9615 should be emitted or not. FIXME: Not implemented. */
9619 /* -V: SVR4 argument to print version ID. */
9621 print_version_id ();
9624 /* -k: Ignore for FreeBSD compatibility. */
9629 /* -s: On i386 Solaris, this tells the native assembler to use
9630 .stab instead of .stab.excl. We always use .stab anyhow. */
9633 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9634 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9637 const char **list, **l;
9639 list = bfd_target_list ();
9640 for (l = list; *l != NULL; l++)
9641 if (CONST_STRNEQ (*l, "elf64-x86-64")
9642 || strcmp (*l, "coff-x86-64") == 0
9643 || strcmp (*l, "pe-x86-64") == 0
9644 || strcmp (*l, "pei-x86-64") == 0
9645 || strcmp (*l, "mach-o-x86-64") == 0)
9647 default_arch = "x86_64";
9651 as_fatal (_("no compiled in support for x86_64"));
9657 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9661 const char **list, **l;
9663 list = bfd_target_list ();
9664 for (l = list; *l != NULL; l++)
9665 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9667 default_arch = "x86_64:32";
9671 as_fatal (_("no compiled in support for 32bit x86_64"));
9675 as_fatal (_("32bit x86_64 is only supported for ELF"));
9680 default_arch = "i386";
9684 #ifdef SVR4_COMMENT_CHARS
9689 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9691 for (s = i386_comment_chars; *s != '\0'; s++)
9695 i386_comment_chars = n;
9701 arch = xstrdup (arg);
9705 as_fatal (_("invalid -march= option: `%s'"), arg);
9706 next = strchr (arch, '+');
9709 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9711 if (strcmp (arch, cpu_arch [j].name) == 0)
9714 if (! cpu_arch[j].flags.bitfield.cpui386)
9717 cpu_arch_name = cpu_arch[j].name;
9718 cpu_sub_arch_name = NULL;
9719 cpu_arch_flags = cpu_arch[j].flags;
9720 cpu_arch_isa = cpu_arch[j].type;
9721 cpu_arch_isa_flags = cpu_arch[j].flags;
9722 if (!cpu_arch_tune_set)
9724 cpu_arch_tune = cpu_arch_isa;
9725 cpu_arch_tune_flags = cpu_arch_isa_flags;
9729 else if (*cpu_arch [j].name == '.'
9730 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9732 /* ISA entension. */
9733 i386_cpu_flags flags;
9735 if (!cpu_arch[j].negated)
9736 flags = cpu_flags_or (cpu_arch_flags,
9739 flags = cpu_flags_and_not (cpu_arch_flags,
9741 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9743 if (cpu_sub_arch_name)
9745 char *name = cpu_sub_arch_name;
9746 cpu_sub_arch_name = concat (name,
9748 (const char *) NULL);
9752 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9753 cpu_arch_flags = flags;
9754 cpu_arch_isa_flags = flags;
9760 if (j >= ARRAY_SIZE (cpu_arch))
9761 as_fatal (_("invalid -march= option: `%s'"), arg);
9765 while (next != NULL );
9770 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9771 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9773 if (strcmp (arg, cpu_arch [j].name) == 0)
9775 cpu_arch_tune_set = 1;
9776 cpu_arch_tune = cpu_arch [j].type;
9777 cpu_arch_tune_flags = cpu_arch[j].flags;
9781 if (j >= ARRAY_SIZE (cpu_arch))
9782 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9785 case OPTION_MMNEMONIC:
9786 if (strcasecmp (arg, "att") == 0)
9788 else if (strcasecmp (arg, "intel") == 0)
9791 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9794 case OPTION_MSYNTAX:
9795 if (strcasecmp (arg, "att") == 0)
9797 else if (strcasecmp (arg, "intel") == 0)
9800 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9803 case OPTION_MINDEX_REG:
9804 allow_index_reg = 1;
9807 case OPTION_MNAKED_REG:
9808 allow_naked_reg = 1;
9811 case OPTION_MOLD_GCC:
9815 case OPTION_MSSE2AVX:
9819 case OPTION_MSSE_CHECK:
9820 if (strcasecmp (arg, "error") == 0)
9821 sse_check = check_error;
9822 else if (strcasecmp (arg, "warning") == 0)
9823 sse_check = check_warning;
9824 else if (strcasecmp (arg, "none") == 0)
9825 sse_check = check_none;
9827 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9830 case OPTION_MOPERAND_CHECK:
9831 if (strcasecmp (arg, "error") == 0)
9832 operand_check = check_error;
9833 else if (strcasecmp (arg, "warning") == 0)
9834 operand_check = check_warning;
9835 else if (strcasecmp (arg, "none") == 0)
9836 operand_check = check_none;
9838 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9841 case OPTION_MAVXSCALAR:
9842 if (strcasecmp (arg, "128") == 0)
9844 else if (strcasecmp (arg, "256") == 0)
9847 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9850 case OPTION_MADD_BND_PREFIX:
9854 case OPTION_MEVEXLIG:
9855 if (strcmp (arg, "128") == 0)
9857 else if (strcmp (arg, "256") == 0)
9859 else if (strcmp (arg, "512") == 0)
9862 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9865 case OPTION_MEVEXRCIG:
9866 if (strcmp (arg, "rne") == 0)
9868 else if (strcmp (arg, "rd") == 0)
9870 else if (strcmp (arg, "ru") == 0)
9872 else if (strcmp (arg, "rz") == 0)
9875 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9878 case OPTION_MEVEXWIG:
9879 if (strcmp (arg, "0") == 0)
9881 else if (strcmp (arg, "1") == 0)
9884 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9887 # if defined (TE_PE) || defined (TE_PEP)
9888 case OPTION_MBIG_OBJ:
9893 case OPTION_OMIT_LOCK_PREFIX:
9894 if (strcasecmp (arg, "yes") == 0)
9895 omit_lock_prefix = 1;
9896 else if (strcasecmp (arg, "no") == 0)
9897 omit_lock_prefix = 0;
9899 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9908 #define MESSAGE_TEMPLATE \
9912 show_arch (FILE *stream, int ext, int check)
9914 static char message[] = MESSAGE_TEMPLATE;
9915 char *start = message + 27;
9917 int size = sizeof (MESSAGE_TEMPLATE);
9924 left = size - (start - message);
9925 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9927 /* Should it be skipped? */
9928 if (cpu_arch [j].skip)
9931 name = cpu_arch [j].name;
9932 len = cpu_arch [j].len;
9935 /* It is an extension. Skip if we aren't asked to show it. */
9946 /* It is an processor. Skip if we show only extension. */
9949 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9951 /* It is an impossible processor - skip. */
9955 /* Reserve 2 spaces for ", " or ",\0" */
9958 /* Check if there is any room. */
9966 p = mempcpy (p, name, len);
9970 /* Output the current message now and start a new one. */
9973 fprintf (stream, "%s\n", message);
9975 left = size - (start - message) - len - 2;
9977 gas_assert (left >= 0);
9979 p = mempcpy (p, name, len);
9984 fprintf (stream, "%s\n", message);
9988 md_show_usage (FILE *stream)
9990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9991 fprintf (stream, _("\
9993 -V print assembler version number\n\
9996 fprintf (stream, _("\
9997 -n Do not optimize code alignment\n\
9998 -q quieten some warnings\n"));
9999 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10000 fprintf (stream, _("\
10003 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10004 || defined (TE_PE) || defined (TE_PEP))
10005 fprintf (stream, _("\
10006 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10008 #ifdef SVR4_COMMENT_CHARS
10009 fprintf (stream, _("\
10010 --divide do not treat `/' as a comment character\n"));
10012 fprintf (stream, _("\
10013 --divide ignored\n"));
10015 fprintf (stream, _("\
10016 -march=CPU[,+EXTENSION...]\n\
10017 generate code for CPU and EXTENSION, CPU is one of:\n"));
10018 show_arch (stream, 0, 1);
10019 fprintf (stream, _("\
10020 EXTENSION is combination of:\n"));
10021 show_arch (stream, 1, 0);
10022 fprintf (stream, _("\
10023 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10024 show_arch (stream, 0, 0);
10025 fprintf (stream, _("\
10026 -msse2avx encode SSE instructions with VEX prefix\n"));
10027 fprintf (stream, _("\
10028 -msse-check=[none|error|warning]\n\
10029 check SSE instructions\n"));
10030 fprintf (stream, _("\
10031 -moperand-check=[none|error|warning]\n\
10032 check operand combinations for validity\n"));
10033 fprintf (stream, _("\
10034 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10036 fprintf (stream, _("\
10037 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10039 fprintf (stream, _("\
10040 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10041 for EVEX.W bit ignored instructions\n"));
10042 fprintf (stream, _("\
10043 -mevexrcig=[rne|rd|ru|rz]\n\
10044 encode EVEX instructions with specific EVEX.RC value\n\
10045 for SAE-only ignored instructions\n"));
10046 fprintf (stream, _("\
10047 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10048 fprintf (stream, _("\
10049 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10050 fprintf (stream, _("\
10051 -mindex-reg support pseudo index registers\n"));
10052 fprintf (stream, _("\
10053 -mnaked-reg don't require `%%' prefix for registers\n"));
10054 fprintf (stream, _("\
10055 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10056 fprintf (stream, _("\
10057 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10058 # if defined (TE_PE) || defined (TE_PEP)
10059 fprintf (stream, _("\
10060 -mbig-obj generate big object files\n"));
10062 fprintf (stream, _("\
10063 -momit-lock-prefix=[no|yes]\n\
10064 strip all lock prefixes\n"));
10067 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10068 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10069 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10071 /* Pick the target format to use. */
10074 i386_target_format (void)
10076 if (!strncmp (default_arch, "x86_64", 6))
10078 update_code_flag (CODE_64BIT, 1);
10079 if (default_arch[6] == '\0')
10080 x86_elf_abi = X86_64_ABI;
10082 x86_elf_abi = X86_64_X32_ABI;
10084 else if (!strcmp (default_arch, "i386"))
10085 update_code_flag (CODE_32BIT, 1);
10087 as_fatal (_("unknown architecture"));
10089 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10090 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10091 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10092 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10094 switch (OUTPUT_FLAVOR)
10096 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10097 case bfd_target_aout_flavour:
10098 return AOUT_TARGET_FORMAT;
10100 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10101 # if defined (TE_PE) || defined (TE_PEP)
10102 case bfd_target_coff_flavour:
10103 if (flag_code == CODE_64BIT)
10104 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10107 # elif defined (TE_GO32)
10108 case bfd_target_coff_flavour:
10109 return "coff-go32";
10111 case bfd_target_coff_flavour:
10112 return "coff-i386";
10115 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10116 case bfd_target_elf_flavour:
10118 const char *format;
10120 switch (x86_elf_abi)
10123 format = ELF_TARGET_FORMAT;
10126 use_rela_relocations = 1;
10128 format = ELF_TARGET_FORMAT64;
10130 case X86_64_X32_ABI:
10131 use_rela_relocations = 1;
10133 disallow_64bit_reloc = 1;
10134 format = ELF_TARGET_FORMAT32;
10137 if (cpu_arch_isa == PROCESSOR_L1OM)
10139 if (x86_elf_abi != X86_64_ABI)
10140 as_fatal (_("Intel L1OM is 64bit only"));
10141 return ELF_TARGET_L1OM_FORMAT;
10143 if (cpu_arch_isa == PROCESSOR_K1OM)
10145 if (x86_elf_abi != X86_64_ABI)
10146 as_fatal (_("Intel K1OM is 64bit only"));
10147 return ELF_TARGET_K1OM_FORMAT;
10153 #if defined (OBJ_MACH_O)
10154 case bfd_target_mach_o_flavour:
10155 if (flag_code == CODE_64BIT)
10157 use_rela_relocations = 1;
10159 return "mach-o-x86-64";
10162 return "mach-o-i386";
10170 #endif /* OBJ_MAYBE_ more than one */
10172 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10174 i386_elf_emit_arch_note (void)
10176 if (IS_ELF && cpu_arch_name != NULL)
10179 asection *seg = now_seg;
10180 subsegT subseg = now_subseg;
10181 Elf_Internal_Note i_note;
10182 Elf_External_Note e_note;
10183 asection *note_secp;
10186 /* Create the .note section. */
10187 note_secp = subseg_new (".note", 0);
10188 bfd_set_section_flags (stdoutput,
10190 SEC_HAS_CONTENTS | SEC_READONLY);
10192 /* Process the arch string. */
10193 len = strlen (cpu_arch_name);
10195 i_note.namesz = len + 1;
10197 i_note.type = NT_ARCH;
10198 p = frag_more (sizeof (e_note.namesz));
10199 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10200 p = frag_more (sizeof (e_note.descsz));
10201 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10202 p = frag_more (sizeof (e_note.type));
10203 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10204 p = frag_more (len + 1);
10205 strcpy (p, cpu_arch_name);
10207 frag_align (2, 0, 0);
10209 subseg_set (seg, subseg);
10215 md_undefined_symbol (char *name)
10217 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10218 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10219 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10220 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10224 if (symbol_find (name))
10225 as_bad (_("GOT already in symbol table"));
10226 GOT_symbol = symbol_new (name, undefined_section,
10227 (valueT) 0, &zero_address_frag);
10234 /* Round up a section size to the appropriate boundary. */
10237 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10239 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10240 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10242 /* For a.out, force the section size to be aligned. If we don't do
10243 this, BFD will align it for us, but it will not write out the
10244 final bytes of the section. This may be a bug in BFD, but it is
10245 easier to fix it here since that is how the other a.out targets
10249 align = bfd_get_section_alignment (stdoutput, segment);
10250 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10257 /* On the i386, PC-relative offsets are relative to the start of the
10258 next instruction. That is, the address of the offset, plus its
10259 size, since the offset is always the last part of the insn. */
10262 md_pcrel_from (fixS *fixP)
10264 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10270 s_bss (int ignore ATTRIBUTE_UNUSED)
10274 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10276 obj_elf_section_change_hook ();
10278 temp = get_absolute_expression ();
10279 subseg_set (bss_section, (subsegT) temp);
10280 demand_empty_rest_of_line ();
10286 i386_validate_fix (fixS *fixp)
10288 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10290 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10294 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10299 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10301 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10303 fixp->fx_subsy = 0;
10308 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10311 bfd_reloc_code_real_type code;
10313 switch (fixp->fx_r_type)
10315 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10316 case BFD_RELOC_SIZE32:
10317 case BFD_RELOC_SIZE64:
10318 if (S_IS_DEFINED (fixp->fx_addsy)
10319 && !S_IS_EXTERNAL (fixp->fx_addsy))
10321 /* Resolve size relocation against local symbol to size of
10322 the symbol plus addend. */
10323 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10324 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10325 && !fits_in_unsigned_long (value))
10326 as_bad_where (fixp->fx_file, fixp->fx_line,
10327 _("symbol size computation overflow"));
10328 fixp->fx_addsy = NULL;
10329 fixp->fx_subsy = NULL;
10330 md_apply_fix (fixp, (valueT *) &value, NULL);
10335 case BFD_RELOC_X86_64_PLT32:
10336 case BFD_RELOC_X86_64_PLT32_BND:
10337 case BFD_RELOC_X86_64_GOT32:
10338 case BFD_RELOC_X86_64_GOTPCREL:
10339 case BFD_RELOC_386_PLT32:
10340 case BFD_RELOC_386_GOT32:
10341 case BFD_RELOC_386_GOTOFF:
10342 case BFD_RELOC_386_GOTPC:
10343 case BFD_RELOC_386_TLS_GD:
10344 case BFD_RELOC_386_TLS_LDM:
10345 case BFD_RELOC_386_TLS_LDO_32:
10346 case BFD_RELOC_386_TLS_IE_32:
10347 case BFD_RELOC_386_TLS_IE:
10348 case BFD_RELOC_386_TLS_GOTIE:
10349 case BFD_RELOC_386_TLS_LE_32:
10350 case BFD_RELOC_386_TLS_LE:
10351 case BFD_RELOC_386_TLS_GOTDESC:
10352 case BFD_RELOC_386_TLS_DESC_CALL:
10353 case BFD_RELOC_X86_64_TLSGD:
10354 case BFD_RELOC_X86_64_TLSLD:
10355 case BFD_RELOC_X86_64_DTPOFF32:
10356 case BFD_RELOC_X86_64_DTPOFF64:
10357 case BFD_RELOC_X86_64_GOTTPOFF:
10358 case BFD_RELOC_X86_64_TPOFF32:
10359 case BFD_RELOC_X86_64_TPOFF64:
10360 case BFD_RELOC_X86_64_GOTOFF64:
10361 case BFD_RELOC_X86_64_GOTPC32:
10362 case BFD_RELOC_X86_64_GOT64:
10363 case BFD_RELOC_X86_64_GOTPCREL64:
10364 case BFD_RELOC_X86_64_GOTPC64:
10365 case BFD_RELOC_X86_64_GOTPLT64:
10366 case BFD_RELOC_X86_64_PLTOFF64:
10367 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10368 case BFD_RELOC_X86_64_TLSDESC_CALL:
10369 case BFD_RELOC_RVA:
10370 case BFD_RELOC_VTABLE_ENTRY:
10371 case BFD_RELOC_VTABLE_INHERIT:
10373 case BFD_RELOC_32_SECREL:
10375 code = fixp->fx_r_type;
10377 case BFD_RELOC_X86_64_32S:
10378 if (!fixp->fx_pcrel)
10380 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10381 code = fixp->fx_r_type;
10385 if (fixp->fx_pcrel)
10387 switch (fixp->fx_size)
10390 as_bad_where (fixp->fx_file, fixp->fx_line,
10391 _("can not do %d byte pc-relative relocation"),
10393 code = BFD_RELOC_32_PCREL;
10395 case 1: code = BFD_RELOC_8_PCREL; break;
10396 case 2: code = BFD_RELOC_16_PCREL; break;
10398 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10399 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10402 case 8: code = BFD_RELOC_64_PCREL; break;
10408 switch (fixp->fx_size)
10411 as_bad_where (fixp->fx_file, fixp->fx_line,
10412 _("can not do %d byte relocation"),
10414 code = BFD_RELOC_32;
10416 case 1: code = BFD_RELOC_8; break;
10417 case 2: code = BFD_RELOC_16; break;
10418 case 4: code = BFD_RELOC_32; break;
10420 case 8: code = BFD_RELOC_64; break;
10427 if ((code == BFD_RELOC_32
10428 || code == BFD_RELOC_32_PCREL
10429 || code == BFD_RELOC_X86_64_32S)
10431 && fixp->fx_addsy == GOT_symbol)
10434 code = BFD_RELOC_386_GOTPC;
10436 code = BFD_RELOC_X86_64_GOTPC32;
10438 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10440 && fixp->fx_addsy == GOT_symbol)
10442 code = BFD_RELOC_X86_64_GOTPC64;
10445 rel = (arelent *) xmalloc (sizeof (arelent));
10446 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10447 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10449 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10451 if (!use_rela_relocations)
10453 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10454 vtable entry to be used in the relocation's section offset. */
10455 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10456 rel->address = fixp->fx_offset;
10457 #if defined (OBJ_COFF) && defined (TE_PE)
10458 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10459 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10464 /* Use the rela in 64bit mode. */
10467 if (disallow_64bit_reloc)
10470 case BFD_RELOC_X86_64_DTPOFF64:
10471 case BFD_RELOC_X86_64_TPOFF64:
10472 case BFD_RELOC_64_PCREL:
10473 case BFD_RELOC_X86_64_GOTOFF64:
10474 case BFD_RELOC_X86_64_GOT64:
10475 case BFD_RELOC_X86_64_GOTPCREL64:
10476 case BFD_RELOC_X86_64_GOTPC64:
10477 case BFD_RELOC_X86_64_GOTPLT64:
10478 case BFD_RELOC_X86_64_PLTOFF64:
10479 as_bad_where (fixp->fx_file, fixp->fx_line,
10480 _("cannot represent relocation type %s in x32 mode"),
10481 bfd_get_reloc_code_name (code));
10487 if (!fixp->fx_pcrel)
10488 rel->addend = fixp->fx_offset;
10492 case BFD_RELOC_X86_64_PLT32:
10493 case BFD_RELOC_X86_64_PLT32_BND:
10494 case BFD_RELOC_X86_64_GOT32:
10495 case BFD_RELOC_X86_64_GOTPCREL:
10496 case BFD_RELOC_X86_64_TLSGD:
10497 case BFD_RELOC_X86_64_TLSLD:
10498 case BFD_RELOC_X86_64_GOTTPOFF:
10499 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10500 case BFD_RELOC_X86_64_TLSDESC_CALL:
10501 rel->addend = fixp->fx_offset - fixp->fx_size;
10504 rel->addend = (section->vma
10506 + fixp->fx_addnumber
10507 + md_pcrel_from (fixp));
10512 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10513 if (rel->howto == NULL)
10515 as_bad_where (fixp->fx_file, fixp->fx_line,
10516 _("cannot represent relocation type %s"),
10517 bfd_get_reloc_code_name (code));
10518 /* Set howto to a garbage value so that we can keep going. */
10519 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10520 gas_assert (rel->howto != NULL);
10526 #include "tc-i386-intel.c"
10529 tc_x86_parse_to_dw2regnum (expressionS *exp)
10531 int saved_naked_reg;
10532 char saved_register_dot;
10534 saved_naked_reg = allow_naked_reg;
10535 allow_naked_reg = 1;
10536 saved_register_dot = register_chars['.'];
10537 register_chars['.'] = '.';
10538 allow_pseudo_reg = 1;
10539 expression_and_evaluate (exp);
10540 allow_pseudo_reg = 0;
10541 register_chars['.'] = saved_register_dot;
10542 allow_naked_reg = saved_naked_reg;
10544 if (exp->X_op == O_register && exp->X_add_number >= 0)
10546 if ((addressT) exp->X_add_number < i386_regtab_size)
10548 exp->X_op = O_constant;
10549 exp->X_add_number = i386_regtab[exp->X_add_number]
10550 .dw2_regnum[flag_code >> 1];
10553 exp->X_op = O_illegal;
10558 tc_x86_frame_initial_instructions (void)
10560 static unsigned int sp_regno[2];
10562 if (!sp_regno[flag_code >> 1])
10564 char *saved_input = input_line_pointer;
10565 char sp[][4] = {"esp", "rsp"};
10568 input_line_pointer = sp[flag_code >> 1];
10569 tc_x86_parse_to_dw2regnum (&exp);
10570 gas_assert (exp.X_op == O_constant);
10571 sp_regno[flag_code >> 1] = exp.X_add_number;
10572 input_line_pointer = saved_input;
10575 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10576 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10580 x86_dwarf2_addr_size (void)
10582 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10583 if (x86_elf_abi == X86_64_X32_ABI)
10586 return bfd_arch_bits_per_address (stdoutput) / 8;
10590 i386_elf_section_type (const char *str, size_t len)
10592 if (flag_code == CODE_64BIT
10593 && len == sizeof ("unwind") - 1
10594 && strncmp (str, "unwind", 6) == 0)
10595 return SHT_X86_64_UNWIND;
10602 i386_solaris_fix_up_eh_frame (segT sec)
10604 if (flag_code == CODE_64BIT)
10605 elf_section_type (sec) = SHT_X86_64_UNWIND;
10611 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10615 exp.X_op = O_secrel;
10616 exp.X_add_symbol = symbol;
10617 exp.X_add_number = 0;
10618 emit_expr (&exp, size);
10622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10623 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10626 x86_64_section_letter (int letter, char **ptr_msg)
10628 if (flag_code == CODE_64BIT)
10631 return SHF_X86_64_LARGE;
10633 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10636 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10641 x86_64_section_word (char *str, size_t len)
10643 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10644 return SHF_X86_64_LARGE;
10650 handle_large_common (int small ATTRIBUTE_UNUSED)
10652 if (flag_code != CODE_64BIT)
10654 s_comm_internal (0, elf_common_parse);
10655 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10659 static segT lbss_section;
10660 asection *saved_com_section_ptr = elf_com_section_ptr;
10661 asection *saved_bss_section = bss_section;
10663 if (lbss_section == NULL)
10665 flagword applicable;
10666 segT seg = now_seg;
10667 subsegT subseg = now_subseg;
10669 /* The .lbss section is for local .largecomm symbols. */
10670 lbss_section = subseg_new (".lbss", 0);
10671 applicable = bfd_applicable_section_flags (stdoutput);
10672 bfd_set_section_flags (stdoutput, lbss_section,
10673 applicable & SEC_ALLOC);
10674 seg_info (lbss_section)->bss = 1;
10676 subseg_set (seg, subseg);
10679 elf_com_section_ptr = &_bfd_elf_large_com_section;
10680 bss_section = lbss_section;
10682 s_comm_internal (0, elf_common_parse);
10684 elf_com_section_ptr = saved_com_section_ptr;
10685 bss_section = saved_bss_section;
10688 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */