1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "dw2gencfi.h"
34 #include "opcode/i386.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
44 #ifndef SCALE1_WHEN_NO_INDEX
45 /* Specifying a scale factor besides 1 when there is no index is
46 futile. eg. `mov (%ebx,2),%al' does exactly the same as
47 `mov (%ebx),%al'. To slavishly follow what the programmer
48 specified, set SCALE1_WHEN_NO_INDEX to 0. */
49 #define SCALE1_WHEN_NO_INDEX 1
53 #define DEFAULT_ARCH "i386"
58 #define INLINE __inline__
64 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
65 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
66 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
67 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
68 static INLINE int fits_in_signed_word PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
70 static INLINE int fits_in_signed_long PARAMS ((offsetT));
71 static int smallest_imm_type PARAMS ((offsetT));
72 static offsetT offset_in_range PARAMS ((offsetT, int));
73 static int add_prefix PARAMS ((unsigned int));
74 static void set_code_flag PARAMS ((int));
75 static void set_16bit_gcc_code_flag PARAMS ((int));
76 static void set_intel_syntax PARAMS ((int));
77 static void set_cpu_arch PARAMS ((int));
78 static char *output_invalid PARAMS ((int c));
79 static int i386_operand PARAMS ((char *operand_string));
80 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
81 static const reg_entry *parse_register PARAMS ((char *reg_string,
83 static char *parse_insn PARAMS ((char *, char *));
84 static char *parse_operands PARAMS ((char *, const char *));
85 static void swap_operands PARAMS ((void));
86 static void optimize_imm PARAMS ((void));
87 static void optimize_disp PARAMS ((void));
88 static int match_template PARAMS ((void));
89 static int check_string PARAMS ((void));
90 static int process_suffix PARAMS ((void));
91 static int check_byte_reg PARAMS ((void));
92 static int check_long_reg PARAMS ((void));
93 static int check_qword_reg PARAMS ((void));
94 static int check_word_reg PARAMS ((void));
95 static int finalize_imm PARAMS ((void));
96 static int process_operands PARAMS ((void));
97 static const seg_entry *build_modrm_byte PARAMS ((void));
98 static void output_insn PARAMS ((void));
99 static void output_branch PARAMS ((void));
100 static void output_jump PARAMS ((void));
101 static void output_interseg_jump PARAMS ((void));
102 static void output_imm PARAMS ((fragS *insn_start_frag,
103 offsetT insn_start_off));
104 static void output_disp PARAMS ((fragS *insn_start_frag,
105 offsetT insn_start_off));
107 static void s_bss PARAMS ((int));
110 static const char *default_arch = DEFAULT_ARCH;
112 /* 'md_assemble ()' gathers together information and puts it into a
119 const reg_entry *regs;
124 /* TM holds the template for the insn were currently assembling. */
127 /* SUFFIX holds the instruction mnemonic suffix if given.
128 (e.g. 'l' for 'movl') */
131 /* OPERANDS gives the number of given operands. */
132 unsigned int operands;
134 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
135 of given register, displacement, memory operands and immediate
137 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
139 /* TYPES [i] is the type (see above #defines) which tells us how to
140 use OP[i] for the corresponding operand. */
141 unsigned int types[MAX_OPERANDS];
143 /* Displacement expression, immediate expression, or register for each
145 union i386_op op[MAX_OPERANDS];
147 /* Flags for operands. */
148 unsigned int flags[MAX_OPERANDS];
149 #define Operand_PCrel 1
151 /* Relocation type for operand */
152 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
154 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
155 the base index byte below. */
156 const reg_entry *base_reg;
157 const reg_entry *index_reg;
158 unsigned int log2_scale_factor;
160 /* SEG gives the seg_entries of this insn. They are zero unless
161 explicit segment overrides are given. */
162 const seg_entry *seg[2];
164 /* PREFIX holds all the given prefix opcodes (usually null).
165 PREFIXES is the number of prefix opcodes. */
166 unsigned int prefixes;
167 unsigned char prefix[MAX_PREFIXES];
169 /* RM and SIB are the modrm byte and the sib byte where the
170 addressing modes of this insn are encoded. */
177 typedef struct _i386_insn i386_insn;
179 /* List of chars besides those in app.c:symbol_chars that can start an
180 operand. Used to prevent the scrubber eating vital white-space. */
182 const char extra_symbol_chars[] = "*%-(@[";
184 const char extra_symbol_chars[] = "*%-([";
187 #if (defined (TE_I386AIX) \
188 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
189 && !defined (TE_LINUX) \
190 && !defined (TE_FreeBSD) \
191 && !defined (TE_NetBSD)))
192 /* This array holds the chars that always start a comment. If the
193 pre-processor is disabled, these aren't very useful. */
194 const char comment_chars[] = "#/";
195 #define PREFIX_SEPARATOR '\\'
197 /* This array holds the chars that only start a comment at the beginning of
198 a line. If the line seems to have the form '# 123 filename'
199 .line and .file directives will appear in the pre-processed output.
200 Note that input_file.c hand checks for '#' at the beginning of the
201 first line of the input file. This is because the compiler outputs
202 #NO_APP at the beginning of its output.
203 Also note that comments started like this one will always work if
204 '/' isn't otherwise defined. */
205 const char line_comment_chars[] = "#";
208 /* Putting '/' here makes it impossible to use the divide operator.
209 However, we need it for compatibility with SVR4 systems. */
210 const char comment_chars[] = "#";
211 #define PREFIX_SEPARATOR '/'
213 const char line_comment_chars[] = "/#";
216 const char line_separator_chars[] = ";";
218 /* Chars that can be used to separate mant from exp in floating point
220 const char EXP_CHARS[] = "eE";
222 /* Chars that mean this number is a floating point constant
225 const char FLT_CHARS[] = "fFdDxX";
227 /* Tables for lexical analysis. */
228 static char mnemonic_chars[256];
229 static char register_chars[256];
230 static char operand_chars[256];
231 static char identifier_chars[256];
232 static char digit_chars[256];
234 /* Lexical macros. */
235 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
236 #define is_operand_char(x) (operand_chars[(unsigned char) x])
237 #define is_register_char(x) (register_chars[(unsigned char) x])
238 #define is_space_char(x) ((x) == ' ')
239 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
240 #define is_digit_char(x) (digit_chars[(unsigned char) x])
242 /* All non-digit non-letter characters that may occur in an operand. */
243 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
245 /* md_assemble() always leaves the strings it's passed unaltered. To
246 effect this we maintain a stack of saved characters that we've smashed
247 with '\0's (indicating end of strings for various sub-fields of the
248 assembler instruction). */
249 static char save_stack[32];
250 static char *save_stack_p;
251 #define END_STRING_AND_SAVE(s) \
252 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
253 #define RESTORE_END_STRING(s) \
254 do { *(s) = *--save_stack_p; } while (0)
256 /* The instruction we're assembling. */
259 /* Possible templates for current insn. */
260 static const templates *current_templates;
262 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
263 static expressionS disp_expressions[2], im_expressions[2];
265 /* Current operand we are working on. */
266 static int this_operand;
268 /* We support four different modes. FLAG_CODE variable is used to distinguish
275 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
277 static enum flag_code flag_code;
278 static int use_rela_relocations = 0;
280 /* The names used to print error messages. */
281 static const char *flag_code_names[] =
288 /* 1 for intel syntax,
290 static int intel_syntax = 0;
292 /* 1 if register prefix % not required. */
293 static int allow_naked_reg = 0;
295 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298 static char stackop_size = '\0';
300 /* Non-zero to optimize code alignment. */
301 int optimize_align_code = 1;
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings = 0;
307 static const char *cpu_arch_name = NULL;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion = 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
320 unsigned int x86_dwarf2_return_column;
322 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
323 int x86_cie_data_alignment;
325 /* Interface to relax_segment.
326 There are 3 major relax states for 386 jump insns because the
327 different types of jumps add different sizes to frags when we're
328 figuring out what sort of jump to choose to reach a given label. */
331 #define UNCOND_JUMP 0
333 #define COND_JUMP86 2
338 #define SMALL16 (SMALL | CODE16)
340 #define BIG16 (BIG | CODE16)
344 #define INLINE __inline__
350 #define ENCODE_RELAX_STATE(type, size) \
351 ((relax_substateT) (((type) << 2) | (size)))
352 #define TYPE_FROM_RELAX_STATE(s) \
354 #define DISP_SIZE_FROM_RELAX_STATE(s) \
355 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
357 /* This table is used by relax_frag to promote short jumps to long
358 ones where necessary. SMALL (short) jumps may be promoted to BIG
359 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
360 don't allow a short jump in a 32 bit code segment to be promoted to
361 a 16 bit offset jump because it's slower (requires data size
362 prefix), and doesn't work, unless the destination is in the bottom
363 64k of the code segment (The top 16 bits of eip are zeroed). */
365 const relax_typeS md_relax_table[] =
368 1) most positive reach of this state,
369 2) most negative reach of this state,
370 3) how many bytes this mode will have in the variable part of the frag
371 4) which index into the table to try if we can't fit into this one. */
373 /* UNCOND_JUMP states. */
374 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
375 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
376 /* dword jmp adds 4 bytes to frag:
377 0 extra opcode bytes, 4 displacement bytes. */
379 /* word jmp adds 2 byte2 to frag:
380 0 extra opcode bytes, 2 displacement bytes. */
383 /* COND_JUMP states. */
384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
386 /* dword conditionals adds 5 bytes to frag:
387 1 extra opcode byte, 4 displacement bytes. */
389 /* word conditionals add 3 bytes to frag:
390 1 extra opcode byte, 2 displacement bytes. */
393 /* COND_JUMP86 states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
399 /* word conditionals add 4 bytes to frag:
400 1 displacement byte and a 3 byte long branch insn. */
404 static const arch_entry cpu_arch[] = {
406 {"i186", Cpu086|Cpu186 },
407 {"i286", Cpu086|Cpu186|Cpu286 },
408 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
409 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
410 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
411 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
412 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
413 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
414 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
415 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
416 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
417 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
421 const pseudo_typeS md_pseudo_table[] =
423 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
424 {"align", s_align_bytes, 0},
426 {"align", s_align_ptwo, 0},
428 {"arch", set_cpu_arch, 0},
432 {"ffloat", float_cons, 'f'},
433 {"dfloat", float_cons, 'd'},
434 {"tfloat", float_cons, 'x'},
436 {"noopt", s_ignore, 0},
437 {"optim", s_ignore, 0},
438 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
439 {"code16", set_code_flag, CODE_16BIT},
440 {"code32", set_code_flag, CODE_32BIT},
441 {"code64", set_code_flag, CODE_64BIT},
442 {"intel_syntax", set_intel_syntax, 1},
443 {"att_syntax", set_intel_syntax, 0},
444 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
445 {"loc", dwarf2_directive_loc, 0},
449 /* For interface with expression (). */
450 extern char *input_line_pointer;
452 /* Hash table for instruction mnemonic lookup. */
453 static struct hash_control *op_hash;
455 /* Hash table for register lookup. */
456 static struct hash_control *reg_hash;
459 i386_align_code (fragP, count)
463 /* Various efficient no-op patterns for aligning code labels.
464 Note: Don't try to assemble the instructions in the comments.
465 0L and 0w are not legal. */
466 static const char f32_1[] =
468 static const char f32_2[] =
469 {0x89,0xf6}; /* movl %esi,%esi */
470 static const char f32_3[] =
471 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
472 static const char f32_4[] =
473 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
474 static const char f32_5[] =
476 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
477 static const char f32_6[] =
478 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
479 static const char f32_7[] =
480 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
481 static const char f32_8[] =
483 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
484 static const char f32_9[] =
485 {0x89,0xf6, /* movl %esi,%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_10[] =
488 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
489 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
490 static const char f32_11[] =
491 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_12[] =
494 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
495 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
496 static const char f32_13[] =
497 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
498 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
499 static const char f32_14[] =
500 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
501 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
502 static const char f32_15[] =
503 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
504 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
505 static const char f16_3[] =
506 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
507 static const char f16_4[] =
508 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
509 static const char f16_5[] =
511 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
512 static const char f16_6[] =
513 {0x89,0xf6, /* mov %si,%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char f16_7[] =
516 {0x8d,0x74,0x00, /* lea 0(%si),%si */
517 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
518 static const char f16_8[] =
519 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
520 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
521 static const char *const f32_patt[] = {
522 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
523 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
525 static const char *const f16_patt[] = {
526 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
527 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
530 if (count <= 0 || count > 15)
533 /* The recommended way to pad 64bit code is to use NOPs preceded by
534 maximally four 0x66 prefixes. Balance the size of nops. */
535 if (flag_code == CODE_64BIT)
538 int nnops = (count + 3) / 4;
539 int len = count / nnops;
540 int remains = count - nnops * len;
543 for (i = 0; i < remains; i++)
545 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
546 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
549 for (; i < nnops; i++)
551 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
552 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
557 if (flag_code == CODE_16BIT)
559 memcpy (fragP->fr_literal + fragP->fr_fix,
560 f16_patt[count - 1], count);
562 /* Adjust jump offset. */
563 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
566 memcpy (fragP->fr_literal + fragP->fr_fix,
567 f32_patt[count - 1], count);
568 fragP->fr_var = count;
571 static INLINE unsigned int
572 mode_from_disp_size (t)
575 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
579 fits_in_signed_byte (num)
582 return (num >= -128) && (num <= 127);
586 fits_in_unsigned_byte (num)
589 return (num & 0xff) == num;
593 fits_in_unsigned_word (num)
596 return (num & 0xffff) == num;
600 fits_in_signed_word (num)
603 return (-32768 <= num) && (num <= 32767);
606 fits_in_signed_long (num)
607 offsetT num ATTRIBUTE_UNUSED;
612 return (!(((offsetT) -1 << 31) & num)
613 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
615 } /* fits_in_signed_long() */
617 fits_in_unsigned_long (num)
618 offsetT num ATTRIBUTE_UNUSED;
623 return (num & (((offsetT) 2 << 31) - 1)) == num;
625 } /* fits_in_unsigned_long() */
628 smallest_imm_type (num)
631 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
633 /* This code is disabled on the 486 because all the Imm1 forms
634 in the opcode table are slower on the i486. They're the
635 versions with the implicitly specified single-position
636 displacement, which has another syntax if you really want to
639 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
641 return (fits_in_signed_byte (num)
642 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_unsigned_byte (num)
644 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
645 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
646 ? (Imm16 | Imm32 | Imm32S | Imm64)
647 : fits_in_signed_long (num)
648 ? (Imm32 | Imm32S | Imm64)
649 : fits_in_unsigned_long (num)
655 offset_in_range (val, size)
663 case 1: mask = ((addressT) 1 << 8) - 1; break;
664 case 2: mask = ((addressT) 1 << 16) - 1; break;
665 case 4: mask = ((addressT) 2 << 31) - 1; break;
667 case 8: mask = ((addressT) 2 << 63) - 1; break;
672 /* If BFD64, sign extend val. */
673 if (!use_rela_relocations)
674 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
675 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
677 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
679 char buf1[40], buf2[40];
681 sprint_value (buf1, val);
682 sprint_value (buf2, val & mask);
683 as_warn (_("%s shortened to %s"), buf1, buf2);
688 /* Returns 0 if attempting to add a prefix where one from the same
689 class already exists, 1 if non rep/repne added, 2 if rep/repne
698 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
699 && flag_code == CODE_64BIT)
707 case CS_PREFIX_OPCODE:
708 case DS_PREFIX_OPCODE:
709 case ES_PREFIX_OPCODE:
710 case FS_PREFIX_OPCODE:
711 case GS_PREFIX_OPCODE:
712 case SS_PREFIX_OPCODE:
716 case REPNE_PREFIX_OPCODE:
717 case REPE_PREFIX_OPCODE:
720 case LOCK_PREFIX_OPCODE:
728 case ADDR_PREFIX_OPCODE:
732 case DATA_PREFIX_OPCODE:
737 if (i.prefix[q] != 0)
739 as_bad (_("same type of prefix used twice"));
744 i.prefix[q] = prefix;
749 set_code_flag (value)
753 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
754 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
755 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
757 as_bad (_("64bit mode not supported on this CPU."));
759 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
761 as_bad (_("32bit mode not supported on this CPU."));
767 set_16bit_gcc_code_flag (new_code_flag)
770 flag_code = new_code_flag;
771 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
772 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
777 set_intel_syntax (syntax_flag)
780 /* Find out if register prefixing is specified. */
781 int ask_naked_reg = 0;
784 if (!is_end_of_line[(unsigned char) *input_line_pointer])
786 char *string = input_line_pointer;
787 int e = get_symbol_end ();
789 if (strcmp (string, "prefix") == 0)
791 else if (strcmp (string, "noprefix") == 0)
794 as_bad (_("bad argument to syntax directive."));
795 *input_line_pointer = e;
797 demand_empty_rest_of_line ();
799 intel_syntax = syntax_flag;
801 if (ask_naked_reg == 0)
802 allow_naked_reg = (intel_syntax
803 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
805 allow_naked_reg = (ask_naked_reg < 0);
810 int dummy ATTRIBUTE_UNUSED;
814 if (!is_end_of_line[(unsigned char) *input_line_pointer])
816 char *string = input_line_pointer;
817 int e = get_symbol_end ();
820 for (i = 0; cpu_arch[i].name; i++)
822 if (strcmp (string, cpu_arch[i].name) == 0)
824 cpu_arch_name = cpu_arch[i].name;
825 cpu_arch_flags = (cpu_arch[i].flags
826 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
830 if (!cpu_arch[i].name)
831 as_bad (_("no such architecture: `%s'"), string);
833 *input_line_pointer = e;
836 as_bad (_("missing cpu architecture"));
838 no_cond_jump_promotion = 0;
839 if (*input_line_pointer == ','
840 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
842 char *string = ++input_line_pointer;
843 int e = get_symbol_end ();
845 if (strcmp (string, "nojumps") == 0)
846 no_cond_jump_promotion = 1;
847 else if (strcmp (string, "jumps") == 0)
850 as_bad (_("no such architecture modifier: `%s'"), string);
852 *input_line_pointer = e;
855 demand_empty_rest_of_line ();
861 if (!strcmp (default_arch, "x86_64"))
862 return bfd_mach_x86_64;
863 else if (!strcmp (default_arch, "i386"))
864 return bfd_mach_i386_i386;
866 as_fatal (_("Unknown architecture"));
872 const char *hash_err;
874 /* Initialize op_hash hash table. */
875 op_hash = hash_new ();
878 const template *optab;
879 templates *core_optab;
881 /* Setup for loop. */
883 core_optab = (templates *) xmalloc (sizeof (templates));
884 core_optab->start = optab;
889 if (optab->name == NULL
890 || strcmp (optab->name, (optab - 1)->name) != 0)
892 /* different name --> ship out current template list;
893 add to hash table; & begin anew. */
894 core_optab->end = optab;
895 hash_err = hash_insert (op_hash,
900 as_fatal (_("Internal Error: Can't hash %s: %s"),
904 if (optab->name == NULL)
906 core_optab = (templates *) xmalloc (sizeof (templates));
907 core_optab->start = optab;
912 /* Initialize reg_hash hash table. */
913 reg_hash = hash_new ();
915 const reg_entry *regtab;
917 for (regtab = i386_regtab;
918 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
921 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
923 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
934 for (c = 0; c < 256; c++)
939 mnemonic_chars[c] = c;
940 register_chars[c] = c;
941 operand_chars[c] = c;
943 else if (ISLOWER (c))
945 mnemonic_chars[c] = c;
946 register_chars[c] = c;
947 operand_chars[c] = c;
949 else if (ISUPPER (c))
951 mnemonic_chars[c] = TOLOWER (c);
952 register_chars[c] = mnemonic_chars[c];
953 operand_chars[c] = c;
956 if (ISALPHA (c) || ISDIGIT (c))
957 identifier_chars[c] = c;
960 identifier_chars[c] = c;
961 operand_chars[c] = c;
966 identifier_chars['@'] = '@';
968 digit_chars['-'] = '-';
969 identifier_chars['_'] = '_';
970 identifier_chars['.'] = '.';
972 for (p = operand_special_chars; *p != '\0'; p++)
973 operand_chars[(unsigned char) *p] = *p;
976 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
977 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
979 record_alignment (text_section, 2);
980 record_alignment (data_section, 2);
981 record_alignment (bss_section, 2);
985 if (flag_code == CODE_64BIT)
987 x86_dwarf2_return_column = 16;
988 x86_cie_data_alignment = -8;
992 x86_dwarf2_return_column = 8;
993 x86_cie_data_alignment = -4;
998 i386_print_statistics (file)
1001 hash_print_statistics (file, "i386 opcode", op_hash);
1002 hash_print_statistics (file, "i386 register", reg_hash);
1007 /* Debugging routines for md_assemble. */
1008 static void pi PARAMS ((char *, i386_insn *));
1009 static void pte PARAMS ((template *));
1010 static void pt PARAMS ((unsigned int));
1011 static void pe PARAMS ((expressionS *));
1012 static void ps PARAMS ((symbolS *));
1021 fprintf (stdout, "%s: template ", line);
1023 fprintf (stdout, " address: base %s index %s scale %x\n",
1024 x->base_reg ? x->base_reg->reg_name : "none",
1025 x->index_reg ? x->index_reg->reg_name : "none",
1026 x->log2_scale_factor);
1027 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1028 x->rm.mode, x->rm.reg, x->rm.regmem);
1029 fprintf (stdout, " sib: base %x index %x scale %x\n",
1030 x->sib.base, x->sib.index, x->sib.scale);
1031 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1032 (x->rex & REX_MODE64) != 0,
1033 (x->rex & REX_EXTX) != 0,
1034 (x->rex & REX_EXTY) != 0,
1035 (x->rex & REX_EXTZ) != 0);
1036 for (i = 0; i < x->operands; i++)
1038 fprintf (stdout, " #%d: ", i + 1);
1040 fprintf (stdout, "\n");
1042 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1043 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1044 if (x->types[i] & Imm)
1046 if (x->types[i] & Disp)
1047 pe (x->op[i].disps);
1056 fprintf (stdout, " %d operands ", t->operands);
1057 fprintf (stdout, "opcode %x ", t->base_opcode);
1058 if (t->extension_opcode != None)
1059 fprintf (stdout, "ext %x ", t->extension_opcode);
1060 if (t->opcode_modifier & D)
1061 fprintf (stdout, "D");
1062 if (t->opcode_modifier & W)
1063 fprintf (stdout, "W");
1064 fprintf (stdout, "\n");
1065 for (i = 0; i < t->operands; i++)
1067 fprintf (stdout, " #%d type ", i + 1);
1068 pt (t->operand_types[i]);
1069 fprintf (stdout, "\n");
1077 fprintf (stdout, " operation %d\n", e->X_op);
1078 fprintf (stdout, " add_number %ld (%lx)\n",
1079 (long) e->X_add_number, (long) e->X_add_number);
1080 if (e->X_add_symbol)
1082 fprintf (stdout, " add_symbol ");
1083 ps (e->X_add_symbol);
1084 fprintf (stdout, "\n");
1088 fprintf (stdout, " op_symbol ");
1089 ps (e->X_op_symbol);
1090 fprintf (stdout, "\n");
1098 fprintf (stdout, "%s type %s%s",
1100 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1101 segment_name (S_GET_SEGMENT (s)));
1110 static const type_names[] =
1123 { BaseIndex, "BaseIndex" },
1127 { Disp32S, "d32s" },
1129 { InOutPortReg, "InOutPortReg" },
1130 { ShiftCount, "ShiftCount" },
1131 { Control, "control reg" },
1132 { Test, "test reg" },
1133 { Debug, "debug reg" },
1134 { FloatReg, "FReg" },
1135 { FloatAcc, "FAcc" },
1139 { JumpAbsolute, "Jump Absolute" },
1150 const struct type_name *ty;
1152 for (ty = type_names; ty->mask; ty++)
1154 fprintf (stdout, "%s, ", ty->tname);
1158 #endif /* DEBUG386 */
1160 static bfd_reloc_code_real_type reloc
1161 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1163 static bfd_reloc_code_real_type
1164 reloc (size, pcrel, sign, other)
1168 bfd_reloc_code_real_type other;
1170 if (other != NO_RELOC)
1176 as_bad (_("There are no unsigned pc-relative relocations"));
1179 case 1: return BFD_RELOC_8_PCREL;
1180 case 2: return BFD_RELOC_16_PCREL;
1181 case 4: return BFD_RELOC_32_PCREL;
1183 as_bad (_("can not do %d byte pc-relative relocation"), size);
1190 case 4: return BFD_RELOC_X86_64_32S;
1195 case 1: return BFD_RELOC_8;
1196 case 2: return BFD_RELOC_16;
1197 case 4: return BFD_RELOC_32;
1198 case 8: return BFD_RELOC_64;
1200 as_bad (_("can not do %s %d byte relocation"),
1201 sign ? "signed" : "unsigned", size);
1205 return BFD_RELOC_NONE;
1208 /* Here we decide which fixups can be adjusted to make them relative to
1209 the beginning of the section instead of the symbol. Basically we need
1210 to make sure that the dynamic relocations are done correctly, so in
1211 some cases we force the original symbol to be used. */
1214 tc_i386_fix_adjustable (fixP)
1215 fixS *fixP ATTRIBUTE_UNUSED;
1217 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1218 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1221 /* Don't adjust pc-relative references to merge sections in 64-bit
1223 if (use_rela_relocations
1224 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1228 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1229 and changed later by validate_fix. */
1230 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1231 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1234 /* adjust_reloc_syms doesn't know about the GOT. */
1235 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1236 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1237 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1238 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1239 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1240 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1241 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1242 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1243 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1244 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1245 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1246 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1247 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1248 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1249 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1250 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1251 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1252 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1253 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1254 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1255 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1261 static int intel_float_operand PARAMS ((const char *mnemonic));
1264 intel_float_operand (mnemonic)
1265 const char *mnemonic;
1267 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1270 if (mnemonic[0] == 'f')
1276 /* This is the guts of the machine-dependent assembler. LINE points to a
1277 machine dependent instruction. This function is supposed to emit
1278 the frags/bytes it assembles to. */
1285 char mnemonic[MAX_MNEM_SIZE];
1287 /* Initialize globals. */
1288 memset (&i, '\0', sizeof (i));
1289 for (j = 0; j < MAX_OPERANDS; j++)
1290 i.reloc[j] = NO_RELOC;
1291 memset (disp_expressions, '\0', sizeof (disp_expressions));
1292 memset (im_expressions, '\0', sizeof (im_expressions));
1293 save_stack_p = save_stack;
1295 /* First parse an instruction mnemonic & call i386_operand for the operands.
1296 We assume that the scrubber has arranged it so that line[0] is the valid
1297 start of a (possibly prefixed) mnemonic. */
1299 line = parse_insn (line, mnemonic);
1303 line = parse_operands (line, mnemonic);
1307 /* Now we've parsed the mnemonic into a set of templates, and have the
1308 operands at hand. */
1310 /* All intel opcodes have reversed operands except for "bound" and
1311 "enter". We also don't reverse intersegment "jmp" and "call"
1312 instructions with 2 immediate operands so that the immediate segment
1313 precedes the offset, as it does when in AT&T mode. "enter" and the
1314 intersegment "jmp" and "call" instructions are the only ones that
1315 have two immediate operands. */
1316 if (intel_syntax && i.operands > 1
1317 && (strcmp (mnemonic, "bound") != 0)
1318 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1324 if (i.disp_operands)
1327 /* Next, we find a template that matches the given insn,
1328 making sure the overlap of the given operands types is consistent
1329 with the template operand types. */
1331 if (!match_template ())
1336 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1338 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1339 i.tm.base_opcode ^= FloatR;
1341 /* Zap movzx and movsx suffix. The suffix may have been set from
1342 "word ptr" or "byte ptr" on the source operand, but we'll use
1343 the suffix later to choose the destination register. */
1344 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1348 if (i.tm.opcode_modifier & FWait)
1349 if (!add_prefix (FWAIT_OPCODE))
1352 /* Check string instruction segment overrides. */
1353 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1355 if (!check_string ())
1359 if (!process_suffix ())
1362 /* Make still unresolved immediate matches conform to size of immediate
1363 given in i.suffix. */
1364 if (!finalize_imm ())
1367 if (i.types[0] & Imm1)
1368 i.imm_operands = 0; /* kludge for shift insns. */
1369 if (i.types[0] & ImplicitRegister)
1371 if (i.types[1] & ImplicitRegister)
1373 if (i.types[2] & ImplicitRegister)
1376 if (i.tm.opcode_modifier & ImmExt)
1380 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1382 /* These Intel Precott New Instructions have the fixed
1383 operands with an opcode suffix which is coded in the same
1384 place as an 8-bit immediate field would be. Here we check
1385 those operands and remove them afterwards. */
1388 for (x = 0; x < i.operands; x++)
1389 if (i.op[x].regs->reg_num != x)
1390 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1391 i.op[x].regs->reg_name, x + 1, i.tm.name);
1395 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1396 opcode suffix which is coded in the same place as an 8-bit
1397 immediate field would be. Here we fake an 8-bit immediate
1398 operand from the opcode suffix stored in tm.extension_opcode. */
1400 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1402 exp = &im_expressions[i.imm_operands++];
1403 i.op[i.operands].imms = exp;
1404 i.types[i.operands++] = Imm8;
1405 exp->X_op = O_constant;
1406 exp->X_add_number = i.tm.extension_opcode;
1407 i.tm.extension_opcode = None;
1410 /* For insns with operands there are more diddles to do to the opcode. */
1413 if (!process_operands ())
1416 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1418 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1419 as_warn (_("translating to `%sp'"), i.tm.name);
1422 /* Handle conversion of 'int $3' --> special int3 insn. */
1423 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1425 i.tm.base_opcode = INT3_OPCODE;
1429 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1430 && i.op[0].disps->X_op == O_constant)
1432 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1433 the absolute address given by the constant. Since ix86 jumps and
1434 calls are pc relative, we need to generate a reloc. */
1435 i.op[0].disps->X_add_symbol = &abs_symbol;
1436 i.op[0].disps->X_op = O_symbol;
1439 if ((i.tm.opcode_modifier & Rex64) != 0)
1440 i.rex |= REX_MODE64;
1442 /* For 8 bit registers we need an empty rex prefix. Also if the
1443 instruction already has a prefix, we need to convert old
1444 registers to new ones. */
1446 if (((i.types[0] & Reg8) != 0
1447 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1448 || ((i.types[1] & Reg8) != 0
1449 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1450 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1455 i.rex |= REX_OPCODE;
1456 for (x = 0; x < 2; x++)
1458 /* Look for 8 bit operand that uses old registers. */
1459 if ((i.types[x] & Reg8) != 0
1460 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1462 /* In case it is "hi" register, give up. */
1463 if (i.op[x].regs->reg_num > 3)
1464 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1465 i.op[x].regs->reg_name);
1467 /* Otherwise it is equivalent to the extended register.
1468 Since the encoding doesn't change this is merely
1469 cosmetic cleanup for debug output. */
1471 i.op[x].regs = i.op[x].regs + 8;
1477 add_prefix (REX_OPCODE | i.rex);
1479 /* We are ready to output the insn. */
1484 parse_insn (line, mnemonic)
1489 char *token_start = l;
1492 /* Non-zero if we found a prefix only acceptable with string insns. */
1493 const char *expecting_string_instruction = NULL;
1498 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1501 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1503 as_bad (_("no such instruction: `%s'"), token_start);
1508 if (!is_space_char (*l)
1509 && *l != END_OF_INSN
1510 && *l != PREFIX_SEPARATOR
1513 as_bad (_("invalid character %s in mnemonic"),
1514 output_invalid (*l));
1517 if (token_start == l)
1519 if (*l == PREFIX_SEPARATOR)
1520 as_bad (_("expecting prefix; got nothing"));
1522 as_bad (_("expecting mnemonic; got nothing"));
1526 /* Look up instruction (or prefix) via hash table. */
1527 current_templates = hash_find (op_hash, mnemonic);
1529 if (*l != END_OF_INSN
1530 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1531 && current_templates
1532 && (current_templates->start->opcode_modifier & IsPrefix))
1534 /* If we are in 16-bit mode, do not allow addr16 or data16.
1535 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1536 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1537 && flag_code != CODE_64BIT
1538 && (((current_templates->start->opcode_modifier & Size32) != 0)
1539 ^ (flag_code == CODE_16BIT)))
1541 as_bad (_("redundant %s prefix"),
1542 current_templates->start->name);
1545 /* Add prefix, checking for repeated prefixes. */
1546 switch (add_prefix (current_templates->start->base_opcode))
1551 expecting_string_instruction = current_templates->start->name;
1554 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1561 if (!current_templates)
1563 /* See if we can get a match by trimming off a suffix. */
1566 case WORD_MNEM_SUFFIX:
1567 case BYTE_MNEM_SUFFIX:
1568 case QWORD_MNEM_SUFFIX:
1569 i.suffix = mnem_p[-1];
1571 current_templates = hash_find (op_hash, mnemonic);
1573 case SHORT_MNEM_SUFFIX:
1574 case LONG_MNEM_SUFFIX:
1577 i.suffix = mnem_p[-1];
1579 current_templates = hash_find (op_hash, mnemonic);
1587 if (intel_float_operand (mnemonic))
1588 i.suffix = SHORT_MNEM_SUFFIX;
1590 i.suffix = LONG_MNEM_SUFFIX;
1592 current_templates = hash_find (op_hash, mnemonic);
1596 if (!current_templates)
1598 as_bad (_("no such instruction: `%s'"), token_start);
1603 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1605 /* Check for a branch hint. We allow ",pt" and ",pn" for
1606 predict taken and predict not taken respectively.
1607 I'm not sure that branch hints actually do anything on loop
1608 and jcxz insns (JumpByte) for current Pentium4 chips. They
1609 may work in the future and it doesn't hurt to accept them
1611 if (l[0] == ',' && l[1] == 'p')
1615 if (!add_prefix (DS_PREFIX_OPCODE))
1619 else if (l[2] == 'n')
1621 if (!add_prefix (CS_PREFIX_OPCODE))
1627 /* Any other comma loses. */
1630 as_bad (_("invalid character %s in mnemonic"),
1631 output_invalid (*l));
1635 /* Check if instruction is supported on specified architecture. */
1636 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1637 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1639 as_warn (_("`%s' is not supported on `%s'"),
1640 current_templates->start->name, cpu_arch_name);
1642 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1644 as_warn (_("use .code16 to ensure correct addressing mode"));
1647 /* Check for rep/repne without a string instruction. */
1648 if (expecting_string_instruction
1649 && !(current_templates->start->opcode_modifier & IsString))
1651 as_bad (_("expecting string instruction after `%s'"),
1652 expecting_string_instruction);
1660 parse_operands (l, mnemonic)
1662 const char *mnemonic;
1666 /* 1 if operand is pending after ','. */
1667 unsigned int expecting_operand = 0;
1669 /* Non-zero if operand parens not balanced. */
1670 unsigned int paren_not_balanced;
1672 while (*l != END_OF_INSN)
1674 /* Skip optional white space before operand. */
1675 if (is_space_char (*l))
1677 if (!is_operand_char (*l) && *l != END_OF_INSN)
1679 as_bad (_("invalid character %s before operand %d"),
1680 output_invalid (*l),
1684 token_start = l; /* after white space */
1685 paren_not_balanced = 0;
1686 while (paren_not_balanced || *l != ',')
1688 if (*l == END_OF_INSN)
1690 if (paren_not_balanced)
1693 as_bad (_("unbalanced parenthesis in operand %d."),
1696 as_bad (_("unbalanced brackets in operand %d."),
1701 break; /* we are done */
1703 else if (!is_operand_char (*l) && !is_space_char (*l))
1705 as_bad (_("invalid character %s in operand %d"),
1706 output_invalid (*l),
1713 ++paren_not_balanced;
1715 --paren_not_balanced;
1720 ++paren_not_balanced;
1722 --paren_not_balanced;
1726 if (l != token_start)
1727 { /* Yes, we've read in another operand. */
1728 unsigned int operand_ok;
1729 this_operand = i.operands++;
1730 if (i.operands > MAX_OPERANDS)
1732 as_bad (_("spurious operands; (%d operands/instruction max)"),
1736 /* Now parse operand adding info to 'i' as we go along. */
1737 END_STRING_AND_SAVE (l);
1741 i386_intel_operand (token_start,
1742 intel_float_operand (mnemonic));
1744 operand_ok = i386_operand (token_start);
1746 RESTORE_END_STRING (l);
1752 if (expecting_operand)
1754 expecting_operand_after_comma:
1755 as_bad (_("expecting operand after ','; got nothing"));
1760 as_bad (_("expecting operand before ','; got nothing"));
1765 /* Now *l must be either ',' or END_OF_INSN. */
1768 if (*++l == END_OF_INSN)
1770 /* Just skip it, if it's \n complain. */
1771 goto expecting_operand_after_comma;
1773 expecting_operand = 1;
1782 union i386_op temp_op;
1783 unsigned int temp_type;
1784 enum bfd_reloc_code_real temp_reloc;
1788 if (i.operands == 2)
1793 else if (i.operands == 3)
1798 temp_type = i.types[xchg2];
1799 i.types[xchg2] = i.types[xchg1];
1800 i.types[xchg1] = temp_type;
1801 temp_op = i.op[xchg2];
1802 i.op[xchg2] = i.op[xchg1];
1803 i.op[xchg1] = temp_op;
1804 temp_reloc = i.reloc[xchg2];
1805 i.reloc[xchg2] = i.reloc[xchg1];
1806 i.reloc[xchg1] = temp_reloc;
1808 if (i.mem_operands == 2)
1810 const seg_entry *temp_seg;
1811 temp_seg = i.seg[0];
1812 i.seg[0] = i.seg[1];
1813 i.seg[1] = temp_seg;
1817 /* Try to ensure constant immediates are represented in the smallest
1822 char guess_suffix = 0;
1826 guess_suffix = i.suffix;
1827 else if (i.reg_operands)
1829 /* Figure out a suffix from the last register operand specified.
1830 We can't do this properly yet, ie. excluding InOutPortReg,
1831 but the following works for instructions with immediates.
1832 In any case, we can't set i.suffix yet. */
1833 for (op = i.operands; --op >= 0;)
1834 if (i.types[op] & Reg)
1836 if (i.types[op] & Reg8)
1837 guess_suffix = BYTE_MNEM_SUFFIX;
1838 else if (i.types[op] & Reg16)
1839 guess_suffix = WORD_MNEM_SUFFIX;
1840 else if (i.types[op] & Reg32)
1841 guess_suffix = LONG_MNEM_SUFFIX;
1842 else if (i.types[op] & Reg64)
1843 guess_suffix = QWORD_MNEM_SUFFIX;
1847 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1848 guess_suffix = WORD_MNEM_SUFFIX;
1850 for (op = i.operands; --op >= 0;)
1851 if (i.types[op] & Imm)
1853 switch (i.op[op].imms->X_op)
1856 /* If a suffix is given, this operand may be shortened. */
1857 switch (guess_suffix)
1859 case LONG_MNEM_SUFFIX:
1860 i.types[op] |= Imm32 | Imm64;
1862 case WORD_MNEM_SUFFIX:
1863 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1865 case BYTE_MNEM_SUFFIX:
1866 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1870 /* If this operand is at most 16 bits, convert it
1871 to a signed 16 bit number before trying to see
1872 whether it will fit in an even smaller size.
1873 This allows a 16-bit operand such as $0xffe0 to
1874 be recognised as within Imm8S range. */
1875 if ((i.types[op] & Imm16)
1876 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1878 i.op[op].imms->X_add_number =
1879 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1881 if ((i.types[op] & Imm32)
1882 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1885 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1886 ^ ((offsetT) 1 << 31))
1887 - ((offsetT) 1 << 31));
1889 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1891 /* We must avoid matching of Imm32 templates when 64bit
1892 only immediate is available. */
1893 if (guess_suffix == QWORD_MNEM_SUFFIX)
1894 i.types[op] &= ~Imm32;
1901 /* Symbols and expressions. */
1903 /* Convert symbolic operand to proper sizes for matching. */
1904 switch (guess_suffix)
1906 case QWORD_MNEM_SUFFIX:
1907 i.types[op] = Imm64 | Imm32S;
1909 case LONG_MNEM_SUFFIX:
1910 i.types[op] = Imm32 | Imm64;
1912 case WORD_MNEM_SUFFIX:
1913 i.types[op] = Imm16 | Imm32 | Imm64;
1916 case BYTE_MNEM_SUFFIX:
1917 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1926 /* Try to use the smallest displacement type too. */
1932 for (op = i.operands; --op >= 0;)
1933 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1935 offsetT disp = i.op[op].disps->X_add_number;
1937 if (i.types[op] & Disp16)
1939 /* We know this operand is at most 16 bits, so
1940 convert to a signed 16 bit number before trying
1941 to see whether it will fit in an even smaller
1944 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1946 else if (i.types[op] & Disp32)
1948 /* We know this operand is at most 32 bits, so convert to a
1949 signed 32 bit number before trying to see whether it will
1950 fit in an even smaller size. */
1951 disp &= (((offsetT) 2 << 31) - 1);
1952 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1954 if (flag_code == CODE_64BIT)
1956 if (fits_in_signed_long (disp))
1957 i.types[op] |= Disp32S;
1958 if (fits_in_unsigned_long (disp))
1959 i.types[op] |= Disp32;
1961 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1962 && fits_in_signed_byte (disp))
1963 i.types[op] |= Disp8;
1970 /* Points to template once we've found it. */
1972 unsigned int overlap0, overlap1, overlap2;
1973 unsigned int found_reverse_match;
1976 #define MATCH(overlap, given, template) \
1977 ((overlap & ~JumpAbsolute) \
1978 && (((given) & (BaseIndex | JumpAbsolute)) \
1979 == ((overlap) & (BaseIndex | JumpAbsolute))))
1981 /* If given types r0 and r1 are registers they must be of the same type
1982 unless the expected operand type register overlap is null.
1983 Note that Acc in a template matches every size of reg. */
1984 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1985 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1986 || ((g0) & Reg) == ((g1) & Reg) \
1987 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1992 found_reverse_match = 0;
1993 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1995 : (i.suffix == WORD_MNEM_SUFFIX
1997 : (i.suffix == SHORT_MNEM_SUFFIX
1999 : (i.suffix == LONG_MNEM_SUFFIX
2001 : (i.suffix == QWORD_MNEM_SUFFIX
2003 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2004 ? No_xSuf : 0))))));
2006 for (t = current_templates->start;
2007 t < current_templates->end;
2010 /* Must have right number of operands. */
2011 if (i.operands != t->operands)
2014 /* Check the suffix, except for some instructions in intel mode. */
2015 if ((t->opcode_modifier & suffix_check)
2017 && (t->opcode_modifier & IgnoreSize))
2019 && t->base_opcode == 0xd9
2020 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2021 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2024 /* Do not verify operands when there are none. */
2025 else if (!t->operands)
2027 if (t->cpu_flags & ~cpu_arch_flags)
2029 /* We've found a match; break out of loop. */
2033 overlap0 = i.types[0] & t->operand_types[0];
2034 switch (t->operands)
2037 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2042 overlap1 = i.types[1] & t->operand_types[1];
2043 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2044 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2045 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2046 t->operand_types[0],
2047 overlap1, i.types[1],
2048 t->operand_types[1]))
2050 /* Check if other direction is valid ... */
2051 if ((t->opcode_modifier & (D | FloatD)) == 0)
2054 /* Try reversing direction of operands. */
2055 overlap0 = i.types[0] & t->operand_types[1];
2056 overlap1 = i.types[1] & t->operand_types[0];
2057 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2058 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2059 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2060 t->operand_types[1],
2061 overlap1, i.types[1],
2062 t->operand_types[0]))
2064 /* Does not match either direction. */
2067 /* found_reverse_match holds which of D or FloatDR
2069 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2071 /* Found a forward 2 operand match here. */
2072 else if (t->operands == 3)
2074 /* Here we make use of the fact that there are no
2075 reverse match 3 operand instructions, and all 3
2076 operand instructions only need to be checked for
2077 register consistency between operands 2 and 3. */
2078 overlap2 = i.types[2] & t->operand_types[2];
2079 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2080 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2081 t->operand_types[1],
2082 overlap2, i.types[2],
2083 t->operand_types[2]))
2087 /* Found either forward/reverse 2 or 3 operand match here:
2088 slip through to break. */
2090 if (t->cpu_flags & ~cpu_arch_flags)
2092 found_reverse_match = 0;
2095 /* We've found a match; break out of loop. */
2099 if (t == current_templates->end)
2101 /* We found no match. */
2102 as_bad (_("suffix or operands invalid for `%s'"),
2103 current_templates->start->name);
2107 if (!quiet_warnings)
2110 && ((i.types[0] & JumpAbsolute)
2111 != (t->operand_types[0] & JumpAbsolute)))
2113 as_warn (_("indirect %s without `*'"), t->name);
2116 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2117 == (IsPrefix | IgnoreSize))
2119 /* Warn them that a data or address size prefix doesn't
2120 affect assembly of the next line of code. */
2121 as_warn (_("stand-alone `%s' prefix"), t->name);
2125 /* Copy the template we found. */
2127 if (found_reverse_match)
2129 /* If we found a reverse match we must alter the opcode
2130 direction bit. found_reverse_match holds bits to change
2131 (different for int & float insns). */
2133 i.tm.base_opcode ^= found_reverse_match;
2135 i.tm.operand_types[0] = t->operand_types[1];
2136 i.tm.operand_types[1] = t->operand_types[0];
2145 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2146 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2148 if (i.seg[0] != NULL && i.seg[0] != &es)
2150 as_bad (_("`%s' operand %d must use `%%es' segment"),
2155 /* There's only ever one segment override allowed per instruction.
2156 This instruction possibly has a legal segment override on the
2157 second operand, so copy the segment to where non-string
2158 instructions store it, allowing common code. */
2159 i.seg[0] = i.seg[1];
2161 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2163 if (i.seg[1] != NULL && i.seg[1] != &es)
2165 as_bad (_("`%s' operand %d must use `%%es' segment"),
2177 /* If matched instruction specifies an explicit instruction mnemonic
2179 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2181 if (i.tm.opcode_modifier & Size16)
2182 i.suffix = WORD_MNEM_SUFFIX;
2183 else if (i.tm.opcode_modifier & Size64)
2184 i.suffix = QWORD_MNEM_SUFFIX;
2186 i.suffix = LONG_MNEM_SUFFIX;
2188 else if (i.reg_operands)
2190 /* If there's no instruction mnemonic suffix we try to invent one
2191 based on register operands. */
2194 /* We take i.suffix from the last register operand specified,
2195 Destination register type is more significant than source
2198 for (op = i.operands; --op >= 0;)
2199 if ((i.types[op] & Reg)
2200 && !(i.tm.operand_types[op] & InOutPortReg))
2202 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2203 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2204 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2209 else if (i.suffix == BYTE_MNEM_SUFFIX)
2211 if (!check_byte_reg ())
2214 else if (i.suffix == LONG_MNEM_SUFFIX)
2216 if (!check_long_reg ())
2219 else if (i.suffix == QWORD_MNEM_SUFFIX)
2221 if (!check_qword_reg ())
2224 else if (i.suffix == WORD_MNEM_SUFFIX)
2226 if (!check_word_reg ())
2229 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2230 /* Do nothing if the instruction is going to ignore the prefix. */
2235 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2237 i.suffix = stackop_size;
2240 /* Change the opcode based on the operand size given by i.suffix;
2241 We need not change things for byte insns. */
2243 if (!i.suffix && (i.tm.opcode_modifier & W))
2245 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2249 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2251 /* It's not a byte, select word/dword operation. */
2252 if (i.tm.opcode_modifier & W)
2254 if (i.tm.opcode_modifier & ShortForm)
2255 i.tm.base_opcode |= 8;
2257 i.tm.base_opcode |= 1;
2260 /* Now select between word & dword operations via the operand
2261 size prefix, except for instructions that will ignore this
2263 if (i.suffix != QWORD_MNEM_SUFFIX
2264 && !(i.tm.opcode_modifier & IgnoreSize)
2265 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2266 || (flag_code == CODE_64BIT
2267 && (i.tm.opcode_modifier & JumpByte))))
2269 unsigned int prefix = DATA_PREFIX_OPCODE;
2270 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2271 prefix = ADDR_PREFIX_OPCODE;
2273 if (!add_prefix (prefix))
2277 /* Set mode64 for an operand. */
2278 if (i.suffix == QWORD_MNEM_SUFFIX
2279 && flag_code == CODE_64BIT
2280 && (i.tm.opcode_modifier & NoRex64) == 0)
2281 i.rex |= REX_MODE64;
2283 /* Size floating point instruction. */
2284 if (i.suffix == LONG_MNEM_SUFFIX)
2286 if (i.tm.opcode_modifier & FloatMF)
2287 i.tm.base_opcode ^= 4;
2298 for (op = i.operands; --op >= 0;)
2300 /* If this is an eight bit register, it's OK. If it's the 16 or
2301 32 bit version of an eight bit register, we will just use the
2302 low portion, and that's OK too. */
2303 if (i.types[op] & Reg8)
2306 /* movzx and movsx should not generate this warning. */
2308 && (i.tm.base_opcode == 0xfb7
2309 || i.tm.base_opcode == 0xfb6
2310 || i.tm.base_opcode == 0x63
2311 || i.tm.base_opcode == 0xfbe
2312 || i.tm.base_opcode == 0xfbf))
2315 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2317 /* Check that the template allows eight bit regs. This
2318 kills insns such as `orb $1,%edx', which maybe should be
2320 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2324 /* Prohibit these changes in the 64bit mode, since the
2325 lowering is more complicated. */
2326 if (flag_code == CODE_64BIT
2327 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2329 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2330 i.op[op].regs->reg_name,
2334 #if REGISTER_WARNINGS
2336 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2337 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2338 (i.op[op].regs + (i.types[op] & Reg16
2339 ? REGNAM_AL - REGNAM_AX
2340 : REGNAM_AL - REGNAM_EAX))->reg_name,
2341 i.op[op].regs->reg_name,
2346 /* Any other register is bad. */
2347 if (i.types[op] & (Reg | RegMMX | RegXMM
2349 | Control | Debug | Test
2350 | FloatReg | FloatAcc))
2352 as_bad (_("`%%%s' not allowed with `%s%c'"),
2353 i.op[op].regs->reg_name,
2367 for (op = i.operands; --op >= 0;)
2368 /* Reject eight bit registers, except where the template requires
2369 them. (eg. movzb) */
2370 if ((i.types[op] & Reg8) != 0
2371 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2373 as_bad (_("`%%%s' not allowed with `%s%c'"),
2374 i.op[op].regs->reg_name,
2379 /* Warn if the e prefix on a general reg is missing. */
2380 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2381 && (i.types[op] & Reg16) != 0
2382 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2384 /* Prohibit these changes in the 64bit mode, since the
2385 lowering is more complicated. */
2386 if (flag_code == CODE_64BIT)
2388 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2389 i.op[op].regs->reg_name,
2393 #if REGISTER_WARNINGS
2395 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2396 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2397 i.op[op].regs->reg_name,
2401 /* Warn if the r prefix on a general reg is missing. */
2402 else if ((i.types[op] & Reg64) != 0
2403 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2405 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2406 i.op[op].regs->reg_name,
2418 for (op = i.operands; --op >= 0; )
2419 /* Reject eight bit registers, except where the template requires
2420 them. (eg. movzb) */
2421 if ((i.types[op] & Reg8) != 0
2422 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2424 as_bad (_("`%%%s' not allowed with `%s%c'"),
2425 i.op[op].regs->reg_name,
2430 /* Warn if the e prefix on a general reg is missing. */
2431 else if (((i.types[op] & Reg16) != 0
2432 || (i.types[op] & Reg32) != 0)
2433 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2435 /* Prohibit these changes in the 64bit mode, since the
2436 lowering is more complicated. */
2437 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2438 i.op[op].regs->reg_name,
2449 for (op = i.operands; --op >= 0;)
2450 /* Reject eight bit registers, except where the template requires
2451 them. (eg. movzb) */
2452 if ((i.types[op] & Reg8) != 0
2453 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2455 as_bad (_("`%%%s' not allowed with `%s%c'"),
2456 i.op[op].regs->reg_name,
2461 /* Warn if the e prefix on a general reg is present. */
2462 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2463 && (i.types[op] & Reg32) != 0
2464 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2466 /* Prohibit these changes in the 64bit mode, since the
2467 lowering is more complicated. */
2468 if (flag_code == CODE_64BIT)
2470 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2471 i.op[op].regs->reg_name,
2476 #if REGISTER_WARNINGS
2477 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2478 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2479 i.op[op].regs->reg_name,
2489 unsigned int overlap0, overlap1, overlap2;
2491 overlap0 = i.types[0] & i.tm.operand_types[0];
2492 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2493 && overlap0 != Imm8 && overlap0 != Imm8S
2494 && overlap0 != Imm16 && overlap0 != Imm32S
2495 && overlap0 != Imm32 && overlap0 != Imm64)
2499 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2501 : (i.suffix == WORD_MNEM_SUFFIX
2503 : (i.suffix == QWORD_MNEM_SUFFIX
2507 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2508 || overlap0 == (Imm16 | Imm32)
2509 || overlap0 == (Imm16 | Imm32S))
2511 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2514 if (overlap0 != Imm8 && overlap0 != Imm8S
2515 && overlap0 != Imm16 && overlap0 != Imm32S
2516 && overlap0 != Imm32 && overlap0 != Imm64)
2518 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2522 i.types[0] = overlap0;
2524 overlap1 = i.types[1] & i.tm.operand_types[1];
2525 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2526 && overlap1 != Imm8 && overlap1 != Imm8S
2527 && overlap1 != Imm16 && overlap1 != Imm32S
2528 && overlap1 != Imm32 && overlap1 != Imm64)
2532 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2534 : (i.suffix == WORD_MNEM_SUFFIX
2536 : (i.suffix == QWORD_MNEM_SUFFIX
2540 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2541 || overlap1 == (Imm16 | Imm32)
2542 || overlap1 == (Imm16 | Imm32S))
2544 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2547 if (overlap1 != Imm8 && overlap1 != Imm8S
2548 && overlap1 != Imm16 && overlap1 != Imm32S
2549 && overlap1 != Imm32 && overlap1 != Imm64)
2551 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2555 i.types[1] = overlap1;
2557 overlap2 = i.types[2] & i.tm.operand_types[2];
2558 assert ((overlap2 & Imm) == 0);
2559 i.types[2] = overlap2;
2567 /* Default segment register this instruction will use for memory
2568 accesses. 0 means unknown. This is only for optimizing out
2569 unnecessary segment overrides. */
2570 const seg_entry *default_seg = 0;
2572 /* The imul $imm, %reg instruction is converted into
2573 imul $imm, %reg, %reg, and the clr %reg instruction
2574 is converted into xor %reg, %reg. */
2575 if (i.tm.opcode_modifier & regKludge)
2577 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2578 /* Pretend we saw the extra register operand. */
2579 assert (i.op[first_reg_op + 1].regs == 0);
2580 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2581 i.types[first_reg_op + 1] = i.types[first_reg_op];
2585 if (i.tm.opcode_modifier & ShortForm)
2587 /* The register or float register operand is in operand 0 or 1. */
2588 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2589 /* Register goes in low 3 bits of opcode. */
2590 i.tm.base_opcode |= i.op[op].regs->reg_num;
2591 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2593 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2595 /* Warn about some common errors, but press on regardless.
2596 The first case can be generated by gcc (<= 2.8.1). */
2597 if (i.operands == 2)
2599 /* Reversed arguments on faddp, fsubp, etc. */
2600 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2601 i.op[1].regs->reg_name,
2602 i.op[0].regs->reg_name);
2606 /* Extraneous `l' suffix on fp insn. */
2607 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2608 i.op[0].regs->reg_name);
2612 else if (i.tm.opcode_modifier & Modrm)
2614 /* The opcode is completed (modulo i.tm.extension_opcode which
2615 must be put into the modrm byte). Now, we make the modrm and
2616 index base bytes based on all the info we've collected. */
2618 default_seg = build_modrm_byte ();
2620 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2622 if (i.tm.base_opcode == POP_SEG_SHORT
2623 && i.op[0].regs->reg_num == 1)
2625 as_bad (_("you can't `pop %%cs'"));
2628 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2629 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2632 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2636 else if ((i.tm.opcode_modifier & IsString) != 0)
2638 /* For the string instructions that allow a segment override
2639 on one of their operands, the default segment is ds. */
2643 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2644 as_warn (_("segment override on `lea' is ineffectual"));
2646 /* If a segment was explicitly specified, and the specified segment
2647 is not the default, use an opcode prefix to select it. If we
2648 never figured out what the default segment is, then default_seg
2649 will be zero at this point, and the specified segment prefix will
2651 if ((i.seg[0]) && (i.seg[0] != default_seg))
2653 if (!add_prefix (i.seg[0]->seg_prefix))
2659 static const seg_entry *
2662 const seg_entry *default_seg = 0;
2664 /* i.reg_operands MUST be the number of real register operands;
2665 implicit registers do not count. */
2666 if (i.reg_operands == 2)
2668 unsigned int source, dest;
2669 source = ((i.types[0]
2670 & (Reg | RegMMX | RegXMM
2672 | Control | Debug | Test))
2677 /* One of the register operands will be encoded in the i.tm.reg
2678 field, the other in the combined i.tm.mode and i.tm.regmem
2679 fields. If no form of this instruction supports a memory
2680 destination operand, then we assume the source operand may
2681 sometimes be a memory operand and so we need to store the
2682 destination in the i.rm.reg field. */
2683 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2685 i.rm.reg = i.op[dest].regs->reg_num;
2686 i.rm.regmem = i.op[source].regs->reg_num;
2687 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2689 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2694 i.rm.reg = i.op[source].regs->reg_num;
2695 i.rm.regmem = i.op[dest].regs->reg_num;
2696 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2698 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2703 { /* If it's not 2 reg operands... */
2706 unsigned int fake_zero_displacement = 0;
2707 unsigned int op = ((i.types[0] & AnyMem)
2709 : (i.types[1] & AnyMem) ? 1 : 2);
2713 if (i.base_reg == 0)
2716 if (!i.disp_operands)
2717 fake_zero_displacement = 1;
2718 if (i.index_reg == 0)
2720 /* Operand is just <disp> */
2721 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2722 && (flag_code != CODE_64BIT))
2724 i.rm.regmem = NO_BASE_REGISTER_16;
2725 i.types[op] &= ~Disp;
2726 i.types[op] |= Disp16;
2728 else if (flag_code != CODE_64BIT
2729 || (i.prefix[ADDR_PREFIX] != 0))
2731 i.rm.regmem = NO_BASE_REGISTER;
2732 i.types[op] &= ~Disp;
2733 i.types[op] |= Disp32;
2737 /* 64bit mode overwrites the 32bit absolute
2738 addressing by RIP relative addressing and
2739 absolute addressing is encoded by one of the
2740 redundant SIB forms. */
2741 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2742 i.sib.base = NO_BASE_REGISTER;
2743 i.sib.index = NO_INDEX_REGISTER;
2744 i.types[op] &= ~Disp;
2745 i.types[op] |= Disp32S;
2748 else /* !i.base_reg && i.index_reg */
2750 i.sib.index = i.index_reg->reg_num;
2751 i.sib.base = NO_BASE_REGISTER;
2752 i.sib.scale = i.log2_scale_factor;
2753 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2754 i.types[op] &= ~Disp;
2755 if (flag_code != CODE_64BIT)
2756 i.types[op] |= Disp32; /* Must be 32 bit */
2758 i.types[op] |= Disp32S;
2759 if ((i.index_reg->reg_flags & RegRex) != 0)
2763 /* RIP addressing for 64bit mode. */
2764 else if (i.base_reg->reg_type == BaseIndex)
2766 i.rm.regmem = NO_BASE_REGISTER;
2767 i.types[op] &= ~Disp;
2768 i.types[op] |= Disp32S;
2769 i.flags[op] = Operand_PCrel;
2771 else if (i.base_reg->reg_type & Reg16)
2773 switch (i.base_reg->reg_num)
2776 if (i.index_reg == 0)
2778 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2779 i.rm.regmem = i.index_reg->reg_num - 6;
2783 if (i.index_reg == 0)
2786 if ((i.types[op] & Disp) == 0)
2788 /* fake (%bp) into 0(%bp) */
2789 i.types[op] |= Disp8;
2790 fake_zero_displacement = 1;
2793 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2794 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2796 default: /* (%si) -> 4 or (%di) -> 5 */
2797 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2799 i.rm.mode = mode_from_disp_size (i.types[op]);
2801 else /* i.base_reg and 32/64 bit mode */
2803 if (flag_code == CODE_64BIT
2804 && (i.types[op] & Disp))
2806 if (i.types[op] & Disp8)
2807 i.types[op] = Disp8 | Disp32S;
2809 i.types[op] = Disp32S;
2811 i.rm.regmem = i.base_reg->reg_num;
2812 if ((i.base_reg->reg_flags & RegRex) != 0)
2814 i.sib.base = i.base_reg->reg_num;
2815 /* x86-64 ignores REX prefix bit here to avoid decoder
2817 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2820 if (i.disp_operands == 0)
2822 fake_zero_displacement = 1;
2823 i.types[op] |= Disp8;
2826 else if (i.base_reg->reg_num == ESP_REG_NUM)
2830 i.sib.scale = i.log2_scale_factor;
2831 if (i.index_reg == 0)
2833 /* <disp>(%esp) becomes two byte modrm with no index
2834 register. We've already stored the code for esp
2835 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2836 Any base register besides %esp will not use the
2837 extra modrm byte. */
2838 i.sib.index = NO_INDEX_REGISTER;
2839 #if !SCALE1_WHEN_NO_INDEX
2840 /* Another case where we force the second modrm byte. */
2841 if (i.log2_scale_factor)
2842 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2847 i.sib.index = i.index_reg->reg_num;
2848 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2849 if ((i.index_reg->reg_flags & RegRex) != 0)
2852 i.rm.mode = mode_from_disp_size (i.types[op]);
2855 if (fake_zero_displacement)
2857 /* Fakes a zero displacement assuming that i.types[op]
2858 holds the correct displacement size. */
2861 assert (i.op[op].disps == 0);
2862 exp = &disp_expressions[i.disp_operands++];
2863 i.op[op].disps = exp;
2864 exp->X_op = O_constant;
2865 exp->X_add_number = 0;
2866 exp->X_add_symbol = (symbolS *) 0;
2867 exp->X_op_symbol = (symbolS *) 0;
2871 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2872 (if any) based on i.tm.extension_opcode. Again, we must be
2873 careful to make sure that segment/control/debug/test/MMX
2874 registers are coded into the i.rm.reg field. */
2879 & (Reg | RegMMX | RegXMM
2881 | Control | Debug | Test))
2884 & (Reg | RegMMX | RegXMM
2886 | Control | Debug | Test))
2889 /* If there is an extension opcode to put here, the register
2890 number must be put into the regmem field. */
2891 if (i.tm.extension_opcode != None)
2893 i.rm.regmem = i.op[op].regs->reg_num;
2894 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2899 i.rm.reg = i.op[op].regs->reg_num;
2900 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2904 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2905 must set it to 3 to indicate this is a register operand
2906 in the regmem field. */
2907 if (!i.mem_operands)
2911 /* Fill in i.rm.reg field with extension opcode (if any). */
2912 if (i.tm.extension_opcode != None)
2913 i.rm.reg = i.tm.extension_opcode;
2924 relax_substateT subtype;
2929 if (flag_code == CODE_16BIT)
2933 if (i.prefix[DATA_PREFIX] != 0)
2939 /* Pentium4 branch hints. */
2940 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2941 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2946 if (i.prefix[REX_PREFIX] != 0)
2952 if (i.prefixes != 0 && !intel_syntax)
2953 as_warn (_("skipping prefixes on this instruction"));
2955 /* It's always a symbol; End frag & setup for relax.
2956 Make sure there is enough room in this frag for the largest
2957 instruction we may generate in md_convert_frag. This is 2
2958 bytes for the opcode and room for the prefix and largest
2960 frag_grow (prefix + 2 + 4);
2961 /* Prefix and 1 opcode byte go in fr_fix. */
2962 p = frag_more (prefix + 1);
2963 if (i.prefix[DATA_PREFIX] != 0)
2964 *p++ = DATA_PREFIX_OPCODE;
2965 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2966 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2967 *p++ = i.prefix[SEG_PREFIX];
2968 if (i.prefix[REX_PREFIX] != 0)
2969 *p++ = i.prefix[REX_PREFIX];
2970 *p = i.tm.base_opcode;
2972 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2973 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2974 else if ((cpu_arch_flags & Cpu386) != 0)
2975 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2977 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2980 sym = i.op[0].disps->X_add_symbol;
2981 off = i.op[0].disps->X_add_number;
2983 if (i.op[0].disps->X_op != O_constant
2984 && i.op[0].disps->X_op != O_symbol)
2986 /* Handle complex expressions. */
2987 sym = make_expr_symbol (i.op[0].disps);
2991 /* 1 possible extra opcode + 4 byte displacement go in var part.
2992 Pass reloc in fr_var. */
2993 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3003 if (i.tm.opcode_modifier & JumpByte)
3005 /* This is a loop or jecxz type instruction. */
3007 if (i.prefix[ADDR_PREFIX] != 0)
3009 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3012 /* Pentium4 branch hints. */
3013 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3014 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3016 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3025 if (flag_code == CODE_16BIT)
3028 if (i.prefix[DATA_PREFIX] != 0)
3030 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3040 if (i.prefix[REX_PREFIX] != 0)
3042 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3046 if (i.prefixes != 0 && !intel_syntax)
3047 as_warn (_("skipping prefixes on this instruction"));
3049 p = frag_more (1 + size);
3050 *p++ = i.tm.base_opcode;
3052 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3053 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3055 /* All jumps handled here are signed, but don't use a signed limit
3056 check for 32 and 16 bit jumps as we want to allow wrap around at
3057 4G and 64k respectively. */
3059 fixP->fx_signed = 1;
3063 output_interseg_jump ()
3071 if (flag_code == CODE_16BIT)
3075 if (i.prefix[DATA_PREFIX] != 0)
3081 if (i.prefix[REX_PREFIX] != 0)
3091 if (i.prefixes != 0 && !intel_syntax)
3092 as_warn (_("skipping prefixes on this instruction"));
3094 /* 1 opcode; 2 segment; offset */
3095 p = frag_more (prefix + 1 + 2 + size);
3097 if (i.prefix[DATA_PREFIX] != 0)
3098 *p++ = DATA_PREFIX_OPCODE;
3100 if (i.prefix[REX_PREFIX] != 0)
3101 *p++ = i.prefix[REX_PREFIX];
3103 *p++ = i.tm.base_opcode;
3104 if (i.op[1].imms->X_op == O_constant)
3106 offsetT n = i.op[1].imms->X_add_number;
3109 && !fits_in_unsigned_word (n)
3110 && !fits_in_signed_word (n))
3112 as_bad (_("16-bit jump out of range"));
3115 md_number_to_chars (p, n, size);
3118 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3119 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3120 if (i.op[0].imms->X_op != O_constant)
3121 as_bad (_("can't handle non absolute segment in `%s'"),
3123 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3130 fragS *insn_start_frag;
3131 offsetT insn_start_off;
3133 /* Tie dwarf2 debug info to the address at the start of the insn.
3134 We can't do this after the insn has been output as the current
3135 frag may have been closed off. eg. by frag_var. */
3136 dwarf2_emit_insn (0);
3138 insn_start_frag = frag_now;
3139 insn_start_off = frag_now_fix ();
3142 if (i.tm.opcode_modifier & Jump)
3144 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3146 else if (i.tm.opcode_modifier & JumpInterSegment)
3147 output_interseg_jump ();
3150 /* Output normal instructions here. */
3154 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3155 byte for the SSE instructions to specify a prefix they require. */
3156 if (i.tm.base_opcode & 0xff0000)
3157 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3159 /* The prefix bytes. */
3161 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3167 md_number_to_chars (p, (valueT) *q, 1);
3171 /* Now the opcode; be careful about word order here! */
3172 if (fits_in_unsigned_byte (i.tm.base_opcode))
3174 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3179 /* Put out high byte first: can't use md_number_to_chars! */
3180 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3181 *p = i.tm.base_opcode & 0xff;
3184 /* Now the modrm byte and sib byte (if present). */
3185 if (i.tm.opcode_modifier & Modrm)
3188 md_number_to_chars (p,
3189 (valueT) (i.rm.regmem << 0
3193 /* If i.rm.regmem == ESP (4)
3194 && i.rm.mode != (Register mode)
3196 ==> need second modrm byte. */
3197 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3199 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3202 md_number_to_chars (p,
3203 (valueT) (i.sib.base << 0
3205 | i.sib.scale << 6),
3210 if (i.disp_operands)
3211 output_disp (insn_start_frag, insn_start_off);
3214 output_imm (insn_start_frag, insn_start_off);
3222 #endif /* DEBUG386 */
3226 output_disp (insn_start_frag, insn_start_off)
3227 fragS *insn_start_frag;
3228 offsetT insn_start_off;
3233 for (n = 0; n < i.operands; n++)
3235 if (i.types[n] & Disp)
3237 if (i.op[n].disps->X_op == O_constant)
3243 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3246 if (i.types[n] & Disp8)
3248 if (i.types[n] & Disp64)
3251 val = offset_in_range (i.op[n].disps->X_add_number,
3253 p = frag_more (size);
3254 md_number_to_chars (p, val, size);
3258 enum bfd_reloc_code_real reloc_type;
3261 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3263 /* The PC relative address is computed relative
3264 to the instruction boundary, so in case immediate
3265 fields follows, we need to adjust the value. */
3266 if (pcrel && i.imm_operands)
3271 for (n1 = 0; n1 < i.operands; n1++)
3272 if (i.types[n1] & Imm)
3274 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3277 if (i.types[n1] & (Imm8 | Imm8S))
3279 if (i.types[n1] & Imm64)
3284 /* We should find the immediate. */
3285 if (n1 == i.operands)
3287 i.op[n].disps->X_add_number -= imm_size;
3290 if (i.types[n] & Disp32S)
3293 if (i.types[n] & (Disp16 | Disp64))
3296 if (i.types[n] & Disp64)
3300 p = frag_more (size);
3301 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3302 if (reloc_type == BFD_RELOC_32
3304 && GOT_symbol == i.op[n].disps->X_add_symbol
3305 && (i.op[n].disps->X_op == O_symbol
3306 || (i.op[n].disps->X_op == O_add
3307 && ((symbol_get_value_expression
3308 (i.op[n].disps->X_op_symbol)->X_op)
3313 if (insn_start_frag == frag_now)
3314 add = (p - frag_now->fr_literal) - insn_start_off;
3319 add = insn_start_frag->fr_fix - insn_start_off;
3320 for (fr = insn_start_frag->fr_next;
3321 fr && fr != frag_now; fr = fr->fr_next)
3323 add += p - frag_now->fr_literal;
3326 /* We don't support dynamic linking on x86-64 yet. */
3327 if (flag_code == CODE_64BIT)
3329 reloc_type = BFD_RELOC_386_GOTPC;
3330 i.op[n].disps->X_add_number += add;
3332 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3333 i.op[n].disps, pcrel, reloc_type);
3340 output_imm (insn_start_frag, insn_start_off)
3341 fragS *insn_start_frag;
3342 offsetT insn_start_off;
3347 for (n = 0; n < i.operands; n++)
3349 if (i.types[n] & Imm)
3351 if (i.op[n].imms->X_op == O_constant)
3357 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3360 if (i.types[n] & (Imm8 | Imm8S))
3362 else if (i.types[n] & Imm64)
3365 val = offset_in_range (i.op[n].imms->X_add_number,
3367 p = frag_more (size);
3368 md_number_to_chars (p, val, size);
3372 /* Not absolute_section.
3373 Need a 32-bit fixup (don't support 8bit
3374 non-absolute imms). Try to support other
3376 enum bfd_reloc_code_real reloc_type;
3380 if ((i.types[n] & (Imm32S))
3381 && i.suffix == QWORD_MNEM_SUFFIX)
3383 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3386 if (i.types[n] & (Imm8 | Imm8S))
3388 if (i.types[n] & Imm64)
3392 p = frag_more (size);
3393 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3395 /* This is tough to explain. We end up with this one if we
3396 * have operands that look like
3397 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3398 * obtain the absolute address of the GOT, and it is strongly
3399 * preferable from a performance point of view to avoid using
3400 * a runtime relocation for this. The actual sequence of
3401 * instructions often look something like:
3406 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3408 * The call and pop essentially return the absolute address
3409 * of the label .L66 and store it in %ebx. The linker itself
3410 * will ultimately change the first operand of the addl so
3411 * that %ebx points to the GOT, but to keep things simple, the
3412 * .o file must have this operand set so that it generates not
3413 * the absolute address of .L66, but the absolute address of
3414 * itself. This allows the linker itself simply treat a GOTPC
3415 * relocation as asking for a pcrel offset to the GOT to be
3416 * added in, and the addend of the relocation is stored in the
3417 * operand field for the instruction itself.
3419 * Our job here is to fix the operand so that it would add
3420 * the correct offset so that %ebx would point to itself. The
3421 * thing that is tricky is that .-.L66 will point to the
3422 * beginning of the instruction, so we need to further modify
3423 * the operand so that it will point to itself. There are
3424 * other cases where you have something like:
3426 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3428 * and here no correction would be required. Internally in
3429 * the assembler we treat operands of this form as not being
3430 * pcrel since the '.' is explicitly mentioned, and I wonder
3431 * whether it would simplify matters to do it this way. Who
3432 * knows. In earlier versions of the PIC patches, the
3433 * pcrel_adjust field was used to store the correction, but
3434 * since the expression is not pcrel, I felt it would be
3435 * confusing to do it this way. */
3437 if (reloc_type == BFD_RELOC_32
3439 && GOT_symbol == i.op[n].imms->X_add_symbol
3440 && (i.op[n].imms->X_op == O_symbol
3441 || (i.op[n].imms->X_op == O_add
3442 && ((symbol_get_value_expression
3443 (i.op[n].imms->X_op_symbol)->X_op)
3448 if (insn_start_frag == frag_now)
3449 add = (p - frag_now->fr_literal) - insn_start_off;
3454 add = insn_start_frag->fr_fix - insn_start_off;
3455 for (fr = insn_start_frag->fr_next;
3456 fr && fr != frag_now; fr = fr->fr_next)
3458 add += p - frag_now->fr_literal;
3461 /* We don't support dynamic linking on x86-64 yet. */
3462 if (flag_code == CODE_64BIT)
3464 reloc_type = BFD_RELOC_386_GOTPC;
3465 i.op[n].imms->X_add_number += add;
3467 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3468 i.op[n].imms, 0, reloc_type);
3475 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
3477 /* Parse operands of the form
3478 <symbol>@GOTOFF+<nnn>
3479 and similar .plt or .got references.
3481 If we find one, set up the correct relocation in RELOC and copy the
3482 input string, minus the `@GOTOFF' into a malloc'd buffer for
3483 parsing by the calling routine. Return this buffer, and if ADJUST
3484 is non-null set it to the length of the string we removed from the
3485 input line. Otherwise return NULL. */
3487 lex_got (reloc, adjust)
3488 enum bfd_reloc_code_real *reloc;
3491 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3492 static const struct {
3494 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3496 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3497 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3498 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3499 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
3500 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3501 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3502 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3503 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
3504 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3505 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
3506 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3507 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
3508 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3513 for (cp = input_line_pointer; *cp != '@'; cp++)
3514 if (is_end_of_line[(unsigned char) *cp])
3517 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3521 len = strlen (gotrel[j].str);
3522 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3524 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3527 char *tmpbuf, *past_reloc;
3529 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3533 if (GOT_symbol == NULL)
3534 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3536 /* Replace the relocation token with ' ', so that
3537 errors like foo@GOTOFF1 will be detected. */
3539 /* The length of the first part of our input line. */
3540 first = cp - input_line_pointer;
3542 /* The second part goes from after the reloc token until
3543 (and including) an end_of_line char. Don't use strlen
3544 here as the end_of_line char may not be a NUL. */
3545 past_reloc = cp + 1 + len;
3546 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3548 second = cp - past_reloc;
3550 /* Allocate and copy string. The trailing NUL shouldn't
3551 be necessary, but be safe. */
3552 tmpbuf = xmalloc (first + second + 2);
3553 memcpy (tmpbuf, input_line_pointer, first);
3554 tmpbuf[first] = ' ';
3555 memcpy (tmpbuf + first + 1, past_reloc, second);
3556 tmpbuf[first + second + 1] = '\0';
3560 as_bad (_("@%s reloc is not supported in %s bit mode"),
3561 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3566 /* Might be a symbol version string. Don't as_bad here. */
3570 /* x86_cons_fix_new is called via the expression parsing code when a
3571 reloc is needed. We use this hook to get the correct .got reloc. */
3572 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3575 x86_cons_fix_new (frag, off, len, exp)
3581 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
3582 got_reloc = NO_RELOC;
3583 fix_new_exp (frag, off, len, exp, 0, r);
3587 x86_cons (exp, size)
3593 /* Handle @GOTOFF and the like in an expression. */
3595 char *gotfree_input_line;
3598 save = input_line_pointer;
3599 gotfree_input_line = lex_got (&got_reloc, &adjust);
3600 if (gotfree_input_line)
3601 input_line_pointer = gotfree_input_line;
3605 if (gotfree_input_line)
3607 /* expression () has merrily parsed up to the end of line,
3608 or a comma - in the wrong buffer. Transfer how far
3609 input_line_pointer has moved to the right buffer. */
3610 input_line_pointer = (save
3611 + (input_line_pointer - gotfree_input_line)
3613 free (gotfree_input_line);
3621 static int i386_immediate PARAMS ((char *));
3624 i386_immediate (imm_start)
3627 char *save_input_line_pointer;
3629 char *gotfree_input_line;
3634 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3636 as_bad (_("only 1 or 2 immediate operands are allowed"));
3640 exp = &im_expressions[i.imm_operands++];
3641 i.op[this_operand].imms = exp;
3643 if (is_space_char (*imm_start))
3646 save_input_line_pointer = input_line_pointer;
3647 input_line_pointer = imm_start;
3650 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3651 if (gotfree_input_line)
3652 input_line_pointer = gotfree_input_line;
3655 exp_seg = expression (exp);
3658 if (*input_line_pointer)
3659 as_bad (_("junk `%s' after expression"), input_line_pointer);
3661 input_line_pointer = save_input_line_pointer;
3663 if (gotfree_input_line)
3664 free (gotfree_input_line);
3667 if (exp->X_op == O_absent || exp->X_op == O_big)
3669 /* Missing or bad expr becomes absolute 0. */
3670 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3672 exp->X_op = O_constant;
3673 exp->X_add_number = 0;
3674 exp->X_add_symbol = (symbolS *) 0;
3675 exp->X_op_symbol = (symbolS *) 0;
3677 else if (exp->X_op == O_constant)
3679 /* Size it properly later. */
3680 i.types[this_operand] |= Imm64;
3681 /* If BFD64, sign extend val. */
3682 if (!use_rela_relocations)
3683 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3684 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3686 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3687 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3688 && exp_seg != absolute_section
3689 && exp_seg != text_section
3690 && exp_seg != data_section
3691 && exp_seg != bss_section
3692 && exp_seg != undefined_section
3693 && !bfd_is_com_section (exp_seg))
3695 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3701 /* This is an address. The size of the address will be
3702 determined later, depending on destination register,
3703 suffix, or the default for the section. */
3704 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3710 static char *i386_scale PARAMS ((char *));
3717 char *save = input_line_pointer;
3719 input_line_pointer = scale;
3720 val = get_absolute_expression ();
3726 i.log2_scale_factor = 0;
3729 i.log2_scale_factor = 1;
3732 i.log2_scale_factor = 2;
3735 i.log2_scale_factor = 3;
3738 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3740 input_line_pointer = save;
3743 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3745 as_warn (_("scale factor of %d without an index register"),
3746 1 << i.log2_scale_factor);
3747 #if SCALE1_WHEN_NO_INDEX
3748 i.log2_scale_factor = 0;
3751 scale = input_line_pointer;
3752 input_line_pointer = save;
3756 static int i386_displacement PARAMS ((char *, char *));
3759 i386_displacement (disp_start, disp_end)
3765 char *save_input_line_pointer;
3767 char *gotfree_input_line;
3769 int bigdisp = Disp32;
3771 if (flag_code == CODE_64BIT)
3773 if (i.prefix[ADDR_PREFIX] == 0)
3776 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3778 i.types[this_operand] |= bigdisp;
3780 exp = &disp_expressions[i.disp_operands];
3781 i.op[this_operand].disps = exp;
3783 save_input_line_pointer = input_line_pointer;
3784 input_line_pointer = disp_start;
3785 END_STRING_AND_SAVE (disp_end);
3787 #ifndef GCC_ASM_O_HACK
3788 #define GCC_ASM_O_HACK 0
3791 END_STRING_AND_SAVE (disp_end + 1);
3792 if ((i.types[this_operand] & BaseIndex) != 0
3793 && displacement_string_end[-1] == '+')
3795 /* This hack is to avoid a warning when using the "o"
3796 constraint within gcc asm statements.
3799 #define _set_tssldt_desc(n,addr,limit,type) \
3800 __asm__ __volatile__ ( \
3802 "movw %w1,2+%0\n\t" \
3804 "movb %b1,4+%0\n\t" \
3805 "movb %4,5+%0\n\t" \
3806 "movb $0,6+%0\n\t" \
3807 "movb %h1,7+%0\n\t" \
3809 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3811 This works great except that the output assembler ends
3812 up looking a bit weird if it turns out that there is
3813 no offset. You end up producing code that looks like:
3826 So here we provide the missing zero. */
3828 *displacement_string_end = '0';
3832 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3833 if (gotfree_input_line)
3834 input_line_pointer = gotfree_input_line;
3837 exp_seg = expression (exp);
3840 if (*input_line_pointer)
3841 as_bad (_("junk `%s' after expression"), input_line_pointer);
3843 RESTORE_END_STRING (disp_end + 1);
3845 RESTORE_END_STRING (disp_end);
3846 input_line_pointer = save_input_line_pointer;
3848 if (gotfree_input_line)
3849 free (gotfree_input_line);
3852 /* We do this to make sure that the section symbol is in
3853 the symbol table. We will ultimately change the relocation
3854 to be relative to the beginning of the section. */
3855 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3856 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3858 if (exp->X_op != O_symbol)
3860 as_bad (_("bad expression used with @%s"),
3861 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3867 if (S_IS_LOCAL (exp->X_add_symbol)
3868 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3869 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3870 exp->X_op = O_subtract;
3871 exp->X_op_symbol = GOT_symbol;
3872 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3873 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3875 i.reloc[this_operand] = BFD_RELOC_32;
3878 if (exp->X_op == O_absent || exp->X_op == O_big)
3880 /* Missing or bad expr becomes absolute 0. */
3881 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3883 exp->X_op = O_constant;
3884 exp->X_add_number = 0;
3885 exp->X_add_symbol = (symbolS *) 0;
3886 exp->X_op_symbol = (symbolS *) 0;
3889 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3890 if (exp->X_op != O_constant
3891 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3892 && exp_seg != absolute_section
3893 && exp_seg != text_section
3894 && exp_seg != data_section
3895 && exp_seg != bss_section
3896 && exp_seg != undefined_section
3897 && !bfd_is_com_section (exp_seg))
3899 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3903 else if (flag_code == CODE_64BIT)
3904 i.types[this_operand] |= Disp32S | Disp32;
3908 static int i386_index_check PARAMS ((const char *));
3910 /* Make sure the memory operand we've been dealt is valid.
3911 Return 1 on success, 0 on a failure. */
3914 i386_index_check (operand_string)
3915 const char *operand_string;
3918 #if INFER_ADDR_PREFIX
3924 if (flag_code == CODE_64BIT)
3926 if (i.prefix[ADDR_PREFIX] == 0)
3930 && ((i.base_reg->reg_type & Reg64) == 0)
3931 && (i.base_reg->reg_type != BaseIndex
3934 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3935 != (Reg64 | BaseIndex))))
3942 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3944 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3945 != (Reg32 | BaseIndex))))
3951 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3955 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3956 != (Reg16 | BaseIndex)))
3958 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3959 != (Reg16 | BaseIndex))
3961 && i.base_reg->reg_num < 6
3962 && i.index_reg->reg_num >= 6
3963 && i.log2_scale_factor == 0))))
3970 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3972 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3973 != (Reg32 | BaseIndex))))
3979 #if INFER_ADDR_PREFIX
3980 if (flag_code != CODE_64BIT
3981 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3983 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3985 /* Change the size of any displacement too. At most one of
3986 Disp16 or Disp32 is set.
3987 FIXME. There doesn't seem to be any real need for separate
3988 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3989 Removing them would probably clean up the code quite a lot. */
3990 if (i.types[this_operand] & (Disp16 | Disp32))
3991 i.types[this_operand] ^= (Disp16 | Disp32);
3996 as_bad (_("`%s' is not a valid base/index expression"),
4000 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4002 flag_code_names[flag_code]);
4008 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4012 i386_operand (operand_string)
4013 char *operand_string;
4017 char *op_string = operand_string;
4019 if (is_space_char (*op_string))
4022 /* We check for an absolute prefix (differentiating,
4023 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4024 if (*op_string == ABSOLUTE_PREFIX)
4027 if (is_space_char (*op_string))
4029 i.types[this_operand] |= JumpAbsolute;
4032 /* Check if operand is a register. */
4033 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4034 && (r = parse_register (op_string, &end_op)) != NULL)
4036 /* Check for a segment override by searching for ':' after a
4037 segment register. */
4039 if (is_space_char (*op_string))
4041 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4046 i.seg[i.mem_operands] = &es;
4049 i.seg[i.mem_operands] = &cs;
4052 i.seg[i.mem_operands] = &ss;
4055 i.seg[i.mem_operands] = &ds;
4058 i.seg[i.mem_operands] = &fs;
4061 i.seg[i.mem_operands] = &gs;
4065 /* Skip the ':' and whitespace. */
4067 if (is_space_char (*op_string))
4070 if (!is_digit_char (*op_string)
4071 && !is_identifier_char (*op_string)
4072 && *op_string != '('
4073 && *op_string != ABSOLUTE_PREFIX)
4075 as_bad (_("bad memory operand `%s'"), op_string);
4078 /* Handle case of %es:*foo. */
4079 if (*op_string == ABSOLUTE_PREFIX)
4082 if (is_space_char (*op_string))
4084 i.types[this_operand] |= JumpAbsolute;
4086 goto do_memory_reference;
4090 as_bad (_("junk `%s' after register"), op_string);
4093 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4094 i.op[this_operand].regs = r;
4097 else if (*op_string == REGISTER_PREFIX)
4099 as_bad (_("bad register name `%s'"), op_string);
4102 else if (*op_string == IMMEDIATE_PREFIX)
4105 if (i.types[this_operand] & JumpAbsolute)
4107 as_bad (_("immediate operand illegal with absolute jump"));
4110 if (!i386_immediate (op_string))
4113 else if (is_digit_char (*op_string)
4114 || is_identifier_char (*op_string)
4115 || *op_string == '(')
4117 /* This is a memory reference of some sort. */
4120 /* Start and end of displacement string expression (if found). */
4121 char *displacement_string_start;
4122 char *displacement_string_end;
4124 do_memory_reference:
4125 if ((i.mem_operands == 1
4126 && (current_templates->start->opcode_modifier & IsString) == 0)
4127 || i.mem_operands == 2)
4129 as_bad (_("too many memory references for `%s'"),
4130 current_templates->start->name);
4134 /* Check for base index form. We detect the base index form by
4135 looking for an ')' at the end of the operand, searching
4136 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4138 base_string = op_string + strlen (op_string);
4141 if (is_space_char (*base_string))
4144 /* If we only have a displacement, set-up for it to be parsed later. */
4145 displacement_string_start = op_string;
4146 displacement_string_end = base_string + 1;
4148 if (*base_string == ')')
4151 unsigned int parens_balanced = 1;
4152 /* We've already checked that the number of left & right ()'s are
4153 equal, so this loop will not be infinite. */
4157 if (*base_string == ')')
4159 if (*base_string == '(')
4162 while (parens_balanced);
4164 temp_string = base_string;
4166 /* Skip past '(' and whitespace. */
4168 if (is_space_char (*base_string))
4171 if (*base_string == ','
4172 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4173 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4175 displacement_string_end = temp_string;
4177 i.types[this_operand] |= BaseIndex;
4181 base_string = end_op;
4182 if (is_space_char (*base_string))
4186 /* There may be an index reg or scale factor here. */
4187 if (*base_string == ',')
4190 if (is_space_char (*base_string))
4193 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4194 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4196 base_string = end_op;
4197 if (is_space_char (*base_string))
4199 if (*base_string == ',')
4202 if (is_space_char (*base_string))
4205 else if (*base_string != ')')
4207 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4212 else if (*base_string == REGISTER_PREFIX)
4214 as_bad (_("bad register name `%s'"), base_string);
4218 /* Check for scale factor. */
4219 if (*base_string != ')')
4221 char *end_scale = i386_scale (base_string);
4226 base_string = end_scale;
4227 if (is_space_char (*base_string))
4229 if (*base_string != ')')
4231 as_bad (_("expecting `)' after scale factor in `%s'"),
4236 else if (!i.index_reg)
4238 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4243 else if (*base_string != ')')
4245 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4250 else if (*base_string == REGISTER_PREFIX)
4252 as_bad (_("bad register name `%s'"), base_string);
4257 /* If there's an expression beginning the operand, parse it,
4258 assuming displacement_string_start and
4259 displacement_string_end are meaningful. */
4260 if (displacement_string_start != displacement_string_end)
4262 if (!i386_displacement (displacement_string_start,
4263 displacement_string_end))
4267 /* Special case for (%dx) while doing input/output op. */
4269 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4271 && i.log2_scale_factor == 0
4272 && i.seg[i.mem_operands] == 0
4273 && (i.types[this_operand] & Disp) == 0)
4275 i.types[this_operand] = InOutPortReg;
4279 if (i386_index_check (operand_string) == 0)
4285 /* It's not a memory operand; argh! */
4286 as_bad (_("invalid char %s beginning operand %d `%s'"),
4287 output_invalid (*op_string),
4292 return 1; /* Normal return. */
4295 /* md_estimate_size_before_relax()
4297 Called just before relax() for rs_machine_dependent frags. The x86
4298 assembler uses these frags to handle variable size jump
4301 Any symbol that is now undefined will not become defined.
4302 Return the correct fr_subtype in the frag.
4303 Return the initial "guess for variable size of frag" to caller.
4304 The guess is actually the growth beyond the fixed part. Whatever
4305 we do to grow the fixed or variable part contributes to our
4309 md_estimate_size_before_relax (fragP, segment)
4313 /* We've already got fragP->fr_subtype right; all we have to do is
4314 check for un-relaxable symbols. On an ELF system, we can't relax
4315 an externally visible symbol, because it may be overridden by a
4317 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4318 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4319 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4320 && (S_IS_EXTERNAL (fragP->fr_symbol)
4321 || S_IS_WEAK (fragP->fr_symbol)))
4325 /* Symbol is undefined in this segment, or we need to keep a
4326 reloc so that weak symbols can be overridden. */
4327 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4328 enum bfd_reloc_code_real reloc_type;
4329 unsigned char *opcode;
4332 if (fragP->fr_var != NO_RELOC)
4333 reloc_type = fragP->fr_var;
4335 reloc_type = BFD_RELOC_16_PCREL;
4337 reloc_type = BFD_RELOC_32_PCREL;
4339 old_fr_fix = fragP->fr_fix;
4340 opcode = (unsigned char *) fragP->fr_opcode;
4342 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4345 /* Make jmp (0xeb) a (d)word displacement jump. */
4347 fragP->fr_fix += size;
4348 fix_new (fragP, old_fr_fix, size,
4350 fragP->fr_offset, 1,
4356 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4358 /* Negate the condition, and branch past an
4359 unconditional jump. */
4362 /* Insert an unconditional jump. */
4364 /* We added two extra opcode bytes, and have a two byte
4366 fragP->fr_fix += 2 + 2;
4367 fix_new (fragP, old_fr_fix + 2, 2,
4369 fragP->fr_offset, 1,
4376 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4381 fixP = fix_new (fragP, old_fr_fix, 1,
4383 fragP->fr_offset, 1,
4385 fixP->fx_signed = 1;
4389 /* This changes the byte-displacement jump 0x7N
4390 to the (d)word-displacement jump 0x0f,0x8N. */
4391 opcode[1] = opcode[0] + 0x10;
4392 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4393 /* We've added an opcode byte. */
4394 fragP->fr_fix += 1 + size;
4395 fix_new (fragP, old_fr_fix + 1, size,
4397 fragP->fr_offset, 1,
4402 BAD_CASE (fragP->fr_subtype);
4406 return fragP->fr_fix - old_fr_fix;
4409 /* Guess size depending on current relax state. Initially the relax
4410 state will correspond to a short jump and we return 1, because
4411 the variable part of the frag (the branch offset) is one byte
4412 long. However, we can relax a section more than once and in that
4413 case we must either set fr_subtype back to the unrelaxed state,
4414 or return the value for the appropriate branch. */
4415 return md_relax_table[fragP->fr_subtype].rlx_length;
4418 /* Called after relax() is finished.
4420 In: Address of frag.
4421 fr_type == rs_machine_dependent.
4422 fr_subtype is what the address relaxed to.
4424 Out: Any fixSs and constants are set up.
4425 Caller will turn frag into a ".space 0". */
4428 md_convert_frag (abfd, sec, fragP)
4429 bfd *abfd ATTRIBUTE_UNUSED;
4430 segT sec ATTRIBUTE_UNUSED;
4433 unsigned char *opcode;
4434 unsigned char *where_to_put_displacement = NULL;
4435 offsetT target_address;
4436 offsetT opcode_address;
4437 unsigned int extension = 0;
4438 offsetT displacement_from_opcode_start;
4440 opcode = (unsigned char *) fragP->fr_opcode;
4442 /* Address we want to reach in file space. */
4443 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4445 /* Address opcode resides at in file space. */
4446 opcode_address = fragP->fr_address + fragP->fr_fix;
4448 /* Displacement from opcode start to fill into instruction. */
4449 displacement_from_opcode_start = target_address - opcode_address;
4451 if ((fragP->fr_subtype & BIG) == 0)
4453 /* Don't have to change opcode. */
4454 extension = 1; /* 1 opcode + 1 displacement */
4455 where_to_put_displacement = &opcode[1];
4459 if (no_cond_jump_promotion
4460 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4461 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4463 switch (fragP->fr_subtype)
4465 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4466 extension = 4; /* 1 opcode + 4 displacement */
4468 where_to_put_displacement = &opcode[1];
4471 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4472 extension = 2; /* 1 opcode + 2 displacement */
4474 where_to_put_displacement = &opcode[1];
4477 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4478 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4479 extension = 5; /* 2 opcode + 4 displacement */
4480 opcode[1] = opcode[0] + 0x10;
4481 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4482 where_to_put_displacement = &opcode[2];
4485 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4486 extension = 3; /* 2 opcode + 2 displacement */
4487 opcode[1] = opcode[0] + 0x10;
4488 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4489 where_to_put_displacement = &opcode[2];
4492 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4497 where_to_put_displacement = &opcode[3];
4501 BAD_CASE (fragP->fr_subtype);
4506 /* Now put displacement after opcode. */
4507 md_number_to_chars ((char *) where_to_put_displacement,
4508 (valueT) (displacement_from_opcode_start - extension),
4509 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4510 fragP->fr_fix += extension;
4513 /* Size of byte displacement jmp. */
4514 int md_short_jump_size = 2;
4516 /* Size of dword displacement jmp. */
4517 int md_long_jump_size = 5;
4519 /* Size of relocation record. */
4520 const int md_reloc_size = 8;
4523 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4525 addressT from_addr, to_addr;
4526 fragS *frag ATTRIBUTE_UNUSED;
4527 symbolS *to_symbol ATTRIBUTE_UNUSED;
4531 offset = to_addr - (from_addr + 2);
4532 /* Opcode for byte-disp jump. */
4533 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4534 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4538 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4540 addressT from_addr, to_addr;
4541 fragS *frag ATTRIBUTE_UNUSED;
4542 symbolS *to_symbol ATTRIBUTE_UNUSED;
4546 offset = to_addr - (from_addr + 5);
4547 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4548 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4551 /* Apply a fixup (fixS) to segment data, once it has been determined
4552 by our caller that we have all the info we need to fix it up.
4554 On the 386, immediates, displacements, and data pointers are all in
4555 the same (little-endian) format, so we don't need to care about which
4559 md_apply_fix3 (fixP, valP, seg)
4560 /* The fix we're to put in. */
4562 /* Pointer to the value of the bits. */
4564 /* Segment fix is from. */
4565 segT seg ATTRIBUTE_UNUSED;
4567 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4568 valueT value = *valP;
4570 #if !defined (TE_Mach)
4573 switch (fixP->fx_r_type)
4579 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4582 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4585 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4590 if (fixP->fx_addsy != NULL
4591 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4592 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4593 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4594 && !use_rela_relocations)
4596 /* This is a hack. There should be a better way to handle this.
4597 This covers for the fact that bfd_install_relocation will
4598 subtract the current location (for partial_inplace, PC relative
4599 relocations); see more below. */
4601 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4603 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4606 value += fixP->fx_where + fixP->fx_frag->fr_address;
4608 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4609 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4611 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
4614 || (symbol_section_p (fixP->fx_addsy)
4615 && sym_seg != absolute_section))
4616 && !generic_force_reloc (fixP))
4618 /* Yes, we add the values in twice. This is because
4619 bfd_install_relocation subtracts them out again. I think
4620 bfd_install_relocation is broken, but I don't dare change
4622 value += fixP->fx_where + fixP->fx_frag->fr_address;
4626 #if defined (OBJ_COFF) && defined (TE_PE)
4627 /* For some reason, the PE format does not store a section
4628 address offset for a PC relative symbol. */
4629 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4630 value += md_pcrel_from (fixP);
4634 /* Fix a few things - the dynamic linker expects certain values here,
4635 and we must not disappoint it. */
4636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4637 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4639 switch (fixP->fx_r_type)
4641 case BFD_RELOC_386_PLT32:
4642 case BFD_RELOC_X86_64_PLT32:
4643 /* Make the jump instruction point to the address of the operand. At
4644 runtime we merely add the offset to the actual PLT entry. */
4648 case BFD_RELOC_386_TLS_GD:
4649 case BFD_RELOC_386_TLS_LDM:
4650 case BFD_RELOC_386_TLS_IE_32:
4651 case BFD_RELOC_386_TLS_IE:
4652 case BFD_RELOC_386_TLS_GOTIE:
4653 case BFD_RELOC_X86_64_TLSGD:
4654 case BFD_RELOC_X86_64_TLSLD:
4655 case BFD_RELOC_X86_64_GOTTPOFF:
4656 value = 0; /* Fully resolved at runtime. No addend. */
4658 case BFD_RELOC_386_TLS_LE:
4659 case BFD_RELOC_386_TLS_LDO_32:
4660 case BFD_RELOC_386_TLS_LE_32:
4661 case BFD_RELOC_X86_64_DTPOFF32:
4662 case BFD_RELOC_X86_64_TPOFF32:
4663 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4666 case BFD_RELOC_386_GOT32:
4667 case BFD_RELOC_X86_64_GOT32:
4668 value = 0; /* Fully resolved at runtime. No addend. */
4671 case BFD_RELOC_VTABLE_INHERIT:
4672 case BFD_RELOC_VTABLE_ENTRY:
4679 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4681 #endif /* !defined (TE_Mach) */
4683 /* Are we finished with this relocation now? */
4684 if (fixP->fx_addsy == NULL)
4686 else if (use_rela_relocations)
4688 fixP->fx_no_overflow = 1;
4689 /* Remember value for tc_gen_reloc. */
4690 fixP->fx_addnumber = value;
4694 md_number_to_chars (p, value, fixP->fx_size);
4697 #define MAX_LITTLENUMS 6
4699 /* Turn the string pointed to by litP into a floating point constant
4700 of type TYPE, and emit the appropriate bytes. The number of
4701 LITTLENUMS emitted is stored in *SIZEP. An error message is
4702 returned, or NULL on OK. */
4705 md_atof (type, litP, sizeP)
4711 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4712 LITTLENUM_TYPE *wordP;
4734 return _("Bad call to md_atof ()");
4736 t = atof_ieee (input_line_pointer, type, words);
4738 input_line_pointer = t;
4740 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4741 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4742 the bigendian 386. */
4743 for (wordP = words + prec - 1; prec--;)
4745 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4746 litP += sizeof (LITTLENUM_TYPE);
4751 char output_invalid_buf[8];
4758 sprintf (output_invalid_buf, "'%c'", c);
4760 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4761 return output_invalid_buf;
4764 /* REG_STRING starts *before* REGISTER_PREFIX. */
4766 static const reg_entry *
4767 parse_register (reg_string, end_op)
4771 char *s = reg_string;
4773 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4776 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4777 if (*s == REGISTER_PREFIX)
4780 if (is_space_char (*s))
4784 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4786 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4787 return (const reg_entry *) NULL;
4791 /* For naked regs, make sure that we are not dealing with an identifier.
4792 This prevents confusing an identifier like `eax_var' with register
4794 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4795 return (const reg_entry *) NULL;
4799 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4801 /* Handle floating point regs, allowing spaces in the (i) part. */
4802 if (r == i386_regtab /* %st is first entry of table */)
4804 if (is_space_char (*s))
4809 if (is_space_char (*s))
4811 if (*s >= '0' && *s <= '7')
4813 r = &i386_float_regtab[*s - '0'];
4815 if (is_space_char (*s))
4823 /* We have "%st(" then garbage. */
4824 return (const reg_entry *) NULL;
4829 && (r->reg_flags & (RegRex64 | RegRex)) != 0
4830 && flag_code != CODE_64BIT)
4832 return (const reg_entry *) NULL;
4838 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4839 const char *md_shortopts = "kVQ:sqn";
4841 const char *md_shortopts = "qn";
4844 struct option md_longopts[] = {
4845 #define OPTION_32 (OPTION_MD_BASE + 0)
4846 {"32", no_argument, NULL, OPTION_32},
4847 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4848 #define OPTION_64 (OPTION_MD_BASE + 1)
4849 {"64", no_argument, NULL, OPTION_64},
4851 {NULL, no_argument, NULL, 0}
4853 size_t md_longopts_size = sizeof (md_longopts);
4856 md_parse_option (c, arg)
4858 char *arg ATTRIBUTE_UNUSED;
4863 optimize_align_code = 0;
4870 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4871 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4872 should be emitted or not. FIXME: Not implemented. */
4876 /* -V: SVR4 argument to print version ID. */
4878 print_version_id ();
4881 /* -k: Ignore for FreeBSD compatibility. */
4886 /* -s: On i386 Solaris, this tells the native assembler to use
4887 .stab instead of .stab.excl. We always use .stab anyhow. */
4892 const char **list, **l;
4894 list = bfd_target_list ();
4895 for (l = list; *l != NULL; l++)
4896 if (strcmp (*l, "elf64-x86-64") == 0)
4898 default_arch = "x86_64";
4902 as_fatal (_("No compiled in support for x86_64"));
4909 default_arch = "i386";
4919 md_show_usage (stream)
4922 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4923 fprintf (stream, _("\
4925 -V print assembler version number\n\
4927 -n Do not optimize code alignment\n\
4928 -q quieten some warnings\n\
4931 fprintf (stream, _("\
4932 -n Do not optimize code alignment\n\
4933 -q quieten some warnings\n"));
4937 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4938 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4940 /* Pick the target format to use. */
4943 i386_target_format ()
4945 if (!strcmp (default_arch, "x86_64"))
4946 set_code_flag (CODE_64BIT);
4947 else if (!strcmp (default_arch, "i386"))
4948 set_code_flag (CODE_32BIT);
4950 as_fatal (_("Unknown architecture"));
4951 switch (OUTPUT_FLAVOR)
4953 #ifdef OBJ_MAYBE_AOUT
4954 case bfd_target_aout_flavour:
4955 return AOUT_TARGET_FORMAT;
4957 #ifdef OBJ_MAYBE_COFF
4958 case bfd_target_coff_flavour:
4961 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4962 case bfd_target_elf_flavour:
4964 if (flag_code == CODE_64BIT)
4965 use_rela_relocations = 1;
4966 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
4975 #endif /* OBJ_MAYBE_ more than one */
4977 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4978 void i386_elf_emit_arch_note ()
4980 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4981 && cpu_arch_name != NULL)
4984 asection *seg = now_seg;
4985 subsegT subseg = now_subseg;
4986 Elf_Internal_Note i_note;
4987 Elf_External_Note e_note;
4988 asection *note_secp;
4991 /* Create the .note section. */
4992 note_secp = subseg_new (".note", 0);
4993 bfd_set_section_flags (stdoutput,
4995 SEC_HAS_CONTENTS | SEC_READONLY);
4997 /* Process the arch string. */
4998 len = strlen (cpu_arch_name);
5000 i_note.namesz = len + 1;
5002 i_note.type = NT_ARCH;
5003 p = frag_more (sizeof (e_note.namesz));
5004 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5005 p = frag_more (sizeof (e_note.descsz));
5006 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5007 p = frag_more (sizeof (e_note.type));
5008 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5009 p = frag_more (len + 1);
5010 strcpy (p, cpu_arch_name);
5012 frag_align (2, 0, 0);
5014 subseg_set (seg, subseg);
5020 md_undefined_symbol (name)
5023 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5024 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5025 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5026 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5030 if (symbol_find (name))
5031 as_bad (_("GOT already in symbol table"));
5032 GOT_symbol = symbol_new (name, undefined_section,
5033 (valueT) 0, &zero_address_frag);
5040 /* Round up a section size to the appropriate boundary. */
5043 md_section_align (segment, size)
5044 segT segment ATTRIBUTE_UNUSED;
5047 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5048 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5050 /* For a.out, force the section size to be aligned. If we don't do
5051 this, BFD will align it for us, but it will not write out the
5052 final bytes of the section. This may be a bug in BFD, but it is
5053 easier to fix it here since that is how the other a.out targets
5057 align = bfd_get_section_alignment (stdoutput, segment);
5058 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5065 /* On the i386, PC-relative offsets are relative to the start of the
5066 next instruction. That is, the address of the offset, plus its
5067 size, since the offset is always the last part of the insn. */
5070 md_pcrel_from (fixP)
5073 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5080 int ignore ATTRIBUTE_UNUSED;
5084 temp = get_absolute_expression ();
5085 subseg_set (bss_section, (subsegT) temp);
5086 demand_empty_rest_of_line ();
5092 i386_validate_fix (fixp)
5095 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5097 /* GOTOFF relocation are nonsense in 64bit mode. */
5098 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5100 if (flag_code != CODE_64BIT)
5102 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5106 if (flag_code == CODE_64BIT)
5108 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5115 tc_gen_reloc (section, fixp)
5116 asection *section ATTRIBUTE_UNUSED;
5120 bfd_reloc_code_real_type code;
5122 switch (fixp->fx_r_type)
5124 case BFD_RELOC_X86_64_PLT32:
5125 case BFD_RELOC_X86_64_GOT32:
5126 case BFD_RELOC_X86_64_GOTPCREL:
5127 case BFD_RELOC_386_PLT32:
5128 case BFD_RELOC_386_GOT32:
5129 case BFD_RELOC_386_GOTOFF:
5130 case BFD_RELOC_386_GOTPC:
5131 case BFD_RELOC_386_TLS_GD:
5132 case BFD_RELOC_386_TLS_LDM:
5133 case BFD_RELOC_386_TLS_LDO_32:
5134 case BFD_RELOC_386_TLS_IE_32:
5135 case BFD_RELOC_386_TLS_IE:
5136 case BFD_RELOC_386_TLS_GOTIE:
5137 case BFD_RELOC_386_TLS_LE_32:
5138 case BFD_RELOC_386_TLS_LE:
5139 case BFD_RELOC_X86_64_32S:
5140 case BFD_RELOC_X86_64_TLSGD:
5141 case BFD_RELOC_X86_64_TLSLD:
5142 case BFD_RELOC_X86_64_DTPOFF32:
5143 case BFD_RELOC_X86_64_GOTTPOFF:
5144 case BFD_RELOC_X86_64_TPOFF32:
5146 case BFD_RELOC_VTABLE_ENTRY:
5147 case BFD_RELOC_VTABLE_INHERIT:
5148 code = fixp->fx_r_type;
5153 switch (fixp->fx_size)
5156 as_bad_where (fixp->fx_file, fixp->fx_line,
5157 _("can not do %d byte pc-relative relocation"),
5159 code = BFD_RELOC_32_PCREL;
5161 case 1: code = BFD_RELOC_8_PCREL; break;
5162 case 2: code = BFD_RELOC_16_PCREL; break;
5163 case 4: code = BFD_RELOC_32_PCREL; break;
5168 switch (fixp->fx_size)
5171 as_bad_where (fixp->fx_file, fixp->fx_line,
5172 _("can not do %d byte relocation"),
5174 code = BFD_RELOC_32;
5176 case 1: code = BFD_RELOC_8; break;
5177 case 2: code = BFD_RELOC_16; break;
5178 case 4: code = BFD_RELOC_32; break;
5180 case 8: code = BFD_RELOC_64; break;
5187 if (code == BFD_RELOC_32
5189 && fixp->fx_addsy == GOT_symbol)
5191 /* We don't support GOTPC on 64bit targets. */
5192 if (flag_code == CODE_64BIT)
5194 code = BFD_RELOC_386_GOTPC;
5197 rel = (arelent *) xmalloc (sizeof (arelent));
5198 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5199 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5201 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5202 if (!use_rela_relocations)
5204 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5205 vtable entry to be used in the relocation's section offset. */
5206 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5207 rel->address = fixp->fx_offset;
5211 /* Use the rela in 64bit mode. */
5214 if (!fixp->fx_pcrel)
5215 rel->addend = fixp->fx_offset;
5219 case BFD_RELOC_X86_64_PLT32:
5220 case BFD_RELOC_X86_64_GOT32:
5221 case BFD_RELOC_X86_64_GOTPCREL:
5222 case BFD_RELOC_X86_64_TLSGD:
5223 case BFD_RELOC_X86_64_TLSLD:
5224 case BFD_RELOC_X86_64_GOTTPOFF:
5225 rel->addend = fixp->fx_offset - fixp->fx_size;
5228 rel->addend = (section->vma
5230 + fixp->fx_addnumber
5231 + md_pcrel_from (fixp));
5236 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5237 if (rel->howto == NULL)
5239 as_bad_where (fixp->fx_file, fixp->fx_line,
5240 _("cannot represent relocation type %s"),
5241 bfd_get_reloc_code_name (code));
5242 /* Set howto to a garbage value so that we can keep going. */
5243 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5244 assert (rel->howto != NULL);
5251 /* Parse operands using Intel syntax. This implements a recursive descent
5252 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5255 FIXME: We do not recognize the full operand grammar defined in the MASM
5256 documentation. In particular, all the structure/union and
5257 high-level macro operands are missing.
5259 Uppercase words are terminals, lower case words are non-terminals.
5260 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5261 bars '|' denote choices. Most grammar productions are implemented in
5262 functions called 'intel_<production>'.
5264 Initial production is 'expr'.
5270 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5272 constant digits [[ radixOverride ]]
5274 dataType BYTE | WORD | DWORD | QWORD | XWORD
5307 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5308 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5310 hexdigit a | b | c | d | e | f
5311 | A | B | C | D | E | F
5321 register specialRegister
5325 segmentRegister CS | DS | ES | FS | GS | SS
5327 specialRegister CR0 | CR2 | CR3
5328 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5329 | TR3 | TR4 | TR5 | TR6 | TR7
5331 We simplify the grammar in obvious places (e.g., register parsing is
5332 done by calling parse_register) and eliminate immediate left recursion
5333 to implement a recursive-descent parser.
5373 /* Parsing structure for the intel syntax parser. Used to implement the
5374 semantic actions for the operand grammar. */
5375 struct intel_parser_s
5377 char *op_string; /* The string being parsed. */
5378 int got_a_float; /* Whether the operand is a float. */
5379 int op_modifier; /* Operand modifier. */
5380 int is_mem; /* 1 if operand is memory reference. */
5381 const reg_entry *reg; /* Last register reference found. */
5382 char *disp; /* Displacement string being built. */
5385 static struct intel_parser_s intel_parser;
5387 /* Token structure for parsing intel syntax. */
5390 int code; /* Token code. */
5391 const reg_entry *reg; /* Register entry for register tokens. */
5392 char *str; /* String representation. */
5395 static struct intel_token cur_token, prev_token;
5397 /* Token codes for the intel parser. Since T_SHORT is already used
5398 by COFF, undefine it first to prevent a warning. */
5413 /* Prototypes for intel parser functions. */
5414 static int intel_match_token PARAMS ((int code));
5415 static void intel_get_token PARAMS ((void));
5416 static void intel_putback_token PARAMS ((void));
5417 static int intel_expr PARAMS ((void));
5418 static int intel_e05 PARAMS ((void));
5419 static int intel_e05_1 PARAMS ((void));
5420 static int intel_e06 PARAMS ((void));
5421 static int intel_e06_1 PARAMS ((void));
5422 static int intel_e09 PARAMS ((void));
5423 static int intel_e09_1 PARAMS ((void));
5424 static int intel_e10 PARAMS ((void));
5425 static int intel_e10_1 PARAMS ((void));
5426 static int intel_e11 PARAMS ((void));
5429 i386_intel_operand (operand_string, got_a_float)
5430 char *operand_string;
5436 /* Initialize token holders. */
5437 cur_token.code = prev_token.code = T_NIL;
5438 cur_token.reg = prev_token.reg = NULL;
5439 cur_token.str = prev_token.str = NULL;
5441 /* Initialize parser structure. */
5442 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5445 strcpy (intel_parser.op_string, operand_string);
5446 intel_parser.got_a_float = got_a_float;
5447 intel_parser.op_modifier = -1;
5448 intel_parser.is_mem = 0;
5449 intel_parser.reg = NULL;
5450 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5451 if (intel_parser.disp == NULL)
5453 intel_parser.disp[0] = '\0';
5455 /* Read the first token and start the parser. */
5457 ret = intel_expr ();
5461 /* If we found a memory reference, hand it over to i386_displacement
5462 to fill in the rest of the operand fields. */
5463 if (intel_parser.is_mem)
5465 if ((i.mem_operands == 1
5466 && (current_templates->start->opcode_modifier & IsString) == 0)
5467 || i.mem_operands == 2)
5469 as_bad (_("too many memory references for '%s'"),
5470 current_templates->start->name);
5475 char *s = intel_parser.disp;
5478 /* Add the displacement expression. */
5480 ret = i386_displacement (s, s + strlen (s));
5482 ret = i386_index_check (operand_string);
5486 /* Constant and OFFSET expressions are handled by i386_immediate. */
5487 else if (intel_parser.op_modifier == OFFSET_FLAT
5488 || intel_parser.reg == NULL)
5489 ret = i386_immediate (intel_parser.disp);
5493 free (intel_parser.disp);
5503 /* expr SHORT e05 */
5504 if (cur_token.code == T_SHORT)
5506 intel_parser.op_modifier = SHORT;
5507 intel_match_token (T_SHORT);
5509 return (intel_e05 ());
5514 return intel_e05 ();
5524 return (intel_e06 () && intel_e05_1 ());
5530 /* e05' addOp e06 e05' */
5531 if (cur_token.code == '+' || cur_token.code == '-')
5533 strcat (intel_parser.disp, cur_token.str);
5534 intel_match_token (cur_token.code);
5536 return (intel_e06 () && intel_e05_1 ());
5551 return (intel_e09 () && intel_e06_1 ());
5557 /* e06' mulOp e09 e06' */
5558 if (cur_token.code == '*' || cur_token.code == '/')
5560 strcat (intel_parser.disp, cur_token.str);
5561 intel_match_token (cur_token.code);
5563 return (intel_e09 () && intel_e06_1 ());
5571 /* e09 OFFSET e10 e09'
5580 /* e09 OFFSET e10 e09' */
5581 if (cur_token.code == T_OFFSET)
5583 intel_parser.is_mem = 0;
5584 intel_parser.op_modifier = OFFSET_FLAT;
5585 intel_match_token (T_OFFSET);
5587 return (intel_e10 () && intel_e09_1 ());
5592 return (intel_e10 () && intel_e09_1 ());
5598 /* e09' PTR e10 e09' */
5599 if (cur_token.code == T_PTR)
5601 if (prev_token.code == T_BYTE)
5602 i.suffix = BYTE_MNEM_SUFFIX;
5604 else if (prev_token.code == T_WORD)
5606 if (intel_parser.got_a_float == 2) /* "fi..." */
5607 i.suffix = SHORT_MNEM_SUFFIX;
5609 i.suffix = WORD_MNEM_SUFFIX;
5612 else if (prev_token.code == T_DWORD)
5614 if (intel_parser.got_a_float == 1) /* "f..." */
5615 i.suffix = SHORT_MNEM_SUFFIX;
5617 i.suffix = LONG_MNEM_SUFFIX;
5620 else if (prev_token.code == T_QWORD)
5622 if (intel_parser.got_a_float == 1) /* "f..." */
5623 i.suffix = LONG_MNEM_SUFFIX;
5625 i.suffix = QWORD_MNEM_SUFFIX;
5628 else if (prev_token.code == T_XWORD)
5629 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5633 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5637 intel_match_token (T_PTR);
5639 return (intel_e10 () && intel_e09_1 ());
5642 /* e09 : e10 e09' */
5643 else if (cur_token.code == ':')
5645 /* Mark as a memory operand only if it's not already known to be an
5646 offset expression. */
5647 if (intel_parser.op_modifier != OFFSET_FLAT)
5648 intel_parser.is_mem = 1;
5650 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5665 return (intel_e11 () && intel_e10_1 ());
5671 /* e10' [ expr ] e10' */
5672 if (cur_token.code == '[')
5674 intel_match_token ('[');
5676 /* Mark as a memory operand only if it's not already known to be an
5677 offset expression. If it's an offset expression, we need to keep
5679 if (intel_parser.op_modifier != OFFSET_FLAT)
5680 intel_parser.is_mem = 1;
5682 strcat (intel_parser.disp, "[");
5684 /* Add a '+' to the displacement string if necessary. */
5685 if (*intel_parser.disp != '\0'
5686 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5687 strcat (intel_parser.disp, "+");
5689 if (intel_expr () && intel_match_token (']'))
5691 /* Preserve brackets when the operand is an offset expression. */
5692 if (intel_parser.op_modifier == OFFSET_FLAT)
5693 strcat (intel_parser.disp, "]");
5695 return intel_e10_1 ();
5722 if (cur_token.code == '(')
5724 intel_match_token ('(');
5725 strcat (intel_parser.disp, "(");
5727 if (intel_expr () && intel_match_token (')'))
5729 strcat (intel_parser.disp, ")");
5737 else if (cur_token.code == '[')
5739 intel_match_token ('[');
5741 /* Mark as a memory operand only if it's not already known to be an
5742 offset expression. If it's an offset expression, we need to keep
5744 if (intel_parser.op_modifier != OFFSET_FLAT)
5745 intel_parser.is_mem = 1;
5747 strcat (intel_parser.disp, "[");
5749 /* Operands for jump/call inside brackets denote absolute addresses. */
5750 if (current_templates->start->opcode_modifier & Jump
5751 || current_templates->start->opcode_modifier & JumpDword
5752 || current_templates->start->opcode_modifier & JumpByte
5753 || current_templates->start->opcode_modifier & JumpInterSegment)
5754 i.types[this_operand] |= JumpAbsolute;
5756 /* Add a '+' to the displacement string if necessary. */
5757 if (*intel_parser.disp != '\0'
5758 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5759 strcat (intel_parser.disp, "+");
5761 if (intel_expr () && intel_match_token (']'))
5763 /* Preserve brackets when the operand is an offset expression. */
5764 if (intel_parser.op_modifier == OFFSET_FLAT)
5765 strcat (intel_parser.disp, "]");
5778 else if (cur_token.code == T_BYTE
5779 || cur_token.code == T_WORD
5780 || cur_token.code == T_DWORD
5781 || cur_token.code == T_QWORD
5782 || cur_token.code == T_XWORD)
5784 intel_match_token (cur_token.code);
5791 else if (cur_token.code == '$' || cur_token.code == '.')
5793 strcat (intel_parser.disp, cur_token.str);
5794 intel_match_token (cur_token.code);
5796 /* Mark as a memory operand only if it's not already known to be an
5797 offset expression. */
5798 if (intel_parser.op_modifier != OFFSET_FLAT)
5799 intel_parser.is_mem = 1;
5805 else if (cur_token.code == T_REG)
5807 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5809 intel_match_token (T_REG);
5811 /* Check for segment change. */
5812 if (cur_token.code == ':')
5814 if (reg->reg_type & (SReg2 | SReg3))
5816 switch (reg->reg_num)
5819 i.seg[i.mem_operands] = &es;
5822 i.seg[i.mem_operands] = &cs;
5825 i.seg[i.mem_operands] = &ss;
5828 i.seg[i.mem_operands] = &ds;
5831 i.seg[i.mem_operands] = &fs;
5834 i.seg[i.mem_operands] = &gs;
5840 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5845 /* Not a segment register. Check for register scaling. */
5846 else if (cur_token.code == '*')
5848 if (!intel_parser.is_mem)
5850 as_bad (_("Register scaling only allowed in memory operands."));
5854 /* What follows must be a valid scale. */
5855 if (intel_match_token ('*')
5856 && strchr ("01248", *cur_token.str))
5859 i.types[this_operand] |= BaseIndex;
5861 /* Set the scale after setting the register (otherwise,
5862 i386_scale will complain) */
5863 i386_scale (cur_token.str);
5864 intel_match_token (T_CONST);
5868 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5874 /* No scaling. If this is a memory operand, the register is either a
5875 base register (first occurrence) or an index register (second
5877 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5879 if (i.base_reg && i.index_reg)
5881 as_bad (_("Too many register references in memory operand.\n"));
5885 if (i.base_reg == NULL)
5890 i.types[this_operand] |= BaseIndex;
5893 /* Offset modifier. Add the register to the displacement string to be
5894 parsed as an immediate expression after we're done. */
5895 else if (intel_parser.op_modifier == OFFSET_FLAT)
5896 strcat (intel_parser.disp, reg->reg_name);
5898 /* It's neither base nor index nor offset. */
5901 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5902 i.op[this_operand].regs = reg;
5906 /* Since registers are not part of the displacement string (except
5907 when we're parsing offset operands), we may need to remove any
5908 preceding '+' from the displacement string. */
5909 if (*intel_parser.disp != '\0'
5910 && intel_parser.op_modifier != OFFSET_FLAT)
5912 char *s = intel_parser.disp;
5913 s += strlen (s) - 1;
5922 else if (cur_token.code == T_ID)
5924 /* Add the identifier to the displacement string. */
5925 strcat (intel_parser.disp, cur_token.str);
5926 intel_match_token (T_ID);
5928 /* The identifier represents a memory reference only if it's not
5929 preceded by an offset modifier. */
5930 if (intel_parser.op_modifier != OFFSET_FLAT)
5931 intel_parser.is_mem = 1;
5937 else if (cur_token.code == T_CONST
5938 || cur_token.code == '-'
5939 || cur_token.code == '+')
5943 /* Allow constants that start with `+' or `-'. */
5944 if (cur_token.code == '-' || cur_token.code == '+')
5946 strcat (intel_parser.disp, cur_token.str);
5947 intel_match_token (cur_token.code);
5948 if (cur_token.code != T_CONST)
5950 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5956 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5957 if (save_str == NULL)
5959 strcpy (save_str, cur_token.str);
5961 /* Get the next token to check for register scaling. */
5962 intel_match_token (cur_token.code);
5964 /* Check if this constant is a scaling factor for an index register. */
5965 if (cur_token.code == '*')
5967 if (intel_match_token ('*') && cur_token.code == T_REG)
5969 if (!intel_parser.is_mem)
5971 as_bad (_("Register scaling only allowed in memory operands."));
5975 /* The constant is followed by `* reg', so it must be
5977 if (strchr ("01248", *save_str))
5979 i.index_reg = cur_token.reg;
5980 i.types[this_operand] |= BaseIndex;
5982 /* Set the scale after setting the register (otherwise,
5983 i386_scale will complain) */
5984 i386_scale (save_str);
5985 intel_match_token (T_REG);
5987 /* Since registers are not part of the displacement
5988 string, we may need to remove any preceding '+' from
5989 the displacement string. */
5990 if (*intel_parser.disp != '\0')
5992 char *s = intel_parser.disp;
5993 s += strlen (s) - 1;
6006 /* The constant was not used for register scaling. Since we have
6007 already consumed the token following `*' we now need to put it
6008 back in the stream. */
6010 intel_putback_token ();
6013 /* Add the constant to the displacement string. */
6014 strcat (intel_parser.disp, save_str);
6020 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6024 /* Match the given token against cur_token. If they match, read the next
6025 token from the operand string. */
6027 intel_match_token (code)
6030 if (cur_token.code == code)
6037 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6042 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6047 const reg_entry *reg;
6048 struct intel_token new_token;
6050 new_token.code = T_NIL;
6051 new_token.reg = NULL;
6052 new_token.str = NULL;
6054 /* Free the memory allocated to the previous token and move
6055 cur_token to prev_token. */
6057 free (prev_token.str);
6059 prev_token = cur_token;
6061 /* Skip whitespace. */
6062 while (is_space_char (*intel_parser.op_string))
6063 intel_parser.op_string++;
6065 /* Return an empty token if we find nothing else on the line. */
6066 if (*intel_parser.op_string == '\0')
6068 cur_token = new_token;
6072 /* The new token cannot be larger than the remainder of the operand
6074 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6075 if (new_token.str == NULL)
6077 new_token.str[0] = '\0';
6079 if (strchr ("0123456789", *intel_parser.op_string))
6081 char *p = new_token.str;
6082 char *q = intel_parser.op_string;
6083 new_token.code = T_CONST;
6085 /* Allow any kind of identifier char to encompass floating point and
6086 hexadecimal numbers. */
6087 while (is_identifier_char (*q))
6091 /* Recognize special symbol names [0-9][bf]. */
6092 if (strlen (intel_parser.op_string) == 2
6093 && (intel_parser.op_string[1] == 'b'
6094 || intel_parser.op_string[1] == 'f'))
6095 new_token.code = T_ID;
6098 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6100 new_token.code = *intel_parser.op_string;
6101 new_token.str[0] = *intel_parser.op_string;
6102 new_token.str[1] = '\0';
6105 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6106 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6108 new_token.code = T_REG;
6109 new_token.reg = reg;
6111 if (*intel_parser.op_string == REGISTER_PREFIX)
6113 new_token.str[0] = REGISTER_PREFIX;
6114 new_token.str[1] = '\0';
6117 strcat (new_token.str, reg->reg_name);
6120 else if (is_identifier_char (*intel_parser.op_string))
6122 char *p = new_token.str;
6123 char *q = intel_parser.op_string;
6125 /* A '.' or '$' followed by an identifier char is an identifier.
6126 Otherwise, it's operator '.' followed by an expression. */
6127 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6129 new_token.code = *q;
6130 new_token.str[0] = *q;
6131 new_token.str[1] = '\0';
6135 while (is_identifier_char (*q) || *q == '@')
6139 if (strcasecmp (new_token.str, "BYTE") == 0)
6140 new_token.code = T_BYTE;
6142 else if (strcasecmp (new_token.str, "WORD") == 0)
6143 new_token.code = T_WORD;
6145 else if (strcasecmp (new_token.str, "DWORD") == 0)
6146 new_token.code = T_DWORD;
6148 else if (strcasecmp (new_token.str, "QWORD") == 0)
6149 new_token.code = T_QWORD;
6151 else if (strcasecmp (new_token.str, "XWORD") == 0)
6152 new_token.code = T_XWORD;
6154 else if (strcasecmp (new_token.str, "PTR") == 0)
6155 new_token.code = T_PTR;
6157 else if (strcasecmp (new_token.str, "SHORT") == 0)
6158 new_token.code = T_SHORT;
6160 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6162 new_token.code = T_OFFSET;
6164 /* ??? This is not mentioned in the MASM grammar but gcc
6165 makes use of it with -mintel-syntax. OFFSET may be
6166 followed by FLAT: */
6167 if (strncasecmp (q, " FLAT:", 6) == 0)
6168 strcat (new_token.str, " FLAT:");
6171 /* ??? This is not mentioned in the MASM grammar. */
6172 else if (strcasecmp (new_token.str, "FLAT") == 0)
6173 new_token.code = T_OFFSET;
6176 new_token.code = T_ID;
6181 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6183 intel_parser.op_string += strlen (new_token.str);
6184 cur_token = new_token;
6187 /* Put cur_token back into the token stream and make cur_token point to
6190 intel_putback_token ()
6192 intel_parser.op_string -= strlen (cur_token.str);
6193 free (cur_token.str);
6194 cur_token = prev_token;
6196 /* Forget prev_token. */
6197 prev_token.code = T_NIL;
6198 prev_token.reg = NULL;
6199 prev_token.str = NULL;
6203 tc_x86_regname_to_dw2regnum (const char *regname)
6205 unsigned int regnum;
6206 unsigned int regnames_count;
6207 char *regnames_32[] =
6209 "eax", "ecx", "edx", "ebx",
6210 "esp", "ebp", "esi", "edi",
6213 char *regnames_64[] =
6215 "rax", "rbx", "rcx", "rdx",
6216 "rdi", "rsi", "rbp", "rsp",
6217 "r8", "r9", "r10", "r11",
6218 "r12", "r13", "r14", "r15",
6223 if (flag_code == CODE_64BIT)
6225 regnames = regnames_64;
6226 regnames_count = ARRAY_SIZE (regnames_64);
6230 regnames = regnames_32;
6231 regnames_count = ARRAY_SIZE (regnames_32);
6234 for (regnum = 0; regnum < regnames_count; regnum++)
6235 if (strcmp (regname, regnames[regnum]) == 0)
6242 tc_x86_frame_initial_instructions (void)
6244 static unsigned int sp_regno;
6247 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6250 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6251 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);