1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
30 #include "safe-ctype.h"
32 #include "dwarf2dbg.h"
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
52 #define RELOC_ENUM enum bfd_reloc_code_real
54 #define RELOC_ENUM int
58 #define DEFAULT_ARCH "i386"
63 #define INLINE __inline__
69 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73 static INLINE int fits_in_signed_word PARAMS ((offsetT));
74 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75 static INLINE int fits_in_signed_long PARAMS ((offsetT));
76 static int smallest_imm_type PARAMS ((offsetT));
77 static offsetT offset_in_range PARAMS ((offsetT, int));
78 static int add_prefix PARAMS ((unsigned int));
79 static void set_code_flag PARAMS ((int));
80 static void set_16bit_gcc_code_flag PARAMS ((int));
81 static void set_intel_syntax PARAMS ((int));
82 static void set_cpu_arch PARAMS ((int));
83 static char *output_invalid PARAMS ((int c));
84 static int i386_operand PARAMS ((char *operand_string));
85 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86 static const reg_entry *parse_register PARAMS ((char *reg_string,
88 static char *parse_insn PARAMS ((char *, char *));
89 static char *parse_operands PARAMS ((char *, const char *));
90 static void swap_operands PARAMS ((void));
91 static void optimize_imm PARAMS ((void));
92 static void optimize_disp PARAMS ((void));
93 static int match_template PARAMS ((void));
94 static int check_string PARAMS ((void));
95 static int process_suffix PARAMS ((void));
96 static int check_byte_reg PARAMS ((void));
97 static int check_long_reg PARAMS ((void));
98 static int check_qword_reg PARAMS ((void));
99 static int check_word_reg PARAMS ((void));
100 static int finalize_imm PARAMS ((void));
101 static int process_operands PARAMS ((void));
102 static const seg_entry *build_modrm_byte PARAMS ((void));
103 static void output_insn PARAMS ((void));
104 static void output_branch PARAMS ((void));
105 static void output_jump PARAMS ((void));
106 static void output_interseg_jump PARAMS ((void));
107 static void output_imm PARAMS ((void));
108 static void output_disp PARAMS ((void));
110 static void s_bss PARAMS ((int));
113 static const char *default_arch = DEFAULT_ARCH;
115 /* 'md_assemble ()' gathers together information and puts it into a
122 const reg_entry *regs;
127 /* TM holds the template for the insn were currently assembling. */
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
134 /* OPERANDS gives the number of given operands. */
135 unsigned int operands;
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
142 /* TYPES [i] is the type (see above #defines) which tells us how to
143 use OP[i] for the corresponding operand. */
144 unsigned int types[MAX_OPERANDS];
146 /* Displacement expression, immediate expression, or register for each
148 union i386_op op[MAX_OPERANDS];
150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152 #define Operand_PCrel 1
154 /* Relocation type for operand */
155 RELOC_ENUM reloc[MAX_OPERANDS];
157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
163 /* SEG gives the seg_entries of this insn. They are zero unless
164 explicit segment overrides are given. */
165 const seg_entry *seg[2];
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
180 typedef struct _i386_insn i386_insn;
182 /* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
185 const char extra_symbol_chars[] = "*%-(@[";
187 const char extra_symbol_chars[] = "*%-([";
190 #if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
195 /* This array holds the chars that always start a comment. If the
196 pre-processor is disabled, these aren't very useful. */
197 const char comment_chars[] = "#/";
198 #define PREFIX_SEPARATOR '\\'
200 /* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
204 first line of the input file. This is because the compiler outputs
205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
207 '/' isn't otherwise defined. */
208 const char line_comment_chars[] = "";
211 /* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213 const char comment_chars[] = "#";
214 #define PREFIX_SEPARATOR '/'
216 const char line_comment_chars[] = "/";
219 const char line_separator_chars[] = ";";
221 /* Chars that can be used to separate mant from exp in floating point
223 const char EXP_CHARS[] = "eE";
225 /* Chars that mean this number is a floating point constant
228 const char FLT_CHARS[] = "fFdDxX";
230 /* Tables for lexical analysis. */
231 static char mnemonic_chars[256];
232 static char register_chars[256];
233 static char operand_chars[256];
234 static char identifier_chars[256];
235 static char digit_chars[256];
237 /* Lexical macros. */
238 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239 #define is_operand_char(x) (operand_chars[(unsigned char) x])
240 #define is_register_char(x) (register_chars[(unsigned char) x])
241 #define is_space_char(x) ((x) == ' ')
242 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243 #define is_digit_char(x) (digit_chars[(unsigned char) x])
245 /* All non-digit non-letter charcters that may occur in an operand. */
246 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
248 /* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
251 assembler instruction). */
252 static char save_stack[32];
253 static char *save_stack_p;
254 #define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256 #define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
259 /* The instruction we're assembling. */
262 /* Possible templates for current insn. */
263 static const templates *current_templates;
265 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
266 static expressionS disp_expressions[2], im_expressions[2];
268 /* Current operand we are working on. */
269 static int this_operand;
271 /* We support four different modes. FLAG_CODE variable is used to distinguish
278 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
280 static enum flag_code flag_code;
281 static int use_rela_relocations = 0;
283 /* The names used to print error messages. */
284 static const char *flag_code_names[] =
291 /* 1 for intel syntax,
293 static int intel_syntax = 0;
295 /* 1 if register prefix % not required. */
296 static int allow_naked_reg = 0;
298 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301 static char stackop_size = '\0';
303 /* Non-zero to quieten some warnings. */
304 static int quiet_warnings = 0;
307 static const char *cpu_arch_name = NULL;
309 /* CPU feature flags. */
310 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
312 /* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314 static unsigned int no_cond_jump_promotion = 0;
316 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319 /* Interface to relax_segment.
320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
325 #define UNCOND_JUMP 0
327 #define COND_JUMP86 2
332 #define SMALL16 (SMALL | CODE16)
334 #define BIG16 (BIG | CODE16)
338 #define INLINE __inline__
344 #define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346 #define TYPE_FROM_RELAX_STATE(s) \
348 #define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
351 /* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
359 const relax_typeS md_relax_table[] =
362 1) most positive reach of this state,
363 2) most negative reach of this state,
364 3) how many bytes this mode will have in the variable part of the frag
365 4) which index into the table to try if we can't fit into this one. */
367 /* UNCOND_JUMP states. */
368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
383 /* word conditionals add 3 bytes to frag:
384 1 extra opcode byte, 2 displacement bytes. */
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
398 static const arch_entry cpu_arch[] = {
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
415 const pseudo_typeS md_pseudo_table[] =
417 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
420 {"align", s_align_ptwo, 0},
422 {"arch", set_cpu_arch, 0},
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
438 {"file", dwarf2_directive_file, 0},
439 {"loc", dwarf2_directive_loc, 0},
443 /* For interface with expression (). */
444 extern char *input_line_pointer;
446 /* Hash table for instruction mnemonic lookup. */
447 static struct hash_control *op_hash;
449 /* Hash table for register lookup. */
450 static struct hash_control *reg_hash;
453 i386_align_code (fragP, count)
457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
460 static const char f32_1[] =
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
519 static const char *const f16_patt[] = {
520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code == CODE_64BIT)
529 if (count > 0 && count <= 15)
531 if (flag_code == CODE_16BIT)
533 memcpy (fragP->fr_literal + fragP->fr_fix,
534 f16_patt[count - 1], count);
536 /* Adjust jump offset. */
537 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
540 memcpy (fragP->fr_literal + fragP->fr_fix,
541 f32_patt[count - 1], count);
542 fragP->fr_var = count;
546 static INLINE unsigned int
547 mode_from_disp_size (t)
550 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
554 fits_in_signed_byte (num)
557 return (num >= -128) && (num <= 127);
561 fits_in_unsigned_byte (num)
564 return (num & 0xff) == num;
568 fits_in_unsigned_word (num)
571 return (num & 0xffff) == num;
575 fits_in_signed_word (num)
578 return (-32768 <= num) && (num <= 32767);
581 fits_in_signed_long (num)
582 offsetT num ATTRIBUTE_UNUSED;
587 return (!(((offsetT) -1 << 31) & num)
588 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
590 } /* fits_in_signed_long() */
592 fits_in_unsigned_long (num)
593 offsetT num ATTRIBUTE_UNUSED;
598 return (num & (((offsetT) 2 << 31) - 1)) == num;
600 } /* fits_in_unsigned_long() */
603 smallest_imm_type (num)
606 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
614 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
616 return (fits_in_signed_byte (num)
617 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
618 : fits_in_unsigned_byte (num)
619 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
620 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
621 ? (Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_signed_long (num)
623 ? (Imm32 | Imm32S | Imm64)
624 : fits_in_unsigned_long (num)
630 offset_in_range (val, size)
638 case 1: mask = ((addressT) 1 << 8) - 1; break;
639 case 2: mask = ((addressT) 1 << 16) - 1; break;
640 case 4: mask = ((addressT) 2 << 31) - 1; break;
642 case 8: mask = ((addressT) 2 << 63) - 1; break;
647 /* If BFD64, sign extend val. */
648 if (!use_rela_relocations)
649 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
650 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
652 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
654 char buf1[40], buf2[40];
656 sprint_value (buf1, val);
657 sprint_value (buf2, val & mask);
658 as_warn (_("%s shortened to %s"), buf1, buf2);
663 /* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
673 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
674 && flag_code == CODE_64BIT)
682 case CS_PREFIX_OPCODE:
683 case DS_PREFIX_OPCODE:
684 case ES_PREFIX_OPCODE:
685 case FS_PREFIX_OPCODE:
686 case GS_PREFIX_OPCODE:
687 case SS_PREFIX_OPCODE:
691 case REPNE_PREFIX_OPCODE:
692 case REPE_PREFIX_OPCODE:
695 case LOCK_PREFIX_OPCODE:
703 case ADDR_PREFIX_OPCODE:
707 case DATA_PREFIX_OPCODE:
712 if (i.prefix[q] != 0)
714 as_bad (_("same type of prefix used twice"));
719 i.prefix[q] = prefix;
724 set_code_flag (value)
728 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
729 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
732 as_bad (_("64bit mode not supported on this CPU."));
734 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
736 as_bad (_("32bit mode not supported on this CPU."));
742 set_16bit_gcc_code_flag (new_code_flag)
745 flag_code = new_code_flag;
746 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
747 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
752 set_intel_syntax (syntax_flag)
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg = 0;
759 if (!is_end_of_line[(unsigned char) *input_line_pointer])
761 char *string = input_line_pointer;
762 int e = get_symbol_end ();
764 if (strcmp (string, "prefix") == 0)
766 else if (strcmp (string, "noprefix") == 0)
769 as_bad (_("bad argument to syntax directive."));
770 *input_line_pointer = e;
772 demand_empty_rest_of_line ();
774 intel_syntax = syntax_flag;
776 if (ask_naked_reg == 0)
779 allow_naked_reg = (intel_syntax
780 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
782 /* Conservative default. */
787 allow_naked_reg = (ask_naked_reg < 0);
792 int dummy ATTRIBUTE_UNUSED;
796 if (!is_end_of_line[(unsigned char) *input_line_pointer])
798 char *string = input_line_pointer;
799 int e = get_symbol_end ();
802 for (i = 0; cpu_arch[i].name; i++)
804 if (strcmp (string, cpu_arch[i].name) == 0)
806 cpu_arch_name = cpu_arch[i].name;
807 cpu_arch_flags = (cpu_arch[i].flags
808 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
812 if (!cpu_arch[i].name)
813 as_bad (_("no such architecture: `%s'"), string);
815 *input_line_pointer = e;
818 as_bad (_("missing cpu architecture"));
820 no_cond_jump_promotion = 0;
821 if (*input_line_pointer == ','
822 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
824 char *string = ++input_line_pointer;
825 int e = get_symbol_end ();
827 if (strcmp (string, "nojumps") == 0)
828 no_cond_jump_promotion = 1;
829 else if (strcmp (string, "jumps") == 0)
832 as_bad (_("no such architecture modifier: `%s'"), string);
834 *input_line_pointer = e;
837 demand_empty_rest_of_line ();
844 if (!strcmp (default_arch, "x86_64"))
845 return bfd_mach_x86_64;
846 else if (!strcmp (default_arch, "i386"))
847 return bfd_mach_i386_i386;
849 as_fatal (_("Unknown architecture"));
856 const char *hash_err;
858 /* Initialize op_hash hash table. */
859 op_hash = hash_new ();
862 const template *optab;
863 templates *core_optab;
865 /* Setup for loop. */
867 core_optab = (templates *) xmalloc (sizeof (templates));
868 core_optab->start = optab;
873 if (optab->name == NULL
874 || strcmp (optab->name, (optab - 1)->name) != 0)
876 /* different name --> ship out current template list;
877 add to hash table; & begin anew. */
878 core_optab->end = optab;
879 hash_err = hash_insert (op_hash,
884 as_fatal (_("Internal Error: Can't hash %s: %s"),
888 if (optab->name == NULL)
890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
896 /* Initialize reg_hash hash table. */
897 reg_hash = hash_new ();
899 const reg_entry *regtab;
901 for (regtab = i386_regtab;
902 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
905 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
907 as_fatal (_("Internal Error: Can't hash %s: %s"),
913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
918 for (c = 0; c < 256; c++)
923 mnemonic_chars[c] = c;
924 register_chars[c] = c;
925 operand_chars[c] = c;
927 else if (ISLOWER (c))
929 mnemonic_chars[c] = c;
930 register_chars[c] = c;
931 operand_chars[c] = c;
933 else if (ISUPPER (c))
935 mnemonic_chars[c] = TOLOWER (c);
936 register_chars[c] = mnemonic_chars[c];
937 operand_chars[c] = c;
940 if (ISALPHA (c) || ISDIGIT (c))
941 identifier_chars[c] = c;
944 identifier_chars[c] = c;
945 operand_chars[c] = c;
950 identifier_chars['@'] = '@';
952 digit_chars['-'] = '-';
953 identifier_chars['_'] = '_';
954 identifier_chars['.'] = '.';
956 for (p = operand_special_chars; *p != '\0'; p++)
957 operand_chars[(unsigned char) *p] = *p;
960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
963 record_alignment (text_section, 2);
964 record_alignment (data_section, 2);
965 record_alignment (bss_section, 2);
971 i386_print_statistics (file)
974 hash_print_statistics (file, "i386 opcode", op_hash);
975 hash_print_statistics (file, "i386 register", reg_hash);
980 /* Debugging routines for md_assemble. */
981 static void pi PARAMS ((char *, i386_insn *));
982 static void pte PARAMS ((template *));
983 static void pt PARAMS ((unsigned int));
984 static void pe PARAMS ((expressionS *));
985 static void ps PARAMS ((symbolS *));
994 fprintf (stdout, "%s: template ", line);
996 fprintf (stdout, " address: base %s index %s scale %x\n",
997 x->base_reg ? x->base_reg->reg_name : "none",
998 x->index_reg ? x->index_reg->reg_name : "none",
999 x->log2_scale_factor);
1000 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1001 x->rm.mode, x->rm.reg, x->rm.regmem);
1002 fprintf (stdout, " sib: base %x index %x scale %x\n",
1003 x->sib.base, x->sib.index, x->sib.scale);
1004 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1005 (x->rex & REX_MODE64) != 0,
1006 (x->rex & REX_EXTX) != 0,
1007 (x->rex & REX_EXTY) != 0,
1008 (x->rex & REX_EXTZ) != 0);
1009 for (i = 0; i < x->operands; i++)
1011 fprintf (stdout, " #%d: ", i + 1);
1013 fprintf (stdout, "\n");
1015 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1016 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1017 if (x->types[i] & Imm)
1019 if (x->types[i] & Disp)
1020 pe (x->op[i].disps);
1029 fprintf (stdout, " %d operands ", t->operands);
1030 fprintf (stdout, "opcode %x ", t->base_opcode);
1031 if (t->extension_opcode != None)
1032 fprintf (stdout, "ext %x ", t->extension_opcode);
1033 if (t->opcode_modifier & D)
1034 fprintf (stdout, "D");
1035 if (t->opcode_modifier & W)
1036 fprintf (stdout, "W");
1037 fprintf (stdout, "\n");
1038 for (i = 0; i < t->operands; i++)
1040 fprintf (stdout, " #%d type ", i + 1);
1041 pt (t->operand_types[i]);
1042 fprintf (stdout, "\n");
1050 fprintf (stdout, " operation %d\n", e->X_op);
1051 fprintf (stdout, " add_number %ld (%lx)\n",
1052 (long) e->X_add_number, (long) e->X_add_number);
1053 if (e->X_add_symbol)
1055 fprintf (stdout, " add_symbol ");
1056 ps (e->X_add_symbol);
1057 fprintf (stdout, "\n");
1061 fprintf (stdout, " op_symbol ");
1062 ps (e->X_op_symbol);
1063 fprintf (stdout, "\n");
1071 fprintf (stdout, "%s type %s%s",
1073 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s)));
1083 static const type_names[] =
1096 { BaseIndex, "BaseIndex" },
1100 { Disp32S, "d32s" },
1102 { InOutPortReg, "InOutPortReg" },
1103 { ShiftCount, "ShiftCount" },
1104 { Control, "control reg" },
1105 { Test, "test reg" },
1106 { Debug, "debug reg" },
1107 { FloatReg, "FReg" },
1108 { FloatAcc, "FAcc" },
1112 { JumpAbsolute, "Jump Absolute" },
1123 const struct type_name *ty;
1125 for (ty = type_names; ty->mask; ty++)
1127 fprintf (stdout, "%s, ", ty->tname);
1131 #endif /* DEBUG386 */
1134 tc_i386_force_relocation (fixp)
1137 #ifdef BFD_ASSEMBLER
1138 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1139 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1144 return fixp->fx_r_type == 7;
1148 #ifdef BFD_ASSEMBLER
1149 static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1152 static bfd_reloc_code_real_type
1153 reloc (size, pcrel, sign, other)
1157 bfd_reloc_code_real_type other;
1159 if (other != NO_RELOC)
1165 as_bad (_("There are no unsigned pc-relative relocations"));
1168 case 1: return BFD_RELOC_8_PCREL;
1169 case 2: return BFD_RELOC_16_PCREL;
1170 case 4: return BFD_RELOC_32_PCREL;
1172 as_bad (_("can not do %d byte pc-relative relocation"), size);
1179 case 4: return BFD_RELOC_X86_64_32S;
1184 case 1: return BFD_RELOC_8;
1185 case 2: return BFD_RELOC_16;
1186 case 4: return BFD_RELOC_32;
1187 case 8: return BFD_RELOC_64;
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign ? "signed" : "unsigned", size);
1194 return BFD_RELOC_NONE;
1197 /* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1203 tc_i386_fix_adjustable (fixP)
1206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
1209 if (S_IS_EXTERNAL (fixP->fx_addsy)
1210 || S_IS_WEAK (fixP->fx_addsy)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1218 /* adjust_reloc_syms doesn't know about the GOT. */
1219 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1220 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1221 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1228 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1230 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1231 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1232 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1237 #define reloc(SIZE,PCREL,SIGN,OTHER) 0
1238 #define BFD_RELOC_16 0
1239 #define BFD_RELOC_32 0
1240 #define BFD_RELOC_16_PCREL 0
1241 #define BFD_RELOC_32_PCREL 0
1242 #define BFD_RELOC_386_PLT32 0
1243 #define BFD_RELOC_386_GOT32 0
1244 #define BFD_RELOC_386_GOTOFF 0
1245 #define BFD_RELOC_386_TLS_GD 0
1246 #define BFD_RELOC_386_TLS_LDM 0
1247 #define BFD_RELOC_386_TLS_LDO_32 0
1248 #define BFD_RELOC_386_TLS_IE_32 0
1249 #define BFD_RELOC_386_TLS_LE_32 0
1250 #define BFD_RELOC_386_TLS_LE 0
1251 #define BFD_RELOC_X86_64_PLT32 0
1252 #define BFD_RELOC_X86_64_GOT32 0
1253 #define BFD_RELOC_X86_64_GOTPCREL 0
1256 static int intel_float_operand PARAMS ((const char *mnemonic));
1259 intel_float_operand (mnemonic)
1260 const char *mnemonic;
1262 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1265 if (mnemonic[0] == 'f')
1271 /* This is the guts of the machine-dependent assembler. LINE points to a
1272 machine dependent instruction. This function is supposed to emit
1273 the frags/bytes it assembles to. */
1280 char mnemonic[MAX_MNEM_SIZE];
1282 /* Initialize globals. */
1283 memset (&i, '\0', sizeof (i));
1284 for (j = 0; j < MAX_OPERANDS; j++)
1285 i.reloc[j] = NO_RELOC;
1286 memset (disp_expressions, '\0', sizeof (disp_expressions));
1287 memset (im_expressions, '\0', sizeof (im_expressions));
1288 save_stack_p = save_stack;
1290 /* First parse an instruction mnemonic & call i386_operand for the operands.
1291 We assume that the scrubber has arranged it so that line[0] is the valid
1292 start of a (possibly prefixed) mnemonic. */
1294 line = parse_insn (line, mnemonic);
1298 line = parse_operands (line, mnemonic);
1302 /* Now we've parsed the mnemonic into a set of templates, and have the
1303 operands at hand. */
1305 /* All intel opcodes have reversed operands except for "bound" and
1306 "enter". We also don't reverse intersegment "jmp" and "call"
1307 instructions with 2 immediate operands so that the immediate segment
1308 precedes the offset, as it does when in AT&T mode. "enter" and the
1309 intersegment "jmp" and "call" instructions are the only ones that
1310 have two immediate operands. */
1311 if (intel_syntax && i.operands > 1
1312 && (strcmp (mnemonic, "bound") != 0)
1313 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1319 if (i.disp_operands)
1322 /* Next, we find a template that matches the given insn,
1323 making sure the overlap of the given operands types is consistent
1324 with the template operand types. */
1326 if (!match_template ())
1329 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1332 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1333 i.tm.base_opcode ^= FloatR;
1335 if (i.tm.opcode_modifier & FWait)
1336 if (!add_prefix (FWAIT_OPCODE))
1339 /* Check string instruction segment overrides. */
1340 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1342 if (!check_string ())
1346 if (!process_suffix ())
1349 /* Make still unresolved immediate matches conform to size of immediate
1350 given in i.suffix. */
1351 if (!finalize_imm ())
1354 if (i.types[0] & Imm1)
1355 i.imm_operands = 0; /* kludge for shift insns. */
1356 if (i.types[0] & ImplicitRegister)
1358 if (i.types[1] & ImplicitRegister)
1360 if (i.types[2] & ImplicitRegister)
1363 if (i.tm.opcode_modifier & ImmExt)
1365 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1366 opcode suffix which is coded in the same place as an 8-bit
1367 immediate field would be. Here we fake an 8-bit immediate
1368 operand from the opcode suffix stored in tm.extension_opcode. */
1372 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1374 exp = &im_expressions[i.imm_operands++];
1375 i.op[i.operands].imms = exp;
1376 i.types[i.operands++] = Imm8;
1377 exp->X_op = O_constant;
1378 exp->X_add_number = i.tm.extension_opcode;
1379 i.tm.extension_opcode = None;
1382 /* For insns with operands there are more diddles to do to the opcode. */
1385 if (!process_operands ())
1388 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1390 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1391 as_warn (_("translating to `%sp'"), i.tm.name);
1394 /* Handle conversion of 'int $3' --> special int3 insn. */
1395 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1397 i.tm.base_opcode = INT3_OPCODE;
1401 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1402 && i.op[0].disps->X_op == O_constant)
1404 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1405 the absolute address given by the constant. Since ix86 jumps and
1406 calls are pc relative, we need to generate a reloc. */
1407 i.op[0].disps->X_add_symbol = &abs_symbol;
1408 i.op[0].disps->X_op = O_symbol;
1411 if ((i.tm.opcode_modifier & Rex64) != 0)
1412 i.rex |= REX_MODE64;
1414 /* For 8 bit registers we need an empty rex prefix. Also if the
1415 instruction already has a prefix, we need to convert old
1416 registers to new ones. */
1418 if (((i.types[0] & Reg8) != 0
1419 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1420 || ((i.types[1] & Reg8) != 0
1421 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1422 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1427 i.rex |= REX_OPCODE;
1428 for (x = 0; x < 2; x++)
1430 /* Look for 8 bit operand that uses old registers. */
1431 if ((i.types[x] & Reg8) != 0
1432 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1434 /* In case it is "hi" register, give up. */
1435 if (i.op[x].regs->reg_num > 3)
1436 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1437 i.op[x].regs->reg_name);
1439 /* Otherwise it is equivalent to the extended register.
1440 Since the encoding doesn't change this is merely
1441 cosmetic cleanup for debug output. */
1443 i.op[x].regs = i.op[x].regs + 8;
1449 add_prefix (REX_OPCODE | i.rex);
1451 /* We are ready to output the insn. */
1456 parse_insn (line, mnemonic)
1461 char *token_start = l;
1464 /* Non-zero if we found a prefix only acceptable with string insns. */
1465 const char *expecting_string_instruction = NULL;
1470 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1473 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1475 as_bad (_("no such instruction: `%s'"), token_start);
1480 if (!is_space_char (*l)
1481 && *l != END_OF_INSN
1482 && *l != PREFIX_SEPARATOR
1485 as_bad (_("invalid character %s in mnemonic"),
1486 output_invalid (*l));
1489 if (token_start == l)
1491 if (*l == PREFIX_SEPARATOR)
1492 as_bad (_("expecting prefix; got nothing"));
1494 as_bad (_("expecting mnemonic; got nothing"));
1498 /* Look up instruction (or prefix) via hash table. */
1499 current_templates = hash_find (op_hash, mnemonic);
1501 if (*l != END_OF_INSN
1502 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1503 && current_templates
1504 && (current_templates->start->opcode_modifier & IsPrefix))
1506 /* If we are in 16-bit mode, do not allow addr16 or data16.
1507 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1508 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1509 && flag_code != CODE_64BIT
1510 && (((current_templates->start->opcode_modifier & Size32) != 0)
1511 ^ (flag_code == CODE_16BIT)))
1513 as_bad (_("redundant %s prefix"),
1514 current_templates->start->name);
1517 /* Add prefix, checking for repeated prefixes. */
1518 switch (add_prefix (current_templates->start->base_opcode))
1523 expecting_string_instruction = current_templates->start->name;
1526 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1533 if (!current_templates)
1535 /* See if we can get a match by trimming off a suffix. */
1538 case WORD_MNEM_SUFFIX:
1539 case BYTE_MNEM_SUFFIX:
1540 case QWORD_MNEM_SUFFIX:
1541 i.suffix = mnem_p[-1];
1543 current_templates = hash_find (op_hash, mnemonic);
1545 case SHORT_MNEM_SUFFIX:
1546 case LONG_MNEM_SUFFIX:
1549 i.suffix = mnem_p[-1];
1551 current_templates = hash_find (op_hash, mnemonic);
1559 if (intel_float_operand (mnemonic))
1560 i.suffix = SHORT_MNEM_SUFFIX;
1562 i.suffix = LONG_MNEM_SUFFIX;
1564 current_templates = hash_find (op_hash, mnemonic);
1568 if (!current_templates)
1570 as_bad (_("no such instruction: `%s'"), token_start);
1575 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1577 /* Check for a branch hint. We allow ",pt" and ",pn" for
1578 predict taken and predict not taken respectively.
1579 I'm not sure that branch hints actually do anything on loop
1580 and jcxz insns (JumpByte) for current Pentium4 chips. They
1581 may work in the future and it doesn't hurt to accept them
1583 if (l[0] == ',' && l[1] == 'p')
1587 if (!add_prefix (DS_PREFIX_OPCODE))
1591 else if (l[2] == 'n')
1593 if (!add_prefix (CS_PREFIX_OPCODE))
1599 /* Any other comma loses. */
1602 as_bad (_("invalid character %s in mnemonic"),
1603 output_invalid (*l));
1607 /* Check if instruction is supported on specified architecture. */
1608 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1609 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1611 as_warn (_("`%s' is not supported on `%s'"),
1612 current_templates->start->name, cpu_arch_name);
1614 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1616 as_warn (_("use .code16 to ensure correct addressing mode"));
1619 /* Check for rep/repne without a string instruction. */
1620 if (expecting_string_instruction
1621 && !(current_templates->start->opcode_modifier & IsString))
1623 as_bad (_("expecting string instruction after `%s'"),
1624 expecting_string_instruction);
1632 parse_operands (l, mnemonic)
1634 const char *mnemonic;
1638 /* 1 if operand is pending after ','. */
1639 unsigned int expecting_operand = 0;
1641 /* Non-zero if operand parens not balanced. */
1642 unsigned int paren_not_balanced;
1644 while (*l != END_OF_INSN)
1646 /* Skip optional white space before operand. */
1647 if (is_space_char (*l))
1649 if (!is_operand_char (*l) && *l != END_OF_INSN)
1651 as_bad (_("invalid character %s before operand %d"),
1652 output_invalid (*l),
1656 token_start = l; /* after white space */
1657 paren_not_balanced = 0;
1658 while (paren_not_balanced || *l != ',')
1660 if (*l == END_OF_INSN)
1662 if (paren_not_balanced)
1665 as_bad (_("unbalanced parenthesis in operand %d."),
1668 as_bad (_("unbalanced brackets in operand %d."),
1673 break; /* we are done */
1675 else if (!is_operand_char (*l) && !is_space_char (*l))
1677 as_bad (_("invalid character %s in operand %d"),
1678 output_invalid (*l),
1685 ++paren_not_balanced;
1687 --paren_not_balanced;
1692 ++paren_not_balanced;
1694 --paren_not_balanced;
1698 if (l != token_start)
1699 { /* Yes, we've read in another operand. */
1700 unsigned int operand_ok;
1701 this_operand = i.operands++;
1702 if (i.operands > MAX_OPERANDS)
1704 as_bad (_("spurious operands; (%d operands/instruction max)"),
1708 /* Now parse operand adding info to 'i' as we go along. */
1709 END_STRING_AND_SAVE (l);
1713 i386_intel_operand (token_start,
1714 intel_float_operand (mnemonic));
1716 operand_ok = i386_operand (token_start);
1718 RESTORE_END_STRING (l);
1724 if (expecting_operand)
1726 expecting_operand_after_comma:
1727 as_bad (_("expecting operand after ','; got nothing"));
1732 as_bad (_("expecting operand before ','; got nothing"));
1737 /* Now *l must be either ',' or END_OF_INSN. */
1740 if (*++l == END_OF_INSN)
1742 /* Just skip it, if it's \n complain. */
1743 goto expecting_operand_after_comma;
1745 expecting_operand = 1;
1754 union i386_op temp_op;
1755 unsigned int temp_type;
1756 RELOC_ENUM temp_reloc;
1760 if (i.operands == 2)
1765 else if (i.operands == 3)
1770 temp_type = i.types[xchg2];
1771 i.types[xchg2] = i.types[xchg1];
1772 i.types[xchg1] = temp_type;
1773 temp_op = i.op[xchg2];
1774 i.op[xchg2] = i.op[xchg1];
1775 i.op[xchg1] = temp_op;
1776 temp_reloc = i.reloc[xchg2];
1777 i.reloc[xchg2] = i.reloc[xchg1];
1778 i.reloc[xchg1] = temp_reloc;
1780 if (i.mem_operands == 2)
1782 const seg_entry *temp_seg;
1783 temp_seg = i.seg[0];
1784 i.seg[0] = i.seg[1];
1785 i.seg[1] = temp_seg;
1789 /* Try to ensure constant immediates are represented in the smallest
1794 char guess_suffix = 0;
1798 guess_suffix = i.suffix;
1799 else if (i.reg_operands)
1801 /* Figure out a suffix from the last register operand specified.
1802 We can't do this properly yet, ie. excluding InOutPortReg,
1803 but the following works for instructions with immediates.
1804 In any case, we can't set i.suffix yet. */
1805 for (op = i.operands; --op >= 0;)
1806 if (i.types[op] & Reg)
1808 if (i.types[op] & Reg8)
1809 guess_suffix = BYTE_MNEM_SUFFIX;
1810 else if (i.types[op] & Reg16)
1811 guess_suffix = WORD_MNEM_SUFFIX;
1812 else if (i.types[op] & Reg32)
1813 guess_suffix = LONG_MNEM_SUFFIX;
1814 else if (i.types[op] & Reg64)
1815 guess_suffix = QWORD_MNEM_SUFFIX;
1819 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1820 guess_suffix = WORD_MNEM_SUFFIX;
1822 for (op = i.operands; --op >= 0;)
1823 if (i.types[op] & Imm)
1825 switch (i.op[op].imms->X_op)
1828 /* If a suffix is given, this operand may be shortened. */
1829 switch (guess_suffix)
1831 case LONG_MNEM_SUFFIX:
1832 i.types[op] |= Imm32 | Imm64;
1834 case WORD_MNEM_SUFFIX:
1835 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1837 case BYTE_MNEM_SUFFIX:
1838 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1842 /* If this operand is at most 16 bits, convert it
1843 to a signed 16 bit number before trying to see
1844 whether it will fit in an even smaller size.
1845 This allows a 16-bit operand such as $0xffe0 to
1846 be recognised as within Imm8S range. */
1847 if ((i.types[op] & Imm16)
1848 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1850 i.op[op].imms->X_add_number =
1851 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1853 if ((i.types[op] & Imm32)
1854 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1857 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1858 ^ ((offsetT) 1 << 31))
1859 - ((offsetT) 1 << 31));
1861 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1863 /* We must avoid matching of Imm32 templates when 64bit
1864 only immediate is available. */
1865 if (guess_suffix == QWORD_MNEM_SUFFIX)
1866 i.types[op] &= ~Imm32;
1873 /* Symbols and expressions. */
1875 /* Convert symbolic operand to proper sizes for matching. */
1876 switch (guess_suffix)
1878 case QWORD_MNEM_SUFFIX:
1879 i.types[op] = Imm64 | Imm32S;
1881 case LONG_MNEM_SUFFIX:
1882 i.types[op] = Imm32 | Imm64;
1884 case WORD_MNEM_SUFFIX:
1885 i.types[op] = Imm16 | Imm32 | Imm64;
1888 case BYTE_MNEM_SUFFIX:
1889 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1898 /* Try to use the smallest displacement type too. */
1904 for (op = i.operands; --op >= 0;)
1905 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1907 offsetT disp = i.op[op].disps->X_add_number;
1909 if (i.types[op] & Disp16)
1911 /* We know this operand is at most 16 bits, so
1912 convert to a signed 16 bit number before trying
1913 to see whether it will fit in an even smaller
1916 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1918 else if (i.types[op] & Disp32)
1920 /* We know this operand is at most 32 bits, so convert to a
1921 signed 32 bit number before trying to see whether it will
1922 fit in an even smaller size. */
1923 disp &= (((offsetT) 2 << 31) - 1);
1924 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1926 if (flag_code == CODE_64BIT)
1928 if (fits_in_signed_long (disp))
1929 i.types[op] |= Disp32S;
1930 if (fits_in_unsigned_long (disp))
1931 i.types[op] |= Disp32;
1933 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1934 && fits_in_signed_byte (disp))
1935 i.types[op] |= Disp8;
1942 /* Points to template once we've found it. */
1944 unsigned int overlap0, overlap1, overlap2;
1945 unsigned int found_reverse_match;
1948 #define MATCH(overlap, given, template) \
1949 ((overlap & ~JumpAbsolute) \
1950 && (((given) & (BaseIndex | JumpAbsolute)) \
1951 == ((overlap) & (BaseIndex | JumpAbsolute))))
1953 /* If given types r0 and r1 are registers they must be of the same type
1954 unless the expected operand type register overlap is null.
1955 Note that Acc in a template matches every size of reg. */
1956 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1957 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1958 || ((g0) & Reg) == ((g1) & Reg) \
1959 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1964 found_reverse_match = 0;
1965 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1967 : (i.suffix == WORD_MNEM_SUFFIX
1969 : (i.suffix == SHORT_MNEM_SUFFIX
1971 : (i.suffix == LONG_MNEM_SUFFIX
1973 : (i.suffix == QWORD_MNEM_SUFFIX
1975 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1976 ? No_xSuf : 0))))));
1978 for (t = current_templates->start;
1979 t < current_templates->end;
1982 /* Must have right number of operands. */
1983 if (i.operands != t->operands)
1986 /* Check the suffix, except for some instructions in intel mode. */
1987 if ((t->opcode_modifier & suffix_check)
1989 && (t->opcode_modifier & IgnoreSize))
1991 && t->base_opcode == 0xd9
1992 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1993 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1996 /* Do not verify operands when there are none. */
1997 else if (!t->operands)
1999 if (t->cpu_flags & ~cpu_arch_flags)
2001 /* We've found a match; break out of loop. */
2005 overlap0 = i.types[0] & t->operand_types[0];
2006 switch (t->operands)
2009 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2014 overlap1 = i.types[1] & t->operand_types[1];
2015 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2016 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2017 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2018 t->operand_types[0],
2019 overlap1, i.types[1],
2020 t->operand_types[1]))
2022 /* Check if other direction is valid ... */
2023 if ((t->opcode_modifier & (D | FloatD)) == 0)
2026 /* Try reversing direction of operands. */
2027 overlap0 = i.types[0] & t->operand_types[1];
2028 overlap1 = i.types[1] & t->operand_types[0];
2029 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2030 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2031 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2032 t->operand_types[1],
2033 overlap1, i.types[1],
2034 t->operand_types[0]))
2036 /* Does not match either direction. */
2039 /* found_reverse_match holds which of D or FloatDR
2041 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2043 /* Found a forward 2 operand match here. */
2044 else if (t->operands == 3)
2046 /* Here we make use of the fact that there are no
2047 reverse match 3 operand instructions, and all 3
2048 operand instructions only need to be checked for
2049 register consistency between operands 2 and 3. */
2050 overlap2 = i.types[2] & t->operand_types[2];
2051 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2052 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2053 t->operand_types[1],
2054 overlap2, i.types[2],
2055 t->operand_types[2]))
2059 /* Found either forward/reverse 2 or 3 operand match here:
2060 slip through to break. */
2062 if (t->cpu_flags & ~cpu_arch_flags)
2064 found_reverse_match = 0;
2067 /* We've found a match; break out of loop. */
2071 if (t == current_templates->end)
2073 /* We found no match. */
2074 as_bad (_("suffix or operands invalid for `%s'"),
2075 current_templates->start->name);
2079 if (!quiet_warnings)
2082 && ((i.types[0] & JumpAbsolute)
2083 != (t->operand_types[0] & JumpAbsolute)))
2085 as_warn (_("indirect %s without `*'"), t->name);
2088 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2089 == (IsPrefix | IgnoreSize))
2091 /* Warn them that a data or address size prefix doesn't
2092 affect assembly of the next line of code. */
2093 as_warn (_("stand-alone `%s' prefix"), t->name);
2097 /* Copy the template we found. */
2099 if (found_reverse_match)
2101 /* If we found a reverse match we must alter the opcode
2102 direction bit. found_reverse_match holds bits to change
2103 (different for int & float insns). */
2105 i.tm.base_opcode ^= found_reverse_match;
2107 i.tm.operand_types[0] = t->operand_types[1];
2108 i.tm.operand_types[1] = t->operand_types[0];
2117 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2118 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2120 if (i.seg[0] != NULL && i.seg[0] != &es)
2122 as_bad (_("`%s' operand %d must use `%%es' segment"),
2127 /* There's only ever one segment override allowed per instruction.
2128 This instruction possibly has a legal segment override on the
2129 second operand, so copy the segment to where non-string
2130 instructions store it, allowing common code. */
2131 i.seg[0] = i.seg[1];
2133 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2135 if (i.seg[1] != NULL && i.seg[1] != &es)
2137 as_bad (_("`%s' operand %d must use `%%es' segment"),
2149 /* If matched instruction specifies an explicit instruction mnemonic
2151 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2153 if (i.tm.opcode_modifier & Size16)
2154 i.suffix = WORD_MNEM_SUFFIX;
2155 else if (i.tm.opcode_modifier & Size64)
2156 i.suffix = QWORD_MNEM_SUFFIX;
2158 i.suffix = LONG_MNEM_SUFFIX;
2160 else if (i.reg_operands)
2162 /* If there's no instruction mnemonic suffix we try to invent one
2163 based on register operands. */
2166 /* We take i.suffix from the last register operand specified,
2167 Destination register type is more significant than source
2170 for (op = i.operands; --op >= 0;)
2171 if ((i.types[op] & Reg)
2172 && !(i.tm.operand_types[op] & InOutPortReg))
2174 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2175 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2176 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2181 else if (i.suffix == BYTE_MNEM_SUFFIX)
2183 if (!check_byte_reg ())
2186 else if (i.suffix == LONG_MNEM_SUFFIX)
2188 if (!check_long_reg ())
2191 else if (i.suffix == QWORD_MNEM_SUFFIX)
2193 if (!check_qword_reg ())
2196 else if (i.suffix == WORD_MNEM_SUFFIX)
2198 if (!check_word_reg ())
2201 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2202 /* Do nothing if the instruction is going to ignore the prefix. */
2207 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2209 i.suffix = stackop_size;
2212 /* Change the opcode based on the operand size given by i.suffix;
2213 We need not change things for byte insns. */
2215 if (!i.suffix && (i.tm.opcode_modifier & W))
2217 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2221 /* For movzx and movsx, need to check the register type. */
2223 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
2224 && i.suffix == BYTE_MNEM_SUFFIX)
2226 unsigned int prefix = DATA_PREFIX_OPCODE;
2228 if ((i.op[1].regs->reg_type & Reg16) != 0)
2229 if (!add_prefix (prefix))
2233 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2235 /* It's not a byte, select word/dword operation. */
2236 if (i.tm.opcode_modifier & W)
2238 if (i.tm.opcode_modifier & ShortForm)
2239 i.tm.base_opcode |= 8;
2241 i.tm.base_opcode |= 1;
2244 /* Now select between word & dword operations via the operand
2245 size prefix, except for instructions that will ignore this
2247 if (i.suffix != QWORD_MNEM_SUFFIX
2248 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2249 && !(i.tm.opcode_modifier & IgnoreSize))
2251 unsigned int prefix = DATA_PREFIX_OPCODE;
2252 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2253 prefix = ADDR_PREFIX_OPCODE;
2255 if (!add_prefix (prefix))
2259 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2260 && !(i.tm.opcode_modifier & IgnoreSize)
2261 && (i.tm.opcode_modifier & JumpByte))
2263 if (!add_prefix (ADDR_PREFIX_OPCODE))
2267 /* Set mode64 for an operand. */
2268 if (i.suffix == QWORD_MNEM_SUFFIX
2269 && (i.tm.opcode_modifier & NoRex64) == 0)
2271 i.rex |= REX_MODE64;
2272 if (flag_code < CODE_64BIT)
2274 as_bad (_("64bit operations available only in 64bit modes."));
2279 /* Size floating point instruction. */
2280 if (i.suffix == LONG_MNEM_SUFFIX)
2282 if (i.tm.opcode_modifier & FloatMF)
2283 i.tm.base_opcode ^= 4;
2294 for (op = i.operands; --op >= 0;)
2296 /* If this is an eight bit register, it's OK. If it's the 16 or
2297 32 bit version of an eight bit register, we will just use the
2298 low portion, and that's OK too. */
2299 if (i.types[op] & Reg8)
2302 /* movzx and movsx should not generate this warning. */
2304 && (i.tm.base_opcode == 0xfb7
2305 || i.tm.base_opcode == 0xfb6
2306 || i.tm.base_opcode == 0x63
2307 || i.tm.base_opcode == 0xfbe
2308 || i.tm.base_opcode == 0xfbf))
2311 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2313 /* Check that the template allows eight bit regs. This
2314 kills insns such as `orb $1,%edx', which maybe should be
2316 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2320 /* Prohibit these changes in the 64bit mode, since the
2321 lowering is more complicated. */
2322 if (flag_code == CODE_64BIT
2323 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2325 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2326 i.op[op].regs->reg_name,
2330 #if REGISTER_WARNINGS
2332 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2333 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2334 (i.op[op].regs + (i.types[op] & Reg16
2335 ? REGNAM_AL - REGNAM_AX
2336 : REGNAM_AL - REGNAM_EAX))->reg_name,
2337 i.op[op].regs->reg_name,
2342 /* Any other register is bad. */
2343 if (i.types[op] & (Reg | RegMMX | RegXMM
2345 | Control | Debug | Test
2346 | FloatReg | FloatAcc))
2348 as_bad (_("`%%%s' not allowed with `%s%c'"),
2349 i.op[op].regs->reg_name,
2363 for (op = i.operands; --op >= 0;)
2364 /* Reject eight bit registers, except where the template requires
2365 them. (eg. movzb) */
2366 if ((i.types[op] & Reg8) != 0
2367 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2369 as_bad (_("`%%%s' not allowed with `%s%c'"),
2370 i.op[op].regs->reg_name,
2375 /* Warn if the e prefix on a general reg is missing. */
2376 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2377 && (i.types[op] & Reg16) != 0
2378 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2380 /* Prohibit these changes in the 64bit mode, since the
2381 lowering is more complicated. */
2382 if (flag_code == CODE_64BIT)
2384 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2385 i.op[op].regs->reg_name,
2389 #if REGISTER_WARNINGS
2391 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2392 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2393 i.op[op].regs->reg_name,
2397 /* Warn if the r prefix on a general reg is missing. */
2398 else if ((i.types[op] & Reg64) != 0
2399 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2401 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2402 i.op[op].regs->reg_name,
2414 for (op = i.operands; --op >= 0; )
2415 /* Reject eight bit registers, except where the template requires
2416 them. (eg. movzb) */
2417 if ((i.types[op] & Reg8) != 0
2418 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2420 as_bad (_("`%%%s' not allowed with `%s%c'"),
2421 i.op[op].regs->reg_name,
2426 /* Warn if the e prefix on a general reg is missing. */
2427 else if (((i.types[op] & Reg16) != 0
2428 || (i.types[op] & Reg32) != 0)
2429 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2431 /* Prohibit these changes in the 64bit mode, since the
2432 lowering is more complicated. */
2433 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2434 i.op[op].regs->reg_name,
2445 for (op = i.operands; --op >= 0;)
2446 /* Reject eight bit registers, except where the template requires
2447 them. (eg. movzb) */
2448 if ((i.types[op] & Reg8) != 0
2449 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2451 as_bad (_("`%%%s' not allowed with `%s%c'"),
2452 i.op[op].regs->reg_name,
2457 /* Warn if the e prefix on a general reg is present. */
2458 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2459 && (i.types[op] & Reg32) != 0
2460 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2462 /* Prohibit these changes in the 64bit mode, since the
2463 lowering is more complicated. */
2464 if (flag_code == CODE_64BIT)
2466 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2467 i.op[op].regs->reg_name,
2472 #if REGISTER_WARNINGS
2473 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2474 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2475 i.op[op].regs->reg_name,
2485 unsigned int overlap0, overlap1, overlap2;
2487 overlap0 = i.types[0] & i.tm.operand_types[0];
2488 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2489 && overlap0 != Imm8 && overlap0 != Imm8S
2490 && overlap0 != Imm16 && overlap0 != Imm32S
2491 && overlap0 != Imm32 && overlap0 != Imm64)
2495 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2497 : (i.suffix == WORD_MNEM_SUFFIX
2499 : (i.suffix == QWORD_MNEM_SUFFIX
2503 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2504 || overlap0 == (Imm16 | Imm32)
2505 || overlap0 == (Imm16 | Imm32S))
2507 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2510 if (overlap0 != Imm8 && overlap0 != Imm8S
2511 && overlap0 != Imm16 && overlap0 != Imm32S
2512 && overlap0 != Imm32 && overlap0 != Imm64)
2514 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2518 i.types[0] = overlap0;
2520 overlap1 = i.types[1] & i.tm.operand_types[1];
2521 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2522 && overlap1 != Imm8 && overlap1 != Imm8S
2523 && overlap1 != Imm16 && overlap1 != Imm32S
2524 && overlap1 != Imm32 && overlap1 != Imm64)
2528 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2530 : (i.suffix == WORD_MNEM_SUFFIX
2532 : (i.suffix == QWORD_MNEM_SUFFIX
2536 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2537 || overlap1 == (Imm16 | Imm32)
2538 || overlap1 == (Imm16 | Imm32S))
2540 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2543 if (overlap1 != Imm8 && overlap1 != Imm8S
2544 && overlap1 != Imm16 && overlap1 != Imm32S
2545 && overlap1 != Imm32 && overlap1 != Imm64)
2547 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2551 i.types[1] = overlap1;
2553 overlap2 = i.types[2] & i.tm.operand_types[2];
2554 assert ((overlap2 & Imm) == 0);
2555 i.types[2] = overlap2;
2563 /* Default segment register this instruction will use for memory
2564 accesses. 0 means unknown. This is only for optimizing out
2565 unnecessary segment overrides. */
2566 const seg_entry *default_seg = 0;
2568 /* The imul $imm, %reg instruction is converted into
2569 imul $imm, %reg, %reg, and the clr %reg instruction
2570 is converted into xor %reg, %reg. */
2571 if (i.tm.opcode_modifier & regKludge)
2573 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2574 /* Pretend we saw the extra register operand. */
2575 assert (i.op[first_reg_op + 1].regs == 0);
2576 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2577 i.types[first_reg_op + 1] = i.types[first_reg_op];
2581 if (i.tm.opcode_modifier & ShortForm)
2583 /* The register or float register operand is in operand 0 or 1. */
2584 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2585 /* Register goes in low 3 bits of opcode. */
2586 i.tm.base_opcode |= i.op[op].regs->reg_num;
2587 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2589 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2591 /* Warn about some common errors, but press on regardless.
2592 The first case can be generated by gcc (<= 2.8.1). */
2593 if (i.operands == 2)
2595 /* Reversed arguments on faddp, fsubp, etc. */
2596 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2597 i.op[1].regs->reg_name,
2598 i.op[0].regs->reg_name);
2602 /* Extraneous `l' suffix on fp insn. */
2603 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2604 i.op[0].regs->reg_name);
2608 else if (i.tm.opcode_modifier & Modrm)
2610 /* The opcode is completed (modulo i.tm.extension_opcode which
2611 must be put into the modrm byte).
2612 Now, we make the modrm & index base bytes based on all the
2613 info we've collected. */
2615 default_seg = build_modrm_byte ();
2617 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2619 if (i.tm.base_opcode == POP_SEG_SHORT
2620 && i.op[0].regs->reg_num == 1)
2622 as_bad (_("you can't `pop %%cs'"));
2625 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2626 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2629 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2633 else if ((i.tm.opcode_modifier & IsString) != 0)
2635 /* For the string instructions that allow a segment override
2636 on one of their operands, the default segment is ds. */
2640 /* If a segment was explicitly specified,
2641 and the specified segment is not the default,
2642 use an opcode prefix to select it.
2643 If we never figured out what the default segment is,
2644 then default_seg will be zero at this point,
2645 and the specified segment prefix will always be used. */
2646 if ((i.seg[0]) && (i.seg[0] != default_seg))
2648 if (!add_prefix (i.seg[0]->seg_prefix))
2654 static const seg_entry *
2657 const seg_entry *default_seg = 0;
2659 /* i.reg_operands MUST be the number of real register operands;
2660 implicit registers do not count. */
2661 if (i.reg_operands == 2)
2663 unsigned int source, dest;
2664 source = ((i.types[0]
2665 & (Reg | RegMMX | RegXMM
2667 | Control | Debug | Test))
2672 /* One of the register operands will be encoded in the i.tm.reg
2673 field, the other in the combined i.tm.mode and i.tm.regmem
2674 fields. If no form of this instruction supports a memory
2675 destination operand, then we assume the source operand may
2676 sometimes be a memory operand and so we need to store the
2677 destination in the i.rm.reg field. */
2678 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2680 i.rm.reg = i.op[dest].regs->reg_num;
2681 i.rm.regmem = i.op[source].regs->reg_num;
2682 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2684 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2689 i.rm.reg = i.op[source].regs->reg_num;
2690 i.rm.regmem = i.op[dest].regs->reg_num;
2691 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2693 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2698 { /* If it's not 2 reg operands... */
2701 unsigned int fake_zero_displacement = 0;
2702 unsigned int op = ((i.types[0] & AnyMem)
2704 : (i.types[1] & AnyMem) ? 1 : 2);
2708 if (i.base_reg == 0)
2711 if (!i.disp_operands)
2712 fake_zero_displacement = 1;
2713 if (i.index_reg == 0)
2715 /* Operand is just <disp> */
2716 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2717 && (flag_code != CODE_64BIT))
2719 i.rm.regmem = NO_BASE_REGISTER_16;
2720 i.types[op] &= ~Disp;
2721 i.types[op] |= Disp16;
2723 else if (flag_code != CODE_64BIT
2724 || (i.prefix[ADDR_PREFIX] != 0))
2726 i.rm.regmem = NO_BASE_REGISTER;
2727 i.types[op] &= ~Disp;
2728 i.types[op] |= Disp32;
2732 /* 64bit mode overwrites the 32bit absolute
2733 addressing by RIP relative addressing and
2734 absolute addressing is encoded by one of the
2735 redundant SIB forms. */
2736 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2737 i.sib.base = NO_BASE_REGISTER;
2738 i.sib.index = NO_INDEX_REGISTER;
2739 i.types[op] &= ~Disp;
2740 i.types[op] |= Disp32S;
2743 else /* !i.base_reg && i.index_reg */
2745 i.sib.index = i.index_reg->reg_num;
2746 i.sib.base = NO_BASE_REGISTER;
2747 i.sib.scale = i.log2_scale_factor;
2748 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2749 i.types[op] &= ~Disp;
2750 if (flag_code != CODE_64BIT)
2751 i.types[op] |= Disp32; /* Must be 32 bit */
2753 i.types[op] |= Disp32S;
2754 if ((i.index_reg->reg_flags & RegRex) != 0)
2758 /* RIP addressing for 64bit mode. */
2759 else if (i.base_reg->reg_type == BaseIndex)
2761 i.rm.regmem = NO_BASE_REGISTER;
2762 i.types[op] &= ~Disp;
2763 i.types[op] |= Disp32S;
2764 i.flags[op] = Operand_PCrel;
2766 else if (i.base_reg->reg_type & Reg16)
2768 switch (i.base_reg->reg_num)
2771 if (i.index_reg == 0)
2773 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2774 i.rm.regmem = i.index_reg->reg_num - 6;
2778 if (i.index_reg == 0)
2781 if ((i.types[op] & Disp) == 0)
2783 /* fake (%bp) into 0(%bp) */
2784 i.types[op] |= Disp8;
2785 fake_zero_displacement = 1;
2788 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2789 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2791 default: /* (%si) -> 4 or (%di) -> 5 */
2792 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2794 i.rm.mode = mode_from_disp_size (i.types[op]);
2796 else /* i.base_reg and 32/64 bit mode */
2798 if (flag_code == CODE_64BIT
2799 && (i.types[op] & Disp))
2801 if (i.types[op] & Disp8)
2802 i.types[op] = Disp8 | Disp32S;
2804 i.types[op] = Disp32S;
2806 i.rm.regmem = i.base_reg->reg_num;
2807 if ((i.base_reg->reg_flags & RegRex) != 0)
2809 i.sib.base = i.base_reg->reg_num;
2810 /* x86-64 ignores REX prefix bit here to avoid decoder
2812 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2815 if (i.disp_operands == 0)
2817 fake_zero_displacement = 1;
2818 i.types[op] |= Disp8;
2821 else if (i.base_reg->reg_num == ESP_REG_NUM)
2825 i.sib.scale = i.log2_scale_factor;
2826 if (i.index_reg == 0)
2828 /* <disp>(%esp) becomes two byte modrm with no index
2829 register. We've already stored the code for esp
2830 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2831 Any base register besides %esp will not use the
2832 extra modrm byte. */
2833 i.sib.index = NO_INDEX_REGISTER;
2834 #if !SCALE1_WHEN_NO_INDEX
2835 /* Another case where we force the second modrm byte. */
2836 if (i.log2_scale_factor)
2837 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2842 i.sib.index = i.index_reg->reg_num;
2843 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2844 if ((i.index_reg->reg_flags & RegRex) != 0)
2847 i.rm.mode = mode_from_disp_size (i.types[op]);
2850 if (fake_zero_displacement)
2852 /* Fakes a zero displacement assuming that i.types[op]
2853 holds the correct displacement size. */
2856 assert (i.op[op].disps == 0);
2857 exp = &disp_expressions[i.disp_operands++];
2858 i.op[op].disps = exp;
2859 exp->X_op = O_constant;
2860 exp->X_add_number = 0;
2861 exp->X_add_symbol = (symbolS *) 0;
2862 exp->X_op_symbol = (symbolS *) 0;
2866 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2867 (if any) based on i.tm.extension_opcode. Again, we must be
2868 careful to make sure that segment/control/debug/test/MMX
2869 registers are coded into the i.rm.reg field. */
2874 & (Reg | RegMMX | RegXMM
2876 | Control | Debug | Test))
2879 & (Reg | RegMMX | RegXMM
2881 | Control | Debug | Test))
2884 /* If there is an extension opcode to put here, the register
2885 number must be put into the regmem field. */
2886 if (i.tm.extension_opcode != None)
2888 i.rm.regmem = i.op[op].regs->reg_num;
2889 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2894 i.rm.reg = i.op[op].regs->reg_num;
2895 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2899 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2900 must set it to 3 to indicate this is a register operand
2901 in the regmem field. */
2902 if (!i.mem_operands)
2906 /* Fill in i.rm.reg field with extension opcode (if any). */
2907 if (i.tm.extension_opcode != None)
2908 i.rm.reg = i.tm.extension_opcode;
2919 relax_substateT subtype;
2924 if (flag_code == CODE_16BIT)
2928 if (i.prefix[DATA_PREFIX] != 0)
2934 /* Pentium4 branch hints. */
2935 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2936 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2941 if (i.prefix[REX_PREFIX] != 0)
2947 if (i.prefixes != 0 && !intel_syntax)
2948 as_warn (_("skipping prefixes on this instruction"));
2950 /* It's always a symbol; End frag & setup for relax.
2951 Make sure there is enough room in this frag for the largest
2952 instruction we may generate in md_convert_frag. This is 2
2953 bytes for the opcode and room for the prefix and largest
2955 frag_grow (prefix + 2 + 4);
2956 /* Prefix and 1 opcode byte go in fr_fix. */
2957 p = frag_more (prefix + 1);
2958 if (i.prefix[DATA_PREFIX] != 0)
2959 *p++ = DATA_PREFIX_OPCODE;
2960 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2961 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2962 *p++ = i.prefix[SEG_PREFIX];
2963 if (i.prefix[REX_PREFIX] != 0)
2964 *p++ = i.prefix[REX_PREFIX];
2965 *p = i.tm.base_opcode;
2967 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2968 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2969 else if ((cpu_arch_flags & Cpu386) != 0)
2970 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2972 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2975 sym = i.op[0].disps->X_add_symbol;
2976 off = i.op[0].disps->X_add_number;
2978 if (i.op[0].disps->X_op != O_constant
2979 && i.op[0].disps->X_op != O_symbol)
2981 /* Handle complex expressions. */
2982 sym = make_expr_symbol (i.op[0].disps);
2986 /* 1 possible extra opcode + 4 byte displacement go in var part.
2987 Pass reloc in fr_var. */
2988 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2997 if (i.tm.opcode_modifier & JumpByte)
2999 /* This is a loop or jecxz type instruction. */
3001 if (i.prefix[ADDR_PREFIX] != 0)
3003 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3006 /* Pentium4 branch hints. */
3007 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3008 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3010 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3019 if (flag_code == CODE_16BIT)
3022 if (i.prefix[DATA_PREFIX] != 0)
3024 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3034 if (i.prefix[REX_PREFIX] != 0)
3036 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3040 if (i.prefixes != 0 && !intel_syntax)
3041 as_warn (_("skipping prefixes on this instruction"));
3043 p = frag_more (1 + size);
3044 *p++ = i.tm.base_opcode;
3046 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3047 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3051 output_interseg_jump ()
3059 if (flag_code == CODE_16BIT)
3063 if (i.prefix[DATA_PREFIX] != 0)
3069 if (i.prefix[REX_PREFIX] != 0)
3079 if (i.prefixes != 0 && !intel_syntax)
3080 as_warn (_("skipping prefixes on this instruction"));
3082 /* 1 opcode; 2 segment; offset */
3083 p = frag_more (prefix + 1 + 2 + size);
3085 if (i.prefix[DATA_PREFIX] != 0)
3086 *p++ = DATA_PREFIX_OPCODE;
3088 if (i.prefix[REX_PREFIX] != 0)
3089 *p++ = i.prefix[REX_PREFIX];
3091 *p++ = i.tm.base_opcode;
3092 if (i.op[1].imms->X_op == O_constant)
3094 offsetT n = i.op[1].imms->X_add_number;
3097 && !fits_in_unsigned_word (n)
3098 && !fits_in_signed_word (n))
3100 as_bad (_("16-bit jump out of range"));
3103 md_number_to_chars (p, n, size);
3106 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3107 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3108 if (i.op[0].imms->X_op != O_constant)
3109 as_bad (_("can't handle non absolute segment in `%s'"),
3111 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3117 /* Tie dwarf2 debug info to the address at the start of the insn.
3118 We can't do this after the insn has been output as the current
3119 frag may have been closed off. eg. by frag_var. */
3120 dwarf2_emit_insn (0);
3123 if (i.tm.opcode_modifier & Jump)
3125 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3127 else if (i.tm.opcode_modifier & JumpInterSegment)
3128 output_interseg_jump ();
3131 /* Output normal instructions here. */
3135 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3136 byte for the SSE instructions to specify a prefix they require. */
3137 if (i.tm.base_opcode & 0xff0000)
3138 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3140 /* The prefix bytes. */
3142 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3148 md_number_to_chars (p, (valueT) *q, 1);
3152 /* Now the opcode; be careful about word order here! */
3153 if (fits_in_unsigned_byte (i.tm.base_opcode))
3155 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3160 /* Put out high byte first: can't use md_number_to_chars! */
3161 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3162 *p = i.tm.base_opcode & 0xff;
3165 /* Now the modrm byte and sib byte (if present). */
3166 if (i.tm.opcode_modifier & Modrm)
3169 md_number_to_chars (p,
3170 (valueT) (i.rm.regmem << 0
3174 /* If i.rm.regmem == ESP (4)
3175 && i.rm.mode != (Register mode)
3177 ==> need second modrm byte. */
3178 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3180 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3183 md_number_to_chars (p,
3184 (valueT) (i.sib.base << 0
3186 | i.sib.scale << 6),
3191 if (i.disp_operands)
3203 #endif /* DEBUG386 */
3212 for (n = 0; n < i.operands; n++)
3214 if (i.types[n] & Disp)
3216 if (i.op[n].disps->X_op == O_constant)
3222 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3225 if (i.types[n] & Disp8)
3227 if (i.types[n] & Disp64)
3230 val = offset_in_range (i.op[n].disps->X_add_number,
3232 p = frag_more (size);
3233 md_number_to_chars (p, val, size);
3239 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3241 /* The PC relative address is computed relative
3242 to the instruction boundary, so in case immediate
3243 fields follows, we need to adjust the value. */
3244 if (pcrel && i.imm_operands)
3249 for (n1 = 0; n1 < i.operands; n1++)
3250 if (i.types[n1] & Imm)
3252 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3255 if (i.types[n1] & (Imm8 | Imm8S))
3257 if (i.types[n1] & Imm64)
3262 /* We should find the immediate. */
3263 if (n1 == i.operands)
3265 i.op[n].disps->X_add_number -= imm_size;
3268 if (i.types[n] & Disp32S)
3271 if (i.types[n] & (Disp16 | Disp64))
3274 if (i.types[n] & Disp64)
3278 p = frag_more (size);
3279 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3280 i.op[n].disps, pcrel,
3281 reloc (size, pcrel, sign, i.reloc[n]));
3293 for (n = 0; n < i.operands; n++)
3295 if (i.types[n] & Imm)
3297 if (i.op[n].imms->X_op == O_constant)
3303 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3306 if (i.types[n] & (Imm8 | Imm8S))
3308 else if (i.types[n] & Imm64)
3311 val = offset_in_range (i.op[n].imms->X_add_number,
3313 p = frag_more (size);
3314 md_number_to_chars (p, val, size);
3318 /* Not absolute_section.
3319 Need a 32-bit fixup (don't support 8bit
3320 non-absolute imms). Try to support other
3322 RELOC_ENUM reloc_type;
3326 if ((i.types[n] & (Imm32S))
3327 && i.suffix == QWORD_MNEM_SUFFIX)
3329 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3332 if (i.types[n] & (Imm8 | Imm8S))
3334 if (i.types[n] & Imm64)
3338 p = frag_more (size);
3339 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3340 #ifdef BFD_ASSEMBLER
3341 if (reloc_type == BFD_RELOC_32
3343 && GOT_symbol == i.op[n].imms->X_add_symbol
3344 && (i.op[n].imms->X_op == O_symbol
3345 || (i.op[n].imms->X_op == O_add
3346 && ((symbol_get_value_expression
3347 (i.op[n].imms->X_op_symbol)->X_op)
3350 /* We don't support dynamic linking on x86-64 yet. */
3351 if (flag_code == CODE_64BIT)
3353 reloc_type = BFD_RELOC_386_GOTPC;
3354 i.op[n].imms->X_add_number += 3;
3357 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3358 i.op[n].imms, 0, reloc_type);
3365 static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3367 /* Parse operands of the form
3368 <symbol>@GOTOFF+<nnn>
3369 and similar .plt or .got references.
3371 If we find one, set up the correct relocation in RELOC and copy the
3372 input string, minus the `@GOTOFF' into a malloc'd buffer for
3373 parsing by the calling routine. Return this buffer, and if ADJUST
3374 is non-null set it to the length of the string we removed from the
3375 input line. Otherwise return NULL. */
3377 lex_got (reloc, adjust)
3381 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3382 static const struct {
3384 const RELOC_ENUM rel[NUM_FLAG_CODE];
3386 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3387 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3388 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3389 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3390 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3391 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3392 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3393 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3394 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3395 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3400 for (cp = input_line_pointer; *cp != '@'; cp++)
3401 if (is_end_of_line[(unsigned char) *cp])
3404 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3408 len = strlen (gotrel[j].str);
3409 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3411 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3414 char *tmpbuf, *past_reloc;
3416 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3420 if (GOT_symbol == NULL)
3421 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3423 /* Replace the relocation token with ' ', so that
3424 errors like foo@GOTOFF1 will be detected. */
3426 /* The length of the first part of our input line. */
3427 first = cp - input_line_pointer;
3429 /* The second part goes from after the reloc token until
3430 (and including) an end_of_line char. Don't use strlen
3431 here as the end_of_line char may not be a NUL. */
3432 past_reloc = cp + 1 + len;
3433 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3435 second = cp - past_reloc;
3437 /* Allocate and copy string. The trailing NUL shouldn't
3438 be necessary, but be safe. */
3439 tmpbuf = xmalloc (first + second + 2);
3440 memcpy (tmpbuf, input_line_pointer, first);
3441 tmpbuf[first] = ' ';
3442 memcpy (tmpbuf + first + 1, past_reloc, second);
3443 tmpbuf[first + second + 1] = '\0';
3447 as_bad (_("@%s reloc is not supported in %s bit mode"),
3448 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3453 /* Might be a symbol version string. Don't as_bad here. */
3457 /* x86_cons_fix_new is called via the expression parsing code when a
3458 reloc is needed. We use this hook to get the correct .got reloc. */
3459 static RELOC_ENUM got_reloc = NO_RELOC;
3462 x86_cons_fix_new (frag, off, len, exp)
3468 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3469 got_reloc = NO_RELOC;
3470 fix_new_exp (frag, off, len, exp, 0, r);
3474 x86_cons (exp, size)
3480 /* Handle @GOTOFF and the like in an expression. */
3482 char *gotfree_input_line;
3485 save = input_line_pointer;
3486 gotfree_input_line = lex_got (&got_reloc, &adjust);
3487 if (gotfree_input_line)
3488 input_line_pointer = gotfree_input_line;
3492 if (gotfree_input_line)
3494 /* expression () has merrily parsed up to the end of line,
3495 or a comma - in the wrong buffer. Transfer how far
3496 input_line_pointer has moved to the right buffer. */
3497 input_line_pointer = (save
3498 + (input_line_pointer - gotfree_input_line)
3500 free (gotfree_input_line);
3508 static int i386_immediate PARAMS ((char *));
3511 i386_immediate (imm_start)
3514 char *save_input_line_pointer;
3516 char *gotfree_input_line;
3521 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3523 as_bad (_("only 1 or 2 immediate operands are allowed"));
3527 exp = &im_expressions[i.imm_operands++];
3528 i.op[this_operand].imms = exp;
3530 if (is_space_char (*imm_start))
3533 save_input_line_pointer = input_line_pointer;
3534 input_line_pointer = imm_start;
3537 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3538 if (gotfree_input_line)
3539 input_line_pointer = gotfree_input_line;
3542 exp_seg = expression (exp);
3545 if (*input_line_pointer)
3546 as_bad (_("junk `%s' after expression"), input_line_pointer);
3548 input_line_pointer = save_input_line_pointer;
3550 if (gotfree_input_line)
3551 free (gotfree_input_line);
3554 if (exp->X_op == O_absent || exp->X_op == O_big)
3556 /* Missing or bad expr becomes absolute 0. */
3557 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3559 exp->X_op = O_constant;
3560 exp->X_add_number = 0;
3561 exp->X_add_symbol = (symbolS *) 0;
3562 exp->X_op_symbol = (symbolS *) 0;
3564 else if (exp->X_op == O_constant)
3566 /* Size it properly later. */
3567 i.types[this_operand] |= Imm64;
3568 /* If BFD64, sign extend val. */
3569 if (!use_rela_relocations)
3570 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3571 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3573 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3575 #ifdef BFD_ASSEMBLER
3576 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3578 && exp_seg != text_section
3579 && exp_seg != data_section
3580 && exp_seg != bss_section
3581 && exp_seg != undefined_section
3582 #ifdef BFD_ASSEMBLER
3583 && !bfd_is_com_section (exp_seg)
3587 #ifdef BFD_ASSEMBLER
3588 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3590 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3597 /* This is an address. The size of the address will be
3598 determined later, depending on destination register,
3599 suffix, or the default for the section. */
3600 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3606 static char *i386_scale PARAMS ((char *));
3613 char *save = input_line_pointer;
3615 input_line_pointer = scale;
3616 val = get_absolute_expression ();
3622 i.log2_scale_factor = 0;
3625 i.log2_scale_factor = 1;
3628 i.log2_scale_factor = 2;
3631 i.log2_scale_factor = 3;
3634 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3636 input_line_pointer = save;
3639 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3641 as_warn (_("scale factor of %d without an index register"),
3642 1 << i.log2_scale_factor);
3643 #if SCALE1_WHEN_NO_INDEX
3644 i.log2_scale_factor = 0;
3647 scale = input_line_pointer;
3648 input_line_pointer = save;
3652 static int i386_displacement PARAMS ((char *, char *));
3655 i386_displacement (disp_start, disp_end)
3661 char *save_input_line_pointer;
3663 char *gotfree_input_line;
3665 int bigdisp = Disp32;
3667 if (flag_code == CODE_64BIT)
3669 if (i.prefix[ADDR_PREFIX] == 0)
3672 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3674 i.types[this_operand] |= bigdisp;
3676 exp = &disp_expressions[i.disp_operands];
3677 i.op[this_operand].disps = exp;
3679 save_input_line_pointer = input_line_pointer;
3680 input_line_pointer = disp_start;
3681 END_STRING_AND_SAVE (disp_end);
3683 #ifndef GCC_ASM_O_HACK
3684 #define GCC_ASM_O_HACK 0
3687 END_STRING_AND_SAVE (disp_end + 1);
3688 if ((i.types[this_operand] & BaseIndex) != 0
3689 && displacement_string_end[-1] == '+')
3691 /* This hack is to avoid a warning when using the "o"
3692 constraint within gcc asm statements.
3695 #define _set_tssldt_desc(n,addr,limit,type) \
3696 __asm__ __volatile__ ( \
3698 "movw %w1,2+%0\n\t" \
3700 "movb %b1,4+%0\n\t" \
3701 "movb %4,5+%0\n\t" \
3702 "movb $0,6+%0\n\t" \
3703 "movb %h1,7+%0\n\t" \
3705 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3707 This works great except that the output assembler ends
3708 up looking a bit weird if it turns out that there is
3709 no offset. You end up producing code that looks like:
3722 So here we provide the missing zero. */
3724 *displacement_string_end = '0';
3728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3729 if (gotfree_input_line)
3730 input_line_pointer = gotfree_input_line;
3733 exp_seg = expression (exp);
3736 if (*input_line_pointer)
3737 as_bad (_("junk `%s' after expression"), input_line_pointer);
3739 RESTORE_END_STRING (disp_end + 1);
3741 RESTORE_END_STRING (disp_end);
3742 input_line_pointer = save_input_line_pointer;
3744 if (gotfree_input_line)
3745 free (gotfree_input_line);
3748 #ifdef BFD_ASSEMBLER
3749 /* We do this to make sure that the section symbol is in
3750 the symbol table. We will ultimately change the relocation
3751 to be relative to the beginning of the section. */
3752 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3753 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3755 if (exp->X_op != O_symbol)
3757 as_bad (_("bad expression used with @%s"),
3758 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3764 if (S_IS_LOCAL (exp->X_add_symbol)
3765 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3766 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3767 exp->X_op = O_subtract;
3768 exp->X_op_symbol = GOT_symbol;
3769 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3770 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3772 i.reloc[this_operand] = BFD_RELOC_32;
3776 if (exp->X_op == O_absent || exp->X_op == O_big)
3778 /* Missing or bad expr becomes absolute 0. */
3779 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3781 exp->X_op = O_constant;
3782 exp->X_add_number = 0;
3783 exp->X_add_symbol = (symbolS *) 0;
3784 exp->X_op_symbol = (symbolS *) 0;
3787 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3788 if (exp->X_op != O_constant
3789 #ifdef BFD_ASSEMBLER
3790 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3792 && exp_seg != text_section
3793 && exp_seg != data_section
3794 && exp_seg != bss_section
3795 && exp_seg != undefined_section)
3797 #ifdef BFD_ASSEMBLER
3798 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3800 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
3805 else if (flag_code == CODE_64BIT)
3806 i.types[this_operand] |= Disp32S | Disp32;
3810 static int i386_index_check PARAMS ((const char *));
3812 /* Make sure the memory operand we've been dealt is valid.
3813 Return 1 on success, 0 on a failure. */
3816 i386_index_check (operand_string)
3817 const char *operand_string;
3820 #if INFER_ADDR_PREFIX
3826 if (flag_code == CODE_64BIT)
3828 if (i.prefix[ADDR_PREFIX] == 0)
3832 && ((i.base_reg->reg_type & Reg64) == 0)
3833 && (i.base_reg->reg_type != BaseIndex
3836 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3837 != (Reg64 | BaseIndex))))
3844 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3846 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3847 != (Reg32 | BaseIndex))))
3853 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3857 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3858 != (Reg16 | BaseIndex)))
3860 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3861 != (Reg16 | BaseIndex))
3863 && i.base_reg->reg_num < 6
3864 && i.index_reg->reg_num >= 6
3865 && i.log2_scale_factor == 0))))
3872 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3874 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3875 != (Reg32 | BaseIndex))))
3881 #if INFER_ADDR_PREFIX
3882 if (flag_code != CODE_64BIT
3883 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3885 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3887 /* Change the size of any displacement too. At most one of
3888 Disp16 or Disp32 is set.
3889 FIXME. There doesn't seem to be any real need for separate
3890 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3891 Removing them would probably clean up the code quite a lot. */
3892 if (i.types[this_operand] & (Disp16 | Disp32))
3893 i.types[this_operand] ^= (Disp16 | Disp32);
3898 as_bad (_("`%s' is not a valid base/index expression"),
3902 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3904 flag_code_names[flag_code]);
3910 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3914 i386_operand (operand_string)
3915 char *operand_string;
3919 char *op_string = operand_string;
3921 if (is_space_char (*op_string))
3924 /* We check for an absolute prefix (differentiating,
3925 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3926 if (*op_string == ABSOLUTE_PREFIX)
3929 if (is_space_char (*op_string))
3931 i.types[this_operand] |= JumpAbsolute;
3934 /* Check if operand is a register. */
3935 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3936 && (r = parse_register (op_string, &end_op)) != NULL)
3938 /* Check for a segment override by searching for ':' after a
3939 segment register. */
3941 if (is_space_char (*op_string))
3943 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3948 i.seg[i.mem_operands] = &es;
3951 i.seg[i.mem_operands] = &cs;
3954 i.seg[i.mem_operands] = &ss;
3957 i.seg[i.mem_operands] = &ds;
3960 i.seg[i.mem_operands] = &fs;
3963 i.seg[i.mem_operands] = &gs;
3967 /* Skip the ':' and whitespace. */
3969 if (is_space_char (*op_string))
3972 if (!is_digit_char (*op_string)
3973 && !is_identifier_char (*op_string)
3974 && *op_string != '('
3975 && *op_string != ABSOLUTE_PREFIX)
3977 as_bad (_("bad memory operand `%s'"), op_string);
3980 /* Handle case of %es:*foo. */
3981 if (*op_string == ABSOLUTE_PREFIX)
3984 if (is_space_char (*op_string))
3986 i.types[this_operand] |= JumpAbsolute;
3988 goto do_memory_reference;
3992 as_bad (_("junk `%s' after register"), op_string);
3995 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3996 i.op[this_operand].regs = r;
3999 else if (*op_string == REGISTER_PREFIX)
4001 as_bad (_("bad register name `%s'"), op_string);
4004 else if (*op_string == IMMEDIATE_PREFIX)
4007 if (i.types[this_operand] & JumpAbsolute)
4009 as_bad (_("immediate operand illegal with absolute jump"));
4012 if (!i386_immediate (op_string))
4015 else if (is_digit_char (*op_string)
4016 || is_identifier_char (*op_string)
4017 || *op_string == '(')
4019 /* This is a memory reference of some sort. */
4022 /* Start and end of displacement string expression (if found). */
4023 char *displacement_string_start;
4024 char *displacement_string_end;
4026 do_memory_reference:
4027 if ((i.mem_operands == 1
4028 && (current_templates->start->opcode_modifier & IsString) == 0)
4029 || i.mem_operands == 2)
4031 as_bad (_("too many memory references for `%s'"),
4032 current_templates->start->name);
4036 /* Check for base index form. We detect the base index form by
4037 looking for an ')' at the end of the operand, searching
4038 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4040 base_string = op_string + strlen (op_string);
4043 if (is_space_char (*base_string))
4046 /* If we only have a displacement, set-up for it to be parsed later. */
4047 displacement_string_start = op_string;
4048 displacement_string_end = base_string + 1;
4050 if (*base_string == ')')
4053 unsigned int parens_balanced = 1;
4054 /* We've already checked that the number of left & right ()'s are
4055 equal, so this loop will not be infinite. */
4059 if (*base_string == ')')
4061 if (*base_string == '(')
4064 while (parens_balanced);
4066 temp_string = base_string;
4068 /* Skip past '(' and whitespace. */
4070 if (is_space_char (*base_string))
4073 if (*base_string == ','
4074 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4075 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4077 displacement_string_end = temp_string;
4079 i.types[this_operand] |= BaseIndex;
4083 base_string = end_op;
4084 if (is_space_char (*base_string))
4088 /* There may be an index reg or scale factor here. */
4089 if (*base_string == ',')
4092 if (is_space_char (*base_string))
4095 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4096 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4098 base_string = end_op;
4099 if (is_space_char (*base_string))
4101 if (*base_string == ',')
4104 if (is_space_char (*base_string))
4107 else if (*base_string != ')')
4109 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4114 else if (*base_string == REGISTER_PREFIX)
4116 as_bad (_("bad register name `%s'"), base_string);
4120 /* Check for scale factor. */
4121 if (*base_string != ')')
4123 char *end_scale = i386_scale (base_string);
4128 base_string = end_scale;
4129 if (is_space_char (*base_string))
4131 if (*base_string != ')')
4133 as_bad (_("expecting `)' after scale factor in `%s'"),
4138 else if (!i.index_reg)
4140 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4145 else if (*base_string != ')')
4147 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4152 else if (*base_string == REGISTER_PREFIX)
4154 as_bad (_("bad register name `%s'"), base_string);
4159 /* If there's an expression beginning the operand, parse it,
4160 assuming displacement_string_start and
4161 displacement_string_end are meaningful. */
4162 if (displacement_string_start != displacement_string_end)
4164 if (!i386_displacement (displacement_string_start,
4165 displacement_string_end))
4169 /* Special case for (%dx) while doing input/output op. */
4171 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4173 && i.log2_scale_factor == 0
4174 && i.seg[i.mem_operands] == 0
4175 && (i.types[this_operand] & Disp) == 0)
4177 i.types[this_operand] = InOutPortReg;
4181 if (i386_index_check (operand_string) == 0)
4187 /* It's not a memory operand; argh! */
4188 as_bad (_("invalid char %s beginning operand %d `%s'"),
4189 output_invalid (*op_string),
4194 return 1; /* Normal return. */
4197 /* md_estimate_size_before_relax()
4199 Called just before relax() for rs_machine_dependent frags. The x86
4200 assembler uses these frags to handle variable size jump
4203 Any symbol that is now undefined will not become defined.
4204 Return the correct fr_subtype in the frag.
4205 Return the initial "guess for variable size of frag" to caller.
4206 The guess is actually the growth beyond the fixed part. Whatever
4207 we do to grow the fixed or variable part contributes to our
4211 md_estimate_size_before_relax (fragP, segment)
4215 /* We've already got fragP->fr_subtype right; all we have to do is
4216 check for un-relaxable symbols. On an ELF system, we can't relax
4217 an externally visible symbol, because it may be overridden by a
4219 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4220 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4221 || S_IS_EXTERNAL (fragP->fr_symbol)
4222 || S_IS_WEAK (fragP->fr_symbol)
4226 /* Symbol is undefined in this segment, or we need to keep a
4227 reloc so that weak symbols can be overridden. */
4228 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4229 RELOC_ENUM reloc_type;
4230 unsigned char *opcode;
4233 if (fragP->fr_var != NO_RELOC)
4234 reloc_type = fragP->fr_var;
4236 reloc_type = BFD_RELOC_16_PCREL;
4238 reloc_type = BFD_RELOC_32_PCREL;
4240 old_fr_fix = fragP->fr_fix;
4241 opcode = (unsigned char *) fragP->fr_opcode;
4243 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4246 /* Make jmp (0xeb) a (d)word displacement jump. */
4248 fragP->fr_fix += size;
4249 fix_new (fragP, old_fr_fix, size,
4251 fragP->fr_offset, 1,
4257 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4259 /* Negate the condition, and branch past an
4260 unconditional jump. */
4263 /* Insert an unconditional jump. */
4265 /* We added two extra opcode bytes, and have a two byte
4267 fragP->fr_fix += 2 + 2;
4268 fix_new (fragP, old_fr_fix + 2, 2,
4270 fragP->fr_offset, 1,
4277 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4280 fix_new (fragP, old_fr_fix, 1,
4282 fragP->fr_offset, 1,
4287 /* This changes the byte-displacement jump 0x7N
4288 to the (d)word-displacement jump 0x0f,0x8N. */
4289 opcode[1] = opcode[0] + 0x10;
4290 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4291 /* We've added an opcode byte. */
4292 fragP->fr_fix += 1 + size;
4293 fix_new (fragP, old_fr_fix + 1, size,
4295 fragP->fr_offset, 1,
4300 BAD_CASE (fragP->fr_subtype);
4304 return fragP->fr_fix - old_fr_fix;
4307 /* Guess size depending on current relax state. Initially the relax
4308 state will correspond to a short jump and we return 1, because
4309 the variable part of the frag (the branch offset) is one byte
4310 long. However, we can relax a section more than once and in that
4311 case we must either set fr_subtype back to the unrelaxed state,
4312 or return the value for the appropriate branch. */
4313 return md_relax_table[fragP->fr_subtype].rlx_length;
4316 /* Called after relax() is finished.
4318 In: Address of frag.
4319 fr_type == rs_machine_dependent.
4320 fr_subtype is what the address relaxed to.
4322 Out: Any fixSs and constants are set up.
4323 Caller will turn frag into a ".space 0". */
4325 #ifndef BFD_ASSEMBLER
4327 md_convert_frag (headers, sec, fragP)
4328 object_headers *headers ATTRIBUTE_UNUSED;
4329 segT sec ATTRIBUTE_UNUSED;
4333 md_convert_frag (abfd, sec, fragP)
4334 bfd *abfd ATTRIBUTE_UNUSED;
4335 segT sec ATTRIBUTE_UNUSED;
4339 unsigned char *opcode;
4340 unsigned char *where_to_put_displacement = NULL;
4341 offsetT target_address;
4342 offsetT opcode_address;
4343 unsigned int extension = 0;
4344 offsetT displacement_from_opcode_start;
4346 opcode = (unsigned char *) fragP->fr_opcode;
4348 /* Address we want to reach in file space. */
4349 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4351 /* Address opcode resides at in file space. */
4352 opcode_address = fragP->fr_address + fragP->fr_fix;
4354 /* Displacement from opcode start to fill into instruction. */
4355 displacement_from_opcode_start = target_address - opcode_address;
4357 if ((fragP->fr_subtype & BIG) == 0)
4359 /* Don't have to change opcode. */
4360 extension = 1; /* 1 opcode + 1 displacement */
4361 where_to_put_displacement = &opcode[1];
4365 if (no_cond_jump_promotion
4366 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4367 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4369 switch (fragP->fr_subtype)
4371 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4372 extension = 4; /* 1 opcode + 4 displacement */
4374 where_to_put_displacement = &opcode[1];
4377 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4378 extension = 2; /* 1 opcode + 2 displacement */
4380 where_to_put_displacement = &opcode[1];
4383 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4384 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4385 extension = 5; /* 2 opcode + 4 displacement */
4386 opcode[1] = opcode[0] + 0x10;
4387 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4388 where_to_put_displacement = &opcode[2];
4391 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4392 extension = 3; /* 2 opcode + 2 displacement */
4393 opcode[1] = opcode[0] + 0x10;
4394 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4395 where_to_put_displacement = &opcode[2];
4398 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4403 where_to_put_displacement = &opcode[3];
4407 BAD_CASE (fragP->fr_subtype);
4412 /* Now put displacement after opcode. */
4413 md_number_to_chars ((char *) where_to_put_displacement,
4414 (valueT) (displacement_from_opcode_start - extension),
4415 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4416 fragP->fr_fix += extension;
4419 /* Size of byte displacement jmp. */
4420 int md_short_jump_size = 2;
4422 /* Size of dword displacement jmp. */
4423 int md_long_jump_size = 5;
4425 /* Size of relocation record. */
4426 const int md_reloc_size = 8;
4429 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4431 addressT from_addr, to_addr;
4432 fragS *frag ATTRIBUTE_UNUSED;
4433 symbolS *to_symbol ATTRIBUTE_UNUSED;
4437 offset = to_addr - (from_addr + 2);
4438 /* Opcode for byte-disp jump. */
4439 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4440 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4444 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4446 addressT from_addr, to_addr;
4447 fragS *frag ATTRIBUTE_UNUSED;
4448 symbolS *to_symbol ATTRIBUTE_UNUSED;
4452 offset = to_addr - (from_addr + 5);
4453 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4454 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4457 /* Apply a fixup (fixS) to segment data, once it has been determined
4458 by our caller that we have all the info we need to fix it up.
4460 On the 386, immediates, displacements, and data pointers are all in
4461 the same (little-endian) format, so we don't need to care about which
4465 md_apply_fix3 (fixP, valP, seg)
4466 /* The fix we're to put in. */
4468 /* Pointer to the value of the bits. */
4470 /* Segment fix is from. */
4471 segT seg ATTRIBUTE_UNUSED;
4473 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4474 valueT value = * valP;
4476 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
4479 switch (fixP->fx_r_type)
4485 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4488 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4491 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4496 /* This is a hack. There should be a better way to handle this.
4497 This covers for the fact that bfd_install_relocation will
4498 subtract the current location (for partial_inplace, PC relative
4499 relocations); see more below. */
4500 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4501 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4502 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4503 && fixP->fx_addsy && !use_rela_relocations)
4506 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4508 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4511 value += fixP->fx_where + fixP->fx_frag->fr_address;
4513 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4514 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4516 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4519 || (symbol_section_p (fixP->fx_addsy)
4520 && fseg != absolute_section))
4521 && !S_IS_EXTERNAL (fixP->fx_addsy)
4522 && !S_IS_WEAK (fixP->fx_addsy)
4523 && S_IS_DEFINED (fixP->fx_addsy)
4524 && !S_IS_COMMON (fixP->fx_addsy))
4526 /* Yes, we add the values in twice. This is because
4527 bfd_perform_relocation subtracts them out again. I think
4528 bfd_perform_relocation is broken, but I don't dare change
4530 value += fixP->fx_where + fixP->fx_frag->fr_address;
4534 #if defined (OBJ_COFF) && defined (TE_PE)
4535 /* For some reason, the PE format does not store a section
4536 address offset for a PC relative symbol. */
4537 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4538 value += md_pcrel_from (fixP);
4542 /* Fix a few things - the dynamic linker expects certain values here,
4543 and we must not dissappoint it. */
4544 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4545 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4547 switch (fixP->fx_r_type)
4549 case BFD_RELOC_386_PLT32:
4550 case BFD_RELOC_X86_64_PLT32:
4551 /* Make the jump instruction point to the address of the operand. At
4552 runtime we merely add the offset to the actual PLT entry. */
4555 case BFD_RELOC_386_GOTPC:
4557 /* This is tough to explain. We end up with this one if we have
4558 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4559 * here is to obtain the absolute address of the GOT, and it is strongly
4560 * preferable from a performance point of view to avoid using a runtime
4561 * relocation for this. The actual sequence of instructions often look
4567 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4569 * The call and pop essentially return the absolute address of
4570 * the label .L66 and store it in %ebx. The linker itself will
4571 * ultimately change the first operand of the addl so that %ebx points to
4572 * the GOT, but to keep things simple, the .o file must have this operand
4573 * set so that it generates not the absolute address of .L66, but the
4574 * absolute address of itself. This allows the linker itself simply
4575 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4576 * added in, and the addend of the relocation is stored in the operand
4577 * field for the instruction itself.
4579 * Our job here is to fix the operand so that it would add the correct
4580 * offset so that %ebx would point to itself. The thing that is tricky is
4581 * that .-.L66 will point to the beginning of the instruction, so we need
4582 * to further modify the operand so that it will point to itself.
4583 * There are other cases where you have something like:
4585 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4587 * and here no correction would be required. Internally in the assembler
4588 * we treat operands of this form as not being pcrel since the '.' is
4589 * explicitly mentioned, and I wonder whether it would simplify matters
4590 * to do it this way. Who knows. In earlier versions of the PIC patches,
4591 * the pcrel_adjust field was used to store the correction, but since the
4592 * expression is not pcrel, I felt it would be confusing to do it this
4597 case BFD_RELOC_386_GOT32:
4598 case BFD_RELOC_386_TLS_GD:
4599 case BFD_RELOC_386_TLS_LDM:
4600 case BFD_RELOC_386_TLS_LDO_32:
4601 case BFD_RELOC_386_TLS_IE_32:
4602 case BFD_RELOC_386_TLS_LE_32:
4603 case BFD_RELOC_386_TLS_LE:
4604 case BFD_RELOC_X86_64_GOT32:
4605 value = 0; /* Fully resolved at runtime. No addend. */
4607 case BFD_RELOC_386_GOTOFF:
4608 case BFD_RELOC_X86_64_GOTPCREL:
4611 case BFD_RELOC_VTABLE_INHERIT:
4612 case BFD_RELOC_VTABLE_ENTRY:
4619 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4621 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4623 /* Are we finished with this relocation now? */
4624 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4626 #ifdef BFD_ASSEMBLER
4627 else if (use_rela_relocations)
4629 fixP->fx_no_overflow = 1;
4630 /* Remember value for tc_gen_reloc. */
4631 fixP->fx_addnumber = value;
4635 md_number_to_chars (p, value, fixP->fx_size);
4638 #define MAX_LITTLENUMS 6
4640 /* Turn the string pointed to by litP into a floating point constant
4641 of type TYPE, and emit the appropriate bytes. The number of
4642 LITTLENUMS emitted is stored in *SIZEP. An error message is
4643 returned, or NULL on OK. */
4646 md_atof (type, litP, sizeP)
4652 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4653 LITTLENUM_TYPE *wordP;
4675 return _("Bad call to md_atof ()");
4677 t = atof_ieee (input_line_pointer, type, words);
4679 input_line_pointer = t;
4681 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4682 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4683 the bigendian 386. */
4684 for (wordP = words + prec - 1; prec--;)
4686 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4687 litP += sizeof (LITTLENUM_TYPE);
4692 char output_invalid_buf[8];
4699 sprintf (output_invalid_buf, "'%c'", c);
4701 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4702 return output_invalid_buf;
4705 /* REG_STRING starts *before* REGISTER_PREFIX. */
4707 static const reg_entry *
4708 parse_register (reg_string, end_op)
4712 char *s = reg_string;
4714 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4717 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4718 if (*s == REGISTER_PREFIX)
4721 if (is_space_char (*s))
4725 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4727 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4728 return (const reg_entry *) NULL;
4732 /* For naked regs, make sure that we are not dealing with an identifier.
4733 This prevents confusing an identifier like `eax_var' with register
4735 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4736 return (const reg_entry *) NULL;
4740 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4742 /* Handle floating point regs, allowing spaces in the (i) part. */
4743 if (r == i386_regtab /* %st is first entry of table */)
4745 if (is_space_char (*s))
4750 if (is_space_char (*s))
4752 if (*s >= '0' && *s <= '7')
4754 r = &i386_float_regtab[*s - '0'];
4756 if (is_space_char (*s))
4764 /* We have "%st(" then garbage. */
4765 return (const reg_entry *) NULL;
4770 && (r->reg_flags & (RegRex64 | RegRex)) != 0
4771 && flag_code != CODE_64BIT)
4773 return (const reg_entry *) NULL;
4779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4780 const char *md_shortopts = "kVQ:sq";
4782 const char *md_shortopts = "q";
4785 struct option md_longopts[] = {
4786 #define OPTION_32 (OPTION_MD_BASE + 0)
4787 {"32", no_argument, NULL, OPTION_32},
4788 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4789 #define OPTION_64 (OPTION_MD_BASE + 1)
4790 {"64", no_argument, NULL, OPTION_64},
4792 {NULL, no_argument, NULL, 0}
4794 size_t md_longopts_size = sizeof (md_longopts);
4797 md_parse_option (c, arg)
4799 char *arg ATTRIBUTE_UNUSED;
4807 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4808 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4809 should be emitted or not. FIXME: Not implemented. */
4813 /* -V: SVR4 argument to print version ID. */
4815 print_version_id ();
4818 /* -k: Ignore for FreeBSD compatibility. */
4823 /* -s: On i386 Solaris, this tells the native assembler to use
4824 .stab instead of .stab.excl. We always use .stab anyhow. */
4829 const char **list, **l;
4831 list = bfd_target_list ();
4832 for (l = list; *l != NULL; l++)
4833 if (strcmp (*l, "elf64-x86-64") == 0)
4835 default_arch = "x86_64";
4839 as_fatal (_("No compiled in support for x86_64"));
4846 default_arch = "i386";
4856 md_show_usage (stream)
4859 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4860 fprintf (stream, _("\
4862 -V print assembler version number\n\
4864 -q quieten some warnings\n\
4867 fprintf (stream, _("\
4868 -q quieten some warnings\n"));
4872 #ifdef BFD_ASSEMBLER
4873 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4874 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4876 /* Pick the target format to use. */
4879 i386_target_format ()
4881 if (!strcmp (default_arch, "x86_64"))
4882 set_code_flag (CODE_64BIT);
4883 else if (!strcmp (default_arch, "i386"))
4884 set_code_flag (CODE_32BIT);
4886 as_fatal (_("Unknown architecture"));
4887 switch (OUTPUT_FLAVOR)
4889 #ifdef OBJ_MAYBE_AOUT
4890 case bfd_target_aout_flavour:
4891 return AOUT_TARGET_FORMAT;
4893 #ifdef OBJ_MAYBE_COFF
4894 case bfd_target_coff_flavour:
4897 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4898 case bfd_target_elf_flavour:
4900 if (flag_code == CODE_64BIT)
4901 use_rela_relocations = 1;
4902 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
4911 #endif /* OBJ_MAYBE_ more than one */
4913 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4914 void i386_elf_emit_arch_note ()
4916 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4917 && cpu_arch_name != NULL)
4920 asection *seg = now_seg;
4921 subsegT subseg = now_subseg;
4922 Elf_Internal_Note i_note;
4923 Elf_External_Note e_note;
4924 asection *note_secp;
4927 /* Create the .note section. */
4928 note_secp = subseg_new (".note", 0);
4929 bfd_set_section_flags (stdoutput,
4931 SEC_HAS_CONTENTS | SEC_READONLY);
4933 /* Process the arch string. */
4934 len = strlen (cpu_arch_name);
4936 i_note.namesz = len + 1;
4938 i_note.type = NT_ARCH;
4939 p = frag_more (sizeof (e_note.namesz));
4940 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4941 p = frag_more (sizeof (e_note.descsz));
4942 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4943 p = frag_more (sizeof (e_note.type));
4944 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4945 p = frag_more (len + 1);
4946 strcpy (p, cpu_arch_name);
4948 frag_align (2, 0, 0);
4950 subseg_set (seg, subseg);
4954 #endif /* BFD_ASSEMBLER */
4957 md_undefined_symbol (name)
4960 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4961 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4962 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4963 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4967 if (symbol_find (name))
4968 as_bad (_("GOT already in symbol table"));
4969 GOT_symbol = symbol_new (name, undefined_section,
4970 (valueT) 0, &zero_address_frag);
4977 /* Round up a section size to the appropriate boundary. */
4980 md_section_align (segment, size)
4981 segT segment ATTRIBUTE_UNUSED;
4984 #ifdef BFD_ASSEMBLER
4985 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4986 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4988 /* For a.out, force the section size to be aligned. If we don't do
4989 this, BFD will align it for us, but it will not write out the
4990 final bytes of the section. This may be a bug in BFD, but it is
4991 easier to fix it here since that is how the other a.out targets
4995 align = bfd_get_section_alignment (stdoutput, segment);
4996 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5004 /* On the i386, PC-relative offsets are relative to the start of the
5005 next instruction. That is, the address of the offset, plus its
5006 size, since the offset is always the last part of the insn. */
5009 md_pcrel_from (fixP)
5012 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5019 int ignore ATTRIBUTE_UNUSED;
5023 temp = get_absolute_expression ();
5024 subseg_set (bss_section, (subsegT) temp);
5025 demand_empty_rest_of_line ();
5030 #ifdef BFD_ASSEMBLER
5033 i386_validate_fix (fixp)
5036 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5038 /* GOTOFF relocation are nonsense in 64bit mode. */
5039 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5041 if (flag_code != CODE_64BIT)
5043 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5047 if (flag_code == CODE_64BIT)
5049 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5056 tc_gen_reloc (section, fixp)
5057 asection *section ATTRIBUTE_UNUSED;
5061 bfd_reloc_code_real_type code;
5063 switch (fixp->fx_r_type)
5065 case BFD_RELOC_X86_64_PLT32:
5066 case BFD_RELOC_X86_64_GOT32:
5067 case BFD_RELOC_X86_64_GOTPCREL:
5068 case BFD_RELOC_386_PLT32:
5069 case BFD_RELOC_386_GOT32:
5070 case BFD_RELOC_386_GOTOFF:
5071 case BFD_RELOC_386_GOTPC:
5072 case BFD_RELOC_386_TLS_GD:
5073 case BFD_RELOC_386_TLS_LDM:
5074 case BFD_RELOC_386_TLS_LDO_32:
5075 case BFD_RELOC_386_TLS_IE_32:
5076 case BFD_RELOC_386_TLS_LE_32:
5077 case BFD_RELOC_386_TLS_LE:
5078 case BFD_RELOC_X86_64_32S:
5080 case BFD_RELOC_VTABLE_ENTRY:
5081 case BFD_RELOC_VTABLE_INHERIT:
5082 code = fixp->fx_r_type;
5087 switch (fixp->fx_size)
5090 as_bad_where (fixp->fx_file, fixp->fx_line,
5091 _("can not do %d byte pc-relative relocation"),
5093 code = BFD_RELOC_32_PCREL;
5095 case 1: code = BFD_RELOC_8_PCREL; break;
5096 case 2: code = BFD_RELOC_16_PCREL; break;
5097 case 4: code = BFD_RELOC_32_PCREL; break;
5102 switch (fixp->fx_size)
5105 as_bad_where (fixp->fx_file, fixp->fx_line,
5106 _("can not do %d byte relocation"),
5108 code = BFD_RELOC_32;
5110 case 1: code = BFD_RELOC_8; break;
5111 case 2: code = BFD_RELOC_16; break;
5112 case 4: code = BFD_RELOC_32; break;
5114 case 8: code = BFD_RELOC_64; break;
5121 if (code == BFD_RELOC_32
5123 && fixp->fx_addsy == GOT_symbol)
5125 /* We don't support GOTPC on 64bit targets. */
5126 if (flag_code == CODE_64BIT)
5128 code = BFD_RELOC_386_GOTPC;
5131 rel = (arelent *) xmalloc (sizeof (arelent));
5132 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5133 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5135 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5136 if (!use_rela_relocations)
5138 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5139 vtable entry to be used in the relocation's section offset. */
5140 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5141 rel->address = fixp->fx_offset;
5144 rel->addend = fixp->fx_addnumber;
5148 /* Use the rela in 64bit mode. */
5151 if (!fixp->fx_pcrel)
5152 rel->addend = fixp->fx_offset;
5156 case BFD_RELOC_X86_64_PLT32:
5157 case BFD_RELOC_X86_64_GOT32:
5158 case BFD_RELOC_X86_64_GOTPCREL:
5159 rel->addend = fixp->fx_offset - fixp->fx_size;
5162 rel->addend = (section->vma
5164 + fixp->fx_addnumber
5165 + md_pcrel_from (fixp));
5170 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5171 if (rel->howto == NULL)
5173 as_bad_where (fixp->fx_file, fixp->fx_line,
5174 _("cannot represent relocation type %s"),
5175 bfd_get_reloc_code_name (code));
5176 /* Set howto to a garbage value so that we can keep going. */
5177 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5178 assert (rel->howto != NULL);
5184 #else /* !BFD_ASSEMBLER */
5186 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5188 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5191 relax_addressT segment_address_in_file;
5193 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5194 Out: GNU LD relocation length code: 0, 1, or 2. */
5196 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
5199 know (fixP->fx_addsy != NULL);
5201 md_number_to_chars (where,
5202 (valueT) (fixP->fx_frag->fr_address
5203 + fixP->fx_where - segment_address_in_file),
5206 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5207 ? S_GET_TYPE (fixP->fx_addsy)
5208 : fixP->fx_addsy->sy_number);
5210 where[6] = (r_symbolnum >> 16) & 0x0ff;
5211 where[5] = (r_symbolnum >> 8) & 0x0ff;
5212 where[4] = r_symbolnum & 0x0ff;
5213 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5214 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5215 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5218 #endif /* OBJ_AOUT or OBJ_BOUT. */
5220 #if defined (I386COFF)
5223 tc_coff_fix2rtype (fixP)
5226 if (fixP->fx_r_type == R_IMAGEBASE)
5229 return (fixP->fx_pcrel ?
5230 (fixP->fx_size == 1 ? R_PCRBYTE :
5231 fixP->fx_size == 2 ? R_PCRWORD :
5233 (fixP->fx_size == 1 ? R_RELBYTE :
5234 fixP->fx_size == 2 ? R_RELWORD :
5239 tc_coff_sizemachdep (frag)
5243 return (frag->fr_next->fr_address - frag->fr_address);
5248 #endif /* I386COFF */
5250 #endif /* !BFD_ASSEMBLER */
5252 /* Parse operands using Intel syntax. This implements a recursive descent
5253 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5256 FIXME: We do not recognize the full operand grammar defined in the MASM
5257 documentation. In particular, all the structure/union and
5258 high-level macro operands are missing.
5260 Uppercase words are terminals, lower case words are non-terminals.
5261 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5262 bars '|' denote choices. Most grammar productions are implemented in
5263 functions called 'intel_<production>'.
5265 Initial production is 'expr'.
5271 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5273 constant digits [[ radixOverride ]]
5275 dataType BYTE | WORD | DWORD | QWORD | XWORD
5308 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5309 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5311 hexdigit a | b | c | d | e | f
5312 | A | B | C | D | E | F
5322 register specialRegister
5326 segmentRegister CS | DS | ES | FS | GS | SS
5328 specialRegister CR0 | CR2 | CR3
5329 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5330 | TR3 | TR4 | TR5 | TR6 | TR7
5332 We simplify the grammar in obvious places (e.g., register parsing is
5333 done by calling parse_register) and eliminate immediate left recursion
5334 to implement a recursive-descent parser.
5374 /* Parsing structure for the intel syntax parser. Used to implement the
5375 semantic actions for the operand grammar. */
5376 struct intel_parser_s
5378 char *op_string; /* The string being parsed. */
5379 int got_a_float; /* Whether the operand is a float. */
5380 int op_modifier; /* Operand modifier. */
5381 int is_mem; /* 1 if operand is memory reference. */
5382 const reg_entry *reg; /* Last register reference found. */
5383 char *disp; /* Displacement string being built. */
5386 static struct intel_parser_s intel_parser;
5388 /* Token structure for parsing intel syntax. */
5391 int code; /* Token code. */
5392 const reg_entry *reg; /* Register entry for register tokens. */
5393 char *str; /* String representation. */
5396 static struct intel_token cur_token, prev_token;
5398 /* Token codes for the intel parser. Since T_SHORT is already used
5399 by COFF, undefine it first to prevent a warning. */
5414 /* Prototypes for intel parser functions. */
5415 static int intel_match_token PARAMS ((int code));
5416 static void intel_get_token PARAMS ((void));
5417 static void intel_putback_token PARAMS ((void));
5418 static int intel_expr PARAMS ((void));
5419 static int intel_e05 PARAMS ((void));
5420 static int intel_e05_1 PARAMS ((void));
5421 static int intel_e06 PARAMS ((void));
5422 static int intel_e06_1 PARAMS ((void));
5423 static int intel_e09 PARAMS ((void));
5424 static int intel_e09_1 PARAMS ((void));
5425 static int intel_e10 PARAMS ((void));
5426 static int intel_e10_1 PARAMS ((void));
5427 static int intel_e11 PARAMS ((void));
5430 i386_intel_operand (operand_string, got_a_float)
5431 char *operand_string;
5437 /* Initialize token holders. */
5438 cur_token.code = prev_token.code = T_NIL;
5439 cur_token.reg = prev_token.reg = NULL;
5440 cur_token.str = prev_token.str = NULL;
5442 /* Initialize parser structure. */
5443 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5446 strcpy (intel_parser.op_string, operand_string);
5447 intel_parser.got_a_float = got_a_float;
5448 intel_parser.op_modifier = -1;
5449 intel_parser.is_mem = 0;
5450 intel_parser.reg = NULL;
5451 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5452 if (intel_parser.disp == NULL)
5454 intel_parser.disp[0] = '\0';
5456 /* Read the first token and start the parser. */
5458 ret = intel_expr ();
5462 /* If we found a memory reference, hand it over to i386_displacement
5463 to fill in the rest of the operand fields. */
5464 if (intel_parser.is_mem)
5466 if ((i.mem_operands == 1
5467 && (current_templates->start->opcode_modifier & IsString) == 0)
5468 || i.mem_operands == 2)
5470 as_bad (_("too many memory references for '%s'"),
5471 current_templates->start->name);
5476 char *s = intel_parser.disp;
5479 /* Add the displacement expression. */
5481 ret = i386_displacement (s, s + strlen (s))
5482 && i386_index_check (s);
5486 /* Constant and OFFSET expressions are handled by i386_immediate. */
5487 else if (intel_parser.op_modifier == OFFSET_FLAT
5488 || intel_parser.reg == NULL)
5489 ret = i386_immediate (intel_parser.disp);
5493 free (intel_parser.disp);
5503 /* expr SHORT e05 */
5504 if (cur_token.code == T_SHORT)
5506 intel_parser.op_modifier = SHORT;
5507 intel_match_token (T_SHORT);
5509 return (intel_e05 ());
5514 return intel_e05 ();
5524 return (intel_e06 () && intel_e05_1 ());
5530 /* e05' addOp e06 e05' */
5531 if (cur_token.code == '+' || cur_token.code == '-')
5533 strcat (intel_parser.disp, cur_token.str);
5534 intel_match_token (cur_token.code);
5536 return (intel_e06 () && intel_e05_1 ());
5551 return (intel_e09 () && intel_e06_1 ());
5557 /* e06' mulOp e09 e06' */
5558 if (cur_token.code == '*' || cur_token.code == '/')
5560 strcat (intel_parser.disp, cur_token.str);
5561 intel_match_token (cur_token.code);
5563 return (intel_e09 () && intel_e06_1 ());
5571 /* e09 OFFSET e10 e09'
5580 /* e09 OFFSET e10 e09' */
5581 if (cur_token.code == T_OFFSET)
5583 intel_parser.is_mem = 0;
5584 intel_parser.op_modifier = OFFSET_FLAT;
5585 intel_match_token (T_OFFSET);
5587 return (intel_e10 () && intel_e09_1 ());
5592 return (intel_e10 () && intel_e09_1 ());
5598 /* e09' PTR e10 e09' */
5599 if (cur_token.code == T_PTR)
5601 if (prev_token.code == T_BYTE)
5602 i.suffix = BYTE_MNEM_SUFFIX;
5604 else if (prev_token.code == T_WORD)
5606 if (intel_parser.got_a_float == 2) /* "fi..." */
5607 i.suffix = SHORT_MNEM_SUFFIX;
5609 i.suffix = WORD_MNEM_SUFFIX;
5612 else if (prev_token.code == T_DWORD)
5614 if (intel_parser.got_a_float == 1) /* "f..." */
5615 i.suffix = SHORT_MNEM_SUFFIX;
5617 i.suffix = LONG_MNEM_SUFFIX;
5620 else if (prev_token.code == T_QWORD)
5622 if (intel_parser.got_a_float == 1) /* "f..." */
5623 i.suffix = LONG_MNEM_SUFFIX;
5625 i.suffix = QWORD_MNEM_SUFFIX;
5628 else if (prev_token.code == T_XWORD)
5629 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5633 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5637 intel_match_token (T_PTR);
5639 return (intel_e10 () && intel_e09_1 ());
5642 /* e09 : e10 e09' */
5643 else if (cur_token.code == ':')
5645 /* Mark as a memory operand only if it's not already known to be an
5646 offset expression. */
5647 if (intel_parser.op_modifier != OFFSET_FLAT)
5648 intel_parser.is_mem = 1;
5650 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5665 return (intel_e11 () && intel_e10_1 ());
5671 /* e10' [ expr ] e10' */
5672 if (cur_token.code == '[')
5674 intel_match_token ('[');
5676 /* Mark as a memory operand only if it's not already known to be an
5677 offset expression. If it's an offset expression, we need to keep
5679 if (intel_parser.op_modifier != OFFSET_FLAT)
5680 intel_parser.is_mem = 1;
5682 strcat (intel_parser.disp, "[");
5684 /* Add a '+' to the displacement string if necessary. */
5685 if (*intel_parser.disp != '\0'
5686 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5687 strcat (intel_parser.disp, "+");
5689 if (intel_expr () && intel_match_token (']'))
5691 /* Preserve brackets when the operand is an offset expression. */
5692 if (intel_parser.op_modifier == OFFSET_FLAT)
5693 strcat (intel_parser.disp, "]");
5695 return intel_e10_1 ();
5722 if (cur_token.code == '(')
5724 intel_match_token ('(');
5725 strcat (intel_parser.disp, "(");
5727 if (intel_expr () && intel_match_token (')'))
5729 strcat (intel_parser.disp, ")");
5737 else if (cur_token.code == '[')
5739 intel_match_token ('[');
5741 /* Mark as a memory operand only if it's not already known to be an
5742 offset expression. If it's an offset expression, we need to keep
5744 if (intel_parser.op_modifier != OFFSET_FLAT)
5745 intel_parser.is_mem = 1;
5747 strcat (intel_parser.disp, "[");
5749 /* Operands for jump/call inside brackets denote absolute addresses. */
5750 if (current_templates->start->opcode_modifier & Jump
5751 || current_templates->start->opcode_modifier & JumpDword
5752 || current_templates->start->opcode_modifier & JumpByte
5753 || current_templates->start->opcode_modifier & JumpInterSegment)
5754 i.types[this_operand] |= JumpAbsolute;
5756 /* Add a '+' to the displacement string if necessary. */
5757 if (*intel_parser.disp != '\0'
5758 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5759 strcat (intel_parser.disp, "+");
5761 if (intel_expr () && intel_match_token (']'))
5763 /* Preserve brackets when the operand is an offset expression. */
5764 if (intel_parser.op_modifier == OFFSET_FLAT)
5765 strcat (intel_parser.disp, "]");
5778 else if (cur_token.code == T_BYTE
5779 || cur_token.code == T_WORD
5780 || cur_token.code == T_DWORD
5781 || cur_token.code == T_QWORD
5782 || cur_token.code == T_XWORD)
5784 intel_match_token (cur_token.code);
5791 else if (cur_token.code == '$' || cur_token.code == '.')
5793 strcat (intel_parser.disp, cur_token.str);
5794 intel_match_token (cur_token.code);
5796 /* Mark as a memory operand only if it's not already known to be an
5797 offset expression. */
5798 if (intel_parser.op_modifier != OFFSET_FLAT)
5799 intel_parser.is_mem = 1;
5805 else if (cur_token.code == T_REG)
5807 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5809 intel_match_token (T_REG);
5811 /* Check for segment change. */
5812 if (cur_token.code == ':')
5814 if (reg->reg_type & (SReg2 | SReg3))
5816 switch (reg->reg_num)
5819 i.seg[i.mem_operands] = &es;
5822 i.seg[i.mem_operands] = &cs;
5825 i.seg[i.mem_operands] = &ss;
5828 i.seg[i.mem_operands] = &ds;
5831 i.seg[i.mem_operands] = &fs;
5834 i.seg[i.mem_operands] = &gs;
5840 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5845 /* Not a segment register. Check for register scaling. */
5846 else if (cur_token.code == '*')
5848 if (!intel_parser.is_mem)
5850 as_bad (_("Register scaling only allowed in memory operands."));
5854 /* What follows must be a valid scale. */
5855 if (intel_match_token ('*')
5856 && strchr ("01248", *cur_token.str))
5859 i.types[this_operand] |= BaseIndex;
5861 /* Set the scale after setting the register (otherwise,
5862 i386_scale will complain) */
5863 i386_scale (cur_token.str);
5864 intel_match_token (T_CONST);
5868 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5874 /* No scaling. If this is a memory operand, the register is either a
5875 base register (first occurrence) or an index register (second
5877 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5879 if (i.base_reg && i.index_reg)
5881 as_bad (_("Too many register references in memory operand.\n"));
5885 if (i.base_reg == NULL)
5890 i.types[this_operand] |= BaseIndex;
5893 /* Offset modifier. Add the register to the displacement string to be
5894 parsed as an immediate expression after we're done. */
5895 else if (intel_parser.op_modifier == OFFSET_FLAT)
5896 strcat (intel_parser.disp, reg->reg_name);
5898 /* It's neither base nor index nor offset. */
5901 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5902 i.op[this_operand].regs = reg;
5906 /* Since registers are not part of the displacement string (except
5907 when we're parsing offset operands), we may need to remove any
5908 preceding '+' from the displacement string. */
5909 if (*intel_parser.disp != '\0'
5910 && intel_parser.op_modifier != OFFSET_FLAT)
5912 char *s = intel_parser.disp;
5913 s += strlen (s) - 1;
5922 else if (cur_token.code == T_ID)
5924 /* Add the identifier to the displacement string. */
5925 strcat (intel_parser.disp, cur_token.str);
5926 intel_match_token (T_ID);
5928 /* The identifier represents a memory reference only if it's not
5929 preceded by an offset modifier. */
5930 if (intel_parser.op_modifier != OFFSET_FLAT)
5931 intel_parser.is_mem = 1;
5937 else if (cur_token.code == T_CONST
5938 || cur_token.code == '-'
5939 || cur_token.code == '+')
5943 /* Allow constants that start with `+' or `-'. */
5944 if (cur_token.code == '-' || cur_token.code == '+')
5946 strcat (intel_parser.disp, cur_token.str);
5947 intel_match_token (cur_token.code);
5948 if (cur_token.code != T_CONST)
5950 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5956 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5957 if (save_str == NULL)
5959 strcpy (save_str, cur_token.str);
5961 /* Get the next token to check for register scaling. */
5962 intel_match_token (cur_token.code);
5964 /* Check if this constant is a scaling factor for an index register. */
5965 if (cur_token.code == '*')
5967 if (intel_match_token ('*') && cur_token.code == T_REG)
5969 if (!intel_parser.is_mem)
5971 as_bad (_("Register scaling only allowed in memory operands."));
5975 /* The constant is followed by `* reg', so it must be
5977 if (strchr ("01248", *save_str))
5979 i.index_reg = cur_token.reg;
5980 i.types[this_operand] |= BaseIndex;
5982 /* Set the scale after setting the register (otherwise,
5983 i386_scale will complain) */
5984 i386_scale (save_str);
5985 intel_match_token (T_REG);
5987 /* Since registers are not part of the displacement
5988 string, we may need to remove any preceding '+' from
5989 the displacement string. */
5990 if (*intel_parser.disp != '\0')
5992 char *s = intel_parser.disp;
5993 s += strlen (s) - 1;
6006 /* The constant was not used for register scaling. Since we have
6007 already consumed the token following `*' we now need to put it
6008 back in the stream. */
6010 intel_putback_token ();
6013 /* Add the constant to the displacement string. */
6014 strcat (intel_parser.disp, save_str);
6020 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6024 /* Match the given token against cur_token. If they match, read the next
6025 token from the operand string. */
6027 intel_match_token (code)
6030 if (cur_token.code == code)
6037 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6042 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6047 const reg_entry *reg;
6048 struct intel_token new_token;
6050 new_token.code = T_NIL;
6051 new_token.reg = NULL;
6052 new_token.str = NULL;
6054 /* Free the memory allocated to the previous token and move
6055 cur_token to prev_token. */
6057 free (prev_token.str);
6059 prev_token = cur_token;
6061 /* Skip whitespace. */
6062 while (is_space_char (*intel_parser.op_string))
6063 intel_parser.op_string++;
6065 /* Return an empty token if we find nothing else on the line. */
6066 if (*intel_parser.op_string == '\0')
6068 cur_token = new_token;
6072 /* The new token cannot be larger than the remainder of the operand
6074 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6075 if (new_token.str == NULL)
6077 new_token.str[0] = '\0';
6079 if (strchr ("0123456789", *intel_parser.op_string))
6081 char *p = new_token.str;
6082 char *q = intel_parser.op_string;
6083 new_token.code = T_CONST;
6085 /* Allow any kind of identifier char to encompass floating point and
6086 hexadecimal numbers. */
6087 while (is_identifier_char (*q))
6091 /* Recognize special symbol names [0-9][bf]. */
6092 if (strlen (intel_parser.op_string) == 2
6093 && (intel_parser.op_string[1] == 'b'
6094 || intel_parser.op_string[1] == 'f'))
6095 new_token.code = T_ID;
6098 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6100 new_token.code = *intel_parser.op_string;
6101 new_token.str[0] = *intel_parser.op_string;
6102 new_token.str[1] = '\0';
6105 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6106 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6108 new_token.code = T_REG;
6109 new_token.reg = reg;
6111 if (*intel_parser.op_string == REGISTER_PREFIX)
6113 new_token.str[0] = REGISTER_PREFIX;
6114 new_token.str[1] = '\0';
6117 strcat (new_token.str, reg->reg_name);
6120 else if (is_identifier_char (*intel_parser.op_string))
6122 char *p = new_token.str;
6123 char *q = intel_parser.op_string;
6125 /* A '.' or '$' followed by an identifier char is an identifier.
6126 Otherwise, it's operator '.' followed by an expression. */
6127 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6129 new_token.code = *q;
6130 new_token.str[0] = *q;
6131 new_token.str[1] = '\0';
6135 while (is_identifier_char (*q) || *q == '@')
6139 if (strcasecmp (new_token.str, "BYTE") == 0)
6140 new_token.code = T_BYTE;
6142 else if (strcasecmp (new_token.str, "WORD") == 0)
6143 new_token.code = T_WORD;
6145 else if (strcasecmp (new_token.str, "DWORD") == 0)
6146 new_token.code = T_DWORD;
6148 else if (strcasecmp (new_token.str, "QWORD") == 0)
6149 new_token.code = T_QWORD;
6151 else if (strcasecmp (new_token.str, "XWORD") == 0)
6152 new_token.code = T_XWORD;
6154 else if (strcasecmp (new_token.str, "PTR") == 0)
6155 new_token.code = T_PTR;
6157 else if (strcasecmp (new_token.str, "SHORT") == 0)
6158 new_token.code = T_SHORT;
6160 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6162 new_token.code = T_OFFSET;
6164 /* ??? This is not mentioned in the MASM grammar but gcc
6165 makes use of it with -mintel-syntax. OFFSET may be
6166 followed by FLAT: */
6167 if (strncasecmp (q, " FLAT:", 6) == 0)
6168 strcat (new_token.str, " FLAT:");
6171 /* ??? This is not mentioned in the MASM grammar. */
6172 else if (strcasecmp (new_token.str, "FLAT") == 0)
6173 new_token.code = T_OFFSET;
6176 new_token.code = T_ID;
6181 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6183 intel_parser.op_string += strlen (new_token.str);
6184 cur_token = new_token;
6187 /* Put cur_token back into the token stream and make cur_token point to
6190 intel_putback_token ()
6192 intel_parser.op_string -= strlen (cur_token.str);
6193 free (cur_token.str);
6194 cur_token = prev_token;
6196 /* Forget prev_token. */
6197 prev_token.code = T_NIL;
6198 prev_token.reg = NULL;
6199 prev_token.str = NULL;