1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2024 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
34 #include "gen-sframe.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
38 #include "opcodes/i386-mnem.h"
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
46 #define DEFAULT_ARCH "i386"
51 #define INLINE __inline__
57 /* Prefixes will be emitted in the order defined below.
58 WAIT_PREFIX must be the first prefix since FWAIT is really is an
59 instruction, and so must come before any prefixes.
60 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
61 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
67 #define HLE_PREFIX REP_PREFIX
68 #define BND_PREFIX REP_PREFIX
70 #define REX_PREFIX 6 /* must come last. */
71 #define MAX_PREFIXES 7 /* max prefixes per opcode */
73 /* we define the syntax here (modulo base,index,scale syntax) */
74 #define REGISTER_PREFIX '%'
75 #define IMMEDIATE_PREFIX '$'
76 #define ABSOLUTE_PREFIX '*'
78 /* these are the instruction mnemonic suffixes in AT&T syntax or
79 memory operand size in Intel syntax. */
80 #define WORD_MNEM_SUFFIX 'w'
81 #define BYTE_MNEM_SUFFIX 'b'
82 #define SHORT_MNEM_SUFFIX 's'
83 #define LONG_MNEM_SUFFIX 'l'
84 #define QWORD_MNEM_SUFFIX 'q'
86 #define END_OF_INSN '\0'
88 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
90 /* This matches the C -> StaticRounding alias in the opcode table. */
91 #define commutative staticrounding
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len:8; /* arch string length */
133 bool skip:1; /* show_arch should skip this. */
134 enum processor_type type; /* arch type */
135 enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */
136 i386_cpu_flags enable; /* cpu feature enable flags */
137 i386_cpu_flags disable; /* cpu feature disable flags */
141 static void update_code_flag (int, int);
142 static void s_insn (int);
143 static void set_code_flag (int);
144 static void set_16bit_gcc_code_flag (int);
145 static void set_intel_syntax (int);
146 static void set_intel_mnemonic (int);
147 static void set_allow_index_reg (int);
148 static void set_check (int);
149 static void set_cpu_arch (int);
151 static void pe_directive_secrel (int);
152 static void pe_directive_secidx (int);
154 static void signed_cons (int);
155 static char *output_invalid (int c);
156 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
158 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
160 static int i386_att_operand (char *);
161 static int i386_intel_operand (char *, int);
162 static int i386_intel_simplify (expressionS *);
163 static int i386_intel_parse_name (const char *, expressionS *);
164 static const reg_entry *parse_register (const char *, char **);
165 static const char *parse_insn (const char *, char *, bool);
166 static char *parse_operands (char *, const char *);
167 static void swap_operands (void);
168 static void swap_2_operands (unsigned int, unsigned int);
169 static enum i386_flag_code i386_addressing_mode (void);
170 static void optimize_imm (void);
171 static bool optimize_disp (const insn_template *t);
172 static const insn_template *match_template (char);
173 static int check_string (void);
174 static int process_suffix (void);
175 static int check_byte_reg (void);
176 static int check_long_reg (void);
177 static int check_qword_reg (void);
178 static int check_word_reg (void);
179 static int finalize_imm (void);
180 static int process_operands (void);
181 static const reg_entry *build_modrm_byte (void);
182 static void output_insn (const struct last_insn *);
183 static void output_imm (fragS *, offsetT);
184 static void output_disp (fragS *, offsetT);
186 static void s_bss (int);
188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
189 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 /* GNU_PROPERTY_X86_ISA_1_USED. */
192 static unsigned int x86_isa_1_used;
193 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
194 static unsigned int x86_feature_2_used;
195 /* Generate x86 used ISA and feature properties. */
196 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
199 static const char *default_arch = DEFAULT_ARCH;
201 /* parse_register() returns this when a register alias cannot be used. */
202 static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0,
203 { Dw2Inval, Dw2Inval } };
205 static const reg_entry *reg_eax;
206 static const reg_entry *reg_ds;
207 static const reg_entry *reg_es;
208 static const reg_entry *reg_ss;
209 static const reg_entry *reg_st0;
210 static const reg_entry *reg_k0;
215 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
216 unsigned char bytes[4];
218 /* Destination or source register specifier. */
219 const reg_entry *register_specifier;
222 /* 'md_assemble ()' gathers together information and puts it into a
229 const reg_entry *regs;
234 no_error, /* Must be first. */
235 operand_size_mismatch,
236 operand_type_mismatch,
237 register_type_mismatch,
238 number_of_operands_mismatch,
239 invalid_instruction_suffix,
241 unsupported_with_intel_mnemonic,
243 unsupported_EGPR_for_addressing,
250 invalid_vsib_address,
251 invalid_vector_register_set,
252 invalid_tmm_register_set,
253 invalid_dest_and_src_register_set,
254 invalid_dest_register_set,
255 invalid_pseudo_prefix,
256 unsupported_vector_index_register,
257 unsupported_broadcast,
260 mask_not_on_destination,
263 unsupported_vector_size,
264 unsupported_rsp_register,
270 /* TM holds the template for the insn were currently assembling. */
273 /* SUFFIX holds the instruction size suffix for byte, word, dword
274 or qword, if given. */
277 /* OPCODE_LENGTH holds the number of base opcode bytes. */
278 unsigned char opcode_length;
280 /* OPERANDS gives the number of given operands. */
281 unsigned int operands;
283 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
284 of given register, displacement, memory operands and immediate
286 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
288 /* TYPES [i] is the type (see above #defines) which tells us how to
289 use OP[i] for the corresponding operand. */
290 i386_operand_type types[MAX_OPERANDS];
292 /* Displacement expression, immediate expression, or register for each
294 union i386_op op[MAX_OPERANDS];
296 /* Flags for operands. */
297 unsigned int flags[MAX_OPERANDS];
298 #define Operand_PCrel 1
299 #define Operand_Mem 2
300 #define Operand_Signed 4 /* .insn only */
302 /* Relocation type for operand */
303 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
305 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
306 the base index byte below. */
307 const reg_entry *base_reg;
308 const reg_entry *index_reg;
309 unsigned int log2_scale_factor;
311 /* SEG gives the seg_entries of this insn. They are zero unless
312 explicit segment overrides are given. */
313 const reg_entry *seg[2];
315 /* PREFIX holds all the given prefix opcodes (usually null).
316 PREFIXES is the number of prefix opcodes. */
317 unsigned int prefixes;
318 unsigned char prefix[MAX_PREFIXES];
320 /* .insn allows for reserved opcode spaces. */
321 unsigned char insn_opcode_space;
323 /* .insn also allows (requires) specifying immediate size. */
324 unsigned char imm_bits[MAX_OPERANDS];
326 /* Register is in low 3 bits of opcode. */
329 /* The operand to a branch insn indicates an absolute branch. */
332 /* The operand to a branch insn indicates a far branch. */
335 /* There is a memory operand of (%dx) which should be only used
336 with input/output instructions. */
337 bool input_output_operand;
339 /* Extended states. */
347 xstate_ymm = 1 << 2 | xstate_xmm,
349 xstate_zmm = 1 << 3 | xstate_ymm,
352 /* Use MASK state. */
356 /* Has GOTPC or TLS relocation. */
357 bool has_gotpc_tls_reloc;
359 /* RM and SIB are the modrm byte and the sib byte where the
360 addressing modes of this insn are encoded. */
368 /* Masking attributes.
370 The struct describes masking, applied to OPERAND in the instruction.
371 REG is a pointer to the corresponding mask register. ZEROING tells
372 whether merging or zeroing mask is used. */
373 struct Mask_Operation
375 const reg_entry *reg;
376 unsigned int zeroing;
377 /* The operand where this operation is associated. */
378 unsigned int operand;
381 /* Rounding control and SAE attributes. */
393 /* In Intel syntax the operand modifier form is supposed to be used, but
394 we continue to accept the immediate forms as well. */
398 /* Broadcasting attributes.
400 The struct describes broadcasting, applied to OPERAND. TYPE is
401 expresses the broadcast factor. */
402 struct Broadcast_Operation
404 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
407 /* Index of broadcasted operand. */
408 unsigned int operand;
410 /* Number of bytes to broadcast. */
414 /* Compressed disp8*N attribute. */
415 unsigned int memshift;
417 /* Prefer load or store in encoding. */
420 dir_encoding_default = 0,
426 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
429 disp_encoding_default = 0,
435 /* Prefer the REX byte in encoding. */
438 /* Prefer the REX2 prefix in encoding. */
441 /* Need to use an Egpr capable encoding (REX2 or EVEX). */
444 /* Disable instruction size optimization. */
447 /* How to encode vector instructions. */
450 vex_encoding_default = 0,
454 vex_encoding_evex512,
459 const char *rep_prefix;
462 const char *hle_prefix;
464 /* Have BND prefix. */
465 const char *bnd_prefix;
467 /* Have NOTRACK prefix. */
468 const char *notrack_prefix;
471 enum i386_error error;
474 typedef struct _i386_insn i386_insn;
476 /* Link RC type with corresponding string, that'll be looked for in
485 static const struct RC_name RC_NamesTable[] =
487 { rne, STRING_COMMA_LEN ("rn-sae") },
488 { rd, STRING_COMMA_LEN ("rd-sae") },
489 { ru, STRING_COMMA_LEN ("ru-sae") },
490 { rz, STRING_COMMA_LEN ("rz-sae") },
491 { saeonly, STRING_COMMA_LEN ("sae") },
494 /* To be indexed by segment register number. */
495 static const unsigned char i386_seg_prefixes[] = {
504 /* List of chars besides those in app.c:symbol_chars that can start an
505 operand. Used to prevent the scrubber eating vital white-space. */
506 const char extra_symbol_chars[] = "*%-([{}"
515 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
516 && !defined (TE_GNU) \
517 && !defined (TE_LINUX) \
518 && !defined (TE_Haiku) \
519 && !defined (TE_FreeBSD) \
520 && !defined (TE_DragonFly) \
521 && !defined (TE_NetBSD))
522 /* This array holds the chars that always start a comment. If the
523 pre-processor is disabled, these aren't very useful. The option
524 --divide will remove '/' from this list. */
525 const char *i386_comment_chars = "#/";
526 #define SVR4_COMMENT_CHARS 1
527 #define PREFIX_SEPARATOR '\\'
530 const char *i386_comment_chars = "#";
531 #define PREFIX_SEPARATOR '/'
534 /* This array holds the chars that only start a comment at the beginning of
535 a line. If the line seems to have the form '# 123 filename'
536 .line and .file directives will appear in the pre-processed output.
537 Note that input_file.c hand checks for '#' at the beginning of the
538 first line of the input file. This is because the compiler outputs
539 #NO_APP at the beginning of its output.
540 Also note that comments started like this one will always work if
541 '/' isn't otherwise defined. */
542 const char line_comment_chars[] = "#/";
544 const char line_separator_chars[] = ";";
546 /* Chars that can be used to separate mant from exp in floating point
548 const char EXP_CHARS[] = "eE";
550 /* Chars that mean this number is a floating point constant
553 const char FLT_CHARS[] = "fFdDxXhHbB";
555 /* Tables for lexical analysis. */
556 static char mnemonic_chars[256];
557 static char register_chars[256];
558 static char operand_chars[256];
560 /* Lexical macros. */
561 #define is_operand_char(x) (operand_chars[(unsigned char) x])
562 #define is_register_char(x) (register_chars[(unsigned char) x])
563 #define is_space_char(x) ((x) == ' ')
565 /* All non-digit non-letter characters that may occur in an operand and
566 which aren't already in extra_symbol_chars[]. */
567 static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]";
569 /* md_assemble() always leaves the strings it's passed unaltered. To
570 effect this we maintain a stack of saved characters that we've smashed
571 with '\0's (indicating end of strings for various sub-fields of the
572 assembler instruction). */
573 static char save_stack[32];
574 static char *save_stack_p;
575 #define END_STRING_AND_SAVE(s) \
576 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
577 #define RESTORE_END_STRING(s) \
578 do { *(s) = *--save_stack_p; } while (0)
580 /* The instruction we're assembling. */
583 /* Possible templates for current insn. */
584 static templates current_templates;
586 /* Per instruction expressionS buffers: max displacements & immediates. */
587 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
588 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
590 /* Current operand we are working on. */
591 static int this_operand = -1;
593 /* Are we processing a .insn directive? */
594 #define dot_insn() (i.tm.mnem_off == MN__insn)
596 enum i386_flag_code i386_flag_code;
597 #define flag_code i386_flag_code /* Permit to continue using original name. */
598 static unsigned int object_64bit;
599 static unsigned int disallow_64bit_reloc;
600 static int use_rela_relocations = 0;
601 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
602 static const char *tls_get_addr;
604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
606 /* The ELF ABI to use. */
614 static enum x86_elf_abi x86_elf_abi = I386_ABI;
617 #if defined (TE_PE) || defined (TE_PEP)
618 /* Use big object file format. */
619 static int use_big_obj = 0;
622 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
623 /* 1 if generating code for a shared library. */
624 static int shared = 0;
626 unsigned int x86_sframe_cfa_sp_reg;
627 /* The other CFA base register for SFrame stack trace info. */
628 unsigned int x86_sframe_cfa_fp_reg;
629 unsigned int x86_sframe_cfa_ra_reg;
633 /* 1 for intel syntax,
635 static int intel_syntax = 0;
637 static enum x86_64_isa
639 amd64 = 1, /* AMD64 ISA. */
640 intel64 /* Intel64 ISA. */
643 /* 1 for intel mnemonic,
644 0 if att mnemonic. */
645 static int intel_mnemonic = !SYSV386_COMPAT;
647 /* 1 if pseudo registers are permitted. */
648 static int allow_pseudo_reg = 0;
650 /* 1 if register prefix % not required. */
651 static int allow_naked_reg = 0;
653 /* 1 if the assembler should add BND prefix for all control-transferring
654 instructions supporting it, even if this prefix wasn't specified
656 static int add_bnd_prefix = 0;
658 /* 1 if pseudo index register, eiz/riz, is allowed . */
659 static int allow_index_reg = 0;
661 /* 1 if the assembler should ignore LOCK prefix, even if it was
662 specified explicitly. */
663 static int omit_lock_prefix = 0;
665 /* 1 if the assembler should encode lfence, mfence, and sfence as
666 "lock addl $0, (%{re}sp)". */
667 static int avoid_fence = 0;
669 /* 1 if lfence should be inserted after every load. */
670 static int lfence_after_load = 0;
672 /* Non-zero if lfence should be inserted before indirect branch. */
673 static enum lfence_before_indirect_branch_kind
675 lfence_branch_none = 0,
676 lfence_branch_register,
677 lfence_branch_memory,
680 lfence_before_indirect_branch;
682 /* Non-zero if lfence should be inserted before ret. */
683 static enum lfence_before_ret_kind
685 lfence_before_ret_none = 0,
686 lfence_before_ret_not,
687 lfence_before_ret_or,
688 lfence_before_ret_shl
692 /* 1 if the assembler should generate relax relocations. */
694 static int generate_relax_relocations
695 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
697 static enum check_kind
703 sse_check, operand_check = check_warning;
705 /* Non-zero if branches should be aligned within power of 2 boundary. */
706 static int align_branch_power = 0;
708 /* Types of branches to align. */
709 enum align_branch_kind
711 align_branch_none = 0,
712 align_branch_jcc = 1,
713 align_branch_fused = 2,
714 align_branch_jmp = 3,
715 align_branch_call = 4,
716 align_branch_indirect = 5,
720 /* Type bits of branches to align. */
721 enum align_branch_bit
723 align_branch_jcc_bit = 1 << align_branch_jcc,
724 align_branch_fused_bit = 1 << align_branch_fused,
725 align_branch_jmp_bit = 1 << align_branch_jmp,
726 align_branch_call_bit = 1 << align_branch_call,
727 align_branch_indirect_bit = 1 << align_branch_indirect,
728 align_branch_ret_bit = 1 << align_branch_ret
731 static unsigned int align_branch = (align_branch_jcc_bit
732 | align_branch_fused_bit
733 | align_branch_jmp_bit);
735 /* Types of condition jump used by macro-fusion. */
738 mf_jcc_jo = 0, /* base opcode 0x70 */
739 mf_jcc_jc, /* base opcode 0x72 */
740 mf_jcc_je, /* base opcode 0x74 */
741 mf_jcc_jna, /* base opcode 0x76 */
742 mf_jcc_js, /* base opcode 0x78 */
743 mf_jcc_jp, /* base opcode 0x7a */
744 mf_jcc_jl, /* base opcode 0x7c */
745 mf_jcc_jle, /* base opcode 0x7e */
748 /* Types of compare flag-modifying insntructions used by macro-fusion. */
751 mf_cmp_test_and, /* test/cmp */
752 mf_cmp_alu_cmp, /* add/sub/cmp */
753 mf_cmp_incdec /* inc/dec */
756 /* The maximum padding size for fused jcc. CMP like instruction can
757 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
759 #define MAX_FUSED_JCC_PADDING_SIZE 20
761 /* The maximum number of prefixes added for an instruction. */
762 static unsigned int align_branch_prefix_size = 5;
765 1. Clear the REX_W bit with register operand if possible.
766 2. Above plus use 128bit vector instruction to clear the full vector
769 static int optimize = 0;
772 1. Clear the REX_W bit with register operand if possible.
773 2. Above plus use 128bit vector instruction to clear the full vector
775 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
778 static int optimize_for_space = 0;
780 /* Register prefix used for error message. */
781 static const char *register_prefix = "%";
783 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
784 leave, push, and pop instructions so that gcc has the same stack
785 frame as in 32 bit mode. */
786 static char stackop_size = '\0';
788 /* Non-zero to optimize code alignment. */
789 int optimize_align_code = 1;
791 /* Non-zero to quieten some warnings. */
792 static int quiet_warnings = 0;
794 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
795 static bool pre_386_16bit_warned;
798 static const char *cpu_arch_name = NULL;
799 static char *cpu_sub_arch_name = NULL;
801 /* CPU feature flags. */
802 i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
804 /* ISA extensions available in 64-bit mode only. */
805 static const i386_cpu_flags cpu_64_flags = CPU_ANY_64_FLAGS;
807 /* If we have selected a cpu we are generating instructions for. */
808 static int cpu_arch_tune_set = 0;
810 /* Cpu we are generating instructions for. */
811 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
813 /* CPU instruction set architecture used. */
814 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
816 /* CPU feature flags of instruction set architecture used. */
817 i386_cpu_flags cpu_arch_isa_flags;
819 /* If set, conditional jumps are not automatically promoted to handle
820 larger than a byte offset. */
821 static bool no_cond_jump_promotion = false;
823 /* This will be set from an expression parser hook if there's any
824 applicable operator involved in an expression. */
827 expr_operator_present,
831 /* Encode SSE instructions with VEX prefix. */
832 static unsigned int sse2avx;
834 /* Encode aligned vector move as unaligned vector move. */
835 static unsigned int use_unaligned_vector_move;
837 /* Maximum permitted vector size. */
841 #define VSZ_DEFAULT VSZ512
842 static unsigned int vector_size = VSZ_DEFAULT;
844 /* Encode scalar AVX instructions with specific vector length. */
851 /* Encode VEX WIG instructions with specific vex.w. */
858 /* Encode scalar EVEX LIG instructions with specific vector length. */
866 /* Encode EVEX WIG instructions with specific evex.w. */
873 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
874 static enum rc_type evexrcig = rne;
876 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
877 static symbolS *GOT_symbol;
879 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
880 unsigned int x86_dwarf2_return_column;
882 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
883 int x86_cie_data_alignment;
885 /* Interface to relax_segment.
886 There are 3 major relax states for 386 jump insns because the
887 different types of jumps add different sizes to frags when we're
888 figuring out what sort of jump to choose to reach a given label.
890 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
891 branches which are handled by md_estimate_size_before_relax() and
892 i386_generic_table_relax_frag(). */
895 #define UNCOND_JUMP 0
897 #define COND_JUMP86 2
898 #define BRANCH_PADDING 3
899 #define BRANCH_PREFIX 4
900 #define FUSED_JCC_PADDING 5
905 #define SMALL16 (SMALL | CODE16)
907 #define BIG16 (BIG | CODE16)
911 #define INLINE __inline__
917 #define ENCODE_RELAX_STATE(type, size) \
918 ((relax_substateT) (((type) << 2) | (size)))
919 #define TYPE_FROM_RELAX_STATE(s) \
921 #define DISP_SIZE_FROM_RELAX_STATE(s) \
922 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
924 /* This table is used by relax_frag to promote short jumps to long
925 ones where necessary. SMALL (short) jumps may be promoted to BIG
926 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
927 don't allow a short jump in a 32 bit code segment to be promoted to
928 a 16 bit offset jump because it's slower (requires data size
929 prefix), and doesn't work, unless the destination is in the bottom
930 64k of the code segment (The top 16 bits of eip are zeroed). */
932 const relax_typeS md_relax_table[] =
935 1) most positive reach of this state,
936 2) most negative reach of this state,
937 3) how many bytes this mode will have in the variable part of the frag
938 4) which index into the table to try if we can't fit into this one. */
940 /* UNCOND_JUMP states. */
941 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
942 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
943 /* dword jmp adds 4 bytes to frag:
944 0 extra opcode bytes, 4 displacement bytes. */
946 /* word jmp adds 2 byte2 to frag:
947 0 extra opcode bytes, 2 displacement bytes. */
950 /* COND_JUMP states. */
951 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
952 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
953 /* dword conditionals adds 5 bytes to frag:
954 1 extra opcode byte, 4 displacement bytes. */
956 /* word conditionals add 3 bytes to frag:
957 1 extra opcode byte, 2 displacement bytes. */
960 /* COND_JUMP86 states. */
961 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
962 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
963 /* dword conditionals adds 5 bytes to frag:
964 1 extra opcode byte, 4 displacement bytes. */
966 /* word conditionals add 4 bytes to frag:
967 1 displacement byte and a 3 byte long branch insn. */
971 #define ARCH(n, t, f, s) \
972 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
974 #define SUBARCH(n, e, d, s) \
975 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
976 CPU_ ## d ## _FLAGS }
977 #define VECARCH(n, e, d, v) \
978 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
979 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
981 static const arch_entry cpu_arch[] =
983 /* Do not replace the first two entries - i386_target_format() and
984 set_cpu_arch() rely on them being there in this order. */
985 ARCH (generic32, GENERIC32, GENERIC32, false),
986 ARCH (generic64, GENERIC64, GENERIC64, false),
987 ARCH (i8086, UNKNOWN, NONE, false),
988 ARCH (i186, UNKNOWN, 186, false),
989 ARCH (i286, UNKNOWN, 286, false),
990 ARCH (i386, I386, 386, false),
991 ARCH (i486, I486, 486, false),
992 ARCH (i586, PENTIUM, 586, false),
993 ARCH (pentium, PENTIUM, 586, false),
994 ARCH (i686, I686, 686, false),
995 ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false),
996 ARCH (pentiumii, PENTIUMPRO, P2, false),
997 ARCH (pentiumiii, PENTIUMPRO, P3, false),
998 ARCH (pentium4, PENTIUM4, P4, false),
999 ARCH (prescott, NOCONA, CORE, false),
1000 ARCH (nocona, NOCONA, NOCONA, false),
1001 ARCH (yonah, CORE, CORE, true),
1002 ARCH (core, CORE, CORE, false),
1003 ARCH (merom, CORE2, CORE2, true),
1004 ARCH (core2, CORE2, CORE2, false),
1005 ARCH (corei7, COREI7, COREI7, false),
1006 ARCH (iamcu, IAMCU, IAMCU, false),
1007 ARCH (k6, K6, K6, false),
1008 ARCH (k6_2, K6, K6_2, false),
1009 ARCH (athlon, ATHLON, ATHLON, false),
1010 ARCH (sledgehammer, K8, K8, true),
1011 ARCH (opteron, K8, K8, false),
1012 ARCH (k8, K8, K8, false),
1013 ARCH (amdfam10, AMDFAM10, AMDFAM10, false),
1014 ARCH (bdver1, BD, BDVER1, false),
1015 ARCH (bdver2, BD, BDVER2, false),
1016 ARCH (bdver3, BD, BDVER3, false),
1017 ARCH (bdver4, BD, BDVER4, false),
1018 ARCH (znver1, ZNVER, ZNVER1, false),
1019 ARCH (znver2, ZNVER, ZNVER2, false),
1020 ARCH (znver3, ZNVER, ZNVER3, false),
1021 ARCH (znver4, ZNVER, ZNVER4, false),
1022 ARCH (znver5, ZNVER, ZNVER5, false),
1023 ARCH (btver1, BT, BTVER1, false),
1024 ARCH (btver2, BT, BTVER2, false),
1026 SUBARCH (8087, 8087, ANY_8087, false),
1027 SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */
1028 SUBARCH (287, 287, ANY_287, false),
1029 SUBARCH (387, 387, ANY_387, false),
1030 SUBARCH (687, 687, ANY_687, false),
1031 SUBARCH (cmov, CMOV, CMOV, false),
1032 SUBARCH (fxsr, FXSR, ANY_FXSR, false),
1033 SUBARCH (mmx, MMX, ANY_MMX, false),
1034 SUBARCH (sse, SSE, ANY_SSE, false),
1035 SUBARCH (sse2, SSE2, ANY_SSE2, false),
1036 SUBARCH (sse3, SSE3, ANY_SSE3, false),
1037 SUBARCH (sse4a, SSE4A, ANY_SSE4A, false),
1038 SUBARCH (ssse3, SSSE3, ANY_SSSE3, false),
1039 SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false),
1040 SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false),
1041 SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false),
1042 VECARCH (avx, AVX, ANY_AVX, reset),
1043 VECARCH (avx2, AVX2, ANY_AVX2, reset),
1044 VECARCH (avx512f, AVX512F, ANY_AVX512F, reset),
1045 VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset),
1046 VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset),
1047 VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset),
1048 VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset),
1049 VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset),
1050 VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset),
1051 SUBARCH (monitor, MONITOR, MONITOR, false),
1052 SUBARCH (vmx, VMX, ANY_VMX, false),
1053 SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false),
1054 SUBARCH (smx, SMX, SMX, false),
1055 SUBARCH (xsave, XSAVE, ANY_XSAVE, false),
1056 SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false),
1057 SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false),
1058 SUBARCH (xsaves, XSAVES, ANY_XSAVES, false),
1059 SUBARCH (aes, AES, ANY_AES, false),
1060 SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false),
1061 SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true),
1062 SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false),
1063 SUBARCH (rdrnd, RDRND, RDRND, false),
1064 SUBARCH (f16c, F16C, ANY_F16C, false),
1065 SUBARCH (bmi2, BMI2, BMI2, false),
1066 SUBARCH (fma, FMA, ANY_FMA, false),
1067 SUBARCH (fma4, FMA4, ANY_FMA4, false),
1068 SUBARCH (xop, XOP, ANY_XOP, false),
1069 SUBARCH (lwp, LWP, ANY_LWP, false),
1070 SUBARCH (movbe, MOVBE, MOVBE, false),
1071 SUBARCH (cx16, CX16, CX16, false),
1072 SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false),
1073 SUBARCH (ept, EPT, ANY_EPT, false),
1074 SUBARCH (lzcnt, LZCNT, LZCNT, false),
1075 SUBARCH (popcnt, POPCNT, POPCNT, false),
1076 SUBARCH (hle, HLE, HLE, false),
1077 SUBARCH (rtm, RTM, ANY_RTM, false),
1078 SUBARCH (tsx, TSX, TSX, false),
1079 SUBARCH (invpcid, INVPCID, INVPCID, false),
1080 SUBARCH (clflush, CLFLUSH, CLFLUSH, false),
1081 SUBARCH (nop, NOP, NOP, false),
1082 SUBARCH (syscall, SYSCALL, SYSCALL, false),
1083 SUBARCH (rdtscp, RDTSCP, RDTSCP, false),
1084 SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false),
1085 SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false),
1086 SUBARCH (padlock, PADLOCK, PADLOCK, false),
1087 SUBARCH (pacifica, SVME, ANY_SVME, true),
1088 SUBARCH (svme, SVME, ANY_SVME, false),
1089 SUBARCH (abm, ABM, ABM, false),
1090 SUBARCH (bmi, BMI, BMI, false),
1091 SUBARCH (tbm, TBM, TBM, false),
1092 SUBARCH (adx, ADX, ADX, false),
1093 SUBARCH (rdseed, RDSEED, RDSEED, false),
1094 SUBARCH (prfchw, PRFCHW, PRFCHW, false),
1095 SUBARCH (smap, SMAP, SMAP, false),
1096 SUBARCH (mpx, MPX, ANY_MPX, false),
1097 SUBARCH (sha, SHA, ANY_SHA, false),
1098 SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false),
1099 SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false),
1100 SUBARCH (se1, SE1, SE1, false),
1101 SUBARCH (clwb, CLWB, CLWB, false),
1102 VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset),
1103 VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset),
1104 VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset),
1105 VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset),
1106 VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset),
1107 VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset),
1108 VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset),
1109 VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset),
1110 VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset),
1111 SUBARCH (clzero, CLZERO, CLZERO, false),
1112 SUBARCH (mwaitx, MWAITX, MWAITX, false),
1113 SUBARCH (ospke, OSPKE, ANY_OSPKE, false),
1114 SUBARCH (rdpid, RDPID, RDPID, false),
1115 SUBARCH (ptwrite, PTWRITE, PTWRITE, false),
1116 SUBARCH (ibt, IBT, IBT, false),
1117 SUBARCH (shstk, SHSTK, SHSTK, false),
1118 SUBARCH (gfni, GFNI, ANY_GFNI, false),
1119 VECARCH (vaes, VAES, ANY_VAES, reset),
1120 VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset),
1121 SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false),
1122 SUBARCH (pconfig, PCONFIG, PCONFIG, false),
1123 SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
1124 SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
1125 SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
1126 SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
1127 SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
1128 SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false),
1129 SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false),
1130 SUBARCH (movdiri, MOVDIRI, MOVDIRI, false),
1131 SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false),
1132 VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
1133 VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
1134 ANY_AVX512_VP2INTERSECT, reset),
1135 SUBARCH (tdx, TDX, TDX, false),
1136 SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
1137 SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
1138 SUBARCH (rdpru, RDPRU, RDPRU, false),
1139 SUBARCH (mcommit, MCOMMIT, MCOMMIT, false),
1140 SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false),
1141 SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false),
1142 SUBARCH (kl, KL, ANY_KL, false),
1143 SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false),
1144 SUBARCH (uintr, UINTR, UINTR, false),
1145 SUBARCH (hreset, HRESET, HRESET, false),
1146 VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset),
1147 SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
1148 VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset),
1149 VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset),
1150 SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false),
1151 SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
1152 SUBARCH (msrlist, MSRLIST, MSRLIST, false),
1153 VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset),
1154 SUBARCH (rao_int, RAO_INT, RAO_INT, false),
1155 SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
1156 SUBARCH (fred, FRED, ANY_FRED, false),
1157 SUBARCH (lkgs, LKGS, ANY_LKGS, false),
1158 VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset),
1159 VECARCH (sha512, SHA512, ANY_SHA512, reset),
1160 VECARCH (sm3, SM3, ANY_SM3, reset),
1161 VECARCH (sm4, SM4, ANY_SM4, reset),
1162 SUBARCH (pbndkb, PBNDKB, PBNDKB, false),
1163 VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
1164 SUBARCH (user_msr, USER_MSR, USER_MSR, false),
1165 SUBARCH (apx_f, APX_F, APX_F, false),
1172 /* Like s_lcomm_internal in gas/read.c but the alignment string
1173 is allowed to be optional. */
1176 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1183 && *input_line_pointer == ',')
1185 align = parse_align (needs_align - 1);
1187 if (align == (addressT) -1)
1202 bss_alloc (symbolP, size, align);
1207 pe_lcomm (int needs_align)
1209 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1213 const pseudo_typeS md_pseudo_table[] =
1215 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1216 {"align", s_align_bytes, 0},
1218 {"align", s_align_ptwo, 0},
1220 {"arch", set_cpu_arch, 0},
1225 {"lcomm", pe_lcomm, 1},
1227 {"ffloat", float_cons, 'f'},
1228 {"dfloat", float_cons, 'd'},
1229 {"tfloat", float_cons, 'x'},
1230 {"hfloat", float_cons, 'h'},
1231 {"bfloat16", float_cons, 'b'},
1233 {"slong", signed_cons, 4},
1234 {"insn", s_insn, 0},
1235 {"noopt", s_ignore, 0},
1236 {"optim", s_ignore, 0},
1237 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1238 {"code16", set_code_flag, CODE_16BIT},
1239 {"code32", set_code_flag, CODE_32BIT},
1241 {"code64", set_code_flag, CODE_64BIT},
1243 {"intel_syntax", set_intel_syntax, 1},
1244 {"att_syntax", set_intel_syntax, 0},
1245 {"intel_mnemonic", set_intel_mnemonic, 1},
1246 {"att_mnemonic", set_intel_mnemonic, 0},
1247 {"allow_index_reg", set_allow_index_reg, 1},
1248 {"disallow_index_reg", set_allow_index_reg, 0},
1249 {"sse_check", set_check, 0},
1250 {"operand_check", set_check, 1},
1251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1252 {"largecomm", handle_large_common, 0},
1254 {"file", dwarf2_directive_file, 0},
1255 {"loc", dwarf2_directive_loc, 0},
1256 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1259 {"secrel32", pe_directive_secrel, 0},
1260 {"secidx", pe_directive_secidx, 0},
1265 /* For interface with expression (). */
1266 extern char *input_line_pointer;
1268 /* Hash table for instruction mnemonic lookup. */
1269 static htab_t op_hash;
1271 /* Hash table for register lookup. */
1272 static htab_t reg_hash;
1274 /* Various efficient no-op patterns for aligning code labels.
1275 Note: Don't try to assemble the instructions in the comments.
1276 0L and 0w are not legal. */
1277 static const unsigned char f32_1[] =
1279 static const unsigned char f32_2[] =
1280 {0x66,0x90}; /* xchg %ax,%ax */
1281 static const unsigned char f32_3[] =
1282 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1283 #define f32_4 (f32_5 + 1) /* leal 0(%esi,%eiz),%esi */
1284 static const unsigned char f32_5[] =
1285 {0x2e,0x8d,0x74,0x26,0x00}; /* leal %cs:0(%esi,%eiz),%esi */
1286 static const unsigned char f32_6[] =
1287 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1288 #define f32_7 (f32_8 + 1) /* leal 0L(%esi,%eiz),%esi */
1289 static const unsigned char f32_8[] =
1290 {0x2e,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal %cs:0L(%esi,%eiz),%esi */
1291 static const unsigned char f64_3[] =
1292 {0x48,0x89,0xf6}; /* mov %rsi,%rsi */
1293 static const unsigned char f64_4[] =
1294 {0x48,0x8d,0x76,0x00}; /* lea 0(%rsi),%rsi */
1295 #define f64_5 (f64_6 + 1) /* lea 0(%rsi,%riz),%rsi */
1296 static const unsigned char f64_6[] =
1297 {0x2e,0x48,0x8d,0x74,0x26,0x00}; /* lea %cs:0(%rsi,%riz),%rsi */
1298 static const unsigned char f64_7[] =
1299 {0x48,0x8d,0xb6,0x00,0x00,0x00,0x00}; /* lea 0L(%rsi),%rsi */
1300 #define f64_8 (f64_9 + 1) /* lea 0L(%rsi,%riz),%rsi */
1301 static const unsigned char f64_9[] =
1302 {0x2e,0x48,0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* lea %cs:0L(%rsi,%riz),%rsi */
1303 #define f16_2 (f64_3 + 1) /* mov %si,%si */
1304 static const unsigned char f16_3[] =
1305 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1306 #define f16_4 (f16_5 + 1) /* lea 0W(%si),%si */
1307 static const unsigned char f16_5[] =
1308 {0x2e,0x8d,0xb4,0x00,0x00}; /* lea %cs:0W(%si),%si */
1309 static const unsigned char jump_disp8[] =
1310 {0xeb}; /* jmp disp8 */
1311 static const unsigned char jump32_disp32[] =
1312 {0xe9}; /* jmp disp32 */
1313 static const unsigned char jump16_disp32[] =
1314 {0x66,0xe9}; /* jmp disp32 */
1315 /* 32-bit NOPs patterns. */
1316 static const unsigned char *const f32_patt[] = {
1317 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8
1319 /* 64-bit NOPs patterns. */
1320 static const unsigned char *const f64_patt[] = {
1321 f32_1, f32_2, f64_3, f64_4, f64_5, f64_6, f64_7, f64_8, f64_9
1323 /* 16-bit NOPs patterns. */
1324 static const unsigned char *const f16_patt[] = {
1325 f32_1, f16_2, f16_3, f16_4, f16_5
1327 /* nopl (%[re]ax) */
1328 static const unsigned char alt_3[] =
1330 /* nopl 0(%[re]ax) */
1331 static const unsigned char alt_4[] =
1332 {0x0f,0x1f,0x40,0x00};
1333 /* nopl 0(%[re]ax,%[re]ax,1) */
1334 #define alt_5 (alt_6 + 1)
1335 /* nopw 0(%[re]ax,%[re]ax,1) */
1336 static const unsigned char alt_6[] =
1337 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1338 /* nopl 0L(%[re]ax) */
1339 static const unsigned char alt_7[] =
1340 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1341 /* nopl 0L(%[re]ax,%[re]ax,1) */
1342 #define alt_8 (alt_9 + 1)
1343 /* nopw 0L(%[re]ax,%[re]ax,1) */
1344 static const unsigned char alt_9[] =
1345 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1346 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1347 #define alt_10 (alt_11 + 1)
1348 /* data16 nopw %cs:0L(%eax,%eax,1) */
1349 static const unsigned char alt_11[] =
1350 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1351 /* 32-bit and 64-bit NOPs patterns. */
1352 static const unsigned char *const alt_patt[] = {
1353 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1354 alt_9, alt_10, alt_11
1357 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1358 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1361 i386_output_nops (char *where, const unsigned char *const *patt,
1362 int count, int max_single_nop_size)
1365 /* Place the longer NOP first. */
1368 const unsigned char *nops;
1370 if (max_single_nop_size < 1)
1372 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1373 max_single_nop_size);
1377 nops = patt[max_single_nop_size - 1];
1378 last = count % max_single_nop_size;
1381 for (offset = 0; offset < count; offset += max_single_nop_size)
1382 memcpy (where + offset, nops, max_single_nop_size);
1386 nops = patt[last - 1];
1387 memcpy (where + offset, nops, last);
1392 fits_in_imm7 (offsetT num)
1394 return (num & 0x7f) == num;
1398 fits_in_imm31 (offsetT num)
1400 return (num & 0x7fffffff) == num;
1403 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1404 single NOP instruction LIMIT. */
1407 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1409 const unsigned char *const *patt = NULL;
1410 int max_single_nop_size;
1411 /* Maximum number of NOPs before switching to jump over NOPs. */
1412 int max_number_of_nops;
1414 switch (fragP->fr_type)
1419 case rs_machine_dependent:
1420 /* Allow NOP padding for jumps and calls. */
1421 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
1422 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
1429 /* We need to decide which NOP sequence to use for 32bit and
1430 64bit. When -mtune= is used:
1432 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1433 PROCESSOR_GENERIC32, f32_patt will be used.
1434 2. For the rest, alt_patt will be used.
1436 When -mtune= isn't used, alt_patt will be used if
1437 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1440 When -march= or .arch is used, we can't use anything beyond
1441 cpu_arch_isa_flags. */
1443 if (fragP->tc_frag_data.code == CODE_16BIT)
1446 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1447 /* Limit number of NOPs to 2 in 16-bit mode. */
1448 max_number_of_nops = 2;
1452 patt = fragP->tc_frag_data.code == CODE_64BIT ? f64_patt : f32_patt;
1453 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1455 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1456 explicitly disabled. */
1457 switch (fragP->tc_frag_data.tune)
1459 case PROCESSOR_UNKNOWN:
1460 /* We use cpu_arch_isa_flags to check if we SHOULD
1461 optimize with nops. */
1462 if (fragP->tc_frag_data.isanop)
1466 case PROCESSOR_PENTIUMPRO:
1467 case PROCESSOR_PENTIUM4:
1468 case PROCESSOR_NOCONA:
1469 case PROCESSOR_CORE:
1470 case PROCESSOR_CORE2:
1471 case PROCESSOR_COREI7:
1472 case PROCESSOR_GENERIC64:
1474 case PROCESSOR_ATHLON:
1476 case PROCESSOR_AMDFAM10:
1478 case PROCESSOR_ZNVER:
1480 if (fragP->tc_frag_data.cpunop)
1484 case PROCESSOR_I386:
1485 case PROCESSOR_I486:
1486 case PROCESSOR_PENTIUM:
1487 case PROCESSOR_I686:
1488 case PROCESSOR_IAMCU:
1489 case PROCESSOR_GENERIC32:
1491 case PROCESSOR_NONE:
1497 switch (fragP->tc_frag_data.tune)
1499 case PROCESSOR_UNKNOWN:
1500 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1501 PROCESSOR_UNKNOWN. */
1506 /* We use cpu_arch_isa_flags to check if we CAN optimize
1508 if (fragP->tc_frag_data.isanop)
1512 case PROCESSOR_NONE:
1517 if (patt != alt_patt)
1519 max_single_nop_size = patt == f32_patt ? ARRAY_SIZE (f32_patt)
1520 : ARRAY_SIZE (f64_patt);
1521 /* Limit number of NOPs to 2 for older processors. */
1522 max_number_of_nops = 2;
1526 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1527 /* Limit number of NOPs to 7 for newer processors. */
1528 max_number_of_nops = 7;
1533 limit = max_single_nop_size;
1535 if (fragP->fr_type == rs_fill_nop)
1537 /* Output NOPs for .nop directive. */
1538 if (limit > max_single_nop_size)
1540 as_bad_where (fragP->fr_file, fragP->fr_line,
1541 _("invalid single nop size: %d "
1542 "(expect within [0, %d])"),
1543 limit, max_single_nop_size);
1547 else if (fragP->fr_type != rs_machine_dependent)
1548 fragP->fr_var = count;
1550 /* Emit a plain NOP first when the last thing we saw may not have been
1551 a proper instruction (e.g. a stand-alone prefix or .byte). */
1552 if (!fragP->tc_frag_data.last_insn_normal)
1558 if ((count / max_single_nop_size) > max_number_of_nops)
1560 /* Generate jump over NOPs. */
1561 offsetT disp = count - 2;
1562 if (fits_in_imm7 (disp))
1564 /* Use "jmp disp8" if possible. */
1566 where[0] = jump_disp8[0];
1572 unsigned int size_of_jump;
1574 if (flag_code == CODE_16BIT)
1576 where[0] = jump16_disp32[0];
1577 where[1] = jump16_disp32[1];
1582 where[0] = jump32_disp32[0];
1586 count -= size_of_jump + 4;
1587 if (!fits_in_imm31 (count))
1589 as_bad_where (fragP->fr_file, fragP->fr_line,
1590 _("jump over nop padding out of range"));
1594 md_number_to_chars (where + size_of_jump, count, 4);
1595 where += size_of_jump + 4;
1599 /* Generate multiple NOPs. */
1600 i386_output_nops (where, patt, count, limit);
1604 operand_type_all_zero (const union i386_operand_type *x)
1606 switch (ARRAY_SIZE(x->array))
1617 return !x->array[0];
1624 operand_type_set (union i386_operand_type *x, unsigned int v)
1626 switch (ARRAY_SIZE(x->array))
1642 x->bitfield.class = ClassNone;
1643 x->bitfield.instance = InstanceNone;
1647 operand_type_equal (const union i386_operand_type *x,
1648 const union i386_operand_type *y)
1650 switch (ARRAY_SIZE(x->array))
1653 if (x->array[2] != y->array[2])
1657 if (x->array[1] != y->array[1])
1661 return x->array[0] == y->array[0];
1669 _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
1673 case Cpu287: return a->bitfield.cpu287;
1674 case Cpu387: return a->bitfield.cpu387;
1675 case Cpu3dnow: return a->bitfield.cpu3dnow;
1676 case Cpu3dnowA: return a->bitfield.cpu3dnowa;
1677 case CpuAVX: return a->bitfield.cpuavx;
1678 case CpuHLE: return a->bitfield.cpuhle;
1679 case CpuAVX512F: return a->bitfield.cpuavx512f;
1680 case CpuAVX512VL: return a->bitfield.cpuavx512vl;
1681 case CpuAPX_F: return a->bitfield.cpuapx_f;
1682 case Cpu64: return a->bitfield.cpu64;
1683 case CpuNo64: return a->bitfield.cpuno64;
1685 gas_assert (cpu < CpuAttrEnums);
1687 return a->bitfield.isa == cpu + 1u;
1691 is_cpu (const insn_template *t, enum i386_cpu cpu)
1693 return _is_cpu(&t->cpu, cpu);
1697 maybe_cpu (const insn_template *t, enum i386_cpu cpu)
1699 return _is_cpu(&t->cpu_any, cpu);
1702 static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a)
1704 const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT;
1705 i386_cpu_flags f = { .array[0] = 0 };
1707 switch (ARRAY_SIZE (a.array))
1710 f.array[CpuAttrEnums / bps]
1711 #ifndef WORDS_BIGENDIAN
1712 |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps);
1714 |= (a.array[0] << CpuIsaBits) >> (CpuAttrEnums % bps);
1716 if (CpuMax / bps > CpuAttrEnums / bps)
1717 f.array[CpuAttrEnums / bps + 1]
1718 #ifndef WORDS_BIGENDIAN
1719 = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps);
1721 = (a.array[0] << CpuIsaBits) << (bps - CpuAttrEnums % bps);
1730 #ifndef WORDS_BIGENDIAN
1731 f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps);
1733 f.array[(a.bitfield.isa - 1) / bps] |= 1u << (~(a.bitfield.isa - 1) % bps);
1740 cpu_flags_all_zero (const union i386_cpu_flags *x)
1742 switch (ARRAY_SIZE(x->array))
1761 return !x->array[0];
1768 cpu_flags_equal (const union i386_cpu_flags *x,
1769 const union i386_cpu_flags *y)
1771 switch (ARRAY_SIZE(x->array))
1774 if (x->array[4] != y->array[4])
1778 if (x->array[3] != y->array[3])
1782 if (x->array[2] != y->array[2])
1786 if (x->array[1] != y->array[1])
1790 return x->array[0] == y->array[0];
1798 cpu_flags_check_cpu64 (const insn_template *t)
1800 return flag_code == CODE_64BIT
1801 ? !t->cpu.bitfield.cpuno64
1802 : !t->cpu.bitfield.cpu64;
1805 static INLINE i386_cpu_flags
1806 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1808 switch (ARRAY_SIZE (x.array))
1811 x.array [4] &= y.array [4];
1814 x.array [3] &= y.array [3];
1817 x.array [2] &= y.array [2];
1820 x.array [1] &= y.array [1];
1823 x.array [0] &= y.array [0];
1831 static INLINE i386_cpu_flags
1832 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1834 switch (ARRAY_SIZE (x.array))
1837 x.array [4] |= y.array [4];
1840 x.array [3] |= y.array [3];
1843 x.array [2] |= y.array [2];
1846 x.array [1] |= y.array [1];
1849 x.array [0] |= y.array [0];
1857 static INLINE i386_cpu_flags
1858 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1860 switch (ARRAY_SIZE (x.array))
1863 x.array [4] &= ~y.array [4];
1866 x.array [3] &= ~y.array [3];
1869 x.array [2] &= ~y.array [2];
1872 x.array [1] &= ~y.array [1];
1875 x.array [0] &= ~y.array [0];
1883 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
1885 static INLINE bool need_evex_encoding (const insn_template *t)
1887 return i.vec_encoding == vex_encoding_evex
1888 || i.vec_encoding == vex_encoding_evex512
1889 || (t->opcode_modifier.vex && i.has_egpr)
1893 #define CPU_FLAGS_ARCH_MATCH 0x1
1894 #define CPU_FLAGS_64BIT_MATCH 0x2
1896 #define CPU_FLAGS_PERFECT_MATCH \
1897 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1899 /* Return CPU flags match bits. */
1902 cpu_flags_match (const insn_template *t)
1904 i386_cpu_flags cpu, active, all = cpu_flags_from_attr (t->cpu);
1905 i386_cpu_flags any = cpu_flags_from_attr (t->cpu_any);
1906 int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0;
1908 all.bitfield.cpu64 = 0;
1909 all.bitfield.cpuno64 = 0;
1910 gas_assert (!any.bitfield.cpu64);
1911 gas_assert (!any.bitfield.cpuno64);
1913 if (cpu_flags_all_zero (&all) && cpu_flags_all_zero (&any))
1915 /* This instruction is available on all archs. */
1916 return match | CPU_FLAGS_ARCH_MATCH;
1919 /* This instruction is available only on some archs. */
1921 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
1922 if (t->opcode_modifier.vex && t->opcode_modifier.evex)
1924 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
1925 know that EVEX encoding will be needed. */
1926 if ((any.bitfield.cpuavx || any.bitfield.cpuavx2 || any.bitfield.cpufma)
1927 && (any.bitfield.cpuavx512f || any.bitfield.cpuavx512vl))
1929 if (need_evex_encoding (t))
1931 any.bitfield.cpuavx = 0;
1932 any.bitfield.cpuavx2 = 0;
1933 any.bitfield.cpufma = 0;
1935 /* need_evex_encoding(t) isn't reliable before operands were
1937 else if (i.operands)
1939 any.bitfield.cpuavx512f = 0;
1940 any.bitfield.cpuavx512vl = 0;
1944 /* Dual non-APX/APX templates need massaging from what APX_F() in the
1945 opcode table has produced. While the direct transformation of the
1946 incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F)
1947 respectively, it's cheaper to move to just cpuid / cpuid&APX_F
1949 if (any.bitfield.cpuapx_f
1950 && (any.bitfield.cpubmi || any.bitfield.cpubmi2
1951 || any.bitfield.cpuavx512f || any.bitfield.cpuavx512bw
1952 || any.bitfield.cpuavx512dq || any.bitfield.cpuamx_tile
1953 || any.bitfield.cpucmpccxadd || any.bitfield.cpuuser_msr))
1955 /* These checks (verifying that APX_F() was properly used in the
1956 opcode table entry) make sure there's no need for an "else" to
1957 the "if()" below. */
1958 gas_assert (!cpu_flags_all_zero (&all));
1959 cpu = cpu_flags_and (all, any);
1960 gas_assert (cpu_flags_equal (&cpu, &all));
1962 if (need_evex_encoding (t))
1965 memset (&any, 0, sizeof (any));
1969 if (flag_code != CODE_64BIT)
1970 active = cpu_flags_and_not (cpu_arch_flags, cpu_64_flags);
1972 active = cpu_arch_flags;
1973 cpu = cpu_flags_and (all, active);
1974 if (cpu_flags_equal (&cpu, &all))
1976 /* AVX and AVX2 present at the same time express an operand size
1977 dependency - strip AVX2 for the purposes here. The operand size
1978 dependent check occurs in check_vecOperands(). */
1979 if (any.bitfield.cpuavx && any.bitfield.cpuavx2)
1980 any.bitfield.cpuavx2 = 0;
1982 cpu = cpu_flags_and (any, active);
1983 if (cpu_flags_all_zero (&any) || !cpu_flags_all_zero (&cpu))
1985 if (all.bitfield.cpuavx)
1987 /* We need to check SSE2AVX with AVX. */
1988 if (!t->opcode_modifier.sse2avx
1989 || (sse2avx && !i.prefix[DATA_PREFIX]))
1990 match |= CPU_FLAGS_ARCH_MATCH;
1993 match |= CPU_FLAGS_ARCH_MATCH;
1999 static INLINE i386_operand_type
2000 operand_type_and (i386_operand_type x, i386_operand_type y)
2002 if (x.bitfield.class != y.bitfield.class)
2003 x.bitfield.class = ClassNone;
2004 if (x.bitfield.instance != y.bitfield.instance)
2005 x.bitfield.instance = InstanceNone;
2007 switch (ARRAY_SIZE (x.array))
2010 x.array [2] &= y.array [2];
2013 x.array [1] &= y.array [1];
2016 x.array [0] &= y.array [0];
2024 static INLINE i386_operand_type
2025 operand_type_and_not (i386_operand_type x, i386_operand_type y)
2027 gas_assert (y.bitfield.class == ClassNone);
2028 gas_assert (y.bitfield.instance == InstanceNone);
2030 switch (ARRAY_SIZE (x.array))
2033 x.array [2] &= ~y.array [2];
2036 x.array [1] &= ~y.array [1];
2039 x.array [0] &= ~y.array [0];
2047 static INLINE i386_operand_type
2048 operand_type_or (i386_operand_type x, i386_operand_type y)
2050 gas_assert (x.bitfield.class == ClassNone ||
2051 y.bitfield.class == ClassNone ||
2052 x.bitfield.class == y.bitfield.class);
2053 gas_assert (x.bitfield.instance == InstanceNone ||
2054 y.bitfield.instance == InstanceNone ||
2055 x.bitfield.instance == y.bitfield.instance);
2057 switch (ARRAY_SIZE (x.array))
2060 x.array [2] |= y.array [2];
2063 x.array [1] |= y.array [1];
2066 x.array [0] |= y.array [0];
2074 static INLINE i386_operand_type
2075 operand_type_xor (i386_operand_type x, i386_operand_type y)
2077 gas_assert (y.bitfield.class == ClassNone);
2078 gas_assert (y.bitfield.instance == InstanceNone);
2080 switch (ARRAY_SIZE (x.array))
2083 x.array [2] ^= y.array [2];
2086 x.array [1] ^= y.array [1];
2089 x.array [0] ^= y.array [0];
2097 static const i386_operand_type anydisp = {
2098 .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 }
2110 operand_type_check (i386_operand_type t, enum operand_type c)
2115 return t.bitfield.class == Reg;
2118 return (t.bitfield.imm8
2122 || t.bitfield.imm32s
2123 || t.bitfield.imm64);
2126 return (t.bitfield.disp8
2127 || t.bitfield.disp16
2128 || t.bitfield.disp32
2129 || t.bitfield.disp64);
2132 return (t.bitfield.disp8
2133 || t.bitfield.disp16
2134 || t.bitfield.disp32
2135 || t.bitfield.disp64
2136 || t.bitfield.baseindex);
2145 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2146 between operand GIVEN and opeand WANTED for instruction template T. */
2149 match_operand_size (const insn_template *t, unsigned int wanted,
2152 return !((i.types[given].bitfield.byte
2153 && !t->operand_types[wanted].bitfield.byte)
2154 || (i.types[given].bitfield.word
2155 && !t->operand_types[wanted].bitfield.word)
2156 || (i.types[given].bitfield.dword
2157 && !t->operand_types[wanted].bitfield.dword)
2158 || (i.types[given].bitfield.qword
2159 && (!t->operand_types[wanted].bitfield.qword
2160 /* Don't allow 64-bit (memory) operands outside of 64-bit
2161 mode, when they're used where a 64-bit GPR could also
2162 be used. Checking is needed for Intel Syntax only. */
2164 && flag_code != CODE_64BIT
2165 && (t->operand_types[wanted].bitfield.class == Reg
2166 || t->operand_types[wanted].bitfield.class == Accum
2167 || t->opcode_modifier.isstring))))
2168 || (i.types[given].bitfield.tbyte
2169 && !t->operand_types[wanted].bitfield.tbyte));
2172 /* Return 1 if there is no conflict in SIMD register between operand
2173 GIVEN and opeand WANTED for instruction template T. */
2176 match_simd_size (const insn_template *t, unsigned int wanted,
2179 return !((i.types[given].bitfield.xmmword
2180 && !t->operand_types[wanted].bitfield.xmmword)
2181 || (i.types[given].bitfield.ymmword
2182 && !t->operand_types[wanted].bitfield.ymmword)
2183 || (i.types[given].bitfield.zmmword
2184 && !t->operand_types[wanted].bitfield.zmmword)
2185 || (i.types[given].bitfield.tmmword
2186 && !t->operand_types[wanted].bitfield.tmmword));
2189 /* Return 1 if there is no conflict in any size between operand GIVEN
2190 and opeand WANTED for instruction template T. */
2193 match_mem_size (const insn_template *t, unsigned int wanted,
2196 return (match_operand_size (t, wanted, given)
2197 && !((i.types[given].bitfield.unspecified
2198 && !i.broadcast.type
2199 && !i.broadcast.bytes
2200 && !t->operand_types[wanted].bitfield.unspecified)
2201 || (i.types[given].bitfield.fword
2202 && !t->operand_types[wanted].bitfield.fword)
2203 /* For scalar opcode templates to allow register and memory
2204 operands at the same time, some special casing is needed
2205 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2206 down-conversion vpmov*. */
2207 || ((t->operand_types[wanted].bitfield.class == RegSIMD
2208 && t->operand_types[wanted].bitfield.byte
2209 + t->operand_types[wanted].bitfield.word
2210 + t->operand_types[wanted].bitfield.dword
2211 + t->operand_types[wanted].bitfield.qword
2212 > !!t->opcode_modifier.broadcast)
2213 ? (i.types[given].bitfield.xmmword
2214 || i.types[given].bitfield.ymmword
2215 || i.types[given].bitfield.zmmword)
2216 : !match_simd_size(t, wanted, given))));
2219 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2220 operands for instruction template T, and it has MATCH_REVERSE set if there
2221 is no size conflict on any operands for the template with operands reversed
2222 (and the template allows for reversing in the first place). */
2224 #define MATCH_STRAIGHT 1
2225 #define MATCH_REVERSE 2
2227 static INLINE unsigned int
2228 operand_size_match (const insn_template *t)
2230 unsigned int j, match = MATCH_STRAIGHT;
2232 /* Don't check non-absolute jump instructions. */
2233 if (t->opcode_modifier.jump
2234 && t->opcode_modifier.jump != JUMP_ABSOLUTE)
2237 /* Check memory and accumulator operand size. */
2238 for (j = 0; j < i.operands; j++)
2240 if (i.types[j].bitfield.class != Reg
2241 && i.types[j].bitfield.class != RegSIMD
2242 && t->opcode_modifier.operandconstraint == ANY_SIZE)
2245 if (t->operand_types[j].bitfield.class == Reg
2246 && !match_operand_size (t, j, j))
2252 if (t->operand_types[j].bitfield.class == RegSIMD
2253 && !match_simd_size (t, j, j))
2259 if (t->operand_types[j].bitfield.instance == Accum
2260 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2266 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2273 if (!t->opcode_modifier.d)
2276 /* Check reverse. */
2277 gas_assert (i.operands >= 2);
2279 for (j = 0; j < i.operands; j++)
2281 unsigned int given = i.operands - j - 1;
2283 /* For FMA4 and XOP insns VEX.W controls just the first two
2284 register operands. And APX_F insns just swap the two source operands,
2285 with the 3rd one being the destination. */
2286 if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)
2287 || is_cpu (t, CpuAPX_F))
2288 given = j < 2 ? 1 - j : j;
2290 if (t->operand_types[j].bitfield.class == Reg
2291 && !match_operand_size (t, j, given))
2294 if (t->operand_types[j].bitfield.class == RegSIMD
2295 && !match_simd_size (t, j, given))
2298 if (t->operand_types[j].bitfield.instance == Accum
2299 && (!match_operand_size (t, j, given)
2300 || !match_simd_size (t, j, given)))
2303 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2307 return match | MATCH_REVERSE;
2311 operand_type_match (i386_operand_type overlap,
2312 i386_operand_type given)
2314 i386_operand_type temp = overlap;
2316 temp.bitfield.unspecified = 0;
2317 temp.bitfield.byte = 0;
2318 temp.bitfield.word = 0;
2319 temp.bitfield.dword = 0;
2320 temp.bitfield.fword = 0;
2321 temp.bitfield.qword = 0;
2322 temp.bitfield.tbyte = 0;
2323 temp.bitfield.xmmword = 0;
2324 temp.bitfield.ymmword = 0;
2325 temp.bitfield.zmmword = 0;
2326 temp.bitfield.tmmword = 0;
2327 if (operand_type_all_zero (&temp))
2330 if (given.bitfield.baseindex == overlap.bitfield.baseindex)
2334 i.error = operand_type_mismatch;
2338 /* If given types g0 and g1 are registers they must be of the same type
2339 unless the expected operand type register overlap is null.
2340 Intel syntax sized memory operands are also checked here. */
2343 operand_type_register_match (i386_operand_type g0,
2344 i386_operand_type t0,
2345 i386_operand_type g1,
2346 i386_operand_type t1)
2348 if (g0.bitfield.class != Reg
2349 && g0.bitfield.class != RegSIMD
2350 && (g0.bitfield.unspecified
2351 || !operand_type_check (g0, anymem)))
2354 if (g1.bitfield.class != Reg
2355 && g1.bitfield.class != RegSIMD
2356 && (g1.bitfield.unspecified
2357 || !operand_type_check (g1, anymem)))
2360 if (g0.bitfield.byte == g1.bitfield.byte
2361 && g0.bitfield.word == g1.bitfield.word
2362 && g0.bitfield.dword == g1.bitfield.dword
2363 && g0.bitfield.qword == g1.bitfield.qword
2364 && g0.bitfield.xmmword == g1.bitfield.xmmword
2365 && g0.bitfield.ymmword == g1.bitfield.ymmword
2366 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2369 /* If expectations overlap in no more than a single size, all is fine. */
2370 g0 = operand_type_and (t0, t1);
2371 if (g0.bitfield.byte
2375 + g0.bitfield.xmmword
2376 + g0.bitfield.ymmword
2377 + g0.bitfield.zmmword <= 1)
2380 i.error = register_type_mismatch;
2385 static INLINE unsigned int
2386 register_number (const reg_entry *r)
2388 unsigned int nr = r->reg_num;
2390 if (r->reg_flags & RegRex)
2393 if (r->reg_flags & (RegVRex | RegRex2))
2399 static INLINE unsigned int
2400 mode_from_disp_size (i386_operand_type t)
2402 if (t.bitfield.disp8)
2404 else if (t.bitfield.disp16
2405 || t.bitfield.disp32)
2412 fits_in_signed_byte (addressT num)
2414 return num + 0x80 <= 0xff;
2418 fits_in_unsigned_byte (addressT num)
2424 fits_in_unsigned_word (addressT num)
2426 return num <= 0xffff;
2430 fits_in_signed_word (addressT num)
2432 return num + 0x8000 <= 0xffff;
2436 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2441 return num + 0x80000000 <= 0xffffffff;
2443 } /* fits_in_signed_long() */
2446 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2451 return num <= 0xffffffff;
2453 } /* fits_in_unsigned_long() */
2455 static INLINE valueT extend_to_32bit_address (addressT num)
2458 if (fits_in_unsigned_long(num))
2459 return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2461 if (!fits_in_signed_long (num))
2462 return num & 0xffffffff;
2469 fits_in_disp8 (offsetT num)
2471 int shift = i.memshift;
2477 mask = (1 << shift) - 1;
2479 /* Return 0 if NUM isn't properly aligned. */
2483 /* Check if NUM will fit in 8bit after shift. */
2484 return fits_in_signed_byte (num >> shift);
2488 fits_in_imm4 (offsetT num)
2490 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2491 return (num & (i.vec_encoding != vex_encoding_evex ? 0xf : 7)) == num;
2494 static i386_operand_type
2495 smallest_imm_type (offsetT num)
2497 i386_operand_type t;
2499 operand_type_set (&t, 0);
2500 t.bitfield.imm64 = 1;
2502 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2504 /* This code is disabled on the 486 because all the Imm1 forms
2505 in the opcode table are slower on the i486. They're the
2506 versions with the implicitly specified single-position
2507 displacement, which has another syntax if you really want to
2509 t.bitfield.imm1 = 1;
2510 t.bitfield.imm8 = 1;
2511 t.bitfield.imm8s = 1;
2512 t.bitfield.imm16 = 1;
2513 t.bitfield.imm32 = 1;
2514 t.bitfield.imm32s = 1;
2516 else if (fits_in_signed_byte (num))
2518 if (fits_in_unsigned_byte (num))
2519 t.bitfield.imm8 = 1;
2520 t.bitfield.imm8s = 1;
2521 t.bitfield.imm16 = 1;
2522 if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2523 t.bitfield.imm32 = 1;
2524 t.bitfield.imm32s = 1;
2526 else if (fits_in_unsigned_byte (num))
2528 t.bitfield.imm8 = 1;
2529 t.bitfield.imm16 = 1;
2530 t.bitfield.imm32 = 1;
2531 t.bitfield.imm32s = 1;
2533 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2535 t.bitfield.imm16 = 1;
2536 if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2537 t.bitfield.imm32 = 1;
2538 t.bitfield.imm32s = 1;
2540 else if (fits_in_signed_long (num))
2542 if (flag_code != CODE_64BIT || fits_in_unsigned_long (num))
2543 t.bitfield.imm32 = 1;
2544 t.bitfield.imm32s = 1;
2546 else if (fits_in_unsigned_long (num))
2547 t.bitfield.imm32 = 1;
2553 offset_in_range (offsetT val, int size)
2559 case 1: mask = ((addressT) 1 << 8) - 1; break;
2560 case 2: mask = ((addressT) 1 << 16) - 1; break;
2562 case 4: mask = ((addressT) 1 << 32) - 1; break;
2564 case sizeof (val): return val;
2568 if ((val & ~mask) != 0 && (-val & ~mask) != 0)
2569 as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64),
2570 (uint64_t) val, (uint64_t) (val & mask));
2575 static INLINE const char *insn_name (const insn_template *t)
2577 return &i386_mnemonics[t->mnem_off];
2590 a. PREFIX_EXIST if attempting to add a prefix where one from the
2591 same class already exists.
2592 b. PREFIX_LOCK if lock prefix is added.
2593 c. PREFIX_REP if rep/repne prefix is added.
2594 d. PREFIX_DS if ds prefix is added.
2595 e. PREFIX_OTHER if other prefix is added.
2598 static enum PREFIX_GROUP
2599 add_prefix (unsigned int prefix)
2601 enum PREFIX_GROUP ret = PREFIX_OTHER;
2604 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2605 && flag_code == CODE_64BIT)
2607 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2608 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2609 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2610 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2621 case DS_PREFIX_OPCODE:
2624 case CS_PREFIX_OPCODE:
2625 case ES_PREFIX_OPCODE:
2626 case FS_PREFIX_OPCODE:
2627 case GS_PREFIX_OPCODE:
2628 case SS_PREFIX_OPCODE:
2632 case REPNE_PREFIX_OPCODE:
2633 case REPE_PREFIX_OPCODE:
2638 case LOCK_PREFIX_OPCODE:
2647 case ADDR_PREFIX_OPCODE:
2651 case DATA_PREFIX_OPCODE:
2655 if (i.prefix[q] != 0)
2663 i.prefix[q] |= prefix;
2666 as_bad (_("same type of prefix used twice"));
2672 update_code_flag (int value, int check)
2674 PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad;
2676 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 )
2678 as_error (_("64bit mode not supported on `%s'."),
2679 cpu_arch_name ? cpu_arch_name : default_arch);
2683 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2685 as_error (_("32bit mode not supported on `%s'."),
2686 cpu_arch_name ? cpu_arch_name : default_arch);
2690 flag_code = (enum flag_code) value;
2692 stackop_size = '\0';
2696 set_code_flag (int value)
2698 update_code_flag (value, 0);
2702 set_16bit_gcc_code_flag (int new_code_flag)
2704 flag_code = (enum flag_code) new_code_flag;
2705 if (flag_code != CODE_16BIT)
2707 stackop_size = LONG_MNEM_SUFFIX;
2711 set_intel_syntax (int syntax_flag)
2713 /* Find out if register prefixing is specified. */
2714 int ask_naked_reg = 0;
2717 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2720 int e = get_symbol_name (&string);
2722 if (strcmp (string, "prefix") == 0)
2724 else if (strcmp (string, "noprefix") == 0)
2727 as_bad (_("bad argument to syntax directive."));
2728 (void) restore_line_pointer (e);
2730 demand_empty_rest_of_line ();
2732 intel_syntax = syntax_flag;
2734 if (ask_naked_reg == 0)
2735 allow_naked_reg = (intel_syntax
2736 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2738 allow_naked_reg = (ask_naked_reg < 0);
2740 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2742 register_prefix = allow_naked_reg ? "" : "%";
2746 set_intel_mnemonic (int mnemonic_flag)
2748 intel_mnemonic = mnemonic_flag;
2752 set_allow_index_reg (int flag)
2754 allow_index_reg = flag;
2758 set_check (int what)
2760 enum check_kind *kind;
2765 kind = &operand_check;
2776 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2779 int e = get_symbol_name (&string);
2781 if (strcmp (string, "none") == 0)
2783 else if (strcmp (string, "warning") == 0)
2784 *kind = check_warning;
2785 else if (strcmp (string, "error") == 0)
2786 *kind = check_error;
2788 as_bad (_("bad argument to %s_check directive."), str);
2789 (void) restore_line_pointer (e);
2792 as_bad (_("missing argument for %s_check directive"), str);
2794 demand_empty_rest_of_line ();
2798 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2799 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2801 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2802 static const char *arch;
2804 /* Intel MCU is only supported on ELF. */
2810 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2811 use default_arch. */
2812 arch = cpu_arch_name;
2814 arch = default_arch;
2817 /* If we are targeting Intel MCU, we must enable it. */
2818 if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU)
2819 == new_flag.bitfield.cpuiamcu)
2822 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2827 extend_cpu_sub_arch_name (const char *pfx, const char *name)
2829 if (cpu_sub_arch_name)
2830 cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name,
2831 pfx, name, (const char *) NULL);
2833 cpu_sub_arch_name = concat (pfx, name, (const char *) NULL);
2836 static void isa_enable (unsigned int idx)
2838 i386_cpu_flags flags = cpu_flags_or (cpu_arch_flags, cpu_arch[idx].enable);
2840 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2842 extend_cpu_sub_arch_name (".", cpu_arch[idx].name);
2843 cpu_arch_flags = flags;
2846 cpu_arch_isa_flags = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[idx].enable);
2849 static void isa_disable (unsigned int idx)
2851 i386_cpu_flags flags
2852 = cpu_flags_and_not (cpu_arch_flags, cpu_arch[idx].disable);
2854 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2856 extend_cpu_sub_arch_name (".no", cpu_arch[idx].name);
2857 cpu_arch_flags = flags;
2861 = cpu_flags_and_not (cpu_arch_isa_flags, cpu_arch[idx].disable);
2865 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2867 typedef struct arch_stack_entry
2869 const struct arch_stack_entry *prev;
2872 i386_cpu_flags flags;
2873 i386_cpu_flags isa_flags;
2874 enum processor_type isa;
2875 enum flag_code flag_code;
2876 unsigned int vector_size;
2878 bool no_cond_jump_promotion;
2880 static const arch_stack_entry *arch_stack_top;
2888 if (is_end_of_line[(unsigned char) *input_line_pointer])
2890 as_bad (_("missing cpu architecture"));
2891 input_line_pointer++;
2895 e = get_symbol_name (&s);
2898 if (strcmp (string, "push") == 0)
2900 arch_stack_entry *top = XNEW (arch_stack_entry);
2902 top->name = cpu_arch_name;
2903 if (cpu_sub_arch_name)
2904 top->sub_name = xstrdup (cpu_sub_arch_name);
2906 top->sub_name = NULL;
2907 top->flags = cpu_arch_flags;
2908 top->isa = cpu_arch_isa;
2909 top->isa_flags = cpu_arch_isa_flags;
2910 top->flag_code = flag_code;
2911 top->vector_size = vector_size;
2912 top->stackop_size = stackop_size;
2913 top->no_cond_jump_promotion = no_cond_jump_promotion;
2915 top->prev = arch_stack_top;
2916 arch_stack_top = top;
2918 (void) restore_line_pointer (e);
2919 demand_empty_rest_of_line ();
2923 if (strcmp (string, "pop") == 0)
2925 const arch_stack_entry *top = arch_stack_top;
2928 as_bad (_(".arch stack is empty"));
2929 else if (top->flag_code != flag_code
2930 || top->stackop_size != stackop_size)
2932 static const unsigned int bits[] = {
2938 as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"),
2939 bits[top->flag_code],
2940 top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : "");
2944 arch_stack_top = top->prev;
2946 cpu_arch_name = top->name;
2947 free (cpu_sub_arch_name);
2948 cpu_sub_arch_name = top->sub_name;
2949 cpu_arch_flags = top->flags;
2950 cpu_arch_isa = top->isa;
2951 cpu_arch_isa_flags = top->isa_flags;
2952 vector_size = top->vector_size;
2953 no_cond_jump_promotion = top->no_cond_jump_promotion;
2958 (void) restore_line_pointer (e);
2959 demand_empty_rest_of_line ();
2963 if (strcmp (string, "default") == 0)
2965 if (strcmp (default_arch, "iamcu") == 0)
2966 string = default_arch;
2969 static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS;
2971 cpu_arch_name = NULL;
2972 free (cpu_sub_arch_name);
2973 cpu_sub_arch_name = NULL;
2974 cpu_arch_flags = cpu_unknown_flags;
2975 cpu_arch_isa = PROCESSOR_UNKNOWN;
2976 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
2977 if (!cpu_arch_tune_set)
2978 cpu_arch_tune = PROCESSOR_UNKNOWN;
2980 vector_size = VSZ_DEFAULT;
2982 j = ARRAY_SIZE (cpu_arch) + 1;
2986 for (; j < ARRAY_SIZE (cpu_arch); j++)
2988 if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0
2989 && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE))
2993 check_cpu_arch_compatible (string, cpu_arch[j].enable);
2995 if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 )
2997 as_bad (_("64bit mode not supported on `%s'."),
2999 (void) restore_line_pointer (e);
3000 ignore_rest_of_line ();
3004 if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
3006 as_bad (_("32bit mode not supported on `%s'."),
3008 (void) restore_line_pointer (e);
3009 ignore_rest_of_line ();
3013 cpu_arch_name = cpu_arch[j].name;
3014 free (cpu_sub_arch_name);
3015 cpu_sub_arch_name = NULL;
3016 cpu_arch_flags = cpu_arch[j].enable;
3017 cpu_arch_isa = cpu_arch[j].type;
3018 cpu_arch_isa_flags = cpu_arch[j].enable;
3019 if (!cpu_arch_tune_set)
3020 cpu_arch_tune = cpu_arch_isa;
3022 vector_size = VSZ_DEFAULT;
3024 pre_386_16bit_warned = false;
3028 if (cpu_flags_all_zero (&cpu_arch[j].enable))
3033 (void) restore_line_pointer (e);
3035 switch (cpu_arch[j].vsz)
3041 #ifdef SVR4_COMMENT_CHARS
3042 if (*input_line_pointer == ':' || *input_line_pointer == '/')
3044 if (*input_line_pointer == '/')
3047 ++input_line_pointer;
3048 switch (get_absolute_expression ())
3050 case 512: vector_size = VSZ512; break;
3051 case 256: vector_size = VSZ256; break;
3052 case 128: vector_size = VSZ128; break;
3054 as_bad (_("Unrecognized vector size specifier"));
3055 ignore_rest_of_line ();
3062 vector_size = VSZ_DEFAULT;
3066 demand_empty_rest_of_line ();
3071 if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch))
3073 /* Disable an ISA extension. */
3074 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
3075 if (cpu_arch[j].type == PROCESSOR_NONE
3076 && strcmp (string + 3, cpu_arch[j].name) == 0)
3080 if (cpu_arch[j].vsz == vsz_set)
3081 vector_size = VSZ_DEFAULT;
3083 (void) restore_line_pointer (e);
3084 demand_empty_rest_of_line ();
3089 if (j == ARRAY_SIZE (cpu_arch))
3090 as_bad (_("no such architecture: `%s'"), string);
3092 *input_line_pointer = e;
3094 no_cond_jump_promotion = 0;
3095 if (*input_line_pointer == ','
3096 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
3098 ++input_line_pointer;
3099 e = get_symbol_name (&s);
3102 if (strcmp (string, "nojumps") == 0)
3103 no_cond_jump_promotion = 1;
3104 else if (strcmp (string, "jumps") == 0)
3107 as_bad (_("no such architecture modifier: `%s'"), string);
3109 (void) restore_line_pointer (e);
3112 demand_empty_rest_of_line ();
3115 enum bfd_architecture
3118 if (cpu_arch_isa == PROCESSOR_IAMCU)
3120 if (!IS_ELF || flag_code == CODE_64BIT)
3121 as_fatal (_("Intel MCU is 32bit ELF only"));
3122 return bfd_arch_iamcu;
3125 return bfd_arch_i386;
3131 if (startswith (default_arch, "x86_64"))
3133 if (default_arch[6] == '\0')
3134 return bfd_mach_x86_64;
3136 return bfd_mach_x64_32;
3138 else if (!strcmp (default_arch, "i386")
3139 || !strcmp (default_arch, "iamcu"))
3141 if (cpu_arch_isa == PROCESSOR_IAMCU)
3144 as_fatal (_("Intel MCU is 32bit ELF only"));
3145 return bfd_mach_i386_iamcu;
3148 return bfd_mach_i386_i386;
3151 as_fatal (_("unknown architecture"));
3154 #include "opcodes/i386-tbl.h"
3157 op_lookup (const char *mnemonic)
3159 i386_op_off_t *pos = str_hash_find (op_hash, mnemonic);
3163 current_templates.start = &i386_optab[pos[0]];
3164 current_templates.end = &i386_optab[pos[1]];
3167 current_templates.end = current_templates.start = NULL;
3173 /* Support pseudo prefixes like {disp32}. */
3174 lex_type ['{'] = LEX_BEGIN_NAME;
3176 /* Initialize op_hash hash table. */
3177 op_hash = str_htab_create ();
3180 const i386_op_off_t *cur = i386_op_sets;
3181 const i386_op_off_t *end = cur + ARRAY_SIZE (i386_op_sets) - 1;
3183 for (; cur < end; ++cur)
3184 if (str_hash_insert (op_hash, insn_name (&i386_optab[*cur]), cur, 0))
3185 as_fatal (_("duplicate %s"), insn_name (&i386_optab[*cur]));
3188 /* Initialize reg_hash hash table. */
3189 reg_hash = str_htab_create ();
3191 const reg_entry *regtab;
3192 unsigned int regtab_size = i386_regtab_size;
3194 for (regtab = i386_regtab; regtab_size--; regtab++)
3196 switch (regtab->reg_type.bitfield.class)
3199 if (regtab->reg_type.bitfield.dword)
3201 if (regtab->reg_type.bitfield.instance == Accum)
3204 else if (regtab->reg_type.bitfield.tbyte)
3206 /* There's no point inserting st(<N>) in the hash table, as
3207 parentheses aren't included in register_chars[] anyway. */
3208 if (regtab->reg_type.bitfield.instance != Accum)
3215 switch (regtab->reg_num)
3217 case 0: reg_es = regtab; break;
3218 case 2: reg_ss = regtab; break;
3219 case 3: reg_ds = regtab; break;
3224 if (!regtab->reg_num)
3229 if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL)
3230 as_fatal (_("duplicate %s"), regtab->reg_name);
3234 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3239 for (c = 0; c < 256; c++)
3241 if (ISDIGIT (c) || ISLOWER (c))
3243 mnemonic_chars[c] = c;
3244 register_chars[c] = c;
3245 operand_chars[c] = c;
3247 else if (ISUPPER (c))
3249 mnemonic_chars[c] = TOLOWER (c);
3250 register_chars[c] = mnemonic_chars[c];
3251 operand_chars[c] = c;
3253 #ifdef SVR4_COMMENT_CHARS
3254 else if (c == '\\' && strchr (i386_comment_chars, '/'))
3255 operand_chars[c] = c;
3259 operand_chars[c] = c;
3262 mnemonic_chars['_'] = '_';
3263 mnemonic_chars['-'] = '-';
3264 mnemonic_chars['.'] = '.';
3266 for (p = extra_symbol_chars; *p != '\0'; p++)
3267 operand_chars[(unsigned char) *p] = *p;
3268 for (p = operand_special_chars; *p != '\0'; p++)
3269 operand_chars[(unsigned char) *p] = *p;
3272 if (flag_code == CODE_64BIT)
3274 #if defined (OBJ_COFF) && defined (TE_PE)
3275 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
3278 x86_dwarf2_return_column = 16;
3280 x86_cie_data_alignment = -8;
3281 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3282 x86_sframe_cfa_sp_reg = 7;
3283 x86_sframe_cfa_fp_reg = 6;
3288 x86_dwarf2_return_column = 8;
3289 x86_cie_data_alignment = -4;
3292 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3293 can be turned into BRANCH_PREFIX frag. */
3294 if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE)
3299 i386_print_statistics (FILE *file)
3301 htab_print_statistics (file, "i386 opcode", op_hash);
3302 htab_print_statistics (file, "i386 register", reg_hash);
3308 htab_delete (op_hash);
3309 htab_delete (reg_hash);
3314 /* Debugging routines for md_assemble. */
3315 static void pte (insn_template *);
3316 static void pt (i386_operand_type);
3317 static void pe (expressionS *);
3318 static void ps (symbolS *);
3321 pi (const char *line, i386_insn *x)
3325 fprintf (stdout, "%s: template ", line);
3327 fprintf (stdout, " address: base %s index %s scale %x\n",
3328 x->base_reg ? x->base_reg->reg_name : "none",
3329 x->index_reg ? x->index_reg->reg_name : "none",
3330 x->log2_scale_factor);
3331 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
3332 x->rm.mode, x->rm.reg, x->rm.regmem);
3333 fprintf (stdout, " sib: base %x index %x scale %x\n",
3334 x->sib.base, x->sib.index, x->sib.scale);
3335 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
3336 (x->rex & REX_W) != 0,
3337 (x->rex & REX_R) != 0,
3338 (x->rex & REX_X) != 0,
3339 (x->rex & REX_B) != 0);
3340 for (j = 0; j < x->operands; j++)
3342 fprintf (stdout, " #%d: ", j + 1);
3344 fprintf (stdout, "\n");
3345 if (x->types[j].bitfield.class == Reg
3346 || x->types[j].bitfield.class == RegMMX
3347 || x->types[j].bitfield.class == RegSIMD
3348 || x->types[j].bitfield.class == RegMask
3349 || x->types[j].bitfield.class == SReg
3350 || x->types[j].bitfield.class == RegCR
3351 || x->types[j].bitfield.class == RegDR
3352 || x->types[j].bitfield.class == RegTR
3353 || x->types[j].bitfield.class == RegBND)
3354 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3355 if (operand_type_check (x->types[j], imm))
3357 if (operand_type_check (x->types[j], disp))
3358 pe (x->op[j].disps);
3363 pte (insn_template *t)
3365 static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 };
3366 static const char *const opc_spc[] = {
3367 NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL,
3368 "XOP08", "XOP09", "XOP0A",
3372 fprintf (stdout, " %d operands ", t->operands);
3373 if (opc_pfx[t->opcode_modifier.opcodeprefix])
3374 fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]);
3375 if (opc_spc[t->opcode_space])
3376 fprintf (stdout, "space %s ", opc_spc[t->opcode_space]);
3377 fprintf (stdout, "opcode %x ", t->base_opcode);
3378 if (t->extension_opcode != None)
3379 fprintf (stdout, "ext %x ", t->extension_opcode);
3380 if (t->opcode_modifier.d)
3381 fprintf (stdout, "D");
3382 if (t->opcode_modifier.w)
3383 fprintf (stdout, "W");
3384 fprintf (stdout, "\n");
3385 for (j = 0; j < t->operands; j++)
3387 fprintf (stdout, " #%d type ", j + 1);
3388 pt (t->operand_types[j]);
3389 fprintf (stdout, "\n");
3396 fprintf (stdout, " operation %d\n", e->X_op);
3397 fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n",
3398 (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number);
3399 if (e->X_add_symbol)
3401 fprintf (stdout, " add_symbol ");
3402 ps (e->X_add_symbol);
3403 fprintf (stdout, "\n");
3407 fprintf (stdout, " op_symbol ");
3408 ps (e->X_op_symbol);
3409 fprintf (stdout, "\n");
3416 fprintf (stdout, "%s type %s%s",
3418 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3419 segment_name (S_GET_SEGMENT (s)));
3422 static struct type_name
3424 i386_operand_type mask;
3427 const type_names[] =
3429 { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" },
3430 { { .bitfield = { .class = Reg, .word = 1 } }, "r16" },
3431 { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" },
3432 { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" },
3433 { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" },
3434 { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" },
3435 { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" },
3436 { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" },
3437 { { .bitfield = { .imm8 = 1 } }, "i8" },
3438 { { .bitfield = { .imm8s = 1 } }, "i8s" },
3439 { { .bitfield = { .imm16 = 1 } }, "i16" },
3440 { { .bitfield = { .imm32 = 1 } }, "i32" },
3441 { { .bitfield = { .imm32s = 1 } }, "i32s" },
3442 { { .bitfield = { .imm64 = 1 } }, "i64" },
3443 { { .bitfield = { .imm1 = 1 } }, "i1" },
3444 { { .bitfield = { .baseindex = 1 } }, "BaseIndex" },
3445 { { .bitfield = { .disp8 = 1 } }, "d8" },
3446 { { .bitfield = { .disp16 = 1 } }, "d16" },
3447 { { .bitfield = { .disp32 = 1 } }, "d32" },
3448 { { .bitfield = { .disp64 = 1 } }, "d64" },
3449 { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" },
3450 { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" },
3451 { { .bitfield = { .class = RegCR } }, "control reg" },
3452 { { .bitfield = { .class = RegTR } }, "test reg" },
3453 { { .bitfield = { .class = RegDR } }, "debug reg" },
3454 { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" },
3455 { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" },
3456 { { .bitfield = { .class = SReg } }, "SReg" },
3457 { { .bitfield = { .class = RegMMX } }, "rMMX" },
3458 { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" },
3459 { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" },
3460 { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
3461 { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
3462 { { .bitfield = { .class = RegMask } }, "Mask reg" },
3466 pt (i386_operand_type t)
3469 i386_operand_type a;
3471 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3473 a = operand_type_and (t, type_names[j].mask);
3474 if (operand_type_equal (&a, &type_names[j].mask))
3475 fprintf (stdout, "%s, ", type_names[j].name);
3480 #endif /* DEBUG386 */
3482 static bfd_reloc_code_real_type
3483 reloc (unsigned int size,
3486 bfd_reloc_code_real_type other)
3488 if (other != NO_RELOC)
3490 reloc_howto_type *rel;
3495 case BFD_RELOC_X86_64_GOT32:
3496 return BFD_RELOC_X86_64_GOT64;
3498 case BFD_RELOC_X86_64_GOTPLT64:
3499 return BFD_RELOC_X86_64_GOTPLT64;
3501 case BFD_RELOC_X86_64_PLTOFF64:
3502 return BFD_RELOC_X86_64_PLTOFF64;
3504 case BFD_RELOC_X86_64_GOTPC32:
3505 other = BFD_RELOC_X86_64_GOTPC64;
3507 case BFD_RELOC_X86_64_GOTPCREL:
3508 other = BFD_RELOC_X86_64_GOTPCREL64;
3510 case BFD_RELOC_X86_64_TPOFF32:
3511 other = BFD_RELOC_X86_64_TPOFF64;
3513 case BFD_RELOC_X86_64_DTPOFF32:
3514 other = BFD_RELOC_X86_64_DTPOFF64;
3520 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3521 if (other == BFD_RELOC_SIZE32)
3524 other = BFD_RELOC_SIZE64;
3527 as_bad (_("there are no pc-relative size relocations"));
3533 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3534 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3537 rel = bfd_reloc_type_lookup (stdoutput, other);
3539 as_bad (_("unknown relocation (%u)"), other);
3540 else if (size != bfd_get_reloc_size (rel))
3541 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3542 bfd_get_reloc_size (rel),
3544 else if (pcrel && !rel->pc_relative)
3545 as_bad (_("non-pc-relative relocation for pc-relative field"));
3546 else if ((rel->complain_on_overflow == complain_overflow_signed
3548 || (rel->complain_on_overflow == complain_overflow_unsigned
3550 as_bad (_("relocated field and relocation type differ in signedness"));
3559 as_bad (_("there are no unsigned pc-relative relocations"));
3562 case 1: return BFD_RELOC_8_PCREL;
3563 case 2: return BFD_RELOC_16_PCREL;
3564 case 4: return BFD_RELOC_32_PCREL;
3565 case 8: return BFD_RELOC_64_PCREL;
3567 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3574 case 4: return BFD_RELOC_X86_64_32S;
3579 case 1: return BFD_RELOC_8;
3580 case 2: return BFD_RELOC_16;
3581 case 4: return BFD_RELOC_32;
3582 case 8: return BFD_RELOC_64;
3584 as_bad (_("cannot do %s %u byte relocation"),
3585 sign > 0 ? "signed" : "unsigned", size);
3591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3592 /* Here we decide which fixups can be adjusted to make them relative to
3593 the beginning of the section instead of the symbol. Basically we need
3594 to make sure that the dynamic relocations are done correctly, so in
3595 some cases we force the original symbol to be used. */
3598 tc_i386_fix_adjustable (fixS *fixP)
3603 /* Don't adjust pc-relative references to merge sections in 64-bit
3605 if (use_rela_relocations
3606 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3610 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3611 and changed later by validate_fix. */
3612 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3613 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3616 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3617 for size relocations. */
3618 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3619 || fixP->fx_r_type == BFD_RELOC_SIZE64
3620 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3621 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3622 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3623 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3624 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3625 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3626 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3627 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3628 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3629 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3631 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3632 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3633 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3634 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3635 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3636 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3637 || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPCRELX
3638 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3639 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3640 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3641 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3642 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3643 || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTTPOFF
3644 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3645 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3647 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3648 || fixP->fx_r_type == BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
3649 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3650 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3651 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3658 want_disp32 (const insn_template *t)
3660 return flag_code != CODE_64BIT
3661 || i.prefix[ADDR_PREFIX]
3662 || (t->mnem_off == MN_lea
3663 && (!i.types[1].bitfield.qword
3664 || t->opcode_modifier.size == SIZE32));
3668 intel_float_operand (const char *mnemonic)
3670 /* Note that the value returned is meaningful only for opcodes with (memory)
3671 operands, hence the code here is free to improperly handle opcodes that
3672 have no operands (for better performance and smaller code). */
3674 if (mnemonic[0] != 'f')
3675 return 0; /* non-math */
3677 switch (mnemonic[1])
3679 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3680 the fs segment override prefix not currently handled because no
3681 call path can make opcodes without operands get here */
3683 return 2 /* integer op */;
3685 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3686 return 3; /* fldcw/fldenv */
3689 if (mnemonic[2] != 'o' /* fnop */)
3690 return 3; /* non-waiting control op */
3693 if (mnemonic[2] == 's')
3694 return 3; /* frstor/frstpm */
3697 if (mnemonic[2] == 'a')
3698 return 3; /* fsave */
3699 if (mnemonic[2] == 't')
3701 switch (mnemonic[3])
3703 case 'c': /* fstcw */
3704 case 'd': /* fstdw */
3705 case 'e': /* fstenv */
3706 case 's': /* fsts[gw] */
3712 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3713 return 0; /* fxsave/fxrstor are not really math ops */
3721 install_template (const insn_template *t)
3727 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
3728 if (t->opcode_modifier.vex && t->opcode_modifier.evex)
3730 if ((maybe_cpu (t, CpuAVX) || maybe_cpu (t, CpuAVX2)
3731 || maybe_cpu (t, CpuFMA))
3732 && (maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512VL)))
3734 if (need_evex_encoding (t))
3736 i.tm.opcode_modifier.vex = 0;
3737 i.tm.cpu.bitfield.cpuavx512f = i.tm.cpu_any.bitfield.cpuavx512f;
3738 i.tm.cpu.bitfield.cpuavx512vl = i.tm.cpu_any.bitfield.cpuavx512vl;
3742 i.tm.opcode_modifier.evex = 0;
3743 if (i.tm.cpu_any.bitfield.cpuavx)
3744 i.tm.cpu.bitfield.cpuavx = 1;
3745 else if (!i.tm.cpu.bitfield.isa)
3746 i.tm.cpu.bitfield.isa = i.tm.cpu_any.bitfield.isa;
3748 gas_assert (i.tm.cpu.bitfield.isa == i.tm.cpu_any.bitfield.isa);
3752 if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
3753 || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
3754 || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
3755 || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR))
3756 && maybe_cpu (t, CpuAPX_F))
3758 if (need_evex_encoding (t))
3759 i.tm.opcode_modifier.vex = 0;
3761 i.tm.opcode_modifier.evex = 0;
3765 /* Note that for pseudo prefixes this produces a length of 1. But for them
3766 the length isn't interesting at all. */
3767 for (l = 1; l < 4; ++l)
3768 if (!(t->base_opcode >> (8 * l)))
3771 i.opcode_length = l;
3774 /* Build the VEX prefix. */
3777 build_vex_prefix (const insn_template *t)
3779 unsigned int register_specifier;
3780 unsigned int vector_length;
3783 /* Check register specifier. */
3784 if (i.vex.register_specifier)
3786 register_specifier =
3787 ~register_number (i.vex.register_specifier) & 0xf;
3788 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3791 register_specifier = 0xf;
3793 /* Use 2-byte VEX prefix by swapping destination and source operand
3794 if there are more than 1 register operand. */
3795 if (i.reg_operands > 1
3796 && i.vec_encoding != vex_encoding_vex3
3797 && i.dir_encoding == dir_encoding_default
3798 && i.operands == i.reg_operands
3799 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3800 && i.tm.opcode_space == SPACE_0F
3801 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3806 swap_2_operands (0, i.operands - 1);
3808 gas_assert (i.rm.mode == 3);
3812 i.rm.regmem = i.rm.reg;
3815 if (i.tm.opcode_modifier.d)
3816 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3817 ? Opcode_ExtD : Opcode_SIMD_IntD;
3818 else /* Use the next insn. */
3819 install_template (&t[1]);
3822 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3823 are no memory operands and at least 3 register ones. */
3824 if (i.reg_operands >= 3
3825 && i.vec_encoding != vex_encoding_vex3
3826 && i.reg_operands == i.operands - i.imm_operands
3827 && i.tm.opcode_modifier.vex
3828 && i.tm.opcode_modifier.commutative
3829 /* .commutative aliases .staticrounding; disambiguate. */
3830 && !i.tm.opcode_modifier.sae
3831 && (i.tm.opcode_modifier.sse2avx
3832 || (optimize > 1 && !i.no_optimize))
3834 && i.vex.register_specifier
3835 && !(i.vex.register_specifier->reg_flags & RegRex))
3837 unsigned int xchg = i.operands - i.reg_operands;
3839 gas_assert (i.tm.opcode_space == SPACE_0F);
3840 gas_assert (!i.tm.opcode_modifier.sae);
3841 gas_assert (operand_type_equal (&i.types[i.operands - 2],
3842 &i.types[i.operands - 3]));
3843 gas_assert (i.rm.mode == 3);
3845 swap_2_operands (xchg, xchg + 1);
3848 xchg = i.rm.regmem | 8;
3849 i.rm.regmem = ~register_specifier & 0xf;
3850 gas_assert (!(i.rm.regmem & 8));
3851 i.vex.register_specifier += xchg - i.rm.regmem;
3852 register_specifier = ~xchg & 0xf;
3855 if (i.tm.opcode_modifier.vex == VEXScalar)
3856 vector_length = avxscalar;
3857 else if (i.tm.opcode_modifier.vex == VEX256)
3859 else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128)
3865 /* Determine vector length from the last multi-length vector
3868 for (op = t->operands; op--;)
3869 if (t->operand_types[op].bitfield.xmmword
3870 && t->operand_types[op].bitfield.ymmword
3871 && i.types[op].bitfield.ymmword)
3878 /* Check the REX.W bit and VEXW. */
3879 if (i.tm.opcode_modifier.vexw == VEXWIG)
3880 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3881 else if (i.tm.opcode_modifier.vexw)
3882 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3884 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3886 /* Use 2-byte VEX prefix if possible. */
3888 && i.vec_encoding != vex_encoding_vex3
3889 && i.tm.opcode_space == SPACE_0F
3890 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3892 /* 2-byte VEX prefix. */
3896 i.vex.bytes[0] = 0xc5;
3898 /* Check the REX.R bit. */
3899 r = (i.rex & REX_R) ? 0 : 1;
3900 i.vex.bytes[1] = (r << 7
3901 | register_specifier << 3
3902 | vector_length << 2
3903 | i.tm.opcode_modifier.opcodeprefix);
3907 /* 3-byte VEX prefix. */
3910 switch (i.tm.opcode_space)
3916 i.vex.bytes[0] = 0xc4;
3921 i.vex.bytes[0] = 0x8f;
3927 /* The high 3 bits of the second VEX byte are 1's compliment
3928 of RXB bits from REX. */
3929 i.vex.bytes[1] = ((~i.rex & 7) << 5)
3930 | (!dot_insn () ? i.tm.opcode_space
3931 : i.insn_opcode_space);
3933 i.vex.bytes[2] = (w << 7
3934 | register_specifier << 3
3935 | vector_length << 2
3936 | i.tm.opcode_modifier.opcodeprefix);
3941 is_any_vex_encoding (const insn_template *t)
3943 return t->opcode_modifier.vex || t->opcode_modifier.evex;
3946 /* We can use this function only when the current encoding is evex. */
3948 is_apx_evex_encoding (void)
3950 return i.rex2 || i.tm.opcode_space == SPACE_EVEXMAP4
3951 || (i.vex.register_specifier
3952 && (i.vex.register_specifier->reg_flags & RegRex2));
3956 is_apx_rex2_encoding (void)
3958 return i.rex2 || i.rex2_encoding
3959 || i.tm.opcode_modifier.rex2;
3963 get_broadcast_bytes (const insn_template *t, bool diag)
3965 unsigned int op, bytes;
3966 const i386_operand_type *types;
3968 if (i.broadcast.type)
3969 return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type;
3971 gas_assert (intel_syntax);
3973 for (op = 0; op < t->operands; ++op)
3974 if (t->operand_types[op].bitfield.baseindex)
3977 gas_assert (op < t->operands);
3979 if (t->opcode_modifier.evex != EVEXDYN)
3980 switch (i.broadcast.bytes)
3983 if (t->operand_types[op].bitfield.word)
3987 if (t->operand_types[op].bitfield.dword)
3991 if (t->operand_types[op].bitfield.qword)
3995 if (t->operand_types[op].bitfield.xmmword)
3997 if (t->operand_types[op].bitfield.ymmword)
3999 if (t->operand_types[op].bitfield.zmmword)
4006 gas_assert (op + 1 < t->operands);
4008 if (t->operand_types[op + 1].bitfield.xmmword
4009 + t->operand_types[op + 1].bitfield.ymmword
4010 + t->operand_types[op + 1].bitfield.zmmword > 1)
4012 types = &i.types[op + 1];
4015 else /* Ambiguous - guess with a preference to non-AVX512VL forms. */
4016 types = &t->operand_types[op];
4018 if (types->bitfield.zmmword)
4020 else if (types->bitfield.ymmword)
4026 as_warn (_("ambiguous broadcast for `%s', using %u-bit form"),
4027 insn_name (t), bytes * 8);
4032 /* Build the EVEX prefix. */
4035 build_evex_prefix (void)
4037 unsigned int register_specifier, w;
4038 rex_byte vrex_used = 0;
4040 /* Check register specifier. */
4041 if (i.vex.register_specifier)
4043 gas_assert ((i.vrex & REX_X) == 0);
4045 register_specifier = i.vex.register_specifier->reg_num;
4046 if ((i.vex.register_specifier->reg_flags & RegRex))
4047 register_specifier += 8;
4048 /* The upper 16 registers are encoded in the fourth byte of the
4050 if (!(i.vex.register_specifier->reg_flags & RegVRex))
4051 i.vex.bytes[3] = 0x8;
4052 register_specifier = ~register_specifier & 0xf;
4056 register_specifier = 0xf;
4058 /* Encode upper 16 vector index register in the fourth byte of
4060 if (!(i.vrex & REX_X))
4061 i.vex.bytes[3] = 0x8;
4066 /* 4 byte EVEX prefix. */
4068 i.vex.bytes[0] = 0x62;
4070 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4072 gas_assert (i.tm.opcode_space >= SPACE_0F);
4073 gas_assert (i.tm.opcode_space <= SPACE_VEXMAP7);
4074 i.vex.bytes[1] = ((~i.rex & 7) << 5)
4075 | (!dot_insn () ? i.tm.opcode_space
4076 : i.insn_opcode_space);
4078 /* The fifth bit of the second EVEX byte is 1's compliment of the
4079 REX_R bit in VREX. */
4080 if (!(i.vrex & REX_R))
4081 i.vex.bytes[1] |= 0x10;
4085 if ((i.reg_operands + i.imm_operands) == i.operands)
4087 /* When all operands are registers, the REX_X bit in REX is not
4088 used. We reuse it to encode the upper 16 registers, which is
4089 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4090 as 1's compliment. */
4091 if ((i.vrex & REX_B))
4094 i.vex.bytes[1] &= ~0x40;
4098 /* EVEX instructions shouldn't need the REX prefix. */
4099 i.vrex &= ~vrex_used;
4100 gas_assert (i.vrex == 0);
4102 /* Check the REX.W bit and VEXW. */
4103 if (i.tm.opcode_modifier.vexw == VEXWIG)
4104 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
4105 else if (i.tm.opcode_modifier.vexw)
4106 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
4108 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
4110 /* The third byte of the EVEX prefix. */
4111 i.vex.bytes[2] = ((w << 7)
4112 | (register_specifier << 3)
4113 | 4 /* Encode the U bit. */
4114 | i.tm.opcode_modifier.opcodeprefix);
4116 /* The fourth byte of the EVEX prefix. */
4117 /* The zeroing-masking bit. */
4118 if (i.mask.reg && i.mask.zeroing)
4119 i.vex.bytes[3] |= 0x80;
4121 /* Don't always set the broadcast bit if there is no RC. */
4122 if (i.rounding.type == rc_none)
4124 /* Encode the vector length. */
4125 unsigned int vec_length;
4127 if (i.tm.opcode_modifier.evex == EVEXDYN)
4131 /* Determine vector length from the last multi-length vector
4133 for (op = i.operands; op--;)
4134 if (i.tm.operand_types[op].bitfield.xmmword
4135 + i.tm.operand_types[op].bitfield.ymmword
4136 + i.tm.operand_types[op].bitfield.zmmword > 1)
4138 if (i.types[op].bitfield.zmmword)
4140 i.tm.opcode_modifier.evex = EVEX512;
4143 else if (i.types[op].bitfield.ymmword)
4145 i.tm.opcode_modifier.evex = EVEX256;
4148 else if (i.types[op].bitfield.xmmword)
4150 i.tm.opcode_modifier.evex = EVEX128;
4153 else if ((i.broadcast.type || i.broadcast.bytes)
4154 && op == i.broadcast.operand)
4156 switch (get_broadcast_bytes (&i.tm, true))
4159 i.tm.opcode_modifier.evex = EVEX512;
4162 i.tm.opcode_modifier.evex = EVEX256;
4165 i.tm.opcode_modifier.evex = EVEX128;
4174 if (op >= MAX_OPERANDS)
4178 switch (i.tm.opcode_modifier.evex)
4180 case EVEXLIG: /* LL' is ignored */
4181 vec_length = evexlig << 5;
4184 vec_length = 0 << 5;
4187 vec_length = 1 << 5;
4190 vec_length = 2 << 5;
4195 vec_length = 3 << 5;
4203 i.vex.bytes[3] |= vec_length;
4204 /* Encode the broadcast bit. */
4205 if (i.broadcast.type || i.broadcast.bytes)
4206 i.vex.bytes[3] |= 0x10;
4208 else if (i.rounding.type != saeonly)
4209 i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5);
4211 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
4214 i.vex.bytes[3] |= i.mask.reg->reg_num;
4217 /* Build (2 bytes) rex2 prefix.
4219 | m | R4 X4 B4 | W R X B |
4221 Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes.
4224 build_rex2_prefix (void)
4227 i.vex.bytes[0] = 0xd5;
4228 /* For the W R X B bits, the variables of rex prefix will be reused. */
4229 i.vex.bytes[1] = ((i.tm.opcode_space << 7)
4230 | (i.rex2 << 4) | i.rex);
4233 /* Build the EVEX prefix (4-byte) for evex insn
4235 | `R`X`B`R' | B'mmm |
4236 | W | v`v`v`v | `x' | pp |
4237 | z| L'L | b | `v | aaa |
4240 build_apx_evex_prefix (void)
4242 build_evex_prefix ();
4244 i.vex.bytes[1] &= ~0x10;
4246 i.vex.bytes[1] |= 0x08;
4248 i.vex.bytes[2] &= ~0x04;
4249 if (i.vex.register_specifier
4250 && i.vex.register_specifier->reg_flags & RegRex2)
4251 i.vex.bytes[3] &= ~0x08;
4253 /* Encode the NDD bit of the instruction promoted from the legacy
4255 if (i.vex.register_specifier && i.tm.opcode_space == SPACE_EVEXMAP4)
4256 i.vex.bytes[3] |= 0x10;
4259 static void establish_rex (void)
4261 /* Note that legacy encodings have at most 2 non-immediate operands. */
4262 unsigned int first = i.imm_operands;
4263 unsigned int last = i.operands > first ? i.operands - first - 1 : first;
4265 /* Respect a user-specified REX prefix. */
4266 i.rex |= i.prefix[REX_PREFIX] & REX_OPCODE;
4268 /* For 8 bit registers we need an empty rex prefix. Also if the
4269 instruction already has a prefix, we need to convert old
4270 registers to new ones. */
4272 if ((i.types[first].bitfield.class == Reg && i.types[first].bitfield.byte
4273 && ((i.op[first].regs->reg_flags & RegRex64) != 0 || i.rex != 0
4275 || (i.types[last].bitfield.class == Reg && i.types[last].bitfield.byte
4276 && ((i.op[last].regs->reg_flags & RegRex64) != 0 || i.rex != 0
4281 if (!is_apx_rex2_encoding () && !is_any_vex_encoding(&i.tm))
4282 i.rex |= REX_OPCODE;
4283 for (x = first; x <= last; x++)
4285 /* Look for 8 bit operand that uses old registers. */
4286 if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte
4287 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4289 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4290 /* In case it is "hi" register, give up. */
4291 if (i.op[x].regs->reg_num > 3)
4292 as_bad (_("can't encode register '%s%s' in an "
4293 "instruction requiring REX/REX2 prefix"),
4294 register_prefix, i.op[x].regs->reg_name);
4296 /* Otherwise it is equivalent to the extended register.
4297 Since the encoding doesn't change this is merely
4298 cosmetic cleanup for debug output. */
4304 if (i.rex == 0 && i.rex2 == 0 && (i.rex_encoding || i.rex2_encoding))
4306 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4307 that uses legacy register. If it is "hi" register, don't add
4308 rex and rex2 prefix. */
4311 for (x = first; x <= last; x++)
4312 if (i.types[x].bitfield.class == Reg
4313 && i.types[x].bitfield.byte
4314 && (i.op[x].regs->reg_flags & RegRex64) == 0
4315 && i.op[x].regs->reg_num > 3)
4317 gas_assert (!(i.op[x].regs->reg_flags & RegRex));
4318 i.rex_encoding = false;
4319 i.rex2_encoding = false;
4327 if (is_apx_rex2_encoding ())
4329 build_rex2_prefix ();
4330 /* The individual REX.RXBW bits got consumed. */
4331 i.rex &= REX_OPCODE;
4333 else if (i.rex != 0)
4334 add_prefix (REX_OPCODE | i.rex);
4338 process_immext (void)
4342 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4343 which is coded in the same place as an 8-bit immediate field
4344 would be. Here we fake an 8-bit immediate operand from the
4345 opcode suffix stored in tm.extension_opcode.
4347 AVX instructions also use this encoding, for some of
4348 3 argument instructions. */
4350 gas_assert (i.imm_operands <= 1
4352 || (is_any_vex_encoding (&i.tm)
4353 && i.operands <= 4)));
4355 exp = &im_expressions[i.imm_operands++];
4356 i.op[i.operands].imms = exp;
4357 i.types[i.operands].bitfield.imm8 = 1;
4359 exp->X_op = O_constant;
4360 exp->X_add_number = i.tm.extension_opcode;
4361 i.tm.extension_opcode = None;
4368 switch (i.tm.opcode_modifier.prefixok)
4376 as_bad (_("invalid instruction `%s' after `%s'"),
4377 insn_name (&i.tm), i.hle_prefix);
4380 if (i.prefix[LOCK_PREFIX])
4382 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
4386 case PrefixHLERelease:
4387 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
4389 as_bad (_("instruction `%s' after `xacquire' not allowed"),
4393 if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem))
4395 as_bad (_("memory destination needed for instruction `%s'"
4396 " after `xrelease'"), insn_name (&i.tm));
4403 /* Encode aligned vector move as unaligned vector move. */
4406 encode_with_unaligned_vector_move (void)
4408 switch (i.tm.base_opcode)
4410 case 0x28: /* Load instructions. */
4411 case 0x29: /* Store instructions. */
4412 /* movaps/movapd/vmovaps/vmovapd. */
4413 if (i.tm.opcode_space == SPACE_0F
4414 && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66)
4415 i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1);
4417 case 0x6f: /* Load instructions. */
4418 case 0x7f: /* Store instructions. */
4419 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4420 if (i.tm.opcode_space == SPACE_0F
4421 && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66)
4422 i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
4429 /* Try the shortest encoding by shortening operand size. */
4432 optimize_encoding (void)
4436 if (i.tm.mnem_off == MN_lea)
4439 lea symbol, %rN -> mov $symbol, %rN
4440 lea (%rM), %rN -> mov %rM, %rN
4441 lea (,%rM,1), %rN -> mov %rM, %rN
4443 and in 32-bit mode for 16-bit addressing
4445 lea (%rM), %rN -> movzx %rM, %rN
4447 and in 64-bit mode zap 32-bit addressing in favor of using a
4448 32-bit (or less) destination.
4450 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4452 if (!i.op[1].regs->reg_type.bitfield.word)
4453 i.tm.opcode_modifier.size = SIZE32;
4454 i.prefix[ADDR_PREFIX] = 0;
4457 if (!i.index_reg && !i.base_reg)
4460 lea symbol, %rN -> mov $symbol, %rN
4462 if (flag_code == CODE_64BIT)
4464 /* Don't transform a relocation to a 16-bit one. */
4466 && i.op[0].disps->X_op != O_constant
4467 && i.op[1].regs->reg_type.bitfield.word)
4470 if (!i.op[1].regs->reg_type.bitfield.qword
4471 || i.tm.opcode_modifier.size == SIZE32)
4473 i.tm.base_opcode = 0xb8;
4474 i.tm.opcode_modifier.modrm = 0;
4475 if (!i.op[1].regs->reg_type.bitfield.word)
4476 i.types[0].bitfield.imm32 = 1;
4479 i.tm.opcode_modifier.size = SIZE16;
4480 i.types[0].bitfield.imm16 = 1;
4485 /* Subject to further optimization below. */
4486 i.tm.base_opcode = 0xc7;
4487 i.tm.extension_opcode = 0;
4488 i.types[0].bitfield.imm32s = 1;
4489 i.types[0].bitfield.baseindex = 0;
4492 /* Outside of 64-bit mode address and operand sizes have to match if
4493 a relocation is involved, as otherwise we wouldn't (currently) or
4494 even couldn't express the relocation correctly. */
4495 else if (i.op[0].disps
4496 && i.op[0].disps->X_op != O_constant
4497 && ((!i.prefix[ADDR_PREFIX])
4498 != (flag_code == CODE_32BIT
4499 ? i.op[1].regs->reg_type.bitfield.dword
4500 : i.op[1].regs->reg_type.bitfield.word)))
4502 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4503 destination is going to grow encoding size. */
4504 else if (flag_code == CODE_16BIT
4505 && (optimize <= 1 || optimize_for_space)
4506 && !i.prefix[ADDR_PREFIX]
4507 && i.op[1].regs->reg_type.bitfield.dword)
4511 i.tm.base_opcode = 0xb8;
4512 i.tm.opcode_modifier.modrm = 0;
4513 if (i.op[1].regs->reg_type.bitfield.dword)
4514 i.types[0].bitfield.imm32 = 1;
4516 i.types[0].bitfield.imm16 = 1;
4519 && i.op[0].disps->X_op == O_constant
4520 && i.op[1].regs->reg_type.bitfield.dword
4521 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4523 && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT))
4524 i.op[0].disps->X_add_number &= 0xffff;
4527 i.tm.operand_types[0] = i.types[0];
4531 i.op[0].imms = &im_expressions[0];
4532 i.op[0].imms->X_op = O_absent;
4535 else if (i.op[0].disps
4536 && (i.op[0].disps->X_op != O_constant
4537 || i.op[0].disps->X_add_number))
4542 lea (%rM), %rN -> mov %rM, %rN
4543 lea (,%rM,1), %rN -> mov %rM, %rN
4544 lea (%rM), %rN -> movzx %rM, %rN
4546 const reg_entry *addr_reg;
4548 if (!i.index_reg && i.base_reg->reg_num != RegIP)
4549 addr_reg = i.base_reg;
4550 else if (!i.base_reg
4551 && i.index_reg->reg_num != RegIZ
4552 && !i.log2_scale_factor)
4553 addr_reg = i.index_reg;
4557 if (addr_reg->reg_type.bitfield.word
4558 && i.op[1].regs->reg_type.bitfield.dword)
4560 if (flag_code != CODE_32BIT)
4562 i.tm.opcode_space = SPACE_0F;
4563 i.tm.base_opcode = 0xb7;
4566 i.tm.base_opcode = 0x8b;
4568 if (addr_reg->reg_type.bitfield.dword
4569 && i.op[1].regs->reg_type.bitfield.qword)
4570 i.tm.opcode_modifier.size = SIZE32;
4572 i.op[0].regs = addr_reg;
4577 i.disp_operands = 0;
4578 i.prefix[ADDR_PREFIX] = 0;
4579 i.prefix[SEG_PREFIX] = 0;
4583 if (optimize_for_space
4584 && i.tm.mnem_off == MN_test
4585 && i.reg_operands == 1
4586 && i.imm_operands == 1
4587 && !i.types[1].bitfield.byte
4588 && i.op[0].imms->X_op == O_constant
4589 && fits_in_imm7 (i.op[0].imms->X_add_number))
4592 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4594 unsigned int base_regnum = i.op[1].regs->reg_num;
4595 if (flag_code == CODE_64BIT || base_regnum < 4)
4597 i.types[1].bitfield.byte = 1;
4598 /* Ignore the suffix. */
4600 /* Convert to byte registers. 8-bit registers are special,
4601 RegRex64 and non-RegRex64 each have 8 registers. */
4602 if (i.types[1].bitfield.word)
4603 /* 32 (or 40) 8-bit registers. */
4605 else if (i.types[1].bitfield.dword)
4606 /* 32 (or 40) 8-bit registers + 32 16-bit registers. */
4609 /* 32 (or 40) 8-bit registers + 32 16-bit registers
4610 + 32 32-bit registers. */
4613 /* In 64-bit mode, the following byte registers cannot be accessed
4614 if using the Rex and Rex2 prefix: AH, BH, CH, DH */
4615 if (!(i.op[1].regs->reg_flags & (RegRex | RegRex2)) && base_regnum < 4)
4620 else if (flag_code == CODE_64BIT
4621 && i.tm.opcode_space == SPACE_BASE
4622 && ((i.types[1].bitfield.qword
4623 && i.reg_operands == 1
4624 && i.imm_operands == 1
4625 && i.op[0].imms->X_op == O_constant
4626 && ((i.tm.base_opcode == 0xb8
4627 && i.tm.extension_opcode == None
4628 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
4629 || (fits_in_imm31 (i.op[0].imms->X_add_number)
4630 && (i.tm.base_opcode == 0x24
4631 || (i.tm.base_opcode == 0x80
4632 && i.tm.extension_opcode == 0x4)
4633 || i.tm.mnem_off == MN_test
4634 || ((i.tm.base_opcode | 1) == 0xc7
4635 && i.tm.extension_opcode == 0x0)))
4636 || (fits_in_imm7 (i.op[0].imms->X_add_number)
4637 && i.tm.base_opcode == 0x83
4638 && i.tm.extension_opcode == 0x4)))
4639 || (i.types[0].bitfield.qword
4640 && ((i.reg_operands == 2
4641 && i.op[0].regs == i.op[1].regs
4642 && (i.tm.mnem_off == MN_xor
4643 || i.tm.mnem_off == MN_sub))
4644 || i.tm.mnem_off == MN_clr))))
4647 andq $imm31, %r64 -> andl $imm31, %r32
4648 andq $imm7, %r64 -> andl $imm7, %r32
4649 testq $imm31, %r64 -> testl $imm31, %r32
4650 xorq %r64, %r64 -> xorl %r32, %r32
4651 subq %r64, %r64 -> subl %r32, %r32
4652 movq $imm31, %r64 -> movl $imm31, %r32
4653 movq $imm32, %r64 -> movl $imm32, %r32
4655 i.tm.opcode_modifier.size = SIZE32;
4658 i.types[0].bitfield.imm32 = 1;
4659 i.types[0].bitfield.imm32s = 0;
4660 i.types[0].bitfield.imm64 = 0;
4664 i.types[0].bitfield.dword = 1;
4665 i.types[0].bitfield.qword = 0;
4667 i.types[1].bitfield.dword = 1;
4668 i.types[1].bitfield.qword = 0;
4669 if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea)
4672 movq $imm31, %r64 -> movl $imm31, %r32
4673 movq $imm32, %r64 -> movl $imm32, %r32
4675 i.tm.operand_types[0].bitfield.imm32 = 1;
4676 i.tm.operand_types[0].bitfield.imm32s = 0;
4677 i.tm.operand_types[0].bitfield.imm64 = 0;
4678 if ((i.tm.base_opcode | 1) == 0xc7)
4681 movq $imm31, %r64 -> movl $imm31, %r32
4683 i.tm.base_opcode = 0xb8;
4684 i.tm.extension_opcode = None;
4685 i.tm.opcode_modifier.w = 0;
4686 i.tm.opcode_modifier.modrm = 0;
4690 else if (optimize > 1
4691 && !optimize_for_space
4692 && i.reg_operands == 2
4693 && i.op[0].regs == i.op[1].regs
4694 && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or)
4695 && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4698 andb %rN, %rN -> testb %rN, %rN
4699 andw %rN, %rN -> testw %rN, %rN
4700 andq %rN, %rN -> testq %rN, %rN
4701 orb %rN, %rN -> testb %rN, %rN
4702 orw %rN, %rN -> testw %rN, %rN
4703 orq %rN, %rN -> testq %rN, %rN
4705 and outside of 64-bit mode
4707 andl %rN, %rN -> testl %rN, %rN
4708 orl %rN, %rN -> testl %rN, %rN
4710 i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4712 else if (i.tm.base_opcode == 0xba
4713 && i.tm.opcode_space == SPACE_0F
4714 && i.reg_operands == 1
4715 && i.op[0].imms->X_op == O_constant
4716 && i.op[0].imms->X_add_number >= 0)
4719 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
4720 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
4721 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4723 With <BT> one of bts, btr, and bts also:
4724 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
4725 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
4730 if (i.tm.extension_opcode != 4)
4732 if (i.types[1].bitfield.qword
4733 && i.op[0].imms->X_add_number < 32
4734 && !(i.op[1].regs->reg_flags & RegRex))
4735 i.tm.opcode_modifier.size = SIZE32;
4738 if (i.types[1].bitfield.word
4739 && i.op[0].imms->X_add_number < 16)
4740 i.tm.opcode_modifier.size = SIZE32;
4743 if (i.op[0].imms->X_add_number < 16)
4744 i.tm.opcode_modifier.size = SIZE16;
4748 else if (i.reg_operands == 3
4749 && i.op[0].regs == i.op[1].regs
4750 && !i.types[2].bitfield.xmmword
4751 && (i.tm.opcode_modifier.vex
4752 || ((!i.mask.reg || i.mask.zeroing)
4753 && i.tm.opcode_modifier.evex
4754 && (i.vec_encoding != vex_encoding_evex
4755 || cpu_arch_isa_flags.bitfield.cpuavx512vl
4756 || is_cpu (&i.tm, CpuAVX512VL)
4757 || (i.tm.operand_types[2].bitfield.zmmword
4758 && i.types[2].bitfield.ymmword))))
4759 && i.tm.opcode_space == SPACE_0F
4760 && ((i.tm.base_opcode | 2) == 0x57
4761 || i.tm.base_opcode == 0xdf
4762 || i.tm.base_opcode == 0xef
4763 || (i.tm.base_opcode | 3) == 0xfb
4764 || i.tm.base_opcode == 0x42
4765 || i.tm.base_opcode == 0x47))
4768 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4770 EVEX VOP %zmmM, %zmmM, %zmmN
4771 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4772 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4773 EVEX VOP %ymmM, %ymmM, %ymmN
4774 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4775 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4776 VEX VOP %ymmM, %ymmM, %ymmN
4777 -> VEX VOP %xmmM, %xmmM, %xmmN
4778 VOP, one of vpandn and vpxor:
4779 VEX VOP %ymmM, %ymmM, %ymmN
4780 -> VEX VOP %xmmM, %xmmM, %xmmN
4781 VOP, one of vpandnd and vpandnq:
4782 EVEX VOP %zmmM, %zmmM, %zmmN
4783 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4784 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4785 EVEX VOP %ymmM, %ymmM, %ymmN
4786 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4787 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4788 VOP, one of vpxord and vpxorq:
4789 EVEX VOP %zmmM, %zmmM, %zmmN
4790 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4791 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4792 EVEX VOP %ymmM, %ymmM, %ymmN
4793 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4794 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4795 VOP, one of kxord and kxorq:
4796 VEX VOP %kM, %kM, %kN
4797 -> VEX kxorw %kM, %kM, %kN
4798 VOP, one of kandnd and kandnq:
4799 VEX VOP %kM, %kM, %kN
4800 -> VEX kandnw %kM, %kM, %kN
4802 if (i.tm.opcode_modifier.evex)
4804 if (i.vec_encoding != vex_encoding_evex)
4806 i.tm.opcode_modifier.vex = VEX128;
4807 i.tm.opcode_modifier.vexw = VEXW0;
4808 i.tm.opcode_modifier.evex = 0;
4809 i.vec_encoding = vex_encoding_vex;
4812 else if (optimize > 1)
4813 i.tm.opcode_modifier.evex = EVEX128;
4817 else if (i.tm.operand_types[0].bitfield.class == RegMask)
4819 i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE;
4820 i.tm.opcode_modifier.vexw = VEXW0;
4823 i.tm.opcode_modifier.vex = VEX128;
4825 if (i.tm.opcode_modifier.vex)
4826 for (j = 0; j < 3; j++)
4828 i.types[j].bitfield.xmmword = 1;
4829 i.types[j].bitfield.ymmword = 0;
4832 else if (i.vec_encoding != vex_encoding_evex
4833 && !i.types[0].bitfield.zmmword
4834 && !i.types[1].bitfield.zmmword
4836 && !i.broadcast.type
4837 && !i.broadcast.bytes
4838 && i.tm.opcode_modifier.evex
4839 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
4840 || (i.tm.base_opcode & ~4) == 0xdb
4841 || (i.tm.base_opcode & ~4) == 0xeb)
4842 && i.tm.extension_opcode == None)
4845 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4846 vmovdqu32 and vmovdqu64:
4847 EVEX VOP %xmmM, %xmmN
4848 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4849 EVEX VOP %ymmM, %ymmN
4850 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4852 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4854 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4856 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4858 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4859 VOP, one of vpand, vpandn, vpor, vpxor:
4860 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4861 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4862 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4863 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4864 EVEX VOP{d,q} mem, %xmmM, %xmmN
4865 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4866 EVEX VOP{d,q} mem, %ymmM, %ymmN
4867 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4869 for (j = 0; j < i.operands; j++)
4870 if (operand_type_check (i.types[j], disp)
4871 && i.op[j].disps->X_op == O_constant)
4873 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4874 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4875 bytes, we choose EVEX Disp8 over VEX Disp32. */
4876 int evex_disp8, vex_disp8;
4877 unsigned int memshift = i.memshift;
4878 offsetT n = i.op[j].disps->X_add_number;
4880 evex_disp8 = fits_in_disp8 (n);
4882 vex_disp8 = fits_in_disp8 (n);
4883 if (evex_disp8 != vex_disp8)
4885 i.memshift = memshift;
4889 i.types[j].bitfield.disp8 = vex_disp8;
4892 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f
4893 && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2)
4894 i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
4895 i.tm.opcode_modifier.vex
4896 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4897 i.tm.opcode_modifier.vexw = VEXW0;
4898 /* VPAND, VPOR, and VPXOR are commutative. */
4899 if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf)
4900 i.tm.opcode_modifier.commutative = 1;
4901 i.tm.opcode_modifier.evex = 0;
4902 i.tm.opcode_modifier.masking = 0;
4903 i.tm.opcode_modifier.broadcast = 0;
4904 i.tm.opcode_modifier.disp8memshift = 0;
4907 i.types[j].bitfield.disp8
4908 = fits_in_disp8 (i.op[j].disps->X_add_number);
4910 else if (optimize_for_space
4911 && i.tm.base_opcode == 0x29
4912 && i.tm.opcode_space == SPACE_0F38
4913 && i.operands == i.reg_operands
4914 && i.op[0].regs == i.op[1].regs
4915 && (!i.tm.opcode_modifier.vex
4916 || !(i.op[0].regs->reg_flags & RegRex))
4917 && !i.tm.opcode_modifier.evex)
4920 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
4921 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
4922 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
4924 i.tm.opcode_space = SPACE_0F;
4925 i.tm.base_opcode = 0x76;
4927 else if (((i.tm.base_opcode >= 0x64
4928 && i.tm.base_opcode <= 0x66
4929 && i.tm.opcode_space == SPACE_0F)
4930 || (i.tm.base_opcode == 0x37
4931 && i.tm.opcode_space == SPACE_0F38))
4932 && i.operands == i.reg_operands
4933 && i.op[0].regs == i.op[1].regs
4934 && !i.tm.opcode_modifier.evex)
4937 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
4938 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
4939 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
4940 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
4941 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
4942 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
4944 i.tm.opcode_space = SPACE_0F;
4945 i.tm.base_opcode = 0xef;
4946 if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex))
4948 if (i.operands == 2)
4950 gas_assert (i.tm.opcode_modifier.sse2avx);
4956 i.op[2].regs = i.op[0].regs;
4957 i.types[2] = i.types[0];
4958 i.flags[2] = i.flags[0];
4959 i.tm.operand_types[2] = i.tm.operand_types[0];
4961 i.tm.opcode_modifier.sse2avx = 0;
4963 i.op[0].regs -= i.op[0].regs->reg_num + 8;
4964 i.op[1].regs = i.op[0].regs;
4967 else if (optimize_for_space
4968 && i.tm.base_opcode == 0x59
4969 && i.tm.opcode_space == SPACE_0F38
4970 && i.operands == i.reg_operands
4971 && i.tm.opcode_modifier.vex
4972 && !(i.op[0].regs->reg_flags & RegRex)
4973 && i.op[0].regs->reg_type.bitfield.xmmword
4974 && i.vec_encoding != vex_encoding_vex3)
4977 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
4979 i.tm.opcode_space = SPACE_0F;
4980 i.tm.base_opcode = 0x6c;
4981 i.tm.opcode_modifier.vexvvvv = 1;
4987 i.op[2].regs = i.op[0].regs;
4988 i.types[2] = i.types[0];
4989 i.flags[2] = i.flags[0];
4990 i.tm.operand_types[2] = i.tm.operand_types[0];
4992 swap_2_operands (1, 2);
4996 /* Return non-zero for load instruction. */
5002 int any_vex_p = is_any_vex_encoding (&i.tm);
5003 unsigned int base_opcode = i.tm.base_opcode | 1;
5007 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
5008 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
5009 if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE)
5013 if (i.tm.mnem_off == MN_pop)
5017 if (i.tm.opcode_space == SPACE_BASE)
5020 if (i.tm.base_opcode == 0x9d
5021 || i.tm.base_opcode == 0x61)
5024 /* movs, cmps, lods, scas. */
5025 if ((i.tm.base_opcode | 0xb) == 0xaf)
5029 if (base_opcode == 0x6f
5030 || i.tm.base_opcode == 0xd7)
5032 /* NB: For AMD-specific insns with implicit memory operands,
5033 they're intentionally not covered. */
5036 /* No memory operand. */
5037 if (!i.mem_operands)
5042 if (i.tm.mnem_off == MN_vldmxcsr)
5045 else if (i.tm.opcode_space == SPACE_BASE)
5047 /* test, not, neg, mul, imul, div, idiv. */
5048 if (base_opcode == 0xf7 && i.tm.extension_opcode != 1)
5052 if (base_opcode == 0xff && i.tm.extension_opcode <= 1)
5055 /* add, or, adc, sbb, and, sub, xor, cmp. */
5056 if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83)
5059 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
5060 if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3)
5061 && i.tm.extension_opcode != 6)
5064 /* Check for x87 instructions. */
5065 if ((base_opcode | 6) == 0xdf)
5067 /* Skip fst, fstp, fstenv, fstcw. */
5068 if (i.tm.base_opcode == 0xd9
5069 && (i.tm.extension_opcode == 2
5070 || i.tm.extension_opcode == 3
5071 || i.tm.extension_opcode == 6
5072 || i.tm.extension_opcode == 7))
5075 /* Skip fisttp, fist, fistp, fstp. */
5076 if (i.tm.base_opcode == 0xdb
5077 && (i.tm.extension_opcode == 1
5078 || i.tm.extension_opcode == 2
5079 || i.tm.extension_opcode == 3
5080 || i.tm.extension_opcode == 7))
5083 /* Skip fisttp, fst, fstp, fsave, fstsw. */
5084 if (i.tm.base_opcode == 0xdd
5085 && (i.tm.extension_opcode == 1
5086 || i.tm.extension_opcode == 2
5087 || i.tm.extension_opcode == 3
5088 || i.tm.extension_opcode == 6
5089 || i.tm.extension_opcode == 7))
5092 /* Skip fisttp, fist, fistp, fbstp, fistp. */
5093 if (i.tm.base_opcode == 0xdf
5094 && (i.tm.extension_opcode == 1
5095 || i.tm.extension_opcode == 2
5096 || i.tm.extension_opcode == 3
5097 || i.tm.extension_opcode == 6
5098 || i.tm.extension_opcode == 7))
5104 else if (i.tm.opcode_space == SPACE_0F)
5106 /* bt, bts, btr, btc. */
5107 if (i.tm.base_opcode == 0xba
5108 && (i.tm.extension_opcode | 3) == 7)
5111 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
5112 if (i.tm.base_opcode == 0xc7
5113 && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE
5114 && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3
5115 || i.tm.extension_opcode == 6))
5118 /* fxrstor, ldmxcsr, xrstor. */
5119 if (i.tm.base_opcode == 0xae
5120 && (i.tm.extension_opcode == 1
5121 || i.tm.extension_opcode == 2
5122 || i.tm.extension_opcode == 5))
5125 /* lgdt, lidt, lmsw. */
5126 if (i.tm.base_opcode == 0x01
5127 && (i.tm.extension_opcode == 2
5128 || i.tm.extension_opcode == 3
5129 || i.tm.extension_opcode == 6))
5133 dest = i.operands - 1;
5135 /* Check fake imm8 operand and 3 source operands. */
5136 if ((i.tm.opcode_modifier.immext
5137 || i.reg_operands + i.mem_operands == 4)
5138 && i.types[dest].bitfield.imm8)
5141 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
5142 if (i.tm.opcode_space == SPACE_BASE
5143 && ((base_opcode | 0x38) == 0x39
5144 || (base_opcode | 2) == 0x87))
5147 if (i.tm.mnem_off == MN_xadd)
5150 /* Check for load instruction. */
5151 return (i.types[dest].bitfield.class != ClassNone
5152 || i.types[dest].bitfield.instance == Accum);
5155 /* Output lfence, 0xfaee8, after instruction. */
5158 insert_lfence_after (void)
5160 if (lfence_after_load && load_insn_p ())
5162 /* There are also two REP string instructions that require
5163 special treatment. Specifically, the compare string (CMPS)
5164 and scan string (SCAS) instructions set EFLAGS in a manner
5165 that depends on the data being compared/scanned. When used
5166 with a REP prefix, the number of iterations may therefore
5167 vary depending on this data. If the data is a program secret
5168 chosen by the adversary using an LVI method,
5169 then this data-dependent behavior may leak some aspect
5171 if (((i.tm.base_opcode | 0x9) == 0xaf)
5172 && i.prefix[REP_PREFIX])
5174 as_warn (_("`%s` changes flags which would affect control flow behavior"),
5177 char *p = frag_more (3);
5184 /* Output lfence, 0xfaee8, before instruction. */
5187 insert_lfence_before (const struct last_insn *last_insn)
5191 if (i.tm.opcode_space != SPACE_BASE)
5194 if (i.tm.base_opcode == 0xff
5195 && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4))
5197 /* Insert lfence before indirect branch if needed. */
5199 if (lfence_before_indirect_branch == lfence_branch_none)
5202 if (i.operands != 1)
5205 if (i.reg_operands == 1)
5207 /* Indirect branch via register. Don't insert lfence with
5208 -mlfence-after-load=yes. */
5209 if (lfence_after_load
5210 || lfence_before_indirect_branch == lfence_branch_memory)
5213 else if (i.mem_operands == 1
5214 && lfence_before_indirect_branch != lfence_branch_register)
5216 as_warn (_("indirect `%s` with memory operand should be avoided"),
5223 if (last_insn->kind != last_insn_other)
5225 as_warn_where (last_insn->file, last_insn->line,
5226 _("`%s` skips -mlfence-before-indirect-branch on `%s`"),
5227 last_insn->name, insn_name (&i.tm));
5238 /* Output or/not/shl and lfence before near ret. */
5239 if (lfence_before_ret != lfence_before_ret_none
5240 && (i.tm.base_opcode | 1) == 0xc3)
5242 if (last_insn->kind != last_insn_other)
5244 as_warn_where (last_insn->file, last_insn->line,
5245 _("`%s` skips -mlfence-before-ret on `%s`"),
5246 last_insn->name, insn_name (&i.tm));
5250 /* Near ret ingore operand size override under CPU64. */
5251 char prefix = flag_code == CODE_64BIT
5253 : i.prefix[DATA_PREFIX] ? 0x66 : 0x0;
5255 if (lfence_before_ret == lfence_before_ret_not)
5257 /* not: 0xf71424, may add prefix
5258 for operand size override or 64-bit code. */
5259 p = frag_more ((prefix ? 2 : 0) + 6 + 3);
5273 p = frag_more ((prefix ? 1 : 0) + 4 + 3);
5276 if (lfence_before_ret == lfence_before_ret_or)
5278 /* or: 0x830c2400, may add prefix
5279 for operand size override or 64-bit code. */
5285 /* shl: 0xc1242400, may add prefix
5286 for operand size override or 64-bit code. */
5301 /* Shared helper for md_assemble() and s_insn(). */
5302 static void init_globals (void)
5306 memset (&i, '\0', sizeof (i));
5307 i.rounding.type = rc_none;
5308 for (j = 0; j < MAX_OPERANDS; j++)
5309 i.reloc[j] = NO_RELOC;
5310 memset (disp_expressions, '\0', sizeof (disp_expressions));
5311 memset (im_expressions, '\0', sizeof (im_expressions));
5312 save_stack_p = save_stack;
5315 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
5316 parsing pass. Instead of introducing a rarely use new insn attribute this
5317 utilizes a common pattern between affected templates. It is deemed
5318 acceptable that this will lead to unnecessary pass 2 preparations in a
5319 limited set of cases. */
5320 static INLINE bool may_need_pass2 (const insn_template *t)
5322 return t->opcode_modifier.sse2avx
5323 /* Note that all SSE2AVX templates have at least one operand. */
5324 ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD
5325 : (t->opcode_space == SPACE_0F
5326 && (t->base_opcode | 1) == 0xbf)
5327 || (t->opcode_space == SPACE_BASE
5328 && t->base_opcode == 0x63);
5331 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5333 /* DWARF register number for EFLAGS. Used for pushf/popf insns. */
5334 #define GINSN_DW2_REGNUM_EFLAGS 49
5335 /* DWARF register number for RSI. Used as dummy value when RegIP/RegIZ. */
5336 #define GINSN_DW2_REGNUM_RSI_DUMMY 4
5338 /* Identify the callee-saved registers in System V AMD64 ABI. */
5341 x86_scfi_callee_saved_p (unsigned int dw2reg_num)
5343 if (dw2reg_num == 3 /* rbx. */
5344 || dw2reg_num == REG_FP /* rbp. */
5345 || dw2reg_num == REG_SP /* rsp. */
5346 || (dw2reg_num >= 12 && dw2reg_num <= 15) /* r12 - r15. */)
5352 /* Check whether an instruction prefix which affects operation size
5353 accompanies. For insns in the legacy space, setting REX.W takes precedence
5354 over the operand-size prefix (66H) when both are used.
5356 The current users of this API are in the handlers for PUSH, POP or other
5357 instructions which affect the stack pointer implicitly: the operation size
5358 (16, 32, or 64 bits) determines the amount by which the stack pointer is
5359 incremented / decremented (2, 4 or 8). */
5362 ginsn_opsize_prefix_p (void)
5364 return (!(i.prefix[REX_PREFIX] & REX_W) && i.prefix[DATA_PREFIX]);
5367 /* Get the DWARF register number for the given register entry.
5368 For specific byte/word/dword register accesses like al, cl, ah, ch, r8d,
5369 r20w etc., we need to identify the DWARF register number for the
5370 corresponding 8-byte GPR.
5372 This function is a hack - it relies on relative ordering of reg entries in
5373 the i386_regtab. FIXME - it will be good to allow a more direct way to get
5374 this information. */
5377 ginsn_dw2_regnum (const reg_entry *ireg)
5379 /* PS: Note the data type here as int32_t, because of Dw2Inval (-1). */
5380 int32_t dwarf_reg = Dw2Inval;
5381 const reg_entry *temp = ireg;
5382 unsigned int idx = 0;
5384 /* ginsn creation is available for AMD64 abi only ATM. Other flag_code
5385 are not expected. */
5386 gas_assert (ireg && flag_code == CODE_64BIT);
5388 /* Watch out for RegIP, RegIZ. These are expected to appear only with
5389 base/index addressing modes. Although creating inaccurate data
5390 dependencies, using a dummy value (lets say volatile register rsi) will
5391 not hurt SCFI. TBD_GINSN_GEN_NOT_SCFI. */
5392 if (ireg->reg_num == RegIP || ireg->reg_num == RegIZ)
5393 return GINSN_DW2_REGNUM_RSI_DUMMY;
5395 dwarf_reg = ireg->dw2_regnum[flag_code >> 1];
5397 if (dwarf_reg == Dw2Inval)
5399 if (ireg <= &i386_regtab[3])
5400 /* For al, cl, dl, bl, bump over to axl, cxl, dxl, bxl respectively by
5403 else if (ireg <= &i386_regtab[7])
5404 /* For ah, ch, dh, bh, bump over to axl, cxl, dxl, bxl respectively by
5409 /* The code relies on the relative ordering of the reg entries in
5410 i386_regtab. There are 32 register entries between axl-r31b,
5411 ax-r31w etc. The assertions here ensures the code does not
5412 recurse indefinitely. */
5413 gas_assert ((temp - &i386_regtab[0]) >= 0);
5414 idx = temp - &i386_regtab[0];
5415 gas_assert (idx + 32 < i386_regtab_size - 1);
5420 dwarf_reg = ginsn_dw2_regnum (temp);
5423 /* Sanity check - failure may indicate state corruption, bad ginsn or
5424 perhaps the i386-reg table and the current function got out of sync. */
5425 gas_assert (dwarf_reg >= 0);
5427 return (unsigned int) dwarf_reg;
5431 x86_ginsn_addsub_reg_mem (const symbolS *insn_end_sym)
5433 unsigned int dw2_regnum;
5434 unsigned int src1_dw2_regnum;
5435 ginsnS *ginsn = NULL;
5436 ginsnS * (*ginsn_func) (const symbolS *, bool,
5437 enum ginsn_src_type, unsigned int, offsetT,
5438 enum ginsn_src_type, unsigned int, offsetT,
5439 enum ginsn_dst_type, unsigned int, offsetT);
5440 uint16_t opcode = i.tm.base_opcode;
5442 gas_assert (i.tm.opcode_space == SPACE_BASE
5443 && (opcode == 0x1 || opcode == 0x29));
5444 ginsn_func = (opcode == 0x1) ? ginsn_new_add : ginsn_new_sub;
5446 /* op %reg, symbol or even other cases where destination involves indirect
5447 access are unnecessary for SCFI correctness. TBD_GINSN_GEN_NOT_SCFI. */
5451 /* op reg, reg/mem. */
5452 src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
5453 /* Of interest only when second opnd is not memory. */
5454 if (i.reg_operands == 2)
5456 dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5457 ginsn = ginsn_func (insn_end_sym, true,
5458 GINSN_SRC_REG, src1_dw2_regnum, 0,
5459 GINSN_SRC_REG, dw2_regnum, 0,
5460 GINSN_DST_REG, dw2_regnum, 0);
5461 ginsn_set_where (ginsn);
5468 x86_ginsn_addsub_mem_reg (const symbolS *insn_end_sym)
5470 unsigned int dw2_regnum;
5471 unsigned int src1_dw2_regnum;
5472 const reg_entry *mem_reg;
5474 ginsnS *ginsn = NULL;
5475 ginsnS * (*ginsn_func) (const symbolS *, bool,
5476 enum ginsn_src_type, unsigned int, offsetT,
5477 enum ginsn_src_type, unsigned int, offsetT,
5478 enum ginsn_dst_type, unsigned int, offsetT);
5479 uint16_t opcode = i.tm.base_opcode;
5481 gas_assert (i.tm.opcode_space == SPACE_BASE
5482 && (opcode == 0x3 || opcode == 0x2b));
5483 ginsn_func = (opcode == 0x3) ? ginsn_new_add : ginsn_new_sub;
5485 /* op symbol, %reg. */
5486 if (i.mem_operands && !i.base_reg && !i.index_reg)
5489 /* op reg/mem, %reg. */
5490 dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5492 if (i.reg_operands == 2)
5494 src1_dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
5495 ginsn = ginsn_func (insn_end_sym, true,
5496 GINSN_SRC_REG, src1_dw2_regnum, 0,
5497 GINSN_SRC_REG, dw2_regnum, 0,
5498 GINSN_DST_REG, dw2_regnum, 0);
5499 ginsn_set_where (ginsn);
5501 else if (i.mem_operands)
5503 mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
5504 src1_dw2_regnum = ginsn_dw2_regnum (mem_reg);
5505 if (i.disp_operands == 1)
5506 gdisp = i.op[0].disps->X_add_number;
5507 ginsn = ginsn_func (insn_end_sym, true,
5508 GINSN_SRC_INDIRECT, src1_dw2_regnum, gdisp,
5509 GINSN_SRC_REG, dw2_regnum, 0,
5510 GINSN_DST_REG, dw2_regnum, 0);
5511 ginsn_set_where (ginsn);
5518 x86_ginsn_alu_imm (const symbolS *insn_end_sym)
5521 unsigned int dw2_regnum;
5522 ginsnS *ginsn = NULL;
5523 enum ginsn_src_type src_type = GINSN_SRC_REG;
5524 enum ginsn_dst_type dst_type = GINSN_DST_REG;
5526 ginsnS * (*ginsn_func) (const symbolS *, bool,
5527 enum ginsn_src_type, unsigned int, offsetT,
5528 enum ginsn_src_type, unsigned int, offsetT,
5529 enum ginsn_dst_type, unsigned int, offsetT);
5531 /* FIXME - create ginsn where dest is REG_SP / REG_FP only ? */
5532 /* Map for insn.tm.extension_opcode
5538 /* add/sub/and imm, %reg only at this time for SCFI.
5539 Although all three ('and', 'or' , 'xor') make the destination reg
5540 untraceable, 'and' op is handled but not 'or' / 'xor' because we will look
5541 into supporting the DRAP pattern at some point. Other opcodes ('adc',
5542 'sbb' and 'cmp') are not generated here either. The ginsn representation
5543 does not have support for the latter three opcodes; GINSN_TYPE_OTHER may
5544 be added for these after x86_ginsn_unhandled () invocation if the
5545 destination register is REG_SP or REG_FP. */
5546 if (i.tm.extension_opcode == 5)
5547 ginsn_func = ginsn_new_sub;
5548 else if (i.tm.extension_opcode == 4)
5549 ginsn_func = ginsn_new_and;
5550 else if (i.tm.extension_opcode == 0)
5551 ginsn_func = ginsn_new_add;
5555 /* TBD_GINSN_REPRESENTATION_LIMIT: There is no representation for when a
5556 symbol is used as an operand, like so:
5557 addq $simd_cmp_op+8, %rdx
5558 Skip generating any ginsn for this. */
5559 if (i.imm_operands == 1
5560 && i.op[0].imms->X_op != O_constant)
5565 These are not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */
5566 if (i.mem_operands == 1)
5569 gas_assert (i.imm_operands == 1);
5570 src_imm = i.op[0].imms->X_add_number;
5571 /* The second operand may be a register or indirect access. For SCFI, only
5572 the case when the second opnd is a register is interesting. Revisit this
5573 if generating ginsns for a different gen mode TBD_GINSN_GEN_NOT_SCFI. */
5574 if (i.reg_operands == 1)
5576 dw2_regnum = ginsn_dw2_regnum (i.op[1].regs);
5577 /* For ginsn, keep the imm as second src operand. */
5578 ginsn = ginsn_func (insn_end_sym, true,
5579 src_type, dw2_regnum, 0,
5580 GINSN_SRC_IMM, 0, src_imm,
5581 dst_type, dw2_regnum, 0);
5583 ginsn_set_where (ginsn);
5589 /* Create ginsn(s) for MOV operations.
5591 The generated ginsns corresponding to mov with indirect access to memory
5592 (src or dest) suffer with loss of information: when both index and base
5593 registers are at play, only base register gets conveyed in ginsn. Note
5594 this TBD_GINSN_GEN_NOT_SCFI. */
5597 x86_ginsn_move (const symbolS *insn_end_sym)
5599 ginsnS *ginsn = NULL;
5600 unsigned int dst_reg;
5601 unsigned int src_reg;
5602 offsetT src_disp = 0;
5603 offsetT dst_disp = 0;
5604 const reg_entry *dst = NULL;
5605 const reg_entry *src = NULL;
5606 uint16_t opcode = i.tm.base_opcode;
5607 enum ginsn_src_type src_type = GINSN_SRC_REG;
5608 enum ginsn_dst_type dst_type = GINSN_DST_REG;
5610 /* mov %reg, symbol or mov symbol, %reg.
5611 Not of interest for SCFI. Also, TBD_GINSN_GEN_NOT_SCFI. */
5612 if (i.mem_operands == 1 && !i.base_reg && !i.index_reg)
5615 gas_assert (i.tm.opcode_space == SPACE_BASE);
5616 if (opcode == 0x8b || opcode == 0x8a)
5618 /* mov disp(%reg), %reg. */
5621 src = (i.base_reg) ? i.base_reg : i.index_reg;
5622 if (i.disp_operands == 1)
5623 src_disp = i.op[0].disps->X_add_number;
5624 src_type = GINSN_SRC_INDIRECT;
5631 else if (opcode == 0x89 || opcode == 0x88)
5633 /* mov %reg, disp(%reg). */
5637 dst = (i.base_reg) ? i.base_reg : i.index_reg;
5638 if (i.disp_operands == 1)
5639 dst_disp = i.op[1].disps->X_add_number;
5640 dst_type = GINSN_DST_INDIRECT;
5646 src_reg = ginsn_dw2_regnum (src);
5647 dst_reg = ginsn_dw2_regnum (dst);
5649 ginsn = ginsn_new_mov (insn_end_sym, true,
5650 src_type, src_reg, src_disp,
5651 dst_type, dst_reg, dst_disp);
5652 ginsn_set_where (ginsn);
5657 /* Generate appropriate ginsn for lea.
5658 Sub-cases marked with TBD_GINSN_INFO_LOSS indicate some loss of information
5659 in the ginsn. But these are fine for now for GINSN_GEN_SCFI generation
5663 x86_ginsn_lea (const symbolS *insn_end_sym)
5665 offsetT src_disp = 0;
5666 ginsnS *ginsn = NULL;
5667 unsigned int base_reg;
5668 unsigned int index_reg;
5669 offsetT index_scale;
5670 unsigned int dst_reg;
5672 if (!i.index_reg && !i.base_reg)
5674 /* lea symbol, %rN. */
5675 dst_reg = ginsn_dw2_regnum (i.op[1].regs);
5676 /* TBD_GINSN_INFO_LOSS - Skip encoding information about the symbol. */
5677 ginsn = ginsn_new_mov (insn_end_sym, false,
5678 GINSN_SRC_IMM, 0xf /* arbitrary const. */, 0,
5679 GINSN_DST_REG, dst_reg, 0);
5681 else if (i.base_reg && !i.index_reg)
5683 /* lea -0x2(%base),%dst. */
5684 base_reg = ginsn_dw2_regnum (i.base_reg);
5685 dst_reg = ginsn_dw2_regnum (i.op[1].regs);
5687 if (i.disp_operands)
5688 src_disp = i.op[0].disps->X_add_number;
5691 /* Generate an ADD ginsn. */
5692 ginsn = ginsn_new_add (insn_end_sym, true,
5693 GINSN_SRC_REG, base_reg, 0,
5694 GINSN_SRC_IMM, 0, src_disp,
5695 GINSN_DST_REG, dst_reg, 0);
5697 /* Generate a MOV ginsn. */
5698 ginsn = ginsn_new_mov (insn_end_sym, true,
5699 GINSN_SRC_REG, base_reg, 0,
5700 GINSN_DST_REG, dst_reg, 0);
5702 else if (!i.base_reg && i.index_reg)
5704 /* lea (,%index,imm), %dst. */
5705 /* TBD_GINSN_INFO_LOSS - There is no explicit ginsn multiply operation,
5706 instead use GINSN_TYPE_OTHER. Also, note that info about displacement
5707 is not carried forward either. But this is fine because
5708 GINSN_TYPE_OTHER will cause SCFI pass to bail out any which way if
5709 dest reg is interesting. */
5710 index_scale = i.log2_scale_factor;
5711 index_reg = ginsn_dw2_regnum (i.index_reg);
5712 dst_reg = ginsn_dw2_regnum (i.op[1].regs);
5713 ginsn = ginsn_new_other (insn_end_sym, true,
5714 GINSN_SRC_REG, index_reg,
5715 GINSN_SRC_IMM, index_scale,
5716 GINSN_DST_REG, dst_reg);
5717 /* FIXME - It seems to make sense to represent a scale factor of 1
5718 correctly here (i.e. not as "other", but rather similar to the
5719 base-without- index case above)? */
5723 /* lea disp(%base,%index,imm) %dst. */
5724 /* TBD_GINSN_INFO_LOSS - Skip adding information about the disp and imm
5726 base_reg = ginsn_dw2_regnum (i.base_reg);
5727 index_reg = ginsn_dw2_regnum (i.index_reg);
5728 dst_reg = ginsn_dw2_regnum (i.op[1].regs);
5729 /* Generate an GINSN_TYPE_OTHER ginsn. */
5730 ginsn = ginsn_new_other (insn_end_sym, true,
5731 GINSN_SRC_REG, base_reg,
5732 GINSN_SRC_REG, index_reg,
5733 GINSN_DST_REG, dst_reg);
5736 ginsn_set_where (ginsn);
5742 x86_ginsn_jump (const symbolS *insn_end_sym, bool cond_p)
5744 ginsnS *ginsn = NULL;
5745 const symbolS *src_symbol;
5746 ginsnS * (*ginsn_func) (const symbolS *sym, bool real_p,
5747 enum ginsn_src_type src_type, unsigned int src_reg,
5748 const symbolS *src_ginsn_sym);
5750 gas_assert (i.disp_operands == 1);
5752 ginsn_func = cond_p ? ginsn_new_jump_cond : ginsn_new_jump;
5753 if (i.op[0].disps->X_op == O_symbol && !i.op[0].disps->X_add_number)
5755 src_symbol = i.op[0].disps->X_add_symbol;
5756 ginsn = ginsn_func (insn_end_sym, true,
5757 GINSN_SRC_SYMBOL, 0, src_symbol);
5759 ginsn_set_where (ginsn);
5763 /* A non-zero addend in jump/JCC target makes control-flow tracking
5764 difficult. Skip SCFI for now. */
5765 as_bad (_("SCFI: `%s' insn with non-zero addend to sym not supported"),
5766 cond_p ? "JCC" : "jmp");
5774 x86_ginsn_enter (const symbolS *insn_end_sym)
5776 ginsnS *ginsn = NULL;
5777 ginsnS *ginsn_next = NULL;
5778 ginsnS *ginsn_last = NULL;
5779 /* In 64-bit mode, the default stack update size is 8 bytes. */
5780 int stack_opnd_size = 8;
5782 gas_assert (i.imm_operands == 2);
5784 /* For non-zero size operands, bail out as untraceable for SCFI. */
5785 if (i.op[0].imms->X_op != O_constant || i.op[0].imms->X_add_symbol != 0
5786 || i.op[1].imms->X_op != O_constant || i.op[1].imms->X_add_symbol != 0)
5788 as_bad ("SCFI: enter insn with non-zero operand not supported");
5792 /* Check if this is a 16-bit op. */
5793 if (ginsn_opsize_prefix_p ())
5794 stack_opnd_size = 2;
5796 /* If the nesting level is 0, the processor pushes the frame pointer from
5797 the BP/EBP/RBP register onto the stack, copies the current stack
5798 pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and
5799 loads the SP/ESP/RSP register with the current stack-pointer value
5800 minus the value in the size operand. */
5801 ginsn = ginsn_new_sub (insn_end_sym, false,
5802 GINSN_SRC_REG, REG_SP, 0,
5803 GINSN_SRC_IMM, 0, stack_opnd_size,
5804 GINSN_DST_REG, REG_SP, 0);
5805 ginsn_set_where (ginsn);
5806 ginsn_next = ginsn_new_store (insn_end_sym, false,
5807 GINSN_SRC_REG, REG_FP,
5808 GINSN_DST_INDIRECT, REG_SP, 0);
5809 ginsn_set_where (ginsn_next);
5810 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
5811 ginsn_last = ginsn_new_mov (insn_end_sym, false,
5812 GINSN_SRC_REG, REG_SP, 0,
5813 GINSN_DST_REG, REG_FP, 0);
5814 ginsn_set_where (ginsn_last);
5815 gas_assert (!ginsn_link_next (ginsn_next, ginsn_last));
5821 x86_ginsn_leave (const symbolS *insn_end_sym)
5823 ginsnS *ginsn = NULL;
5824 ginsnS *ginsn_next = NULL;
5825 ginsnS *ginsn_last = NULL;
5826 /* In 64-bit mode, the default stack update size is 8 bytes. */
5827 int stack_opnd_size = 8;
5829 /* Check if this is a 16-bit op. */
5830 if (ginsn_opsize_prefix_p ())
5831 stack_opnd_size = 2;
5833 /* The 'leave' instruction copies the contents of the RBP register
5834 into the RSP register to release all stack space allocated to the
5836 ginsn = ginsn_new_mov (insn_end_sym, false,
5837 GINSN_SRC_REG, REG_FP, 0,
5838 GINSN_DST_REG, REG_SP, 0);
5839 ginsn_set_where (ginsn);
5840 /* Then it restores the old value of the RBP register from the stack. */
5841 ginsn_next = ginsn_new_load (insn_end_sym, false,
5842 GINSN_SRC_INDIRECT, REG_SP, 0,
5843 GINSN_DST_REG, REG_FP);
5844 ginsn_set_where (ginsn_next);
5845 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
5846 ginsn_last = ginsn_new_add (insn_end_sym, false,
5847 GINSN_SRC_REG, REG_SP, 0,
5848 GINSN_SRC_IMM, 0, stack_opnd_size,
5849 GINSN_DST_REG, REG_SP, 0);
5850 ginsn_set_where (ginsn_next);
5851 gas_assert (!ginsn_link_next (ginsn_next, ginsn_last));
5856 /* Check if an instruction is whitelisted.
5858 Some instructions may appear with REG_SP or REG_FP as destination, because
5859 which they are deemed 'interesting' for SCFI. Whitelist them here if they
5860 do not affect SCFI correctness. */
5863 x86_ginsn_safe_to_skip_p (void)
5865 bool skip_p = false;
5866 uint16_t opcode = i.tm.base_opcode;
5873 if (i.tm.opcode_space != SPACE_BASE)
5875 /* cmp imm, reg/rem. */
5876 if (i.tm.extension_opcode == 7)
5884 if (i.tm.opcode_space != SPACE_BASE)
5886 /* cmp imm/reg/mem, reg/rem. */
5894 /* test imm/reg/mem, reg/mem. */
5895 if (i.tm.opcode_space != SPACE_BASE)
5907 #define X86_GINSN_UNHANDLED_NONE 0
5908 #define X86_GINSN_UNHANDLED_DEST_REG 1
5909 #define X86_GINSN_UNHANDLED_CFG 2
5910 #define X86_GINSN_UNHANDLED_STACKOP 3
5911 #define X86_GINSN_UNHANDLED_UNEXPECTED 4
5913 /* Check the input insn for its impact on the correctness of the synthesized
5914 CFI. Returns an error code to the caller. */
5917 x86_ginsn_unhandled (void)
5919 int err = X86_GINSN_UNHANDLED_NONE;
5920 const reg_entry *reg_op;
5921 unsigned int dw2_regnum;
5923 /* Keep an eye out for instructions affecting control flow. */
5924 if (i.tm.opcode_modifier.jump)
5925 err = X86_GINSN_UNHANDLED_CFG;
5926 /* Also, for any instructions involving an implicit update to the stack
5928 else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_STACK_OP)
5929 err = X86_GINSN_UNHANDLED_STACKOP;
5930 /* Finally, also check if the missed instructions are affecting REG_SP or
5931 REG_FP. The destination operand is the last at all stages of assembly
5932 (due to following AT&T syntax layout in the internal representation). In
5933 case of Intel syntax input, this still remains true as swap_operands ()
5935 PS: These checks do not involve index / base reg, as indirect memory
5936 accesses via REG_SP or REG_FP do not affect SCFI correctness.
5937 (Also note these instructions are candidates for other ginsn generation
5938 modes in future. TBD_GINSN_GEN_NOT_SCFI.) */
5939 else if (i.operands && i.reg_operands
5940 && !(i.flags[i.operands - 1] & Operand_Mem))
5942 reg_op = i.op[i.operands - 1].regs;
5945 dw2_regnum = ginsn_dw2_regnum (reg_op);
5946 if (dw2_regnum == REG_SP || dw2_regnum == REG_FP)
5947 err = X86_GINSN_UNHANDLED_DEST_REG;
5950 /* Something unexpected. Indicate to caller. */
5951 err = X86_GINSN_UNHANDLED_UNEXPECTED;
5957 /* Generate one or more generic GAS instructions, a.k.a, ginsns for the current
5958 machine instruction.
5960 Returns the head of linked list of ginsn(s) added, if success; Returns NULL
5963 The input ginsn_gen_mode GMODE determines the set of minimal necessary
5964 ginsns necessary for correctness of any passes applicable for that mode.
5965 For supporting the GINSN_GEN_SCFI generation mode, following is the list of
5966 machine instructions that must be translated into the corresponding ginsns
5967 to ensure correctness of SCFI:
5968 - All instructions affecting the two registers that could potentially
5969 be used as the base register for CFA tracking. For SCFI, the base
5970 register for CFA tracking is limited to REG_SP and REG_FP only for
5972 - All change of flow instructions: conditional and unconditional branches,
5973 call and return from functions.
5974 - All instructions that can potentially be a register save / restore
5976 - All instructions that perform stack manipulation implicitly: the CALL,
5977 RET, PUSH, POP, ENTER, and LEAVE instructions.
5979 The function currently supports GINSN_GEN_SCFI ginsn generation mode only.
5980 To support other generation modes will require work on this target-specific
5981 process of creation of ginsns:
5982 - Some of such places are tagged with TBD_GINSN_GEN_NOT_SCFI to serve as
5983 possible starting points.
5984 - Also note that ginsn representation may need enhancements. Specifically,
5985 note some TBD_GINSN_INFO_LOSS and TBD_GINSN_REPRESENTATION_LIMIT markers.
5989 x86_ginsn_new (const symbolS *insn_end_sym, enum ginsn_gen_mode gmode)
5993 unsigned int dw2_regnum;
5994 const reg_entry *mem_reg;
5995 ginsnS *ginsn = NULL;
5996 ginsnS *ginsn_next = NULL;
5997 /* In 64-bit mode, the default stack update size is 8 bytes. */
5998 int stack_opnd_size = 8;
6000 /* Currently supports generation of selected ginsns, sufficient for
6001 the use-case of SCFI only. */
6002 if (gmode != GINSN_GEN_SCFI)
6005 opcode = i.tm.base_opcode;
6007 /* Until it is clear how to handle APX NDD and other new opcodes, disallow
6009 if (is_apx_rex2_encoding ()
6010 || (i.tm.opcode_modifier.evex && is_apx_evex_encoding ()))
6012 as_bad (_("SCFI: unsupported APX op %#x may cause incorrect CFI"),
6019 case 0x1: /* add reg, reg/mem. */
6020 case 0x29: /* sub reg, reg/mem. */
6021 if (i.tm.opcode_space != SPACE_BASE)
6023 ginsn = x86_ginsn_addsub_reg_mem (insn_end_sym);
6026 case 0x3: /* add reg/mem, reg. */
6027 case 0x2b: /* sub reg/mem, reg. */
6028 if (i.tm.opcode_space != SPACE_BASE)
6030 ginsn = x86_ginsn_addsub_mem_reg (insn_end_sym);
6033 case 0xa0: /* push fs. */
6034 case 0xa8: /* push gs. */
6035 /* push fs / push gs have opcode_space == SPACE_0F. */
6036 if (i.tm.opcode_space != SPACE_0F)
6038 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6039 /* Check if operation size is 16-bit. */
6040 if (ginsn_opsize_prefix_p ())
6041 stack_opnd_size = 2;
6042 ginsn = ginsn_new_sub (insn_end_sym, false,
6043 GINSN_SRC_REG, REG_SP, 0,
6044 GINSN_SRC_IMM, 0, stack_opnd_size,
6045 GINSN_DST_REG, REG_SP, 0);
6046 ginsn_set_where (ginsn);
6047 ginsn_next = ginsn_new_store (insn_end_sym, false,
6048 GINSN_SRC_REG, dw2_regnum,
6049 GINSN_DST_INDIRECT, REG_SP, 0);
6050 ginsn_set_where (ginsn_next);
6051 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6054 case 0xa1: /* pop fs. */
6055 case 0xa9: /* pop gs. */
6056 /* pop fs / pop gs have opcode_space == SPACE_0F. */
6057 if (i.tm.opcode_space != SPACE_0F)
6059 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6060 /* Check if operation size is 16-bit. */
6061 if (ginsn_opsize_prefix_p ())
6062 stack_opnd_size = 2;
6063 ginsn = ginsn_new_load (insn_end_sym, false,
6064 GINSN_SRC_INDIRECT, REG_SP, 0,
6065 GINSN_DST_REG, dw2_regnum);
6066 ginsn_set_where (ginsn);
6067 ginsn_next = ginsn_new_add (insn_end_sym, false,
6068 GINSN_SRC_REG, REG_SP, 0,
6069 GINSN_SRC_IMM, 0, stack_opnd_size,
6070 GINSN_DST_REG, REG_SP, 0);
6071 ginsn_set_where (ginsn_next);
6072 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6076 if (i.tm.opcode_space != SPACE_BASE)
6079 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6080 /* Check if operation size is 16-bit. */
6081 if (ginsn_opsize_prefix_p ())
6082 stack_opnd_size = 2;
6083 ginsn = ginsn_new_sub (insn_end_sym, false,
6084 GINSN_SRC_REG, REG_SP, 0,
6085 GINSN_SRC_IMM, 0, stack_opnd_size,
6086 GINSN_DST_REG, REG_SP, 0);
6087 ginsn_set_where (ginsn);
6088 ginsn_next = ginsn_new_store (insn_end_sym, false,
6089 GINSN_SRC_REG, dw2_regnum,
6090 GINSN_DST_INDIRECT, REG_SP, 0);
6091 ginsn_set_where (ginsn_next);
6092 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6096 if (i.tm.opcode_space != SPACE_BASE)
6099 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6100 ginsn = ginsn_new_load (insn_end_sym, false,
6101 GINSN_SRC_INDIRECT, REG_SP, 0,
6102 GINSN_DST_REG, dw2_regnum);
6103 ginsn_set_where (ginsn);
6104 /* Check if operation size is 16-bit. */
6105 if (ginsn_opsize_prefix_p ())
6106 stack_opnd_size = 2;
6107 ginsn_next = ginsn_new_add (insn_end_sym, false,
6108 GINSN_SRC_REG, REG_SP, 0,
6109 GINSN_SRC_IMM, 0, stack_opnd_size,
6110 GINSN_DST_REG, REG_SP, 0);
6111 ginsn_set_where (ginsn_next);
6112 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6115 case 0x6a: /* push imm8. */
6116 case 0x68: /* push imm16/imm32. */
6117 if (i.tm.opcode_space != SPACE_BASE)
6119 /* Check if operation size is 16-bit. */
6120 if (ginsn_opsize_prefix_p ())
6121 stack_opnd_size = 2;
6122 /* Skip getting the value of imm from machine instruction
6123 because this is not important for SCFI. */
6124 ginsn = ginsn_new_sub (insn_end_sym, false,
6125 GINSN_SRC_REG, REG_SP, 0,
6126 GINSN_SRC_IMM, 0, stack_opnd_size,
6127 GINSN_DST_REG, REG_SP, 0);
6128 ginsn_set_where (ginsn);
6129 ginsn_next = ginsn_new_store (insn_end_sym, false,
6131 GINSN_DST_INDIRECT, REG_SP, 0);
6132 ginsn_set_where (ginsn_next);
6133 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6136 /* PS: Opcodes 0x80 ... 0x8f with opcode_space SPACE_0F are present
6137 only after relaxation. They do not need to be handled for ginsn
6140 if (i.tm.opcode_space != SPACE_BASE)
6142 ginsn = x86_ginsn_jump (insn_end_sym, true);
6148 if (i.tm.opcode_space != SPACE_BASE)
6150 ginsn = x86_ginsn_alu_imm (insn_end_sym);
6153 case 0x8a: /* mov r/m8, r8. */
6154 case 0x8b: /* mov r/m(16/32/64), r(16/32/64). */
6155 case 0x88: /* mov r8, r/m8. */
6156 case 0x89: /* mov r(16/32/64), r/m(16/32/64). */
6157 if (i.tm.opcode_space != SPACE_BASE)
6159 ginsn = x86_ginsn_move (insn_end_sym);
6163 if (i.tm.opcode_space != SPACE_BASE)
6165 /* lea disp(%base,%index,imm) %dst. */
6166 ginsn = x86_ginsn_lea (insn_end_sym);
6170 if (i.tm.opcode_space != SPACE_BASE)
6172 /* pop to reg/mem. */
6175 mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
6176 /* Use dummy register if no base or index. Unlike other opcodes,
6177 ginsns must be generated as this affect stack pointer. */
6178 dw2_regnum = (mem_reg
6179 ? ginsn_dw2_regnum (mem_reg)
6180 : GINSN_DW2_REGNUM_RSI_DUMMY);
6183 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6184 ginsn = ginsn_new_load (insn_end_sym, false,
6185 GINSN_SRC_INDIRECT, REG_SP, 0,
6186 GINSN_DST_INDIRECT, dw2_regnum);
6187 ginsn_set_where (ginsn);
6188 /* Check if operation size is 16-bit. */
6189 if (ginsn_opsize_prefix_p ())
6190 stack_opnd_size = 2;
6191 ginsn_next = ginsn_new_add (insn_end_sym, false,
6192 GINSN_SRC_REG, REG_SP, 0,
6193 GINSN_SRC_IMM, 0, stack_opnd_size,
6194 GINSN_DST_REG, REG_SP, 0);
6195 ginsn_set_where (ginsn_next);
6196 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6200 if (i.tm.opcode_space != SPACE_BASE)
6202 /* pushf / pushfq. */
6203 /* Check if operation size is 16-bit. */
6204 if (ginsn_opsize_prefix_p ())
6205 stack_opnd_size = 2;
6206 ginsn = ginsn_new_sub (insn_end_sym, false,
6207 GINSN_SRC_REG, REG_SP, 0,
6208 GINSN_SRC_IMM, 0, stack_opnd_size,
6209 GINSN_DST_REG, REG_SP, 0);
6210 ginsn_set_where (ginsn);
6211 /* FIXME - hardcode the actual DWARF reg number value. As for SCFI
6212 correctness, although this behaves simply a placeholder value; its
6213 just clearer if the value is correct. */
6214 dw2_regnum = GINSN_DW2_REGNUM_EFLAGS;
6215 ginsn_next = ginsn_new_store (insn_end_sym, false,
6216 GINSN_SRC_REG, dw2_regnum,
6217 GINSN_DST_INDIRECT, REG_SP, 0);
6218 ginsn_set_where (ginsn_next);
6219 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6223 if (i.tm.opcode_space != SPACE_BASE)
6226 /* Check if operation size is 16-bit. */
6227 if (ginsn_opsize_prefix_p ())
6228 stack_opnd_size = 2;
6229 /* FIXME - hardcode the actual DWARF reg number value. As for SCFI
6230 correctness, although this behaves simply a placeholder value; its
6231 just clearer if the value is correct. */
6232 dw2_regnum = GINSN_DW2_REGNUM_EFLAGS;
6233 ginsn = ginsn_new_load (insn_end_sym, false,
6234 GINSN_SRC_INDIRECT, REG_SP, 0,
6235 GINSN_DST_REG, dw2_regnum);
6236 ginsn_set_where (ginsn);
6237 ginsn_next = ginsn_new_add (insn_end_sym, false,
6238 GINSN_SRC_REG, REG_SP, 0,
6239 GINSN_SRC_IMM, 0, stack_opnd_size,
6240 GINSN_DST_REG, REG_SP, 0);
6241 ginsn_set_where (ginsn_next);
6242 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6246 if (i.tm.opcode_space != SPACE_BASE)
6248 /* push from reg/mem. */
6249 if (i.tm.extension_opcode == 6)
6251 /* Check if operation size is 16-bit. */
6252 if (ginsn_opsize_prefix_p ())
6253 stack_opnd_size = 2;
6254 ginsn = ginsn_new_sub (insn_end_sym, false,
6255 GINSN_SRC_REG, REG_SP, 0,
6256 GINSN_SRC_IMM, 0, stack_opnd_size,
6257 GINSN_DST_REG, REG_SP, 0);
6258 ginsn_set_where (ginsn);
6261 mem_reg = (i.base_reg) ? i.base_reg : i.index_reg;
6262 /* Use dummy register if no base or index. Unlike other opcodes,
6263 ginsns must be generated as this affect stack pointer. */
6264 dw2_regnum = (mem_reg
6265 ? ginsn_dw2_regnum (mem_reg)
6266 : GINSN_DW2_REGNUM_RSI_DUMMY);
6269 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6270 ginsn_next = ginsn_new_store (insn_end_sym, false,
6271 GINSN_SRC_INDIRECT, dw2_regnum,
6272 GINSN_DST_INDIRECT, REG_SP, 0);
6273 ginsn_set_where (ginsn_next);
6274 gas_assert (!ginsn_link_next (ginsn, ginsn_next));
6276 else if (i.tm.extension_opcode == 4)
6278 /* jmp r/m. E.g., notrack jmp *%rax. */
6281 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6282 ginsn = ginsn_new_jump (insn_end_sym, true,
6283 GINSN_SRC_REG, dw2_regnum, NULL);
6284 ginsn_set_where (ginsn);
6286 else if (i.mem_operands && i.index_reg)
6288 /* jmp *0x0(,%rax,8). */
6289 dw2_regnum = ginsn_dw2_regnum (i.index_reg);
6290 ginsn = ginsn_new_jump (insn_end_sym, true,
6291 GINSN_SRC_REG, dw2_regnum, NULL);
6292 ginsn_set_where (ginsn);
6294 else if (i.mem_operands && i.base_reg)
6296 dw2_regnum = ginsn_dw2_regnum (i.base_reg);
6297 ginsn = ginsn_new_jump (insn_end_sym, true,
6298 GINSN_SRC_REG, dw2_regnum, NULL);
6299 ginsn_set_where (ginsn);
6302 else if (i.tm.extension_opcode == 2)
6304 /* 0xFF /2 (call). */
6307 dw2_regnum = ginsn_dw2_regnum (i.op[0].regs);
6308 ginsn = ginsn_new_call (insn_end_sym, true,
6309 GINSN_SRC_REG, dw2_regnum, NULL);
6310 ginsn_set_where (ginsn);
6312 else if (i.mem_operands && i.base_reg)
6314 dw2_regnum = ginsn_dw2_regnum (i.base_reg);
6315 ginsn = ginsn_new_call (insn_end_sym, true,
6316 GINSN_SRC_REG, dw2_regnum, NULL);
6317 ginsn_set_where (ginsn);
6322 case 0xc2: /* ret imm16. */
6323 case 0xc3: /* ret. */
6324 if (i.tm.opcode_space != SPACE_BASE)
6327 ginsn = ginsn_new_return (insn_end_sym, true);
6328 ginsn_set_where (ginsn);
6332 if (i.tm.opcode_space != SPACE_BASE)
6335 ginsn = x86_ginsn_enter (insn_end_sym);
6339 if (i.tm.opcode_space != SPACE_BASE)
6342 ginsn = x86_ginsn_leave (insn_end_sym);
6345 case 0xe0 ... 0xe2: /* loop / loope / loopne. */
6346 case 0xe3: /* jecxz / jrcxz. */
6347 if (i.tm.opcode_space != SPACE_BASE)
6349 ginsn = x86_ginsn_jump (insn_end_sym, true);
6350 ginsn_set_where (ginsn);
6354 if (i.tm.opcode_space != SPACE_BASE)
6356 /* PS: SCFI machinery does not care about which func is being
6357 called. OK to skip that info. */
6358 ginsn = ginsn_new_call (insn_end_sym, true,
6359 GINSN_SRC_SYMBOL, 0, NULL);
6360 ginsn_set_where (ginsn);
6363 /* PS: opcode 0xe9 appears only after relaxation. Skip here. */
6365 /* If opcode_space != SPACE_BASE, this is not a jmp insn. Skip it
6366 for GINSN_GEN_SCFI. */
6367 if (i.tm.opcode_space != SPACE_BASE)
6369 /* Unconditional jmp. */
6370 ginsn = x86_ginsn_jump (insn_end_sym, false);
6371 ginsn_set_where (ginsn);
6375 /* TBD_GINSN_GEN_NOT_SCFI: Skip all other opcodes uninteresting for
6376 GINSN_GEN_SCFI mode. */
6380 if (!ginsn && !x86_ginsn_safe_to_skip_p ())
6382 /* For all unhandled insns that are not whitelisted, check that they do
6383 not impact SCFI correctness. */
6384 err = x86_ginsn_unhandled ();
6387 case X86_GINSN_UNHANDLED_NONE:
6389 case X86_GINSN_UNHANDLED_DEST_REG:
6390 /* Not all writes to REG_FP are harmful in context of SCFI. Simply
6391 generate a GINSN_TYPE_OTHER with destination set to the
6392 appropriate register. The SCFI machinery will bail out if this
6393 ginsn affects SCFI correctness. */
6394 dw2_regnum = ginsn_dw2_regnum (i.op[i.operands - 1].regs);
6395 ginsn = ginsn_new_other (insn_end_sym, true,
6398 GINSN_DST_REG, dw2_regnum);
6399 ginsn_set_where (ginsn);
6401 case X86_GINSN_UNHANDLED_CFG:
6402 case X86_GINSN_UNHANDLED_STACKOP:
6403 as_bad (_("SCFI: unhandled op %#x may cause incorrect CFI"), opcode);
6405 case X86_GINSN_UNHANDLED_UNEXPECTED:
6406 as_bad (_("SCFI: unexpected op %#x may cause incorrect CFI"),
6420 /* This is the guts of the machine-dependent assembler. LINE points to a
6421 machine dependent instruction. This function is supposed to emit
6422 the frags/bytes it assembles to. */
6425 md_assemble (char *line)
6428 char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL;
6429 const char *end, *pass1_mnem = NULL;
6430 enum i386_error pass1_err = 0;
6431 const insn_template *t;
6432 struct last_insn *last_insn
6433 = &seg_info(now_seg)->tc_segment_info_data.last_insn;
6435 /* Initialize globals. */
6436 current_templates.end = current_templates.start = NULL;
6440 /* Suppress optimization when the last thing we saw may not have been
6441 a proper instruction (e.g. a stand-alone prefix or .byte). */
6442 if (last_insn->kind != last_insn_other)
6443 i.no_optimize = true;
6445 /* First parse an instruction mnemonic & call i386_operand for the operands.
6446 We assume that the scrubber has arranged it so that line[0] is the valid
6447 start of a (possibly prefixed) mnemonic. */
6449 end = parse_insn (line, mnemonic, false);
6452 if (pass1_mnem != NULL)
6454 if (i.error != no_error)
6456 gas_assert (current_templates.start != NULL);
6457 if (may_need_pass2 (current_templates.start) && !i.suffix)
6459 /* No point in trying a 2nd pass - it'll only find the same suffix
6461 mnem_suffix = i.suffix;
6466 t = current_templates.start;
6467 if (may_need_pass2 (t))
6469 /* Make a copy of the full line in case we need to retry. */
6470 copy = xstrdup (line);
6473 mnem_suffix = i.suffix;
6475 line = parse_operands (line, mnemonic);
6483 /* Now we've parsed the mnemonic into a set of templates, and have the
6484 operands at hand. */
6486 /* All Intel opcodes have reversed operands except for "bound", "enter",
6487 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
6488 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
6489 intersegment "jmp" and "call" instructions with 2 immediate operands so
6490 that the immediate segment precedes the offset consistently in Intel and
6494 && (t->mnem_off != MN_bound)
6495 && !startswith (mnemonic, "invlpg")
6496 && !startswith (mnemonic, "monitor")
6497 && !startswith (mnemonic, "mwait")
6498 && (t->mnem_off != MN_pvalidate)
6499 && !startswith (mnemonic, "rmp")
6500 && (t->mnem_off != MN_tpause)
6501 && (t->mnem_off != MN_umwait)
6502 && !(i.operands == 2
6503 && operand_type_check (i.types[0], imm)
6504 && operand_type_check (i.types[1], imm)))
6507 /* The order of the immediates should be reversed for 2-immediates EXTRQ
6508 and INSERTQ instructions. Also UWRMSR wants its immediate to be in the
6509 "canonical" place (first), despite it appearing last (in AT&T syntax, or
6510 because of the swapping above) in the incoming set of operands. */
6511 if ((i.imm_operands == 2
6512 && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq))
6513 || (t->mnem_off == MN_uwrmsr && i.imm_operands
6514 && i.operands > i.imm_operands))
6515 swap_2_operands (0, 1);
6519 /* For USER_MSR instructions, imm32 stands for the name of an model specific
6520 register (MSR). That's an unsigned quantity, whereas all other insns with
6521 32-bit immediate and 64-bit operand size use sign-extended
6522 immediates (imm32s). Therefore these insns are special-cased, bypassing
6523 the normal handling of immediates here. */
6524 if (is_cpu(current_templates.start, CpuUSER_MSR))
6526 for (j = 0; j < i.operands; j++)
6528 if (operand_type_check(i.types[j], imm))
6529 i.types[j] = smallest_imm_type (i.op[j].imms->X_add_number);
6536 if (i.disp_operands && !optimize_disp (t))
6539 /* Next, we find a template that matches the given insn,
6540 making sure the overlap of the given operands types is consistent
6541 with the template operand types. */
6543 if (!(t = match_template (mnem_suffix)))
6545 const char *err_msg;
6547 if (copy && !mnem_suffix)
6552 pass1_err = i.error;
6553 pass1_mnem = insn_name (current_templates.start);
6557 /* If a non-/only-64bit template (group) was found in pass 1, and if
6558 _some_ template (group) was found in pass 2, squash pass 1's
6560 if (pass1_err == unsupported_64bit)
6566 switch (pass1_mnem ? pass1_err : i.error)
6570 case operand_size_mismatch:
6571 err_msg = _("operand size mismatch");
6573 case operand_type_mismatch:
6574 err_msg = _("operand type mismatch");
6576 case register_type_mismatch:
6577 err_msg = _("register type mismatch");
6579 case number_of_operands_mismatch:
6580 err_msg = _("number of operands mismatch");
6582 case invalid_instruction_suffix:
6583 err_msg = _("invalid instruction suffix");
6586 err_msg = _("constant doesn't fit in 4 bits");
6588 case unsupported_with_intel_mnemonic:
6589 err_msg = _("unsupported with Intel mnemonic");
6591 case unsupported_syntax:
6592 err_msg = _("unsupported syntax");
6594 case unsupported_EGPR_for_addressing:
6595 err_msg = _("extended GPR cannot be used as base/index");
6598 as_bad (_("unsupported instruction `%s'"),
6599 pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6601 case unsupported_on_arch:
6602 as_bad (_("`%s' is not supported on `%s%s'"),
6603 pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6604 cpu_arch_name ? cpu_arch_name : default_arch,
6605 cpu_sub_arch_name ? cpu_sub_arch_name : "");
6607 case unsupported_64bit:
6608 if (ISLOWER (mnem_suffix))
6610 if (flag_code == CODE_64BIT)
6611 as_bad (_("`%s%c' is not supported in 64-bit mode"),
6612 pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6615 as_bad (_("`%s%c' is only supported in 64-bit mode"),
6616 pass1_mnem ? pass1_mnem : insn_name (current_templates.start),
6621 if (flag_code == CODE_64BIT)
6622 as_bad (_("`%s' is not supported in 64-bit mode"),
6623 pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6625 as_bad (_("`%s' is only supported in 64-bit mode"),
6626 pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6629 case no_vex_encoding:
6630 err_msg = _("no VEX/XOP encoding");
6632 case no_evex_encoding:
6633 err_msg = _("no EVEX encoding");
6635 case invalid_sib_address:
6636 err_msg = _("invalid SIB address");
6638 case invalid_vsib_address:
6639 err_msg = _("invalid VSIB address");
6641 case invalid_vector_register_set:
6642 err_msg = _("mask, index, and destination registers must be distinct");
6644 case invalid_tmm_register_set:
6645 err_msg = _("all tmm registers must be distinct");
6647 case invalid_dest_and_src_register_set:
6648 err_msg = _("destination and source registers must be distinct");
6650 case invalid_dest_register_set:
6651 err_msg = _("two dest registers must be distinct");
6653 case invalid_pseudo_prefix:
6654 err_msg = _("rex2 pseudo prefix cannot be used");
6656 case unsupported_vector_index_register:
6657 err_msg = _("unsupported vector index register");
6659 case unsupported_broadcast:
6660 err_msg = _("unsupported broadcast");
6662 case broadcast_needed:
6663 err_msg = _("broadcast is needed for operand of such type");
6665 case unsupported_masking:
6666 err_msg = _("unsupported masking");
6668 case mask_not_on_destination:
6669 err_msg = _("mask not on destination operand");
6671 case no_default_mask:
6672 err_msg = _("default mask isn't allowed");
6674 case unsupported_rc_sae:
6675 err_msg = _("unsupported static rounding/sae");
6677 case unsupported_vector_size:
6678 as_bad (_("vector size above %u required for `%s'"), 128u << vector_size,
6679 pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6681 case unsupported_rsp_register:
6682 err_msg = _("'rsp' register cannot be used");
6684 case internal_error:
6685 err_msg = _("internal error");
6688 as_bad (_("%s for `%s'"), err_msg,
6689 pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
6695 if (sse_check != check_none
6696 /* The opcode space check isn't strictly needed; it's there only to
6697 bypass the logic below when easily possible. */
6698 && t->opcode_space >= SPACE_0F
6699 && t->opcode_space <= SPACE_0F3A
6700 && !is_cpu (&i.tm, CpuSSE4a)
6701 && !is_any_vex_encoding (t))
6705 for (j = 0; j < t->operands; ++j)
6707 if (t->operand_types[j].bitfield.class == RegMMX)
6709 if (t->operand_types[j].bitfield.class == RegSIMD)
6713 if (j >= t->operands && simd)
6714 (sse_check == check_warning
6716 : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm));
6719 if (i.tm.opcode_modifier.fwait)
6720 if (!add_prefix (FWAIT_OPCODE))
6723 /* Check if REP prefix is OK. */
6724 if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep)
6726 as_bad (_("invalid instruction `%s' after `%s'"),
6727 insn_name (&i.tm), i.rep_prefix);
6731 /* Check for lock without a lockable instruction. Destination operand
6732 must be memory unless it is xchg (0x86). */
6733 if (i.prefix[LOCK_PREFIX])
6735 if (i.tm.opcode_modifier.prefixok < PrefixLock
6736 || i.mem_operands == 0
6737 || (i.tm.base_opcode != 0x86
6738 && !(i.flags[i.operands - 1] & Operand_Mem)))
6740 as_bad (_("expecting lockable instruction after `lock'"));
6744 /* Zap the redundant prefix from XCHG when optimizing. */
6745 if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize)
6746 i.prefix[LOCK_PREFIX] = 0;
6749 if (is_any_vex_encoding (&i.tm)
6750 || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX
6751 || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)
6753 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
6754 if (i.prefix[DATA_PREFIX])
6756 as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm));
6760 /* Don't allow e.g. KMOV in TLS code sequences. */
6761 for (j = i.imm_operands; j < i.operands; ++j)
6764 case BFD_RELOC_386_TLS_GOTIE:
6765 case BFD_RELOC_386_TLS_LE_32:
6766 case BFD_RELOC_X86_64_GOTTPOFF:
6767 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
6768 case BFD_RELOC_X86_64_TLSLD:
6769 as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm));
6776 /* Check if HLE prefix is OK. */
6777 if (i.hle_prefix && !check_hle ())
6780 /* Check BND prefix. */
6781 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
6782 as_bad (_("expecting valid branch instruction after `bnd'"));
6784 /* Check NOTRACK prefix. */
6785 if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack)
6786 as_bad (_("expecting indirect branch instruction after `notrack'"));
6788 if (is_cpu (&i.tm, CpuMPX))
6790 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
6791 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
6792 else if (flag_code != CODE_16BIT
6793 ? i.prefix[ADDR_PREFIX]
6794 : i.mem_operands && !i.prefix[ADDR_PREFIX])
6795 as_bad (_("16-bit address isn't allowed in MPX instructions"));
6798 /* Insert BND prefix. */
6799 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
6801 if (!i.prefix[BND_PREFIX])
6802 add_prefix (BND_PREFIX_OPCODE);
6803 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
6805 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
6806 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
6810 /* Check string instruction segment overrides. */
6811 if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0)
6813 gas_assert (i.mem_operands);
6814 if (!check_string ())
6816 i.disp_operands = 0;
6819 /* The memory operand of (%dx) should be only used with input/output
6820 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
6821 if (i.input_output_operand
6822 && ((i.tm.base_opcode | 0x82) != 0xee
6823 || i.tm.opcode_space != SPACE_BASE))
6825 as_bad (_("input/output port address isn't allowed with `%s'"),
6830 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
6831 optimize_encoding ();
6833 /* Past optimization there's no need to distinguish vex_encoding_evex and
6834 vex_encoding_evex512 anymore. */
6835 if (i.vec_encoding == vex_encoding_evex512)
6836 i.vec_encoding = vex_encoding_evex;
6838 if (use_unaligned_vector_move)
6839 encode_with_unaligned_vector_move ();
6841 if (!process_suffix ())
6844 /* Check if IP-relative addressing requirements can be satisfied. */
6845 if (is_cpu (&i.tm, CpuPREFETCHI)
6846 && !(i.base_reg && i.base_reg->reg_num == RegIP))
6847 as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm));
6849 /* Update operand types and check extended states. */
6850 for (j = 0; j < i.operands; j++)
6852 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
6853 switch (i.tm.operand_types[j].bitfield.class)
6858 i.xstate |= xstate_mmx;
6861 i.xstate |= xstate_mask;
6864 if (i.tm.operand_types[j].bitfield.tmmword)
6865 i.xstate |= xstate_tmm;
6866 else if (i.tm.operand_types[j].bitfield.zmmword
6867 && !i.tm.opcode_modifier.vex
6868 && vector_size >= VSZ512)
6869 i.xstate |= xstate_zmm;
6870 else if (i.tm.operand_types[j].bitfield.ymmword
6871 && vector_size >= VSZ256)
6872 i.xstate |= xstate_ymm;
6873 else if (i.tm.operand_types[j].bitfield.xmmword)
6874 i.xstate |= xstate_xmm;
6879 /* Make still unresolved immediate matches conform to size of immediate
6880 given in i.suffix. */
6881 if (!finalize_imm ())
6884 if (i.types[0].bitfield.imm1)
6885 i.imm_operands = 0; /* kludge for shift insns. */
6887 /* For insns with operands there are more diddles to do to the opcode. */
6890 if (!process_operands ())
6893 else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
6895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
6896 as_warn (_("translating to `%sp'"), insn_name (&i.tm));
6899 if (is_any_vex_encoding (&i.tm))
6901 if (!cpu_arch_flags.bitfield.cpui286)
6903 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
6908 /* Check for explicit REX prefix. */
6909 if (i.prefix[REX_PREFIX] || i.rex_encoding)
6911 as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm));
6915 /* Check for explicit REX2 prefix. */
6916 if (i.rex2_encoding)
6918 as_bad (_("{rex2} prefix invalid with `%s'"), insn_name (&i.tm));
6922 if (is_apx_evex_encoding ())
6923 build_apx_evex_prefix ();
6924 else if (i.tm.opcode_modifier.vex)
6925 build_vex_prefix (t);
6927 build_evex_prefix ();
6929 /* The individual REX.RXBW bits got consumed. */
6930 i.rex &= REX_OPCODE;
6932 /* The rex2 bits got consumed. */
6936 /* Handle conversion of 'int $3' --> special int3 insn. */
6937 if (i.tm.mnem_off == MN_int
6938 && i.op[0].imms->X_add_number == 3)
6940 i.tm.base_opcode = INT3_OPCODE;
6944 if ((i.tm.opcode_modifier.jump == JUMP
6945 || i.tm.opcode_modifier.jump == JUMP_BYTE
6946 || i.tm.opcode_modifier.jump == JUMP_DWORD)
6947 && i.op[0].disps->X_op == O_constant)
6949 /* Convert "jmp constant" (and "call constant") to a jump (call) to
6950 the absolute address given by the constant. Since ix86 jumps and
6951 calls are pc relative, we need to generate a reloc. */
6952 i.op[0].disps->X_add_symbol = &abs_symbol;
6953 i.op[0].disps->X_op = O_symbol;
6958 insert_lfence_before (last_insn);
6960 /* We are ready to output the insn. */
6961 output_insn (last_insn);
6963 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
6964 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
6965 performed in i386_target_format. */
6966 if (IS_ELF && flag_synth_cfi)
6969 ginsn = x86_ginsn_new (symbol_temp_new_now (), frch_ginsn_gen_mode ());
6970 frch_ginsn_data_append (ginsn);
6974 insert_lfence_after ();
6976 if (i.tm.opcode_modifier.isprefix)
6978 last_insn->kind = last_insn_prefix;
6979 last_insn->name = insn_name (&i.tm);
6980 last_insn->file = as_where (&last_insn->line);
6983 last_insn->kind = last_insn_other;
6986 /* The Q suffix is generally valid only in 64-bit mode, with very few
6987 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
6988 and fisttp only one of their two templates is matched below: That's
6989 sufficient since other relevant attributes are the same between both
6990 respective templates. */
6991 static INLINE bool q_suffix_allowed(const insn_template *t)
6993 return flag_code == CODE_64BIT
6994 || (t->opcode_space == SPACE_BASE
6995 && t->base_opcode == 0xdf
6996 && (t->extension_opcode & 1)) /* fild / fistp / fisttp */
6997 || t->mnem_off == MN_cmpxchg8b;
7001 parse_insn (const char *line, char *mnemonic, bool prefix_only)
7003 const char *l = line, *token_start = l;
7005 bool pass1 = !current_templates.start;
7007 const insn_template *t;
7013 /* Pseudo-prefixes start with an opening figure brace. */
7014 if ((*mnem_p = *l) == '{')
7019 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
7024 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7027 as_bad (_("no such instruction: `%s'"), token_start);
7032 /* Pseudo-prefixes end with a closing figure brace. */
7033 if (*mnemonic == '{' && *l == '}')
7036 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
7040 /* Point l at the closing brace if there's no other separator. */
7041 if (*l != END_OF_INSN && !is_space_char (*l)
7042 && *l != PREFIX_SEPARATOR)
7045 else if (!is_space_char (*l)
7046 && *l != END_OF_INSN
7048 || (*l != PREFIX_SEPARATOR && *l != ',')))
7052 as_bad (_("invalid character %s in mnemonic"),
7053 output_invalid (*l));
7056 if (token_start == l)
7058 if (!intel_syntax && *l == PREFIX_SEPARATOR)
7059 as_bad (_("expecting prefix; got nothing"));
7061 as_bad (_("expecting mnemonic; got nothing"));
7065 /* Look up instruction (or prefix) via hash table. */
7066 op_lookup (mnemonic);
7068 if (*l != END_OF_INSN
7069 && (!is_space_char (*l) || l[1] != END_OF_INSN)
7070 && current_templates.start
7071 && current_templates.start->opcode_modifier.isprefix)
7073 supported = cpu_flags_match (current_templates.start);
7074 if (!(supported & CPU_FLAGS_64BIT_MATCH))
7076 as_bad ((flag_code != CODE_64BIT
7077 ? _("`%s' is only supported in 64-bit mode")
7078 : _("`%s' is not supported in 64-bit mode")),
7079 insn_name (current_templates.start));
7082 if (supported != CPU_FLAGS_PERFECT_MATCH)
7084 as_bad (_("`%s' is not supported on `%s%s'"),
7085 insn_name (current_templates.start),
7086 cpu_arch_name ? cpu_arch_name : default_arch,
7087 cpu_sub_arch_name ? cpu_sub_arch_name : "");
7090 /* If we are in 16-bit mode, do not allow addr16 or data16.
7091 Similarly, in 32-bit mode, do not allow addr32 or data32. */
7092 if ((current_templates.start->opcode_modifier.size == SIZE16
7093 || current_templates.start->opcode_modifier.size == SIZE32)
7094 && flag_code != CODE_64BIT
7095 && ((current_templates.start->opcode_modifier.size == SIZE32)
7096 ^ (flag_code == CODE_16BIT)))
7098 as_bad (_("redundant %s prefix"),
7099 insn_name (current_templates.start));
7103 if (current_templates.start->base_opcode == PSEUDO_PREFIX)
7105 /* Handle pseudo prefixes. */
7106 switch (current_templates.start->extension_opcode)
7110 i.disp_encoding = disp_encoding_8bit;
7114 i.disp_encoding = disp_encoding_16bit;
7118 i.disp_encoding = disp_encoding_32bit;
7122 i.dir_encoding = dir_encoding_load;
7126 i.dir_encoding = dir_encoding_store;
7130 i.vec_encoding = vex_encoding_vex;
7134 i.vec_encoding = vex_encoding_vex3;
7138 i.vec_encoding = vex_encoding_evex;
7142 i.rex_encoding = true;
7146 i.rex2_encoding = true;
7148 case Prefix_NoOptimize:
7150 i.no_optimize = true;
7158 /* Add prefix, checking for repeated prefixes. */
7159 switch (add_prefix (current_templates.start->base_opcode))
7164 if (is_cpu (current_templates.start, CpuIBT))
7165 i.notrack_prefix = insn_name (current_templates.start);
7168 if (is_cpu (current_templates.start, CpuHLE))
7169 i.hle_prefix = insn_name (current_templates.start);
7170 else if (is_cpu (current_templates.start, CpuMPX))
7171 i.bnd_prefix = insn_name (current_templates.start);
7173 i.rep_prefix = insn_name (current_templates.start);
7179 /* Skip past PREFIX_SEPARATOR and reset token_start. */
7189 if (!current_templates.start)
7191 /* Deprecated functionality (new code should use pseudo-prefixes instead):
7192 Check if we should swap operand or force 32bit displacement in
7194 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
7196 if (i.dir_encoding == dir_encoding_default)
7197 i.dir_encoding = dir_encoding_swap;
7199 as_warn (_("ignoring `.s' suffix due to earlier `{%s}'"),
7200 i.dir_encoding == dir_encoding_load ? "load" : "store");
7202 else if (mnem_p - 3 == dot_p
7206 if (i.disp_encoding == disp_encoding_default)
7207 i.disp_encoding = disp_encoding_8bit;
7208 else if (i.disp_encoding != disp_encoding_8bit)
7209 as_warn (_("ignoring `.d8' suffix due to earlier `{disp<N>}'"));
7211 else if (mnem_p - 4 == dot_p
7216 if (i.disp_encoding == disp_encoding_default)
7217 i.disp_encoding = disp_encoding_32bit;
7218 else if (i.disp_encoding != disp_encoding_32bit)
7219 as_warn (_("ignoring `.d32' suffix due to earlier `{disp<N>}'"));
7225 op_lookup (mnemonic);
7228 if (!current_templates.start || !pass1)
7230 current_templates.start = NULL;
7233 if (mnem_p > mnemonic)
7235 /* See if we can get a match by trimming off a suffix. */
7238 case WORD_MNEM_SUFFIX:
7239 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
7240 i.suffix = SHORT_MNEM_SUFFIX;
7243 case BYTE_MNEM_SUFFIX:
7244 case QWORD_MNEM_SUFFIX:
7245 i.suffix = mnem_p[-1];
7247 op_lookup (mnemonic);
7249 case SHORT_MNEM_SUFFIX:
7250 case LONG_MNEM_SUFFIX:
7253 i.suffix = mnem_p[-1];
7255 op_lookup (mnemonic);
7263 if (intel_float_operand (mnemonic) == 1)
7264 i.suffix = SHORT_MNEM_SUFFIX;
7266 i.suffix = LONG_MNEM_SUFFIX;
7268 op_lookup (mnemonic);
7270 /* For compatibility reasons accept MOVSD and CMPSD without
7271 operands even in AT&T mode. */
7272 else if (*l == END_OF_INSN
7273 || (is_space_char (*l) && l[1] == END_OF_INSN))
7276 op_lookup (mnemonic);
7277 if (current_templates.start != NULL
7279 && (current_templates.start->base_opcode | 2) == 0xa6
7280 && current_templates.start->opcode_space
7282 && mnem_p[-2] == 's')
7284 as_warn (_("found `%sd'; assuming `%sl' was meant"),
7285 mnemonic, mnemonic);
7286 i.suffix = LONG_MNEM_SUFFIX;
7290 current_templates.start = NULL;
7298 if (!current_templates.start)
7301 as_bad (_("no such instruction: `%s'"), token_start);
7306 if (current_templates.start->opcode_modifier.jump == JUMP
7307 || current_templates.start->opcode_modifier.jump == JUMP_BYTE)
7309 /* Check for a branch hint. We allow ",pt" and ",pn" for
7310 predict taken and predict not taken respectively.
7311 I'm not sure that branch hints actually do anything on loop
7312 and jcxz insns (JumpByte) for current Pentium4 chips. They
7313 may work in the future and it doesn't hurt to accept them
7315 if (l[0] == ',' && l[1] == 'p')
7319 if (!add_prefix (DS_PREFIX_OPCODE))
7323 else if (l[2] == 'n')
7325 if (!add_prefix (CS_PREFIX_OPCODE))
7331 /* Any other comma loses. */
7334 as_bad (_("invalid character %s in mnemonic"),
7335 output_invalid (*l));
7339 /* Check if instruction is supported on specified architecture. */
7341 for (t = current_templates.start; t < current_templates.end; ++t)
7343 supported |= cpu_flags_match (t);
7345 if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t))
7346 supported &= ~CPU_FLAGS_64BIT_MATCH;
7348 if (supported == CPU_FLAGS_PERFECT_MATCH)
7354 if (supported & CPU_FLAGS_64BIT_MATCH)
7355 i.error = unsupported_on_arch;
7357 i.error = unsupported_64bit;
7364 parse_operands (char *l, const char *mnemonic)
7368 /* 1 if operand is pending after ','. */
7369 unsigned int expecting_operand = 0;
7371 while (*l != END_OF_INSN)
7373 /* Non-zero if operand parens not balanced. */
7374 unsigned int paren_not_balanced = 0;
7375 /* True if inside double quotes. */
7376 bool in_quotes = false;
7378 /* Skip optional white space before operand. */
7379 if (is_space_char (*l))
7381 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
7383 as_bad (_("invalid character %s before operand %d"),
7384 output_invalid (*l),
7388 token_start = l; /* After white space. */
7389 while (in_quotes || paren_not_balanced || *l != ',')
7391 if (*l == END_OF_INSN)
7395 as_bad (_("unbalanced double quotes in operand %d."),
7399 if (paren_not_balanced)
7401 know (!intel_syntax);
7402 as_bad (_("unbalanced parenthesis in operand %d."),
7407 break; /* we are done */
7409 else if (*l == '\\' && l[1] == '"')
7412 in_quotes = !in_quotes;
7413 else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l))
7415 as_bad (_("invalid character %s in operand %d"),
7416 output_invalid (*l),
7420 if (!intel_syntax && !in_quotes)
7423 ++paren_not_balanced;
7425 --paren_not_balanced;
7429 if (l != token_start)
7430 { /* Yes, we've read in another operand. */
7431 unsigned int operand_ok;
7432 this_operand = i.operands++;
7433 if (i.operands > MAX_OPERANDS)
7435 as_bad (_("spurious operands; (%d operands/instruction max)"),
7439 i.types[this_operand].bitfield.unspecified = 1;
7440 /* Now parse operand adding info to 'i' as we go along. */
7441 END_STRING_AND_SAVE (l);
7443 if (i.mem_operands > 1)
7445 as_bad (_("too many memory references for `%s'"),
7452 i386_intel_operand (token_start,
7453 intel_float_operand (mnemonic));
7455 operand_ok = i386_att_operand (token_start);
7457 RESTORE_END_STRING (l);
7463 if (expecting_operand)
7465 expecting_operand_after_comma:
7466 as_bad (_("expecting operand after ','; got nothing"));
7471 as_bad (_("expecting operand before ','; got nothing"));
7476 /* Now *l must be either ',' or END_OF_INSN. */
7479 if (*++l == END_OF_INSN)
7481 /* Just skip it, if it's \n complain. */
7482 goto expecting_operand_after_comma;
7484 expecting_operand = 1;
7491 swap_2_operands (unsigned int xchg1, unsigned int xchg2)
7493 union i386_op temp_op;
7494 i386_operand_type temp_type;
7495 unsigned int temp_flags;
7496 enum bfd_reloc_code_real temp_reloc;
7498 temp_type = i.types[xchg2];
7499 i.types[xchg2] = i.types[xchg1];
7500 i.types[xchg1] = temp_type;
7502 temp_flags = i.flags[xchg2];
7503 i.flags[xchg2] = i.flags[xchg1];
7504 i.flags[xchg1] = temp_flags;
7506 temp_op = i.op[xchg2];
7507 i.op[xchg2] = i.op[xchg1];
7508 i.op[xchg1] = temp_op;
7510 temp_reloc = i.reloc[xchg2];
7511 i.reloc[xchg2] = i.reloc[xchg1];
7512 i.reloc[xchg1] = temp_reloc;
7514 temp_flags = i.imm_bits[xchg2];
7515 i.imm_bits[xchg2] = i.imm_bits[xchg1];
7516 i.imm_bits[xchg1] = temp_flags;
7520 if (i.mask.operand == xchg1)
7521 i.mask.operand = xchg2;
7522 else if (i.mask.operand == xchg2)
7523 i.mask.operand = xchg1;
7525 if (i.broadcast.type || i.broadcast.bytes)
7527 if (i.broadcast.operand == xchg1)
7528 i.broadcast.operand = xchg2;
7529 else if (i.broadcast.operand == xchg2)
7530 i.broadcast.operand = xchg1;
7535 swap_operands (void)
7541 swap_2_operands (1, i.operands - 2);
7545 swap_2_operands (0, i.operands - 1);
7551 if (i.mem_operands == 2)
7553 const reg_entry *temp_seg;
7554 temp_seg = i.seg[0];
7555 i.seg[0] = i.seg[1];
7556 i.seg[1] = temp_seg;
7560 /* Try to ensure constant immediates are represented in the smallest
7565 char guess_suffix = 0;
7569 guess_suffix = i.suffix;
7570 else if (i.reg_operands)
7572 /* Figure out a suffix from the last register operand specified.
7573 We can't do this properly yet, i.e. excluding special register
7574 instances, but the following works for instructions with
7575 immediates. In any case, we can't set i.suffix yet. */
7576 for (op = i.operands; --op >= 0;)
7577 if (i.types[op].bitfield.class != Reg)
7579 else if (i.types[op].bitfield.byte)
7581 guess_suffix = BYTE_MNEM_SUFFIX;
7584 else if (i.types[op].bitfield.word)
7586 guess_suffix = WORD_MNEM_SUFFIX;
7589 else if (i.types[op].bitfield.dword)
7591 guess_suffix = LONG_MNEM_SUFFIX;
7594 else if (i.types[op].bitfield.qword)
7596 guess_suffix = QWORD_MNEM_SUFFIX;
7600 else if ((flag_code == CODE_16BIT)
7601 ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
7602 guess_suffix = WORD_MNEM_SUFFIX;
7603 else if (flag_code != CODE_64BIT
7604 || (!(i.prefix[REX_PREFIX] & REX_W)
7605 /* A more generic (but also more involved) way of dealing
7606 with the special case(s) would be to go look for
7607 DefaultSize attributes on any of the templates. */
7608 && current_templates.start->mnem_off != MN_push))
7609 guess_suffix = LONG_MNEM_SUFFIX;
7611 for (op = i.operands; --op >= 0;)
7612 if (operand_type_check (i.types[op], imm))
7614 switch (i.op[op].imms->X_op)
7617 /* If a suffix is given, this operand may be shortened. */
7618 switch (guess_suffix)
7620 case LONG_MNEM_SUFFIX:
7621 i.types[op].bitfield.imm32 = 1;
7622 i.types[op].bitfield.imm64 = 1;
7624 case WORD_MNEM_SUFFIX:
7625 i.types[op].bitfield.imm16 = 1;
7626 i.types[op].bitfield.imm32 = 1;
7627 i.types[op].bitfield.imm32s = 1;
7628 i.types[op].bitfield.imm64 = 1;
7630 case BYTE_MNEM_SUFFIX:
7631 i.types[op].bitfield.imm8 = 1;
7632 i.types[op].bitfield.imm8s = 1;
7633 i.types[op].bitfield.imm16 = 1;
7634 i.types[op].bitfield.imm32 = 1;
7635 i.types[op].bitfield.imm32s = 1;
7636 i.types[op].bitfield.imm64 = 1;
7640 /* If this operand is at most 16 bits, convert it
7641 to a signed 16 bit number before trying to see
7642 whether it will fit in an even smaller size.
7643 This allows a 16-bit operand such as $0xffe0 to
7644 be recognised as within Imm8S range. */
7645 if ((i.types[op].bitfield.imm16)
7646 && fits_in_unsigned_word (i.op[op].imms->X_add_number))
7648 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
7649 ^ 0x8000) - 0x8000);
7652 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
7653 if ((i.types[op].bitfield.imm32)
7654 && fits_in_unsigned_long (i.op[op].imms->X_add_number))
7656 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
7657 ^ ((offsetT) 1 << 31))
7658 - ((offsetT) 1 << 31));
7662 = operand_type_or (i.types[op],
7663 smallest_imm_type (i.op[op].imms->X_add_number));
7665 /* We must avoid matching of Imm32 templates when 64bit
7666 only immediate is available. */
7667 if (guess_suffix == QWORD_MNEM_SUFFIX)
7668 i.types[op].bitfield.imm32 = 0;
7675 /* Symbols and expressions. */
7677 /* Convert symbolic operand to proper sizes for matching, but don't
7678 prevent matching a set of insns that only supports sizes other
7679 than those matching the insn suffix. */
7681 i386_operand_type mask, allowed;
7682 const insn_template *t = current_templates.start;
7684 operand_type_set (&mask, 0);
7685 switch (guess_suffix)
7687 case QWORD_MNEM_SUFFIX:
7688 mask.bitfield.imm64 = 1;
7689 mask.bitfield.imm32s = 1;
7691 case LONG_MNEM_SUFFIX:
7692 mask.bitfield.imm32 = 1;
7694 case WORD_MNEM_SUFFIX:
7695 mask.bitfield.imm16 = 1;
7697 case BYTE_MNEM_SUFFIX:
7698 mask.bitfield.imm8 = 1;
7704 allowed = operand_type_and (t->operand_types[op], mask);
7705 while (++t < current_templates.end)
7707 allowed = operand_type_or (allowed, t->operand_types[op]);
7708 allowed = operand_type_and (allowed, mask);
7711 if (!operand_type_all_zero (&allowed))
7712 i.types[op] = operand_type_and (i.types[op], mask);
7719 /* Try to use the smallest displacement type too. */
7721 optimize_disp (const insn_template *t)
7725 if (!want_disp32 (t)
7726 && (!t->opcode_modifier.jump
7727 || i.jumpabsolute || i.types[0].bitfield.baseindex))
7729 for (op = 0; op < i.operands; ++op)
7731 const expressionS *exp = i.op[op].disps;
7733 if (!operand_type_check (i.types[op], disp))
7736 if (exp->X_op != O_constant)
7739 /* Since displacement is signed extended to 64bit, don't allow
7740 disp32 if it is out of range. */
7741 if (fits_in_signed_long (exp->X_add_number))
7744 i.types[op].bitfield.disp32 = 0;
7745 if (i.types[op].bitfield.baseindex)
7747 as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"),
7748 (uint64_t) exp->X_add_number);
7754 /* Don't optimize displacement for movabs since it only takes 64bit
7756 if (i.disp_encoding > disp_encoding_8bit
7757 || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs))
7760 for (op = i.operands; op-- > 0;)
7761 if (operand_type_check (i.types[op], disp))
7763 if (i.op[op].disps->X_op == O_constant)
7765 offsetT op_disp = i.op[op].disps->X_add_number;
7767 if (!op_disp && i.types[op].bitfield.baseindex)
7769 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7770 i.op[op].disps = NULL;
7775 if (i.types[op].bitfield.disp16
7776 && fits_in_unsigned_word (op_disp))
7778 /* If this operand is at most 16 bits, convert
7779 to a signed 16 bit number and don't use 64bit
7781 op_disp = ((op_disp ^ 0x8000) - 0x8000);
7782 i.types[op].bitfield.disp64 = 0;
7786 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
7787 if ((flag_code != CODE_64BIT
7788 ? i.types[op].bitfield.disp32
7790 && (!t->opcode_modifier.jump
7791 || i.jumpabsolute || i.types[op].bitfield.baseindex))
7792 && fits_in_unsigned_long (op_disp))
7794 /* If this operand is at most 32 bits, convert
7795 to a signed 32 bit number and don't use 64bit
7797 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
7798 i.types[op].bitfield.disp64 = 0;
7799 i.types[op].bitfield.disp32 = 1;
7802 if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp))
7804 i.types[op].bitfield.disp64 = 0;
7805 i.types[op].bitfield.disp32 = 1;
7808 if ((i.types[op].bitfield.disp32
7809 || i.types[op].bitfield.disp16)
7810 && fits_in_disp8 (op_disp))
7811 i.types[op].bitfield.disp8 = 1;
7813 i.op[op].disps->X_add_number = op_disp;
7815 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7816 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
7818 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
7819 i.op[op].disps, 0, i.reloc[op]);
7820 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7823 /* We only support 64bit displacement on constants. */
7824 i.types[op].bitfield.disp64 = 0;
7830 /* Return 1 if there is a match in broadcast bytes between operand
7831 GIVEN and instruction template T. */
7834 match_broadcast_size (const insn_template *t, unsigned int given)
7836 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
7837 && i.types[given].bitfield.byte)
7838 || (t->opcode_modifier.broadcast == WORD_BROADCAST
7839 && i.types[given].bitfield.word)
7840 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
7841 && i.types[given].bitfield.dword)
7842 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
7843 && i.types[given].bitfield.qword));
7846 /* Check if operands are valid for the instruction. */
7849 check_VecOperands (const insn_template *t)
7854 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
7855 any one operand are implicity requiring AVX512VL support if the actual
7856 operand size is YMMword or XMMword. Since this function runs after
7857 template matching, there's no need to check for YMMword/XMMword in
7859 cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512);
7860 if (!cpu_flags_all_zero (&cpu)
7861 && !is_cpu (t, CpuAVX512VL)
7862 && !cpu_arch_flags.bitfield.cpuavx512vl
7863 && (!t->opcode_modifier.vex || need_evex_encoding (t)))
7865 for (op = 0; op < t->operands; ++op)
7867 if (t->operand_types[op].bitfield.zmmword
7868 && (i.types[op].bitfield.ymmword
7869 || i.types[op].bitfield.xmmword))
7871 i.error = operand_size_mismatch;
7877 /* Somewhat similarly, templates specifying both AVX and AVX2 are
7878 requiring AVX2 support if the actual operand size is YMMword. */
7879 if (maybe_cpu (t, CpuAVX) && maybe_cpu (t, CpuAVX2)
7880 && !cpu_arch_flags.bitfield.cpuavx2)
7882 for (op = 0; op < t->operands; ++op)
7884 if (t->operand_types[op].bitfield.xmmword
7885 && i.types[op].bitfield.ymmword)
7887 i.error = operand_size_mismatch;
7893 /* Without VSIB byte, we can't have a vector register for index. */
7894 if (!t->opcode_modifier.sib
7896 && (i.index_reg->reg_type.bitfield.xmmword
7897 || i.index_reg->reg_type.bitfield.ymmword
7898 || i.index_reg->reg_type.bitfield.zmmword))
7900 i.error = unsupported_vector_index_register;
7904 /* Check if default mask is allowed. */
7905 if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK
7906 && (!i.mask.reg || i.mask.reg->reg_num == 0))
7908 i.error = no_default_mask;
7912 /* For VSIB byte, we need a vector register for index, and all vector
7913 registers must be distinct. */
7914 if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM)
7917 || !((t->opcode_modifier.sib == VECSIB128
7918 && i.index_reg->reg_type.bitfield.xmmword)
7919 || (t->opcode_modifier.sib == VECSIB256
7920 && i.index_reg->reg_type.bitfield.ymmword)
7921 || (t->opcode_modifier.sib == VECSIB512
7922 && i.index_reg->reg_type.bitfield.zmmword)))
7924 i.error = invalid_vsib_address;
7928 gas_assert (i.reg_operands == 2 || i.mask.reg);
7929 if (i.reg_operands == 2 && !i.mask.reg)
7931 gas_assert (i.types[0].bitfield.class == RegSIMD);
7932 gas_assert (i.types[0].bitfield.xmmword
7933 || i.types[0].bitfield.ymmword);
7934 gas_assert (i.types[2].bitfield.class == RegSIMD);
7935 gas_assert (i.types[2].bitfield.xmmword
7936 || i.types[2].bitfield.ymmword);
7937 if (operand_check == check_none)
7939 if (register_number (i.op[0].regs)
7940 != register_number (i.index_reg)
7941 && register_number (i.op[2].regs)
7942 != register_number (i.index_reg)
7943 && register_number (i.op[0].regs)
7944 != register_number (i.op[2].regs))
7946 if (operand_check == check_error)
7948 i.error = invalid_vector_register_set;
7951 as_warn (_("mask, index, and destination registers should be distinct"));
7953 else if (i.reg_operands == 1 && i.mask.reg)
7955 if (i.types[1].bitfield.class == RegSIMD
7956 && (i.types[1].bitfield.xmmword
7957 || i.types[1].bitfield.ymmword
7958 || i.types[1].bitfield.zmmword)
7959 && (register_number (i.op[1].regs)
7960 == register_number (i.index_reg)))
7962 if (operand_check == check_error)
7964 i.error = invalid_vector_register_set;
7967 if (operand_check != check_none)
7968 as_warn (_("index and destination registers should be distinct"));
7973 /* For AMX instructions with 3 TMM register operands, all operands
7974 must be distinct. */
7975 if (i.reg_operands == 3
7976 && t->operand_types[0].bitfield.tmmword
7977 && (i.op[0].regs == i.op[1].regs
7978 || i.op[0].regs == i.op[2].regs
7979 || i.op[1].regs == i.op[2].regs))
7981 i.error = invalid_tmm_register_set;
7985 /* For some special instructions require that destination must be distinct
7986 from source registers. */
7987 if (t->opcode_modifier.operandconstraint == DISTINCT_DEST)
7989 unsigned int dest_reg = i.operands - 1;
7991 know (i.operands >= 3);
7993 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
7994 if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs
7995 || (i.reg_operands > 2
7996 && i.op[dest_reg - 2].regs == i.op[dest_reg].regs))
7998 i.error = invalid_dest_and_src_register_set;
8003 /* Check if broadcast is supported by the instruction and is applied
8004 to the memory operand. */
8005 if (i.broadcast.type || i.broadcast.bytes)
8007 i386_operand_type type, overlap;
8009 /* Check if specified broadcast is supported in this instruction,
8010 and its broadcast bytes match the memory operand. */
8011 op = i.broadcast.operand;
8012 if (!t->opcode_modifier.broadcast
8013 || !(i.flags[op] & Operand_Mem)
8014 || (!i.types[op].bitfield.unspecified
8015 && !match_broadcast_size (t, op)))
8018 i.error = unsupported_broadcast;
8022 operand_type_set (&type, 0);
8023 switch (get_broadcast_bytes (t, false))
8026 type.bitfield.word = 1;
8029 type.bitfield.dword = 1;
8032 type.bitfield.qword = 1;
8035 type.bitfield.xmmword = 1;
8038 if (vector_size < VSZ256)
8040 type.bitfield.ymmword = 1;
8043 if (vector_size < VSZ512)
8045 type.bitfield.zmmword = 1;
8051 overlap = operand_type_and (type, t->operand_types[op]);
8052 if (t->operand_types[op].bitfield.class == RegSIMD
8053 && t->operand_types[op].bitfield.byte
8054 + t->operand_types[op].bitfield.word
8055 + t->operand_types[op].bitfield.dword
8056 + t->operand_types[op].bitfield.qword > 1)
8058 overlap.bitfield.xmmword = 0;
8059 overlap.bitfield.ymmword = 0;
8060 overlap.bitfield.zmmword = 0;
8062 if (operand_type_all_zero (&overlap))
8065 if (t->opcode_modifier.checkoperandsize)
8069 type.bitfield.baseindex = 1;
8070 for (j = 0; j < i.operands; ++j)
8073 && !operand_type_register_match(i.types[j],
8074 t->operand_types[j],
8076 t->operand_types[op]))
8081 /* If broadcast is supported in this instruction, we need to check if
8082 operand of one-element size isn't specified without broadcast. */
8083 else if (t->opcode_modifier.broadcast && i.mem_operands)
8085 /* Find memory operand. */
8086 for (op = 0; op < i.operands; op++)
8087 if (i.flags[op] & Operand_Mem)
8089 gas_assert (op < i.operands);
8090 /* Check size of the memory operand. */
8091 if (match_broadcast_size (t, op))
8093 i.error = broadcast_needed;
8098 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
8100 /* Check if requested masking is supported. */
8103 if (!t->opcode_modifier.masking)
8105 i.error = unsupported_masking;
8109 /* Common rules for masking:
8110 - mask register destinations permit only zeroing-masking, without
8111 that actually being expressed by a {z} operand suffix or EVEX.z,
8112 - memory destinations allow only merging-masking,
8113 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
8116 && (t->operand_types[t->operands - 1].bitfield.class == RegMask
8117 || (i.flags[t->operands - 1] & Operand_Mem)
8118 || t->opcode_modifier.sib))
8120 i.error = unsupported_masking;
8125 /* Check if masking is applied to dest operand. */
8126 if (i.mask.reg && (i.mask.operand != i.operands - 1))
8128 i.error = mask_not_on_destination;
8133 if (i.rounding.type != rc_none)
8135 if (!t->opcode_modifier.sae
8136 || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding)
8139 i.error = unsupported_rc_sae;
8143 /* Non-EVEX.LIG forms need to have a ZMM register as at least one
8145 if (t->opcode_modifier.evex != EVEXLIG)
8147 for (op = 0; op < t->operands; ++op)
8148 if (i.types[op].bitfield.zmmword)
8150 if (op >= t->operands)
8152 i.error = operand_size_mismatch;
8158 /* Check the special Imm4 cases; must be the first operand. */
8159 if ((is_cpu (t, CpuXOP) && t->operands == 5)
8160 || (is_cpu (t, CpuAPX_F) && t->opcode_space == SPACE_0F3A))
8162 if (i.op[0].imms->X_op != O_constant
8163 || !fits_in_imm4 (i.op[0].imms->X_add_number))
8169 /* Turn off Imm<N> so that update_imm won't complain. */
8170 if (t->operands == 5)
8171 operand_type_set (&i.types[0], 0);
8174 /* Check vector Disp8 operand. */
8175 if (t->opcode_modifier.disp8memshift
8176 && (!t->opcode_modifier.vex
8177 || need_evex_encoding (t))
8178 && i.disp_encoding <= disp_encoding_8bit)
8180 if (i.broadcast.type || i.broadcast.bytes)
8181 i.memshift = t->opcode_modifier.broadcast - 1;
8182 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
8183 i.memshift = t->opcode_modifier.disp8memshift;
8186 const i386_operand_type *type = NULL, *fallback = NULL;
8189 for (op = 0; op < i.operands; op++)
8190 if (i.flags[op] & Operand_Mem)
8192 if (t->opcode_modifier.evex == EVEXLIG)
8193 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
8194 else if (t->operand_types[op].bitfield.xmmword
8195 + t->operand_types[op].bitfield.ymmword
8196 + t->operand_types[op].bitfield.zmmword <= 1)
8197 type = &t->operand_types[op];
8198 else if (!i.types[op].bitfield.unspecified)
8199 type = &i.types[op];
8200 else /* Ambiguities get resolved elsewhere. */
8201 fallback = &t->operand_types[op];
8203 else if (i.types[op].bitfield.class == RegSIMD
8204 && t->opcode_modifier.evex != EVEXLIG)
8206 if (i.types[op].bitfield.zmmword)
8208 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
8210 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
8214 if (!type && !i.memshift)
8218 if (type->bitfield.zmmword)
8220 else if (type->bitfield.ymmword)
8222 else if (type->bitfield.xmmword)
8226 /* For the check in fits_in_disp8(). */
8227 if (i.memshift == 0)
8231 for (op = 0; op < i.operands; op++)
8232 if (operand_type_check (i.types[op], disp)
8233 && i.op[op].disps->X_op == O_constant)
8235 if (fits_in_disp8 (i.op[op].disps->X_add_number))
8237 i.types[op].bitfield.disp8 = 1;
8240 i.types[op].bitfield.disp8 = 0;
8249 /* Check if encoding requirements are met by the instruction. */
8252 VEX_check_encoding (const insn_template *t)
8254 if (i.vec_encoding == vex_encoding_error)
8256 i.error = unsupported;
8260 /* Vector size restrictions. */
8261 if ((vector_size < VSZ512
8262 && t->opcode_modifier.evex == EVEX512)
8263 || (vector_size < VSZ256
8264 && (t->opcode_modifier.evex == EVEX256
8265 || t->opcode_modifier.vex == VEX256)))
8267 i.error = unsupported_vector_size;
8271 if (i.vec_encoding == vex_encoding_evex
8272 || i.vec_encoding == vex_encoding_evex512)
8274 /* This instruction must be encoded with EVEX prefix. */
8275 if (!t->opcode_modifier.evex)
8277 i.error = no_evex_encoding;
8283 if (!t->opcode_modifier.vex)
8285 /* This instruction template doesn't have VEX prefix. */
8286 if (i.vec_encoding != vex_encoding_default)
8288 i.error = no_vex_encoding;
8297 /* Check if Egprs operands are valid for the instruction. */
8300 check_EgprOperands (const insn_template *t)
8302 if (!t->opcode_modifier.noegpr)
8305 for (unsigned int op = 0; op < i.operands; op++)
8307 if (i.types[op].bitfield.class != Reg)
8310 if (i.op[op].regs->reg_flags & RegRex2)
8312 i.error = register_type_mismatch;
8317 if ((i.index_reg && (i.index_reg->reg_flags & RegRex2))
8318 || (i.base_reg && (i.base_reg->reg_flags & RegRex2)))
8320 i.error = unsupported_EGPR_for_addressing;
8324 /* Check if pseudo prefix {rex2} is valid. */
8325 if (i.rex2_encoding)
8327 i.error = invalid_pseudo_prefix;
8334 /* Check if APX operands are valid for the instruction. */
8336 check_APX_operands (const insn_template *t)
8338 /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
8340 switch (t->mnem_off)
8344 if (register_number (i.op[0].regs) == register_number (i.op[1].regs))
8346 i.error = invalid_dest_register_set;
8352 if (register_number (i.op[0].regs) == 4
8353 || register_number (i.op[1].regs) == 4)
8355 i.error = unsupported_rsp_register;
8363 /* Check if the instruction use the REX registers or REX prefix. */
8365 check_Rex_required (void)
8367 for (unsigned int op = 0; op < i.operands; op++)
8369 if (i.types[op].bitfield.class != Reg)
8372 if (i.op[op].regs->reg_flags & (RegRex | RegRex64))
8376 if ((i.index_reg && (i.index_reg->reg_flags & (RegRex | RegRex64)))
8377 || (i.base_reg && (i.base_reg->reg_flags & (RegRex | RegRex64))))
8380 /* Check pseudo prefix {rex} are valid. */
8381 return i.rex_encoding;
8384 /* Optimize APX NDD insns to legacy insns. */
8386 can_convert_NDD_to_legacy (const insn_template *t)
8388 unsigned int match_dest_op = ~0;
8390 if (!i.tm.opcode_modifier.nf
8391 && i.reg_operands >= 2)
8393 unsigned int dest = i.operands - 1;
8394 unsigned int src1 = i.operands - 2;
8395 unsigned int src2 = (i.operands > 3) ? i.operands - 3 : 0;
8397 if (i.types[src1].bitfield.class == Reg
8398 && i.op[src1].regs == i.op[dest].regs)
8399 match_dest_op = src1;
8400 /* If the first operand is the same as the third operand,
8401 these instructions need to support the ability to commutative
8402 the first two operands and still not change the semantics in order
8404 else if (optimize > 1
8405 && t->opcode_modifier.commutative
8406 && i.types[src2].bitfield.class == Reg
8407 && i.op[src2].regs == i.op[dest].regs)
8408 match_dest_op = src2;
8410 return match_dest_op;
8413 /* Helper function for the progress() macro in match_template(). */
8414 static INLINE enum i386_error progress (enum i386_error new,
8415 enum i386_error last,
8416 unsigned int line, unsigned int *line_p)
8418 if (line <= *line_p)
8424 static const insn_template *
8425 match_template (char mnem_suffix)
8427 /* Points to template once we've found it. */
8428 const insn_template *t;
8429 i386_operand_type overlap0, overlap1, overlap2, overlap3;
8430 i386_operand_type overlap4;
8431 unsigned int found_reverse_match;
8432 i386_operand_type operand_types [MAX_OPERANDS];
8433 int addr_prefix_disp;
8434 unsigned int j, size_match, check_register, errline = __LINE__;
8435 enum i386_error specific_error = number_of_operands_mismatch;
8436 #define progress(err) progress (err, specific_error, __LINE__, &errline)
8438 #if MAX_OPERANDS != 5
8439 # error "MAX_OPERANDS must be 5."
8442 found_reverse_match = 0;
8443 addr_prefix_disp = -1;
8445 for (t = current_templates.start; t < current_templates.end; t++)
8447 addr_prefix_disp = -1;
8448 found_reverse_match = 0;
8450 /* Must have right number of operands. */
8451 if (i.operands != t->operands)
8454 /* Check processor support. */
8455 specific_error = progress (unsupported);
8456 if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH)
8459 /* Check AT&T mnemonic. */
8460 specific_error = progress (unsupported_with_intel_mnemonic);
8461 if (!intel_syntax && intel_mnemonic
8462 && t->opcode_modifier.dialect == ATT_MNEMONIC)
8465 /* Check AT&T/Intel syntax. */
8466 specific_error = progress (unsupported_syntax);
8468 ? t->opcode_modifier.dialect >= ATT_SYNTAX
8469 : t->opcode_modifier.dialect == INTEL_SYNTAX)
8472 /* Check Intel64/AMD64 ISA. */
8476 /* Default: Don't accept Intel64. */
8477 if (t->opcode_modifier.isa64 == INTEL64)
8481 /* -mamd64: Don't accept Intel64 and Intel64 only. */
8482 if (t->opcode_modifier.isa64 >= INTEL64)
8486 /* -mintel64: Don't accept AMD64. */
8487 if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT)
8492 /* Check the suffix. */
8493 specific_error = progress (invalid_instruction_suffix);
8494 if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX)
8495 || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX)
8496 || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX)
8497 || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX)
8498 || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX))
8501 specific_error = progress (operand_size_mismatch);
8502 size_match = operand_size_match (t);
8506 /* This is intentionally not
8508 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
8510 as the case of a missing * on the operand is accepted (perhaps with
8511 a warning, issued further down). */
8512 specific_error = progress (operand_type_mismatch);
8513 if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE)
8516 /* In Intel syntax, normally we can check for memory operand size when
8517 there is no mnemonic suffix. But jmp and call have 2 different
8518 encodings with Dword memory operand size. Skip the "near" one
8519 (permitting a register operand) when "far" was requested. */
8521 && t->opcode_modifier.jump == JUMP_ABSOLUTE
8522 && t->operand_types[0].bitfield.class == Reg)
8525 for (j = 0; j < MAX_OPERANDS; j++)
8526 operand_types[j] = t->operand_types[j];
8528 /* In general, don't allow 32-bit operands on pre-386. */
8529 specific_error = progress (mnem_suffix ? invalid_instruction_suffix
8530 : operand_size_mismatch);
8531 j = i.imm_operands + (t->operands > i.imm_operands + 1);
8532 if (i.suffix == LONG_MNEM_SUFFIX
8533 && !cpu_arch_flags.bitfield.cpui386
8535 ? (t->opcode_modifier.mnemonicsize != IGNORESIZE
8536 && !intel_float_operand (insn_name (t)))
8537 : intel_float_operand (insn_name (t)) != 2)
8538 && (t->operands == i.imm_operands
8539 || (operand_types[i.imm_operands].bitfield.class != RegMMX
8540 && operand_types[i.imm_operands].bitfield.class != RegSIMD
8541 && operand_types[i.imm_operands].bitfield.class != RegMask)
8542 || (operand_types[j].bitfield.class != RegMMX
8543 && operand_types[j].bitfield.class != RegSIMD
8544 && operand_types[j].bitfield.class != RegMask))
8545 && !t->opcode_modifier.sib)
8548 /* Do not verify operands when there are none. */
8551 if (VEX_check_encoding (t))
8553 specific_error = progress (i.error);
8557 /* Check if pseudo prefix {rex2} is valid. */
8558 if (t->opcode_modifier.noegpr && i.rex2_encoding)
8560 specific_error = progress (invalid_pseudo_prefix);
8564 /* We've found a match; break out of loop. */
8568 if (!t->opcode_modifier.jump
8569 || t->opcode_modifier.jump == JUMP_ABSOLUTE)
8571 /* There should be only one Disp operand. */
8572 for (j = 0; j < MAX_OPERANDS; j++)
8573 if (operand_type_check (operand_types[j], disp))
8575 if (j < MAX_OPERANDS)
8577 bool override = (i.prefix[ADDR_PREFIX] != 0);
8579 addr_prefix_disp = j;
8581 /* Address size prefix will turn Disp64 operand into Disp32 and
8582 Disp32/Disp16 one into Disp16/Disp32 respectively. */
8586 override = !override;
8589 if (operand_types[j].bitfield.disp32
8590 && operand_types[j].bitfield.disp16)
8592 operand_types[j].bitfield.disp16 = override;
8593 operand_types[j].bitfield.disp32 = !override;
8595 gas_assert (!operand_types[j].bitfield.disp64);
8599 if (operand_types[j].bitfield.disp64)
8601 gas_assert (!operand_types[j].bitfield.disp32);
8602 operand_types[j].bitfield.disp32 = override;
8603 operand_types[j].bitfield.disp64 = !override;
8605 operand_types[j].bitfield.disp16 = 0;
8611 /* We check register size if needed. */
8612 if (t->opcode_modifier.checkoperandsize)
8614 check_register = (1 << t->operands) - 1;
8615 if (i.broadcast.type || i.broadcast.bytes)
8616 check_register &= ~(1 << i.broadcast.operand);
8621 overlap0 = operand_type_and (i.types[0], operand_types[0]);
8622 switch (t->operands)
8625 if (!operand_type_match (overlap0, i.types[0]))
8628 /* Allow the ModR/M encoding to be requested by using the {load} or
8629 {store} pseudo prefix on an applicable insn. */
8630 if (!t->opcode_modifier.modrm
8631 && i.reg_operands == 1
8632 && ((i.dir_encoding == dir_encoding_load
8633 && t->mnem_off != MN_pop)
8634 || (i.dir_encoding == dir_encoding_store
8635 && t->mnem_off != MN_push))
8637 && t->mnem_off != MN_bswap)
8642 /* xchg %eax, %eax is a special case. It is an alias for nop
8643 only in 32bit mode and we can use opcode 0x90. In 64bit
8644 mode, we can't use 0x90 for xchg %eax, %eax since it should
8645 zero-extend %eax to %rax. */
8646 if (t->base_opcode == 0x90
8647 && t->opcode_space == SPACE_BASE)
8649 if (flag_code == CODE_64BIT
8650 && i.types[0].bitfield.instance == Accum
8651 && i.types[0].bitfield.dword
8652 && i.types[1].bitfield.instance == Accum)
8655 /* Allow the ModR/M encoding to be requested by using the
8656 {load} or {store} pseudo prefix. */
8657 if (i.dir_encoding == dir_encoding_load
8658 || i.dir_encoding == dir_encoding_store)
8662 if (t->base_opcode == MOV_AX_DISP32
8663 && t->opcode_space == SPACE_BASE
8664 && t->mnem_off != MN_movabs)
8666 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
8667 if (i.reloc[0] == BFD_RELOC_386_GOT32)
8670 /* xrelease mov %eax, <disp> is another special case. It must not
8671 match the accumulator-only encoding of mov. */
8675 /* Allow the ModR/M encoding to be requested by using a suitable
8676 {load} or {store} pseudo prefix. */
8677 if (i.dir_encoding == (i.types[0].bitfield.instance == Accum
8678 ? dir_encoding_store
8679 : dir_encoding_load)
8680 && !i.types[0].bitfield.disp64
8681 && !i.types[1].bitfield.disp64)
8685 /* Allow the ModR/M encoding to be requested by using the {load} or
8686 {store} pseudo prefix on an applicable insn. */
8687 if (!t->opcode_modifier.modrm
8688 && i.reg_operands == 1
8689 && i.imm_operands == 1
8690 && (i.dir_encoding == dir_encoding_load
8691 || i.dir_encoding == dir_encoding_store)
8692 && t->opcode_space == SPACE_BASE)
8694 if (t->base_opcode == 0xb0 /* mov $imm, %reg */
8695 && i.dir_encoding == dir_encoding_store)
8698 if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */
8699 && (t->base_opcode != 0x3c /* cmp $imm, %acc */
8700 || i.dir_encoding == dir_encoding_load))
8703 if (t->base_opcode == 0xa8 /* test $imm, %acc */
8704 && i.dir_encoding == dir_encoding_load)
8710 if (!(size_match & MATCH_STRAIGHT))
8712 /* Reverse direction of operands if swapping is possible in the first
8713 place (operands need to be symmetric) and
8714 - the load form is requested, and the template is a store form,
8715 - the store form is requested, and the template is a load form,
8716 - the non-default (swapped) form is requested. */
8717 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
8719 j = i.operands - 1 - (t->opcode_space == SPACE_EVEXMAP4
8720 && t->opcode_modifier.vexvvvv);
8722 if (t->opcode_modifier.d && i.reg_operands == i.operands
8723 && !operand_type_all_zero (&overlap1))
8724 switch (i.dir_encoding)
8726 case dir_encoding_load:
8727 if (operand_type_check (operand_types[j], anymem)
8728 || t->opcode_modifier.regmem)
8732 case dir_encoding_store:
8733 if (!operand_type_check (operand_types[j], anymem)
8734 && !t->opcode_modifier.regmem)
8738 case dir_encoding_swap:
8741 case dir_encoding_default:
8745 /* If we want store form, we skip the current load. */
8746 if ((i.dir_encoding == dir_encoding_store
8747 || i.dir_encoding == dir_encoding_swap)
8748 && i.mem_operands == 0
8749 && t->opcode_modifier.load)
8754 overlap1 = operand_type_and (i.types[1], operand_types[1]);
8755 if (!operand_type_match (overlap0, i.types[0])
8756 || !operand_type_match (overlap1, i.types[1])
8757 || ((check_register & 3) == 3
8758 && !operand_type_register_match (i.types[0],
8763 specific_error = progress (i.error);
8765 /* Check if other direction is valid ... */
8766 if (!t->opcode_modifier.d)
8770 if (!(size_match & MATCH_REVERSE))
8772 /* Try reversing direction of operands. */
8773 j = is_cpu (t, CpuFMA4)
8774 || is_cpu (t, CpuXOP)
8775 || is_cpu (t, CpuAPX_F) ? 1 : i.operands - 1;
8776 overlap0 = operand_type_and (i.types[0], operand_types[j]);
8777 overlap1 = operand_type_and (i.types[j], operand_types[0]);
8778 overlap2 = operand_type_and (i.types[1], operand_types[1]);
8779 gas_assert (t->operands != 3 || !check_register
8780 || is_cpu (t, CpuAPX_F));
8781 if (!operand_type_match (overlap0, i.types[0])
8782 || !operand_type_match (overlap1, i.types[j])
8783 || (t->operands == 3
8784 && !operand_type_match (overlap2, i.types[1]))
8786 && !operand_type_register_match (i.types[0],
8791 /* Does not match either direction. */
8792 specific_error = progress (i.error);
8795 /* found_reverse_match holds which variant of D
8797 if (!t->opcode_modifier.d)
8798 found_reverse_match = 0;
8799 else if (operand_types[0].bitfield.tbyte)
8801 if (t->opcode_modifier.operandconstraint != UGH)
8802 found_reverse_match = Opcode_FloatD;
8804 found_reverse_match = ~0;
8805 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
8806 if ((t->extension_opcode & 4)
8807 && (intel_syntax || intel_mnemonic))
8808 found_reverse_match |= Opcode_FloatR;
8810 else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP))
8812 found_reverse_match = Opcode_VexW;
8813 goto check_operands_345;
8815 else if (is_cpu (t, CpuAPX_F) && i.operands == 3)
8817 found_reverse_match = Opcode_D;
8818 goto check_operands_345;
8820 else if (t->opcode_space != SPACE_BASE
8821 && (t->opcode_space != SPACE_0F
8822 /* MOV to/from CR/DR/TR, as an exception, follow
8823 the base opcode space encoding model. */
8824 || (t->base_opcode | 7) != 0x27))
8825 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
8826 ? Opcode_ExtD : Opcode_SIMD_IntD;
8827 else if (!t->opcode_modifier.commutative)
8828 found_reverse_match = Opcode_D;
8830 found_reverse_match = ~0;
8834 /* Found a forward 2 operand match here. */
8836 switch (t->operands)
8839 overlap4 = operand_type_and (i.types[4], operand_types[4]);
8840 if (!operand_type_match (overlap4, i.types[4])
8841 || !operand_type_register_match (i.types[3],
8846 specific_error = progress (i.error);
8851 overlap3 = operand_type_and (i.types[3], operand_types[3]);
8852 if (!operand_type_match (overlap3, i.types[3])
8853 || ((check_register & 0xa) == 0xa
8854 && !operand_type_register_match (i.types[1],
8858 || ((check_register & 0xc) == 0xc
8859 && !operand_type_register_match (i.types[2],
8864 specific_error = progress (i.error);
8869 overlap2 = operand_type_and (i.types[2], operand_types[2]);
8870 if (!operand_type_match (overlap2, i.types[2])
8871 || ((check_register & 5) == 5
8872 && !operand_type_register_match (i.types[0],
8876 || ((check_register & 6) == 6
8877 && !operand_type_register_match (i.types[1],
8882 specific_error = progress (i.error);
8888 /* Found either forward/reverse 2, 3 or 4 operand match here:
8889 slip through to break. */
8892 /* Check if VEX/EVEX encoding requirements can be satisfied. */
8893 if (VEX_check_encoding (t))
8895 specific_error = progress (i.error);
8899 /* Check if EGPR operands(r16-r31) are valid. */
8900 if (check_EgprOperands (t))
8902 specific_error = progress (i.error);
8906 /* Check if vector operands are valid. */
8907 if (check_VecOperands (t))
8909 specific_error = progress (i.error);
8913 /* Check if APX operands are valid. */
8914 if (check_APX_operands (t))
8916 specific_error = progress (i.error);
8920 /* Check whether to use the shorter VEX encoding for certain insns where
8921 the EVEX encoding comes first in the table. This requires the respective
8922 AVX-* feature to be explicitly enabled.
8924 Most of the respective insns have just a single EVEX and a single VEX
8925 template. The one that's presently different is generated using the
8926 Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter
8927 two of which may fall back to their two corresponding VEX forms. */
8928 j = t->mnem_off != MN_vcvtneps2bf16 ? 1 : 2;
8929 if ((t == current_templates.start || j > 1)
8930 && t->opcode_modifier.disp8memshift
8931 && !t->opcode_modifier.vex
8932 && !need_evex_encoding (t)
8933 && t + j < current_templates.end
8934 && t[j].opcode_modifier.vex)
8937 unsigned int memshift = i.memshift;
8940 cpu = cpu_flags_and (cpu_flags_from_attr (t[j].cpu),
8941 cpu_arch_isa_flags);
8942 if (!cpu_flags_all_zero (&cpu)
8943 && (!i.types[0].bitfield.disp8
8944 || !operand_type_check (i.types[0], disp)
8945 || i.op[0].disps->X_op != O_constant
8946 || fits_in_disp8 (i.op[0].disps->X_add_number)))
8948 specific_error = progress (internal_error);
8952 i.memshift = memshift;
8955 /* If we can optimize a NDD insn to legacy insn, like
8956 add %r16, %r8, %r8 -> add %r16, %r8,
8957 add %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
8958 Note that the semantics have not been changed. */
8961 && i.vec_encoding != vex_encoding_evex
8962 && t + 1 < current_templates.end
8963 && !t[1].opcode_modifier.evex
8964 && t[1].opcode_space <= SPACE_0F38
8965 && t->opcode_modifier.vexvvvv == VexVVVV_DST
8966 && (i.types[i.operands - 1].bitfield.dword
8967 || i.types[i.operands - 1].bitfield.qword))
8969 unsigned int match_dest_op = can_convert_NDD_to_legacy (t);
8971 if (match_dest_op != (unsigned int) ~0)
8974 /* We ensure that the next template has the same input
8975 operands as the original matching template by the first
8976 opernd (ATT). To avoid someone support new NDD insns and
8977 put it in the wrong position. */
8978 overlap0 = operand_type_and (i.types[0],
8979 t[1].operand_types[0]);
8980 if (t->opcode_modifier.d)
8981 overlap1 = operand_type_and (i.types[0],
8982 t[1].operand_types[1]);
8983 if (!operand_type_match (overlap0, i.types[0])
8984 && (!t->opcode_modifier.d
8985 || !operand_type_match (overlap1, i.types[0])))
8989 && (t[1].opcode_space <= SPACE_0F
8990 /* Some non-legacy-map0/1 insns can be shorter when
8991 legacy-encoded and when no REX prefix is required. */
8992 || (!check_EgprOperands (t + 1)
8993 && !check_Rex_required ()
8994 && !i.op[i.operands - 1].regs->reg_type.bitfield.qword)))
8996 if (i.operands > 2 && match_dest_op == i.operands - 3)
8997 swap_2_operands (match_dest_op, i.operands - 2);
9002 specific_error = progress (internal_error);
9009 /* We've found a match; break out of loop. */
9015 if (t == current_templates.end)
9017 /* We found no match. */
9018 i.error = specific_error;
9022 if (!quiet_warnings)
9025 && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)))
9026 as_warn (_("indirect %s without `*'"), insn_name (t));
9028 if (t->opcode_modifier.isprefix
9029 && t->opcode_modifier.mnemonicsize == IGNORESIZE)
9031 /* Warn them that a data or address size prefix doesn't
9032 affect assembly of the next line of code. */
9033 as_warn (_("stand-alone `%s' prefix"), insn_name (t));
9037 /* Copy the template we found. */
9038 install_template (t);
9040 if (addr_prefix_disp != -1)
9041 i.tm.operand_types[addr_prefix_disp]
9042 = operand_types[addr_prefix_disp];
9044 switch (found_reverse_match)
9050 case Opcode_FloatR | Opcode_FloatD:
9051 i.tm.extension_opcode ^= Opcode_FloatR >> 3;
9052 found_reverse_match &= Opcode_FloatD;
9056 /* If we found a reverse match we must alter the opcode direction
9057 bit and clear/flip the regmem modifier one. found_reverse_match
9058 holds bits to change (different for int & float insns). */
9060 i.tm.base_opcode ^= found_reverse_match;
9062 if (i.tm.opcode_space == SPACE_EVEXMAP4)
9065 /* Certain SIMD insns have their load forms specified in the opcode
9066 table, and hence we need to _set_ RegMem instead of clearing it.
9067 We need to avoid setting the bit though on insns like KMOVW. */
9068 i.tm.opcode_modifier.regmem
9069 = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d
9070 && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx
9071 && !i.tm.opcode_modifier.regmem;
9075 i.tm.operand_types[0] = operand_types[i.operands - 1];
9076 i.tm.operand_types[i.operands - 1] = operand_types[0];
9080 /* Only the first two register operands need reversing, alongside
9082 i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
9085 j = i.tm.operand_types[0].bitfield.imm8;
9086 i.tm.operand_types[j] = operand_types[j + 1];
9087 i.tm.operand_types[j + 1] = operand_types[j];
9097 unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0;
9098 unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0;
9100 if (i.seg[op] != NULL && i.seg[op] != reg_es)
9102 as_bad (_("`%s' operand %u must use `%ses' segment"),
9104 intel_syntax ? i.tm.operands - es_op : es_op + 1,
9109 /* There's only ever one segment override allowed per instruction.
9110 This instruction possibly has a legal segment override on the
9111 second operand, so copy the segment to where non-string
9112 instructions store it, allowing common code. */
9113 i.seg[op] = i.seg[1];
9119 process_suffix (void)
9121 bool is_movx = false;
9123 /* If matched instruction specifies an explicit instruction mnemonic
9125 if (i.tm.opcode_modifier.size == SIZE16)
9126 i.suffix = WORD_MNEM_SUFFIX;
9127 else if (i.tm.opcode_modifier.size == SIZE32)
9128 i.suffix = LONG_MNEM_SUFFIX;
9129 else if (i.tm.opcode_modifier.size == SIZE64)
9130 i.suffix = QWORD_MNEM_SUFFIX;
9131 else if (i.reg_operands
9132 && (i.operands > 1 || i.types[0].bitfield.class == Reg)
9133 && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG)
9135 unsigned int numop = i.operands;
9138 is_movx = (i.tm.opcode_space == SPACE_0F
9139 && (i.tm.base_opcode | 8) == 0xbe)
9140 || (i.tm.opcode_space == SPACE_BASE
9141 && i.tm.base_opcode == 0x63
9142 && is_cpu (&i.tm, Cpu64));
9144 /* movsx/movzx want only their source operand considered here, for the
9145 ambiguity checking below. The suffix will be replaced afterwards
9146 to represent the destination (register). */
9147 if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63))
9150 /* crc32 needs REX.W set regardless of suffix / source operand size. */
9151 if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword)
9154 /* If there's no instruction mnemonic suffix we try to invent one
9155 based on GPR operands. */
9158 /* We take i.suffix from the last register operand specified,
9159 Destination register type is more significant than source
9160 register type. crc32 in SSE4.2 prefers source register
9162 unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands;
9165 if (i.tm.operand_types[op].bitfield.instance == InstanceNone
9166 || i.tm.operand_types[op].bitfield.instance == Accum)
9168 if (i.types[op].bitfield.class != Reg)
9170 if (i.types[op].bitfield.byte)
9171 i.suffix = BYTE_MNEM_SUFFIX;
9172 else if (i.types[op].bitfield.word)
9173 i.suffix = WORD_MNEM_SUFFIX;
9174 else if (i.types[op].bitfield.dword)
9175 i.suffix = LONG_MNEM_SUFFIX;
9176 else if (i.types[op].bitfield.qword)
9177 i.suffix = QWORD_MNEM_SUFFIX;
9183 /* As an exception, movsx/movzx silently default to a byte source
9185 if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax)
9186 i.suffix = BYTE_MNEM_SUFFIX;
9188 else if (i.suffix == BYTE_MNEM_SUFFIX)
9190 if (!check_byte_reg ())
9193 else if (i.suffix == LONG_MNEM_SUFFIX)
9195 if (!check_long_reg ())
9198 else if (i.suffix == QWORD_MNEM_SUFFIX)
9200 if (!check_qword_reg ())
9203 else if (i.suffix == WORD_MNEM_SUFFIX)
9205 if (!check_word_reg ())
9208 else if (intel_syntax
9209 && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
9210 /* Do nothing if the instruction is going to ignore the prefix. */
9215 /* Undo the movsx/movzx change done above. */
9218 else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE
9221 i.suffix = stackop_size;
9222 if (stackop_size == LONG_MNEM_SUFFIX)
9224 /* stackop_size is set to LONG_MNEM_SUFFIX for the
9225 .code16gcc directive to support 16-bit mode with
9226 32-bit address. For IRET without a suffix, generate
9227 16-bit IRET (opcode 0xcf) to return from an interrupt
9229 if (i.tm.base_opcode == 0xcf)
9231 i.suffix = WORD_MNEM_SUFFIX;
9232 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
9234 /* Warn about changed behavior for segment register push/pop. */
9235 else if ((i.tm.base_opcode | 1) == 0x07)
9236 as_warn (_("generating 32-bit `%s', unlike earlier gas versions"),
9241 && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE
9242 || i.tm.opcode_modifier.jump == JUMP_BYTE
9243 || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT
9244 || (i.tm.opcode_space == SPACE_0F
9245 && i.tm.base_opcode == 0x01 /* [ls][gi]dt */
9246 && i.tm.extension_opcode <= 3)))
9251 if (!i.tm.opcode_modifier.no_qsuf)
9253 if (i.tm.opcode_modifier.jump == JUMP_BYTE
9254 || i.tm.opcode_modifier.no_lsuf)
9255 i.suffix = QWORD_MNEM_SUFFIX;
9260 if (!i.tm.opcode_modifier.no_lsuf)
9261 i.suffix = LONG_MNEM_SUFFIX;
9264 if (!i.tm.opcode_modifier.no_wsuf)
9265 i.suffix = WORD_MNEM_SUFFIX;
9271 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
9272 /* Also cover lret/retf/iret in 64-bit mode. */
9273 || (flag_code == CODE_64BIT
9274 && !i.tm.opcode_modifier.no_lsuf
9275 && !i.tm.opcode_modifier.no_qsuf))
9276 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
9277 /* Explicit sizing prefixes are assumed to disambiguate insns. */
9278 && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W)
9279 /* Accept FLDENV et al without suffix. */
9280 && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf))
9282 unsigned int suffixes, evex = 0;
9284 suffixes = !i.tm.opcode_modifier.no_bsuf;
9285 if (!i.tm.opcode_modifier.no_wsuf)
9287 if (!i.tm.opcode_modifier.no_lsuf)
9289 if (!i.tm.opcode_modifier.no_ssuf)
9291 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
9294 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
9295 also suitable for AT&T syntax mode, it was requested that this be
9296 restricted to just Intel syntax. */
9297 if (intel_syntax && is_any_vex_encoding (&i.tm)
9298 && !i.broadcast.type && !i.broadcast.bytes)
9302 for (op = 0; op < i.tm.operands; ++op)
9304 if (vector_size < VSZ512)
9306 i.tm.operand_types[op].bitfield.zmmword = 0;
9307 if (vector_size < VSZ256)
9309 i.tm.operand_types[op].bitfield.ymmword = 0;
9310 if (i.tm.operand_types[op].bitfield.xmmword
9311 && i.tm.opcode_modifier.evex == EVEXDYN)
9312 i.tm.opcode_modifier.evex = EVEX128;
9314 else if (i.tm.operand_types[op].bitfield.ymmword
9315 && !i.tm.operand_types[op].bitfield.xmmword
9316 && i.tm.opcode_modifier.evex == EVEXDYN)
9317 i.tm.opcode_modifier.evex = EVEX256;
9319 else if (i.tm.opcode_modifier.evex
9320 && !cpu_arch_flags.bitfield.cpuavx512vl)
9322 if (i.tm.operand_types[op].bitfield.ymmword)
9323 i.tm.operand_types[op].bitfield.xmmword = 0;
9324 if (i.tm.operand_types[op].bitfield.zmmword)
9325 i.tm.operand_types[op].bitfield.ymmword = 0;
9326 if (i.tm.opcode_modifier.evex == EVEXDYN)
9327 i.tm.opcode_modifier.evex = EVEX512;
9330 if (i.tm.operand_types[op].bitfield.xmmword
9331 + i.tm.operand_types[op].bitfield.ymmword
9332 + i.tm.operand_types[op].bitfield.zmmword < 2)
9335 /* Any properly sized operand disambiguates the insn. */
9336 if (i.types[op].bitfield.xmmword
9337 || i.types[op].bitfield.ymmword
9338 || i.types[op].bitfield.zmmword)
9340 suffixes &= ~(7 << 6);
9345 if ((i.flags[op] & Operand_Mem)
9346 && i.tm.operand_types[op].bitfield.unspecified)
9348 if (i.tm.operand_types[op].bitfield.xmmword)
9350 if (i.tm.operand_types[op].bitfield.ymmword)
9352 if (i.tm.operand_types[op].bitfield.zmmword)
9354 if (i.tm.opcode_modifier.evex)
9360 /* Are multiple suffixes / operand sizes allowed? */
9361 if (suffixes & (suffixes - 1))
9364 && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE
9365 || operand_check == check_error))
9367 as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm));
9370 if (operand_check == check_error)
9372 as_bad (_("no instruction mnemonic suffix given and "
9373 "no register operands; can't size `%s'"), insn_name (&i.tm));
9376 if (operand_check == check_warning)
9377 as_warn (_("%s; using default for `%s'"),
9379 ? _("ambiguous operand size")
9380 : _("no instruction mnemonic suffix given and "
9381 "no register operands"),
9384 if (i.tm.opcode_modifier.floatmf)
9385 i.suffix = SHORT_MNEM_SUFFIX;
9387 /* handled below */;
9389 i.tm.opcode_modifier.evex = evex;
9390 else if (flag_code == CODE_16BIT)
9391 i.suffix = WORD_MNEM_SUFFIX;
9392 else if (!i.tm.opcode_modifier.no_lsuf)
9393 i.suffix = LONG_MNEM_SUFFIX;
9395 i.suffix = QWORD_MNEM_SUFFIX;
9401 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
9402 In AT&T syntax, if there is no suffix (warned about above), the default
9403 will be byte extension. */
9404 if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
9405 i.tm.base_opcode |= 1;
9407 /* For further processing, the suffix should represent the destination
9408 (register). This is already the case when one was used with
9409 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
9410 no suffix to begin with. */
9411 if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix)
9413 if (i.types[1].bitfield.word)
9414 i.suffix = WORD_MNEM_SUFFIX;
9415 else if (i.types[1].bitfield.qword)
9416 i.suffix = QWORD_MNEM_SUFFIX;
9418 i.suffix = LONG_MNEM_SUFFIX;
9420 i.tm.opcode_modifier.w = 0;
9424 if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3)
9425 i.short_form = (i.tm.operand_types[0].bitfield.class == Reg)
9426 != (i.tm.operand_types[1].bitfield.class == Reg);
9428 /* Change the opcode based on the operand size given by i.suffix. */
9431 /* Size floating point instruction. */
9432 case LONG_MNEM_SUFFIX:
9433 if (i.tm.opcode_modifier.floatmf)
9435 i.tm.base_opcode ^= 4;
9439 case WORD_MNEM_SUFFIX:
9440 case QWORD_MNEM_SUFFIX:
9441 /* It's not a byte, select word/dword operation. */
9442 if (i.tm.opcode_modifier.w)
9445 i.tm.base_opcode |= 8;
9447 i.tm.base_opcode |= 1;
9450 case SHORT_MNEM_SUFFIX:
9451 /* Now select between word & dword operations via the operand
9452 size prefix, except for instructions that will ignore this
9454 if (i.suffix != QWORD_MNEM_SUFFIX
9455 && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE
9456 && !i.tm.opcode_modifier.floatmf
9457 && (!is_any_vex_encoding (&i.tm)
9458 || i.tm.opcode_space == SPACE_EVEXMAP4)
9459 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
9460 || (flag_code == CODE_64BIT
9461 && i.tm.opcode_modifier.jump == JUMP_BYTE)))
9463 unsigned int prefix = DATA_PREFIX_OPCODE;
9465 if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */
9466 prefix = ADDR_PREFIX_OPCODE;
9468 /* The DATA PREFIX of EVEX promoted from legacy APX instructions
9469 needs to be adjusted. */
9470 if (i.tm.opcode_space == SPACE_EVEXMAP4)
9472 gas_assert (!i.tm.opcode_modifier.opcodeprefix);
9473 i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
9475 else if (!add_prefix (prefix))
9479 /* Set mode64 for an operand. */
9480 if (i.suffix == QWORD_MNEM_SUFFIX
9481 && flag_code == CODE_64BIT
9482 && !i.tm.opcode_modifier.norex64
9483 && !i.tm.opcode_modifier.vexw
9484 /* Special case for xchg %rax,%rax. It is NOP and doesn't
9486 && ! (i.operands == 2
9487 && i.tm.base_opcode == 0x90
9488 && i.tm.opcode_space == SPACE_BASE
9489 && i.types[0].bitfield.instance == Accum
9490 && i.types[0].bitfield.qword
9491 && i.types[1].bitfield.instance == Accum))
9497 /* Select word/dword/qword operation with explicit data sizing prefix
9498 when there are no suitable register operands. */
9499 if (i.tm.opcode_modifier.w
9500 && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W))
9502 || (i.reg_operands == 1
9504 && (i.tm.operand_types[0].bitfield.instance == RegC
9506 || i.tm.operand_types[0].bitfield.instance == RegD
9507 || i.tm.operand_types[1].bitfield.instance == RegD
9508 || i.tm.mnem_off == MN_crc32))))
9509 i.tm.base_opcode |= 1;
9513 if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG)
9515 gas_assert (!i.suffix);
9516 gas_assert (i.reg_operands);
9518 if (i.tm.operand_types[0].bitfield.instance == Accum
9521 /* The address size override prefix changes the size of the
9523 if (flag_code == CODE_64BIT
9524 && i.op[0].regs->reg_type.bitfield.word)
9526 as_bad (_("16-bit addressing unavailable for `%s'"),
9531 if ((flag_code == CODE_32BIT
9532 ? i.op[0].regs->reg_type.bitfield.word
9533 : i.op[0].regs->reg_type.bitfield.dword)
9534 && !add_prefix (ADDR_PREFIX_OPCODE))
9539 /* Check invalid register operand when the address size override
9540 prefix changes the size of register operands. */
9542 enum { need_word, need_dword, need_qword } need;
9544 /* Check the register operand for the address size prefix if
9545 the memory operand has no real registers, like symbol, DISP
9546 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
9547 if (i.mem_operands == 1
9548 && i.reg_operands == 1
9550 && i.types[1].bitfield.class == Reg
9551 && (flag_code == CODE_32BIT
9552 ? i.op[1].regs->reg_type.bitfield.word
9553 : i.op[1].regs->reg_type.bitfield.dword)
9554 && ((i.base_reg == NULL && i.index_reg == NULL)
9555 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9556 || (x86_elf_abi == X86_64_X32_ABI
9558 && i.base_reg->reg_num == RegIP
9559 && i.base_reg->reg_type.bitfield.qword))
9563 && !add_prefix (ADDR_PREFIX_OPCODE))
9566 if (flag_code == CODE_32BIT)
9567 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
9568 else if (i.prefix[ADDR_PREFIX])
9571 need = flag_code == CODE_64BIT ? need_qword : need_word;
9573 for (op = 0; op < i.operands; op++)
9575 if (i.types[op].bitfield.class != Reg)
9581 if (i.op[op].regs->reg_type.bitfield.word)
9585 if (i.op[op].regs->reg_type.bitfield.dword)
9589 if (i.op[op].regs->reg_type.bitfield.qword)
9594 as_bad (_("invalid register operand size for `%s'"),
9605 check_byte_reg (void)
9609 for (op = i.operands; --op >= 0;)
9611 /* Skip non-register operands. */
9612 if (i.types[op].bitfield.class != Reg)
9615 /* If this is an eight bit register, it's OK. If it's the 16 or
9616 32 bit version of an eight bit register, we will just use the
9617 low portion, and that's OK too. */
9618 if (i.types[op].bitfield.byte)
9621 /* I/O port address operands are OK too. */
9622 if (i.tm.operand_types[op].bitfield.instance == RegD
9623 && i.tm.operand_types[op].bitfield.word)
9626 /* crc32 only wants its source operand checked here. */
9627 if (i.tm.mnem_off == MN_crc32 && op != 0)
9630 /* Any other register is bad. */
9631 as_bad (_("`%s%s' not allowed with `%s%c'"),
9632 register_prefix, i.op[op].regs->reg_name,
9633 insn_name (&i.tm), i.suffix);
9640 check_long_reg (void)
9644 for (op = i.operands; --op >= 0;)
9645 /* Skip non-register operands. */
9646 if (i.types[op].bitfield.class != Reg)
9648 /* Reject eight bit registers, except where the template requires
9649 them. (eg. movzb) */
9650 else if (i.types[op].bitfield.byte
9651 && (i.tm.operand_types[op].bitfield.class == Reg
9652 || i.tm.operand_types[op].bitfield.instance == Accum)
9653 && (i.tm.operand_types[op].bitfield.word
9654 || i.tm.operand_types[op].bitfield.dword))
9656 as_bad (_("`%s%s' not allowed with `%s%c'"),
9658 i.op[op].regs->reg_name,
9663 /* Error if the e prefix on a general reg is missing, or if the r
9664 prefix on a general reg is present. */
9665 else if ((i.types[op].bitfield.word
9666 || i.types[op].bitfield.qword)
9667 && (i.tm.operand_types[op].bitfield.class == Reg
9668 || i.tm.operand_types[op].bitfield.instance == Accum)
9669 && i.tm.operand_types[op].bitfield.dword)
9671 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9672 register_prefix, i.op[op].regs->reg_name,
9680 check_qword_reg (void)
9684 for (op = i.operands; --op >= 0; )
9685 /* Skip non-register operands. */
9686 if (i.types[op].bitfield.class != Reg)
9688 /* Reject eight bit registers, except where the template requires
9689 them. (eg. movzb) */
9690 else if (i.types[op].bitfield.byte
9691 && (i.tm.operand_types[op].bitfield.class == Reg
9692 || i.tm.operand_types[op].bitfield.instance == Accum)
9693 && (i.tm.operand_types[op].bitfield.word
9694 || i.tm.operand_types[op].bitfield.dword
9695 || i.tm.operand_types[op].bitfield.qword))
9697 as_bad (_("`%s%s' not allowed with `%s%c'"),
9699 i.op[op].regs->reg_name,
9704 /* Error if the r prefix on a general reg is missing. */
9705 else if ((i.types[op].bitfield.word
9706 || i.types[op].bitfield.dword)
9707 && (i.tm.operand_types[op].bitfield.class == Reg
9708 || i.tm.operand_types[op].bitfield.instance == Accum)
9709 && i.tm.operand_types[op].bitfield.qword)
9711 /* Prohibit these changes in the 64bit mode, since the
9712 lowering is more complicated. */
9713 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9714 register_prefix, i.op[op].regs->reg_name, i.suffix);
9721 check_word_reg (void)
9724 for (op = i.operands; --op >= 0;)
9725 /* Skip non-register operands. */
9726 if (i.types[op].bitfield.class != Reg)
9728 /* Reject eight bit registers, except where the template requires
9729 them. (eg. movzb) */
9730 else if (i.types[op].bitfield.byte
9731 && (i.tm.operand_types[op].bitfield.class == Reg
9732 || i.tm.operand_types[op].bitfield.instance == Accum)
9733 && (i.tm.operand_types[op].bitfield.word
9734 || i.tm.operand_types[op].bitfield.dword))
9736 as_bad (_("`%s%s' not allowed with `%s%c'"),
9738 i.op[op].regs->reg_name,
9743 /* Error if the e or r prefix on a general reg is present. */
9744 else if ((i.types[op].bitfield.dword
9745 || i.types[op].bitfield.qword)
9746 && (i.tm.operand_types[op].bitfield.class == Reg
9747 || i.tm.operand_types[op].bitfield.instance == Accum)
9748 && i.tm.operand_types[op].bitfield.word)
9750 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
9751 register_prefix, i.op[op].regs->reg_name,
9759 update_imm (unsigned int j)
9761 i386_operand_type overlap = i.types[j];
9763 if (i.tm.operand_types[j].bitfield.imm8
9764 && i.tm.operand_types[j].bitfield.imm8s
9765 && overlap.bitfield.imm8 && overlap.bitfield.imm8s)
9767 /* This combination is used on 8-bit immediates where e.g. $~0 is
9768 desirable to permit. We're past operand type matching, so simply
9769 put things back in the shape they were before introducing the
9770 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
9771 overlap.bitfield.imm8s = 0;
9774 if (overlap.bitfield.imm8
9775 + overlap.bitfield.imm8s
9776 + overlap.bitfield.imm16
9777 + overlap.bitfield.imm32
9778 + overlap.bitfield.imm32s
9779 + overlap.bitfield.imm64 > 1)
9781 static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } };
9782 static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } };
9783 static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } };
9784 static const i386_operand_type imm16_32 = { .bitfield =
9785 { .imm16 = 1, .imm32 = 1 }
9787 static const i386_operand_type imm16_32s = { .bitfield =
9788 { .imm16 = 1, .imm32s = 1 }
9790 static const i386_operand_type imm16_32_32s = { .bitfield =
9791 { .imm16 = 1, .imm32 = 1, .imm32s = 1 }
9796 i386_operand_type temp;
9798 operand_type_set (&temp, 0);
9799 if (i.suffix == BYTE_MNEM_SUFFIX)
9801 temp.bitfield.imm8 = overlap.bitfield.imm8;
9802 temp.bitfield.imm8s = overlap.bitfield.imm8s;
9804 else if (i.suffix == WORD_MNEM_SUFFIX)
9805 temp.bitfield.imm16 = overlap.bitfield.imm16;
9806 else if (i.suffix == QWORD_MNEM_SUFFIX)
9808 temp.bitfield.imm64 = overlap.bitfield.imm64;
9809 temp.bitfield.imm32s = overlap.bitfield.imm32s;
9812 temp.bitfield.imm32 = overlap.bitfield.imm32;
9815 else if (operand_type_equal (&overlap, &imm16_32_32s)
9816 || operand_type_equal (&overlap, &imm16_32)
9817 || operand_type_equal (&overlap, &imm16_32s))
9819 if ((flag_code == CODE_16BIT)
9820 ^ (i.prefix[DATA_PREFIX] != 0 && !(i.prefix[REX_PREFIX] & REX_W)))
9825 else if (i.prefix[REX_PREFIX] & REX_W)
9826 overlap = operand_type_and (overlap, imm32s);
9827 else if (i.prefix[DATA_PREFIX])
9828 overlap = operand_type_and (overlap,
9829 flag_code != CODE_16BIT ? imm16 : imm32);
9830 if (overlap.bitfield.imm8
9831 + overlap.bitfield.imm8s
9832 + overlap.bitfield.imm16
9833 + overlap.bitfield.imm32
9834 + overlap.bitfield.imm32s
9835 + overlap.bitfield.imm64 != 1)
9837 as_bad (_("no instruction mnemonic suffix given; "
9838 "can't determine immediate size"));
9842 i.types[j] = overlap;
9852 /* Update the first 2 immediate operands. */
9853 n = i.operands > 2 ? 2 : i.operands;
9856 for (j = 0; j < n; j++)
9857 if (update_imm (j) == 0)
9860 /* The 3rd operand can't be immediate operand. */
9861 gas_assert (operand_type_check (i.types[2], imm) == 0);
9867 static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit,
9870 if (r->reg_flags & RegRex)
9872 if (i.rex & rex_bit)
9873 as_bad (_("same type of prefix used twice"));
9876 else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier)
9878 gas_assert (i.vex.register_specifier == r);
9879 i.vex.register_specifier += 8;
9882 if (r->reg_flags & RegVRex)
9885 if (r->reg_flags & RegRex2)
9890 set_rex_rex2 (const reg_entry *r, unsigned int rex_bit)
9892 if ((r->reg_flags & RegRex) != 0)
9894 if ((r->reg_flags & RegRex2) != 0)
9899 process_operands (void)
9901 /* Default segment register this instruction will use for memory
9902 accesses. 0 means unknown. This is only for optimizing out
9903 unnecessary segment overrides. */
9904 const reg_entry *default_seg = NULL;
9906 for (unsigned int j = 0; j < i.operands; j++)
9907 if (i.types[j].bitfield.instance != InstanceNone)
9910 if (i.tm.opcode_modifier.sse2avx)
9912 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
9914 i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B);
9915 i.prefix[REX_PREFIX] = 0;
9918 /* ImmExt should be processed after SSE2AVX. */
9919 else if (i.tm.opcode_modifier.immext)
9922 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
9923 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
9924 new destination operand here, while converting the source one to register
9926 if (i.tm.mnem_off == MN_tilezero)
9928 i.op[1].regs = i.op[0].regs;
9929 i.op[0].regs -= i.op[0].regs->reg_num;
9930 i.types[1] = i.types[0];
9931 i.tm.operand_types[1] = i.tm.operand_types[0];
9932 i.flags[1] = i.flags[0];
9938 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
9940 static const i386_operand_type regxmm = {
9941 .bitfield = { .class = RegSIMD, .xmmword = 1 }
9943 unsigned int dupl = i.operands;
9944 unsigned int dest = dupl - 1;
9947 /* The destination must be an xmm register. */
9948 gas_assert (i.reg_operands
9949 && MAX_OPERANDS > dupl
9950 && operand_type_equal (&i.types[dest], ®xmm));
9952 if (i.tm.operand_types[0].bitfield.instance == Accum
9953 && i.tm.operand_types[0].bitfield.xmmword)
9955 /* Keep xmm0 for instructions with VEX prefix and 3
9957 i.tm.operand_types[0].bitfield.instance = InstanceNone;
9958 i.tm.operand_types[0].bitfield.class = RegSIMD;
9963 if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0)
9965 gas_assert ((MAX_OPERANDS - 1) > dupl);
9967 /* Add the implicit xmm0 for instructions with VEX prefix
9969 for (j = i.operands; j > 0; j--)
9971 i.op[j] = i.op[j - 1];
9972 i.types[j] = i.types[j - 1];
9973 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
9974 i.flags[j] = i.flags[j - 1];
9977 = (const reg_entry *) str_hash_find (reg_hash, "xmm0");
9978 i.types[0] = regxmm;
9979 i.tm.operand_types[0] = regxmm;
9982 i.reg_operands += 2;
9987 i.op[dupl] = i.op[dest];
9988 i.types[dupl] = i.types[dest];
9989 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
9990 i.flags[dupl] = i.flags[dest];
9999 i.op[dupl] = i.op[dest];
10000 i.types[dupl] = i.types[dest];
10001 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
10002 i.flags[dupl] = i.flags[dest];
10005 if (i.tm.opcode_modifier.immext)
10008 else if (i.tm.operand_types[0].bitfield.instance == Accum
10009 && i.tm.opcode_modifier.modrm)
10013 for (j = 1; j < i.operands; j++)
10015 i.op[j - 1] = i.op[j];
10016 i.types[j - 1] = i.types[j];
10018 /* We need to adjust fields in i.tm since they are used by
10019 build_modrm_byte. */
10020 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
10022 i.flags[j - 1] = i.flags[j];
10025 /* No adjustment to i.reg_operands: This was already done at the top
10026 of the function. */
10030 else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP)
10032 unsigned int regnum, first_reg_in_group, last_reg_in_group;
10034 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10035 gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD);
10036 regnum = register_number (i.op[1].regs);
10037 first_reg_in_group = regnum & ~3;
10038 last_reg_in_group = first_reg_in_group + 3;
10039 if (regnum != first_reg_in_group)
10040 as_warn (_("source register `%s%s' implicitly denotes"
10041 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
10042 register_prefix, i.op[1].regs->reg_name,
10043 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
10044 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
10045 insn_name (&i.tm));
10047 else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE)
10049 /* The imul $imm, %reg instruction is converted into
10050 imul $imm, %reg, %reg, and the clr %reg instruction
10051 is converted into xor %reg, %reg. */
10053 unsigned int first_reg_op;
10055 if (operand_type_check (i.types[0], reg))
10059 /* Pretend we saw the extra register operand. */
10060 gas_assert (i.reg_operands == 1
10061 && i.op[first_reg_op + 1].regs == 0);
10062 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
10063 i.types[first_reg_op + 1] = i.types[first_reg_op];
10068 if (i.tm.opcode_modifier.modrm)
10070 /* The opcode is completed (modulo i.tm.extension_opcode which
10071 must be put into the modrm byte). Now, we make the modrm and
10072 index base bytes based on all the info we've collected. */
10074 default_seg = build_modrm_byte ();
10076 if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH)
10078 /* Warn about some common errors, but press on regardless. */
10079 if (i.operands == 2)
10081 /* Reversed arguments on faddp or fmulp. */
10082 as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm),
10083 register_prefix, i.op[!intel_syntax].regs->reg_name,
10084 register_prefix, i.op[intel_syntax].regs->reg_name);
10086 else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE)
10088 /* Extraneous `l' suffix on fp insn. */
10089 as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm),
10090 register_prefix, i.op[0].regs->reg_name);
10094 else if (i.types[0].bitfield.class == SReg && !dot_insn ())
10096 if (flag_code != CODE_64BIT
10097 ? i.tm.base_opcode == POP_SEG_SHORT
10098 && i.op[0].regs->reg_num == 1
10099 : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff)
10100 && i.op[0].regs->reg_num < 4)
10102 as_bad (_("you can't `%s %s%s'"),
10103 insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name);
10106 if (i.op[0].regs->reg_num > 3
10107 && i.tm.opcode_space == SPACE_BASE )
10109 i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff;
10110 i.tm.opcode_space = SPACE_0F;
10112 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
10114 else if (i.tm.opcode_space == SPACE_BASE
10115 && (i.tm.base_opcode & ~3) == MOV_AX_DISP32)
10117 default_seg = reg_ds;
10119 else if (i.tm.opcode_modifier.isstring)
10121 /* For the string instructions that allow a segment override
10122 on one of their operands, the default segment is ds. */
10123 default_seg = reg_ds;
10125 else if (i.short_form)
10127 /* The register operand is in the 1st or 2nd non-immediate operand. */
10128 const reg_entry *r = i.op[i.imm_operands].regs;
10131 && r->reg_type.bitfield.instance == Accum
10132 && i.op[i.imm_operands + 1].regs)
10133 r = i.op[i.imm_operands + 1].regs;
10134 /* Register goes in low 3 bits of opcode. */
10135 i.tm.base_opcode |= r->reg_num;
10136 set_rex_vrex (r, REX_B, false);
10138 if (dot_insn () && i.reg_operands == 2)
10140 gas_assert (is_any_vex_encoding (&i.tm)
10141 || i.vec_encoding != vex_encoding_default);
10142 i.vex.register_specifier = i.op[i.operands - 1].regs;
10145 else if (i.reg_operands == 1
10146 && !i.flags[i.operands - 1]
10147 && i.tm.operand_types[i.operands - 1].bitfield.instance
10150 gas_assert (is_any_vex_encoding (&i.tm)
10151 || i.vec_encoding != vex_encoding_default);
10152 i.vex.register_specifier = i.op[i.operands - 1].regs;
10155 if ((i.seg[0] || i.prefix[SEG_PREFIX])
10156 && i.tm.mnem_off == MN_lea)
10158 if (!quiet_warnings)
10159 as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm));
10160 if (optimize && !i.no_optimize)
10163 i.prefix[SEG_PREFIX] = 0;
10167 /* If a segment was explicitly specified, and the specified segment
10168 is neither the default nor the one already recorded from a prefix,
10169 use an opcode prefix to select it. If we never figured out what
10170 the default segment is, then default_seg will be zero at this
10171 point, and the specified segment prefix will always be used. */
10173 && i.seg[0] != default_seg
10174 && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX])
10176 if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num]))
10182 static const reg_entry *
10183 build_modrm_byte (void)
10185 const reg_entry *default_seg = NULL;
10186 unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext
10187 /* Compensate for kludge in md_assemble(). */
10188 + i.tm.operand_types[0].bitfield.imm1;
10189 unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext;
10190 unsigned int v, op, reg_slot = ~0;
10192 /* Accumulator (in particular %st), shift count (%cl), and alike need
10193 to be skipped just like immediate operands do. */
10194 if (i.tm.operand_types[source].bitfield.instance)
10196 while (i.tm.operand_types[dest].bitfield.instance)
10199 for (op = source; op < i.operands; ++op)
10200 if (i.tm.operand_types[op].bitfield.baseindex)
10203 if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4)
10207 /* There are 2 kinds of instructions:
10208 1. 5 operands: 4 register operands or 3 register operands
10209 plus 1 memory operand plus one Imm4 operand, VexXDS, and
10210 VexW0 or VexW1. The destination must be either XMM, YMM or
10212 2. 4 operands: 4 register operands or 3 register operands
10213 plus 1 memory operand, with VexXDS.
10214 3. Other equivalent combinations when coming from s_insn(). */
10215 gas_assert (i.tm.opcode_modifier.vexvvvv
10216 && i.tm.opcode_modifier.vexw);
10217 gas_assert (dot_insn ()
10218 || i.tm.operand_types[dest].bitfield.class == RegSIMD);
10220 /* Of the first two non-immediate operands the one with the template
10221 not allowing for a memory one is encoded in the immediate operand. */
10223 reg_slot = source + 1;
10225 reg_slot = source++;
10229 gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD);
10230 gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex));
10233 gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone);
10235 if (i.imm_operands == 0)
10237 /* When there is no immediate operand, generate an 8bit
10238 immediate operand to encode the first operand. */
10239 exp = &im_expressions[i.imm_operands++];
10240 i.op[i.operands].imms = exp;
10241 i.types[i.operands].bitfield.imm8 = 1;
10244 exp->X_op = O_constant;
10248 gas_assert (i.imm_operands == 1);
10249 gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
10250 gas_assert (!i.tm.opcode_modifier.immext);
10252 /* Turn on Imm8 again so that output_imm will generate it. */
10253 i.types[0].bitfield.imm8 = 1;
10255 exp = i.op[0].imms;
10257 exp->X_add_number |= register_number (i.op[reg_slot].regs)
10258 << (3 + !(i.tm.opcode_modifier.evex
10259 || i.vec_encoding == vex_encoding_evex));
10262 if (i.tm.opcode_modifier.vexvvvv == VexVVVV_DST)
10269 for (v = source + 1; v < dest; ++v)
10275 if (i.tm.extension_opcode != None)
10277 if (dest != source)
10281 gas_assert (source < dest);
10282 if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES
10285 unsigned int tmp = source;
10291 if (v < MAX_OPERANDS)
10293 gas_assert (i.tm.opcode_modifier.vexvvvv);
10294 i.vex.register_specifier = i.op[v].regs;
10297 if (op < i.operands)
10299 if (i.mem_operands)
10301 unsigned int fake_zero_displacement = 0;
10303 gas_assert (i.flags[op] & Operand_Mem);
10305 if (i.tm.opcode_modifier.sib)
10307 /* The index register of VSIB shouldn't be RegIZ. */
10308 if (i.tm.opcode_modifier.sib != SIBMEM
10309 && i.index_reg->reg_num == RegIZ)
10312 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10315 i.sib.base = NO_BASE_REGISTER;
10316 i.sib.scale = i.log2_scale_factor;
10317 i.types[op] = operand_type_and_not (i.types[op], anydisp);
10318 i.types[op].bitfield.disp32 = 1;
10321 /* Since the mandatory SIB always has index register, so
10322 the code logic remains unchanged. The non-mandatory SIB
10323 without index register is allowed and will be handled
10327 if (i.index_reg->reg_num == RegIZ)
10328 i.sib.index = NO_INDEX_REGISTER;
10330 i.sib.index = i.index_reg->reg_num;
10331 set_rex_vrex (i.index_reg, REX_X, false);
10335 default_seg = reg_ds;
10337 if (i.base_reg == 0)
10340 if (!i.disp_operands)
10341 fake_zero_displacement = 1;
10342 if (i.index_reg == 0)
10344 /* Both check for VSIB and mandatory non-vector SIB. */
10345 gas_assert (!i.tm.opcode_modifier.sib
10346 || i.tm.opcode_modifier.sib == SIBMEM);
10347 /* Operand is just <disp> */
10348 i.types[op] = operand_type_and_not (i.types[op], anydisp);
10349 if (flag_code == CODE_64BIT)
10351 /* 64bit mode overwrites the 32bit absolute
10352 addressing by RIP relative addressing and
10353 absolute addressing is encoded by one of the
10354 redundant SIB forms. */
10355 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10356 i.sib.base = NO_BASE_REGISTER;
10357 i.sib.index = NO_INDEX_REGISTER;
10358 i.types[op].bitfield.disp32 = 1;
10360 else if ((flag_code == CODE_16BIT)
10361 ^ (i.prefix[ADDR_PREFIX] != 0))
10363 i.rm.regmem = NO_BASE_REGISTER_16;
10364 i.types[op].bitfield.disp16 = 1;
10368 i.rm.regmem = NO_BASE_REGISTER;
10369 i.types[op].bitfield.disp32 = 1;
10372 else if (!i.tm.opcode_modifier.sib)
10374 /* !i.base_reg && i.index_reg */
10375 if (i.index_reg->reg_num == RegIZ)
10376 i.sib.index = NO_INDEX_REGISTER;
10378 i.sib.index = i.index_reg->reg_num;
10379 i.sib.base = NO_BASE_REGISTER;
10380 i.sib.scale = i.log2_scale_factor;
10381 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10382 i.types[op] = operand_type_and_not (i.types[op], anydisp);
10383 i.types[op].bitfield.disp32 = 1;
10384 set_rex_rex2 (i.index_reg, REX_X);
10387 /* RIP addressing for 64bit mode. */
10388 else if (i.base_reg->reg_num == RegIP)
10390 gas_assert (!i.tm.opcode_modifier.sib);
10391 i.rm.regmem = NO_BASE_REGISTER;
10392 i.types[op].bitfield.disp8 = 0;
10393 i.types[op].bitfield.disp16 = 0;
10394 i.types[op].bitfield.disp32 = 1;
10395 i.types[op].bitfield.disp64 = 0;
10396 i.flags[op] |= Operand_PCrel;
10397 if (! i.disp_operands)
10398 fake_zero_displacement = 1;
10400 else if (i.base_reg->reg_type.bitfield.word)
10402 gas_assert (!i.tm.opcode_modifier.sib);
10403 switch (i.base_reg->reg_num)
10405 case 3: /* (%bx) */
10406 if (i.index_reg == 0)
10408 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
10409 i.rm.regmem = i.index_reg->reg_num - 6;
10411 case 5: /* (%bp) */
10412 default_seg = reg_ss;
10413 if (i.index_reg == 0)
10416 if (operand_type_check (i.types[op], disp) == 0)
10418 /* fake (%bp) into 0(%bp) */
10419 if (i.disp_encoding == disp_encoding_16bit)
10420 i.types[op].bitfield.disp16 = 1;
10422 i.types[op].bitfield.disp8 = 1;
10423 fake_zero_displacement = 1;
10426 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
10427 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
10429 default: /* (%si) -> 4 or (%di) -> 5 */
10430 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
10432 if (!fake_zero_displacement
10433 && !i.disp_operands
10434 && i.disp_encoding)
10436 fake_zero_displacement = 1;
10437 if (i.disp_encoding == disp_encoding_8bit)
10438 i.types[op].bitfield.disp8 = 1;
10440 i.types[op].bitfield.disp16 = 1;
10442 i.rm.mode = mode_from_disp_size (i.types[op]);
10444 else /* i.base_reg and 32/64 bit mode */
10446 if (operand_type_check (i.types[op], disp))
10448 i.types[op].bitfield.disp16 = 0;
10449 i.types[op].bitfield.disp64 = 0;
10450 i.types[op].bitfield.disp32 = 1;
10453 if (!i.tm.opcode_modifier.sib)
10454 i.rm.regmem = i.base_reg->reg_num;
10455 set_rex_rex2 (i.base_reg, REX_B);
10456 i.sib.base = i.base_reg->reg_num;
10457 /* x86-64 ignores REX prefix bit here to avoid decoder
10459 if (!(i.base_reg->reg_flags & RegRex)
10460 && (i.base_reg->reg_num == EBP_REG_NUM
10461 || i.base_reg->reg_num == ESP_REG_NUM))
10462 default_seg = reg_ss;
10463 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
10465 fake_zero_displacement = 1;
10466 if (i.disp_encoding == disp_encoding_32bit)
10467 i.types[op].bitfield.disp32 = 1;
10469 i.types[op].bitfield.disp8 = 1;
10471 i.sib.scale = i.log2_scale_factor;
10472 if (i.index_reg == 0)
10474 /* Only check for VSIB. */
10475 gas_assert (i.tm.opcode_modifier.sib != VECSIB128
10476 && i.tm.opcode_modifier.sib != VECSIB256
10477 && i.tm.opcode_modifier.sib != VECSIB512);
10479 /* <disp>(%esp) becomes two byte modrm with no index
10480 register. We've already stored the code for esp
10481 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
10482 Any base register besides %esp will not use the
10483 extra modrm byte. */
10484 i.sib.index = NO_INDEX_REGISTER;
10486 else if (!i.tm.opcode_modifier.sib)
10488 if (i.index_reg->reg_num == RegIZ)
10489 i.sib.index = NO_INDEX_REGISTER;
10491 i.sib.index = i.index_reg->reg_num;
10492 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
10493 set_rex_rex2 (i.index_reg, REX_X);
10496 if (i.disp_operands
10497 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
10498 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
10502 if (!fake_zero_displacement
10503 && !i.disp_operands
10504 && i.disp_encoding)
10506 fake_zero_displacement = 1;
10507 if (i.disp_encoding == disp_encoding_8bit)
10508 i.types[op].bitfield.disp8 = 1;
10510 i.types[op].bitfield.disp32 = 1;
10512 i.rm.mode = mode_from_disp_size (i.types[op]);
10516 if (fake_zero_displacement)
10518 /* Fakes a zero displacement assuming that i.types[op]
10519 holds the correct displacement size. */
10522 gas_assert (i.op[op].disps == 0);
10523 exp = &disp_expressions[i.disp_operands++];
10524 i.op[op].disps = exp;
10525 exp->X_op = O_constant;
10526 exp->X_add_number = 0;
10527 exp->X_add_symbol = (symbolS *) 0;
10528 exp->X_op_symbol = (symbolS *) 0;
10534 i.rm.regmem = i.op[op].regs->reg_num;
10535 set_rex_vrex (i.op[op].regs, REX_B, false);
10546 if (!i.tm.opcode_modifier.regmem)
10548 gas_assert (source < MAX_OPERANDS);
10549 i.rm.regmem = i.op[source].regs->reg_num;
10550 set_rex_vrex (i.op[source].regs, REX_B,
10551 dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx);
10556 gas_assert (dest < MAX_OPERANDS);
10557 i.rm.regmem = i.op[dest].regs->reg_num;
10558 set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx);
10563 /* Fill in i.rm.reg field with extension opcode (if any) or the
10564 appropriate register. */
10565 if (i.tm.extension_opcode != None)
10566 i.rm.reg = i.tm.extension_opcode;
10567 else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS)
10569 i.rm.reg = i.op[dest].regs->reg_num;
10570 set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx);
10574 gas_assert (source < MAX_OPERANDS);
10575 i.rm.reg = i.op[source].regs->reg_num;
10576 set_rex_vrex (i.op[source].regs, REX_R, false);
10579 if (flag_code != CODE_64BIT && (i.rex & REX_R))
10581 gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR);
10583 add_prefix (LOCK_PREFIX_OPCODE);
10586 return default_seg;
10590 frag_opcode_byte (unsigned char byte)
10592 if (now_seg != absolute_section)
10593 FRAG_APPEND_1_CHAR (byte);
10595 ++abs_section_offset;
10598 static unsigned int
10599 flip_code16 (unsigned int code16)
10601 gas_assert (i.tm.operands == 1);
10603 return !(i.prefix[REX_PREFIX] & REX_W)
10604 && (code16 ? i.tm.operand_types[0].bitfield.disp32
10605 : i.tm.operand_types[0].bitfield.disp16)
10610 output_branch (void)
10616 relax_substateT subtype;
10620 if (now_seg == absolute_section)
10622 as_bad (_("relaxable branches not supported in absolute section"));
10626 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
10627 size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL;
10630 if (i.prefix[DATA_PREFIX] != 0)
10634 code16 ^= flip_code16(code16);
10636 /* Pentium4 branch hints. */
10637 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
10638 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
10643 if (i.prefix[REX_PREFIX] != 0)
10649 /* BND prefixed jump. */
10650 if (i.prefix[BND_PREFIX] != 0)
10656 if (i.prefixes != 0)
10657 as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
10659 /* It's always a symbol; End frag & setup for relax.
10660 Make sure there is enough room in this frag for the largest
10661 instruction we may generate in md_convert_frag. This is 2
10662 bytes for the opcode and room for the prefix and largest
10664 frag_grow (prefix + 2 + 4);
10665 /* Prefix and 1 opcode byte go in fr_fix. */
10666 p = frag_more (prefix + 1);
10667 if (i.prefix[DATA_PREFIX] != 0)
10668 *p++ = DATA_PREFIX_OPCODE;
10669 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
10670 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
10671 *p++ = i.prefix[SEG_PREFIX];
10672 if (i.prefix[BND_PREFIX] != 0)
10673 *p++ = BND_PREFIX_OPCODE;
10674 if (i.prefix[REX_PREFIX] != 0)
10675 *p++ = i.prefix[REX_PREFIX];
10676 *p = i.tm.base_opcode;
10678 if ((unsigned char) *p == JUMP_PC_RELATIVE)
10679 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
10680 else if (cpu_arch_flags.bitfield.cpui386)
10681 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
10683 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
10686 sym = i.op[0].disps->X_add_symbol;
10687 off = i.op[0].disps->X_add_number;
10689 if (i.op[0].disps->X_op != O_constant
10690 && i.op[0].disps->X_op != O_symbol)
10692 /* Handle complex expressions. */
10693 sym = make_expr_symbol (i.op[0].disps);
10697 /* 1 possible extra opcode + 4 byte displacement go in var part.
10698 Pass reloc in fr_var. */
10699 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
10702 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10703 /* Return TRUE iff PLT32 relocation should be used for branching to
10707 need_plt32_p (symbolS *s)
10709 /* PLT32 relocation is ELF only. */
10714 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
10715 krtld support it. */
10719 /* Since there is no need to prepare for PLT branch on x86-64, we
10720 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
10721 be used as a marker for 32-bit PC-relative branches. */
10728 /* Weak or undefined symbol need PLT32 relocation. */
10729 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
10732 /* Non-global symbol doesn't need PLT32 relocation. */
10733 if (! S_IS_EXTERNAL (s))
10736 /* Other global symbols need PLT32 relocation. NB: Symbol with
10737 non-default visibilities are treated as normal global symbol
10738 so that PLT32 relocation can be used as a marker for 32-bit
10739 PC-relative branches. It is useful for linker relaxation. */
10750 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
10752 if (i.tm.opcode_modifier.jump == JUMP_BYTE)
10754 /* This is a loop or jecxz type instruction. */
10756 if (i.prefix[ADDR_PREFIX] != 0)
10758 frag_opcode_byte (ADDR_PREFIX_OPCODE);
10761 /* Pentium4 branch hints. */
10762 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
10763 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
10765 frag_opcode_byte (i.prefix[SEG_PREFIX]);
10774 if (flag_code == CODE_16BIT)
10777 if (i.prefix[DATA_PREFIX] != 0)
10779 frag_opcode_byte (DATA_PREFIX_OPCODE);
10781 code16 ^= flip_code16(code16);
10789 /* BND prefixed jump. */
10790 if (i.prefix[BND_PREFIX] != 0)
10792 frag_opcode_byte (i.prefix[BND_PREFIX]);
10796 if (i.prefix[REX_PREFIX] != 0)
10798 frag_opcode_byte (i.prefix[REX_PREFIX]);
10802 if (i.prefixes != 0)
10803 as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
10805 if (now_seg == absolute_section)
10807 abs_section_offset += i.opcode_length + size;
10811 p = frag_more (i.opcode_length + size);
10812 switch (i.opcode_length)
10815 *p++ = i.tm.base_opcode >> 8;
10816 /* Fall through. */
10818 *p++ = i.tm.base_opcode;
10824 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10825 if (flag_code == CODE_64BIT && size == 4
10826 && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0
10827 && need_plt32_p (i.op[0].disps->X_add_symbol))
10828 jump_reloc = BFD_RELOC_X86_64_PLT32;
10831 jump_reloc = reloc (size, 1, 1, jump_reloc);
10833 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
10834 i.op[0].disps, 1, jump_reloc);
10836 /* All jumps handled here are signed, but don't unconditionally use a
10837 signed limit check for 32 and 16 bit jumps as we want to allow wrap
10838 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
10843 fixP->fx_signed = 1;
10847 if (i.tm.mnem_off == MN_xbegin)
10848 fixP->fx_signed = 1;
10852 if (flag_code == CODE_64BIT)
10853 fixP->fx_signed = 1;
10859 output_interseg_jump (void)
10867 if (flag_code == CODE_16BIT)
10871 if (i.prefix[DATA_PREFIX] != 0)
10878 gas_assert (!i.prefix[REX_PREFIX]);
10884 if (i.prefixes != 0)
10885 as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm));
10887 if (now_seg == absolute_section)
10889 abs_section_offset += prefix + 1 + 2 + size;
10893 /* 1 opcode; 2 segment; offset */
10894 p = frag_more (prefix + 1 + 2 + size);
10896 if (i.prefix[DATA_PREFIX] != 0)
10897 *p++ = DATA_PREFIX_OPCODE;
10899 if (i.prefix[REX_PREFIX] != 0)
10900 *p++ = i.prefix[REX_PREFIX];
10902 *p++ = i.tm.base_opcode;
10903 if (i.op[1].imms->X_op == O_constant)
10905 offsetT n = i.op[1].imms->X_add_number;
10908 && !fits_in_unsigned_word (n)
10909 && !fits_in_signed_word (n))
10911 as_bad (_("16-bit jump out of range"));
10914 md_number_to_chars (p, n, size);
10917 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
10918 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
10921 if (i.op[0].imms->X_op == O_constant)
10922 md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2);
10924 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
10925 i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0]));
10928 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10933 asection *seg = now_seg;
10934 subsegT subseg = now_subseg;
10936 unsigned int alignment, align_size_1;
10937 unsigned int isa_1_descsz, feature_2_descsz, descsz;
10938 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
10939 unsigned int padding;
10941 if (!IS_ELF || !x86_used_note)
10944 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
10946 /* The .note.gnu.property section layout:
10948 Field Length Contents
10951 n_descsz 4 The note descriptor size
10952 n_type 4 NT_GNU_PROPERTY_TYPE_0
10954 n_desc n_descsz The program property array
10958 /* Create the .note.gnu.property section. */
10959 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
10960 bfd_set_section_flags (sec,
10967 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
10978 bfd_set_section_alignment (sec, alignment);
10979 elf_section_type (sec) = SHT_NOTE;
10981 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
10983 isa_1_descsz_raw = 4 + 4 + 4;
10984 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
10985 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
10987 feature_2_descsz_raw = isa_1_descsz;
10988 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
10990 feature_2_descsz_raw += 4 + 4 + 4;
10991 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
10992 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
10995 descsz = feature_2_descsz;
10996 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
10997 p = frag_more (4 + 4 + 4 + 4 + descsz);
10999 /* Write n_namsz. */
11000 md_number_to_chars (p, (valueT) 4, 4);
11002 /* Write n_descsz. */
11003 md_number_to_chars (p + 4, (valueT) descsz, 4);
11005 /* Write n_type. */
11006 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
11008 /* Write n_name. */
11009 memcpy (p + 4 * 3, "GNU", 4);
11011 /* Write 4-byte type. */
11012 md_number_to_chars (p + 4 * 4,
11013 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
11015 /* Write 4-byte data size. */
11016 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
11018 /* Write 4-byte data. */
11019 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
11021 /* Zero out paddings. */
11022 padding = isa_1_descsz - isa_1_descsz_raw;
11024 memset (p + 4 * 7, 0, padding);
11026 /* Write 4-byte type. */
11027 md_number_to_chars (p + isa_1_descsz + 4 * 4,
11028 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
11030 /* Write 4-byte data size. */
11031 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
11033 /* Write 4-byte data. */
11034 md_number_to_chars (p + isa_1_descsz + 4 * 6,
11035 (valueT) x86_feature_2_used, 4);
11037 /* Zero out paddings. */
11038 padding = feature_2_descsz - feature_2_descsz_raw;
11040 memset (p + isa_1_descsz + 4 * 7, 0, padding);
11042 /* We probably can't restore the current segment, for there likely
11043 isn't one yet... */
11045 subseg_set (seg, subseg);
11049 x86_support_sframe_p (void)
11051 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
11052 return (x86_elf_abi == X86_64_ABI);
11056 x86_sframe_ra_tracking_p (void)
11058 /* In AMD64, return address is always stored on the stack at a fixed offset
11059 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
11060 Do not track explicitly via an SFrame Frame Row Entry. */
11065 x86_sframe_cfa_ra_offset (void)
11067 gas_assert (x86_elf_abi == X86_64_ABI);
11068 return (offsetT) -8;
11072 x86_sframe_get_abi_arch (void)
11074 unsigned char sframe_abi_arch = 0;
11076 if (x86_support_sframe_p ())
11078 gas_assert (!target_big_endian);
11079 sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE;
11082 return sframe_abi_arch;
11087 static unsigned int
11088 encoding_length (const fragS *start_frag, offsetT start_off,
11089 const char *frag_now_ptr)
11091 unsigned int len = 0;
11093 if (start_frag != frag_now)
11095 const fragS *fr = start_frag;
11100 } while (fr && fr != frag_now);
11103 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
11106 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
11107 be macro-fused with conditional jumps.
11108 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
11109 or is one of the following format:
11119 it is unfusible. */
11122 maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p)
11124 /* No RIP address. */
11125 if (i.base_reg && i.base_reg->reg_num == RegIP)
11128 /* No opcodes outside of base encoding space. */
11129 if (i.tm.opcode_space != SPACE_BASE)
11132 /* add, sub without add/sub m, imm. */
11133 if (i.tm.base_opcode <= 5
11134 || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d)
11135 || ((i.tm.base_opcode | 3) == 0x83
11136 && (i.tm.extension_opcode == 0x5
11137 || i.tm.extension_opcode == 0x0)))
11139 *mf_cmp_p = mf_cmp_alu_cmp;
11140 return !(i.mem_operands && i.imm_operands);
11143 /* and without and m, imm. */
11144 if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25)
11145 || ((i.tm.base_opcode | 3) == 0x83
11146 && i.tm.extension_opcode == 0x4))
11148 *mf_cmp_p = mf_cmp_test_and;
11149 return !(i.mem_operands && i.imm_operands);
11152 /* test without test m imm. */
11153 if ((i.tm.base_opcode | 1) == 0x85
11154 || (i.tm.base_opcode | 1) == 0xa9
11155 || ((i.tm.base_opcode | 1) == 0xf7
11156 && i.tm.extension_opcode == 0))
11158 *mf_cmp_p = mf_cmp_test_and;
11159 return !(i.mem_operands && i.imm_operands);
11162 /* cmp without cmp m, imm. */
11163 if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d)
11164 || ((i.tm.base_opcode | 3) == 0x83
11165 && (i.tm.extension_opcode == 0x7)))
11167 *mf_cmp_p = mf_cmp_alu_cmp;
11168 return !(i.mem_operands && i.imm_operands);
11171 /* inc, dec without inc/dec m. */
11172 if ((is_cpu (&i.tm, CpuNo64)
11173 && (i.tm.base_opcode | 0xf) == 0x4f)
11174 || ((i.tm.base_opcode | 1) == 0xff
11175 && i.tm.extension_opcode <= 0x1))
11177 *mf_cmp_p = mf_cmp_incdec;
11178 return !i.mem_operands;
11184 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
11187 add_fused_jcc_padding_frag_p (enum mf_cmp_kind *mf_cmp_p,
11188 const struct last_insn *last_insn)
11190 /* NB: Don't work with COND_JUMP86 without i386. */
11191 if (!align_branch_power
11192 || now_seg == absolute_section
11193 || !cpu_arch_flags.bitfield.cpui386
11194 || !(align_branch & align_branch_fused_bit))
11197 if (maybe_fused_with_jcc_p (mf_cmp_p))
11199 if (last_insn->kind == last_insn_other)
11202 as_warn_where (last_insn->file, last_insn->line,
11203 _("`%s` skips -malign-branch-boundary on `%s`"),
11204 last_insn->name, insn_name (&i.tm));
11210 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
11213 add_branch_prefix_frag_p (const struct last_insn *last_insn)
11215 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
11216 to PadLock instructions since they include prefixes in opcode. */
11217 if (!align_branch_power
11218 || !align_branch_prefix_size
11219 || now_seg == absolute_section
11220 || is_cpu (&i.tm, CpuPadLock)
11221 || !cpu_arch_flags.bitfield.cpui386)
11224 /* Don't add prefix if it is a prefix or there is no operand in case
11225 that segment prefix is special. */
11226 if (!i.operands || i.tm.opcode_modifier.isprefix)
11229 if (last_insn->kind == last_insn_other)
11233 as_warn_where (last_insn->file, last_insn->line,
11234 _("`%s` skips -malign-branch-boundary on `%s`"),
11235 last_insn->name, insn_name (&i.tm));
11240 /* Return 1 if a BRANCH_PADDING frag should be generated. */
11243 add_branch_padding_frag_p (enum align_branch_kind *branch_p,
11244 enum mf_jcc_kind *mf_jcc_p,
11245 const struct last_insn *last_insn)
11249 /* NB: Don't work with COND_JUMP86 without i386. */
11250 if (!align_branch_power
11251 || now_seg == absolute_section
11252 || !cpu_arch_flags.bitfield.cpui386
11253 || i.tm.opcode_space != SPACE_BASE)
11258 /* Check for jcc and direct jmp. */
11259 if (i.tm.opcode_modifier.jump == JUMP)
11261 if (i.tm.base_opcode == JUMP_PC_RELATIVE)
11263 *branch_p = align_branch_jmp;
11264 add_padding = align_branch & align_branch_jmp_bit;
11268 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
11269 igore the lowest bit. */
11270 *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1;
11271 *branch_p = align_branch_jcc;
11272 if ((align_branch & align_branch_jcc_bit))
11276 else if ((i.tm.base_opcode | 1) == 0xc3)
11279 *branch_p = align_branch_ret;
11280 if ((align_branch & align_branch_ret_bit))
11285 /* Check for indirect jmp, direct and indirect calls. */
11286 if (i.tm.base_opcode == 0xe8)
11289 *branch_p = align_branch_call;
11290 if ((align_branch & align_branch_call_bit))
11293 else if (i.tm.base_opcode == 0xff
11294 && (i.tm.extension_opcode == 2
11295 || i.tm.extension_opcode == 4))
11297 /* Indirect call and jmp. */
11298 *branch_p = align_branch_indirect;
11299 if ((align_branch & align_branch_indirect_bit))
11306 && (i.op[0].disps->X_op == O_symbol
11307 || (i.op[0].disps->X_op == O_subtract
11308 && i.op[0].disps->X_op_symbol == GOT_symbol)))
11310 symbolS *s = i.op[0].disps->X_add_symbol;
11311 /* No padding to call to global or undefined tls_get_addr. */
11312 if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s))
11313 && strcmp (S_GET_NAME (s), tls_get_addr) == 0)
11319 && last_insn->kind != last_insn_other)
11322 as_warn_where (last_insn->file, last_insn->line,
11323 _("`%s` skips -malign-branch-boundary on `%s`"),
11324 last_insn->name, insn_name (&i.tm));
11328 return add_padding;
11332 output_insn (const struct last_insn *last_insn)
11334 fragS *insn_start_frag;
11335 offsetT insn_start_off;
11336 fragS *fragP = NULL;
11337 enum align_branch_kind branch = align_branch_none;
11338 /* The initializer is arbitrary just to avoid uninitialized error.
11339 it's actually either assigned in add_branch_padding_frag_p
11340 or never be used. */
11341 enum mf_jcc_kind mf_jcc = mf_jcc_jo;
11343 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11344 if (IS_ELF && x86_used_note && now_seg != absolute_section)
11346 if ((i.xstate & xstate_tmm) == xstate_tmm
11347 || is_cpu (&i.tm, CpuAMX_TILE))
11348 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
11350 if (is_cpu (&i.tm, Cpu8087)
11351 || is_cpu (&i.tm, Cpu287)
11352 || is_cpu (&i.tm, Cpu387)
11353 || is_cpu (&i.tm, Cpu687)
11354 || is_cpu (&i.tm, CpuFISTTP))
11355 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
11357 if ((i.xstate & xstate_mmx)
11358 || i.tm.mnem_off == MN_emms
11359 || i.tm.mnem_off == MN_femms)
11360 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
11364 if (i.index_reg->reg_type.bitfield.zmmword)
11365 i.xstate |= xstate_zmm;
11366 else if (i.index_reg->reg_type.bitfield.ymmword)
11367 i.xstate |= xstate_ymm;
11368 else if (i.index_reg->reg_type.bitfield.xmmword)
11369 i.xstate |= xstate_xmm;
11372 /* vzeroall / vzeroupper */
11373 if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX))
11374 i.xstate |= xstate_ymm;
11376 if ((i.xstate & xstate_xmm)
11377 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
11378 || (i.tm.base_opcode == 0xae
11379 && (is_cpu (&i.tm, CpuSSE)
11380 || is_cpu (&i.tm, CpuAVX)))
11381 || is_cpu (&i.tm, CpuWideKL)
11382 || is_cpu (&i.tm, CpuKL))
11383 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
11385 if ((i.xstate & xstate_ymm) == xstate_ymm)
11386 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
11387 if ((i.xstate & xstate_zmm) == xstate_zmm)
11388 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
11389 if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask)
11390 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK;
11391 if (is_cpu (&i.tm, CpuFXSR))
11392 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
11393 if (is_cpu (&i.tm, CpuXsave))
11394 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
11395 if (is_cpu (&i.tm, CpuXsaveopt))
11396 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
11397 if (is_cpu (&i.tm, CpuXSAVEC))
11398 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
11400 if (x86_feature_2_used
11401 || is_cpu (&i.tm, CpuCMOV)
11402 || is_cpu (&i.tm, CpuSYSCALL)
11403 || i.tm.mnem_off == MN_cmpxchg8b)
11404 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE;
11405 if (is_cpu (&i.tm, CpuSSE3)
11406 || is_cpu (&i.tm, CpuSSSE3)
11407 || is_cpu (&i.tm, CpuSSE4_1)
11408 || is_cpu (&i.tm, CpuSSE4_2)
11409 || is_cpu (&i.tm, CpuCX16)
11410 || is_cpu (&i.tm, CpuPOPCNT)
11411 /* LAHF-SAHF insns in 64-bit mode. */
11412 || (flag_code == CODE_64BIT
11413 && (i.tm.base_opcode | 1) == 0x9f
11414 && i.tm.opcode_space == SPACE_BASE))
11415 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2;
11416 if (is_cpu (&i.tm, CpuAVX)
11417 || is_cpu (&i.tm, CpuAVX2)
11418 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
11419 XOP, FMA4, LPW, TBM, and AMX. */
11420 || (i.tm.opcode_modifier.vex
11421 && !is_cpu (&i.tm, CpuAVX512F)
11422 && !is_cpu (&i.tm, CpuAVX512BW)
11423 && !is_cpu (&i.tm, CpuAVX512DQ)
11424 && !is_cpu (&i.tm, CpuXOP)
11425 && !is_cpu (&i.tm, CpuFMA4)
11426 && !is_cpu (&i.tm, CpuLWP)
11427 && !is_cpu (&i.tm, CpuTBM)
11428 && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM))
11429 || is_cpu (&i.tm, CpuF16C)
11430 || is_cpu (&i.tm, CpuFMA)
11431 || is_cpu (&i.tm, CpuLZCNT)
11432 || is_cpu (&i.tm, CpuMovbe)
11433 || is_cpu (&i.tm, CpuXSAVES)
11434 || (x86_feature_2_used
11435 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
11436 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
11437 | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0)
11438 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3;
11439 if (is_cpu (&i.tm, CpuAVX512F)
11440 || is_cpu (&i.tm, CpuAVX512BW)
11441 || is_cpu (&i.tm, CpuAVX512DQ)
11442 || is_cpu (&i.tm, CpuAVX512VL)
11443 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
11444 AVX512-4FMAPS, and AVX512-4VNNIW. */
11445 || (i.tm.opcode_modifier.evex
11446 && !is_cpu (&i.tm, CpuAVX512ER)
11447 && !is_cpu (&i.tm, CpuAVX512PF)
11448 && !is_cpu (&i.tm, CpuAVX512_4FMAPS)
11449 && !is_cpu (&i.tm, CpuAVX512_4VNNIW)))
11450 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4;
11454 /* Tie dwarf2 debug info to the address at the start of the insn.
11455 We can't do this after the insn has been output as the current
11456 frag may have been closed off. eg. by frag_var. */
11457 dwarf2_emit_insn (0);
11459 insn_start_frag = frag_now;
11460 insn_start_off = frag_now_fix ();
11462 if (add_branch_padding_frag_p (&branch, &mf_jcc, last_insn))
11465 /* Branch can be 8 bytes. Leave some room for prefixes. */
11466 unsigned int max_branch_padding_size = 14;
11468 /* Align section to boundary. */
11469 record_alignment (now_seg, align_branch_power);
11471 /* Make room for padding. */
11472 frag_grow (max_branch_padding_size);
11474 /* Start of the padding. */
11479 frag_var (rs_machine_dependent, max_branch_padding_size, 0,
11480 ENCODE_RELAX_STATE (BRANCH_PADDING, 0),
11483 fragP->tc_frag_data.mf_type = mf_jcc;
11484 fragP->tc_frag_data.branch_type = branch;
11485 fragP->tc_frag_data.max_bytes = max_branch_padding_size;
11488 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)
11489 && !pre_386_16bit_warned)
11491 as_warn (_("use .code16 to ensure correct addressing mode"));
11492 pre_386_16bit_warned = true;
11495 /* Output jumps. */
11496 if (i.tm.opcode_modifier.jump == JUMP)
11498 else if (i.tm.opcode_modifier.jump == JUMP_BYTE
11499 || i.tm.opcode_modifier.jump == JUMP_DWORD)
11501 else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT)
11502 output_interseg_jump ();
11505 /* Output normal instructions here. */
11509 enum mf_cmp_kind mf_cmp;
11512 && (i.tm.base_opcode == 0xaee8
11513 || i.tm.base_opcode == 0xaef0
11514 || i.tm.base_opcode == 0xaef8))
11516 /* Encode lfence, mfence, and sfence as
11517 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
11518 if (flag_code == CODE_16BIT)
11519 as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm));
11520 else if (omit_lock_prefix)
11521 as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"),
11522 insn_name (&i.tm));
11523 else if (now_seg != absolute_section)
11525 offsetT val = 0x240483f0ULL;
11528 md_number_to_chars (p, val, 5);
11531 abs_section_offset += 5;
11535 /* Some processors fail on LOCK prefix. This options makes
11536 assembler ignore LOCK prefix and serves as a workaround. */
11537 if (omit_lock_prefix)
11539 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE
11540 && i.tm.opcode_modifier.isprefix)
11542 i.prefix[LOCK_PREFIX] = 0;
11546 /* Skip if this is a branch. */
11548 else if (add_fused_jcc_padding_frag_p (&mf_cmp, last_insn))
11550 /* Make room for padding. */
11551 frag_grow (MAX_FUSED_JCC_PADDING_SIZE);
11556 frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0,
11557 ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0),
11560 fragP->tc_frag_data.mf_type = mf_cmp;
11561 fragP->tc_frag_data.branch_type = align_branch_fused;
11562 fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE;
11564 else if (add_branch_prefix_frag_p (last_insn))
11566 unsigned int max_prefix_size = align_branch_prefix_size;
11568 /* Make room for padding. */
11569 frag_grow (max_prefix_size);
11574 frag_var (rs_machine_dependent, max_prefix_size, 0,
11575 ENCODE_RELAX_STATE (BRANCH_PREFIX, 0),
11578 fragP->tc_frag_data.max_bytes = max_prefix_size;
11581 /* Since the VEX/EVEX prefix contains the implicit prefix, we
11582 don't need the explicit prefix. */
11583 if (!is_any_vex_encoding (&i.tm))
11585 switch (i.tm.opcode_modifier.opcodeprefix)
11594 if (!is_cpu (&i.tm, CpuPadLock)
11595 || (i.prefix[REP_PREFIX] != 0xf3))
11599 switch (i.opcode_length)
11604 /* Check for pseudo prefixes. */
11605 if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode)
11607 as_bad_where (insn_start_frag->fr_file,
11608 insn_start_frag->fr_line,
11609 _("pseudo prefix without instruction"));
11619 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11620 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
11621 R_X86_64_GOTTPOFF relocation so that linker can safely
11622 perform IE->LE optimization. A dummy REX_OPCODE prefix
11623 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
11624 relocation for GDesc -> IE/LE optimization. */
11625 if (x86_elf_abi == X86_64_X32_ABI
11626 && !is_apx_rex2_encoding ()
11628 && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
11629 || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
11630 && i.prefix[REX_PREFIX] == 0)
11631 add_prefix (REX_OPCODE);
11634 /* The prefix bytes. */
11635 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
11637 frag_opcode_byte (*q);
11639 if (is_apx_rex2_encoding ())
11641 frag_opcode_byte (i.vex.bytes[0]);
11642 frag_opcode_byte (i.vex.bytes[1]);
11647 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
11653 frag_opcode_byte (*q);
11656 /* There should be no other prefixes for instructions
11657 with VEX prefix. */
11661 /* For EVEX instructions i.vrex should become 0 after
11662 build_evex_prefix. For VEX instructions upper 16 registers
11663 aren't available, so VREX should be 0. */
11666 /* Now the VEX prefix. */
11667 if (now_seg != absolute_section)
11669 p = frag_more (i.vex.length);
11670 for (j = 0; j < i.vex.length; j++)
11671 p[j] = i.vex.bytes[j];
11674 abs_section_offset += i.vex.length;
11677 /* Now the opcode; be careful about word order here! */
11678 j = i.opcode_length;
11680 switch (i.tm.opcode_space)
11695 if (now_seg == absolute_section)
11696 abs_section_offset += j;
11699 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
11705 && i.tm.opcode_space != SPACE_BASE)
11708 if (i.tm.opcode_space != SPACE_0F)
11709 *p++ = i.tm.opcode_space == SPACE_0F38
11713 switch (i.opcode_length)
11716 /* Put out high byte first: can't use md_number_to_chars! */
11717 *p++ = (i.tm.base_opcode >> 8) & 0xff;
11718 /* Fall through. */
11720 *p = i.tm.base_opcode & 0xff;
11729 /* Now the modrm byte and sib byte (if present). */
11730 if (i.tm.opcode_modifier.modrm)
11732 frag_opcode_byte ((i.rm.regmem << 0)
11734 | (i.rm.mode << 6));
11735 /* If i.rm.regmem == ESP (4)
11736 && i.rm.mode != (Register mode)
11738 ==> need second modrm byte. */
11739 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
11741 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
11742 frag_opcode_byte ((i.sib.base << 0)
11743 | (i.sib.index << 3)
11744 | (i.sib.scale << 6));
11747 if (i.disp_operands)
11748 output_disp (insn_start_frag, insn_start_off);
11750 if (i.imm_operands)
11751 output_imm (insn_start_frag, insn_start_off);
11754 * frag_now_fix () returning plain abs_section_offset when we're in the
11755 * absolute section, and abs_section_offset not getting updated as data
11756 * gets added to the frag breaks the logic below.
11758 if (now_seg != absolute_section)
11760 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
11762 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
11766 /* NB: Don't add prefix with GOTPC relocation since
11767 output_disp() above depends on the fixed encoding
11768 length. Can't add prefix with TLS relocation since
11769 it breaks TLS linker optimization. */
11770 unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j;
11771 /* Prefix count on the current instruction. */
11772 unsigned int count = i.vex.length;
11774 for (k = 0; k < ARRAY_SIZE (i.prefix); k++)
11775 /* REX byte is encoded in VEX/EVEX prefix. */
11776 if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length))
11779 /* Count prefixes for extended opcode maps. */
11781 switch (i.tm.opcode_space)
11796 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
11799 /* Set the maximum prefix size in BRANCH_PREFIX
11801 if (fragP->tc_frag_data.max_bytes > max)
11802 fragP->tc_frag_data.max_bytes = max;
11803 if (fragP->tc_frag_data.max_bytes > count)
11804 fragP->tc_frag_data.max_bytes -= count;
11806 fragP->tc_frag_data.max_bytes = 0;
11810 /* Remember the maximum prefix size in FUSED_JCC_PADDING
11812 unsigned int max_prefix_size;
11813 if (align_branch_prefix_size > max)
11814 max_prefix_size = max;
11816 max_prefix_size = align_branch_prefix_size;
11817 if (max_prefix_size > count)
11818 fragP->tc_frag_data.max_prefix_length
11819 = max_prefix_size - count;
11822 /* Use existing segment prefix if possible. Use CS
11823 segment prefix in 64-bit mode. In 32-bit mode, use SS
11824 segment prefix with ESP/EBP base register and use DS
11825 segment prefix without ESP/EBP base register. */
11826 if (i.prefix[SEG_PREFIX])
11827 fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX];
11828 else if (flag_code == CODE_64BIT)
11829 fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE;
11830 else if (i.base_reg
11831 && (i.base_reg->reg_num == 4
11832 || i.base_reg->reg_num == 5))
11833 fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE;
11835 fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE;
11840 /* NB: Don't work with COND_JUMP86 without i386. */
11841 if (align_branch_power
11842 && now_seg != absolute_section
11843 && cpu_arch_flags.bitfield.cpui386)
11845 /* Terminate each frag so that we can add prefix and check for
11847 frag_wane (frag_now);
11854 pi ("" /*line*/, &i);
11856 #endif /* DEBUG386 */
11859 /* Return the size of the displacement operand N. */
11862 disp_size (unsigned int n)
11866 if (i.types[n].bitfield.disp64)
11868 else if (i.types[n].bitfield.disp8)
11870 else if (i.types[n].bitfield.disp16)
11875 /* Return the size of the immediate operand N. */
11878 imm_size (unsigned int n)
11881 if (i.types[n].bitfield.imm64)
11883 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
11885 else if (i.types[n].bitfield.imm16)
11891 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
11896 for (n = 0; n < i.operands; n++)
11898 if (operand_type_check (i.types[n], disp))
11900 int size = disp_size (n);
11902 if (now_seg == absolute_section)
11903 abs_section_offset += size;
11904 else if (i.op[n].disps->X_op == O_constant)
11906 offsetT val = i.op[n].disps->X_add_number;
11908 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
11910 p = frag_more (size);
11911 md_number_to_chars (p, val, size);
11915 enum bfd_reloc_code_real reloc_type;
11916 bool pcrel = (i.flags[n] & Operand_PCrel) != 0;
11917 bool sign = (flag_code == CODE_64BIT && size == 4
11918 && (!want_disp32 (&i.tm)
11919 || (i.tm.opcode_modifier.jump && !i.jumpabsolute
11920 && !i.types[n].bitfield.baseindex)))
11924 /* We can't have 8 bit displacement here. */
11925 gas_assert (!i.types[n].bitfield.disp8);
11927 /* The PC relative address is computed relative
11928 to the instruction boundary, so in case immediate
11929 fields follows, we need to adjust the value. */
11930 if (pcrel && i.imm_operands)
11935 for (n1 = 0; n1 < i.operands; n1++)
11936 if (operand_type_check (i.types[n1], imm))
11938 /* Only one immediate is allowed for PC
11939 relative address, except with .insn. */
11940 gas_assert (sz == 0 || dot_insn ());
11941 sz += imm_size (n1);
11943 /* We should find at least one immediate. */
11944 gas_assert (sz != 0);
11945 i.op[n].disps->X_add_number -= sz;
11948 p = frag_more (size);
11949 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
11951 && GOT_symbol == i.op[n].disps->X_add_symbol
11952 && (((reloc_type == BFD_RELOC_32
11953 || reloc_type == BFD_RELOC_X86_64_32S
11954 || (reloc_type == BFD_RELOC_64
11956 && (i.op[n].disps->X_op == O_symbol
11957 || (i.op[n].disps->X_op == O_add
11958 && ((symbol_get_value_expression
11959 (i.op[n].disps->X_op_symbol)->X_op)
11961 || reloc_type == BFD_RELOC_32_PCREL))
11965 reloc_type = BFD_RELOC_386_GOTPC;
11966 i.has_gotpc_tls_reloc = true;
11967 i.op[n].disps->X_add_number +=
11968 encoding_length (insn_start_frag, insn_start_off, p);
11970 else if (reloc_type == BFD_RELOC_64)
11971 reloc_type = BFD_RELOC_X86_64_GOTPC64;
11973 /* Don't do the adjustment for x86-64, as there
11974 the pcrel addressing is relative to the _next_
11975 insn, and that is taken care of in other code. */
11976 reloc_type = BFD_RELOC_X86_64_GOTPC32;
11978 else if (align_branch_power)
11980 switch (reloc_type)
11982 case BFD_RELOC_386_TLS_GD:
11983 case BFD_RELOC_386_TLS_LDM:
11984 case BFD_RELOC_386_TLS_IE:
11985 case BFD_RELOC_386_TLS_IE_32:
11986 case BFD_RELOC_386_TLS_GOTIE:
11987 case BFD_RELOC_386_TLS_GOTDESC:
11988 case BFD_RELOC_386_TLS_DESC_CALL:
11989 case BFD_RELOC_X86_64_TLSGD:
11990 case BFD_RELOC_X86_64_TLSLD:
11991 case BFD_RELOC_X86_64_GOTTPOFF:
11992 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
11993 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11994 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
11995 case BFD_RELOC_X86_64_TLSDESC_CALL:
11996 i.has_gotpc_tls_reloc = true;
12001 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
12002 size, i.op[n].disps, pcrel,
12005 if (flag_code == CODE_64BIT && size == 4 && pcrel
12006 && !i.prefix[ADDR_PREFIX])
12007 fixP->fx_signed = 1;
12009 /* Set fx_tcbit3 for REX2 prefix. */
12010 if (is_apx_rex2_encoding ())
12011 fixP->fx_tcbit3 = 1;
12013 /* Check for "call/jmp *mem", "mov mem, %reg",
12014 "test %reg, mem" and "binop mem, %reg" where binop
12015 is one of adc, add, and, cmp, or, sbb, sub, xor
12016 instructions without data prefix. Always generate
12017 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
12018 if (i.prefix[DATA_PREFIX] == 0
12019 && (generate_relax_relocations
12022 && i.rm.regmem == 5))
12024 || (i.rm.mode == 0 && i.rm.regmem == 5))
12025 && i.tm.opcode_space == SPACE_BASE
12026 && ((i.operands == 1
12027 && i.tm.base_opcode == 0xff
12028 && (i.rm.reg == 2 || i.rm.reg == 4))
12029 || (i.operands == 2
12030 && (i.tm.base_opcode == 0x8b
12031 || i.tm.base_opcode == 0x85
12032 || (i.tm.base_opcode & ~0x38) == 0x03))))
12036 fixP->fx_tcbit = i.rex != 0;
12038 && (i.base_reg->reg_num == RegIP))
12039 fixP->fx_tcbit2 = 1;
12042 fixP->fx_tcbit2 = 1;
12050 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
12055 for (n = 0; n < i.operands; n++)
12057 if (operand_type_check (i.types[n], imm))
12059 int size = imm_size (n);
12061 if (now_seg == absolute_section)
12062 abs_section_offset += size;
12063 else if (i.op[n].imms->X_op == O_constant)
12067 val = offset_in_range (i.op[n].imms->X_add_number,
12069 p = frag_more (size);
12070 md_number_to_chars (p, val, size);
12074 /* Not absolute_section.
12075 Need a 32-bit fixup (don't support 8bit
12076 non-absolute imms). Try to support other
12078 enum bfd_reloc_code_real reloc_type;
12081 if (i.types[n].bitfield.imm32s
12082 && (i.suffix == QWORD_MNEM_SUFFIX
12083 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)
12084 || (i.prefix[REX_PREFIX] & REX_W)
12090 p = frag_more (size);
12091 reloc_type = reloc (size, 0, sign, i.reloc[n]);
12093 /* This is tough to explain. We end up with this one if we
12094 * have operands that look like
12095 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
12096 * obtain the absolute address of the GOT, and it is strongly
12097 * preferable from a performance point of view to avoid using
12098 * a runtime relocation for this. The actual sequence of
12099 * instructions often look something like:
12104 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
12106 * The call and pop essentially return the absolute address
12107 * of the label .L66 and store it in %ebx. The linker itself
12108 * will ultimately change the first operand of the addl so
12109 * that %ebx points to the GOT, but to keep things simple, the
12110 * .o file must have this operand set so that it generates not
12111 * the absolute address of .L66, but the absolute address of
12112 * itself. This allows the linker itself simply treat a GOTPC
12113 * relocation as asking for a pcrel offset to the GOT to be
12114 * added in, and the addend of the relocation is stored in the
12115 * operand field for the instruction itself.
12117 * Our job here is to fix the operand so that it would add
12118 * the correct offset so that %ebx would point to itself. The
12119 * thing that is tricky is that .-.L66 will point to the
12120 * beginning of the instruction, so we need to further modify
12121 * the operand so that it will point to itself. There are
12122 * other cases where you have something like:
12124 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
12126 * and here no correction would be required. Internally in
12127 * the assembler we treat operands of this form as not being
12128 * pcrel since the '.' is explicitly mentioned, and I wonder
12129 * whether it would simplify matters to do it this way. Who
12130 * knows. In earlier versions of the PIC patches, the
12131 * pcrel_adjust field was used to store the correction, but
12132 * since the expression is not pcrel, I felt it would be
12133 * confusing to do it this way. */
12135 if ((reloc_type == BFD_RELOC_32
12136 || reloc_type == BFD_RELOC_X86_64_32S
12137 || reloc_type == BFD_RELOC_64)
12139 && GOT_symbol == i.op[n].imms->X_add_symbol
12140 && (i.op[n].imms->X_op == O_symbol
12141 || (i.op[n].imms->X_op == O_add
12142 && ((symbol_get_value_expression
12143 (i.op[n].imms->X_op_symbol)->X_op)
12147 reloc_type = BFD_RELOC_386_GOTPC;
12148 else if (size == 4)
12149 reloc_type = BFD_RELOC_X86_64_GOTPC32;
12150 else if (size == 8)
12151 reloc_type = BFD_RELOC_X86_64_GOTPC64;
12152 i.has_gotpc_tls_reloc = true;
12153 i.op[n].imms->X_add_number +=
12154 encoding_length (insn_start_frag, insn_start_off, p);
12156 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
12157 i.op[n].imms, 0, reloc_type);
12163 /* x86_cons_fix_new is called via the expression parsing code when a
12164 reloc is needed. We use this hook to get the correct .got reloc. */
12165 static int cons_sign = -1;
12168 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
12169 expressionS *exp, bfd_reloc_code_real_type r)
12171 r = reloc (len, 0, cons_sign, r);
12174 if (exp->X_op == O_secrel)
12176 exp->X_op = O_symbol;
12177 r = BFD_RELOC_32_SECREL;
12179 else if (exp->X_op == O_secidx)
12180 r = BFD_RELOC_16_SECIDX;
12183 fix_new_exp (frag, off, len, exp, 0, r);
12186 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
12187 purpose of the `.dc.a' internal pseudo-op. */
12190 x86_address_bytes (void)
12192 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
12194 return stdoutput->arch_info->bits_per_address / 8;
12197 #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
12198 || defined (LEX_AT)) && !defined (TE_PE)
12199 # define lex_got(reloc, adjust, types) NULL
12201 /* Parse operands of the form
12202 <symbol>@GOTOFF+<nnn>
12203 and similar .plt or .got references.
12205 If we find one, set up the correct relocation in RELOC and copy the
12206 input string, minus the `@GOTOFF' into a malloc'd buffer for
12207 parsing by the calling routine. Return this buffer, and if ADJUST
12208 is non-null set it to the length of the string we removed from the
12209 input line. Otherwise return NULL. */
12211 lex_got (enum bfd_reloc_code_real *rel,
12213 i386_operand_type *types)
12215 /* Some of the relocations depend on the size of what field is to
12216 be relocated. But in our callers i386_immediate and i386_displacement
12217 we don't yet know the operand size (this will be set by insn
12218 matching). Hence we record the word32 relocation here,
12219 and adjust the reloc according to the real size in reloc(). */
12220 static const struct
12224 const enum bfd_reloc_code_real rel[2];
12225 const i386_operand_type types64;
12226 bool need_GOT_symbol;
12231 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
12232 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
12233 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
12234 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
12235 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
12236 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
12237 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
12238 { .imm64 = 1, .disp64 = 1 } }
12241 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12242 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
12243 BFD_RELOC_SIZE32 },
12244 { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false },
12246 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
12247 BFD_RELOC_X86_64_PLTOFF64 },
12248 { .bitfield = { .imm64 = 1 } }, true },
12249 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
12250 BFD_RELOC_X86_64_PLT32 },
12251 OPERAND_TYPE_IMM32_32S_DISP32, false },
12252 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
12253 BFD_RELOC_X86_64_GOTPLT64 },
12254 OPERAND_TYPE_IMM64_DISP64, true },
12255 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
12256 BFD_RELOC_X86_64_GOTOFF64 },
12257 OPERAND_TYPE_IMM64_DISP64, true },
12258 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
12259 BFD_RELOC_X86_64_GOTPCREL },
12260 OPERAND_TYPE_IMM32_32S_DISP32, true },
12261 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
12262 BFD_RELOC_X86_64_TLSGD },
12263 OPERAND_TYPE_IMM32_32S_DISP32, true },
12264 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
12265 _dummy_first_bfd_reloc_code_real },
12266 OPERAND_TYPE_NONE, true },
12267 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
12268 BFD_RELOC_X86_64_TLSLD },
12269 OPERAND_TYPE_IMM32_32S_DISP32, true },
12270 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
12271 BFD_RELOC_X86_64_GOTTPOFF },
12272 OPERAND_TYPE_IMM32_32S_DISP32, true },
12273 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
12274 BFD_RELOC_X86_64_TPOFF32 },
12275 OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
12276 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
12277 _dummy_first_bfd_reloc_code_real },
12278 OPERAND_TYPE_NONE, true },
12279 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
12280 BFD_RELOC_X86_64_DTPOFF32 },
12281 OPERAND_TYPE_IMM32_32S_64_DISP32_64, true },
12282 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
12283 _dummy_first_bfd_reloc_code_real },
12284 OPERAND_TYPE_NONE, true },
12285 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
12286 _dummy_first_bfd_reloc_code_real },
12287 OPERAND_TYPE_NONE, true },
12288 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
12289 BFD_RELOC_X86_64_GOT32 },
12290 OPERAND_TYPE_IMM32_32S_64_DISP32, true },
12291 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
12292 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
12293 OPERAND_TYPE_IMM32_32S_DISP32, true },
12294 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
12295 BFD_RELOC_X86_64_TLSDESC_CALL },
12296 OPERAND_TYPE_IMM32_32S_DISP32, true },
12298 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
12299 BFD_RELOC_32_SECREL },
12300 OPERAND_TYPE_IMM32_32S_64_DISP32_64, false },
12303 #undef OPERAND_TYPE_IMM32_32S_DISP32
12304 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
12305 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
12306 #undef OPERAND_TYPE_IMM64_DISP64
12312 #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE)
12317 for (cp = input_line_pointer; *cp != '@'; cp++)
12318 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
12321 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
12323 int len = gotrel[j].len;
12324 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
12326 if (gotrel[j].rel[object_64bit] != 0)
12329 char *tmpbuf, *past_reloc;
12331 *rel = gotrel[j].rel[object_64bit];
12335 if (flag_code != CODE_64BIT)
12337 types->bitfield.imm32 = 1;
12338 types->bitfield.disp32 = 1;
12341 *types = gotrel[j].types64;
12344 if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL)
12345 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
12347 /* The length of the first part of our input line. */
12348 first = cp - input_line_pointer;
12350 /* The second part goes from after the reloc token until
12351 (and including) an end_of_line char or comma. */
12352 past_reloc = cp + 1 + len;
12354 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
12356 second = cp + 1 - past_reloc;
12358 /* Allocate and copy string. The trailing NUL shouldn't
12359 be necessary, but be safe. */
12360 tmpbuf = XNEWVEC (char, first + second + 2);
12361 memcpy (tmpbuf, input_line_pointer, first);
12362 if (second != 0 && *past_reloc != ' ')
12363 /* Replace the relocation token with ' ', so that
12364 errors like foo@GOTOFF1 will be detected. */
12365 tmpbuf[first++] = ' ';
12367 /* Increment length by 1 if the relocation token is
12372 memcpy (tmpbuf + first, past_reloc, second);
12373 tmpbuf[first + second] = '\0';
12377 as_bad (_("@%s reloc is not supported with %d-bit output format"),
12378 gotrel[j].str, 1 << (5 + object_64bit));
12383 /* Might be a symbol version string. Don't as_bad here. */
12388 bfd_reloc_code_real_type
12389 x86_cons (expressionS *exp, int size)
12391 bfd_reloc_code_real_type got_reloc = NO_RELOC;
12393 intel_syntax = -intel_syntax;
12395 expr_mode = expr_operator_none;
12397 #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
12398 && !defined (LEX_AT)) \
12400 if (size == 4 || (object_64bit && size == 8))
12402 /* Handle @GOTOFF and the like in an expression. */
12404 char *gotfree_input_line;
12407 save = input_line_pointer;
12408 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
12409 if (gotfree_input_line)
12410 input_line_pointer = gotfree_input_line;
12414 if (gotfree_input_line)
12416 /* expression () has merrily parsed up to the end of line,
12417 or a comma - in the wrong buffer. Transfer how far
12418 input_line_pointer has moved to the right buffer. */
12419 input_line_pointer = (save
12420 + (input_line_pointer - gotfree_input_line)
12422 free (gotfree_input_line);
12423 if (exp->X_op == O_constant
12424 || exp->X_op == O_absent
12425 || exp->X_op == O_illegal
12426 || exp->X_op == O_register
12427 || exp->X_op == O_big)
12429 char c = *input_line_pointer;
12430 *input_line_pointer = 0;
12431 as_bad (_("missing or invalid expression `%s'"), save);
12432 *input_line_pointer = c;
12434 else if ((got_reloc == BFD_RELOC_386_PLT32
12435 || got_reloc == BFD_RELOC_X86_64_PLT32)
12436 && exp->X_op != O_symbol)
12438 char c = *input_line_pointer;
12439 *input_line_pointer = 0;
12440 as_bad (_("invalid PLT expression `%s'"), save);
12441 *input_line_pointer = c;
12449 intel_syntax = -intel_syntax;
12452 i386_intel_simplify (exp);
12454 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
12455 if (size <= 4 && expr_mode == expr_operator_present
12456 && exp->X_op == O_constant && !object_64bit)
12457 exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
12463 signed_cons (int size)
12472 s_insn (int dummy ATTRIBUTE_UNUSED)
12474 char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr;
12475 char *saved_ilp = find_end_of_line (line, false), saved_char;
12479 bool vex = false, xop = false, evex = false;
12480 struct last_insn *last_insn;
12484 saved_char = *saved_ilp;
12487 end = parse_insn (line, mnemonic, true);
12491 *saved_ilp = saved_char;
12492 ignore_rest_of_line ();
12496 line += end - line;
12498 current_templates.start = &i.tm;
12499 current_templates.end = &i.tm + 1;
12500 i.tm.mnem_off = MN__insn;
12501 i.tm.extension_opcode = None;
12503 if (startswith (line, "VEX")
12504 && (line[3] == '.' || is_space_char (line[3])))
12509 else if (startswith (line, "XOP") && ISDIGIT (line[3]))
12512 unsigned long n = strtoul (line + 3, &e, 16);
12514 if (e == line + 5 && n >= 0x08 && n <= 0x1f
12515 && (*e == '.' || is_space_char (*e)))
12518 /* Arrange for build_vex_prefix() to emit 0x8f. */
12519 i.tm.opcode_space = SPACE_XOP08;
12520 i.insn_opcode_space = n;
12524 else if (startswith (line, "EVEX")
12525 && (line[4] == '.' || is_space_char (line[4])))
12532 ? i.vec_encoding == vex_encoding_evex
12534 ? i.vec_encoding == vex_encoding_vex
12535 || i.vec_encoding == vex_encoding_vex3
12536 : i.vec_encoding != vex_encoding_default)
12538 as_bad (_("pseudo-prefix conflicts with encoding specifier"));
12542 if (line > end && i.vec_encoding == vex_encoding_default)
12543 i.vec_encoding = evex ? vex_encoding_evex : vex_encoding_vex;
12545 if (i.vec_encoding != vex_encoding_default)
12547 /* Only address size and segment override prefixes are permitted with
12548 VEX/XOP/EVEX encodings. */
12549 const unsigned char *p = i.prefix;
12551 for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p)
12562 as_bad (_("illegal prefix used with VEX/XOP/EVEX"));
12568 if (line > end && *line == '.')
12570 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
12578 i.tm.opcode_modifier.evex = EVEX128;
12580 i.tm.opcode_modifier.vex = VEX128;
12585 i.tm.opcode_modifier.evex = EVEX256;
12587 i.tm.opcode_modifier.vex = VEX256;
12592 i.tm.opcode_modifier.evex = EVEX512;
12597 i.tm.opcode_modifier.evex = EVEX_L3;
12601 if (line[3] == 'G')
12604 i.tm.opcode_modifier.evex = EVEXLIG;
12606 i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
12612 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
12617 if (line[2] == '2' && line[3] == '8')
12620 i.tm.opcode_modifier.evex = EVEX128;
12622 i.tm.opcode_modifier.vex = VEX128;
12628 if (line[2] == '5' && line[3] == '6')
12631 i.tm.opcode_modifier.evex = EVEX256;
12633 i.tm.opcode_modifier.vex = VEX256;
12639 if (evex && line[2] == '1' && line[3] == '2')
12641 i.tm.opcode_modifier.evex = EVEX512;
12648 if (line > end && *line == '.')
12650 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
12654 if (line[2] == 'P')
12659 if (line[2] == '6')
12661 i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66;
12666 case 'F': case 'f':
12667 if (line[2] == '3')
12669 i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3;
12672 else if (line[2] == '2')
12674 i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2;
12681 if (line > end && !xop && *line == '.')
12683 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
12687 if (TOUPPER (line[2]) != 'F')
12689 if (line[3] == '.' || is_space_char (line[3]))
12691 i.insn_opcode_space = SPACE_0F;
12694 else if (line[3] == '3'
12695 && (line[4] == '8' || TOUPPER (line[4]) == 'A')
12696 && (line[5] == '.' || is_space_char (line[5])))
12698 i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A;
12704 if (ISDIGIT (line[2]) && line[2] != '0')
12707 unsigned long n = strtoul (line + 2, &e, 10);
12709 if (n <= (evex ? 15 : 31)
12710 && (*e == '.' || is_space_char (*e)))
12712 i.insn_opcode_space = n;
12720 if (line > end && *line == '.' && line[1] == 'W')
12722 /* VEX.W, XOP.W, EVEX.W */
12726 i.tm.opcode_modifier.vexw = VEXW0;
12730 i.tm.opcode_modifier.vexw = VEXW1;
12734 if (line[3] == 'G')
12736 i.tm.opcode_modifier.vexw = VEXWIG;
12742 if (i.tm.opcode_modifier.vexw)
12746 if (line > end && *line && !is_space_char (*line))
12748 /* Improve diagnostic a little. */
12749 if (*line == '.' && line[1] && !is_space_char (line[1]))
12754 /* Before processing the opcode expression, find trailing "+r" or
12755 "/<digit>" specifiers. */
12756 for (ptr = line; ; ++ptr)
12761 ptr = strpbrk (ptr, "+/,");
12762 if (ptr == NULL || *ptr == ',')
12765 if (*ptr == '+' && ptr[1] == 'r'
12766 && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ',')))
12770 i.short_form = true;
12774 if (*ptr == '/' && ISDIGIT (ptr[1])
12775 && (n = strtoul (ptr + 1, &e, 8)) < 8
12777 && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ',')))
12781 i.tm.extension_opcode = n;
12782 i.tm.opcode_modifier.modrm = 1;
12787 input_line_pointer = line;
12788 val = get_absolute_expression ();
12789 line = input_line_pointer;
12791 if (i.short_form && (val & 7))
12792 as_warn ("`+r' assumes low three opcode bits to be clear");
12794 for (j = 1; j < sizeof(val); ++j)
12795 if (!(val >> (j * 8)))
12798 /* Trim off a prefix if present. */
12799 if (j > 1 && !vex && !xop && !evex)
12801 uint8_t byte = val >> ((j - 1) * 8);
12805 case DATA_PREFIX_OPCODE:
12806 case REPE_PREFIX_OPCODE:
12807 case REPNE_PREFIX_OPCODE:
12808 if (!add_prefix (byte))
12810 val &= ((uint64_t)1 << (--j * 8)) - 1;
12815 /* Trim off encoding space. */
12816 if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f)
12818 uint8_t byte = val >> ((--j - 1) * 8);
12820 i.insn_opcode_space = SPACE_0F;
12821 switch (byte & -(j > 1))
12824 i.insn_opcode_space = SPACE_0F38;
12828 i.insn_opcode_space = SPACE_0F3A;
12832 i.tm.opcode_space = i.insn_opcode_space;
12833 val &= ((uint64_t)1 << (j * 8)) - 1;
12835 if (!i.tm.opcode_space && (vex || evex))
12836 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
12837 Also avoid hitting abort() there or in build_evex_prefix(). */
12838 i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F
12843 as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val);
12846 i.opcode_length = j;
12848 /* Handle operands, if any. */
12851 i386_operand_type combined;
12852 expressionS *disp_exp = NULL;
12857 ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]);
12865 as_bad (_("expecting operand after ','; got nothing"));
12869 if (i.mem_operands > 1)
12871 as_bad (_("too many memory references for `%s'"),
12872 &i386_mnemonics[MN__insn]);
12876 /* No need to distinguish vex_encoding_evex and vex_encoding_evex512. */
12877 if (i.vec_encoding == vex_encoding_evex512)
12878 i.vec_encoding = vex_encoding_evex;
12880 /* Are we to emit ModR/M encoding? */
12883 || i.reg_operands > (i.vec_encoding != vex_encoding_default)
12884 || i.tm.extension_opcode != None))
12885 i.tm.opcode_modifier.modrm = 1;
12887 if (!i.tm.opcode_modifier.modrm
12889 > i.short_form + 0U + (i.vec_encoding != vex_encoding_default)
12890 || i.mem_operands))
12892 as_bad (_("too many register/memory operands"));
12896 /* Enforce certain constraints on operands. */
12897 switch (i.reg_operands + i.mem_operands
12898 + (i.tm.extension_opcode != None))
12903 as_bad (_("too few register/memory operands"));
12906 /* Fall through. */
12908 if (i.tm.opcode_modifier.modrm)
12910 as_bad (_("too few register/memory operands"));
12920 && (i.op[0].imms->X_op != O_constant
12921 || !fits_in_imm4 (i.op[0].imms->X_add_number)))
12923 as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4);
12926 /* Fall through. */
12928 if (i.vec_encoding != vex_encoding_default)
12930 i.tm.opcode_modifier.vexvvvv = 1;
12933 /* Fall through. */
12935 as_bad (_("too many register/memory operands"));
12939 /* Bring operands into canonical order (imm, mem, reg). */
12944 for (j = 1; j < i.operands; ++j)
12946 if ((!operand_type_check (i.types[j - 1], imm)
12947 && operand_type_check (i.types[j], imm))
12948 || (i.types[j - 1].bitfield.class != ClassNone
12949 && i.types[j].bitfield.class == ClassNone))
12951 swap_2_operands (j - 1, j);
12958 /* For Intel syntax swap the order of register operands. */
12960 switch (i.reg_operands)
12967 swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2);
12968 /* Fall through. */
12971 swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1);
12978 /* Enforce constraints when using VSIB. */
12980 && (i.index_reg->reg_type.bitfield.xmmword
12981 || i.index_reg->reg_type.bitfield.ymmword
12982 || i.index_reg->reg_type.bitfield.zmmword))
12984 if (i.vec_encoding == vex_encoding_default)
12986 as_bad (_("VSIB unavailable with legacy encoding"));
12990 if (i.vec_encoding == vex_encoding_evex
12991 && i.reg_operands > 1)
12993 /* We could allow two register operands, encoding the 2nd one in
12994 an 8-bit immediate like for 4-register-operand insns, but that
12995 would require ugly fiddling with process_operands() and/or
12996 build_modrm_byte(). */
12997 as_bad (_("too many register operands with VSIB"));
13001 i.tm.opcode_modifier.sib = 1;
13004 /* Establish operand size encoding. */
13005 operand_type_set (&combined, 0);
13007 for (j = i.imm_operands; j < i.operands; ++j)
13009 /* Look for 8-bit operands that use old registers. */
13010 if (i.vec_encoding != vex_encoding_default
13011 && flag_code == CODE_64BIT
13012 && i.types[j].bitfield.class == Reg
13013 && i.types[j].bitfield.byte
13014 && !(i.op[j].regs->reg_flags & RegRex64)
13015 && i.op[j].regs->reg_num > 3)
13016 as_bad (_("can't encode register '%s%s' with VEX/XOP/EVEX"),
13017 register_prefix, i.op[j].regs->reg_name);
13019 i.types[j].bitfield.instance = InstanceNone;
13021 if (operand_type_check (i.types[j], disp))
13023 i.types[j].bitfield.baseindex = 1;
13024 disp_exp = i.op[j].disps;
13027 if (evex && i.types[j].bitfield.baseindex)
13029 unsigned int n = i.memshift;
13031 if (i.types[j].bitfield.byte)
13033 else if (i.types[j].bitfield.word)
13035 else if (i.types[j].bitfield.dword)
13037 else if (i.types[j].bitfield.qword)
13039 else if (i.types[j].bitfield.xmmword)
13041 else if (i.types[j].bitfield.ymmword)
13043 else if (i.types[j].bitfield.zmmword)
13046 if (i.memshift < 32 && n != i.memshift)
13047 as_warn ("conflicting memory operand size specifiers");
13051 if ((i.broadcast.type || i.broadcast.bytes)
13052 && j == i.broadcast.operand)
13055 combined = operand_type_or (combined, i.types[j]);
13056 combined.bitfield.class = ClassNone;
13059 switch ((i.broadcast.type ? i.broadcast.type : 1)
13060 << (i.memshift < 32 ? i.memshift : 0))
13062 case 64: combined.bitfield.zmmword = 1; break;
13063 case 32: combined.bitfield.ymmword = 1; break;
13064 case 16: combined.bitfield.xmmword = 1; break;
13065 case 8: combined.bitfield.qword = 1; break;
13066 case 4: combined.bitfield.dword = 1; break;
13069 if (i.vec_encoding == vex_encoding_default)
13071 if (flag_code == CODE_64BIT && combined.bitfield.qword)
13073 else if ((flag_code == CODE_16BIT ? combined.bitfield.dword
13074 : combined.bitfield.word)
13075 && !add_prefix (DATA_PREFIX_OPCODE))
13078 else if (!i.tm.opcode_modifier.vexw)
13080 if (flag_code == CODE_64BIT)
13082 if (combined.bitfield.qword)
13083 i.tm.opcode_modifier.vexw = VEXW1;
13084 else if (combined.bitfield.dword)
13085 i.tm.opcode_modifier.vexw = VEXW0;
13088 if (!i.tm.opcode_modifier.vexw)
13089 i.tm.opcode_modifier.vexw = VEXWIG;
13094 if (!i.tm.opcode_modifier.vex)
13096 if (combined.bitfield.ymmword)
13097 i.tm.opcode_modifier.vex = VEX256;
13098 else if (combined.bitfield.xmmword)
13099 i.tm.opcode_modifier.vex = VEX128;
13104 if (!i.tm.opcode_modifier.evex)
13106 /* Do _not_ consider AVX512VL here. */
13107 if (i.rounding.type != rc_none || combined.bitfield.zmmword)
13108 i.tm.opcode_modifier.evex = EVEX512;
13109 else if (combined.bitfield.ymmword)
13110 i.tm.opcode_modifier.evex = EVEX256;
13111 else if (combined.bitfield.xmmword)
13112 i.tm.opcode_modifier.evex = EVEX128;
13115 if (i.memshift >= 32)
13117 unsigned int n = 0;
13119 switch (i.tm.opcode_modifier.evex)
13121 case EVEX512: n = 64; break;
13122 case EVEX256: n = 32; break;
13123 case EVEX128: n = 16; break;
13126 if (i.broadcast.type)
13127 n /= i.broadcast.type;
13130 for (i.memshift = 0; !(n & 1); n >>= 1)
13132 else if (disp_exp != NULL && disp_exp->X_op == O_constant
13133 && disp_exp->X_add_number != 0
13134 && i.disp_encoding != disp_encoding_32bit)
13136 if (!quiet_warnings)
13137 as_warn ("cannot determine memory operand size");
13138 i.disp_encoding = disp_encoding_32bit;
13143 if (i.memshift >= 32)
13146 i.vec_encoding = vex_encoding_error;
13148 if (i.disp_operands && !optimize_disp (&i.tm))
13151 /* Establish size for immediate operands. */
13152 for (j = 0; j < i.imm_operands; ++j)
13154 expressionS *expP = i.op[j].imms;
13156 gas_assert (operand_type_check (i.types[j], imm));
13157 operand_type_set (&i.types[j], 0);
13159 if (i.imm_bits[j] > 32)
13160 i.types[j].bitfield.imm64 = 1;
13161 else if (i.imm_bits[j] > 16)
13163 if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed))
13164 i.types[j].bitfield.imm32s = 1;
13166 i.types[j].bitfield.imm32 = 1;
13168 else if (i.imm_bits[j] > 8)
13169 i.types[j].bitfield.imm16 = 1;
13170 else if (i.imm_bits[j] > 0)
13172 if (i.flags[j] & Operand_Signed)
13173 i.types[j].bitfield.imm8s = 1;
13175 i.types[j].bitfield.imm8 = 1;
13177 else if (expP->X_op == O_constant)
13179 i.types[j] = smallest_imm_type (expP->X_add_number);
13180 i.types[j].bitfield.imm1 = 0;
13181 /* Oddly enough imm_size() checks imm64 first, so the bit needs
13182 zapping since smallest_imm_type() sets it unconditionally. */
13183 if (flag_code != CODE_64BIT)
13185 i.types[j].bitfield.imm64 = 0;
13186 i.types[j].bitfield.imm32s = 0;
13187 i.types[j].bitfield.imm32 = 1;
13189 else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s)
13190 i.types[j].bitfield.imm64 = 0;
13193 /* Non-constant expressions are sized heuristically. */
13196 case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break;
13197 case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break;
13198 case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break;
13202 for (j = 0; j < i.operands; ++j)
13203 i.tm.operand_types[j] = i.types[j];
13205 process_operands ();
13208 /* Don't set opcode until after processing operands, to avoid any
13209 potential special casing there. */
13210 i.tm.base_opcode |= val;
13212 if (i.vec_encoding == vex_encoding_error
13213 || (i.vec_encoding != vex_encoding_evex
13214 ? i.broadcast.type || i.broadcast.bytes
13215 || i.rounding.type != rc_none
13217 : (i.mem_operands && i.rounding.type != rc_none)
13218 || ((i.broadcast.type || i.broadcast.bytes)
13219 && !(i.flags[i.broadcast.operand] & Operand_Mem))))
13221 as_bad (_("conflicting .insn operands"));
13227 if (!i.tm.opcode_modifier.vex)
13228 i.tm.opcode_modifier.vex = VEXScalar; /* LIG */
13230 build_vex_prefix (NULL);
13231 i.rex &= REX_OPCODE;
13235 if (!i.tm.opcode_modifier.evex)
13236 i.tm.opcode_modifier.evex = EVEXLIG;
13238 build_evex_prefix ();
13239 i.rex &= REX_OPCODE;
13244 last_insn = &seg_info(now_seg)->tc_segment_info_data.last_insn;
13245 output_insn (last_insn);
13246 last_insn->kind = last_insn_directive;
13247 last_insn->name = ".insn directive";
13248 last_insn->file = as_where (&last_insn->line);
13250 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
13251 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
13252 performed in i386_target_format. */
13253 if (IS_ELF && flag_synth_cfi)
13254 as_bad (_("SCFI: hand-crafting instructions not supported"));
13258 *saved_ilp = saved_char;
13259 input_line_pointer = line;
13261 demand_empty_rest_of_line ();
13263 /* Make sure dot_insn() won't yield "true" anymore. */
13269 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
13276 if (exp.X_op == O_symbol)
13277 exp.X_op = O_secrel;
13279 emit_expr (&exp, 4);
13281 while (*input_line_pointer++ == ',');
13283 input_line_pointer--;
13284 demand_empty_rest_of_line ();
13288 pe_directive_secidx (int dummy ATTRIBUTE_UNUSED)
13295 if (exp.X_op == O_symbol)
13296 exp.X_op = O_secidx;
13298 emit_expr (&exp, 2);
13300 while (*input_line_pointer++ == ',');
13302 input_line_pointer--;
13303 demand_empty_rest_of_line ();
13307 /* Handle Rounding Control / SAE specifiers. */
13310 RC_SAE_specifier (const char *pstr)
13314 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
13316 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
13318 if (i.rounding.type != rc_none)
13320 as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name);
13324 if (i.vec_encoding == vex_encoding_default)
13325 i.vec_encoding = vex_encoding_evex512;
13326 else if (i.vec_encoding != vex_encoding_evex
13327 && i.vec_encoding != vex_encoding_evex512)
13330 i.rounding.type = RC_NamesTable[j].type;
13332 return (char *)(pstr + RC_NamesTable[j].len);
13339 /* Handle Vector operations. */
13342 check_VecOperations (char *op_string)
13344 const reg_entry *mask;
13351 if (*op_string == '{')
13355 /* Check broadcasts. */
13356 if (startswith (op_string, "1to"))
13358 unsigned int bcst_type;
13360 if (i.broadcast.type)
13361 goto duplicated_vec_op;
13364 if (*op_string == '8')
13366 else if (*op_string == '4')
13368 else if (*op_string == '2')
13370 else if (*op_string == '1'
13371 && *(op_string+1) == '6')
13376 else if (*op_string == '3'
13377 && *(op_string+1) == '2')
13384 as_bad (_("Unsupported broadcast: `%s'"), saved);
13389 if (i.vec_encoding == vex_encoding_default)
13390 i.vec_encoding = vex_encoding_evex;
13391 else if (i.vec_encoding != vex_encoding_evex
13392 && i.vec_encoding != vex_encoding_evex512)
13393 goto unknown_vec_op;
13395 i.broadcast.type = bcst_type;
13396 i.broadcast.operand = this_operand;
13398 /* For .insn a data size specifier may be appended. */
13399 if (dot_insn () && *op_string == ':')
13400 goto dot_insn_modifier;
13402 /* Check .insn special cases. */
13403 else if (dot_insn () && *op_string == ':')
13406 switch (op_string[1])
13411 if (i.memshift < 32)
13412 goto duplicated_vec_op;
13414 n = strtoul (op_string + 2, &end_op, 0);
13416 for (i.memshift = 0; !(n & 1); n >>= 1)
13418 if (i.memshift < 32 && n == 1)
13419 op_string = end_op;
13422 case 's': case 'u':
13423 /* This isn't really a "vector" operation, but a sign/size
13424 specifier for immediate operands of .insn. Note that AT&T
13425 syntax handles the same in i386_immediate(). */
13429 if (i.imm_bits[this_operand])
13430 goto duplicated_vec_op;
13432 n = strtoul (op_string + 2, &end_op, 0);
13433 if (n && n <= (flag_code == CODE_64BIT ? 64 : 32))
13435 i.imm_bits[this_operand] = n;
13436 if (op_string[1] == 's')
13437 i.flags[this_operand] |= Operand_Signed;
13438 op_string = end_op;
13443 /* Check masking operation. */
13444 else if ((mask = parse_register (op_string, &end_op)) != NULL)
13446 if (mask == &bad_reg)
13449 /* k0 can't be used for write mask. */
13450 if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num)
13452 as_bad (_("`%s%s' can't be used for write mask"),
13453 register_prefix, mask->reg_name);
13460 i.mask.operand = this_operand;
13462 else if (i.mask.reg->reg_num)
13463 goto duplicated_vec_op;
13468 /* Only "{z}" is allowed here. No need to check
13469 zeroing mask explicitly. */
13470 if (i.mask.operand != (unsigned int) this_operand)
13472 as_bad (_("invalid write mask `%s'"), saved);
13477 op_string = end_op;
13479 /* Check zeroing-flag for masking operation. */
13480 else if (*op_string == 'z')
13484 i.mask.reg = reg_k0;
13485 i.mask.zeroing = 1;
13486 i.mask.operand = this_operand;
13490 if (i.mask.zeroing)
13493 as_bad (_("duplicated `%s'"), saved);
13497 i.mask.zeroing = 1;
13499 /* Only "{%k}" is allowed here. No need to check mask
13500 register explicitly. */
13501 if (i.mask.operand != (unsigned int) this_operand)
13503 as_bad (_("invalid zeroing-masking `%s'"),
13511 else if (intel_syntax
13512 && (op_string = RC_SAE_specifier (op_string)) != NULL)
13513 i.rounding.modifier = true;
13515 goto unknown_vec_op;
13517 if (*op_string != '}')
13519 as_bad (_("missing `}' in `%s'"), saved);
13524 /* Strip whitespace since the addition of pseudo prefixes
13525 changed how the scrubber treats '{'. */
13526 if (is_space_char (*op_string))
13532 /* We don't know this one. */
13533 as_bad (_("unknown vector operation: `%s'"), saved);
13537 if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num)
13539 as_bad (_("zeroing-masking only allowed with write mask"));
13547 i386_immediate (char *imm_start)
13549 char *save_input_line_pointer;
13550 char *gotfree_input_line;
13553 i386_operand_type types;
13555 operand_type_set (&types, ~0);
13557 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
13559 as_bad (_("at most %d immediate operands are allowed"),
13560 MAX_IMMEDIATE_OPERANDS);
13564 exp = &im_expressions[i.imm_operands++];
13565 i.op[this_operand].imms = exp;
13567 if (is_space_char (*imm_start))
13570 save_input_line_pointer = input_line_pointer;
13571 input_line_pointer = imm_start;
13573 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
13574 if (gotfree_input_line)
13575 input_line_pointer = gotfree_input_line;
13577 expr_mode = expr_operator_none;
13578 exp_seg = expression (exp);
13580 /* For .insn immediates there may be a size specifier. */
13581 if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':'
13582 && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u'))
13585 unsigned long n = strtoul (input_line_pointer + 3, &e, 0);
13587 if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32))
13589 i.imm_bits[this_operand] = n;
13590 if (input_line_pointer[2] == 's')
13591 i.flags[this_operand] |= Operand_Signed;
13592 input_line_pointer = e + 1;
13596 SKIP_WHITESPACE ();
13597 if (*input_line_pointer)
13598 as_bad (_("junk `%s' after expression"), input_line_pointer);
13600 input_line_pointer = save_input_line_pointer;
13601 if (gotfree_input_line)
13603 free (gotfree_input_line);
13605 if (exp->X_op == O_constant)
13606 exp->X_op = O_illegal;
13609 if (exp_seg == reg_section)
13611 as_bad (_("illegal immediate register operand %s"), imm_start);
13615 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
13619 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
13620 i386_operand_type types, const char *imm_start)
13622 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
13625 as_bad (_("missing or invalid immediate expression `%s'"),
13629 else if (exp->X_op == O_constant)
13631 /* Size it properly later. */
13632 i.types[this_operand].bitfield.imm64 = 1;
13634 /* If not 64bit, sign/zero extend val, to account for wraparound
13636 if (expr_mode == expr_operator_present
13637 && flag_code != CODE_64BIT && !object_64bit)
13638 exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
13640 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13641 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
13642 && exp_seg != absolute_section
13643 && exp_seg != text_section
13644 && exp_seg != data_section
13645 && exp_seg != bss_section
13646 && exp_seg != undefined_section
13647 && !bfd_is_com_section (exp_seg))
13649 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
13655 /* This is an address. The size of the address will be
13656 determined later, depending on destination register,
13657 suffix, or the default for the section. */
13658 i.types[this_operand].bitfield.imm8 = 1;
13659 i.types[this_operand].bitfield.imm16 = 1;
13660 i.types[this_operand].bitfield.imm32 = 1;
13661 i.types[this_operand].bitfield.imm32s = 1;
13662 i.types[this_operand].bitfield.imm64 = 1;
13663 i.types[this_operand] = operand_type_and (i.types[this_operand],
13671 i386_scale (char *scale)
13674 char *save = input_line_pointer;
13676 input_line_pointer = scale;
13677 val = get_absolute_expression ();
13682 i.log2_scale_factor = 0;
13685 i.log2_scale_factor = 1;
13688 i.log2_scale_factor = 2;
13691 i.log2_scale_factor = 3;
13695 char sep = *input_line_pointer;
13697 *input_line_pointer = '\0';
13698 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
13700 *input_line_pointer = sep;
13701 input_line_pointer = save;
13705 if (i.log2_scale_factor != 0 && i.index_reg == 0)
13707 as_warn (_("scale factor of %d without an index register"),
13708 1 << i.log2_scale_factor);
13709 i.log2_scale_factor = 0;
13711 scale = input_line_pointer;
13712 input_line_pointer = save;
13717 i386_displacement (char *disp_start, char *disp_end)
13721 char *save_input_line_pointer;
13722 char *gotfree_input_line;
13724 i386_operand_type bigdisp, types = anydisp;
13727 if (i.disp_operands == MAX_MEMORY_OPERANDS)
13729 as_bad (_("at most %d displacement operands are allowed"),
13730 MAX_MEMORY_OPERANDS);
13734 operand_type_set (&bigdisp, 0);
13736 || i.types[this_operand].bitfield.baseindex
13737 || (current_templates.start->opcode_modifier.jump != JUMP
13738 && current_templates.start->opcode_modifier.jump != JUMP_DWORD))
13740 i386_addressing_mode ();
13741 override = (i.prefix[ADDR_PREFIX] != 0);
13742 if (flag_code == CODE_64BIT)
13744 bigdisp.bitfield.disp32 = 1;
13746 bigdisp.bitfield.disp64 = 1;
13748 else if ((flag_code == CODE_16BIT) ^ override)
13749 bigdisp.bitfield.disp16 = 1;
13751 bigdisp.bitfield.disp32 = 1;
13755 /* For PC-relative branches, the width of the displacement may be
13756 dependent upon data size, but is never dependent upon address size.
13757 Also make sure to not unintentionally match against a non-PC-relative
13758 branch template. */
13759 const insn_template *t = current_templates.start;
13760 bool has_intel64 = false;
13762 while (++t < current_templates.end)
13764 if (t->opcode_modifier.jump
13765 != current_templates.start->opcode_modifier.jump)
13767 if ((t->opcode_modifier.isa64 >= INTEL64))
13768 has_intel64 = true;
13770 current_templates.end = t;
13772 override = (i.prefix[DATA_PREFIX] != 0);
13773 if (flag_code == CODE_64BIT)
13775 if ((override || i.suffix == WORD_MNEM_SUFFIX)
13776 && (!intel64 || !has_intel64))
13777 bigdisp.bitfield.disp16 = 1;
13779 bigdisp.bitfield.disp32 = 1;
13784 override = (i.suffix == (flag_code != CODE_16BIT
13786 : LONG_MNEM_SUFFIX));
13787 bigdisp.bitfield.disp32 = 1;
13788 if ((flag_code == CODE_16BIT) ^ override)
13790 bigdisp.bitfield.disp32 = 0;
13791 bigdisp.bitfield.disp16 = 1;
13795 i.types[this_operand] = operand_type_or (i.types[this_operand],
13798 exp = &disp_expressions[i.disp_operands];
13799 i.op[this_operand].disps = exp;
13801 save_input_line_pointer = input_line_pointer;
13802 input_line_pointer = disp_start;
13803 END_STRING_AND_SAVE (disp_end);
13805 #ifndef GCC_ASM_O_HACK
13806 #define GCC_ASM_O_HACK 0
13809 END_STRING_AND_SAVE (disp_end + 1);
13810 if (i.types[this_operand].bitfield.baseIndex
13811 && displacement_string_end[-1] == '+')
13813 /* This hack is to avoid a warning when using the "o"
13814 constraint within gcc asm statements.
13817 #define _set_tssldt_desc(n,addr,limit,type) \
13818 __asm__ __volatile__ ( \
13819 "movw %w2,%0\n\t" \
13820 "movw %w1,2+%0\n\t" \
13821 "rorl $16,%1\n\t" \
13822 "movb %b1,4+%0\n\t" \
13823 "movb %4,5+%0\n\t" \
13824 "movb $0,6+%0\n\t" \
13825 "movb %h1,7+%0\n\t" \
13827 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
13829 This works great except that the output assembler ends
13830 up looking a bit weird if it turns out that there is
13831 no offset. You end up producing code that looks like:
13844 So here we provide the missing zero. */
13846 *displacement_string_end = '0';
13849 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
13850 if (gotfree_input_line)
13851 input_line_pointer = gotfree_input_line;
13853 expr_mode = expr_operator_none;
13854 exp_seg = expression (exp);
13856 SKIP_WHITESPACE ();
13857 if (*input_line_pointer)
13858 as_bad (_("junk `%s' after expression"), input_line_pointer);
13860 RESTORE_END_STRING (disp_end + 1);
13862 input_line_pointer = save_input_line_pointer;
13863 if (gotfree_input_line)
13865 free (gotfree_input_line);
13867 if (exp->X_op == O_constant || exp->X_op == O_register)
13868 exp->X_op = O_illegal;
13871 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
13873 RESTORE_END_STRING (disp_end);
13879 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
13880 i386_operand_type types, const char *disp_start)
13884 /* We do this to make sure that the section symbol is in
13885 the symbol table. We will ultimately change the relocation
13886 to be relative to the beginning of the section. */
13887 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
13888 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
13889 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
13891 if (exp->X_op != O_symbol)
13894 if (S_IS_LOCAL (exp->X_add_symbol)
13895 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
13896 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
13897 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
13898 exp->X_op = O_subtract;
13899 exp->X_op_symbol = GOT_symbol;
13900 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
13901 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
13902 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
13903 i.reloc[this_operand] = BFD_RELOC_64;
13905 i.reloc[this_operand] = BFD_RELOC_32;
13908 else if (exp->X_op == O_absent
13909 || exp->X_op == O_illegal
13910 || exp->X_op == O_big)
13913 as_bad (_("missing or invalid displacement expression `%s'"),
13918 else if (exp->X_op == O_constant)
13920 /* Sizing gets taken care of by optimize_disp().
13922 If not 64bit, sign/zero extend val, to account for wraparound
13924 if (expr_mode == expr_operator_present
13925 && flag_code != CODE_64BIT && !object_64bit)
13926 exp->X_add_number = extend_to_32bit_address (exp->X_add_number);
13929 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
13930 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
13931 && exp_seg != absolute_section
13932 && exp_seg != text_section
13933 && exp_seg != data_section
13934 && exp_seg != bss_section
13935 && exp_seg != undefined_section
13936 && !bfd_is_com_section (exp_seg))
13938 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
13943 else if (current_templates.start->opcode_modifier.jump == JUMP_BYTE)
13944 i.types[this_operand].bitfield.disp8 = 1;
13946 /* Check if this is a displacement only operand. */
13947 if (!i.types[this_operand].bitfield.baseindex)
13948 i.types[this_operand] =
13949 operand_type_or (operand_type_and_not (i.types[this_operand], anydisp),
13950 operand_type_and (i.types[this_operand], types));
13955 /* Return the active addressing mode, taking address override and
13956 registers forming the address into consideration. Update the
13957 address override prefix if necessary. */
13959 static enum flag_code
13960 i386_addressing_mode (void)
13962 enum flag_code addr_mode;
13964 if (i.prefix[ADDR_PREFIX])
13965 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
13966 else if (flag_code == CODE_16BIT
13967 && is_cpu (current_templates.start, CpuMPX)
13968 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
13969 from md_assemble() by "is not a valid base/index expression"
13970 when there is a base and/or index. */
13971 && !i.types[this_operand].bitfield.baseindex)
13973 /* MPX insn memory operands with neither base nor index must be forced
13974 to use 32-bit addressing in 16-bit mode. */
13975 addr_mode = CODE_32BIT;
13976 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
13978 gas_assert (!i.types[this_operand].bitfield.disp16);
13979 gas_assert (!i.types[this_operand].bitfield.disp32);
13983 addr_mode = flag_code;
13985 #if INFER_ADDR_PREFIX
13986 if (i.mem_operands == 0)
13988 /* Infer address prefix from the first memory operand. */
13989 const reg_entry *addr_reg = i.base_reg;
13991 if (addr_reg == NULL)
13992 addr_reg = i.index_reg;
13996 if (addr_reg->reg_type.bitfield.dword)
13997 addr_mode = CODE_32BIT;
13998 else if (flag_code != CODE_64BIT
13999 && addr_reg->reg_type.bitfield.word)
14000 addr_mode = CODE_16BIT;
14002 if (addr_mode != flag_code)
14004 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
14006 /* Change the size of any displacement too. At most one
14007 of Disp16 or Disp32 is set.
14008 FIXME. There doesn't seem to be any real need for
14009 separate Disp16 and Disp32 flags. The same goes for
14010 Imm16 and Imm32. Removing them would probably clean
14011 up the code quite a lot. */
14012 if (flag_code != CODE_64BIT
14013 && (i.types[this_operand].bitfield.disp16
14014 || i.types[this_operand].bitfield.disp32))
14016 static const i386_operand_type disp16_32 = {
14017 .bitfield = { .disp16 = 1, .disp32 = 1 }
14020 i.types[this_operand]
14021 = operand_type_xor (i.types[this_operand], disp16_32);
14032 /* Make sure the memory operand we've been dealt is valid.
14033 Return 1 on success, 0 on a failure. */
14036 i386_index_check (const char *operand_string)
14038 const char *kind = "base/index";
14039 enum flag_code addr_mode = i386_addressing_mode ();
14040 const insn_template *t = current_templates.end - 1;
14042 if (t->opcode_modifier.isstring)
14044 /* Memory operands of string insns are special in that they only allow
14045 a single register (rDI, rSI, or rBX) as their memory address. */
14046 const reg_entry *expected_reg;
14047 static const char di_si[][2][4] =
14053 static const char bx[][4] = { "ebx", "bx", "rbx" };
14055 kind = "string address";
14057 if (t->opcode_modifier.prefixok == PrefixRep)
14059 int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0;
14062 if (!t->operand_types[0].bitfield.baseindex
14063 || ((!i.mem_operands != !intel_syntax)
14064 && t->operand_types[1].bitfield.baseindex))
14067 = (const reg_entry *) str_hash_find (reg_hash,
14068 di_si[addr_mode][op == es_op]);
14072 = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]);
14074 if (i.base_reg != expected_reg
14076 || operand_type_check (i.types[this_operand], disp))
14078 /* The second memory operand must have the same size as
14082 && !((addr_mode == CODE_64BIT
14083 && i.base_reg->reg_type.bitfield.qword)
14084 || (addr_mode == CODE_32BIT
14085 ? i.base_reg->reg_type.bitfield.dword
14086 : i.base_reg->reg_type.bitfield.word)))
14089 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
14091 intel_syntax ? '[' : '(',
14093 expected_reg->reg_name,
14094 intel_syntax ? ']' : ')');
14101 as_bad (_("`%s' is not a valid %s expression"),
14102 operand_string, kind);
14107 t = current_templates.start;
14109 if (addr_mode != CODE_16BIT)
14111 /* 32-bit/64-bit checks. */
14112 if (i.disp_encoding == disp_encoding_16bit)
14115 as_bad (_("invalid `%s' prefix"),
14116 addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}");
14121 && ((addr_mode == CODE_64BIT
14122 ? !i.base_reg->reg_type.bitfield.qword
14123 : !i.base_reg->reg_type.bitfield.dword)
14124 || (i.index_reg && i.base_reg->reg_num == RegIP)
14125 || i.base_reg->reg_num == RegIZ))
14127 && !i.index_reg->reg_type.bitfield.xmmword
14128 && !i.index_reg->reg_type.bitfield.ymmword
14129 && !i.index_reg->reg_type.bitfield.zmmword
14130 && ((addr_mode == CODE_64BIT
14131 ? !i.index_reg->reg_type.bitfield.qword
14132 : !i.index_reg->reg_type.bitfield.dword)
14133 || !i.index_reg->reg_type.bitfield.baseindex)))
14136 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
14137 if (t->mnem_off == MN_bndmk
14138 || t->mnem_off == MN_bndldx
14139 || t->mnem_off == MN_bndstx
14140 || t->opcode_modifier.sib == SIBMEM)
14142 /* They cannot use RIP-relative addressing. */
14143 if (i.base_reg && i.base_reg->reg_num == RegIP)
14145 as_bad (_("`%s' cannot be used here"), operand_string);
14149 /* bndldx and bndstx ignore their scale factor. */
14150 if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx)
14151 && i.log2_scale_factor)
14152 as_warn (_("register scaling is being ignored here"));
14157 /* 16-bit checks. */
14158 if (i.disp_encoding == disp_encoding_32bit)
14162 && (!i.base_reg->reg_type.bitfield.word
14163 || !i.base_reg->reg_type.bitfield.baseindex))
14165 && (!i.index_reg->reg_type.bitfield.word
14166 || !i.index_reg->reg_type.bitfield.baseindex
14168 && i.base_reg->reg_num < 6
14169 && i.index_reg->reg_num >= 6
14170 && i.log2_scale_factor == 0))))
14177 /* Handle vector immediates. */
14180 RC_SAE_immediate (const char *imm_start)
14182 const char *pstr = imm_start;
14187 pstr = RC_SAE_specifier (pstr + 1);
14191 if (*pstr++ != '}')
14193 as_bad (_("Missing '}': '%s'"), imm_start);
14196 /* RC/SAE immediate string should contain nothing more. */;
14199 as_bad (_("Junk after '}': '%s'"), imm_start);
14203 /* Internally this doesn't count as an operand. */
14209 static INLINE bool starts_memory_operand (char c)
14212 || is_name_beginner (c)
14213 || strchr ("([\"+-!~", c);
14216 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
14220 i386_att_operand (char *operand_string)
14222 const reg_entry *r;
14224 char *op_string = operand_string;
14226 if (is_space_char (*op_string))
14229 /* We check for an absolute prefix (differentiating,
14230 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
14231 if (*op_string == ABSOLUTE_PREFIX
14232 && current_templates.start->opcode_modifier.jump)
14235 if (is_space_char (*op_string))
14237 i.jumpabsolute = true;
14240 /* Check if operand is a register. */
14241 if ((r = parse_register (op_string, &end_op)) != NULL)
14243 i386_operand_type temp;
14248 /* Check for a segment override by searching for ':' after a
14249 segment register. */
14250 op_string = end_op;
14251 if (is_space_char (*op_string))
14253 if (*op_string == ':' && r->reg_type.bitfield.class == SReg)
14255 i.seg[i.mem_operands] = r;
14257 /* Skip the ':' and whitespace. */
14259 if (is_space_char (*op_string))
14262 /* Handle case of %es:*foo. */
14263 if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX
14264 && current_templates.start->opcode_modifier.jump)
14267 if (is_space_char (*op_string))
14269 i.jumpabsolute = true;
14272 if (!starts_memory_operand (*op_string))
14274 as_bad (_("bad memory operand `%s'"), op_string);
14277 goto do_memory_reference;
14280 /* Handle vector operations. */
14281 if (*op_string == '{')
14283 op_string = check_VecOperations (op_string);
14284 if (op_string == NULL)
14290 as_bad (_("junk `%s' after register"), op_string);
14294 /* Reject pseudo registers for .insn. */
14295 if (dot_insn () && r->reg_type.bitfield.class == ClassNone)
14297 as_bad (_("`%s%s' cannot be used here"),
14298 register_prefix, r->reg_name);
14302 temp = r->reg_type;
14303 temp.bitfield.baseindex = 0;
14304 i.types[this_operand] = operand_type_or (i.types[this_operand],
14306 i.types[this_operand].bitfield.unspecified = 0;
14307 i.op[this_operand].regs = r;
14310 /* A GPR may follow an RC or SAE immediate only if a (vector) register
14311 operand was also present earlier on. */
14312 if (i.rounding.type != rc_none && temp.bitfield.class == Reg
14313 && i.reg_operands == 1)
14317 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j)
14318 if (i.rounding.type == RC_NamesTable[j].type)
14320 as_bad (_("`%s': misplaced `{%s}'"),
14321 insn_name (current_templates.start), RC_NamesTable[j].name);
14325 else if (*op_string == REGISTER_PREFIX)
14327 as_bad (_("bad register name `%s'"), op_string);
14330 else if (*op_string == IMMEDIATE_PREFIX)
14333 if (i.jumpabsolute)
14335 as_bad (_("immediate operand illegal with absolute jump"));
14338 if (!i386_immediate (op_string))
14340 if (i.rounding.type != rc_none)
14342 as_bad (_("`%s': RC/SAE operand must follow immediate operands"),
14343 insn_name (current_templates.start));
14347 else if (RC_SAE_immediate (operand_string))
14349 /* If it is a RC or SAE immediate, do the necessary placement check:
14350 Only another immediate or a GPR may precede it. */
14351 if (i.mem_operands || i.reg_operands + i.imm_operands > 1
14352 || (i.reg_operands == 1
14353 && i.op[0].regs->reg_type.bitfield.class != Reg))
14355 as_bad (_("`%s': misplaced `%s'"),
14356 insn_name (current_templates.start), operand_string);
14360 else if (starts_memory_operand (*op_string))
14362 /* This is a memory reference of some sort. */
14365 /* Start and end of displacement string expression (if found). */
14366 char *displacement_string_start;
14367 char *displacement_string_end;
14369 do_memory_reference:
14370 /* Check for base index form. We detect the base index form by
14371 looking for an ')' at the end of the operand, searching
14372 for the '(' matching it, and finding a REGISTER_PREFIX or ','
14374 base_string = op_string + strlen (op_string);
14376 /* Handle vector operations. */
14378 if (is_space_char (*base_string))
14381 if (*base_string == '}')
14383 char *vop_start = NULL;
14385 while (base_string-- > op_string)
14387 if (*base_string == '"')
14389 if (*base_string != '{')
14392 vop_start = base_string;
14395 if (is_space_char (*base_string))
14398 if (*base_string != '}')
14406 as_bad (_("unbalanced figure braces"));
14410 if (check_VecOperations (vop_start) == NULL)
14414 /* If we only have a displacement, set-up for it to be parsed later. */
14415 displacement_string_start = op_string;
14416 displacement_string_end = base_string + 1;
14418 if (*base_string == ')')
14421 unsigned int parens_not_balanced = 0;
14422 bool in_quotes = false;
14424 /* We've already checked that the number of left & right ()'s are
14425 equal, and that there's a matching set of double quotes. */
14426 end_op = base_string;
14427 for (temp_string = op_string; temp_string < end_op; temp_string++)
14429 if (*temp_string == '\\' && temp_string[1] == '"')
14431 else if (*temp_string == '"')
14432 in_quotes = !in_quotes;
14433 else if (!in_quotes)
14435 if (*temp_string == '(' && !parens_not_balanced++)
14436 base_string = temp_string;
14437 if (*temp_string == ')')
14438 --parens_not_balanced;
14442 temp_string = base_string;
14444 /* Skip past '(' and whitespace. */
14445 gas_assert (*base_string == '(');
14447 if (is_space_char (*base_string))
14450 if (*base_string == ','
14451 || ((i.base_reg = parse_register (base_string, &end_op))
14454 displacement_string_end = temp_string;
14456 i.types[this_operand].bitfield.baseindex = 1;
14460 if (i.base_reg == &bad_reg)
14462 base_string = end_op;
14463 if (is_space_char (*base_string))
14467 /* There may be an index reg or scale factor here. */
14468 if (*base_string == ',')
14471 if (is_space_char (*base_string))
14474 if ((i.index_reg = parse_register (base_string, &end_op))
14477 if (i.index_reg == &bad_reg)
14479 base_string = end_op;
14480 if (is_space_char (*base_string))
14482 if (*base_string == ',')
14485 if (is_space_char (*base_string))
14488 else if (*base_string != ')')
14490 as_bad (_("expecting `,' or `)' "
14491 "after index register in `%s'"),
14496 else if (*base_string == REGISTER_PREFIX)
14498 end_op = strchr (base_string, ',');
14501 as_bad (_("bad register name `%s'"), base_string);
14505 /* Check for scale factor. */
14506 if (*base_string != ')')
14508 char *end_scale = i386_scale (base_string);
14513 base_string = end_scale;
14514 if (is_space_char (*base_string))
14516 if (*base_string != ')')
14518 as_bad (_("expecting `)' "
14519 "after scale factor in `%s'"),
14524 else if (!i.index_reg)
14526 as_bad (_("expecting index register or scale factor "
14527 "after `,'; got '%c'"),
14532 else if (*base_string != ')')
14534 as_bad (_("expecting `,' or `)' "
14535 "after base register in `%s'"),
14540 else if (*base_string == REGISTER_PREFIX)
14542 end_op = strchr (base_string, ',');
14545 as_bad (_("bad register name `%s'"), base_string);
14550 /* If there's an expression beginning the operand, parse it,
14551 assuming displacement_string_start and
14552 displacement_string_end are meaningful. */
14553 if (displacement_string_start != displacement_string_end)
14555 if (!i386_displacement (displacement_string_start,
14556 displacement_string_end))
14560 /* Special case for (%dx) while doing input/output op. */
14562 && i.base_reg->reg_type.bitfield.instance == RegD
14563 && i.base_reg->reg_type.bitfield.word
14564 && i.index_reg == 0
14565 && i.log2_scale_factor == 0
14566 && i.seg[i.mem_operands] == 0
14567 && !operand_type_check (i.types[this_operand], disp))
14569 i.types[this_operand] = i.base_reg->reg_type;
14570 i.op[this_operand].regs = i.base_reg;
14572 i.input_output_operand = true;
14576 if (i386_index_check (operand_string) == 0)
14578 i.flags[this_operand] |= Operand_Mem;
14583 /* It's not a memory operand; argh! */
14584 as_bad (_("invalid char %s beginning operand %d `%s'"),
14585 output_invalid (*op_string),
14590 return 1; /* Normal return. */
14593 /* Calculate the maximum variable size (i.e., excluding fr_fix)
14594 that an rs_machine_dependent frag may reach. */
14597 i386_frag_max_var (fragS *frag)
14599 /* The only relaxable frags are for jumps.
14600 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
14601 gas_assert (frag->fr_type == rs_machine_dependent);
14602 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
14605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14607 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
14609 /* STT_GNU_IFUNC symbol must go through PLT. */
14610 if ((symbol_get_bfdsym (fr_symbol)->flags
14611 & BSF_GNU_INDIRECT_FUNCTION) != 0)
14614 if (!S_IS_EXTERNAL (fr_symbol))
14615 /* Symbol may be weak or local. */
14616 return !S_IS_WEAK (fr_symbol);
14618 /* Global symbols with non-default visibility can't be preempted. */
14619 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
14622 if (fr_var != NO_RELOC)
14623 switch ((enum bfd_reloc_code_real) fr_var)
14625 case BFD_RELOC_386_PLT32:
14626 case BFD_RELOC_X86_64_PLT32:
14627 /* Symbol with PLT relocation may be preempted. */
14633 /* Global symbols with default visibility in a shared library may be
14634 preempted by another definition. */
14639 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
14640 Note also work for Skylake and Cascadelake.
14641 ---------------------------------------------------------------------
14642 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
14643 | ------ | ----------- | ------- | -------- |
14645 | Jno | N | N | Y |
14646 | Jc/Jb | Y | N | Y |
14647 | Jae/Jnb | Y | N | Y |
14648 | Je/Jz | Y | Y | Y |
14649 | Jne/Jnz | Y | Y | Y |
14650 | Jna/Jbe | Y | N | Y |
14651 | Ja/Jnbe | Y | N | Y |
14653 | Jns | N | N | Y |
14654 | Jp/Jpe | N | N | Y |
14655 | Jnp/Jpo | N | N | Y |
14656 | Jl/Jnge | Y | Y | Y |
14657 | Jge/Jnl | Y | Y | Y |
14658 | Jle/Jng | Y | Y | Y |
14659 | Jg/Jnle | Y | Y | Y |
14660 --------------------------------------------------------------------- */
14662 i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc)
14664 if (mf_cmp == mf_cmp_alu_cmp)
14665 return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna)
14666 || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle);
14667 if (mf_cmp == mf_cmp_incdec)
14668 return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl
14669 || mf_jcc == mf_jcc_jle);
14670 if (mf_cmp == mf_cmp_test_and)
14675 /* Return the next non-empty frag. */
14678 i386_next_non_empty_frag (fragS *fragP)
14680 /* There may be a frag with a ".fill 0" when there is no room in
14681 the current frag for frag_grow in output_insn. */
14682 for (fragP = fragP->fr_next;
14684 && fragP->fr_type == rs_fill
14685 && fragP->fr_fix == 0);
14686 fragP = fragP->fr_next)
14691 /* Return the next jcc frag after BRANCH_PADDING. */
14694 i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP)
14696 fragS *branch_fragP;
14700 if (pad_fragP->fr_type == rs_machine_dependent
14701 && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype)
14702 == BRANCH_PADDING))
14704 branch_fragP = i386_next_non_empty_frag (pad_fragP);
14705 if (branch_fragP->fr_type != rs_machine_dependent)
14707 if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP
14708 && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type,
14709 pad_fragP->tc_frag_data.mf_type))
14710 return branch_fragP;
14716 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
14719 i386_classify_machine_dependent_frag (fragS *fragP)
14723 fragS *branch_fragP;
14725 unsigned int max_prefix_length;
14727 if (fragP->tc_frag_data.classified)
14730 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
14731 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
14732 for (next_fragP = fragP;
14733 next_fragP != NULL;
14734 next_fragP = next_fragP->fr_next)
14736 next_fragP->tc_frag_data.classified = 1;
14737 if (next_fragP->fr_type == rs_machine_dependent)
14738 switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype))
14740 case BRANCH_PADDING:
14741 /* The BRANCH_PADDING frag must be followed by a branch
14743 branch_fragP = i386_next_non_empty_frag (next_fragP);
14744 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
14746 case FUSED_JCC_PADDING:
14747 /* Check if this is a fused jcc:
14749 CMP like instruction
14753 cmp_fragP = i386_next_non_empty_frag (next_fragP);
14754 pad_fragP = i386_next_non_empty_frag (cmp_fragP);
14755 branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP);
14758 /* The BRANCH_PADDING frag is merged with the
14759 FUSED_JCC_PADDING frag. */
14760 next_fragP->tc_frag_data.u.branch_fragP = branch_fragP;
14761 /* CMP like instruction size. */
14762 next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix;
14763 frag_wane (pad_fragP);
14764 /* Skip to branch_fragP. */
14765 next_fragP = branch_fragP;
14767 else if (next_fragP->tc_frag_data.max_prefix_length)
14769 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
14771 next_fragP->fr_subtype
14772 = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0);
14773 next_fragP->tc_frag_data.max_bytes
14774 = next_fragP->tc_frag_data.max_prefix_length;
14775 /* This will be updated in the BRANCH_PREFIX scan. */
14776 next_fragP->tc_frag_data.max_prefix_length = 0;
14779 frag_wane (next_fragP);
14784 /* Stop if there is no BRANCH_PREFIX. */
14785 if (!align_branch_prefix_size)
14788 /* Scan for BRANCH_PREFIX. */
14789 for (; fragP != NULL; fragP = fragP->fr_next)
14791 if (fragP->fr_type != rs_machine_dependent
14792 || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
14796 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
14797 COND_JUMP_PREFIX. */
14798 max_prefix_length = 0;
14799 for (next_fragP = fragP;
14800 next_fragP != NULL;
14801 next_fragP = next_fragP->fr_next)
14803 if (next_fragP->fr_type == rs_fill)
14804 /* Skip rs_fill frags. */
14806 else if (next_fragP->fr_type != rs_machine_dependent)
14807 /* Stop for all other frags. */
14810 /* rs_machine_dependent frags. */
14811 if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
14814 /* Count BRANCH_PREFIX frags. */
14815 if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE)
14817 max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE;
14818 frag_wane (next_fragP);
14822 += next_fragP->tc_frag_data.max_bytes;
14824 else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
14826 || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
14827 == FUSED_JCC_PADDING))
14829 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
14830 fragP->tc_frag_data.u.padding_fragP = next_fragP;
14834 /* Stop for other rs_machine_dependent frags. */
14838 fragP->tc_frag_data.max_prefix_length = max_prefix_length;
14840 /* Skip to the next frag. */
14841 fragP = next_fragP;
14845 /* Compute padding size for
14848 CMP like instruction
14850 COND_JUMP/UNCOND_JUMP
14855 COND_JUMP/UNCOND_JUMP
14859 i386_branch_padding_size (fragS *fragP, offsetT address)
14861 unsigned int offset, size, padding_size;
14862 fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP;
14864 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
14866 address = fragP->fr_address;
14867 address += fragP->fr_fix;
14869 /* CMP like instrunction size. */
14870 size = fragP->tc_frag_data.cmp_size;
14872 /* The base size of the branch frag. */
14873 size += branch_fragP->fr_fix;
14875 /* Add opcode and displacement bytes for the rs_machine_dependent
14877 if (branch_fragP->fr_type == rs_machine_dependent)
14878 size += md_relax_table[branch_fragP->fr_subtype].rlx_length;
14880 /* Check if branch is within boundary and doesn't end at the last
14882 offset = address & ((1U << align_branch_power) - 1);
14883 if ((offset + size) >= (1U << align_branch_power))
14884 /* Padding needed to avoid crossing boundary. */
14885 padding_size = (1U << align_branch_power) - offset;
14887 /* No padding needed. */
14890 /* The return value may be saved in tc_frag_data.length which is
14892 if (!fits_in_unsigned_byte (padding_size))
14895 return padding_size;
14898 /* i386_generic_table_relax_frag()
14900 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
14901 grow/shrink padding to align branch frags. Hand others to
14905 i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch)
14907 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
14908 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
14910 long padding_size = i386_branch_padding_size (fragP, 0);
14911 long grow = padding_size - fragP->tc_frag_data.length;
14913 /* When the BRANCH_PREFIX frag is used, the computed address
14914 must match the actual address and there should be no padding. */
14915 if (fragP->tc_frag_data.padding_address
14916 && (fragP->tc_frag_data.padding_address != fragP->fr_address
14920 /* Update the padding size. */
14922 fragP->tc_frag_data.length = padding_size;
14926 else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
14928 fragS *padding_fragP, *next_fragP;
14929 long padding_size, left_size, last_size;
14931 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
14932 if (!padding_fragP)
14933 /* Use the padding set by the leading BRANCH_PREFIX frag. */
14934 return (fragP->tc_frag_data.length
14935 - fragP->tc_frag_data.last_length);
14937 /* Compute the relative address of the padding frag in the very
14938 first time where the BRANCH_PREFIX frag sizes are zero. */
14939 if (!fragP->tc_frag_data.padding_address)
14940 fragP->tc_frag_data.padding_address
14941 = padding_fragP->fr_address - (fragP->fr_address - stretch);
14943 /* First update the last length from the previous interation. */
14944 left_size = fragP->tc_frag_data.prefix_length;
14945 for (next_fragP = fragP;
14946 next_fragP != padding_fragP;
14947 next_fragP = next_fragP->fr_next)
14948 if (next_fragP->fr_type == rs_machine_dependent
14949 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
14954 int max = next_fragP->tc_frag_data.max_bytes;
14958 if (max > left_size)
14963 next_fragP->tc_frag_data.last_length = size;
14967 next_fragP->tc_frag_data.last_length = 0;
14970 /* Check the padding size for the padding frag. */
14971 padding_size = i386_branch_padding_size
14972 (padding_fragP, (fragP->fr_address
14973 + fragP->tc_frag_data.padding_address));
14975 last_size = fragP->tc_frag_data.prefix_length;
14976 /* Check if there is change from the last interation. */
14977 if (padding_size == last_size)
14979 /* Update the expected address of the padding frag. */
14980 padding_fragP->tc_frag_data.padding_address
14981 = (fragP->fr_address + padding_size
14982 + fragP->tc_frag_data.padding_address);
14986 if (padding_size > fragP->tc_frag_data.max_prefix_length)
14988 /* No padding if there is no sufficient room. Clear the
14989 expected address of the padding frag. */
14990 padding_fragP->tc_frag_data.padding_address = 0;
14994 /* Store the expected address of the padding frag. */
14995 padding_fragP->tc_frag_data.padding_address
14996 = (fragP->fr_address + padding_size
14997 + fragP->tc_frag_data.padding_address);
14999 fragP->tc_frag_data.prefix_length = padding_size;
15001 /* Update the length for the current interation. */
15002 left_size = padding_size;
15003 for (next_fragP = fragP;
15004 next_fragP != padding_fragP;
15005 next_fragP = next_fragP->fr_next)
15006 if (next_fragP->fr_type == rs_machine_dependent
15007 && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)
15012 int max = next_fragP->tc_frag_data.max_bytes;
15016 if (max > left_size)
15021 next_fragP->tc_frag_data.length = size;
15025 next_fragP->tc_frag_data.length = 0;
15028 return (fragP->tc_frag_data.length
15029 - fragP->tc_frag_data.last_length);
15031 return relax_frag (segment, fragP, stretch);
15034 /* md_estimate_size_before_relax()
15036 Called just before relax() for rs_machine_dependent frags. The x86
15037 assembler uses these frags to handle variable size jump
15040 Any symbol that is now undefined will not become defined.
15041 Return the correct fr_subtype in the frag.
15042 Return the initial "guess for variable size of frag" to caller.
15043 The guess is actually the growth beyond the fixed part. Whatever
15044 we do to grow the fixed or variable part contributes to our
15048 md_estimate_size_before_relax (fragS *fragP, segT segment)
15050 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15051 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX
15052 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING)
15054 i386_classify_machine_dependent_frag (fragP);
15055 return fragP->tc_frag_data.length;
15058 /* We've already got fragP->fr_subtype right; all we have to do is
15059 check for un-relaxable symbols. On an ELF system, we can't relax
15060 an externally visible symbol, because it may be overridden by a
15062 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
15063 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15065 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
15068 #if defined (OBJ_COFF) && defined (TE_PE)
15069 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
15070 && S_IS_WEAK (fragP->fr_symbol))
15074 /* Symbol is undefined in this segment, or we need to keep a
15075 reloc so that weak symbols can be overridden. */
15076 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
15077 enum bfd_reloc_code_real reloc_type;
15078 unsigned char *opcode;
15082 if (fragP->fr_var != NO_RELOC)
15083 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
15084 else if (size == 2)
15085 reloc_type = BFD_RELOC_16_PCREL;
15086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15087 else if (fragP->tc_frag_data.code == CODE_64BIT
15088 && fragP->fr_offset == 0
15089 && need_plt32_p (fragP->fr_symbol))
15090 reloc_type = BFD_RELOC_X86_64_PLT32;
15093 reloc_type = BFD_RELOC_32_PCREL;
15095 old_fr_fix = fragP->fr_fix;
15096 opcode = (unsigned char *) fragP->fr_opcode;
15098 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
15101 /* Make jmp (0xeb) a (d)word displacement jump. */
15103 fragP->fr_fix += size;
15104 fixP = fix_new (fragP, old_fr_fix, size,
15106 fragP->fr_offset, 1,
15112 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
15114 /* Negate the condition, and branch past an
15115 unconditional jump. */
15118 /* Insert an unconditional jump. */
15120 /* We added two extra opcode bytes, and have a two byte
15122 fragP->fr_fix += 2 + 2;
15123 fix_new (fragP, old_fr_fix + 2, 2,
15125 fragP->fr_offset, 1,
15129 /* Fall through. */
15132 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
15134 fragP->fr_fix += 1;
15135 fixP = fix_new (fragP, old_fr_fix, 1,
15137 fragP->fr_offset, 1,
15138 BFD_RELOC_8_PCREL);
15139 fixP->fx_signed = 1;
15143 /* This changes the byte-displacement jump 0x7N
15144 to the (d)word-displacement jump 0x0f,0x8N. */
15145 opcode[1] = opcode[0] + 0x10;
15146 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15147 /* We've added an opcode byte. */
15148 fragP->fr_fix += 1 + size;
15149 fixP = fix_new (fragP, old_fr_fix + 1, size,
15151 fragP->fr_offset, 1,
15156 BAD_CASE (fragP->fr_subtype);
15160 /* All jumps handled here are signed, but don't unconditionally use a
15161 signed limit check for 32 and 16 bit jumps as we want to allow wrap
15162 around at 4G (outside of 64-bit mode) and 64k. */
15163 if (size == 4 && flag_code == CODE_64BIT)
15164 fixP->fx_signed = 1;
15167 return fragP->fr_fix - old_fr_fix;
15170 /* Guess size depending on current relax state. Initially the relax
15171 state will correspond to a short jump and we return 1, because
15172 the variable part of the frag (the branch offset) is one byte
15173 long. However, we can relax a section more than once and in that
15174 case we must either set fr_subtype back to the unrelaxed state,
15175 or return the value for the appropriate branch. */
15176 return md_relax_table[fragP->fr_subtype].rlx_length;
15179 /* Called after relax() is finished.
15181 In: Address of frag.
15182 fr_type == rs_machine_dependent.
15183 fr_subtype is what the address relaxed to.
15185 Out: Any fixSs and constants are set up.
15186 Caller will turn frag into a ".space 0". */
15189 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
15192 unsigned char *opcode;
15193 unsigned char *where_to_put_displacement = NULL;
15194 offsetT target_address;
15195 offsetT opcode_address;
15196 unsigned int extension = 0;
15197 offsetT displacement_from_opcode_start;
15199 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING
15200 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING
15201 || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15203 /* Generate nop padding. */
15204 unsigned int size = fragP->tc_frag_data.length;
15207 if (size > fragP->tc_frag_data.max_bytes)
15213 const char *branch = "branch";
15214 const char *prefix = "";
15215 fragS *padding_fragP;
15216 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)
15219 padding_fragP = fragP->tc_frag_data.u.padding_fragP;
15220 switch (fragP->tc_frag_data.default_prefix)
15225 case CS_PREFIX_OPCODE:
15228 case DS_PREFIX_OPCODE:
15231 case ES_PREFIX_OPCODE:
15234 case FS_PREFIX_OPCODE:
15237 case GS_PREFIX_OPCODE:
15240 case SS_PREFIX_OPCODE:
15245 msg = _("%s:%u: add %d%s at 0x%llx to align "
15246 "%s within %d-byte boundary\n");
15248 msg = _("%s:%u: add additional %d%s at 0x%llx to "
15249 "align %s within %d-byte boundary\n");
15253 padding_fragP = fragP;
15254 msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align "
15255 "%s within %d-byte boundary\n");
15259 switch (padding_fragP->tc_frag_data.branch_type)
15261 case align_branch_jcc:
15264 case align_branch_fused:
15265 branch = "fused jcc";
15267 case align_branch_jmp:
15270 case align_branch_call:
15273 case align_branch_indirect:
15274 branch = "indiret branch";
15276 case align_branch_ret:
15283 fprintf (stdout, msg,
15284 fragP->fr_file, fragP->fr_line, size, prefix,
15285 (long long) fragP->fr_address, branch,
15286 1 << align_branch_power);
15288 if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX)
15289 memset (fragP->fr_opcode,
15290 fragP->tc_frag_data.default_prefix, size);
15292 i386_generate_nops (fragP, (char *) fragP->fr_opcode,
15294 fragP->fr_fix += size;
15299 opcode = (unsigned char *) fragP->fr_opcode;
15301 /* Address we want to reach in file space. */
15302 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
15304 /* Address opcode resides at in file space. */
15305 opcode_address = fragP->fr_address + fragP->fr_fix;
15307 /* Displacement from opcode start to fill into instruction. */
15308 displacement_from_opcode_start = target_address - opcode_address;
15310 if ((fragP->fr_subtype & BIG) == 0)
15312 /* Don't have to change opcode. */
15313 extension = 1; /* 1 opcode + 1 displacement */
15314 where_to_put_displacement = &opcode[1];
15318 if (no_cond_jump_promotion
15319 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
15320 as_warn_where (fragP->fr_file, fragP->fr_line,
15321 _("long jump required"));
15323 switch (fragP->fr_subtype)
15325 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
15326 extension = 4; /* 1 opcode + 4 displacement */
15328 where_to_put_displacement = &opcode[1];
15331 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
15332 extension = 2; /* 1 opcode + 2 displacement */
15334 where_to_put_displacement = &opcode[1];
15337 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
15338 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
15339 extension = 5; /* 2 opcode + 4 displacement */
15340 opcode[1] = opcode[0] + 0x10;
15341 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15342 where_to_put_displacement = &opcode[2];
15345 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
15346 extension = 3; /* 2 opcode + 2 displacement */
15347 opcode[1] = opcode[0] + 0x10;
15348 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
15349 where_to_put_displacement = &opcode[2];
15352 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
15357 where_to_put_displacement = &opcode[3];
15361 BAD_CASE (fragP->fr_subtype);
15366 /* If size if less then four we are sure that the operand fits,
15367 but if it's 4, then it could be that the displacement is larger
15369 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
15371 && ((addressT) (displacement_from_opcode_start - extension
15372 + ((addressT) 1 << 31))
15373 > (((addressT) 2 << 31) - 1)))
15375 as_bad_where (fragP->fr_file, fragP->fr_line,
15376 _("jump target out of range"));
15377 /* Make us emit 0. */
15378 displacement_from_opcode_start = extension;
15380 /* Now put displacement after opcode. */
15381 md_number_to_chars ((char *) where_to_put_displacement,
15382 (valueT) (displacement_from_opcode_start - extension),
15383 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
15384 fragP->fr_fix += extension;
15387 /* Apply a fixup (fixP) to segment data, once it has been determined
15388 by our caller that we have all the info we need to fix it up.
15390 Parameter valP is the pointer to the value of the bits.
15392 On the 386, immediates, displacements, and data pointers are all in
15393 the same (little-endian) format, so we don't need to care about which
15394 we are handling. */
15397 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
15399 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
15400 valueT value = *valP;
15402 #if !defined (TE_Mach)
15403 if (fixP->fx_pcrel)
15405 switch (fixP->fx_r_type)
15411 fixP->fx_r_type = BFD_RELOC_64_PCREL;
15414 case BFD_RELOC_X86_64_32S:
15415 fixP->fx_r_type = BFD_RELOC_32_PCREL;
15418 fixP->fx_r_type = BFD_RELOC_16_PCREL;
15421 fixP->fx_r_type = BFD_RELOC_8_PCREL;
15426 if (fixP->fx_addsy != NULL
15427 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
15428 || fixP->fx_r_type == BFD_RELOC_64_PCREL
15429 || fixP->fx_r_type == BFD_RELOC_16_PCREL
15430 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
15431 && !use_rela_relocations)
15433 /* This is a hack. There should be a better way to handle this.
15434 This covers for the fact that bfd_install_relocation will
15435 subtract the current location (for partial_inplace, PC relative
15436 relocations); see more below. */
15440 || OUTPUT_FLAVOR == bfd_target_coff_flavour
15443 value += fixP->fx_where + fixP->fx_frag->fr_address;
15445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15448 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
15450 if ((sym_seg == seg
15451 || (symbol_section_p (fixP->fx_addsy)
15452 && sym_seg != absolute_section))
15453 && !generic_force_reloc (fixP))
15455 /* Yes, we add the values in twice. This is because
15456 bfd_install_relocation subtracts them out again. I think
15457 bfd_install_relocation is broken, but I don't dare change
15459 value += fixP->fx_where + fixP->fx_frag->fr_address;
15463 #if defined (OBJ_COFF) && defined (TE_PE)
15464 /* For some reason, the PE format does not store a
15465 section address offset for a PC relative symbol. */
15466 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
15467 || S_IS_WEAK (fixP->fx_addsy))
15468 value += md_pcrel_from (fixP);
15471 #if defined (OBJ_COFF) && defined (TE_PE)
15472 if (fixP->fx_addsy != NULL
15473 && S_IS_WEAK (fixP->fx_addsy)
15474 /* PR 16858: Do not modify weak function references. */
15475 && ! fixP->fx_pcrel)
15477 #if !defined (TE_PEP)
15478 /* For x86 PE weak function symbols are neither PC-relative
15479 nor do they set S_IS_FUNCTION. So the only reliable way
15480 to detect them is to check the flags of their containing
15482 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
15483 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
15487 value -= S_GET_VALUE (fixP->fx_addsy);
15491 /* Fix a few things - the dynamic linker expects certain values here,
15492 and we must not disappoint it. */
15493 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15494 if (IS_ELF && fixP->fx_addsy)
15495 switch (fixP->fx_r_type)
15497 case BFD_RELOC_386_PLT32:
15498 case BFD_RELOC_X86_64_PLT32:
15499 /* Make the jump instruction point to the address of the operand.
15500 At runtime we merely add the offset to the actual PLT entry.
15501 NB: Subtract the offset size only for jump instructions. */
15502 if (fixP->fx_pcrel)
15506 case BFD_RELOC_386_TLS_GD:
15507 case BFD_RELOC_386_TLS_LDM:
15508 case BFD_RELOC_386_TLS_IE_32:
15509 case BFD_RELOC_386_TLS_IE:
15510 case BFD_RELOC_386_TLS_GOTIE:
15511 case BFD_RELOC_386_TLS_GOTDESC:
15512 case BFD_RELOC_X86_64_TLSGD:
15513 case BFD_RELOC_X86_64_TLSLD:
15514 case BFD_RELOC_X86_64_GOTTPOFF:
15515 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
15516 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
15517 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
15518 value = 0; /* Fully resolved at runtime. No addend. */
15520 case BFD_RELOC_386_TLS_LE:
15521 case BFD_RELOC_386_TLS_LDO_32:
15522 case BFD_RELOC_386_TLS_LE_32:
15523 case BFD_RELOC_X86_64_DTPOFF32:
15524 case BFD_RELOC_X86_64_DTPOFF64:
15525 case BFD_RELOC_X86_64_TPOFF32:
15526 case BFD_RELOC_X86_64_TPOFF64:
15527 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15530 case BFD_RELOC_386_TLS_DESC_CALL:
15531 case BFD_RELOC_X86_64_TLSDESC_CALL:
15532 value = 0; /* Fully resolved at runtime. No addend. */
15533 S_SET_THREAD_LOCAL (fixP->fx_addsy);
15537 case BFD_RELOC_VTABLE_INHERIT:
15538 case BFD_RELOC_VTABLE_ENTRY:
15545 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
15547 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
15549 value = extend_to_32bit_address (value);
15552 #endif /* !defined (TE_Mach) */
15554 /* Are we finished with this relocation now? */
15555 if (fixP->fx_addsy == NULL)
15558 switch (fixP->fx_r_type)
15560 case BFD_RELOC_X86_64_32S:
15561 fixP->fx_signed = 1;
15568 #if defined (OBJ_COFF) && defined (TE_PE)
15569 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
15572 /* Remember value for tc_gen_reloc. */
15573 fixP->fx_addnumber = value;
15574 /* Clear out the frag for now. */
15578 else if (use_rela_relocations)
15580 if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC)
15581 fixP->fx_no_overflow = 1;
15582 /* Remember value for tc_gen_reloc. */
15583 fixP->fx_addnumber = value;
15587 md_number_to_chars (p, value, fixP->fx_size);
15591 md_atof (int type, char *litP, int *sizeP)
15593 /* This outputs the LITTLENUMs in REVERSE order;
15594 in accord with the bigendian 386. */
15595 return ieee_md_atof (type, litP, sizeP, false);
15598 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
15601 output_invalid (int c)
15604 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
15607 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
15608 "(0x%x)", (unsigned char) c);
15609 return output_invalid_buf;
15612 /* Verify that @r can be used in the current context. */
15614 static bool check_register (const reg_entry *r)
15616 if (allow_pseudo_reg)
15619 if (operand_type_all_zero (&r->reg_type))
15622 if ((r->reg_type.bitfield.dword
15623 || (r->reg_type.bitfield.class == SReg && r->reg_num > 3)
15624 || r->reg_type.bitfield.class == RegCR
15625 || r->reg_type.bitfield.class == RegDR)
15626 && !cpu_arch_flags.bitfield.cpui386)
15629 if (r->reg_type.bitfield.class == RegTR
15630 && (flag_code == CODE_64BIT
15631 || !cpu_arch_flags.bitfield.cpui386
15632 || cpu_arch_isa_flags.bitfield.cpui586
15633 || cpu_arch_isa_flags.bitfield.cpui686))
15636 if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx)
15639 if (!cpu_arch_flags.bitfield.cpuavx512f)
15641 if (r->reg_type.bitfield.zmmword
15642 || r->reg_type.bitfield.class == RegMask)
15645 if (!cpu_arch_flags.bitfield.cpuavx)
15647 if (r->reg_type.bitfield.ymmword)
15650 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
15655 if (r->reg_type.bitfield.zmmword)
15657 if (vector_size < VSZ512)
15660 if (i.vec_encoding == vex_encoding_default)
15661 i.vec_encoding = vex_encoding_evex512;
15662 else if (i.vec_encoding != vex_encoding_evex
15663 && i.vec_encoding != vex_encoding_evex512)
15664 i.vec_encoding = vex_encoding_error;
15667 if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword)
15670 if (r->reg_type.bitfield.tmmword
15671 && (!cpu_arch_flags.bitfield.cpuamx_tile
15672 || flag_code != CODE_64BIT))
15675 if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
15678 /* Don't allow fake index register unless allow_index_reg isn't 0. */
15679 if (!allow_index_reg && r->reg_num == RegIZ)
15682 /* Upper 16 vector registers are only available with VREX in 64bit
15683 mode, and require EVEX encoding. */
15684 if (r->reg_flags & RegVRex)
15686 if (!cpu_arch_flags.bitfield.cpuavx512f
15687 || flag_code != CODE_64BIT)
15690 if (i.vec_encoding == vex_encoding_default
15691 || i.vec_encoding == vex_encoding_evex512)
15692 i.vec_encoding = vex_encoding_evex;
15693 else if (i.vec_encoding != vex_encoding_evex)
15694 i.vec_encoding = vex_encoding_error;
15697 if (r->reg_flags & RegRex2)
15699 if (!cpu_arch_flags.bitfield.cpuapx_f
15700 || flag_code != CODE_64BIT)
15706 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
15707 && (!cpu_arch_flags.bitfield.cpu64
15708 || r->reg_type.bitfield.class != RegCR
15710 && flag_code != CODE_64BIT)
15713 if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat
15720 /* REG_STRING starts *before* REGISTER_PREFIX. */
15722 static const reg_entry *
15723 parse_real_register (const char *reg_string, char **end_op)
15725 const char *s = reg_string;
15727 char reg_name_given[MAX_REG_NAME_SIZE + 1];
15728 const reg_entry *r;
15730 /* Skip possible REGISTER_PREFIX and possible whitespace. */
15731 if (*s == REGISTER_PREFIX)
15734 if (is_space_char (*s))
15737 p = reg_name_given;
15738 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
15740 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
15741 return (const reg_entry *) NULL;
15745 if (is_part_of_name (*s))
15746 return (const reg_entry *) NULL;
15748 *end_op = (char *) s;
15750 r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given);
15752 /* Handle floating point regs, allowing spaces in the (i) part. */
15755 if (!cpu_arch_flags.bitfield.cpu8087
15756 && !cpu_arch_flags.bitfield.cpu287
15757 && !cpu_arch_flags.bitfield.cpu387
15758 && !allow_pseudo_reg)
15759 return (const reg_entry *) NULL;
15761 if (is_space_char (*s))
15766 if (is_space_char (*s))
15768 if (*s >= '0' && *s <= '7')
15770 int fpr = *s - '0';
15772 if (is_space_char (*s))
15776 *end_op = (char *) s + 1;
15777 know (r[fpr].reg_num == fpr);
15781 /* We have "%st(" then garbage. */
15782 return (const reg_entry *) NULL;
15786 return r && check_register (r) ? r : NULL;
15789 /* REG_STRING starts *before* REGISTER_PREFIX. */
15791 static const reg_entry *
15792 parse_register (const char *reg_string, char **end_op)
15794 const reg_entry *r;
15796 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
15797 r = parse_real_register (reg_string, end_op);
15802 char *save = input_line_pointer;
15803 char *buf = xstrdup (reg_string), *name;
15806 input_line_pointer = buf;
15807 get_symbol_name (&name);
15808 symbolP = symbol_find (name);
15809 while (symbolP && symbol_equated_p (symbolP))
15811 const expressionS *e = symbol_get_value_expression(symbolP);
15813 if (e->X_add_number)
15815 symbolP = e->X_add_symbol;
15817 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
15819 const expressionS *e = symbol_get_value_expression (symbolP);
15821 if (e->X_op == O_register)
15823 know (e->X_add_number >= 0
15824 && (valueT) e->X_add_number < i386_regtab_size);
15825 r = i386_regtab + e->X_add_number;
15826 *end_op = (char *) reg_string + (input_line_pointer - buf);
15828 if (r && !check_register (r))
15830 as_bad (_("register '%s%s' cannot be used here"),
15831 register_prefix, r->reg_name);
15835 input_line_pointer = save;
15842 i386_parse_name (char *name, expressionS *e, char *nextcharP)
15844 const reg_entry *r = NULL;
15845 char *end = input_line_pointer;
15847 /* We only know the terminating character here. It being double quote could
15848 be the closing one of a quoted symbol name, or an opening one from a
15849 following string (or another quoted symbol name). Since the latter can't
15850 be valid syntax for anything, bailing in either case is good enough. */
15851 if (*nextcharP == '"')
15855 if (*name == REGISTER_PREFIX || allow_naked_reg)
15856 r = parse_real_register (name, &input_line_pointer);
15857 if (r && end <= input_line_pointer)
15859 *nextcharP = *input_line_pointer;
15860 *input_line_pointer = 0;
15861 e->X_op = O_register;
15862 e->X_add_number = r - i386_regtab;
15865 input_line_pointer = end;
15867 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
15871 md_operand (expressionS *e)
15874 const reg_entry *r;
15876 switch (*input_line_pointer)
15878 case REGISTER_PREFIX:
15879 r = parse_real_register (input_line_pointer, &end);
15882 e->X_op = O_register;
15883 e->X_add_number = r - i386_regtab;
15884 input_line_pointer = end;
15889 gas_assert (intel_syntax);
15890 end = input_line_pointer++;
15892 if (*input_line_pointer == ']')
15894 ++input_line_pointer;
15895 e->X_op_symbol = make_expr_symbol (e);
15896 e->X_add_symbol = NULL;
15897 e->X_add_number = 0;
15902 e->X_op = O_absent;
15903 input_line_pointer = end;
15910 /* To maintain consistency with !BFD64 builds of gas record, whether any
15911 (binary) operator was involved in an expression. As expressions are
15912 evaluated in only 32 bits when !BFD64, we use this to decide whether to
15913 truncate results. */
15914 bool i386_record_operator (operatorT op,
15915 const expressionS *left,
15916 const expressionS *right)
15918 if (op == O_absent)
15923 /* Since the expression parser applies unary operators fine to bignum
15924 operands, we don't need to be concerned of respective operands not
15925 fitting in 32 bits. */
15926 if (right->X_op == O_constant && right->X_unsigned
15927 && !fits_in_unsigned_long (right->X_add_number))
15930 /* This isn't entirely right: The pattern can also result when constant
15931 expressions are folded (e.g. 0xffffffff + 1). */
15932 else if ((left->X_op == O_constant && left->X_unsigned
15933 && !fits_in_unsigned_long (left->X_add_number))
15934 || (right->X_op == O_constant && right->X_unsigned
15935 && !fits_in_unsigned_long (right->X_add_number)))
15936 expr_mode = expr_large_value;
15938 if (expr_mode != expr_large_value)
15939 expr_mode = expr_operator_present;
15945 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15946 const char *md_shortopts = "kVQ:sqnO::";
15948 const char *md_shortopts = "qnO::";
15951 #define OPTION_32 (OPTION_MD_BASE + 0)
15952 #define OPTION_64 (OPTION_MD_BASE + 1)
15953 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
15954 #define OPTION_MARCH (OPTION_MD_BASE + 3)
15955 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
15956 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
15957 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
15958 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
15959 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
15960 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
15961 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
15962 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
15963 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
15964 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
15965 #define OPTION_X32 (OPTION_MD_BASE + 14)
15966 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
15967 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
15968 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
15969 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
15970 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
15971 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
15972 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
15973 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
15974 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
15975 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
15976 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
15977 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
15978 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
15979 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
15980 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
15981 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
15982 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
15983 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
15984 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
15985 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
15987 struct option md_longopts[] =
15989 {"32", no_argument, NULL, OPTION_32},
15990 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
15991 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
15992 {"64", no_argument, NULL, OPTION_64},
15994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
15995 {"x32", no_argument, NULL, OPTION_X32},
15996 {"mshared", no_argument, NULL, OPTION_MSHARED},
15997 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
15999 {"divide", no_argument, NULL, OPTION_DIVIDE},
16000 {"march", required_argument, NULL, OPTION_MARCH},
16001 {"mtune", required_argument, NULL, OPTION_MTUNE},
16002 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
16003 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
16004 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
16005 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
16006 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
16007 {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE},
16008 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
16009 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
16010 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
16011 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
16012 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
16013 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
16014 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
16015 # if defined (TE_PE) || defined (TE_PEP)
16016 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
16018 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
16019 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
16020 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
16021 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
16022 {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY},
16023 {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE},
16024 {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH},
16025 {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES},
16026 {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD},
16027 {"mlfence-before-indirect-branch", required_argument, NULL,
16028 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
16029 {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET},
16030 {"mamd64", no_argument, NULL, OPTION_MAMD64},
16031 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
16032 {NULL, no_argument, NULL, 0}
16034 size_t md_longopts_size = sizeof (md_longopts);
16037 md_parse_option (int c, const char *arg)
16040 char *arch, *next, *saved, *type;
16045 optimize_align_code = 0;
16049 quiet_warnings = 1;
16052 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16053 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
16054 should be emitted or not. FIXME: Not implemented. */
16056 if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
16060 /* -V: SVR4 argument to print version ID. */
16062 print_version_id ();
16065 /* -k: Ignore for FreeBSD compatibility. */
16070 /* -s: On i386 Solaris, this tells the native assembler to use
16071 .stab instead of .stab.excl. We always use .stab anyhow. */
16074 case OPTION_MSHARED:
16078 case OPTION_X86_USED_NOTE:
16079 if (strcasecmp (arg, "yes") == 0)
16081 else if (strcasecmp (arg, "no") == 0)
16084 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
16089 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16090 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16093 const char **list, **l;
16095 list = bfd_target_list ();
16096 for (l = list; *l != NULL; l++)
16097 if (startswith (*l, "elf64-x86-64")
16098 || strcmp (*l, "coff-x86-64") == 0
16099 || strcmp (*l, "pe-x86-64") == 0
16100 || strcmp (*l, "pei-x86-64") == 0
16101 || strcmp (*l, "mach-o-x86-64") == 0)
16103 default_arch = "x86_64";
16107 as_fatal (_("no compiled in support for x86_64"));
16113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16117 const char **list, **l;
16119 list = bfd_target_list ();
16120 for (l = list; *l != NULL; l++)
16121 if (startswith (*l, "elf32-x86-64"))
16123 default_arch = "x86_64:32";
16127 as_fatal (_("no compiled in support for 32bit x86_64"));
16131 as_fatal (_("32bit x86_64 is only supported for ELF"));
16137 const char **list, **l;
16139 list = bfd_target_list ();
16140 for (l = list; *l != NULL; l++)
16141 if (strstr (*l, "-i386")
16142 || strstr (*l, "-go32"))
16144 default_arch = "i386";
16148 as_fatal (_("no compiled in support for ix86"));
16153 case OPTION_DIVIDE:
16154 #ifdef SVR4_COMMENT_CHARS
16159 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
16161 for (s = i386_comment_chars; *s != '\0'; s++)
16165 i386_comment_chars = n;
16171 saved = xstrdup (arg);
16173 /* Allow -march=+nosse. */
16181 as_fatal (_("invalid -march= option: `%s'"), arg);
16182 next = strchr (arch, '+');
16185 vsz = strchr (arch, '/');
16188 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16190 if (vsz && cpu_arch[j].vsz != vsz_set)
16193 if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE
16194 && strcmp (arch, cpu_arch[j].name) == 0)
16197 if (! cpu_arch[j].enable.bitfield.cpui386)
16200 cpu_arch_name = cpu_arch[j].name;
16201 free (cpu_sub_arch_name);
16202 cpu_sub_arch_name = NULL;
16203 cpu_arch_flags = cpu_arch[j].enable;
16204 cpu_arch_isa = cpu_arch[j].type;
16205 cpu_arch_isa_flags = cpu_arch[j].enable;
16206 if (!cpu_arch_tune_set)
16207 cpu_arch_tune = cpu_arch_isa;
16208 vector_size = VSZ_DEFAULT;
16211 else if (cpu_arch[j].type == PROCESSOR_NONE
16212 && strcmp (arch, cpu_arch[j].name) == 0
16213 && !cpu_flags_all_zero (&cpu_arch[j].enable))
16215 /* ISA extension. */
16218 switch (cpu_arch[j].vsz)
16227 unsigned long val = strtoul (vsz, &end, 0);
16233 case 512: vector_size = VSZ512; break;
16234 case 256: vector_size = VSZ256; break;
16235 case 128: vector_size = VSZ128; break;
16237 as_warn (_("Unrecognized vector size specifier ignored"));
16242 /* Fall through. */
16244 vector_size = VSZ_DEFAULT;
16252 if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no"))
16254 /* Disable an ISA extension. */
16255 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16256 if (cpu_arch[j].type == PROCESSOR_NONE
16257 && strcmp (arch + 2, cpu_arch[j].name) == 0)
16260 if (cpu_arch[j].vsz == vsz_set)
16261 vector_size = VSZ_DEFAULT;
16266 if (j >= ARRAY_SIZE (cpu_arch))
16267 as_fatal (_("invalid -march= option: `%s'"), arg);
16271 while (next != NULL);
16277 as_fatal (_("invalid -mtune= option: `%s'"), arg);
16278 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16280 if (cpu_arch[j].type != PROCESSOR_NONE
16281 && strcmp (arg, cpu_arch[j].name) == 0)
16283 cpu_arch_tune_set = 1;
16284 cpu_arch_tune = cpu_arch [j].type;
16288 if (j >= ARRAY_SIZE (cpu_arch))
16289 as_fatal (_("invalid -mtune= option: `%s'"), arg);
16292 case OPTION_MMNEMONIC:
16293 if (strcasecmp (arg, "att") == 0)
16294 intel_mnemonic = 0;
16295 else if (strcasecmp (arg, "intel") == 0)
16296 intel_mnemonic = 1;
16298 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
16301 case OPTION_MSYNTAX:
16302 if (strcasecmp (arg, "att") == 0)
16304 else if (strcasecmp (arg, "intel") == 0)
16307 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
16310 case OPTION_MINDEX_REG:
16311 allow_index_reg = 1;
16314 case OPTION_MNAKED_REG:
16315 allow_naked_reg = 1;
16318 case OPTION_MSSE2AVX:
16322 case OPTION_MUSE_UNALIGNED_VECTOR_MOVE:
16323 use_unaligned_vector_move = 1;
16326 case OPTION_MSSE_CHECK:
16327 if (strcasecmp (arg, "error") == 0)
16328 sse_check = check_error;
16329 else if (strcasecmp (arg, "warning") == 0)
16330 sse_check = check_warning;
16331 else if (strcasecmp (arg, "none") == 0)
16332 sse_check = check_none;
16334 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
16337 case OPTION_MOPERAND_CHECK:
16338 if (strcasecmp (arg, "error") == 0)
16339 operand_check = check_error;
16340 else if (strcasecmp (arg, "warning") == 0)
16341 operand_check = check_warning;
16342 else if (strcasecmp (arg, "none") == 0)
16343 operand_check = check_none;
16345 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
16348 case OPTION_MAVXSCALAR:
16349 if (strcasecmp (arg, "128") == 0)
16350 avxscalar = vex128;
16351 else if (strcasecmp (arg, "256") == 0)
16352 avxscalar = vex256;
16354 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
16357 case OPTION_MVEXWIG:
16358 if (strcmp (arg, "0") == 0)
16360 else if (strcmp (arg, "1") == 0)
16363 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
16366 case OPTION_MADD_BND_PREFIX:
16367 add_bnd_prefix = 1;
16370 case OPTION_MEVEXLIG:
16371 if (strcmp (arg, "128") == 0)
16372 evexlig = evexl128;
16373 else if (strcmp (arg, "256") == 0)
16374 evexlig = evexl256;
16375 else if (strcmp (arg, "512") == 0)
16376 evexlig = evexl512;
16378 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
16381 case OPTION_MEVEXRCIG:
16382 if (strcmp (arg, "rne") == 0)
16384 else if (strcmp (arg, "rd") == 0)
16386 else if (strcmp (arg, "ru") == 0)
16388 else if (strcmp (arg, "rz") == 0)
16391 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
16394 case OPTION_MEVEXWIG:
16395 if (strcmp (arg, "0") == 0)
16397 else if (strcmp (arg, "1") == 0)
16400 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
16403 # if defined (TE_PE) || defined (TE_PEP)
16404 case OPTION_MBIG_OBJ:
16409 case OPTION_MOMIT_LOCK_PREFIX:
16410 if (strcasecmp (arg, "yes") == 0)
16411 omit_lock_prefix = 1;
16412 else if (strcasecmp (arg, "no") == 0)
16413 omit_lock_prefix = 0;
16415 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
16418 case OPTION_MFENCE_AS_LOCK_ADD:
16419 if (strcasecmp (arg, "yes") == 0)
16421 else if (strcasecmp (arg, "no") == 0)
16424 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
16427 case OPTION_MLFENCE_AFTER_LOAD:
16428 if (strcasecmp (arg, "yes") == 0)
16429 lfence_after_load = 1;
16430 else if (strcasecmp (arg, "no") == 0)
16431 lfence_after_load = 0;
16433 as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg);
16436 case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH:
16437 if (strcasecmp (arg, "all") == 0)
16439 lfence_before_indirect_branch = lfence_branch_all;
16440 if (lfence_before_ret == lfence_before_ret_none)
16441 lfence_before_ret = lfence_before_ret_shl;
16443 else if (strcasecmp (arg, "memory") == 0)
16444 lfence_before_indirect_branch = lfence_branch_memory;
16445 else if (strcasecmp (arg, "register") == 0)
16446 lfence_before_indirect_branch = lfence_branch_register;
16447 else if (strcasecmp (arg, "none") == 0)
16448 lfence_before_indirect_branch = lfence_branch_none;
16450 as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"),
16454 case OPTION_MLFENCE_BEFORE_RET:
16455 if (strcasecmp (arg, "or") == 0)
16456 lfence_before_ret = lfence_before_ret_or;
16457 else if (strcasecmp (arg, "not") == 0)
16458 lfence_before_ret = lfence_before_ret_not;
16459 else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0)
16460 lfence_before_ret = lfence_before_ret_shl;
16461 else if (strcasecmp (arg, "none") == 0)
16462 lfence_before_ret = lfence_before_ret_none;
16464 as_fatal (_("invalid -mlfence-before-ret= option: `%s'"),
16468 case OPTION_MRELAX_RELOCATIONS:
16469 if (strcasecmp (arg, "yes") == 0)
16470 generate_relax_relocations = 1;
16471 else if (strcasecmp (arg, "no") == 0)
16472 generate_relax_relocations = 0;
16474 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
16477 case OPTION_MALIGN_BRANCH_BOUNDARY:
16480 long int align = strtoul (arg, &end, 0);
16485 align_branch_power = 0;
16488 else if (align >= 16)
16491 for (align_power = 0;
16493 align >>= 1, align_power++)
16495 /* Limit alignment power to 31. */
16496 if (align == 1 && align_power < 32)
16498 align_branch_power = align_power;
16503 as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg);
16507 case OPTION_MALIGN_BRANCH_PREFIX_SIZE:
16510 int align = strtoul (arg, &end, 0);
16511 /* Some processors only support 5 prefixes. */
16512 if (*end == '\0' && align >= 0 && align < 6)
16514 align_branch_prefix_size = align;
16517 as_fatal (_("invalid -malign-branch-prefix-size= value: %s"),
16522 case OPTION_MALIGN_BRANCH:
16524 saved = xstrdup (arg);
16528 next = strchr (type, '+');
16531 if (strcasecmp (type, "jcc") == 0)
16532 align_branch |= align_branch_jcc_bit;
16533 else if (strcasecmp (type, "fused") == 0)
16534 align_branch |= align_branch_fused_bit;
16535 else if (strcasecmp (type, "jmp") == 0)
16536 align_branch |= align_branch_jmp_bit;
16537 else if (strcasecmp (type, "call") == 0)
16538 align_branch |= align_branch_call_bit;
16539 else if (strcasecmp (type, "ret") == 0)
16540 align_branch |= align_branch_ret_bit;
16541 else if (strcasecmp (type, "indirect") == 0)
16542 align_branch |= align_branch_indirect_bit;
16544 as_fatal (_("invalid -malign-branch= option: `%s'"), arg);
16547 while (next != NULL);
16551 case OPTION_MBRANCHES_WITH_32B_BOUNDARIES:
16552 align_branch_power = 5;
16553 align_branch_prefix_size = 5;
16554 align_branch = (align_branch_jcc_bit
16555 | align_branch_fused_bit
16556 | align_branch_jmp_bit);
16559 case OPTION_MAMD64:
16563 case OPTION_MINTEL64:
16571 /* Turn off -Os. */
16572 optimize_for_space = 0;
16574 else if (*arg == 's')
16576 optimize_for_space = 1;
16577 /* Turn on all encoding optimizations. */
16578 optimize = INT_MAX;
16582 optimize = atoi (arg);
16583 /* Turn off -Os. */
16584 optimize_for_space = 0;
16594 #define MESSAGE_TEMPLATE \
16598 output_message (FILE *stream, char *p, char *message, char *start,
16599 int *left_p, const char *name, int len)
16601 int size = sizeof (MESSAGE_TEMPLATE);
16602 int left = *left_p;
16604 /* Reserve 2 spaces for ", " or ",\0" */
16607 /* Check if there is any room. */
16615 p = mempcpy (p, name, len);
16619 /* Output the current message now and start a new one. */
16622 fprintf (stream, "%s\n", message);
16624 left = size - (start - message) - len - 2;
16626 gas_assert (left >= 0);
16628 p = mempcpy (p, name, len);
16636 show_arch (FILE *stream, int ext, int check)
16638 static char message[] = MESSAGE_TEMPLATE;
16639 char *start = message + 27;
16641 int size = sizeof (MESSAGE_TEMPLATE);
16648 left = size - (start - message);
16652 p = output_message (stream, p, message, start, &left,
16653 STRING_COMMA_LEN ("default"));
16654 p = output_message (stream, p, message, start, &left,
16655 STRING_COMMA_LEN ("push"));
16656 p = output_message (stream, p, message, start, &left,
16657 STRING_COMMA_LEN ("pop"));
16660 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16662 /* Should it be skipped? */
16663 if (cpu_arch [j].skip)
16666 name = cpu_arch [j].name;
16667 len = cpu_arch [j].len;
16668 if (cpu_arch[j].type == PROCESSOR_NONE)
16670 /* It is an extension. Skip if we aren't asked to show it. */
16671 if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable))
16676 /* It is an processor. Skip if we show only extension. */
16679 else if (check && ! cpu_arch[j].enable.bitfield.cpui386)
16681 /* It is an impossible processor - skip. */
16685 p = output_message (stream, p, message, start, &left, name, len);
16688 /* Display disabled extensions. */
16690 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
16694 if (cpu_arch[j].type != PROCESSOR_NONE
16695 || !cpu_flags_all_zero (&cpu_arch[j].enable))
16697 str = xasprintf ("no%s", cpu_arch[j].name);
16698 p = output_message (stream, p, message, start, &left, str,
16704 fprintf (stream, "%s\n", message);
16708 md_show_usage (FILE *stream)
16710 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16711 fprintf (stream, _("\
16712 -Qy, -Qn ignored\n\
16713 -V print assembler version number\n\
16716 fprintf (stream, _("\
16717 -n do not optimize code alignment\n\
16718 -O{012s} attempt some code optimizations\n\
16719 -q quieten some warnings\n"));
16720 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16721 fprintf (stream, _("\
16725 # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16726 fprintf (stream, _("\
16727 --32/--64/--x32 generate 32bit/64bit/x32 object\n"));
16728 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
16729 fprintf (stream, _("\
16730 --32/--64 generate 32bit/64bit object\n"));
16733 #ifdef SVR4_COMMENT_CHARS
16734 fprintf (stream, _("\
16735 --divide do not treat `/' as a comment character\n"));
16737 fprintf (stream, _("\
16738 --divide ignored\n"));
16740 fprintf (stream, _("\
16741 -march=CPU[,+EXTENSION...]\n\
16742 generate code for CPU and EXTENSION, CPU is one of:\n"));
16743 show_arch (stream, 0, 1);
16744 fprintf (stream, _("\
16745 EXTENSION is combination of (possibly \"no\"-prefixed):\n"));
16746 show_arch (stream, 1, 0);
16747 fprintf (stream, _("\
16748 -mtune=CPU optimize for CPU, CPU is one of:\n"));
16749 show_arch (stream, 0, 0);
16750 fprintf (stream, _("\
16751 -msse2avx encode SSE instructions with VEX prefix\n"));
16752 fprintf (stream, _("\
16753 -muse-unaligned-vector-move\n\
16754 encode aligned vector move as unaligned vector move\n"));
16755 fprintf (stream, _("\
16756 -msse-check=[none|error|warning] (default: warning)\n\
16757 check SSE instructions\n"));
16758 fprintf (stream, _("\
16759 -moperand-check=[none|error|warning] (default: warning)\n\
16760 check operand combinations for validity\n"));
16761 fprintf (stream, _("\
16762 -mavxscalar=[128|256] (default: 128)\n\
16763 encode scalar AVX instructions with specific vector\n\
16765 fprintf (stream, _("\
16766 -mvexwig=[0|1] (default: 0)\n\
16767 encode VEX instructions with specific VEX.W value\n\
16768 for VEX.W bit ignored instructions\n"));
16769 fprintf (stream, _("\
16770 -mevexlig=[128|256|512] (default: 128)\n\
16771 encode scalar EVEX instructions with specific vector\n\
16773 fprintf (stream, _("\
16774 -mevexwig=[0|1] (default: 0)\n\
16775 encode EVEX instructions with specific EVEX.W value\n\
16776 for EVEX.W bit ignored instructions\n"));
16777 fprintf (stream, _("\
16778 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
16779 encode EVEX instructions with specific EVEX.RC value\n\
16780 for SAE-only ignored instructions\n"));
16781 fprintf (stream, _("\
16782 -mmnemonic=[att|intel] "));
16783 if (SYSV386_COMPAT)
16784 fprintf (stream, _("(default: att)\n"));
16786 fprintf (stream, _("(default: intel)\n"));
16787 fprintf (stream, _("\
16788 use AT&T/Intel mnemonic (AT&T syntax only)\n"));
16789 fprintf (stream, _("\
16790 -msyntax=[att|intel] (default: att)\n\
16791 use AT&T/Intel syntax\n"));
16792 fprintf (stream, _("\
16793 -mindex-reg support pseudo index registers\n"));
16794 fprintf (stream, _("\
16795 -mnaked-reg don't require `%%' prefix for registers\n"));
16796 fprintf (stream, _("\
16797 -madd-bnd-prefix add BND prefix for all valid branches\n"));
16798 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16799 fprintf (stream, _("\
16800 -mshared disable branch optimization for shared code\n"));
16801 fprintf (stream, _("\
16802 -mx86-used-note=[no|yes] "));
16803 if (DEFAULT_X86_USED_NOTE)
16804 fprintf (stream, _("(default: yes)\n"));
16806 fprintf (stream, _("(default: no)\n"));
16807 fprintf (stream, _("\
16808 generate x86 used ISA and feature properties\n"));
16810 #if defined (TE_PE) || defined (TE_PEP)
16811 fprintf (stream, _("\
16812 -mbig-obj generate big object files\n"));
16814 fprintf (stream, _("\
16815 -momit-lock-prefix=[no|yes] (default: no)\n\
16816 strip all lock prefixes\n"));
16817 fprintf (stream, _("\
16818 -mfence-as-lock-add=[no|yes] (default: no)\n\
16819 encode lfence, mfence and sfence as\n\
16820 lock addl $0x0, (%%{re}sp)\n"));
16821 fprintf (stream, _("\
16822 -mrelax-relocations=[no|yes] "));
16823 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
16824 fprintf (stream, _("(default: yes)\n"));
16826 fprintf (stream, _("(default: no)\n"));
16827 fprintf (stream, _("\
16828 generate relax relocations\n"));
16829 fprintf (stream, _("\
16830 -malign-branch-boundary=NUM (default: 0)\n\
16831 align branches within NUM byte boundary\n"));
16832 fprintf (stream, _("\
16833 -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\
16834 TYPE is combination of jcc, fused, jmp, call, ret,\n\
16836 specify types of branches to align\n"));
16837 fprintf (stream, _("\
16838 -malign-branch-prefix-size=NUM (default: 5)\n\
16839 align branches with NUM prefixes per instruction\n"));
16840 fprintf (stream, _("\
16841 -mbranches-within-32B-boundaries\n\
16842 align branches within 32 byte boundary\n"));
16843 fprintf (stream, _("\
16844 -mlfence-after-load=[no|yes] (default: no)\n\
16845 generate lfence after load\n"));
16846 fprintf (stream, _("\
16847 -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\
16848 generate lfence before indirect near branch\n"));
16849 fprintf (stream, _("\
16850 -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\
16851 generate lfence before ret\n"));
16852 fprintf (stream, _("\
16853 -mamd64 accept only AMD64 ISA [default]\n"));
16854 fprintf (stream, _("\
16855 -mintel64 accept only Intel64 ISA\n"));
16858 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
16859 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
16860 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
16862 /* Pick the target format to use. */
16865 i386_target_format (void)
16867 if (startswith (default_arch, "x86_64"))
16869 update_code_flag (CODE_64BIT, 1);
16870 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16871 if (default_arch[6] == '\0')
16872 x86_elf_abi = X86_64_ABI;
16874 x86_elf_abi = X86_64_X32_ABI;
16877 else if (!strcmp (default_arch, "i386"))
16878 update_code_flag (CODE_32BIT, 1);
16879 else if (!strcmp (default_arch, "iamcu"))
16881 update_code_flag (CODE_32BIT, 1);
16882 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
16884 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
16885 cpu_arch_name = "iamcu";
16886 free (cpu_sub_arch_name);
16887 cpu_sub_arch_name = NULL;
16888 cpu_arch_flags = iamcu_flags;
16889 cpu_arch_isa = PROCESSOR_IAMCU;
16890 cpu_arch_isa_flags = iamcu_flags;
16891 if (!cpu_arch_tune_set)
16892 cpu_arch_tune = PROCESSOR_IAMCU;
16894 else if (cpu_arch_isa != PROCESSOR_IAMCU)
16895 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
16899 as_fatal (_("unknown architecture"));
16901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
16902 if (IS_ELF && flag_synth_cfi && x86_elf_abi != X86_64_ABI)
16903 as_fatal (_("SCFI is not supported for this ABI"));
16906 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
16907 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable;
16909 switch (OUTPUT_FLAVOR)
16911 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
16912 case bfd_target_aout_flavour:
16913 return AOUT_TARGET_FORMAT;
16915 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
16916 # if defined (TE_PE) || defined (TE_PEP)
16917 case bfd_target_coff_flavour:
16918 if (flag_code == CODE_64BIT)
16921 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
16923 return use_big_obj ? "pe-bigobj-i386" : "pe-i386";
16924 # elif defined (TE_GO32)
16925 case bfd_target_coff_flavour:
16926 return "coff-go32";
16928 case bfd_target_coff_flavour:
16929 return "coff-i386";
16932 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
16933 case bfd_target_elf_flavour:
16935 const char *format;
16937 switch (x86_elf_abi)
16940 format = ELF_TARGET_FORMAT;
16942 tls_get_addr = "___tls_get_addr";
16946 use_rela_relocations = 1;
16949 tls_get_addr = "__tls_get_addr";
16951 format = ELF_TARGET_FORMAT64;
16953 case X86_64_X32_ABI:
16954 use_rela_relocations = 1;
16957 tls_get_addr = "__tls_get_addr";
16959 disallow_64bit_reloc = 1;
16960 format = ELF_TARGET_FORMAT32;
16963 if (cpu_arch_isa == PROCESSOR_IAMCU)
16965 if (x86_elf_abi != I386_ABI)
16966 as_fatal (_("Intel MCU is 32bit only"));
16967 return ELF_TARGET_IAMCU_FORMAT;
16973 #if defined (OBJ_MACH_O)
16974 case bfd_target_mach_o_flavour:
16975 if (flag_code == CODE_64BIT)
16977 use_rela_relocations = 1;
16979 return "mach-o-x86-64";
16982 return "mach-o-i386";
16990 #endif /* OBJ_MAYBE_ more than one */
16993 md_undefined_symbol (char *name)
16995 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
16996 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
16997 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
16998 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
17002 if (symbol_find (name))
17003 as_bad (_("GOT already in symbol table"));
17004 GOT_symbol = symbol_new (name, undefined_section,
17005 &zero_address_frag, 0);
17012 #if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
17013 /* Round up a section size to the appropriate boundary. */
17016 md_section_align (segT segment, valueT size)
17018 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
17020 /* For a.out, force the section size to be aligned. If we don't do
17021 this, BFD will align it for us, but it will not write out the
17022 final bytes of the section. This may be a bug in BFD, but it is
17023 easier to fix it here since that is how the other a.out targets
17027 align = bfd_section_alignment (segment);
17028 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
17035 /* On the i386, PC-relative offsets are relative to the start of the
17036 next instruction. That is, the address of the offset, plus its
17037 size, since the offset is always the last part of the insn. */
17040 md_pcrel_from (fixS *fixP)
17042 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
17048 s_bss (int ignore ATTRIBUTE_UNUSED)
17052 temp = get_absolute_expression ();
17053 subseg_set (bss_section, (subsegT) temp);
17054 demand_empty_rest_of_line ();
17059 /* Remember constant directive. */
17062 i386_cons_align (int ignore ATTRIBUTE_UNUSED)
17064 struct last_insn *last_insn
17065 = &seg_info(now_seg)->tc_segment_info_data.last_insn;
17067 if (bfd_section_flags (now_seg) & SEC_CODE)
17069 last_insn->kind = last_insn_directive;
17070 last_insn->name = "constant directive";
17071 last_insn->file = as_where (&last_insn->line);
17076 i386_validate_fix (fixS *fixp)
17078 if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section)
17080 reloc_howto_type *howto;
17082 howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
17083 as_bad_where (fixp->fx_file, fixp->fx_line,
17084 _("invalid %s relocation against register"),
17085 howto ? howto->name : "<unknown>");
17089 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17090 if (fixp->fx_r_type == BFD_RELOC_SIZE32
17091 || fixp->fx_r_type == BFD_RELOC_SIZE64)
17092 return IS_ELF && fixp->fx_addsy
17093 && (!S_IS_DEFINED (fixp->fx_addsy)
17094 || S_IS_EXTERNAL (fixp->fx_addsy));
17096 if (fixp->fx_tcbit3)
17098 if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF)
17099 fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTTPOFF;
17100 else if (fixp->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC)
17101 fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC;
17105 if (fixp->fx_subsy)
17107 if (fixp->fx_subsy == GOT_symbol)
17109 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
17113 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17114 if (fixp->fx_tcbit2)
17116 if (fixp->fx_tcbit3)
17117 fixp->fx_r_type = BFD_RELOC_X86_64_CODE_4_GOTPCRELX;
17119 fixp->fx_r_type = (fixp->fx_tcbit
17120 ? BFD_RELOC_X86_64_REX_GOTPCRELX
17121 : BFD_RELOC_X86_64_GOTPCRELX);
17125 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
17130 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
17132 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
17134 fixp->fx_subsy = 0;
17137 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17140 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
17141 to section. Since PLT32 relocation must be against symbols,
17142 turn such PLT32 relocation into PC32 relocation. */
17144 && (fixp->fx_r_type == BFD_RELOC_386_PLT32
17145 || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32)
17146 && symbol_section_p (fixp->fx_addsy))
17147 fixp->fx_r_type = BFD_RELOC_32_PCREL;
17150 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
17151 && fixp->fx_tcbit2)
17152 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
17161 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
17164 bfd_reloc_code_real_type code;
17166 switch (fixp->fx_r_type)
17168 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17171 case BFD_RELOC_SIZE32:
17172 case BFD_RELOC_SIZE64:
17174 && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))
17175 && (!fixp->fx_subsy
17176 || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))))
17177 sym = fixp->fx_addsy;
17178 else if (fixp->fx_subsy
17179 && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy))
17180 && (!fixp->fx_addsy
17181 || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy))))
17182 sym = fixp->fx_subsy;
17185 if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym))
17187 /* Resolve size relocation against local symbol to size of
17188 the symbol plus addend. */
17189 valueT value = S_GET_SIZE (sym);
17191 if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM)
17192 value = bfd_section_size (S_GET_SEGMENT (sym));
17193 if (sym == fixp->fx_subsy)
17196 if (fixp->fx_addsy)
17197 value += S_GET_VALUE (fixp->fx_addsy);
17199 else if (fixp->fx_subsy)
17200 value -= S_GET_VALUE (fixp->fx_subsy);
17201 value += fixp->fx_offset;
17202 if (fixp->fx_r_type == BFD_RELOC_SIZE32
17204 && !fits_in_unsigned_long (value))
17205 as_bad_where (fixp->fx_file, fixp->fx_line,
17206 _("symbol size computation overflow"));
17207 fixp->fx_addsy = NULL;
17208 fixp->fx_subsy = NULL;
17209 md_apply_fix (fixp, (valueT *) &value, NULL);
17212 if (!fixp->fx_addsy || fixp->fx_subsy)
17214 as_bad_where (fixp->fx_file, fixp->fx_line,
17215 "unsupported expression involving @size");
17219 /* Fall through. */
17221 case BFD_RELOC_X86_64_PLT32:
17222 case BFD_RELOC_X86_64_GOT32:
17223 case BFD_RELOC_X86_64_GOTPCREL:
17224 case BFD_RELOC_X86_64_GOTPCRELX:
17225 case BFD_RELOC_X86_64_REX_GOTPCRELX:
17226 case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
17227 case BFD_RELOC_386_PLT32:
17228 case BFD_RELOC_386_GOT32:
17229 case BFD_RELOC_386_GOT32X:
17230 case BFD_RELOC_386_GOTOFF:
17231 case BFD_RELOC_386_GOTPC:
17232 case BFD_RELOC_386_TLS_GD:
17233 case BFD_RELOC_386_TLS_LDM:
17234 case BFD_RELOC_386_TLS_LDO_32:
17235 case BFD_RELOC_386_TLS_IE_32:
17236 case BFD_RELOC_386_TLS_IE:
17237 case BFD_RELOC_386_TLS_GOTIE:
17238 case BFD_RELOC_386_TLS_LE_32:
17239 case BFD_RELOC_386_TLS_LE:
17240 case BFD_RELOC_386_TLS_GOTDESC:
17241 case BFD_RELOC_386_TLS_DESC_CALL:
17242 case BFD_RELOC_X86_64_TLSGD:
17243 case BFD_RELOC_X86_64_TLSLD:
17244 case BFD_RELOC_X86_64_DTPOFF32:
17245 case BFD_RELOC_X86_64_DTPOFF64:
17246 case BFD_RELOC_X86_64_GOTTPOFF:
17247 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
17248 case BFD_RELOC_X86_64_TPOFF32:
17249 case BFD_RELOC_X86_64_TPOFF64:
17250 case BFD_RELOC_X86_64_GOTOFF64:
17251 case BFD_RELOC_X86_64_GOTPC32:
17252 case BFD_RELOC_X86_64_GOT64:
17253 case BFD_RELOC_X86_64_GOTPCREL64:
17254 case BFD_RELOC_X86_64_GOTPC64:
17255 case BFD_RELOC_X86_64_GOTPLT64:
17256 case BFD_RELOC_X86_64_PLTOFF64:
17257 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17258 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
17259 case BFD_RELOC_X86_64_TLSDESC_CALL:
17260 case BFD_RELOC_RVA:
17261 case BFD_RELOC_VTABLE_ENTRY:
17262 case BFD_RELOC_VTABLE_INHERIT:
17264 case BFD_RELOC_32_SECREL:
17265 case BFD_RELOC_16_SECIDX:
17267 code = fixp->fx_r_type;
17269 case BFD_RELOC_X86_64_32S:
17270 if (!fixp->fx_pcrel)
17272 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
17273 code = fixp->fx_r_type;
17276 /* Fall through. */
17278 if (fixp->fx_pcrel)
17280 switch (fixp->fx_size)
17283 as_bad_where (fixp->fx_file, fixp->fx_line,
17284 _("can not do %d byte pc-relative relocation"),
17286 code = BFD_RELOC_32_PCREL;
17288 case 1: code = BFD_RELOC_8_PCREL; break;
17289 case 2: code = BFD_RELOC_16_PCREL; break;
17290 case 4: code = BFD_RELOC_32_PCREL; break;
17292 case 8: code = BFD_RELOC_64_PCREL; break;
17298 switch (fixp->fx_size)
17301 as_bad_where (fixp->fx_file, fixp->fx_line,
17302 _("can not do %d byte relocation"),
17304 code = BFD_RELOC_32;
17306 case 1: code = BFD_RELOC_8; break;
17307 case 2: code = BFD_RELOC_16; break;
17308 case 4: code = BFD_RELOC_32; break;
17310 case 8: code = BFD_RELOC_64; break;
17317 if ((code == BFD_RELOC_32
17318 || code == BFD_RELOC_32_PCREL
17319 || code == BFD_RELOC_X86_64_32S)
17321 && fixp->fx_addsy == GOT_symbol)
17324 code = BFD_RELOC_386_GOTPC;
17326 code = BFD_RELOC_X86_64_GOTPC32;
17328 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
17330 && fixp->fx_addsy == GOT_symbol)
17332 code = BFD_RELOC_X86_64_GOTPC64;
17335 rel = XNEW (arelent);
17336 rel->sym_ptr_ptr = XNEW (asymbol *);
17337 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
17339 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
17341 if (!use_rela_relocations)
17343 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
17344 vtable entry to be used in the relocation's section offset. */
17345 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
17346 rel->address = fixp->fx_offset;
17347 #if defined (OBJ_COFF) && defined (TE_PE)
17348 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
17349 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
17354 /* Use the rela in 64bit mode. */
17357 if (disallow_64bit_reloc)
17360 case BFD_RELOC_X86_64_DTPOFF64:
17361 case BFD_RELOC_X86_64_TPOFF64:
17362 case BFD_RELOC_64_PCREL:
17363 case BFD_RELOC_X86_64_GOTOFF64:
17364 case BFD_RELOC_X86_64_GOT64:
17365 case BFD_RELOC_X86_64_GOTPCREL64:
17366 case BFD_RELOC_X86_64_GOTPC64:
17367 case BFD_RELOC_X86_64_GOTPLT64:
17368 case BFD_RELOC_X86_64_PLTOFF64:
17369 as_bad_where (fixp->fx_file, fixp->fx_line,
17370 _("cannot represent relocation type %s in x32 mode"),
17371 bfd_get_reloc_code_name (code));
17377 if (!fixp->fx_pcrel)
17378 rel->addend = fixp->fx_offset;
17382 case BFD_RELOC_X86_64_PLT32:
17383 case BFD_RELOC_X86_64_GOT32:
17384 case BFD_RELOC_X86_64_GOTPCREL:
17385 case BFD_RELOC_X86_64_GOTPCRELX:
17386 case BFD_RELOC_X86_64_REX_GOTPCRELX:
17387 case BFD_RELOC_X86_64_CODE_4_GOTPCRELX:
17388 case BFD_RELOC_X86_64_TLSGD:
17389 case BFD_RELOC_X86_64_TLSLD:
17390 case BFD_RELOC_X86_64_GOTTPOFF:
17391 case BFD_RELOC_X86_64_CODE_4_GOTTPOFF:
17392 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17393 case BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC:
17394 case BFD_RELOC_X86_64_TLSDESC_CALL:
17395 rel->addend = fixp->fx_offset - fixp->fx_size;
17398 rel->addend = (section->vma
17400 + fixp->fx_addnumber
17401 + md_pcrel_from (fixp));
17406 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
17407 if (rel->howto == NULL)
17409 as_bad_where (fixp->fx_file, fixp->fx_line,
17410 _("cannot represent relocation type %s"),
17411 bfd_get_reloc_code_name (code));
17412 /* Set howto to a garbage value so that we can keep going. */
17413 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
17414 gas_assert (rel->howto != NULL);
17420 #include "tc-i386-intel.c"
17423 tc_x86_parse_to_dw2regnum (expressionS *exp)
17425 int saved_naked_reg;
17426 char saved_register_dot;
17428 saved_naked_reg = allow_naked_reg;
17429 allow_naked_reg = 1;
17430 saved_register_dot = register_chars['.'];
17431 register_chars['.'] = '.';
17432 allow_pseudo_reg = 1;
17433 expression_and_evaluate (exp);
17434 allow_pseudo_reg = 0;
17435 register_chars['.'] = saved_register_dot;
17436 allow_naked_reg = saved_naked_reg;
17438 if (exp->X_op == O_register && exp->X_add_number >= 0)
17440 if ((addressT) exp->X_add_number < i386_regtab_size)
17442 exp->X_op = O_constant;
17443 exp->X_add_number = i386_regtab[exp->X_add_number]
17444 .dw2_regnum[flag_code >> 1];
17447 exp->X_op = O_illegal;
17452 tc_x86_frame_initial_instructions (void)
17454 static unsigned int sp_regno[2];
17456 if (!sp_regno[flag_code >> 1])
17458 char *saved_input = input_line_pointer;
17459 char sp[][4] = {"esp", "rsp"};
17462 input_line_pointer = sp[flag_code >> 1];
17463 tc_x86_parse_to_dw2regnum (&exp);
17464 gas_assert (exp.X_op == O_constant);
17465 sp_regno[flag_code >> 1] = exp.X_add_number;
17466 input_line_pointer = saved_input;
17469 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
17470 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
17474 x86_dwarf2_addr_size (void)
17476 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
17477 if (x86_elf_abi == X86_64_X32_ABI)
17480 return bfd_arch_bits_per_address (stdoutput) / 8;
17485 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
17489 exp.X_op = O_secrel;
17490 exp.X_add_symbol = symbol;
17491 exp.X_add_number = 0;
17492 emit_expr (&exp, size);
17496 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
17498 i386_elf_section_type (const char *str, size_t len)
17500 if (flag_code == CODE_64BIT
17501 && len == sizeof ("unwind") - 1
17502 && startswith (str, "unwind"))
17503 return SHT_X86_64_UNWIND;
17509 i386_elf_section_change_hook (void)
17511 struct i386_segment_info *info = &seg_info(now_seg)->tc_segment_info_data;
17512 struct i386_segment_info *curr, *prev;
17514 if (info->subseg == now_subseg)
17517 /* Find the (or make a) list entry to save state into. */
17518 for (prev = info; (curr = prev->next) != NULL; prev = curr)
17519 if (curr->subseg == info->subseg)
17523 curr = XNEW (struct i386_segment_info);
17524 curr->subseg = info->subseg;
17528 curr->last_insn = info->last_insn;
17530 /* Find the list entry to load state from. */
17531 for (curr = info->next; curr; curr = curr->next)
17532 if (curr->subseg == now_subseg)
17535 info->last_insn = curr->last_insn;
17537 memset (&info->last_insn, 0, sizeof (info->last_insn));
17538 info->subseg = now_subseg;
17543 i386_solaris_fix_up_eh_frame (segT sec)
17545 if (flag_code == CODE_64BIT)
17546 elf_section_type (sec) = SHT_X86_64_UNWIND;
17550 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
17553 x86_64_section_letter (int letter, const char **ptr_msg)
17555 if (flag_code == CODE_64BIT)
17558 return SHF_X86_64_LARGE;
17560 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
17563 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
17568 handle_large_common (int small ATTRIBUTE_UNUSED)
17570 if (flag_code != CODE_64BIT)
17572 s_comm_internal (0, elf_common_parse);
17573 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
17577 static segT lbss_section;
17578 asection *saved_com_section_ptr = elf_com_section_ptr;
17579 asection *saved_bss_section = bss_section;
17581 if (lbss_section == NULL)
17583 flagword applicable;
17584 segT seg = now_seg;
17585 subsegT subseg = now_subseg;
17587 /* The .lbss section is for local .largecomm symbols. */
17588 lbss_section = subseg_new (".lbss", 0);
17589 applicable = bfd_applicable_section_flags (stdoutput);
17590 bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC);
17591 seg_info (lbss_section)->bss = 1;
17593 subseg_set (seg, subseg);
17596 elf_com_section_ptr = &_bfd_elf_large_com_section;
17597 bss_section = lbss_section;
17599 s_comm_internal (0, elf_common_parse);
17601 elf_com_section_ptr = saved_com_section_ptr;
17602 bss_section = saved_bss_section;
17605 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */