1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
159 PROCESSOR_PENTIUMPRO,
172 /* x86 arch names, types and features */
175 const char *name; /* arch name */
176 enum processor_type type; /* arch type */
177 i386_cpu_flags flags; /* cpu feature flags */
181 static void set_code_flag (int);
182 static void set_16bit_gcc_code_flag (int);
183 static void set_intel_syntax (int);
184 static void set_intel_mnemonic (int);
185 static void set_allow_index_reg (int);
186 static void set_sse_check (int);
187 static void set_cpu_arch (int);
189 static void pe_directive_secrel (int);
191 static void signed_cons (int);
192 static char *output_invalid (int c);
193 static int i386_att_operand (char *);
194 static int i386_intel_operand (char *, int);
195 static const reg_entry *parse_register (char *, char **);
196 static char *parse_insn (char *, char *);
197 static char *parse_operands (char *, const char *);
198 static void swap_operands (void);
199 static void swap_2_operands (int, int);
200 static void optimize_imm (void);
201 static void optimize_disp (void);
202 static int match_template (void);
203 static int check_string (void);
204 static int process_suffix (void);
205 static int check_byte_reg (void);
206 static int check_long_reg (void);
207 static int check_qword_reg (void);
208 static int check_word_reg (void);
209 static int finalize_imm (void);
210 static void process_drex (void);
211 static int process_operands (void);
212 static const seg_entry *build_modrm_byte (void);
213 static void output_insn (void);
214 static void output_imm (fragS *, offsetT);
215 static void output_disp (fragS *, offsetT);
217 static void s_bss (int);
219 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220 static void handle_large_common (int small ATTRIBUTE_UNUSED);
223 static const char *default_arch = DEFAULT_ARCH;
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes[3];
231 /* Destination or source register specifier. */
232 const reg_entry *register_specifier;
235 /* 'md_assemble ()' gathers together information and puts it into a
242 const reg_entry *regs;
247 /* TM holds the template for the insn were currently assembling. */
250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
254 /* OPERANDS gives the number of given operands. */
255 unsigned int operands;
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
260 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
262 /* TYPES [i] is the type (see above #defines) which tells us how to
263 use OP[i] for the corresponding operand. */
264 i386_operand_type types[MAX_OPERANDS];
266 /* Displacement expression, immediate expression, or register for each
268 union i386_op op[MAX_OPERANDS];
270 /* Flags for operands. */
271 unsigned int flags[MAX_OPERANDS];
272 #define Operand_PCrel 1
274 /* Relocation type for operand */
275 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry *base_reg;
280 const reg_entry *index_reg;
281 unsigned int log2_scale_factor;
283 /* SEG gives the seg_entries of this insn. They are zero unless
284 explicit segment overrides are given. */
285 const seg_entry *seg[2];
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes;
290 unsigned char prefix[MAX_PREFIXES];
292 /* RM and SIB are the modrm byte and the sib byte where the
293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
303 typedef struct _i386_insn i386_insn;
305 /* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
307 const char extra_symbol_chars[] = "*%-(["
316 #if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
318 && !defined (TE_GNU) \
319 && !defined (TE_LINUX) \
320 && !defined (TE_NETWARE) \
321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
323 /* This array holds the chars that always start a comment. If the
324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326 const char *i386_comment_chars = "#/";
327 #define SVR4_COMMENT_CHARS 1
328 #define PREFIX_SEPARATOR '\\'
331 const char *i386_comment_chars = "#";
332 #define PREFIX_SEPARATOR '/'
335 /* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
339 first line of the input file. This is because the compiler outputs
340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
342 '/' isn't otherwise defined. */
343 const char line_comment_chars[] = "#/";
345 const char line_separator_chars[] = ";";
347 /* Chars that can be used to separate mant from exp in floating point
349 const char EXP_CHARS[] = "eE";
351 /* Chars that mean this number is a floating point constant
354 const char FLT_CHARS[] = "fFdDxX";
356 /* Tables for lexical analysis. */
357 static char mnemonic_chars[256];
358 static char register_chars[256];
359 static char operand_chars[256];
360 static char identifier_chars[256];
361 static char digit_chars[256];
363 /* Lexical macros. */
364 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365 #define is_operand_char(x) (operand_chars[(unsigned char) x])
366 #define is_register_char(x) (register_chars[(unsigned char) x])
367 #define is_space_char(x) ((x) == ' ')
368 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369 #define is_digit_char(x) (digit_chars[(unsigned char) x])
371 /* All non-digit non-letter characters that may occur in an operand. */
372 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
374 /* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
377 assembler instruction). */
378 static char save_stack[32];
379 static char *save_stack_p;
380 #define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382 #define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
385 /* The instruction we're assembling. */
388 /* Possible templates for current insn. */
389 static const templates *current_templates;
391 /* Per instruction expressionS buffers: max displacements & immediates. */
392 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
393 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
395 /* Current operand we are working on. */
396 static int this_operand;
398 /* We support four different modes. FLAG_CODE variable is used to distinguish
406 static enum flag_code flag_code;
407 static unsigned int object_64bit;
408 static int use_rela_relocations = 0;
410 /* The names used to print error messages. */
411 static const char *flag_code_names[] =
418 /* 1 for intel syntax,
420 static int intel_syntax = 0;
422 /* 1 for intel mnemonic,
423 0 if att mnemonic. */
424 static int intel_mnemonic = !SYSV386_COMPAT;
426 /* 1 if support old (<= 2.8.1) versions of gcc. */
427 static int old_gcc = OLDGCC_COMPAT;
429 /* 1 if pseudo registers are permitted. */
430 static int allow_pseudo_reg = 0;
432 /* 1 if register prefix % not required. */
433 static int allow_naked_reg = 0;
435 /* 1 if pseudo index register, eiz/riz, is allowed . */
436 static int allow_index_reg = 0;
446 /* Register prefix used for error message. */
447 static const char *register_prefix = "%";
449 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452 static char stackop_size = '\0';
454 /* Non-zero to optimize code alignment. */
455 int optimize_align_code = 1;
457 /* Non-zero to quieten some warnings. */
458 static int quiet_warnings = 0;
461 static const char *cpu_arch_name = NULL;
462 static char *cpu_sub_arch_name = NULL;
464 /* CPU feature flags. */
465 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
467 /* If we have selected a cpu we are generating instructions for. */
468 static int cpu_arch_tune_set = 0;
470 /* Cpu we are generating instructions for. */
471 static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
473 /* CPU feature flags of cpu we are generating instructions for. */
474 static i386_cpu_flags cpu_arch_tune_flags;
476 /* CPU instruction set architecture used. */
477 static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
479 /* CPU feature flags of instruction set architecture used. */
480 static i386_cpu_flags cpu_arch_isa_flags;
482 /* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484 static unsigned int no_cond_jump_promotion = 0;
486 /* Encode SSE instructions with VEX prefix. */
487 static unsigned int sse2avx;
489 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
490 static symbolS *GOT_symbol;
492 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
493 unsigned int x86_dwarf2_return_column;
495 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496 int x86_cie_data_alignment;
498 /* Interface to relax_segment.
499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
504 #define UNCOND_JUMP 0
506 #define COND_JUMP86 2
511 #define SMALL16 (SMALL | CODE16)
513 #define BIG16 (BIG | CODE16)
517 #define INLINE __inline__
523 #define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525 #define TYPE_FROM_RELAX_STATE(s) \
527 #define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
530 /* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
538 const relax_typeS md_relax_table[] =
541 1) most positive reach of this state,
542 2) most negative reach of this state,
543 3) how many bytes this mode will have in the variable part of the frag
544 4) which index into the table to try if we can't fit into this one. */
546 /* UNCOND_JUMP states. */
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
562 /* word conditionals add 3 bytes to frag:
563 1 extra opcode byte, 2 displacement bytes. */
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
577 static const arch_entry cpu_arch[] =
579 { "generic32", PROCESSOR_GENERIC32,
580 CPU_GENERIC32_FLAGS },
581 { "generic64", PROCESSOR_GENERIC64,
582 CPU_GENERIC64_FLAGS },
583 { "i8086", PROCESSOR_UNKNOWN,
585 { "i186", PROCESSOR_UNKNOWN,
587 { "i286", PROCESSOR_UNKNOWN,
589 { "i386", PROCESSOR_I386,
591 { "i486", PROCESSOR_I486,
593 { "i586", PROCESSOR_PENTIUM,
595 { "i686", PROCESSOR_PENTIUMPRO,
597 { "pentium", PROCESSOR_PENTIUM,
599 { "pentiumpro", PROCESSOR_PENTIUMPRO,
601 { "pentiumii", PROCESSOR_PENTIUMPRO,
603 { "pentiumiii",PROCESSOR_PENTIUMPRO,
605 { "pentium4", PROCESSOR_PENTIUM4,
607 { "prescott", PROCESSOR_NOCONA,
609 { "nocona", PROCESSOR_NOCONA,
611 { "yonah", PROCESSOR_CORE,
613 { "core", PROCESSOR_CORE,
615 { "merom", PROCESSOR_CORE2,
617 { "core2", PROCESSOR_CORE2,
619 { "k6", PROCESSOR_K6,
621 { "k6_2", PROCESSOR_K6,
623 { "athlon", PROCESSOR_ATHLON,
625 { "sledgehammer", PROCESSOR_K8,
627 { "opteron", PROCESSOR_K8,
629 { "k8", PROCESSOR_K8,
631 { "amdfam10", PROCESSOR_AMDFAM10,
632 CPU_AMDFAM10_FLAGS },
633 { ".mmx", PROCESSOR_UNKNOWN,
635 { ".sse", PROCESSOR_UNKNOWN,
637 { ".sse2", PROCESSOR_UNKNOWN,
639 { ".sse3", PROCESSOR_UNKNOWN,
641 { ".ssse3", PROCESSOR_UNKNOWN,
643 { ".sse4.1", PROCESSOR_UNKNOWN,
645 { ".sse4.2", PROCESSOR_UNKNOWN,
647 { ".sse4", PROCESSOR_UNKNOWN,
649 { ".avx", PROCESSOR_UNKNOWN,
651 { ".vmx", PROCESSOR_UNKNOWN,
653 { ".smx", PROCESSOR_UNKNOWN,
655 { ".xsave", PROCESSOR_UNKNOWN,
657 { ".aes", PROCESSOR_UNKNOWN,
659 { ".pclmul", PROCESSOR_UNKNOWN,
661 { ".clmul", PROCESSOR_UNKNOWN,
663 { ".fma", PROCESSOR_UNKNOWN,
665 { ".movbe", PROCESSOR_UNKNOWN,
667 { ".ept", PROCESSOR_UNKNOWN,
669 { ".3dnow", PROCESSOR_UNKNOWN,
671 { ".3dnowa", PROCESSOR_UNKNOWN,
673 { ".padlock", PROCESSOR_UNKNOWN,
675 { ".pacifica", PROCESSOR_UNKNOWN,
677 { ".svme", PROCESSOR_UNKNOWN,
679 { ".sse4a", PROCESSOR_UNKNOWN,
681 { ".abm", PROCESSOR_UNKNOWN,
683 { ".sse5", PROCESSOR_UNKNOWN,
687 const pseudo_typeS md_pseudo_table[] =
689 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes, 0},
692 {"align", s_align_ptwo, 0},
694 {"arch", set_cpu_arch, 0},
698 {"ffloat", float_cons, 'f'},
699 {"dfloat", float_cons, 'd'},
700 {"tfloat", float_cons, 'x'},
702 {"slong", signed_cons, 4},
703 {"noopt", s_ignore, 0},
704 {"optim", s_ignore, 0},
705 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
706 {"code16", set_code_flag, CODE_16BIT},
707 {"code32", set_code_flag, CODE_32BIT},
708 {"code64", set_code_flag, CODE_64BIT},
709 {"intel_syntax", set_intel_syntax, 1},
710 {"att_syntax", set_intel_syntax, 0},
711 {"intel_mnemonic", set_intel_mnemonic, 1},
712 {"att_mnemonic", set_intel_mnemonic, 0},
713 {"allow_index_reg", set_allow_index_reg, 1},
714 {"disallow_index_reg", set_allow_index_reg, 0},
715 {"sse_check", set_sse_check, 0},
716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common, 0},
719 {"file", (void (*) (int)) dwarf2_directive_file, 0},
720 {"loc", dwarf2_directive_loc, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
724 {"secrel32", pe_directive_secrel, 0},
729 /* For interface with expression (). */
730 extern char *input_line_pointer;
732 /* Hash table for instruction mnemonic lookup. */
733 static struct hash_control *op_hash;
735 /* Hash table for register lookup. */
736 static struct hash_control *reg_hash;
739 i386_align_code (fragS *fragP, int count)
741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
744 static const char f32_1[] =
746 static const char f32_2[] =
747 {0x66,0x90}; /* xchg %ax,%ax */
748 static const char f32_3[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5[] =
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8[] =
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
780 static const char f16_3[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
782 static const char f16_4[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5[] =
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
796 static const char jump_31[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
801 static const char *const f32_patt[] = {
802 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
803 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
805 static const char *const f16_patt[] = {
806 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
809 static const char alt_3[] =
811 /* nopl 0(%[re]ax) */
812 static const char alt_4[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11[] =
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12[] =
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13[] =
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15[] =
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
889 static const char alt_short_13[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
894 static const char alt_short_14[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt[] = {
903 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
904 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
905 alt_short_14, alt_short_15
907 static const char *const alt_long_patt[] = {
908 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
909 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
910 alt_long_14, alt_long_15
913 /* Only align for at least a positive non-zero boundary. */
914 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
935 if (flag_code == CODE_16BIT)
939 memcpy (fragP->fr_literal + fragP->fr_fix,
941 /* Adjust jump offset. */
942 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
945 memcpy (fragP->fr_literal + fragP->fr_fix,
946 f16_patt[count - 1], count);
950 const char *const *patt = NULL;
952 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune)
957 case PROCESSOR_UNKNOWN:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
960 if (cpu_arch_isa_flags.bitfield.cpui686)
961 patt = alt_long_patt;
965 case PROCESSOR_PENTIUMPRO:
966 case PROCESSOR_PENTIUM4:
967 case PROCESSOR_NOCONA:
969 case PROCESSOR_CORE2:
970 case PROCESSOR_GENERIC64:
971 patt = alt_long_patt;
974 case PROCESSOR_ATHLON:
976 case PROCESSOR_AMDFAM10:
977 patt = alt_short_patt;
981 case PROCESSOR_PENTIUM:
982 case PROCESSOR_GENERIC32:
989 switch (cpu_arch_tune)
991 case PROCESSOR_UNKNOWN:
992 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
993 PROCESSOR_UNKNOWN. */
999 case PROCESSOR_PENTIUM:
1001 case PROCESSOR_ATHLON:
1003 case PROCESSOR_AMDFAM10:
1004 case PROCESSOR_GENERIC32:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1007 if (cpu_arch_isa_flags.bitfield.cpui686)
1008 patt = alt_short_patt;
1012 case PROCESSOR_PENTIUMPRO:
1013 case PROCESSOR_PENTIUM4:
1014 case PROCESSOR_NOCONA:
1015 case PROCESSOR_CORE:
1016 case PROCESSOR_CORE2:
1017 if (cpu_arch_isa_flags.bitfield.cpui686)
1018 patt = alt_long_patt;
1022 case PROCESSOR_GENERIC64:
1023 patt = alt_long_patt;
1028 if (patt == f32_patt)
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1034 memcpy (fragP->fr_literal + fragP->fr_fix,
1035 patt[count - 1], count);
1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding = count;
1050 while (padding > 15)
1053 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1058 memcpy (fragP->fr_literal + fragP->fr_fix,
1059 patt [padding - 1], padding);
1062 fragP->fr_var = count;
1066 operand_type_all_zero (const union i386_operand_type *x)
1068 switch (ARRAY_SIZE(x->array))
1077 return !x->array[0];
1084 operand_type_set (union i386_operand_type *x, unsigned int v)
1086 switch (ARRAY_SIZE(x->array))
1101 operand_type_equal (const union i386_operand_type *x,
1102 const union i386_operand_type *y)
1104 switch (ARRAY_SIZE(x->array))
1107 if (x->array[2] != y->array[2])
1110 if (x->array[1] != y->array[1])
1113 return x->array[0] == y->array[0];
1121 cpu_flags_all_zero (const union i386_cpu_flags *x)
1123 switch (ARRAY_SIZE(x->array))
1132 return !x->array[0];
1139 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1141 switch (ARRAY_SIZE(x->array))
1156 cpu_flags_equal (const union i386_cpu_flags *x,
1157 const union i386_cpu_flags *y)
1159 switch (ARRAY_SIZE(x->array))
1162 if (x->array[2] != y->array[2])
1165 if (x->array[1] != y->array[1])
1168 return x->array[0] == y->array[0];
1176 cpu_flags_check_cpu64 (i386_cpu_flags f)
1178 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1179 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1182 static INLINE i386_cpu_flags
1183 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1185 switch (ARRAY_SIZE (x.array))
1188 x.array [2] &= y.array [2];
1190 x.array [1] &= y.array [1];
1192 x.array [0] &= y.array [0];
1200 static INLINE i386_cpu_flags
1201 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1203 switch (ARRAY_SIZE (x.array))
1206 x.array [2] |= y.array [2];
1208 x.array [1] |= y.array [1];
1210 x.array [0] |= y.array [0];
1218 #define CPU_FLAGS_ARCH_MATCH 0x1
1219 #define CPU_FLAGS_64BIT_MATCH 0x2
1220 #define CPU_FLAGS_AES_MATCH 0x4
1221 #define CPU_FLAGS_AVX_MATCH 0x8
1223 #define CPU_FLAGS_32BIT_MATCH \
1224 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
1225 #define CPU_FLAGS_PERFECT_MATCH \
1226 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1228 /* Return CPU flags match bits. */
1231 cpu_flags_match (const template *t)
1233 i386_cpu_flags x = t->cpu_flags;
1234 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1236 x.bitfield.cpu64 = 0;
1237 x.bitfield.cpuno64 = 0;
1239 if (cpu_flags_all_zero (&x))
1241 /* This instruction is available on all archs. */
1242 match |= CPU_FLAGS_32BIT_MATCH;
1246 /* This instruction is available only on some archs. */
1247 i386_cpu_flags cpu = cpu_arch_flags;
1249 cpu.bitfield.cpu64 = 0;
1250 cpu.bitfield.cpuno64 = 0;
1251 cpu = cpu_flags_and (x, cpu);
1252 if (!cpu_flags_all_zero (&cpu))
1254 if (x.bitfield.cpuavx)
1256 /* We only need to check AES/SSE2AVX with AVX. */
1257 if (cpu.bitfield.cpuavx)
1259 /* Check SSE2AVX. */
1260 if (!t->opcode_modifier.sse2avx|| sse2avx)
1262 match |= (CPU_FLAGS_ARCH_MATCH
1263 | CPU_FLAGS_AVX_MATCH);
1265 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1266 match |= CPU_FLAGS_AES_MATCH;
1270 match |= CPU_FLAGS_ARCH_MATCH;
1273 match |= CPU_FLAGS_32BIT_MATCH;
1279 static INLINE i386_operand_type
1280 operand_type_and (i386_operand_type x, i386_operand_type y)
1282 switch (ARRAY_SIZE (x.array))
1285 x.array [2] &= y.array [2];
1287 x.array [1] &= y.array [1];
1289 x.array [0] &= y.array [0];
1297 static INLINE i386_operand_type
1298 operand_type_or (i386_operand_type x, i386_operand_type y)
1300 switch (ARRAY_SIZE (x.array))
1303 x.array [2] |= y.array [2];
1305 x.array [1] |= y.array [1];
1307 x.array [0] |= y.array [0];
1315 static INLINE i386_operand_type
1316 operand_type_xor (i386_operand_type x, i386_operand_type y)
1318 switch (ARRAY_SIZE (x.array))
1321 x.array [2] ^= y.array [2];
1323 x.array [1] ^= y.array [1];
1325 x.array [0] ^= y.array [0];
1333 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1334 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1335 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1336 static const i386_operand_type inoutportreg
1337 = OPERAND_TYPE_INOUTPORTREG;
1338 static const i386_operand_type reg16_inoutportreg
1339 = OPERAND_TYPE_REG16_INOUTPORTREG;
1340 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1341 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1342 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1343 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1344 static const i386_operand_type anydisp
1345 = OPERAND_TYPE_ANYDISP;
1346 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1347 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1348 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1349 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1350 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1351 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1352 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1353 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1354 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1355 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1356 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1357 static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
1368 operand_type_check (i386_operand_type t, enum operand_type c)
1373 return (t.bitfield.reg8
1376 || t.bitfield.reg64);
1379 return (t.bitfield.imm8
1383 || t.bitfield.imm32s
1384 || t.bitfield.imm64);
1387 return (t.bitfield.disp8
1388 || t.bitfield.disp16
1389 || t.bitfield.disp32
1390 || t.bitfield.disp32s
1391 || t.bitfield.disp64);
1394 return (t.bitfield.disp8
1395 || t.bitfield.disp16
1396 || t.bitfield.disp32
1397 || t.bitfield.disp32s
1398 || t.bitfield.disp64
1399 || t.bitfield.baseindex);
1408 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1409 operand J for instruction template T. */
1412 match_reg_size (const template *t, unsigned int j)
1414 return !((i.types[j].bitfield.byte
1415 && !t->operand_types[j].bitfield.byte)
1416 || (i.types[j].bitfield.word
1417 && !t->operand_types[j].bitfield.word)
1418 || (i.types[j].bitfield.dword
1419 && !t->operand_types[j].bitfield.dword)
1420 || (i.types[j].bitfield.qword
1421 && !t->operand_types[j].bitfield.qword));
1424 /* Return 1 if there is no conflict in any size on operand J for
1425 instruction template T. */
1428 match_mem_size (const template *t, unsigned int j)
1430 return (match_reg_size (t, j)
1431 && !((i.types[j].bitfield.unspecified
1432 && !t->operand_types[j].bitfield.unspecified)
1433 || (i.types[j].bitfield.fword
1434 && !t->operand_types[j].bitfield.fword)
1435 || (i.types[j].bitfield.tbyte
1436 && !t->operand_types[j].bitfield.tbyte)
1437 || (i.types[j].bitfield.xmmword
1438 && !t->operand_types[j].bitfield.xmmword)
1439 || (i.types[j].bitfield.ymmword
1440 && !t->operand_types[j].bitfield.ymmword)));
1443 /* Return 1 if there is no size conflict on any operands for
1444 instruction template T. */
1447 operand_size_match (const template *t)
1452 /* Don't check jump instructions. */
1453 if (t->opcode_modifier.jump
1454 || t->opcode_modifier.jumpbyte
1455 || t->opcode_modifier.jumpdword
1456 || t->opcode_modifier.jumpintersegment)
1459 /* Check memory and accumulator operand size. */
1460 for (j = 0; j < i.operands; j++)
1462 if (t->operand_types[j].bitfield.anysize)
1465 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1471 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1479 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1482 /* Check reverse. */
1483 assert (i.operands == 2);
1486 for (j = 0; j < 2; j++)
1488 if (t->operand_types[j].bitfield.acc
1489 && !match_reg_size (t, j ? 0 : 1))
1495 if (i.types[j].bitfield.mem
1496 && !match_mem_size (t, j ? 0 : 1))
1507 operand_type_match (i386_operand_type overlap,
1508 i386_operand_type given)
1510 i386_operand_type temp = overlap;
1512 temp.bitfield.jumpabsolute = 0;
1513 temp.bitfield.unspecified = 0;
1514 temp.bitfield.byte = 0;
1515 temp.bitfield.word = 0;
1516 temp.bitfield.dword = 0;
1517 temp.bitfield.fword = 0;
1518 temp.bitfield.qword = 0;
1519 temp.bitfield.tbyte = 0;
1520 temp.bitfield.xmmword = 0;
1521 temp.bitfield.ymmword = 0;
1522 if (operand_type_all_zero (&temp))
1525 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1526 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1529 /* If given types g0 and g1 are registers they must be of the same type
1530 unless the expected operand type register overlap is null.
1531 Note that Acc in a template matches every size of reg. */
1534 operand_type_register_match (i386_operand_type m0,
1535 i386_operand_type g0,
1536 i386_operand_type t0,
1537 i386_operand_type m1,
1538 i386_operand_type g1,
1539 i386_operand_type t1)
1541 if (!operand_type_check (g0, reg))
1544 if (!operand_type_check (g1, reg))
1547 if (g0.bitfield.reg8 == g1.bitfield.reg8
1548 && g0.bitfield.reg16 == g1.bitfield.reg16
1549 && g0.bitfield.reg32 == g1.bitfield.reg32
1550 && g0.bitfield.reg64 == g1.bitfield.reg64)
1553 if (m0.bitfield.acc)
1555 t0.bitfield.reg8 = 1;
1556 t0.bitfield.reg16 = 1;
1557 t0.bitfield.reg32 = 1;
1558 t0.bitfield.reg64 = 1;
1561 if (m1.bitfield.acc)
1563 t1.bitfield.reg8 = 1;
1564 t1.bitfield.reg16 = 1;
1565 t1.bitfield.reg32 = 1;
1566 t1.bitfield.reg64 = 1;
1569 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1570 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1571 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1572 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1575 static INLINE unsigned int
1576 mode_from_disp_size (i386_operand_type t)
1578 if (t.bitfield.disp8)
1580 else if (t.bitfield.disp16
1581 || t.bitfield.disp32
1582 || t.bitfield.disp32s)
1589 fits_in_signed_byte (offsetT num)
1591 return (num >= -128) && (num <= 127);
1595 fits_in_unsigned_byte (offsetT num)
1597 return (num & 0xff) == num;
1601 fits_in_unsigned_word (offsetT num)
1603 return (num & 0xffff) == num;
1607 fits_in_signed_word (offsetT num)
1609 return (-32768 <= num) && (num <= 32767);
1613 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1618 return (!(((offsetT) -1 << 31) & num)
1619 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1621 } /* fits_in_signed_long() */
1624 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1629 return (num & (((offsetT) 2 << 31) - 1)) == num;
1631 } /* fits_in_unsigned_long() */
1634 fits_in_imm4 (offsetT num)
1636 return (num & 0xf) == num;
1639 static i386_operand_type
1640 smallest_imm_type (offsetT num)
1642 i386_operand_type t;
1644 operand_type_set (&t, 0);
1645 t.bitfield.imm64 = 1;
1647 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1649 /* This code is disabled on the 486 because all the Imm1 forms
1650 in the opcode table are slower on the i486. They're the
1651 versions with the implicitly specified single-position
1652 displacement, which has another syntax if you really want to
1654 t.bitfield.imm1 = 1;
1655 t.bitfield.imm8 = 1;
1656 t.bitfield.imm8s = 1;
1657 t.bitfield.imm16 = 1;
1658 t.bitfield.imm32 = 1;
1659 t.bitfield.imm32s = 1;
1661 else if (fits_in_signed_byte (num))
1663 t.bitfield.imm8 = 1;
1664 t.bitfield.imm8s = 1;
1665 t.bitfield.imm16 = 1;
1666 t.bitfield.imm32 = 1;
1667 t.bitfield.imm32s = 1;
1669 else if (fits_in_unsigned_byte (num))
1671 t.bitfield.imm8 = 1;
1672 t.bitfield.imm16 = 1;
1673 t.bitfield.imm32 = 1;
1674 t.bitfield.imm32s = 1;
1676 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1678 t.bitfield.imm16 = 1;
1679 t.bitfield.imm32 = 1;
1680 t.bitfield.imm32s = 1;
1682 else if (fits_in_signed_long (num))
1684 t.bitfield.imm32 = 1;
1685 t.bitfield.imm32s = 1;
1687 else if (fits_in_unsigned_long (num))
1688 t.bitfield.imm32 = 1;
1694 offset_in_range (offsetT val, int size)
1700 case 1: mask = ((addressT) 1 << 8) - 1; break;
1701 case 2: mask = ((addressT) 1 << 16) - 1; break;
1702 case 4: mask = ((addressT) 2 << 31) - 1; break;
1704 case 8: mask = ((addressT) 2 << 63) - 1; break;
1709 /* If BFD64, sign extend val. */
1710 if (!use_rela_relocations)
1711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1716 char buf1[40], buf2[40];
1718 sprint_value (buf1, val);
1719 sprint_value (buf2, val & mask);
1720 as_warn (_("%s shortened to %s"), buf1, buf2);
1725 /* Returns 0 if attempting to add a prefix where one from the same
1726 class already exists, 1 if non rep/repne added, 2 if rep/repne
1729 add_prefix (unsigned int prefix)
1734 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1735 && flag_code == CODE_64BIT)
1737 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1738 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1739 && (prefix & (REX_R | REX_X | REX_B))))
1750 case CS_PREFIX_OPCODE:
1751 case DS_PREFIX_OPCODE:
1752 case ES_PREFIX_OPCODE:
1753 case FS_PREFIX_OPCODE:
1754 case GS_PREFIX_OPCODE:
1755 case SS_PREFIX_OPCODE:
1759 case REPNE_PREFIX_OPCODE:
1760 case REPE_PREFIX_OPCODE:
1763 case LOCK_PREFIX_OPCODE:
1771 case ADDR_PREFIX_OPCODE:
1775 case DATA_PREFIX_OPCODE:
1779 if (i.prefix[q] != 0)
1787 i.prefix[q] |= prefix;
1790 as_bad (_("same type of prefix used twice"));
1796 set_code_flag (int value)
1799 if (flag_code == CODE_64BIT)
1801 cpu_arch_flags.bitfield.cpu64 = 1;
1802 cpu_arch_flags.bitfield.cpuno64 = 0;
1806 cpu_arch_flags.bitfield.cpu64 = 0;
1807 cpu_arch_flags.bitfield.cpuno64 = 1;
1809 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1811 as_bad (_("64bit mode not supported on this CPU."));
1813 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1815 as_bad (_("32bit mode not supported on this CPU."));
1817 stackop_size = '\0';
1821 set_16bit_gcc_code_flag (int new_code_flag)
1823 flag_code = new_code_flag;
1824 if (flag_code != CODE_16BIT)
1826 cpu_arch_flags.bitfield.cpu64 = 0;
1827 cpu_arch_flags.bitfield.cpuno64 = 1;
1828 stackop_size = LONG_MNEM_SUFFIX;
1832 set_intel_syntax (int syntax_flag)
1834 /* Find out if register prefixing is specified. */
1835 int ask_naked_reg = 0;
1838 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1840 char *string = input_line_pointer;
1841 int e = get_symbol_end ();
1843 if (strcmp (string, "prefix") == 0)
1845 else if (strcmp (string, "noprefix") == 0)
1848 as_bad (_("bad argument to syntax directive."));
1849 *input_line_pointer = e;
1851 demand_empty_rest_of_line ();
1853 intel_syntax = syntax_flag;
1855 if (ask_naked_reg == 0)
1856 allow_naked_reg = (intel_syntax
1857 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1859 allow_naked_reg = (ask_naked_reg < 0);
1861 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1862 identifier_chars['$'] = intel_syntax ? '$' : 0;
1863 register_prefix = allow_naked_reg ? "" : "%";
1867 set_intel_mnemonic (int mnemonic_flag)
1869 intel_mnemonic = mnemonic_flag;
1873 set_allow_index_reg (int flag)
1875 allow_index_reg = flag;
1879 set_sse_check (int dummy ATTRIBUTE_UNUSED)
1883 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1885 char *string = input_line_pointer;
1886 int e = get_symbol_end ();
1888 if (strcmp (string, "none") == 0)
1889 sse_check = sse_check_none;
1890 else if (strcmp (string, "warning") == 0)
1891 sse_check = sse_check_warning;
1892 else if (strcmp (string, "error") == 0)
1893 sse_check = sse_check_error;
1895 as_bad (_("bad argument to sse_check directive."));
1896 *input_line_pointer = e;
1899 as_bad (_("missing argument for sse_check directive"));
1901 demand_empty_rest_of_line ();
1905 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1909 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1911 char *string = input_line_pointer;
1912 int e = get_symbol_end ();
1914 i386_cpu_flags flags;
1916 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1918 if (strcmp (string, cpu_arch[i].name) == 0)
1922 cpu_arch_name = cpu_arch[i].name;
1923 cpu_sub_arch_name = NULL;
1924 cpu_arch_flags = cpu_arch[i].flags;
1925 if (flag_code == CODE_64BIT)
1927 cpu_arch_flags.bitfield.cpu64 = 1;
1928 cpu_arch_flags.bitfield.cpuno64 = 0;
1932 cpu_arch_flags.bitfield.cpu64 = 0;
1933 cpu_arch_flags.bitfield.cpuno64 = 1;
1935 cpu_arch_isa = cpu_arch[i].type;
1936 cpu_arch_isa_flags = cpu_arch[i].flags;
1937 if (!cpu_arch_tune_set)
1939 cpu_arch_tune = cpu_arch_isa;
1940 cpu_arch_tune_flags = cpu_arch_isa_flags;
1945 flags = cpu_flags_or (cpu_arch_flags,
1947 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1949 if (cpu_sub_arch_name)
1951 char *name = cpu_sub_arch_name;
1952 cpu_sub_arch_name = concat (name,
1954 (const char *) NULL);
1958 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1959 cpu_arch_flags = flags;
1961 *input_line_pointer = e;
1962 demand_empty_rest_of_line ();
1966 if (i >= ARRAY_SIZE (cpu_arch))
1967 as_bad (_("no such architecture: `%s'"), string);
1969 *input_line_pointer = e;
1972 as_bad (_("missing cpu architecture"));
1974 no_cond_jump_promotion = 0;
1975 if (*input_line_pointer == ','
1976 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1978 char *string = ++input_line_pointer;
1979 int e = get_symbol_end ();
1981 if (strcmp (string, "nojumps") == 0)
1982 no_cond_jump_promotion = 1;
1983 else if (strcmp (string, "jumps") == 0)
1986 as_bad (_("no such architecture modifier: `%s'"), string);
1988 *input_line_pointer = e;
1991 demand_empty_rest_of_line ();
1997 if (!strcmp (default_arch, "x86_64"))
1998 return bfd_mach_x86_64;
1999 else if (!strcmp (default_arch, "i386"))
2000 return bfd_mach_i386_i386;
2002 as_fatal (_("Unknown architecture"));
2008 const char *hash_err;
2010 /* Initialize op_hash hash table. */
2011 op_hash = hash_new ();
2014 const template *optab;
2015 templates *core_optab;
2017 /* Setup for loop. */
2019 core_optab = (templates *) xmalloc (sizeof (templates));
2020 core_optab->start = optab;
2025 if (optab->name == NULL
2026 || strcmp (optab->name, (optab - 1)->name) != 0)
2028 /* different name --> ship out current template list;
2029 add to hash table; & begin anew. */
2030 core_optab->end = optab;
2031 hash_err = hash_insert (op_hash,
2033 (void *) core_optab);
2036 as_fatal (_("Internal Error: Can't hash %s: %s"),
2040 if (optab->name == NULL)
2042 core_optab = (templates *) xmalloc (sizeof (templates));
2043 core_optab->start = optab;
2048 /* Initialize reg_hash hash table. */
2049 reg_hash = hash_new ();
2051 const reg_entry *regtab;
2052 unsigned int regtab_size = i386_regtab_size;
2054 for (regtab = i386_regtab; regtab_size--; regtab++)
2056 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2058 as_fatal (_("Internal Error: Can't hash %s: %s"),
2064 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2069 for (c = 0; c < 256; c++)
2074 mnemonic_chars[c] = c;
2075 register_chars[c] = c;
2076 operand_chars[c] = c;
2078 else if (ISLOWER (c))
2080 mnemonic_chars[c] = c;
2081 register_chars[c] = c;
2082 operand_chars[c] = c;
2084 else if (ISUPPER (c))
2086 mnemonic_chars[c] = TOLOWER (c);
2087 register_chars[c] = mnemonic_chars[c];
2088 operand_chars[c] = c;
2091 if (ISALPHA (c) || ISDIGIT (c))
2092 identifier_chars[c] = c;
2095 identifier_chars[c] = c;
2096 operand_chars[c] = c;
2101 identifier_chars['@'] = '@';
2104 identifier_chars['?'] = '?';
2105 operand_chars['?'] = '?';
2107 digit_chars['-'] = '-';
2108 mnemonic_chars['_'] = '_';
2109 mnemonic_chars['-'] = '-';
2110 mnemonic_chars['.'] = '.';
2111 identifier_chars['_'] = '_';
2112 identifier_chars['.'] = '.';
2114 for (p = operand_special_chars; *p != '\0'; p++)
2115 operand_chars[(unsigned char) *p] = *p;
2118 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2121 record_alignment (text_section, 2);
2122 record_alignment (data_section, 2);
2123 record_alignment (bss_section, 2);
2127 if (flag_code == CODE_64BIT)
2129 x86_dwarf2_return_column = 16;
2130 x86_cie_data_alignment = -8;
2134 x86_dwarf2_return_column = 8;
2135 x86_cie_data_alignment = -4;
2140 i386_print_statistics (FILE *file)
2142 hash_print_statistics (file, "i386 opcode", op_hash);
2143 hash_print_statistics (file, "i386 register", reg_hash);
2148 /* Debugging routines for md_assemble. */
2149 static void pte (template *);
2150 static void pt (i386_operand_type);
2151 static void pe (expressionS *);
2152 static void ps (symbolS *);
2155 pi (char *line, i386_insn *x)
2159 fprintf (stdout, "%s: template ", line);
2161 fprintf (stdout, " address: base %s index %s scale %x\n",
2162 x->base_reg ? x->base_reg->reg_name : "none",
2163 x->index_reg ? x->index_reg->reg_name : "none",
2164 x->log2_scale_factor);
2165 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2166 x->rm.mode, x->rm.reg, x->rm.regmem);
2167 fprintf (stdout, " sib: base %x index %x scale %x\n",
2168 x->sib.base, x->sib.index, x->sib.scale);
2169 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2170 (x->rex & REX_W) != 0,
2171 (x->rex & REX_R) != 0,
2172 (x->rex & REX_X) != 0,
2173 (x->rex & REX_B) != 0);
2174 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2175 x->drex.reg, x->drex.rex);
2176 for (i = 0; i < x->operands; i++)
2178 fprintf (stdout, " #%d: ", i + 1);
2180 fprintf (stdout, "\n");
2181 if (x->types[i].bitfield.reg8
2182 || x->types[i].bitfield.reg16
2183 || x->types[i].bitfield.reg32
2184 || x->types[i].bitfield.reg64
2185 || x->types[i].bitfield.regmmx
2186 || x->types[i].bitfield.regxmm
2187 || x->types[i].bitfield.regymm
2188 || x->types[i].bitfield.sreg2
2189 || x->types[i].bitfield.sreg3
2190 || x->types[i].bitfield.control
2191 || x->types[i].bitfield.debug
2192 || x->types[i].bitfield.test)
2193 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2194 if (operand_type_check (x->types[i], imm))
2196 if (operand_type_check (x->types[i], disp))
2197 pe (x->op[i].disps);
2205 fprintf (stdout, " %d operands ", t->operands);
2206 fprintf (stdout, "opcode %x ", t->base_opcode);
2207 if (t->extension_opcode != None)
2208 fprintf (stdout, "ext %x ", t->extension_opcode);
2209 if (t->opcode_modifier.d)
2210 fprintf (stdout, "D");
2211 if (t->opcode_modifier.w)
2212 fprintf (stdout, "W");
2213 fprintf (stdout, "\n");
2214 for (i = 0; i < t->operands; i++)
2216 fprintf (stdout, " #%d type ", i + 1);
2217 pt (t->operand_types[i]);
2218 fprintf (stdout, "\n");
2225 fprintf (stdout, " operation %d\n", e->X_op);
2226 fprintf (stdout, " add_number %ld (%lx)\n",
2227 (long) e->X_add_number, (long) e->X_add_number);
2228 if (e->X_add_symbol)
2230 fprintf (stdout, " add_symbol ");
2231 ps (e->X_add_symbol);
2232 fprintf (stdout, "\n");
2236 fprintf (stdout, " op_symbol ");
2237 ps (e->X_op_symbol);
2238 fprintf (stdout, "\n");
2245 fprintf (stdout, "%s type %s%s",
2247 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2248 segment_name (S_GET_SEGMENT (s)));
2251 static struct type_name
2253 i386_operand_type mask;
2256 const type_names[] =
2258 { OPERAND_TYPE_REG8, "r8" },
2259 { OPERAND_TYPE_REG16, "r16" },
2260 { OPERAND_TYPE_REG32, "r32" },
2261 { OPERAND_TYPE_REG64, "r64" },
2262 { OPERAND_TYPE_IMM8, "i8" },
2263 { OPERAND_TYPE_IMM8, "i8s" },
2264 { OPERAND_TYPE_IMM16, "i16" },
2265 { OPERAND_TYPE_IMM32, "i32" },
2266 { OPERAND_TYPE_IMM32S, "i32s" },
2267 { OPERAND_TYPE_IMM64, "i64" },
2268 { OPERAND_TYPE_IMM1, "i1" },
2269 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2270 { OPERAND_TYPE_DISP8, "d8" },
2271 { OPERAND_TYPE_DISP16, "d16" },
2272 { OPERAND_TYPE_DISP32, "d32" },
2273 { OPERAND_TYPE_DISP32S, "d32s" },
2274 { OPERAND_TYPE_DISP64, "d64" },
2275 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2276 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2277 { OPERAND_TYPE_CONTROL, "control reg" },
2278 { OPERAND_TYPE_TEST, "test reg" },
2279 { OPERAND_TYPE_DEBUG, "debug reg" },
2280 { OPERAND_TYPE_FLOATREG, "FReg" },
2281 { OPERAND_TYPE_FLOATACC, "FAcc" },
2282 { OPERAND_TYPE_SREG2, "SReg2" },
2283 { OPERAND_TYPE_SREG3, "SReg3" },
2284 { OPERAND_TYPE_ACC, "Acc" },
2285 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2286 { OPERAND_TYPE_REGMMX, "rMMX" },
2287 { OPERAND_TYPE_REGXMM, "rXMM" },
2288 { OPERAND_TYPE_ESSEG, "es" },
2289 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
2293 pt (i386_operand_type t)
2296 i386_operand_type a;
2298 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2300 a = operand_type_and (t, type_names[j].mask);
2301 if (!UINTS_ALL_ZERO (a))
2302 fprintf (stdout, "%s, ", type_names[j].name);
2307 #endif /* DEBUG386 */
2309 static bfd_reloc_code_real_type
2310 reloc (unsigned int size,
2313 bfd_reloc_code_real_type other)
2315 if (other != NO_RELOC)
2317 reloc_howto_type *reloc;
2322 case BFD_RELOC_X86_64_GOT32:
2323 return BFD_RELOC_X86_64_GOT64;
2325 case BFD_RELOC_X86_64_PLTOFF64:
2326 return BFD_RELOC_X86_64_PLTOFF64;
2328 case BFD_RELOC_X86_64_GOTPC32:
2329 other = BFD_RELOC_X86_64_GOTPC64;
2331 case BFD_RELOC_X86_64_GOTPCREL:
2332 other = BFD_RELOC_X86_64_GOTPCREL64;
2334 case BFD_RELOC_X86_64_TPOFF32:
2335 other = BFD_RELOC_X86_64_TPOFF64;
2337 case BFD_RELOC_X86_64_DTPOFF32:
2338 other = BFD_RELOC_X86_64_DTPOFF64;
2344 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2345 if (size == 4 && flag_code != CODE_64BIT)
2348 reloc = bfd_reloc_type_lookup (stdoutput, other);
2350 as_bad (_("unknown relocation (%u)"), other);
2351 else if (size != bfd_get_reloc_size (reloc))
2352 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2353 bfd_get_reloc_size (reloc),
2355 else if (pcrel && !reloc->pc_relative)
2356 as_bad (_("non-pc-relative relocation for pc-relative field"));
2357 else if ((reloc->complain_on_overflow == complain_overflow_signed
2359 || (reloc->complain_on_overflow == complain_overflow_unsigned
2361 as_bad (_("relocated field and relocation type differ in signedness"));
2370 as_bad (_("there are no unsigned pc-relative relocations"));
2373 case 1: return BFD_RELOC_8_PCREL;
2374 case 2: return BFD_RELOC_16_PCREL;
2375 case 4: return BFD_RELOC_32_PCREL;
2376 case 8: return BFD_RELOC_64_PCREL;
2378 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2385 case 4: return BFD_RELOC_X86_64_32S;
2390 case 1: return BFD_RELOC_8;
2391 case 2: return BFD_RELOC_16;
2392 case 4: return BFD_RELOC_32;
2393 case 8: return BFD_RELOC_64;
2395 as_bad (_("cannot do %s %u byte relocation"),
2396 sign > 0 ? "signed" : "unsigned", size);
2400 return BFD_RELOC_NONE;
2403 /* Here we decide which fixups can be adjusted to make them relative to
2404 the beginning of the section instead of the symbol. Basically we need
2405 to make sure that the dynamic relocations are done correctly, so in
2406 some cases we force the original symbol to be used. */
2409 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2415 /* Don't adjust pc-relative references to merge sections in 64-bit
2417 if (use_rela_relocations
2418 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2422 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2423 and changed later by validate_fix. */
2424 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2425 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2428 /* adjust_reloc_syms doesn't know about the GOT. */
2429 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2430 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2431 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2432 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2433 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2434 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2435 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2436 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2437 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2438 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2439 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2440 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2441 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2442 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2443 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2444 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2445 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2446 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2447 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2448 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2449 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2450 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2451 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2452 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2453 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2454 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2455 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2456 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2463 intel_float_operand (const char *mnemonic)
2465 /* Note that the value returned is meaningful only for opcodes with (memory)
2466 operands, hence the code here is free to improperly handle opcodes that
2467 have no operands (for better performance and smaller code). */
2469 if (mnemonic[0] != 'f')
2470 return 0; /* non-math */
2472 switch (mnemonic[1])
2474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2475 the fs segment override prefix not currently handled because no
2476 call path can make opcodes without operands get here */
2478 return 2 /* integer op */;
2480 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2481 return 3; /* fldcw/fldenv */
2484 if (mnemonic[2] != 'o' /* fnop */)
2485 return 3; /* non-waiting control op */
2488 if (mnemonic[2] == 's')
2489 return 3; /* frstor/frstpm */
2492 if (mnemonic[2] == 'a')
2493 return 3; /* fsave */
2494 if (mnemonic[2] == 't')
2496 switch (mnemonic[3])
2498 case 'c': /* fstcw */
2499 case 'd': /* fstdw */
2500 case 'e': /* fstenv */
2501 case 's': /* fsts[gw] */
2507 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2508 return 0; /* fxsave/fxrstor are not really math ops */
2515 /* Build the VEX prefix. */
2518 build_vex_prefix (void)
2520 unsigned int register_specifier;
2521 unsigned int implied_prefix;
2522 unsigned int vector_length;
2524 /* Check register specifier. */
2525 if (i.vex.register_specifier)
2527 register_specifier = i.vex.register_specifier->reg_num;
2528 if ((i.vex.register_specifier->reg_flags & RegRex))
2529 register_specifier += 8;
2530 register_specifier = ~register_specifier & 0xf;
2533 register_specifier = 0xf;
2535 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2537 switch ((i.tm.base_opcode >> 8) & 0xff)
2542 case DATA_PREFIX_OPCODE:
2545 case REPE_PREFIX_OPCODE:
2548 case REPNE_PREFIX_OPCODE:
2555 /* Use 2-byte VEX prefix if possible. */
2556 if (i.tm.opcode_modifier.vex0f
2557 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2559 /* 2-byte VEX prefix. */
2563 i.vex.bytes[0] = 0xc5;
2565 /* Check the REX.R bit. */
2566 r = (i.rex & REX_R) ? 0 : 1;
2567 i.vex.bytes[1] = (r << 7
2568 | register_specifier << 3
2569 | vector_length << 2
2574 /* 3-byte VEX prefix. */
2577 if (i.tm.opcode_modifier.vex0f)
2579 else if (i.tm.opcode_modifier.vex0f38)
2581 else if (i.tm.opcode_modifier.vex0f3a)
2587 i.vex.bytes[0] = 0xc4;
2589 /* The high 3 bits of the second VEX byte are 1's compliment
2590 of RXB bits from REX. */
2591 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2593 /* Check the REX.W bit. */
2594 w = (i.rex & REX_W) ? 1 : 0;
2595 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2600 if (i.tm.opcode_modifier.vexw1)
2604 i.vex.bytes[2] = (w << 7
2605 | register_specifier << 3
2606 | vector_length << 2
2612 process_immext (void)
2616 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2618 /* SSE3 Instructions have the fixed operands with an opcode
2619 suffix which is coded in the same place as an 8-bit immediate
2620 field would be. Here we check those operands and remove them
2624 for (x = 0; x < i.operands; x++)
2625 if (i.op[x].regs->reg_num != x)
2626 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2627 register_prefix, i.op[x].regs->reg_name, x + 1,
2633 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2634 which is coded in the same place as an 8-bit immediate field
2635 would be. Here we fake an 8-bit immediate operand from the
2636 opcode suffix stored in tm.extension_opcode.
2638 SSE5 and AVX instructions also use this encoding, for some of
2639 3 argument instructions. */
2641 assert (i.imm_operands == 0
2643 || (i.tm.cpu_flags.bitfield.cpusse5
2645 || (i.tm.opcode_modifier.vex
2646 && i.operands <= 4)));
2648 exp = &im_expressions[i.imm_operands++];
2649 i.op[i.operands].imms = exp;
2650 i.types[i.operands] = imm8;
2652 exp->X_op = O_constant;
2653 exp->X_add_number = i.tm.extension_opcode;
2654 i.tm.extension_opcode = None;
2657 /* This is the guts of the machine-dependent assembler. LINE points to a
2658 machine dependent instruction. This function is supposed to emit
2659 the frags/bytes it assembles to. */
2662 md_assemble (char *line)
2665 char mnemonic[MAX_MNEM_SIZE];
2667 /* Initialize globals. */
2668 memset (&i, '\0', sizeof (i));
2669 for (j = 0; j < MAX_OPERANDS; j++)
2670 i.reloc[j] = NO_RELOC;
2671 memset (disp_expressions, '\0', sizeof (disp_expressions));
2672 memset (im_expressions, '\0', sizeof (im_expressions));
2673 save_stack_p = save_stack;
2675 /* First parse an instruction mnemonic & call i386_operand for the operands.
2676 We assume that the scrubber has arranged it so that line[0] is the valid
2677 start of a (possibly prefixed) mnemonic. */
2679 line = parse_insn (line, mnemonic);
2683 line = parse_operands (line, mnemonic);
2687 /* Now we've parsed the mnemonic into a set of templates, and have the
2688 operands at hand. */
2690 /* All intel opcodes have reversed operands except for "bound" and
2691 "enter". We also don't reverse intersegment "jmp" and "call"
2692 instructions with 2 immediate operands so that the immediate segment
2693 precedes the offset, as it does when in AT&T mode. */
2696 && (strcmp (mnemonic, "bound") != 0)
2697 && (strcmp (mnemonic, "invlpga") != 0)
2698 && !(operand_type_check (i.types[0], imm)
2699 && operand_type_check (i.types[1], imm)))
2702 /* The order of the immediates should be reversed
2703 for 2 immediates extrq and insertq instructions */
2704 if (i.imm_operands == 2
2705 && (strcmp (mnemonic, "extrq") == 0
2706 || strcmp (mnemonic, "insertq") == 0))
2707 swap_2_operands (0, 1);
2712 /* Don't optimize displacement for movabs since it only takes 64bit
2715 && (flag_code != CODE_64BIT
2716 || strcmp (mnemonic, "movabs") != 0))
2719 /* Next, we find a template that matches the given insn,
2720 making sure the overlap of the given operands types is consistent
2721 with the template operand types. */
2723 if (!match_template ())
2726 if (sse_check != sse_check_none
2727 && !i.tm.opcode_modifier.noavx
2728 && (i.tm.cpu_flags.bitfield.cpusse
2729 || i.tm.cpu_flags.bitfield.cpusse2
2730 || i.tm.cpu_flags.bitfield.cpusse3
2731 || i.tm.cpu_flags.bitfield.cpussse3
2732 || i.tm.cpu_flags.bitfield.cpusse4_1
2733 || i.tm.cpu_flags.bitfield.cpusse4_2))
2735 (sse_check == sse_check_warning
2737 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2740 /* Zap movzx and movsx suffix. The suffix has been set from
2741 "word ptr" or "byte ptr" on the source operand in Intel syntax
2742 or extracted from mnemonic in AT&T syntax. But we'll use
2743 the destination register to choose the suffix for encoding. */
2744 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2746 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2747 there is no suffix, the default will be byte extension. */
2748 if (i.reg_operands != 2
2751 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2756 if (i.tm.opcode_modifier.fwait)
2757 if (!add_prefix (FWAIT_OPCODE))
2760 /* Check string instruction segment overrides. */
2761 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2763 if (!check_string ())
2767 if (!process_suffix ())
2770 /* Make still unresolved immediate matches conform to size of immediate
2771 given in i.suffix. */
2772 if (!finalize_imm ())
2775 if (i.types[0].bitfield.imm1)
2776 i.imm_operands = 0; /* kludge for shift insns. */
2778 for (j = 0; j < 3; j++)
2779 if (i.types[j].bitfield.inoutportreg
2780 || i.types[j].bitfield.shiftcount
2781 || i.types[j].bitfield.acc
2782 || i.types[j].bitfield.floatacc)
2785 /* ImmExt should be processed after SSE2AVX. */
2786 if (!i.tm.opcode_modifier.sse2avx
2787 && i.tm.opcode_modifier.immext)
2790 /* For insns with operands there are more diddles to do to the opcode. */
2793 if (!process_operands ())
2796 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2798 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2799 as_warn (_("translating to `%sp'"), i.tm.name);
2802 if (i.tm.opcode_modifier.vex)
2803 build_vex_prefix ();
2805 /* Handle conversion of 'int $3' --> special int3 insn. */
2806 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2808 i.tm.base_opcode = INT3_OPCODE;
2812 if ((i.tm.opcode_modifier.jump
2813 || i.tm.opcode_modifier.jumpbyte
2814 || i.tm.opcode_modifier.jumpdword)
2815 && i.op[0].disps->X_op == O_constant)
2817 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2818 the absolute address given by the constant. Since ix86 jumps and
2819 calls are pc relative, we need to generate a reloc. */
2820 i.op[0].disps->X_add_symbol = &abs_symbol;
2821 i.op[0].disps->X_op = O_symbol;
2824 if (i.tm.opcode_modifier.rex64)
2827 /* For 8 bit registers we need an empty rex prefix. Also if the
2828 instruction already has a prefix, we need to convert old
2829 registers to new ones. */
2831 if ((i.types[0].bitfield.reg8
2832 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2833 || (i.types[1].bitfield.reg8
2834 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2835 || ((i.types[0].bitfield.reg8
2836 || i.types[1].bitfield.reg8)
2841 i.rex |= REX_OPCODE;
2842 for (x = 0; x < 2; x++)
2844 /* Look for 8 bit operand that uses old registers. */
2845 if (i.types[x].bitfield.reg8
2846 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2848 /* In case it is "hi" register, give up. */
2849 if (i.op[x].regs->reg_num > 3)
2850 as_bad (_("can't encode register '%s%s' in an "
2851 "instruction requiring REX prefix."),
2852 register_prefix, i.op[x].regs->reg_name);
2854 /* Otherwise it is equivalent to the extended register.
2855 Since the encoding doesn't change this is merely
2856 cosmetic cleanup for debug output. */
2858 i.op[x].regs = i.op[x].regs + 8;
2863 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2865 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2870 else if (i.rex != 0)
2871 add_prefix (REX_OPCODE | i.rex);
2873 /* We are ready to output the insn. */
2878 parse_insn (char *line, char *mnemonic)
2881 char *token_start = l;
2886 /* Non-zero if we found a prefix only acceptable with string insns. */
2887 const char *expecting_string_instruction = NULL;
2892 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2895 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2897 as_bad (_("no such instruction: `%s'"), token_start);
2902 if (!is_space_char (*l)
2903 && *l != END_OF_INSN
2905 || (*l != PREFIX_SEPARATOR
2908 as_bad (_("invalid character %s in mnemonic"),
2909 output_invalid (*l));
2912 if (token_start == l)
2914 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2915 as_bad (_("expecting prefix; got nothing"));
2917 as_bad (_("expecting mnemonic; got nothing"));
2921 /* Look up instruction (or prefix) via hash table. */
2922 current_templates = hash_find (op_hash, mnemonic);
2924 if (*l != END_OF_INSN
2925 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2926 && current_templates
2927 && current_templates->start->opcode_modifier.isprefix)
2929 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2931 as_bad ((flag_code != CODE_64BIT
2932 ? _("`%s' is only supported in 64-bit mode")
2933 : _("`%s' is not supported in 64-bit mode")),
2934 current_templates->start->name);
2937 /* If we are in 16-bit mode, do not allow addr16 or data16.
2938 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2939 if ((current_templates->start->opcode_modifier.size16
2940 || current_templates->start->opcode_modifier.size32)
2941 && flag_code != CODE_64BIT
2942 && (current_templates->start->opcode_modifier.size32
2943 ^ (flag_code == CODE_16BIT)))
2945 as_bad (_("redundant %s prefix"),
2946 current_templates->start->name);
2949 /* Add prefix, checking for repeated prefixes. */
2950 switch (add_prefix (current_templates->start->base_opcode))
2955 expecting_string_instruction = current_templates->start->name;
2958 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2965 if (!current_templates)
2967 /* See if we can get a match by trimming off a suffix. */
2970 case WORD_MNEM_SUFFIX:
2971 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2972 i.suffix = SHORT_MNEM_SUFFIX;
2974 case BYTE_MNEM_SUFFIX:
2975 case QWORD_MNEM_SUFFIX:
2976 i.suffix = mnem_p[-1];
2978 current_templates = hash_find (op_hash, mnemonic);
2980 case SHORT_MNEM_SUFFIX:
2981 case LONG_MNEM_SUFFIX:
2984 i.suffix = mnem_p[-1];
2986 current_templates = hash_find (op_hash, mnemonic);
2994 if (intel_float_operand (mnemonic) == 1)
2995 i.suffix = SHORT_MNEM_SUFFIX;
2997 i.suffix = LONG_MNEM_SUFFIX;
2999 current_templates = hash_find (op_hash, mnemonic);
3003 if (!current_templates)
3005 as_bad (_("no such instruction: `%s'"), token_start);
3010 if (current_templates->start->opcode_modifier.jump
3011 || current_templates->start->opcode_modifier.jumpbyte)
3013 /* Check for a branch hint. We allow ",pt" and ",pn" for
3014 predict taken and predict not taken respectively.
3015 I'm not sure that branch hints actually do anything on loop
3016 and jcxz insns (JumpByte) for current Pentium4 chips. They
3017 may work in the future and it doesn't hurt to accept them
3019 if (l[0] == ',' && l[1] == 'p')
3023 if (!add_prefix (DS_PREFIX_OPCODE))
3027 else if (l[2] == 'n')
3029 if (!add_prefix (CS_PREFIX_OPCODE))
3035 /* Any other comma loses. */
3038 as_bad (_("invalid character %s in mnemonic"),
3039 output_invalid (*l));
3043 /* Check if instruction is supported on specified architecture. */
3045 for (t = current_templates->start; t < current_templates->end; ++t)
3047 supported |= cpu_flags_match (t);
3048 if (supported == CPU_FLAGS_PERFECT_MATCH)
3052 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3054 as_bad (flag_code == CODE_64BIT
3055 ? _("`%s' is not supported in 64-bit mode")
3056 : _("`%s' is only supported in 64-bit mode"),
3057 current_templates->start->name);
3060 if (supported != CPU_FLAGS_PERFECT_MATCH)
3062 as_bad (_("`%s' is not supported on `%s%s'"),
3063 current_templates->start->name, cpu_arch_name,
3064 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3069 if (!cpu_arch_flags.bitfield.cpui386
3070 && (flag_code != CODE_16BIT))
3072 as_warn (_("use .code16 to ensure correct addressing mode"));
3075 /* Check for rep/repne without a string instruction. */
3076 if (expecting_string_instruction)
3078 static templates override;
3080 for (t = current_templates->start; t < current_templates->end; ++t)
3081 if (t->opcode_modifier.isstring)
3083 if (t >= current_templates->end)
3085 as_bad (_("expecting string instruction after `%s'"),
3086 expecting_string_instruction);
3089 for (override.start = t; t < current_templates->end; ++t)
3090 if (!t->opcode_modifier.isstring)
3093 current_templates = &override;
3100 parse_operands (char *l, const char *mnemonic)
3104 /* 1 if operand is pending after ','. */
3105 unsigned int expecting_operand = 0;
3107 /* Non-zero if operand parens not balanced. */
3108 unsigned int paren_not_balanced;
3110 while (*l != END_OF_INSN)
3112 /* Skip optional white space before operand. */
3113 if (is_space_char (*l))
3115 if (!is_operand_char (*l) && *l != END_OF_INSN)
3117 as_bad (_("invalid character %s before operand %d"),
3118 output_invalid (*l),
3122 token_start = l; /* after white space */
3123 paren_not_balanced = 0;
3124 while (paren_not_balanced || *l != ',')
3126 if (*l == END_OF_INSN)
3128 if (paren_not_balanced)
3131 as_bad (_("unbalanced parenthesis in operand %d."),
3134 as_bad (_("unbalanced brackets in operand %d."),
3139 break; /* we are done */
3141 else if (!is_operand_char (*l) && !is_space_char (*l))
3143 as_bad (_("invalid character %s in operand %d"),
3144 output_invalid (*l),
3151 ++paren_not_balanced;
3153 --paren_not_balanced;
3158 ++paren_not_balanced;
3160 --paren_not_balanced;
3164 if (l != token_start)
3165 { /* Yes, we've read in another operand. */
3166 unsigned int operand_ok;
3167 this_operand = i.operands++;
3168 i.types[this_operand].bitfield.unspecified = 1;
3169 if (i.operands > MAX_OPERANDS)
3171 as_bad (_("spurious operands; (%d operands/instruction max)"),
3175 /* Now parse operand adding info to 'i' as we go along. */
3176 END_STRING_AND_SAVE (l);
3180 i386_intel_operand (token_start,
3181 intel_float_operand (mnemonic));
3183 operand_ok = i386_att_operand (token_start);
3185 RESTORE_END_STRING (l);
3191 if (expecting_operand)
3193 expecting_operand_after_comma:
3194 as_bad (_("expecting operand after ','; got nothing"));
3199 as_bad (_("expecting operand before ','; got nothing"));
3204 /* Now *l must be either ',' or END_OF_INSN. */
3207 if (*++l == END_OF_INSN)
3209 /* Just skip it, if it's \n complain. */
3210 goto expecting_operand_after_comma;
3212 expecting_operand = 1;
3219 swap_2_operands (int xchg1, int xchg2)
3221 union i386_op temp_op;
3222 i386_operand_type temp_type;
3223 enum bfd_reloc_code_real temp_reloc;
3225 temp_type = i.types[xchg2];
3226 i.types[xchg2] = i.types[xchg1];
3227 i.types[xchg1] = temp_type;
3228 temp_op = i.op[xchg2];
3229 i.op[xchg2] = i.op[xchg1];
3230 i.op[xchg1] = temp_op;
3231 temp_reloc = i.reloc[xchg2];
3232 i.reloc[xchg2] = i.reloc[xchg1];
3233 i.reloc[xchg1] = temp_reloc;
3237 swap_operands (void)
3243 swap_2_operands (1, i.operands - 2);
3246 swap_2_operands (0, i.operands - 1);
3252 if (i.mem_operands == 2)
3254 const seg_entry *temp_seg;
3255 temp_seg = i.seg[0];
3256 i.seg[0] = i.seg[1];
3257 i.seg[1] = temp_seg;
3261 /* Try to ensure constant immediates are represented in the smallest
3266 char guess_suffix = 0;
3270 guess_suffix = i.suffix;
3271 else if (i.reg_operands)
3273 /* Figure out a suffix from the last register operand specified.
3274 We can't do this properly yet, ie. excluding InOutPortReg,
3275 but the following works for instructions with immediates.
3276 In any case, we can't set i.suffix yet. */
3277 for (op = i.operands; --op >= 0;)
3278 if (i.types[op].bitfield.reg8)
3280 guess_suffix = BYTE_MNEM_SUFFIX;
3283 else if (i.types[op].bitfield.reg16)
3285 guess_suffix = WORD_MNEM_SUFFIX;
3288 else if (i.types[op].bitfield.reg32)
3290 guess_suffix = LONG_MNEM_SUFFIX;
3293 else if (i.types[op].bitfield.reg64)
3295 guess_suffix = QWORD_MNEM_SUFFIX;
3299 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3300 guess_suffix = WORD_MNEM_SUFFIX;
3302 for (op = i.operands; --op >= 0;)
3303 if (operand_type_check (i.types[op], imm))
3305 switch (i.op[op].imms->X_op)
3308 /* If a suffix is given, this operand may be shortened. */
3309 switch (guess_suffix)
3311 case LONG_MNEM_SUFFIX:
3312 i.types[op].bitfield.imm32 = 1;
3313 i.types[op].bitfield.imm64 = 1;
3315 case WORD_MNEM_SUFFIX:
3316 i.types[op].bitfield.imm16 = 1;
3317 i.types[op].bitfield.imm32 = 1;
3318 i.types[op].bitfield.imm32s = 1;
3319 i.types[op].bitfield.imm64 = 1;
3321 case BYTE_MNEM_SUFFIX:
3322 i.types[op].bitfield.imm8 = 1;
3323 i.types[op].bitfield.imm8s = 1;
3324 i.types[op].bitfield.imm16 = 1;
3325 i.types[op].bitfield.imm32 = 1;
3326 i.types[op].bitfield.imm32s = 1;
3327 i.types[op].bitfield.imm64 = 1;
3331 /* If this operand is at most 16 bits, convert it
3332 to a signed 16 bit number before trying to see
3333 whether it will fit in an even smaller size.
3334 This allows a 16-bit operand such as $0xffe0 to
3335 be recognised as within Imm8S range. */
3336 if ((i.types[op].bitfield.imm16)
3337 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3339 i.op[op].imms->X_add_number =
3340 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3342 if ((i.types[op].bitfield.imm32)
3343 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3346 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3347 ^ ((offsetT) 1 << 31))
3348 - ((offsetT) 1 << 31));
3351 = operand_type_or (i.types[op],
3352 smallest_imm_type (i.op[op].imms->X_add_number));
3354 /* We must avoid matching of Imm32 templates when 64bit
3355 only immediate is available. */
3356 if (guess_suffix == QWORD_MNEM_SUFFIX)
3357 i.types[op].bitfield.imm32 = 0;
3364 /* Symbols and expressions. */
3366 /* Convert symbolic operand to proper sizes for matching, but don't
3367 prevent matching a set of insns that only supports sizes other
3368 than those matching the insn suffix. */
3370 i386_operand_type mask, allowed;
3373 operand_type_set (&mask, 0);
3374 operand_type_set (&allowed, 0);
3376 for (t = current_templates->start;
3377 t < current_templates->end;
3379 allowed = operand_type_or (allowed,
3380 t->operand_types[op]);
3381 switch (guess_suffix)
3383 case QWORD_MNEM_SUFFIX:
3384 mask.bitfield.imm64 = 1;
3385 mask.bitfield.imm32s = 1;
3387 case LONG_MNEM_SUFFIX:
3388 mask.bitfield.imm32 = 1;
3390 case WORD_MNEM_SUFFIX:
3391 mask.bitfield.imm16 = 1;
3393 case BYTE_MNEM_SUFFIX:
3394 mask.bitfield.imm8 = 1;
3399 allowed = operand_type_and (mask, allowed);
3400 if (!operand_type_all_zero (&allowed))
3401 i.types[op] = operand_type_and (i.types[op], mask);
3408 /* Try to use the smallest displacement type too. */
3410 optimize_disp (void)
3414 for (op = i.operands; --op >= 0;)
3415 if (operand_type_check (i.types[op], disp))
3417 if (i.op[op].disps->X_op == O_constant)
3419 offsetT disp = i.op[op].disps->X_add_number;
3421 if (i.types[op].bitfield.disp16
3422 && (disp & ~(offsetT) 0xffff) == 0)
3424 /* If this operand is at most 16 bits, convert
3425 to a signed 16 bit number and don't use 64bit
3427 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3428 i.types[op].bitfield.disp64 = 0;
3430 if (i.types[op].bitfield.disp32
3431 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3433 /* If this operand is at most 32 bits, convert
3434 to a signed 32 bit number and don't use 64bit
3436 disp &= (((offsetT) 2 << 31) - 1);
3437 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3438 i.types[op].bitfield.disp64 = 0;
3440 if (!disp && i.types[op].bitfield.baseindex)
3442 i.types[op].bitfield.disp8 = 0;
3443 i.types[op].bitfield.disp16 = 0;
3444 i.types[op].bitfield.disp32 = 0;
3445 i.types[op].bitfield.disp32s = 0;
3446 i.types[op].bitfield.disp64 = 0;
3450 else if (flag_code == CODE_64BIT)
3452 if (fits_in_signed_long (disp))
3454 i.types[op].bitfield.disp64 = 0;
3455 i.types[op].bitfield.disp32s = 1;
3457 if (fits_in_unsigned_long (disp))
3458 i.types[op].bitfield.disp32 = 1;
3460 if ((i.types[op].bitfield.disp32
3461 || i.types[op].bitfield.disp32s
3462 || i.types[op].bitfield.disp16)
3463 && fits_in_signed_byte (disp))
3464 i.types[op].bitfield.disp8 = 1;
3466 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3467 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3469 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3470 i.op[op].disps, 0, i.reloc[op]);
3471 i.types[op].bitfield.disp8 = 0;
3472 i.types[op].bitfield.disp16 = 0;
3473 i.types[op].bitfield.disp32 = 0;
3474 i.types[op].bitfield.disp32s = 0;
3475 i.types[op].bitfield.disp64 = 0;
3478 /* We only support 64bit displacement on constants. */
3479 i.types[op].bitfield.disp64 = 0;
3483 /* Check if operands are valid for the instrucrtion. Update VEX
3487 VEX_check_operands (const template *t)
3489 if (!t->opcode_modifier.vex)
3492 /* Only check VEX_Imm4, which must be the first operand. */
3493 if (t->operand_types[0].bitfield.vex_imm4)
3495 if (i.op[0].imms->X_op != O_constant
3496 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3499 /* Turn off Imm8 so that update_imm won't complain. */
3500 i.types[0] = vex_imm4;
3507 match_template (void)
3509 /* Points to template once we've found it. */
3511 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3512 i386_operand_type overlap4;
3513 unsigned int found_reverse_match;
3514 i386_opcode_modifier suffix_check;
3515 i386_operand_type operand_types [MAX_OPERANDS];
3516 int addr_prefix_disp;
3518 unsigned int found_cpu_match;
3519 unsigned int check_register;
3521 #if MAX_OPERANDS != 5
3522 # error "MAX_OPERANDS must be 5."
3525 found_reverse_match = 0;
3526 addr_prefix_disp = -1;
3528 memset (&suffix_check, 0, sizeof (suffix_check));
3529 if (i.suffix == BYTE_MNEM_SUFFIX)
3530 suffix_check.no_bsuf = 1;
3531 else if (i.suffix == WORD_MNEM_SUFFIX)
3532 suffix_check.no_wsuf = 1;
3533 else if (i.suffix == SHORT_MNEM_SUFFIX)
3534 suffix_check.no_ssuf = 1;
3535 else if (i.suffix == LONG_MNEM_SUFFIX)
3536 suffix_check.no_lsuf = 1;
3537 else if (i.suffix == QWORD_MNEM_SUFFIX)
3538 suffix_check.no_qsuf = 1;
3539 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3540 suffix_check.no_ldsuf = 1;
3542 for (t = current_templates->start; t < current_templates->end; t++)
3544 addr_prefix_disp = -1;
3546 /* Must have right number of operands. */
3547 if (i.operands != t->operands)
3550 /* Check processor support. */
3551 found_cpu_match = (cpu_flags_match (t)
3552 == CPU_FLAGS_PERFECT_MATCH);
3553 if (!found_cpu_match)
3556 /* Check old gcc support. */
3557 if (!old_gcc && t->opcode_modifier.oldgcc)
3560 /* Check AT&T mnemonic. */
3561 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3564 /* Check AT&T syntax Intel syntax. */
3565 if ((intel_syntax && t->opcode_modifier.attsyntax)
3566 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3569 /* Check the suffix, except for some instructions in intel mode. */
3570 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3571 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3572 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3573 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3574 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3575 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3576 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3579 if (!operand_size_match (t))
3582 for (j = 0; j < MAX_OPERANDS; j++)
3583 operand_types[j] = t->operand_types[j];
3585 /* In general, don't allow 64-bit operands in 32-bit mode. */
3586 if (i.suffix == QWORD_MNEM_SUFFIX
3587 && flag_code != CODE_64BIT
3589 ? (!t->opcode_modifier.ignoresize
3590 && !intel_float_operand (t->name))
3591 : intel_float_operand (t->name) != 2)
3592 && ((!operand_types[0].bitfield.regmmx
3593 && !operand_types[0].bitfield.regxmm
3594 && !operand_types[0].bitfield.regymm)
3595 || (!operand_types[t->operands > 1].bitfield.regmmx
3596 && !!operand_types[t->operands > 1].bitfield.regxmm
3597 && !!operand_types[t->operands > 1].bitfield.regymm))
3598 && (t->base_opcode != 0x0fc7
3599 || t->extension_opcode != 1 /* cmpxchg8b */))
3602 /* In general, don't allow 32-bit operands on pre-386. */
3603 else if (i.suffix == LONG_MNEM_SUFFIX
3604 && !cpu_arch_flags.bitfield.cpui386
3606 ? (!t->opcode_modifier.ignoresize
3607 && !intel_float_operand (t->name))
3608 : intel_float_operand (t->name) != 2)
3609 && ((!operand_types[0].bitfield.regmmx
3610 && !operand_types[0].bitfield.regxmm)
3611 || (!operand_types[t->operands > 1].bitfield.regmmx
3612 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3615 /* Do not verify operands when there are none. */
3619 /* We've found a match; break out of loop. */
3623 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3624 into Disp32/Disp16/Disp32 operand. */
3625 if (i.prefix[ADDR_PREFIX] != 0)
3627 /* There should be only one Disp operand. */
3631 for (j = 0; j < MAX_OPERANDS; j++)
3633 if (operand_types[j].bitfield.disp16)
3635 addr_prefix_disp = j;
3636 operand_types[j].bitfield.disp32 = 1;
3637 operand_types[j].bitfield.disp16 = 0;
3643 for (j = 0; j < MAX_OPERANDS; j++)
3645 if (operand_types[j].bitfield.disp32)
3647 addr_prefix_disp = j;
3648 operand_types[j].bitfield.disp32 = 0;
3649 operand_types[j].bitfield.disp16 = 1;
3655 for (j = 0; j < MAX_OPERANDS; j++)
3657 if (operand_types[j].bitfield.disp64)
3659 addr_prefix_disp = j;
3660 operand_types[j].bitfield.disp64 = 0;
3661 operand_types[j].bitfield.disp32 = 1;
3669 /* We check register size only if size of operands can be
3670 encoded the canonical way. */
3671 check_register = t->opcode_modifier.w;
3672 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3673 switch (t->operands)
3676 if (!operand_type_match (overlap0, i.types[0]))
3680 /* xchg %eax, %eax is a special case. It is an aliase for nop
3681 only in 32bit mode and we can use opcode 0x90. In 64bit
3682 mode, we can't use 0x90 for xchg %eax, %eax since it should
3683 zero-extend %eax to %rax. */
3684 if (flag_code == CODE_64BIT
3685 && t->base_opcode == 0x90
3686 && operand_type_equal (&i.types [0], &acc32)
3687 && operand_type_equal (&i.types [1], &acc32))
3692 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3693 if (!operand_type_match (overlap0, i.types[0])
3694 || !operand_type_match (overlap1, i.types[1])
3696 && !operand_type_register_match (overlap0, i.types[0],
3698 overlap1, i.types[1],
3701 /* Check if other direction is valid ... */
3702 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3705 /* Try reversing direction of operands. */
3706 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3707 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3708 if (!operand_type_match (overlap0, i.types[0])
3709 || !operand_type_match (overlap1, i.types[1])
3711 && !operand_type_register_match (overlap0,
3718 /* Does not match either direction. */
3721 /* found_reverse_match holds which of D or FloatDR
3723 if (t->opcode_modifier.d)
3724 found_reverse_match = Opcode_D;
3725 else if (t->opcode_modifier.floatd)
3726 found_reverse_match = Opcode_FloatD;
3728 found_reverse_match = 0;
3729 if (t->opcode_modifier.floatr)
3730 found_reverse_match |= Opcode_FloatR;
3734 /* Found a forward 2 operand match here. */
3735 switch (t->operands)
3738 overlap4 = operand_type_and (i.types[4],
3741 overlap3 = operand_type_and (i.types[3],
3744 overlap2 = operand_type_and (i.types[2],
3749 switch (t->operands)
3752 if (!operand_type_match (overlap4, i.types[4])
3753 || !operand_type_register_match (overlap3,
3761 if (!operand_type_match (overlap3, i.types[3])
3763 && !operand_type_register_match (overlap2,
3771 /* Here we make use of the fact that there are no
3772 reverse match 3 operand instructions, and all 3
3773 operand instructions only need to be checked for
3774 register consistency between operands 2 and 3. */
3775 if (!operand_type_match (overlap2, i.types[2])
3777 && !operand_type_register_match (overlap1,
3787 /* Found either forward/reverse 2, 3 or 4 operand match here:
3788 slip through to break. */
3790 if (!found_cpu_match)
3792 found_reverse_match = 0;
3796 /* Check if VEX operands are valid. */
3797 if (VEX_check_operands (t))
3800 /* We've found a match; break out of loop. */
3804 if (t == current_templates->end)
3806 /* We found no match. */
3808 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3809 current_templates->start->name);
3811 as_bad (_("suffix or operands invalid for `%s'"),
3812 current_templates->start->name);
3816 if (!quiet_warnings)
3819 && (i.types[0].bitfield.jumpabsolute
3820 != operand_types[0].bitfield.jumpabsolute))
3822 as_warn (_("indirect %s without `*'"), t->name);
3825 if (t->opcode_modifier.isprefix
3826 && t->opcode_modifier.ignoresize)
3828 /* Warn them that a data or address size prefix doesn't
3829 affect assembly of the next line of code. */
3830 as_warn (_("stand-alone `%s' prefix"), t->name);
3834 /* Copy the template we found. */
3837 if (addr_prefix_disp != -1)
3838 i.tm.operand_types[addr_prefix_disp]
3839 = operand_types[addr_prefix_disp];
3841 if (found_reverse_match)
3843 /* If we found a reverse match we must alter the opcode
3844 direction bit. found_reverse_match holds bits to change
3845 (different for int & float insns). */
3847 i.tm.base_opcode ^= found_reverse_match;
3849 i.tm.operand_types[0] = operand_types[1];
3850 i.tm.operand_types[1] = operand_types[0];
3859 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3860 if (i.tm.operand_types[mem_op].bitfield.esseg)
3862 if (i.seg[0] != NULL && i.seg[0] != &es)
3864 as_bad (_("`%s' operand %d must use `%ses' segment"),
3870 /* There's only ever one segment override allowed per instruction.
3871 This instruction possibly has a legal segment override on the
3872 second operand, so copy the segment to where non-string
3873 instructions store it, allowing common code. */
3874 i.seg[0] = i.seg[1];
3876 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3878 if (i.seg[1] != NULL && i.seg[1] != &es)
3880 as_bad (_("`%s' operand %d must use `%ses' segment"),
3891 process_suffix (void)
3893 /* If matched instruction specifies an explicit instruction mnemonic
3895 if (i.tm.opcode_modifier.size16)
3896 i.suffix = WORD_MNEM_SUFFIX;
3897 else if (i.tm.opcode_modifier.size32)
3898 i.suffix = LONG_MNEM_SUFFIX;
3899 else if (i.tm.opcode_modifier.size64)
3900 i.suffix = QWORD_MNEM_SUFFIX;
3901 else if (i.reg_operands)
3903 /* If there's no instruction mnemonic suffix we try to invent one
3904 based on register operands. */
3907 /* We take i.suffix from the last register operand specified,
3908 Destination register type is more significant than source
3909 register type. crc32 in SSE4.2 prefers source register
3911 if (i.tm.base_opcode == 0xf20f38f1)
3913 if (i.types[0].bitfield.reg16)
3914 i.suffix = WORD_MNEM_SUFFIX;
3915 else if (i.types[0].bitfield.reg32)
3916 i.suffix = LONG_MNEM_SUFFIX;
3917 else if (i.types[0].bitfield.reg64)
3918 i.suffix = QWORD_MNEM_SUFFIX;
3920 else if (i.tm.base_opcode == 0xf20f38f0)
3922 if (i.types[0].bitfield.reg8)
3923 i.suffix = BYTE_MNEM_SUFFIX;
3930 if (i.tm.base_opcode == 0xf20f38f1
3931 || i.tm.base_opcode == 0xf20f38f0)
3933 /* We have to know the operand size for crc32. */
3934 as_bad (_("ambiguous memory operand size for `%s`"),
3939 for (op = i.operands; --op >= 0;)
3940 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3942 if (i.types[op].bitfield.reg8)
3944 i.suffix = BYTE_MNEM_SUFFIX;
3947 else if (i.types[op].bitfield.reg16)
3949 i.suffix = WORD_MNEM_SUFFIX;
3952 else if (i.types[op].bitfield.reg32)
3954 i.suffix = LONG_MNEM_SUFFIX;
3957 else if (i.types[op].bitfield.reg64)
3959 i.suffix = QWORD_MNEM_SUFFIX;
3965 else if (i.suffix == BYTE_MNEM_SUFFIX)
3967 if (!check_byte_reg ())
3970 else if (i.suffix == LONG_MNEM_SUFFIX)
3972 if (!check_long_reg ())
3975 else if (i.suffix == QWORD_MNEM_SUFFIX)
3978 && i.tm.opcode_modifier.ignoresize
3979 && i.tm.opcode_modifier.no_qsuf)
3981 else if (!check_qword_reg ())
3984 else if (i.suffix == WORD_MNEM_SUFFIX)
3986 if (!check_word_reg ())
3989 else if (i.suffix == XMMWORD_MNEM_SUFFIX
3990 || i.suffix == YMMWORD_MNEM_SUFFIX)
3992 /* Skip if the instruction has x/y suffix. match_template
3993 should check if it is a valid suffix. */
3995 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
3996 /* Do nothing if the instruction is going to ignore the prefix. */
4001 else if (i.tm.opcode_modifier.defaultsize
4003 /* exclude fldenv/frstor/fsave/fstenv */
4004 && i.tm.opcode_modifier.no_ssuf)
4006 i.suffix = stackop_size;
4008 else if (intel_syntax
4010 && (i.tm.operand_types[0].bitfield.jumpabsolute
4011 || i.tm.opcode_modifier.jumpbyte
4012 || i.tm.opcode_modifier.jumpintersegment
4013 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4014 && i.tm.extension_opcode <= 3)))
4019 if (!i.tm.opcode_modifier.no_qsuf)
4021 i.suffix = QWORD_MNEM_SUFFIX;
4025 if (!i.tm.opcode_modifier.no_lsuf)
4026 i.suffix = LONG_MNEM_SUFFIX;
4029 if (!i.tm.opcode_modifier.no_wsuf)
4030 i.suffix = WORD_MNEM_SUFFIX;
4039 if (i.tm.opcode_modifier.w)
4041 as_bad (_("no instruction mnemonic suffix given and "
4042 "no register operands; can't size instruction"));
4048 unsigned int suffixes;
4050 suffixes = !i.tm.opcode_modifier.no_bsuf;
4051 if (!i.tm.opcode_modifier.no_wsuf)
4053 if (!i.tm.opcode_modifier.no_lsuf)
4055 if (!i.tm.opcode_modifier.no_ldsuf)
4057 if (!i.tm.opcode_modifier.no_ssuf)
4059 if (!i.tm.opcode_modifier.no_qsuf)
4062 /* There are more than suffix matches. */
4063 if (i.tm.opcode_modifier.w
4064 || ((suffixes & (suffixes - 1))
4065 && !i.tm.opcode_modifier.defaultsize
4066 && !i.tm.opcode_modifier.ignoresize))
4068 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4074 /* Change the opcode based on the operand size given by i.suffix;
4075 We don't need to change things for byte insns. */
4078 && i.suffix != BYTE_MNEM_SUFFIX
4079 && i.suffix != XMMWORD_MNEM_SUFFIX
4080 && i.suffix != YMMWORD_MNEM_SUFFIX)
4082 /* It's not a byte, select word/dword operation. */
4083 if (i.tm.opcode_modifier.w)
4085 if (i.tm.opcode_modifier.shortform)
4086 i.tm.base_opcode |= 8;
4088 i.tm.base_opcode |= 1;
4091 /* Now select between word & dword operations via the operand
4092 size prefix, except for instructions that will ignore this
4094 if (i.tm.opcode_modifier.addrprefixop0)
4096 /* The address size override prefix changes the size of the
4098 if ((flag_code == CODE_32BIT
4099 && i.op->regs[0].reg_type.bitfield.reg16)
4100 || (flag_code != CODE_32BIT
4101 && i.op->regs[0].reg_type.bitfield.reg32))
4102 if (!add_prefix (ADDR_PREFIX_OPCODE))
4105 else if (i.suffix != QWORD_MNEM_SUFFIX
4106 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
4107 && !i.tm.opcode_modifier.ignoresize
4108 && !i.tm.opcode_modifier.floatmf
4109 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4110 || (flag_code == CODE_64BIT
4111 && i.tm.opcode_modifier.jumpbyte)))
4113 unsigned int prefix = DATA_PREFIX_OPCODE;
4115 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
4116 prefix = ADDR_PREFIX_OPCODE;
4118 if (!add_prefix (prefix))
4122 /* Set mode64 for an operand. */
4123 if (i.suffix == QWORD_MNEM_SUFFIX
4124 && flag_code == CODE_64BIT
4125 && !i.tm.opcode_modifier.norex64)
4127 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4128 need rex64. cmpxchg8b is also a special case. */
4129 if (! (i.operands == 2
4130 && i.tm.base_opcode == 0x90
4131 && i.tm.extension_opcode == None
4132 && operand_type_equal (&i.types [0], &acc64)
4133 && operand_type_equal (&i.types [1], &acc64))
4134 && ! (i.operands == 1
4135 && i.tm.base_opcode == 0xfc7
4136 && i.tm.extension_opcode == 1
4137 && !operand_type_check (i.types [0], reg)
4138 && operand_type_check (i.types [0], anymem)))
4142 /* Size floating point instruction. */
4143 if (i.suffix == LONG_MNEM_SUFFIX)
4144 if (i.tm.opcode_modifier.floatmf)
4145 i.tm.base_opcode ^= 4;
4152 check_byte_reg (void)
4156 for (op = i.operands; --op >= 0;)
4158 /* If this is an eight bit register, it's OK. If it's the 16 or
4159 32 bit version of an eight bit register, we will just use the
4160 low portion, and that's OK too. */
4161 if (i.types[op].bitfield.reg8)
4164 /* Don't generate this warning if not needed. */
4165 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
4168 /* crc32 doesn't generate this warning. */
4169 if (i.tm.base_opcode == 0xf20f38f0)
4172 if ((i.types[op].bitfield.reg16
4173 || i.types[op].bitfield.reg32
4174 || i.types[op].bitfield.reg64)
4175 && i.op[op].regs->reg_num < 4)
4177 /* Prohibit these changes in the 64bit mode, since the
4178 lowering is more complicated. */
4179 if (flag_code == CODE_64BIT
4180 && !i.tm.operand_types[op].bitfield.inoutportreg)
4182 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4183 register_prefix, i.op[op].regs->reg_name,
4187 #if REGISTER_WARNINGS
4189 && !i.tm.operand_types[op].bitfield.inoutportreg)
4190 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4192 (i.op[op].regs + (i.types[op].bitfield.reg16
4193 ? REGNAM_AL - REGNAM_AX
4194 : REGNAM_AL - REGNAM_EAX))->reg_name,
4196 i.op[op].regs->reg_name,
4201 /* Any other register is bad. */
4202 if (i.types[op].bitfield.reg16
4203 || i.types[op].bitfield.reg32
4204 || i.types[op].bitfield.reg64
4205 || i.types[op].bitfield.regmmx
4206 || i.types[op].bitfield.regxmm
4207 || i.types[op].bitfield.regymm
4208 || i.types[op].bitfield.sreg2
4209 || i.types[op].bitfield.sreg3
4210 || i.types[op].bitfield.control
4211 || i.types[op].bitfield.debug
4212 || i.types[op].bitfield.test
4213 || i.types[op].bitfield.floatreg
4214 || i.types[op].bitfield.floatacc)
4216 as_bad (_("`%s%s' not allowed with `%s%c'"),
4218 i.op[op].regs->reg_name,
4228 check_long_reg (void)
4232 for (op = i.operands; --op >= 0;)
4233 /* Reject eight bit registers, except where the template requires
4234 them. (eg. movzb) */
4235 if (i.types[op].bitfield.reg8
4236 && (i.tm.operand_types[op].bitfield.reg16
4237 || i.tm.operand_types[op].bitfield.reg32
4238 || i.tm.operand_types[op].bitfield.acc))
4240 as_bad (_("`%s%s' not allowed with `%s%c'"),
4242 i.op[op].regs->reg_name,
4247 /* Warn if the e prefix on a general reg is missing. */
4248 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4249 && i.types[op].bitfield.reg16
4250 && (i.tm.operand_types[op].bitfield.reg32
4251 || i.tm.operand_types[op].bitfield.acc))
4253 /* Prohibit these changes in the 64bit mode, since the
4254 lowering is more complicated. */
4255 if (flag_code == CODE_64BIT)
4257 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4258 register_prefix, i.op[op].regs->reg_name,
4262 #if REGISTER_WARNINGS
4264 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4266 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
4268 i.op[op].regs->reg_name,
4272 /* Warn if the r prefix on a general reg is missing. */
4273 else if (i.types[op].bitfield.reg64
4274 && (i.tm.operand_types[op].bitfield.reg32
4275 || i.tm.operand_types[op].bitfield.acc))
4278 && i.tm.opcode_modifier.toqword
4279 && !i.types[0].bitfield.regxmm)
4281 /* Convert to QWORD. We want REX byte. */
4282 i.suffix = QWORD_MNEM_SUFFIX;
4286 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4287 register_prefix, i.op[op].regs->reg_name,
4296 check_qword_reg (void)
4300 for (op = i.operands; --op >= 0; )
4301 /* Reject eight bit registers, except where the template requires
4302 them. (eg. movzb) */
4303 if (i.types[op].bitfield.reg8
4304 && (i.tm.operand_types[op].bitfield.reg16
4305 || i.tm.operand_types[op].bitfield.reg32
4306 || i.tm.operand_types[op].bitfield.acc))
4308 as_bad (_("`%s%s' not allowed with `%s%c'"),
4310 i.op[op].regs->reg_name,
4315 /* Warn if the e prefix on a general reg is missing. */
4316 else if ((i.types[op].bitfield.reg16
4317 || i.types[op].bitfield.reg32)
4318 && (i.tm.operand_types[op].bitfield.reg32
4319 || i.tm.operand_types[op].bitfield.acc))
4321 /* Prohibit these changes in the 64bit mode, since the
4322 lowering is more complicated. */
4324 && i.tm.opcode_modifier.todword
4325 && !i.types[0].bitfield.regxmm)
4327 /* Convert to DWORD. We don't want REX byte. */
4328 i.suffix = LONG_MNEM_SUFFIX;
4332 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4333 register_prefix, i.op[op].regs->reg_name,
4342 check_word_reg (void)
4345 for (op = i.operands; --op >= 0;)
4346 /* Reject eight bit registers, except where the template requires
4347 them. (eg. movzb) */
4348 if (i.types[op].bitfield.reg8
4349 && (i.tm.operand_types[op].bitfield.reg16
4350 || i.tm.operand_types[op].bitfield.reg32
4351 || i.tm.operand_types[op].bitfield.acc))
4353 as_bad (_("`%s%s' not allowed with `%s%c'"),
4355 i.op[op].regs->reg_name,
4360 /* Warn if the e prefix on a general reg is present. */
4361 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4362 && i.types[op].bitfield.reg32
4363 && (i.tm.operand_types[op].bitfield.reg16
4364 || i.tm.operand_types[op].bitfield.acc))
4366 /* Prohibit these changes in the 64bit mode, since the
4367 lowering is more complicated. */
4368 if (flag_code == CODE_64BIT)
4370 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4371 register_prefix, i.op[op].regs->reg_name,
4376 #if REGISTER_WARNINGS
4377 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4379 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4381 i.op[op].regs->reg_name,
4389 update_imm (unsigned int j)
4391 i386_operand_type overlap;
4393 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4394 if ((overlap.bitfield.imm8
4395 || overlap.bitfield.imm8s
4396 || overlap.bitfield.imm16
4397 || overlap.bitfield.imm32
4398 || overlap.bitfield.imm32s
4399 || overlap.bitfield.imm64)
4400 && !operand_type_equal (&overlap, &imm8)
4401 && !operand_type_equal (&overlap, &imm8s)
4402 && !operand_type_equal (&overlap, &imm16)
4403 && !operand_type_equal (&overlap, &imm32)
4404 && !operand_type_equal (&overlap, &imm32s)
4405 && !operand_type_equal (&overlap, &imm64))
4409 i386_operand_type temp;
4411 operand_type_set (&temp, 0);
4412 if (i.suffix == BYTE_MNEM_SUFFIX)
4414 temp.bitfield.imm8 = overlap.bitfield.imm8;
4415 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4417 else if (i.suffix == WORD_MNEM_SUFFIX)
4418 temp.bitfield.imm16 = overlap.bitfield.imm16;
4419 else if (i.suffix == QWORD_MNEM_SUFFIX)
4421 temp.bitfield.imm64 = overlap.bitfield.imm64;
4422 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4425 temp.bitfield.imm32 = overlap.bitfield.imm32;
4428 else if (operand_type_equal (&overlap, &imm16_32_32s)
4429 || operand_type_equal (&overlap, &imm16_32)
4430 || operand_type_equal (&overlap, &imm16_32s))
4432 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4437 if (!operand_type_equal (&overlap, &imm8)
4438 && !operand_type_equal (&overlap, &imm8s)
4439 && !operand_type_equal (&overlap, &imm16)
4440 && !operand_type_equal (&overlap, &imm32)
4441 && !operand_type_equal (&overlap, &imm32s)
4442 && !operand_type_equal (&overlap, &imm64))
4444 as_bad (_("no instruction mnemonic suffix given; "
4445 "can't determine immediate size"));
4449 i.types[j] = overlap;
4459 for (j = 0; j < 2; j++)
4460 if (update_imm (j) == 0)
4463 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4464 assert (operand_type_check (i.types[2], imm) == 0);
4472 i.drex.modrm_reg = 0;
4473 i.drex.modrm_regmem = 0;
4475 /* SSE5 4 operand instructions must have the destination the same as
4476 one of the inputs. Figure out the destination register and cache
4477 it away in the drex field, and remember which fields to use for
4479 if (i.tm.opcode_modifier.drex
4480 && i.tm.opcode_modifier.drexv
4483 i.tm.extension_opcode = None;
4485 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4486 if (i.types[0].bitfield.regxmm != 0
4487 && i.types[1].bitfield.regxmm != 0
4488 && i.types[2].bitfield.regxmm != 0
4489 && i.types[3].bitfield.regxmm != 0
4490 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4491 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4493 /* Clear the arguments that are stored in drex. */
4494 operand_type_set (&i.types[0], 0);
4495 operand_type_set (&i.types[3], 0);
4496 i.reg_operands -= 2;
4498 /* There are two different ways to encode a 4 operand
4499 instruction with all registers that uses OC1 set to
4500 0 or 1. Favor setting OC1 to 0 since this mimics the
4501 actions of other SSE5 assemblers. Use modrm encoding 2
4502 for register/register. Include the high order bit that
4503 is normally stored in the REX byte in the register
4505 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4506 i.drex.modrm_reg = 2;
4507 i.drex.modrm_regmem = 1;
4508 i.drex.reg = (i.op[3].regs->reg_num
4509 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4512 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4513 else if (i.types[0].bitfield.regxmm != 0
4514 && i.types[1].bitfield.regxmm != 0
4515 && (i.types[2].bitfield.regxmm
4516 || operand_type_check (i.types[2], anymem))
4517 && i.types[3].bitfield.regxmm != 0
4518 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4519 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4521 /* clear the arguments that are stored in drex */
4522 operand_type_set (&i.types[0], 0);
4523 operand_type_set (&i.types[3], 0);
4524 i.reg_operands -= 2;
4526 /* Specify the modrm encoding for memory addressing. Include
4527 the high order bit that is normally stored in the REX byte
4528 in the register field. */
4529 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4530 i.drex.modrm_reg = 1;
4531 i.drex.modrm_regmem = 2;
4532 i.drex.reg = (i.op[3].regs->reg_num
4533 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4536 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4537 else if (i.types[0].bitfield.regxmm != 0
4538 && operand_type_check (i.types[1], anymem) != 0
4539 && i.types[2].bitfield.regxmm != 0
4540 && i.types[3].bitfield.regxmm != 0
4541 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4542 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4544 /* Clear the arguments that are stored in drex. */
4545 operand_type_set (&i.types[0], 0);
4546 operand_type_set (&i.types[3], 0);
4547 i.reg_operands -= 2;
4549 /* Specify the modrm encoding for memory addressing. Include
4550 the high order bit that is normally stored in the REX byte
4551 in the register field. */
4552 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4553 i.drex.modrm_reg = 2;
4554 i.drex.modrm_regmem = 1;
4555 i.drex.reg = (i.op[3].regs->reg_num
4556 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4559 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4560 else if (i.types[0].bitfield.regxmm != 0
4561 && i.types[1].bitfield.regxmm != 0
4562 && i.types[2].bitfield.regxmm != 0
4563 && i.types[3].bitfield.regxmm != 0
4564 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4565 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4567 /* clear the arguments that are stored in drex */
4568 operand_type_set (&i.types[2], 0);
4569 operand_type_set (&i.types[3], 0);
4570 i.reg_operands -= 2;
4572 /* There are two different ways to encode a 4 operand
4573 instruction with all registers that uses OC1 set to
4574 0 or 1. Favor setting OC1 to 0 since this mimics the
4575 actions of other SSE5 assemblers. Use modrm encoding
4576 2 for register/register. Include the high order bit that
4577 is normally stored in the REX byte in the register
4579 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4580 i.drex.modrm_reg = 1;
4581 i.drex.modrm_regmem = 0;
4583 /* Remember the register, including the upper bits */
4584 i.drex.reg = (i.op[3].regs->reg_num
4585 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4588 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4589 else if (i.types[0].bitfield.regxmm != 0
4590 && (i.types[1].bitfield.regxmm
4591 || operand_type_check (i.types[1], anymem))
4592 && i.types[2].bitfield.regxmm != 0
4593 && i.types[3].bitfield.regxmm != 0
4594 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4595 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4597 /* Clear the arguments that are stored in drex. */
4598 operand_type_set (&i.types[2], 0);
4599 operand_type_set (&i.types[3], 0);
4600 i.reg_operands -= 2;
4602 /* Specify the modrm encoding and remember the register
4603 including the bits normally stored in the REX byte. */
4604 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4605 i.drex.modrm_reg = 0;
4606 i.drex.modrm_regmem = 1;
4607 i.drex.reg = (i.op[3].regs->reg_num
4608 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4611 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4612 else if (operand_type_check (i.types[0], anymem) != 0
4613 && i.types[1].bitfield.regxmm != 0
4614 && i.types[2].bitfield.regxmm != 0
4615 && i.types[3].bitfield.regxmm != 0
4616 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4617 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4619 /* clear the arguments that are stored in drex */
4620 operand_type_set (&i.types[2], 0);
4621 operand_type_set (&i.types[3], 0);
4622 i.reg_operands -= 2;
4624 /* Specify the modrm encoding and remember the register
4625 including the bits normally stored in the REX byte. */
4626 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4627 i.drex.modrm_reg = 1;
4628 i.drex.modrm_regmem = 0;
4629 i.drex.reg = (i.op[3].regs->reg_num
4630 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4634 as_bad (_("Incorrect operands for the '%s' instruction"),
4638 /* SSE5 instructions with the DREX byte where the only memory operand
4639 is in the 2nd argument, and the first and last xmm register must
4640 match, and is encoded in the DREX byte. */
4641 else if (i.tm.opcode_modifier.drex
4642 && !i.tm.opcode_modifier.drexv
4645 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4646 if (i.types[0].bitfield.regxmm != 0
4647 && (i.types[1].bitfield.regxmm
4648 || operand_type_check(i.types[1], anymem))
4649 && i.types[2].bitfield.regxmm != 0
4650 && i.types[3].bitfield.regxmm != 0
4651 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4652 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4654 /* clear the arguments that are stored in drex */
4655 operand_type_set (&i.types[0], 0);
4656 operand_type_set (&i.types[3], 0);
4657 i.reg_operands -= 2;
4659 /* Specify the modrm encoding and remember the register
4660 including the high bit normally stored in the REX
4662 i.drex.modrm_reg = 2;
4663 i.drex.modrm_regmem = 1;
4664 i.drex.reg = (i.op[3].regs->reg_num
4665 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4669 as_bad (_("Incorrect operands for the '%s' instruction"),
4673 /* SSE5 3 operand instructions that the result is a register, being
4674 either operand can be a memory operand, using OC0 to note which
4675 one is the memory. */
4676 else if (i.tm.opcode_modifier.drex
4677 && i.tm.opcode_modifier.drexv
4680 i.tm.extension_opcode = None;
4682 /* Case 1: 3 operand insn, src1 = register. */
4683 if (i.types[0].bitfield.regxmm != 0
4684 && i.types[1].bitfield.regxmm != 0
4685 && i.types[2].bitfield.regxmm != 0)
4687 /* Clear the arguments that are stored in drex. */
4688 operand_type_set (&i.types[2], 0);
4691 /* Specify the modrm encoding and remember the register
4692 including the high bit normally stored in the REX byte. */
4693 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4694 i.drex.modrm_reg = 1;
4695 i.drex.modrm_regmem = 0;
4696 i.drex.reg = (i.op[2].regs->reg_num
4697 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4700 /* Case 2: 3 operand insn, src1 = memory. */
4701 else if (operand_type_check (i.types[0], anymem) != 0
4702 && i.types[1].bitfield.regxmm != 0
4703 && i.types[2].bitfield.regxmm != 0)
4705 /* Clear the arguments that are stored in drex. */
4706 operand_type_set (&i.types[2], 0);
4709 /* Specify the modrm encoding and remember the register
4710 including the high bit normally stored in the REX
4712 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4713 i.drex.modrm_reg = 1;
4714 i.drex.modrm_regmem = 0;
4715 i.drex.reg = (i.op[2].regs->reg_num
4716 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4719 /* Case 3: 3 operand insn, src2 = memory. */
4720 else if (i.types[0].bitfield.regxmm != 0
4721 && operand_type_check (i.types[1], anymem) != 0
4722 && i.types[2].bitfield.regxmm != 0)
4724 /* Clear the arguments that are stored in drex. */
4725 operand_type_set (&i.types[2], 0);
4728 /* Specify the modrm encoding and remember the register
4729 including the high bit normally stored in the REX byte. */
4730 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4731 i.drex.modrm_reg = 0;
4732 i.drex.modrm_regmem = 1;
4733 i.drex.reg = (i.op[2].regs->reg_num
4734 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4738 as_bad (_("Incorrect operands for the '%s' instruction"),
4742 /* SSE5 4 operand instructions that are the comparison instructions
4743 where the first operand is the immediate value of the comparison
4745 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4747 /* Case 1: 4 operand insn, src1 = reg/memory. */
4748 if (operand_type_check (i.types[0], imm) != 0
4749 && (i.types[1].bitfield.regxmm
4750 || operand_type_check (i.types[1], anymem))
4751 && i.types[2].bitfield.regxmm != 0
4752 && i.types[3].bitfield.regxmm != 0)
4754 /* clear the arguments that are stored in drex */
4755 operand_type_set (&i.types[3], 0);
4758 /* Specify the modrm encoding and remember the register
4759 including the high bit normally stored in the REX byte. */
4760 i.drex.modrm_reg = 2;
4761 i.drex.modrm_regmem = 1;
4762 i.drex.reg = (i.op[3].regs->reg_num
4763 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4766 /* Case 2: 3 operand insn with ImmExt that places the
4767 opcode_extension as an immediate argument. This is used for
4768 all of the varients of comparison that supplies the appropriate
4769 value as part of the instruction. */
4770 else if ((i.types[0].bitfield.regxmm
4771 || operand_type_check (i.types[0], anymem))
4772 && i.types[1].bitfield.regxmm != 0
4773 && i.types[2].bitfield.regxmm != 0
4774 && operand_type_check (i.types[3], imm) != 0)
4776 /* clear the arguments that are stored in drex */
4777 operand_type_set (&i.types[2], 0);
4780 /* Specify the modrm encoding and remember the register
4781 including the high bit normally stored in the REX byte. */
4782 i.drex.modrm_reg = 1;
4783 i.drex.modrm_regmem = 0;
4784 i.drex.reg = (i.op[2].regs->reg_num
4785 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4789 as_bad (_("Incorrect operands for the '%s' instruction"),
4793 else if (i.tm.opcode_modifier.drex
4794 || i.tm.opcode_modifier.drexv
4795 || i.tm.opcode_modifier.drexc)
4796 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4800 bad_implicit_operand (int xmm)
4802 const char *reg = xmm ? "xmm0" : "ymm0";
4804 as_bad (_("the last operand of `%s' must be `%s%s'"),
4805 i.tm.name, register_prefix, reg);
4807 as_bad (_("the first operand of `%s' must be `%s%s'"),
4808 i.tm.name, register_prefix, reg);
4813 process_operands (void)
4815 /* Default segment register this instruction will use for memory
4816 accesses. 0 means unknown. This is only for optimizing out
4817 unnecessary segment overrides. */
4818 const seg_entry *default_seg = 0;
4820 /* Handle all of the DREX munging that SSE5 needs. */
4821 if (i.tm.opcode_modifier.drex
4822 || i.tm.opcode_modifier.drexv
4823 || i.tm.opcode_modifier.drexc)
4826 if (i.tm.opcode_modifier.sse2avx
4827 && (i.tm.opcode_modifier.vexnds
4828 || i.tm.opcode_modifier.vexndd))
4830 unsigned int dup = i.operands;
4831 unsigned int dest = dup - 1;
4834 /* The destination must be an xmm register. */
4835 assert (i.reg_operands
4836 && MAX_OPERANDS > dup
4837 && operand_type_equal (&i.types[dest], ®xmm));
4839 if (i.tm.opcode_modifier.firstxmm0)
4841 /* The first operand is implicit and must be xmm0. */
4842 assert (operand_type_equal (&i.types[0], ®xmm));
4843 if (i.op[0].regs->reg_num != 0)
4844 return bad_implicit_operand (1);
4846 if (i.tm.opcode_modifier.vex3sources)
4848 /* Keep xmm0 for instructions with VEX prefix and 3
4854 /* We remove the first xmm0 and keep the number of
4855 operands unchanged, which in fact duplicates the
4857 for (j = 1; j < i.operands; j++)
4859 i.op[j - 1] = i.op[j];
4860 i.types[j - 1] = i.types[j];
4861 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4865 else if (i.tm.opcode_modifier.implicit1stxmm0)
4867 assert ((MAX_OPERANDS - 1) > dup
4868 && i.tm.opcode_modifier.vex3sources);
4870 /* Add the implicit xmm0 for instructions with VEX prefix
4872 for (j = i.operands; j > 0; j--)
4874 i.op[j] = i.op[j - 1];
4875 i.types[j] = i.types[j - 1];
4876 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4879 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4880 i.types[0] = regxmm;
4881 i.tm.operand_types[0] = regxmm;
4884 i.reg_operands += 2;
4889 i.op[dup] = i.op[dest];
4890 i.types[dup] = i.types[dest];
4891 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4900 i.op[dup] = i.op[dest];
4901 i.types[dup] = i.types[dest];
4902 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4905 if (i.tm.opcode_modifier.immext)
4908 else if (i.tm.opcode_modifier.firstxmm0)
4912 /* The first operand is implicit and must be xmm0/ymm0. */
4913 assert (i.reg_operands
4914 && (operand_type_equal (&i.types[0], ®xmm)
4915 || operand_type_equal (&i.types[0], ®ymm)));
4916 if (i.op[0].regs->reg_num != 0)
4917 return bad_implicit_operand (i.types[0].bitfield.regxmm);
4919 for (j = 1; j < i.operands; j++)
4921 i.op[j - 1] = i.op[j];
4922 i.types[j - 1] = i.types[j];
4924 /* We need to adjust fields in i.tm since they are used by
4925 build_modrm_byte. */
4926 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4933 else if (i.tm.opcode_modifier.regkludge)
4935 /* The imul $imm, %reg instruction is converted into
4936 imul $imm, %reg, %reg, and the clr %reg instruction
4937 is converted into xor %reg, %reg. */
4939 unsigned int first_reg_op;
4941 if (operand_type_check (i.types[0], reg))
4945 /* Pretend we saw the extra register operand. */
4946 assert (i.reg_operands == 1
4947 && i.op[first_reg_op + 1].regs == 0);
4948 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4949 i.types[first_reg_op + 1] = i.types[first_reg_op];
4954 if (i.tm.opcode_modifier.shortform)
4956 if (i.types[0].bitfield.sreg2
4957 || i.types[0].bitfield.sreg3)
4959 if (i.tm.base_opcode == POP_SEG_SHORT
4960 && i.op[0].regs->reg_num == 1)
4962 as_bad (_("you can't `pop %scs'"), register_prefix);
4965 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4966 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4971 /* The register or float register operand is in operand
4975 if (i.types[0].bitfield.floatreg
4976 || operand_type_check (i.types[0], reg))
4980 /* Register goes in low 3 bits of opcode. */
4981 i.tm.base_opcode |= i.op[op].regs->reg_num;
4982 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4984 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4986 /* Warn about some common errors, but press on regardless.
4987 The first case can be generated by gcc (<= 2.8.1). */
4988 if (i.operands == 2)
4990 /* Reversed arguments on faddp, fsubp, etc. */
4991 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4992 register_prefix, i.op[1].regs->reg_name,
4993 register_prefix, i.op[0].regs->reg_name);
4997 /* Extraneous `l' suffix on fp insn. */
4998 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4999 register_prefix, i.op[0].regs->reg_name);
5004 else if (i.tm.opcode_modifier.modrm)
5006 /* The opcode is completed (modulo i.tm.extension_opcode which
5007 must be put into the modrm byte). Now, we make the modrm and
5008 index base bytes based on all the info we've collected. */
5010 default_seg = build_modrm_byte ();
5012 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5016 else if (i.tm.opcode_modifier.isstring)
5018 /* For the string instructions that allow a segment override
5019 on one of their operands, the default segment is ds. */
5023 if (i.tm.base_opcode == 0x8d /* lea */
5026 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5028 /* If a segment was explicitly specified, and the specified segment
5029 is not the default, use an opcode prefix to select it. If we
5030 never figured out what the default segment is, then default_seg
5031 will be zero at this point, and the specified segment prefix will
5033 if ((i.seg[0]) && (i.seg[0] != default_seg))
5035 if (!add_prefix (i.seg[0]->seg_prefix))
5041 static const seg_entry *
5042 build_modrm_byte (void)
5044 const seg_entry *default_seg = 0;
5045 unsigned int source, dest;
5048 /* The first operand of instructions with VEX prefix and 3 sources
5049 must be VEX_Imm4. */
5050 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5053 unsigned int nds, reg;
5055 if (i.tm.opcode_modifier.veximmext
5056 && i.tm.opcode_modifier.immext)
5058 dest = i.operands - 2;
5062 dest = i.operands - 1;
5065 /* There are 2 kinds of instructions:
5066 1. 5 operands: one immediate operand and 4 register
5067 operands or 3 register operands plus 1 memory operand.
5068 It must have VexNDS and VexW0 or VexW1. The destination
5069 must be either XMM or YMM register.
5070 2. 4 operands: 4 register operands or 3 register operands
5071 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5072 if (!((i.reg_operands == 4
5073 || (i.reg_operands == 3 && i.mem_operands == 1))
5074 && i.tm.opcode_modifier.vexnds
5075 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5076 || operand_type_equal (&i.tm.operand_types[dest], ®ymm))
5078 && i.imm_operands == 1
5079 && i.types[0].bitfield.vex_imm4
5080 && (i.tm.opcode_modifier.vexw0
5081 || i.tm.opcode_modifier.vexw1))
5083 && (i.imm_operands == 0
5084 || (i.imm_operands == 1
5085 && i.tm.opcode_modifier.immext))
5086 && i.tm.opcode_modifier.veximmext))))
5089 if (i.imm_operands == 0)
5091 /* When there is no immediate operand, generate an 8bit
5092 immediate operand to encode the first operand. */
5093 expressionS *exp = &im_expressions[i.imm_operands++];
5094 i.op[i.operands].imms = exp;
5095 i.types[i.operands] = imm8;
5097 /* If VexW1 is set, the first operand is the source and
5098 the second operand is encoded in the immediate operand. */
5099 if (i.tm.opcode_modifier.vexw1)
5110 /* FMA swaps REG and NDS. */
5111 if (i.tm.cpu_flags.bitfield.cpufma)
5119 assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
5120 || operand_type_equal (&i.tm.operand_types[reg],
5122 exp->X_op = O_constant;
5124 = ((i.op[reg].regs->reg_num
5125 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5131 if (i.tm.opcode_modifier.vexw0)
5133 /* If VexW0 is set, the third operand is the source and
5134 the second operand is encoded in the immediate
5141 /* VexW1 is set, the second operand is the source and
5142 the third operand is encoded in the immediate
5148 if (i.tm.opcode_modifier.immext)
5150 /* When ImmExt is set, the immdiate byte is the last
5152 imm = i.operands - 1;
5160 /* Turn on Imm8 so that output_imm will generate it. */
5161 i.types[imm].bitfield.imm8 = 1;
5164 assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm)
5165 || operand_type_equal (&i.tm.operand_types[reg],
5167 i.op[imm].imms->X_add_number
5168 |= ((i.op[reg].regs->reg_num
5169 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5172 assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
5173 || operand_type_equal (&i.tm.operand_types[nds], ®ymm));
5174 i.vex.register_specifier = i.op[nds].regs;
5180 /* SSE5 4 operand instructions are encoded in such a way that one of
5181 the inputs must match the destination register. Process_drex hides
5182 the 3rd argument in the drex field, so that by the time we get
5183 here, it looks to GAS as if this is a 2 operand instruction. */
5184 if ((i.tm.opcode_modifier.drex
5185 || i.tm.opcode_modifier.drexv
5186 || i.tm.opcode_modifier.drexc)
5187 && i.reg_operands == 2)
5189 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5190 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5192 i.rm.reg = reg->reg_num;
5193 i.rm.regmem = regmem->reg_num;
5195 if ((reg->reg_flags & RegRex) != 0)
5197 if ((regmem->reg_flags & RegRex) != 0)
5201 /* i.reg_operands MUST be the number of real register operands;
5202 implicit registers do not count. If there are 3 register
5203 operands, it must be a instruction with VexNDS. For a
5204 instruction with VexNDD, the destination register is encoded
5205 in VEX prefix. If there are 4 register operands, it must be
5206 a instruction with VEX prefix and 3 sources. */
5207 else if (i.mem_operands == 0
5208 && ((i.reg_operands == 2
5209 && !i.tm.opcode_modifier.vexndd)
5210 || (i.reg_operands == 3
5211 && i.tm.opcode_modifier.vexnds)
5212 || (i.reg_operands == 4 && vex_3_sources)))
5220 /* When there are 3 operands, one of them may be immediate,
5221 which may be the first or the last operand. Otherwise,
5222 the first operand must be shift count register (cl) or it
5223 is an instruction with VexNDS. */
5224 assert (i.imm_operands == 1
5225 || (i.imm_operands == 0
5226 && (i.tm.opcode_modifier.vexnds
5227 || i.types[0].bitfield.shiftcount)));
5228 if (operand_type_check (i.types[0], imm)
5229 || i.types[0].bitfield.shiftcount)
5235 /* When there are 4 operands, the first two must be 8bit
5236 immediate operands. The source operand will be the 3rd
5239 For instructions with VexNDS, if the first operand
5240 an imm8, the source operand is the 2nd one. If the last
5241 operand is imm8, the source operand is the first one. */
5242 assert ((i.imm_operands == 2
5243 && i.types[0].bitfield.imm8
5244 && i.types[1].bitfield.imm8)
5245 || (i.tm.opcode_modifier.vexnds
5246 && i.imm_operands == 1
5247 && (i.types[0].bitfield.imm8
5248 || i.types[i.operands - 1].bitfield.imm8)));
5249 if (i.tm.opcode_modifier.vexnds)
5251 if (i.types[0].bitfield.imm8)
5269 if (i.tm.opcode_modifier.vexnds)
5271 /* For instructions with VexNDS, the register-only
5272 source operand must be XMM or YMM register. It is
5273 encoded in VEX prefix. */
5274 if ((dest + 1) >= i.operands
5275 || (!operand_type_equal (&i.tm.operand_types[dest],
5277 && !operand_type_equal (&i.tm.operand_types[dest],
5280 i.vex.register_specifier = i.op[dest].regs;
5286 /* One of the register operands will be encoded in the i.tm.reg
5287 field, the other in the combined i.tm.mode and i.tm.regmem
5288 fields. If no form of this instruction supports a memory
5289 destination operand, then we assume the source operand may
5290 sometimes be a memory operand and so we need to store the
5291 destination in the i.rm.reg field. */
5292 if (!i.tm.operand_types[dest].bitfield.regmem
5293 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
5295 i.rm.reg = i.op[dest].regs->reg_num;
5296 i.rm.regmem = i.op[source].regs->reg_num;
5297 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5299 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5304 i.rm.reg = i.op[source].regs->reg_num;
5305 i.rm.regmem = i.op[dest].regs->reg_num;
5306 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
5308 if ((i.op[source].regs->reg_flags & RegRex) != 0)
5311 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
5313 if (!i.types[0].bitfield.control
5314 && !i.types[1].bitfield.control)
5316 i.rex &= ~(REX_R | REX_B);
5317 add_prefix (LOCK_PREFIX_OPCODE);
5321 { /* If it's not 2 reg operands... */
5326 unsigned int fake_zero_displacement = 0;
5329 /* This has been precalculated for SSE5 instructions
5330 that have a DREX field earlier in process_drex. */
5331 if (i.tm.opcode_modifier.drex
5332 || i.tm.opcode_modifier.drexv
5333 || i.tm.opcode_modifier.drexc)
5334 op = i.drex.modrm_regmem;
5337 for (op = 0; op < i.operands; op++)
5338 if (operand_type_check (i.types[op], anymem))
5340 assert (op < i.operands);
5345 if (i.base_reg == 0)
5348 if (!i.disp_operands)
5349 fake_zero_displacement = 1;
5350 if (i.index_reg == 0)
5352 /* Operand is just <disp> */
5353 if (flag_code == CODE_64BIT)
5355 /* 64bit mode overwrites the 32bit absolute
5356 addressing by RIP relative addressing and
5357 absolute addressing is encoded by one of the
5358 redundant SIB forms. */
5359 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5360 i.sib.base = NO_BASE_REGISTER;
5361 i.sib.index = NO_INDEX_REGISTER;
5362 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
5363 ? disp32s : disp32);
5365 else if ((flag_code == CODE_16BIT)
5366 ^ (i.prefix[ADDR_PREFIX] != 0))
5368 i.rm.regmem = NO_BASE_REGISTER_16;
5369 i.types[op] = disp16;
5373 i.rm.regmem = NO_BASE_REGISTER;
5374 i.types[op] = disp32;
5377 else /* !i.base_reg && i.index_reg */
5379 if (i.index_reg->reg_num == RegEiz
5380 || i.index_reg->reg_num == RegRiz)
5381 i.sib.index = NO_INDEX_REGISTER;
5383 i.sib.index = i.index_reg->reg_num;
5384 i.sib.base = NO_BASE_REGISTER;
5385 i.sib.scale = i.log2_scale_factor;
5386 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5387 i.types[op].bitfield.disp8 = 0;
5388 i.types[op].bitfield.disp16 = 0;
5389 i.types[op].bitfield.disp64 = 0;
5390 if (flag_code != CODE_64BIT)
5392 /* Must be 32 bit */
5393 i.types[op].bitfield.disp32 = 1;
5394 i.types[op].bitfield.disp32s = 0;
5398 i.types[op].bitfield.disp32 = 0;
5399 i.types[op].bitfield.disp32s = 1;
5401 if ((i.index_reg->reg_flags & RegRex) != 0)
5405 /* RIP addressing for 64bit mode. */
5406 else if (i.base_reg->reg_num == RegRip ||
5407 i.base_reg->reg_num == RegEip)
5409 i.rm.regmem = NO_BASE_REGISTER;
5410 i.types[op].bitfield.disp8 = 0;
5411 i.types[op].bitfield.disp16 = 0;
5412 i.types[op].bitfield.disp32 = 0;
5413 i.types[op].bitfield.disp32s = 1;
5414 i.types[op].bitfield.disp64 = 0;
5415 i.flags[op] |= Operand_PCrel;
5416 if (! i.disp_operands)
5417 fake_zero_displacement = 1;
5419 else if (i.base_reg->reg_type.bitfield.reg16)
5421 switch (i.base_reg->reg_num)
5424 if (i.index_reg == 0)
5426 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5427 i.rm.regmem = i.index_reg->reg_num - 6;
5431 if (i.index_reg == 0)
5434 if (operand_type_check (i.types[op], disp) == 0)
5436 /* fake (%bp) into 0(%bp) */
5437 i.types[op].bitfield.disp8 = 1;
5438 fake_zero_displacement = 1;
5441 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5442 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5444 default: /* (%si) -> 4 or (%di) -> 5 */
5445 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5447 i.rm.mode = mode_from_disp_size (i.types[op]);
5449 else /* i.base_reg and 32/64 bit mode */
5451 if (flag_code == CODE_64BIT
5452 && operand_type_check (i.types[op], disp))
5454 i386_operand_type temp;
5455 operand_type_set (&temp, 0);
5456 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5458 if (i.prefix[ADDR_PREFIX] == 0)
5459 i.types[op].bitfield.disp32s = 1;
5461 i.types[op].bitfield.disp32 = 1;
5464 i.rm.regmem = i.base_reg->reg_num;
5465 if ((i.base_reg->reg_flags & RegRex) != 0)
5467 i.sib.base = i.base_reg->reg_num;
5468 /* x86-64 ignores REX prefix bit here to avoid decoder
5470 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5473 if (i.disp_operands == 0)
5475 fake_zero_displacement = 1;
5476 i.types[op].bitfield.disp8 = 1;
5479 else if (i.base_reg->reg_num == ESP_REG_NUM)
5483 i.sib.scale = i.log2_scale_factor;
5484 if (i.index_reg == 0)
5486 /* <disp>(%esp) becomes two byte modrm with no index
5487 register. We've already stored the code for esp
5488 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5489 Any base register besides %esp will not use the
5490 extra modrm byte. */
5491 i.sib.index = NO_INDEX_REGISTER;
5495 if (i.index_reg->reg_num == RegEiz
5496 || i.index_reg->reg_num == RegRiz)
5497 i.sib.index = NO_INDEX_REGISTER;
5499 i.sib.index = i.index_reg->reg_num;
5500 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5501 if ((i.index_reg->reg_flags & RegRex) != 0)
5506 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5507 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5510 i.rm.mode = mode_from_disp_size (i.types[op]);
5513 if (fake_zero_displacement)
5515 /* Fakes a zero displacement assuming that i.types[op]
5516 holds the correct displacement size. */
5519 assert (i.op[op].disps == 0);
5520 exp = &disp_expressions[i.disp_operands++];
5521 i.op[op].disps = exp;
5522 exp->X_op = O_constant;
5523 exp->X_add_number = 0;
5524 exp->X_add_symbol = (symbolS *) 0;
5525 exp->X_op_symbol = (symbolS *) 0;
5533 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5534 (if any) based on i.tm.extension_opcode. Again, we must be
5535 careful to make sure that segment/control/debug/test/MMX
5536 registers are coded into the i.rm.reg field. */
5541 /* This has been precalculated for SSE5 instructions
5542 that have a DREX field earlier in process_drex. */
5543 if (i.tm.opcode_modifier.drex
5544 || i.tm.opcode_modifier.drexv
5545 || i.tm.opcode_modifier.drexc)
5547 op = i.drex.modrm_reg;
5548 i.rm.reg = i.op[op].regs->reg_num;
5549 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5554 unsigned int vex_reg = ~0;
5556 for (op = 0; op < i.operands; op++)
5557 if (i.types[op].bitfield.reg8
5558 || i.types[op].bitfield.reg16
5559 || i.types[op].bitfield.reg32
5560 || i.types[op].bitfield.reg64
5561 || i.types[op].bitfield.regmmx
5562 || i.types[op].bitfield.regxmm
5563 || i.types[op].bitfield.regymm
5564 || i.types[op].bitfield.sreg2
5565 || i.types[op].bitfield.sreg3
5566 || i.types[op].bitfield.control
5567 || i.types[op].bitfield.debug
5568 || i.types[op].bitfield.test)
5573 else if (i.tm.opcode_modifier.vexnds)
5575 /* For instructions with VexNDS, the register-only
5576 source operand is encoded in VEX prefix. */
5577 assert (mem != (unsigned int) ~0);
5582 assert (op < i.operands);
5587 assert (vex_reg < i.operands);
5590 else if (i.tm.opcode_modifier.vexndd)
5592 /* For instructions with VexNDD, there should be
5593 no memory operand and the register destination
5594 is encoded in VEX prefix. */
5595 assert (i.mem_operands == 0
5596 && (op + 2) == i.operands);
5600 assert (op < i.operands);
5602 if (vex_reg != (unsigned int) ~0)
5604 assert (i.reg_operands == 2);
5606 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5608 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5611 i.vex.register_specifier = i.op[vex_reg].regs;
5614 /* If there is an extension opcode to put here, the
5615 register number must be put into the regmem field. */
5616 if (i.tm.extension_opcode != None)
5618 i.rm.regmem = i.op[op].regs->reg_num;
5619 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5624 i.rm.reg = i.op[op].regs->reg_num;
5625 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5630 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5631 must set it to 3 to indicate this is a register operand
5632 in the regmem field. */
5633 if (!i.mem_operands)
5637 /* Fill in i.rm.reg field with extension opcode (if any). */
5638 if (i.tm.extension_opcode != None
5639 && !(i.tm.opcode_modifier.drex
5640 || i.tm.opcode_modifier.drexv
5641 || i.tm.opcode_modifier.drexc))
5642 i.rm.reg = i.tm.extension_opcode;
5648 output_branch (void)
5653 relax_substateT subtype;
5658 if (flag_code == CODE_16BIT)
5662 if (i.prefix[DATA_PREFIX] != 0)
5668 /* Pentium4 branch hints. */
5669 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5670 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5675 if (i.prefix[REX_PREFIX] != 0)
5681 if (i.prefixes != 0 && !intel_syntax)
5682 as_warn (_("skipping prefixes on this instruction"));
5684 /* It's always a symbol; End frag & setup for relax.
5685 Make sure there is enough room in this frag for the largest
5686 instruction we may generate in md_convert_frag. This is 2
5687 bytes for the opcode and room for the prefix and largest
5689 frag_grow (prefix + 2 + 4);
5690 /* Prefix and 1 opcode byte go in fr_fix. */
5691 p = frag_more (prefix + 1);
5692 if (i.prefix[DATA_PREFIX] != 0)
5693 *p++ = DATA_PREFIX_OPCODE;
5694 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5695 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5696 *p++ = i.prefix[SEG_PREFIX];
5697 if (i.prefix[REX_PREFIX] != 0)
5698 *p++ = i.prefix[REX_PREFIX];
5699 *p = i.tm.base_opcode;
5701 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5702 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5703 else if (cpu_arch_flags.bitfield.cpui386)
5704 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5706 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5709 sym = i.op[0].disps->X_add_symbol;
5710 off = i.op[0].disps->X_add_number;
5712 if (i.op[0].disps->X_op != O_constant
5713 && i.op[0].disps->X_op != O_symbol)
5715 /* Handle complex expressions. */
5716 sym = make_expr_symbol (i.op[0].disps);
5720 /* 1 possible extra opcode + 4 byte displacement go in var part.
5721 Pass reloc in fr_var. */
5722 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5732 if (i.tm.opcode_modifier.jumpbyte)
5734 /* This is a loop or jecxz type instruction. */
5736 if (i.prefix[ADDR_PREFIX] != 0)
5738 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5741 /* Pentium4 branch hints. */
5742 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5743 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5745 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5754 if (flag_code == CODE_16BIT)
5757 if (i.prefix[DATA_PREFIX] != 0)
5759 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5769 if (i.prefix[REX_PREFIX] != 0)
5771 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5775 if (i.prefixes != 0 && !intel_syntax)
5776 as_warn (_("skipping prefixes on this instruction"));
5778 p = frag_more (1 + size);
5779 *p++ = i.tm.base_opcode;
5781 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5782 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5784 /* All jumps handled here are signed, but don't use a signed limit
5785 check for 32 and 16 bit jumps as we want to allow wrap around at
5786 4G and 64k respectively. */
5788 fixP->fx_signed = 1;
5792 output_interseg_jump (void)
5800 if (flag_code == CODE_16BIT)
5804 if (i.prefix[DATA_PREFIX] != 0)
5810 if (i.prefix[REX_PREFIX] != 0)
5820 if (i.prefixes != 0 && !intel_syntax)
5821 as_warn (_("skipping prefixes on this instruction"));
5823 /* 1 opcode; 2 segment; offset */
5824 p = frag_more (prefix + 1 + 2 + size);
5826 if (i.prefix[DATA_PREFIX] != 0)
5827 *p++ = DATA_PREFIX_OPCODE;
5829 if (i.prefix[REX_PREFIX] != 0)
5830 *p++ = i.prefix[REX_PREFIX];
5832 *p++ = i.tm.base_opcode;
5833 if (i.op[1].imms->X_op == O_constant)
5835 offsetT n = i.op[1].imms->X_add_number;
5838 && !fits_in_unsigned_word (n)
5839 && !fits_in_signed_word (n))
5841 as_bad (_("16-bit jump out of range"));
5844 md_number_to_chars (p, n, size);
5847 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5848 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5849 if (i.op[0].imms->X_op != O_constant)
5850 as_bad (_("can't handle non absolute segment in `%s'"),
5852 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5858 fragS *insn_start_frag;
5859 offsetT insn_start_off;
5861 /* Tie dwarf2 debug info to the address at the start of the insn.
5862 We can't do this after the insn has been output as the current
5863 frag may have been closed off. eg. by frag_var. */
5864 dwarf2_emit_insn (0);
5866 insn_start_frag = frag_now;
5867 insn_start_off = frag_now_fix ();
5870 if (i.tm.opcode_modifier.jump)
5872 else if (i.tm.opcode_modifier.jumpbyte
5873 || i.tm.opcode_modifier.jumpdword)
5875 else if (i.tm.opcode_modifier.jumpintersegment)
5876 output_interseg_jump ();
5879 /* Output normal instructions here. */
5883 unsigned int prefix;
5885 /* Since the VEX prefix contains the implicit prefix, we don't
5886 need the explicit prefix. */
5887 if (!i.tm.opcode_modifier.vex)
5889 switch (i.tm.opcode_length)
5892 if (i.tm.base_opcode & 0xff000000)
5894 prefix = (i.tm.base_opcode >> 24) & 0xff;
5899 if ((i.tm.base_opcode & 0xff0000) != 0)
5901 prefix = (i.tm.base_opcode >> 16) & 0xff;
5902 if (i.tm.cpu_flags.bitfield.cpupadlock)
5905 if (prefix != REPE_PREFIX_OPCODE
5906 || (i.prefix[LOCKREP_PREFIX]
5907 != REPE_PREFIX_OPCODE))
5908 add_prefix (prefix);
5911 add_prefix (prefix);
5920 /* The prefix bytes. */
5921 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5923 FRAG_APPEND_1_CHAR (*q);
5926 if (i.tm.opcode_modifier.vex)
5928 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5933 /* REX byte is encoded in VEX prefix. */
5937 FRAG_APPEND_1_CHAR (*q);
5940 /* There should be no other prefixes for instructions
5945 /* Now the VEX prefix. */
5946 p = frag_more (i.vex.length);
5947 for (j = 0; j < i.vex.length; j++)
5948 p[j] = i.vex.bytes[j];
5951 /* Now the opcode; be careful about word order here! */
5952 if (i.tm.opcode_length == 1)
5954 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5958 switch (i.tm.opcode_length)
5962 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5972 /* Put out high byte first: can't use md_number_to_chars! */
5973 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5974 *p = i.tm.base_opcode & 0xff;
5976 /* On SSE5, encode the OC1 bit in the DREX field if this
5977 encoding has multiple formats. */
5978 if (i.tm.opcode_modifier.drex
5979 && i.tm.opcode_modifier.drexv
5980 && DREX_OC1 (i.tm.extension_opcode))
5981 *p |= DREX_OC1_MASK;
5984 /* Now the modrm byte and sib byte (if present). */
5985 if (i.tm.opcode_modifier.modrm)
5987 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5990 /* If i.rm.regmem == ESP (4)
5991 && i.rm.mode != (Register mode)
5993 ==> need second modrm byte. */
5994 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5996 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5997 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5999 | i.sib.scale << 6));
6002 /* Write the DREX byte if needed. */
6003 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6006 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6008 /* Encode the OC0 bit if this encoding has multiple
6010 if ((i.tm.opcode_modifier.drex
6011 || i.tm.opcode_modifier.drexv)
6012 && DREX_OC0 (i.tm.extension_opcode))
6013 *p |= DREX_OC0_MASK;
6016 if (i.disp_operands)
6017 output_disp (insn_start_frag, insn_start_off);
6020 output_imm (insn_start_frag, insn_start_off);
6026 pi ("" /*line*/, &i);
6028 #endif /* DEBUG386 */
6031 /* Return the size of the displacement operand N. */
6034 disp_size (unsigned int n)
6037 if (i.types[n].bitfield.disp64)
6039 else if (i.types[n].bitfield.disp8)
6041 else if (i.types[n].bitfield.disp16)
6046 /* Return the size of the immediate operand N. */
6049 imm_size (unsigned int n)
6052 if (i.types[n].bitfield.imm64)
6054 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6056 else if (i.types[n].bitfield.imm16)
6062 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
6067 for (n = 0; n < i.operands; n++)
6069 if (operand_type_check (i.types[n], disp))
6071 if (i.op[n].disps->X_op == O_constant)
6073 int size = disp_size (n);
6076 val = offset_in_range (i.op[n].disps->X_add_number,
6078 p = frag_more (size);
6079 md_number_to_chars (p, val, size);
6083 enum bfd_reloc_code_real reloc_type;
6084 int size = disp_size (n);
6085 int sign = i.types[n].bitfield.disp32s;
6086 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6088 /* We can't have 8 bit displacement here. */
6089 assert (!i.types[n].bitfield.disp8);
6091 /* The PC relative address is computed relative
6092 to the instruction boundary, so in case immediate
6093 fields follows, we need to adjust the value. */
6094 if (pcrel && i.imm_operands)
6099 for (n1 = 0; n1 < i.operands; n1++)
6100 if (operand_type_check (i.types[n1], imm))
6102 /* Only one immediate is allowed for PC
6103 relative address. */
6106 i.op[n].disps->X_add_number -= sz;
6108 /* We should find the immediate. */
6112 p = frag_more (size);
6113 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
6115 && GOT_symbol == i.op[n].disps->X_add_symbol
6116 && (((reloc_type == BFD_RELOC_32
6117 || reloc_type == BFD_RELOC_X86_64_32S
6118 || (reloc_type == BFD_RELOC_64
6120 && (i.op[n].disps->X_op == O_symbol
6121 || (i.op[n].disps->X_op == O_add
6122 && ((symbol_get_value_expression
6123 (i.op[n].disps->X_op_symbol)->X_op)
6125 || reloc_type == BFD_RELOC_32_PCREL))
6129 if (insn_start_frag == frag_now)
6130 add = (p - frag_now->fr_literal) - insn_start_off;
6135 add = insn_start_frag->fr_fix - insn_start_off;
6136 for (fr = insn_start_frag->fr_next;
6137 fr && fr != frag_now; fr = fr->fr_next)
6139 add += p - frag_now->fr_literal;
6144 reloc_type = BFD_RELOC_386_GOTPC;
6145 i.op[n].imms->X_add_number += add;
6147 else if (reloc_type == BFD_RELOC_64)
6148 reloc_type = BFD_RELOC_X86_64_GOTPC64;
6150 /* Don't do the adjustment for x86-64, as there
6151 the pcrel addressing is relative to the _next_
6152 insn, and that is taken care of in other code. */
6153 reloc_type = BFD_RELOC_X86_64_GOTPC32;
6155 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6156 i.op[n].disps, pcrel, reloc_type);
6163 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
6168 for (n = 0; n < i.operands; n++)
6170 if (operand_type_check (i.types[n], imm))
6172 if (i.op[n].imms->X_op == O_constant)
6174 int size = imm_size (n);
6177 val = offset_in_range (i.op[n].imms->X_add_number,
6179 p = frag_more (size);
6180 md_number_to_chars (p, val, size);
6184 /* Not absolute_section.
6185 Need a 32-bit fixup (don't support 8bit
6186 non-absolute imms). Try to support other
6188 enum bfd_reloc_code_real reloc_type;
6189 int size = imm_size (n);
6192 if (i.types[n].bitfield.imm32s
6193 && (i.suffix == QWORD_MNEM_SUFFIX
6194 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
6199 p = frag_more (size);
6200 reloc_type = reloc (size, 0, sign, i.reloc[n]);
6202 /* This is tough to explain. We end up with this one if we
6203 * have operands that look like
6204 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6205 * obtain the absolute address of the GOT, and it is strongly
6206 * preferable from a performance point of view to avoid using
6207 * a runtime relocation for this. The actual sequence of
6208 * instructions often look something like:
6213 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6215 * The call and pop essentially return the absolute address
6216 * of the label .L66 and store it in %ebx. The linker itself
6217 * will ultimately change the first operand of the addl so
6218 * that %ebx points to the GOT, but to keep things simple, the
6219 * .o file must have this operand set so that it generates not
6220 * the absolute address of .L66, but the absolute address of
6221 * itself. This allows the linker itself simply treat a GOTPC
6222 * relocation as asking for a pcrel offset to the GOT to be
6223 * added in, and the addend of the relocation is stored in the
6224 * operand field for the instruction itself.
6226 * Our job here is to fix the operand so that it would add
6227 * the correct offset so that %ebx would point to itself. The
6228 * thing that is tricky is that .-.L66 will point to the
6229 * beginning of the instruction, so we need to further modify
6230 * the operand so that it will point to itself. There are
6231 * other cases where you have something like:
6233 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6235 * and here no correction would be required. Internally in
6236 * the assembler we treat operands of this form as not being
6237 * pcrel since the '.' is explicitly mentioned, and I wonder
6238 * whether it would simplify matters to do it this way. Who
6239 * knows. In earlier versions of the PIC patches, the
6240 * pcrel_adjust field was used to store the correction, but
6241 * since the expression is not pcrel, I felt it would be
6242 * confusing to do it this way. */
6244 if ((reloc_type == BFD_RELOC_32
6245 || reloc_type == BFD_RELOC_X86_64_32S
6246 || reloc_type == BFD_RELOC_64)
6248 && GOT_symbol == i.op[n].imms->X_add_symbol
6249 && (i.op[n].imms->X_op == O_symbol
6250 || (i.op[n].imms->X_op == O_add
6251 && ((symbol_get_value_expression
6252 (i.op[n].imms->X_op_symbol)->X_op)
6257 if (insn_start_frag == frag_now)
6258 add = (p - frag_now->fr_literal) - insn_start_off;
6263 add = insn_start_frag->fr_fix - insn_start_off;
6264 for (fr = insn_start_frag->fr_next;
6265 fr && fr != frag_now; fr = fr->fr_next)
6267 add += p - frag_now->fr_literal;
6271 reloc_type = BFD_RELOC_386_GOTPC;
6273 reloc_type = BFD_RELOC_X86_64_GOTPC32;
6275 reloc_type = BFD_RELOC_X86_64_GOTPC64;
6276 i.op[n].imms->X_add_number += add;
6278 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6279 i.op[n].imms, 0, reloc_type);
6285 /* x86_cons_fix_new is called via the expression parsing code when a
6286 reloc is needed. We use this hook to get the correct .got reloc. */
6287 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6288 static int cons_sign = -1;
6291 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
6294 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6296 got_reloc = NO_RELOC;
6299 if (exp->X_op == O_secrel)
6301 exp->X_op = O_symbol;
6302 r = BFD_RELOC_32_SECREL;
6306 fix_new_exp (frag, off, len, exp, 0, r);
6309 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6310 # define lex_got(reloc, adjust, types) NULL
6312 /* Parse operands of the form
6313 <symbol>@GOTOFF+<nnn>
6314 and similar .plt or .got references.
6316 If we find one, set up the correct relocation in RELOC and copy the
6317 input string, minus the `@GOTOFF' into a malloc'd buffer for
6318 parsing by the calling routine. Return this buffer, and if ADJUST
6319 is non-null set it to the length of the string we removed from the
6320 input line. Otherwise return NULL. */
6322 lex_got (enum bfd_reloc_code_real *reloc,
6324 i386_operand_type *types)
6326 /* Some of the relocations depend on the size of what field is to
6327 be relocated. But in our callers i386_immediate and i386_displacement
6328 we don't yet know the operand size (this will be set by insn
6329 matching). Hence we record the word32 relocation here,
6330 and adjust the reloc according to the real size in reloc(). */
6331 static const struct {
6333 const enum bfd_reloc_code_real rel[2];
6334 const i386_operand_type types64;
6337 BFD_RELOC_X86_64_PLTOFF64 },
6338 OPERAND_TYPE_IMM64 },
6339 { "PLT", { BFD_RELOC_386_PLT32,
6340 BFD_RELOC_X86_64_PLT32 },
6341 OPERAND_TYPE_IMM32_32S_DISP32 },
6343 BFD_RELOC_X86_64_GOTPLT64 },
6344 OPERAND_TYPE_IMM64_DISP64 },
6345 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6346 BFD_RELOC_X86_64_GOTOFF64 },
6347 OPERAND_TYPE_IMM64_DISP64 },
6349 BFD_RELOC_X86_64_GOTPCREL },
6350 OPERAND_TYPE_IMM32_32S_DISP32 },
6351 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6352 BFD_RELOC_X86_64_TLSGD },
6353 OPERAND_TYPE_IMM32_32S_DISP32 },
6354 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6356 OPERAND_TYPE_NONE },
6358 BFD_RELOC_X86_64_TLSLD },
6359 OPERAND_TYPE_IMM32_32S_DISP32 },
6360 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6361 BFD_RELOC_X86_64_GOTTPOFF },
6362 OPERAND_TYPE_IMM32_32S_DISP32 },
6363 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6364 BFD_RELOC_X86_64_TPOFF32 },
6365 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6366 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6368 OPERAND_TYPE_NONE },
6369 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6370 BFD_RELOC_X86_64_DTPOFF32 },
6372 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
6373 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6375 OPERAND_TYPE_NONE },
6376 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6378 OPERAND_TYPE_NONE },
6379 { "GOT", { BFD_RELOC_386_GOT32,
6380 BFD_RELOC_X86_64_GOT32 },
6381 OPERAND_TYPE_IMM32_32S_64_DISP32 },
6382 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6383 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
6384 OPERAND_TYPE_IMM32_32S_DISP32 },
6385 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6386 BFD_RELOC_X86_64_TLSDESC_CALL },
6387 OPERAND_TYPE_IMM32_32S_DISP32 },
6395 for (cp = input_line_pointer; *cp != '@'; cp++)
6396 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
6399 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
6403 len = strlen (gotrel[j].str);
6404 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
6406 if (gotrel[j].rel[object_64bit] != 0)
6409 char *tmpbuf, *past_reloc;
6411 *reloc = gotrel[j].rel[object_64bit];
6417 if (flag_code != CODE_64BIT)
6419 types->bitfield.imm32 = 1;
6420 types->bitfield.disp32 = 1;
6423 *types = gotrel[j].types64;
6426 if (GOT_symbol == NULL)
6427 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6429 /* The length of the first part of our input line. */
6430 first = cp - input_line_pointer;
6432 /* The second part goes from after the reloc token until
6433 (and including) an end_of_line char or comma. */
6434 past_reloc = cp + 1 + len;
6436 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6438 second = cp + 1 - past_reloc;
6440 /* Allocate and copy string. The trailing NUL shouldn't
6441 be necessary, but be safe. */
6442 tmpbuf = xmalloc (first + second + 2);
6443 memcpy (tmpbuf, input_line_pointer, first);
6444 if (second != 0 && *past_reloc != ' ')
6445 /* Replace the relocation token with ' ', so that
6446 errors like foo@GOTOFF1 will be detected. */
6447 tmpbuf[first++] = ' ';
6448 memcpy (tmpbuf + first, past_reloc, second);
6449 tmpbuf[first + second] = '\0';
6453 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6454 gotrel[j].str, 1 << (5 + object_64bit));
6459 /* Might be a symbol version string. Don't as_bad here. */
6464 x86_cons (expressionS *exp, int size)
6466 if (size == 4 || (object_64bit && size == 8))
6468 /* Handle @GOTOFF and the like in an expression. */
6470 char *gotfree_input_line;
6473 save = input_line_pointer;
6474 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
6475 if (gotfree_input_line)
6476 input_line_pointer = gotfree_input_line;
6480 if (gotfree_input_line)
6482 /* expression () has merrily parsed up to the end of line,
6483 or a comma - in the wrong buffer. Transfer how far
6484 input_line_pointer has moved to the right buffer. */
6485 input_line_pointer = (save
6486 + (input_line_pointer - gotfree_input_line)
6488 free (gotfree_input_line);
6489 if (exp->X_op == O_constant
6490 || exp->X_op == O_absent
6491 || exp->X_op == O_illegal
6492 || exp->X_op == O_register
6493 || exp->X_op == O_big)
6495 char c = *input_line_pointer;
6496 *input_line_pointer = 0;
6497 as_bad (_("missing or invalid expression `%s'"), save);
6498 *input_line_pointer = c;
6507 static void signed_cons (int size)
6509 if (flag_code == CODE_64BIT)
6517 pe_directive_secrel (dummy)
6518 int dummy ATTRIBUTE_UNUSED;
6525 if (exp.X_op == O_symbol)
6526 exp.X_op = O_secrel;
6528 emit_expr (&exp, 4);
6530 while (*input_line_pointer++ == ',');
6532 input_line_pointer--;
6533 demand_empty_rest_of_line ();
6538 i386_immediate (char *imm_start)
6540 char *save_input_line_pointer;
6541 char *gotfree_input_line;
6544 i386_operand_type types;
6546 operand_type_set (&types, ~0);
6548 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6550 as_bad (_("at most %d immediate operands are allowed"),
6551 MAX_IMMEDIATE_OPERANDS);
6555 exp = &im_expressions[i.imm_operands++];
6556 i.op[this_operand].imms = exp;
6558 if (is_space_char (*imm_start))
6561 save_input_line_pointer = input_line_pointer;
6562 input_line_pointer = imm_start;
6564 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6565 if (gotfree_input_line)
6566 input_line_pointer = gotfree_input_line;
6568 exp_seg = expression (exp);
6571 if (*input_line_pointer)
6572 as_bad (_("junk `%s' after expression"), input_line_pointer);
6574 input_line_pointer = save_input_line_pointer;
6575 if (gotfree_input_line)
6576 free (gotfree_input_line);
6578 if (exp->X_op == O_absent
6579 || exp->X_op == O_illegal
6580 || exp->X_op == O_big
6581 || (gotfree_input_line
6582 && (exp->X_op == O_constant
6583 || exp->X_op == O_register)))
6585 as_bad (_("missing or invalid immediate expression `%s'"),
6589 else if (exp->X_op == O_constant)
6591 /* Size it properly later. */
6592 i.types[this_operand].bitfield.imm64 = 1;
6593 /* If BFD64, sign extend val. */
6594 if (!use_rela_relocations
6595 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6597 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
6599 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6600 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
6601 && exp_seg != absolute_section
6602 && exp_seg != text_section
6603 && exp_seg != data_section
6604 && exp_seg != bss_section
6605 && exp_seg != undefined_section
6606 && !bfd_is_com_section (exp_seg))
6608 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6612 else if (!intel_syntax && exp->X_op == O_register)
6614 as_bad (_("illegal immediate register operand %s"), imm_start);
6619 /* This is an address. The size of the address will be
6620 determined later, depending on destination register,
6621 suffix, or the default for the section. */
6622 i.types[this_operand].bitfield.imm8 = 1;
6623 i.types[this_operand].bitfield.imm16 = 1;
6624 i.types[this_operand].bitfield.imm32 = 1;
6625 i.types[this_operand].bitfield.imm32s = 1;
6626 i.types[this_operand].bitfield.imm64 = 1;
6627 i.types[this_operand] = operand_type_and (i.types[this_operand],
6635 i386_scale (char *scale)
6638 char *save = input_line_pointer;
6640 input_line_pointer = scale;
6641 val = get_absolute_expression ();
6646 i.log2_scale_factor = 0;
6649 i.log2_scale_factor = 1;
6652 i.log2_scale_factor = 2;
6655 i.log2_scale_factor = 3;
6659 char sep = *input_line_pointer;
6661 *input_line_pointer = '\0';
6662 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6664 *input_line_pointer = sep;
6665 input_line_pointer = save;
6669 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6671 as_warn (_("scale factor of %d without an index register"),
6672 1 << i.log2_scale_factor);
6673 i.log2_scale_factor = 0;
6675 scale = input_line_pointer;
6676 input_line_pointer = save;
6681 i386_displacement (char *disp_start, char *disp_end)
6685 char *save_input_line_pointer;
6686 char *gotfree_input_line;
6688 i386_operand_type bigdisp, types = anydisp;
6691 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6693 as_bad (_("at most %d displacement operands are allowed"),
6694 MAX_MEMORY_OPERANDS);
6698 operand_type_set (&bigdisp, 0);
6699 if ((i.types[this_operand].bitfield.jumpabsolute)
6700 || (!current_templates->start->opcode_modifier.jump
6701 && !current_templates->start->opcode_modifier.jumpdword))
6703 bigdisp.bitfield.disp32 = 1;
6704 override = (i.prefix[ADDR_PREFIX] != 0);
6705 if (flag_code == CODE_64BIT)
6709 bigdisp.bitfield.disp32s = 1;
6710 bigdisp.bitfield.disp64 = 1;
6713 else if ((flag_code == CODE_16BIT) ^ override)
6715 bigdisp.bitfield.disp32 = 0;
6716 bigdisp.bitfield.disp16 = 1;
6721 /* For PC-relative branches, the width of the displacement
6722 is dependent upon data size, not address size. */
6723 override = (i.prefix[DATA_PREFIX] != 0);
6724 if (flag_code == CODE_64BIT)
6726 if (override || i.suffix == WORD_MNEM_SUFFIX)
6727 bigdisp.bitfield.disp16 = 1;
6730 bigdisp.bitfield.disp32 = 1;
6731 bigdisp.bitfield.disp32s = 1;
6737 override = (i.suffix == (flag_code != CODE_16BIT
6739 : LONG_MNEM_SUFFIX));
6740 bigdisp.bitfield.disp32 = 1;
6741 if ((flag_code == CODE_16BIT) ^ override)
6743 bigdisp.bitfield.disp32 = 0;
6744 bigdisp.bitfield.disp16 = 1;
6748 i.types[this_operand] = operand_type_or (i.types[this_operand],
6751 exp = &disp_expressions[i.disp_operands];
6752 i.op[this_operand].disps = exp;
6754 save_input_line_pointer = input_line_pointer;
6755 input_line_pointer = disp_start;
6756 END_STRING_AND_SAVE (disp_end);
6758 #ifndef GCC_ASM_O_HACK
6759 #define GCC_ASM_O_HACK 0
6762 END_STRING_AND_SAVE (disp_end + 1);
6763 if (i.types[this_operand].bitfield.baseIndex
6764 && displacement_string_end[-1] == '+')
6766 /* This hack is to avoid a warning when using the "o"
6767 constraint within gcc asm statements.
6770 #define _set_tssldt_desc(n,addr,limit,type) \
6771 __asm__ __volatile__ ( \
6773 "movw %w1,2+%0\n\t" \
6775 "movb %b1,4+%0\n\t" \
6776 "movb %4,5+%0\n\t" \
6777 "movb $0,6+%0\n\t" \
6778 "movb %h1,7+%0\n\t" \
6780 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6782 This works great except that the output assembler ends
6783 up looking a bit weird if it turns out that there is
6784 no offset. You end up producing code that looks like:
6797 So here we provide the missing zero. */
6799 *displacement_string_end = '0';
6802 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6803 if (gotfree_input_line)
6804 input_line_pointer = gotfree_input_line;
6806 exp_seg = expression (exp);
6809 if (*input_line_pointer)
6810 as_bad (_("junk `%s' after expression"), input_line_pointer);
6812 RESTORE_END_STRING (disp_end + 1);
6814 input_line_pointer = save_input_line_pointer;
6815 if (gotfree_input_line)
6816 free (gotfree_input_line);
6819 /* We do this to make sure that the section symbol is in
6820 the symbol table. We will ultimately change the relocation
6821 to be relative to the beginning of the section. */
6822 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6823 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6824 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6826 if (exp->X_op != O_symbol)
6829 if (S_IS_LOCAL (exp->X_add_symbol)
6830 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6831 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6832 exp->X_op = O_subtract;
6833 exp->X_op_symbol = GOT_symbol;
6834 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6835 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6836 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6837 i.reloc[this_operand] = BFD_RELOC_64;
6839 i.reloc[this_operand] = BFD_RELOC_32;
6842 else if (exp->X_op == O_absent
6843 || exp->X_op == O_illegal
6844 || exp->X_op == O_big
6845 || (gotfree_input_line
6846 && (exp->X_op == O_constant
6847 || exp->X_op == O_register)))
6850 as_bad (_("missing or invalid displacement expression `%s'"),
6855 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6856 else if (exp->X_op != O_constant
6857 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6858 && exp_seg != absolute_section
6859 && exp_seg != text_section
6860 && exp_seg != data_section
6861 && exp_seg != bss_section
6862 && exp_seg != undefined_section
6863 && !bfd_is_com_section (exp_seg))
6865 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6870 RESTORE_END_STRING (disp_end);
6872 /* Check if this is a displacement only operand. */
6873 bigdisp = i.types[this_operand];
6874 bigdisp.bitfield.disp8 = 0;
6875 bigdisp.bitfield.disp16 = 0;
6876 bigdisp.bitfield.disp32 = 0;
6877 bigdisp.bitfield.disp32s = 0;
6878 bigdisp.bitfield.disp64 = 0;
6879 if (operand_type_all_zero (&bigdisp))
6880 i.types[this_operand] = operand_type_and (i.types[this_operand],
6886 /* Make sure the memory operand we've been dealt is valid.
6887 Return 1 on success, 0 on a failure. */
6890 i386_index_check (const char *operand_string)
6893 #if INFER_ADDR_PREFIX
6899 if (flag_code == CODE_64BIT)
6902 && ((i.prefix[ADDR_PREFIX] == 0
6903 && !i.base_reg->reg_type.bitfield.reg64)
6904 || (i.prefix[ADDR_PREFIX]
6905 && !i.base_reg->reg_type.bitfield.reg32))
6907 || i.base_reg->reg_num !=
6908 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6910 && (!i.index_reg->reg_type.bitfield.baseindex
6911 || (i.prefix[ADDR_PREFIX] == 0
6912 && i.index_reg->reg_num != RegRiz
6913 && !i.index_reg->reg_type.bitfield.reg64
6915 || (i.prefix[ADDR_PREFIX]
6916 && i.index_reg->reg_num != RegEiz
6917 && !i.index_reg->reg_type.bitfield.reg32))))
6922 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6926 && (!i.base_reg->reg_type.bitfield.reg16
6927 || !i.base_reg->reg_type.bitfield.baseindex))
6929 && (!i.index_reg->reg_type.bitfield.reg16
6930 || !i.index_reg->reg_type.bitfield.baseindex
6932 && i.base_reg->reg_num < 6
6933 && i.index_reg->reg_num >= 6
6934 && i.log2_scale_factor == 0))))
6941 && !i.base_reg->reg_type.bitfield.reg32)
6943 && ((!i.index_reg->reg_type.bitfield.reg32
6944 && i.index_reg->reg_num != RegEiz)
6945 || !i.index_reg->reg_type.bitfield.baseindex)))
6951 #if INFER_ADDR_PREFIX
6952 if (i.prefix[ADDR_PREFIX] == 0)
6954 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6956 /* Change the size of any displacement too. At most one of
6957 Disp16 or Disp32 is set.
6958 FIXME. There doesn't seem to be any real need for separate
6959 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6960 Removing them would probably clean up the code quite a lot. */
6961 if (flag_code != CODE_64BIT
6962 && (i.types[this_operand].bitfield.disp16
6963 || i.types[this_operand].bitfield.disp32))
6964 i.types[this_operand]
6965 = operand_type_xor (i.types[this_operand], disp16_32);
6970 as_bad (_("`%s' is not a valid base/index expression"),
6974 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6976 flag_code_names[flag_code]);
6981 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
6985 i386_att_operand (char *operand_string)
6989 char *op_string = operand_string;
6991 if (is_space_char (*op_string))
6994 /* We check for an absolute prefix (differentiating,
6995 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6996 if (*op_string == ABSOLUTE_PREFIX)
6999 if (is_space_char (*op_string))
7001 i.types[this_operand].bitfield.jumpabsolute = 1;
7004 /* Check if operand is a register. */
7005 if ((r = parse_register (op_string, &end_op)) != NULL)
7007 i386_operand_type temp;
7009 /* Check for a segment override by searching for ':' after a
7010 segment register. */
7012 if (is_space_char (*op_string))
7014 if (*op_string == ':'
7015 && (r->reg_type.bitfield.sreg2
7016 || r->reg_type.bitfield.sreg3))
7021 i.seg[i.mem_operands] = &es;
7024 i.seg[i.mem_operands] = &cs;
7027 i.seg[i.mem_operands] = &ss;
7030 i.seg[i.mem_operands] = &ds;
7033 i.seg[i.mem_operands] = &fs;
7036 i.seg[i.mem_operands] = &gs;
7040 /* Skip the ':' and whitespace. */
7042 if (is_space_char (*op_string))
7045 if (!is_digit_char (*op_string)
7046 && !is_identifier_char (*op_string)
7047 && *op_string != '('
7048 && *op_string != ABSOLUTE_PREFIX)
7050 as_bad (_("bad memory operand `%s'"), op_string);
7053 /* Handle case of %es:*foo. */
7054 if (*op_string == ABSOLUTE_PREFIX)
7057 if (is_space_char (*op_string))
7059 i.types[this_operand].bitfield.jumpabsolute = 1;
7061 goto do_memory_reference;
7065 as_bad (_("junk `%s' after register"), op_string);
7069 temp.bitfield.baseindex = 0;
7070 i.types[this_operand] = operand_type_or (i.types[this_operand],
7072 i.types[this_operand].bitfield.unspecified = 0;
7073 i.op[this_operand].regs = r;
7076 else if (*op_string == REGISTER_PREFIX)
7078 as_bad (_("bad register name `%s'"), op_string);
7081 else if (*op_string == IMMEDIATE_PREFIX)
7084 if (i.types[this_operand].bitfield.jumpabsolute)
7086 as_bad (_("immediate operand illegal with absolute jump"));
7089 if (!i386_immediate (op_string))
7092 else if (is_digit_char (*op_string)
7093 || is_identifier_char (*op_string)
7094 || *op_string == '(')
7096 /* This is a memory reference of some sort. */
7099 /* Start and end of displacement string expression (if found). */
7100 char *displacement_string_start;
7101 char *displacement_string_end;
7103 do_memory_reference:
7104 if ((i.mem_operands == 1
7105 && !current_templates->start->opcode_modifier.isstring)
7106 || i.mem_operands == 2)
7108 as_bad (_("too many memory references for `%s'"),
7109 current_templates->start->name);
7113 /* Check for base index form. We detect the base index form by
7114 looking for an ')' at the end of the operand, searching
7115 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7117 base_string = op_string + strlen (op_string);
7120 if (is_space_char (*base_string))
7123 /* If we only have a displacement, set-up for it to be parsed later. */
7124 displacement_string_start = op_string;
7125 displacement_string_end = base_string + 1;
7127 if (*base_string == ')')
7130 unsigned int parens_balanced = 1;
7131 /* We've already checked that the number of left & right ()'s are
7132 equal, so this loop will not be infinite. */
7136 if (*base_string == ')')
7138 if (*base_string == '(')
7141 while (parens_balanced);
7143 temp_string = base_string;
7145 /* Skip past '(' and whitespace. */
7147 if (is_space_char (*base_string))
7150 if (*base_string == ','
7151 || ((i.base_reg = parse_register (base_string, &end_op))
7154 displacement_string_end = temp_string;
7156 i.types[this_operand].bitfield.baseindex = 1;
7160 base_string = end_op;
7161 if (is_space_char (*base_string))
7165 /* There may be an index reg or scale factor here. */
7166 if (*base_string == ',')
7169 if (is_space_char (*base_string))
7172 if ((i.index_reg = parse_register (base_string, &end_op))
7175 base_string = end_op;
7176 if (is_space_char (*base_string))
7178 if (*base_string == ',')
7181 if (is_space_char (*base_string))
7184 else if (*base_string != ')')
7186 as_bad (_("expecting `,' or `)' "
7187 "after index register in `%s'"),
7192 else if (*base_string == REGISTER_PREFIX)
7194 as_bad (_("bad register name `%s'"), base_string);
7198 /* Check for scale factor. */
7199 if (*base_string != ')')
7201 char *end_scale = i386_scale (base_string);
7206 base_string = end_scale;
7207 if (is_space_char (*base_string))
7209 if (*base_string != ')')
7211 as_bad (_("expecting `)' "
7212 "after scale factor in `%s'"),
7217 else if (!i.index_reg)
7219 as_bad (_("expecting index register or scale factor "
7220 "after `,'; got '%c'"),
7225 else if (*base_string != ')')
7227 as_bad (_("expecting `,' or `)' "
7228 "after base register in `%s'"),
7233 else if (*base_string == REGISTER_PREFIX)
7235 as_bad (_("bad register name `%s'"), base_string);
7240 /* If there's an expression beginning the operand, parse it,
7241 assuming displacement_string_start and
7242 displacement_string_end are meaningful. */
7243 if (displacement_string_start != displacement_string_end)
7245 if (!i386_displacement (displacement_string_start,
7246 displacement_string_end))
7250 /* Special case for (%dx) while doing input/output op. */
7252 && operand_type_equal (&i.base_reg->reg_type,
7253 ®16_inoutportreg)
7255 && i.log2_scale_factor == 0
7256 && i.seg[i.mem_operands] == 0
7257 && !operand_type_check (i.types[this_operand], disp))
7259 i.types[this_operand] = inoutportreg;
7263 if (i386_index_check (operand_string) == 0)
7265 i.types[this_operand].bitfield.mem = 1;
7270 /* It's not a memory operand; argh! */
7271 as_bad (_("invalid char %s beginning operand %d `%s'"),
7272 output_invalid (*op_string),
7277 return 1; /* Normal return. */
7280 /* md_estimate_size_before_relax()
7282 Called just before relax() for rs_machine_dependent frags. The x86
7283 assembler uses these frags to handle variable size jump
7286 Any symbol that is now undefined will not become defined.
7287 Return the correct fr_subtype in the frag.
7288 Return the initial "guess for variable size of frag" to caller.
7289 The guess is actually the growth beyond the fixed part. Whatever
7290 we do to grow the fixed or variable part contributes to our
7294 md_estimate_size_before_relax (fragP, segment)
7298 /* We've already got fragP->fr_subtype right; all we have to do is
7299 check for un-relaxable symbols. On an ELF system, we can't relax
7300 an externally visible symbol, because it may be overridden by a
7302 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
7303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7305 && (S_IS_EXTERNAL (fragP->fr_symbol)
7306 || S_IS_WEAK (fragP->fr_symbol)))
7310 /* Symbol is undefined in this segment, or we need to keep a
7311 reloc so that weak symbols can be overridden. */
7312 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
7313 enum bfd_reloc_code_real reloc_type;
7314 unsigned char *opcode;
7317 if (fragP->fr_var != NO_RELOC)
7318 reloc_type = fragP->fr_var;
7320 reloc_type = BFD_RELOC_16_PCREL;
7322 reloc_type = BFD_RELOC_32_PCREL;
7324 old_fr_fix = fragP->fr_fix;
7325 opcode = (unsigned char *) fragP->fr_opcode;
7327 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
7330 /* Make jmp (0xeb) a (d)word displacement jump. */
7332 fragP->fr_fix += size;
7333 fix_new (fragP, old_fr_fix, size,
7335 fragP->fr_offset, 1,
7341 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
7343 /* Negate the condition, and branch past an
7344 unconditional jump. */
7347 /* Insert an unconditional jump. */
7349 /* We added two extra opcode bytes, and have a two byte
7351 fragP->fr_fix += 2 + 2;
7352 fix_new (fragP, old_fr_fix + 2, 2,
7354 fragP->fr_offset, 1,
7361 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7366 fixP = fix_new (fragP, old_fr_fix, 1,
7368 fragP->fr_offset, 1,
7370 fixP->fx_signed = 1;
7374 /* This changes the byte-displacement jump 0x7N
7375 to the (d)word-displacement jump 0x0f,0x8N. */
7376 opcode[1] = opcode[0] + 0x10;
7377 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7378 /* We've added an opcode byte. */
7379 fragP->fr_fix += 1 + size;
7380 fix_new (fragP, old_fr_fix + 1, size,
7382 fragP->fr_offset, 1,
7387 BAD_CASE (fragP->fr_subtype);
7391 return fragP->fr_fix - old_fr_fix;
7394 /* Guess size depending on current relax state. Initially the relax
7395 state will correspond to a short jump and we return 1, because
7396 the variable part of the frag (the branch offset) is one byte
7397 long. However, we can relax a section more than once and in that
7398 case we must either set fr_subtype back to the unrelaxed state,
7399 or return the value for the appropriate branch. */
7400 return md_relax_table[fragP->fr_subtype].rlx_length;
7403 /* Called after relax() is finished.
7405 In: Address of frag.
7406 fr_type == rs_machine_dependent.
7407 fr_subtype is what the address relaxed to.
7409 Out: Any fixSs and constants are set up.
7410 Caller will turn frag into a ".space 0". */
7413 md_convert_frag (abfd, sec, fragP)
7414 bfd *abfd ATTRIBUTE_UNUSED;
7415 segT sec ATTRIBUTE_UNUSED;
7418 unsigned char *opcode;
7419 unsigned char *where_to_put_displacement = NULL;
7420 offsetT target_address;
7421 offsetT opcode_address;
7422 unsigned int extension = 0;
7423 offsetT displacement_from_opcode_start;
7425 opcode = (unsigned char *) fragP->fr_opcode;
7427 /* Address we want to reach in file space. */
7428 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
7430 /* Address opcode resides at in file space. */
7431 opcode_address = fragP->fr_address + fragP->fr_fix;
7433 /* Displacement from opcode start to fill into instruction. */
7434 displacement_from_opcode_start = target_address - opcode_address;
7436 if ((fragP->fr_subtype & BIG) == 0)
7438 /* Don't have to change opcode. */
7439 extension = 1; /* 1 opcode + 1 displacement */
7440 where_to_put_displacement = &opcode[1];
7444 if (no_cond_jump_promotion
7445 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
7446 as_warn_where (fragP->fr_file, fragP->fr_line,
7447 _("long jump required"));
7449 switch (fragP->fr_subtype)
7451 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7452 extension = 4; /* 1 opcode + 4 displacement */
7454 where_to_put_displacement = &opcode[1];
7457 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7458 extension = 2; /* 1 opcode + 2 displacement */
7460 where_to_put_displacement = &opcode[1];
7463 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7464 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7465 extension = 5; /* 2 opcode + 4 displacement */
7466 opcode[1] = opcode[0] + 0x10;
7467 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7468 where_to_put_displacement = &opcode[2];
7471 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7472 extension = 3; /* 2 opcode + 2 displacement */
7473 opcode[1] = opcode[0] + 0x10;
7474 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7475 where_to_put_displacement = &opcode[2];
7478 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7483 where_to_put_displacement = &opcode[3];
7487 BAD_CASE (fragP->fr_subtype);
7492 /* If size if less then four we are sure that the operand fits,
7493 but if it's 4, then it could be that the displacement is larger
7495 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7497 && ((addressT) (displacement_from_opcode_start - extension
7498 + ((addressT) 1 << 31))
7499 > (((addressT) 2 << 31) - 1)))
7501 as_bad_where (fragP->fr_file, fragP->fr_line,
7502 _("jump target out of range"));
7503 /* Make us emit 0. */
7504 displacement_from_opcode_start = extension;
7506 /* Now put displacement after opcode. */
7507 md_number_to_chars ((char *) where_to_put_displacement,
7508 (valueT) (displacement_from_opcode_start - extension),
7509 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
7510 fragP->fr_fix += extension;
7513 /* Apply a fixup (fixS) to segment data, once it has been determined
7514 by our caller that we have all the info we need to fix it up.
7516 On the 386, immediates, displacements, and data pointers are all in
7517 the same (little-endian) format, so we don't need to care about which
7521 md_apply_fix (fixP, valP, seg)
7522 /* The fix we're to put in. */
7524 /* Pointer to the value of the bits. */
7526 /* Segment fix is from. */
7527 segT seg ATTRIBUTE_UNUSED;
7529 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
7530 valueT value = *valP;
7532 #if !defined (TE_Mach)
7535 switch (fixP->fx_r_type)
7541 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7544 case BFD_RELOC_X86_64_32S:
7545 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7548 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7551 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7556 if (fixP->fx_addsy != NULL
7557 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
7558 || fixP->fx_r_type == BFD_RELOC_64_PCREL
7559 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7560 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7561 && !use_rela_relocations)
7563 /* This is a hack. There should be a better way to handle this.
7564 This covers for the fact that bfd_install_relocation will
7565 subtract the current location (for partial_inplace, PC relative
7566 relocations); see more below. */
7570 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7573 value += fixP->fx_where + fixP->fx_frag->fr_address;
7575 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7578 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
7581 || (symbol_section_p (fixP->fx_addsy)
7582 && sym_seg != absolute_section))
7583 && !generic_force_reloc (fixP))
7585 /* Yes, we add the values in twice. This is because
7586 bfd_install_relocation subtracts them out again. I think
7587 bfd_install_relocation is broken, but I don't dare change
7589 value += fixP->fx_where + fixP->fx_frag->fr_address;
7593 #if defined (OBJ_COFF) && defined (TE_PE)
7594 /* For some reason, the PE format does not store a
7595 section address offset for a PC relative symbol. */
7596 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7597 || S_IS_WEAK (fixP->fx_addsy))
7598 value += md_pcrel_from (fixP);
7602 /* Fix a few things - the dynamic linker expects certain values here,
7603 and we must not disappoint it. */
7604 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7605 if (IS_ELF && fixP->fx_addsy)
7606 switch (fixP->fx_r_type)
7608 case BFD_RELOC_386_PLT32:
7609 case BFD_RELOC_X86_64_PLT32:
7610 /* Make the jump instruction point to the address of the operand. At
7611 runtime we merely add the offset to the actual PLT entry. */
7615 case BFD_RELOC_386_TLS_GD:
7616 case BFD_RELOC_386_TLS_LDM:
7617 case BFD_RELOC_386_TLS_IE_32:
7618 case BFD_RELOC_386_TLS_IE:
7619 case BFD_RELOC_386_TLS_GOTIE:
7620 case BFD_RELOC_386_TLS_GOTDESC:
7621 case BFD_RELOC_X86_64_TLSGD:
7622 case BFD_RELOC_X86_64_TLSLD:
7623 case BFD_RELOC_X86_64_GOTTPOFF:
7624 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7625 value = 0; /* Fully resolved at runtime. No addend. */
7627 case BFD_RELOC_386_TLS_LE:
7628 case BFD_RELOC_386_TLS_LDO_32:
7629 case BFD_RELOC_386_TLS_LE_32:
7630 case BFD_RELOC_X86_64_DTPOFF32:
7631 case BFD_RELOC_X86_64_DTPOFF64:
7632 case BFD_RELOC_X86_64_TPOFF32:
7633 case BFD_RELOC_X86_64_TPOFF64:
7634 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7637 case BFD_RELOC_386_TLS_DESC_CALL:
7638 case BFD_RELOC_X86_64_TLSDESC_CALL:
7639 value = 0; /* Fully resolved at runtime. No addend. */
7640 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7644 case BFD_RELOC_386_GOT32:
7645 case BFD_RELOC_X86_64_GOT32:
7646 value = 0; /* Fully resolved at runtime. No addend. */
7649 case BFD_RELOC_VTABLE_INHERIT:
7650 case BFD_RELOC_VTABLE_ENTRY:
7657 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7659 #endif /* !defined (TE_Mach) */
7661 /* Are we finished with this relocation now? */
7662 if (fixP->fx_addsy == NULL)
7664 else if (use_rela_relocations)
7666 fixP->fx_no_overflow = 1;
7667 /* Remember value for tc_gen_reloc. */
7668 fixP->fx_addnumber = value;
7672 md_number_to_chars (p, value, fixP->fx_size);
7676 md_atof (int type, char *litP, int *sizeP)
7678 /* This outputs the LITTLENUMs in REVERSE order;
7679 in accord with the bigendian 386. */
7680 return ieee_md_atof (type, litP, sizeP, FALSE);
7683 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7686 output_invalid (int c)
7689 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7692 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7693 "(0x%x)", (unsigned char) c);
7694 return output_invalid_buf;
7697 /* REG_STRING starts *before* REGISTER_PREFIX. */
7699 static const reg_entry *
7700 parse_real_register (char *reg_string, char **end_op)
7702 char *s = reg_string;
7704 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7707 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7708 if (*s == REGISTER_PREFIX)
7711 if (is_space_char (*s))
7715 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7717 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7718 return (const reg_entry *) NULL;
7722 /* For naked regs, make sure that we are not dealing with an identifier.
7723 This prevents confusing an identifier like `eax_var' with register
7725 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7726 return (const reg_entry *) NULL;
7730 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7732 /* Handle floating point regs, allowing spaces in the (i) part. */
7733 if (r == i386_regtab /* %st is first entry of table */)
7735 if (is_space_char (*s))
7740 if (is_space_char (*s))
7742 if (*s >= '0' && *s <= '7')
7746 if (is_space_char (*s))
7751 r = hash_find (reg_hash, "st(0)");
7756 /* We have "%st(" then garbage. */
7757 return (const reg_entry *) NULL;
7761 if (r == NULL || allow_pseudo_reg)
7764 if (operand_type_all_zero (&r->reg_type))
7765 return (const reg_entry *) NULL;
7767 if ((r->reg_type.bitfield.reg32
7768 || r->reg_type.bitfield.sreg3
7769 || r->reg_type.bitfield.control
7770 || r->reg_type.bitfield.debug
7771 || r->reg_type.bitfield.test)
7772 && !cpu_arch_flags.bitfield.cpui386)
7773 return (const reg_entry *) NULL;
7775 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7776 return (const reg_entry *) NULL;
7778 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7779 return (const reg_entry *) NULL;
7781 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7782 return (const reg_entry *) NULL;
7784 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7785 if (!allow_index_reg
7786 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7787 return (const reg_entry *) NULL;
7789 if (((r->reg_flags & (RegRex64 | RegRex))
7790 || r->reg_type.bitfield.reg64)
7791 && (!cpu_arch_flags.bitfield.cpulm
7792 || !operand_type_equal (&r->reg_type, &control))
7793 && flag_code != CODE_64BIT)
7794 return (const reg_entry *) NULL;
7796 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7797 return (const reg_entry *) NULL;
7802 /* REG_STRING starts *before* REGISTER_PREFIX. */
7804 static const reg_entry *
7805 parse_register (char *reg_string, char **end_op)
7809 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7810 r = parse_real_register (reg_string, end_op);
7815 char *save = input_line_pointer;
7819 input_line_pointer = reg_string;
7820 c = get_symbol_end ();
7821 symbolP = symbol_find (reg_string);
7822 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7824 const expressionS *e = symbol_get_value_expression (symbolP);
7826 know (e->X_op == O_register);
7827 know (e->X_add_number >= 0
7828 && (valueT) e->X_add_number < i386_regtab_size);
7829 r = i386_regtab + e->X_add_number;
7830 *end_op = input_line_pointer;
7832 *input_line_pointer = c;
7833 input_line_pointer = save;
7839 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7842 char *end = input_line_pointer;
7845 r = parse_register (name, &input_line_pointer);
7846 if (r && end <= input_line_pointer)
7848 *nextcharP = *input_line_pointer;
7849 *input_line_pointer = 0;
7850 e->X_op = O_register;
7851 e->X_add_number = r - i386_regtab;
7854 input_line_pointer = end;
7860 md_operand (expressionS *e)
7862 if (*input_line_pointer == REGISTER_PREFIX)
7865 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7869 e->X_op = O_register;
7870 e->X_add_number = r - i386_regtab;
7871 input_line_pointer = end;
7877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7878 const char *md_shortopts = "kVQ:sqn";
7880 const char *md_shortopts = "qn";
7883 #define OPTION_32 (OPTION_MD_BASE + 0)
7884 #define OPTION_64 (OPTION_MD_BASE + 1)
7885 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7886 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7887 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7888 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7889 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7890 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7891 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7892 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7893 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7894 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7896 struct option md_longopts[] =
7898 {"32", no_argument, NULL, OPTION_32},
7899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7900 {"64", no_argument, NULL, OPTION_64},
7902 {"divide", no_argument, NULL, OPTION_DIVIDE},
7903 {"march", required_argument, NULL, OPTION_MARCH},
7904 {"mtune", required_argument, NULL, OPTION_MTUNE},
7905 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7906 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7907 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7908 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7909 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7910 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
7911 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7912 {NULL, no_argument, NULL, 0}
7914 size_t md_longopts_size = sizeof (md_longopts);
7917 md_parse_option (int c, char *arg)
7925 optimize_align_code = 0;
7932 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7933 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7934 should be emitted or not. FIXME: Not implemented. */
7938 /* -V: SVR4 argument to print version ID. */
7940 print_version_id ();
7943 /* -k: Ignore for FreeBSD compatibility. */
7948 /* -s: On i386 Solaris, this tells the native assembler to use
7949 .stab instead of .stab.excl. We always use .stab anyhow. */
7952 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7955 const char **list, **l;
7957 list = bfd_target_list ();
7958 for (l = list; *l != NULL; l++)
7959 if (CONST_STRNEQ (*l, "elf64-x86-64")
7960 || strcmp (*l, "coff-x86-64") == 0
7961 || strcmp (*l, "pe-x86-64") == 0
7962 || strcmp (*l, "pei-x86-64") == 0)
7964 default_arch = "x86_64";
7968 as_fatal (_("No compiled in support for x86_64"));
7975 default_arch = "i386";
7979 #ifdef SVR4_COMMENT_CHARS
7984 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7986 for (s = i386_comment_chars; *s != '\0'; s++)
7990 i386_comment_chars = n;
7996 arch = xstrdup (arg);
8000 as_fatal (_("Invalid -march= option: `%s'"), arg);
8001 next = strchr (arch, '+');
8004 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8006 if (strcmp (arch, cpu_arch [i].name) == 0)
8009 cpu_arch_name = cpu_arch[i].name;
8010 cpu_sub_arch_name = NULL;
8011 cpu_arch_flags = cpu_arch[i].flags;
8012 cpu_arch_isa = cpu_arch[i].type;
8013 cpu_arch_isa_flags = cpu_arch[i].flags;
8014 if (!cpu_arch_tune_set)
8016 cpu_arch_tune = cpu_arch_isa;
8017 cpu_arch_tune_flags = cpu_arch_isa_flags;
8021 else if (*cpu_arch [i].name == '.'
8022 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8024 /* ISA entension. */
8025 i386_cpu_flags flags;
8026 flags = cpu_flags_or (cpu_arch_flags,
8028 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
8030 if (cpu_sub_arch_name)
8032 char *name = cpu_sub_arch_name;
8033 cpu_sub_arch_name = concat (name,
8035 (const char *) NULL);
8039 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8040 cpu_arch_flags = flags;
8046 if (i >= ARRAY_SIZE (cpu_arch))
8047 as_fatal (_("Invalid -march= option: `%s'"), arg);
8051 while (next != NULL );
8056 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8057 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8059 if (strcmp (arg, cpu_arch [i].name) == 0)
8061 cpu_arch_tune_set = 1;
8062 cpu_arch_tune = cpu_arch [i].type;
8063 cpu_arch_tune_flags = cpu_arch[i].flags;
8067 if (i >= ARRAY_SIZE (cpu_arch))
8068 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8071 case OPTION_MMNEMONIC:
8072 if (strcasecmp (arg, "att") == 0)
8074 else if (strcasecmp (arg, "intel") == 0)
8077 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8080 case OPTION_MSYNTAX:
8081 if (strcasecmp (arg, "att") == 0)
8083 else if (strcasecmp (arg, "intel") == 0)
8086 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8089 case OPTION_MINDEX_REG:
8090 allow_index_reg = 1;
8093 case OPTION_MNAKED_REG:
8094 allow_naked_reg = 1;
8097 case OPTION_MOLD_GCC:
8101 case OPTION_MSSE2AVX:
8105 case OPTION_MSSE_CHECK:
8106 if (strcasecmp (arg, "error") == 0)
8107 sse_check = sse_check_error;
8108 else if (strcasecmp (arg, "warning") == 0)
8109 sse_check = sse_check_warning;
8110 else if (strcasecmp (arg, "none") == 0)
8111 sse_check = sse_check_none;
8113 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8123 md_show_usage (stream)
8126 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8127 fprintf (stream, _("\
8129 -V print assembler version number\n\
8132 fprintf (stream, _("\
8133 -n Do not optimize code alignment\n\
8134 -q quieten some warnings\n"));
8135 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8136 fprintf (stream, _("\
8139 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8140 fprintf (stream, _("\
8141 --32/--64 generate 32bit/64bit code\n"));
8143 #ifdef SVR4_COMMENT_CHARS
8144 fprintf (stream, _("\
8145 --divide do not treat `/' as a comment character\n"));
8147 fprintf (stream, _("\
8148 --divide ignored\n"));
8150 fprintf (stream, _("\
8151 -march=CPU[,+EXTENSION...]\n\
8152 generate code for CPU and EXTENSION, CPU is one of:\n\
8153 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8154 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8155 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8156 generic32, generic64\n\
8157 EXTENSION is combination of:\n\
8158 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8159 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8160 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
8161 fprintf (stream, _("\
8162 -mtune=CPU optimize for CPU, CPU is one of:\n\
8163 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8164 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8165 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8166 generic32, generic64\n"));
8167 fprintf (stream, _("\
8168 -msse2avx encode SSE instructions with VEX prefix\n"));
8169 fprintf (stream, _("\
8170 -msse-check=[none|error|warning]\n\
8171 check SSE instructions\n"));
8172 fprintf (stream, _("\
8173 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8174 fprintf (stream, _("\
8175 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8176 fprintf (stream, _("\
8177 -mindex-reg support pseudo index registers\n"));
8178 fprintf (stream, _("\
8179 -mnaked-reg don't require `%%' prefix for registers\n"));
8180 fprintf (stream, _("\
8181 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8184 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8185 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8187 /* Pick the target format to use. */
8190 i386_target_format (void)
8192 if (!strcmp (default_arch, "x86_64"))
8194 set_code_flag (CODE_64BIT);
8195 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8197 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8198 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8199 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8200 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8201 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8202 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8203 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8204 cpu_arch_isa_flags.bitfield.cpummx= 1;
8205 cpu_arch_isa_flags.bitfield.cpusse = 1;
8206 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8208 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8210 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8211 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8212 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8213 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8214 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8215 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8216 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8217 cpu_arch_tune_flags.bitfield.cpummx= 1;
8218 cpu_arch_tune_flags.bitfield.cpusse = 1;
8219 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8222 else if (!strcmp (default_arch, "i386"))
8224 set_code_flag (CODE_32BIT);
8225 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8227 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8228 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8229 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8231 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8233 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8234 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8235 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8239 as_fatal (_("Unknown architecture"));
8240 switch (OUTPUT_FLAVOR)
8243 case bfd_target_coff_flavour:
8244 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8247 #ifdef OBJ_MAYBE_AOUT
8248 case bfd_target_aout_flavour:
8249 return AOUT_TARGET_FORMAT;
8251 #ifdef OBJ_MAYBE_COFF
8252 case bfd_target_coff_flavour:
8255 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8256 case bfd_target_elf_flavour:
8258 if (flag_code == CODE_64BIT)
8261 use_rela_relocations = 1;
8263 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
8272 #endif /* OBJ_MAYBE_ more than one */
8274 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8276 i386_elf_emit_arch_note (void)
8278 if (IS_ELF && cpu_arch_name != NULL)
8281 asection *seg = now_seg;
8282 subsegT subseg = now_subseg;
8283 Elf_Internal_Note i_note;
8284 Elf_External_Note e_note;
8285 asection *note_secp;
8288 /* Create the .note section. */
8289 note_secp = subseg_new (".note", 0);
8290 bfd_set_section_flags (stdoutput,
8292 SEC_HAS_CONTENTS | SEC_READONLY);
8294 /* Process the arch string. */
8295 len = strlen (cpu_arch_name);
8297 i_note.namesz = len + 1;
8299 i_note.type = NT_ARCH;
8300 p = frag_more (sizeof (e_note.namesz));
8301 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8302 p = frag_more (sizeof (e_note.descsz));
8303 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8304 p = frag_more (sizeof (e_note.type));
8305 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8306 p = frag_more (len + 1);
8307 strcpy (p, cpu_arch_name);
8309 frag_align (2, 0, 0);
8311 subseg_set (seg, subseg);
8317 md_undefined_symbol (name)
8320 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8321 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8322 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8323 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
8327 if (symbol_find (name))
8328 as_bad (_("GOT already in symbol table"));
8329 GOT_symbol = symbol_new (name, undefined_section,
8330 (valueT) 0, &zero_address_frag);
8337 /* Round up a section size to the appropriate boundary. */
8340 md_section_align (segment, size)
8341 segT segment ATTRIBUTE_UNUSED;
8344 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8345 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8347 /* For a.out, force the section size to be aligned. If we don't do
8348 this, BFD will align it for us, but it will not write out the
8349 final bytes of the section. This may be a bug in BFD, but it is
8350 easier to fix it here since that is how the other a.out targets
8354 align = bfd_get_section_alignment (stdoutput, segment);
8355 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8362 /* On the i386, PC-relative offsets are relative to the start of the
8363 next instruction. That is, the address of the offset, plus its
8364 size, since the offset is always the last part of the insn. */
8367 md_pcrel_from (fixS *fixP)
8369 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8375 s_bss (int ignore ATTRIBUTE_UNUSED)
8379 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8381 obj_elf_section_change_hook ();
8383 temp = get_absolute_expression ();
8384 subseg_set (bss_section, (subsegT) temp);
8385 demand_empty_rest_of_line ();
8391 i386_validate_fix (fixS *fixp)
8393 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8395 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8399 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8404 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8406 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
8413 tc_gen_reloc (section, fixp)
8414 asection *section ATTRIBUTE_UNUSED;
8418 bfd_reloc_code_real_type code;
8420 switch (fixp->fx_r_type)
8422 case BFD_RELOC_X86_64_PLT32:
8423 case BFD_RELOC_X86_64_GOT32:
8424 case BFD_RELOC_X86_64_GOTPCREL:
8425 case BFD_RELOC_386_PLT32:
8426 case BFD_RELOC_386_GOT32:
8427 case BFD_RELOC_386_GOTOFF:
8428 case BFD_RELOC_386_GOTPC:
8429 case BFD_RELOC_386_TLS_GD:
8430 case BFD_RELOC_386_TLS_LDM:
8431 case BFD_RELOC_386_TLS_LDO_32:
8432 case BFD_RELOC_386_TLS_IE_32:
8433 case BFD_RELOC_386_TLS_IE:
8434 case BFD_RELOC_386_TLS_GOTIE:
8435 case BFD_RELOC_386_TLS_LE_32:
8436 case BFD_RELOC_386_TLS_LE:
8437 case BFD_RELOC_386_TLS_GOTDESC:
8438 case BFD_RELOC_386_TLS_DESC_CALL:
8439 case BFD_RELOC_X86_64_TLSGD:
8440 case BFD_RELOC_X86_64_TLSLD:
8441 case BFD_RELOC_X86_64_DTPOFF32:
8442 case BFD_RELOC_X86_64_DTPOFF64:
8443 case BFD_RELOC_X86_64_GOTTPOFF:
8444 case BFD_RELOC_X86_64_TPOFF32:
8445 case BFD_RELOC_X86_64_TPOFF64:
8446 case BFD_RELOC_X86_64_GOTOFF64:
8447 case BFD_RELOC_X86_64_GOTPC32:
8448 case BFD_RELOC_X86_64_GOT64:
8449 case BFD_RELOC_X86_64_GOTPCREL64:
8450 case BFD_RELOC_X86_64_GOTPC64:
8451 case BFD_RELOC_X86_64_GOTPLT64:
8452 case BFD_RELOC_X86_64_PLTOFF64:
8453 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8454 case BFD_RELOC_X86_64_TLSDESC_CALL:
8456 case BFD_RELOC_VTABLE_ENTRY:
8457 case BFD_RELOC_VTABLE_INHERIT:
8459 case BFD_RELOC_32_SECREL:
8461 code = fixp->fx_r_type;
8463 case BFD_RELOC_X86_64_32S:
8464 if (!fixp->fx_pcrel)
8466 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8467 code = fixp->fx_r_type;
8473 switch (fixp->fx_size)
8476 as_bad_where (fixp->fx_file, fixp->fx_line,
8477 _("can not do %d byte pc-relative relocation"),
8479 code = BFD_RELOC_32_PCREL;
8481 case 1: code = BFD_RELOC_8_PCREL; break;
8482 case 2: code = BFD_RELOC_16_PCREL; break;
8483 case 4: code = BFD_RELOC_32_PCREL; break;
8485 case 8: code = BFD_RELOC_64_PCREL; break;
8491 switch (fixp->fx_size)
8494 as_bad_where (fixp->fx_file, fixp->fx_line,
8495 _("can not do %d byte relocation"),
8497 code = BFD_RELOC_32;
8499 case 1: code = BFD_RELOC_8; break;
8500 case 2: code = BFD_RELOC_16; break;
8501 case 4: code = BFD_RELOC_32; break;
8503 case 8: code = BFD_RELOC_64; break;
8510 if ((code == BFD_RELOC_32
8511 || code == BFD_RELOC_32_PCREL
8512 || code == BFD_RELOC_X86_64_32S)
8514 && fixp->fx_addsy == GOT_symbol)
8517 code = BFD_RELOC_386_GOTPC;
8519 code = BFD_RELOC_X86_64_GOTPC32;
8521 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8523 && fixp->fx_addsy == GOT_symbol)
8525 code = BFD_RELOC_X86_64_GOTPC64;
8528 rel = (arelent *) xmalloc (sizeof (arelent));
8529 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8530 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8532 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
8534 if (!use_rela_relocations)
8536 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8537 vtable entry to be used in the relocation's section offset. */
8538 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8539 rel->address = fixp->fx_offset;
8543 /* Use the rela in 64bit mode. */
8546 if (!fixp->fx_pcrel)
8547 rel->addend = fixp->fx_offset;
8551 case BFD_RELOC_X86_64_PLT32:
8552 case BFD_RELOC_X86_64_GOT32:
8553 case BFD_RELOC_X86_64_GOTPCREL:
8554 case BFD_RELOC_X86_64_TLSGD:
8555 case BFD_RELOC_X86_64_TLSLD:
8556 case BFD_RELOC_X86_64_GOTTPOFF:
8557 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8558 case BFD_RELOC_X86_64_TLSDESC_CALL:
8559 rel->addend = fixp->fx_offset - fixp->fx_size;
8562 rel->addend = (section->vma
8564 + fixp->fx_addnumber
8565 + md_pcrel_from (fixp));
8570 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8571 if (rel->howto == NULL)
8573 as_bad_where (fixp->fx_file, fixp->fx_line,
8574 _("cannot represent relocation type %s"),
8575 bfd_get_reloc_code_name (code));
8576 /* Set howto to a garbage value so that we can keep going. */
8577 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8578 assert (rel->howto != NULL);
8585 /* Parse operands using Intel syntax. This implements a recursive descent
8586 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8589 FIXME: We do not recognize the full operand grammar defined in the MASM
8590 documentation. In particular, all the structure/union and
8591 high-level macro operands are missing.
8593 Uppercase words are terminals, lower case words are non-terminals.
8594 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8595 bars '|' denote choices. Most grammar productions are implemented in
8596 functions called 'intel_<production>'.
8598 Initial production is 'expr'.
8604 binOp & | AND | \| | OR | ^ | XOR
8606 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8608 constant digits [[ radixOverride ]]
8610 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8648 => expr expr cmpOp e04
8651 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8652 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8654 hexdigit a | b | c | d | e | f
8655 | A | B | C | D | E | F
8661 mulOp * | / | % | MOD | << | SHL | >> | SHR
8665 register specialRegister
8669 segmentRegister CS | DS | ES | FS | GS | SS
8671 specialRegister CR0 | CR2 | CR3 | CR4
8672 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8673 | TR3 | TR4 | TR5 | TR6 | TR7
8675 We simplify the grammar in obvious places (e.g., register parsing is
8676 done by calling parse_register) and eliminate immediate left recursion
8677 to implement a recursive-descent parser.
8681 expr' cmpOp e04 expr'
8733 /* Parsing structure for the intel syntax parser. Used to implement the
8734 semantic actions for the operand grammar. */
8735 struct intel_parser_s
8737 char *op_string; /* The string being parsed. */
8738 int got_a_float; /* Whether the operand is a float. */
8739 int op_modifier; /* Operand modifier. */
8740 int is_mem; /* 1 if operand is memory reference. */
8741 int in_offset; /* >=1 if parsing operand of offset. */
8742 int in_bracket; /* >=1 if parsing operand in brackets. */
8743 const reg_entry *reg; /* Last register reference found. */
8744 char *disp; /* Displacement string being built. */
8745 char *next_operand; /* Resume point when splitting operands. */
8748 static struct intel_parser_s intel_parser;
8750 /* Token structure for parsing intel syntax. */
8753 int code; /* Token code. */
8754 const reg_entry *reg; /* Register entry for register tokens. */
8755 char *str; /* String representation. */
8758 static struct intel_token cur_token, prev_token;
8760 /* Token codes for the intel parser. Since T_SHORT is already used
8761 by COFF, undefine it first to prevent a warning. */
8779 #define T_YMMWORD 16
8781 /* Prototypes for intel parser functions. */
8782 static int intel_match_token (int);
8783 static void intel_putback_token (void);
8784 static void intel_get_token (void);
8785 static int intel_expr (void);
8786 static int intel_e04 (void);
8787 static int intel_e05 (void);
8788 static int intel_e06 (void);
8789 static int intel_e09 (void);
8790 static int intel_e10 (void);
8791 static int intel_e11 (void);
8794 i386_intel_operand (char *operand_string, int got_a_float)
8799 p = intel_parser.op_string = xstrdup (operand_string);
8800 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8804 /* Initialize token holders. */
8805 cur_token.code = prev_token.code = T_NIL;
8806 cur_token.reg = prev_token.reg = NULL;
8807 cur_token.str = prev_token.str = NULL;
8809 /* Initialize parser structure. */
8810 intel_parser.got_a_float = got_a_float;
8811 intel_parser.op_modifier = 0;
8812 intel_parser.is_mem = 0;
8813 intel_parser.in_offset = 0;
8814 intel_parser.in_bracket = 0;
8815 intel_parser.reg = NULL;
8816 intel_parser.disp[0] = '\0';
8817 intel_parser.next_operand = NULL;
8819 /* Read the first token and start the parser. */
8821 ret = intel_expr ();
8826 if (cur_token.code != T_NIL)
8828 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8829 current_templates->start->name, cur_token.str);
8832 /* If we found a memory reference, hand it over to i386_displacement
8833 to fill in the rest of the operand fields. */
8834 else if (intel_parser.is_mem)
8836 if ((i.mem_operands == 1
8837 && !current_templates->start->opcode_modifier.isstring)
8838 || i.mem_operands == 2)
8840 as_bad (_("too many memory references for '%s'"),
8841 current_templates->start->name);
8846 char *s = intel_parser.disp;
8847 i.types[this_operand].bitfield.mem = 1;
8850 if (!quiet_warnings && intel_parser.is_mem < 0)
8851 /* See the comments in intel_bracket_expr. */
8852 as_warn (_("Treating `%s' as memory reference"), operand_string);
8854 /* Add the displacement expression. */
8856 ret = i386_displacement (s, s + strlen (s));
8859 /* Swap base and index in 16-bit memory operands like
8860 [si+bx]. Since i386_index_check is also used in AT&T
8861 mode we have to do that here. */
8864 && i.base_reg->reg_type.bitfield.reg16
8865 && i.index_reg->reg_type.bitfield.reg16
8866 && i.base_reg->reg_num >= 6
8867 && i.index_reg->reg_num < 6)
8869 const reg_entry *base = i.index_reg;
8871 i.index_reg = i.base_reg;
8874 ret = i386_index_check (operand_string);
8879 /* Constant and OFFSET expressions are handled by i386_immediate. */
8880 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
8881 || intel_parser.reg == NULL)
8883 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8885 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8886 as_warn (_("Segment override ignored"));
8887 i.seg[i.mem_operands] = NULL;
8889 ret = i386_immediate (intel_parser.disp);
8892 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
8894 if (!ret || !intel_parser.next_operand)
8896 intel_parser.op_string = intel_parser.next_operand;
8897 this_operand = i.operands++;
8898 i.types[this_operand].bitfield.unspecified = 1;
8902 free (intel_parser.disp);
8907 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8911 expr' cmpOp e04 expr'
8916 /* XXX Implement the comparison operators. */
8917 return intel_e04 ();
8934 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8935 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
8937 if (cur_token.code == '+')
8939 else if (cur_token.code == '-')
8940 nregs = NUM_ADDRESS_REGS;
8944 strcat (intel_parser.disp, cur_token.str);
8945 intel_match_token (cur_token.code);
8956 int nregs = ~NUM_ADDRESS_REGS;
8963 if (cur_token.code == '&'
8964 || cur_token.code == '|'
8965 || cur_token.code == '^')
8969 str[0] = cur_token.code;
8971 strcat (intel_parser.disp, str);
8976 intel_match_token (cur_token.code);
8981 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8982 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8993 int nregs = ~NUM_ADDRESS_REGS;
9000 if (cur_token.code == '*'
9001 || cur_token.code == '/'
9002 || cur_token.code == '%')
9006 str[0] = cur_token.code;
9008 strcat (intel_parser.disp, str);
9010 else if (cur_token.code == T_SHL)
9011 strcat (intel_parser.disp, "<<");
9012 else if (cur_token.code == T_SHR)
9013 strcat (intel_parser.disp, ">>");
9017 intel_match_token (cur_token.code);
9022 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9023 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9041 int nregs = ~NUM_ADDRESS_REGS;
9046 /* Don't consume constants here. */
9047 if (cur_token.code == '+' || cur_token.code == '-')
9049 /* Need to look one token ahead - if the next token
9050 is a constant, the current token is its sign. */
9053 intel_match_token (cur_token.code);
9054 next_code = cur_token.code;
9055 intel_putback_token ();
9056 if (next_code == T_CONST)
9060 /* e09 OFFSET e09 */
9061 if (cur_token.code == T_OFFSET)
9064 ++intel_parser.in_offset;
9068 else if (cur_token.code == T_SHORT)
9069 intel_parser.op_modifier |= 1 << T_SHORT;
9072 else if (cur_token.code == '+')
9073 strcat (intel_parser.disp, "+");
9078 else if (cur_token.code == '-' || cur_token.code == '~')
9084 str[0] = cur_token.code;
9086 strcat (intel_parser.disp, str);
9093 intel_match_token (cur_token.code);
9101 /* e09' PTR e10 e09' */
9102 if (cur_token.code == T_PTR)
9106 if (prev_token.code == T_BYTE)
9108 suffix = BYTE_MNEM_SUFFIX;
9109 i.types[this_operand].bitfield.byte = 1;
9112 else if (prev_token.code == T_WORD)
9114 if ((current_templates->start->name[0] == 'l'
9115 && current_templates->start->name[2] == 's'
9116 && current_templates->start->name[3] == 0)
9117 || current_templates->start->base_opcode == 0x62 /* bound */)
9118 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9119 else if (intel_parser.got_a_float == 2) /* "fi..." */
9120 suffix = SHORT_MNEM_SUFFIX;
9122 suffix = WORD_MNEM_SUFFIX;
9123 i.types[this_operand].bitfield.word = 1;
9126 else if (prev_token.code == T_DWORD)
9128 if ((current_templates->start->name[0] == 'l'
9129 && current_templates->start->name[2] == 's'
9130 && current_templates->start->name[3] == 0)
9131 || current_templates->start->base_opcode == 0x62 /* bound */)
9132 suffix = WORD_MNEM_SUFFIX;
9133 else if (flag_code == CODE_16BIT
9134 && (current_templates->start->opcode_modifier.jump
9135 || current_templates->start->opcode_modifier.jumpdword))
9136 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9137 else if (intel_parser.got_a_float == 1) /* "f..." */
9138 suffix = SHORT_MNEM_SUFFIX;
9140 suffix = LONG_MNEM_SUFFIX;
9141 i.types[this_operand].bitfield.dword = 1;
9144 else if (prev_token.code == T_FWORD)
9146 if (current_templates->start->name[0] == 'l'
9147 && current_templates->start->name[2] == 's'
9148 && current_templates->start->name[3] == 0)
9149 suffix = LONG_MNEM_SUFFIX;
9150 else if (!intel_parser.got_a_float)
9152 if (flag_code == CODE_16BIT)
9153 add_prefix (DATA_PREFIX_OPCODE);
9154 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9157 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9158 i.types[this_operand].bitfield.fword = 1;
9161 else if (prev_token.code == T_QWORD)
9163 if (current_templates->start->base_opcode == 0x62 /* bound */
9164 || intel_parser.got_a_float == 1) /* "f..." */
9165 suffix = LONG_MNEM_SUFFIX;
9167 suffix = QWORD_MNEM_SUFFIX;
9168 i.types[this_operand].bitfield.qword = 1;
9171 else if (prev_token.code == T_TBYTE)
9173 if (intel_parser.got_a_float == 1)
9174 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9176 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9179 else if (prev_token.code == T_XMMWORD)
9181 suffix = XMMWORD_MNEM_SUFFIX;
9182 i.types[this_operand].bitfield.xmmword = 1;
9185 else if (prev_token.code == T_YMMWORD)
9187 suffix = YMMWORD_MNEM_SUFFIX;
9188 i.types[this_operand].bitfield.ymmword = 1;
9193 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9197 i.types[this_operand].bitfield.unspecified = 0;
9199 /* Operands for jump/call using 'ptr' notation denote absolute
9201 if (current_templates->start->opcode_modifier.jump
9202 || current_templates->start->opcode_modifier.jumpdword)
9203 i.types[this_operand].bitfield.jumpabsolute = 1;
9205 if (current_templates->start->base_opcode == 0x8d /* lea */)
9209 else if (i.suffix != suffix)
9211 as_bad (_("Conflicting operand modifiers"));
9217 /* e09' : e10 e09' */
9218 else if (cur_token.code == ':')
9220 if (prev_token.code != T_REG)
9222 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9223 segment/group identifier (which we don't have), using comma
9224 as the operand separator there is even less consistent, since
9225 there all branches only have a single operand. */
9226 if (this_operand != 0
9227 || intel_parser.in_offset
9228 || intel_parser.in_bracket
9229 || (!current_templates->start->opcode_modifier.jump
9230 && !current_templates->start->opcode_modifier.jumpdword
9231 && !current_templates->start->opcode_modifier.jumpintersegment
9232 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
9233 return intel_match_token (T_NIL);
9234 /* Remember the start of the 2nd operand and terminate 1st
9236 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9237 another expression), but it gets at least the simplest case
9238 (a plain number or symbol on the left side) right. */
9239 intel_parser.next_operand = intel_parser.op_string;
9240 *--intel_parser.op_string = '\0';
9241 return intel_match_token (':');
9249 intel_match_token (cur_token.code);
9255 --intel_parser.in_offset;
9258 if (NUM_ADDRESS_REGS > nregs)
9260 as_bad (_("Invalid operand to `OFFSET'"));
9263 intel_parser.op_modifier |= 1 << T_OFFSET;
9266 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9267 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9272 intel_bracket_expr (void)
9274 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9275 const char *start = intel_parser.op_string;
9278 if (i.op[this_operand].regs)
9279 return intel_match_token (T_NIL);
9281 intel_match_token ('[');
9283 /* Mark as a memory operand only if it's not already known to be an
9284 offset expression. If it's an offset expression, we need to keep
9286 if (!intel_parser.in_offset)
9288 ++intel_parser.in_bracket;
9290 /* Operands for jump/call inside brackets denote absolute addresses. */
9291 if (current_templates->start->opcode_modifier.jump
9292 || current_templates->start->opcode_modifier.jumpdword)
9293 i.types[this_operand].bitfield.jumpabsolute = 1;
9295 /* Unfortunately gas always diverged from MASM in a respect that can't
9296 be easily fixed without risking to break code sequences likely to be
9297 encountered (the testsuite even check for this): MASM doesn't consider
9298 an expression inside brackets unconditionally as a memory reference.
9299 When that is e.g. a constant, an offset expression, or the sum of the
9300 two, this is still taken as a constant load. gas, however, always
9301 treated these as memory references. As a compromise, we'll try to make
9302 offset expressions inside brackets work the MASM way (since that's
9303 less likely to be found in real world code), but make constants alone
9304 continue to work the traditional gas way. In either case, issue a
9306 intel_parser.op_modifier &= ~was_offset;
9309 strcat (intel_parser.disp, "[");
9311 /* Add a '+' to the displacement string if necessary. */
9312 if (*intel_parser.disp != '\0'
9313 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9314 strcat (intel_parser.disp, "+");
9317 && (len = intel_parser.op_string - start - 1,
9318 intel_match_token (']')))
9320 /* Preserve brackets when the operand is an offset expression. */
9321 if (intel_parser.in_offset)
9322 strcat (intel_parser.disp, "]");
9325 --intel_parser.in_bracket;
9326 if (i.base_reg || i.index_reg)
9327 intel_parser.is_mem = 1;
9328 if (!intel_parser.is_mem)
9330 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9331 /* Defer the warning until all of the operand was parsed. */
9332 intel_parser.is_mem = -1;
9333 else if (!quiet_warnings)
9334 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9335 len, start, len, start);
9338 intel_parser.op_modifier |= was_offset;
9355 while (cur_token.code == '[')
9357 if (!intel_bracket_expr ())
9383 switch (cur_token.code)
9387 intel_match_token ('(');
9388 strcat (intel_parser.disp, "(");
9390 if (intel_expr () && intel_match_token (')'))
9392 strcat (intel_parser.disp, ")");
9399 return intel_bracket_expr ();
9404 strcat (intel_parser.disp, cur_token.str);
9405 intel_match_token (cur_token.code);
9407 /* Mark as a memory operand only if it's not already known to be an
9408 offset expression. */
9409 if (!intel_parser.in_offset)
9410 intel_parser.is_mem = 1;
9417 const reg_entry *reg = intel_parser.reg = cur_token.reg;
9419 intel_match_token (T_REG);
9421 /* Check for segment change. */
9422 if (cur_token.code == ':')
9424 if (!reg->reg_type.bitfield.sreg2
9425 && !reg->reg_type.bitfield.sreg3)
9427 as_bad (_("`%s' is not a valid segment register"),
9431 else if (i.mem_operands >= 2)
9432 as_warn (_("Segment override ignored"));
9433 else if (i.seg[i.mem_operands])
9434 as_warn (_("Extra segment override ignored"));
9437 if (!intel_parser.in_offset)
9438 intel_parser.is_mem = 1;
9439 switch (reg->reg_num)
9442 i.seg[i.mem_operands] = &es;
9445 i.seg[i.mem_operands] = &cs;
9448 i.seg[i.mem_operands] = &ss;
9451 i.seg[i.mem_operands] = &ds;
9454 i.seg[i.mem_operands] = &fs;
9457 i.seg[i.mem_operands] = &gs;
9463 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9465 as_bad (_("cannot use `FLAT' here"));
9469 /* Not a segment register. Check for register scaling. */
9470 else if (cur_token.code == '*')
9472 if (!intel_parser.in_bracket)
9474 as_bad (_("Register scaling only allowed in memory operands"));
9478 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
9479 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9480 else if (i.index_reg)
9481 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
9483 /* What follows must be a valid scale. */
9484 intel_match_token ('*');
9486 i.types[this_operand].bitfield.baseindex = 1;
9488 /* Set the scale after setting the register (otherwise,
9489 i386_scale will complain) */
9490 if (cur_token.code == '+' || cur_token.code == '-')
9492 char *str, sign = cur_token.code;
9493 intel_match_token (cur_token.code);
9494 if (cur_token.code != T_CONST)
9496 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9500 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9501 strcpy (str + 1, cur_token.str);
9503 if (!i386_scale (str))
9507 else if (!i386_scale (cur_token.str))
9509 intel_match_token (cur_token.code);
9512 /* No scaling. If this is a memory operand, the register is either a
9513 base register (first occurrence) or an index register (second
9515 else if (intel_parser.in_bracket)
9520 else if (!i.index_reg)
9524 as_bad (_("Too many register references in memory operand"));
9528 i.types[this_operand].bitfield.baseindex = 1;
9531 /* It's neither base nor index. */
9532 else if (!intel_parser.in_offset && !intel_parser.is_mem)
9534 i386_operand_type temp = reg->reg_type;
9535 temp.bitfield.baseindex = 0;
9536 i.types[this_operand] = operand_type_or (i.types[this_operand],
9538 i.types[this_operand].bitfield.unspecified = 0;
9539 i.op[this_operand].regs = reg;
9544 as_bad (_("Invalid use of register"));
9548 /* Since registers are not part of the displacement string (except
9549 when we're parsing offset operands), we may need to remove any
9550 preceding '+' from the displacement string. */
9551 if (*intel_parser.disp != '\0'
9552 && !intel_parser.in_offset)
9554 char *s = intel_parser.disp;
9555 s += strlen (s) - 1;
9580 intel_match_token (cur_token.code);
9582 if (cur_token.code == T_PTR)
9585 /* It must have been an identifier. */
9586 intel_putback_token ();
9587 cur_token.code = T_ID;
9593 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9597 /* The identifier represents a memory reference only if it's not
9598 preceded by an offset modifier and if it's not an equate. */
9599 symbolP = symbol_find(cur_token.str);
9600 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9601 intel_parser.is_mem = 1;
9609 char *save_str, sign = 0;
9611 /* Allow constants that start with `+' or `-'. */
9612 if (cur_token.code == '-' || cur_token.code == '+')
9614 sign = cur_token.code;
9615 intel_match_token (cur_token.code);
9616 if (cur_token.code != T_CONST)
9618 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9624 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9625 strcpy (save_str + !!sign, cur_token.str);
9629 /* Get the next token to check for register scaling. */
9630 intel_match_token (cur_token.code);
9632 /* Check if this constant is a scaling factor for an
9634 if (cur_token.code == '*')
9636 if (intel_match_token ('*') && cur_token.code == T_REG)
9638 const reg_entry *reg = cur_token.reg;
9640 if (!intel_parser.in_bracket)
9642 as_bad (_("Register scaling only allowed "
9643 "in memory operands"));
9647 /* Disallow things like [1*si].
9648 sp and esp are invalid as index. */
9649 if (reg->reg_type.bitfield.reg16)
9650 reg = i386_regtab + REGNAM_AX + 4;
9651 else if (i.index_reg)
9652 reg = i386_regtab + REGNAM_EAX + 4;
9654 /* The constant is followed by `* reg', so it must be
9657 i.types[this_operand].bitfield.baseindex = 1;
9659 /* Set the scale after setting the register (otherwise,
9660 i386_scale will complain) */
9661 if (!i386_scale (save_str))
9663 intel_match_token (T_REG);
9665 /* Since registers are not part of the displacement
9666 string, we may need to remove any preceding '+' from
9667 the displacement string. */
9668 if (*intel_parser.disp != '\0')
9670 char *s = intel_parser.disp;
9671 s += strlen (s) - 1;
9681 /* The constant was not used for register scaling. Since we have
9682 already consumed the token following `*' we now need to put it
9683 back in the stream. */
9684 intel_putback_token ();
9687 /* Add the constant to the displacement string. */
9688 strcat (intel_parser.disp, save_str);
9695 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9699 /* Match the given token against cur_token. If they match, read the next
9700 token from the operand string. */
9702 intel_match_token (int code)
9704 if (cur_token.code == code)
9711 as_bad (_("Unexpected token `%s'"), cur_token.str);
9716 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9718 intel_get_token (void)
9721 const reg_entry *reg;
9722 struct intel_token new_token;
9724 new_token.code = T_NIL;
9725 new_token.reg = NULL;
9726 new_token.str = NULL;
9728 /* Free the memory allocated to the previous token and move
9729 cur_token to prev_token. */
9731 free (prev_token.str);
9733 prev_token = cur_token;
9735 /* Skip whitespace. */
9736 while (is_space_char (*intel_parser.op_string))
9737 intel_parser.op_string++;
9739 /* Return an empty token if we find nothing else on the line. */
9740 if (*intel_parser.op_string == '\0')
9742 cur_token = new_token;
9746 /* The new token cannot be larger than the remainder of the operand
9748 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
9749 new_token.str[0] = '\0';
9751 if (strchr ("0123456789", *intel_parser.op_string))
9753 char *p = new_token.str;
9754 char *q = intel_parser.op_string;
9755 new_token.code = T_CONST;
9757 /* Allow any kind of identifier char to encompass floating point and
9758 hexadecimal numbers. */
9759 while (is_identifier_char (*q))
9763 /* Recognize special symbol names [0-9][bf]. */
9764 if (strlen (intel_parser.op_string) == 2
9765 && (intel_parser.op_string[1] == 'b'
9766 || intel_parser.op_string[1] == 'f'))
9767 new_token.code = T_ID;
9770 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
9772 size_t len = end_op - intel_parser.op_string;
9774 new_token.code = T_REG;
9775 new_token.reg = reg;
9777 memcpy (new_token.str, intel_parser.op_string, len);
9778 new_token.str[len] = '\0';
9781 else if (is_identifier_char (*intel_parser.op_string))
9783 char *p = new_token.str;
9784 char *q = intel_parser.op_string;
9786 /* A '.' or '$' followed by an identifier char is an identifier.
9787 Otherwise, it's operator '.' followed by an expression. */
9788 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9790 new_token.code = '.';
9791 new_token.str[0] = '.';
9792 new_token.str[1] = '\0';
9796 while (is_identifier_char (*q) || *q == '@')
9800 if (strcasecmp (new_token.str, "NOT") == 0)
9801 new_token.code = '~';
9803 else if (strcasecmp (new_token.str, "MOD") == 0)
9804 new_token.code = '%';
9806 else if (strcasecmp (new_token.str, "AND") == 0)
9807 new_token.code = '&';
9809 else if (strcasecmp (new_token.str, "OR") == 0)
9810 new_token.code = '|';
9812 else if (strcasecmp (new_token.str, "XOR") == 0)
9813 new_token.code = '^';
9815 else if (strcasecmp (new_token.str, "SHL") == 0)
9816 new_token.code = T_SHL;
9818 else if (strcasecmp (new_token.str, "SHR") == 0)
9819 new_token.code = T_SHR;
9821 else if (strcasecmp (new_token.str, "BYTE") == 0)
9822 new_token.code = T_BYTE;
9824 else if (strcasecmp (new_token.str, "WORD") == 0)
9825 new_token.code = T_WORD;
9827 else if (strcasecmp (new_token.str, "DWORD") == 0)
9828 new_token.code = T_DWORD;
9830 else if (strcasecmp (new_token.str, "FWORD") == 0)
9831 new_token.code = T_FWORD;
9833 else if (strcasecmp (new_token.str, "QWORD") == 0)
9834 new_token.code = T_QWORD;
9836 else if (strcasecmp (new_token.str, "TBYTE") == 0
9837 /* XXX remove (gcc still uses it) */
9838 || strcasecmp (new_token.str, "XWORD") == 0)
9839 new_token.code = T_TBYTE;
9841 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9842 || strcasecmp (new_token.str, "OWORD") == 0)
9843 new_token.code = T_XMMWORD;
9845 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9846 new_token.code = T_YMMWORD;
9848 else if (strcasecmp (new_token.str, "PTR") == 0)
9849 new_token.code = T_PTR;
9851 else if (strcasecmp (new_token.str, "SHORT") == 0)
9852 new_token.code = T_SHORT;
9854 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9856 new_token.code = T_OFFSET;
9858 /* ??? This is not mentioned in the MASM grammar but gcc
9859 makes use of it with -mintel-syntax. OFFSET may be
9860 followed by FLAT: */
9861 if (strncasecmp (q, " FLAT:", 6) == 0)
9862 strcat (new_token.str, " FLAT:");
9866 new_token.code = T_ID;
9870 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9872 new_token.code = *intel_parser.op_string;
9873 new_token.str[0] = *intel_parser.op_string;
9874 new_token.str[1] = '\0';
9877 else if (strchr ("<>", *intel_parser.op_string)
9878 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9880 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9881 new_token.str[0] = *intel_parser.op_string;
9882 new_token.str[1] = *intel_parser.op_string;
9883 new_token.str[2] = '\0';
9887 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
9889 intel_parser.op_string += strlen (new_token.str);
9890 cur_token = new_token;
9893 /* Put cur_token back into the token stream and make cur_token point to
9896 intel_putback_token (void)
9898 if (cur_token.code != T_NIL)
9900 intel_parser.op_string -= strlen (cur_token.str);
9901 free (cur_token.str);
9903 cur_token = prev_token;
9905 /* Forget prev_token. */
9906 prev_token.code = T_NIL;
9907 prev_token.reg = NULL;
9908 prev_token.str = NULL;
9912 tc_x86_parse_to_dw2regnum (expressionS *exp)
9914 int saved_naked_reg;
9915 char saved_register_dot;
9917 saved_naked_reg = allow_naked_reg;
9918 allow_naked_reg = 1;
9919 saved_register_dot = register_chars['.'];
9920 register_chars['.'] = '.';
9921 allow_pseudo_reg = 1;
9922 expression_and_evaluate (exp);
9923 allow_pseudo_reg = 0;
9924 register_chars['.'] = saved_register_dot;
9925 allow_naked_reg = saved_naked_reg;
9927 if (exp->X_op == O_register && exp->X_add_number >= 0)
9929 if ((addressT) exp->X_add_number < i386_regtab_size)
9931 exp->X_op = O_constant;
9932 exp->X_add_number = i386_regtab[exp->X_add_number]
9933 .dw2_regnum[flag_code >> 1];
9936 exp->X_op = O_illegal;
9941 tc_x86_frame_initial_instructions (void)
9943 static unsigned int sp_regno[2];
9945 if (!sp_regno[flag_code >> 1])
9947 char *saved_input = input_line_pointer;
9948 char sp[][4] = {"esp", "rsp"};
9951 input_line_pointer = sp[flag_code >> 1];
9952 tc_x86_parse_to_dw2regnum (&exp);
9953 assert (exp.X_op == O_constant);
9954 sp_regno[flag_code >> 1] = exp.X_add_number;
9955 input_line_pointer = saved_input;
9958 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
9959 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
9963 i386_elf_section_type (const char *str, size_t len)
9965 if (flag_code == CODE_64BIT
9966 && len == sizeof ("unwind") - 1
9967 && strncmp (str, "unwind", 6) == 0)
9968 return SHT_X86_64_UNWIND;
9975 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9979 expr.X_op = O_secrel;
9980 expr.X_add_symbol = symbol;
9981 expr.X_add_number = 0;
9982 emit_expr (&expr, size);
9986 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9987 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9990 x86_64_section_letter (int letter, char **ptr_msg)
9992 if (flag_code == CODE_64BIT)
9995 return SHF_X86_64_LARGE;
9997 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10000 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
10005 x86_64_section_word (char *str, size_t len)
10007 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10008 return SHF_X86_64_LARGE;
10014 handle_large_common (int small ATTRIBUTE_UNUSED)
10016 if (flag_code != CODE_64BIT)
10018 s_comm_internal (0, elf_common_parse);
10019 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10023 static segT lbss_section;
10024 asection *saved_com_section_ptr = elf_com_section_ptr;
10025 asection *saved_bss_section = bss_section;
10027 if (lbss_section == NULL)
10029 flagword applicable;
10030 segT seg = now_seg;
10031 subsegT subseg = now_subseg;
10033 /* The .lbss section is for local .largecomm symbols. */
10034 lbss_section = subseg_new (".lbss", 0);
10035 applicable = bfd_applicable_section_flags (stdoutput);
10036 bfd_set_section_flags (stdoutput, lbss_section,
10037 applicable & SEC_ALLOC);
10038 seg_info (lbss_section)->bss = 1;
10040 subseg_set (seg, subseg);
10043 elf_com_section_ptr = &_bfd_elf_large_com_section;
10044 bss_section = lbss_section;
10046 s_comm_internal (0, elf_common_parse);
10048 elf_com_section_ptr = saved_com_section_ptr;
10049 bss_section = saved_bss_section;
10052 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */