1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2019 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
39 #ifdef HAVE_SYS_PARAM_H
40 #include <sys/param.h>
43 #define INT_MAX (int) (((unsigned) (-1)) >> 1)
47 #ifndef REGISTER_WARNINGS
48 #define REGISTER_WARNINGS 1
51 #ifndef INFER_ADDR_PREFIX
52 #define INFER_ADDR_PREFIX 1
56 #define DEFAULT_ARCH "i386"
61 #define INLINE __inline__
67 /* Prefixes will be emitted in the order defined below.
68 WAIT_PREFIX must be the first prefix since FWAIT is really is an
69 instruction, and so must come before any prefixes.
70 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
71 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
77 #define HLE_PREFIX REP_PREFIX
78 #define BND_PREFIX REP_PREFIX
80 #define REX_PREFIX 6 /* must come last. */
81 #define MAX_PREFIXES 7 /* max prefixes per opcode */
83 /* we define the syntax here (modulo base,index,scale syntax) */
84 #define REGISTER_PREFIX '%'
85 #define IMMEDIATE_PREFIX '$'
86 #define ABSOLUTE_PREFIX '*'
88 /* these are the instruction mnemonic suffixes in AT&T syntax or
89 memory operand size in Intel syntax. */
90 #define WORD_MNEM_SUFFIX 'w'
91 #define BYTE_MNEM_SUFFIX 'b'
92 #define SHORT_MNEM_SUFFIX 's'
93 #define LONG_MNEM_SUFFIX 'l'
94 #define QWORD_MNEM_SUFFIX 'q'
95 /* Intel Syntax. Use a non-ascii letter since since it never appears
97 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
99 #define END_OF_INSN '\0'
101 /* This matches the C -> StaticRounding alias in the opcode table. */
102 #define commutative staticrounding
105 'templates' is for grouping together 'template' structures for opcodes
106 of the same name. This is only used for storing the insns in the grand
107 ole hash table of insns.
108 The templates themselves start at START and range up to (but not including)
113 const insn_template *start;
114 const insn_template *end;
118 /* 386 operand encoding bytes: see 386 book for details of this. */
121 unsigned int regmem; /* codes register or memory operand */
122 unsigned int reg; /* codes register operand (or extended opcode) */
123 unsigned int mode; /* how to interpret regmem & reg */
127 /* x86-64 extension prefix. */
128 typedef int rex_byte;
130 /* 386 opcode byte to code indirect addressing. */
139 /* x86 arch names, types and features */
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 enum processor_type type; /* arch type */
145 i386_cpu_flags flags; /* cpu feature flags */
146 unsigned int skip; /* show_arch should skip this. */
150 /* Used to turn off indicated flags. */
153 const char *name; /* arch name */
154 unsigned int len; /* arch string length */
155 i386_cpu_flags flags; /* cpu feature flags */
159 static void update_code_flag (int, int);
160 static void set_code_flag (int);
161 static void set_16bit_gcc_code_flag (int);
162 static void set_intel_syntax (int);
163 static void set_intel_mnemonic (int);
164 static void set_allow_index_reg (int);
165 static void set_check (int);
166 static void set_cpu_arch (int);
168 static void pe_directive_secrel (int);
170 static void signed_cons (int);
171 static char *output_invalid (int c);
172 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
174 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
176 static int i386_att_operand (char *);
177 static int i386_intel_operand (char *, int);
178 static int i386_intel_simplify (expressionS *);
179 static int i386_intel_parse_name (const char *, expressionS *);
180 static const reg_entry *parse_register (char *, char **);
181 static char *parse_insn (char *, char *);
182 static char *parse_operands (char *, const char *);
183 static void swap_operands (void);
184 static void swap_2_operands (int, int);
185 static void optimize_imm (void);
186 static void optimize_disp (void);
187 static const insn_template *match_template (char);
188 static int check_string (void);
189 static int process_suffix (void);
190 static int check_byte_reg (void);
191 static int check_long_reg (void);
192 static int check_qword_reg (void);
193 static int check_word_reg (void);
194 static int finalize_imm (void);
195 static int process_operands (void);
196 static const seg_entry *build_modrm_byte (void);
197 static void output_insn (void);
198 static void output_imm (fragS *, offsetT);
199 static void output_disp (fragS *, offsetT);
201 static void s_bss (int);
203 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
204 static void handle_large_common (int small ATTRIBUTE_UNUSED);
206 /* GNU_PROPERTY_X86_ISA_1_USED. */
207 static unsigned int x86_isa_1_used;
208 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
209 static unsigned int x86_feature_2_used;
210 /* Generate x86 used ISA and feature properties. */
211 static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE;
214 static const char *default_arch = DEFAULT_ARCH;
216 /* This struct describes rounding control and SAE in the instruction. */
230 static struct RC_Operation rc_op;
232 /* The struct describes masking, applied to OPERAND in the instruction.
233 MASK is a pointer to the corresponding mask register. ZEROING tells
234 whether merging or zeroing mask is used. */
235 struct Mask_Operation
237 const reg_entry *mask;
238 unsigned int zeroing;
239 /* The operand where this operation is associated. */
243 static struct Mask_Operation mask_op;
245 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
247 struct Broadcast_Operation
249 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
252 /* Index of broadcasted operand. */
255 /* Number of bytes to broadcast. */
259 static struct Broadcast_Operation broadcast_op;
264 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
265 unsigned char bytes[4];
267 /* Destination or source register specifier. */
268 const reg_entry *register_specifier;
271 /* 'md_assemble ()' gathers together information and puts it into a
278 const reg_entry *regs;
283 operand_size_mismatch,
284 operand_type_mismatch,
285 register_type_mismatch,
286 number_of_operands_mismatch,
287 invalid_instruction_suffix,
289 unsupported_with_intel_mnemonic,
292 invalid_vsib_address,
293 invalid_vector_register_set,
294 unsupported_vector_index_register,
295 unsupported_broadcast,
298 mask_not_on_destination,
301 rc_sae_operand_not_last_imm,
302 invalid_register_operand,
307 /* TM holds the template for the insn were currently assembling. */
310 /* SUFFIX holds the instruction size suffix for byte, word, dword
311 or qword, if given. */
314 /* OPERANDS gives the number of given operands. */
315 unsigned int operands;
317 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
318 of given register, displacement, memory operands and immediate
320 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
322 /* TYPES [i] is the type (see above #defines) which tells us how to
323 use OP[i] for the corresponding operand. */
324 i386_operand_type types[MAX_OPERANDS];
326 /* Displacement expression, immediate expression, or register for each
328 union i386_op op[MAX_OPERANDS];
330 /* Flags for operands. */
331 unsigned int flags[MAX_OPERANDS];
332 #define Operand_PCrel 1
333 #define Operand_Mem 2
335 /* Relocation type for operand */
336 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
338 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
339 the base index byte below. */
340 const reg_entry *base_reg;
341 const reg_entry *index_reg;
342 unsigned int log2_scale_factor;
344 /* SEG gives the seg_entries of this insn. They are zero unless
345 explicit segment overrides are given. */
346 const seg_entry *seg[2];
348 /* Copied first memory operand string, for re-checking. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
353 unsigned int prefixes;
354 unsigned char prefix[MAX_PREFIXES];
356 /* Has MMX register operands. */
357 bfd_boolean has_regmmx;
359 /* Has XMM register operands. */
360 bfd_boolean has_regxmm;
362 /* Has YMM register operands. */
363 bfd_boolean has_regymm;
365 /* Has ZMM register operands. */
366 bfd_boolean has_regzmm;
368 /* RM and SIB are the modrm byte and the sib byte where the
369 addressing modes of this insn are encoded. */
376 /* Masking attributes. */
377 struct Mask_Operation *mask;
379 /* Rounding control and SAE attributes. */
380 struct RC_Operation *rounding;
382 /* Broadcasting attributes. */
383 struct Broadcast_Operation *broadcast;
385 /* Compressed disp8*N attribute. */
386 unsigned int memshift;
388 /* Prefer load or store in encoding. */
391 dir_encoding_default = 0,
397 /* Prefer 8bit or 32bit displacement in encoding. */
400 disp_encoding_default = 0,
405 /* Prefer the REX byte in encoding. */
406 bfd_boolean rex_encoding;
408 /* Disable instruction size optimization. */
409 bfd_boolean no_optimize;
411 /* How to encode vector instructions. */
414 vex_encoding_default = 0,
421 const char *rep_prefix;
424 const char *hle_prefix;
426 /* Have BND prefix. */
427 const char *bnd_prefix;
429 /* Have NOTRACK prefix. */
430 const char *notrack_prefix;
433 enum i386_error error;
436 typedef struct _i386_insn i386_insn;
438 /* Link RC type with corresponding string, that'll be looked for in
447 static const struct RC_name RC_NamesTable[] =
449 { rne, STRING_COMMA_LEN ("rn-sae") },
450 { rd, STRING_COMMA_LEN ("rd-sae") },
451 { ru, STRING_COMMA_LEN ("ru-sae") },
452 { rz, STRING_COMMA_LEN ("rz-sae") },
453 { saeonly, STRING_COMMA_LEN ("sae") },
456 /* List of chars besides those in app.c:symbol_chars that can start an
457 operand. Used to prevent the scrubber eating vital white-space. */
458 const char extra_symbol_chars[] = "*%-([{}"
467 #if (defined (TE_I386AIX) \
468 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
469 && !defined (TE_GNU) \
470 && !defined (TE_LINUX) \
471 && !defined (TE_NACL) \
472 && !defined (TE_FreeBSD) \
473 && !defined (TE_DragonFly) \
474 && !defined (TE_NetBSD)))
475 /* This array holds the chars that always start a comment. If the
476 pre-processor is disabled, these aren't very useful. The option
477 --divide will remove '/' from this list. */
478 const char *i386_comment_chars = "#/";
479 #define SVR4_COMMENT_CHARS 1
480 #define PREFIX_SEPARATOR '\\'
483 const char *i386_comment_chars = "#";
484 #define PREFIX_SEPARATOR '/'
487 /* This array holds the chars that only start a comment at the beginning of
488 a line. If the line seems to have the form '# 123 filename'
489 .line and .file directives will appear in the pre-processed output.
490 Note that input_file.c hand checks for '#' at the beginning of the
491 first line of the input file. This is because the compiler outputs
492 #NO_APP at the beginning of its output.
493 Also note that comments started like this one will always work if
494 '/' isn't otherwise defined. */
495 const char line_comment_chars[] = "#/";
497 const char line_separator_chars[] = ";";
499 /* Chars that can be used to separate mant from exp in floating point
501 const char EXP_CHARS[] = "eE";
503 /* Chars that mean this number is a floating point constant
506 const char FLT_CHARS[] = "fFdDxX";
508 /* Tables for lexical analysis. */
509 static char mnemonic_chars[256];
510 static char register_chars[256];
511 static char operand_chars[256];
512 static char identifier_chars[256];
513 static char digit_chars[256];
515 /* Lexical macros. */
516 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
517 #define is_operand_char(x) (operand_chars[(unsigned char) x])
518 #define is_register_char(x) (register_chars[(unsigned char) x])
519 #define is_space_char(x) ((x) == ' ')
520 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
521 #define is_digit_char(x) (digit_chars[(unsigned char) x])
523 /* All non-digit non-letter characters that may occur in an operand. */
524 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
526 /* md_assemble() always leaves the strings it's passed unaltered. To
527 effect this we maintain a stack of saved characters that we've smashed
528 with '\0's (indicating end of strings for various sub-fields of the
529 assembler instruction). */
530 static char save_stack[32];
531 static char *save_stack_p;
532 #define END_STRING_AND_SAVE(s) \
533 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
534 #define RESTORE_END_STRING(s) \
535 do { *(s) = *--save_stack_p; } while (0)
537 /* The instruction we're assembling. */
540 /* Possible templates for current insn. */
541 static const templates *current_templates;
543 /* Per instruction expressionS buffers: max displacements & immediates. */
544 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
545 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
547 /* Current operand we are working on. */
548 static int this_operand = -1;
550 /* We support four different modes. FLAG_CODE variable is used to distinguish
558 static enum flag_code flag_code;
559 static unsigned int object_64bit;
560 static unsigned int disallow_64bit_reloc;
561 static int use_rela_relocations = 0;
563 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
564 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
565 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
567 /* The ELF ABI to use. */
575 static enum x86_elf_abi x86_elf_abi = I386_ABI;
578 #if defined (TE_PE) || defined (TE_PEP)
579 /* Use big object file format. */
580 static int use_big_obj = 0;
583 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
584 /* 1 if generating code for a shared library. */
585 static int shared = 0;
588 /* 1 for intel syntax,
590 static int intel_syntax = 0;
592 /* 1 for Intel64 ISA,
596 /* 1 for intel mnemonic,
597 0 if att mnemonic. */
598 static int intel_mnemonic = !SYSV386_COMPAT;
600 /* 1 if pseudo registers are permitted. */
601 static int allow_pseudo_reg = 0;
603 /* 1 if register prefix % not required. */
604 static int allow_naked_reg = 0;
606 /* 1 if the assembler should add BND prefix for all control-transferring
607 instructions supporting it, even if this prefix wasn't specified
609 static int add_bnd_prefix = 0;
611 /* 1 if pseudo index register, eiz/riz, is allowed . */
612 static int allow_index_reg = 0;
614 /* 1 if the assembler should ignore LOCK prefix, even if it was
615 specified explicitly. */
616 static int omit_lock_prefix = 0;
618 /* 1 if the assembler should encode lfence, mfence, and sfence as
619 "lock addl $0, (%{re}sp)". */
620 static int avoid_fence = 0;
622 /* 1 if the assembler should generate relax relocations. */
624 static int generate_relax_relocations
625 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
627 static enum check_kind
633 sse_check, operand_check = check_warning;
636 1. Clear the REX_W bit with register operand if possible.
637 2. Above plus use 128bit vector instruction to clear the full vector
640 static int optimize = 0;
643 1. Clear the REX_W bit with register operand if possible.
644 2. Above plus use 128bit vector instruction to clear the full vector
646 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
649 static int optimize_for_space = 0;
651 /* Register prefix used for error message. */
652 static const char *register_prefix = "%";
654 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
655 leave, push, and pop instructions so that gcc has the same stack
656 frame as in 32 bit mode. */
657 static char stackop_size = '\0';
659 /* Non-zero to optimize code alignment. */
660 int optimize_align_code = 1;
662 /* Non-zero to quieten some warnings. */
663 static int quiet_warnings = 0;
666 static const char *cpu_arch_name = NULL;
667 static char *cpu_sub_arch_name = NULL;
669 /* CPU feature flags. */
670 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
672 /* If we have selected a cpu we are generating instructions for. */
673 static int cpu_arch_tune_set = 0;
675 /* Cpu we are generating instructions for. */
676 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
678 /* CPU feature flags of cpu we are generating instructions for. */
679 static i386_cpu_flags cpu_arch_tune_flags;
681 /* CPU instruction set architecture used. */
682 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
684 /* CPU feature flags of instruction set architecture used. */
685 i386_cpu_flags cpu_arch_isa_flags;
687 /* If set, conditional jumps are not automatically promoted to handle
688 larger than a byte offset. */
689 static unsigned int no_cond_jump_promotion = 0;
691 /* Encode SSE instructions with VEX prefix. */
692 static unsigned int sse2avx;
694 /* Encode scalar AVX instructions with specific vector length. */
701 /* Encode VEX WIG instructions with specific vex.w. */
708 /* Encode scalar EVEX LIG instructions with specific vector length. */
716 /* Encode EVEX WIG instructions with specific evex.w. */
723 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
724 static enum rc_type evexrcig = rne;
726 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
727 static symbolS *GOT_symbol;
729 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
730 unsigned int x86_dwarf2_return_column;
732 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
733 int x86_cie_data_alignment;
735 /* Interface to relax_segment.
736 There are 3 major relax states for 386 jump insns because the
737 different types of jumps add different sizes to frags when we're
738 figuring out what sort of jump to choose to reach a given label. */
741 #define UNCOND_JUMP 0
743 #define COND_JUMP86 2
748 #define SMALL16 (SMALL | CODE16)
750 #define BIG16 (BIG | CODE16)
754 #define INLINE __inline__
760 #define ENCODE_RELAX_STATE(type, size) \
761 ((relax_substateT) (((type) << 2) | (size)))
762 #define TYPE_FROM_RELAX_STATE(s) \
764 #define DISP_SIZE_FROM_RELAX_STATE(s) \
765 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
767 /* This table is used by relax_frag to promote short jumps to long
768 ones where necessary. SMALL (short) jumps may be promoted to BIG
769 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
770 don't allow a short jump in a 32 bit code segment to be promoted to
771 a 16 bit offset jump because it's slower (requires data size
772 prefix), and doesn't work, unless the destination is in the bottom
773 64k of the code segment (The top 16 bits of eip are zeroed). */
775 const relax_typeS md_relax_table[] =
778 1) most positive reach of this state,
779 2) most negative reach of this state,
780 3) how many bytes this mode will have in the variable part of the frag
781 4) which index into the table to try if we can't fit into this one. */
783 /* UNCOND_JUMP states. */
784 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
785 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
786 /* dword jmp adds 4 bytes to frag:
787 0 extra opcode bytes, 4 displacement bytes. */
789 /* word jmp adds 2 byte2 to frag:
790 0 extra opcode bytes, 2 displacement bytes. */
793 /* COND_JUMP states. */
794 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
795 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
796 /* dword conditionals adds 5 bytes to frag:
797 1 extra opcode byte, 4 displacement bytes. */
799 /* word conditionals add 3 bytes to frag:
800 1 extra opcode byte, 2 displacement bytes. */
803 /* COND_JUMP86 states. */
804 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
805 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
806 /* dword conditionals adds 5 bytes to frag:
807 1 extra opcode byte, 4 displacement bytes. */
809 /* word conditionals add 4 bytes to frag:
810 1 displacement byte and a 3 byte long branch insn. */
814 static const arch_entry cpu_arch[] =
816 /* Do not replace the first two entries - i386_target_format()
817 relies on them being there in this order. */
818 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
819 CPU_GENERIC32_FLAGS, 0 },
820 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
821 CPU_GENERIC64_FLAGS, 0 },
822 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
824 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
826 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
828 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
830 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
832 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
834 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
836 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
838 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
839 CPU_PENTIUMPRO_FLAGS, 0 },
840 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
842 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
844 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
846 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
848 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
849 CPU_NOCONA_FLAGS, 0 },
850 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
852 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
854 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
855 CPU_CORE2_FLAGS, 1 },
856 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
857 CPU_CORE2_FLAGS, 0 },
858 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
859 CPU_COREI7_FLAGS, 0 },
860 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
862 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
864 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
865 CPU_IAMCU_FLAGS, 0 },
866 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
868 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
870 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
871 CPU_ATHLON_FLAGS, 0 },
872 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
874 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
876 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
878 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
879 CPU_AMDFAM10_FLAGS, 0 },
880 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
881 CPU_BDVER1_FLAGS, 0 },
882 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
883 CPU_BDVER2_FLAGS, 0 },
884 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
885 CPU_BDVER3_FLAGS, 0 },
886 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
887 CPU_BDVER4_FLAGS, 0 },
888 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
889 CPU_ZNVER1_FLAGS, 0 },
890 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
891 CPU_ZNVER2_FLAGS, 0 },
892 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
893 CPU_BTVER1_FLAGS, 0 },
894 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
895 CPU_BTVER2_FLAGS, 0 },
896 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
898 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
900 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
902 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
904 { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN,
908 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
912 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
914 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
916 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
917 CPU_SSSE3_FLAGS, 0 },
918 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
919 CPU_SSE4_1_FLAGS, 0 },
920 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
921 CPU_SSE4_2_FLAGS, 0 },
922 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
923 CPU_SSE4_2_FLAGS, 0 },
924 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
928 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
929 CPU_AVX512F_FLAGS, 0 },
930 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
931 CPU_AVX512CD_FLAGS, 0 },
932 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
933 CPU_AVX512ER_FLAGS, 0 },
934 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
935 CPU_AVX512PF_FLAGS, 0 },
936 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
937 CPU_AVX512DQ_FLAGS, 0 },
938 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
939 CPU_AVX512BW_FLAGS, 0 },
940 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
941 CPU_AVX512VL_FLAGS, 0 },
942 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
944 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
945 CPU_VMFUNC_FLAGS, 0 },
946 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
948 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
949 CPU_XSAVE_FLAGS, 0 },
950 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
951 CPU_XSAVEOPT_FLAGS, 0 },
952 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
953 CPU_XSAVEC_FLAGS, 0 },
954 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
955 CPU_XSAVES_FLAGS, 0 },
956 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
958 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
959 CPU_PCLMUL_FLAGS, 0 },
960 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
961 CPU_PCLMUL_FLAGS, 1 },
962 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
963 CPU_FSGSBASE_FLAGS, 0 },
964 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
965 CPU_RDRND_FLAGS, 0 },
966 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
968 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
970 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
976 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
978 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
979 CPU_MOVBE_FLAGS, 0 },
980 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
982 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
984 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
985 CPU_LZCNT_FLAGS, 0 },
986 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
988 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
990 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
991 CPU_INVPCID_FLAGS, 0 },
992 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
993 CPU_CLFLUSH_FLAGS, 0 },
994 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
996 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
997 CPU_SYSCALL_FLAGS, 0 },
998 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
999 CPU_RDTSCP_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
1001 CPU_3DNOW_FLAGS, 0 },
1002 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
1003 CPU_3DNOWA_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
1005 CPU_PADLOCK_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
1007 CPU_SVME_FLAGS, 1 },
1008 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
1009 CPU_SVME_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
1011 CPU_SSE4A_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
1014 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
1016 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
1018 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
1020 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
1021 CPU_RDSEED_FLAGS, 0 },
1022 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
1023 CPU_PRFCHW_FLAGS, 0 },
1024 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
1025 CPU_SMAP_FLAGS, 0 },
1026 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
1028 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
1030 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
1031 CPU_CLFLUSHOPT_FLAGS, 0 },
1032 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
1033 CPU_PREFETCHWT1_FLAGS, 0 },
1034 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
1036 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
1037 CPU_CLWB_FLAGS, 0 },
1038 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
1039 CPU_AVX512IFMA_FLAGS, 0 },
1040 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
1041 CPU_AVX512VBMI_FLAGS, 0 },
1042 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
1043 CPU_AVX512_4FMAPS_FLAGS, 0 },
1044 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
1045 CPU_AVX512_4VNNIW_FLAGS, 0 },
1046 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
1047 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
1048 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1049 CPU_AVX512_VBMI2_FLAGS, 0 },
1050 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1051 CPU_AVX512_VNNI_FLAGS, 0 },
1052 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1053 CPU_AVX512_BITALG_FLAGS, 0 },
1054 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
1055 CPU_CLZERO_FLAGS, 0 },
1056 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
1057 CPU_MWAITX_FLAGS, 0 },
1058 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
1059 CPU_OSPKE_FLAGS, 0 },
1060 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
1061 CPU_RDPID_FLAGS, 0 },
1062 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1063 CPU_PTWRITE_FLAGS, 0 },
1064 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1066 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1067 CPU_SHSTK_FLAGS, 0 },
1068 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1069 CPU_GFNI_FLAGS, 0 },
1070 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1071 CPU_VAES_FLAGS, 0 },
1072 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1073 CPU_VPCLMULQDQ_FLAGS, 0 },
1074 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1075 CPU_WBNOINVD_FLAGS, 0 },
1076 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1077 CPU_PCONFIG_FLAGS, 0 },
1078 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1079 CPU_WAITPKG_FLAGS, 0 },
1080 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1081 CPU_CLDEMOTE_FLAGS, 0 },
1082 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1083 CPU_MOVDIRI_FLAGS, 0 },
1084 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1085 CPU_MOVDIR64B_FLAGS, 0 },
1086 { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN,
1087 CPU_AVX512_BF16_FLAGS, 0 },
1088 { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN,
1089 CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
1090 { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
1091 CPU_ENQCMD_FLAGS, 0 },
1094 static const noarch_entry cpu_noarch[] =
1096 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1097 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1098 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1099 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1100 { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS },
1101 { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS },
1102 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1103 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1104 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1105 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1106 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1107 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1108 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1109 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1110 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1111 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1112 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1113 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1114 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1115 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1116 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1117 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1118 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1119 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1120 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1121 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1122 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1123 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1124 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1125 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1126 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1127 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1128 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1129 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1130 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
1131 { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
1132 { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
1133 { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
1137 /* Like s_lcomm_internal in gas/read.c but the alignment string
1138 is allowed to be optional. */
1141 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1148 && *input_line_pointer == ',')
1150 align = parse_align (needs_align - 1);
1152 if (align == (addressT) -1)
1167 bss_alloc (symbolP, size, align);
1172 pe_lcomm (int needs_align)
1174 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1178 const pseudo_typeS md_pseudo_table[] =
1180 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1181 {"align", s_align_bytes, 0},
1183 {"align", s_align_ptwo, 0},
1185 {"arch", set_cpu_arch, 0},
1189 {"lcomm", pe_lcomm, 1},
1191 {"ffloat", float_cons, 'f'},
1192 {"dfloat", float_cons, 'd'},
1193 {"tfloat", float_cons, 'x'},
1195 {"slong", signed_cons, 4},
1196 {"noopt", s_ignore, 0},
1197 {"optim", s_ignore, 0},
1198 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1199 {"code16", set_code_flag, CODE_16BIT},
1200 {"code32", set_code_flag, CODE_32BIT},
1202 {"code64", set_code_flag, CODE_64BIT},
1204 {"intel_syntax", set_intel_syntax, 1},
1205 {"att_syntax", set_intel_syntax, 0},
1206 {"intel_mnemonic", set_intel_mnemonic, 1},
1207 {"att_mnemonic", set_intel_mnemonic, 0},
1208 {"allow_index_reg", set_allow_index_reg, 1},
1209 {"disallow_index_reg", set_allow_index_reg, 0},
1210 {"sse_check", set_check, 0},
1211 {"operand_check", set_check, 1},
1212 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1213 {"largecomm", handle_large_common, 0},
1215 {"file", dwarf2_directive_file, 0},
1216 {"loc", dwarf2_directive_loc, 0},
1217 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1220 {"secrel32", pe_directive_secrel, 0},
1225 /* For interface with expression (). */
1226 extern char *input_line_pointer;
1228 /* Hash table for instruction mnemonic lookup. */
1229 static struct hash_control *op_hash;
1231 /* Hash table for register lookup. */
1232 static struct hash_control *reg_hash;
1234 /* Various efficient no-op patterns for aligning code labels.
1235 Note: Don't try to assemble the instructions in the comments.
1236 0L and 0w are not legal. */
1237 static const unsigned char f32_1[] =
1239 static const unsigned char f32_2[] =
1240 {0x66,0x90}; /* xchg %ax,%ax */
1241 static const unsigned char f32_3[] =
1242 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1243 static const unsigned char f32_4[] =
1244 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1245 static const unsigned char f32_6[] =
1246 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1247 static const unsigned char f32_7[] =
1248 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1249 static const unsigned char f16_3[] =
1250 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
1251 static const unsigned char f16_4[] =
1252 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1253 static const unsigned char jump_disp8[] =
1254 {0xeb}; /* jmp disp8 */
1255 static const unsigned char jump32_disp32[] =
1256 {0xe9}; /* jmp disp32 */
1257 static const unsigned char jump16_disp32[] =
1258 {0x66,0xe9}; /* jmp disp32 */
1259 /* 32-bit NOPs patterns. */
1260 static const unsigned char *const f32_patt[] = {
1261 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
1263 /* 16-bit NOPs patterns. */
1264 static const unsigned char *const f16_patt[] = {
1265 f32_1, f32_2, f16_3, f16_4
1267 /* nopl (%[re]ax) */
1268 static const unsigned char alt_3[] =
1270 /* nopl 0(%[re]ax) */
1271 static const unsigned char alt_4[] =
1272 {0x0f,0x1f,0x40,0x00};
1273 /* nopl 0(%[re]ax,%[re]ax,1) */
1274 static const unsigned char alt_5[] =
1275 {0x0f,0x1f,0x44,0x00,0x00};
1276 /* nopw 0(%[re]ax,%[re]ax,1) */
1277 static const unsigned char alt_6[] =
1278 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1279 /* nopl 0L(%[re]ax) */
1280 static const unsigned char alt_7[] =
1281 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1282 /* nopl 0L(%[re]ax,%[re]ax,1) */
1283 static const unsigned char alt_8[] =
1284 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1285 /* nopw 0L(%[re]ax,%[re]ax,1) */
1286 static const unsigned char alt_9[] =
1287 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1288 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1289 static const unsigned char alt_10[] =
1290 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1291 /* data16 nopw %cs:0L(%eax,%eax,1) */
1292 static const unsigned char alt_11[] =
1293 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1294 /* 32-bit and 64-bit NOPs patterns. */
1295 static const unsigned char *const alt_patt[] = {
1296 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1297 alt_9, alt_10, alt_11
1300 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1301 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1304 i386_output_nops (char *where, const unsigned char *const *patt,
1305 int count, int max_single_nop_size)
1308 /* Place the longer NOP first. */
1311 const unsigned char *nops;
1313 if (max_single_nop_size < 1)
1315 as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"),
1316 max_single_nop_size);
1320 nops = patt[max_single_nop_size - 1];
1322 /* Use the smaller one if the requsted one isn't available. */
1325 max_single_nop_size--;
1326 nops = patt[max_single_nop_size - 1];
1329 last = count % max_single_nop_size;
1332 for (offset = 0; offset < count; offset += max_single_nop_size)
1333 memcpy (where + offset, nops, max_single_nop_size);
1337 nops = patt[last - 1];
1340 /* Use the smaller one plus one-byte NOP if the needed one
1343 nops = patt[last - 1];
1344 memcpy (where + offset, nops, last);
1345 where[offset + last] = *patt[0];
1348 memcpy (where + offset, nops, last);
1353 fits_in_imm7 (offsetT num)
1355 return (num & 0x7f) == num;
1359 fits_in_imm31 (offsetT num)
1361 return (num & 0x7fffffff) == num;
1364 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1365 single NOP instruction LIMIT. */
1368 i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
1370 const unsigned char *const *patt = NULL;
1371 int max_single_nop_size;
1372 /* Maximum number of NOPs before switching to jump over NOPs. */
1373 int max_number_of_nops;
1375 switch (fragP->fr_type)
1384 /* We need to decide which NOP sequence to use for 32bit and
1385 64bit. When -mtune= is used:
1387 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1388 PROCESSOR_GENERIC32, f32_patt will be used.
1389 2. For the rest, alt_patt will be used.
1391 When -mtune= isn't used, alt_patt will be used if
1392 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1395 When -march= or .arch is used, we can't use anything beyond
1396 cpu_arch_isa_flags. */
1398 if (flag_code == CODE_16BIT)
1401 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1402 /* Limit number of NOPs to 2 in 16-bit mode. */
1403 max_number_of_nops = 2;
1407 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1409 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1410 switch (cpu_arch_tune)
1412 case PROCESSOR_UNKNOWN:
1413 /* We use cpu_arch_isa_flags to check if we SHOULD
1414 optimize with nops. */
1415 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1420 case PROCESSOR_PENTIUM4:
1421 case PROCESSOR_NOCONA:
1422 case PROCESSOR_CORE:
1423 case PROCESSOR_CORE2:
1424 case PROCESSOR_COREI7:
1425 case PROCESSOR_L1OM:
1426 case PROCESSOR_K1OM:
1427 case PROCESSOR_GENERIC64:
1429 case PROCESSOR_ATHLON:
1431 case PROCESSOR_AMDFAM10:
1433 case PROCESSOR_ZNVER:
1437 case PROCESSOR_I386:
1438 case PROCESSOR_I486:
1439 case PROCESSOR_PENTIUM:
1440 case PROCESSOR_PENTIUMPRO:
1441 case PROCESSOR_IAMCU:
1442 case PROCESSOR_GENERIC32:
1449 switch (fragP->tc_frag_data.tune)
1451 case PROCESSOR_UNKNOWN:
1452 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1453 PROCESSOR_UNKNOWN. */
1457 case PROCESSOR_I386:
1458 case PROCESSOR_I486:
1459 case PROCESSOR_PENTIUM:
1460 case PROCESSOR_IAMCU:
1462 case PROCESSOR_ATHLON:
1464 case PROCESSOR_AMDFAM10:
1466 case PROCESSOR_ZNVER:
1468 case PROCESSOR_GENERIC32:
1469 /* We use cpu_arch_isa_flags to check if we CAN optimize
1471 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1476 case PROCESSOR_PENTIUMPRO:
1477 case PROCESSOR_PENTIUM4:
1478 case PROCESSOR_NOCONA:
1479 case PROCESSOR_CORE:
1480 case PROCESSOR_CORE2:
1481 case PROCESSOR_COREI7:
1482 case PROCESSOR_L1OM:
1483 case PROCESSOR_K1OM:
1484 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1489 case PROCESSOR_GENERIC64:
1495 if (patt == f32_patt)
1497 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1498 /* Limit number of NOPs to 2 for older processors. */
1499 max_number_of_nops = 2;
1503 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1504 /* Limit number of NOPs to 7 for newer processors. */
1505 max_number_of_nops = 7;
1510 limit = max_single_nop_size;
1512 if (fragP->fr_type == rs_fill_nop)
1514 /* Output NOPs for .nop directive. */
1515 if (limit > max_single_nop_size)
1517 as_bad_where (fragP->fr_file, fragP->fr_line,
1518 _("invalid single nop size: %d "
1519 "(expect within [0, %d])"),
1520 limit, max_single_nop_size);
1525 fragP->fr_var = count;
1527 if ((count / max_single_nop_size) > max_number_of_nops)
1529 /* Generate jump over NOPs. */
1530 offsetT disp = count - 2;
1531 if (fits_in_imm7 (disp))
1533 /* Use "jmp disp8" if possible. */
1535 where[0] = jump_disp8[0];
1541 unsigned int size_of_jump;
1543 if (flag_code == CODE_16BIT)
1545 where[0] = jump16_disp32[0];
1546 where[1] = jump16_disp32[1];
1551 where[0] = jump32_disp32[0];
1555 count -= size_of_jump + 4;
1556 if (!fits_in_imm31 (count))
1558 as_bad_where (fragP->fr_file, fragP->fr_line,
1559 _("jump over nop padding out of range"));
1563 md_number_to_chars (where + size_of_jump, count, 4);
1564 where += size_of_jump + 4;
1568 /* Generate multiple NOPs. */
1569 i386_output_nops (where, patt, count, limit);
1573 operand_type_all_zero (const union i386_operand_type *x)
1575 switch (ARRAY_SIZE(x->array))
1586 return !x->array[0];
1593 operand_type_set (union i386_operand_type *x, unsigned int v)
1595 switch (ARRAY_SIZE(x->array))
1613 operand_type_equal (const union i386_operand_type *x,
1614 const union i386_operand_type *y)
1616 switch (ARRAY_SIZE(x->array))
1619 if (x->array[2] != y->array[2])
1623 if (x->array[1] != y->array[1])
1627 return x->array[0] == y->array[0];
1635 cpu_flags_all_zero (const union i386_cpu_flags *x)
1637 switch (ARRAY_SIZE(x->array))
1652 return !x->array[0];
1659 cpu_flags_equal (const union i386_cpu_flags *x,
1660 const union i386_cpu_flags *y)
1662 switch (ARRAY_SIZE(x->array))
1665 if (x->array[3] != y->array[3])
1669 if (x->array[2] != y->array[2])
1673 if (x->array[1] != y->array[1])
1677 return x->array[0] == y->array[0];
1685 cpu_flags_check_cpu64 (i386_cpu_flags f)
1687 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1688 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1691 static INLINE i386_cpu_flags
1692 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1694 switch (ARRAY_SIZE (x.array))
1697 x.array [3] &= y.array [3];
1700 x.array [2] &= y.array [2];
1703 x.array [1] &= y.array [1];
1706 x.array [0] &= y.array [0];
1714 static INLINE i386_cpu_flags
1715 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1717 switch (ARRAY_SIZE (x.array))
1720 x.array [3] |= y.array [3];
1723 x.array [2] |= y.array [2];
1726 x.array [1] |= y.array [1];
1729 x.array [0] |= y.array [0];
1737 static INLINE i386_cpu_flags
1738 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1740 switch (ARRAY_SIZE (x.array))
1743 x.array [3] &= ~y.array [3];
1746 x.array [2] &= ~y.array [2];
1749 x.array [1] &= ~y.array [1];
1752 x.array [0] &= ~y.array [0];
1760 #define CPU_FLAGS_ARCH_MATCH 0x1
1761 #define CPU_FLAGS_64BIT_MATCH 0x2
1763 #define CPU_FLAGS_PERFECT_MATCH \
1764 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
1766 /* Return CPU flags match bits. */
1769 cpu_flags_match (const insn_template *t)
1771 i386_cpu_flags x = t->cpu_flags;
1772 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1774 x.bitfield.cpu64 = 0;
1775 x.bitfield.cpuno64 = 0;
1777 if (cpu_flags_all_zero (&x))
1779 /* This instruction is available on all archs. */
1780 match |= CPU_FLAGS_ARCH_MATCH;
1784 /* This instruction is available only on some archs. */
1785 i386_cpu_flags cpu = cpu_arch_flags;
1787 /* AVX512VL is no standalone feature - match it and then strip it. */
1788 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1790 x.bitfield.cpuavx512vl = 0;
1792 cpu = cpu_flags_and (x, cpu);
1793 if (!cpu_flags_all_zero (&cpu))
1795 if (x.bitfield.cpuavx)
1797 /* We need to check a few extra flags with AVX. */
1798 if (cpu.bitfield.cpuavx
1799 && (!t->opcode_modifier.sse2avx || sse2avx)
1800 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1801 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1802 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1803 match |= CPU_FLAGS_ARCH_MATCH;
1805 else if (x.bitfield.cpuavx512f)
1807 /* We need to check a few extra flags with AVX512F. */
1808 if (cpu.bitfield.cpuavx512f
1809 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1810 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1811 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1812 match |= CPU_FLAGS_ARCH_MATCH;
1815 match |= CPU_FLAGS_ARCH_MATCH;
1821 static INLINE i386_operand_type
1822 operand_type_and (i386_operand_type x, i386_operand_type y)
1824 switch (ARRAY_SIZE (x.array))
1827 x.array [2] &= y.array [2];
1830 x.array [1] &= y.array [1];
1833 x.array [0] &= y.array [0];
1841 static INLINE i386_operand_type
1842 operand_type_and_not (i386_operand_type x, i386_operand_type y)
1844 switch (ARRAY_SIZE (x.array))
1847 x.array [2] &= ~y.array [2];
1850 x.array [1] &= ~y.array [1];
1853 x.array [0] &= ~y.array [0];
1861 static INLINE i386_operand_type
1862 operand_type_or (i386_operand_type x, i386_operand_type y)
1864 switch (ARRAY_SIZE (x.array))
1867 x.array [2] |= y.array [2];
1870 x.array [1] |= y.array [1];
1873 x.array [0] |= y.array [0];
1881 static INLINE i386_operand_type
1882 operand_type_xor (i386_operand_type x, i386_operand_type y)
1884 switch (ARRAY_SIZE (x.array))
1887 x.array [2] ^= y.array [2];
1890 x.array [1] ^= y.array [1];
1893 x.array [0] ^= y.array [0];
1901 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1902 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1903 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1904 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1905 static const i386_operand_type anydisp
1906 = OPERAND_TYPE_ANYDISP;
1907 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1908 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1909 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1910 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1911 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1912 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1913 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1914 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1915 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1916 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1917 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1928 operand_type_check (i386_operand_type t, enum operand_type c)
1933 return t.bitfield.reg;
1936 return (t.bitfield.imm8
1940 || t.bitfield.imm32s
1941 || t.bitfield.imm64);
1944 return (t.bitfield.disp8
1945 || t.bitfield.disp16
1946 || t.bitfield.disp32
1947 || t.bitfield.disp32s
1948 || t.bitfield.disp64);
1951 return (t.bitfield.disp8
1952 || t.bitfield.disp16
1953 || t.bitfield.disp32
1954 || t.bitfield.disp32s
1955 || t.bitfield.disp64
1956 || t.bitfield.baseindex);
1965 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
1966 between operand GIVEN and opeand WANTED for instruction template T. */
1969 match_operand_size (const insn_template *t, unsigned int wanted,
1972 return !((i.types[given].bitfield.byte
1973 && !t->operand_types[wanted].bitfield.byte)
1974 || (i.types[given].bitfield.word
1975 && !t->operand_types[wanted].bitfield.word)
1976 || (i.types[given].bitfield.dword
1977 && !t->operand_types[wanted].bitfield.dword)
1978 || (i.types[given].bitfield.qword
1979 && !t->operand_types[wanted].bitfield.qword)
1980 || (i.types[given].bitfield.tbyte
1981 && !t->operand_types[wanted].bitfield.tbyte));
1984 /* Return 1 if there is no conflict in SIMD register between operand
1985 GIVEN and opeand WANTED for instruction template T. */
1988 match_simd_size (const insn_template *t, unsigned int wanted,
1991 return !((i.types[given].bitfield.xmmword
1992 && !t->operand_types[wanted].bitfield.xmmword)
1993 || (i.types[given].bitfield.ymmword
1994 && !t->operand_types[wanted].bitfield.ymmword)
1995 || (i.types[given].bitfield.zmmword
1996 && !t->operand_types[wanted].bitfield.zmmword));
1999 /* Return 1 if there is no conflict in any size between operand GIVEN
2000 and opeand WANTED for instruction template T. */
2003 match_mem_size (const insn_template *t, unsigned int wanted,
2006 return (match_operand_size (t, wanted, given)
2007 && !((i.types[given].bitfield.unspecified
2009 && !t->operand_types[wanted].bitfield.unspecified)
2010 || (i.types[given].bitfield.fword
2011 && !t->operand_types[wanted].bitfield.fword)
2012 /* For scalar opcode templates to allow register and memory
2013 operands at the same time, some special casing is needed
2014 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2015 down-conversion vpmov*. */
2016 || ((t->operand_types[wanted].bitfield.regsimd
2017 && !t->opcode_modifier.broadcast
2018 && (t->operand_types[wanted].bitfield.byte
2019 || t->operand_types[wanted].bitfield.word
2020 || t->operand_types[wanted].bitfield.dword
2021 || t->operand_types[wanted].bitfield.qword))
2022 ? (i.types[given].bitfield.xmmword
2023 || i.types[given].bitfield.ymmword
2024 || i.types[given].bitfield.zmmword)
2025 : !match_simd_size(t, wanted, given))));
2028 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2029 operands for instruction template T, and it has MATCH_REVERSE set if there
2030 is no size conflict on any operands for the template with operands reversed
2031 (and the template allows for reversing in the first place). */
2033 #define MATCH_STRAIGHT 1
2034 #define MATCH_REVERSE 2
2036 static INLINE unsigned int
2037 operand_size_match (const insn_template *t)
2039 unsigned int j, match = MATCH_STRAIGHT;
2041 /* Don't check jump instructions. */
2042 if (t->opcode_modifier.jump
2043 || t->opcode_modifier.jumpbyte
2044 || t->opcode_modifier.jumpdword
2045 || t->opcode_modifier.jumpintersegment)
2048 /* Check memory and accumulator operand size. */
2049 for (j = 0; j < i.operands; j++)
2051 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
2052 && t->operand_types[j].bitfield.anysize)
2055 if (t->operand_types[j].bitfield.reg
2056 && !match_operand_size (t, j, j))
2062 if (t->operand_types[j].bitfield.regsimd
2063 && !match_simd_size (t, j, j))
2069 if (t->operand_types[j].bitfield.acc
2070 && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j)))
2076 if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j))
2083 if (!t->opcode_modifier.d)
2087 i.error = operand_size_mismatch;
2091 /* Check reverse. */
2092 gas_assert (i.operands >= 2 && i.operands <= 3);
2094 for (j = 0; j < i.operands; j++)
2096 unsigned int given = i.operands - j - 1;
2098 if (t->operand_types[j].bitfield.reg
2099 && !match_operand_size (t, j, given))
2102 if (t->operand_types[j].bitfield.regsimd
2103 && !match_simd_size (t, j, given))
2106 if (t->operand_types[j].bitfield.acc
2107 && (!match_operand_size (t, j, given)
2108 || !match_simd_size (t, j, given)))
2111 if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given))
2115 return match | MATCH_REVERSE;
2119 operand_type_match (i386_operand_type overlap,
2120 i386_operand_type given)
2122 i386_operand_type temp = overlap;
2124 temp.bitfield.jumpabsolute = 0;
2125 temp.bitfield.unspecified = 0;
2126 temp.bitfield.byte = 0;
2127 temp.bitfield.word = 0;
2128 temp.bitfield.dword = 0;
2129 temp.bitfield.fword = 0;
2130 temp.bitfield.qword = 0;
2131 temp.bitfield.tbyte = 0;
2132 temp.bitfield.xmmword = 0;
2133 temp.bitfield.ymmword = 0;
2134 temp.bitfield.zmmword = 0;
2135 if (operand_type_all_zero (&temp))
2138 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2139 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2143 i.error = operand_type_mismatch;
2147 /* If given types g0 and g1 are registers they must be of the same type
2148 unless the expected operand type register overlap is null.
2149 Memory operand size of certain SIMD instructions is also being checked
2153 operand_type_register_match (i386_operand_type g0,
2154 i386_operand_type t0,
2155 i386_operand_type g1,
2156 i386_operand_type t1)
2158 if (!g0.bitfield.reg
2159 && !g0.bitfield.regsimd
2160 && (!operand_type_check (g0, anymem)
2161 || g0.bitfield.unspecified
2162 || !t0.bitfield.regsimd))
2165 if (!g1.bitfield.reg
2166 && !g1.bitfield.regsimd
2167 && (!operand_type_check (g1, anymem)
2168 || g1.bitfield.unspecified
2169 || !t1.bitfield.regsimd))
2172 if (g0.bitfield.byte == g1.bitfield.byte
2173 && g0.bitfield.word == g1.bitfield.word
2174 && g0.bitfield.dword == g1.bitfield.dword
2175 && g0.bitfield.qword == g1.bitfield.qword
2176 && g0.bitfield.xmmword == g1.bitfield.xmmword
2177 && g0.bitfield.ymmword == g1.bitfield.ymmword
2178 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2181 if (!(t0.bitfield.byte & t1.bitfield.byte)
2182 && !(t0.bitfield.word & t1.bitfield.word)
2183 && !(t0.bitfield.dword & t1.bitfield.dword)
2184 && !(t0.bitfield.qword & t1.bitfield.qword)
2185 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2186 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2187 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2190 i.error = register_type_mismatch;
2195 static INLINE unsigned int
2196 register_number (const reg_entry *r)
2198 unsigned int nr = r->reg_num;
2200 if (r->reg_flags & RegRex)
2203 if (r->reg_flags & RegVRex)
2209 static INLINE unsigned int
2210 mode_from_disp_size (i386_operand_type t)
2212 if (t.bitfield.disp8)
2214 else if (t.bitfield.disp16
2215 || t.bitfield.disp32
2216 || t.bitfield.disp32s)
2223 fits_in_signed_byte (addressT num)
2225 return num + 0x80 <= 0xff;
2229 fits_in_unsigned_byte (addressT num)
2235 fits_in_unsigned_word (addressT num)
2237 return num <= 0xffff;
2241 fits_in_signed_word (addressT num)
2243 return num + 0x8000 <= 0xffff;
2247 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2252 return num + 0x80000000 <= 0xffffffff;
2254 } /* fits_in_signed_long() */
2257 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2262 return num <= 0xffffffff;
2264 } /* fits_in_unsigned_long() */
2267 fits_in_disp8 (offsetT num)
2269 int shift = i.memshift;
2275 mask = (1 << shift) - 1;
2277 /* Return 0 if NUM isn't properly aligned. */
2281 /* Check if NUM will fit in 8bit after shift. */
2282 return fits_in_signed_byte (num >> shift);
2286 fits_in_imm4 (offsetT num)
2288 return (num & 0xf) == num;
2291 static i386_operand_type
2292 smallest_imm_type (offsetT num)
2294 i386_operand_type t;
2296 operand_type_set (&t, 0);
2297 t.bitfield.imm64 = 1;
2299 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2301 /* This code is disabled on the 486 because all the Imm1 forms
2302 in the opcode table are slower on the i486. They're the
2303 versions with the implicitly specified single-position
2304 displacement, which has another syntax if you really want to
2306 t.bitfield.imm1 = 1;
2307 t.bitfield.imm8 = 1;
2308 t.bitfield.imm8s = 1;
2309 t.bitfield.imm16 = 1;
2310 t.bitfield.imm32 = 1;
2311 t.bitfield.imm32s = 1;
2313 else if (fits_in_signed_byte (num))
2315 t.bitfield.imm8 = 1;
2316 t.bitfield.imm8s = 1;
2317 t.bitfield.imm16 = 1;
2318 t.bitfield.imm32 = 1;
2319 t.bitfield.imm32s = 1;
2321 else if (fits_in_unsigned_byte (num))
2323 t.bitfield.imm8 = 1;
2324 t.bitfield.imm16 = 1;
2325 t.bitfield.imm32 = 1;
2326 t.bitfield.imm32s = 1;
2328 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2330 t.bitfield.imm16 = 1;
2331 t.bitfield.imm32 = 1;
2332 t.bitfield.imm32s = 1;
2334 else if (fits_in_signed_long (num))
2336 t.bitfield.imm32 = 1;
2337 t.bitfield.imm32s = 1;
2339 else if (fits_in_unsigned_long (num))
2340 t.bitfield.imm32 = 1;
2346 offset_in_range (offsetT val, int size)
2352 case 1: mask = ((addressT) 1 << 8) - 1; break;
2353 case 2: mask = ((addressT) 1 << 16) - 1; break;
2354 case 4: mask = ((addressT) 2 << 31) - 1; break;
2356 case 8: mask = ((addressT) 2 << 63) - 1; break;
2362 /* If BFD64, sign extend val for 32bit address mode. */
2363 if (flag_code != CODE_64BIT
2364 || i.prefix[ADDR_PREFIX])
2365 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2366 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2369 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2371 char buf1[40], buf2[40];
2373 sprint_value (buf1, val);
2374 sprint_value (buf2, val & mask);
2375 as_warn (_("%s shortened to %s"), buf1, buf2);
2390 a. PREFIX_EXIST if attempting to add a prefix where one from the
2391 same class already exists.
2392 b. PREFIX_LOCK if lock prefix is added.
2393 c. PREFIX_REP if rep/repne prefix is added.
2394 d. PREFIX_DS if ds prefix is added.
2395 e. PREFIX_OTHER if other prefix is added.
2398 static enum PREFIX_GROUP
2399 add_prefix (unsigned int prefix)
2401 enum PREFIX_GROUP ret = PREFIX_OTHER;
2404 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2405 && flag_code == CODE_64BIT)
2407 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2408 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2409 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2410 || (i.prefix[REX_PREFIX] & prefix & REX_B))
2421 case DS_PREFIX_OPCODE:
2424 case CS_PREFIX_OPCODE:
2425 case ES_PREFIX_OPCODE:
2426 case FS_PREFIX_OPCODE:
2427 case GS_PREFIX_OPCODE:
2428 case SS_PREFIX_OPCODE:
2432 case REPNE_PREFIX_OPCODE:
2433 case REPE_PREFIX_OPCODE:
2438 case LOCK_PREFIX_OPCODE:
2447 case ADDR_PREFIX_OPCODE:
2451 case DATA_PREFIX_OPCODE:
2455 if (i.prefix[q] != 0)
2463 i.prefix[q] |= prefix;
2466 as_bad (_("same type of prefix used twice"));
2472 update_code_flag (int value, int check)
2474 PRINTF_LIKE ((*as_error));
2476 flag_code = (enum flag_code) value;
2477 if (flag_code == CODE_64BIT)
2479 cpu_arch_flags.bitfield.cpu64 = 1;
2480 cpu_arch_flags.bitfield.cpuno64 = 0;
2484 cpu_arch_flags.bitfield.cpu64 = 0;
2485 cpu_arch_flags.bitfield.cpuno64 = 1;
2487 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2490 as_error = as_fatal;
2493 (*as_error) (_("64bit mode not supported on `%s'."),
2494 cpu_arch_name ? cpu_arch_name : default_arch);
2496 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2499 as_error = as_fatal;
2502 (*as_error) (_("32bit mode not supported on `%s'."),
2503 cpu_arch_name ? cpu_arch_name : default_arch);
2505 stackop_size = '\0';
2509 set_code_flag (int value)
2511 update_code_flag (value, 0);
2515 set_16bit_gcc_code_flag (int new_code_flag)
2517 flag_code = (enum flag_code) new_code_flag;
2518 if (flag_code != CODE_16BIT)
2520 cpu_arch_flags.bitfield.cpu64 = 0;
2521 cpu_arch_flags.bitfield.cpuno64 = 1;
2522 stackop_size = LONG_MNEM_SUFFIX;
2526 set_intel_syntax (int syntax_flag)
2528 /* Find out if register prefixing is specified. */
2529 int ask_naked_reg = 0;
2532 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2535 int e = get_symbol_name (&string);
2537 if (strcmp (string, "prefix") == 0)
2539 else if (strcmp (string, "noprefix") == 0)
2542 as_bad (_("bad argument to syntax directive."));
2543 (void) restore_line_pointer (e);
2545 demand_empty_rest_of_line ();
2547 intel_syntax = syntax_flag;
2549 if (ask_naked_reg == 0)
2550 allow_naked_reg = (intel_syntax
2551 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2553 allow_naked_reg = (ask_naked_reg < 0);
2555 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2557 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2558 identifier_chars['$'] = intel_syntax ? '$' : 0;
2559 register_prefix = allow_naked_reg ? "" : "%";
2563 set_intel_mnemonic (int mnemonic_flag)
2565 intel_mnemonic = mnemonic_flag;
2569 set_allow_index_reg (int flag)
2571 allow_index_reg = flag;
2575 set_check (int what)
2577 enum check_kind *kind;
2582 kind = &operand_check;
2593 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2596 int e = get_symbol_name (&string);
2598 if (strcmp (string, "none") == 0)
2600 else if (strcmp (string, "warning") == 0)
2601 *kind = check_warning;
2602 else if (strcmp (string, "error") == 0)
2603 *kind = check_error;
2605 as_bad (_("bad argument to %s_check directive."), str);
2606 (void) restore_line_pointer (e);
2609 as_bad (_("missing argument for %s_check directive"), str);
2611 demand_empty_rest_of_line ();
2615 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2616 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2618 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2619 static const char *arch;
2621 /* Intel LIOM is only supported on ELF. */
2627 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2628 use default_arch. */
2629 arch = cpu_arch_name;
2631 arch = default_arch;
2634 /* If we are targeting Intel MCU, we must enable it. */
2635 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2636 || new_flag.bitfield.cpuiamcu)
2639 /* If we are targeting Intel L1OM, we must enable it. */
2640 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2641 || new_flag.bitfield.cpul1om)
2644 /* If we are targeting Intel K1OM, we must enable it. */
2645 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2646 || new_flag.bitfield.cpuk1om)
2649 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2654 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2658 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2661 int e = get_symbol_name (&string);
2663 i386_cpu_flags flags;
2665 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2667 if (strcmp (string, cpu_arch[j].name) == 0)
2669 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2673 cpu_arch_name = cpu_arch[j].name;
2674 cpu_sub_arch_name = NULL;
2675 cpu_arch_flags = cpu_arch[j].flags;
2676 if (flag_code == CODE_64BIT)
2678 cpu_arch_flags.bitfield.cpu64 = 1;
2679 cpu_arch_flags.bitfield.cpuno64 = 0;
2683 cpu_arch_flags.bitfield.cpu64 = 0;
2684 cpu_arch_flags.bitfield.cpuno64 = 1;
2686 cpu_arch_isa = cpu_arch[j].type;
2687 cpu_arch_isa_flags = cpu_arch[j].flags;
2688 if (!cpu_arch_tune_set)
2690 cpu_arch_tune = cpu_arch_isa;
2691 cpu_arch_tune_flags = cpu_arch_isa_flags;
2696 flags = cpu_flags_or (cpu_arch_flags,
2699 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2701 if (cpu_sub_arch_name)
2703 char *name = cpu_sub_arch_name;
2704 cpu_sub_arch_name = concat (name,
2706 (const char *) NULL);
2710 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2711 cpu_arch_flags = flags;
2712 cpu_arch_isa_flags = flags;
2716 = cpu_flags_or (cpu_arch_isa_flags,
2718 (void) restore_line_pointer (e);
2719 demand_empty_rest_of_line ();
2724 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2726 /* Disable an ISA extension. */
2727 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2728 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2730 flags = cpu_flags_and_not (cpu_arch_flags,
2731 cpu_noarch[j].flags);
2732 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2734 if (cpu_sub_arch_name)
2736 char *name = cpu_sub_arch_name;
2737 cpu_sub_arch_name = concat (name, string,
2738 (const char *) NULL);
2742 cpu_sub_arch_name = xstrdup (string);
2743 cpu_arch_flags = flags;
2744 cpu_arch_isa_flags = flags;
2746 (void) restore_line_pointer (e);
2747 demand_empty_rest_of_line ();
2751 j = ARRAY_SIZE (cpu_arch);
2754 if (j >= ARRAY_SIZE (cpu_arch))
2755 as_bad (_("no such architecture: `%s'"), string);
2757 *input_line_pointer = e;
2760 as_bad (_("missing cpu architecture"));
2762 no_cond_jump_promotion = 0;
2763 if (*input_line_pointer == ','
2764 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2769 ++input_line_pointer;
2770 e = get_symbol_name (&string);
2772 if (strcmp (string, "nojumps") == 0)
2773 no_cond_jump_promotion = 1;
2774 else if (strcmp (string, "jumps") == 0)
2777 as_bad (_("no such architecture modifier: `%s'"), string);
2779 (void) restore_line_pointer (e);
2782 demand_empty_rest_of_line ();
2785 enum bfd_architecture
2788 if (cpu_arch_isa == PROCESSOR_L1OM)
2790 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2791 || flag_code != CODE_64BIT)
2792 as_fatal (_("Intel L1OM is 64bit ELF only"));
2793 return bfd_arch_l1om;
2795 else if (cpu_arch_isa == PROCESSOR_K1OM)
2797 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2798 || flag_code != CODE_64BIT)
2799 as_fatal (_("Intel K1OM is 64bit ELF only"));
2800 return bfd_arch_k1om;
2802 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2804 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2805 || flag_code == CODE_64BIT)
2806 as_fatal (_("Intel MCU is 32bit ELF only"));
2807 return bfd_arch_iamcu;
2810 return bfd_arch_i386;
2816 if (!strncmp (default_arch, "x86_64", 6))
2818 if (cpu_arch_isa == PROCESSOR_L1OM)
2820 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2821 || default_arch[6] != '\0')
2822 as_fatal (_("Intel L1OM is 64bit ELF only"));
2823 return bfd_mach_l1om;
2825 else if (cpu_arch_isa == PROCESSOR_K1OM)
2827 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2828 || default_arch[6] != '\0')
2829 as_fatal (_("Intel K1OM is 64bit ELF only"));
2830 return bfd_mach_k1om;
2832 else if (default_arch[6] == '\0')
2833 return bfd_mach_x86_64;
2835 return bfd_mach_x64_32;
2837 else if (!strcmp (default_arch, "i386")
2838 || !strcmp (default_arch, "iamcu"))
2840 if (cpu_arch_isa == PROCESSOR_IAMCU)
2842 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2843 as_fatal (_("Intel MCU is 32bit ELF only"));
2844 return bfd_mach_i386_iamcu;
2847 return bfd_mach_i386_i386;
2850 as_fatal (_("unknown architecture"));
2856 const char *hash_err;
2858 /* Support pseudo prefixes like {disp32}. */
2859 lex_type ['{'] = LEX_BEGIN_NAME;
2861 /* Initialize op_hash hash table. */
2862 op_hash = hash_new ();
2865 const insn_template *optab;
2866 templates *core_optab;
2868 /* Setup for loop. */
2870 core_optab = XNEW (templates);
2871 core_optab->start = optab;
2876 if (optab->name == NULL
2877 || strcmp (optab->name, (optab - 1)->name) != 0)
2879 /* different name --> ship out current template list;
2880 add to hash table; & begin anew. */
2881 core_optab->end = optab;
2882 hash_err = hash_insert (op_hash,
2884 (void *) core_optab);
2887 as_fatal (_("can't hash %s: %s"),
2891 if (optab->name == NULL)
2893 core_optab = XNEW (templates);
2894 core_optab->start = optab;
2899 /* Initialize reg_hash hash table. */
2900 reg_hash = hash_new ();
2902 const reg_entry *regtab;
2903 unsigned int regtab_size = i386_regtab_size;
2905 for (regtab = i386_regtab; regtab_size--; regtab++)
2907 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2909 as_fatal (_("can't hash %s: %s"),
2915 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2920 for (c = 0; c < 256; c++)
2925 mnemonic_chars[c] = c;
2926 register_chars[c] = c;
2927 operand_chars[c] = c;
2929 else if (ISLOWER (c))
2931 mnemonic_chars[c] = c;
2932 register_chars[c] = c;
2933 operand_chars[c] = c;
2935 else if (ISUPPER (c))
2937 mnemonic_chars[c] = TOLOWER (c);
2938 register_chars[c] = mnemonic_chars[c];
2939 operand_chars[c] = c;
2941 else if (c == '{' || c == '}')
2943 mnemonic_chars[c] = c;
2944 operand_chars[c] = c;
2947 if (ISALPHA (c) || ISDIGIT (c))
2948 identifier_chars[c] = c;
2951 identifier_chars[c] = c;
2952 operand_chars[c] = c;
2957 identifier_chars['@'] = '@';
2960 identifier_chars['?'] = '?';
2961 operand_chars['?'] = '?';
2963 digit_chars['-'] = '-';
2964 mnemonic_chars['_'] = '_';
2965 mnemonic_chars['-'] = '-';
2966 mnemonic_chars['.'] = '.';
2967 identifier_chars['_'] = '_';
2968 identifier_chars['.'] = '.';
2970 for (p = operand_special_chars; *p != '\0'; p++)
2971 operand_chars[(unsigned char) *p] = *p;
2974 if (flag_code == CODE_64BIT)
2976 #if defined (OBJ_COFF) && defined (TE_PE)
2977 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2980 x86_dwarf2_return_column = 16;
2982 x86_cie_data_alignment = -8;
2986 x86_dwarf2_return_column = 8;
2987 x86_cie_data_alignment = -4;
2992 i386_print_statistics (FILE *file)
2994 hash_print_statistics (file, "i386 opcode", op_hash);
2995 hash_print_statistics (file, "i386 register", reg_hash);
3000 /* Debugging routines for md_assemble. */
3001 static void pte (insn_template *);
3002 static void pt (i386_operand_type);
3003 static void pe (expressionS *);
3004 static void ps (symbolS *);
3007 pi (const char *line, i386_insn *x)
3011 fprintf (stdout, "%s: template ", line);
3013 fprintf (stdout, " address: base %s index %s scale %x\n",
3014 x->base_reg ? x->base_reg->reg_name : "none",
3015 x->index_reg ? x->index_reg->reg_name : "none",
3016 x->log2_scale_factor);
3017 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
3018 x->rm.mode, x->rm.reg, x->rm.regmem);
3019 fprintf (stdout, " sib: base %x index %x scale %x\n",
3020 x->sib.base, x->sib.index, x->sib.scale);
3021 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
3022 (x->rex & REX_W) != 0,
3023 (x->rex & REX_R) != 0,
3024 (x->rex & REX_X) != 0,
3025 (x->rex & REX_B) != 0);
3026 for (j = 0; j < x->operands; j++)
3028 fprintf (stdout, " #%d: ", j + 1);
3030 fprintf (stdout, "\n");
3031 if (x->types[j].bitfield.reg
3032 || x->types[j].bitfield.regmmx
3033 || x->types[j].bitfield.regsimd
3034 || x->types[j].bitfield.sreg2
3035 || x->types[j].bitfield.sreg3
3036 || x->types[j].bitfield.control
3037 || x->types[j].bitfield.debug
3038 || x->types[j].bitfield.test)
3039 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
3040 if (operand_type_check (x->types[j], imm))
3042 if (operand_type_check (x->types[j], disp))
3043 pe (x->op[j].disps);
3048 pte (insn_template *t)
3051 fprintf (stdout, " %d operands ", t->operands);
3052 fprintf (stdout, "opcode %x ", t->base_opcode);
3053 if (t->extension_opcode != None)
3054 fprintf (stdout, "ext %x ", t->extension_opcode);
3055 if (t->opcode_modifier.d)
3056 fprintf (stdout, "D");
3057 if (t->opcode_modifier.w)
3058 fprintf (stdout, "W");
3059 fprintf (stdout, "\n");
3060 for (j = 0; j < t->operands; j++)
3062 fprintf (stdout, " #%d type ", j + 1);
3063 pt (t->operand_types[j]);
3064 fprintf (stdout, "\n");
3071 fprintf (stdout, " operation %d\n", e->X_op);
3072 fprintf (stdout, " add_number %ld (%lx)\n",
3073 (long) e->X_add_number, (long) e->X_add_number);
3074 if (e->X_add_symbol)
3076 fprintf (stdout, " add_symbol ");
3077 ps (e->X_add_symbol);
3078 fprintf (stdout, "\n");
3082 fprintf (stdout, " op_symbol ");
3083 ps (e->X_op_symbol);
3084 fprintf (stdout, "\n");
3091 fprintf (stdout, "%s type %s%s",
3093 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3094 segment_name (S_GET_SEGMENT (s)));
3097 static struct type_name
3099 i386_operand_type mask;
3102 const type_names[] =
3104 { OPERAND_TYPE_REG8, "r8" },
3105 { OPERAND_TYPE_REG16, "r16" },
3106 { OPERAND_TYPE_REG32, "r32" },
3107 { OPERAND_TYPE_REG64, "r64" },
3108 { OPERAND_TYPE_ACC8, "acc8" },
3109 { OPERAND_TYPE_ACC16, "acc16" },
3110 { OPERAND_TYPE_ACC32, "acc32" },
3111 { OPERAND_TYPE_ACC64, "acc64" },
3112 { OPERAND_TYPE_IMM8, "i8" },
3113 { OPERAND_TYPE_IMM8, "i8s" },
3114 { OPERAND_TYPE_IMM16, "i16" },
3115 { OPERAND_TYPE_IMM32, "i32" },
3116 { OPERAND_TYPE_IMM32S, "i32s" },
3117 { OPERAND_TYPE_IMM64, "i64" },
3118 { OPERAND_TYPE_IMM1, "i1" },
3119 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3120 { OPERAND_TYPE_DISP8, "d8" },
3121 { OPERAND_TYPE_DISP16, "d16" },
3122 { OPERAND_TYPE_DISP32, "d32" },
3123 { OPERAND_TYPE_DISP32S, "d32s" },
3124 { OPERAND_TYPE_DISP64, "d64" },
3125 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3126 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3127 { OPERAND_TYPE_CONTROL, "control reg" },
3128 { OPERAND_TYPE_TEST, "test reg" },
3129 { OPERAND_TYPE_DEBUG, "debug reg" },
3130 { OPERAND_TYPE_FLOATREG, "FReg" },
3131 { OPERAND_TYPE_FLOATACC, "FAcc" },
3132 { OPERAND_TYPE_SREG2, "SReg2" },
3133 { OPERAND_TYPE_SREG3, "SReg3" },
3134 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3135 { OPERAND_TYPE_REGMMX, "rMMX" },
3136 { OPERAND_TYPE_REGXMM, "rXMM" },
3137 { OPERAND_TYPE_REGYMM, "rYMM" },
3138 { OPERAND_TYPE_REGZMM, "rZMM" },
3139 { OPERAND_TYPE_REGMASK, "Mask reg" },
3140 { OPERAND_TYPE_ESSEG, "es" },
3144 pt (i386_operand_type t)
3147 i386_operand_type a;
3149 for (j = 0; j < ARRAY_SIZE (type_names); j++)
3151 a = operand_type_and (t, type_names[j].mask);
3152 if (operand_type_equal (&a, &type_names[j].mask))
3153 fprintf (stdout, "%s, ", type_names[j].name);
3158 #endif /* DEBUG386 */
3160 static bfd_reloc_code_real_type
3161 reloc (unsigned int size,
3164 bfd_reloc_code_real_type other)
3166 if (other != NO_RELOC)
3168 reloc_howto_type *rel;
3173 case BFD_RELOC_X86_64_GOT32:
3174 return BFD_RELOC_X86_64_GOT64;
3176 case BFD_RELOC_X86_64_GOTPLT64:
3177 return BFD_RELOC_X86_64_GOTPLT64;
3179 case BFD_RELOC_X86_64_PLTOFF64:
3180 return BFD_RELOC_X86_64_PLTOFF64;
3182 case BFD_RELOC_X86_64_GOTPC32:
3183 other = BFD_RELOC_X86_64_GOTPC64;
3185 case BFD_RELOC_X86_64_GOTPCREL:
3186 other = BFD_RELOC_X86_64_GOTPCREL64;
3188 case BFD_RELOC_X86_64_TPOFF32:
3189 other = BFD_RELOC_X86_64_TPOFF64;
3191 case BFD_RELOC_X86_64_DTPOFF32:
3192 other = BFD_RELOC_X86_64_DTPOFF64;
3198 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3199 if (other == BFD_RELOC_SIZE32)
3202 other = BFD_RELOC_SIZE64;
3205 as_bad (_("there are no pc-relative size relocations"));
3211 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3212 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3215 rel = bfd_reloc_type_lookup (stdoutput, other);
3217 as_bad (_("unknown relocation (%u)"), other);
3218 else if (size != bfd_get_reloc_size (rel))
3219 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3220 bfd_get_reloc_size (rel),
3222 else if (pcrel && !rel->pc_relative)
3223 as_bad (_("non-pc-relative relocation for pc-relative field"));
3224 else if ((rel->complain_on_overflow == complain_overflow_signed
3226 || (rel->complain_on_overflow == complain_overflow_unsigned
3228 as_bad (_("relocated field and relocation type differ in signedness"));
3237 as_bad (_("there are no unsigned pc-relative relocations"));
3240 case 1: return BFD_RELOC_8_PCREL;
3241 case 2: return BFD_RELOC_16_PCREL;
3242 case 4: return BFD_RELOC_32_PCREL;
3243 case 8: return BFD_RELOC_64_PCREL;
3245 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3252 case 4: return BFD_RELOC_X86_64_32S;
3257 case 1: return BFD_RELOC_8;
3258 case 2: return BFD_RELOC_16;
3259 case 4: return BFD_RELOC_32;
3260 case 8: return BFD_RELOC_64;
3262 as_bad (_("cannot do %s %u byte relocation"),
3263 sign > 0 ? "signed" : "unsigned", size);
3269 /* Here we decide which fixups can be adjusted to make them relative to
3270 the beginning of the section instead of the symbol. Basically we need
3271 to make sure that the dynamic relocations are done correctly, so in
3272 some cases we force the original symbol to be used. */
3275 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3277 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3281 /* Don't adjust pc-relative references to merge sections in 64-bit
3283 if (use_rela_relocations
3284 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3288 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3289 and changed later by validate_fix. */
3290 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3291 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3294 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3295 for size relocations. */
3296 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3297 || fixP->fx_r_type == BFD_RELOC_SIZE64
3298 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3299 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3300 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3301 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3302 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3303 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3304 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3305 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3306 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3307 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3308 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3309 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3310 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3311 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3312 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3313 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3314 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3315 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3316 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3317 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3318 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3319 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3320 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3321 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3322 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3323 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3324 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3325 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3326 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3327 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3328 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3335 intel_float_operand (const char *mnemonic)
3337 /* Note that the value returned is meaningful only for opcodes with (memory)
3338 operands, hence the code here is free to improperly handle opcodes that
3339 have no operands (for better performance and smaller code). */
3341 if (mnemonic[0] != 'f')
3342 return 0; /* non-math */
3344 switch (mnemonic[1])
3346 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3347 the fs segment override prefix not currently handled because no
3348 call path can make opcodes without operands get here */
3350 return 2 /* integer op */;
3352 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3353 return 3; /* fldcw/fldenv */
3356 if (mnemonic[2] != 'o' /* fnop */)
3357 return 3; /* non-waiting control op */
3360 if (mnemonic[2] == 's')
3361 return 3; /* frstor/frstpm */
3364 if (mnemonic[2] == 'a')
3365 return 3; /* fsave */
3366 if (mnemonic[2] == 't')
3368 switch (mnemonic[3])
3370 case 'c': /* fstcw */
3371 case 'd': /* fstdw */
3372 case 'e': /* fstenv */
3373 case 's': /* fsts[gw] */
3379 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3380 return 0; /* fxsave/fxrstor are not really math ops */
3387 /* Build the VEX prefix. */
3390 build_vex_prefix (const insn_template *t)
3392 unsigned int register_specifier;
3393 unsigned int implied_prefix;
3394 unsigned int vector_length;
3397 /* Check register specifier. */
3398 if (i.vex.register_specifier)
3400 register_specifier =
3401 ~register_number (i.vex.register_specifier) & 0xf;
3402 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3405 register_specifier = 0xf;
3407 /* Use 2-byte VEX prefix by swapping destination and source operand
3408 if there are more than 1 register operand. */
3409 if (i.reg_operands > 1
3410 && i.vec_encoding != vex_encoding_vex3
3411 && i.dir_encoding == dir_encoding_default
3412 && i.operands == i.reg_operands
3413 && operand_type_equal (&i.types[0], &i.types[i.operands - 1])
3414 && i.tm.opcode_modifier.vexopcode == VEX0F
3415 && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d)
3418 unsigned int xchg = i.operands - 1;
3419 union i386_op temp_op;
3420 i386_operand_type temp_type;
3422 temp_type = i.types[xchg];
3423 i.types[xchg] = i.types[0];
3424 i.types[0] = temp_type;
3425 temp_op = i.op[xchg];
3426 i.op[xchg] = i.op[0];
3429 gas_assert (i.rm.mode == 3);
3433 i.rm.regmem = i.rm.reg;
3436 if (i.tm.opcode_modifier.d)
3437 i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e
3438 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
3439 else /* Use the next insn. */
3443 /* Use 2-byte VEX prefix by swapping commutative source operands if there
3444 are no memory operands and at least 3 register ones. */
3445 if (i.reg_operands >= 3
3446 && i.vec_encoding != vex_encoding_vex3
3447 && i.reg_operands == i.operands - i.imm_operands
3448 && i.tm.opcode_modifier.vex
3449 && i.tm.opcode_modifier.commutative
3450 && (i.tm.opcode_modifier.sse2avx || optimize > 1)
3452 && i.vex.register_specifier
3453 && !(i.vex.register_specifier->reg_flags & RegRex))
3455 unsigned int xchg = i.operands - i.reg_operands;
3456 union i386_op temp_op;
3457 i386_operand_type temp_type;
3459 gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F);
3460 gas_assert (!i.tm.opcode_modifier.sae);
3461 gas_assert (operand_type_equal (&i.types[i.operands - 2],
3462 &i.types[i.operands - 3]));
3463 gas_assert (i.rm.mode == 3);
3465 temp_type = i.types[xchg];
3466 i.types[xchg] = i.types[xchg + 1];
3467 i.types[xchg + 1] = temp_type;
3468 temp_op = i.op[xchg];
3469 i.op[xchg] = i.op[xchg + 1];
3470 i.op[xchg + 1] = temp_op;
3473 xchg = i.rm.regmem | 8;
3474 i.rm.regmem = ~register_specifier & 0xf;
3475 gas_assert (!(i.rm.regmem & 8));
3476 i.vex.register_specifier += xchg - i.rm.regmem;
3477 register_specifier = ~xchg & 0xf;
3480 if (i.tm.opcode_modifier.vex == VEXScalar)
3481 vector_length = avxscalar;
3482 else if (i.tm.opcode_modifier.vex == VEX256)
3488 /* Determine vector length from the last multi-length vector
3491 for (op = t->operands; op--;)
3492 if (t->operand_types[op].bitfield.xmmword
3493 && t->operand_types[op].bitfield.ymmword
3494 && i.types[op].bitfield.ymmword)
3501 switch ((i.tm.base_opcode >> 8) & 0xff)
3506 case DATA_PREFIX_OPCODE:
3509 case REPE_PREFIX_OPCODE:
3512 case REPNE_PREFIX_OPCODE:
3519 /* Check the REX.W bit and VEXW. */
3520 if (i.tm.opcode_modifier.vexw == VEXWIG)
3521 w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0;
3522 else if (i.tm.opcode_modifier.vexw)
3523 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3525 w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0;
3527 /* Use 2-byte VEX prefix if possible. */
3529 && i.vec_encoding != vex_encoding_vex3
3530 && i.tm.opcode_modifier.vexopcode == VEX0F
3531 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3533 /* 2-byte VEX prefix. */
3537 i.vex.bytes[0] = 0xc5;
3539 /* Check the REX.R bit. */
3540 r = (i.rex & REX_R) ? 0 : 1;
3541 i.vex.bytes[1] = (r << 7
3542 | register_specifier << 3
3543 | vector_length << 2
3548 /* 3-byte VEX prefix. */
3553 switch (i.tm.opcode_modifier.vexopcode)
3557 i.vex.bytes[0] = 0xc4;
3561 i.vex.bytes[0] = 0xc4;
3565 i.vex.bytes[0] = 0xc4;
3569 i.vex.bytes[0] = 0x8f;
3573 i.vex.bytes[0] = 0x8f;
3577 i.vex.bytes[0] = 0x8f;
3583 /* The high 3 bits of the second VEX byte are 1's compliment
3584 of RXB bits from REX. */
3585 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3587 i.vex.bytes[2] = (w << 7
3588 | register_specifier << 3
3589 | vector_length << 2
3594 static INLINE bfd_boolean
3595 is_evex_encoding (const insn_template *t)
3597 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
3598 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3599 || t->opcode_modifier.sae;
3602 static INLINE bfd_boolean
3603 is_any_vex_encoding (const insn_template *t)
3605 return t->opcode_modifier.vex || t->opcode_modifier.vexopcode
3606 || is_evex_encoding (t);
3609 /* Build the EVEX prefix. */
3612 build_evex_prefix (void)
3614 unsigned int register_specifier;
3615 unsigned int implied_prefix;
3617 rex_byte vrex_used = 0;
3619 /* Check register specifier. */
3620 if (i.vex.register_specifier)
3622 gas_assert ((i.vrex & REX_X) == 0);
3624 register_specifier = i.vex.register_specifier->reg_num;
3625 if ((i.vex.register_specifier->reg_flags & RegRex))
3626 register_specifier += 8;
3627 /* The upper 16 registers are encoded in the fourth byte of the
3629 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3630 i.vex.bytes[3] = 0x8;
3631 register_specifier = ~register_specifier & 0xf;
3635 register_specifier = 0xf;
3637 /* Encode upper 16 vector index register in the fourth byte of
3639 if (!(i.vrex & REX_X))
3640 i.vex.bytes[3] = 0x8;
3645 switch ((i.tm.base_opcode >> 8) & 0xff)
3650 case DATA_PREFIX_OPCODE:
3653 case REPE_PREFIX_OPCODE:
3656 case REPNE_PREFIX_OPCODE:
3663 /* 4 byte EVEX prefix. */
3665 i.vex.bytes[0] = 0x62;
3668 switch (i.tm.opcode_modifier.vexopcode)
3684 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3686 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3688 /* The fifth bit of the second EVEX byte is 1's compliment of the
3689 REX_R bit in VREX. */
3690 if (!(i.vrex & REX_R))
3691 i.vex.bytes[1] |= 0x10;
3695 if ((i.reg_operands + i.imm_operands) == i.operands)
3697 /* When all operands are registers, the REX_X bit in REX is not
3698 used. We reuse it to encode the upper 16 registers, which is
3699 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3700 as 1's compliment. */
3701 if ((i.vrex & REX_B))
3704 i.vex.bytes[1] &= ~0x40;
3708 /* EVEX instructions shouldn't need the REX prefix. */
3709 i.vrex &= ~vrex_used;
3710 gas_assert (i.vrex == 0);
3712 /* Check the REX.W bit and VEXW. */
3713 if (i.tm.opcode_modifier.vexw == VEXWIG)
3714 w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
3715 else if (i.tm.opcode_modifier.vexw)
3716 w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
3718 w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
3720 /* Encode the U bit. */
3721 implied_prefix |= 0x4;
3723 /* The third byte of the EVEX prefix. */
3724 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3726 /* The fourth byte of the EVEX prefix. */
3727 /* The zeroing-masking bit. */
3728 if (i.mask && i.mask->zeroing)
3729 i.vex.bytes[3] |= 0x80;
3731 /* Don't always set the broadcast bit if there is no RC. */
3734 /* Encode the vector length. */
3735 unsigned int vec_length;
3737 if (!i.tm.opcode_modifier.evex
3738 || i.tm.opcode_modifier.evex == EVEXDYN)
3742 /* Determine vector length from the last multi-length vector
3745 for (op = i.operands; op--;)
3746 if (i.tm.operand_types[op].bitfield.xmmword
3747 + i.tm.operand_types[op].bitfield.ymmword
3748 + i.tm.operand_types[op].bitfield.zmmword > 1)
3750 if (i.types[op].bitfield.zmmword)
3752 i.tm.opcode_modifier.evex = EVEX512;
3755 else if (i.types[op].bitfield.ymmword)
3757 i.tm.opcode_modifier.evex = EVEX256;
3760 else if (i.types[op].bitfield.xmmword)
3762 i.tm.opcode_modifier.evex = EVEX128;
3765 else if (i.broadcast && (int) op == i.broadcast->operand)
3767 switch (i.broadcast->bytes)
3770 i.tm.opcode_modifier.evex = EVEX512;
3773 i.tm.opcode_modifier.evex = EVEX256;
3776 i.tm.opcode_modifier.evex = EVEX128;
3785 if (op >= MAX_OPERANDS)
3789 switch (i.tm.opcode_modifier.evex)
3791 case EVEXLIG: /* LL' is ignored */
3792 vec_length = evexlig << 5;
3795 vec_length = 0 << 5;
3798 vec_length = 1 << 5;
3801 vec_length = 2 << 5;
3807 i.vex.bytes[3] |= vec_length;
3808 /* Encode the broadcast bit. */
3810 i.vex.bytes[3] |= 0x10;
3814 if (i.rounding->type != saeonly)
3815 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3817 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3820 if (i.mask && i.mask->mask)
3821 i.vex.bytes[3] |= i.mask->mask->reg_num;
3825 process_immext (void)
3829 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3832 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3833 with an opcode suffix which is coded in the same place as an
3834 8-bit immediate field would be.
3835 Here we check those operands and remove them afterwards. */
3838 for (x = 0; x < i.operands; x++)
3839 if (register_number (i.op[x].regs) != x)
3840 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3841 register_prefix, i.op[x].regs->reg_name, x + 1,
3847 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3849 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3850 suffix which is coded in the same place as an 8-bit immediate
3852 Here we check those operands and remove them afterwards. */
3855 if (i.operands != 3)
3858 for (x = 0; x < 2; x++)
3859 if (register_number (i.op[x].regs) != x)
3860 goto bad_register_operand;
3862 /* Check for third operand for mwaitx/monitorx insn. */
3863 if (register_number (i.op[x].regs)
3864 != (x + (i.tm.extension_opcode == 0xfb)))
3866 bad_register_operand:
3867 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3868 register_prefix, i.op[x].regs->reg_name, x+1,
3875 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3876 which is coded in the same place as an 8-bit immediate field
3877 would be. Here we fake an 8-bit immediate operand from the
3878 opcode suffix stored in tm.extension_opcode.
3880 AVX instructions also use this encoding, for some of
3881 3 argument instructions. */
3883 gas_assert (i.imm_operands <= 1
3885 || (is_any_vex_encoding (&i.tm)
3886 && i.operands <= 4)));
3888 exp = &im_expressions[i.imm_operands++];
3889 i.op[i.operands].imms = exp;
3890 i.types[i.operands] = imm8;
3892 exp->X_op = O_constant;
3893 exp->X_add_number = i.tm.extension_opcode;
3894 i.tm.extension_opcode = None;
3901 switch (i.tm.opcode_modifier.hleprefixok)
3906 as_bad (_("invalid instruction `%s' after `%s'"),
3907 i.tm.name, i.hle_prefix);
3910 if (i.prefix[LOCK_PREFIX])
3912 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3916 case HLEPrefixRelease:
3917 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3919 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3923 if (i.mem_operands == 0
3924 || !operand_type_check (i.types[i.operands - 1], anymem))
3926 as_bad (_("memory destination needed for instruction `%s'"
3927 " after `xrelease'"), i.tm.name);
3934 /* Try the shortest encoding by shortening operand size. */
3937 optimize_encoding (void)
3941 if (optimize_for_space
3942 && i.reg_operands == 1
3943 && i.imm_operands == 1
3944 && !i.types[1].bitfield.byte
3945 && i.op[0].imms->X_op == O_constant
3946 && fits_in_imm7 (i.op[0].imms->X_add_number)
3947 && ((i.tm.base_opcode == 0xa8
3948 && i.tm.extension_opcode == None)
3949 || (i.tm.base_opcode == 0xf6
3950 && i.tm.extension_opcode == 0x0)))
3953 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3955 unsigned int base_regnum = i.op[1].regs->reg_num;
3956 if (flag_code == CODE_64BIT || base_regnum < 4)
3958 i.types[1].bitfield.byte = 1;
3959 /* Ignore the suffix. */
3961 if (base_regnum >= 4
3962 && !(i.op[1].regs->reg_flags & RegRex))
3964 /* Handle SP, BP, SI and DI registers. */
3965 if (i.types[1].bitfield.word)
3967 else if (i.types[1].bitfield.dword)
3975 else if (flag_code == CODE_64BIT
3976 && ((i.types[1].bitfield.qword
3977 && i.reg_operands == 1
3978 && i.imm_operands == 1
3979 && i.op[0].imms->X_op == O_constant
3980 && ((i.tm.base_opcode == 0xb0
3981 && i.tm.extension_opcode == None
3982 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3983 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3984 && (((i.tm.base_opcode == 0x24
3985 || i.tm.base_opcode == 0xa8)
3986 && i.tm.extension_opcode == None)
3987 || (i.tm.base_opcode == 0x80
3988 && i.tm.extension_opcode == 0x4)
3989 || ((i.tm.base_opcode == 0xf6
3990 || i.tm.base_opcode == 0xc6)
3991 && i.tm.extension_opcode == 0x0)))
3992 || (fits_in_imm7 (i.op[0].imms->X_add_number)
3993 && i.tm.base_opcode == 0x83
3994 && i.tm.extension_opcode == 0x4)))
3995 || (i.types[0].bitfield.qword
3996 && ((i.reg_operands == 2
3997 && i.op[0].regs == i.op[1].regs
3998 && ((i.tm.base_opcode == 0x30
3999 || i.tm.base_opcode == 0x28)
4000 && i.tm.extension_opcode == None))
4001 || (i.reg_operands == 1
4003 && i.tm.base_opcode == 0x30
4004 && i.tm.extension_opcode == None)))))
4007 andq $imm31, %r64 -> andl $imm31, %r32
4008 andq $imm7, %r64 -> andl $imm7, %r32
4009 testq $imm31, %r64 -> testl $imm31, %r32
4010 xorq %r64, %r64 -> xorl %r32, %r32
4011 subq %r64, %r64 -> subl %r32, %r32
4012 movq $imm31, %r64 -> movl $imm31, %r32
4013 movq $imm32, %r64 -> movl $imm32, %r32
4015 i.tm.opcode_modifier.norex64 = 1;
4016 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
4019 movq $imm31, %r64 -> movl $imm31, %r32
4020 movq $imm32, %r64 -> movl $imm32, %r32
4022 i.tm.operand_types[0].bitfield.imm32 = 1;
4023 i.tm.operand_types[0].bitfield.imm32s = 0;
4024 i.tm.operand_types[0].bitfield.imm64 = 0;
4025 i.types[0].bitfield.imm32 = 1;
4026 i.types[0].bitfield.imm32s = 0;
4027 i.types[0].bitfield.imm64 = 0;
4028 i.types[1].bitfield.dword = 1;
4029 i.types[1].bitfield.qword = 0;
4030 if (i.tm.base_opcode == 0xc6)
4033 movq $imm31, %r64 -> movl $imm31, %r32
4035 i.tm.base_opcode = 0xb0;
4036 i.tm.extension_opcode = None;
4037 i.tm.opcode_modifier.shortform = 1;
4038 i.tm.opcode_modifier.modrm = 0;
4042 else if (optimize > 1
4043 && !optimize_for_space
4044 && i.reg_operands == 2
4045 && i.op[0].regs == i.op[1].regs
4046 && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8
4047 || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20)
4048 && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword))
4051 andb %rN, %rN -> testb %rN, %rN
4052 andw %rN, %rN -> testw %rN, %rN
4053 andq %rN, %rN -> testq %rN, %rN
4054 orb %rN, %rN -> testb %rN, %rN
4055 orw %rN, %rN -> testw %rN, %rN
4056 orq %rN, %rN -> testq %rN, %rN
4058 and outside of 64-bit mode
4060 andl %rN, %rN -> testl %rN, %rN
4061 orl %rN, %rN -> testl %rN, %rN
4063 i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1);
4065 else if (i.reg_operands == 3
4066 && i.op[0].regs == i.op[1].regs
4067 && !i.types[2].bitfield.xmmword
4068 && (i.tm.opcode_modifier.vex
4069 || ((!i.mask || i.mask->zeroing)
4071 && is_evex_encoding (&i.tm)
4072 && (i.vec_encoding != vex_encoding_evex
4073 || cpu_arch_isa_flags.bitfield.cpuavx512vl
4074 || i.tm.cpu_flags.bitfield.cpuavx512vl
4075 || (i.tm.operand_types[2].bitfield.zmmword
4076 && i.types[2].bitfield.ymmword))))
4077 && ((i.tm.base_opcode == 0x55
4078 || i.tm.base_opcode == 0x6655
4079 || i.tm.base_opcode == 0x66df
4080 || i.tm.base_opcode == 0x57
4081 || i.tm.base_opcode == 0x6657
4082 || i.tm.base_opcode == 0x66ef
4083 || i.tm.base_opcode == 0x66f8
4084 || i.tm.base_opcode == 0x66f9
4085 || i.tm.base_opcode == 0x66fa
4086 || i.tm.base_opcode == 0x66fb
4087 || i.tm.base_opcode == 0x42
4088 || i.tm.base_opcode == 0x6642
4089 || i.tm.base_opcode == 0x47
4090 || i.tm.base_opcode == 0x6647)
4091 && i.tm.extension_opcode == None))
4094 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
4096 EVEX VOP %zmmM, %zmmM, %zmmN
4097 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4098 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4099 EVEX VOP %ymmM, %ymmM, %ymmN
4100 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
4101 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4102 VEX VOP %ymmM, %ymmM, %ymmN
4103 -> VEX VOP %xmmM, %xmmM, %xmmN
4104 VOP, one of vpandn and vpxor:
4105 VEX VOP %ymmM, %ymmM, %ymmN
4106 -> VEX VOP %xmmM, %xmmM, %xmmN
4107 VOP, one of vpandnd and vpandnq:
4108 EVEX VOP %zmmM, %zmmM, %zmmN
4109 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4110 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4111 EVEX VOP %ymmM, %ymmM, %ymmN
4112 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
4113 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4114 VOP, one of vpxord and vpxorq:
4115 EVEX VOP %zmmM, %zmmM, %zmmN
4116 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4117 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4118 EVEX VOP %ymmM, %ymmM, %ymmN
4119 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
4120 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
4121 VOP, one of kxord and kxorq:
4122 VEX VOP %kM, %kM, %kN
4123 -> VEX kxorw %kM, %kM, %kN
4124 VOP, one of kandnd and kandnq:
4125 VEX VOP %kM, %kM, %kN
4126 -> VEX kandnw %kM, %kM, %kN
4128 if (is_evex_encoding (&i.tm))
4130 if (i.vec_encoding != vex_encoding_evex)
4132 i.tm.opcode_modifier.vex = VEX128;
4133 i.tm.opcode_modifier.vexw = VEXW0;
4134 i.tm.opcode_modifier.evex = 0;
4136 else if (optimize > 1)
4137 i.tm.opcode_modifier.evex = EVEX128;
4141 else if (i.tm.operand_types[0].bitfield.regmask)
4143 i.tm.base_opcode &= 0xff;
4144 i.tm.opcode_modifier.vexw = VEXW0;
4147 i.tm.opcode_modifier.vex = VEX128;
4149 if (i.tm.opcode_modifier.vex)
4150 for (j = 0; j < 3; j++)
4152 i.types[j].bitfield.xmmword = 1;
4153 i.types[j].bitfield.ymmword = 0;
4156 else if (i.vec_encoding != vex_encoding_evex
4157 && !i.types[0].bitfield.zmmword
4158 && !i.types[1].bitfield.zmmword
4161 && is_evex_encoding (&i.tm)
4162 && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f
4163 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f
4164 || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f
4165 || (i.tm.base_opcode & ~4) == 0x66db
4166 || (i.tm.base_opcode & ~4) == 0x66eb)
4167 && i.tm.extension_opcode == None)
4170 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
4171 vmovdqu32 and vmovdqu64:
4172 EVEX VOP %xmmM, %xmmN
4173 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
4174 EVEX VOP %ymmM, %ymmN
4175 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
4177 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
4179 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
4181 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
4183 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
4184 VOP, one of vpand, vpandn, vpor, vpxor:
4185 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
4186 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
4187 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
4188 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
4189 EVEX VOP{d,q} mem, %xmmM, %xmmN
4190 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
4191 EVEX VOP{d,q} mem, %ymmM, %ymmN
4192 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
4194 for (j = 0; j < i.operands; j++)
4195 if (operand_type_check (i.types[j], disp)
4196 && i.op[j].disps->X_op == O_constant)
4198 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
4199 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
4200 bytes, we choose EVEX Disp8 over VEX Disp32. */
4201 int evex_disp8, vex_disp8;
4202 unsigned int memshift = i.memshift;
4203 offsetT n = i.op[j].disps->X_add_number;
4205 evex_disp8 = fits_in_disp8 (n);
4207 vex_disp8 = fits_in_disp8 (n);
4208 if (evex_disp8 != vex_disp8)
4210 i.memshift = memshift;
4214 i.types[j].bitfield.disp8 = vex_disp8;
4217 if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f)
4218 i.tm.base_opcode ^= 0xf36f ^ 0xf26f;
4219 i.tm.opcode_modifier.vex
4220 = i.types[0].bitfield.ymmword ? VEX256 : VEX128;
4221 i.tm.opcode_modifier.vexw = VEXW0;
4222 /* VPAND, VPOR, and VPXOR are commutative. */
4223 if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df)
4224 i.tm.opcode_modifier.commutative = 1;
4225 i.tm.opcode_modifier.evex = 0;
4226 i.tm.opcode_modifier.masking = 0;
4227 i.tm.opcode_modifier.broadcast = 0;
4228 i.tm.opcode_modifier.disp8memshift = 0;
4231 i.types[j].bitfield.disp8
4232 = fits_in_disp8 (i.op[j].disps->X_add_number);
4236 /* This is the guts of the machine-dependent assembler. LINE points to a
4237 machine dependent instruction. This function is supposed to emit
4238 the frags/bytes it assembles to. */
4241 md_assemble (char *line)
4244 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
4245 const insn_template *t;
4247 /* Initialize globals. */
4248 memset (&i, '\0', sizeof (i));
4249 for (j = 0; j < MAX_OPERANDS; j++)
4250 i.reloc[j] = NO_RELOC;
4251 memset (disp_expressions, '\0', sizeof (disp_expressions));
4252 memset (im_expressions, '\0', sizeof (im_expressions));
4253 save_stack_p = save_stack;
4255 /* First parse an instruction mnemonic & call i386_operand for the operands.
4256 We assume that the scrubber has arranged it so that line[0] is the valid
4257 start of a (possibly prefixed) mnemonic. */
4259 line = parse_insn (line, mnemonic);
4262 mnem_suffix = i.suffix;
4264 line = parse_operands (line, mnemonic);
4266 xfree (i.memop1_string);
4267 i.memop1_string = NULL;
4271 /* Now we've parsed the mnemonic into a set of templates, and have the
4272 operands at hand. */
4274 /* All intel opcodes have reversed operands except for "bound" and
4275 "enter". We also don't reverse intersegment "jmp" and "call"
4276 instructions with 2 immediate operands so that the immediate segment
4277 precedes the offset, as it does when in AT&T mode. */
4280 && (strcmp (mnemonic, "bound") != 0)
4281 && (strcmp (mnemonic, "invlpga") != 0)
4282 && !(operand_type_check (i.types[0], imm)
4283 && operand_type_check (i.types[1], imm)))
4286 /* The order of the immediates should be reversed
4287 for 2 immediates extrq and insertq instructions */
4288 if (i.imm_operands == 2
4289 && (strcmp (mnemonic, "extrq") == 0
4290 || strcmp (mnemonic, "insertq") == 0))
4291 swap_2_operands (0, 1);
4296 /* Don't optimize displacement for movabs since it only takes 64bit
4299 && i.disp_encoding != disp_encoding_32bit
4300 && (flag_code != CODE_64BIT
4301 || strcmp (mnemonic, "movabs") != 0))
4304 /* Next, we find a template that matches the given insn,
4305 making sure the overlap of the given operands types is consistent
4306 with the template operand types. */
4308 if (!(t = match_template (mnem_suffix)))
4311 if (sse_check != check_none
4312 && !i.tm.opcode_modifier.noavx
4313 && !i.tm.cpu_flags.bitfield.cpuavx
4314 && (i.tm.cpu_flags.bitfield.cpusse
4315 || i.tm.cpu_flags.bitfield.cpusse2
4316 || i.tm.cpu_flags.bitfield.cpusse3
4317 || i.tm.cpu_flags.bitfield.cpussse3
4318 || i.tm.cpu_flags.bitfield.cpusse4_1
4319 || i.tm.cpu_flags.bitfield.cpusse4_2
4320 || i.tm.cpu_flags.bitfield.cpupclmul
4321 || i.tm.cpu_flags.bitfield.cpuaes
4322 || i.tm.cpu_flags.bitfield.cpugfni))
4324 (sse_check == check_warning
4326 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4329 /* Zap movzx and movsx suffix. The suffix has been set from
4330 "word ptr" or "byte ptr" on the source operand in Intel syntax
4331 or extracted from mnemonic in AT&T syntax. But we'll use
4332 the destination register to choose the suffix for encoding. */
4333 if ((i.tm.base_opcode & ~9) == 0x0fb6)
4335 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4336 there is no suffix, the default will be byte extension. */
4337 if (i.reg_operands != 2
4340 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4345 if (i.tm.opcode_modifier.fwait)
4346 if (!add_prefix (FWAIT_OPCODE))
4349 /* Check if REP prefix is OK. */
4350 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4352 as_bad (_("invalid instruction `%s' after `%s'"),
4353 i.tm.name, i.rep_prefix);
4357 /* Check for lock without a lockable instruction. Destination operand
4358 must be memory unless it is xchg (0x86). */
4359 if (i.prefix[LOCK_PREFIX]
4360 && (!i.tm.opcode_modifier.islockable
4361 || i.mem_operands == 0
4362 || (i.tm.base_opcode != 0x86
4363 && !operand_type_check (i.types[i.operands - 1], anymem))))
4365 as_bad (_("expecting lockable instruction after `lock'"));
4369 /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */
4370 if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm))
4372 as_bad (_("data size prefix invalid with `%s'"), i.tm.name);
4376 /* Check if HLE prefix is OK. */
4377 if (i.hle_prefix && !check_hle ())
4380 /* Check BND prefix. */
4381 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4382 as_bad (_("expecting valid branch instruction after `bnd'"));
4384 /* Check NOTRACK prefix. */
4385 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4386 as_bad (_("expecting indirect branch instruction after `notrack'"));
4388 if (i.tm.cpu_flags.bitfield.cpumpx)
4390 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4391 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4392 else if (flag_code != CODE_16BIT
4393 ? i.prefix[ADDR_PREFIX]
4394 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4395 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4398 /* Insert BND prefix. */
4399 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4401 if (!i.prefix[BND_PREFIX])
4402 add_prefix (BND_PREFIX_OPCODE);
4403 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4405 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4406 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4410 /* Check string instruction segment overrides. */
4411 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
4413 if (!check_string ())
4415 i.disp_operands = 0;
4418 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4419 optimize_encoding ();
4421 if (!process_suffix ())
4424 /* Update operand types. */
4425 for (j = 0; j < i.operands; j++)
4426 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4428 /* Make still unresolved immediate matches conform to size of immediate
4429 given in i.suffix. */
4430 if (!finalize_imm ())
4433 if (i.types[0].bitfield.imm1)
4434 i.imm_operands = 0; /* kludge for shift insns. */
4436 /* We only need to check those implicit registers for instructions
4437 with 3 operands or less. */
4438 if (i.operands <= 3)
4439 for (j = 0; j < i.operands; j++)
4440 if (i.types[j].bitfield.inoutportreg
4441 || i.types[j].bitfield.shiftcount
4442 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
4445 /* ImmExt should be processed after SSE2AVX. */
4446 if (!i.tm.opcode_modifier.sse2avx
4447 && i.tm.opcode_modifier.immext)
4450 /* For insns with operands there are more diddles to do to the opcode. */
4453 if (!process_operands ())
4456 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4458 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4459 as_warn (_("translating to `%sp'"), i.tm.name);
4462 if (is_any_vex_encoding (&i.tm))
4464 if (!cpu_arch_flags.bitfield.cpui286)
4466 as_bad (_("instruction `%s' isn't supported outside of protected mode."),
4471 if (i.tm.opcode_modifier.vex)
4472 build_vex_prefix (t);
4474 build_evex_prefix ();
4477 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4478 instructions may define INT_OPCODE as well, so avoid this corner
4479 case for those instructions that use MODRM. */
4480 if (i.tm.base_opcode == INT_OPCODE
4481 && !i.tm.opcode_modifier.modrm
4482 && i.op[0].imms->X_add_number == 3)
4484 i.tm.base_opcode = INT3_OPCODE;
4488 if ((i.tm.opcode_modifier.jump
4489 || i.tm.opcode_modifier.jumpbyte
4490 || i.tm.opcode_modifier.jumpdword)
4491 && i.op[0].disps->X_op == O_constant)
4493 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4494 the absolute address given by the constant. Since ix86 jumps and
4495 calls are pc relative, we need to generate a reloc. */
4496 i.op[0].disps->X_add_symbol = &abs_symbol;
4497 i.op[0].disps->X_op = O_symbol;
4500 if (i.tm.opcode_modifier.rex64)
4503 /* For 8 bit registers we need an empty rex prefix. Also if the
4504 instruction already has a prefix, we need to convert old
4505 registers to new ones. */
4507 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
4508 && (i.op[0].regs->reg_flags & RegRex64) != 0)
4509 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
4510 && (i.op[1].regs->reg_flags & RegRex64) != 0)
4511 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4512 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
4517 i.rex |= REX_OPCODE;
4518 for (x = 0; x < 2; x++)
4520 /* Look for 8 bit operand that uses old registers. */
4521 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
4522 && (i.op[x].regs->reg_flags & RegRex64) == 0)
4524 /* In case it is "hi" register, give up. */
4525 if (i.op[x].regs->reg_num > 3)
4526 as_bad (_("can't encode register '%s%s' in an "
4527 "instruction requiring REX prefix."),
4528 register_prefix, i.op[x].regs->reg_name);
4530 /* Otherwise it is equivalent to the extended register.
4531 Since the encoding doesn't change this is merely
4532 cosmetic cleanup for debug output. */
4534 i.op[x].regs = i.op[x].regs + 8;
4539 if (i.rex == 0 && i.rex_encoding)
4541 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4542 that uses legacy register. If it is "hi" register, don't add
4543 the REX_OPCODE byte. */
4545 for (x = 0; x < 2; x++)
4546 if (i.types[x].bitfield.reg
4547 && i.types[x].bitfield.byte
4548 && (i.op[x].regs->reg_flags & RegRex64) == 0
4549 && i.op[x].regs->reg_num > 3)
4551 i.rex_encoding = FALSE;
4560 add_prefix (REX_OPCODE | i.rex);
4562 /* We are ready to output the insn. */
4567 parse_insn (char *line, char *mnemonic)
4570 char *token_start = l;
4573 const insn_template *t;
4579 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4584 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
4586 as_bad (_("no such instruction: `%s'"), token_start);
4591 if (!is_space_char (*l)
4592 && *l != END_OF_INSN
4594 || (*l != PREFIX_SEPARATOR
4597 as_bad (_("invalid character %s in mnemonic"),
4598 output_invalid (*l));
4601 if (token_start == l)
4603 if (!intel_syntax && *l == PREFIX_SEPARATOR)
4604 as_bad (_("expecting prefix; got nothing"));
4606 as_bad (_("expecting mnemonic; got nothing"));
4610 /* Look up instruction (or prefix) via hash table. */
4611 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4613 if (*l != END_OF_INSN
4614 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4615 && current_templates
4616 && current_templates->start->opcode_modifier.isprefix)
4618 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
4620 as_bad ((flag_code != CODE_64BIT
4621 ? _("`%s' is only supported in 64-bit mode")
4622 : _("`%s' is not supported in 64-bit mode")),
4623 current_templates->start->name);
4626 /* If we are in 16-bit mode, do not allow addr16 or data16.
4627 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4628 if ((current_templates->start->opcode_modifier.size == SIZE16
4629 || current_templates->start->opcode_modifier.size == SIZE32)
4630 && flag_code != CODE_64BIT
4631 && ((current_templates->start->opcode_modifier.size == SIZE32)
4632 ^ (flag_code == CODE_16BIT)))
4634 as_bad (_("redundant %s prefix"),
4635 current_templates->start->name);
4638 if (current_templates->start->opcode_length == 0)
4640 /* Handle pseudo prefixes. */
4641 switch (current_templates->start->base_opcode)
4645 i.disp_encoding = disp_encoding_8bit;
4649 i.disp_encoding = disp_encoding_32bit;
4653 i.dir_encoding = dir_encoding_load;
4657 i.dir_encoding = dir_encoding_store;
4661 i.vec_encoding = vex_encoding_vex2;
4665 i.vec_encoding = vex_encoding_vex3;
4669 i.vec_encoding = vex_encoding_evex;
4673 i.rex_encoding = TRUE;
4677 i.no_optimize = TRUE;
4685 /* Add prefix, checking for repeated prefixes. */
4686 switch (add_prefix (current_templates->start->base_opcode))
4691 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4692 i.notrack_prefix = current_templates->start->name;
4695 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4696 i.hle_prefix = current_templates->start->name;
4697 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4698 i.bnd_prefix = current_templates->start->name;
4700 i.rep_prefix = current_templates->start->name;
4706 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4713 if (!current_templates)
4715 /* Deprecated functionality (new code should use pseudo-prefixes instead):
4716 Check if we should swap operand or force 32bit displacement in
4718 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4719 i.dir_encoding = dir_encoding_swap;
4720 else if (mnem_p - 3 == dot_p
4723 i.disp_encoding = disp_encoding_8bit;
4724 else if (mnem_p - 4 == dot_p
4728 i.disp_encoding = disp_encoding_32bit;
4733 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4736 if (!current_templates)
4739 if (mnem_p > mnemonic)
4741 /* See if we can get a match by trimming off a suffix. */
4744 case WORD_MNEM_SUFFIX:
4745 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4746 i.suffix = SHORT_MNEM_SUFFIX;
4749 case BYTE_MNEM_SUFFIX:
4750 case QWORD_MNEM_SUFFIX:
4751 i.suffix = mnem_p[-1];
4753 current_templates = (const templates *) hash_find (op_hash,
4756 case SHORT_MNEM_SUFFIX:
4757 case LONG_MNEM_SUFFIX:
4760 i.suffix = mnem_p[-1];
4762 current_templates = (const templates *) hash_find (op_hash,
4771 if (intel_float_operand (mnemonic) == 1)
4772 i.suffix = SHORT_MNEM_SUFFIX;
4774 i.suffix = LONG_MNEM_SUFFIX;
4776 current_templates = (const templates *) hash_find (op_hash,
4783 if (!current_templates)
4785 as_bad (_("no such instruction: `%s'"), token_start);
4790 if (current_templates->start->opcode_modifier.jump
4791 || current_templates->start->opcode_modifier.jumpbyte)
4793 /* Check for a branch hint. We allow ",pt" and ",pn" for
4794 predict taken and predict not taken respectively.
4795 I'm not sure that branch hints actually do anything on loop
4796 and jcxz insns (JumpByte) for current Pentium4 chips. They
4797 may work in the future and it doesn't hurt to accept them
4799 if (l[0] == ',' && l[1] == 'p')
4803 if (!add_prefix (DS_PREFIX_OPCODE))
4807 else if (l[2] == 'n')
4809 if (!add_prefix (CS_PREFIX_OPCODE))
4815 /* Any other comma loses. */
4818 as_bad (_("invalid character %s in mnemonic"),
4819 output_invalid (*l));
4823 /* Check if instruction is supported on specified architecture. */
4825 for (t = current_templates->start; t < current_templates->end; ++t)
4827 supported |= cpu_flags_match (t);
4828 if (supported == CPU_FLAGS_PERFECT_MATCH)
4830 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4831 as_warn (_("use .code16 to ensure correct addressing mode"));
4837 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4838 as_bad (flag_code == CODE_64BIT
4839 ? _("`%s' is not supported in 64-bit mode")
4840 : _("`%s' is only supported in 64-bit mode"),
4841 current_templates->start->name);
4843 as_bad (_("`%s' is not supported on `%s%s'"),
4844 current_templates->start->name,
4845 cpu_arch_name ? cpu_arch_name : default_arch,
4846 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4852 parse_operands (char *l, const char *mnemonic)
4856 /* 1 if operand is pending after ','. */
4857 unsigned int expecting_operand = 0;
4859 /* Non-zero if operand parens not balanced. */
4860 unsigned int paren_not_balanced;
4862 while (*l != END_OF_INSN)
4864 /* Skip optional white space before operand. */
4865 if (is_space_char (*l))
4867 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4869 as_bad (_("invalid character %s before operand %d"),
4870 output_invalid (*l),
4874 token_start = l; /* After white space. */
4875 paren_not_balanced = 0;
4876 while (paren_not_balanced || *l != ',')
4878 if (*l == END_OF_INSN)
4880 if (paren_not_balanced)
4883 as_bad (_("unbalanced parenthesis in operand %d."),
4886 as_bad (_("unbalanced brackets in operand %d."),
4891 break; /* we are done */
4893 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4895 as_bad (_("invalid character %s in operand %d"),
4896 output_invalid (*l),
4903 ++paren_not_balanced;
4905 --paren_not_balanced;
4910 ++paren_not_balanced;
4912 --paren_not_balanced;
4916 if (l != token_start)
4917 { /* Yes, we've read in another operand. */
4918 unsigned int operand_ok;
4919 this_operand = i.operands++;
4920 if (i.operands > MAX_OPERANDS)
4922 as_bad (_("spurious operands; (%d operands/instruction max)"),
4926 i.types[this_operand].bitfield.unspecified = 1;
4927 /* Now parse operand adding info to 'i' as we go along. */
4928 END_STRING_AND_SAVE (l);
4930 if (i.mem_operands > 1)
4932 as_bad (_("too many memory references for `%s'"),
4939 i386_intel_operand (token_start,
4940 intel_float_operand (mnemonic));
4942 operand_ok = i386_att_operand (token_start);
4944 RESTORE_END_STRING (l);
4950 if (expecting_operand)
4952 expecting_operand_after_comma:
4953 as_bad (_("expecting operand after ','; got nothing"));
4958 as_bad (_("expecting operand before ','; got nothing"));
4963 /* Now *l must be either ',' or END_OF_INSN. */
4966 if (*++l == END_OF_INSN)
4968 /* Just skip it, if it's \n complain. */
4969 goto expecting_operand_after_comma;
4971 expecting_operand = 1;
4978 swap_2_operands (int xchg1, int xchg2)
4980 union i386_op temp_op;
4981 i386_operand_type temp_type;
4982 unsigned int temp_flags;
4983 enum bfd_reloc_code_real temp_reloc;
4985 temp_type = i.types[xchg2];
4986 i.types[xchg2] = i.types[xchg1];
4987 i.types[xchg1] = temp_type;
4989 temp_flags = i.flags[xchg2];
4990 i.flags[xchg2] = i.flags[xchg1];
4991 i.flags[xchg1] = temp_flags;
4993 temp_op = i.op[xchg2];
4994 i.op[xchg2] = i.op[xchg1];
4995 i.op[xchg1] = temp_op;
4997 temp_reloc = i.reloc[xchg2];
4998 i.reloc[xchg2] = i.reloc[xchg1];
4999 i.reloc[xchg1] = temp_reloc;
5003 if (i.mask->operand == xchg1)
5004 i.mask->operand = xchg2;
5005 else if (i.mask->operand == xchg2)
5006 i.mask->operand = xchg1;
5010 if (i.broadcast->operand == xchg1)
5011 i.broadcast->operand = xchg2;
5012 else if (i.broadcast->operand == xchg2)
5013 i.broadcast->operand = xchg1;
5017 if (i.rounding->operand == xchg1)
5018 i.rounding->operand = xchg2;
5019 else if (i.rounding->operand == xchg2)
5020 i.rounding->operand = xchg1;
5025 swap_operands (void)
5031 swap_2_operands (1, i.operands - 2);
5035 swap_2_operands (0, i.operands - 1);
5041 if (i.mem_operands == 2)
5043 const seg_entry *temp_seg;
5044 temp_seg = i.seg[0];
5045 i.seg[0] = i.seg[1];
5046 i.seg[1] = temp_seg;
5050 /* Try to ensure constant immediates are represented in the smallest
5055 char guess_suffix = 0;
5059 guess_suffix = i.suffix;
5060 else if (i.reg_operands)
5062 /* Figure out a suffix from the last register operand specified.
5063 We can't do this properly yet, ie. excluding InOutPortReg,
5064 but the following works for instructions with immediates.
5065 In any case, we can't set i.suffix yet. */
5066 for (op = i.operands; --op >= 0;)
5067 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5069 guess_suffix = BYTE_MNEM_SUFFIX;
5072 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5074 guess_suffix = WORD_MNEM_SUFFIX;
5077 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5079 guess_suffix = LONG_MNEM_SUFFIX;
5082 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5084 guess_suffix = QWORD_MNEM_SUFFIX;
5088 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5089 guess_suffix = WORD_MNEM_SUFFIX;
5091 for (op = i.operands; --op >= 0;)
5092 if (operand_type_check (i.types[op], imm))
5094 switch (i.op[op].imms->X_op)
5097 /* If a suffix is given, this operand may be shortened. */
5098 switch (guess_suffix)
5100 case LONG_MNEM_SUFFIX:
5101 i.types[op].bitfield.imm32 = 1;
5102 i.types[op].bitfield.imm64 = 1;
5104 case WORD_MNEM_SUFFIX:
5105 i.types[op].bitfield.imm16 = 1;
5106 i.types[op].bitfield.imm32 = 1;
5107 i.types[op].bitfield.imm32s = 1;
5108 i.types[op].bitfield.imm64 = 1;
5110 case BYTE_MNEM_SUFFIX:
5111 i.types[op].bitfield.imm8 = 1;
5112 i.types[op].bitfield.imm8s = 1;
5113 i.types[op].bitfield.imm16 = 1;
5114 i.types[op].bitfield.imm32 = 1;
5115 i.types[op].bitfield.imm32s = 1;
5116 i.types[op].bitfield.imm64 = 1;
5120 /* If this operand is at most 16 bits, convert it
5121 to a signed 16 bit number before trying to see
5122 whether it will fit in an even smaller size.
5123 This allows a 16-bit operand such as $0xffe0 to
5124 be recognised as within Imm8S range. */
5125 if ((i.types[op].bitfield.imm16)
5126 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
5128 i.op[op].imms->X_add_number =
5129 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
5132 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
5133 if ((i.types[op].bitfield.imm32)
5134 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
5137 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
5138 ^ ((offsetT) 1 << 31))
5139 - ((offsetT) 1 << 31));
5143 = operand_type_or (i.types[op],
5144 smallest_imm_type (i.op[op].imms->X_add_number));
5146 /* We must avoid matching of Imm32 templates when 64bit
5147 only immediate is available. */
5148 if (guess_suffix == QWORD_MNEM_SUFFIX)
5149 i.types[op].bitfield.imm32 = 0;
5156 /* Symbols and expressions. */
5158 /* Convert symbolic operand to proper sizes for matching, but don't
5159 prevent matching a set of insns that only supports sizes other
5160 than those matching the insn suffix. */
5162 i386_operand_type mask, allowed;
5163 const insn_template *t;
5165 operand_type_set (&mask, 0);
5166 operand_type_set (&allowed, 0);
5168 for (t = current_templates->start;
5169 t < current_templates->end;
5171 allowed = operand_type_or (allowed,
5172 t->operand_types[op]);
5173 switch (guess_suffix)
5175 case QWORD_MNEM_SUFFIX:
5176 mask.bitfield.imm64 = 1;
5177 mask.bitfield.imm32s = 1;
5179 case LONG_MNEM_SUFFIX:
5180 mask.bitfield.imm32 = 1;
5182 case WORD_MNEM_SUFFIX:
5183 mask.bitfield.imm16 = 1;
5185 case BYTE_MNEM_SUFFIX:
5186 mask.bitfield.imm8 = 1;
5191 allowed = operand_type_and (mask, allowed);
5192 if (!operand_type_all_zero (&allowed))
5193 i.types[op] = operand_type_and (i.types[op], mask);
5200 /* Try to use the smallest displacement type too. */
5202 optimize_disp (void)
5206 for (op = i.operands; --op >= 0;)
5207 if (operand_type_check (i.types[op], disp))
5209 if (i.op[op].disps->X_op == O_constant)
5211 offsetT op_disp = i.op[op].disps->X_add_number;
5213 if (i.types[op].bitfield.disp16
5214 && (op_disp & ~(offsetT) 0xffff) == 0)
5216 /* If this operand is at most 16 bits, convert
5217 to a signed 16 bit number and don't use 64bit
5219 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
5220 i.types[op].bitfield.disp64 = 0;
5223 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
5224 if (i.types[op].bitfield.disp32
5225 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
5227 /* If this operand is at most 32 bits, convert
5228 to a signed 32 bit number and don't use 64bit
5230 op_disp &= (((offsetT) 2 << 31) - 1);
5231 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
5232 i.types[op].bitfield.disp64 = 0;
5235 if (!op_disp && i.types[op].bitfield.baseindex)
5237 i.types[op].bitfield.disp8 = 0;
5238 i.types[op].bitfield.disp16 = 0;
5239 i.types[op].bitfield.disp32 = 0;
5240 i.types[op].bitfield.disp32s = 0;
5241 i.types[op].bitfield.disp64 = 0;
5245 else if (flag_code == CODE_64BIT)
5247 if (fits_in_signed_long (op_disp))
5249 i.types[op].bitfield.disp64 = 0;
5250 i.types[op].bitfield.disp32s = 1;
5252 if (i.prefix[ADDR_PREFIX]
5253 && fits_in_unsigned_long (op_disp))
5254 i.types[op].bitfield.disp32 = 1;
5256 if ((i.types[op].bitfield.disp32
5257 || i.types[op].bitfield.disp32s
5258 || i.types[op].bitfield.disp16)
5259 && fits_in_disp8 (op_disp))
5260 i.types[op].bitfield.disp8 = 1;
5262 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5263 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
5265 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
5266 i.op[op].disps, 0, i.reloc[op]);
5267 i.types[op].bitfield.disp8 = 0;
5268 i.types[op].bitfield.disp16 = 0;
5269 i.types[op].bitfield.disp32 = 0;
5270 i.types[op].bitfield.disp32s = 0;
5271 i.types[op].bitfield.disp64 = 0;
5274 /* We only support 64bit displacement on constants. */
5275 i.types[op].bitfield.disp64 = 0;
5279 /* Return 1 if there is a match in broadcast bytes between operand
5280 GIVEN and instruction template T. */
5283 match_broadcast_size (const insn_template *t, unsigned int given)
5285 return ((t->opcode_modifier.broadcast == BYTE_BROADCAST
5286 && i.types[given].bitfield.byte)
5287 || (t->opcode_modifier.broadcast == WORD_BROADCAST
5288 && i.types[given].bitfield.word)
5289 || (t->opcode_modifier.broadcast == DWORD_BROADCAST
5290 && i.types[given].bitfield.dword)
5291 || (t->opcode_modifier.broadcast == QWORD_BROADCAST
5292 && i.types[given].bitfield.qword));
5295 /* Check if operands are valid for the instruction. */
5298 check_VecOperands (const insn_template *t)
5302 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5304 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5305 any one operand are implicity requiring AVX512VL support if the actual
5306 operand size is YMMword or XMMword. Since this function runs after
5307 template matching, there's no need to check for YMMword/XMMword in
5309 cpu = cpu_flags_and (t->cpu_flags, avx512);
5310 if (!cpu_flags_all_zero (&cpu)
5311 && !t->cpu_flags.bitfield.cpuavx512vl
5312 && !cpu_arch_flags.bitfield.cpuavx512vl)
5314 for (op = 0; op < t->operands; ++op)
5316 if (t->operand_types[op].bitfield.zmmword
5317 && (i.types[op].bitfield.ymmword
5318 || i.types[op].bitfield.xmmword))
5320 i.error = unsupported;
5326 /* Without VSIB byte, we can't have a vector register for index. */
5327 if (!t->opcode_modifier.vecsib
5329 && (i.index_reg->reg_type.bitfield.xmmword
5330 || i.index_reg->reg_type.bitfield.ymmword
5331 || i.index_reg->reg_type.bitfield.zmmword))
5333 i.error = unsupported_vector_index_register;
5337 /* Check if default mask is allowed. */
5338 if (t->opcode_modifier.nodefmask
5339 && (!i.mask || i.mask->mask->reg_num == 0))
5341 i.error = no_default_mask;
5345 /* For VSIB byte, we need a vector register for index, and all vector
5346 registers must be distinct. */
5347 if (t->opcode_modifier.vecsib)
5350 || !((t->opcode_modifier.vecsib == VecSIB128
5351 && i.index_reg->reg_type.bitfield.xmmword)
5352 || (t->opcode_modifier.vecsib == VecSIB256
5353 && i.index_reg->reg_type.bitfield.ymmword)
5354 || (t->opcode_modifier.vecsib == VecSIB512
5355 && i.index_reg->reg_type.bitfield.zmmword)))
5357 i.error = invalid_vsib_address;
5361 gas_assert (i.reg_operands == 2 || i.mask);
5362 if (i.reg_operands == 2 && !i.mask)
5364 gas_assert (i.types[0].bitfield.regsimd);
5365 gas_assert (i.types[0].bitfield.xmmword
5366 || i.types[0].bitfield.ymmword);
5367 gas_assert (i.types[2].bitfield.regsimd);
5368 gas_assert (i.types[2].bitfield.xmmword
5369 || i.types[2].bitfield.ymmword);
5370 if (operand_check == check_none)
5372 if (register_number (i.op[0].regs)
5373 != register_number (i.index_reg)
5374 && register_number (i.op[2].regs)
5375 != register_number (i.index_reg)
5376 && register_number (i.op[0].regs)
5377 != register_number (i.op[2].regs))
5379 if (operand_check == check_error)
5381 i.error = invalid_vector_register_set;
5384 as_warn (_("mask, index, and destination registers should be distinct"));
5386 else if (i.reg_operands == 1 && i.mask)
5388 if (i.types[1].bitfield.regsimd
5389 && (i.types[1].bitfield.xmmword
5390 || i.types[1].bitfield.ymmword
5391 || i.types[1].bitfield.zmmword)
5392 && (register_number (i.op[1].regs)
5393 == register_number (i.index_reg)))
5395 if (operand_check == check_error)
5397 i.error = invalid_vector_register_set;
5400 if (operand_check != check_none)
5401 as_warn (_("index and destination registers should be distinct"));
5406 /* Check if broadcast is supported by the instruction and is applied
5407 to the memory operand. */
5410 i386_operand_type type, overlap;
5412 /* Check if specified broadcast is supported in this instruction,
5413 and its broadcast bytes match the memory operand. */
5414 op = i.broadcast->operand;
5415 if (!t->opcode_modifier.broadcast
5416 || !(i.flags[op] & Operand_Mem)
5417 || (!i.types[op].bitfield.unspecified
5418 && !match_broadcast_size (t, op)))
5421 i.error = unsupported_broadcast;
5425 i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1))
5426 * i.broadcast->type);
5427 operand_type_set (&type, 0);
5428 switch (i.broadcast->bytes)
5431 type.bitfield.word = 1;
5434 type.bitfield.dword = 1;
5437 type.bitfield.qword = 1;
5440 type.bitfield.xmmword = 1;
5443 type.bitfield.ymmword = 1;
5446 type.bitfield.zmmword = 1;
5452 overlap = operand_type_and (type, t->operand_types[op]);
5453 if (operand_type_all_zero (&overlap))
5456 if (t->opcode_modifier.checkregsize)
5460 type.bitfield.baseindex = 1;
5461 for (j = 0; j < i.operands; ++j)
5464 && !operand_type_register_match(i.types[j],
5465 t->operand_types[j],
5467 t->operand_types[op]))
5472 /* If broadcast is supported in this instruction, we need to check if
5473 operand of one-element size isn't specified without broadcast. */
5474 else if (t->opcode_modifier.broadcast && i.mem_operands)
5476 /* Find memory operand. */
5477 for (op = 0; op < i.operands; op++)
5478 if (operand_type_check (i.types[op], anymem))
5480 gas_assert (op < i.operands);
5481 /* Check size of the memory operand. */
5482 if (match_broadcast_size (t, op))
5484 i.error = broadcast_needed;
5489 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
5491 /* Check if requested masking is supported. */
5494 switch (t->opcode_modifier.masking)
5498 case MERGING_MASKING:
5499 if (i.mask->zeroing)
5502 i.error = unsupported_masking;
5506 case DYNAMIC_MASKING:
5507 /* Memory destinations allow only merging masking. */
5508 if (i.mask->zeroing && i.mem_operands)
5510 /* Find memory operand. */
5511 for (op = 0; op < i.operands; op++)
5512 if (i.flags[op] & Operand_Mem)
5514 gas_assert (op < i.operands);
5515 if (op == i.operands - 1)
5517 i.error = unsupported_masking;
5527 /* Check if masking is applied to dest operand. */
5528 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5530 i.error = mask_not_on_destination;
5537 if (!t->opcode_modifier.sae
5538 || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding))
5540 i.error = unsupported_rc_sae;
5543 /* If the instruction has several immediate operands and one of
5544 them is rounding, the rounding operand should be the last
5545 immediate operand. */
5546 if (i.imm_operands > 1
5547 && i.rounding->operand != (int) (i.imm_operands - 1))
5549 i.error = rc_sae_operand_not_last_imm;
5554 /* Check vector Disp8 operand. */
5555 if (t->opcode_modifier.disp8memshift
5556 && i.disp_encoding != disp_encoding_32bit)
5559 i.memshift = t->opcode_modifier.broadcast - 1;
5560 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
5561 i.memshift = t->opcode_modifier.disp8memshift;
5564 const i386_operand_type *type = NULL;
5567 for (op = 0; op < i.operands; op++)
5568 if (operand_type_check (i.types[op], anymem))
5570 if (t->opcode_modifier.evex == EVEXLIG)
5571 i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX);
5572 else if (t->operand_types[op].bitfield.xmmword
5573 + t->operand_types[op].bitfield.ymmword
5574 + t->operand_types[op].bitfield.zmmword <= 1)
5575 type = &t->operand_types[op];
5576 else if (!i.types[op].bitfield.unspecified)
5577 type = &i.types[op];
5579 else if (i.types[op].bitfield.regsimd
5580 && t->opcode_modifier.evex != EVEXLIG)
5582 if (i.types[op].bitfield.zmmword)
5584 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5586 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5592 if (type->bitfield.zmmword)
5594 else if (type->bitfield.ymmword)
5596 else if (type->bitfield.xmmword)
5600 /* For the check in fits_in_disp8(). */
5601 if (i.memshift == 0)
5605 for (op = 0; op < i.operands; op++)
5606 if (operand_type_check (i.types[op], disp)
5607 && i.op[op].disps->X_op == O_constant)
5609 if (fits_in_disp8 (i.op[op].disps->X_add_number))
5611 i.types[op].bitfield.disp8 = 1;
5614 i.types[op].bitfield.disp8 = 0;
5623 /* Check if operands are valid for the instruction. Update VEX
5627 VEX_check_operands (const insn_template *t)
5629 if (i.vec_encoding == vex_encoding_evex)
5631 /* This instruction must be encoded with EVEX prefix. */
5632 if (!is_evex_encoding (t))
5634 i.error = unsupported;
5640 if (!t->opcode_modifier.vex)
5642 /* This instruction template doesn't have VEX prefix. */
5643 if (i.vec_encoding != vex_encoding_default)
5645 i.error = unsupported;
5651 /* Check the special Imm4 cases; must be the first operand. */
5652 if (t->cpu_flags.bitfield.cpuxop && t->operands == 5)
5654 if (i.op[0].imms->X_op != O_constant
5655 || !fits_in_imm4 (i.op[0].imms->X_add_number))
5661 /* Turn off Imm<N> so that update_imm won't complain. */
5662 operand_type_set (&i.types[0], 0);
5668 static const insn_template *
5669 match_template (char mnem_suffix)
5671 /* Points to template once we've found it. */
5672 const insn_template *t;
5673 i386_operand_type overlap0, overlap1, overlap2, overlap3;
5674 i386_operand_type overlap4;
5675 unsigned int found_reverse_match;
5676 i386_opcode_modifier suffix_check, mnemsuf_check;
5677 i386_operand_type operand_types [MAX_OPERANDS];
5678 int addr_prefix_disp;
5680 unsigned int found_cpu_match, size_match;
5681 unsigned int check_register;
5682 enum i386_error specific_error = 0;
5684 #if MAX_OPERANDS != 5
5685 # error "MAX_OPERANDS must be 5."
5688 found_reverse_match = 0;
5689 addr_prefix_disp = -1;
5691 memset (&suffix_check, 0, sizeof (suffix_check));
5692 if (intel_syntax && i.broadcast)
5694 else if (i.suffix == BYTE_MNEM_SUFFIX)
5695 suffix_check.no_bsuf = 1;
5696 else if (i.suffix == WORD_MNEM_SUFFIX)
5697 suffix_check.no_wsuf = 1;
5698 else if (i.suffix == SHORT_MNEM_SUFFIX)
5699 suffix_check.no_ssuf = 1;
5700 else if (i.suffix == LONG_MNEM_SUFFIX)
5701 suffix_check.no_lsuf = 1;
5702 else if (i.suffix == QWORD_MNEM_SUFFIX)
5703 suffix_check.no_qsuf = 1;
5704 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
5705 suffix_check.no_ldsuf = 1;
5707 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5710 switch (mnem_suffix)
5712 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5713 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5714 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5715 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5716 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5720 /* Must have right number of operands. */
5721 i.error = number_of_operands_mismatch;
5723 for (t = current_templates->start; t < current_templates->end; t++)
5725 addr_prefix_disp = -1;
5726 found_reverse_match = 0;
5728 if (i.operands != t->operands)
5731 /* Check processor support. */
5732 i.error = unsupported;
5733 found_cpu_match = (cpu_flags_match (t)
5734 == CPU_FLAGS_PERFECT_MATCH);
5735 if (!found_cpu_match)
5738 /* Check AT&T mnemonic. */
5739 i.error = unsupported_with_intel_mnemonic;
5740 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
5743 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
5744 i.error = unsupported_syntax;
5745 if ((intel_syntax && t->opcode_modifier.attsyntax)
5746 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5747 || (intel64 && t->opcode_modifier.amd64)
5748 || (!intel64 && t->opcode_modifier.intel64))
5751 /* Check the suffix, except for some instructions in intel mode. */
5752 i.error = invalid_instruction_suffix;
5753 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5754 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5755 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5756 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5757 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5758 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5759 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
5761 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5762 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5763 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5764 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5765 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5766 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5767 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5770 size_match = operand_size_match (t);
5774 for (j = 0; j < MAX_OPERANDS; j++)
5775 operand_types[j] = t->operand_types[j];
5777 /* In general, don't allow 64-bit operands in 32-bit mode. */
5778 if (i.suffix == QWORD_MNEM_SUFFIX
5779 && flag_code != CODE_64BIT
5781 ? (!t->opcode_modifier.ignoresize
5782 && !t->opcode_modifier.broadcast
5783 && !intel_float_operand (t->name))
5784 : intel_float_operand (t->name) != 2)
5785 && ((!operand_types[0].bitfield.regmmx
5786 && !operand_types[0].bitfield.regsimd)
5787 || (!operand_types[t->operands > 1].bitfield.regmmx
5788 && !operand_types[t->operands > 1].bitfield.regsimd))
5789 && (t->base_opcode != 0x0fc7
5790 || t->extension_opcode != 1 /* cmpxchg8b */))
5793 /* In general, don't allow 32-bit operands on pre-386. */
5794 else if (i.suffix == LONG_MNEM_SUFFIX
5795 && !cpu_arch_flags.bitfield.cpui386
5797 ? (!t->opcode_modifier.ignoresize
5798 && !intel_float_operand (t->name))
5799 : intel_float_operand (t->name) != 2)
5800 && ((!operand_types[0].bitfield.regmmx
5801 && !operand_types[0].bitfield.regsimd)
5802 || (!operand_types[t->operands > 1].bitfield.regmmx
5803 && !operand_types[t->operands > 1].bitfield.regsimd)))
5806 /* Do not verify operands when there are none. */
5810 /* We've found a match; break out of loop. */
5814 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5815 into Disp32/Disp16/Disp32 operand. */
5816 if (i.prefix[ADDR_PREFIX] != 0)
5818 /* There should be only one Disp operand. */
5822 for (j = 0; j < MAX_OPERANDS; j++)
5824 if (operand_types[j].bitfield.disp16)
5826 addr_prefix_disp = j;
5827 operand_types[j].bitfield.disp32 = 1;
5828 operand_types[j].bitfield.disp16 = 0;
5834 for (j = 0; j < MAX_OPERANDS; j++)
5836 if (operand_types[j].bitfield.disp32)
5838 addr_prefix_disp = j;
5839 operand_types[j].bitfield.disp32 = 0;
5840 operand_types[j].bitfield.disp16 = 1;
5846 for (j = 0; j < MAX_OPERANDS; j++)
5848 if (operand_types[j].bitfield.disp64)
5850 addr_prefix_disp = j;
5851 operand_types[j].bitfield.disp64 = 0;
5852 operand_types[j].bitfield.disp32 = 1;
5860 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5861 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5864 /* We check register size if needed. */
5865 if (t->opcode_modifier.checkregsize)
5867 check_register = (1 << t->operands) - 1;
5869 check_register &= ~(1 << i.broadcast->operand);
5874 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5875 switch (t->operands)
5878 if (!operand_type_match (overlap0, i.types[0]))
5882 /* xchg %eax, %eax is a special case. It is an alias for nop
5883 only in 32bit mode and we can use opcode 0x90. In 64bit
5884 mode, we can't use 0x90 for xchg %eax, %eax since it should
5885 zero-extend %eax to %rax. */
5886 if (flag_code == CODE_64BIT
5887 && t->base_opcode == 0x90
5888 && i.types[0].bitfield.acc && i.types[0].bitfield.dword
5889 && i.types[1].bitfield.acc && i.types[1].bitfield.dword)
5891 /* xrelease mov %eax, <disp> is another special case. It must not
5892 match the accumulator-only encoding of mov. */
5893 if (flag_code != CODE_64BIT
5895 && t->base_opcode == 0xa0
5896 && i.types[0].bitfield.acc
5897 && operand_type_check (i.types[1], anymem))
5902 if (!(size_match & MATCH_STRAIGHT))
5904 /* Reverse direction of operands if swapping is possible in the first
5905 place (operands need to be symmetric) and
5906 - the load form is requested, and the template is a store form,
5907 - the store form is requested, and the template is a load form,
5908 - the non-default (swapped) form is requested. */
5909 overlap1 = operand_type_and (operand_types[0], operand_types[1]);
5910 if (t->opcode_modifier.d && i.reg_operands == i.operands
5911 && !operand_type_all_zero (&overlap1))
5912 switch (i.dir_encoding)
5914 case dir_encoding_load:
5915 if (operand_type_check (operand_types[i.operands - 1], anymem)
5916 || operand_types[i.operands - 1].bitfield.regmem)
5920 case dir_encoding_store:
5921 if (!operand_type_check (operand_types[i.operands - 1], anymem)
5922 && !operand_types[i.operands - 1].bitfield.regmem)
5926 case dir_encoding_swap:
5929 case dir_encoding_default:
5932 /* If we want store form, we skip the current load. */
5933 if ((i.dir_encoding == dir_encoding_store
5934 || i.dir_encoding == dir_encoding_swap)
5935 && i.mem_operands == 0
5936 && t->opcode_modifier.load)
5941 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5942 if (!operand_type_match (overlap0, i.types[0])
5943 || !operand_type_match (overlap1, i.types[1])
5944 || ((check_register & 3) == 3
5945 && !operand_type_register_match (i.types[0],
5950 /* Check if other direction is valid ... */
5951 if (!t->opcode_modifier.d)
5955 if (!(size_match & MATCH_REVERSE))
5957 /* Try reversing direction of operands. */
5958 overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]);
5959 overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]);
5960 if (!operand_type_match (overlap0, i.types[0])
5961 || !operand_type_match (overlap1, i.types[i.operands - 1])
5963 && !operand_type_register_match (i.types[0],
5964 operand_types[i.operands - 1],
5965 i.types[i.operands - 1],
5968 /* Does not match either direction. */
5971 /* found_reverse_match holds which of D or FloatR
5973 if (!t->opcode_modifier.d)
5974 found_reverse_match = 0;
5975 else if (operand_types[0].bitfield.tbyte)
5976 found_reverse_match = Opcode_FloatD;
5977 else if (operand_types[0].bitfield.xmmword
5978 || operand_types[i.operands - 1].bitfield.xmmword
5979 || operand_types[0].bitfield.regmmx
5980 || operand_types[i.operands - 1].bitfield.regmmx
5981 || is_any_vex_encoding(t))
5982 found_reverse_match = (t->base_opcode & 0xee) != 0x6e
5983 ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD;
5985 found_reverse_match = Opcode_D;
5986 if (t->opcode_modifier.floatr)
5987 found_reverse_match |= Opcode_FloatR;
5991 /* Found a forward 2 operand match here. */
5992 switch (t->operands)
5995 overlap4 = operand_type_and (i.types[4],
5999 overlap3 = operand_type_and (i.types[3],
6003 overlap2 = operand_type_and (i.types[2],
6008 switch (t->operands)
6011 if (!operand_type_match (overlap4, i.types[4])
6012 || !operand_type_register_match (i.types[3],
6019 if (!operand_type_match (overlap3, i.types[3])
6020 || ((check_register & 0xa) == 0xa
6021 && !operand_type_register_match (i.types[1],
6025 || ((check_register & 0xc) == 0xc
6026 && !operand_type_register_match (i.types[2],
6033 /* Here we make use of the fact that there are no
6034 reverse match 3 operand instructions. */
6035 if (!operand_type_match (overlap2, i.types[2])
6036 || ((check_register & 5) == 5
6037 && !operand_type_register_match (i.types[0],
6041 || ((check_register & 6) == 6
6042 && !operand_type_register_match (i.types[1],
6050 /* Found either forward/reverse 2, 3 or 4 operand match here:
6051 slip through to break. */
6053 if (!found_cpu_match)
6056 /* Check if vector and VEX operands are valid. */
6057 if (check_VecOperands (t) || VEX_check_operands (t))
6059 specific_error = i.error;
6063 /* We've found a match; break out of loop. */
6067 if (t == current_templates->end)
6069 /* We found no match. */
6070 const char *err_msg;
6071 switch (specific_error ? specific_error : i.error)
6075 case operand_size_mismatch:
6076 err_msg = _("operand size mismatch");
6078 case operand_type_mismatch:
6079 err_msg = _("operand type mismatch");
6081 case register_type_mismatch:
6082 err_msg = _("register type mismatch");
6084 case number_of_operands_mismatch:
6085 err_msg = _("number of operands mismatch");
6087 case invalid_instruction_suffix:
6088 err_msg = _("invalid instruction suffix");
6091 err_msg = _("constant doesn't fit in 4 bits");
6093 case unsupported_with_intel_mnemonic:
6094 err_msg = _("unsupported with Intel mnemonic");
6096 case unsupported_syntax:
6097 err_msg = _("unsupported syntax");
6100 as_bad (_("unsupported instruction `%s'"),
6101 current_templates->start->name);
6103 case invalid_vsib_address:
6104 err_msg = _("invalid VSIB address");
6106 case invalid_vector_register_set:
6107 err_msg = _("mask, index, and destination registers must be distinct");
6109 case unsupported_vector_index_register:
6110 err_msg = _("unsupported vector index register");
6112 case unsupported_broadcast:
6113 err_msg = _("unsupported broadcast");
6115 case broadcast_needed:
6116 err_msg = _("broadcast is needed for operand of such type");
6118 case unsupported_masking:
6119 err_msg = _("unsupported masking");
6121 case mask_not_on_destination:
6122 err_msg = _("mask not on destination operand");
6124 case no_default_mask:
6125 err_msg = _("default mask isn't allowed");
6127 case unsupported_rc_sae:
6128 err_msg = _("unsupported static rounding/sae");
6130 case rc_sae_operand_not_last_imm:
6132 err_msg = _("RC/SAE operand must precede immediate operands");
6134 err_msg = _("RC/SAE operand must follow immediate operands");
6136 case invalid_register_operand:
6137 err_msg = _("invalid register operand");
6140 as_bad (_("%s for `%s'"), err_msg,
6141 current_templates->start->name);
6145 if (!quiet_warnings)
6148 && (i.types[0].bitfield.jumpabsolute
6149 != operand_types[0].bitfield.jumpabsolute))
6151 as_warn (_("indirect %s without `*'"), t->name);
6154 if (t->opcode_modifier.isprefix
6155 && t->opcode_modifier.ignoresize)
6157 /* Warn them that a data or address size prefix doesn't
6158 affect assembly of the next line of code. */
6159 as_warn (_("stand-alone `%s' prefix"), t->name);
6163 /* Copy the template we found. */
6166 if (addr_prefix_disp != -1)
6167 i.tm.operand_types[addr_prefix_disp]
6168 = operand_types[addr_prefix_disp];
6170 if (found_reverse_match)
6172 /* If we found a reverse match we must alter the opcode
6173 direction bit. found_reverse_match holds bits to change
6174 (different for int & float insns). */
6176 i.tm.base_opcode ^= found_reverse_match;
6178 i.tm.operand_types[0] = operand_types[i.operands - 1];
6179 i.tm.operand_types[i.operands - 1] = operand_types[0];
6188 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
6189 if (i.tm.operand_types[mem_op].bitfield.esseg)
6191 if (i.seg[0] != NULL && i.seg[0] != &es)
6193 as_bad (_("`%s' operand %d must use `%ses' segment"),
6199 /* There's only ever one segment override allowed per instruction.
6200 This instruction possibly has a legal segment override on the
6201 second operand, so copy the segment to where non-string
6202 instructions store it, allowing common code. */
6203 i.seg[0] = i.seg[1];
6205 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
6207 if (i.seg[1] != NULL && i.seg[1] != &es)
6209 as_bad (_("`%s' operand %d must use `%ses' segment"),
6220 process_suffix (void)
6222 /* If matched instruction specifies an explicit instruction mnemonic
6224 if (i.tm.opcode_modifier.size == SIZE16)
6225 i.suffix = WORD_MNEM_SUFFIX;
6226 else if (i.tm.opcode_modifier.size == SIZE32)
6227 i.suffix = LONG_MNEM_SUFFIX;
6228 else if (i.tm.opcode_modifier.size == SIZE64)
6229 i.suffix = QWORD_MNEM_SUFFIX;
6230 else if (i.reg_operands)
6232 /* If there's no instruction mnemonic suffix we try to invent one
6233 based on register operands. */
6236 /* We take i.suffix from the last register operand specified,
6237 Destination register type is more significant than source
6238 register type. crc32 in SSE4.2 prefers source register
6240 if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg)
6242 if (i.types[0].bitfield.byte)
6243 i.suffix = BYTE_MNEM_SUFFIX;
6244 else if (i.types[0].bitfield.word)
6245 i.suffix = WORD_MNEM_SUFFIX;
6246 else if (i.types[0].bitfield.dword)
6247 i.suffix = LONG_MNEM_SUFFIX;
6248 else if (i.types[0].bitfield.qword)
6249 i.suffix = QWORD_MNEM_SUFFIX;
6256 if (i.tm.base_opcode == 0xf20f38f0)
6258 /* We have to know the operand size for crc32. */
6259 as_bad (_("ambiguous memory operand size for `%s`"),
6264 for (op = i.operands; --op >= 0;)
6265 if (!i.tm.operand_types[op].bitfield.inoutportreg
6266 && !i.tm.operand_types[op].bitfield.shiftcount)
6268 if (!i.types[op].bitfield.reg)
6270 if (i.types[op].bitfield.byte)
6271 i.suffix = BYTE_MNEM_SUFFIX;
6272 else if (i.types[op].bitfield.word)
6273 i.suffix = WORD_MNEM_SUFFIX;
6274 else if (i.types[op].bitfield.dword)
6275 i.suffix = LONG_MNEM_SUFFIX;
6276 else if (i.types[op].bitfield.qword)
6277 i.suffix = QWORD_MNEM_SUFFIX;
6284 else if (i.suffix == BYTE_MNEM_SUFFIX)
6287 && i.tm.opcode_modifier.ignoresize
6288 && i.tm.opcode_modifier.no_bsuf)
6290 else if (!check_byte_reg ())
6293 else if (i.suffix == LONG_MNEM_SUFFIX)
6296 && i.tm.opcode_modifier.ignoresize
6297 && i.tm.opcode_modifier.no_lsuf
6298 && !i.tm.opcode_modifier.todword
6299 && !i.tm.opcode_modifier.toqword)
6301 else if (!check_long_reg ())
6304 else if (i.suffix == QWORD_MNEM_SUFFIX)
6307 && i.tm.opcode_modifier.ignoresize
6308 && i.tm.opcode_modifier.no_qsuf
6309 && !i.tm.opcode_modifier.todword
6310 && !i.tm.opcode_modifier.toqword)
6312 else if (!check_qword_reg ())
6315 else if (i.suffix == WORD_MNEM_SUFFIX)
6318 && i.tm.opcode_modifier.ignoresize
6319 && i.tm.opcode_modifier.no_wsuf)
6321 else if (!check_word_reg ())
6324 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
6325 /* Do nothing if the instruction is going to ignore the prefix. */
6330 else if (i.tm.opcode_modifier.defaultsize
6332 /* exclude fldenv/frstor/fsave/fstenv */
6333 && i.tm.opcode_modifier.no_ssuf)
6335 if (stackop_size == LONG_MNEM_SUFFIX
6336 && i.tm.base_opcode == 0xcf)
6338 /* stackop_size is set to LONG_MNEM_SUFFIX for the
6339 .code16gcc directive to support 16-bit mode with
6340 32-bit address. For IRET without a suffix, generate
6341 16-bit IRET (opcode 0xcf) to return from an interrupt
6343 i.suffix = WORD_MNEM_SUFFIX;
6344 as_warn (_("generating 16-bit `iret' for .code16gcc directive"));
6347 i.suffix = stackop_size;
6349 else if (intel_syntax
6351 && (i.tm.operand_types[0].bitfield.jumpabsolute
6352 || i.tm.opcode_modifier.jumpbyte
6353 || i.tm.opcode_modifier.jumpintersegment
6354 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
6355 && i.tm.extension_opcode <= 3)))
6360 if (!i.tm.opcode_modifier.no_qsuf)
6362 i.suffix = QWORD_MNEM_SUFFIX;
6367 if (!i.tm.opcode_modifier.no_lsuf)
6368 i.suffix = LONG_MNEM_SUFFIX;
6371 if (!i.tm.opcode_modifier.no_wsuf)
6372 i.suffix = WORD_MNEM_SUFFIX;
6381 if (i.tm.opcode_modifier.w)
6383 as_bad (_("no instruction mnemonic suffix given and "
6384 "no register operands; can't size instruction"));
6390 unsigned int suffixes;
6392 suffixes = !i.tm.opcode_modifier.no_bsuf;
6393 if (!i.tm.opcode_modifier.no_wsuf)
6395 if (!i.tm.opcode_modifier.no_lsuf)
6397 if (!i.tm.opcode_modifier.no_ldsuf)
6399 if (!i.tm.opcode_modifier.no_ssuf)
6401 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
6404 /* There are more than suffix matches. */
6405 if (i.tm.opcode_modifier.w
6406 || ((suffixes & (suffixes - 1))
6407 && !i.tm.opcode_modifier.defaultsize
6408 && !i.tm.opcode_modifier.ignoresize))
6410 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6416 /* Change the opcode based on the operand size given by i.suffix. */
6419 /* Size floating point instruction. */
6420 case LONG_MNEM_SUFFIX:
6421 if (i.tm.opcode_modifier.floatmf)
6423 i.tm.base_opcode ^= 4;
6427 case WORD_MNEM_SUFFIX:
6428 case QWORD_MNEM_SUFFIX:
6429 /* It's not a byte, select word/dword operation. */
6430 if (i.tm.opcode_modifier.w)
6432 if (i.tm.opcode_modifier.shortform)
6433 i.tm.base_opcode |= 8;
6435 i.tm.base_opcode |= 1;
6438 case SHORT_MNEM_SUFFIX:
6439 /* Now select between word & dword operations via the operand
6440 size prefix, except for instructions that will ignore this
6442 if (i.reg_operands > 0
6443 && i.types[0].bitfield.reg
6444 && i.tm.opcode_modifier.addrprefixopreg
6445 && (i.tm.opcode_modifier.immext
6446 || i.operands == 1))
6448 /* The address size override prefix changes the size of the
6450 if ((flag_code == CODE_32BIT
6451 && i.op[0].regs->reg_type.bitfield.word)
6452 || (flag_code != CODE_32BIT
6453 && i.op[0].regs->reg_type.bitfield.dword))
6454 if (!add_prefix (ADDR_PREFIX_OPCODE))
6457 else if (i.suffix != QWORD_MNEM_SUFFIX
6458 && !i.tm.opcode_modifier.ignoresize
6459 && !i.tm.opcode_modifier.floatmf
6460 && !is_any_vex_encoding (&i.tm)
6461 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6462 || (flag_code == CODE_64BIT
6463 && i.tm.opcode_modifier.jumpbyte)))
6465 unsigned int prefix = DATA_PREFIX_OPCODE;
6467 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
6468 prefix = ADDR_PREFIX_OPCODE;
6470 if (!add_prefix (prefix))
6474 /* Set mode64 for an operand. */
6475 if (i.suffix == QWORD_MNEM_SUFFIX
6476 && flag_code == CODE_64BIT
6477 && !i.tm.opcode_modifier.norex64
6478 /* Special case for xchg %rax,%rax. It is NOP and doesn't
6480 && ! (i.operands == 2
6481 && i.tm.base_opcode == 0x90
6482 && i.tm.extension_opcode == None
6483 && i.types[0].bitfield.acc && i.types[0].bitfield.qword
6484 && i.types[1].bitfield.acc && i.types[1].bitfield.qword))
6490 if (i.reg_operands != 0
6492 && i.tm.opcode_modifier.addrprefixopreg
6493 && !i.tm.opcode_modifier.immext)
6495 /* Check invalid register operand when the address size override
6496 prefix changes the size of register operands. */
6498 enum { need_word, need_dword, need_qword } need;
6500 if (flag_code == CODE_32BIT)
6501 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6504 if (i.prefix[ADDR_PREFIX])
6507 need = flag_code == CODE_64BIT ? need_qword : need_word;
6510 for (op = 0; op < i.operands; op++)
6511 if (i.types[op].bitfield.reg
6512 && ((need == need_word
6513 && !i.op[op].regs->reg_type.bitfield.word)
6514 || (need == need_dword
6515 && !i.op[op].regs->reg_type.bitfield.dword)
6516 || (need == need_qword
6517 && !i.op[op].regs->reg_type.bitfield.qword)))
6519 as_bad (_("invalid register operand size for `%s'"),
6529 check_byte_reg (void)
6533 for (op = i.operands; --op >= 0;)
6535 /* Skip non-register operands. */
6536 if (!i.types[op].bitfield.reg)
6539 /* If this is an eight bit register, it's OK. If it's the 16 or
6540 32 bit version of an eight bit register, we will just use the
6541 low portion, and that's OK too. */
6542 if (i.types[op].bitfield.byte)
6545 /* I/O port address operands are OK too. */
6546 if (i.tm.operand_types[op].bitfield.inoutportreg)
6549 /* crc32 doesn't generate this warning. */
6550 if (i.tm.base_opcode == 0xf20f38f0)
6553 if ((i.types[op].bitfield.word
6554 || i.types[op].bitfield.dword
6555 || i.types[op].bitfield.qword)
6556 && i.op[op].regs->reg_num < 4
6557 /* Prohibit these changes in 64bit mode, since the lowering
6558 would be more complicated. */
6559 && flag_code != CODE_64BIT)
6561 #if REGISTER_WARNINGS
6562 if (!quiet_warnings)
6563 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6565 (i.op[op].regs + (i.types[op].bitfield.word
6566 ? REGNAM_AL - REGNAM_AX
6567 : REGNAM_AL - REGNAM_EAX))->reg_name,
6569 i.op[op].regs->reg_name,
6574 /* Any other register is bad. */
6575 if (i.types[op].bitfield.reg
6576 || i.types[op].bitfield.regmmx
6577 || i.types[op].bitfield.regsimd
6578 || i.types[op].bitfield.sreg2
6579 || i.types[op].bitfield.sreg3
6580 || i.types[op].bitfield.control
6581 || i.types[op].bitfield.debug
6582 || i.types[op].bitfield.test)
6584 as_bad (_("`%s%s' not allowed with `%s%c'"),
6586 i.op[op].regs->reg_name,
6596 check_long_reg (void)
6600 for (op = i.operands; --op >= 0;)
6601 /* Skip non-register operands. */
6602 if (!i.types[op].bitfield.reg)
6604 /* Reject eight bit registers, except where the template requires
6605 them. (eg. movzb) */
6606 else if (i.types[op].bitfield.byte
6607 && (i.tm.operand_types[op].bitfield.reg
6608 || i.tm.operand_types[op].bitfield.acc)
6609 && (i.tm.operand_types[op].bitfield.word
6610 || i.tm.operand_types[op].bitfield.dword))
6612 as_bad (_("`%s%s' not allowed with `%s%c'"),
6614 i.op[op].regs->reg_name,
6619 /* Warn if the e prefix on a general reg is missing. */
6620 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6621 && i.types[op].bitfield.word
6622 && (i.tm.operand_types[op].bitfield.reg
6623 || i.tm.operand_types[op].bitfield.acc)
6624 && i.tm.operand_types[op].bitfield.dword)
6626 /* Prohibit these changes in the 64bit mode, since the
6627 lowering is more complicated. */
6628 if (flag_code == CODE_64BIT)
6630 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6631 register_prefix, i.op[op].regs->reg_name,
6635 #if REGISTER_WARNINGS
6636 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6638 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6639 register_prefix, i.op[op].regs->reg_name, i.suffix);
6642 /* Warn if the r prefix on a general reg is present. */
6643 else if (i.types[op].bitfield.qword
6644 && (i.tm.operand_types[op].bitfield.reg
6645 || i.tm.operand_types[op].bitfield.acc)
6646 && i.tm.operand_types[op].bitfield.dword)
6649 && i.tm.opcode_modifier.toqword
6650 && !i.types[0].bitfield.regsimd)
6652 /* Convert to QWORD. We want REX byte. */
6653 i.suffix = QWORD_MNEM_SUFFIX;
6657 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6658 register_prefix, i.op[op].regs->reg_name,
6667 check_qword_reg (void)
6671 for (op = i.operands; --op >= 0; )
6672 /* Skip non-register operands. */
6673 if (!i.types[op].bitfield.reg)
6675 /* Reject eight bit registers, except where the template requires
6676 them. (eg. movzb) */
6677 else if (i.types[op].bitfield.byte
6678 && (i.tm.operand_types[op].bitfield.reg
6679 || i.tm.operand_types[op].bitfield.acc)
6680 && (i.tm.operand_types[op].bitfield.word
6681 || i.tm.operand_types[op].bitfield.dword))
6683 as_bad (_("`%s%s' not allowed with `%s%c'"),
6685 i.op[op].regs->reg_name,
6690 /* Warn if the r prefix on a general reg is missing. */
6691 else if ((i.types[op].bitfield.word
6692 || i.types[op].bitfield.dword)
6693 && (i.tm.operand_types[op].bitfield.reg
6694 || i.tm.operand_types[op].bitfield.acc)
6695 && i.tm.operand_types[op].bitfield.qword)
6697 /* Prohibit these changes in the 64bit mode, since the
6698 lowering is more complicated. */
6700 && i.tm.opcode_modifier.todword
6701 && !i.types[0].bitfield.regsimd)
6703 /* Convert to DWORD. We don't want REX byte. */
6704 i.suffix = LONG_MNEM_SUFFIX;
6708 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6709 register_prefix, i.op[op].regs->reg_name,
6718 check_word_reg (void)
6721 for (op = i.operands; --op >= 0;)
6722 /* Skip non-register operands. */
6723 if (!i.types[op].bitfield.reg)
6725 /* Reject eight bit registers, except where the template requires
6726 them. (eg. movzb) */
6727 else if (i.types[op].bitfield.byte
6728 && (i.tm.operand_types[op].bitfield.reg
6729 || i.tm.operand_types[op].bitfield.acc)
6730 && (i.tm.operand_types[op].bitfield.word
6731 || i.tm.operand_types[op].bitfield.dword))
6733 as_bad (_("`%s%s' not allowed with `%s%c'"),
6735 i.op[op].regs->reg_name,
6740 /* Warn if the e or r prefix on a general reg is present. */
6741 else if ((!quiet_warnings || flag_code == CODE_64BIT)
6742 && (i.types[op].bitfield.dword
6743 || i.types[op].bitfield.qword)
6744 && (i.tm.operand_types[op].bitfield.reg
6745 || i.tm.operand_types[op].bitfield.acc)
6746 && i.tm.operand_types[op].bitfield.word)
6748 /* Prohibit these changes in the 64bit mode, since the
6749 lowering is more complicated. */
6750 if (flag_code == CODE_64BIT)
6752 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
6753 register_prefix, i.op[op].regs->reg_name,
6757 #if REGISTER_WARNINGS
6758 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6760 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6761 register_prefix, i.op[op].regs->reg_name, i.suffix);
6768 update_imm (unsigned int j)
6770 i386_operand_type overlap = i.types[j];
6771 if ((overlap.bitfield.imm8
6772 || overlap.bitfield.imm8s
6773 || overlap.bitfield.imm16
6774 || overlap.bitfield.imm32
6775 || overlap.bitfield.imm32s
6776 || overlap.bitfield.imm64)
6777 && !operand_type_equal (&overlap, &imm8)
6778 && !operand_type_equal (&overlap, &imm8s)
6779 && !operand_type_equal (&overlap, &imm16)
6780 && !operand_type_equal (&overlap, &imm32)
6781 && !operand_type_equal (&overlap, &imm32s)
6782 && !operand_type_equal (&overlap, &imm64))
6786 i386_operand_type temp;
6788 operand_type_set (&temp, 0);
6789 if (i.suffix == BYTE_MNEM_SUFFIX)
6791 temp.bitfield.imm8 = overlap.bitfield.imm8;
6792 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6794 else if (i.suffix == WORD_MNEM_SUFFIX)
6795 temp.bitfield.imm16 = overlap.bitfield.imm16;
6796 else if (i.suffix == QWORD_MNEM_SUFFIX)
6798 temp.bitfield.imm64 = overlap.bitfield.imm64;
6799 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6802 temp.bitfield.imm32 = overlap.bitfield.imm32;
6805 else if (operand_type_equal (&overlap, &imm16_32_32s)
6806 || operand_type_equal (&overlap, &imm16_32)
6807 || operand_type_equal (&overlap, &imm16_32s))
6809 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
6814 if (!operand_type_equal (&overlap, &imm8)
6815 && !operand_type_equal (&overlap, &imm8s)
6816 && !operand_type_equal (&overlap, &imm16)
6817 && !operand_type_equal (&overlap, &imm32)
6818 && !operand_type_equal (&overlap, &imm32s)
6819 && !operand_type_equal (&overlap, &imm64))
6821 as_bad (_("no instruction mnemonic suffix given; "
6822 "can't determine immediate size"));
6826 i.types[j] = overlap;
6836 /* Update the first 2 immediate operands. */
6837 n = i.operands > 2 ? 2 : i.operands;
6840 for (j = 0; j < n; j++)
6841 if (update_imm (j) == 0)
6844 /* The 3rd operand can't be immediate operand. */
6845 gas_assert (operand_type_check (i.types[2], imm) == 0);
6852 process_operands (void)
6854 /* Default segment register this instruction will use for memory
6855 accesses. 0 means unknown. This is only for optimizing out
6856 unnecessary segment overrides. */
6857 const seg_entry *default_seg = 0;
6859 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6861 unsigned int dupl = i.operands;
6862 unsigned int dest = dupl - 1;
6865 /* The destination must be an xmm register. */
6866 gas_assert (i.reg_operands
6867 && MAX_OPERANDS > dupl
6868 && operand_type_equal (&i.types[dest], ®xmm));
6870 if (i.tm.operand_types[0].bitfield.acc
6871 && i.tm.operand_types[0].bitfield.xmmword)
6873 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6875 /* Keep xmm0 for instructions with VEX prefix and 3
6877 i.tm.operand_types[0].bitfield.acc = 0;
6878 i.tm.operand_types[0].bitfield.regsimd = 1;
6883 /* We remove the first xmm0 and keep the number of
6884 operands unchanged, which in fact duplicates the
6886 for (j = 1; j < i.operands; j++)
6888 i.op[j - 1] = i.op[j];
6889 i.types[j - 1] = i.types[j];
6890 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6894 else if (i.tm.opcode_modifier.implicit1stxmm0)
6896 gas_assert ((MAX_OPERANDS - 1) > dupl
6897 && (i.tm.opcode_modifier.vexsources
6900 /* Add the implicit xmm0 for instructions with VEX prefix
6902 for (j = i.operands; j > 0; j--)
6904 i.op[j] = i.op[j - 1];
6905 i.types[j] = i.types[j - 1];
6906 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6909 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6910 i.types[0] = regxmm;
6911 i.tm.operand_types[0] = regxmm;
6914 i.reg_operands += 2;
6919 i.op[dupl] = i.op[dest];
6920 i.types[dupl] = i.types[dest];
6921 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6930 i.op[dupl] = i.op[dest];
6931 i.types[dupl] = i.types[dest];
6932 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6935 if (i.tm.opcode_modifier.immext)
6938 else if (i.tm.operand_types[0].bitfield.acc
6939 && i.tm.operand_types[0].bitfield.xmmword)
6943 for (j = 1; j < i.operands; j++)
6945 i.op[j - 1] = i.op[j];
6946 i.types[j - 1] = i.types[j];
6948 /* We need to adjust fields in i.tm since they are used by
6949 build_modrm_byte. */
6950 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6957 else if (i.tm.opcode_modifier.implicitquadgroup)
6959 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6961 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6962 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6963 regnum = register_number (i.op[1].regs);
6964 first_reg_in_group = regnum & ~3;
6965 last_reg_in_group = first_reg_in_group + 3;
6966 if (regnum != first_reg_in_group)
6967 as_warn (_("source register `%s%s' implicitly denotes"
6968 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6969 register_prefix, i.op[1].regs->reg_name,
6970 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6971 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6974 else if (i.tm.opcode_modifier.regkludge)
6976 /* The imul $imm, %reg instruction is converted into
6977 imul $imm, %reg, %reg, and the clr %reg instruction
6978 is converted into xor %reg, %reg. */
6980 unsigned int first_reg_op;
6982 if (operand_type_check (i.types[0], reg))
6986 /* Pretend we saw the extra register operand. */
6987 gas_assert (i.reg_operands == 1
6988 && i.op[first_reg_op + 1].regs == 0);
6989 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6990 i.types[first_reg_op + 1] = i.types[first_reg_op];
6995 if (i.tm.opcode_modifier.shortform)
6997 if (i.types[0].bitfield.sreg2
6998 || i.types[0].bitfield.sreg3)
7000 if (i.tm.base_opcode == POP_SEG_SHORT
7001 && i.op[0].regs->reg_num == 1)
7003 as_bad (_("you can't `pop %scs'"), register_prefix);
7006 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
7007 if ((i.op[0].regs->reg_flags & RegRex) != 0)
7012 /* The register or float register operand is in operand
7016 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7017 || operand_type_check (i.types[0], reg))
7021 /* Register goes in low 3 bits of opcode. */
7022 i.tm.base_opcode |= i.op[op].regs->reg_num;
7023 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7025 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
7027 /* Warn about some common errors, but press on regardless.
7028 The first case can be generated by gcc (<= 2.8.1). */
7029 if (i.operands == 2)
7031 /* Reversed arguments on faddp, fsubp, etc. */
7032 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
7033 register_prefix, i.op[!intel_syntax].regs->reg_name,
7034 register_prefix, i.op[intel_syntax].regs->reg_name);
7038 /* Extraneous `l' suffix on fp insn. */
7039 as_warn (_("translating to `%s %s%s'"), i.tm.name,
7040 register_prefix, i.op[0].regs->reg_name);
7045 else if (i.tm.opcode_modifier.modrm)
7047 /* The opcode is completed (modulo i.tm.extension_opcode which
7048 must be put into the modrm byte). Now, we make the modrm and
7049 index base bytes based on all the info we've collected. */
7051 default_seg = build_modrm_byte ();
7053 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
7057 else if (i.tm.opcode_modifier.isstring)
7059 /* For the string instructions that allow a segment override
7060 on one of their operands, the default segment is ds. */
7064 if (i.tm.base_opcode == 0x8d /* lea */
7067 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
7069 /* If a segment was explicitly specified, and the specified segment
7070 is not the default, use an opcode prefix to select it. If we
7071 never figured out what the default segment is, then default_seg
7072 will be zero at this point, and the specified segment prefix will
7074 if ((i.seg[0]) && (i.seg[0] != default_seg))
7076 if (!add_prefix (i.seg[0]->seg_prefix))
7082 static const seg_entry *
7083 build_modrm_byte (void)
7085 const seg_entry *default_seg = 0;
7086 unsigned int source, dest;
7089 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
7092 unsigned int nds, reg_slot;
7095 dest = i.operands - 1;
7098 /* There are 2 kinds of instructions:
7099 1. 5 operands: 4 register operands or 3 register operands
7100 plus 1 memory operand plus one Imm4 operand, VexXDS, and
7101 VexW0 or VexW1. The destination must be either XMM, YMM or
7103 2. 4 operands: 4 register operands or 3 register operands
7104 plus 1 memory operand, with VexXDS. */
7105 gas_assert ((i.reg_operands == 4
7106 || (i.reg_operands == 3 && i.mem_operands == 1))
7107 && i.tm.opcode_modifier.vexvvvv == VEXXDS
7108 && i.tm.opcode_modifier.vexw
7109 && i.tm.operand_types[dest].bitfield.regsimd);
7111 /* If VexW1 is set, the first non-immediate operand is the source and
7112 the second non-immediate one is encoded in the immediate operand. */
7113 if (i.tm.opcode_modifier.vexw == VEXW1)
7115 source = i.imm_operands;
7116 reg_slot = i.imm_operands + 1;
7120 source = i.imm_operands + 1;
7121 reg_slot = i.imm_operands;
7124 if (i.imm_operands == 0)
7126 /* When there is no immediate operand, generate an 8bit
7127 immediate operand to encode the first operand. */
7128 exp = &im_expressions[i.imm_operands++];
7129 i.op[i.operands].imms = exp;
7130 i.types[i.operands] = imm8;
7133 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
7134 exp->X_op = O_constant;
7135 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
7136 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7140 gas_assert (i.imm_operands == 1);
7141 gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number));
7142 gas_assert (!i.tm.opcode_modifier.immext);
7144 /* Turn on Imm8 again so that output_imm will generate it. */
7145 i.types[0].bitfield.imm8 = 1;
7147 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
7148 i.op[0].imms->X_add_number
7149 |= register_number (i.op[reg_slot].regs) << 4;
7150 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
7153 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
7154 i.vex.register_specifier = i.op[nds].regs;
7159 /* i.reg_operands MUST be the number of real register operands;
7160 implicit registers do not count. If there are 3 register
7161 operands, it must be a instruction with VexNDS. For a
7162 instruction with VexNDD, the destination register is encoded
7163 in VEX prefix. If there are 4 register operands, it must be
7164 a instruction with VEX prefix and 3 sources. */
7165 if (i.mem_operands == 0
7166 && ((i.reg_operands == 2
7167 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7168 || (i.reg_operands == 3
7169 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7170 || (i.reg_operands == 4 && vex_3_sources)))
7178 /* When there are 3 operands, one of them may be immediate,
7179 which may be the first or the last operand. Otherwise,
7180 the first operand must be shift count register (cl) or it
7181 is an instruction with VexNDS. */
7182 gas_assert (i.imm_operands == 1
7183 || (i.imm_operands == 0
7184 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7185 || i.types[0].bitfield.shiftcount)));
7186 if (operand_type_check (i.types[0], imm)
7187 || i.types[0].bitfield.shiftcount)
7193 /* When there are 4 operands, the first two must be 8bit
7194 immediate operands. The source operand will be the 3rd
7197 For instructions with VexNDS, if the first operand
7198 an imm8, the source operand is the 2nd one. If the last
7199 operand is imm8, the source operand is the first one. */
7200 gas_assert ((i.imm_operands == 2
7201 && i.types[0].bitfield.imm8
7202 && i.types[1].bitfield.imm8)
7203 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7204 && i.imm_operands == 1
7205 && (i.types[0].bitfield.imm8
7206 || i.types[i.operands - 1].bitfield.imm8
7208 if (i.imm_operands == 2)
7212 if (i.types[0].bitfield.imm8)
7219 if (is_evex_encoding (&i.tm))
7221 /* For EVEX instructions, when there are 5 operands, the
7222 first one must be immediate operand. If the second one
7223 is immediate operand, the source operand is the 3th
7224 one. If the last one is immediate operand, the source
7225 operand is the 2nd one. */
7226 gas_assert (i.imm_operands == 2
7227 && i.tm.opcode_modifier.sae
7228 && operand_type_check (i.types[0], imm));
7229 if (operand_type_check (i.types[1], imm))
7231 else if (operand_type_check (i.types[4], imm))
7245 /* RC/SAE operand could be between DEST and SRC. That happens
7246 when one operand is GPR and the other one is XMM/YMM/ZMM
7248 if (i.rounding && i.rounding->operand == (int) dest)
7251 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7253 /* For instructions with VexNDS, the register-only source
7254 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
7255 register. It is encoded in VEX prefix. We need to
7256 clear RegMem bit before calling operand_type_equal. */
7258 i386_operand_type op;
7261 /* Check register-only source operand when two source
7262 operands are swapped. */
7263 if (!i.tm.operand_types[source].bitfield.baseindex
7264 && i.tm.operand_types[dest].bitfield.baseindex)
7272 op = i.tm.operand_types[vvvv];
7273 op.bitfield.regmem = 0;
7274 if ((dest + 1) >= i.operands
7275 || ((!op.bitfield.reg
7276 || (!op.bitfield.dword && !op.bitfield.qword))
7277 && !op.bitfield.regsimd
7278 && !operand_type_equal (&op, ®mask)))
7280 i.vex.register_specifier = i.op[vvvv].regs;
7286 /* One of the register operands will be encoded in the i.tm.reg
7287 field, the other in the combined i.tm.mode and i.tm.regmem
7288 fields. If no form of this instruction supports a memory
7289 destination operand, then we assume the source operand may
7290 sometimes be a memory operand and so we need to store the
7291 destination in the i.rm.reg field. */
7292 if (!i.tm.operand_types[dest].bitfield.regmem
7293 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
7295 i.rm.reg = i.op[dest].regs->reg_num;
7296 i.rm.regmem = i.op[source].regs->reg_num;
7297 if (i.op[dest].regs->reg_type.bitfield.regmmx
7298 || i.op[source].regs->reg_type.bitfield.regmmx)
7299 i.has_regmmx = TRUE;
7300 else if (i.op[dest].regs->reg_type.bitfield.regsimd
7301 || i.op[source].regs->reg_type.bitfield.regsimd)
7303 if (i.types[dest].bitfield.zmmword
7304 || i.types[source].bitfield.zmmword)
7305 i.has_regzmm = TRUE;
7306 else if (i.types[dest].bitfield.ymmword
7307 || i.types[source].bitfield.ymmword)
7308 i.has_regymm = TRUE;
7310 i.has_regxmm = TRUE;
7312 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7314 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7316 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7318 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7323 i.rm.reg = i.op[source].regs->reg_num;
7324 i.rm.regmem = i.op[dest].regs->reg_num;
7325 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
7327 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
7329 if ((i.op[source].regs->reg_flags & RegRex) != 0)
7331 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
7334 if (flag_code != CODE_64BIT && (i.rex & REX_R))
7336 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
7339 add_prefix (LOCK_PREFIX_OPCODE);
7343 { /* If it's not 2 reg operands... */
7348 unsigned int fake_zero_displacement = 0;
7351 for (op = 0; op < i.operands; op++)
7352 if (operand_type_check (i.types[op], anymem))
7354 gas_assert (op < i.operands);
7356 if (i.tm.opcode_modifier.vecsib)
7358 if (i.index_reg->reg_num == RegIZ)
7361 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7364 i.sib.base = NO_BASE_REGISTER;
7365 i.sib.scale = i.log2_scale_factor;
7366 i.types[op].bitfield.disp8 = 0;
7367 i.types[op].bitfield.disp16 = 0;
7368 i.types[op].bitfield.disp64 = 0;
7369 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7371 /* Must be 32 bit */
7372 i.types[op].bitfield.disp32 = 1;
7373 i.types[op].bitfield.disp32s = 0;
7377 i.types[op].bitfield.disp32 = 0;
7378 i.types[op].bitfield.disp32s = 1;
7381 i.sib.index = i.index_reg->reg_num;
7382 if ((i.index_reg->reg_flags & RegRex) != 0)
7384 if ((i.index_reg->reg_flags & RegVRex) != 0)
7390 if (i.base_reg == 0)
7393 if (!i.disp_operands)
7394 fake_zero_displacement = 1;
7395 if (i.index_reg == 0)
7397 i386_operand_type newdisp;
7399 gas_assert (!i.tm.opcode_modifier.vecsib);
7400 /* Operand is just <disp> */
7401 if (flag_code == CODE_64BIT)
7403 /* 64bit mode overwrites the 32bit absolute
7404 addressing by RIP relative addressing and
7405 absolute addressing is encoded by one of the
7406 redundant SIB forms. */
7407 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7408 i.sib.base = NO_BASE_REGISTER;
7409 i.sib.index = NO_INDEX_REGISTER;
7410 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
7412 else if ((flag_code == CODE_16BIT)
7413 ^ (i.prefix[ADDR_PREFIX] != 0))
7415 i.rm.regmem = NO_BASE_REGISTER_16;
7420 i.rm.regmem = NO_BASE_REGISTER;
7423 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7424 i.types[op] = operand_type_or (i.types[op], newdisp);
7426 else if (!i.tm.opcode_modifier.vecsib)
7428 /* !i.base_reg && i.index_reg */
7429 if (i.index_reg->reg_num == RegIZ)
7430 i.sib.index = NO_INDEX_REGISTER;
7432 i.sib.index = i.index_reg->reg_num;
7433 i.sib.base = NO_BASE_REGISTER;
7434 i.sib.scale = i.log2_scale_factor;
7435 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7436 i.types[op].bitfield.disp8 = 0;
7437 i.types[op].bitfield.disp16 = 0;
7438 i.types[op].bitfield.disp64 = 0;
7439 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
7441 /* Must be 32 bit */
7442 i.types[op].bitfield.disp32 = 1;
7443 i.types[op].bitfield.disp32s = 0;
7447 i.types[op].bitfield.disp32 = 0;
7448 i.types[op].bitfield.disp32s = 1;
7450 if ((i.index_reg->reg_flags & RegRex) != 0)
7454 /* RIP addressing for 64bit mode. */
7455 else if (i.base_reg->reg_num == RegIP)
7457 gas_assert (!i.tm.opcode_modifier.vecsib);
7458 i.rm.regmem = NO_BASE_REGISTER;
7459 i.types[op].bitfield.disp8 = 0;
7460 i.types[op].bitfield.disp16 = 0;
7461 i.types[op].bitfield.disp32 = 0;
7462 i.types[op].bitfield.disp32s = 1;
7463 i.types[op].bitfield.disp64 = 0;
7464 i.flags[op] |= Operand_PCrel;
7465 if (! i.disp_operands)
7466 fake_zero_displacement = 1;
7468 else if (i.base_reg->reg_type.bitfield.word)
7470 gas_assert (!i.tm.opcode_modifier.vecsib);
7471 switch (i.base_reg->reg_num)
7474 if (i.index_reg == 0)
7476 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7477 i.rm.regmem = i.index_reg->reg_num - 6;
7481 if (i.index_reg == 0)
7484 if (operand_type_check (i.types[op], disp) == 0)
7486 /* fake (%bp) into 0(%bp) */
7487 i.types[op].bitfield.disp8 = 1;
7488 fake_zero_displacement = 1;
7491 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7492 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7494 default: /* (%si) -> 4 or (%di) -> 5 */
7495 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7497 i.rm.mode = mode_from_disp_size (i.types[op]);
7499 else /* i.base_reg and 32/64 bit mode */
7501 if (flag_code == CODE_64BIT
7502 && operand_type_check (i.types[op], disp))
7504 i.types[op].bitfield.disp16 = 0;
7505 i.types[op].bitfield.disp64 = 0;
7506 if (i.prefix[ADDR_PREFIX] == 0)
7508 i.types[op].bitfield.disp32 = 0;
7509 i.types[op].bitfield.disp32s = 1;
7513 i.types[op].bitfield.disp32 = 1;
7514 i.types[op].bitfield.disp32s = 0;
7518 if (!i.tm.opcode_modifier.vecsib)
7519 i.rm.regmem = i.base_reg->reg_num;
7520 if ((i.base_reg->reg_flags & RegRex) != 0)
7522 i.sib.base = i.base_reg->reg_num;
7523 /* x86-64 ignores REX prefix bit here to avoid decoder
7525 if (!(i.base_reg->reg_flags & RegRex)
7526 && (i.base_reg->reg_num == EBP_REG_NUM
7527 || i.base_reg->reg_num == ESP_REG_NUM))
7529 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
7531 fake_zero_displacement = 1;
7532 i.types[op].bitfield.disp8 = 1;
7534 i.sib.scale = i.log2_scale_factor;
7535 if (i.index_reg == 0)
7537 gas_assert (!i.tm.opcode_modifier.vecsib);
7538 /* <disp>(%esp) becomes two byte modrm with no index
7539 register. We've already stored the code for esp
7540 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7541 Any base register besides %esp will not use the
7542 extra modrm byte. */
7543 i.sib.index = NO_INDEX_REGISTER;
7545 else if (!i.tm.opcode_modifier.vecsib)
7547 if (i.index_reg->reg_num == RegIZ)
7548 i.sib.index = NO_INDEX_REGISTER;
7550 i.sib.index = i.index_reg->reg_num;
7551 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7552 if ((i.index_reg->reg_flags & RegRex) != 0)
7557 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7558 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7562 if (!fake_zero_displacement
7566 fake_zero_displacement = 1;
7567 if (i.disp_encoding == disp_encoding_8bit)
7568 i.types[op].bitfield.disp8 = 1;
7570 i.types[op].bitfield.disp32 = 1;
7572 i.rm.mode = mode_from_disp_size (i.types[op]);
7576 if (fake_zero_displacement)
7578 /* Fakes a zero displacement assuming that i.types[op]
7579 holds the correct displacement size. */
7582 gas_assert (i.op[op].disps == 0);
7583 exp = &disp_expressions[i.disp_operands++];
7584 i.op[op].disps = exp;
7585 exp->X_op = O_constant;
7586 exp->X_add_number = 0;
7587 exp->X_add_symbol = (symbolS *) 0;
7588 exp->X_op_symbol = (symbolS *) 0;
7596 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
7598 if (operand_type_check (i.types[0], imm))
7599 i.vex.register_specifier = NULL;
7602 /* VEX.vvvv encodes one of the sources when the first
7603 operand is not an immediate. */
7604 if (i.tm.opcode_modifier.vexw == VEXW0)
7605 i.vex.register_specifier = i.op[0].regs;
7607 i.vex.register_specifier = i.op[1].regs;
7610 /* Destination is a XMM register encoded in the ModRM.reg
7612 i.rm.reg = i.op[2].regs->reg_num;
7613 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7616 /* ModRM.rm and VEX.B encodes the other source. */
7617 if (!i.mem_operands)
7621 if (i.tm.opcode_modifier.vexw == VEXW0)
7622 i.rm.regmem = i.op[1].regs->reg_num;
7624 i.rm.regmem = i.op[0].regs->reg_num;
7626 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7630 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
7632 i.vex.register_specifier = i.op[2].regs;
7633 if (!i.mem_operands)
7636 i.rm.regmem = i.op[1].regs->reg_num;
7637 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7641 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7642 (if any) based on i.tm.extension_opcode. Again, we must be
7643 careful to make sure that segment/control/debug/test/MMX
7644 registers are coded into the i.rm.reg field. */
7645 else if (i.reg_operands)
7648 unsigned int vex_reg = ~0;
7650 for (op = 0; op < i.operands; op++)
7652 if (i.types[op].bitfield.reg
7653 || i.types[op].bitfield.regbnd
7654 || i.types[op].bitfield.regmask
7655 || i.types[op].bitfield.sreg2
7656 || i.types[op].bitfield.sreg3
7657 || i.types[op].bitfield.control
7658 || i.types[op].bitfield.debug
7659 || i.types[op].bitfield.test)
7661 if (i.types[op].bitfield.regsimd)
7663 if (i.types[op].bitfield.zmmword)
7664 i.has_regzmm = TRUE;
7665 else if (i.types[op].bitfield.ymmword)
7666 i.has_regymm = TRUE;
7668 i.has_regxmm = TRUE;
7671 if (i.types[op].bitfield.regmmx)
7673 i.has_regmmx = TRUE;
7680 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7682 /* For instructions with VexNDS, the register-only
7683 source operand is encoded in VEX prefix. */
7684 gas_assert (mem != (unsigned int) ~0);
7689 gas_assert (op < i.operands);
7693 /* Check register-only source operand when two source
7694 operands are swapped. */
7695 if (!i.tm.operand_types[op].bitfield.baseindex
7696 && i.tm.operand_types[op + 1].bitfield.baseindex)
7700 gas_assert (mem == (vex_reg + 1)
7701 && op < i.operands);
7706 gas_assert (vex_reg < i.operands);
7710 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7712 /* For instructions with VexNDD, the register destination
7713 is encoded in VEX prefix. */
7714 if (i.mem_operands == 0)
7716 /* There is no memory operand. */
7717 gas_assert ((op + 2) == i.operands);
7722 /* There are only 2 non-immediate operands. */
7723 gas_assert (op < i.imm_operands + 2
7724 && i.operands == i.imm_operands + 2);
7725 vex_reg = i.imm_operands + 1;
7729 gas_assert (op < i.operands);
7731 if (vex_reg != (unsigned int) ~0)
7733 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7735 if ((!type->bitfield.reg
7736 || (!type->bitfield.dword && !type->bitfield.qword))
7737 && !type->bitfield.regsimd
7738 && !operand_type_equal (type, ®mask))
7741 i.vex.register_specifier = i.op[vex_reg].regs;
7744 /* Don't set OP operand twice. */
7747 /* If there is an extension opcode to put here, the
7748 register number must be put into the regmem field. */
7749 if (i.tm.extension_opcode != None)
7751 i.rm.regmem = i.op[op].regs->reg_num;
7752 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7754 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7759 i.rm.reg = i.op[op].regs->reg_num;
7760 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7762 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7767 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7768 must set it to 3 to indicate this is a register operand
7769 in the regmem field. */
7770 if (!i.mem_operands)
7774 /* Fill in i.rm.reg field with extension opcode (if any). */
7775 if (i.tm.extension_opcode != None)
7776 i.rm.reg = i.tm.extension_opcode;
7782 output_branch (void)
7788 relax_substateT subtype;
7792 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
7793 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
7796 if (i.prefix[DATA_PREFIX] != 0)
7802 /* Pentium4 branch hints. */
7803 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7804 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7809 if (i.prefix[REX_PREFIX] != 0)
7815 /* BND prefixed jump. */
7816 if (i.prefix[BND_PREFIX] != 0)
7818 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7822 if (i.prefixes != 0 && !intel_syntax)
7823 as_warn (_("skipping prefixes on this instruction"));
7825 /* It's always a symbol; End frag & setup for relax.
7826 Make sure there is enough room in this frag for the largest
7827 instruction we may generate in md_convert_frag. This is 2
7828 bytes for the opcode and room for the prefix and largest
7830 frag_grow (prefix + 2 + 4);
7831 /* Prefix and 1 opcode byte go in fr_fix. */
7832 p = frag_more (prefix + 1);
7833 if (i.prefix[DATA_PREFIX] != 0)
7834 *p++ = DATA_PREFIX_OPCODE;
7835 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7836 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7837 *p++ = i.prefix[SEG_PREFIX];
7838 if (i.prefix[REX_PREFIX] != 0)
7839 *p++ = i.prefix[REX_PREFIX];
7840 *p = i.tm.base_opcode;
7842 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7843 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7844 else if (cpu_arch_flags.bitfield.cpui386)
7845 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7847 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7850 sym = i.op[0].disps->X_add_symbol;
7851 off = i.op[0].disps->X_add_number;
7853 if (i.op[0].disps->X_op != O_constant
7854 && i.op[0].disps->X_op != O_symbol)
7856 /* Handle complex expressions. */
7857 sym = make_expr_symbol (i.op[0].disps);
7861 /* 1 possible extra opcode + 4 byte displacement go in var part.
7862 Pass reloc in fr_var. */
7863 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7866 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7867 /* Return TRUE iff PLT32 relocation should be used for branching to
7871 need_plt32_p (symbolS *s)
7873 /* PLT32 relocation is ELF only. */
7878 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
7879 krtld support it. */
7883 /* Since there is no need to prepare for PLT branch on x86-64, we
7884 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7885 be used as a marker for 32-bit PC-relative branches. */
7889 /* Weak or undefined symbol need PLT32 relocation. */
7890 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7893 /* Non-global symbol doesn't need PLT32 relocation. */
7894 if (! S_IS_EXTERNAL (s))
7897 /* Other global symbols need PLT32 relocation. NB: Symbol with
7898 non-default visibilities are treated as normal global symbol
7899 so that PLT32 relocation can be used as a marker for 32-bit
7900 PC-relative branches. It is useful for linker relaxation. */
7911 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7913 if (i.tm.opcode_modifier.jumpbyte)
7915 /* This is a loop or jecxz type instruction. */
7917 if (i.prefix[ADDR_PREFIX] != 0)
7919 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7922 /* Pentium4 branch hints. */
7923 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7924 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7926 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7935 if (flag_code == CODE_16BIT)
7938 if (i.prefix[DATA_PREFIX] != 0)
7940 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7950 if (i.prefix[REX_PREFIX] != 0)
7952 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7956 /* BND prefixed jump. */
7957 if (i.prefix[BND_PREFIX] != 0)
7959 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7963 if (i.prefixes != 0 && !intel_syntax)
7964 as_warn (_("skipping prefixes on this instruction"));
7966 p = frag_more (i.tm.opcode_length + size);
7967 switch (i.tm.opcode_length)
7970 *p++ = i.tm.base_opcode >> 8;
7973 *p++ = i.tm.base_opcode;
7979 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7981 && jump_reloc == NO_RELOC
7982 && need_plt32_p (i.op[0].disps->X_add_symbol))
7983 jump_reloc = BFD_RELOC_X86_64_PLT32;
7986 jump_reloc = reloc (size, 1, 1, jump_reloc);
7988 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7989 i.op[0].disps, 1, jump_reloc);
7991 /* All jumps handled here are signed, but don't use a signed limit
7992 check for 32 and 16 bit jumps as we want to allow wrap around at
7993 4G and 64k respectively. */
7995 fixP->fx_signed = 1;
7999 output_interseg_jump (void)
8007 if (flag_code == CODE_16BIT)
8011 if (i.prefix[DATA_PREFIX] != 0)
8017 if (i.prefix[REX_PREFIX] != 0)
8027 if (i.prefixes != 0 && !intel_syntax)
8028 as_warn (_("skipping prefixes on this instruction"));
8030 /* 1 opcode; 2 segment; offset */
8031 p = frag_more (prefix + 1 + 2 + size);
8033 if (i.prefix[DATA_PREFIX] != 0)
8034 *p++ = DATA_PREFIX_OPCODE;
8036 if (i.prefix[REX_PREFIX] != 0)
8037 *p++ = i.prefix[REX_PREFIX];
8039 *p++ = i.tm.base_opcode;
8040 if (i.op[1].imms->X_op == O_constant)
8042 offsetT n = i.op[1].imms->X_add_number;
8045 && !fits_in_unsigned_word (n)
8046 && !fits_in_signed_word (n))
8048 as_bad (_("16-bit jump out of range"));
8051 md_number_to_chars (p, n, size);
8054 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8055 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
8056 if (i.op[0].imms->X_op != O_constant)
8057 as_bad (_("can't handle non absolute segment in `%s'"),
8059 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
8062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8067 asection *seg = now_seg;
8068 subsegT subseg = now_subseg;
8070 unsigned int alignment, align_size_1;
8071 unsigned int isa_1_descsz, feature_2_descsz, descsz;
8072 unsigned int isa_1_descsz_raw, feature_2_descsz_raw;
8073 unsigned int padding;
8075 if (!IS_ELF || !x86_used_note)
8078 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86;
8080 /* The .note.gnu.property section layout:
8082 Field Length Contents
8085 n_descsz 4 The note descriptor size
8086 n_type 4 NT_GNU_PROPERTY_TYPE_0
8088 n_desc n_descsz The program property array
8092 /* Create the .note.gnu.property section. */
8093 sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0);
8094 bfd_set_section_flags (stdoutput, sec,
8101 if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64)
8112 bfd_set_section_alignment (stdoutput, sec, alignment);
8113 elf_section_type (sec) = SHT_NOTE;
8115 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
8117 isa_1_descsz_raw = 4 + 4 + 4;
8118 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
8119 isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1;
8121 feature_2_descsz_raw = isa_1_descsz;
8122 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
8124 feature_2_descsz_raw += 4 + 4 + 4;
8125 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
8126 feature_2_descsz = ((feature_2_descsz_raw + align_size_1)
8129 descsz = feature_2_descsz;
8130 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
8131 p = frag_more (4 + 4 + 4 + 4 + descsz);
8133 /* Write n_namsz. */
8134 md_number_to_chars (p, (valueT) 4, 4);
8136 /* Write n_descsz. */
8137 md_number_to_chars (p + 4, (valueT) descsz, 4);
8140 md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4);
8143 memcpy (p + 4 * 3, "GNU", 4);
8145 /* Write 4-byte type. */
8146 md_number_to_chars (p + 4 * 4,
8147 (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4);
8149 /* Write 4-byte data size. */
8150 md_number_to_chars (p + 4 * 5, (valueT) 4, 4);
8152 /* Write 4-byte data. */
8153 md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4);
8155 /* Zero out paddings. */
8156 padding = isa_1_descsz - isa_1_descsz_raw;
8158 memset (p + 4 * 7, 0, padding);
8160 /* Write 4-byte type. */
8161 md_number_to_chars (p + isa_1_descsz + 4 * 4,
8162 (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4);
8164 /* Write 4-byte data size. */
8165 md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4);
8167 /* Write 4-byte data. */
8168 md_number_to_chars (p + isa_1_descsz + 4 * 6,
8169 (valueT) x86_feature_2_used, 4);
8171 /* Zero out paddings. */
8172 padding = feature_2_descsz - feature_2_descsz_raw;
8174 memset (p + isa_1_descsz + 4 * 7, 0, padding);
8176 /* We probably can't restore the current segment, for there likely
8179 subseg_set (seg, subseg);
8184 encoding_length (const fragS *start_frag, offsetT start_off,
8185 const char *frag_now_ptr)
8187 unsigned int len = 0;
8189 if (start_frag != frag_now)
8191 const fragS *fr = start_frag;
8196 } while (fr && fr != frag_now);
8199 return len - start_off + (frag_now_ptr - frag_now->fr_literal);
8205 fragS *insn_start_frag;
8206 offsetT insn_start_off;
8208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8209 if (IS_ELF && x86_used_note)
8211 if (i.tm.cpu_flags.bitfield.cpucmov)
8212 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV;
8213 if (i.tm.cpu_flags.bitfield.cpusse)
8214 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE;
8215 if (i.tm.cpu_flags.bitfield.cpusse2)
8216 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2;
8217 if (i.tm.cpu_flags.bitfield.cpusse3)
8218 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3;
8219 if (i.tm.cpu_flags.bitfield.cpussse3)
8220 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3;
8221 if (i.tm.cpu_flags.bitfield.cpusse4_1)
8222 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1;
8223 if (i.tm.cpu_flags.bitfield.cpusse4_2)
8224 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2;
8225 if (i.tm.cpu_flags.bitfield.cpuavx)
8226 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX;
8227 if (i.tm.cpu_flags.bitfield.cpuavx2)
8228 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2;
8229 if (i.tm.cpu_flags.bitfield.cpufma)
8230 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA;
8231 if (i.tm.cpu_flags.bitfield.cpuavx512f)
8232 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F;
8233 if (i.tm.cpu_flags.bitfield.cpuavx512cd)
8234 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD;
8235 if (i.tm.cpu_flags.bitfield.cpuavx512er)
8236 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER;
8237 if (i.tm.cpu_flags.bitfield.cpuavx512pf)
8238 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF;
8239 if (i.tm.cpu_flags.bitfield.cpuavx512vl)
8240 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL;
8241 if (i.tm.cpu_flags.bitfield.cpuavx512dq)
8242 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ;
8243 if (i.tm.cpu_flags.bitfield.cpuavx512bw)
8244 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW;
8245 if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps)
8246 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS;
8247 if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)
8248 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW;
8249 if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg)
8250 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG;
8251 if (i.tm.cpu_flags.bitfield.cpuavx512ifma)
8252 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA;
8253 if (i.tm.cpu_flags.bitfield.cpuavx512vbmi)
8254 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI;
8255 if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2)
8256 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2;
8257 if (i.tm.cpu_flags.bitfield.cpuavx512_vnni)
8258 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI;
8259 if (i.tm.cpu_flags.bitfield.cpuavx512_bf16)
8260 x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16;
8262 if (i.tm.cpu_flags.bitfield.cpu8087
8263 || i.tm.cpu_flags.bitfield.cpu287
8264 || i.tm.cpu_flags.bitfield.cpu387
8265 || i.tm.cpu_flags.bitfield.cpu687
8266 || i.tm.cpu_flags.bitfield.cpufisttp)
8267 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87;
8268 /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor
8269 Xfence instructions. */
8270 if (i.tm.base_opcode != 0xf18
8271 && i.tm.base_opcode != 0xf0d
8272 && i.tm.base_opcode != 0xfaef8
8274 || i.tm.cpu_flags.bitfield.cpummx
8275 || i.tm.cpu_flags.bitfield.cpua3dnow
8276 || i.tm.cpu_flags.bitfield.cpua3dnowa))
8277 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX;
8279 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM;
8281 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM;
8283 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM;
8284 if (i.tm.cpu_flags.bitfield.cpufxsr)
8285 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR;
8286 if (i.tm.cpu_flags.bitfield.cpuxsave)
8287 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE;
8288 if (i.tm.cpu_flags.bitfield.cpuxsaveopt)
8289 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT;
8290 if (i.tm.cpu_flags.bitfield.cpuxsavec)
8291 x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC;
8295 /* Tie dwarf2 debug info to the address at the start of the insn.
8296 We can't do this after the insn has been output as the current
8297 frag may have been closed off. eg. by frag_var. */
8298 dwarf2_emit_insn (0);
8300 insn_start_frag = frag_now;
8301 insn_start_off = frag_now_fix ();
8304 if (i.tm.opcode_modifier.jump)
8306 else if (i.tm.opcode_modifier.jumpbyte
8307 || i.tm.opcode_modifier.jumpdword)
8309 else if (i.tm.opcode_modifier.jumpintersegment)
8310 output_interseg_jump ();
8313 /* Output normal instructions here. */
8317 unsigned int prefix;
8320 && (i.tm.base_opcode == 0xfaee8
8321 || i.tm.base_opcode == 0xfaef0
8322 || i.tm.base_opcode == 0xfaef8))
8324 /* Encode lfence, mfence, and sfence as
8325 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
8326 offsetT val = 0x240483f0ULL;
8328 md_number_to_chars (p, val, 5);
8332 /* Some processors fail on LOCK prefix. This options makes
8333 assembler ignore LOCK prefix and serves as a workaround. */
8334 if (omit_lock_prefix)
8336 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
8338 i.prefix[LOCK_PREFIX] = 0;
8341 /* Since the VEX/EVEX prefix contains the implicit prefix, we
8342 don't need the explicit prefix. */
8343 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
8345 switch (i.tm.opcode_length)
8348 if (i.tm.base_opcode & 0xff000000)
8350 prefix = (i.tm.base_opcode >> 24) & 0xff;
8351 if (!i.tm.cpu_flags.bitfield.cpupadlock
8352 || prefix != REPE_PREFIX_OPCODE
8353 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
8354 add_prefix (prefix);
8358 if ((i.tm.base_opcode & 0xff0000) != 0)
8360 prefix = (i.tm.base_opcode >> 16) & 0xff;
8361 add_prefix (prefix);
8367 /* Check for pseudo prefixes. */
8368 as_bad_where (insn_start_frag->fr_file,
8369 insn_start_frag->fr_line,
8370 _("pseudo prefix without instruction"));
8376 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8377 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
8378 R_X86_64_GOTTPOFF relocation so that linker can safely
8379 perform IE->LE optimization. */
8380 if (x86_elf_abi == X86_64_X32_ABI
8382 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
8383 && i.prefix[REX_PREFIX] == 0)
8384 add_prefix (REX_OPCODE);
8387 /* The prefix bytes. */
8388 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
8390 FRAG_APPEND_1_CHAR (*q);
8394 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
8399 /* REX byte is encoded in VEX prefix. */
8403 FRAG_APPEND_1_CHAR (*q);
8406 /* There should be no other prefixes for instructions
8411 /* For EVEX instructions i.vrex should become 0 after
8412 build_evex_prefix. For VEX instructions upper 16 registers
8413 aren't available, so VREX should be 0. */
8416 /* Now the VEX prefix. */
8417 p = frag_more (i.vex.length);
8418 for (j = 0; j < i.vex.length; j++)
8419 p[j] = i.vex.bytes[j];
8422 /* Now the opcode; be careful about word order here! */
8423 if (i.tm.opcode_length == 1)
8425 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
8429 switch (i.tm.opcode_length)
8433 *p++ = (i.tm.base_opcode >> 24) & 0xff;
8434 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8438 *p++ = (i.tm.base_opcode >> 16) & 0xff;
8448 /* Put out high byte first: can't use md_number_to_chars! */
8449 *p++ = (i.tm.base_opcode >> 8) & 0xff;
8450 *p = i.tm.base_opcode & 0xff;
8453 /* Now the modrm byte and sib byte (if present). */
8454 if (i.tm.opcode_modifier.modrm)
8456 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
8459 /* If i.rm.regmem == ESP (4)
8460 && i.rm.mode != (Register mode)
8462 ==> need second modrm byte. */
8463 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
8465 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
8466 FRAG_APPEND_1_CHAR ((i.sib.base << 0
8468 | i.sib.scale << 6));
8471 if (i.disp_operands)
8472 output_disp (insn_start_frag, insn_start_off);
8475 output_imm (insn_start_frag, insn_start_off);
8478 * frag_now_fix () returning plain abs_section_offset when we're in the
8479 * absolute section, and abs_section_offset not getting updated as data
8480 * gets added to the frag breaks the logic below.
8482 if (now_seg != absolute_section)
8484 j = encoding_length (insn_start_frag, insn_start_off, frag_more (0));
8486 as_warn (_("instruction length of %u bytes exceeds the limit of 15"),
8494 pi ("" /*line*/, &i);
8496 #endif /* DEBUG386 */
8499 /* Return the size of the displacement operand N. */
8502 disp_size (unsigned int n)
8506 if (i.types[n].bitfield.disp64)
8508 else if (i.types[n].bitfield.disp8)
8510 else if (i.types[n].bitfield.disp16)
8515 /* Return the size of the immediate operand N. */
8518 imm_size (unsigned int n)
8521 if (i.types[n].bitfield.imm64)
8523 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
8525 else if (i.types[n].bitfield.imm16)
8531 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
8536 for (n = 0; n < i.operands; n++)
8538 if (operand_type_check (i.types[n], disp))
8540 if (i.op[n].disps->X_op == O_constant)
8542 int size = disp_size (n);
8543 offsetT val = i.op[n].disps->X_add_number;
8545 val = offset_in_range (val >> (size == 1 ? i.memshift : 0),
8547 p = frag_more (size);
8548 md_number_to_chars (p, val, size);
8552 enum bfd_reloc_code_real reloc_type;
8553 int size = disp_size (n);
8554 int sign = i.types[n].bitfield.disp32s;
8555 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
8558 /* We can't have 8 bit displacement here. */
8559 gas_assert (!i.types[n].bitfield.disp8);
8561 /* The PC relative address is computed relative
8562 to the instruction boundary, so in case immediate
8563 fields follows, we need to adjust the value. */
8564 if (pcrel && i.imm_operands)
8569 for (n1 = 0; n1 < i.operands; n1++)
8570 if (operand_type_check (i.types[n1], imm))
8572 /* Only one immediate is allowed for PC
8573 relative address. */
8574 gas_assert (sz == 0);
8576 i.op[n].disps->X_add_number -= sz;
8578 /* We should find the immediate. */
8579 gas_assert (sz != 0);
8582 p = frag_more (size);
8583 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
8585 && GOT_symbol == i.op[n].disps->X_add_symbol
8586 && (((reloc_type == BFD_RELOC_32
8587 || reloc_type == BFD_RELOC_X86_64_32S
8588 || (reloc_type == BFD_RELOC_64
8590 && (i.op[n].disps->X_op == O_symbol
8591 || (i.op[n].disps->X_op == O_add
8592 && ((symbol_get_value_expression
8593 (i.op[n].disps->X_op_symbol)->X_op)
8595 || reloc_type == BFD_RELOC_32_PCREL))
8599 reloc_type = BFD_RELOC_386_GOTPC;
8600 i.op[n].imms->X_add_number +=
8601 encoding_length (insn_start_frag, insn_start_off, p);
8603 else if (reloc_type == BFD_RELOC_64)
8604 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8606 /* Don't do the adjustment for x86-64, as there
8607 the pcrel addressing is relative to the _next_
8608 insn, and that is taken care of in other code. */
8609 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8611 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8612 size, i.op[n].disps, pcrel,
8614 /* Check for "call/jmp *mem", "mov mem, %reg",
8615 "test %reg, mem" and "binop mem, %reg" where binop
8616 is one of adc, add, and, cmp, or, sbb, sub, xor
8617 instructions without data prefix. Always generate
8618 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
8619 if (i.prefix[DATA_PREFIX] == 0
8620 && (generate_relax_relocations
8623 && i.rm.regmem == 5))
8625 || (i.rm.mode == 0 && i.rm.regmem == 5))
8626 && ((i.operands == 1
8627 && i.tm.base_opcode == 0xff
8628 && (i.rm.reg == 2 || i.rm.reg == 4))
8630 && (i.tm.base_opcode == 0x8b
8631 || i.tm.base_opcode == 0x85
8632 || (i.tm.base_opcode & 0xc7) == 0x03))))
8636 fixP->fx_tcbit = i.rex != 0;
8638 && (i.base_reg->reg_num == RegIP))
8639 fixP->fx_tcbit2 = 1;
8642 fixP->fx_tcbit2 = 1;
8650 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
8655 for (n = 0; n < i.operands; n++)
8657 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8658 if (i.rounding && (int) n == i.rounding->operand)
8661 if (operand_type_check (i.types[n], imm))
8663 if (i.op[n].imms->X_op == O_constant)
8665 int size = imm_size (n);
8668 val = offset_in_range (i.op[n].imms->X_add_number,
8670 p = frag_more (size);
8671 md_number_to_chars (p, val, size);
8675 /* Not absolute_section.
8676 Need a 32-bit fixup (don't support 8bit
8677 non-absolute imms). Try to support other
8679 enum bfd_reloc_code_real reloc_type;
8680 int size = imm_size (n);
8683 if (i.types[n].bitfield.imm32s
8684 && (i.suffix == QWORD_MNEM_SUFFIX
8685 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
8690 p = frag_more (size);
8691 reloc_type = reloc (size, 0, sign, i.reloc[n]);
8693 /* This is tough to explain. We end up with this one if we
8694 * have operands that look like
8695 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8696 * obtain the absolute address of the GOT, and it is strongly
8697 * preferable from a performance point of view to avoid using
8698 * a runtime relocation for this. The actual sequence of
8699 * instructions often look something like:
8704 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8706 * The call and pop essentially return the absolute address
8707 * of the label .L66 and store it in %ebx. The linker itself
8708 * will ultimately change the first operand of the addl so
8709 * that %ebx points to the GOT, but to keep things simple, the
8710 * .o file must have this operand set so that it generates not
8711 * the absolute address of .L66, but the absolute address of
8712 * itself. This allows the linker itself simply treat a GOTPC
8713 * relocation as asking for a pcrel offset to the GOT to be
8714 * added in, and the addend of the relocation is stored in the
8715 * operand field for the instruction itself.
8717 * Our job here is to fix the operand so that it would add
8718 * the correct offset so that %ebx would point to itself. The
8719 * thing that is tricky is that .-.L66 will point to the
8720 * beginning of the instruction, so we need to further modify
8721 * the operand so that it will point to itself. There are
8722 * other cases where you have something like:
8724 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8726 * and here no correction would be required. Internally in
8727 * the assembler we treat operands of this form as not being
8728 * pcrel since the '.' is explicitly mentioned, and I wonder
8729 * whether it would simplify matters to do it this way. Who
8730 * knows. In earlier versions of the PIC patches, the
8731 * pcrel_adjust field was used to store the correction, but
8732 * since the expression is not pcrel, I felt it would be
8733 * confusing to do it this way. */
8735 if ((reloc_type == BFD_RELOC_32
8736 || reloc_type == BFD_RELOC_X86_64_32S
8737 || reloc_type == BFD_RELOC_64)
8739 && GOT_symbol == i.op[n].imms->X_add_symbol
8740 && (i.op[n].imms->X_op == O_symbol
8741 || (i.op[n].imms->X_op == O_add
8742 && ((symbol_get_value_expression
8743 (i.op[n].imms->X_op_symbol)->X_op)
8747 reloc_type = BFD_RELOC_386_GOTPC;
8749 reloc_type = BFD_RELOC_X86_64_GOTPC32;
8751 reloc_type = BFD_RELOC_X86_64_GOTPC64;
8752 i.op[n].imms->X_add_number +=
8753 encoding_length (insn_start_frag, insn_start_off, p);
8755 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8756 i.op[n].imms, 0, reloc_type);
8762 /* x86_cons_fix_new is called via the expression parsing code when a
8763 reloc is needed. We use this hook to get the correct .got reloc. */
8764 static int cons_sign = -1;
8767 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
8768 expressionS *exp, bfd_reloc_code_real_type r)
8770 r = reloc (len, 0, cons_sign, r);
8773 if (exp->X_op == O_secrel)
8775 exp->X_op = O_symbol;
8776 r = BFD_RELOC_32_SECREL;
8780 fix_new_exp (frag, off, len, exp, 0, r);
8783 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8784 purpose of the `.dc.a' internal pseudo-op. */
8787 x86_address_bytes (void)
8789 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8791 return stdoutput->arch_info->bits_per_address / 8;
8794 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8796 # define lex_got(reloc, adjust, types) NULL
8798 /* Parse operands of the form
8799 <symbol>@GOTOFF+<nnn>
8800 and similar .plt or .got references.
8802 If we find one, set up the correct relocation in RELOC and copy the
8803 input string, minus the `@GOTOFF' into a malloc'd buffer for
8804 parsing by the calling routine. Return this buffer, and if ADJUST
8805 is non-null set it to the length of the string we removed from the
8806 input line. Otherwise return NULL. */
8808 lex_got (enum bfd_reloc_code_real *rel,
8810 i386_operand_type *types)
8812 /* Some of the relocations depend on the size of what field is to
8813 be relocated. But in our callers i386_immediate and i386_displacement
8814 we don't yet know the operand size (this will be set by insn
8815 matching). Hence we record the word32 relocation here,
8816 and adjust the reloc according to the real size in reloc(). */
8817 static const struct {
8820 const enum bfd_reloc_code_real rel[2];
8821 const i386_operand_type types64;
8823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8824 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8826 OPERAND_TYPE_IMM32_64 },
8828 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8829 BFD_RELOC_X86_64_PLTOFF64 },
8830 OPERAND_TYPE_IMM64 },
8831 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8832 BFD_RELOC_X86_64_PLT32 },
8833 OPERAND_TYPE_IMM32_32S_DISP32 },
8834 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8835 BFD_RELOC_X86_64_GOTPLT64 },
8836 OPERAND_TYPE_IMM64_DISP64 },
8837 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8838 BFD_RELOC_X86_64_GOTOFF64 },
8839 OPERAND_TYPE_IMM64_DISP64 },
8840 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8841 BFD_RELOC_X86_64_GOTPCREL },
8842 OPERAND_TYPE_IMM32_32S_DISP32 },
8843 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8844 BFD_RELOC_X86_64_TLSGD },
8845 OPERAND_TYPE_IMM32_32S_DISP32 },
8846 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8847 _dummy_first_bfd_reloc_code_real },
8848 OPERAND_TYPE_NONE },
8849 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8850 BFD_RELOC_X86_64_TLSLD },
8851 OPERAND_TYPE_IMM32_32S_DISP32 },
8852 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8853 BFD_RELOC_X86_64_GOTTPOFF },
8854 OPERAND_TYPE_IMM32_32S_DISP32 },
8855 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8856 BFD_RELOC_X86_64_TPOFF32 },
8857 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8858 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8859 _dummy_first_bfd_reloc_code_real },
8860 OPERAND_TYPE_NONE },
8861 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8862 BFD_RELOC_X86_64_DTPOFF32 },
8863 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8864 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8865 _dummy_first_bfd_reloc_code_real },
8866 OPERAND_TYPE_NONE },
8867 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8868 _dummy_first_bfd_reloc_code_real },
8869 OPERAND_TYPE_NONE },
8870 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8871 BFD_RELOC_X86_64_GOT32 },
8872 OPERAND_TYPE_IMM32_32S_64_DISP32 },
8873 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8874 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
8875 OPERAND_TYPE_IMM32_32S_DISP32 },
8876 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8877 BFD_RELOC_X86_64_TLSDESC_CALL },
8878 OPERAND_TYPE_IMM32_32S_DISP32 },
8883 #if defined (OBJ_MAYBE_ELF)
8888 for (cp = input_line_pointer; *cp != '@'; cp++)
8889 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8892 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8894 int len = gotrel[j].len;
8895 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8897 if (gotrel[j].rel[object_64bit] != 0)
8900 char *tmpbuf, *past_reloc;
8902 *rel = gotrel[j].rel[object_64bit];
8906 if (flag_code != CODE_64BIT)
8908 types->bitfield.imm32 = 1;
8909 types->bitfield.disp32 = 1;
8912 *types = gotrel[j].types64;
8915 if (j != 0 && GOT_symbol == NULL)
8916 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8918 /* The length of the first part of our input line. */
8919 first = cp - input_line_pointer;
8921 /* The second part goes from after the reloc token until
8922 (and including) an end_of_line char or comma. */
8923 past_reloc = cp + 1 + len;
8925 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8927 second = cp + 1 - past_reloc;
8929 /* Allocate and copy string. The trailing NUL shouldn't
8930 be necessary, but be safe. */
8931 tmpbuf = XNEWVEC (char, first + second + 2);
8932 memcpy (tmpbuf, input_line_pointer, first);
8933 if (second != 0 && *past_reloc != ' ')
8934 /* Replace the relocation token with ' ', so that
8935 errors like foo@GOTOFF1 will be detected. */
8936 tmpbuf[first++] = ' ';
8938 /* Increment length by 1 if the relocation token is
8943 memcpy (tmpbuf + first, past_reloc, second);
8944 tmpbuf[first + second] = '\0';
8948 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8949 gotrel[j].str, 1 << (5 + object_64bit));
8954 /* Might be a symbol version string. Don't as_bad here. */
8963 /* Parse operands of the form
8964 <symbol>@SECREL32+<nnn>
8966 If we find one, set up the correct relocation in RELOC and copy the
8967 input string, minus the `@SECREL32' into a malloc'd buffer for
8968 parsing by the calling routine. Return this buffer, and if ADJUST
8969 is non-null set it to the length of the string we removed from the
8970 input line. Otherwise return NULL.
8972 This function is copied from the ELF version above adjusted for PE targets. */
8975 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8976 int *adjust ATTRIBUTE_UNUSED,
8977 i386_operand_type *types)
8983 const enum bfd_reloc_code_real rel[2];
8984 const i386_operand_type types64;
8988 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8989 BFD_RELOC_32_SECREL },
8990 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8996 for (cp = input_line_pointer; *cp != '@'; cp++)
8997 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
9000 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
9002 int len = gotrel[j].len;
9004 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
9006 if (gotrel[j].rel[object_64bit] != 0)
9009 char *tmpbuf, *past_reloc;
9011 *rel = gotrel[j].rel[object_64bit];
9017 if (flag_code != CODE_64BIT)
9019 types->bitfield.imm32 = 1;
9020 types->bitfield.disp32 = 1;
9023 *types = gotrel[j].types64;
9026 /* The length of the first part of our input line. */
9027 first = cp - input_line_pointer;
9029 /* The second part goes from after the reloc token until
9030 (and including) an end_of_line char or comma. */
9031 past_reloc = cp + 1 + len;
9033 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
9035 second = cp + 1 - past_reloc;
9037 /* Allocate and copy string. The trailing NUL shouldn't
9038 be necessary, but be safe. */
9039 tmpbuf = XNEWVEC (char, first + second + 2);
9040 memcpy (tmpbuf, input_line_pointer, first);
9041 if (second != 0 && *past_reloc != ' ')
9042 /* Replace the relocation token with ' ', so that
9043 errors like foo@SECLREL321 will be detected. */
9044 tmpbuf[first++] = ' ';
9045 memcpy (tmpbuf + first, past_reloc, second);
9046 tmpbuf[first + second] = '\0';
9050 as_bad (_("@%s reloc is not supported with %d-bit output format"),
9051 gotrel[j].str, 1 << (5 + object_64bit));
9056 /* Might be a symbol version string. Don't as_bad here. */
9062 bfd_reloc_code_real_type
9063 x86_cons (expressionS *exp, int size)
9065 bfd_reloc_code_real_type got_reloc = NO_RELOC;
9067 intel_syntax = -intel_syntax;
9070 if (size == 4 || (object_64bit && size == 8))
9072 /* Handle @GOTOFF and the like in an expression. */
9074 char *gotfree_input_line;
9077 save = input_line_pointer;
9078 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
9079 if (gotfree_input_line)
9080 input_line_pointer = gotfree_input_line;
9084 if (gotfree_input_line)
9086 /* expression () has merrily parsed up to the end of line,
9087 or a comma - in the wrong buffer. Transfer how far
9088 input_line_pointer has moved to the right buffer. */
9089 input_line_pointer = (save
9090 + (input_line_pointer - gotfree_input_line)
9092 free (gotfree_input_line);
9093 if (exp->X_op == O_constant
9094 || exp->X_op == O_absent
9095 || exp->X_op == O_illegal
9096 || exp->X_op == O_register
9097 || exp->X_op == O_big)
9099 char c = *input_line_pointer;
9100 *input_line_pointer = 0;
9101 as_bad (_("missing or invalid expression `%s'"), save);
9102 *input_line_pointer = c;
9104 else if ((got_reloc == BFD_RELOC_386_PLT32
9105 || got_reloc == BFD_RELOC_X86_64_PLT32)
9106 && exp->X_op != O_symbol)
9108 char c = *input_line_pointer;
9109 *input_line_pointer = 0;
9110 as_bad (_("invalid PLT expression `%s'"), save);
9111 *input_line_pointer = c;
9118 intel_syntax = -intel_syntax;
9121 i386_intel_simplify (exp);
9127 signed_cons (int size)
9129 if (flag_code == CODE_64BIT)
9137 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
9144 if (exp.X_op == O_symbol)
9145 exp.X_op = O_secrel;
9147 emit_expr (&exp, 4);
9149 while (*input_line_pointer++ == ',');
9151 input_line_pointer--;
9152 demand_empty_rest_of_line ();
9156 /* Handle Vector operations. */
9159 check_VecOperations (char *op_string, char *op_end)
9161 const reg_entry *mask;
9166 && (op_end == NULL || op_string < op_end))
9169 if (*op_string == '{')
9173 /* Check broadcasts. */
9174 if (strncmp (op_string, "1to", 3) == 0)
9179 goto duplicated_vec_op;
9182 if (*op_string == '8')
9184 else if (*op_string == '4')
9186 else if (*op_string == '2')
9188 else if (*op_string == '1'
9189 && *(op_string+1) == '6')
9196 as_bad (_("Unsupported broadcast: `%s'"), saved);
9201 broadcast_op.type = bcst_type;
9202 broadcast_op.operand = this_operand;
9203 broadcast_op.bytes = 0;
9204 i.broadcast = &broadcast_op;
9206 /* Check masking operation. */
9207 else if ((mask = parse_register (op_string, &end_op)) != NULL)
9209 /* k0 can't be used for write mask. */
9210 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
9212 as_bad (_("`%s%s' can't be used for write mask"),
9213 register_prefix, mask->reg_name);
9219 mask_op.mask = mask;
9220 mask_op.zeroing = 0;
9221 mask_op.operand = this_operand;
9227 goto duplicated_vec_op;
9229 i.mask->mask = mask;
9231 /* Only "{z}" is allowed here. No need to check
9232 zeroing mask explicitly. */
9233 if (i.mask->operand != this_operand)
9235 as_bad (_("invalid write mask `%s'"), saved);
9242 /* Check zeroing-flag for masking operation. */
9243 else if (*op_string == 'z')
9247 mask_op.mask = NULL;
9248 mask_op.zeroing = 1;
9249 mask_op.operand = this_operand;
9254 if (i.mask->zeroing)
9257 as_bad (_("duplicated `%s'"), saved);
9261 i.mask->zeroing = 1;
9263 /* Only "{%k}" is allowed here. No need to check mask
9264 register explicitly. */
9265 if (i.mask->operand != this_operand)
9267 as_bad (_("invalid zeroing-masking `%s'"),
9276 goto unknown_vec_op;
9278 if (*op_string != '}')
9280 as_bad (_("missing `}' in `%s'"), saved);
9285 /* Strip whitespace since the addition of pseudo prefixes
9286 changed how the scrubber treats '{'. */
9287 if (is_space_char (*op_string))
9293 /* We don't know this one. */
9294 as_bad (_("unknown vector operation: `%s'"), saved);
9298 if (i.mask && i.mask->zeroing && !i.mask->mask)
9300 as_bad (_("zeroing-masking only allowed with write mask"));
9308 i386_immediate (char *imm_start)
9310 char *save_input_line_pointer;
9311 char *gotfree_input_line;
9314 i386_operand_type types;
9316 operand_type_set (&types, ~0);
9318 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
9320 as_bad (_("at most %d immediate operands are allowed"),
9321 MAX_IMMEDIATE_OPERANDS);
9325 exp = &im_expressions[i.imm_operands++];
9326 i.op[this_operand].imms = exp;
9328 if (is_space_char (*imm_start))
9331 save_input_line_pointer = input_line_pointer;
9332 input_line_pointer = imm_start;
9334 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9335 if (gotfree_input_line)
9336 input_line_pointer = gotfree_input_line;
9338 exp_seg = expression (exp);
9342 /* Handle vector operations. */
9343 if (*input_line_pointer == '{')
9345 input_line_pointer = check_VecOperations (input_line_pointer,
9347 if (input_line_pointer == NULL)
9351 if (*input_line_pointer)
9352 as_bad (_("junk `%s' after expression"), input_line_pointer);
9354 input_line_pointer = save_input_line_pointer;
9355 if (gotfree_input_line)
9357 free (gotfree_input_line);
9359 if (exp->X_op == O_constant || exp->X_op == O_register)
9360 exp->X_op = O_illegal;
9363 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
9367 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9368 i386_operand_type types, const char *imm_start)
9370 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
9373 as_bad (_("missing or invalid immediate expression `%s'"),
9377 else if (exp->X_op == O_constant)
9379 /* Size it properly later. */
9380 i.types[this_operand].bitfield.imm64 = 1;
9381 /* If not 64bit, sign extend val. */
9382 if (flag_code != CODE_64BIT
9383 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
9385 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
9387 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9388 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
9389 && exp_seg != absolute_section
9390 && exp_seg != text_section
9391 && exp_seg != data_section
9392 && exp_seg != bss_section
9393 && exp_seg != undefined_section
9394 && !bfd_is_com_section (exp_seg))
9396 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9400 else if (!intel_syntax && exp_seg == reg_section)
9403 as_bad (_("illegal immediate register operand %s"), imm_start);
9408 /* This is an address. The size of the address will be
9409 determined later, depending on destination register,
9410 suffix, or the default for the section. */
9411 i.types[this_operand].bitfield.imm8 = 1;
9412 i.types[this_operand].bitfield.imm16 = 1;
9413 i.types[this_operand].bitfield.imm32 = 1;
9414 i.types[this_operand].bitfield.imm32s = 1;
9415 i.types[this_operand].bitfield.imm64 = 1;
9416 i.types[this_operand] = operand_type_and (i.types[this_operand],
9424 i386_scale (char *scale)
9427 char *save = input_line_pointer;
9429 input_line_pointer = scale;
9430 val = get_absolute_expression ();
9435 i.log2_scale_factor = 0;
9438 i.log2_scale_factor = 1;
9441 i.log2_scale_factor = 2;
9444 i.log2_scale_factor = 3;
9448 char sep = *input_line_pointer;
9450 *input_line_pointer = '\0';
9451 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
9453 *input_line_pointer = sep;
9454 input_line_pointer = save;
9458 if (i.log2_scale_factor != 0 && i.index_reg == 0)
9460 as_warn (_("scale factor of %d without an index register"),
9461 1 << i.log2_scale_factor);
9462 i.log2_scale_factor = 0;
9464 scale = input_line_pointer;
9465 input_line_pointer = save;
9470 i386_displacement (char *disp_start, char *disp_end)
9474 char *save_input_line_pointer;
9475 char *gotfree_input_line;
9477 i386_operand_type bigdisp, types = anydisp;
9480 if (i.disp_operands == MAX_MEMORY_OPERANDS)
9482 as_bad (_("at most %d displacement operands are allowed"),
9483 MAX_MEMORY_OPERANDS);
9487 operand_type_set (&bigdisp, 0);
9488 if ((i.types[this_operand].bitfield.jumpabsolute)
9489 || (!current_templates->start->opcode_modifier.jump
9490 && !current_templates->start->opcode_modifier.jumpdword))
9492 bigdisp.bitfield.disp32 = 1;
9493 override = (i.prefix[ADDR_PREFIX] != 0);
9494 if (flag_code == CODE_64BIT)
9498 bigdisp.bitfield.disp32s = 1;
9499 bigdisp.bitfield.disp64 = 1;
9502 else if ((flag_code == CODE_16BIT) ^ override)
9504 bigdisp.bitfield.disp32 = 0;
9505 bigdisp.bitfield.disp16 = 1;
9510 /* For PC-relative branches, the width of the displacement
9511 is dependent upon data size, not address size. */
9512 override = (i.prefix[DATA_PREFIX] != 0);
9513 if (flag_code == CODE_64BIT)
9515 if (override || i.suffix == WORD_MNEM_SUFFIX)
9516 bigdisp.bitfield.disp16 = 1;
9519 bigdisp.bitfield.disp32 = 1;
9520 bigdisp.bitfield.disp32s = 1;
9526 override = (i.suffix == (flag_code != CODE_16BIT
9528 : LONG_MNEM_SUFFIX));
9529 bigdisp.bitfield.disp32 = 1;
9530 if ((flag_code == CODE_16BIT) ^ override)
9532 bigdisp.bitfield.disp32 = 0;
9533 bigdisp.bitfield.disp16 = 1;
9537 i.types[this_operand] = operand_type_or (i.types[this_operand],
9540 exp = &disp_expressions[i.disp_operands];
9541 i.op[this_operand].disps = exp;
9543 save_input_line_pointer = input_line_pointer;
9544 input_line_pointer = disp_start;
9545 END_STRING_AND_SAVE (disp_end);
9547 #ifndef GCC_ASM_O_HACK
9548 #define GCC_ASM_O_HACK 0
9551 END_STRING_AND_SAVE (disp_end + 1);
9552 if (i.types[this_operand].bitfield.baseIndex
9553 && displacement_string_end[-1] == '+')
9555 /* This hack is to avoid a warning when using the "o"
9556 constraint within gcc asm statements.
9559 #define _set_tssldt_desc(n,addr,limit,type) \
9560 __asm__ __volatile__ ( \
9562 "movw %w1,2+%0\n\t" \
9564 "movb %b1,4+%0\n\t" \
9565 "movb %4,5+%0\n\t" \
9566 "movb $0,6+%0\n\t" \
9567 "movb %h1,7+%0\n\t" \
9569 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
9571 This works great except that the output assembler ends
9572 up looking a bit weird if it turns out that there is
9573 no offset. You end up producing code that looks like:
9586 So here we provide the missing zero. */
9588 *displacement_string_end = '0';
9591 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
9592 if (gotfree_input_line)
9593 input_line_pointer = gotfree_input_line;
9595 exp_seg = expression (exp);
9598 if (*input_line_pointer)
9599 as_bad (_("junk `%s' after expression"), input_line_pointer);
9601 RESTORE_END_STRING (disp_end + 1);
9603 input_line_pointer = save_input_line_pointer;
9604 if (gotfree_input_line)
9606 free (gotfree_input_line);
9608 if (exp->X_op == O_constant || exp->X_op == O_register)
9609 exp->X_op = O_illegal;
9612 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9614 RESTORE_END_STRING (disp_end);
9620 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9621 i386_operand_type types, const char *disp_start)
9623 i386_operand_type bigdisp;
9626 /* We do this to make sure that the section symbol is in
9627 the symbol table. We will ultimately change the relocation
9628 to be relative to the beginning of the section. */
9629 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
9630 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9631 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9633 if (exp->X_op != O_symbol)
9636 if (S_IS_LOCAL (exp->X_add_symbol)
9637 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9638 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
9639 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
9640 exp->X_op = O_subtract;
9641 exp->X_op_symbol = GOT_symbol;
9642 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
9643 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
9644 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9645 i.reloc[this_operand] = BFD_RELOC_64;
9647 i.reloc[this_operand] = BFD_RELOC_32;
9650 else if (exp->X_op == O_absent
9651 || exp->X_op == O_illegal
9652 || exp->X_op == O_big)
9655 as_bad (_("missing or invalid displacement expression `%s'"),
9660 else if (flag_code == CODE_64BIT
9661 && !i.prefix[ADDR_PREFIX]
9662 && exp->X_op == O_constant)
9664 /* Since displacement is signed extended to 64bit, don't allow
9665 disp32 and turn off disp32s if they are out of range. */
9666 i.types[this_operand].bitfield.disp32 = 0;
9667 if (!fits_in_signed_long (exp->X_add_number))
9669 i.types[this_operand].bitfield.disp32s = 0;
9670 if (i.types[this_operand].bitfield.baseindex)
9672 as_bad (_("0x%lx out range of signed 32bit displacement"),
9673 (long) exp->X_add_number);
9679 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
9680 else if (exp->X_op != O_constant
9681 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9682 && exp_seg != absolute_section
9683 && exp_seg != text_section
9684 && exp_seg != data_section
9685 && exp_seg != bss_section
9686 && exp_seg != undefined_section
9687 && !bfd_is_com_section (exp_seg))
9689 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
9694 /* Check if this is a displacement only operand. */
9695 bigdisp = i.types[this_operand];
9696 bigdisp.bitfield.disp8 = 0;
9697 bigdisp.bitfield.disp16 = 0;
9698 bigdisp.bitfield.disp32 = 0;
9699 bigdisp.bitfield.disp32s = 0;
9700 bigdisp.bitfield.disp64 = 0;
9701 if (operand_type_all_zero (&bigdisp))
9702 i.types[this_operand] = operand_type_and (i.types[this_operand],
9708 /* Return the active addressing mode, taking address override and
9709 registers forming the address into consideration. Update the
9710 address override prefix if necessary. */
9712 static enum flag_code
9713 i386_addressing_mode (void)
9715 enum flag_code addr_mode;
9717 if (i.prefix[ADDR_PREFIX])
9718 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9721 addr_mode = flag_code;
9723 #if INFER_ADDR_PREFIX
9724 if (i.mem_operands == 0)
9726 /* Infer address prefix from the first memory operand. */
9727 const reg_entry *addr_reg = i.base_reg;
9729 if (addr_reg == NULL)
9730 addr_reg = i.index_reg;
9734 if (addr_reg->reg_type.bitfield.dword)
9735 addr_mode = CODE_32BIT;
9736 else if (flag_code != CODE_64BIT
9737 && addr_reg->reg_type.bitfield.word)
9738 addr_mode = CODE_16BIT;
9740 if (addr_mode != flag_code)
9742 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9744 /* Change the size of any displacement too. At most one
9745 of Disp16 or Disp32 is set.
9746 FIXME. There doesn't seem to be any real need for
9747 separate Disp16 and Disp32 flags. The same goes for
9748 Imm16 and Imm32. Removing them would probably clean
9749 up the code quite a lot. */
9750 if (flag_code != CODE_64BIT
9751 && (i.types[this_operand].bitfield.disp16
9752 || i.types[this_operand].bitfield.disp32))
9753 i.types[this_operand]
9754 = operand_type_xor (i.types[this_operand], disp16_32);
9764 /* Make sure the memory operand we've been dealt is valid.
9765 Return 1 on success, 0 on a failure. */
9768 i386_index_check (const char *operand_string)
9770 const char *kind = "base/index";
9771 enum flag_code addr_mode = i386_addressing_mode ();
9773 if (current_templates->start->opcode_modifier.isstring
9774 && !current_templates->start->cpu_flags.bitfield.cpupadlock
9775 && (current_templates->end[-1].opcode_modifier.isstring
9778 /* Memory operands of string insns are special in that they only allow
9779 a single register (rDI, rSI, or rBX) as their memory address. */
9780 const reg_entry *expected_reg;
9781 static const char *di_si[][2] =
9787 static const char *bx[] = { "ebx", "bx", "rbx" };
9789 kind = "string address";
9791 if (current_templates->start->opcode_modifier.repprefixok)
9793 i386_operand_type type = current_templates->end[-1].operand_types[0];
9795 if (!type.bitfield.baseindex
9796 || ((!i.mem_operands != !intel_syntax)
9797 && current_templates->end[-1].operand_types[1]
9798 .bitfield.baseindex))
9799 type = current_templates->end[-1].operand_types[1];
9800 expected_reg = hash_find (reg_hash,
9801 di_si[addr_mode][type.bitfield.esseg]);
9805 expected_reg = hash_find (reg_hash, bx[addr_mode]);
9807 if (i.base_reg != expected_reg
9809 || operand_type_check (i.types[this_operand], disp))
9811 /* The second memory operand must have the same size as
9815 && !((addr_mode == CODE_64BIT
9816 && i.base_reg->reg_type.bitfield.qword)
9817 || (addr_mode == CODE_32BIT
9818 ? i.base_reg->reg_type.bitfield.dword
9819 : i.base_reg->reg_type.bitfield.word)))
9822 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9824 intel_syntax ? '[' : '(',
9826 expected_reg->reg_name,
9827 intel_syntax ? ']' : ')');
9834 as_bad (_("`%s' is not a valid %s expression"),
9835 operand_string, kind);
9840 if (addr_mode != CODE_16BIT)
9842 /* 32-bit/64-bit checks. */
9844 && ((addr_mode == CODE_64BIT
9845 ? !i.base_reg->reg_type.bitfield.qword
9846 : !i.base_reg->reg_type.bitfield.dword)
9847 || (i.index_reg && i.base_reg->reg_num == RegIP)
9848 || i.base_reg->reg_num == RegIZ))
9850 && !i.index_reg->reg_type.bitfield.xmmword
9851 && !i.index_reg->reg_type.bitfield.ymmword
9852 && !i.index_reg->reg_type.bitfield.zmmword
9853 && ((addr_mode == CODE_64BIT
9854 ? !i.index_reg->reg_type.bitfield.qword
9855 : !i.index_reg->reg_type.bitfield.dword)
9856 || !i.index_reg->reg_type.bitfield.baseindex)))
9859 /* bndmk, bndldx, and bndstx have special restrictions. */
9860 if (current_templates->start->base_opcode == 0xf30f1b
9861 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9863 /* They cannot use RIP-relative addressing. */
9864 if (i.base_reg && i.base_reg->reg_num == RegIP)
9866 as_bad (_("`%s' cannot be used here"), operand_string);
9870 /* bndldx and bndstx ignore their scale factor. */
9871 if (current_templates->start->base_opcode != 0xf30f1b
9872 && i.log2_scale_factor)
9873 as_warn (_("register scaling is being ignored here"));
9878 /* 16-bit checks. */
9880 && (!i.base_reg->reg_type.bitfield.word
9881 || !i.base_reg->reg_type.bitfield.baseindex))
9883 && (!i.index_reg->reg_type.bitfield.word
9884 || !i.index_reg->reg_type.bitfield.baseindex
9886 && i.base_reg->reg_num < 6
9887 && i.index_reg->reg_num >= 6
9888 && i.log2_scale_factor == 0))))
9895 /* Handle vector immediates. */
9898 RC_SAE_immediate (const char *imm_start)
9900 unsigned int match_found, j;
9901 const char *pstr = imm_start;
9909 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9911 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9915 rc_op.type = RC_NamesTable[j].type;
9916 rc_op.operand = this_operand;
9917 i.rounding = &rc_op;
9921 as_bad (_("duplicated `%s'"), imm_start);
9924 pstr += RC_NamesTable[j].len;
9934 as_bad (_("Missing '}': '%s'"), imm_start);
9937 /* RC/SAE immediate string should contain nothing more. */;
9940 as_bad (_("Junk after '}': '%s'"), imm_start);
9944 exp = &im_expressions[i.imm_operands++];
9945 i.op[this_operand].imms = exp;
9947 exp->X_op = O_constant;
9948 exp->X_add_number = 0;
9949 exp->X_add_symbol = (symbolS *) 0;
9950 exp->X_op_symbol = (symbolS *) 0;
9952 i.types[this_operand].bitfield.imm8 = 1;
9956 /* Only string instructions can have a second memory operand, so
9957 reduce current_templates to just those if it contains any. */
9959 maybe_adjust_templates (void)
9961 const insn_template *t;
9963 gas_assert (i.mem_operands == 1);
9965 for (t = current_templates->start; t < current_templates->end; ++t)
9966 if (t->opcode_modifier.isstring)
9969 if (t < current_templates->end)
9971 static templates aux_templates;
9972 bfd_boolean recheck;
9974 aux_templates.start = t;
9975 for (; t < current_templates->end; ++t)
9976 if (!t->opcode_modifier.isstring)
9978 aux_templates.end = t;
9980 /* Determine whether to re-check the first memory operand. */
9981 recheck = (aux_templates.start != current_templates->start
9982 || t != current_templates->end);
9984 current_templates = &aux_templates;
9989 if (i.memop1_string != NULL
9990 && i386_index_check (i.memop1_string) == 0)
9999 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
10003 i386_att_operand (char *operand_string)
10005 const reg_entry *r;
10007 char *op_string = operand_string;
10009 if (is_space_char (*op_string))
10012 /* We check for an absolute prefix (differentiating,
10013 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
10014 if (*op_string == ABSOLUTE_PREFIX)
10017 if (is_space_char (*op_string))
10019 i.types[this_operand].bitfield.jumpabsolute = 1;
10022 /* Check if operand is a register. */
10023 if ((r = parse_register (op_string, &end_op)) != NULL)
10025 i386_operand_type temp;
10027 /* Check for a segment override by searching for ':' after a
10028 segment register. */
10029 op_string = end_op;
10030 if (is_space_char (*op_string))
10032 if (*op_string == ':'
10033 && (r->reg_type.bitfield.sreg2
10034 || r->reg_type.bitfield.sreg3))
10036 switch (r->reg_num)
10039 i.seg[i.mem_operands] = &es;
10042 i.seg[i.mem_operands] = &cs;
10045 i.seg[i.mem_operands] = &ss;
10048 i.seg[i.mem_operands] = &ds;
10051 i.seg[i.mem_operands] = &fs;
10054 i.seg[i.mem_operands] = &gs;
10058 /* Skip the ':' and whitespace. */
10060 if (is_space_char (*op_string))
10063 if (!is_digit_char (*op_string)
10064 && !is_identifier_char (*op_string)
10065 && *op_string != '('
10066 && *op_string != ABSOLUTE_PREFIX)
10068 as_bad (_("bad memory operand `%s'"), op_string);
10071 /* Handle case of %es:*foo. */
10072 if (*op_string == ABSOLUTE_PREFIX)
10075 if (is_space_char (*op_string))
10077 i.types[this_operand].bitfield.jumpabsolute = 1;
10079 goto do_memory_reference;
10082 /* Handle vector operations. */
10083 if (*op_string == '{')
10085 op_string = check_VecOperations (op_string, NULL);
10086 if (op_string == NULL)
10092 as_bad (_("junk `%s' after register"), op_string);
10095 temp = r->reg_type;
10096 temp.bitfield.baseindex = 0;
10097 i.types[this_operand] = operand_type_or (i.types[this_operand],
10099 i.types[this_operand].bitfield.unspecified = 0;
10100 i.op[this_operand].regs = r;
10103 else if (*op_string == REGISTER_PREFIX)
10105 as_bad (_("bad register name `%s'"), op_string);
10108 else if (*op_string == IMMEDIATE_PREFIX)
10111 if (i.types[this_operand].bitfield.jumpabsolute)
10113 as_bad (_("immediate operand illegal with absolute jump"));
10116 if (!i386_immediate (op_string))
10119 else if (RC_SAE_immediate (operand_string))
10121 /* If it is a RC or SAE immediate, do nothing. */
10124 else if (is_digit_char (*op_string)
10125 || is_identifier_char (*op_string)
10126 || *op_string == '"'
10127 || *op_string == '(')
10129 /* This is a memory reference of some sort. */
10132 /* Start and end of displacement string expression (if found). */
10133 char *displacement_string_start;
10134 char *displacement_string_end;
10137 do_memory_reference:
10138 if (i.mem_operands == 1 && !maybe_adjust_templates ())
10140 if ((i.mem_operands == 1
10141 && !current_templates->start->opcode_modifier.isstring)
10142 || i.mem_operands == 2)
10144 as_bad (_("too many memory references for `%s'"),
10145 current_templates->start->name);
10149 /* Check for base index form. We detect the base index form by
10150 looking for an ')' at the end of the operand, searching
10151 for the '(' matching it, and finding a REGISTER_PREFIX or ','
10153 base_string = op_string + strlen (op_string);
10155 /* Handle vector operations. */
10156 vop_start = strchr (op_string, '{');
10157 if (vop_start && vop_start < base_string)
10159 if (check_VecOperations (vop_start, base_string) == NULL)
10161 base_string = vop_start;
10165 if (is_space_char (*base_string))
10168 /* If we only have a displacement, set-up for it to be parsed later. */
10169 displacement_string_start = op_string;
10170 displacement_string_end = base_string + 1;
10172 if (*base_string == ')')
10175 unsigned int parens_balanced = 1;
10176 /* We've already checked that the number of left & right ()'s are
10177 equal, so this loop will not be infinite. */
10181 if (*base_string == ')')
10183 if (*base_string == '(')
10186 while (parens_balanced);
10188 temp_string = base_string;
10190 /* Skip past '(' and whitespace. */
10192 if (is_space_char (*base_string))
10195 if (*base_string == ','
10196 || ((i.base_reg = parse_register (base_string, &end_op))
10199 displacement_string_end = temp_string;
10201 i.types[this_operand].bitfield.baseindex = 1;
10205 base_string = end_op;
10206 if (is_space_char (*base_string))
10210 /* There may be an index reg or scale factor here. */
10211 if (*base_string == ',')
10214 if (is_space_char (*base_string))
10217 if ((i.index_reg = parse_register (base_string, &end_op))
10220 base_string = end_op;
10221 if (is_space_char (*base_string))
10223 if (*base_string == ',')
10226 if (is_space_char (*base_string))
10229 else if (*base_string != ')')
10231 as_bad (_("expecting `,' or `)' "
10232 "after index register in `%s'"),
10237 else if (*base_string == REGISTER_PREFIX)
10239 end_op = strchr (base_string, ',');
10242 as_bad (_("bad register name `%s'"), base_string);
10246 /* Check for scale factor. */
10247 if (*base_string != ')')
10249 char *end_scale = i386_scale (base_string);
10254 base_string = end_scale;
10255 if (is_space_char (*base_string))
10257 if (*base_string != ')')
10259 as_bad (_("expecting `)' "
10260 "after scale factor in `%s'"),
10265 else if (!i.index_reg)
10267 as_bad (_("expecting index register or scale factor "
10268 "after `,'; got '%c'"),
10273 else if (*base_string != ')')
10275 as_bad (_("expecting `,' or `)' "
10276 "after base register in `%s'"),
10281 else if (*base_string == REGISTER_PREFIX)
10283 end_op = strchr (base_string, ',');
10286 as_bad (_("bad register name `%s'"), base_string);
10291 /* If there's an expression beginning the operand, parse it,
10292 assuming displacement_string_start and
10293 displacement_string_end are meaningful. */
10294 if (displacement_string_start != displacement_string_end)
10296 if (!i386_displacement (displacement_string_start,
10297 displacement_string_end))
10301 /* Special case for (%dx) while doing input/output op. */
10303 && i.base_reg->reg_type.bitfield.inoutportreg
10304 && i.index_reg == 0
10305 && i.log2_scale_factor == 0
10306 && i.seg[i.mem_operands] == 0
10307 && !operand_type_check (i.types[this_operand], disp))
10309 i.types[this_operand] = i.base_reg->reg_type;
10313 if (i386_index_check (operand_string) == 0)
10315 i.flags[this_operand] |= Operand_Mem;
10316 if (i.mem_operands == 0)
10317 i.memop1_string = xstrdup (operand_string);
10322 /* It's not a memory operand; argh! */
10323 as_bad (_("invalid char %s beginning operand %d `%s'"),
10324 output_invalid (*op_string),
10329 return 1; /* Normal return. */
10332 /* Calculate the maximum variable size (i.e., excluding fr_fix)
10333 that an rs_machine_dependent frag may reach. */
10336 i386_frag_max_var (fragS *frag)
10338 /* The only relaxable frags are for jumps.
10339 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
10340 gas_assert (frag->fr_type == rs_machine_dependent);
10341 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
10344 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10346 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
10348 /* STT_GNU_IFUNC symbol must go through PLT. */
10349 if ((symbol_get_bfdsym (fr_symbol)->flags
10350 & BSF_GNU_INDIRECT_FUNCTION) != 0)
10353 if (!S_IS_EXTERNAL (fr_symbol))
10354 /* Symbol may be weak or local. */
10355 return !S_IS_WEAK (fr_symbol);
10357 /* Global symbols with non-default visibility can't be preempted. */
10358 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
10361 if (fr_var != NO_RELOC)
10362 switch ((enum bfd_reloc_code_real) fr_var)
10364 case BFD_RELOC_386_PLT32:
10365 case BFD_RELOC_X86_64_PLT32:
10366 /* Symbol with PLT relocation may be preempted. */
10372 /* Global symbols with default visibility in a shared library may be
10373 preempted by another definition. */
10378 /* md_estimate_size_before_relax()
10380 Called just before relax() for rs_machine_dependent frags. The x86
10381 assembler uses these frags to handle variable size jump
10384 Any symbol that is now undefined will not become defined.
10385 Return the correct fr_subtype in the frag.
10386 Return the initial "guess for variable size of frag" to caller.
10387 The guess is actually the growth beyond the fixed part. Whatever
10388 we do to grow the fixed or variable part contributes to our
10392 md_estimate_size_before_relax (fragS *fragP, segT segment)
10394 /* We've already got fragP->fr_subtype right; all we have to do is
10395 check for un-relaxable symbols. On an ELF system, we can't relax
10396 an externally visible symbol, because it may be overridden by a
10398 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
10399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10401 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
10404 #if defined (OBJ_COFF) && defined (TE_PE)
10405 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
10406 && S_IS_WEAK (fragP->fr_symbol))
10410 /* Symbol is undefined in this segment, or we need to keep a
10411 reloc so that weak symbols can be overridden. */
10412 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
10413 enum bfd_reloc_code_real reloc_type;
10414 unsigned char *opcode;
10417 if (fragP->fr_var != NO_RELOC)
10418 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
10419 else if (size == 2)
10420 reloc_type = BFD_RELOC_16_PCREL;
10421 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10422 else if (need_plt32_p (fragP->fr_symbol))
10423 reloc_type = BFD_RELOC_X86_64_PLT32;
10426 reloc_type = BFD_RELOC_32_PCREL;
10428 old_fr_fix = fragP->fr_fix;
10429 opcode = (unsigned char *) fragP->fr_opcode;
10431 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
10434 /* Make jmp (0xeb) a (d)word displacement jump. */
10436 fragP->fr_fix += size;
10437 fix_new (fragP, old_fr_fix, size,
10439 fragP->fr_offset, 1,
10445 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
10447 /* Negate the condition, and branch past an
10448 unconditional jump. */
10451 /* Insert an unconditional jump. */
10453 /* We added two extra opcode bytes, and have a two byte
10455 fragP->fr_fix += 2 + 2;
10456 fix_new (fragP, old_fr_fix + 2, 2,
10458 fragP->fr_offset, 1,
10462 /* Fall through. */
10465 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
10469 fragP->fr_fix += 1;
10470 fixP = fix_new (fragP, old_fr_fix, 1,
10472 fragP->fr_offset, 1,
10473 BFD_RELOC_8_PCREL);
10474 fixP->fx_signed = 1;
10478 /* This changes the byte-displacement jump 0x7N
10479 to the (d)word-displacement jump 0x0f,0x8N. */
10480 opcode[1] = opcode[0] + 0x10;
10481 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10482 /* We've added an opcode byte. */
10483 fragP->fr_fix += 1 + size;
10484 fix_new (fragP, old_fr_fix + 1, size,
10486 fragP->fr_offset, 1,
10491 BAD_CASE (fragP->fr_subtype);
10495 return fragP->fr_fix - old_fr_fix;
10498 /* Guess size depending on current relax state. Initially the relax
10499 state will correspond to a short jump and we return 1, because
10500 the variable part of the frag (the branch offset) is one byte
10501 long. However, we can relax a section more than once and in that
10502 case we must either set fr_subtype back to the unrelaxed state,
10503 or return the value for the appropriate branch. */
10504 return md_relax_table[fragP->fr_subtype].rlx_length;
10507 /* Called after relax() is finished.
10509 In: Address of frag.
10510 fr_type == rs_machine_dependent.
10511 fr_subtype is what the address relaxed to.
10513 Out: Any fixSs and constants are set up.
10514 Caller will turn frag into a ".space 0". */
10517 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
10520 unsigned char *opcode;
10521 unsigned char *where_to_put_displacement = NULL;
10522 offsetT target_address;
10523 offsetT opcode_address;
10524 unsigned int extension = 0;
10525 offsetT displacement_from_opcode_start;
10527 opcode = (unsigned char *) fragP->fr_opcode;
10529 /* Address we want to reach in file space. */
10530 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
10532 /* Address opcode resides at in file space. */
10533 opcode_address = fragP->fr_address + fragP->fr_fix;
10535 /* Displacement from opcode start to fill into instruction. */
10536 displacement_from_opcode_start = target_address - opcode_address;
10538 if ((fragP->fr_subtype & BIG) == 0)
10540 /* Don't have to change opcode. */
10541 extension = 1; /* 1 opcode + 1 displacement */
10542 where_to_put_displacement = &opcode[1];
10546 if (no_cond_jump_promotion
10547 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
10548 as_warn_where (fragP->fr_file, fragP->fr_line,
10549 _("long jump required"));
10551 switch (fragP->fr_subtype)
10553 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
10554 extension = 4; /* 1 opcode + 4 displacement */
10556 where_to_put_displacement = &opcode[1];
10559 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
10560 extension = 2; /* 1 opcode + 2 displacement */
10562 where_to_put_displacement = &opcode[1];
10565 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
10566 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
10567 extension = 5; /* 2 opcode + 4 displacement */
10568 opcode[1] = opcode[0] + 0x10;
10569 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10570 where_to_put_displacement = &opcode[2];
10573 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
10574 extension = 3; /* 2 opcode + 2 displacement */
10575 opcode[1] = opcode[0] + 0x10;
10576 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
10577 where_to_put_displacement = &opcode[2];
10580 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
10585 where_to_put_displacement = &opcode[3];
10589 BAD_CASE (fragP->fr_subtype);
10594 /* If size if less then four we are sure that the operand fits,
10595 but if it's 4, then it could be that the displacement is larger
10597 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
10599 && ((addressT) (displacement_from_opcode_start - extension
10600 + ((addressT) 1 << 31))
10601 > (((addressT) 2 << 31) - 1)))
10603 as_bad_where (fragP->fr_file, fragP->fr_line,
10604 _("jump target out of range"));
10605 /* Make us emit 0. */
10606 displacement_from_opcode_start = extension;
10608 /* Now put displacement after opcode. */
10609 md_number_to_chars ((char *) where_to_put_displacement,
10610 (valueT) (displacement_from_opcode_start - extension),
10611 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
10612 fragP->fr_fix += extension;
10615 /* Apply a fixup (fixP) to segment data, once it has been determined
10616 by our caller that we have all the info we need to fix it up.
10618 Parameter valP is the pointer to the value of the bits.
10620 On the 386, immediates, displacements, and data pointers are all in
10621 the same (little-endian) format, so we don't need to care about which
10622 we are handling. */
10625 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
10627 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
10628 valueT value = *valP;
10630 #if !defined (TE_Mach)
10631 if (fixP->fx_pcrel)
10633 switch (fixP->fx_r_type)
10639 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10642 case BFD_RELOC_X86_64_32S:
10643 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10646 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10649 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10654 if (fixP->fx_addsy != NULL
10655 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
10656 || fixP->fx_r_type == BFD_RELOC_64_PCREL
10657 || fixP->fx_r_type == BFD_RELOC_16_PCREL
10658 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
10659 && !use_rela_relocations)
10661 /* This is a hack. There should be a better way to handle this.
10662 This covers for the fact that bfd_install_relocation will
10663 subtract the current location (for partial_inplace, PC relative
10664 relocations); see more below. */
10668 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10671 value += fixP->fx_where + fixP->fx_frag->fr_address;
10673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10676 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
10678 if ((sym_seg == seg
10679 || (symbol_section_p (fixP->fx_addsy)
10680 && sym_seg != absolute_section))
10681 && !generic_force_reloc (fixP))
10683 /* Yes, we add the values in twice. This is because
10684 bfd_install_relocation subtracts them out again. I think
10685 bfd_install_relocation is broken, but I don't dare change
10687 value += fixP->fx_where + fixP->fx_frag->fr_address;
10691 #if defined (OBJ_COFF) && defined (TE_PE)
10692 /* For some reason, the PE format does not store a
10693 section address offset for a PC relative symbol. */
10694 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
10695 || S_IS_WEAK (fixP->fx_addsy))
10696 value += md_pcrel_from (fixP);
10699 #if defined (OBJ_COFF) && defined (TE_PE)
10700 if (fixP->fx_addsy != NULL
10701 && S_IS_WEAK (fixP->fx_addsy)
10702 /* PR 16858: Do not modify weak function references. */
10703 && ! fixP->fx_pcrel)
10705 #if !defined (TE_PEP)
10706 /* For x86 PE weak function symbols are neither PC-relative
10707 nor do they set S_IS_FUNCTION. So the only reliable way
10708 to detect them is to check the flags of their containing
10710 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10711 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10715 value -= S_GET_VALUE (fixP->fx_addsy);
10719 /* Fix a few things - the dynamic linker expects certain values here,
10720 and we must not disappoint it. */
10721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10722 if (IS_ELF && fixP->fx_addsy)
10723 switch (fixP->fx_r_type)
10725 case BFD_RELOC_386_PLT32:
10726 case BFD_RELOC_X86_64_PLT32:
10727 /* Make the jump instruction point to the address of the operand.
10728 At runtime we merely add the offset to the actual PLT entry.
10729 NB: Subtract the offset size only for jump instructions. */
10730 if (fixP->fx_pcrel)
10734 case BFD_RELOC_386_TLS_GD:
10735 case BFD_RELOC_386_TLS_LDM:
10736 case BFD_RELOC_386_TLS_IE_32:
10737 case BFD_RELOC_386_TLS_IE:
10738 case BFD_RELOC_386_TLS_GOTIE:
10739 case BFD_RELOC_386_TLS_GOTDESC:
10740 case BFD_RELOC_X86_64_TLSGD:
10741 case BFD_RELOC_X86_64_TLSLD:
10742 case BFD_RELOC_X86_64_GOTTPOFF:
10743 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10744 value = 0; /* Fully resolved at runtime. No addend. */
10746 case BFD_RELOC_386_TLS_LE:
10747 case BFD_RELOC_386_TLS_LDO_32:
10748 case BFD_RELOC_386_TLS_LE_32:
10749 case BFD_RELOC_X86_64_DTPOFF32:
10750 case BFD_RELOC_X86_64_DTPOFF64:
10751 case BFD_RELOC_X86_64_TPOFF32:
10752 case BFD_RELOC_X86_64_TPOFF64:
10753 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10756 case BFD_RELOC_386_TLS_DESC_CALL:
10757 case BFD_RELOC_X86_64_TLSDESC_CALL:
10758 value = 0; /* Fully resolved at runtime. No addend. */
10759 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10763 case BFD_RELOC_VTABLE_INHERIT:
10764 case BFD_RELOC_VTABLE_ENTRY:
10771 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
10773 #endif /* !defined (TE_Mach) */
10775 /* Are we finished with this relocation now? */
10776 if (fixP->fx_addsy == NULL)
10778 #if defined (OBJ_COFF) && defined (TE_PE)
10779 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10782 /* Remember value for tc_gen_reloc. */
10783 fixP->fx_addnumber = value;
10784 /* Clear out the frag for now. */
10788 else if (use_rela_relocations)
10790 fixP->fx_no_overflow = 1;
10791 /* Remember value for tc_gen_reloc. */
10792 fixP->fx_addnumber = value;
10796 md_number_to_chars (p, value, fixP->fx_size);
10800 md_atof (int type, char *litP, int *sizeP)
10802 /* This outputs the LITTLENUMs in REVERSE order;
10803 in accord with the bigendian 386. */
10804 return ieee_md_atof (type, litP, sizeP, FALSE);
10807 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
10810 output_invalid (int c)
10813 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10816 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10817 "(0x%x)", (unsigned char) c);
10818 return output_invalid_buf;
10821 /* REG_STRING starts *before* REGISTER_PREFIX. */
10823 static const reg_entry *
10824 parse_real_register (char *reg_string, char **end_op)
10826 char *s = reg_string;
10828 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10829 const reg_entry *r;
10831 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10832 if (*s == REGISTER_PREFIX)
10835 if (is_space_char (*s))
10838 p = reg_name_given;
10839 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
10841 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
10842 return (const reg_entry *) NULL;
10846 /* For naked regs, make sure that we are not dealing with an identifier.
10847 This prevents confusing an identifier like `eax_var' with register
10849 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10850 return (const reg_entry *) NULL;
10854 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10856 /* Handle floating point regs, allowing spaces in the (i) part. */
10857 if (r == i386_regtab /* %st is first entry of table */)
10859 if (!cpu_arch_flags.bitfield.cpu8087
10860 && !cpu_arch_flags.bitfield.cpu287
10861 && !cpu_arch_flags.bitfield.cpu387)
10862 return (const reg_entry *) NULL;
10864 if (is_space_char (*s))
10869 if (is_space_char (*s))
10871 if (*s >= '0' && *s <= '7')
10873 int fpr = *s - '0';
10875 if (is_space_char (*s))
10880 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
10885 /* We have "%st(" then garbage. */
10886 return (const reg_entry *) NULL;
10890 if (r == NULL || allow_pseudo_reg)
10893 if (operand_type_all_zero (&r->reg_type))
10894 return (const reg_entry *) NULL;
10896 if ((r->reg_type.bitfield.dword
10897 || r->reg_type.bitfield.sreg3
10898 || r->reg_type.bitfield.control
10899 || r->reg_type.bitfield.debug
10900 || r->reg_type.bitfield.test)
10901 && !cpu_arch_flags.bitfield.cpui386)
10902 return (const reg_entry *) NULL;
10904 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
10905 return (const reg_entry *) NULL;
10907 if (!cpu_arch_flags.bitfield.cpuavx512f)
10909 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10910 return (const reg_entry *) NULL;
10912 if (!cpu_arch_flags.bitfield.cpuavx)
10914 if (r->reg_type.bitfield.ymmword)
10915 return (const reg_entry *) NULL;
10917 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10918 return (const reg_entry *) NULL;
10922 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10923 return (const reg_entry *) NULL;
10925 /* Don't allow fake index register unless allow_index_reg isn't 0. */
10926 if (!allow_index_reg && r->reg_num == RegIZ)
10927 return (const reg_entry *) NULL;
10929 /* Upper 16 vector registers are only available with VREX in 64bit
10930 mode, and require EVEX encoding. */
10931 if (r->reg_flags & RegVRex)
10933 if (!cpu_arch_flags.bitfield.cpuavx512f
10934 || flag_code != CODE_64BIT)
10935 return (const reg_entry *) NULL;
10937 i.vec_encoding = vex_encoding_evex;
10940 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10941 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
10942 && flag_code != CODE_64BIT)
10943 return (const reg_entry *) NULL;
10945 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10946 return (const reg_entry *) NULL;
10951 /* REG_STRING starts *before* REGISTER_PREFIX. */
10953 static const reg_entry *
10954 parse_register (char *reg_string, char **end_op)
10956 const reg_entry *r;
10958 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10959 r = parse_real_register (reg_string, end_op);
10964 char *save = input_line_pointer;
10968 input_line_pointer = reg_string;
10969 c = get_symbol_name (®_string);
10970 symbolP = symbol_find (reg_string);
10971 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10973 const expressionS *e = symbol_get_value_expression (symbolP);
10975 know (e->X_op == O_register);
10976 know (e->X_add_number >= 0
10977 && (valueT) e->X_add_number < i386_regtab_size);
10978 r = i386_regtab + e->X_add_number;
10979 if ((r->reg_flags & RegVRex))
10980 i.vec_encoding = vex_encoding_evex;
10981 *end_op = input_line_pointer;
10983 *input_line_pointer = c;
10984 input_line_pointer = save;
10990 i386_parse_name (char *name, expressionS *e, char *nextcharP)
10992 const reg_entry *r;
10993 char *end = input_line_pointer;
10996 r = parse_register (name, &input_line_pointer);
10997 if (r && end <= input_line_pointer)
10999 *nextcharP = *input_line_pointer;
11000 *input_line_pointer = 0;
11001 e->X_op = O_register;
11002 e->X_add_number = r - i386_regtab;
11005 input_line_pointer = end;
11007 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
11011 md_operand (expressionS *e)
11014 const reg_entry *r;
11016 switch (*input_line_pointer)
11018 case REGISTER_PREFIX:
11019 r = parse_real_register (input_line_pointer, &end);
11022 e->X_op = O_register;
11023 e->X_add_number = r - i386_regtab;
11024 input_line_pointer = end;
11029 gas_assert (intel_syntax);
11030 end = input_line_pointer++;
11032 if (*input_line_pointer == ']')
11034 ++input_line_pointer;
11035 e->X_op_symbol = make_expr_symbol (e);
11036 e->X_add_symbol = NULL;
11037 e->X_add_number = 0;
11042 e->X_op = O_absent;
11043 input_line_pointer = end;
11050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11051 const char *md_shortopts = "kVQ:sqnO::";
11053 const char *md_shortopts = "qnO::";
11056 #define OPTION_32 (OPTION_MD_BASE + 0)
11057 #define OPTION_64 (OPTION_MD_BASE + 1)
11058 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
11059 #define OPTION_MARCH (OPTION_MD_BASE + 3)
11060 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
11061 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
11062 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
11063 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
11064 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
11065 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
11066 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
11067 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
11068 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
11069 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
11070 #define OPTION_X32 (OPTION_MD_BASE + 14)
11071 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
11072 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
11073 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
11074 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
11075 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
11076 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
11077 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
11078 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
11079 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
11080 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
11081 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
11082 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
11084 struct option md_longopts[] =
11086 {"32", no_argument, NULL, OPTION_32},
11087 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11088 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11089 {"64", no_argument, NULL, OPTION_64},
11091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11092 {"x32", no_argument, NULL, OPTION_X32},
11093 {"mshared", no_argument, NULL, OPTION_MSHARED},
11094 {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE},
11096 {"divide", no_argument, NULL, OPTION_DIVIDE},
11097 {"march", required_argument, NULL, OPTION_MARCH},
11098 {"mtune", required_argument, NULL, OPTION_MTUNE},
11099 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
11100 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
11101 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
11102 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
11103 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
11104 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
11105 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
11106 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
11107 {"mvexwig", required_argument, NULL, OPTION_MVEXWIG},
11108 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
11109 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
11110 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
11111 # if defined (TE_PE) || defined (TE_PEP)
11112 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
11114 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
11115 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
11116 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
11117 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
11118 {"mamd64", no_argument, NULL, OPTION_MAMD64},
11119 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
11120 {NULL, no_argument, NULL, 0}
11122 size_t md_longopts_size = sizeof (md_longopts);
11125 md_parse_option (int c, const char *arg)
11128 char *arch, *next, *saved;
11133 optimize_align_code = 0;
11137 quiet_warnings = 1;
11140 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11141 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
11142 should be emitted or not. FIXME: Not implemented. */
11144 if ((arg[0] != 'y' && arg[0] != 'n') || arg[1])
11148 /* -V: SVR4 argument to print version ID. */
11150 print_version_id ();
11153 /* -k: Ignore for FreeBSD compatibility. */
11158 /* -s: On i386 Solaris, this tells the native assembler to use
11159 .stab instead of .stab.excl. We always use .stab anyhow. */
11162 case OPTION_MSHARED:
11166 case OPTION_X86_USED_NOTE:
11167 if (strcasecmp (arg, "yes") == 0)
11169 else if (strcasecmp (arg, "no") == 0)
11172 as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg);
11177 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11178 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11181 const char **list, **l;
11183 list = bfd_target_list ();
11184 for (l = list; *l != NULL; l++)
11185 if (CONST_STRNEQ (*l, "elf64-x86-64")
11186 || strcmp (*l, "coff-x86-64") == 0
11187 || strcmp (*l, "pe-x86-64") == 0
11188 || strcmp (*l, "pei-x86-64") == 0
11189 || strcmp (*l, "mach-o-x86-64") == 0)
11191 default_arch = "x86_64";
11195 as_fatal (_("no compiled in support for x86_64"));
11201 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11205 const char **list, **l;
11207 list = bfd_target_list ();
11208 for (l = list; *l != NULL; l++)
11209 if (CONST_STRNEQ (*l, "elf32-x86-64"))
11211 default_arch = "x86_64:32";
11215 as_fatal (_("no compiled in support for 32bit x86_64"));
11219 as_fatal (_("32bit x86_64 is only supported for ELF"));
11224 default_arch = "i386";
11227 case OPTION_DIVIDE:
11228 #ifdef SVR4_COMMENT_CHARS
11233 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
11235 for (s = i386_comment_chars; *s != '\0'; s++)
11239 i386_comment_chars = n;
11245 saved = xstrdup (arg);
11247 /* Allow -march=+nosse. */
11253 as_fatal (_("invalid -march= option: `%s'"), arg);
11254 next = strchr (arch, '+');
11257 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11259 if (strcmp (arch, cpu_arch [j].name) == 0)
11262 if (! cpu_arch[j].flags.bitfield.cpui386)
11265 cpu_arch_name = cpu_arch[j].name;
11266 cpu_sub_arch_name = NULL;
11267 cpu_arch_flags = cpu_arch[j].flags;
11268 cpu_arch_isa = cpu_arch[j].type;
11269 cpu_arch_isa_flags = cpu_arch[j].flags;
11270 if (!cpu_arch_tune_set)
11272 cpu_arch_tune = cpu_arch_isa;
11273 cpu_arch_tune_flags = cpu_arch_isa_flags;
11277 else if (*cpu_arch [j].name == '.'
11278 && strcmp (arch, cpu_arch [j].name + 1) == 0)
11280 /* ISA extension. */
11281 i386_cpu_flags flags;
11283 flags = cpu_flags_or (cpu_arch_flags,
11284 cpu_arch[j].flags);
11286 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11288 if (cpu_sub_arch_name)
11290 char *name = cpu_sub_arch_name;
11291 cpu_sub_arch_name = concat (name,
11293 (const char *) NULL);
11297 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
11298 cpu_arch_flags = flags;
11299 cpu_arch_isa_flags = flags;
11303 = cpu_flags_or (cpu_arch_isa_flags,
11304 cpu_arch[j].flags);
11309 if (j >= ARRAY_SIZE (cpu_arch))
11311 /* Disable an ISA extension. */
11312 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11313 if (strcmp (arch, cpu_noarch [j].name) == 0)
11315 i386_cpu_flags flags;
11317 flags = cpu_flags_and_not (cpu_arch_flags,
11318 cpu_noarch[j].flags);
11319 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
11321 if (cpu_sub_arch_name)
11323 char *name = cpu_sub_arch_name;
11324 cpu_sub_arch_name = concat (arch,
11325 (const char *) NULL);
11329 cpu_sub_arch_name = xstrdup (arch);
11330 cpu_arch_flags = flags;
11331 cpu_arch_isa_flags = flags;
11336 if (j >= ARRAY_SIZE (cpu_noarch))
11337 j = ARRAY_SIZE (cpu_arch);
11340 if (j >= ARRAY_SIZE (cpu_arch))
11341 as_fatal (_("invalid -march= option: `%s'"), arg);
11345 while (next != NULL);
11351 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11352 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11354 if (strcmp (arg, cpu_arch [j].name) == 0)
11356 cpu_arch_tune_set = 1;
11357 cpu_arch_tune = cpu_arch [j].type;
11358 cpu_arch_tune_flags = cpu_arch[j].flags;
11362 if (j >= ARRAY_SIZE (cpu_arch))
11363 as_fatal (_("invalid -mtune= option: `%s'"), arg);
11366 case OPTION_MMNEMONIC:
11367 if (strcasecmp (arg, "att") == 0)
11368 intel_mnemonic = 0;
11369 else if (strcasecmp (arg, "intel") == 0)
11370 intel_mnemonic = 1;
11372 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
11375 case OPTION_MSYNTAX:
11376 if (strcasecmp (arg, "att") == 0)
11378 else if (strcasecmp (arg, "intel") == 0)
11381 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
11384 case OPTION_MINDEX_REG:
11385 allow_index_reg = 1;
11388 case OPTION_MNAKED_REG:
11389 allow_naked_reg = 1;
11392 case OPTION_MSSE2AVX:
11396 case OPTION_MSSE_CHECK:
11397 if (strcasecmp (arg, "error") == 0)
11398 sse_check = check_error;
11399 else if (strcasecmp (arg, "warning") == 0)
11400 sse_check = check_warning;
11401 else if (strcasecmp (arg, "none") == 0)
11402 sse_check = check_none;
11404 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
11407 case OPTION_MOPERAND_CHECK:
11408 if (strcasecmp (arg, "error") == 0)
11409 operand_check = check_error;
11410 else if (strcasecmp (arg, "warning") == 0)
11411 operand_check = check_warning;
11412 else if (strcasecmp (arg, "none") == 0)
11413 operand_check = check_none;
11415 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
11418 case OPTION_MAVXSCALAR:
11419 if (strcasecmp (arg, "128") == 0)
11420 avxscalar = vex128;
11421 else if (strcasecmp (arg, "256") == 0)
11422 avxscalar = vex256;
11424 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
11427 case OPTION_MVEXWIG:
11428 if (strcmp (arg, "0") == 0)
11430 else if (strcmp (arg, "1") == 0)
11433 as_fatal (_("invalid -mvexwig= option: `%s'"), arg);
11436 case OPTION_MADD_BND_PREFIX:
11437 add_bnd_prefix = 1;
11440 case OPTION_MEVEXLIG:
11441 if (strcmp (arg, "128") == 0)
11442 evexlig = evexl128;
11443 else if (strcmp (arg, "256") == 0)
11444 evexlig = evexl256;
11445 else if (strcmp (arg, "512") == 0)
11446 evexlig = evexl512;
11448 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
11451 case OPTION_MEVEXRCIG:
11452 if (strcmp (arg, "rne") == 0)
11454 else if (strcmp (arg, "rd") == 0)
11456 else if (strcmp (arg, "ru") == 0)
11458 else if (strcmp (arg, "rz") == 0)
11461 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
11464 case OPTION_MEVEXWIG:
11465 if (strcmp (arg, "0") == 0)
11467 else if (strcmp (arg, "1") == 0)
11470 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
11473 # if defined (TE_PE) || defined (TE_PEP)
11474 case OPTION_MBIG_OBJ:
11479 case OPTION_MOMIT_LOCK_PREFIX:
11480 if (strcasecmp (arg, "yes") == 0)
11481 omit_lock_prefix = 1;
11482 else if (strcasecmp (arg, "no") == 0)
11483 omit_lock_prefix = 0;
11485 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
11488 case OPTION_MFENCE_AS_LOCK_ADD:
11489 if (strcasecmp (arg, "yes") == 0)
11491 else if (strcasecmp (arg, "no") == 0)
11494 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
11497 case OPTION_MRELAX_RELOCATIONS:
11498 if (strcasecmp (arg, "yes") == 0)
11499 generate_relax_relocations = 1;
11500 else if (strcasecmp (arg, "no") == 0)
11501 generate_relax_relocations = 0;
11503 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
11506 case OPTION_MAMD64:
11510 case OPTION_MINTEL64:
11518 /* Turn off -Os. */
11519 optimize_for_space = 0;
11521 else if (*arg == 's')
11523 optimize_for_space = 1;
11524 /* Turn on all encoding optimizations. */
11525 optimize = INT_MAX;
11529 optimize = atoi (arg);
11530 /* Turn off -Os. */
11531 optimize_for_space = 0;
11541 #define MESSAGE_TEMPLATE \
11545 output_message (FILE *stream, char *p, char *message, char *start,
11546 int *left_p, const char *name, int len)
11548 int size = sizeof (MESSAGE_TEMPLATE);
11549 int left = *left_p;
11551 /* Reserve 2 spaces for ", " or ",\0" */
11554 /* Check if there is any room. */
11562 p = mempcpy (p, name, len);
11566 /* Output the current message now and start a new one. */
11569 fprintf (stream, "%s\n", message);
11571 left = size - (start - message) - len - 2;
11573 gas_assert (left >= 0);
11575 p = mempcpy (p, name, len);
11583 show_arch (FILE *stream, int ext, int check)
11585 static char message[] = MESSAGE_TEMPLATE;
11586 char *start = message + 27;
11588 int size = sizeof (MESSAGE_TEMPLATE);
11595 left = size - (start - message);
11596 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
11598 /* Should it be skipped? */
11599 if (cpu_arch [j].skip)
11602 name = cpu_arch [j].name;
11603 len = cpu_arch [j].len;
11606 /* It is an extension. Skip if we aren't asked to show it. */
11617 /* It is an processor. Skip if we show only extension. */
11620 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
11622 /* It is an impossible processor - skip. */
11626 p = output_message (stream, p, message, start, &left, name, len);
11629 /* Display disabled extensions. */
11631 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11633 name = cpu_noarch [j].name;
11634 len = cpu_noarch [j].len;
11635 p = output_message (stream, p, message, start, &left, name,
11640 fprintf (stream, "%s\n", message);
11644 md_show_usage (FILE *stream)
11646 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11647 fprintf (stream, _("\
11648 -Qy, -Qn ignored\n\
11649 -V print assembler version number\n\
11652 fprintf (stream, _("\
11653 -n Do not optimize code alignment\n\
11654 -q quieten some warnings\n"));
11655 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11656 fprintf (stream, _("\
11659 #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11660 || defined (TE_PE) || defined (TE_PEP))
11661 fprintf (stream, _("\
11662 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
11664 #ifdef SVR4_COMMENT_CHARS
11665 fprintf (stream, _("\
11666 --divide do not treat `/' as a comment character\n"));
11668 fprintf (stream, _("\
11669 --divide ignored\n"));
11671 fprintf (stream, _("\
11672 -march=CPU[,+EXTENSION...]\n\
11673 generate code for CPU and EXTENSION, CPU is one of:\n"));
11674 show_arch (stream, 0, 1);
11675 fprintf (stream, _("\
11676 EXTENSION is combination of:\n"));
11677 show_arch (stream, 1, 0);
11678 fprintf (stream, _("\
11679 -mtune=CPU optimize for CPU, CPU is one of:\n"));
11680 show_arch (stream, 0, 0);
11681 fprintf (stream, _("\
11682 -msse2avx encode SSE instructions with VEX prefix\n"));
11683 fprintf (stream, _("\
11684 -msse-check=[none|error|warning] (default: warning)\n\
11685 check SSE instructions\n"));
11686 fprintf (stream, _("\
11687 -moperand-check=[none|error|warning] (default: warning)\n\
11688 check operand combinations for validity\n"));
11689 fprintf (stream, _("\
11690 -mavxscalar=[128|256] (default: 128)\n\
11691 encode scalar AVX instructions with specific vector\n\
11693 fprintf (stream, _("\
11694 -mvexwig=[0|1] (default: 0)\n\
11695 encode VEX instructions with specific VEX.W value\n\
11696 for VEX.W bit ignored instructions\n"));
11697 fprintf (stream, _("\
11698 -mevexlig=[128|256|512] (default: 128)\n\
11699 encode scalar EVEX instructions with specific vector\n\
11701 fprintf (stream, _("\
11702 -mevexwig=[0|1] (default: 0)\n\
11703 encode EVEX instructions with specific EVEX.W value\n\
11704 for EVEX.W bit ignored instructions\n"));
11705 fprintf (stream, _("\
11706 -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\
11707 encode EVEX instructions with specific EVEX.RC value\n\
11708 for SAE-only ignored instructions\n"));
11709 fprintf (stream, _("\
11710 -mmnemonic=[att|intel] "));
11711 if (SYSV386_COMPAT)
11712 fprintf (stream, _("(default: att)\n"));
11714 fprintf (stream, _("(default: intel)\n"));
11715 fprintf (stream, _("\
11716 use AT&T/Intel mnemonic\n"));
11717 fprintf (stream, _("\
11718 -msyntax=[att|intel] (default: att)\n\
11719 use AT&T/Intel syntax\n"));
11720 fprintf (stream, _("\
11721 -mindex-reg support pseudo index registers\n"));
11722 fprintf (stream, _("\
11723 -mnaked-reg don't require `%%' prefix for registers\n"));
11724 fprintf (stream, _("\
11725 -madd-bnd-prefix add BND prefix for all valid branches\n"));
11726 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11727 fprintf (stream, _("\
11728 -mshared disable branch optimization for shared code\n"));
11729 fprintf (stream, _("\
11730 -mx86-used-note=[no|yes] "));
11731 if (DEFAULT_X86_USED_NOTE)
11732 fprintf (stream, _("(default: yes)\n"));
11734 fprintf (stream, _("(default: no)\n"));
11735 fprintf (stream, _("\
11736 generate x86 used ISA and feature properties\n"));
11738 #if defined (TE_PE) || defined (TE_PEP)
11739 fprintf (stream, _("\
11740 -mbig-obj generate big object files\n"));
11742 fprintf (stream, _("\
11743 -momit-lock-prefix=[no|yes] (default: no)\n\
11744 strip all lock prefixes\n"));
11745 fprintf (stream, _("\
11746 -mfence-as-lock-add=[no|yes] (default: no)\n\
11747 encode lfence, mfence and sfence as\n\
11748 lock addl $0x0, (%%{re}sp)\n"));
11749 fprintf (stream, _("\
11750 -mrelax-relocations=[no|yes] "));
11751 if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS)
11752 fprintf (stream, _("(default: yes)\n"));
11754 fprintf (stream, _("(default: no)\n"));
11755 fprintf (stream, _("\
11756 generate relax relocations\n"));
11757 fprintf (stream, _("\
11758 -mamd64 accept only AMD64 ISA [default]\n"));
11759 fprintf (stream, _("\
11760 -mintel64 accept only Intel64 ISA\n"));
11763 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
11764 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11765 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
11767 /* Pick the target format to use. */
11770 i386_target_format (void)
11772 if (!strncmp (default_arch, "x86_64", 6))
11774 update_code_flag (CODE_64BIT, 1);
11775 if (default_arch[6] == '\0')
11776 x86_elf_abi = X86_64_ABI;
11778 x86_elf_abi = X86_64_X32_ABI;
11780 else if (!strcmp (default_arch, "i386"))
11781 update_code_flag (CODE_32BIT, 1);
11782 else if (!strcmp (default_arch, "iamcu"))
11784 update_code_flag (CODE_32BIT, 1);
11785 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11787 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11788 cpu_arch_name = "iamcu";
11789 cpu_sub_arch_name = NULL;
11790 cpu_arch_flags = iamcu_flags;
11791 cpu_arch_isa = PROCESSOR_IAMCU;
11792 cpu_arch_isa_flags = iamcu_flags;
11793 if (!cpu_arch_tune_set)
11795 cpu_arch_tune = cpu_arch_isa;
11796 cpu_arch_tune_flags = cpu_arch_isa_flags;
11799 else if (cpu_arch_isa != PROCESSOR_IAMCU)
11800 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11804 as_fatal (_("unknown architecture"));
11806 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11807 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11808 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11809 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11811 switch (OUTPUT_FLAVOR)
11813 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
11814 case bfd_target_aout_flavour:
11815 return AOUT_TARGET_FORMAT;
11817 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11818 # if defined (TE_PE) || defined (TE_PEP)
11819 case bfd_target_coff_flavour:
11820 if (flag_code == CODE_64BIT)
11821 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11824 # elif defined (TE_GO32)
11825 case bfd_target_coff_flavour:
11826 return "coff-go32";
11828 case bfd_target_coff_flavour:
11829 return "coff-i386";
11832 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11833 case bfd_target_elf_flavour:
11835 const char *format;
11837 switch (x86_elf_abi)
11840 format = ELF_TARGET_FORMAT;
11843 use_rela_relocations = 1;
11845 format = ELF_TARGET_FORMAT64;
11847 case X86_64_X32_ABI:
11848 use_rela_relocations = 1;
11850 disallow_64bit_reloc = 1;
11851 format = ELF_TARGET_FORMAT32;
11854 if (cpu_arch_isa == PROCESSOR_L1OM)
11856 if (x86_elf_abi != X86_64_ABI)
11857 as_fatal (_("Intel L1OM is 64bit only"));
11858 return ELF_TARGET_L1OM_FORMAT;
11860 else if (cpu_arch_isa == PROCESSOR_K1OM)
11862 if (x86_elf_abi != X86_64_ABI)
11863 as_fatal (_("Intel K1OM is 64bit only"));
11864 return ELF_TARGET_K1OM_FORMAT;
11866 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11868 if (x86_elf_abi != I386_ABI)
11869 as_fatal (_("Intel MCU is 32bit only"));
11870 return ELF_TARGET_IAMCU_FORMAT;
11876 #if defined (OBJ_MACH_O)
11877 case bfd_target_mach_o_flavour:
11878 if (flag_code == CODE_64BIT)
11880 use_rela_relocations = 1;
11882 return "mach-o-x86-64";
11885 return "mach-o-i386";
11893 #endif /* OBJ_MAYBE_ more than one */
11896 md_undefined_symbol (char *name)
11898 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11899 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11900 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11901 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
11905 if (symbol_find (name))
11906 as_bad (_("GOT already in symbol table"));
11907 GOT_symbol = symbol_new (name, undefined_section,
11908 (valueT) 0, &zero_address_frag);
11915 /* Round up a section size to the appropriate boundary. */
11918 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
11920 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11921 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11923 /* For a.out, force the section size to be aligned. If we don't do
11924 this, BFD will align it for us, but it will not write out the
11925 final bytes of the section. This may be a bug in BFD, but it is
11926 easier to fix it here since that is how the other a.out targets
11930 align = bfd_get_section_alignment (stdoutput, segment);
11931 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
11938 /* On the i386, PC-relative offsets are relative to the start of the
11939 next instruction. That is, the address of the offset, plus its
11940 size, since the offset is always the last part of the insn. */
11943 md_pcrel_from (fixS *fixP)
11945 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11951 s_bss (int ignore ATTRIBUTE_UNUSED)
11955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11957 obj_elf_section_change_hook ();
11959 temp = get_absolute_expression ();
11960 subseg_set (bss_section, (subsegT) temp);
11961 demand_empty_rest_of_line ();
11967 i386_validate_fix (fixS *fixp)
11969 if (fixp->fx_subsy)
11971 if (fixp->fx_subsy == GOT_symbol)
11973 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11978 if (fixp->fx_tcbit2)
11979 fixp->fx_r_type = (fixp->fx_tcbit
11980 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11981 : BFD_RELOC_X86_64_GOTPCRELX);
11984 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11989 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11991 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11993 fixp->fx_subsy = 0;
11996 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11997 else if (!object_64bit)
11999 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
12000 && fixp->fx_tcbit2)
12001 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
12007 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
12010 bfd_reloc_code_real_type code;
12012 switch (fixp->fx_r_type)
12014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12015 case BFD_RELOC_SIZE32:
12016 case BFD_RELOC_SIZE64:
12017 if (S_IS_DEFINED (fixp->fx_addsy)
12018 && !S_IS_EXTERNAL (fixp->fx_addsy))
12020 /* Resolve size relocation against local symbol to size of
12021 the symbol plus addend. */
12022 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
12023 if (fixp->fx_r_type == BFD_RELOC_SIZE32
12024 && !fits_in_unsigned_long (value))
12025 as_bad_where (fixp->fx_file, fixp->fx_line,
12026 _("symbol size computation overflow"));
12027 fixp->fx_addsy = NULL;
12028 fixp->fx_subsy = NULL;
12029 md_apply_fix (fixp, (valueT *) &value, NULL);
12033 /* Fall through. */
12035 case BFD_RELOC_X86_64_PLT32:
12036 case BFD_RELOC_X86_64_GOT32:
12037 case BFD_RELOC_X86_64_GOTPCREL:
12038 case BFD_RELOC_X86_64_GOTPCRELX:
12039 case BFD_RELOC_X86_64_REX_GOTPCRELX:
12040 case BFD_RELOC_386_PLT32:
12041 case BFD_RELOC_386_GOT32:
12042 case BFD_RELOC_386_GOT32X:
12043 case BFD_RELOC_386_GOTOFF:
12044 case BFD_RELOC_386_GOTPC:
12045 case BFD_RELOC_386_TLS_GD:
12046 case BFD_RELOC_386_TLS_LDM:
12047 case BFD_RELOC_386_TLS_LDO_32:
12048 case BFD_RELOC_386_TLS_IE_32:
12049 case BFD_RELOC_386_TLS_IE:
12050 case BFD_RELOC_386_TLS_GOTIE:
12051 case BFD_RELOC_386_TLS_LE_32:
12052 case BFD_RELOC_386_TLS_LE:
12053 case BFD_RELOC_386_TLS_GOTDESC:
12054 case BFD_RELOC_386_TLS_DESC_CALL:
12055 case BFD_RELOC_X86_64_TLSGD:
12056 case BFD_RELOC_X86_64_TLSLD:
12057 case BFD_RELOC_X86_64_DTPOFF32:
12058 case BFD_RELOC_X86_64_DTPOFF64:
12059 case BFD_RELOC_X86_64_GOTTPOFF:
12060 case BFD_RELOC_X86_64_TPOFF32:
12061 case BFD_RELOC_X86_64_TPOFF64:
12062 case BFD_RELOC_X86_64_GOTOFF64:
12063 case BFD_RELOC_X86_64_GOTPC32:
12064 case BFD_RELOC_X86_64_GOT64:
12065 case BFD_RELOC_X86_64_GOTPCREL64:
12066 case BFD_RELOC_X86_64_GOTPC64:
12067 case BFD_RELOC_X86_64_GOTPLT64:
12068 case BFD_RELOC_X86_64_PLTOFF64:
12069 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12070 case BFD_RELOC_X86_64_TLSDESC_CALL:
12071 case BFD_RELOC_RVA:
12072 case BFD_RELOC_VTABLE_ENTRY:
12073 case BFD_RELOC_VTABLE_INHERIT:
12075 case BFD_RELOC_32_SECREL:
12077 code = fixp->fx_r_type;
12079 case BFD_RELOC_X86_64_32S:
12080 if (!fixp->fx_pcrel)
12082 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
12083 code = fixp->fx_r_type;
12086 /* Fall through. */
12088 if (fixp->fx_pcrel)
12090 switch (fixp->fx_size)
12093 as_bad_where (fixp->fx_file, fixp->fx_line,
12094 _("can not do %d byte pc-relative relocation"),
12096 code = BFD_RELOC_32_PCREL;
12098 case 1: code = BFD_RELOC_8_PCREL; break;
12099 case 2: code = BFD_RELOC_16_PCREL; break;
12100 case 4: code = BFD_RELOC_32_PCREL; break;
12102 case 8: code = BFD_RELOC_64_PCREL; break;
12108 switch (fixp->fx_size)
12111 as_bad_where (fixp->fx_file, fixp->fx_line,
12112 _("can not do %d byte relocation"),
12114 code = BFD_RELOC_32;
12116 case 1: code = BFD_RELOC_8; break;
12117 case 2: code = BFD_RELOC_16; break;
12118 case 4: code = BFD_RELOC_32; break;
12120 case 8: code = BFD_RELOC_64; break;
12127 if ((code == BFD_RELOC_32
12128 || code == BFD_RELOC_32_PCREL
12129 || code == BFD_RELOC_X86_64_32S)
12131 && fixp->fx_addsy == GOT_symbol)
12134 code = BFD_RELOC_386_GOTPC;
12136 code = BFD_RELOC_X86_64_GOTPC32;
12138 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
12140 && fixp->fx_addsy == GOT_symbol)
12142 code = BFD_RELOC_X86_64_GOTPC64;
12145 rel = XNEW (arelent);
12146 rel->sym_ptr_ptr = XNEW (asymbol *);
12147 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12149 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
12151 if (!use_rela_relocations)
12153 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
12154 vtable entry to be used in the relocation's section offset. */
12155 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12156 rel->address = fixp->fx_offset;
12157 #if defined (OBJ_COFF) && defined (TE_PE)
12158 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
12159 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
12164 /* Use the rela in 64bit mode. */
12167 if (disallow_64bit_reloc)
12170 case BFD_RELOC_X86_64_DTPOFF64:
12171 case BFD_RELOC_X86_64_TPOFF64:
12172 case BFD_RELOC_64_PCREL:
12173 case BFD_RELOC_X86_64_GOTOFF64:
12174 case BFD_RELOC_X86_64_GOT64:
12175 case BFD_RELOC_X86_64_GOTPCREL64:
12176 case BFD_RELOC_X86_64_GOTPC64:
12177 case BFD_RELOC_X86_64_GOTPLT64:
12178 case BFD_RELOC_X86_64_PLTOFF64:
12179 as_bad_where (fixp->fx_file, fixp->fx_line,
12180 _("cannot represent relocation type %s in x32 mode"),
12181 bfd_get_reloc_code_name (code));
12187 if (!fixp->fx_pcrel)
12188 rel->addend = fixp->fx_offset;
12192 case BFD_RELOC_X86_64_PLT32:
12193 case BFD_RELOC_X86_64_GOT32:
12194 case BFD_RELOC_X86_64_GOTPCREL:
12195 case BFD_RELOC_X86_64_GOTPCRELX:
12196 case BFD_RELOC_X86_64_REX_GOTPCRELX:
12197 case BFD_RELOC_X86_64_TLSGD:
12198 case BFD_RELOC_X86_64_TLSLD:
12199 case BFD_RELOC_X86_64_GOTTPOFF:
12200 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
12201 case BFD_RELOC_X86_64_TLSDESC_CALL:
12202 rel->addend = fixp->fx_offset - fixp->fx_size;
12205 rel->addend = (section->vma
12207 + fixp->fx_addnumber
12208 + md_pcrel_from (fixp));
12213 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
12214 if (rel->howto == NULL)
12216 as_bad_where (fixp->fx_file, fixp->fx_line,
12217 _("cannot represent relocation type %s"),
12218 bfd_get_reloc_code_name (code));
12219 /* Set howto to a garbage value so that we can keep going. */
12220 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
12221 gas_assert (rel->howto != NULL);
12227 #include "tc-i386-intel.c"
12230 tc_x86_parse_to_dw2regnum (expressionS *exp)
12232 int saved_naked_reg;
12233 char saved_register_dot;
12235 saved_naked_reg = allow_naked_reg;
12236 allow_naked_reg = 1;
12237 saved_register_dot = register_chars['.'];
12238 register_chars['.'] = '.';
12239 allow_pseudo_reg = 1;
12240 expression_and_evaluate (exp);
12241 allow_pseudo_reg = 0;
12242 register_chars['.'] = saved_register_dot;
12243 allow_naked_reg = saved_naked_reg;
12245 if (exp->X_op == O_register && exp->X_add_number >= 0)
12247 if ((addressT) exp->X_add_number < i386_regtab_size)
12249 exp->X_op = O_constant;
12250 exp->X_add_number = i386_regtab[exp->X_add_number]
12251 .dw2_regnum[flag_code >> 1];
12254 exp->X_op = O_illegal;
12259 tc_x86_frame_initial_instructions (void)
12261 static unsigned int sp_regno[2];
12263 if (!sp_regno[flag_code >> 1])
12265 char *saved_input = input_line_pointer;
12266 char sp[][4] = {"esp", "rsp"};
12269 input_line_pointer = sp[flag_code >> 1];
12270 tc_x86_parse_to_dw2regnum (&exp);
12271 gas_assert (exp.X_op == O_constant);
12272 sp_regno[flag_code >> 1] = exp.X_add_number;
12273 input_line_pointer = saved_input;
12276 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
12277 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
12281 x86_dwarf2_addr_size (void)
12283 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
12284 if (x86_elf_abi == X86_64_X32_ABI)
12287 return bfd_arch_bits_per_address (stdoutput) / 8;
12291 i386_elf_section_type (const char *str, size_t len)
12293 if (flag_code == CODE_64BIT
12294 && len == sizeof ("unwind") - 1
12295 && strncmp (str, "unwind", 6) == 0)
12296 return SHT_X86_64_UNWIND;
12303 i386_solaris_fix_up_eh_frame (segT sec)
12305 if (flag_code == CODE_64BIT)
12306 elf_section_type (sec) = SHT_X86_64_UNWIND;
12312 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
12316 exp.X_op = O_secrel;
12317 exp.X_add_symbol = symbol;
12318 exp.X_add_number = 0;
12319 emit_expr (&exp, size);
12323 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12324 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
12327 x86_64_section_letter (int letter, const char **ptr_msg)
12329 if (flag_code == CODE_64BIT)
12332 return SHF_X86_64_LARGE;
12334 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
12337 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
12342 x86_64_section_word (char *str, size_t len)
12344 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
12345 return SHF_X86_64_LARGE;
12351 handle_large_common (int small ATTRIBUTE_UNUSED)
12353 if (flag_code != CODE_64BIT)
12355 s_comm_internal (0, elf_common_parse);
12356 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
12360 static segT lbss_section;
12361 asection *saved_com_section_ptr = elf_com_section_ptr;
12362 asection *saved_bss_section = bss_section;
12364 if (lbss_section == NULL)
12366 flagword applicable;
12367 segT seg = now_seg;
12368 subsegT subseg = now_subseg;
12370 /* The .lbss section is for local .largecomm symbols. */
12371 lbss_section = subseg_new (".lbss", 0);
12372 applicable = bfd_applicable_section_flags (stdoutput);
12373 bfd_set_section_flags (stdoutput, lbss_section,
12374 applicable & SEC_ALLOC);
12375 seg_info (lbss_section)->bss = 1;
12377 subseg_set (seg, subseg);
12380 elf_com_section_ptr = &_bfd_elf_large_com_section;
12381 bss_section = lbss_section;
12383 s_comm_internal (0, elf_common_parse);
12385 elf_com_section_ptr = saved_com_section_ptr;
12386 bss_section = saved_bss_section;
12389 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */