1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
3 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better.
33 #include "opcode/i386.h"
35 #ifndef REGISTER_WARNINGS
36 #define REGISTER_WARNINGS 1
39 #ifndef INFER_ADDR_PREFIX
40 #define INFER_ADDR_PREFIX 1
43 #ifndef SCALE1_WHEN_NO_INDEX
44 /* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48 #define SCALE1_WHEN_NO_INDEX 1
54 static unsigned int mode_from_disp_size PARAMS ((unsigned int));
55 static int fits_in_signed_byte PARAMS ((offsetT));
56 static int fits_in_unsigned_byte PARAMS ((offsetT));
57 static int fits_in_unsigned_word PARAMS ((offsetT));
58 static int fits_in_signed_word PARAMS ((offsetT));
59 static int smallest_imm_type PARAMS ((offsetT));
60 static offsetT offset_in_range PARAMS ((offsetT, int));
61 static int add_prefix PARAMS ((unsigned int));
62 static void set_16bit_code_flag PARAMS ((int));
63 static void set_16bit_gcc_code_flag PARAMS((int));
64 static void set_intel_syntax PARAMS ((int));
65 static void set_cpu_arch PARAMS ((int));
68 static bfd_reloc_code_real_type reloc
69 PARAMS ((int, int, bfd_reloc_code_real_type));
72 /* 'md_assemble ()' gathers together information and puts it into a
79 const reg_entry *regs;
84 /* TM holds the template for the insn were currently assembling. */
87 /* SUFFIX holds the instruction mnemonic suffix if given.
88 (e.g. 'l' for 'movl') */
91 /* OPERANDS gives the number of given operands. */
92 unsigned int operands;
94 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
95 of given register, displacement, memory operands and immediate
97 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
99 /* TYPES [i] is the type (see above #defines) which tells us how to
100 use OP[i] for the corresponding operand. */
101 unsigned int types[MAX_OPERANDS];
103 /* Displacement expression, immediate expression, or register for each
105 union i386_op op[MAX_OPERANDS];
107 /* Relocation type for operand */
109 enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS];
111 int disp_reloc[MAX_OPERANDS];
114 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
115 the base index byte below. */
116 const reg_entry *base_reg;
117 const reg_entry *index_reg;
118 unsigned int log2_scale_factor;
120 /* SEG gives the seg_entries of this insn. They are zero unless
121 explicit segment overrides are given. */
122 const seg_entry *seg[2]; /* segments for memory operands (if given) */
124 /* PREFIX holds all the given prefix opcodes (usually null).
125 PREFIXES is the number of prefix opcodes. */
126 unsigned int prefixes;
127 unsigned char prefix[MAX_PREFIXES];
129 /* RM and SIB are the modrm byte and the sib byte where the
130 addressing modes of this insn are encoded. */
136 typedef struct _i386_insn i386_insn;
138 /* List of chars besides those in app.c:symbol_chars that can start an
139 operand. Used to prevent the scrubber eating vital white-space. */
141 const char extra_symbol_chars[] = "*%-(@";
143 const char extra_symbol_chars[] = "*%-(";
146 /* This array holds the chars that always start a comment. If the
147 pre-processor is disabled, these aren't very useful */
148 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD))
149 /* Putting '/' here makes it impossible to use the divide operator.
150 However, we need it for compatibility with SVR4 systems. */
151 const char comment_chars[] = "#/";
152 #define PREFIX_SEPARATOR '\\'
154 const char comment_chars[] = "#";
155 #define PREFIX_SEPARATOR '/'
158 /* This array holds the chars that only start a comment at the beginning of
159 a line. If the line seems to have the form '# 123 filename'
160 .line and .file directives will appear in the pre-processed output */
161 /* Note that input_file.c hand checks for '#' at the beginning of the
162 first line of the input file. This is because the compiler outputs
163 #NO_APP at the beginning of its output. */
164 /* Also note that comments started like this one will always work if
165 '/' isn't otherwise defined. */
166 #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (TE_LINUX) && !defined(TE_FreeBSD))
167 const char line_comment_chars[] = "";
169 const char line_comment_chars[] = "/";
172 const char line_separator_chars[] = "";
174 /* Chars that can be used to separate mant from exp in floating point nums */
175 const char EXP_CHARS[] = "eE";
177 /* Chars that mean this number is a floating point constant */
180 const char FLT_CHARS[] = "fFdDxX";
182 /* tables for lexical analysis */
183 static char mnemonic_chars[256];
184 static char register_chars[256];
185 static char operand_chars[256];
186 static char identifier_chars[256];
187 static char digit_chars[256];
190 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
191 #define is_operand_char(x) (operand_chars[(unsigned char) x])
192 #define is_register_char(x) (register_chars[(unsigned char) x])
193 #define is_space_char(x) ((x) == ' ')
194 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
195 #define is_digit_char(x) (digit_chars[(unsigned char) x])
197 /* put here all non-digit non-letter charcters that may occur in an operand */
198 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
200 /* md_assemble() always leaves the strings it's passed unaltered. To
201 effect this we maintain a stack of saved characters that we've smashed
202 with '\0's (indicating end of strings for various sub-fields of the
203 assembler instruction). */
204 static char save_stack[32];
205 static char *save_stack_p; /* stack pointer */
206 #define END_STRING_AND_SAVE(s) \
207 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
208 #define RESTORE_END_STRING(s) \
209 do { *(s) = *--save_stack_p; } while (0)
211 /* The instruction we're assembling. */
214 /* Possible templates for current insn. */
215 static const templates *current_templates;
217 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
218 static expressionS disp_expressions[2], im_expressions[2];
220 static int this_operand; /* Current operand we are working on. */
222 static int flag_do_long_jump; /* FIXME what does this do? */
224 static int flag_16bit_code; /* 1 if we're writing 16-bit code,
227 static int intel_syntax = 0; /* 1 for intel syntax, 0 if att syntax. */
229 static const char *cpu_arch_name = NULL; /* cpu name */
231 static unsigned int cpu_arch_flags = 0; /* cpu feature flags */
233 static int allow_naked_reg = 0; /* 1 if register prefix % not required */
235 static char stackop_size = '\0'; /* Used in 16 bit gcc mode to add an l
236 suffix to call, ret, enter, leave, push,
237 and pop instructions so that gcc has the
238 same stack frame as in 32 bit mode. */
240 /* Interface to relax_segment.
241 There are 2 relax states for 386 jump insns: one for conditional &
242 one for unconditional jumps. This is because these two types of
243 jumps add different sizes to frags when we're figuring out what
244 sort of jump to choose to reach a given label. */
247 #define COND_JUMP 1 /* conditional jump */
248 #define UNCOND_JUMP 2 /* unconditional jump */
252 #define SMALL16 (SMALL|CODE16)
254 #define BIG16 (BIG|CODE16)
258 #define INLINE __inline__
264 #define ENCODE_RELAX_STATE(type,size) \
265 ((relax_substateT)((type<<2) | (size)))
266 #define SIZE_FROM_RELAX_STATE(s) \
267 ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) )
269 /* This table is used by relax_frag to promote short jumps to long
270 ones where necessary. SMALL (short) jumps may be promoted to BIG
271 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
272 don't allow a short jump in a 32 bit code segment to be promoted to
273 a 16 bit offset jump because it's slower (requires data size
274 prefix), and doesn't work, unless the destination is in the bottom
275 64k of the code segment (The top 16 bits of eip are zeroed). */
277 const relax_typeS md_relax_table[] =
280 1) most positive reach of this state,
281 2) most negative reach of this state,
282 3) how many bytes this mode will add to the size of the current frag
283 4) which index into the table to try if we can't fit into this one.
290 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
291 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
292 /* dword conditionals adds 4 bytes to frag:
293 1 extra opcode byte, 3 extra displacement bytes. */
295 /* word conditionals add 2 bytes to frag:
296 1 extra opcode byte, 1 extra displacement byte. */
299 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
300 {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
301 /* dword jmp adds 3 bytes to frag:
302 0 extra opcode bytes, 3 extra displacement bytes. */
304 /* word jmp adds 1 byte to frag:
305 0 extra opcode bytes, 1 extra displacement byte. */
310 static const arch_entry cpu_arch[] = {
312 {"i186", Cpu086|Cpu186 },
313 {"i286", Cpu086|Cpu186|Cpu286 },
314 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
315 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
316 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
317 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
318 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
319 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
320 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow },
321 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow },
327 i386_align_code (fragP, count)
331 /* Various efficient no-op patterns for aligning code labels. */
332 /* Note: Don't try to assemble the instructions in the comments. */
333 /* 0L and 0w are not legal */
334 static const char f32_1[] =
336 static const char f32_2[] =
337 {0x89,0xf6}; /* movl %esi,%esi */
338 static const char f32_3[] =
339 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
340 static const char f32_4[] =
341 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
342 static const char f32_5[] =
344 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
345 static const char f32_6[] =
346 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
347 static const char f32_7[] =
348 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
349 static const char f32_8[] =
351 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
352 static const char f32_9[] =
353 {0x89,0xf6, /* movl %esi,%esi */
354 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
355 static const char f32_10[] =
356 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
357 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
358 static const char f32_11[] =
359 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
360 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
361 static const char f32_12[] =
362 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
363 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
364 static const char f32_13[] =
365 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
366 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
367 static const char f32_14[] =
368 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
369 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
370 static const char f32_15[] =
371 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
372 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
373 static const char f16_3[] =
374 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
375 static const char f16_4[] =
376 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
377 static const char f16_5[] =
379 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
380 static const char f16_6[] =
381 {0x89,0xf6, /* mov %si,%si */
382 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
383 static const char f16_7[] =
384 {0x8d,0x74,0x00, /* lea 0(%si),%si */
385 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
386 static const char f16_8[] =
387 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
388 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
389 static const char *const f32_patt[] = {
390 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
391 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
393 static const char *const f16_patt[] = {
394 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
395 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
398 if (count > 0 && count <= 15)
402 memcpy(fragP->fr_literal + fragP->fr_fix,
403 f16_patt[count - 1], count);
404 if (count > 8) /* adjust jump offset */
405 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
408 memcpy(fragP->fr_literal + fragP->fr_fix,
409 f32_patt[count - 1], count);
410 fragP->fr_var = count;
414 static char *output_invalid PARAMS ((int c));
415 static int i386_operand PARAMS ((char *operand_string));
416 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
417 static const reg_entry *parse_register PARAMS ((char *reg_string,
421 static void s_bss PARAMS ((int));
424 symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
426 static INLINE unsigned int
427 mode_from_disp_size (t)
430 return (t & Disp8) ? 1 : (t & (Disp16|Disp32)) ? 2 : 0;
434 fits_in_signed_byte (num)
437 return (num >= -128) && (num <= 127);
438 } /* fits_in_signed_byte() */
441 fits_in_unsigned_byte (num)
444 return (num & 0xff) == num;
445 } /* fits_in_unsigned_byte() */
448 fits_in_unsigned_word (num)
451 return (num & 0xffff) == num;
452 } /* fits_in_unsigned_word() */
455 fits_in_signed_word (num)
458 return (-32768 <= num) && (num <= 32767);
459 } /* fits_in_signed_word() */
462 smallest_imm_type (num)
465 if (cpu_arch_flags != 0
466 && cpu_arch_flags != (Cpu086|Cpu186|Cpu286|Cpu386|Cpu486))
468 /* This code is disabled on the 486 because all the Imm1 forms
469 in the opcode table are slower on the i486. They're the
470 versions with the implicitly specified single-position
471 displacement, which has another syntax if you really want to
474 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32;
476 return (fits_in_signed_byte (num)
477 ? (Imm8S | Imm8 | Imm16 | Imm32)
478 : fits_in_unsigned_byte (num)
479 ? (Imm8 | Imm16 | Imm32)
480 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
483 } /* smallest_imm_type() */
486 offset_in_range (val, size)
494 case 1: mask = ((addressT) 1 << 8) - 1; break;
495 case 2: mask = ((addressT) 1 << 16) - 1; break;
496 case 4: mask = ((addressT) 2 << 31) - 1; break;
500 /* If BFD64, sign extend val. */
501 if ((val & ~ (((addressT) 2 << 31) - 1)) == 0)
502 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
504 if ((val & ~ mask) != 0 && (val & ~ mask) != ~ mask)
506 char buf1[40], buf2[40];
508 sprint_value (buf1, val);
509 sprint_value (buf2, val & mask);
510 as_warn (_("%s shortened to %s"), buf1, buf2);
515 /* Returns 0 if attempting to add a prefix where one from the same
516 class already exists, 1 if non rep/repne added, 2 if rep/repne
530 case CS_PREFIX_OPCODE:
531 case DS_PREFIX_OPCODE:
532 case ES_PREFIX_OPCODE:
533 case FS_PREFIX_OPCODE:
534 case GS_PREFIX_OPCODE:
535 case SS_PREFIX_OPCODE:
539 case REPNE_PREFIX_OPCODE:
540 case REPE_PREFIX_OPCODE:
543 case LOCK_PREFIX_OPCODE:
551 case ADDR_PREFIX_OPCODE:
555 case DATA_PREFIX_OPCODE:
562 as_bad (_("same type of prefix used twice"));
567 i.prefix[q] = prefix;
572 set_16bit_code_flag (new_16bit_code_flag)
573 int new_16bit_code_flag;
575 flag_16bit_code = new_16bit_code_flag;
580 set_16bit_gcc_code_flag (new_16bit_code_flag)
581 int new_16bit_code_flag;
583 flag_16bit_code = new_16bit_code_flag;
584 stackop_size = new_16bit_code_flag ? 'l' : '\0';
588 set_intel_syntax (syntax_flag)
591 /* Find out if register prefixing is specified. */
592 int ask_naked_reg = 0;
595 if (! is_end_of_line[(unsigned char) *input_line_pointer])
597 char *string = input_line_pointer;
598 int e = get_symbol_end ();
600 if (strcmp(string, "prefix") == 0)
602 else if (strcmp(string, "noprefix") == 0)
605 as_bad (_("bad argument to syntax directive."));
606 *input_line_pointer = e;
608 demand_empty_rest_of_line ();
610 intel_syntax = syntax_flag;
612 if (ask_naked_reg == 0)
615 allow_naked_reg = (intel_syntax
616 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
618 allow_naked_reg = 0; /* conservative default */
622 allow_naked_reg = (ask_naked_reg < 0);
627 int dummy ATTRIBUTE_UNUSED;
631 if (! is_end_of_line[(unsigned char) *input_line_pointer])
633 char *string = input_line_pointer;
634 int e = get_symbol_end ();
637 for (i = 0; cpu_arch[i].name; i++)
639 if (strcmp (string, cpu_arch[i].name) == 0)
641 cpu_arch_name = cpu_arch[i].name;
642 cpu_arch_flags = cpu_arch[i].flags;
646 if (!cpu_arch[i].name)
647 as_bad (_("no such architecture: `%s'"), string);
649 *input_line_pointer = e;
652 as_bad (_("missing cpu architecture"));
654 demand_empty_rest_of_line ();
657 const pseudo_typeS md_pseudo_table[] =
659 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
660 {"align", s_align_bytes, 0},
662 {"align", s_align_ptwo, 0},
664 {"arch", set_cpu_arch, 0},
668 {"ffloat", float_cons, 'f'},
669 {"dfloat", float_cons, 'd'},
670 {"tfloat", float_cons, 'x'},
672 {"noopt", s_ignore, 0},
673 {"optim", s_ignore, 0},
674 {"code16gcc", set_16bit_gcc_code_flag, 1},
675 {"code16", set_16bit_code_flag, 1},
676 {"code32", set_16bit_code_flag, 0},
677 {"intel_syntax", set_intel_syntax, 1},
678 {"att_syntax", set_intel_syntax, 0},
682 /* for interface with expression () */
683 extern char *input_line_pointer;
685 /* hash table for instruction mnemonic lookup */
686 static struct hash_control *op_hash;
687 /* hash table for register lookup */
688 static struct hash_control *reg_hash;
694 const char *hash_err;
696 /* initialize op_hash hash table */
697 op_hash = hash_new ();
700 register const template *optab;
701 register templates *core_optab;
703 optab = i386_optab; /* setup for loop */
704 core_optab = (templates *) xmalloc (sizeof (templates));
705 core_optab->start = optab;
710 if (optab->name == NULL
711 || strcmp (optab->name, (optab - 1)->name) != 0)
713 /* different name --> ship out current template list;
714 add to hash table; & begin anew */
715 core_optab->end = optab;
716 hash_err = hash_insert (op_hash,
722 as_fatal (_("Internal Error: Can't hash %s: %s"),
726 if (optab->name == NULL)
728 core_optab = (templates *) xmalloc (sizeof (templates));
729 core_optab->start = optab;
734 /* initialize reg_hash hash table */
735 reg_hash = hash_new ();
737 register const reg_entry *regtab;
739 for (regtab = i386_regtab;
740 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
743 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
749 /* fill in lexical tables: mnemonic_chars, operand_chars. */
754 for (c = 0; c < 256; c++)
759 mnemonic_chars[c] = c;
760 register_chars[c] = c;
761 operand_chars[c] = c;
763 else if (islower (c))
765 mnemonic_chars[c] = c;
766 register_chars[c] = c;
767 operand_chars[c] = c;
769 else if (isupper (c))
771 mnemonic_chars[c] = tolower (c);
772 register_chars[c] = mnemonic_chars[c];
773 operand_chars[c] = c;
776 if (isalpha (c) || isdigit (c))
777 identifier_chars[c] = c;
780 identifier_chars[c] = c;
781 operand_chars[c] = c;
786 identifier_chars['@'] = '@';
788 digit_chars['-'] = '-';
789 identifier_chars['_'] = '_';
790 identifier_chars['.'] = '.';
792 for (p = operand_special_chars; *p != '\0'; p++)
793 operand_chars[(unsigned char) *p] = *p;
796 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
797 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
799 record_alignment (text_section, 2);
800 record_alignment (data_section, 2);
801 record_alignment (bss_section, 2);
807 i386_print_statistics (file)
810 hash_print_statistics (file, "i386 opcode", op_hash);
811 hash_print_statistics (file, "i386 register", reg_hash);
817 /* debugging routines for md_assemble */
818 static void pi PARAMS ((char *, i386_insn *));
819 static void pte PARAMS ((template *));
820 static void pt PARAMS ((unsigned int));
821 static void pe PARAMS ((expressionS *));
822 static void ps PARAMS ((symbolS *));
829 register template *p;
832 fprintf (stdout, "%s: template ", line);
834 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x",
835 x->rm.mode, x->rm.reg, x->rm.regmem);
836 fprintf (stdout, " base %x index %x scale %x\n",
837 x->bi.base, x->bi.index, x->bi.scale);
838 for (i = 0; i < x->operands; i++)
840 fprintf (stdout, " #%d: ", i + 1);
842 fprintf (stdout, "\n");
844 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
845 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
846 if (x->types[i] & Imm)
848 if (x->types[i] & Disp)
858 fprintf (stdout, " %d operands ", t->operands);
859 fprintf (stdout, "opcode %x ",
861 if (t->extension_opcode != None)
862 fprintf (stdout, "ext %x ", t->extension_opcode);
863 if (t->opcode_modifier & D)
864 fprintf (stdout, "D");
865 if (t->opcode_modifier & W)
866 fprintf (stdout, "W");
867 fprintf (stdout, "\n");
868 for (i = 0; i < t->operands; i++)
870 fprintf (stdout, " #%d type ", i + 1);
871 pt (t->operand_types[i]);
872 fprintf (stdout, "\n");
880 fprintf (stdout, " operation %d\n", e->X_op);
881 fprintf (stdout, " add_number %ld (%lx)\n",
882 (long) e->X_add_number, (long) e->X_add_number);
885 fprintf (stdout, " add_symbol ");
886 ps (e->X_add_symbol);
887 fprintf (stdout, "\n");
891 fprintf (stdout, " op_symbol ");
893 fprintf (stdout, "\n");
901 fprintf (stdout, "%s type %s%s",
903 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
904 segment_name (S_GET_SEGMENT (s)));
923 { BaseIndex, "BaseIndex" },
927 { InOutPortReg, "InOutPortReg" },
928 { ShiftCount, "ShiftCount" },
929 { Control, "control reg" },
930 { Test, "test reg" },
931 { Debug, "debug reg" },
932 { FloatReg, "FReg" },
933 { FloatAcc, "FAcc" },
937 { JumpAbsolute, "Jump Absolute" },
948 register struct type_name *ty;
952 fprintf (stdout, _("Unknown"));
956 for (ty = type_names; ty->mask; ty++)
958 fprintf (stdout, "%s, ", ty->tname);
963 #endif /* DEBUG386 */
966 tc_i386_force_relocation (fixp)
970 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
971 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
976 return fixp->fx_r_type == 7;
981 static bfd_reloc_code_real_type reloc
982 PARAMS ((int, int, bfd_reloc_code_real_type));
984 static bfd_reloc_code_real_type
985 reloc (size, pcrel, other)
988 bfd_reloc_code_real_type other;
990 if (other != NO_RELOC) return other;
996 case 1: return BFD_RELOC_8_PCREL;
997 case 2: return BFD_RELOC_16_PCREL;
998 case 4: return BFD_RELOC_32_PCREL;
1000 as_bad (_("can not do %d byte pc-relative relocation"), size);
1006 case 1: return BFD_RELOC_8;
1007 case 2: return BFD_RELOC_16;
1008 case 4: return BFD_RELOC_32;
1010 as_bad (_("can not do %d byte relocation"), size);
1013 return BFD_RELOC_NONE;
1017 * Here we decide which fixups can be adjusted to make them relative to
1018 * the beginning of the section instead of the symbol. Basically we need
1019 * to make sure that the dynamic relocations are done correctly, so in
1020 * some cases we force the original symbol to be used.
1023 tc_i386_fix_adjustable (fixP)
1026 #if defined (OBJ_ELF) || defined (TE_PE)
1027 /* Prevent all adjustments to global symbols, or else dynamic
1028 linking will not work correctly. */
1029 if (S_IS_EXTERN (fixP->fx_addsy))
1031 if (S_IS_WEAK (fixP->fx_addsy))
1034 /* adjust_reloc_syms doesn't know about the GOT */
1035 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1036 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1037 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1038 || fixP->fx_r_type == BFD_RELOC_RVA
1039 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1040 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1045 #define reloc(SIZE,PCREL,OTHER) 0
1046 #define BFD_RELOC_16 0
1047 #define BFD_RELOC_32 0
1048 #define BFD_RELOC_16_PCREL 0
1049 #define BFD_RELOC_32_PCREL 0
1050 #define BFD_RELOC_386_PLT32 0
1051 #define BFD_RELOC_386_GOT32 0
1052 #define BFD_RELOC_386_GOTOFF 0
1056 intel_float_operand PARAMS ((char *mnemonic));
1059 intel_float_operand (mnemonic)
1062 if (mnemonic[0] == 'f' && mnemonic[1] =='i')
1065 if (mnemonic[0] == 'f')
1071 /* This is the guts of the machine-dependent assembler. LINE points to a
1072 machine dependent instruction. This function is supposed to emit
1073 the frags/bytes it assembles to. */
1079 /* Points to template once we've found it. */
1082 /* Count the size of the instruction generated. */
1087 char mnemonic[MAX_MNEM_SIZE];
1089 /* Initialize globals. */
1090 memset (&i, '\0', sizeof (i));
1091 for (j = 0; j < MAX_OPERANDS; j++)
1092 i.disp_reloc[j] = NO_RELOC;
1093 memset (disp_expressions, '\0', sizeof (disp_expressions));
1094 memset (im_expressions, '\0', sizeof (im_expressions));
1095 save_stack_p = save_stack; /* reset stack pointer */
1097 /* First parse an instruction mnemonic & call i386_operand for the operands.
1098 We assume that the scrubber has arranged it so that line[0] is the valid
1099 start of a (possibly prefixed) mnemonic. */
1102 char *token_start = l;
1105 /* Non-zero if we found a prefix only acceptable with string insns. */
1106 const char *expecting_string_instruction = NULL;
1111 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1114 if (mnem_p >= mnemonic + sizeof (mnemonic))
1116 as_bad (_("no such instruction: `%s'"), token_start);
1121 if (!is_space_char (*l)
1122 && *l != END_OF_INSN
1123 && *l != PREFIX_SEPARATOR)
1125 as_bad (_("invalid character %s in mnemonic"),
1126 output_invalid (*l));
1129 if (token_start == l)
1131 if (*l == PREFIX_SEPARATOR)
1132 as_bad (_("expecting prefix; got nothing"));
1134 as_bad (_("expecting mnemonic; got nothing"));
1138 /* Look up instruction (or prefix) via hash table. */
1139 current_templates = hash_find (op_hash, mnemonic);
1141 if (*l != END_OF_INSN
1142 && (! is_space_char (*l) || l[1] != END_OF_INSN)
1143 && current_templates
1144 && (current_templates->start->opcode_modifier & IsPrefix))
1146 /* If we are in 16-bit mode, do not allow addr16 or data16.
1147 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1148 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1149 && (((current_templates->start->opcode_modifier & Size32) != 0)
1152 as_bad (_("redundant %s prefix"),
1153 current_templates->start->name);
1156 /* Add prefix, checking for repeated prefixes. */
1157 switch (add_prefix (current_templates->start->base_opcode))
1162 expecting_string_instruction =
1163 current_templates->start->name;
1166 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1173 if (!current_templates)
1175 /* See if we can get a match by trimming off a suffix. */
1178 case WORD_MNEM_SUFFIX:
1179 case BYTE_MNEM_SUFFIX:
1180 case SHORT_MNEM_SUFFIX:
1181 case LONG_MNEM_SUFFIX:
1182 i.suffix = mnem_p[-1];
1184 current_templates = hash_find (op_hash, mnemonic);
1188 case DWORD_MNEM_SUFFIX:
1191 i.suffix = mnem_p[-1];
1193 current_templates = hash_find (op_hash, mnemonic);
1197 if (!current_templates)
1199 as_bad (_("no such instruction: `%s'"), token_start);
1204 /* Check if instruction is supported on specified architecture. */
1205 if (cpu_arch_flags != 0)
1207 if (current_templates->start->cpu_flags & ~ cpu_arch_flags)
1209 as_warn (_("`%s' is not supported on `%s'"),
1210 current_templates->start->name, cpu_arch_name);
1212 else if ((Cpu386 & ~ cpu_arch_flags) && !flag_16bit_code)
1214 as_warn (_("use .code16 to ensure correct addressing mode"));
1218 /* check for rep/repne without a string instruction */
1219 if (expecting_string_instruction
1220 && !(current_templates->start->opcode_modifier & IsString))
1222 as_bad (_("expecting string instruction after `%s'"),
1223 expecting_string_instruction);
1227 /* There may be operands to parse. */
1228 if (*l != END_OF_INSN)
1230 /* parse operands */
1232 /* 1 if operand is pending after ','. */
1233 unsigned int expecting_operand = 0;
1235 /* Non-zero if operand parens not balanced. */
1236 unsigned int paren_not_balanced;
1240 /* skip optional white space before operand */
1241 if (is_space_char (*l))
1243 if (!is_operand_char (*l) && *l != END_OF_INSN)
1245 as_bad (_("invalid character %s before operand %d"),
1246 output_invalid (*l),
1250 token_start = l; /* after white space */
1251 paren_not_balanced = 0;
1252 while (paren_not_balanced || *l != ',')
1254 if (*l == END_OF_INSN)
1256 if (paren_not_balanced)
1259 as_bad (_("unbalanced parenthesis in operand %d."),
1262 as_bad (_("unbalanced brackets in operand %d."),
1267 break; /* we are done */
1269 else if (!is_operand_char (*l) && !is_space_char (*l))
1271 as_bad (_("invalid character %s in operand %d"),
1272 output_invalid (*l),
1279 ++paren_not_balanced;
1281 --paren_not_balanced;
1286 ++paren_not_balanced;
1288 --paren_not_balanced;
1292 if (l != token_start)
1293 { /* yes, we've read in another operand */
1294 unsigned int operand_ok;
1295 this_operand = i.operands++;
1296 if (i.operands > MAX_OPERANDS)
1298 as_bad (_("spurious operands; (%d operands/instruction max)"),
1302 /* now parse operand adding info to 'i' as we go along */
1303 END_STRING_AND_SAVE (l);
1306 operand_ok = i386_intel_operand (token_start, intel_float_operand (mnemonic));
1308 operand_ok = i386_operand (token_start);
1310 RESTORE_END_STRING (l); /* restore old contents */
1316 if (expecting_operand)
1318 expecting_operand_after_comma:
1319 as_bad (_("expecting operand after ','; got nothing"));
1324 as_bad (_("expecting operand before ','; got nothing"));
1329 /* now *l must be either ',' or END_OF_INSN */
1332 if (*++l == END_OF_INSN)
1333 { /* just skip it, if it's \n complain */
1334 goto expecting_operand_after_comma;
1336 expecting_operand = 1;
1339 while (*l != END_OF_INSN); /* until we get end of insn */
1343 /* Now we've parsed the mnemonic into a set of templates, and have the
1346 Next, we find a template that matches the given insn,
1347 making sure the overlap of the given operands types is consistent
1348 with the template operand types. */
1350 #define MATCH(overlap, given, template) \
1351 ((overlap & ~JumpAbsolute) \
1352 && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
1354 /* If given types r0 and r1 are registers they must be of the same type
1355 unless the expected operand type register overlap is null.
1356 Note that Acc in a template matches every size of reg. */
1357 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1358 ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
1359 ((g0) & Reg) == ((g1) & Reg) || \
1360 ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1363 register unsigned int overlap0, overlap1;
1364 unsigned int overlap2;
1365 unsigned int found_reverse_match;
1368 /* All intel opcodes have reversed operands except for "bound" and
1369 "enter". We also don't reverse intersegment "jmp" and "call"
1370 instructions with 2 immediate operands so that the immediate segment
1371 precedes the offset, as it does when in AT&T mode. "enter" and the
1372 intersegment "jmp" and "call" instructions are the only ones that
1373 have two immediate operands. */
1374 if (intel_syntax && i.operands > 1
1375 && (strcmp (mnemonic, "bound") != 0)
1376 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1378 union i386_op temp_op;
1379 unsigned int temp_type;
1383 if (i.operands == 2)
1388 else if (i.operands == 3)
1393 temp_type = i.types[xchg2];
1394 i.types[xchg2] = i.types[xchg1];
1395 i.types[xchg1] = temp_type;
1396 temp_op = i.op[xchg2];
1397 i.op[xchg2] = i.op[xchg1];
1398 i.op[xchg1] = temp_op;
1400 if (i.mem_operands == 2)
1402 const seg_entry *temp_seg;
1403 temp_seg = i.seg[0];
1404 i.seg[0] = i.seg[1];
1405 i.seg[1] = temp_seg;
1411 /* Try to ensure constant immediates are represented in the smallest
1413 char guess_suffix = 0;
1417 guess_suffix = i.suffix;
1418 else if (i.reg_operands)
1420 /* Figure out a suffix from the last register operand specified.
1421 We can't do this properly yet, ie. excluding InOutPortReg,
1422 but the following works for instructions with immediates.
1423 In any case, we can't set i.suffix yet. */
1424 for (op = i.operands; --op >= 0; )
1425 if (i.types[op] & Reg)
1427 if (i.types[op] & Reg8)
1428 guess_suffix = BYTE_MNEM_SUFFIX;
1429 else if (i.types[op] & Reg16)
1430 guess_suffix = WORD_MNEM_SUFFIX;
1434 else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0))
1435 guess_suffix = WORD_MNEM_SUFFIX;
1437 for (op = i.operands; --op >= 0; )
1438 if ((i.types[op] & Imm)
1439 && i.op[op].imms->X_op == O_constant)
1441 /* If a suffix is given, this operand may be shortened. */
1442 switch (guess_suffix)
1444 case WORD_MNEM_SUFFIX:
1445 i.types[op] |= Imm16;
1447 case BYTE_MNEM_SUFFIX:
1448 i.types[op] |= Imm16 | Imm8 | Imm8S;
1452 /* If this operand is at most 16 bits, convert it to a
1453 signed 16 bit number before trying to see whether it will
1454 fit in an even smaller size. This allows a 16-bit operand
1455 such as $0xffe0 to be recognised as within Imm8S range. */
1456 if ((i.types[op] & Imm16)
1457 && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0)
1459 i.op[op].imms->X_add_number =
1460 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1462 i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number);
1469 found_reverse_match = 0;
1470 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1472 : (i.suffix == WORD_MNEM_SUFFIX
1474 : (i.suffix == SHORT_MNEM_SUFFIX
1476 : (i.suffix == LONG_MNEM_SUFFIX
1478 : (i.suffix == DWORD_MNEM_SUFFIX
1480 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
1482 for (t = current_templates->start;
1483 t < current_templates->end;
1486 /* Must have right number of operands. */
1487 if (i.operands != t->operands)
1490 /* Check the suffix, except for some instructions in intel mode. */
1491 if ((t->opcode_modifier & suffix_check)
1493 && t->base_opcode == 0xd9
1494 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
1495 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
1498 else if (!t->operands)
1499 break; /* 0 operands always matches */
1501 overlap0 = i.types[0] & t->operand_types[0];
1502 switch (t->operands)
1505 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
1510 overlap1 = i.types[1] & t->operand_types[1];
1511 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
1512 || !MATCH (overlap1, i.types[1], t->operand_types[1])
1513 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1514 t->operand_types[0],
1515 overlap1, i.types[1],
1516 t->operand_types[1]))
1519 /* check if other direction is valid ... */
1520 if ((t->opcode_modifier & (D|FloatD)) == 0)
1523 /* try reversing direction of operands */
1524 overlap0 = i.types[0] & t->operand_types[1];
1525 overlap1 = i.types[1] & t->operand_types[0];
1526 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
1527 || !MATCH (overlap1, i.types[1], t->operand_types[0])
1528 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
1529 t->operand_types[1],
1530 overlap1, i.types[1],
1531 t->operand_types[0]))
1533 /* does not match either direction */
1536 /* found_reverse_match holds which of D or FloatDR
1538 found_reverse_match = t->opcode_modifier & (D|FloatDR);
1541 /* found a forward 2 operand match here */
1542 if (t->operands == 3)
1544 /* Here we make use of the fact that there are no
1545 reverse match 3 operand instructions, and all 3
1546 operand instructions only need to be checked for
1547 register consistency between operands 2 and 3. */
1548 overlap2 = i.types[2] & t->operand_types[2];
1549 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
1550 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
1551 t->operand_types[1],
1552 overlap2, i.types[2],
1553 t->operand_types[2]))
1557 /* found either forward/reverse 2 or 3 operand match here:
1558 slip through to break */
1560 break; /* we've found a match; break out of loop */
1561 } /* for (t = ... */
1562 if (t == current_templates->end)
1563 { /* we found no match */
1564 as_bad (_("suffix or operands invalid for `%s'"),
1565 current_templates->start->name);
1570 && (i.types[0] & JumpAbsolute) != (t->operand_types[0] & JumpAbsolute))
1572 as_warn (_("indirect %s without `*'"), t->name);
1575 if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) == (IsPrefix|IgnoreSize))
1577 /* Warn them that a data or address size prefix doesn't affect
1578 assembly of the next line of code. */
1579 as_warn (_("stand-alone `%s' prefix"), t->name);
1582 /* Copy the template we found. */
1584 if (found_reverse_match)
1586 /* If we found a reverse match we must alter the opcode
1587 direction bit. found_reverse_match holds bits to change
1588 (different for int & float insns). */
1590 i.tm.base_opcode ^= found_reverse_match;
1592 i.tm.operand_types[0] = t->operand_types[1];
1593 i.tm.operand_types[1] = t->operand_types[0];
1596 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1599 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1600 i.tm.base_opcode ^= FloatR;
1602 if (i.tm.opcode_modifier & FWait)
1603 if (! add_prefix (FWAIT_OPCODE))
1606 /* Check string instruction segment overrides */
1607 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1609 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
1610 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
1612 if (i.seg[0] != NULL && i.seg[0] != &es)
1614 as_bad (_("`%s' operand %d must use `%%es' segment"),
1619 /* There's only ever one segment override allowed per instruction.
1620 This instruction possibly has a legal segment override on the
1621 second operand, so copy the segment to where non-string
1622 instructions store it, allowing common code. */
1623 i.seg[0] = i.seg[1];
1625 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
1627 if (i.seg[1] != NULL && i.seg[1] != &es)
1629 as_bad (_("`%s' operand %d must use `%%es' segment"),
1637 /* If matched instruction specifies an explicit instruction mnemonic
1639 if (i.tm.opcode_modifier & (Size16 | Size32))
1641 if (i.tm.opcode_modifier & Size16)
1642 i.suffix = WORD_MNEM_SUFFIX;
1644 i.suffix = LONG_MNEM_SUFFIX;
1646 else if (i.reg_operands)
1648 /* If there's no instruction mnemonic suffix we try to invent one
1649 based on register operands. */
1652 /* We take i.suffix from the last register operand specified,
1653 Destination register type is more significant than source
1656 for (op = i.operands; --op >= 0; )
1657 if ((i.types[op] & Reg)
1658 && !(i.tm.operand_types[op] & InOutPortReg))
1660 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
1661 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
1666 else if (i.suffix == BYTE_MNEM_SUFFIX)
1669 for (op = i.operands; --op >= 0; )
1671 /* If this is an eight bit register, it's OK. If it's
1672 the 16 or 32 bit version of an eight bit register,
1673 we will just use the low portion, and that's OK too. */
1674 if (i.types[op] & Reg8)
1677 /* movzx and movsx should not generate this warning. */
1679 && (i.tm.base_opcode == 0xfb7
1680 || i.tm.base_opcode == 0xfb6
1681 || i.tm.base_opcode == 0xfbe
1682 || i.tm.base_opcode == 0xfbf))
1685 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
1687 /* Check that the template allows eight bit regs
1688 This kills insns such as `orb $1,%edx', which
1689 maybe should be allowed. */
1690 && (i.tm.operand_types[op] & (Reg8|InOutPortReg))
1694 #if REGISTER_WARNINGS
1695 if ((i.tm.operand_types[op] & InOutPortReg) == 0)
1696 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1697 (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name,
1698 i.op[op].regs->reg_name,
1703 /* Any other register is bad */
1704 if (i.types[op] & (Reg | RegMMX | RegXMM
1706 | Control | Debug | Test
1707 | FloatReg | FloatAcc))
1709 as_bad (_("`%%%s' not allowed with `%s%c'"),
1710 i.op[op].regs->reg_name,
1717 else if (i.suffix == LONG_MNEM_SUFFIX)
1720 for (op = i.operands; --op >= 0; )
1721 /* Reject eight bit registers, except where the template
1722 requires them. (eg. movzb) */
1723 if ((i.types[op] & Reg8) != 0
1724 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1726 as_bad (_("`%%%s' not allowed with `%s%c'"),
1727 i.op[op].regs->reg_name,
1732 #if REGISTER_WARNINGS
1733 /* Warn if the e prefix on a general reg is missing. */
1734 else if ((i.types[op] & Reg16) != 0
1735 && (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
1737 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1738 (i.op[op].regs + 8)->reg_name,
1739 i.op[op].regs->reg_name,
1744 else if (i.suffix == WORD_MNEM_SUFFIX)
1747 for (op = i.operands; --op >= 0; )
1748 /* Reject eight bit registers, except where the template
1749 requires them. (eg. movzb) */
1750 if ((i.types[op] & Reg8) != 0
1751 && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
1753 as_bad (_("`%%%s' not allowed with `%s%c'"),
1754 i.op[op].regs->reg_name,
1759 #if REGISTER_WARNINGS
1760 /* Warn if the e prefix on a general reg is present. */
1761 else if ((i.types[op] & Reg32) != 0
1762 && (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
1764 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
1765 (i.op[op].regs - 8)->reg_name,
1766 i.op[op].regs->reg_name,
1774 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
1776 i.suffix = stackop_size;
1779 /* Make still unresolved immediate matches conform to size of immediate
1780 given in i.suffix. Note: overlap2 cannot be an immediate! */
1781 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32))
1782 && overlap0 != Imm8 && overlap0 != Imm8S
1783 && overlap0 != Imm16 && overlap0 != Imm32)
1787 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1788 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
1790 else if (overlap0 == (Imm16 | Imm32))
1793 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1797 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1801 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32))
1802 && overlap1 != Imm8 && overlap1 != Imm8S
1803 && overlap1 != Imm16 && overlap1 != Imm32)
1807 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
1808 (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32));
1810 else if (overlap1 == (Imm16 | Imm32))
1813 (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32;
1817 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
1821 assert ((overlap2 & Imm) == 0);
1823 i.types[0] = overlap0;
1824 if (overlap0 & ImplicitRegister)
1826 if (overlap0 & Imm1)
1827 i.imm_operands = 0; /* kludge for shift insns */
1829 i.types[1] = overlap1;
1830 if (overlap1 & ImplicitRegister)
1833 i.types[2] = overlap2;
1834 if (overlap2 & ImplicitRegister)
1837 /* Finalize opcode. First, we change the opcode based on the operand
1838 size given by i.suffix: We need not change things for byte insns. */
1840 if (!i.suffix && (i.tm.opcode_modifier & W))
1842 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
1846 /* For movzx and movsx, need to check the register type */
1848 && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
1849 if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
1851 unsigned int prefix = DATA_PREFIX_OPCODE;
1853 if ((i.op[1].regs->reg_type & Reg16) != 0)
1854 if (!add_prefix (prefix))
1858 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
1860 /* It's not a byte, select word/dword operation. */
1861 if (i.tm.opcode_modifier & W)
1863 if (i.tm.opcode_modifier & ShortForm)
1864 i.tm.base_opcode |= 8;
1866 i.tm.base_opcode |= 1;
1868 /* Now select between word & dword operations via the operand
1869 size prefix, except for instructions that will ignore this
1871 if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX))
1872 || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code
1873 && !(i.tm.opcode_modifier & IgnoreSize))
1875 unsigned int prefix = DATA_PREFIX_OPCODE;
1876 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
1877 prefix = ADDR_PREFIX_OPCODE;
1879 if (! add_prefix (prefix))
1882 /* Size floating point instruction. */
1883 if (i.suffix == LONG_MNEM_SUFFIX
1884 || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX))
1886 if (i.tm.opcode_modifier & FloatMF)
1887 i.tm.base_opcode ^= 4;
1891 if (i.tm.opcode_modifier & ImmExt)
1893 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1894 opcode suffix which is coded in the same place as an 8-bit
1895 immediate field would be. Here we fake an 8-bit immediate
1896 operand from the opcode suffix stored in tm.extension_opcode. */
1900 assert(i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1902 exp = &im_expressions[i.imm_operands++];
1903 i.op[i.operands].imms = exp;
1904 i.types[i.operands++] = Imm8;
1905 exp->X_op = O_constant;
1906 exp->X_add_number = i.tm.extension_opcode;
1907 i.tm.extension_opcode = None;
1910 /* For insns with operands there are more diddles to do to the opcode. */
1913 /* Default segment register this instruction will use
1914 for memory accesses. 0 means unknown.
1915 This is only for optimizing out unnecessary segment overrides. */
1916 const seg_entry *default_seg = 0;
1918 /* The imul $imm, %reg instruction is converted into
1919 imul $imm, %reg, %reg, and the clr %reg instruction
1920 is converted into xor %reg, %reg. */
1921 if (i.tm.opcode_modifier & regKludge)
1923 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
1924 /* Pretend we saw the extra register operand. */
1925 assert (i.op[first_reg_op+1].regs == 0);
1926 i.op[first_reg_op+1].regs = i.op[first_reg_op].regs;
1927 i.types[first_reg_op+1] = i.types[first_reg_op];
1931 if (i.tm.opcode_modifier & ShortForm)
1933 /* The register or float register operand is in operand 0 or 1. */
1934 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
1935 /* Register goes in low 3 bits of opcode. */
1936 i.tm.base_opcode |= i.op[op].regs->reg_num;
1937 if ((i.tm.opcode_modifier & Ugh) != 0)
1939 /* Warn about some common errors, but press on regardless.
1940 The first case can be generated by gcc (<= 2.8.1). */
1941 if (i.operands == 2)
1943 /* reversed arguments on faddp, fsubp, etc. */
1944 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
1945 i.op[1].regs->reg_name,
1946 i.op[0].regs->reg_name);
1950 /* extraneous `l' suffix on fp insn */
1951 as_warn (_("translating to `%s %%%s'"), i.tm.name,
1952 i.op[0].regs->reg_name);
1956 else if (i.tm.opcode_modifier & Modrm)
1958 /* The opcode is completed (modulo i.tm.extension_opcode which
1959 must be put into the modrm byte).
1960 Now, we make the modrm & index base bytes based on all the
1961 info we've collected. */
1963 /* i.reg_operands MUST be the number of real register operands;
1964 implicit registers do not count. */
1965 if (i.reg_operands == 2)
1967 unsigned int source, dest;
1968 source = ((i.types[0]
1969 & (Reg | RegMMX | RegXMM
1971 | Control | Debug | Test))
1976 /* One of the register operands will be encoded in the
1977 i.tm.reg field, the other in the combined i.tm.mode
1978 and i.tm.regmem fields. If no form of this
1979 instruction supports a memory destination operand,
1980 then we assume the source operand may sometimes be
1981 a memory operand and so we need to store the
1982 destination in the i.rm.reg field. */
1983 if ((i.tm.operand_types[dest] & AnyMem) == 0)
1985 i.rm.reg = i.op[dest].regs->reg_num;
1986 i.rm.regmem = i.op[source].regs->reg_num;
1990 i.rm.reg = i.op[source].regs->reg_num;
1991 i.rm.regmem = i.op[dest].regs->reg_num;
1995 { /* if it's not 2 reg operands... */
1998 unsigned int fake_zero_displacement = 0;
1999 unsigned int op = ((i.types[0] & AnyMem)
2001 : (i.types[1] & AnyMem) ? 1 : 2);
2008 if (! i.disp_operands)
2009 fake_zero_displacement = 1;
2012 /* Operand is just <disp> */
2013 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
2015 i.rm.regmem = NO_BASE_REGISTER_16;
2016 i.types[op] &= ~Disp;
2017 i.types[op] |= Disp16;
2021 i.rm.regmem = NO_BASE_REGISTER;
2022 i.types[op] &= ~Disp;
2023 i.types[op] |= Disp32;
2026 else /* ! i.base_reg && i.index_reg */
2028 i.sib.index = i.index_reg->reg_num;
2029 i.sib.base = NO_BASE_REGISTER;
2030 i.sib.scale = i.log2_scale_factor;
2031 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2032 i.types[op] &= ~Disp;
2033 i.types[op] |= Disp32; /* Must be 32 bit */
2036 else if (i.base_reg->reg_type & Reg16)
2038 switch (i.base_reg->reg_num)
2043 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2044 i.rm.regmem = i.index_reg->reg_num - 6;
2051 if ((i.types[op] & Disp) == 0)
2053 /* fake (%bp) into 0(%bp) */
2054 i.types[op] |= Disp8;
2055 fake_zero_displacement = 1;
2058 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2059 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2061 default: /* (%si) -> 4 or (%di) -> 5 */
2062 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2064 i.rm.mode = mode_from_disp_size (i.types[op]);
2066 else /* i.base_reg and 32 bit mode */
2068 i.rm.regmem = i.base_reg->reg_num;
2069 i.sib.base = i.base_reg->reg_num;
2070 if (i.base_reg->reg_num == EBP_REG_NUM)
2073 if (i.disp_operands == 0)
2075 fake_zero_displacement = 1;
2076 i.types[op] |= Disp8;
2079 else if (i.base_reg->reg_num == ESP_REG_NUM)
2083 i.sib.scale = i.log2_scale_factor;
2086 /* <disp>(%esp) becomes two byte modrm
2087 with no index register. We've already
2088 stored the code for esp in i.rm.regmem
2089 ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
2090 base register besides %esp will not use
2091 the extra modrm byte. */
2092 i.sib.index = NO_INDEX_REGISTER;
2093 #if ! SCALE1_WHEN_NO_INDEX
2094 /* Another case where we force the second
2096 if (i.log2_scale_factor)
2097 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2102 i.sib.index = i.index_reg->reg_num;
2103 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2105 i.rm.mode = mode_from_disp_size (i.types[op]);
2108 if (fake_zero_displacement)
2110 /* Fakes a zero displacement assuming that i.types[op]
2111 holds the correct displacement size. */
2114 assert (i.op[op].disps == 0);
2115 exp = &disp_expressions[i.disp_operands++];
2116 i.op[op].disps = exp;
2117 exp->X_op = O_constant;
2118 exp->X_add_number = 0;
2119 exp->X_add_symbol = (symbolS *) 0;
2120 exp->X_op_symbol = (symbolS *) 0;
2124 /* Fill in i.rm.reg or i.rm.regmem field with register
2125 operand (if any) based on i.tm.extension_opcode.
2126 Again, we must be careful to make sure that
2127 segment/control/debug/test/MMX registers are coded
2128 into the i.rm.reg field. */
2133 & (Reg | RegMMX | RegXMM
2135 | Control | Debug | Test))
2138 & (Reg | RegMMX | RegXMM
2140 | Control | Debug | Test))
2143 /* If there is an extension opcode to put here, the
2144 register number must be put into the regmem field. */
2145 if (i.tm.extension_opcode != None)
2146 i.rm.regmem = i.op[op].regs->reg_num;
2148 i.rm.reg = i.op[op].regs->reg_num;
2150 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2
2151 we must set it to 3 to indicate this is a register
2152 operand in the regmem field. */
2153 if (!i.mem_operands)
2157 /* Fill in i.rm.reg field with extension opcode (if any). */
2158 if (i.tm.extension_opcode != None)
2159 i.rm.reg = i.tm.extension_opcode;
2162 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2164 if (i.tm.base_opcode == POP_SEG_SHORT && i.op[0].regs->reg_num == 1)
2166 as_bad (_("you can't `pop %%cs'"));
2169 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2171 else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32)
2175 else if ((i.tm.opcode_modifier & IsString) != 0)
2177 /* For the string instructions that allow a segment override
2178 on one of their operands, the default segment is ds. */
2182 /* If a segment was explicitly specified,
2183 and the specified segment is not the default,
2184 use an opcode prefix to select it.
2185 If we never figured out what the default segment is,
2186 then default_seg will be zero at this point,
2187 and the specified segment prefix will always be used. */
2188 if ((i.seg[0]) && (i.seg[0] != default_seg))
2190 if (! add_prefix (i.seg[0]->seg_prefix))
2194 else if ((i.tm.opcode_modifier & Ugh) != 0)
2196 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2197 as_warn (_("translating to `%sp'"), i.tm.name);
2201 /* Handle conversion of 'int $3' --> special int3 insn. */
2202 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2204 i.tm.base_opcode = INT3_OPCODE;
2208 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
2209 && i.op[0].disps->X_op == O_constant)
2211 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2212 the absolute address given by the constant. Since ix86 jumps and
2213 calls are pc relative, we need to generate a reloc. */
2214 i.op[0].disps->X_add_symbol = &abs_symbol;
2215 i.op[0].disps->X_op = O_symbol;
2218 /* We are ready to output the insn. */
2223 if (i.tm.opcode_modifier & Jump)
2230 if (flag_16bit_code)
2234 if (i.prefix[DATA_PREFIX])
2245 if (i.prefixes != 0 && !intel_syntax)
2246 as_warn (_("skipping prefixes on this instruction"));
2248 /* It's always a symbol; End frag & setup for relax.
2249 Make sure there is enough room in this frag for the largest
2250 instruction we may generate in md_convert_frag. This is 2
2251 bytes for the opcode and room for the prefix and largest
2253 frag_grow (prefix + 2 + size);
2254 insn_size += prefix + 1;
2255 /* Prefix and 1 opcode byte go in fr_fix. */
2256 p = frag_more (prefix + 1);
2258 *p++ = DATA_PREFIX_OPCODE;
2259 *p = i.tm.base_opcode;
2260 /* 1 possible extra opcode + displacement go in fr_var. */
2261 frag_var (rs_machine_dependent,
2264 ((unsigned char) *p == JUMP_PC_RELATIVE
2265 ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16
2266 : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16),
2267 i.op[0].disps->X_add_symbol,
2268 i.op[0].disps->X_add_number,
2271 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
2275 if (i.tm.opcode_modifier & JumpByte)
2277 /* This is a loop or jecxz type instruction. */
2279 if (i.prefix[ADDR_PREFIX])
2282 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2291 if (flag_16bit_code)
2294 if (i.prefix[DATA_PREFIX])
2297 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
2307 if (i.prefixes != 0 && !intel_syntax)
2308 as_warn (_("skipping prefixes on this instruction"));
2310 if (fits_in_unsigned_byte (i.tm.base_opcode))
2312 insn_size += 1 + size;
2313 p = frag_more (1 + size);
2317 /* opcode can be at most two bytes */
2318 insn_size += 2 + size;
2319 p = frag_more (2 + size);
2320 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2322 *p++ = i.tm.base_opcode & 0xff;
2324 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2325 i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0]));
2327 else if (i.tm.opcode_modifier & JumpInterSegment)
2334 if (flag_16bit_code)
2338 if (i.prefix[DATA_PREFIX])
2349 if (i.prefixes != 0 && !intel_syntax)
2350 as_warn (_("skipping prefixes on this instruction"));
2352 insn_size += prefix + 1 + 2 + size; /* 1 opcode; 2 segment; offset */
2353 p = frag_more (prefix + 1 + 2 + size);
2355 *p++ = DATA_PREFIX_OPCODE;
2356 *p++ = i.tm.base_opcode;
2357 if (i.op[1].imms->X_op == O_constant)
2359 offsetT n = i.op[1].imms->X_add_number;
2362 && !fits_in_unsigned_word (n)
2363 && !fits_in_signed_word (n))
2365 as_bad (_("16-bit jump out of range"));
2368 md_number_to_chars (p, n, size);
2371 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2372 i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0]));
2373 if (i.op[0].imms->X_op != O_constant)
2374 as_bad (_("can't handle non absolute segment in `%s'"),
2376 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
2380 /* Output normal instructions here. */
2383 /* The prefix bytes. */
2385 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
2392 md_number_to_chars (p, (valueT) *q, 1);
2396 /* Now the opcode; be careful about word order here! */
2397 if (fits_in_unsigned_byte (i.tm.base_opcode))
2400 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
2402 else if (fits_in_unsigned_word (i.tm.base_opcode))
2406 /* put out high byte first: can't use md_number_to_chars! */
2407 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2408 *p = i.tm.base_opcode & 0xff;
2411 { /* opcode is either 3 or 4 bytes */
2412 if (i.tm.base_opcode & 0xff000000)
2416 *p++ = (i.tm.base_opcode >> 24) & 0xff;
2423 *p++ = (i.tm.base_opcode >> 16) & 0xff;
2424 *p++ = (i.tm.base_opcode >> 8) & 0xff;
2425 *p = (i.tm.base_opcode) & 0xff;
2428 /* Now the modrm byte and sib byte (if present). */
2429 if (i.tm.opcode_modifier & Modrm)
2433 md_number_to_chars (p,
2434 (valueT) (i.rm.regmem << 0
2438 /* If i.rm.regmem == ESP (4)
2439 && i.rm.mode != (Register mode)
2441 ==> need second modrm byte. */
2442 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
2444 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
2448 md_number_to_chars (p,
2449 (valueT) (i.sib.base << 0
2451 | i.sib.scale << 6),
2456 if (i.disp_operands)
2458 register unsigned int n;
2460 for (n = 0; n < i.operands; n++)
2462 if (i.types[n] & Disp)
2464 if (i.op[n].disps->X_op == O_constant)
2470 if (i.types[n] & (Disp8 | Disp16))
2473 if (i.types[n] & Disp8)
2476 val = offset_in_range (i.op[n].disps->X_add_number,
2479 p = frag_more (size);
2480 md_number_to_chars (p, val, size);
2486 if (i.types[n] & Disp16)
2490 p = frag_more (size);
2491 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2493 reloc (size, 0, i.disp_reloc[n]));
2497 } /* end displacement output */
2499 /* output immediate */
2502 register unsigned int n;
2504 for (n = 0; n < i.operands; n++)
2506 if (i.types[n] & Imm)
2508 if (i.op[n].imms->X_op == O_constant)
2514 if (i.types[n] & (Imm8 | Imm8S | Imm16))
2517 if (i.types[n] & (Imm8 | Imm8S))
2520 val = offset_in_range (i.op[n].imms->X_add_number,
2523 p = frag_more (size);
2524 md_number_to_chars (p, val, size);
2527 { /* not absolute_section */
2528 /* Need a 32-bit fixup (don't support 8bit
2529 non-absolute imms). Try to support other
2531 #ifdef BFD_ASSEMBLER
2532 enum bfd_reloc_code_real reloc_type;
2538 if (i.types[n] & Imm16)
2540 else if (i.types[n] & (Imm8 | Imm8S))
2544 p = frag_more (size);
2545 reloc_type = reloc (size, 0, i.disp_reloc[0]);
2546 #ifdef BFD_ASSEMBLER
2547 if (reloc_type == BFD_RELOC_32
2549 && GOT_symbol == i.op[n].imms->X_add_symbol
2550 && (i.op[n].imms->X_op == O_symbol
2551 || (i.op[n].imms->X_op == O_add
2552 && ((symbol_get_value_expression
2553 (i.op[n].imms->X_op_symbol)->X_op)
2556 reloc_type = BFD_RELOC_386_GOTPC;
2557 i.op[n].imms->X_add_number += 3;
2560 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2561 i.op[n].imms, 0, reloc_type);
2565 } /* end immediate output */
2573 #endif /* DEBUG386 */
2577 static int i386_immediate PARAMS ((char *));
2580 i386_immediate (imm_start)
2583 char *save_input_line_pointer;
2587 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
2589 as_bad (_("only 1 or 2 immediate operands are allowed"));
2593 exp = &im_expressions[i.imm_operands++];
2594 i.op[this_operand].imms = exp;
2596 if (is_space_char (*imm_start))
2599 save_input_line_pointer = input_line_pointer;
2600 input_line_pointer = imm_start;
2605 * We can have operands of the form
2606 * <symbol>@GOTOFF+<nnn>
2607 * Take the easy way out here and copy everything
2608 * into a temporary buffer...
2612 cp = strchr (input_line_pointer, '@');
2619 /* GOT relocations are not supported in 16 bit mode */
2620 if (flag_16bit_code)
2621 as_bad (_("GOT relocations not supported in 16 bit mode"));
2623 if (GOT_symbol == NULL)
2624 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2626 if (strncmp (cp + 1, "PLT", 3) == 0)
2628 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2631 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2633 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2636 else if (strncmp (cp + 1, "GOT", 3) == 0)
2638 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2642 as_bad (_("bad reloc specifier in expression"));
2644 /* Replace the relocation token with ' ', so that errors like
2645 foo@GOTOFF1 will be detected. */
2646 first = cp - input_line_pointer;
2647 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2648 memcpy (tmpbuf, input_line_pointer, first);
2649 tmpbuf[first] = ' ';
2650 strcpy (tmpbuf + first + 1, cp + 1 + len);
2651 input_line_pointer = tmpbuf;
2656 exp_seg = expression (exp);
2659 if (*input_line_pointer)
2660 as_bad (_("ignoring junk `%s' after expression"), input_line_pointer);
2662 input_line_pointer = save_input_line_pointer;
2664 if (exp->X_op == O_absent || exp->X_op == O_big)
2666 /* missing or bad expr becomes absolute 0 */
2667 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
2669 exp->X_op = O_constant;
2670 exp->X_add_number = 0;
2671 exp->X_add_symbol = (symbolS *) 0;
2672 exp->X_op_symbol = (symbolS *) 0;
2675 if (exp->X_op == O_constant)
2677 i.types[this_operand] |= Imm32; /* Size it properly later. */
2679 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2681 #ifdef BFD_ASSEMBLER
2682 OUTPUT_FLAVOR == bfd_target_aout_flavour &&
2684 exp_seg != text_section
2685 && exp_seg != data_section
2686 && exp_seg != bss_section
2687 && exp_seg != undefined_section
2688 #ifdef BFD_ASSEMBLER
2689 && !bfd_is_com_section (exp_seg)
2693 #ifdef BFD_ASSEMBLER
2694 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
2696 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
2703 /* This is an address. The size of the address will be
2704 determined later, depending on destination register,
2705 suffix, or the default for the section. We exclude
2706 Imm8S here so that `push $foo' and other instructions
2707 with an Imm8S form will use Imm16 or Imm32. */
2708 i.types[this_operand] |= (Imm8 | Imm16 | Imm32);
2714 static int i386_scale PARAMS ((char *));
2720 if (!isdigit (*scale))
2727 i.log2_scale_factor = 0;
2730 i.log2_scale_factor = 1;
2733 i.log2_scale_factor = 2;
2736 i.log2_scale_factor = 3;
2740 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
2744 if (i.log2_scale_factor != 0 && ! i.index_reg)
2746 as_warn (_("scale factor of %d without an index register"),
2747 1 << i.log2_scale_factor);
2748 #if SCALE1_WHEN_NO_INDEX
2749 i.log2_scale_factor = 0;
2755 static int i386_displacement PARAMS ((char *, char *));
2758 i386_displacement (disp_start, disp_end)
2762 register expressionS *exp;
2764 char *save_input_line_pointer;
2765 int bigdisp = Disp32;
2767 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0))
2769 i.types[this_operand] |= bigdisp;
2771 exp = &disp_expressions[i.disp_operands];
2772 i.op[this_operand].disps = exp;
2774 save_input_line_pointer = input_line_pointer;
2775 input_line_pointer = disp_start;
2776 END_STRING_AND_SAVE (disp_end);
2778 #ifndef GCC_ASM_O_HACK
2779 #define GCC_ASM_O_HACK 0
2782 END_STRING_AND_SAVE (disp_end + 1);
2783 if ((i.types[this_operand] & BaseIndex) != 0
2784 && displacement_string_end[-1] == '+')
2786 /* This hack is to avoid a warning when using the "o"
2787 constraint within gcc asm statements.
2790 #define _set_tssldt_desc(n,addr,limit,type) \
2791 __asm__ __volatile__ ( \
2793 "movw %w1,2+%0\n\t" \
2795 "movb %b1,4+%0\n\t" \
2796 "movb %4,5+%0\n\t" \
2797 "movb $0,6+%0\n\t" \
2798 "movb %h1,7+%0\n\t" \
2800 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
2802 This works great except that the output assembler ends
2803 up looking a bit weird if it turns out that there is
2804 no offset. You end up producing code that looks like:
2817 So here we provide the missing zero.
2820 *displacement_string_end = '0';
2826 * We can have operands of the form
2827 * <symbol>@GOTOFF+<nnn>
2828 * Take the easy way out here and copy everything
2829 * into a temporary buffer...
2833 cp = strchr (input_line_pointer, '@');
2840 /* GOT relocations are not supported in 16 bit mode */
2841 if (flag_16bit_code)
2842 as_bad (_("GOT relocations not supported in 16 bit mode"));
2844 if (GOT_symbol == NULL)
2845 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
2847 if (strncmp (cp + 1, "PLT", 3) == 0)
2849 i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32;
2852 else if (strncmp (cp + 1, "GOTOFF", 6) == 0)
2854 i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF;
2857 else if (strncmp (cp + 1, "GOT", 3) == 0)
2859 i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32;
2863 as_bad (_("bad reloc specifier in expression"));
2865 /* Replace the relocation token with ' ', so that errors like
2866 foo@GOTOFF1 will be detected. */
2867 first = cp - input_line_pointer;
2868 tmpbuf = (char *) alloca (strlen(input_line_pointer));
2869 memcpy (tmpbuf, input_line_pointer, first);
2870 tmpbuf[first] = ' ';
2871 strcpy (tmpbuf + first + 1, cp + 1 + len);
2872 input_line_pointer = tmpbuf;
2877 exp_seg = expression (exp);
2879 #ifdef BFD_ASSEMBLER
2880 /* We do this to make sure that the section symbol is in
2881 the symbol table. We will ultimately change the relocation
2882 to be relative to the beginning of the section */
2883 if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF)
2885 if (S_IS_LOCAL(exp->X_add_symbol)
2886 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
2887 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
2888 assert (exp->X_op == O_symbol);
2889 exp->X_op = O_subtract;
2890 exp->X_op_symbol = GOT_symbol;
2891 i.disp_reloc[this_operand] = BFD_RELOC_32;
2896 if (*input_line_pointer)
2897 as_bad (_("ignoring junk `%s' after expression"),
2898 input_line_pointer);
2900 RESTORE_END_STRING (disp_end + 1);
2902 RESTORE_END_STRING (disp_end);
2903 input_line_pointer = save_input_line_pointer;
2905 if (exp->X_op == O_absent || exp->X_op == O_big)
2907 /* missing or bad expr becomes absolute 0 */
2908 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2910 exp->X_op = O_constant;
2911 exp->X_add_number = 0;
2912 exp->X_add_symbol = (symbolS *) 0;
2913 exp->X_op_symbol = (symbolS *) 0;
2916 if (exp->X_op == O_constant)
2918 if (i.types[this_operand] & Disp16)
2920 /* We know this operand is at most 16 bits, so convert to a
2921 signed 16 bit number before trying to see whether it will
2922 fit in an even smaller size. */
2924 (((exp->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2926 if (fits_in_signed_byte (exp->X_add_number))
2927 i.types[this_operand] |= Disp8;
2929 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
2931 #ifdef BFD_ASSEMBLER
2932 OUTPUT_FLAVOR == bfd_target_aout_flavour &&
2934 exp_seg != text_section
2935 && exp_seg != data_section
2936 && exp_seg != bss_section
2937 && exp_seg != undefined_section)
2939 #ifdef BFD_ASSEMBLER
2940 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
2942 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
2950 static int i386_operand_modifier PARAMS ((char **, int));
2953 i386_operand_modifier (op_string, got_a_float)
2957 if (!strncasecmp (*op_string, "BYTE PTR", 8))
2959 i.suffix = BYTE_MNEM_SUFFIX;
2964 else if (!strncasecmp (*op_string, "WORD PTR", 8))
2966 if (got_a_float == 2) /* "fi..." */
2967 i.suffix = SHORT_MNEM_SUFFIX;
2969 i.suffix = WORD_MNEM_SUFFIX;
2974 else if (!strncasecmp (*op_string, "DWORD PTR", 9))
2976 if (got_a_float == 1) /* "f..." */
2977 i.suffix = SHORT_MNEM_SUFFIX;
2979 i.suffix = LONG_MNEM_SUFFIX;
2984 else if (!strncasecmp (*op_string, "QWORD PTR", 9))
2986 i.suffix = DWORD_MNEM_SUFFIX;
2991 else if (!strncasecmp (*op_string, "XWORD PTR", 9))
2993 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
2998 else if (!strncasecmp (*op_string, "SHORT", 5))
3004 else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12))
3010 else if (!strncasecmp (*op_string, "FLAT", 4))
3016 else return NONE_FOUND;
3019 static char * build_displacement_string PARAMS ((int, char *));
3022 build_displacement_string (initial_disp, op_string)
3026 char *temp_string = (char *) malloc (strlen (op_string) + 1);
3027 char *end_of_operand_string;
3031 temp_string[0] = '\0';
3032 tc = end_of_operand_string = strchr (op_string, '[');
3033 if (initial_disp && !end_of_operand_string)
3035 strcpy (temp_string, op_string);
3039 /* Build the whole displacement string */
3042 strncpy (temp_string, op_string, end_of_operand_string - op_string);
3043 temp_string[end_of_operand_string - op_string] = '\0';
3047 temp_disp = op_string;
3049 while (*temp_disp != '\0')
3052 int add_minus = (*temp_disp == '-');
3054 if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[')
3057 if (is_space_char (*temp_disp))
3060 /* Don't consider registers */
3061 if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg)
3062 && parse_register (temp_disp, &end_op)) )
3064 char *string_start = temp_disp;
3066 while (*temp_disp != ']'
3067 && *temp_disp != '+'
3068 && *temp_disp != '-'
3069 && *temp_disp != '*')
3073 strcat (temp_string, "-");
3075 strcat (temp_string, "+");
3077 strncat (temp_string, string_start, temp_disp - string_start);
3078 if (*temp_disp == '+' || *temp_disp == '-')
3082 while (*temp_disp != '\0'
3083 && *temp_disp != '+'
3084 && *temp_disp != '-')
3091 static int i386_parse_seg PARAMS ((char *));
3094 i386_parse_seg (op_string)
3097 if (is_space_char (*op_string))
3100 /* Should be one of es, cs, ss, ds fs or gs */
3101 switch (*op_string++)
3104 i.seg[i.mem_operands] = &es;
3107 i.seg[i.mem_operands] = &cs;
3110 i.seg[i.mem_operands] = &ss;
3113 i.seg[i.mem_operands] = &ds;
3116 i.seg[i.mem_operands] = &fs;
3119 i.seg[i.mem_operands] = &gs;
3122 as_bad (_("bad segment name `%s'"), op_string);
3126 if (*op_string++ != 's')
3128 as_bad (_("bad segment name `%s'"), op_string);
3132 if (is_space_char (*op_string))
3135 if (*op_string != ':')
3137 as_bad (_("bad segment name `%s'"), op_string);
3145 static int i386_index_check PARAMS((const char *));
3147 /* Make sure the memory operand we've been dealt is valid.
3148 Returns 1 on success, 0 on a failure.
3151 i386_index_check (operand_string)
3152 const char *operand_string;
3154 #if INFER_ADDR_PREFIX
3159 if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)
3160 /* 16 bit mode checks */
3162 && ((i.base_reg->reg_type & (Reg16|BaseIndex))
3163 != (Reg16|BaseIndex)))
3165 && (((i.index_reg->reg_type & (Reg16|BaseIndex))
3166 != (Reg16|BaseIndex))
3168 && i.base_reg->reg_num < 6
3169 && i.index_reg->reg_num >= 6
3170 && i.log2_scale_factor == 0))))
3171 /* 32 bit mode checks */
3173 && (i.base_reg->reg_type & Reg32) == 0)
3175 && ((i.index_reg->reg_type & (Reg32|BaseIndex))
3176 != (Reg32|BaseIndex)))))
3178 #if INFER_ADDR_PREFIX
3179 if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
3181 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3183 /* Change the size of any displacement too. At most one of
3184 Disp16 or Disp32 is set.
3185 FIXME. There doesn't seem to be any real need for separate
3186 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
3187 Removing them would probably clean up the code quite a lot.
3189 if (i.types[this_operand] & (Disp16|Disp32))
3190 i.types[this_operand] ^= (Disp16|Disp32);
3195 as_bad (_("`%s' is not a valid base/index expression"),
3199 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3201 flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32");
3207 static int i386_intel_memory_operand PARAMS ((char *));
3210 i386_intel_memory_operand (operand_string)
3211 char *operand_string;
3213 char *op_string = operand_string;
3214 char *end_of_operand_string;
3216 if ((i.mem_operands == 1
3217 && (current_templates->start->opcode_modifier & IsString) == 0)
3218 || i.mem_operands == 2)
3220 as_bad (_("too many memory references for `%s'"),
3221 current_templates->start->name);
3225 /* First check for a segment override. */
3226 if (*op_string != '[')
3230 end_seg = strchr (op_string, ':');
3233 if (!i386_parse_seg (op_string))
3235 op_string = end_seg + 1;
3239 /* Look for displacement preceding open bracket */
3240 if (*op_string != '[')
3244 if (i.disp_operands)
3247 temp_string = build_displacement_string (true, op_string);
3249 if (!i386_displacement (temp_string, temp_string + strlen (temp_string)))
3256 end_of_operand_string = strchr (op_string, '[');
3257 if (!end_of_operand_string)
3258 end_of_operand_string = op_string + strlen (op_string);
3260 if (is_space_char (*end_of_operand_string))
3261 --end_of_operand_string;
3263 op_string = end_of_operand_string;
3266 if (*op_string == '[')
3270 /* Pick off each component and figure out where it belongs */
3272 end_of_operand_string = op_string;
3274 while (*op_string != ']')
3276 const reg_entry *temp_reg;
3280 while (*end_of_operand_string != '+'
3281 && *end_of_operand_string != '-'
3282 && *end_of_operand_string != '*'
3283 && *end_of_operand_string != ']')
3284 end_of_operand_string++;
3286 temp_string = op_string;
3287 if (*temp_string == '+')
3290 if (is_space_char (*temp_string))
3294 if ((*temp_string == REGISTER_PREFIX || allow_naked_reg)
3295 && (temp_reg = parse_register (temp_string, &end_op)) != NULL)
3297 if (i.base_reg == NULL)
3298 i.base_reg = temp_reg;
3300 i.index_reg = temp_reg;
3302 i.types[this_operand] |= BaseIndex;
3304 else if (*temp_string == REGISTER_PREFIX)
3306 as_bad (_("bad register name `%s'"), temp_string);
3309 else if (is_digit_char (*op_string)
3310 || *op_string == '+' || *op_string == '-')
3314 if (i.disp_operands != 0)
3317 temp_string = build_displacement_string (false, op_string);
3319 temp_str = temp_string;
3320 if (*temp_str == '+')
3323 if (!i386_displacement (temp_str, temp_str + strlen (temp_str)))
3331 end_of_operand_string = op_string;
3332 while (*end_of_operand_string != ']'
3333 && *end_of_operand_string != '+'
3334 && *end_of_operand_string != '-'
3335 && *end_of_operand_string != '*')
3336 ++end_of_operand_string;
3338 else if (*op_string == '*')
3342 if (i.base_reg && !i.index_reg)
3344 i.index_reg = i.base_reg;
3348 if (!i386_scale (op_string))
3351 op_string = end_of_operand_string;
3352 ++end_of_operand_string;
3356 if (i386_index_check (operand_string) == 0)
3364 i386_intel_operand (operand_string, got_a_float)
3365 char *operand_string;
3368 const reg_entry * r;
3370 char *op_string = operand_string;
3372 int operand_modifier = i386_operand_modifier (&op_string, got_a_float);
3373 if (is_space_char (*op_string))
3376 switch (operand_modifier)
3383 if (!i386_intel_memory_operand (op_string))
3389 if (!i386_immediate (op_string))
3395 /* Should be register or immediate */
3396 if (is_digit_char (*op_string)
3397 && strchr (op_string, '[') == 0)
3399 if (!i386_immediate (op_string))
3402 else if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3403 && (r = parse_register (op_string, &end_op)) != NULL)
3405 /* Check for a segment override by searching for ':' after a
3406 segment register. */
3408 if (is_space_char (*op_string))
3410 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3415 i.seg[i.mem_operands] = &es;
3418 i.seg[i.mem_operands] = &cs;
3421 i.seg[i.mem_operands] = &ss;
3424 i.seg[i.mem_operands] = &ds;
3427 i.seg[i.mem_operands] = &fs;
3430 i.seg[i.mem_operands] = &gs;
3435 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3436 i.op[this_operand].regs = r;
3439 else if (*op_string == REGISTER_PREFIX)
3441 as_bad (_("bad register name `%s'"), op_string);
3444 else if (!i386_intel_memory_operand (op_string))
3453 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
3457 i386_operand (operand_string)
3458 char *operand_string;
3462 char *op_string = operand_string;
3464 if (is_space_char (*op_string))
3467 /* We check for an absolute prefix (differentiating,
3468 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
3469 if (*op_string == ABSOLUTE_PREFIX)
3472 if (is_space_char (*op_string))
3474 i.types[this_operand] |= JumpAbsolute;
3477 /* Check if operand is a register. */
3478 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3479 && (r = parse_register (op_string, &end_op)) != NULL)
3481 /* Check for a segment override by searching for ':' after a
3482 segment register. */
3484 if (is_space_char (*op_string))
3486 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3491 i.seg[i.mem_operands] = &es;
3494 i.seg[i.mem_operands] = &cs;
3497 i.seg[i.mem_operands] = &ss;
3500 i.seg[i.mem_operands] = &ds;
3503 i.seg[i.mem_operands] = &fs;
3506 i.seg[i.mem_operands] = &gs;
3510 /* Skip the ':' and whitespace. */
3512 if (is_space_char (*op_string))
3515 if (!is_digit_char (*op_string)
3516 && !is_identifier_char (*op_string)
3517 && *op_string != '('
3518 && *op_string != ABSOLUTE_PREFIX)
3520 as_bad (_("bad memory operand `%s'"), op_string);
3523 /* Handle case of %es:*foo. */
3524 if (*op_string == ABSOLUTE_PREFIX)
3527 if (is_space_char (*op_string))
3529 i.types[this_operand] |= JumpAbsolute;
3531 goto do_memory_reference;
3535 as_bad (_("junk `%s' after register"), op_string);
3538 i.types[this_operand] |= r->reg_type & ~BaseIndex;
3539 i.op[this_operand].regs = r;
3542 else if (*op_string == REGISTER_PREFIX)
3544 as_bad (_("bad register name `%s'"), op_string);
3547 else if (*op_string == IMMEDIATE_PREFIX)
3548 { /* ... or an immediate */
3550 if (i.types[this_operand] & JumpAbsolute)
3552 as_bad (_("immediate operand illegal with absolute jump"));
3555 if (!i386_immediate (op_string))
3558 else if (is_digit_char (*op_string)
3559 || is_identifier_char (*op_string)
3560 || *op_string == '(' )
3562 /* This is a memory reference of some sort. */
3565 /* Start and end of displacement string expression (if found). */
3566 char *displacement_string_start;
3567 char *displacement_string_end;
3569 do_memory_reference:
3570 if ((i.mem_operands == 1
3571 && (current_templates->start->opcode_modifier & IsString) == 0)
3572 || i.mem_operands == 2)
3574 as_bad (_("too many memory references for `%s'"),
3575 current_templates->start->name);
3579 /* Check for base index form. We detect the base index form by
3580 looking for an ')' at the end of the operand, searching
3581 for the '(' matching it, and finding a REGISTER_PREFIX or ','
3583 base_string = op_string + strlen (op_string);
3586 if (is_space_char (*base_string))
3589 /* If we only have a displacement, set-up for it to be parsed later. */
3590 displacement_string_start = op_string;
3591 displacement_string_end = base_string + 1;
3593 if (*base_string == ')')
3596 unsigned int parens_balanced = 1;
3597 /* We've already checked that the number of left & right ()'s are
3598 equal, so this loop will not be infinite. */
3602 if (*base_string == ')')
3604 if (*base_string == '(')
3607 while (parens_balanced);
3609 temp_string = base_string;
3611 /* Skip past '(' and whitespace. */
3613 if (is_space_char (*base_string))
3616 if (*base_string == ','
3617 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3618 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
3620 displacement_string_end = temp_string;
3622 i.types[this_operand] |= BaseIndex;
3626 base_string = end_op;
3627 if (is_space_char (*base_string))
3631 /* There may be an index reg or scale factor here. */
3632 if (*base_string == ',')
3635 if (is_space_char (*base_string))
3638 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
3639 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
3641 base_string = end_op;
3642 if (is_space_char (*base_string))
3644 if (*base_string == ',')
3647 if (is_space_char (*base_string))
3650 else if (*base_string != ')' )
3652 as_bad (_("expecting `,' or `)' after index register in `%s'"),
3657 else if (*base_string == REGISTER_PREFIX)
3659 as_bad (_("bad register name `%s'"), base_string);
3663 /* Check for scale factor. */
3664 if (isdigit ((unsigned char) *base_string))
3666 if (!i386_scale (base_string))
3670 if (is_space_char (*base_string))
3672 if (*base_string != ')')
3674 as_bad (_("expecting `)' after scale factor in `%s'"),
3679 else if (!i.index_reg)
3681 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
3686 else if (*base_string != ')')
3688 as_bad (_("expecting `,' or `)' after base register in `%s'"),
3693 else if (*base_string == REGISTER_PREFIX)
3695 as_bad (_("bad register name `%s'"), base_string);
3700 /* If there's an expression beginning the operand, parse it,
3701 assuming displacement_string_start and
3702 displacement_string_end are meaningful. */
3703 if (displacement_string_start != displacement_string_end)
3705 if (!i386_displacement (displacement_string_start,
3706 displacement_string_end))
3710 /* Special case for (%dx) while doing input/output op. */
3712 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
3714 && i.log2_scale_factor == 0
3715 && i.seg[i.mem_operands] == 0
3716 && (i.types[this_operand] & Disp) == 0)
3718 i.types[this_operand] = InOutPortReg;
3722 if (i386_index_check (operand_string) == 0)
3727 { /* it's not a memory operand; argh! */
3728 as_bad (_("invalid char %s beginning operand %d `%s'"),
3729 output_invalid (*op_string),
3734 return 1; /* normal return */
3738 * md_estimate_size_before_relax()
3740 * Called just before relax().
3741 * Any symbol that is now undefined will not become defined.
3742 * Return the correct fr_subtype in the frag.
3743 * Return the initial "guess for fr_var" to caller.
3744 * The guess for fr_var is ACTUALLY the growth beyond fr_fix.
3745 * Whatever we do to grow fr_fix or fr_var contributes to our returned value.
3746 * Although it may not be explicit in the frag, pretend fr_var starts with a
3750 md_estimate_size_before_relax (fragP, segment)
3751 register fragS *fragP;
3752 register segT segment;
3754 register unsigned char *opcode;
3755 register int old_fr_fix;
3757 old_fr_fix = fragP->fr_fix;
3758 opcode = (unsigned char *) fragP->fr_opcode;
3759 /* We've already got fragP->fr_subtype right; all we have to do is
3760 check for un-relaxable symbols. */
3761 if (S_GET_SEGMENT (fragP->fr_symbol) != segment)
3763 /* symbol is undefined in this segment */
3764 int code16 = fragP->fr_subtype & CODE16;
3765 int size = code16 ? 2 : 4;
3766 #ifdef BFD_ASSEMBLER
3767 enum bfd_reloc_code_real reloc_type;
3772 if (GOT_symbol /* Not quite right - we should switch on presence of
3773 @PLT, but I cannot see how to get to that from
3774 here. We should have done this in md_assemble to
3775 really get it right all of the time, but I think it
3776 does not matter that much, as this will be right
3777 most of the time. ERY */
3778 && S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)
3779 reloc_type = BFD_RELOC_386_PLT32;
3781 reloc_type = BFD_RELOC_16_PCREL;
3783 reloc_type = BFD_RELOC_32_PCREL;
3787 case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */
3788 opcode[0] = 0xe9; /* dword disp jmp */
3789 fragP->fr_fix += size;
3790 fix_new (fragP, old_fr_fix, size,
3792 fragP->fr_offset, 1,
3797 /* This changes the byte-displacement jump 0x7N
3798 to the dword-displacement jump 0x0f,0x8N. */
3799 opcode[1] = opcode[0] + 0x10;
3800 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3801 fragP->fr_fix += 1 + size; /* we've added an opcode byte */
3802 fix_new (fragP, old_fr_fix + 1, size,
3804 fragP->fr_offset, 1,
3810 return (fragP->fr_var + fragP->fr_fix - old_fr_fix);
3811 } /* md_estimate_size_before_relax() */
3814 * md_convert_frag();
3816 * Called after relax() is finished.
3817 * In: Address of frag.
3818 * fr_type == rs_machine_dependent.
3819 * fr_subtype is what the address relaxed to.
3821 * Out: Any fixSs and constants are set up.
3822 * Caller will turn frag into a ".space 0".
3824 #ifndef BFD_ASSEMBLER
3826 md_convert_frag (headers, sec, fragP)
3827 object_headers *headers ATTRIBUTE_UNUSED;
3828 segT sec ATTRIBUTE_UNUSED;
3829 register fragS *fragP;
3832 md_convert_frag (abfd, sec, fragP)
3833 bfd *abfd ATTRIBUTE_UNUSED;
3834 segT sec ATTRIBUTE_UNUSED;
3835 register fragS *fragP;
3838 register unsigned char *opcode;
3839 unsigned char *where_to_put_displacement = NULL;
3840 offsetT target_address;
3841 offsetT opcode_address;
3842 unsigned int extension = 0;
3843 offsetT displacement_from_opcode_start;
3845 opcode = (unsigned char *) fragP->fr_opcode;
3847 /* Address we want to reach in file space. */
3848 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
3849 #ifdef BFD_ASSEMBLER /* not needed otherwise? */
3850 target_address += symbol_get_frag (fragP->fr_symbol)->fr_address;
3853 /* Address opcode resides at in file space. */
3854 opcode_address = fragP->fr_address + fragP->fr_fix;
3856 /* Displacement from opcode start to fill into instruction. */
3857 displacement_from_opcode_start = target_address - opcode_address;
3859 switch (fragP->fr_subtype)
3861 case ENCODE_RELAX_STATE (COND_JUMP, SMALL):
3862 case ENCODE_RELAX_STATE (COND_JUMP, SMALL16):
3863 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL):
3864 case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16):
3865 /* don't have to change opcode */
3866 extension = 1; /* 1 opcode + 1 displacement */
3867 where_to_put_displacement = &opcode[1];
3870 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
3871 extension = 5; /* 2 opcode + 4 displacement */
3872 opcode[1] = opcode[0] + 0x10;
3873 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3874 where_to_put_displacement = &opcode[2];
3877 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
3878 extension = 4; /* 1 opcode + 4 displacement */
3880 where_to_put_displacement = &opcode[1];
3883 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
3884 extension = 3; /* 2 opcode + 2 displacement */
3885 opcode[1] = opcode[0] + 0x10;
3886 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
3887 where_to_put_displacement = &opcode[2];
3890 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
3891 extension = 2; /* 1 opcode + 2 displacement */
3893 where_to_put_displacement = &opcode[1];
3897 BAD_CASE (fragP->fr_subtype);
3900 /* now put displacement after opcode */
3901 md_number_to_chars ((char *) where_to_put_displacement,
3902 (valueT) (displacement_from_opcode_start - extension),
3903 SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
3904 fragP->fr_fix += extension;
3908 int md_short_jump_size = 2; /* size of byte displacement jmp */
3909 int md_long_jump_size = 5; /* size of dword displacement jmp */
3910 const int md_reloc_size = 8; /* Size of relocation record */
3913 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
3915 addressT from_addr, to_addr;
3916 fragS *frag ATTRIBUTE_UNUSED;
3917 symbolS *to_symbol ATTRIBUTE_UNUSED;
3921 offset = to_addr - (from_addr + 2);
3922 md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */
3923 md_number_to_chars (ptr + 1, (valueT) offset, 1);
3927 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
3929 addressT from_addr, to_addr;
3935 if (flag_do_long_jump)
3937 offset = to_addr - S_GET_VALUE (to_symbol);
3938 md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */
3939 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3940 fix_new (frag, (ptr + 1) - frag->fr_literal, 4,
3941 to_symbol, (offsetT) 0, 0, BFD_RELOC_32);
3945 offset = to_addr - (from_addr + 5);
3946 md_number_to_chars (ptr, (valueT) 0xe9, 1);
3947 md_number_to_chars (ptr + 1, (valueT) offset, 4);
3951 /* Apply a fixup (fixS) to segment data, once it has been determined
3952 by our caller that we have all the info we need to fix it up.
3954 On the 386, immediates, displacements, and data pointers are all in
3955 the same (little-endian) format, so we don't need to care about which
3959 md_apply_fix3 (fixP, valp, seg)
3960 fixS *fixP; /* The fix we're to put in. */
3961 valueT *valp; /* Pointer to the value of the bits. */
3962 segT seg ATTRIBUTE_UNUSED; /* Segment fix is from. */
3964 register char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
3965 valueT value = *valp;
3967 #if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
3970 switch (fixP->fx_r_type)
3976 fixP->fx_r_type = BFD_RELOC_32_PCREL;
3979 fixP->fx_r_type = BFD_RELOC_16_PCREL;
3982 fixP->fx_r_type = BFD_RELOC_8_PCREL;
3987 /* This is a hack. There should be a better way to handle this.
3988 This covers for the fact that bfd_install_relocation will
3989 subtract the current location (for partial_inplace, PC relative
3990 relocations); see more below. */
3991 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
3992 || fixP->fx_r_type == BFD_RELOC_16_PCREL
3993 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
3997 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
3999 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4002 value += fixP->fx_where + fixP->fx_frag->fr_address;
4004 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4005 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4007 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4010 || (symbol_section_p (fixP->fx_addsy)
4011 && fseg != absolute_section))
4012 && ! S_IS_EXTERNAL (fixP->fx_addsy)
4013 && ! S_IS_WEAK (fixP->fx_addsy)
4014 && S_IS_DEFINED (fixP->fx_addsy)
4015 && ! S_IS_COMMON (fixP->fx_addsy))
4017 /* Yes, we add the values in twice. This is because
4018 bfd_perform_relocation subtracts them out again. I think
4019 bfd_perform_relocation is broken, but I don't dare change
4021 value += fixP->fx_where + fixP->fx_frag->fr_address;
4025 #if defined (OBJ_COFF) && defined (TE_PE)
4026 /* For some reason, the PE format does not store a section
4027 address offset for a PC relative symbol. */
4028 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4029 value += md_pcrel_from (fixP);
4030 else if (S_IS_EXTERNAL (fixP->fx_addsy)
4031 || S_IS_WEAK (fixP->fx_addsy))
4033 /* We are generating an external relocation for this defined
4034 symbol. We add the address, because
4035 bfd_install_relocation will subtract it. VALUE already
4036 holds the symbol value, because fixup_segment added it
4037 in. We subtract it out, and then we subtract it out
4038 again because bfd_install_relocation will add it in
4040 value += md_pcrel_from (fixP);
4041 value -= 2 * S_GET_VALUE (fixP->fx_addsy);
4046 else if (fixP->fx_addsy != NULL
4047 && S_IS_DEFINED (fixP->fx_addsy)
4048 && (S_IS_EXTERNAL (fixP->fx_addsy)
4049 || S_IS_WEAK (fixP->fx_addsy)))
4051 /* We are generating an external relocation for this defined
4052 symbol. VALUE already holds the symbol value, and
4053 bfd_install_relocation will add it in again. We don't want
4055 value -= 2 * S_GET_VALUE (fixP->fx_addsy);
4059 /* Fix a few things - the dynamic linker expects certain values here,
4060 and we must not dissappoint it. */
4061 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4062 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4064 switch (fixP->fx_r_type) {
4065 case BFD_RELOC_386_PLT32:
4066 /* Make the jump instruction point to the address of the operand. At
4067 runtime we merely add the offset to the actual PLT entry. */
4070 case BFD_RELOC_386_GOTPC:
4072 * This is tough to explain. We end up with this one if we have
4073 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4074 * here is to obtain the absolute address of the GOT, and it is strongly
4075 * preferable from a performance point of view to avoid using a runtime
4076 * relocation for this. The actual sequence of instructions often look
4082 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4084 * The call and pop essentially return the absolute address of
4085 * the label .L66 and store it in %ebx. The linker itself will
4086 * ultimately change the first operand of the addl so that %ebx points to
4087 * the GOT, but to keep things simple, the .o file must have this operand
4088 * set so that it generates not the absolute address of .L66, but the
4089 * absolute address of itself. This allows the linker itself simply
4090 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4091 * added in, and the addend of the relocation is stored in the operand
4092 * field for the instruction itself.
4094 * Our job here is to fix the operand so that it would add the correct
4095 * offset so that %ebx would point to itself. The thing that is tricky is
4096 * that .-.L66 will point to the beginning of the instruction, so we need
4097 * to further modify the operand so that it will point to itself.
4098 * There are other cases where you have something like:
4100 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4102 * and here no correction would be required. Internally in the assembler
4103 * we treat operands of this form as not being pcrel since the '.' is
4104 * explicitly mentioned, and I wonder whether it would simplify matters
4105 * to do it this way. Who knows. In earlier versions of the PIC patches,
4106 * the pcrel_adjust field was used to store the correction, but since the
4107 * expression is not pcrel, I felt it would be confusing to do it this way.
4111 case BFD_RELOC_386_GOT32:
4112 value = 0; /* Fully resolved at runtime. No addend. */
4114 case BFD_RELOC_386_GOTOFF:
4117 case BFD_RELOC_VTABLE_INHERIT:
4118 case BFD_RELOC_VTABLE_ENTRY:
4125 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4127 #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
4128 md_number_to_chars (p, value, fixP->fx_size);
4134 #define MAX_LITTLENUMS 6
4136 /* Turn the string pointed to by litP into a floating point constant of type
4137 type, and emit the appropriate bytes. The number of LITTLENUMS emitted
4138 is stored in *sizeP . An error message is returned, or NULL on OK. */
4140 md_atof (type, litP, sizeP)
4146 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4147 LITTLENUM_TYPE *wordP;
4169 return _("Bad call to md_atof ()");
4171 t = atof_ieee (input_line_pointer, type, words);
4173 input_line_pointer = t;
4175 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4176 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4177 the bigendian 386. */
4178 for (wordP = words + prec - 1; prec--;)
4180 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4181 litP += sizeof (LITTLENUM_TYPE);
4186 char output_invalid_buf[8];
4193 sprintf (output_invalid_buf, "'%c'", c);
4195 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4196 return output_invalid_buf;
4200 /* REG_STRING starts *before* REGISTER_PREFIX. */
4202 static const reg_entry *
4203 parse_register (reg_string, end_op)
4207 char *s = reg_string;
4209 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4212 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4213 if (*s == REGISTER_PREFIX)
4216 if (is_space_char (*s))
4220 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4222 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4223 return (const reg_entry *) NULL;
4229 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4231 /* Handle floating point regs, allowing spaces in the (i) part. */
4232 if (r == i386_regtab /* %st is first entry of table */)
4234 if (is_space_char (*s))
4239 if (is_space_char (*s))
4241 if (*s >= '0' && *s <= '7')
4243 r = &i386_float_regtab[*s - '0'];
4245 if (is_space_char (*s))
4253 /* We have "%st(" then garbage */
4254 return (const reg_entry *) NULL;
4261 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4262 CONST char *md_shortopts = "kmVQ:sq";
4264 CONST char *md_shortopts = "m";
4266 struct option md_longopts[] = {
4267 {NULL, no_argument, NULL, 0}
4269 size_t md_longopts_size = sizeof (md_longopts);
4272 md_parse_option (c, arg)
4274 char *arg ATTRIBUTE_UNUSED;
4279 flag_do_long_jump = 1;
4282 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4283 /* -k: Ignore for FreeBSD compatibility. */
4287 /* -V: SVR4 argument to print version ID. */
4289 print_version_id ();
4292 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4293 should be emitted or not. FIXME: Not implemented. */
4298 /* -s: On i386 Solaris, this tells the native assembler to use
4299 .stab instead of .stab.excl. We always use .stab anyhow. */
4303 /* -q: On i386 Solaris, this tells the native assembler to do
4315 md_show_usage (stream)
4318 fprintf (stream, _("\
4319 -m do long jump\n"));
4320 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4321 fprintf (stream, _("\
4322 -V print assembler version number\n\
4330 #ifdef BFD_ASSEMBLER
4331 #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \
4332 || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \
4333 || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)))
4335 /* Pick the target format to use. */
4338 i386_target_format ()
4340 switch (OUTPUT_FLAVOR)
4342 #ifdef OBJ_MAYBE_AOUT
4343 case bfd_target_aout_flavour:
4344 return AOUT_TARGET_FORMAT;
4346 #ifdef OBJ_MAYBE_COFF
4347 case bfd_target_coff_flavour:
4350 #ifdef OBJ_MAYBE_ELF
4351 case bfd_target_elf_flavour:
4352 return "elf32-i386";
4360 #endif /* OBJ_MAYBE_ more than one */
4361 #endif /* BFD_ASSEMBLER */
4364 md_undefined_symbol (name)
4367 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4368 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4369 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4370 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
4374 if (symbol_find (name))
4375 as_bad (_("GOT already in symbol table"));
4376 GOT_symbol = symbol_new (name, undefined_section,
4377 (valueT) 0, &zero_address_frag);
4384 /* Round up a section size to the appropriate boundary. */
4386 md_section_align (segment, size)
4387 segT segment ATTRIBUTE_UNUSED;
4390 #ifdef BFD_ASSEMBLER
4391 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4392 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4394 /* For a.out, force the section size to be aligned. If we don't do
4395 this, BFD will align it for us, but it will not write out the
4396 final bytes of the section. This may be a bug in BFD, but it is
4397 easier to fix it here since that is how the other a.out targets
4401 align = bfd_get_section_alignment (stdoutput, segment);
4402 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4410 /* On the i386, PC-relative offsets are relative to the start of the
4411 next instruction. That is, the address of the offset, plus its
4412 size, since the offset is always the last part of the insn. */
4415 md_pcrel_from (fixP)
4418 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
4425 int ignore ATTRIBUTE_UNUSED;
4429 temp = get_absolute_expression ();
4430 subseg_set (bss_section, (subsegT) temp);
4431 demand_empty_rest_of_line ();
4437 #ifdef BFD_ASSEMBLER
4440 i386_validate_fix (fixp)
4443 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
4445 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
4451 tc_gen_reloc (section, fixp)
4452 asection *section ATTRIBUTE_UNUSED;
4456 bfd_reloc_code_real_type code;
4458 switch (fixp->fx_r_type)
4460 case BFD_RELOC_386_PLT32:
4461 case BFD_RELOC_386_GOT32:
4462 case BFD_RELOC_386_GOTOFF:
4463 case BFD_RELOC_386_GOTPC:
4465 case BFD_RELOC_VTABLE_ENTRY:
4466 case BFD_RELOC_VTABLE_INHERIT:
4467 code = fixp->fx_r_type;
4472 switch (fixp->fx_size)
4475 as_bad (_("can not do %d byte pc-relative relocation"),
4477 code = BFD_RELOC_32_PCREL;
4479 case 1: code = BFD_RELOC_8_PCREL; break;
4480 case 2: code = BFD_RELOC_16_PCREL; break;
4481 case 4: code = BFD_RELOC_32_PCREL; break;
4486 switch (fixp->fx_size)
4489 as_bad (_("can not do %d byte relocation"), fixp->fx_size);
4490 code = BFD_RELOC_32;
4492 case 1: code = BFD_RELOC_8; break;
4493 case 2: code = BFD_RELOC_16; break;
4494 case 4: code = BFD_RELOC_32; break;
4500 if (code == BFD_RELOC_32
4502 && fixp->fx_addsy == GOT_symbol)
4503 code = BFD_RELOC_386_GOTPC;
4505 rel = (arelent *) xmalloc (sizeof (arelent));
4506 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
4507 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
4509 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
4510 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
4511 vtable entry to be used in the relocation's section offset. */
4512 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4513 rel->address = fixp->fx_offset;
4516 rel->addend = fixp->fx_addnumber;
4520 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
4521 if (rel->howto == NULL)
4523 as_bad_where (fixp->fx_file, fixp->fx_line,
4524 _("cannot represent relocation type %s"),
4525 bfd_get_reloc_code_name (code));
4526 /* Set howto to a garbage value so that we can keep going. */
4527 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
4528 assert (rel->howto != NULL);
4534 #else /* ! BFD_ASSEMBLER */
4536 #if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
4538 tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4541 relax_addressT segment_address_in_file;
4544 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4545 * Out: GNU LD relocation length code: 0, 1, or 2.
4548 static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4551 know (fixP->fx_addsy != NULL);
4553 md_number_to_chars (where,
4554 (valueT) (fixP->fx_frag->fr_address
4555 + fixP->fx_where - segment_address_in_file),
4558 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4559 ? S_GET_TYPE (fixP->fx_addsy)
4560 : fixP->fx_addsy->sy_number);
4562 where[6] = (r_symbolnum >> 16) & 0x0ff;
4563 where[5] = (r_symbolnum >> 8) & 0x0ff;
4564 where[4] = r_symbolnum & 0x0ff;
4565 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
4566 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
4567 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
4570 #endif /* OBJ_AOUT or OBJ_BOUT */
4572 #if defined (I386COFF)
4575 tc_coff_fix2rtype (fixP)
4578 if (fixP->fx_r_type == R_IMAGEBASE)
4581 return (fixP->fx_pcrel ?
4582 (fixP->fx_size == 1 ? R_PCRBYTE :
4583 fixP->fx_size == 2 ? R_PCRWORD :
4585 (fixP->fx_size == 1 ? R_RELBYTE :
4586 fixP->fx_size == 2 ? R_RELWORD :
4591 tc_coff_sizemachdep (frag)
4595 return (frag->fr_next->fr_address - frag->fr_address);
4600 #endif /* I386COFF */
4602 #endif /* ! BFD_ASSEMBLER */
4604 /* end of tc-i386.c */