1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
139 /* Used to turn off indicated flags. */
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
148 static void update_code_flag (int, int);
149 static void set_code_flag (int);
150 static void set_16bit_gcc_code_flag (int);
151 static void set_intel_syntax (int);
152 static void set_intel_mnemonic (int);
153 static void set_allow_index_reg (int);
154 static void set_check (int);
155 static void set_cpu_arch (int);
157 static void pe_directive_secrel (int);
159 static void signed_cons (int);
160 static char *output_invalid (int c);
161 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
163 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
165 static int i386_att_operand (char *);
166 static int i386_intel_operand (char *, int);
167 static int i386_intel_simplify (expressionS *);
168 static int i386_intel_parse_name (const char *, expressionS *);
169 static const reg_entry *parse_register (char *, char **);
170 static char *parse_insn (char *, char *);
171 static char *parse_operands (char *, const char *);
172 static void swap_operands (void);
173 static void swap_2_operands (int, int);
174 static void optimize_imm (void);
175 static void optimize_disp (void);
176 static const insn_template *match_template (char);
177 static int check_string (void);
178 static int process_suffix (void);
179 static int check_byte_reg (void);
180 static int check_long_reg (void);
181 static int check_qword_reg (void);
182 static int check_word_reg (void);
183 static int finalize_imm (void);
184 static int process_operands (void);
185 static const seg_entry *build_modrm_byte (void);
186 static void output_insn (void);
187 static void output_imm (fragS *, offsetT);
188 static void output_disp (fragS *, offsetT);
190 static void s_bss (int);
192 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193 static void handle_large_common (int small ATTRIBUTE_UNUSED);
196 static const char *default_arch = DEFAULT_ARCH;
198 /* This struct describes rounding control and SAE in the instruction. */
212 static struct RC_Operation rc_op;
214 /* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217 struct Mask_Operation
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
225 static struct Mask_Operation mask_op;
227 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
229 struct Broadcast_Operation
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
234 /* Index of broadcasted operand. */
238 static struct Broadcast_Operation broadcast_op;
243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
250 /* 'md_assemble ()' gathers together information and puts it into a
257 const reg_entry *regs;
262 operand_size_mismatch,
263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
269 unsupported_with_intel_mnemonic,
272 invalid_vsib_address,
273 invalid_vector_register_set,
274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
279 mask_not_on_destination,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
288 /* TM holds the template for the insn were currently assembling. */
291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
295 /* OPERANDS gives the number of given operands. */
296 unsigned int operands;
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303 /* TYPES [i] is the type (see above #defines) which tells us how to
304 use OP[i] for the corresponding operand. */
305 i386_operand_type types[MAX_OPERANDS];
307 /* Displacement expression, immediate expression, or register for each
309 union i386_op op[MAX_OPERANDS];
311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313 #define Operand_PCrel 1
315 /* Relocation type for operand */
316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
324 /* SEG gives the seg_entries of this insn. They are zero unless
325 explicit segment overrides are given. */
326 const seg_entry *seg[2];
328 /* Copied first memory operand string, for re-checking. */
331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
336 /* RM and SIB are the modrm byte and the sib byte where the
337 addressing modes of this insn are encoded. */
344 /* Masking attributes. */
345 struct Mask_Operation *mask;
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
356 /* Prefer load or store in encoding. */
359 dir_encoding_default = 0,
364 /* Prefer 8bit or 32bit displacement in encoding. */
367 disp_encoding_default = 0,
372 /* How to encode vector instructions. */
375 vex_encoding_default = 0,
382 const char *rep_prefix;
385 const char *hle_prefix;
387 /* Have BND prefix. */
388 const char *bnd_prefix;
390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
394 enum i386_error error;
397 typedef struct _i386_insn i386_insn;
399 /* Link RC type with corresponding string, that'll be looked for in
408 static const struct RC_name RC_NamesTable[] =
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
417 /* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
419 const char extra_symbol_chars[] = "*%-([{}"
428 #if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
430 && !defined (TE_GNU) \
431 && !defined (TE_LINUX) \
432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
434 && !defined (TE_FreeBSD) \
435 && !defined (TE_DragonFly) \
436 && !defined (TE_NetBSD)))
437 /* This array holds the chars that always start a comment. If the
438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440 const char *i386_comment_chars = "#/";
441 #define SVR4_COMMENT_CHARS 1
442 #define PREFIX_SEPARATOR '\\'
445 const char *i386_comment_chars = "#";
446 #define PREFIX_SEPARATOR '/'
449 /* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
453 first line of the input file. This is because the compiler outputs
454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
456 '/' isn't otherwise defined. */
457 const char line_comment_chars[] = "#/";
459 const char line_separator_chars[] = ";";
461 /* Chars that can be used to separate mant from exp in floating point
463 const char EXP_CHARS[] = "eE";
465 /* Chars that mean this number is a floating point constant
468 const char FLT_CHARS[] = "fFdDxX";
470 /* Tables for lexical analysis. */
471 static char mnemonic_chars[256];
472 static char register_chars[256];
473 static char operand_chars[256];
474 static char identifier_chars[256];
475 static char digit_chars[256];
477 /* Lexical macros. */
478 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479 #define is_operand_char(x) (operand_chars[(unsigned char) x])
480 #define is_register_char(x) (register_chars[(unsigned char) x])
481 #define is_space_char(x) ((x) == ' ')
482 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483 #define is_digit_char(x) (digit_chars[(unsigned char) x])
485 /* All non-digit non-letter characters that may occur in an operand. */
486 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488 /* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
491 assembler instruction). */
492 static char save_stack[32];
493 static char *save_stack_p;
494 #define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496 #define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
499 /* The instruction we're assembling. */
502 /* Possible templates for current insn. */
503 static const templates *current_templates;
505 /* Per instruction expressionS buffers: max displacements & immediates. */
506 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
509 /* Current operand we are working on. */
510 static int this_operand = -1;
512 /* We support four different modes. FLAG_CODE variable is used to distinguish
520 static enum flag_code flag_code;
521 static unsigned int object_64bit;
522 static unsigned int disallow_64bit_reloc;
523 static int use_rela_relocations = 0;
525 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529 /* The ELF ABI to use. */
537 static enum x86_elf_abi x86_elf_abi = I386_ABI;
540 #if defined (TE_PE) || defined (TE_PEP)
541 /* Use big object file format. */
542 static int use_big_obj = 0;
545 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546 /* 1 if generating code for a shared library. */
547 static int shared = 0;
550 /* 1 for intel syntax,
552 static int intel_syntax = 0;
554 /* 1 for Intel64 ISA,
558 /* 1 for intel mnemonic,
559 0 if att mnemonic. */
560 static int intel_mnemonic = !SYSV386_COMPAT;
562 /* 1 if support old (<= 2.8.1) versions of gcc. */
563 static int old_gcc = OLDGCC_COMPAT;
565 /* 1 if pseudo registers are permitted. */
566 static int allow_pseudo_reg = 0;
568 /* 1 if register prefix % not required. */
569 static int allow_naked_reg = 0;
571 /* 1 if the assembler should add BND prefix for all control-transferring
572 instructions supporting it, even if this prefix wasn't specified
574 static int add_bnd_prefix = 0;
576 /* 1 if pseudo index register, eiz/riz, is allowed . */
577 static int allow_index_reg = 0;
579 /* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581 static int omit_lock_prefix = 0;
583 /* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585 static int avoid_fence = 0;
587 /* 1 if the assembler should generate relax relocations. */
589 static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592 static enum check_kind
598 sse_check, operand_check = check_warning;
600 /* Register prefix used for error message. */
601 static const char *register_prefix = "%";
603 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606 static char stackop_size = '\0';
608 /* Non-zero to optimize code alignment. */
609 int optimize_align_code = 1;
611 /* Non-zero to quieten some warnings. */
612 static int quiet_warnings = 0;
615 static const char *cpu_arch_name = NULL;
616 static char *cpu_sub_arch_name = NULL;
618 /* CPU feature flags. */
619 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621 /* If we have selected a cpu we are generating instructions for. */
622 static int cpu_arch_tune_set = 0;
624 /* Cpu we are generating instructions for. */
625 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
627 /* CPU feature flags of cpu we are generating instructions for. */
628 static i386_cpu_flags cpu_arch_tune_flags;
630 /* CPU instruction set architecture used. */
631 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
633 /* CPU feature flags of instruction set architecture used. */
634 i386_cpu_flags cpu_arch_isa_flags;
636 /* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638 static unsigned int no_cond_jump_promotion = 0;
640 /* Encode SSE instructions with VEX prefix. */
641 static unsigned int sse2avx;
643 /* Encode scalar AVX instructions with specific vector length. */
650 /* Encode scalar EVEX LIG instructions with specific vector length. */
658 /* Encode EVEX WIG instructions with specific evex.w. */
665 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
666 static enum rc_type evexrcig = rne;
668 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
669 static symbolS *GOT_symbol;
671 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
672 unsigned int x86_dwarf2_return_column;
674 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675 int x86_cie_data_alignment;
677 /* Interface to relax_segment.
678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
683 #define UNCOND_JUMP 0
685 #define COND_JUMP86 2
690 #define SMALL16 (SMALL | CODE16)
692 #define BIG16 (BIG | CODE16)
696 #define INLINE __inline__
702 #define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704 #define TYPE_FROM_RELAX_STATE(s) \
706 #define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
709 /* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
717 const relax_typeS md_relax_table[] =
720 1) most positive reach of this state,
721 2) most negative reach of this state,
722 3) how many bytes this mode will have in the variable part of the frag
723 4) which index into the table to try if we can't fit into this one. */
725 /* UNCOND_JUMP states. */
726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
741 /* word conditionals add 3 bytes to frag:
742 1 extra opcode byte, 2 displacement bytes. */
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
756 static const arch_entry cpu_arch[] =
758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
761 CPU_GENERIC32_FLAGS, 0 },
762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
763 CPU_GENERIC64_FLAGS, 0 },
764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
781 CPU_PENTIUMPRO_FLAGS, 0 },
782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
791 CPU_NOCONA_FLAGS, 0 },
792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
797 CPU_CORE2_FLAGS, 1 },
798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
799 CPU_CORE2_FLAGS, 0 },
800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
801 CPU_COREI7_FLAGS, 0 },
802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
807 CPU_IAMCU_FLAGS, 0 },
808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
813 CPU_ATHLON_FLAGS, 0 },
814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
821 CPU_AMDFAM10_FLAGS, 0 },
822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
823 CPU_BDVER1_FLAGS, 0 },
824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
825 CPU_BDVER2_FLAGS, 0 },
826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
827 CPU_BDVER3_FLAGS, 0 },
828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
829 CPU_BDVER4_FLAGS, 0 },
830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
831 CPU_ZNVER1_FLAGS, 0 },
832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
833 CPU_BTVER1_FLAGS, 0 },
834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
835 CPU_BTVER2_FLAGS, 0 },
836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
853 CPU_SSSE3_FLAGS, 0 },
854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
855 CPU_SSE4_1_FLAGS, 0 },
856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
857 CPU_SSE4_2_FLAGS, 0 },
858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
859 CPU_SSE4_2_FLAGS, 0 },
860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
865 CPU_AVX512F_FLAGS, 0 },
866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
867 CPU_AVX512CD_FLAGS, 0 },
868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
869 CPU_AVX512ER_FLAGS, 0 },
870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
871 CPU_AVX512PF_FLAGS, 0 },
872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
873 CPU_AVX512DQ_FLAGS, 0 },
874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
875 CPU_AVX512BW_FLAGS, 0 },
876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
877 CPU_AVX512VL_FLAGS, 0 },
878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
881 CPU_VMFUNC_FLAGS, 0 },
882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
885 CPU_XSAVE_FLAGS, 0 },
886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
887 CPU_XSAVEOPT_FLAGS, 0 },
888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
889 CPU_XSAVEC_FLAGS, 0 },
890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
891 CPU_XSAVES_FLAGS, 0 },
892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
895 CPU_PCLMUL_FLAGS, 0 },
896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
897 CPU_PCLMUL_FLAGS, 1 },
898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
899 CPU_FSGSBASE_FLAGS, 0 },
900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
901 CPU_RDRND_FLAGS, 0 },
902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
915 CPU_MOVBE_FLAGS, 0 },
916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
921 CPU_LZCNT_FLAGS, 0 },
922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
927 CPU_INVPCID_FLAGS, 0 },
928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
929 CPU_CLFLUSH_FLAGS, 0 },
930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
933 CPU_SYSCALL_FLAGS, 0 },
934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
935 CPU_RDTSCP_FLAGS, 0 },
936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
937 CPU_3DNOW_FLAGS, 0 },
938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
939 CPU_3DNOWA_FLAGS, 0 },
940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
941 CPU_PADLOCK_FLAGS, 0 },
942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
947 CPU_SSE4A_FLAGS, 0 },
948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
957 CPU_RDSEED_FLAGS, 0 },
958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
959 CPU_PRFCHW_FLAGS, 0 },
960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
967 CPU_CLFLUSHOPT_FLAGS, 0 },
968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
969 CPU_PREFETCHWT1_FLAGS, 0 },
970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
975 CPU_AVX512IFMA_FLAGS, 0 },
976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
977 CPU_AVX512VBMI_FLAGS, 0 },
978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
991 CPU_CLZERO_FLAGS, 0 },
992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
993 CPU_MWAITX_FLAGS, 0 },
994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
995 CPU_OSPKE_FLAGS, 0 },
996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
997 CPU_RDPID_FLAGS, 0 },
998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
1000 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1002 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1003 CPU_SHSTK_FLAGS, 0 },
1004 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1005 CPU_GFNI_FLAGS, 0 },
1006 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1007 CPU_VAES_FLAGS, 0 },
1008 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1009 CPU_VPCLMULQDQ_FLAGS, 0 },
1010 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1011 CPU_WBNOINVD_FLAGS, 0 },
1012 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1013 CPU_PCONFIG_FLAGS, 0 },
1016 static const noarch_entry cpu_noarch[] =
1018 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1019 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1020 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1021 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
1022 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1023 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1024 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1025 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1026 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1027 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1028 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1029 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
1030 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1031 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1036 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1037 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1038 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1039 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1040 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
1041 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
1042 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
1043 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
1044 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
1045 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
1046 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
1047 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1048 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
1052 /* Like s_lcomm_internal in gas/read.c but the alignment string
1053 is allowed to be optional. */
1056 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1063 && *input_line_pointer == ',')
1065 align = parse_align (needs_align - 1);
1067 if (align == (addressT) -1)
1082 bss_alloc (symbolP, size, align);
1087 pe_lcomm (int needs_align)
1089 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1093 const pseudo_typeS md_pseudo_table[] =
1095 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1096 {"align", s_align_bytes, 0},
1098 {"align", s_align_ptwo, 0},
1100 {"arch", set_cpu_arch, 0},
1104 {"lcomm", pe_lcomm, 1},
1106 {"ffloat", float_cons, 'f'},
1107 {"dfloat", float_cons, 'd'},
1108 {"tfloat", float_cons, 'x'},
1110 {"slong", signed_cons, 4},
1111 {"noopt", s_ignore, 0},
1112 {"optim", s_ignore, 0},
1113 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1114 {"code16", set_code_flag, CODE_16BIT},
1115 {"code32", set_code_flag, CODE_32BIT},
1117 {"code64", set_code_flag, CODE_64BIT},
1119 {"intel_syntax", set_intel_syntax, 1},
1120 {"att_syntax", set_intel_syntax, 0},
1121 {"intel_mnemonic", set_intel_mnemonic, 1},
1122 {"att_mnemonic", set_intel_mnemonic, 0},
1123 {"allow_index_reg", set_allow_index_reg, 1},
1124 {"disallow_index_reg", set_allow_index_reg, 0},
1125 {"sse_check", set_check, 0},
1126 {"operand_check", set_check, 1},
1127 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1128 {"largecomm", handle_large_common, 0},
1130 {"file", dwarf2_directive_file, 0},
1131 {"loc", dwarf2_directive_loc, 0},
1132 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1135 {"secrel32", pe_directive_secrel, 0},
1140 /* For interface with expression (). */
1141 extern char *input_line_pointer;
1143 /* Hash table for instruction mnemonic lookup. */
1144 static struct hash_control *op_hash;
1146 /* Hash table for register lookup. */
1147 static struct hash_control *reg_hash;
1150 i386_align_code (fragS *fragP, int count)
1152 /* Various efficient no-op patterns for aligning code labels.
1153 Note: Don't try to assemble the instructions in the comments.
1154 0L and 0w are not legal. */
1155 static const unsigned char f32_1[] =
1157 static const unsigned char f32_2[] =
1158 {0x66,0x90}; /* xchg %ax,%ax */
1159 static const unsigned char f32_3[] =
1160 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1161 static const unsigned char f32_4[] =
1162 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1163 static const unsigned char f32_5[] =
1165 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1166 static const unsigned char f32_6[] =
1167 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1168 static const unsigned char f32_7[] =
1169 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1170 static const unsigned char f32_8[] =
1172 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1173 static const unsigned char f32_9[] =
1174 {0x89,0xf6, /* movl %esi,%esi */
1175 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1176 static const unsigned char f32_10[] =
1177 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1179 static const unsigned char f32_11[] =
1180 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1181 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1182 static const unsigned char f32_12[] =
1183 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1184 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1185 static const unsigned char f32_13[] =
1186 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1187 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1188 static const unsigned char f32_14[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1190 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1191 static const unsigned char f16_3[] =
1192 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1193 static const unsigned char f16_4[] =
1194 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1195 static const unsigned char f16_5[] =
1197 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1198 static const unsigned char f16_6[] =
1199 {0x89,0xf6, /* mov %si,%si */
1200 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1201 static const unsigned char f16_7[] =
1202 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1203 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1204 static const unsigned char f16_8[] =
1205 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1206 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1207 static const unsigned char jump_31[] =
1208 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1209 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1210 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1211 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1212 static const unsigned char *const f32_patt[] = {
1213 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1214 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1216 static const unsigned char *const f16_patt[] = {
1217 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1219 /* nopl (%[re]ax) */
1220 static const unsigned char alt_3[] =
1222 /* nopl 0(%[re]ax) */
1223 static const unsigned char alt_4[] =
1224 {0x0f,0x1f,0x40,0x00};
1225 /* nopl 0(%[re]ax,%[re]ax,1) */
1226 static const unsigned char alt_5[] =
1227 {0x0f,0x1f,0x44,0x00,0x00};
1228 /* nopw 0(%[re]ax,%[re]ax,1) */
1229 static const unsigned char alt_6[] =
1230 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1231 /* nopl 0L(%[re]ax) */
1232 static const unsigned char alt_7[] =
1233 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1234 /* nopl 0L(%[re]ax,%[re]ax,1) */
1235 static const unsigned char alt_8[] =
1236 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1237 /* nopw 0L(%[re]ax,%[re]ax,1) */
1238 static const unsigned char alt_9[] =
1239 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1240 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1241 static const unsigned char alt_10[] =
1242 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1243 static const unsigned char *const alt_patt[] = {
1244 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1248 /* Only align for at least a positive non-zero boundary. */
1249 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1252 /* We need to decide which NOP sequence to use for 32bit and
1253 64bit. When -mtune= is used:
1255 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1256 PROCESSOR_GENERIC32, f32_patt will be used.
1257 2. For the rest, alt_patt will be used.
1259 When -mtune= isn't used, alt_patt will be used if
1260 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1263 When -march= or .arch is used, we can't use anything beyond
1264 cpu_arch_isa_flags. */
1266 if (flag_code == CODE_16BIT)
1270 memcpy (fragP->fr_literal + fragP->fr_fix,
1272 /* Adjust jump offset. */
1273 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1276 memcpy (fragP->fr_literal + fragP->fr_fix,
1277 f16_patt[count - 1], count);
1281 const unsigned char *const *patt = NULL;
1283 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1285 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1286 switch (cpu_arch_tune)
1288 case PROCESSOR_UNKNOWN:
1289 /* We use cpu_arch_isa_flags to check if we SHOULD
1290 optimize with nops. */
1291 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1296 case PROCESSOR_PENTIUM4:
1297 case PROCESSOR_NOCONA:
1298 case PROCESSOR_CORE:
1299 case PROCESSOR_CORE2:
1300 case PROCESSOR_COREI7:
1301 case PROCESSOR_L1OM:
1302 case PROCESSOR_K1OM:
1303 case PROCESSOR_GENERIC64:
1305 case PROCESSOR_ATHLON:
1307 case PROCESSOR_AMDFAM10:
1309 case PROCESSOR_ZNVER:
1313 case PROCESSOR_I386:
1314 case PROCESSOR_I486:
1315 case PROCESSOR_PENTIUM:
1316 case PROCESSOR_PENTIUMPRO:
1317 case PROCESSOR_IAMCU:
1318 case PROCESSOR_GENERIC32:
1325 switch (fragP->tc_frag_data.tune)
1327 case PROCESSOR_UNKNOWN:
1328 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1329 PROCESSOR_UNKNOWN. */
1333 case PROCESSOR_I386:
1334 case PROCESSOR_I486:
1335 case PROCESSOR_PENTIUM:
1336 case PROCESSOR_IAMCU:
1338 case PROCESSOR_ATHLON:
1340 case PROCESSOR_AMDFAM10:
1342 case PROCESSOR_ZNVER:
1344 case PROCESSOR_GENERIC32:
1345 /* We use cpu_arch_isa_flags to check if we CAN optimize
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1352 case PROCESSOR_PENTIUMPRO:
1353 case PROCESSOR_PENTIUM4:
1354 case PROCESSOR_NOCONA:
1355 case PROCESSOR_CORE:
1356 case PROCESSOR_CORE2:
1357 case PROCESSOR_COREI7:
1358 case PROCESSOR_L1OM:
1359 case PROCESSOR_K1OM:
1360 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1365 case PROCESSOR_GENERIC64:
1371 if (patt == f32_patt)
1373 /* If the padding is less than 15 bytes, we use the normal
1374 ones. Otherwise, we use a jump instruction and adjust
1378 /* For 64bit, the limit is 3 bytes. */
1379 if (flag_code == CODE_64BIT
1380 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1385 memcpy (fragP->fr_literal + fragP->fr_fix,
1386 patt[count - 1], count);
1389 memcpy (fragP->fr_literal + fragP->fr_fix,
1391 /* Adjust jump offset. */
1392 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1397 /* Maximum length of an instruction is 10 byte. If the
1398 padding is greater than 10 bytes and we don't use jump,
1399 we have to break it into smaller pieces. */
1400 int padding = count;
1401 while (padding > 10)
1404 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1409 memcpy (fragP->fr_literal + fragP->fr_fix,
1410 patt [padding - 1], padding);
1413 fragP->fr_var = count;
1417 operand_type_all_zero (const union i386_operand_type *x)
1419 switch (ARRAY_SIZE(x->array))
1430 return !x->array[0];
1437 operand_type_set (union i386_operand_type *x, unsigned int v)
1439 switch (ARRAY_SIZE(x->array))
1457 operand_type_equal (const union i386_operand_type *x,
1458 const union i386_operand_type *y)
1460 switch (ARRAY_SIZE(x->array))
1463 if (x->array[2] != y->array[2])
1467 if (x->array[1] != y->array[1])
1471 return x->array[0] == y->array[0];
1479 cpu_flags_all_zero (const union i386_cpu_flags *x)
1481 switch (ARRAY_SIZE(x->array))
1496 return !x->array[0];
1503 cpu_flags_equal (const union i386_cpu_flags *x,
1504 const union i386_cpu_flags *y)
1506 switch (ARRAY_SIZE(x->array))
1509 if (x->array[3] != y->array[3])
1513 if (x->array[2] != y->array[2])
1517 if (x->array[1] != y->array[1])
1521 return x->array[0] == y->array[0];
1529 cpu_flags_check_cpu64 (i386_cpu_flags f)
1531 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1532 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1535 static INLINE i386_cpu_flags
1536 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1538 switch (ARRAY_SIZE (x.array))
1541 x.array [3] &= y.array [3];
1544 x.array [2] &= y.array [2];
1547 x.array [1] &= y.array [1];
1550 x.array [0] &= y.array [0];
1558 static INLINE i386_cpu_flags
1559 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1561 switch (ARRAY_SIZE (x.array))
1564 x.array [3] |= y.array [3];
1567 x.array [2] |= y.array [2];
1570 x.array [1] |= y.array [1];
1573 x.array [0] |= y.array [0];
1581 static INLINE i386_cpu_flags
1582 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1584 switch (ARRAY_SIZE (x.array))
1587 x.array [3] &= ~y.array [3];
1590 x.array [2] &= ~y.array [2];
1593 x.array [1] &= ~y.array [1];
1596 x.array [0] &= ~y.array [0];
1604 #define CPU_FLAGS_ARCH_MATCH 0x1
1605 #define CPU_FLAGS_64BIT_MATCH 0x2
1606 #define CPU_FLAGS_AES_MATCH 0x4
1607 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1608 #define CPU_FLAGS_AVX_MATCH 0x10
1610 #define CPU_FLAGS_32BIT_MATCH \
1611 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1612 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1613 #define CPU_FLAGS_PERFECT_MATCH \
1614 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1616 /* Return CPU flags match bits. */
1619 cpu_flags_match (const insn_template *t)
1621 i386_cpu_flags x = t->cpu_flags;
1622 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1624 x.bitfield.cpu64 = 0;
1625 x.bitfield.cpuno64 = 0;
1627 if (cpu_flags_all_zero (&x))
1629 /* This instruction is available on all archs. */
1630 match |= CPU_FLAGS_32BIT_MATCH;
1634 /* This instruction is available only on some archs. */
1635 i386_cpu_flags cpu = cpu_arch_flags;
1637 cpu = cpu_flags_and (x, cpu);
1638 if (!cpu_flags_all_zero (&cpu))
1640 if (x.bitfield.cpuavx)
1642 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1643 if (cpu.bitfield.cpuavx)
1645 /* Check SSE2AVX. */
1646 if (!t->opcode_modifier.sse2avx|| sse2avx)
1648 match |= (CPU_FLAGS_ARCH_MATCH
1649 | CPU_FLAGS_AVX_MATCH);
1651 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1652 match |= CPU_FLAGS_AES_MATCH;
1654 if (!x.bitfield.cpupclmul
1655 || cpu.bitfield.cpupclmul)
1656 match |= CPU_FLAGS_PCLMUL_MATCH;
1660 match |= CPU_FLAGS_ARCH_MATCH;
1662 else if (x.bitfield.cpuavx512vl)
1664 /* Match AVX512VL. */
1665 if (cpu.bitfield.cpuavx512vl)
1667 /* Need another match. */
1668 cpu.bitfield.cpuavx512vl = 0;
1669 if (!cpu_flags_all_zero (&cpu))
1670 match |= CPU_FLAGS_32BIT_MATCH;
1672 match |= CPU_FLAGS_ARCH_MATCH;
1675 match |= CPU_FLAGS_ARCH_MATCH;
1678 match |= CPU_FLAGS_32BIT_MATCH;
1684 static INLINE i386_operand_type
1685 operand_type_and (i386_operand_type x, i386_operand_type y)
1687 switch (ARRAY_SIZE (x.array))
1690 x.array [2] &= y.array [2];
1693 x.array [1] &= y.array [1];
1696 x.array [0] &= y.array [0];
1704 static INLINE i386_operand_type
1705 operand_type_or (i386_operand_type x, i386_operand_type y)
1707 switch (ARRAY_SIZE (x.array))
1710 x.array [2] |= y.array [2];
1713 x.array [1] |= y.array [1];
1716 x.array [0] |= y.array [0];
1724 static INLINE i386_operand_type
1725 operand_type_xor (i386_operand_type x, i386_operand_type y)
1727 switch (ARRAY_SIZE (x.array))
1730 x.array [2] ^= y.array [2];
1733 x.array [1] ^= y.array [1];
1736 x.array [0] ^= y.array [0];
1744 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1745 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1746 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1747 static const i386_operand_type inoutportreg
1748 = OPERAND_TYPE_INOUTPORTREG;
1749 static const i386_operand_type reg16_inoutportreg
1750 = OPERAND_TYPE_REG16_INOUTPORTREG;
1751 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1752 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1753 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1754 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1755 static const i386_operand_type anydisp
1756 = OPERAND_TYPE_ANYDISP;
1757 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1758 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1759 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1760 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1761 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1762 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1763 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1764 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1765 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1766 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1767 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1768 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1779 operand_type_check (i386_operand_type t, enum operand_type c)
1784 return t.bitfield.reg;
1787 return (t.bitfield.imm8
1791 || t.bitfield.imm32s
1792 || t.bitfield.imm64);
1795 return (t.bitfield.disp8
1796 || t.bitfield.disp16
1797 || t.bitfield.disp32
1798 || t.bitfield.disp32s
1799 || t.bitfield.disp64);
1802 return (t.bitfield.disp8
1803 || t.bitfield.disp16
1804 || t.bitfield.disp32
1805 || t.bitfield.disp32s
1806 || t.bitfield.disp64
1807 || t.bitfield.baseindex);
1816 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
1817 operand J for instruction template T. */
1820 match_reg_size (const insn_template *t, unsigned int j)
1822 return !((i.types[j].bitfield.byte
1823 && !t->operand_types[j].bitfield.byte)
1824 || (i.types[j].bitfield.word
1825 && !t->operand_types[j].bitfield.word)
1826 || (i.types[j].bitfield.dword
1827 && !t->operand_types[j].bitfield.dword)
1828 || (i.types[j].bitfield.qword
1829 && !t->operand_types[j].bitfield.qword)
1830 || (i.types[j].bitfield.tbyte
1831 && !t->operand_types[j].bitfield.tbyte));
1834 /* Return 1 if there is no conflict in SIMD register on
1835 operand J for instruction template T. */
1838 match_simd_size (const insn_template *t, unsigned int j)
1840 return !((i.types[j].bitfield.xmmword
1841 && !t->operand_types[j].bitfield.xmmword)
1842 || (i.types[j].bitfield.ymmword
1843 && !t->operand_types[j].bitfield.ymmword)
1844 || (i.types[j].bitfield.zmmword
1845 && !t->operand_types[j].bitfield.zmmword));
1848 /* Return 1 if there is no conflict in any size on operand J for
1849 instruction template T. */
1852 match_mem_size (const insn_template *t, unsigned int j)
1854 return (match_reg_size (t, j)
1855 && !((i.types[j].bitfield.unspecified
1857 && !t->operand_types[j].bitfield.unspecified)
1858 || (i.types[j].bitfield.fword
1859 && !t->operand_types[j].bitfield.fword)
1860 /* For scalar opcode templates to allow register and memory
1861 operands at the same time, some special casing is needed
1863 || ((t->operand_types[j].bitfield.regsimd
1864 && !t->opcode_modifier.broadcast
1865 && (t->operand_types[j].bitfield.dword
1866 || t->operand_types[j].bitfield.qword))
1867 ? (i.types[j].bitfield.xmmword
1868 || i.types[j].bitfield.ymmword
1869 || i.types[j].bitfield.zmmword)
1870 : !match_simd_size(t, j))));
1873 /* Return 1 if there is no size conflict on any operands for
1874 instruction template T. */
1877 operand_size_match (const insn_template *t)
1882 /* Don't check jump instructions. */
1883 if (t->opcode_modifier.jump
1884 || t->opcode_modifier.jumpbyte
1885 || t->opcode_modifier.jumpdword
1886 || t->opcode_modifier.jumpintersegment)
1889 /* Check memory and accumulator operand size. */
1890 for (j = 0; j < i.operands; j++)
1892 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1893 && t->operand_types[j].bitfield.anysize)
1896 if (t->operand_types[j].bitfield.reg
1897 && !match_reg_size (t, j))
1903 if (t->operand_types[j].bitfield.regsimd
1904 && !match_simd_size (t, j))
1910 if (t->operand_types[j].bitfield.acc
1911 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1917 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1926 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1929 i.error = operand_size_mismatch;
1933 /* Check reverse. */
1934 gas_assert (i.operands == 2);
1937 for (j = 0; j < 2; j++)
1939 if ((t->operand_types[j].bitfield.reg
1940 || t->operand_types[j].bitfield.acc)
1941 && !match_reg_size (t, j ? 0 : 1))
1944 if (i.types[j].bitfield.mem
1945 && !match_mem_size (t, j ? 0 : 1))
1953 operand_type_match (i386_operand_type overlap,
1954 i386_operand_type given)
1956 i386_operand_type temp = overlap;
1958 temp.bitfield.jumpabsolute = 0;
1959 temp.bitfield.unspecified = 0;
1960 temp.bitfield.byte = 0;
1961 temp.bitfield.word = 0;
1962 temp.bitfield.dword = 0;
1963 temp.bitfield.fword = 0;
1964 temp.bitfield.qword = 0;
1965 temp.bitfield.tbyte = 0;
1966 temp.bitfield.xmmword = 0;
1967 temp.bitfield.ymmword = 0;
1968 temp.bitfield.zmmword = 0;
1969 if (operand_type_all_zero (&temp))
1972 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1973 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1977 i.error = operand_type_mismatch;
1981 /* If given types g0 and g1 are registers they must be of the same type
1982 unless the expected operand type register overlap is null.
1983 Memory operand size of certain SIMD instructions is also being checked
1987 operand_type_register_match (i386_operand_type g0,
1988 i386_operand_type t0,
1989 i386_operand_type g1,
1990 i386_operand_type t1)
1992 if (!g0.bitfield.reg
1993 && !g0.bitfield.regsimd
1994 && (!operand_type_check (g0, anymem)
1995 || g0.bitfield.unspecified
1996 || !t0.bitfield.regsimd))
1999 if (!g1.bitfield.reg
2000 && !g1.bitfield.regsimd
2001 && (!operand_type_check (g1, anymem)
2002 || g1.bitfield.unspecified
2003 || !t1.bitfield.regsimd))
2006 if (g0.bitfield.byte == g1.bitfield.byte
2007 && g0.bitfield.word == g1.bitfield.word
2008 && g0.bitfield.dword == g1.bitfield.dword
2009 && g0.bitfield.qword == g1.bitfield.qword
2010 && g0.bitfield.xmmword == g1.bitfield.xmmword
2011 && g0.bitfield.ymmword == g1.bitfield.ymmword
2012 && g0.bitfield.zmmword == g1.bitfield.zmmword)
2015 if (!(t0.bitfield.byte & t1.bitfield.byte)
2016 && !(t0.bitfield.word & t1.bitfield.word)
2017 && !(t0.bitfield.dword & t1.bitfield.dword)
2018 && !(t0.bitfield.qword & t1.bitfield.qword)
2019 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2020 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2021 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
2024 i.error = register_type_mismatch;
2029 static INLINE unsigned int
2030 register_number (const reg_entry *r)
2032 unsigned int nr = r->reg_num;
2034 if (r->reg_flags & RegRex)
2037 if (r->reg_flags & RegVRex)
2043 static INLINE unsigned int
2044 mode_from_disp_size (i386_operand_type t)
2046 if (t.bitfield.disp8)
2048 else if (t.bitfield.disp16
2049 || t.bitfield.disp32
2050 || t.bitfield.disp32s)
2057 fits_in_signed_byte (addressT num)
2059 return num + 0x80 <= 0xff;
2063 fits_in_unsigned_byte (addressT num)
2069 fits_in_unsigned_word (addressT num)
2071 return num <= 0xffff;
2075 fits_in_signed_word (addressT num)
2077 return num + 0x8000 <= 0xffff;
2081 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
2086 return num + 0x80000000 <= 0xffffffff;
2088 } /* fits_in_signed_long() */
2091 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
2096 return num <= 0xffffffff;
2098 } /* fits_in_unsigned_long() */
2101 fits_in_disp8 (offsetT num)
2103 int shift = i.memshift;
2109 mask = (1 << shift) - 1;
2111 /* Return 0 if NUM isn't properly aligned. */
2115 /* Check if NUM will fit in 8bit after shift. */
2116 return fits_in_signed_byte (num >> shift);
2120 fits_in_imm4 (offsetT num)
2122 return (num & 0xf) == num;
2125 static i386_operand_type
2126 smallest_imm_type (offsetT num)
2128 i386_operand_type t;
2130 operand_type_set (&t, 0);
2131 t.bitfield.imm64 = 1;
2133 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2135 /* This code is disabled on the 486 because all the Imm1 forms
2136 in the opcode table are slower on the i486. They're the
2137 versions with the implicitly specified single-position
2138 displacement, which has another syntax if you really want to
2140 t.bitfield.imm1 = 1;
2141 t.bitfield.imm8 = 1;
2142 t.bitfield.imm8s = 1;
2143 t.bitfield.imm16 = 1;
2144 t.bitfield.imm32 = 1;
2145 t.bitfield.imm32s = 1;
2147 else if (fits_in_signed_byte (num))
2149 t.bitfield.imm8 = 1;
2150 t.bitfield.imm8s = 1;
2151 t.bitfield.imm16 = 1;
2152 t.bitfield.imm32 = 1;
2153 t.bitfield.imm32s = 1;
2155 else if (fits_in_unsigned_byte (num))
2157 t.bitfield.imm8 = 1;
2158 t.bitfield.imm16 = 1;
2159 t.bitfield.imm32 = 1;
2160 t.bitfield.imm32s = 1;
2162 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2164 t.bitfield.imm16 = 1;
2165 t.bitfield.imm32 = 1;
2166 t.bitfield.imm32s = 1;
2168 else if (fits_in_signed_long (num))
2170 t.bitfield.imm32 = 1;
2171 t.bitfield.imm32s = 1;
2173 else if (fits_in_unsigned_long (num))
2174 t.bitfield.imm32 = 1;
2180 offset_in_range (offsetT val, int size)
2186 case 1: mask = ((addressT) 1 << 8) - 1; break;
2187 case 2: mask = ((addressT) 1 << 16) - 1; break;
2188 case 4: mask = ((addressT) 2 << 31) - 1; break;
2190 case 8: mask = ((addressT) 2 << 63) - 1; break;
2196 /* If BFD64, sign extend val for 32bit address mode. */
2197 if (flag_code != CODE_64BIT
2198 || i.prefix[ADDR_PREFIX])
2199 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2200 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2203 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2205 char buf1[40], buf2[40];
2207 sprint_value (buf1, val);
2208 sprint_value (buf2, val & mask);
2209 as_warn (_("%s shortened to %s"), buf1, buf2);
2224 a. PREFIX_EXIST if attempting to add a prefix where one from the
2225 same class already exists.
2226 b. PREFIX_LOCK if lock prefix is added.
2227 c. PREFIX_REP if rep/repne prefix is added.
2228 d. PREFIX_DS if ds prefix is added.
2229 e. PREFIX_OTHER if other prefix is added.
2232 static enum PREFIX_GROUP
2233 add_prefix (unsigned int prefix)
2235 enum PREFIX_GROUP ret = PREFIX_OTHER;
2238 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2239 && flag_code == CODE_64BIT)
2241 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2242 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2243 && (prefix & (REX_R | REX_X | REX_B))))
2254 case DS_PREFIX_OPCODE:
2257 case CS_PREFIX_OPCODE:
2258 case ES_PREFIX_OPCODE:
2259 case FS_PREFIX_OPCODE:
2260 case GS_PREFIX_OPCODE:
2261 case SS_PREFIX_OPCODE:
2265 case REPNE_PREFIX_OPCODE:
2266 case REPE_PREFIX_OPCODE:
2271 case LOCK_PREFIX_OPCODE:
2280 case ADDR_PREFIX_OPCODE:
2284 case DATA_PREFIX_OPCODE:
2288 if (i.prefix[q] != 0)
2296 i.prefix[q] |= prefix;
2299 as_bad (_("same type of prefix used twice"));
2305 update_code_flag (int value, int check)
2307 PRINTF_LIKE ((*as_error));
2309 flag_code = (enum flag_code) value;
2310 if (flag_code == CODE_64BIT)
2312 cpu_arch_flags.bitfield.cpu64 = 1;
2313 cpu_arch_flags.bitfield.cpuno64 = 0;
2317 cpu_arch_flags.bitfield.cpu64 = 0;
2318 cpu_arch_flags.bitfield.cpuno64 = 1;
2320 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2323 as_error = as_fatal;
2326 (*as_error) (_("64bit mode not supported on `%s'."),
2327 cpu_arch_name ? cpu_arch_name : default_arch);
2329 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2332 as_error = as_fatal;
2335 (*as_error) (_("32bit mode not supported on `%s'."),
2336 cpu_arch_name ? cpu_arch_name : default_arch);
2338 stackop_size = '\0';
2342 set_code_flag (int value)
2344 update_code_flag (value, 0);
2348 set_16bit_gcc_code_flag (int new_code_flag)
2350 flag_code = (enum flag_code) new_code_flag;
2351 if (flag_code != CODE_16BIT)
2353 cpu_arch_flags.bitfield.cpu64 = 0;
2354 cpu_arch_flags.bitfield.cpuno64 = 1;
2355 stackop_size = LONG_MNEM_SUFFIX;
2359 set_intel_syntax (int syntax_flag)
2361 /* Find out if register prefixing is specified. */
2362 int ask_naked_reg = 0;
2365 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2368 int e = get_symbol_name (&string);
2370 if (strcmp (string, "prefix") == 0)
2372 else if (strcmp (string, "noprefix") == 0)
2375 as_bad (_("bad argument to syntax directive."));
2376 (void) restore_line_pointer (e);
2378 demand_empty_rest_of_line ();
2380 intel_syntax = syntax_flag;
2382 if (ask_naked_reg == 0)
2383 allow_naked_reg = (intel_syntax
2384 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2386 allow_naked_reg = (ask_naked_reg < 0);
2388 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2390 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2391 identifier_chars['$'] = intel_syntax ? '$' : 0;
2392 register_prefix = allow_naked_reg ? "" : "%";
2396 set_intel_mnemonic (int mnemonic_flag)
2398 intel_mnemonic = mnemonic_flag;
2402 set_allow_index_reg (int flag)
2404 allow_index_reg = flag;
2408 set_check (int what)
2410 enum check_kind *kind;
2415 kind = &operand_check;
2426 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2429 int e = get_symbol_name (&string);
2431 if (strcmp (string, "none") == 0)
2433 else if (strcmp (string, "warning") == 0)
2434 *kind = check_warning;
2435 else if (strcmp (string, "error") == 0)
2436 *kind = check_error;
2438 as_bad (_("bad argument to %s_check directive."), str);
2439 (void) restore_line_pointer (e);
2442 as_bad (_("missing argument for %s_check directive"), str);
2444 demand_empty_rest_of_line ();
2448 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2449 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2451 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2452 static const char *arch;
2454 /* Intel LIOM is only supported on ELF. */
2460 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2461 use default_arch. */
2462 arch = cpu_arch_name;
2464 arch = default_arch;
2467 /* If we are targeting Intel MCU, we must enable it. */
2468 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2469 || new_flag.bitfield.cpuiamcu)
2472 /* If we are targeting Intel L1OM, we must enable it. */
2473 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2474 || new_flag.bitfield.cpul1om)
2477 /* If we are targeting Intel K1OM, we must enable it. */
2478 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2479 || new_flag.bitfield.cpuk1om)
2482 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2487 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2491 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2494 int e = get_symbol_name (&string);
2496 i386_cpu_flags flags;
2498 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2500 if (strcmp (string, cpu_arch[j].name) == 0)
2502 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2506 cpu_arch_name = cpu_arch[j].name;
2507 cpu_sub_arch_name = NULL;
2508 cpu_arch_flags = cpu_arch[j].flags;
2509 if (flag_code == CODE_64BIT)
2511 cpu_arch_flags.bitfield.cpu64 = 1;
2512 cpu_arch_flags.bitfield.cpuno64 = 0;
2516 cpu_arch_flags.bitfield.cpu64 = 0;
2517 cpu_arch_flags.bitfield.cpuno64 = 1;
2519 cpu_arch_isa = cpu_arch[j].type;
2520 cpu_arch_isa_flags = cpu_arch[j].flags;
2521 if (!cpu_arch_tune_set)
2523 cpu_arch_tune = cpu_arch_isa;
2524 cpu_arch_tune_flags = cpu_arch_isa_flags;
2529 flags = cpu_flags_or (cpu_arch_flags,
2532 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2534 if (cpu_sub_arch_name)
2536 char *name = cpu_sub_arch_name;
2537 cpu_sub_arch_name = concat (name,
2539 (const char *) NULL);
2543 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2544 cpu_arch_flags = flags;
2545 cpu_arch_isa_flags = flags;
2547 (void) restore_line_pointer (e);
2548 demand_empty_rest_of_line ();
2553 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2555 /* Disable an ISA extension. */
2556 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2557 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2559 flags = cpu_flags_and_not (cpu_arch_flags,
2560 cpu_noarch[j].flags);
2561 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2563 if (cpu_sub_arch_name)
2565 char *name = cpu_sub_arch_name;
2566 cpu_sub_arch_name = concat (name, string,
2567 (const char *) NULL);
2571 cpu_sub_arch_name = xstrdup (string);
2572 cpu_arch_flags = flags;
2573 cpu_arch_isa_flags = flags;
2575 (void) restore_line_pointer (e);
2576 demand_empty_rest_of_line ();
2580 j = ARRAY_SIZE (cpu_arch);
2583 if (j >= ARRAY_SIZE (cpu_arch))
2584 as_bad (_("no such architecture: `%s'"), string);
2586 *input_line_pointer = e;
2589 as_bad (_("missing cpu architecture"));
2591 no_cond_jump_promotion = 0;
2592 if (*input_line_pointer == ','
2593 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2598 ++input_line_pointer;
2599 e = get_symbol_name (&string);
2601 if (strcmp (string, "nojumps") == 0)
2602 no_cond_jump_promotion = 1;
2603 else if (strcmp (string, "jumps") == 0)
2606 as_bad (_("no such architecture modifier: `%s'"), string);
2608 (void) restore_line_pointer (e);
2611 demand_empty_rest_of_line ();
2614 enum bfd_architecture
2617 if (cpu_arch_isa == PROCESSOR_L1OM)
2619 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2620 || flag_code != CODE_64BIT)
2621 as_fatal (_("Intel L1OM is 64bit ELF only"));
2622 return bfd_arch_l1om;
2624 else if (cpu_arch_isa == PROCESSOR_K1OM)
2626 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2627 || flag_code != CODE_64BIT)
2628 as_fatal (_("Intel K1OM is 64bit ELF only"));
2629 return bfd_arch_k1om;
2631 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2633 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2634 || flag_code == CODE_64BIT)
2635 as_fatal (_("Intel MCU is 32bit ELF only"));
2636 return bfd_arch_iamcu;
2639 return bfd_arch_i386;
2645 if (!strncmp (default_arch, "x86_64", 6))
2647 if (cpu_arch_isa == PROCESSOR_L1OM)
2649 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2650 || default_arch[6] != '\0')
2651 as_fatal (_("Intel L1OM is 64bit ELF only"));
2652 return bfd_mach_l1om;
2654 else if (cpu_arch_isa == PROCESSOR_K1OM)
2656 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2657 || default_arch[6] != '\0')
2658 as_fatal (_("Intel K1OM is 64bit ELF only"));
2659 return bfd_mach_k1om;
2661 else if (default_arch[6] == '\0')
2662 return bfd_mach_x86_64;
2664 return bfd_mach_x64_32;
2666 else if (!strcmp (default_arch, "i386")
2667 || !strcmp (default_arch, "iamcu"))
2669 if (cpu_arch_isa == PROCESSOR_IAMCU)
2671 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2672 as_fatal (_("Intel MCU is 32bit ELF only"));
2673 return bfd_mach_i386_iamcu;
2676 return bfd_mach_i386_i386;
2679 as_fatal (_("unknown architecture"));
2685 const char *hash_err;
2687 /* Support pseudo prefixes like {disp32}. */
2688 lex_type ['{'] = LEX_BEGIN_NAME;
2690 /* Initialize op_hash hash table. */
2691 op_hash = hash_new ();
2694 const insn_template *optab;
2695 templates *core_optab;
2697 /* Setup for loop. */
2699 core_optab = XNEW (templates);
2700 core_optab->start = optab;
2705 if (optab->name == NULL
2706 || strcmp (optab->name, (optab - 1)->name) != 0)
2708 /* different name --> ship out current template list;
2709 add to hash table; & begin anew. */
2710 core_optab->end = optab;
2711 hash_err = hash_insert (op_hash,
2713 (void *) core_optab);
2716 as_fatal (_("can't hash %s: %s"),
2720 if (optab->name == NULL)
2722 core_optab = XNEW (templates);
2723 core_optab->start = optab;
2728 /* Initialize reg_hash hash table. */
2729 reg_hash = hash_new ();
2731 const reg_entry *regtab;
2732 unsigned int regtab_size = i386_regtab_size;
2734 for (regtab = i386_regtab; regtab_size--; regtab++)
2736 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2738 as_fatal (_("can't hash %s: %s"),
2744 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2749 for (c = 0; c < 256; c++)
2754 mnemonic_chars[c] = c;
2755 register_chars[c] = c;
2756 operand_chars[c] = c;
2758 else if (ISLOWER (c))
2760 mnemonic_chars[c] = c;
2761 register_chars[c] = c;
2762 operand_chars[c] = c;
2764 else if (ISUPPER (c))
2766 mnemonic_chars[c] = TOLOWER (c);
2767 register_chars[c] = mnemonic_chars[c];
2768 operand_chars[c] = c;
2770 else if (c == '{' || c == '}')
2772 mnemonic_chars[c] = c;
2773 operand_chars[c] = c;
2776 if (ISALPHA (c) || ISDIGIT (c))
2777 identifier_chars[c] = c;
2780 identifier_chars[c] = c;
2781 operand_chars[c] = c;
2786 identifier_chars['@'] = '@';
2789 identifier_chars['?'] = '?';
2790 operand_chars['?'] = '?';
2792 digit_chars['-'] = '-';
2793 mnemonic_chars['_'] = '_';
2794 mnemonic_chars['-'] = '-';
2795 mnemonic_chars['.'] = '.';
2796 identifier_chars['_'] = '_';
2797 identifier_chars['.'] = '.';
2799 for (p = operand_special_chars; *p != '\0'; p++)
2800 operand_chars[(unsigned char) *p] = *p;
2803 if (flag_code == CODE_64BIT)
2805 #if defined (OBJ_COFF) && defined (TE_PE)
2806 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2809 x86_dwarf2_return_column = 16;
2811 x86_cie_data_alignment = -8;
2815 x86_dwarf2_return_column = 8;
2816 x86_cie_data_alignment = -4;
2821 i386_print_statistics (FILE *file)
2823 hash_print_statistics (file, "i386 opcode", op_hash);
2824 hash_print_statistics (file, "i386 register", reg_hash);
2829 /* Debugging routines for md_assemble. */
2830 static void pte (insn_template *);
2831 static void pt (i386_operand_type);
2832 static void pe (expressionS *);
2833 static void ps (symbolS *);
2836 pi (char *line, i386_insn *x)
2840 fprintf (stdout, "%s: template ", line);
2842 fprintf (stdout, " address: base %s index %s scale %x\n",
2843 x->base_reg ? x->base_reg->reg_name : "none",
2844 x->index_reg ? x->index_reg->reg_name : "none",
2845 x->log2_scale_factor);
2846 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2847 x->rm.mode, x->rm.reg, x->rm.regmem);
2848 fprintf (stdout, " sib: base %x index %x scale %x\n",
2849 x->sib.base, x->sib.index, x->sib.scale);
2850 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2851 (x->rex & REX_W) != 0,
2852 (x->rex & REX_R) != 0,
2853 (x->rex & REX_X) != 0,
2854 (x->rex & REX_B) != 0);
2855 for (j = 0; j < x->operands; j++)
2857 fprintf (stdout, " #%d: ", j + 1);
2859 fprintf (stdout, "\n");
2860 if (x->types[j].bitfield.reg
2861 || x->types[j].bitfield.regmmx
2862 || x->types[j].bitfield.regsimd
2863 || x->types[j].bitfield.sreg2
2864 || x->types[j].bitfield.sreg3
2865 || x->types[j].bitfield.control
2866 || x->types[j].bitfield.debug
2867 || x->types[j].bitfield.test)
2868 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2869 if (operand_type_check (x->types[j], imm))
2871 if (operand_type_check (x->types[j], disp))
2872 pe (x->op[j].disps);
2877 pte (insn_template *t)
2880 fprintf (stdout, " %d operands ", t->operands);
2881 fprintf (stdout, "opcode %x ", t->base_opcode);
2882 if (t->extension_opcode != None)
2883 fprintf (stdout, "ext %x ", t->extension_opcode);
2884 if (t->opcode_modifier.d)
2885 fprintf (stdout, "D");
2886 if (t->opcode_modifier.w)
2887 fprintf (stdout, "W");
2888 fprintf (stdout, "\n");
2889 for (j = 0; j < t->operands; j++)
2891 fprintf (stdout, " #%d type ", j + 1);
2892 pt (t->operand_types[j]);
2893 fprintf (stdout, "\n");
2900 fprintf (stdout, " operation %d\n", e->X_op);
2901 fprintf (stdout, " add_number %ld (%lx)\n",
2902 (long) e->X_add_number, (long) e->X_add_number);
2903 if (e->X_add_symbol)
2905 fprintf (stdout, " add_symbol ");
2906 ps (e->X_add_symbol);
2907 fprintf (stdout, "\n");
2911 fprintf (stdout, " op_symbol ");
2912 ps (e->X_op_symbol);
2913 fprintf (stdout, "\n");
2920 fprintf (stdout, "%s type %s%s",
2922 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2923 segment_name (S_GET_SEGMENT (s)));
2926 static struct type_name
2928 i386_operand_type mask;
2931 const type_names[] =
2933 { OPERAND_TYPE_REG8, "r8" },
2934 { OPERAND_TYPE_REG16, "r16" },
2935 { OPERAND_TYPE_REG32, "r32" },
2936 { OPERAND_TYPE_REG64, "r64" },
2937 { OPERAND_TYPE_IMM8, "i8" },
2938 { OPERAND_TYPE_IMM8, "i8s" },
2939 { OPERAND_TYPE_IMM16, "i16" },
2940 { OPERAND_TYPE_IMM32, "i32" },
2941 { OPERAND_TYPE_IMM32S, "i32s" },
2942 { OPERAND_TYPE_IMM64, "i64" },
2943 { OPERAND_TYPE_IMM1, "i1" },
2944 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2945 { OPERAND_TYPE_DISP8, "d8" },
2946 { OPERAND_TYPE_DISP16, "d16" },
2947 { OPERAND_TYPE_DISP32, "d32" },
2948 { OPERAND_TYPE_DISP32S, "d32s" },
2949 { OPERAND_TYPE_DISP64, "d64" },
2950 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2951 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2952 { OPERAND_TYPE_CONTROL, "control reg" },
2953 { OPERAND_TYPE_TEST, "test reg" },
2954 { OPERAND_TYPE_DEBUG, "debug reg" },
2955 { OPERAND_TYPE_FLOATREG, "FReg" },
2956 { OPERAND_TYPE_FLOATACC, "FAcc" },
2957 { OPERAND_TYPE_SREG2, "SReg2" },
2958 { OPERAND_TYPE_SREG3, "SReg3" },
2959 { OPERAND_TYPE_ACC, "Acc" },
2960 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2961 { OPERAND_TYPE_REGMMX, "rMMX" },
2962 { OPERAND_TYPE_REGXMM, "rXMM" },
2963 { OPERAND_TYPE_REGYMM, "rYMM" },
2964 { OPERAND_TYPE_REGZMM, "rZMM" },
2965 { OPERAND_TYPE_REGMASK, "Mask reg" },
2966 { OPERAND_TYPE_ESSEG, "es" },
2970 pt (i386_operand_type t)
2973 i386_operand_type a;
2975 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2977 a = operand_type_and (t, type_names[j].mask);
2978 if (!operand_type_all_zero (&a))
2979 fprintf (stdout, "%s, ", type_names[j].name);
2984 #endif /* DEBUG386 */
2986 static bfd_reloc_code_real_type
2987 reloc (unsigned int size,
2990 bfd_reloc_code_real_type other)
2992 if (other != NO_RELOC)
2994 reloc_howto_type *rel;
2999 case BFD_RELOC_X86_64_GOT32:
3000 return BFD_RELOC_X86_64_GOT64;
3002 case BFD_RELOC_X86_64_GOTPLT64:
3003 return BFD_RELOC_X86_64_GOTPLT64;
3005 case BFD_RELOC_X86_64_PLTOFF64:
3006 return BFD_RELOC_X86_64_PLTOFF64;
3008 case BFD_RELOC_X86_64_GOTPC32:
3009 other = BFD_RELOC_X86_64_GOTPC64;
3011 case BFD_RELOC_X86_64_GOTPCREL:
3012 other = BFD_RELOC_X86_64_GOTPCREL64;
3014 case BFD_RELOC_X86_64_TPOFF32:
3015 other = BFD_RELOC_X86_64_TPOFF64;
3017 case BFD_RELOC_X86_64_DTPOFF32:
3018 other = BFD_RELOC_X86_64_DTPOFF64;
3024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3025 if (other == BFD_RELOC_SIZE32)
3028 other = BFD_RELOC_SIZE64;
3031 as_bad (_("there are no pc-relative size relocations"));
3037 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3038 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
3041 rel = bfd_reloc_type_lookup (stdoutput, other);
3043 as_bad (_("unknown relocation (%u)"), other);
3044 else if (size != bfd_get_reloc_size (rel))
3045 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
3046 bfd_get_reloc_size (rel),
3048 else if (pcrel && !rel->pc_relative)
3049 as_bad (_("non-pc-relative relocation for pc-relative field"));
3050 else if ((rel->complain_on_overflow == complain_overflow_signed
3052 || (rel->complain_on_overflow == complain_overflow_unsigned
3054 as_bad (_("relocated field and relocation type differ in signedness"));
3063 as_bad (_("there are no unsigned pc-relative relocations"));
3066 case 1: return BFD_RELOC_8_PCREL;
3067 case 2: return BFD_RELOC_16_PCREL;
3068 case 4: return BFD_RELOC_32_PCREL;
3069 case 8: return BFD_RELOC_64_PCREL;
3071 as_bad (_("cannot do %u byte pc-relative relocation"), size);
3078 case 4: return BFD_RELOC_X86_64_32S;
3083 case 1: return BFD_RELOC_8;
3084 case 2: return BFD_RELOC_16;
3085 case 4: return BFD_RELOC_32;
3086 case 8: return BFD_RELOC_64;
3088 as_bad (_("cannot do %s %u byte relocation"),
3089 sign > 0 ? "signed" : "unsigned", size);
3095 /* Here we decide which fixups can be adjusted to make them relative to
3096 the beginning of the section instead of the symbol. Basically we need
3097 to make sure that the dynamic relocations are done correctly, so in
3098 some cases we force the original symbol to be used. */
3101 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
3103 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3107 /* Don't adjust pc-relative references to merge sections in 64-bit
3109 if (use_rela_relocations
3110 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3114 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3115 and changed later by validate_fix. */
3116 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3117 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3120 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3121 for size relocations. */
3122 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3123 || fixP->fx_r_type == BFD_RELOC_SIZE64
3124 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
3125 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3126 || fixP->fx_r_type == BFD_RELOC_386_GOT32
3127 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
3128 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3129 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3130 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3131 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
3132 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3133 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
3134 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3135 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3136 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3137 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3138 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
3140 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
3141 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3142 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
3143 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3144 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3145 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
3146 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
3147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3148 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
3149 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3150 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
3151 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3152 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
3153 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3154 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3161 intel_float_operand (const char *mnemonic)
3163 /* Note that the value returned is meaningful only for opcodes with (memory)
3164 operands, hence the code here is free to improperly handle opcodes that
3165 have no operands (for better performance and smaller code). */
3167 if (mnemonic[0] != 'f')
3168 return 0; /* non-math */
3170 switch (mnemonic[1])
3172 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3173 the fs segment override prefix not currently handled because no
3174 call path can make opcodes without operands get here */
3176 return 2 /* integer op */;
3178 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3179 return 3; /* fldcw/fldenv */
3182 if (mnemonic[2] != 'o' /* fnop */)
3183 return 3; /* non-waiting control op */
3186 if (mnemonic[2] == 's')
3187 return 3; /* frstor/frstpm */
3190 if (mnemonic[2] == 'a')
3191 return 3; /* fsave */
3192 if (mnemonic[2] == 't')
3194 switch (mnemonic[3])
3196 case 'c': /* fstcw */
3197 case 'd': /* fstdw */
3198 case 'e': /* fstenv */
3199 case 's': /* fsts[gw] */
3205 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3206 return 0; /* fxsave/fxrstor are not really math ops */
3213 /* Build the VEX prefix. */
3216 build_vex_prefix (const insn_template *t)
3218 unsigned int register_specifier;
3219 unsigned int implied_prefix;
3220 unsigned int vector_length;
3222 /* Check register specifier. */
3223 if (i.vex.register_specifier)
3225 register_specifier =
3226 ~register_number (i.vex.register_specifier) & 0xf;
3227 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3230 register_specifier = 0xf;
3232 /* Use 2-byte VEX prefix by swapping destination and source
3234 if (i.vec_encoding != vex_encoding_vex3
3235 && i.dir_encoding == dir_encoding_default
3236 && i.operands == i.reg_operands
3237 && i.tm.opcode_modifier.vexopcode == VEX0F
3238 && i.tm.opcode_modifier.load
3241 unsigned int xchg = i.operands - 1;
3242 union i386_op temp_op;
3243 i386_operand_type temp_type;
3245 temp_type = i.types[xchg];
3246 i.types[xchg] = i.types[0];
3247 i.types[0] = temp_type;
3248 temp_op = i.op[xchg];
3249 i.op[xchg] = i.op[0];
3252 gas_assert (i.rm.mode == 3);
3256 i.rm.regmem = i.rm.reg;
3259 /* Use the next insn. */
3263 if (i.tm.opcode_modifier.vex == VEXScalar)
3264 vector_length = avxscalar;
3265 else if (i.tm.opcode_modifier.vex == VEX256)
3272 for (op = 0; op < t->operands; ++op)
3273 if (t->operand_types[op].bitfield.xmmword
3274 && t->operand_types[op].bitfield.ymmword
3275 && i.types[op].bitfield.ymmword)
3282 switch ((i.tm.base_opcode >> 8) & 0xff)
3287 case DATA_PREFIX_OPCODE:
3290 case REPE_PREFIX_OPCODE:
3293 case REPNE_PREFIX_OPCODE:
3300 /* Use 2-byte VEX prefix if possible. */
3301 if (i.vec_encoding != vex_encoding_vex3
3302 && i.tm.opcode_modifier.vexopcode == VEX0F
3303 && i.tm.opcode_modifier.vexw != VEXW1
3304 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3306 /* 2-byte VEX prefix. */
3310 i.vex.bytes[0] = 0xc5;
3312 /* Check the REX.R bit. */
3313 r = (i.rex & REX_R) ? 0 : 1;
3314 i.vex.bytes[1] = (r << 7
3315 | register_specifier << 3
3316 | vector_length << 2
3321 /* 3-byte VEX prefix. */
3326 switch (i.tm.opcode_modifier.vexopcode)
3330 i.vex.bytes[0] = 0xc4;
3334 i.vex.bytes[0] = 0xc4;
3338 i.vex.bytes[0] = 0xc4;
3342 i.vex.bytes[0] = 0x8f;
3346 i.vex.bytes[0] = 0x8f;
3350 i.vex.bytes[0] = 0x8f;
3356 /* The high 3 bits of the second VEX byte are 1's compliment
3357 of RXB bits from REX. */
3358 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3360 /* Check the REX.W bit. */
3361 w = (i.rex & REX_W) ? 1 : 0;
3362 if (i.tm.opcode_modifier.vexw == VEXW1)
3365 i.vex.bytes[2] = (w << 7
3366 | register_specifier << 3
3367 | vector_length << 2
3372 /* Build the EVEX prefix. */
3375 build_evex_prefix (void)
3377 unsigned int register_specifier;
3378 unsigned int implied_prefix;
3380 rex_byte vrex_used = 0;
3382 /* Check register specifier. */
3383 if (i.vex.register_specifier)
3385 gas_assert ((i.vrex & REX_X) == 0);
3387 register_specifier = i.vex.register_specifier->reg_num;
3388 if ((i.vex.register_specifier->reg_flags & RegRex))
3389 register_specifier += 8;
3390 /* The upper 16 registers are encoded in the fourth byte of the
3392 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3393 i.vex.bytes[3] = 0x8;
3394 register_specifier = ~register_specifier & 0xf;
3398 register_specifier = 0xf;
3400 /* Encode upper 16 vector index register in the fourth byte of
3402 if (!(i.vrex & REX_X))
3403 i.vex.bytes[3] = 0x8;
3408 switch ((i.tm.base_opcode >> 8) & 0xff)
3413 case DATA_PREFIX_OPCODE:
3416 case REPE_PREFIX_OPCODE:
3419 case REPNE_PREFIX_OPCODE:
3426 /* 4 byte EVEX prefix. */
3428 i.vex.bytes[0] = 0x62;
3431 switch (i.tm.opcode_modifier.vexopcode)
3447 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3449 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3451 /* The fifth bit of the second EVEX byte is 1's compliment of the
3452 REX_R bit in VREX. */
3453 if (!(i.vrex & REX_R))
3454 i.vex.bytes[1] |= 0x10;
3458 if ((i.reg_operands + i.imm_operands) == i.operands)
3460 /* When all operands are registers, the REX_X bit in REX is not
3461 used. We reuse it to encode the upper 16 registers, which is
3462 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3463 as 1's compliment. */
3464 if ((i.vrex & REX_B))
3467 i.vex.bytes[1] &= ~0x40;
3471 /* EVEX instructions shouldn't need the REX prefix. */
3472 i.vrex &= ~vrex_used;
3473 gas_assert (i.vrex == 0);
3475 /* Check the REX.W bit. */
3476 w = (i.rex & REX_W) ? 1 : 0;
3477 if (i.tm.opcode_modifier.vexw)
3479 if (i.tm.opcode_modifier.vexw == VEXW1)
3482 /* If w is not set it means we are dealing with WIG instruction. */
3485 if (evexwig == evexw1)
3489 /* Encode the U bit. */
3490 implied_prefix |= 0x4;
3492 /* The third byte of the EVEX prefix. */
3493 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3495 /* The fourth byte of the EVEX prefix. */
3496 /* The zeroing-masking bit. */
3497 if (i.mask && i.mask->zeroing)
3498 i.vex.bytes[3] |= 0x80;
3500 /* Don't always set the broadcast bit if there is no RC. */
3503 /* Encode the vector length. */
3504 unsigned int vec_length;
3506 switch (i.tm.opcode_modifier.evex)
3508 case EVEXLIG: /* LL' is ignored */
3509 vec_length = evexlig << 5;
3512 vec_length = 0 << 5;
3515 vec_length = 1 << 5;
3518 vec_length = 2 << 5;
3524 i.vex.bytes[3] |= vec_length;
3525 /* Encode the broadcast bit. */
3527 i.vex.bytes[3] |= 0x10;
3531 if (i.rounding->type != saeonly)
3532 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3534 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3537 if (i.mask && i.mask->mask)
3538 i.vex.bytes[3] |= i.mask->mask->reg_num;
3542 process_immext (void)
3546 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3549 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3550 with an opcode suffix which is coded in the same place as an
3551 8-bit immediate field would be.
3552 Here we check those operands and remove them afterwards. */
3555 for (x = 0; x < i.operands; x++)
3556 if (register_number (i.op[x].regs) != x)
3557 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3558 register_prefix, i.op[x].regs->reg_name, x + 1,
3564 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3566 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3567 suffix which is coded in the same place as an 8-bit immediate
3569 Here we check those operands and remove them afterwards. */
3572 if (i.operands != 3)
3575 for (x = 0; x < 2; x++)
3576 if (register_number (i.op[x].regs) != x)
3577 goto bad_register_operand;
3579 /* Check for third operand for mwaitx/monitorx insn. */
3580 if (register_number (i.op[x].regs)
3581 != (x + (i.tm.extension_opcode == 0xfb)))
3583 bad_register_operand:
3584 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3585 register_prefix, i.op[x].regs->reg_name, x+1,
3592 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3593 which is coded in the same place as an 8-bit immediate field
3594 would be. Here we fake an 8-bit immediate operand from the
3595 opcode suffix stored in tm.extension_opcode.
3597 AVX instructions also use this encoding, for some of
3598 3 argument instructions. */
3600 gas_assert (i.imm_operands <= 1
3602 || ((i.tm.opcode_modifier.vex
3603 || i.tm.opcode_modifier.evex)
3604 && i.operands <= 4)));
3606 exp = &im_expressions[i.imm_operands++];
3607 i.op[i.operands].imms = exp;
3608 i.types[i.operands] = imm8;
3610 exp->X_op = O_constant;
3611 exp->X_add_number = i.tm.extension_opcode;
3612 i.tm.extension_opcode = None;
3619 switch (i.tm.opcode_modifier.hleprefixok)
3624 as_bad (_("invalid instruction `%s' after `%s'"),
3625 i.tm.name, i.hle_prefix);
3628 if (i.prefix[LOCK_PREFIX])
3630 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3634 case HLEPrefixRelease:
3635 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3637 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3641 if (i.mem_operands == 0
3642 || !operand_type_check (i.types[i.operands - 1], anymem))
3644 as_bad (_("memory destination needed for instruction `%s'"
3645 " after `xrelease'"), i.tm.name);
3652 /* This is the guts of the machine-dependent assembler. LINE points to a
3653 machine dependent instruction. This function is supposed to emit
3654 the frags/bytes it assembles to. */
3657 md_assemble (char *line)
3660 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
3661 const insn_template *t;
3663 /* Initialize globals. */
3664 memset (&i, '\0', sizeof (i));
3665 for (j = 0; j < MAX_OPERANDS; j++)
3666 i.reloc[j] = NO_RELOC;
3667 memset (disp_expressions, '\0', sizeof (disp_expressions));
3668 memset (im_expressions, '\0', sizeof (im_expressions));
3669 save_stack_p = save_stack;
3671 /* First parse an instruction mnemonic & call i386_operand for the operands.
3672 We assume that the scrubber has arranged it so that line[0] is the valid
3673 start of a (possibly prefixed) mnemonic. */
3675 line = parse_insn (line, mnemonic);
3678 mnem_suffix = i.suffix;
3680 line = parse_operands (line, mnemonic);
3682 xfree (i.memop1_string);
3683 i.memop1_string = NULL;
3687 /* Now we've parsed the mnemonic into a set of templates, and have the
3688 operands at hand. */
3690 /* All intel opcodes have reversed operands except for "bound" and
3691 "enter". We also don't reverse intersegment "jmp" and "call"
3692 instructions with 2 immediate operands so that the immediate segment
3693 precedes the offset, as it does when in AT&T mode. */
3696 && (strcmp (mnemonic, "bound") != 0)
3697 && (strcmp (mnemonic, "invlpga") != 0)
3698 && !(operand_type_check (i.types[0], imm)
3699 && operand_type_check (i.types[1], imm)))
3702 /* The order of the immediates should be reversed
3703 for 2 immediates extrq and insertq instructions */
3704 if (i.imm_operands == 2
3705 && (strcmp (mnemonic, "extrq") == 0
3706 || strcmp (mnemonic, "insertq") == 0))
3707 swap_2_operands (0, 1);
3712 /* Don't optimize displacement for movabs since it only takes 64bit
3715 && i.disp_encoding != disp_encoding_32bit
3716 && (flag_code != CODE_64BIT
3717 || strcmp (mnemonic, "movabs") != 0))
3720 /* Next, we find a template that matches the given insn,
3721 making sure the overlap of the given operands types is consistent
3722 with the template operand types. */
3724 if (!(t = match_template (mnem_suffix)))
3727 if (sse_check != check_none
3728 && !i.tm.opcode_modifier.noavx
3729 && (i.tm.cpu_flags.bitfield.cpusse
3730 || i.tm.cpu_flags.bitfield.cpusse2
3731 || i.tm.cpu_flags.bitfield.cpusse3
3732 || i.tm.cpu_flags.bitfield.cpussse3
3733 || i.tm.cpu_flags.bitfield.cpusse4_1
3734 || i.tm.cpu_flags.bitfield.cpusse4_2))
3736 (sse_check == check_warning
3738 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3741 /* Zap movzx and movsx suffix. The suffix has been set from
3742 "word ptr" or "byte ptr" on the source operand in Intel syntax
3743 or extracted from mnemonic in AT&T syntax. But we'll use
3744 the destination register to choose the suffix for encoding. */
3745 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3747 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3748 there is no suffix, the default will be byte extension. */
3749 if (i.reg_operands != 2
3752 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3757 if (i.tm.opcode_modifier.fwait)
3758 if (!add_prefix (FWAIT_OPCODE))
3761 /* Check if REP prefix is OK. */
3762 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3764 as_bad (_("invalid instruction `%s' after `%s'"),
3765 i.tm.name, i.rep_prefix);
3769 /* Check for lock without a lockable instruction. Destination operand
3770 must be memory unless it is xchg (0x86). */
3771 if (i.prefix[LOCK_PREFIX]
3772 && (!i.tm.opcode_modifier.islockable
3773 || i.mem_operands == 0
3774 || (i.tm.base_opcode != 0x86
3775 && !operand_type_check (i.types[i.operands - 1], anymem))))
3777 as_bad (_("expecting lockable instruction after `lock'"));
3781 /* Check if HLE prefix is OK. */
3782 if (i.hle_prefix && !check_hle ())
3785 /* Check BND prefix. */
3786 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3787 as_bad (_("expecting valid branch instruction after `bnd'"));
3789 /* Check NOTRACK prefix. */
3790 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3791 as_bad (_("expecting indirect branch instruction after `notrack'"));
3793 if (i.tm.cpu_flags.bitfield.cpumpx)
3795 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3796 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3797 else if (flag_code != CODE_16BIT
3798 ? i.prefix[ADDR_PREFIX]
3799 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3800 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3803 /* Insert BND prefix. */
3805 && i.tm.opcode_modifier.bndprefixok
3806 && !i.prefix[BND_PREFIX])
3807 add_prefix (BND_PREFIX_OPCODE);
3809 /* Check string instruction segment overrides. */
3810 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3812 if (!check_string ())
3814 i.disp_operands = 0;
3817 if (!process_suffix ())
3820 /* Update operand types. */
3821 for (j = 0; j < i.operands; j++)
3822 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3824 /* Make still unresolved immediate matches conform to size of immediate
3825 given in i.suffix. */
3826 if (!finalize_imm ())
3829 if (i.types[0].bitfield.imm1)
3830 i.imm_operands = 0; /* kludge for shift insns. */
3832 /* We only need to check those implicit registers for instructions
3833 with 3 operands or less. */
3834 if (i.operands <= 3)
3835 for (j = 0; j < i.operands; j++)
3836 if (i.types[j].bitfield.inoutportreg
3837 || i.types[j].bitfield.shiftcount
3838 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
3841 /* ImmExt should be processed after SSE2AVX. */
3842 if (!i.tm.opcode_modifier.sse2avx
3843 && i.tm.opcode_modifier.immext)
3846 /* For insns with operands there are more diddles to do to the opcode. */
3849 if (!process_operands ())
3852 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3854 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3855 as_warn (_("translating to `%sp'"), i.tm.name);
3858 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3860 if (flag_code == CODE_16BIT)
3862 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3867 if (i.tm.opcode_modifier.vex)
3868 build_vex_prefix (t);
3870 build_evex_prefix ();
3873 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3874 instructions may define INT_OPCODE as well, so avoid this corner
3875 case for those instructions that use MODRM. */
3876 if (i.tm.base_opcode == INT_OPCODE
3877 && !i.tm.opcode_modifier.modrm
3878 && i.op[0].imms->X_add_number == 3)
3880 i.tm.base_opcode = INT3_OPCODE;
3884 if ((i.tm.opcode_modifier.jump
3885 || i.tm.opcode_modifier.jumpbyte
3886 || i.tm.opcode_modifier.jumpdword)
3887 && i.op[0].disps->X_op == O_constant)
3889 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3890 the absolute address given by the constant. Since ix86 jumps and
3891 calls are pc relative, we need to generate a reloc. */
3892 i.op[0].disps->X_add_symbol = &abs_symbol;
3893 i.op[0].disps->X_op = O_symbol;
3896 if (i.tm.opcode_modifier.rex64)
3899 /* For 8 bit registers we need an empty rex prefix. Also if the
3900 instruction already has a prefix, we need to convert old
3901 registers to new ones. */
3903 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
3904 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3905 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
3906 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3907 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3908 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
3913 i.rex |= REX_OPCODE;
3914 for (x = 0; x < 2; x++)
3916 /* Look for 8 bit operand that uses old registers. */
3917 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
3918 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3920 /* In case it is "hi" register, give up. */
3921 if (i.op[x].regs->reg_num > 3)
3922 as_bad (_("can't encode register '%s%s' in an "
3923 "instruction requiring REX prefix."),
3924 register_prefix, i.op[x].regs->reg_name);
3926 /* Otherwise it is equivalent to the extended register.
3927 Since the encoding doesn't change this is merely
3928 cosmetic cleanup for debug output. */
3930 i.op[x].regs = i.op[x].regs + 8;
3936 add_prefix (REX_OPCODE | i.rex);
3938 /* We are ready to output the insn. */
3943 parse_insn (char *line, char *mnemonic)
3946 char *token_start = l;
3949 const insn_template *t;
3955 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3960 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3962 as_bad (_("no such instruction: `%s'"), token_start);
3967 if (!is_space_char (*l)
3968 && *l != END_OF_INSN
3970 || (*l != PREFIX_SEPARATOR
3973 as_bad (_("invalid character %s in mnemonic"),
3974 output_invalid (*l));
3977 if (token_start == l)
3979 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3980 as_bad (_("expecting prefix; got nothing"));
3982 as_bad (_("expecting mnemonic; got nothing"));
3986 /* Look up instruction (or prefix) via hash table. */
3987 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3989 if (*l != END_OF_INSN
3990 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3991 && current_templates
3992 && current_templates->start->opcode_modifier.isprefix)
3994 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3996 as_bad ((flag_code != CODE_64BIT
3997 ? _("`%s' is only supported in 64-bit mode")
3998 : _("`%s' is not supported in 64-bit mode")),
3999 current_templates->start->name);
4002 /* If we are in 16-bit mode, do not allow addr16 or data16.
4003 Similarly, in 32-bit mode, do not allow addr32 or data32. */
4004 if ((current_templates->start->opcode_modifier.size16
4005 || current_templates->start->opcode_modifier.size32)
4006 && flag_code != CODE_64BIT
4007 && (current_templates->start->opcode_modifier.size32
4008 ^ (flag_code == CODE_16BIT)))
4010 as_bad (_("redundant %s prefix"),
4011 current_templates->start->name);
4014 if (current_templates->start->opcode_length == 0)
4016 /* Handle pseudo prefixes. */
4017 switch (current_templates->start->base_opcode)
4021 i.disp_encoding = disp_encoding_8bit;
4025 i.disp_encoding = disp_encoding_32bit;
4029 i.dir_encoding = dir_encoding_load;
4033 i.dir_encoding = dir_encoding_store;
4037 i.vec_encoding = vex_encoding_vex2;
4041 i.vec_encoding = vex_encoding_vex3;
4045 i.vec_encoding = vex_encoding_evex;
4053 /* Add prefix, checking for repeated prefixes. */
4054 switch (add_prefix (current_templates->start->base_opcode))
4059 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4060 i.notrack_prefix = current_templates->start->name;
4063 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4064 i.hle_prefix = current_templates->start->name;
4065 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4066 i.bnd_prefix = current_templates->start->name;
4068 i.rep_prefix = current_templates->start->name;
4074 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4081 if (!current_templates)
4083 /* Check if we should swap operand or force 32bit displacement in
4085 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
4086 i.dir_encoding = dir_encoding_store;
4087 else if (mnem_p - 3 == dot_p
4090 i.disp_encoding = disp_encoding_8bit;
4091 else if (mnem_p - 4 == dot_p
4095 i.disp_encoding = disp_encoding_32bit;
4100 current_templates = (const templates *) hash_find (op_hash, mnemonic);
4103 if (!current_templates)
4106 /* See if we can get a match by trimming off a suffix. */
4109 case WORD_MNEM_SUFFIX:
4110 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4111 i.suffix = SHORT_MNEM_SUFFIX;
4114 case BYTE_MNEM_SUFFIX:
4115 case QWORD_MNEM_SUFFIX:
4116 i.suffix = mnem_p[-1];
4118 current_templates = (const templates *) hash_find (op_hash,
4121 case SHORT_MNEM_SUFFIX:
4122 case LONG_MNEM_SUFFIX:
4125 i.suffix = mnem_p[-1];
4127 current_templates = (const templates *) hash_find (op_hash,
4136 if (intel_float_operand (mnemonic) == 1)
4137 i.suffix = SHORT_MNEM_SUFFIX;
4139 i.suffix = LONG_MNEM_SUFFIX;
4141 current_templates = (const templates *) hash_find (op_hash,
4146 if (!current_templates)
4148 as_bad (_("no such instruction: `%s'"), token_start);
4153 if (current_templates->start->opcode_modifier.jump
4154 || current_templates->start->opcode_modifier.jumpbyte)
4156 /* Check for a branch hint. We allow ",pt" and ",pn" for
4157 predict taken and predict not taken respectively.
4158 I'm not sure that branch hints actually do anything on loop
4159 and jcxz insns (JumpByte) for current Pentium4 chips. They
4160 may work in the future and it doesn't hurt to accept them
4162 if (l[0] == ',' && l[1] == 'p')
4166 if (!add_prefix (DS_PREFIX_OPCODE))
4170 else if (l[2] == 'n')
4172 if (!add_prefix (CS_PREFIX_OPCODE))
4178 /* Any other comma loses. */
4181 as_bad (_("invalid character %s in mnemonic"),
4182 output_invalid (*l));
4186 /* Check if instruction is supported on specified architecture. */
4188 for (t = current_templates->start; t < current_templates->end; ++t)
4190 supported |= cpu_flags_match (t);
4191 if (supported == CPU_FLAGS_PERFECT_MATCH)
4195 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4197 as_bad (flag_code == CODE_64BIT
4198 ? _("`%s' is not supported in 64-bit mode")
4199 : _("`%s' is only supported in 64-bit mode"),
4200 current_templates->start->name);
4203 if (supported != CPU_FLAGS_PERFECT_MATCH)
4205 as_bad (_("`%s' is not supported on `%s%s'"),
4206 current_templates->start->name,
4207 cpu_arch_name ? cpu_arch_name : default_arch,
4208 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4213 if (!cpu_arch_flags.bitfield.cpui386
4214 && (flag_code != CODE_16BIT))
4216 as_warn (_("use .code16 to ensure correct addressing mode"));
4223 parse_operands (char *l, const char *mnemonic)
4227 /* 1 if operand is pending after ','. */
4228 unsigned int expecting_operand = 0;
4230 /* Non-zero if operand parens not balanced. */
4231 unsigned int paren_not_balanced;
4233 while (*l != END_OF_INSN)
4235 /* Skip optional white space before operand. */
4236 if (is_space_char (*l))
4238 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
4240 as_bad (_("invalid character %s before operand %d"),
4241 output_invalid (*l),
4245 token_start = l; /* After white space. */
4246 paren_not_balanced = 0;
4247 while (paren_not_balanced || *l != ',')
4249 if (*l == END_OF_INSN)
4251 if (paren_not_balanced)
4254 as_bad (_("unbalanced parenthesis in operand %d."),
4257 as_bad (_("unbalanced brackets in operand %d."),
4262 break; /* we are done */
4264 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
4266 as_bad (_("invalid character %s in operand %d"),
4267 output_invalid (*l),
4274 ++paren_not_balanced;
4276 --paren_not_balanced;
4281 ++paren_not_balanced;
4283 --paren_not_balanced;
4287 if (l != token_start)
4288 { /* Yes, we've read in another operand. */
4289 unsigned int operand_ok;
4290 this_operand = i.operands++;
4291 if (i.operands > MAX_OPERANDS)
4293 as_bad (_("spurious operands; (%d operands/instruction max)"),
4297 i.types[this_operand].bitfield.unspecified = 1;
4298 /* Now parse operand adding info to 'i' as we go along. */
4299 END_STRING_AND_SAVE (l);
4303 i386_intel_operand (token_start,
4304 intel_float_operand (mnemonic));
4306 operand_ok = i386_att_operand (token_start);
4308 RESTORE_END_STRING (l);
4314 if (expecting_operand)
4316 expecting_operand_after_comma:
4317 as_bad (_("expecting operand after ','; got nothing"));
4322 as_bad (_("expecting operand before ','; got nothing"));
4327 /* Now *l must be either ',' or END_OF_INSN. */
4330 if (*++l == END_OF_INSN)
4332 /* Just skip it, if it's \n complain. */
4333 goto expecting_operand_after_comma;
4335 expecting_operand = 1;
4342 swap_2_operands (int xchg1, int xchg2)
4344 union i386_op temp_op;
4345 i386_operand_type temp_type;
4346 enum bfd_reloc_code_real temp_reloc;
4348 temp_type = i.types[xchg2];
4349 i.types[xchg2] = i.types[xchg1];
4350 i.types[xchg1] = temp_type;
4351 temp_op = i.op[xchg2];
4352 i.op[xchg2] = i.op[xchg1];
4353 i.op[xchg1] = temp_op;
4354 temp_reloc = i.reloc[xchg2];
4355 i.reloc[xchg2] = i.reloc[xchg1];
4356 i.reloc[xchg1] = temp_reloc;
4360 if (i.mask->operand == xchg1)
4361 i.mask->operand = xchg2;
4362 else if (i.mask->operand == xchg2)
4363 i.mask->operand = xchg1;
4367 if (i.broadcast->operand == xchg1)
4368 i.broadcast->operand = xchg2;
4369 else if (i.broadcast->operand == xchg2)
4370 i.broadcast->operand = xchg1;
4374 if (i.rounding->operand == xchg1)
4375 i.rounding->operand = xchg2;
4376 else if (i.rounding->operand == xchg2)
4377 i.rounding->operand = xchg1;
4382 swap_operands (void)
4388 swap_2_operands (1, i.operands - 2);
4392 swap_2_operands (0, i.operands - 1);
4398 if (i.mem_operands == 2)
4400 const seg_entry *temp_seg;
4401 temp_seg = i.seg[0];
4402 i.seg[0] = i.seg[1];
4403 i.seg[1] = temp_seg;
4407 /* Try to ensure constant immediates are represented in the smallest
4412 char guess_suffix = 0;
4416 guess_suffix = i.suffix;
4417 else if (i.reg_operands)
4419 /* Figure out a suffix from the last register operand specified.
4420 We can't do this properly yet, ie. excluding InOutPortReg,
4421 but the following works for instructions with immediates.
4422 In any case, we can't set i.suffix yet. */
4423 for (op = i.operands; --op >= 0;)
4424 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
4426 guess_suffix = BYTE_MNEM_SUFFIX;
4429 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
4431 guess_suffix = WORD_MNEM_SUFFIX;
4434 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
4436 guess_suffix = LONG_MNEM_SUFFIX;
4439 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
4441 guess_suffix = QWORD_MNEM_SUFFIX;
4445 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4446 guess_suffix = WORD_MNEM_SUFFIX;
4448 for (op = i.operands; --op >= 0;)
4449 if (operand_type_check (i.types[op], imm))
4451 switch (i.op[op].imms->X_op)
4454 /* If a suffix is given, this operand may be shortened. */
4455 switch (guess_suffix)
4457 case LONG_MNEM_SUFFIX:
4458 i.types[op].bitfield.imm32 = 1;
4459 i.types[op].bitfield.imm64 = 1;
4461 case WORD_MNEM_SUFFIX:
4462 i.types[op].bitfield.imm16 = 1;
4463 i.types[op].bitfield.imm32 = 1;
4464 i.types[op].bitfield.imm32s = 1;
4465 i.types[op].bitfield.imm64 = 1;
4467 case BYTE_MNEM_SUFFIX:
4468 i.types[op].bitfield.imm8 = 1;
4469 i.types[op].bitfield.imm8s = 1;
4470 i.types[op].bitfield.imm16 = 1;
4471 i.types[op].bitfield.imm32 = 1;
4472 i.types[op].bitfield.imm32s = 1;
4473 i.types[op].bitfield.imm64 = 1;
4477 /* If this operand is at most 16 bits, convert it
4478 to a signed 16 bit number before trying to see
4479 whether it will fit in an even smaller size.
4480 This allows a 16-bit operand such as $0xffe0 to
4481 be recognised as within Imm8S range. */
4482 if ((i.types[op].bitfield.imm16)
4483 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4485 i.op[op].imms->X_add_number =
4486 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4489 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
4490 if ((i.types[op].bitfield.imm32)
4491 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4494 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4495 ^ ((offsetT) 1 << 31))
4496 - ((offsetT) 1 << 31));
4500 = operand_type_or (i.types[op],
4501 smallest_imm_type (i.op[op].imms->X_add_number));
4503 /* We must avoid matching of Imm32 templates when 64bit
4504 only immediate is available. */
4505 if (guess_suffix == QWORD_MNEM_SUFFIX)
4506 i.types[op].bitfield.imm32 = 0;
4513 /* Symbols and expressions. */
4515 /* Convert symbolic operand to proper sizes for matching, but don't
4516 prevent matching a set of insns that only supports sizes other
4517 than those matching the insn suffix. */
4519 i386_operand_type mask, allowed;
4520 const insn_template *t;
4522 operand_type_set (&mask, 0);
4523 operand_type_set (&allowed, 0);
4525 for (t = current_templates->start;
4526 t < current_templates->end;
4528 allowed = operand_type_or (allowed,
4529 t->operand_types[op]);
4530 switch (guess_suffix)
4532 case QWORD_MNEM_SUFFIX:
4533 mask.bitfield.imm64 = 1;
4534 mask.bitfield.imm32s = 1;
4536 case LONG_MNEM_SUFFIX:
4537 mask.bitfield.imm32 = 1;
4539 case WORD_MNEM_SUFFIX:
4540 mask.bitfield.imm16 = 1;
4542 case BYTE_MNEM_SUFFIX:
4543 mask.bitfield.imm8 = 1;
4548 allowed = operand_type_and (mask, allowed);
4549 if (!operand_type_all_zero (&allowed))
4550 i.types[op] = operand_type_and (i.types[op], mask);
4557 /* Try to use the smallest displacement type too. */
4559 optimize_disp (void)
4563 for (op = i.operands; --op >= 0;)
4564 if (operand_type_check (i.types[op], disp))
4566 if (i.op[op].disps->X_op == O_constant)
4568 offsetT op_disp = i.op[op].disps->X_add_number;
4570 if (i.types[op].bitfield.disp16
4571 && (op_disp & ~(offsetT) 0xffff) == 0)
4573 /* If this operand is at most 16 bits, convert
4574 to a signed 16 bit number and don't use 64bit
4576 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4577 i.types[op].bitfield.disp64 = 0;
4580 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
4581 if (i.types[op].bitfield.disp32
4582 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4584 /* If this operand is at most 32 bits, convert
4585 to a signed 32 bit number and don't use 64bit
4587 op_disp &= (((offsetT) 2 << 31) - 1);
4588 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4589 i.types[op].bitfield.disp64 = 0;
4592 if (!op_disp && i.types[op].bitfield.baseindex)
4594 i.types[op].bitfield.disp8 = 0;
4595 i.types[op].bitfield.disp16 = 0;
4596 i.types[op].bitfield.disp32 = 0;
4597 i.types[op].bitfield.disp32s = 0;
4598 i.types[op].bitfield.disp64 = 0;
4602 else if (flag_code == CODE_64BIT)
4604 if (fits_in_signed_long (op_disp))
4606 i.types[op].bitfield.disp64 = 0;
4607 i.types[op].bitfield.disp32s = 1;
4609 if (i.prefix[ADDR_PREFIX]
4610 && fits_in_unsigned_long (op_disp))
4611 i.types[op].bitfield.disp32 = 1;
4613 if ((i.types[op].bitfield.disp32
4614 || i.types[op].bitfield.disp32s
4615 || i.types[op].bitfield.disp16)
4616 && fits_in_disp8 (op_disp))
4617 i.types[op].bitfield.disp8 = 1;
4619 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4620 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4622 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4623 i.op[op].disps, 0, i.reloc[op]);
4624 i.types[op].bitfield.disp8 = 0;
4625 i.types[op].bitfield.disp16 = 0;
4626 i.types[op].bitfield.disp32 = 0;
4627 i.types[op].bitfield.disp32s = 0;
4628 i.types[op].bitfield.disp64 = 0;
4631 /* We only support 64bit displacement on constants. */
4632 i.types[op].bitfield.disp64 = 0;
4636 /* Check if operands are valid for the instruction. */
4639 check_VecOperands (const insn_template *t)
4643 /* Without VSIB byte, we can't have a vector register for index. */
4644 if (!t->opcode_modifier.vecsib
4646 && (i.index_reg->reg_type.bitfield.xmmword
4647 || i.index_reg->reg_type.bitfield.ymmword
4648 || i.index_reg->reg_type.bitfield.zmmword))
4650 i.error = unsupported_vector_index_register;
4654 /* Check if default mask is allowed. */
4655 if (t->opcode_modifier.nodefmask
4656 && (!i.mask || i.mask->mask->reg_num == 0))
4658 i.error = no_default_mask;
4662 /* For VSIB byte, we need a vector register for index, and all vector
4663 registers must be distinct. */
4664 if (t->opcode_modifier.vecsib)
4667 || !((t->opcode_modifier.vecsib == VecSIB128
4668 && i.index_reg->reg_type.bitfield.xmmword)
4669 || (t->opcode_modifier.vecsib == VecSIB256
4670 && i.index_reg->reg_type.bitfield.ymmword)
4671 || (t->opcode_modifier.vecsib == VecSIB512
4672 && i.index_reg->reg_type.bitfield.zmmword)))
4674 i.error = invalid_vsib_address;
4678 gas_assert (i.reg_operands == 2 || i.mask);
4679 if (i.reg_operands == 2 && !i.mask)
4681 gas_assert (i.types[0].bitfield.regsimd);
4682 gas_assert (i.types[0].bitfield.xmmword
4683 || i.types[0].bitfield.ymmword);
4684 gas_assert (i.types[2].bitfield.regsimd);
4685 gas_assert (i.types[2].bitfield.xmmword
4686 || i.types[2].bitfield.ymmword);
4687 if (operand_check == check_none)
4689 if (register_number (i.op[0].regs)
4690 != register_number (i.index_reg)
4691 && register_number (i.op[2].regs)
4692 != register_number (i.index_reg)
4693 && register_number (i.op[0].regs)
4694 != register_number (i.op[2].regs))
4696 if (operand_check == check_error)
4698 i.error = invalid_vector_register_set;
4701 as_warn (_("mask, index, and destination registers should be distinct"));
4703 else if (i.reg_operands == 1 && i.mask)
4705 if (i.types[1].bitfield.regsimd
4706 && (i.types[1].bitfield.xmmword
4707 || i.types[1].bitfield.ymmword
4708 || i.types[1].bitfield.zmmword)
4709 && (register_number (i.op[1].regs)
4710 == register_number (i.index_reg)))
4712 if (operand_check == check_error)
4714 i.error = invalid_vector_register_set;
4717 if (operand_check != check_none)
4718 as_warn (_("index and destination registers should be distinct"));
4723 /* Check if broadcast is supported by the instruction and is applied
4724 to the memory operand. */
4727 int broadcasted_opnd_size;
4729 /* Check if specified broadcast is supported in this instruction,
4730 and it's applied to memory operand of DWORD or QWORD type,
4731 depending on VecESize. */
4732 if (i.broadcast->type != t->opcode_modifier.broadcast
4733 || !i.types[i.broadcast->operand].bitfield.mem
4734 || (t->opcode_modifier.vecesize == 0
4735 && !i.types[i.broadcast->operand].bitfield.dword
4736 && !i.types[i.broadcast->operand].bitfield.unspecified)
4737 || (t->opcode_modifier.vecesize == 1
4738 && !i.types[i.broadcast->operand].bitfield.qword
4739 && !i.types[i.broadcast->operand].bitfield.unspecified))
4742 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4743 if (i.broadcast->type == BROADCAST_1TO16)
4744 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4745 else if (i.broadcast->type == BROADCAST_1TO8)
4746 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4747 else if (i.broadcast->type == BROADCAST_1TO4)
4748 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4749 else if (i.broadcast->type == BROADCAST_1TO2)
4750 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4754 if ((broadcasted_opnd_size == 256
4755 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4756 || (broadcasted_opnd_size == 512
4757 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4760 i.error = unsupported_broadcast;
4764 /* If broadcast is supported in this instruction, we need to check if
4765 operand of one-element size isn't specified without broadcast. */
4766 else if (t->opcode_modifier.broadcast && i.mem_operands)
4768 /* Find memory operand. */
4769 for (op = 0; op < i.operands; op++)
4770 if (operand_type_check (i.types[op], anymem))
4772 gas_assert (op < i.operands);
4773 /* Check size of the memory operand. */
4774 if ((t->opcode_modifier.vecesize == 0
4775 && i.types[op].bitfield.dword)
4776 || (t->opcode_modifier.vecesize == 1
4777 && i.types[op].bitfield.qword))
4779 i.error = broadcast_needed;
4784 /* Check if requested masking is supported. */
4786 && (!t->opcode_modifier.masking
4788 && t->opcode_modifier.masking == MERGING_MASKING)))
4790 i.error = unsupported_masking;
4794 /* Check if masking is applied to dest operand. */
4795 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4797 i.error = mask_not_on_destination;
4804 if ((i.rounding->type != saeonly
4805 && !t->opcode_modifier.staticrounding)
4806 || (i.rounding->type == saeonly
4807 && (t->opcode_modifier.staticrounding
4808 || !t->opcode_modifier.sae)))
4810 i.error = unsupported_rc_sae;
4813 /* If the instruction has several immediate operands and one of
4814 them is rounding, the rounding operand should be the last
4815 immediate operand. */
4816 if (i.imm_operands > 1
4817 && i.rounding->operand != (int) (i.imm_operands - 1))
4819 i.error = rc_sae_operand_not_last_imm;
4824 /* Check vector Disp8 operand. */
4825 if (t->opcode_modifier.disp8memshift
4826 && i.disp_encoding != disp_encoding_32bit)
4829 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4831 i.memshift = t->opcode_modifier.disp8memshift;
4833 for (op = 0; op < i.operands; op++)
4834 if (operand_type_check (i.types[op], disp)
4835 && i.op[op].disps->X_op == O_constant)
4837 if (fits_in_disp8 (i.op[op].disps->X_add_number))
4839 i.types[op].bitfield.disp8 = 1;
4842 i.types[op].bitfield.disp8 = 0;
4851 /* Check if operands are valid for the instruction. Update VEX
4855 VEX_check_operands (const insn_template *t)
4857 if (i.vec_encoding == vex_encoding_evex)
4859 /* This instruction must be encoded with EVEX prefix. */
4860 if (!t->opcode_modifier.evex)
4862 i.error = unsupported;
4868 if (!t->opcode_modifier.vex)
4870 /* This instruction template doesn't have VEX prefix. */
4871 if (i.vec_encoding != vex_encoding_default)
4873 i.error = unsupported;
4879 /* Only check VEX_Imm4, which must be the first operand. */
4880 if (t->operand_types[0].bitfield.vec_imm4)
4882 if (i.op[0].imms->X_op != O_constant
4883 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4889 /* Turn off Imm8 so that update_imm won't complain. */
4890 i.types[0] = vec_imm4;
4896 static const insn_template *
4897 match_template (char mnem_suffix)
4899 /* Points to template once we've found it. */
4900 const insn_template *t;
4901 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4902 i386_operand_type overlap4;
4903 unsigned int found_reverse_match;
4904 i386_opcode_modifier suffix_check, mnemsuf_check;
4905 i386_operand_type operand_types [MAX_OPERANDS];
4906 int addr_prefix_disp;
4908 unsigned int found_cpu_match;
4909 unsigned int check_register;
4910 enum i386_error specific_error = 0;
4912 #if MAX_OPERANDS != 5
4913 # error "MAX_OPERANDS must be 5."
4916 found_reverse_match = 0;
4917 addr_prefix_disp = -1;
4919 memset (&suffix_check, 0, sizeof (suffix_check));
4920 if (i.suffix == BYTE_MNEM_SUFFIX)
4921 suffix_check.no_bsuf = 1;
4922 else if (i.suffix == WORD_MNEM_SUFFIX)
4923 suffix_check.no_wsuf = 1;
4924 else if (i.suffix == SHORT_MNEM_SUFFIX)
4925 suffix_check.no_ssuf = 1;
4926 else if (i.suffix == LONG_MNEM_SUFFIX)
4927 suffix_check.no_lsuf = 1;
4928 else if (i.suffix == QWORD_MNEM_SUFFIX)
4929 suffix_check.no_qsuf = 1;
4930 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4931 suffix_check.no_ldsuf = 1;
4933 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4936 switch (mnem_suffix)
4938 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4939 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4940 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4941 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4942 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4946 /* Must have right number of operands. */
4947 i.error = number_of_operands_mismatch;
4949 for (t = current_templates->start; t < current_templates->end; t++)
4951 addr_prefix_disp = -1;
4953 if (i.operands != t->operands)
4956 /* Check processor support. */
4957 i.error = unsupported;
4958 found_cpu_match = (cpu_flags_match (t)
4959 == CPU_FLAGS_PERFECT_MATCH);
4960 if (!found_cpu_match)
4963 /* Check old gcc support. */
4964 i.error = old_gcc_only;
4965 if (!old_gcc && t->opcode_modifier.oldgcc)
4968 /* Check AT&T mnemonic. */
4969 i.error = unsupported_with_intel_mnemonic;
4970 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4973 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
4974 i.error = unsupported_syntax;
4975 if ((intel_syntax && t->opcode_modifier.attsyntax)
4976 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4977 || (intel64 && t->opcode_modifier.amd64)
4978 || (!intel64 && t->opcode_modifier.intel64))
4981 /* Check the suffix, except for some instructions in intel mode. */
4982 i.error = invalid_instruction_suffix;
4983 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4984 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4985 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4986 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4987 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4988 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4989 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4991 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4992 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4993 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4994 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4995 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4996 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4997 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5000 if (!operand_size_match (t))
5003 for (j = 0; j < MAX_OPERANDS; j++)
5004 operand_types[j] = t->operand_types[j];
5006 /* In general, don't allow 64-bit operands in 32-bit mode. */
5007 if (i.suffix == QWORD_MNEM_SUFFIX
5008 && flag_code != CODE_64BIT
5010 ? (!t->opcode_modifier.ignoresize
5011 && !intel_float_operand (t->name))
5012 : intel_float_operand (t->name) != 2)
5013 && ((!operand_types[0].bitfield.regmmx
5014 && !operand_types[0].bitfield.regsimd)
5015 || (!operand_types[t->operands > 1].bitfield.regmmx
5016 && !operand_types[t->operands > 1].bitfield.regsimd))
5017 && (t->base_opcode != 0x0fc7
5018 || t->extension_opcode != 1 /* cmpxchg8b */))
5021 /* In general, don't allow 32-bit operands on pre-386. */
5022 else if (i.suffix == LONG_MNEM_SUFFIX
5023 && !cpu_arch_flags.bitfield.cpui386
5025 ? (!t->opcode_modifier.ignoresize
5026 && !intel_float_operand (t->name))
5027 : intel_float_operand (t->name) != 2)
5028 && ((!operand_types[0].bitfield.regmmx
5029 && !operand_types[0].bitfield.regsimd)
5030 || (!operand_types[t->operands > 1].bitfield.regmmx
5031 && !operand_types[t->operands > 1].bitfield.regsimd)))
5034 /* Do not verify operands when there are none. */
5038 /* We've found a match; break out of loop. */
5042 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5043 into Disp32/Disp16/Disp32 operand. */
5044 if (i.prefix[ADDR_PREFIX] != 0)
5046 /* There should be only one Disp operand. */
5050 for (j = 0; j < MAX_OPERANDS; j++)
5052 if (operand_types[j].bitfield.disp16)
5054 addr_prefix_disp = j;
5055 operand_types[j].bitfield.disp32 = 1;
5056 operand_types[j].bitfield.disp16 = 0;
5062 for (j = 0; j < MAX_OPERANDS; j++)
5064 if (operand_types[j].bitfield.disp32)
5066 addr_prefix_disp = j;
5067 operand_types[j].bitfield.disp32 = 0;
5068 operand_types[j].bitfield.disp16 = 1;
5074 for (j = 0; j < MAX_OPERANDS; j++)
5076 if (operand_types[j].bitfield.disp64)
5078 addr_prefix_disp = j;
5079 operand_types[j].bitfield.disp64 = 0;
5080 operand_types[j].bitfield.disp32 = 1;
5088 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5089 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5092 /* We check register size if needed. */
5093 check_register = t->opcode_modifier.checkregsize;
5094 overlap0 = operand_type_and (i.types[0], operand_types[0]);
5095 switch (t->operands)
5098 if (!operand_type_match (overlap0, i.types[0]))
5102 /* xchg %eax, %eax is a special case. It is an alias for nop
5103 only in 32bit mode and we can use opcode 0x90. In 64bit
5104 mode, we can't use 0x90 for xchg %eax, %eax since it should
5105 zero-extend %eax to %rax. */
5106 if (flag_code == CODE_64BIT
5107 && t->base_opcode == 0x90
5108 && operand_type_equal (&i.types [0], &acc32)
5109 && operand_type_equal (&i.types [1], &acc32))
5111 /* If we want store form, we reverse direction of operands. */
5112 if (i.dir_encoding == dir_encoding_store
5113 && t->opcode_modifier.d)
5118 /* If we want store form, we skip the current load. */
5119 if (i.dir_encoding == dir_encoding_store
5120 && i.mem_operands == 0
5121 && t->opcode_modifier.load)
5126 overlap1 = operand_type_and (i.types[1], operand_types[1]);
5127 if (!operand_type_match (overlap0, i.types[0])
5128 || !operand_type_match (overlap1, i.types[1])
5130 && !operand_type_register_match (i.types[0],
5135 /* Check if other direction is valid ... */
5136 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
5140 /* Try reversing direction of operands. */
5141 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5142 overlap1 = operand_type_and (i.types[1], operand_types[0]);
5143 if (!operand_type_match (overlap0, i.types[0])
5144 || !operand_type_match (overlap1, i.types[1])
5146 && !operand_type_register_match (i.types[0],
5151 /* Does not match either direction. */
5154 /* found_reverse_match holds which of D or FloatDR
5156 if (t->opcode_modifier.d)
5157 found_reverse_match = Opcode_D;
5158 else if (t->opcode_modifier.floatd)
5159 found_reverse_match = Opcode_FloatD;
5161 found_reverse_match = 0;
5162 if (t->opcode_modifier.floatr)
5163 found_reverse_match |= Opcode_FloatR;
5167 /* Found a forward 2 operand match here. */
5168 switch (t->operands)
5171 overlap4 = operand_type_and (i.types[4],
5175 overlap3 = operand_type_and (i.types[3],
5179 overlap2 = operand_type_and (i.types[2],
5184 switch (t->operands)
5187 if (!operand_type_match (overlap4, i.types[4])
5188 || !operand_type_register_match (i.types[3],
5195 if (!operand_type_match (overlap3, i.types[3])
5197 && !operand_type_register_match (i.types[2],
5204 /* Here we make use of the fact that there are no
5205 reverse match 3 operand instructions, and all 3
5206 operand instructions only need to be checked for
5207 register consistency between operands 2 and 3. */
5208 if (!operand_type_match (overlap2, i.types[2])
5210 && !operand_type_register_match (i.types[1],
5218 /* Found either forward/reverse 2, 3 or 4 operand match here:
5219 slip through to break. */
5221 if (!found_cpu_match)
5223 found_reverse_match = 0;
5227 /* Check if vector and VEX operands are valid. */
5228 if (check_VecOperands (t) || VEX_check_operands (t))
5230 specific_error = i.error;
5234 /* We've found a match; break out of loop. */
5238 if (t == current_templates->end)
5240 /* We found no match. */
5241 const char *err_msg;
5242 switch (specific_error ? specific_error : i.error)
5246 case operand_size_mismatch:
5247 err_msg = _("operand size mismatch");
5249 case operand_type_mismatch:
5250 err_msg = _("operand type mismatch");
5252 case register_type_mismatch:
5253 err_msg = _("register type mismatch");
5255 case number_of_operands_mismatch:
5256 err_msg = _("number of operands mismatch");
5258 case invalid_instruction_suffix:
5259 err_msg = _("invalid instruction suffix");
5262 err_msg = _("constant doesn't fit in 4 bits");
5265 err_msg = _("only supported with old gcc");
5267 case unsupported_with_intel_mnemonic:
5268 err_msg = _("unsupported with Intel mnemonic");
5270 case unsupported_syntax:
5271 err_msg = _("unsupported syntax");
5274 as_bad (_("unsupported instruction `%s'"),
5275 current_templates->start->name);
5277 case invalid_vsib_address:
5278 err_msg = _("invalid VSIB address");
5280 case invalid_vector_register_set:
5281 err_msg = _("mask, index, and destination registers must be distinct");
5283 case unsupported_vector_index_register:
5284 err_msg = _("unsupported vector index register");
5286 case unsupported_broadcast:
5287 err_msg = _("unsupported broadcast");
5289 case broadcast_not_on_src_operand:
5290 err_msg = _("broadcast not on source memory operand");
5292 case broadcast_needed:
5293 err_msg = _("broadcast is needed for operand of such type");
5295 case unsupported_masking:
5296 err_msg = _("unsupported masking");
5298 case mask_not_on_destination:
5299 err_msg = _("mask not on destination operand");
5301 case no_default_mask:
5302 err_msg = _("default mask isn't allowed");
5304 case unsupported_rc_sae:
5305 err_msg = _("unsupported static rounding/sae");
5307 case rc_sae_operand_not_last_imm:
5309 err_msg = _("RC/SAE operand must precede immediate operands");
5311 err_msg = _("RC/SAE operand must follow immediate operands");
5313 case invalid_register_operand:
5314 err_msg = _("invalid register operand");
5317 as_bad (_("%s for `%s'"), err_msg,
5318 current_templates->start->name);
5322 if (!quiet_warnings)
5325 && (i.types[0].bitfield.jumpabsolute
5326 != operand_types[0].bitfield.jumpabsolute))
5328 as_warn (_("indirect %s without `*'"), t->name);
5331 if (t->opcode_modifier.isprefix
5332 && t->opcode_modifier.ignoresize)
5334 /* Warn them that a data or address size prefix doesn't
5335 affect assembly of the next line of code. */
5336 as_warn (_("stand-alone `%s' prefix"), t->name);
5340 /* Copy the template we found. */
5343 if (addr_prefix_disp != -1)
5344 i.tm.operand_types[addr_prefix_disp]
5345 = operand_types[addr_prefix_disp];
5347 if (found_reverse_match)
5349 /* If we found a reverse match we must alter the opcode
5350 direction bit. found_reverse_match holds bits to change
5351 (different for int & float insns). */
5353 i.tm.base_opcode ^= found_reverse_match;
5355 i.tm.operand_types[0] = operand_types[1];
5356 i.tm.operand_types[1] = operand_types[0];
5365 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5366 if (i.tm.operand_types[mem_op].bitfield.esseg)
5368 if (i.seg[0] != NULL && i.seg[0] != &es)
5370 as_bad (_("`%s' operand %d must use `%ses' segment"),
5376 /* There's only ever one segment override allowed per instruction.
5377 This instruction possibly has a legal segment override on the
5378 second operand, so copy the segment to where non-string
5379 instructions store it, allowing common code. */
5380 i.seg[0] = i.seg[1];
5382 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5384 if (i.seg[1] != NULL && i.seg[1] != &es)
5386 as_bad (_("`%s' operand %d must use `%ses' segment"),
5397 process_suffix (void)
5399 /* If matched instruction specifies an explicit instruction mnemonic
5401 if (i.tm.opcode_modifier.size16)
5402 i.suffix = WORD_MNEM_SUFFIX;
5403 else if (i.tm.opcode_modifier.size32)
5404 i.suffix = LONG_MNEM_SUFFIX;
5405 else if (i.tm.opcode_modifier.size64)
5406 i.suffix = QWORD_MNEM_SUFFIX;
5407 else if (i.reg_operands)
5409 /* If there's no instruction mnemonic suffix we try to invent one
5410 based on register operands. */
5413 /* We take i.suffix from the last register operand specified,
5414 Destination register type is more significant than source
5415 register type. crc32 in SSE4.2 prefers source register
5417 if (i.tm.base_opcode == 0xf20f38f1)
5419 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
5420 i.suffix = WORD_MNEM_SUFFIX;
5421 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
5422 i.suffix = LONG_MNEM_SUFFIX;
5423 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
5424 i.suffix = QWORD_MNEM_SUFFIX;
5426 else if (i.tm.base_opcode == 0xf20f38f0)
5428 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
5429 i.suffix = BYTE_MNEM_SUFFIX;
5436 if (i.tm.base_opcode == 0xf20f38f1
5437 || i.tm.base_opcode == 0xf20f38f0)
5439 /* We have to know the operand size for crc32. */
5440 as_bad (_("ambiguous memory operand size for `%s`"),
5445 for (op = i.operands; --op >= 0;)
5446 if (!i.tm.operand_types[op].bitfield.inoutportreg
5447 && !i.tm.operand_types[op].bitfield.shiftcount)
5449 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
5451 i.suffix = BYTE_MNEM_SUFFIX;
5454 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
5456 i.suffix = WORD_MNEM_SUFFIX;
5459 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
5461 i.suffix = LONG_MNEM_SUFFIX;
5464 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
5466 i.suffix = QWORD_MNEM_SUFFIX;
5472 else if (i.suffix == BYTE_MNEM_SUFFIX)
5475 && i.tm.opcode_modifier.ignoresize
5476 && i.tm.opcode_modifier.no_bsuf)
5478 else if (!check_byte_reg ())
5481 else if (i.suffix == LONG_MNEM_SUFFIX)
5484 && i.tm.opcode_modifier.ignoresize
5485 && i.tm.opcode_modifier.no_lsuf)
5487 else if (!check_long_reg ())
5490 else if (i.suffix == QWORD_MNEM_SUFFIX)
5493 && i.tm.opcode_modifier.ignoresize
5494 && i.tm.opcode_modifier.no_qsuf)
5496 else if (!check_qword_reg ())
5499 else if (i.suffix == WORD_MNEM_SUFFIX)
5502 && i.tm.opcode_modifier.ignoresize
5503 && i.tm.opcode_modifier.no_wsuf)
5505 else if (!check_word_reg ())
5508 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5509 || i.suffix == YMMWORD_MNEM_SUFFIX
5510 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5512 /* Skip if the instruction has x/y/z suffix. match_template
5513 should check if it is a valid suffix. */
5515 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5516 /* Do nothing if the instruction is going to ignore the prefix. */
5521 else if (i.tm.opcode_modifier.defaultsize
5523 /* exclude fldenv/frstor/fsave/fstenv */
5524 && i.tm.opcode_modifier.no_ssuf)
5526 i.suffix = stackop_size;
5528 else if (intel_syntax
5530 && (i.tm.operand_types[0].bitfield.jumpabsolute
5531 || i.tm.opcode_modifier.jumpbyte
5532 || i.tm.opcode_modifier.jumpintersegment
5533 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5534 && i.tm.extension_opcode <= 3)))
5539 if (!i.tm.opcode_modifier.no_qsuf)
5541 i.suffix = QWORD_MNEM_SUFFIX;
5546 if (!i.tm.opcode_modifier.no_lsuf)
5547 i.suffix = LONG_MNEM_SUFFIX;
5550 if (!i.tm.opcode_modifier.no_wsuf)
5551 i.suffix = WORD_MNEM_SUFFIX;
5560 if (i.tm.opcode_modifier.w)
5562 as_bad (_("no instruction mnemonic suffix given and "
5563 "no register operands; can't size instruction"));
5569 unsigned int suffixes;
5571 suffixes = !i.tm.opcode_modifier.no_bsuf;
5572 if (!i.tm.opcode_modifier.no_wsuf)
5574 if (!i.tm.opcode_modifier.no_lsuf)
5576 if (!i.tm.opcode_modifier.no_ldsuf)
5578 if (!i.tm.opcode_modifier.no_ssuf)
5580 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
5583 /* There are more than suffix matches. */
5584 if (i.tm.opcode_modifier.w
5585 || ((suffixes & (suffixes - 1))
5586 && !i.tm.opcode_modifier.defaultsize
5587 && !i.tm.opcode_modifier.ignoresize))
5589 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5595 /* Change the opcode based on the operand size given by i.suffix;
5596 We don't need to change things for byte insns. */
5599 && i.suffix != BYTE_MNEM_SUFFIX
5600 && i.suffix != XMMWORD_MNEM_SUFFIX
5601 && i.suffix != YMMWORD_MNEM_SUFFIX
5602 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5604 /* It's not a byte, select word/dword operation. */
5605 if (i.tm.opcode_modifier.w)
5607 if (i.tm.opcode_modifier.shortform)
5608 i.tm.base_opcode |= 8;
5610 i.tm.base_opcode |= 1;
5613 /* Now select between word & dword operations via the operand
5614 size prefix, except for instructions that will ignore this
5616 if (i.tm.opcode_modifier.addrprefixop0)
5618 /* The address size override prefix changes the size of the
5620 if ((flag_code == CODE_32BIT
5621 && i.op->regs[0].reg_type.bitfield.word)
5622 || (flag_code != CODE_32BIT
5623 && i.op->regs[0].reg_type.bitfield.dword))
5624 if (!add_prefix (ADDR_PREFIX_OPCODE))
5627 else if (i.suffix != QWORD_MNEM_SUFFIX
5628 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5629 && !i.tm.opcode_modifier.ignoresize
5630 && !i.tm.opcode_modifier.floatmf
5631 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5632 || (flag_code == CODE_64BIT
5633 && i.tm.opcode_modifier.jumpbyte)))
5635 unsigned int prefix = DATA_PREFIX_OPCODE;
5637 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5638 prefix = ADDR_PREFIX_OPCODE;
5640 if (!add_prefix (prefix))
5644 /* Set mode64 for an operand. */
5645 if (i.suffix == QWORD_MNEM_SUFFIX
5646 && flag_code == CODE_64BIT
5647 && !i.tm.opcode_modifier.norex64)
5649 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5650 need rex64. cmpxchg8b is also a special case. */
5651 if (! (i.operands == 2
5652 && i.tm.base_opcode == 0x90
5653 && i.tm.extension_opcode == None
5654 && operand_type_equal (&i.types [0], &acc64)
5655 && operand_type_equal (&i.types [1], &acc64))
5656 && ! (i.operands == 1
5657 && i.tm.base_opcode == 0xfc7
5658 && i.tm.extension_opcode == 1
5659 && !operand_type_check (i.types [0], reg)
5660 && operand_type_check (i.types [0], anymem)))
5664 /* Size floating point instruction. */
5665 if (i.suffix == LONG_MNEM_SUFFIX)
5666 if (i.tm.opcode_modifier.floatmf)
5667 i.tm.base_opcode ^= 4;
5674 check_byte_reg (void)
5678 for (op = i.operands; --op >= 0;)
5680 /* Skip non-register operands. */
5681 if (!i.types[op].bitfield.reg)
5684 /* If this is an eight bit register, it's OK. If it's the 16 or
5685 32 bit version of an eight bit register, we will just use the
5686 low portion, and that's OK too. */
5687 if (i.types[op].bitfield.byte)
5690 /* I/O port address operands are OK too. */
5691 if (i.tm.operand_types[op].bitfield.inoutportreg)
5694 /* crc32 doesn't generate this warning. */
5695 if (i.tm.base_opcode == 0xf20f38f0)
5698 if ((i.types[op].bitfield.word
5699 || i.types[op].bitfield.dword
5700 || i.types[op].bitfield.qword)
5701 && i.op[op].regs->reg_num < 4
5702 /* Prohibit these changes in 64bit mode, since the lowering
5703 would be more complicated. */
5704 && flag_code != CODE_64BIT)
5706 #if REGISTER_WARNINGS
5707 if (!quiet_warnings)
5708 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5710 (i.op[op].regs + (i.types[op].bitfield.word
5711 ? REGNAM_AL - REGNAM_AX
5712 : REGNAM_AL - REGNAM_EAX))->reg_name,
5714 i.op[op].regs->reg_name,
5719 /* Any other register is bad. */
5720 if (i.types[op].bitfield.reg
5721 || i.types[op].bitfield.regmmx
5722 || i.types[op].bitfield.regsimd
5723 || i.types[op].bitfield.sreg2
5724 || i.types[op].bitfield.sreg3
5725 || i.types[op].bitfield.control
5726 || i.types[op].bitfield.debug
5727 || i.types[op].bitfield.test)
5729 as_bad (_("`%s%s' not allowed with `%s%c'"),
5731 i.op[op].regs->reg_name,
5741 check_long_reg (void)
5745 for (op = i.operands; --op >= 0;)
5746 /* Skip non-register operands. */
5747 if (!i.types[op].bitfield.reg)
5749 /* Reject eight bit registers, except where the template requires
5750 them. (eg. movzb) */
5751 else if (i.types[op].bitfield.byte
5752 && (i.tm.operand_types[op].bitfield.reg
5753 || i.tm.operand_types[op].bitfield.acc)
5754 && (i.tm.operand_types[op].bitfield.word
5755 || i.tm.operand_types[op].bitfield.dword))
5757 as_bad (_("`%s%s' not allowed with `%s%c'"),
5759 i.op[op].regs->reg_name,
5764 /* Warn if the e prefix on a general reg is missing. */
5765 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5766 && i.types[op].bitfield.word
5767 && (i.tm.operand_types[op].bitfield.reg
5768 || i.tm.operand_types[op].bitfield.acc)
5769 && i.tm.operand_types[op].bitfield.dword)
5771 /* Prohibit these changes in the 64bit mode, since the
5772 lowering is more complicated. */
5773 if (flag_code == CODE_64BIT)
5775 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5776 register_prefix, i.op[op].regs->reg_name,
5780 #if REGISTER_WARNINGS
5781 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5783 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5784 register_prefix, i.op[op].regs->reg_name, i.suffix);
5787 /* Warn if the r prefix on a general reg is present. */
5788 else if (i.types[op].bitfield.qword
5789 && (i.tm.operand_types[op].bitfield.reg
5790 || i.tm.operand_types[op].bitfield.acc)
5791 && i.tm.operand_types[op].bitfield.dword)
5794 && i.tm.opcode_modifier.toqword
5795 && !i.types[0].bitfield.regsimd)
5797 /* Convert to QWORD. We want REX byte. */
5798 i.suffix = QWORD_MNEM_SUFFIX;
5802 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5803 register_prefix, i.op[op].regs->reg_name,
5812 check_qword_reg (void)
5816 for (op = i.operands; --op >= 0; )
5817 /* Skip non-register operands. */
5818 if (!i.types[op].bitfield.reg)
5820 /* Reject eight bit registers, except where the template requires
5821 them. (eg. movzb) */
5822 else if (i.types[op].bitfield.byte
5823 && (i.tm.operand_types[op].bitfield.reg
5824 || i.tm.operand_types[op].bitfield.acc)
5825 && (i.tm.operand_types[op].bitfield.word
5826 || i.tm.operand_types[op].bitfield.dword))
5828 as_bad (_("`%s%s' not allowed with `%s%c'"),
5830 i.op[op].regs->reg_name,
5835 /* Warn if the r prefix on a general reg is missing. */
5836 else if ((i.types[op].bitfield.word
5837 || i.types[op].bitfield.dword)
5838 && (i.tm.operand_types[op].bitfield.reg
5839 || i.tm.operand_types[op].bitfield.acc)
5840 && i.tm.operand_types[op].bitfield.qword)
5842 /* Prohibit these changes in the 64bit mode, since the
5843 lowering is more complicated. */
5845 && i.tm.opcode_modifier.todword
5846 && !i.types[0].bitfield.regsimd)
5848 /* Convert to DWORD. We don't want REX byte. */
5849 i.suffix = LONG_MNEM_SUFFIX;
5853 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5854 register_prefix, i.op[op].regs->reg_name,
5863 check_word_reg (void)
5866 for (op = i.operands; --op >= 0;)
5867 /* Skip non-register operands. */
5868 if (!i.types[op].bitfield.reg)
5870 /* Reject eight bit registers, except where the template requires
5871 them. (eg. movzb) */
5872 else if (i.types[op].bitfield.byte
5873 && (i.tm.operand_types[op].bitfield.reg
5874 || i.tm.operand_types[op].bitfield.acc)
5875 && (i.tm.operand_types[op].bitfield.word
5876 || i.tm.operand_types[op].bitfield.dword))
5878 as_bad (_("`%s%s' not allowed with `%s%c'"),
5880 i.op[op].regs->reg_name,
5885 /* Warn if the e or r prefix on a general reg is present. */
5886 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5887 && (i.types[op].bitfield.dword
5888 || i.types[op].bitfield.qword)
5889 && (i.tm.operand_types[op].bitfield.reg
5890 || i.tm.operand_types[op].bitfield.acc)
5891 && i.tm.operand_types[op].bitfield.word)
5893 /* Prohibit these changes in the 64bit mode, since the
5894 lowering is more complicated. */
5895 if (flag_code == CODE_64BIT)
5897 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5898 register_prefix, i.op[op].regs->reg_name,
5902 #if REGISTER_WARNINGS
5903 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5905 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5906 register_prefix, i.op[op].regs->reg_name, i.suffix);
5913 update_imm (unsigned int j)
5915 i386_operand_type overlap = i.types[j];
5916 if ((overlap.bitfield.imm8
5917 || overlap.bitfield.imm8s
5918 || overlap.bitfield.imm16
5919 || overlap.bitfield.imm32
5920 || overlap.bitfield.imm32s
5921 || overlap.bitfield.imm64)
5922 && !operand_type_equal (&overlap, &imm8)
5923 && !operand_type_equal (&overlap, &imm8s)
5924 && !operand_type_equal (&overlap, &imm16)
5925 && !operand_type_equal (&overlap, &imm32)
5926 && !operand_type_equal (&overlap, &imm32s)
5927 && !operand_type_equal (&overlap, &imm64))
5931 i386_operand_type temp;
5933 operand_type_set (&temp, 0);
5934 if (i.suffix == BYTE_MNEM_SUFFIX)
5936 temp.bitfield.imm8 = overlap.bitfield.imm8;
5937 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5939 else if (i.suffix == WORD_MNEM_SUFFIX)
5940 temp.bitfield.imm16 = overlap.bitfield.imm16;
5941 else if (i.suffix == QWORD_MNEM_SUFFIX)
5943 temp.bitfield.imm64 = overlap.bitfield.imm64;
5944 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5947 temp.bitfield.imm32 = overlap.bitfield.imm32;
5950 else if (operand_type_equal (&overlap, &imm16_32_32s)
5951 || operand_type_equal (&overlap, &imm16_32)
5952 || operand_type_equal (&overlap, &imm16_32s))
5954 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5959 if (!operand_type_equal (&overlap, &imm8)
5960 && !operand_type_equal (&overlap, &imm8s)
5961 && !operand_type_equal (&overlap, &imm16)
5962 && !operand_type_equal (&overlap, &imm32)
5963 && !operand_type_equal (&overlap, &imm32s)
5964 && !operand_type_equal (&overlap, &imm64))
5966 as_bad (_("no instruction mnemonic suffix given; "
5967 "can't determine immediate size"));
5971 i.types[j] = overlap;
5981 /* Update the first 2 immediate operands. */
5982 n = i.operands > 2 ? 2 : i.operands;
5985 for (j = 0; j < n; j++)
5986 if (update_imm (j) == 0)
5989 /* The 3rd operand can't be immediate operand. */
5990 gas_assert (operand_type_check (i.types[2], imm) == 0);
5997 process_operands (void)
5999 /* Default segment register this instruction will use for memory
6000 accesses. 0 means unknown. This is only for optimizing out
6001 unnecessary segment overrides. */
6002 const seg_entry *default_seg = 0;
6004 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
6006 unsigned int dupl = i.operands;
6007 unsigned int dest = dupl - 1;
6010 /* The destination must be an xmm register. */
6011 gas_assert (i.reg_operands
6012 && MAX_OPERANDS > dupl
6013 && operand_type_equal (&i.types[dest], ®xmm));
6015 if (i.tm.operand_types[0].bitfield.acc
6016 && i.tm.operand_types[0].bitfield.xmmword)
6018 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
6020 /* Keep xmm0 for instructions with VEX prefix and 3
6022 i.tm.operand_types[0].bitfield.acc = 0;
6023 i.tm.operand_types[0].bitfield.regsimd = 1;
6028 /* We remove the first xmm0 and keep the number of
6029 operands unchanged, which in fact duplicates the
6031 for (j = 1; j < i.operands; j++)
6033 i.op[j - 1] = i.op[j];
6034 i.types[j - 1] = i.types[j];
6035 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6039 else if (i.tm.opcode_modifier.implicit1stxmm0)
6041 gas_assert ((MAX_OPERANDS - 1) > dupl
6042 && (i.tm.opcode_modifier.vexsources
6045 /* Add the implicit xmm0 for instructions with VEX prefix
6047 for (j = i.operands; j > 0; j--)
6049 i.op[j] = i.op[j - 1];
6050 i.types[j] = i.types[j - 1];
6051 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6054 = (const reg_entry *) hash_find (reg_hash, "xmm0");
6055 i.types[0] = regxmm;
6056 i.tm.operand_types[0] = regxmm;
6059 i.reg_operands += 2;
6064 i.op[dupl] = i.op[dest];
6065 i.types[dupl] = i.types[dest];
6066 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6075 i.op[dupl] = i.op[dest];
6076 i.types[dupl] = i.types[dest];
6077 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
6080 if (i.tm.opcode_modifier.immext)
6083 else if (i.tm.operand_types[0].bitfield.acc
6084 && i.tm.operand_types[0].bitfield.xmmword)
6088 for (j = 1; j < i.operands; j++)
6090 i.op[j - 1] = i.op[j];
6091 i.types[j - 1] = i.types[j];
6093 /* We need to adjust fields in i.tm since they are used by
6094 build_modrm_byte. */
6095 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6102 else if (i.tm.opcode_modifier.implicitquadgroup)
6104 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6105 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
6106 unsigned int regnum = register_number (i.op[1].regs);
6107 unsigned int first_reg_in_group = regnum & ~3;
6108 unsigned int last_reg_in_group = first_reg_in_group + 3;
6109 if (regnum != first_reg_in_group) {
6110 as_warn (_("the second source register `%s%s' implicitly denotes"
6111 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6112 register_prefix, i.op[1].regs->reg_name,
6113 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6114 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6118 else if (i.tm.opcode_modifier.regkludge)
6120 /* The imul $imm, %reg instruction is converted into
6121 imul $imm, %reg, %reg, and the clr %reg instruction
6122 is converted into xor %reg, %reg. */
6124 unsigned int first_reg_op;
6126 if (operand_type_check (i.types[0], reg))
6130 /* Pretend we saw the extra register operand. */
6131 gas_assert (i.reg_operands == 1
6132 && i.op[first_reg_op + 1].regs == 0);
6133 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6134 i.types[first_reg_op + 1] = i.types[first_reg_op];
6139 if (i.tm.opcode_modifier.shortform)
6141 if (i.types[0].bitfield.sreg2
6142 || i.types[0].bitfield.sreg3)
6144 if (i.tm.base_opcode == POP_SEG_SHORT
6145 && i.op[0].regs->reg_num == 1)
6147 as_bad (_("you can't `pop %scs'"), register_prefix);
6150 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6151 if ((i.op[0].regs->reg_flags & RegRex) != 0)
6156 /* The register or float register operand is in operand
6160 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
6161 || operand_type_check (i.types[0], reg))
6165 /* Register goes in low 3 bits of opcode. */
6166 i.tm.base_opcode |= i.op[op].regs->reg_num;
6167 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6169 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
6171 /* Warn about some common errors, but press on regardless.
6172 The first case can be generated by gcc (<= 2.8.1). */
6173 if (i.operands == 2)
6175 /* Reversed arguments on faddp, fsubp, etc. */
6176 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
6177 register_prefix, i.op[!intel_syntax].regs->reg_name,
6178 register_prefix, i.op[intel_syntax].regs->reg_name);
6182 /* Extraneous `l' suffix on fp insn. */
6183 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6184 register_prefix, i.op[0].regs->reg_name);
6189 else if (i.tm.opcode_modifier.modrm)
6191 /* The opcode is completed (modulo i.tm.extension_opcode which
6192 must be put into the modrm byte). Now, we make the modrm and
6193 index base bytes based on all the info we've collected. */
6195 default_seg = build_modrm_byte ();
6197 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
6201 else if (i.tm.opcode_modifier.isstring)
6203 /* For the string instructions that allow a segment override
6204 on one of their operands, the default segment is ds. */
6208 if (i.tm.base_opcode == 0x8d /* lea */
6211 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
6213 /* If a segment was explicitly specified, and the specified segment
6214 is not the default, use an opcode prefix to select it. If we
6215 never figured out what the default segment is, then default_seg
6216 will be zero at this point, and the specified segment prefix will
6218 if ((i.seg[0]) && (i.seg[0] != default_seg))
6220 if (!add_prefix (i.seg[0]->seg_prefix))
6226 static const seg_entry *
6227 build_modrm_byte (void)
6229 const seg_entry *default_seg = 0;
6230 unsigned int source, dest;
6233 /* The first operand of instructions with VEX prefix and 3 sources
6234 must be VEX_Imm4. */
6235 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
6238 unsigned int nds, reg_slot;
6241 if (i.tm.opcode_modifier.veximmext
6242 && i.tm.opcode_modifier.immext)
6244 dest = i.operands - 2;
6245 gas_assert (dest == 3);
6248 dest = i.operands - 1;
6251 /* There are 2 kinds of instructions:
6252 1. 5 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6254 VexW0 or VexW1. The destination must be either XMM, YMM or
6256 2. 4 operands: 4 register operands or 3 register operands
6257 plus 1 memory operand, VexXDS, and VexImmExt */
6258 gas_assert ((i.reg_operands == 4
6259 || (i.reg_operands == 3 && i.mem_operands == 1))
6260 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6261 && (i.tm.opcode_modifier.veximmext
6262 || (i.imm_operands == 1
6263 && i.types[0].bitfield.vec_imm4
6264 && (i.tm.opcode_modifier.vexw == VEXW0
6265 || i.tm.opcode_modifier.vexw == VEXW1)
6266 && i.tm.operand_types[dest].bitfield.regsimd)));
6268 if (i.imm_operands == 0)
6270 /* When there is no immediate operand, generate an 8bit
6271 immediate operand to encode the first operand. */
6272 exp = &im_expressions[i.imm_operands++];
6273 i.op[i.operands].imms = exp;
6274 i.types[i.operands] = imm8;
6276 /* If VexW1 is set, the first operand is the source and
6277 the second operand is encoded in the immediate operand. */
6278 if (i.tm.opcode_modifier.vexw == VEXW1)
6289 /* FMA swaps REG and NDS. */
6290 if (i.tm.cpu_flags.bitfield.cpufma)
6298 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6299 exp->X_op = O_constant;
6300 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6301 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6305 unsigned int imm_slot;
6307 if (i.tm.opcode_modifier.vexw == VEXW0)
6309 /* If VexW0 is set, the third operand is the source and
6310 the second operand is encoded in the immediate
6317 /* VexW1 is set, the second operand is the source and
6318 the third operand is encoded in the immediate
6324 if (i.tm.opcode_modifier.immext)
6326 /* When ImmExt is set, the immediate byte is the last
6328 imm_slot = i.operands - 1;
6336 /* Turn on Imm8 so that output_imm will generate it. */
6337 i.types[imm_slot].bitfield.imm8 = 1;
6340 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6341 i.op[imm_slot].imms->X_add_number
6342 |= register_number (i.op[reg_slot].regs) << 4;
6343 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6346 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
6347 i.vex.register_specifier = i.op[nds].regs;
6352 /* i.reg_operands MUST be the number of real register operands;
6353 implicit registers do not count. If there are 3 register
6354 operands, it must be a instruction with VexNDS. For a
6355 instruction with VexNDD, the destination register is encoded
6356 in VEX prefix. If there are 4 register operands, it must be
6357 a instruction with VEX prefix and 3 sources. */
6358 if (i.mem_operands == 0
6359 && ((i.reg_operands == 2
6360 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6361 || (i.reg_operands == 3
6362 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6363 || (i.reg_operands == 4 && vex_3_sources)))
6371 /* When there are 3 operands, one of them may be immediate,
6372 which may be the first or the last operand. Otherwise,
6373 the first operand must be shift count register (cl) or it
6374 is an instruction with VexNDS. */
6375 gas_assert (i.imm_operands == 1
6376 || (i.imm_operands == 0
6377 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6378 || i.types[0].bitfield.shiftcount)));
6379 if (operand_type_check (i.types[0], imm)
6380 || i.types[0].bitfield.shiftcount)
6386 /* When there are 4 operands, the first two must be 8bit
6387 immediate operands. The source operand will be the 3rd
6390 For instructions with VexNDS, if the first operand
6391 an imm8, the source operand is the 2nd one. If the last
6392 operand is imm8, the source operand is the first one. */
6393 gas_assert ((i.imm_operands == 2
6394 && i.types[0].bitfield.imm8
6395 && i.types[1].bitfield.imm8)
6396 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6397 && i.imm_operands == 1
6398 && (i.types[0].bitfield.imm8
6399 || i.types[i.operands - 1].bitfield.imm8
6401 if (i.imm_operands == 2)
6405 if (i.types[0].bitfield.imm8)
6412 if (i.tm.opcode_modifier.evex)
6414 /* For EVEX instructions, when there are 5 operands, the
6415 first one must be immediate operand. If the second one
6416 is immediate operand, the source operand is the 3th
6417 one. If the last one is immediate operand, the source
6418 operand is the 2nd one. */
6419 gas_assert (i.imm_operands == 2
6420 && i.tm.opcode_modifier.sae
6421 && operand_type_check (i.types[0], imm));
6422 if (operand_type_check (i.types[1], imm))
6424 else if (operand_type_check (i.types[4], imm))
6438 /* RC/SAE operand could be between DEST and SRC. That happens
6439 when one operand is GPR and the other one is XMM/YMM/ZMM
6441 if (i.rounding && i.rounding->operand == (int) dest)
6444 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6446 /* For instructions with VexNDS, the register-only source
6447 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
6448 register. It is encoded in VEX prefix. We need to
6449 clear RegMem bit before calling operand_type_equal. */
6451 i386_operand_type op;
6454 /* Check register-only source operand when two source
6455 operands are swapped. */
6456 if (!i.tm.operand_types[source].bitfield.baseindex
6457 && i.tm.operand_types[dest].bitfield.baseindex)
6465 op = i.tm.operand_types[vvvv];
6466 op.bitfield.regmem = 0;
6467 if ((dest + 1) >= i.operands
6468 || ((!op.bitfield.reg
6469 || (!op.bitfield.dword && !op.bitfield.qword))
6470 && !op.bitfield.regsimd
6471 && !operand_type_equal (&op, ®mask)))
6473 i.vex.register_specifier = i.op[vvvv].regs;
6479 /* One of the register operands will be encoded in the i.tm.reg
6480 field, the other in the combined i.tm.mode and i.tm.regmem
6481 fields. If no form of this instruction supports a memory
6482 destination operand, then we assume the source operand may
6483 sometimes be a memory operand and so we need to store the
6484 destination in the i.rm.reg field. */
6485 if (!i.tm.operand_types[dest].bitfield.regmem
6486 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6488 i.rm.reg = i.op[dest].regs->reg_num;
6489 i.rm.regmem = i.op[source].regs->reg_num;
6490 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6492 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6494 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6496 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6501 i.rm.reg = i.op[source].regs->reg_num;
6502 i.rm.regmem = i.op[dest].regs->reg_num;
6503 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6505 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6507 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6509 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6512 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6514 if (!i.types[0].bitfield.control
6515 && !i.types[1].bitfield.control)
6517 i.rex &= ~(REX_R | REX_B);
6518 add_prefix (LOCK_PREFIX_OPCODE);
6522 { /* If it's not 2 reg operands... */
6527 unsigned int fake_zero_displacement = 0;
6530 for (op = 0; op < i.operands; op++)
6531 if (operand_type_check (i.types[op], anymem))
6533 gas_assert (op < i.operands);
6535 if (i.tm.opcode_modifier.vecsib)
6537 if (i.index_reg->reg_num == RegEiz
6538 || i.index_reg->reg_num == RegRiz)
6541 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6544 i.sib.base = NO_BASE_REGISTER;
6545 i.sib.scale = i.log2_scale_factor;
6546 i.types[op].bitfield.disp8 = 0;
6547 i.types[op].bitfield.disp16 = 0;
6548 i.types[op].bitfield.disp64 = 0;
6549 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6551 /* Must be 32 bit */
6552 i.types[op].bitfield.disp32 = 1;
6553 i.types[op].bitfield.disp32s = 0;
6557 i.types[op].bitfield.disp32 = 0;
6558 i.types[op].bitfield.disp32s = 1;
6561 i.sib.index = i.index_reg->reg_num;
6562 if ((i.index_reg->reg_flags & RegRex) != 0)
6564 if ((i.index_reg->reg_flags & RegVRex) != 0)
6570 if (i.base_reg == 0)
6573 if (!i.disp_operands)
6574 fake_zero_displacement = 1;
6575 if (i.index_reg == 0)
6577 gas_assert (!i.tm.opcode_modifier.vecsib);
6578 /* Operand is just <disp> */
6579 if (flag_code == CODE_64BIT)
6581 /* 64bit mode overwrites the 32bit absolute
6582 addressing by RIP relative addressing and
6583 absolute addressing is encoded by one of the
6584 redundant SIB forms. */
6585 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6586 i.sib.base = NO_BASE_REGISTER;
6587 i.sib.index = NO_INDEX_REGISTER;
6588 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6589 ? disp32s : disp32);
6591 else if ((flag_code == CODE_16BIT)
6592 ^ (i.prefix[ADDR_PREFIX] != 0))
6594 i.rm.regmem = NO_BASE_REGISTER_16;
6595 i.types[op] = disp16;
6599 i.rm.regmem = NO_BASE_REGISTER;
6600 i.types[op] = disp32;
6603 else if (!i.tm.opcode_modifier.vecsib)
6605 /* !i.base_reg && i.index_reg */
6606 if (i.index_reg->reg_num == RegEiz
6607 || i.index_reg->reg_num == RegRiz)
6608 i.sib.index = NO_INDEX_REGISTER;
6610 i.sib.index = i.index_reg->reg_num;
6611 i.sib.base = NO_BASE_REGISTER;
6612 i.sib.scale = i.log2_scale_factor;
6613 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6614 i.types[op].bitfield.disp8 = 0;
6615 i.types[op].bitfield.disp16 = 0;
6616 i.types[op].bitfield.disp64 = 0;
6617 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6619 /* Must be 32 bit */
6620 i.types[op].bitfield.disp32 = 1;
6621 i.types[op].bitfield.disp32s = 0;
6625 i.types[op].bitfield.disp32 = 0;
6626 i.types[op].bitfield.disp32s = 1;
6628 if ((i.index_reg->reg_flags & RegRex) != 0)
6632 /* RIP addressing for 64bit mode. */
6633 else if (i.base_reg->reg_num == RegRip ||
6634 i.base_reg->reg_num == RegEip)
6636 gas_assert (!i.tm.opcode_modifier.vecsib);
6637 i.rm.regmem = NO_BASE_REGISTER;
6638 i.types[op].bitfield.disp8 = 0;
6639 i.types[op].bitfield.disp16 = 0;
6640 i.types[op].bitfield.disp32 = 0;
6641 i.types[op].bitfield.disp32s = 1;
6642 i.types[op].bitfield.disp64 = 0;
6643 i.flags[op] |= Operand_PCrel;
6644 if (! i.disp_operands)
6645 fake_zero_displacement = 1;
6647 else if (i.base_reg->reg_type.bitfield.word)
6649 gas_assert (!i.tm.opcode_modifier.vecsib);
6650 switch (i.base_reg->reg_num)
6653 if (i.index_reg == 0)
6655 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6656 i.rm.regmem = i.index_reg->reg_num - 6;
6660 if (i.index_reg == 0)
6663 if (operand_type_check (i.types[op], disp) == 0)
6665 /* fake (%bp) into 0(%bp) */
6666 i.types[op].bitfield.disp8 = 1;
6667 fake_zero_displacement = 1;
6670 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6671 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6673 default: /* (%si) -> 4 or (%di) -> 5 */
6674 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6676 i.rm.mode = mode_from_disp_size (i.types[op]);
6678 else /* i.base_reg and 32/64 bit mode */
6680 if (flag_code == CODE_64BIT
6681 && operand_type_check (i.types[op], disp))
6683 i386_operand_type temp;
6684 operand_type_set (&temp, 0);
6685 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6687 if (i.prefix[ADDR_PREFIX] == 0)
6688 i.types[op].bitfield.disp32s = 1;
6690 i.types[op].bitfield.disp32 = 1;
6693 if (!i.tm.opcode_modifier.vecsib)
6694 i.rm.regmem = i.base_reg->reg_num;
6695 if ((i.base_reg->reg_flags & RegRex) != 0)
6697 i.sib.base = i.base_reg->reg_num;
6698 /* x86-64 ignores REX prefix bit here to avoid decoder
6700 if (!(i.base_reg->reg_flags & RegRex)
6701 && (i.base_reg->reg_num == EBP_REG_NUM
6702 || i.base_reg->reg_num == ESP_REG_NUM))
6704 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6706 fake_zero_displacement = 1;
6707 i.types[op].bitfield.disp8 = 1;
6709 i.sib.scale = i.log2_scale_factor;
6710 if (i.index_reg == 0)
6712 gas_assert (!i.tm.opcode_modifier.vecsib);
6713 /* <disp>(%esp) becomes two byte modrm with no index
6714 register. We've already stored the code for esp
6715 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6716 Any base register besides %esp will not use the
6717 extra modrm byte. */
6718 i.sib.index = NO_INDEX_REGISTER;
6720 else if (!i.tm.opcode_modifier.vecsib)
6722 if (i.index_reg->reg_num == RegEiz
6723 || i.index_reg->reg_num == RegRiz)
6724 i.sib.index = NO_INDEX_REGISTER;
6726 i.sib.index = i.index_reg->reg_num;
6727 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6728 if ((i.index_reg->reg_flags & RegRex) != 0)
6733 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6734 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6738 if (!fake_zero_displacement
6742 fake_zero_displacement = 1;
6743 if (i.disp_encoding == disp_encoding_8bit)
6744 i.types[op].bitfield.disp8 = 1;
6746 i.types[op].bitfield.disp32 = 1;
6748 i.rm.mode = mode_from_disp_size (i.types[op]);
6752 if (fake_zero_displacement)
6754 /* Fakes a zero displacement assuming that i.types[op]
6755 holds the correct displacement size. */
6758 gas_assert (i.op[op].disps == 0);
6759 exp = &disp_expressions[i.disp_operands++];
6760 i.op[op].disps = exp;
6761 exp->X_op = O_constant;
6762 exp->X_add_number = 0;
6763 exp->X_add_symbol = (symbolS *) 0;
6764 exp->X_op_symbol = (symbolS *) 0;
6772 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6774 if (operand_type_check (i.types[0], imm))
6775 i.vex.register_specifier = NULL;
6778 /* VEX.vvvv encodes one of the sources when the first
6779 operand is not an immediate. */
6780 if (i.tm.opcode_modifier.vexw == VEXW0)
6781 i.vex.register_specifier = i.op[0].regs;
6783 i.vex.register_specifier = i.op[1].regs;
6786 /* Destination is a XMM register encoded in the ModRM.reg
6788 i.rm.reg = i.op[2].regs->reg_num;
6789 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6792 /* ModRM.rm and VEX.B encodes the other source. */
6793 if (!i.mem_operands)
6797 if (i.tm.opcode_modifier.vexw == VEXW0)
6798 i.rm.regmem = i.op[1].regs->reg_num;
6800 i.rm.regmem = i.op[0].regs->reg_num;
6802 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6806 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6808 i.vex.register_specifier = i.op[2].regs;
6809 if (!i.mem_operands)
6812 i.rm.regmem = i.op[1].regs->reg_num;
6813 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6817 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6818 (if any) based on i.tm.extension_opcode. Again, we must be
6819 careful to make sure that segment/control/debug/test/MMX
6820 registers are coded into the i.rm.reg field. */
6821 else if (i.reg_operands)
6824 unsigned int vex_reg = ~0;
6826 for (op = 0; op < i.operands; op++)
6827 if (i.types[op].bitfield.reg
6828 || i.types[op].bitfield.regmmx
6829 || i.types[op].bitfield.regsimd
6830 || i.types[op].bitfield.regbnd
6831 || i.types[op].bitfield.regmask
6832 || i.types[op].bitfield.sreg2
6833 || i.types[op].bitfield.sreg3
6834 || i.types[op].bitfield.control
6835 || i.types[op].bitfield.debug
6836 || i.types[op].bitfield.test)
6841 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6843 /* For instructions with VexNDS, the register-only
6844 source operand is encoded in VEX prefix. */
6845 gas_assert (mem != (unsigned int) ~0);
6850 gas_assert (op < i.operands);
6854 /* Check register-only source operand when two source
6855 operands are swapped. */
6856 if (!i.tm.operand_types[op].bitfield.baseindex
6857 && i.tm.operand_types[op + 1].bitfield.baseindex)
6861 gas_assert (mem == (vex_reg + 1)
6862 && op < i.operands);
6867 gas_assert (vex_reg < i.operands);
6871 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6873 /* For instructions with VexNDD, the register destination
6874 is encoded in VEX prefix. */
6875 if (i.mem_operands == 0)
6877 /* There is no memory operand. */
6878 gas_assert ((op + 2) == i.operands);
6883 /* There are only 2 operands. */
6884 gas_assert (op < 2 && i.operands == 2);
6889 gas_assert (op < i.operands);
6891 if (vex_reg != (unsigned int) ~0)
6893 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6895 if ((!type->bitfield.reg
6896 || (!type->bitfield.dword && !type->bitfield.qword))
6897 && !type->bitfield.regsimd
6898 && !operand_type_equal (type, ®mask))
6901 i.vex.register_specifier = i.op[vex_reg].regs;
6904 /* Don't set OP operand twice. */
6907 /* If there is an extension opcode to put here, the
6908 register number must be put into the regmem field. */
6909 if (i.tm.extension_opcode != None)
6911 i.rm.regmem = i.op[op].regs->reg_num;
6912 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6914 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6919 i.rm.reg = i.op[op].regs->reg_num;
6920 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6922 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6927 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6928 must set it to 3 to indicate this is a register operand
6929 in the regmem field. */
6930 if (!i.mem_operands)
6934 /* Fill in i.rm.reg field with extension opcode (if any). */
6935 if (i.tm.extension_opcode != None)
6936 i.rm.reg = i.tm.extension_opcode;
6942 output_branch (void)
6948 relax_substateT subtype;
6952 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6953 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6956 if (i.prefix[DATA_PREFIX] != 0)
6962 /* Pentium4 branch hints. */
6963 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6964 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6969 if (i.prefix[REX_PREFIX] != 0)
6975 /* BND prefixed jump. */
6976 if (i.prefix[BND_PREFIX] != 0)
6978 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6982 if (i.prefixes != 0 && !intel_syntax)
6983 as_warn (_("skipping prefixes on this instruction"));
6985 /* It's always a symbol; End frag & setup for relax.
6986 Make sure there is enough room in this frag for the largest
6987 instruction we may generate in md_convert_frag. This is 2
6988 bytes for the opcode and room for the prefix and largest
6990 frag_grow (prefix + 2 + 4);
6991 /* Prefix and 1 opcode byte go in fr_fix. */
6992 p = frag_more (prefix + 1);
6993 if (i.prefix[DATA_PREFIX] != 0)
6994 *p++ = DATA_PREFIX_OPCODE;
6995 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6996 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6997 *p++ = i.prefix[SEG_PREFIX];
6998 if (i.prefix[REX_PREFIX] != 0)
6999 *p++ = i.prefix[REX_PREFIX];
7000 *p = i.tm.base_opcode;
7002 if ((unsigned char) *p == JUMP_PC_RELATIVE)
7003 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
7004 else if (cpu_arch_flags.bitfield.cpui386)
7005 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
7007 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
7010 sym = i.op[0].disps->X_add_symbol;
7011 off = i.op[0].disps->X_add_number;
7013 if (i.op[0].disps->X_op != O_constant
7014 && i.op[0].disps->X_op != O_symbol)
7016 /* Handle complex expressions. */
7017 sym = make_expr_symbol (i.op[0].disps);
7021 /* 1 possible extra opcode + 4 byte displacement go in var part.
7022 Pass reloc in fr_var. */
7023 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
7026 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7027 /* Return TRUE iff PLT32 relocation should be used for branching to
7031 need_plt32_p (symbolS *s)
7033 /* PLT32 relocation is ELF only. */
7037 /* Since there is no need to prepare for PLT branch on x86-64, we
7038 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7039 be used as a marker for 32-bit PC-relative branches. */
7043 /* Weak or undefined symbol need PLT32 relocation. */
7044 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7047 /* Non-global symbol doesn't need PLT32 relocation. */
7048 if (! S_IS_EXTERNAL (s))
7051 /* Other global symbols need PLT32 relocation. NB: Symbol with
7052 non-default visibilities are treated as normal global symbol
7053 so that PLT32 relocation can be used as a marker for 32-bit
7054 PC-relative branches. It is useful for linker relaxation. */
7065 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
7067 if (i.tm.opcode_modifier.jumpbyte)
7069 /* This is a loop or jecxz type instruction. */
7071 if (i.prefix[ADDR_PREFIX] != 0)
7073 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7076 /* Pentium4 branch hints. */
7077 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7078 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7080 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7089 if (flag_code == CODE_16BIT)
7092 if (i.prefix[DATA_PREFIX] != 0)
7094 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7104 if (i.prefix[REX_PREFIX] != 0)
7106 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7110 /* BND prefixed jump. */
7111 if (i.prefix[BND_PREFIX] != 0)
7113 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7117 if (i.prefixes != 0 && !intel_syntax)
7118 as_warn (_("skipping prefixes on this instruction"));
7120 p = frag_more (i.tm.opcode_length + size);
7121 switch (i.tm.opcode_length)
7124 *p++ = i.tm.base_opcode >> 8;
7127 *p++ = i.tm.base_opcode;
7133 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7135 && jump_reloc == NO_RELOC
7136 && need_plt32_p (i.op[0].disps->X_add_symbol))
7137 jump_reloc = BFD_RELOC_X86_64_PLT32;
7140 jump_reloc = reloc (size, 1, 1, jump_reloc);
7142 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7143 i.op[0].disps, 1, jump_reloc);
7145 /* All jumps handled here are signed, but don't use a signed limit
7146 check for 32 and 16 bit jumps as we want to allow wrap around at
7147 4G and 64k respectively. */
7149 fixP->fx_signed = 1;
7153 output_interseg_jump (void)
7161 if (flag_code == CODE_16BIT)
7165 if (i.prefix[DATA_PREFIX] != 0)
7171 if (i.prefix[REX_PREFIX] != 0)
7181 if (i.prefixes != 0 && !intel_syntax)
7182 as_warn (_("skipping prefixes on this instruction"));
7184 /* 1 opcode; 2 segment; offset */
7185 p = frag_more (prefix + 1 + 2 + size);
7187 if (i.prefix[DATA_PREFIX] != 0)
7188 *p++ = DATA_PREFIX_OPCODE;
7190 if (i.prefix[REX_PREFIX] != 0)
7191 *p++ = i.prefix[REX_PREFIX];
7193 *p++ = i.tm.base_opcode;
7194 if (i.op[1].imms->X_op == O_constant)
7196 offsetT n = i.op[1].imms->X_add_number;
7199 && !fits_in_unsigned_word (n)
7200 && !fits_in_signed_word (n))
7202 as_bad (_("16-bit jump out of range"));
7205 md_number_to_chars (p, n, size);
7208 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7209 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
7210 if (i.op[0].imms->X_op != O_constant)
7211 as_bad (_("can't handle non absolute segment in `%s'"),
7213 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7219 fragS *insn_start_frag;
7220 offsetT insn_start_off;
7222 /* Tie dwarf2 debug info to the address at the start of the insn.
7223 We can't do this after the insn has been output as the current
7224 frag may have been closed off. eg. by frag_var. */
7225 dwarf2_emit_insn (0);
7227 insn_start_frag = frag_now;
7228 insn_start_off = frag_now_fix ();
7231 if (i.tm.opcode_modifier.jump)
7233 else if (i.tm.opcode_modifier.jumpbyte
7234 || i.tm.opcode_modifier.jumpdword)
7236 else if (i.tm.opcode_modifier.jumpintersegment)
7237 output_interseg_jump ();
7240 /* Output normal instructions here. */
7244 unsigned int prefix;
7247 && i.tm.base_opcode == 0xfae
7249 && i.imm_operands == 1
7250 && (i.op[0].imms->X_add_number == 0xe8
7251 || i.op[0].imms->X_add_number == 0xf0
7252 || i.op[0].imms->X_add_number == 0xf8))
7254 /* Encode lfence, mfence, and sfence as
7255 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7256 offsetT val = 0x240483f0ULL;
7258 md_number_to_chars (p, val, 5);
7262 /* Some processors fail on LOCK prefix. This options makes
7263 assembler ignore LOCK prefix and serves as a workaround. */
7264 if (omit_lock_prefix)
7266 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7268 i.prefix[LOCK_PREFIX] = 0;
7271 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7272 don't need the explicit prefix. */
7273 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
7275 switch (i.tm.opcode_length)
7278 if (i.tm.base_opcode & 0xff000000)
7280 prefix = (i.tm.base_opcode >> 24) & 0xff;
7285 if ((i.tm.base_opcode & 0xff0000) != 0)
7287 prefix = (i.tm.base_opcode >> 16) & 0xff;
7288 if (i.tm.cpu_flags.bitfield.cpupadlock)
7291 if (prefix != REPE_PREFIX_OPCODE
7292 || (i.prefix[REP_PREFIX]
7293 != REPE_PREFIX_OPCODE))
7294 add_prefix (prefix);
7297 add_prefix (prefix);
7303 /* Check for pseudo prefixes. */
7304 as_bad_where (insn_start_frag->fr_file,
7305 insn_start_frag->fr_line,
7306 _("pseudo prefix without instruction"));
7312 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7313 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7314 R_X86_64_GOTTPOFF relocation so that linker can safely
7315 perform IE->LE optimization. */
7316 if (x86_elf_abi == X86_64_X32_ABI
7318 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7319 && i.prefix[REX_PREFIX] == 0)
7320 add_prefix (REX_OPCODE);
7323 /* The prefix bytes. */
7324 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7326 FRAG_APPEND_1_CHAR (*q);
7330 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7335 /* REX byte is encoded in VEX prefix. */
7339 FRAG_APPEND_1_CHAR (*q);
7342 /* There should be no other prefixes for instructions
7347 /* For EVEX instructions i.vrex should become 0 after
7348 build_evex_prefix. For VEX instructions upper 16 registers
7349 aren't available, so VREX should be 0. */
7352 /* Now the VEX prefix. */
7353 p = frag_more (i.vex.length);
7354 for (j = 0; j < i.vex.length; j++)
7355 p[j] = i.vex.bytes[j];
7358 /* Now the opcode; be careful about word order here! */
7359 if (i.tm.opcode_length == 1)
7361 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7365 switch (i.tm.opcode_length)
7369 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7370 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7374 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7384 /* Put out high byte first: can't use md_number_to_chars! */
7385 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7386 *p = i.tm.base_opcode & 0xff;
7389 /* Now the modrm byte and sib byte (if present). */
7390 if (i.tm.opcode_modifier.modrm)
7392 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7395 /* If i.rm.regmem == ESP (4)
7396 && i.rm.mode != (Register mode)
7398 ==> need second modrm byte. */
7399 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7401 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
7402 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7404 | i.sib.scale << 6));
7407 if (i.disp_operands)
7408 output_disp (insn_start_frag, insn_start_off);
7411 output_imm (insn_start_frag, insn_start_off);
7417 pi ("" /*line*/, &i);
7419 #endif /* DEBUG386 */
7422 /* Return the size of the displacement operand N. */
7425 disp_size (unsigned int n)
7429 if (i.types[n].bitfield.disp64)
7431 else if (i.types[n].bitfield.disp8)
7433 else if (i.types[n].bitfield.disp16)
7438 /* Return the size of the immediate operand N. */
7441 imm_size (unsigned int n)
7444 if (i.types[n].bitfield.imm64)
7446 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7448 else if (i.types[n].bitfield.imm16)
7454 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7459 for (n = 0; n < i.operands; n++)
7461 if (operand_type_check (i.types[n], disp))
7463 if (i.op[n].disps->X_op == O_constant)
7465 int size = disp_size (n);
7466 offsetT val = i.op[n].disps->X_add_number;
7468 val = offset_in_range (val >> i.memshift, size);
7469 p = frag_more (size);
7470 md_number_to_chars (p, val, size);
7474 enum bfd_reloc_code_real reloc_type;
7475 int size = disp_size (n);
7476 int sign = i.types[n].bitfield.disp32s;
7477 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7480 /* We can't have 8 bit displacement here. */
7481 gas_assert (!i.types[n].bitfield.disp8);
7483 /* The PC relative address is computed relative
7484 to the instruction boundary, so in case immediate
7485 fields follows, we need to adjust the value. */
7486 if (pcrel && i.imm_operands)
7491 for (n1 = 0; n1 < i.operands; n1++)
7492 if (operand_type_check (i.types[n1], imm))
7494 /* Only one immediate is allowed for PC
7495 relative address. */
7496 gas_assert (sz == 0);
7498 i.op[n].disps->X_add_number -= sz;
7500 /* We should find the immediate. */
7501 gas_assert (sz != 0);
7504 p = frag_more (size);
7505 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
7507 && GOT_symbol == i.op[n].disps->X_add_symbol
7508 && (((reloc_type == BFD_RELOC_32
7509 || reloc_type == BFD_RELOC_X86_64_32S
7510 || (reloc_type == BFD_RELOC_64
7512 && (i.op[n].disps->X_op == O_symbol
7513 || (i.op[n].disps->X_op == O_add
7514 && ((symbol_get_value_expression
7515 (i.op[n].disps->X_op_symbol)->X_op)
7517 || reloc_type == BFD_RELOC_32_PCREL))
7521 if (insn_start_frag == frag_now)
7522 add = (p - frag_now->fr_literal) - insn_start_off;
7527 add = insn_start_frag->fr_fix - insn_start_off;
7528 for (fr = insn_start_frag->fr_next;
7529 fr && fr != frag_now; fr = fr->fr_next)
7531 add += p - frag_now->fr_literal;
7536 reloc_type = BFD_RELOC_386_GOTPC;
7537 i.op[n].imms->X_add_number += add;
7539 else if (reloc_type == BFD_RELOC_64)
7540 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7542 /* Don't do the adjustment for x86-64, as there
7543 the pcrel addressing is relative to the _next_
7544 insn, and that is taken care of in other code. */
7545 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7547 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7548 size, i.op[n].disps, pcrel,
7550 /* Check for "call/jmp *mem", "mov mem, %reg",
7551 "test %reg, mem" and "binop mem, %reg" where binop
7552 is one of adc, add, and, cmp, or, sbb, sub, xor
7553 instructions. Always generate R_386_GOT32X for
7554 "sym*GOT" operand in 32-bit mode. */
7555 if ((generate_relax_relocations
7558 && i.rm.regmem == 5))
7560 || (i.rm.mode == 0 && i.rm.regmem == 5))
7561 && ((i.operands == 1
7562 && i.tm.base_opcode == 0xff
7563 && (i.rm.reg == 2 || i.rm.reg == 4))
7565 && (i.tm.base_opcode == 0x8b
7566 || i.tm.base_opcode == 0x85
7567 || (i.tm.base_opcode & 0xc7) == 0x03))))
7571 fixP->fx_tcbit = i.rex != 0;
7573 && (i.base_reg->reg_num == RegRip
7574 || i.base_reg->reg_num == RegEip))
7575 fixP->fx_tcbit2 = 1;
7578 fixP->fx_tcbit2 = 1;
7586 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7591 for (n = 0; n < i.operands; n++)
7593 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7594 if (i.rounding && (int) n == i.rounding->operand)
7597 if (operand_type_check (i.types[n], imm))
7599 if (i.op[n].imms->X_op == O_constant)
7601 int size = imm_size (n);
7604 val = offset_in_range (i.op[n].imms->X_add_number,
7606 p = frag_more (size);
7607 md_number_to_chars (p, val, size);
7611 /* Not absolute_section.
7612 Need a 32-bit fixup (don't support 8bit
7613 non-absolute imms). Try to support other
7615 enum bfd_reloc_code_real reloc_type;
7616 int size = imm_size (n);
7619 if (i.types[n].bitfield.imm32s
7620 && (i.suffix == QWORD_MNEM_SUFFIX
7621 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7626 p = frag_more (size);
7627 reloc_type = reloc (size, 0, sign, i.reloc[n]);
7629 /* This is tough to explain. We end up with this one if we
7630 * have operands that look like
7631 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7632 * obtain the absolute address of the GOT, and it is strongly
7633 * preferable from a performance point of view to avoid using
7634 * a runtime relocation for this. The actual sequence of
7635 * instructions often look something like:
7640 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7642 * The call and pop essentially return the absolute address
7643 * of the label .L66 and store it in %ebx. The linker itself
7644 * will ultimately change the first operand of the addl so
7645 * that %ebx points to the GOT, but to keep things simple, the
7646 * .o file must have this operand set so that it generates not
7647 * the absolute address of .L66, but the absolute address of
7648 * itself. This allows the linker itself simply treat a GOTPC
7649 * relocation as asking for a pcrel offset to the GOT to be
7650 * added in, and the addend of the relocation is stored in the
7651 * operand field for the instruction itself.
7653 * Our job here is to fix the operand so that it would add
7654 * the correct offset so that %ebx would point to itself. The
7655 * thing that is tricky is that .-.L66 will point to the
7656 * beginning of the instruction, so we need to further modify
7657 * the operand so that it will point to itself. There are
7658 * other cases where you have something like:
7660 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7662 * and here no correction would be required. Internally in
7663 * the assembler we treat operands of this form as not being
7664 * pcrel since the '.' is explicitly mentioned, and I wonder
7665 * whether it would simplify matters to do it this way. Who
7666 * knows. In earlier versions of the PIC patches, the
7667 * pcrel_adjust field was used to store the correction, but
7668 * since the expression is not pcrel, I felt it would be
7669 * confusing to do it this way. */
7671 if ((reloc_type == BFD_RELOC_32
7672 || reloc_type == BFD_RELOC_X86_64_32S
7673 || reloc_type == BFD_RELOC_64)
7675 && GOT_symbol == i.op[n].imms->X_add_symbol
7676 && (i.op[n].imms->X_op == O_symbol
7677 || (i.op[n].imms->X_op == O_add
7678 && ((symbol_get_value_expression
7679 (i.op[n].imms->X_op_symbol)->X_op)
7684 if (insn_start_frag == frag_now)
7685 add = (p - frag_now->fr_literal) - insn_start_off;
7690 add = insn_start_frag->fr_fix - insn_start_off;
7691 for (fr = insn_start_frag->fr_next;
7692 fr && fr != frag_now; fr = fr->fr_next)
7694 add += p - frag_now->fr_literal;
7698 reloc_type = BFD_RELOC_386_GOTPC;
7700 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7702 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7703 i.op[n].imms->X_add_number += add;
7705 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7706 i.op[n].imms, 0, reloc_type);
7712 /* x86_cons_fix_new is called via the expression parsing code when a
7713 reloc is needed. We use this hook to get the correct .got reloc. */
7714 static int cons_sign = -1;
7717 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7718 expressionS *exp, bfd_reloc_code_real_type r)
7720 r = reloc (len, 0, cons_sign, r);
7723 if (exp->X_op == O_secrel)
7725 exp->X_op = O_symbol;
7726 r = BFD_RELOC_32_SECREL;
7730 fix_new_exp (frag, off, len, exp, 0, r);
7733 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7734 purpose of the `.dc.a' internal pseudo-op. */
7737 x86_address_bytes (void)
7739 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7741 return stdoutput->arch_info->bits_per_address / 8;
7744 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7746 # define lex_got(reloc, adjust, types) NULL
7748 /* Parse operands of the form
7749 <symbol>@GOTOFF+<nnn>
7750 and similar .plt or .got references.
7752 If we find one, set up the correct relocation in RELOC and copy the
7753 input string, minus the `@GOTOFF' into a malloc'd buffer for
7754 parsing by the calling routine. Return this buffer, and if ADJUST
7755 is non-null set it to the length of the string we removed from the
7756 input line. Otherwise return NULL. */
7758 lex_got (enum bfd_reloc_code_real *rel,
7760 i386_operand_type *types)
7762 /* Some of the relocations depend on the size of what field is to
7763 be relocated. But in our callers i386_immediate and i386_displacement
7764 we don't yet know the operand size (this will be set by insn
7765 matching). Hence we record the word32 relocation here,
7766 and adjust the reloc according to the real size in reloc(). */
7767 static const struct {
7770 const enum bfd_reloc_code_real rel[2];
7771 const i386_operand_type types64;
7773 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7774 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7776 OPERAND_TYPE_IMM32_64 },
7778 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7779 BFD_RELOC_X86_64_PLTOFF64 },
7780 OPERAND_TYPE_IMM64 },
7781 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7782 BFD_RELOC_X86_64_PLT32 },
7783 OPERAND_TYPE_IMM32_32S_DISP32 },
7784 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7785 BFD_RELOC_X86_64_GOTPLT64 },
7786 OPERAND_TYPE_IMM64_DISP64 },
7787 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7788 BFD_RELOC_X86_64_GOTOFF64 },
7789 OPERAND_TYPE_IMM64_DISP64 },
7790 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7791 BFD_RELOC_X86_64_GOTPCREL },
7792 OPERAND_TYPE_IMM32_32S_DISP32 },
7793 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7794 BFD_RELOC_X86_64_TLSGD },
7795 OPERAND_TYPE_IMM32_32S_DISP32 },
7796 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7797 _dummy_first_bfd_reloc_code_real },
7798 OPERAND_TYPE_NONE },
7799 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7800 BFD_RELOC_X86_64_TLSLD },
7801 OPERAND_TYPE_IMM32_32S_DISP32 },
7802 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7803 BFD_RELOC_X86_64_GOTTPOFF },
7804 OPERAND_TYPE_IMM32_32S_DISP32 },
7805 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7806 BFD_RELOC_X86_64_TPOFF32 },
7807 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7808 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7809 _dummy_first_bfd_reloc_code_real },
7810 OPERAND_TYPE_NONE },
7811 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7812 BFD_RELOC_X86_64_DTPOFF32 },
7813 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7814 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7815 _dummy_first_bfd_reloc_code_real },
7816 OPERAND_TYPE_NONE },
7817 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7818 _dummy_first_bfd_reloc_code_real },
7819 OPERAND_TYPE_NONE },
7820 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7821 BFD_RELOC_X86_64_GOT32 },
7822 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7823 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7824 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7825 OPERAND_TYPE_IMM32_32S_DISP32 },
7826 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7827 BFD_RELOC_X86_64_TLSDESC_CALL },
7828 OPERAND_TYPE_IMM32_32S_DISP32 },
7833 #if defined (OBJ_MAYBE_ELF)
7838 for (cp = input_line_pointer; *cp != '@'; cp++)
7839 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7842 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7844 int len = gotrel[j].len;
7845 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7847 if (gotrel[j].rel[object_64bit] != 0)
7850 char *tmpbuf, *past_reloc;
7852 *rel = gotrel[j].rel[object_64bit];
7856 if (flag_code != CODE_64BIT)
7858 types->bitfield.imm32 = 1;
7859 types->bitfield.disp32 = 1;
7862 *types = gotrel[j].types64;
7865 if (j != 0 && GOT_symbol == NULL)
7866 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7868 /* The length of the first part of our input line. */
7869 first = cp - input_line_pointer;
7871 /* The second part goes from after the reloc token until
7872 (and including) an end_of_line char or comma. */
7873 past_reloc = cp + 1 + len;
7875 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7877 second = cp + 1 - past_reloc;
7879 /* Allocate and copy string. The trailing NUL shouldn't
7880 be necessary, but be safe. */
7881 tmpbuf = XNEWVEC (char, first + second + 2);
7882 memcpy (tmpbuf, input_line_pointer, first);
7883 if (second != 0 && *past_reloc != ' ')
7884 /* Replace the relocation token with ' ', so that
7885 errors like foo@GOTOFF1 will be detected. */
7886 tmpbuf[first++] = ' ';
7888 /* Increment length by 1 if the relocation token is
7893 memcpy (tmpbuf + first, past_reloc, second);
7894 tmpbuf[first + second] = '\0';
7898 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7899 gotrel[j].str, 1 << (5 + object_64bit));
7904 /* Might be a symbol version string. Don't as_bad here. */
7913 /* Parse operands of the form
7914 <symbol>@SECREL32+<nnn>
7916 If we find one, set up the correct relocation in RELOC and copy the
7917 input string, minus the `@SECREL32' into a malloc'd buffer for
7918 parsing by the calling routine. Return this buffer, and if ADJUST
7919 is non-null set it to the length of the string we removed from the
7920 input line. Otherwise return NULL.
7922 This function is copied from the ELF version above adjusted for PE targets. */
7925 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7926 int *adjust ATTRIBUTE_UNUSED,
7927 i386_operand_type *types)
7933 const enum bfd_reloc_code_real rel[2];
7934 const i386_operand_type types64;
7938 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7939 BFD_RELOC_32_SECREL },
7940 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7946 for (cp = input_line_pointer; *cp != '@'; cp++)
7947 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7950 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7952 int len = gotrel[j].len;
7954 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7956 if (gotrel[j].rel[object_64bit] != 0)
7959 char *tmpbuf, *past_reloc;
7961 *rel = gotrel[j].rel[object_64bit];
7967 if (flag_code != CODE_64BIT)
7969 types->bitfield.imm32 = 1;
7970 types->bitfield.disp32 = 1;
7973 *types = gotrel[j].types64;
7976 /* The length of the first part of our input line. */
7977 first = cp - input_line_pointer;
7979 /* The second part goes from after the reloc token until
7980 (and including) an end_of_line char or comma. */
7981 past_reloc = cp + 1 + len;
7983 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7985 second = cp + 1 - past_reloc;
7987 /* Allocate and copy string. The trailing NUL shouldn't
7988 be necessary, but be safe. */
7989 tmpbuf = XNEWVEC (char, first + second + 2);
7990 memcpy (tmpbuf, input_line_pointer, first);
7991 if (second != 0 && *past_reloc != ' ')
7992 /* Replace the relocation token with ' ', so that
7993 errors like foo@SECLREL321 will be detected. */
7994 tmpbuf[first++] = ' ';
7995 memcpy (tmpbuf + first, past_reloc, second);
7996 tmpbuf[first + second] = '\0';
8000 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8001 gotrel[j].str, 1 << (5 + object_64bit));
8006 /* Might be a symbol version string. Don't as_bad here. */
8012 bfd_reloc_code_real_type
8013 x86_cons (expressionS *exp, int size)
8015 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8017 intel_syntax = -intel_syntax;
8020 if (size == 4 || (object_64bit && size == 8))
8022 /* Handle @GOTOFF and the like in an expression. */
8024 char *gotfree_input_line;
8027 save = input_line_pointer;
8028 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
8029 if (gotfree_input_line)
8030 input_line_pointer = gotfree_input_line;
8034 if (gotfree_input_line)
8036 /* expression () has merrily parsed up to the end of line,
8037 or a comma - in the wrong buffer. Transfer how far
8038 input_line_pointer has moved to the right buffer. */
8039 input_line_pointer = (save
8040 + (input_line_pointer - gotfree_input_line)
8042 free (gotfree_input_line);
8043 if (exp->X_op == O_constant
8044 || exp->X_op == O_absent
8045 || exp->X_op == O_illegal
8046 || exp->X_op == O_register
8047 || exp->X_op == O_big)
8049 char c = *input_line_pointer;
8050 *input_line_pointer = 0;
8051 as_bad (_("missing or invalid expression `%s'"), save);
8052 *input_line_pointer = c;
8059 intel_syntax = -intel_syntax;
8062 i386_intel_simplify (exp);
8068 signed_cons (int size)
8070 if (flag_code == CODE_64BIT)
8078 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
8085 if (exp.X_op == O_symbol)
8086 exp.X_op = O_secrel;
8088 emit_expr (&exp, 4);
8090 while (*input_line_pointer++ == ',');
8092 input_line_pointer--;
8093 demand_empty_rest_of_line ();
8097 /* Handle Vector operations. */
8100 check_VecOperations (char *op_string, char *op_end)
8102 const reg_entry *mask;
8107 && (op_end == NULL || op_string < op_end))
8110 if (*op_string == '{')
8114 /* Check broadcasts. */
8115 if (strncmp (op_string, "1to", 3) == 0)
8120 goto duplicated_vec_op;
8123 if (*op_string == '8')
8124 bcst_type = BROADCAST_1TO8;
8125 else if (*op_string == '4')
8126 bcst_type = BROADCAST_1TO4;
8127 else if (*op_string == '2')
8128 bcst_type = BROADCAST_1TO2;
8129 else if (*op_string == '1'
8130 && *(op_string+1) == '6')
8132 bcst_type = BROADCAST_1TO16;
8137 as_bad (_("Unsupported broadcast: `%s'"), saved);
8142 broadcast_op.type = bcst_type;
8143 broadcast_op.operand = this_operand;
8144 i.broadcast = &broadcast_op;
8146 /* Check masking operation. */
8147 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8149 /* k0 can't be used for write mask. */
8150 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
8152 as_bad (_("`%s%s' can't be used for write mask"),
8153 register_prefix, mask->reg_name);
8159 mask_op.mask = mask;
8160 mask_op.zeroing = 0;
8161 mask_op.operand = this_operand;
8167 goto duplicated_vec_op;
8169 i.mask->mask = mask;
8171 /* Only "{z}" is allowed here. No need to check
8172 zeroing mask explicitly. */
8173 if (i.mask->operand != this_operand)
8175 as_bad (_("invalid write mask `%s'"), saved);
8182 /* Check zeroing-flag for masking operation. */
8183 else if (*op_string == 'z')
8187 mask_op.mask = NULL;
8188 mask_op.zeroing = 1;
8189 mask_op.operand = this_operand;
8194 if (i.mask->zeroing)
8197 as_bad (_("duplicated `%s'"), saved);
8201 i.mask->zeroing = 1;
8203 /* Only "{%k}" is allowed here. No need to check mask
8204 register explicitly. */
8205 if (i.mask->operand != this_operand)
8207 as_bad (_("invalid zeroing-masking `%s'"),
8216 goto unknown_vec_op;
8218 if (*op_string != '}')
8220 as_bad (_("missing `}' in `%s'"), saved);
8227 /* We don't know this one. */
8228 as_bad (_("unknown vector operation: `%s'"), saved);
8232 if (i.mask && i.mask->zeroing && !i.mask->mask)
8234 as_bad (_("zeroing-masking only allowed with write mask"));
8242 i386_immediate (char *imm_start)
8244 char *save_input_line_pointer;
8245 char *gotfree_input_line;
8248 i386_operand_type types;
8250 operand_type_set (&types, ~0);
8252 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8254 as_bad (_("at most %d immediate operands are allowed"),
8255 MAX_IMMEDIATE_OPERANDS);
8259 exp = &im_expressions[i.imm_operands++];
8260 i.op[this_operand].imms = exp;
8262 if (is_space_char (*imm_start))
8265 save_input_line_pointer = input_line_pointer;
8266 input_line_pointer = imm_start;
8268 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8269 if (gotfree_input_line)
8270 input_line_pointer = gotfree_input_line;
8272 exp_seg = expression (exp);
8276 /* Handle vector operations. */
8277 if (*input_line_pointer == '{')
8279 input_line_pointer = check_VecOperations (input_line_pointer,
8281 if (input_line_pointer == NULL)
8285 if (*input_line_pointer)
8286 as_bad (_("junk `%s' after expression"), input_line_pointer);
8288 input_line_pointer = save_input_line_pointer;
8289 if (gotfree_input_line)
8291 free (gotfree_input_line);
8293 if (exp->X_op == O_constant || exp->X_op == O_register)
8294 exp->X_op = O_illegal;
8297 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8301 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8302 i386_operand_type types, const char *imm_start)
8304 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
8307 as_bad (_("missing or invalid immediate expression `%s'"),
8311 else if (exp->X_op == O_constant)
8313 /* Size it properly later. */
8314 i.types[this_operand].bitfield.imm64 = 1;
8315 /* If not 64bit, sign extend val. */
8316 if (flag_code != CODE_64BIT
8317 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8319 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
8321 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8322 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
8323 && exp_seg != absolute_section
8324 && exp_seg != text_section
8325 && exp_seg != data_section
8326 && exp_seg != bss_section
8327 && exp_seg != undefined_section
8328 && !bfd_is_com_section (exp_seg))
8330 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8334 else if (!intel_syntax && exp_seg == reg_section)
8337 as_bad (_("illegal immediate register operand %s"), imm_start);
8342 /* This is an address. The size of the address will be
8343 determined later, depending on destination register,
8344 suffix, or the default for the section. */
8345 i.types[this_operand].bitfield.imm8 = 1;
8346 i.types[this_operand].bitfield.imm16 = 1;
8347 i.types[this_operand].bitfield.imm32 = 1;
8348 i.types[this_operand].bitfield.imm32s = 1;
8349 i.types[this_operand].bitfield.imm64 = 1;
8350 i.types[this_operand] = operand_type_and (i.types[this_operand],
8358 i386_scale (char *scale)
8361 char *save = input_line_pointer;
8363 input_line_pointer = scale;
8364 val = get_absolute_expression ();
8369 i.log2_scale_factor = 0;
8372 i.log2_scale_factor = 1;
8375 i.log2_scale_factor = 2;
8378 i.log2_scale_factor = 3;
8382 char sep = *input_line_pointer;
8384 *input_line_pointer = '\0';
8385 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8387 *input_line_pointer = sep;
8388 input_line_pointer = save;
8392 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8394 as_warn (_("scale factor of %d without an index register"),
8395 1 << i.log2_scale_factor);
8396 i.log2_scale_factor = 0;
8398 scale = input_line_pointer;
8399 input_line_pointer = save;
8404 i386_displacement (char *disp_start, char *disp_end)
8408 char *save_input_line_pointer;
8409 char *gotfree_input_line;
8411 i386_operand_type bigdisp, types = anydisp;
8414 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8416 as_bad (_("at most %d displacement operands are allowed"),
8417 MAX_MEMORY_OPERANDS);
8421 operand_type_set (&bigdisp, 0);
8422 if ((i.types[this_operand].bitfield.jumpabsolute)
8423 || (!current_templates->start->opcode_modifier.jump
8424 && !current_templates->start->opcode_modifier.jumpdword))
8426 bigdisp.bitfield.disp32 = 1;
8427 override = (i.prefix[ADDR_PREFIX] != 0);
8428 if (flag_code == CODE_64BIT)
8432 bigdisp.bitfield.disp32s = 1;
8433 bigdisp.bitfield.disp64 = 1;
8436 else if ((flag_code == CODE_16BIT) ^ override)
8438 bigdisp.bitfield.disp32 = 0;
8439 bigdisp.bitfield.disp16 = 1;
8444 /* For PC-relative branches, the width of the displacement
8445 is dependent upon data size, not address size. */
8446 override = (i.prefix[DATA_PREFIX] != 0);
8447 if (flag_code == CODE_64BIT)
8449 if (override || i.suffix == WORD_MNEM_SUFFIX)
8450 bigdisp.bitfield.disp16 = 1;
8453 bigdisp.bitfield.disp32 = 1;
8454 bigdisp.bitfield.disp32s = 1;
8460 override = (i.suffix == (flag_code != CODE_16BIT
8462 : LONG_MNEM_SUFFIX));
8463 bigdisp.bitfield.disp32 = 1;
8464 if ((flag_code == CODE_16BIT) ^ override)
8466 bigdisp.bitfield.disp32 = 0;
8467 bigdisp.bitfield.disp16 = 1;
8471 i.types[this_operand] = operand_type_or (i.types[this_operand],
8474 exp = &disp_expressions[i.disp_operands];
8475 i.op[this_operand].disps = exp;
8477 save_input_line_pointer = input_line_pointer;
8478 input_line_pointer = disp_start;
8479 END_STRING_AND_SAVE (disp_end);
8481 #ifndef GCC_ASM_O_HACK
8482 #define GCC_ASM_O_HACK 0
8485 END_STRING_AND_SAVE (disp_end + 1);
8486 if (i.types[this_operand].bitfield.baseIndex
8487 && displacement_string_end[-1] == '+')
8489 /* This hack is to avoid a warning when using the "o"
8490 constraint within gcc asm statements.
8493 #define _set_tssldt_desc(n,addr,limit,type) \
8494 __asm__ __volatile__ ( \
8496 "movw %w1,2+%0\n\t" \
8498 "movb %b1,4+%0\n\t" \
8499 "movb %4,5+%0\n\t" \
8500 "movb $0,6+%0\n\t" \
8501 "movb %h1,7+%0\n\t" \
8503 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8505 This works great except that the output assembler ends
8506 up looking a bit weird if it turns out that there is
8507 no offset. You end up producing code that looks like:
8520 So here we provide the missing zero. */
8522 *displacement_string_end = '0';
8525 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
8526 if (gotfree_input_line)
8527 input_line_pointer = gotfree_input_line;
8529 exp_seg = expression (exp);
8532 if (*input_line_pointer)
8533 as_bad (_("junk `%s' after expression"), input_line_pointer);
8535 RESTORE_END_STRING (disp_end + 1);
8537 input_line_pointer = save_input_line_pointer;
8538 if (gotfree_input_line)
8540 free (gotfree_input_line);
8542 if (exp->X_op == O_constant || exp->X_op == O_register)
8543 exp->X_op = O_illegal;
8546 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8548 RESTORE_END_STRING (disp_end);
8554 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8555 i386_operand_type types, const char *disp_start)
8557 i386_operand_type bigdisp;
8560 /* We do this to make sure that the section symbol is in
8561 the symbol table. We will ultimately change the relocation
8562 to be relative to the beginning of the section. */
8563 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8564 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8565 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8567 if (exp->X_op != O_symbol)
8570 if (S_IS_LOCAL (exp->X_add_symbol)
8571 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8572 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8573 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8574 exp->X_op = O_subtract;
8575 exp->X_op_symbol = GOT_symbol;
8576 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8577 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8578 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8579 i.reloc[this_operand] = BFD_RELOC_64;
8581 i.reloc[this_operand] = BFD_RELOC_32;
8584 else if (exp->X_op == O_absent
8585 || exp->X_op == O_illegal
8586 || exp->X_op == O_big)
8589 as_bad (_("missing or invalid displacement expression `%s'"),
8594 else if (flag_code == CODE_64BIT
8595 && !i.prefix[ADDR_PREFIX]
8596 && exp->X_op == O_constant)
8598 /* Since displacement is signed extended to 64bit, don't allow
8599 disp32 and turn off disp32s if they are out of range. */
8600 i.types[this_operand].bitfield.disp32 = 0;
8601 if (!fits_in_signed_long (exp->X_add_number))
8603 i.types[this_operand].bitfield.disp32s = 0;
8604 if (i.types[this_operand].bitfield.baseindex)
8606 as_bad (_("0x%lx out range of signed 32bit displacement"),
8607 (long) exp->X_add_number);
8613 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8614 else if (exp->X_op != O_constant
8615 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8616 && exp_seg != absolute_section
8617 && exp_seg != text_section
8618 && exp_seg != data_section
8619 && exp_seg != bss_section
8620 && exp_seg != undefined_section
8621 && !bfd_is_com_section (exp_seg))
8623 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8628 /* Check if this is a displacement only operand. */
8629 bigdisp = i.types[this_operand];
8630 bigdisp.bitfield.disp8 = 0;
8631 bigdisp.bitfield.disp16 = 0;
8632 bigdisp.bitfield.disp32 = 0;
8633 bigdisp.bitfield.disp32s = 0;
8634 bigdisp.bitfield.disp64 = 0;
8635 if (operand_type_all_zero (&bigdisp))
8636 i.types[this_operand] = operand_type_and (i.types[this_operand],
8642 /* Return the active addressing mode, taking address override and
8643 registers forming the address into consideration. Update the
8644 address override prefix if necessary. */
8646 static enum flag_code
8647 i386_addressing_mode (void)
8649 enum flag_code addr_mode;
8651 if (i.prefix[ADDR_PREFIX])
8652 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8655 addr_mode = flag_code;
8657 #if INFER_ADDR_PREFIX
8658 if (i.mem_operands == 0)
8660 /* Infer address prefix from the first memory operand. */
8661 const reg_entry *addr_reg = i.base_reg;
8663 if (addr_reg == NULL)
8664 addr_reg = i.index_reg;
8668 if (addr_reg->reg_num == RegEip
8669 || addr_reg->reg_num == RegEiz
8670 || addr_reg->reg_type.bitfield.dword)
8671 addr_mode = CODE_32BIT;
8672 else if (flag_code != CODE_64BIT
8673 && addr_reg->reg_type.bitfield.word)
8674 addr_mode = CODE_16BIT;
8676 if (addr_mode != flag_code)
8678 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8680 /* Change the size of any displacement too. At most one
8681 of Disp16 or Disp32 is set.
8682 FIXME. There doesn't seem to be any real need for
8683 separate Disp16 and Disp32 flags. The same goes for
8684 Imm16 and Imm32. Removing them would probably clean
8685 up the code quite a lot. */
8686 if (flag_code != CODE_64BIT
8687 && (i.types[this_operand].bitfield.disp16
8688 || i.types[this_operand].bitfield.disp32))
8689 i.types[this_operand]
8690 = operand_type_xor (i.types[this_operand], disp16_32);
8700 /* Make sure the memory operand we've been dealt is valid.
8701 Return 1 on success, 0 on a failure. */
8704 i386_index_check (const char *operand_string)
8706 const char *kind = "base/index";
8707 enum flag_code addr_mode = i386_addressing_mode ();
8709 if (current_templates->start->opcode_modifier.isstring
8710 && !current_templates->start->opcode_modifier.immext
8711 && (current_templates->end[-1].opcode_modifier.isstring
8714 /* Memory operands of string insns are special in that they only allow
8715 a single register (rDI, rSI, or rBX) as their memory address. */
8716 const reg_entry *expected_reg;
8717 static const char *di_si[][2] =
8723 static const char *bx[] = { "ebx", "bx", "rbx" };
8725 kind = "string address";
8727 if (current_templates->start->opcode_modifier.repprefixok)
8729 i386_operand_type type = current_templates->end[-1].operand_types[0];
8731 if (!type.bitfield.baseindex
8732 || ((!i.mem_operands != !intel_syntax)
8733 && current_templates->end[-1].operand_types[1]
8734 .bitfield.baseindex))
8735 type = current_templates->end[-1].operand_types[1];
8736 expected_reg = hash_find (reg_hash,
8737 di_si[addr_mode][type.bitfield.esseg]);
8741 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8743 if (i.base_reg != expected_reg
8745 || operand_type_check (i.types[this_operand], disp))
8747 /* The second memory operand must have the same size as
8751 && !((addr_mode == CODE_64BIT
8752 && i.base_reg->reg_type.bitfield.qword)
8753 || (addr_mode == CODE_32BIT
8754 ? i.base_reg->reg_type.bitfield.dword
8755 : i.base_reg->reg_type.bitfield.word)))
8758 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8760 intel_syntax ? '[' : '(',
8762 expected_reg->reg_name,
8763 intel_syntax ? ']' : ')');
8770 as_bad (_("`%s' is not a valid %s expression"),
8771 operand_string, kind);
8776 if (addr_mode != CODE_16BIT)
8778 /* 32-bit/64-bit checks. */
8780 && (addr_mode == CODE_64BIT
8781 ? !i.base_reg->reg_type.bitfield.qword
8782 : !i.base_reg->reg_type.bitfield.dword)
8784 || (i.base_reg->reg_num
8785 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8787 && !i.index_reg->reg_type.bitfield.xmmword
8788 && !i.index_reg->reg_type.bitfield.ymmword
8789 && !i.index_reg->reg_type.bitfield.zmmword
8790 && ((addr_mode == CODE_64BIT
8791 ? !(i.index_reg->reg_type.bitfield.qword
8792 || i.index_reg->reg_num == RegRiz)
8793 : !(i.index_reg->reg_type.bitfield.dword
8794 || i.index_reg->reg_num == RegEiz))
8795 || !i.index_reg->reg_type.bitfield.baseindex)))
8798 /* bndmk, bndldx, and bndstx have special restrictions. */
8799 if (current_templates->start->base_opcode == 0xf30f1b
8800 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8802 /* They cannot use RIP-relative addressing. */
8803 if (i.base_reg && i.base_reg->reg_num == RegRip)
8805 as_bad (_("`%s' cannot be used here"), operand_string);
8809 /* bndldx and bndstx ignore their scale factor. */
8810 if (current_templates->start->base_opcode != 0xf30f1b
8811 && i.log2_scale_factor)
8812 as_warn (_("register scaling is being ignored here"));
8817 /* 16-bit checks. */
8819 && (!i.base_reg->reg_type.bitfield.word
8820 || !i.base_reg->reg_type.bitfield.baseindex))
8822 && (!i.index_reg->reg_type.bitfield.word
8823 || !i.index_reg->reg_type.bitfield.baseindex
8825 && i.base_reg->reg_num < 6
8826 && i.index_reg->reg_num >= 6
8827 && i.log2_scale_factor == 0))))
8834 /* Handle vector immediates. */
8837 RC_SAE_immediate (const char *imm_start)
8839 unsigned int match_found, j;
8840 const char *pstr = imm_start;
8848 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8850 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8854 rc_op.type = RC_NamesTable[j].type;
8855 rc_op.operand = this_operand;
8856 i.rounding = &rc_op;
8860 as_bad (_("duplicated `%s'"), imm_start);
8863 pstr += RC_NamesTable[j].len;
8873 as_bad (_("Missing '}': '%s'"), imm_start);
8876 /* RC/SAE immediate string should contain nothing more. */;
8879 as_bad (_("Junk after '}': '%s'"), imm_start);
8883 exp = &im_expressions[i.imm_operands++];
8884 i.op[this_operand].imms = exp;
8886 exp->X_op = O_constant;
8887 exp->X_add_number = 0;
8888 exp->X_add_symbol = (symbolS *) 0;
8889 exp->X_op_symbol = (symbolS *) 0;
8891 i.types[this_operand].bitfield.imm8 = 1;
8895 /* Only string instructions can have a second memory operand, so
8896 reduce current_templates to just those if it contains any. */
8898 maybe_adjust_templates (void)
8900 const insn_template *t;
8902 gas_assert (i.mem_operands == 1);
8904 for (t = current_templates->start; t < current_templates->end; ++t)
8905 if (t->opcode_modifier.isstring)
8908 if (t < current_templates->end)
8910 static templates aux_templates;
8911 bfd_boolean recheck;
8913 aux_templates.start = t;
8914 for (; t < current_templates->end; ++t)
8915 if (!t->opcode_modifier.isstring)
8917 aux_templates.end = t;
8919 /* Determine whether to re-check the first memory operand. */
8920 recheck = (aux_templates.start != current_templates->start
8921 || t != current_templates->end);
8923 current_templates = &aux_templates;
8928 if (i.memop1_string != NULL
8929 && i386_index_check (i.memop1_string) == 0)
8938 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8942 i386_att_operand (char *operand_string)
8946 char *op_string = operand_string;
8948 if (is_space_char (*op_string))
8951 /* We check for an absolute prefix (differentiating,
8952 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8953 if (*op_string == ABSOLUTE_PREFIX)
8956 if (is_space_char (*op_string))
8958 i.types[this_operand].bitfield.jumpabsolute = 1;
8961 /* Check if operand is a register. */
8962 if ((r = parse_register (op_string, &end_op)) != NULL)
8964 i386_operand_type temp;
8966 /* Check for a segment override by searching for ':' after a
8967 segment register. */
8969 if (is_space_char (*op_string))
8971 if (*op_string == ':'
8972 && (r->reg_type.bitfield.sreg2
8973 || r->reg_type.bitfield.sreg3))
8978 i.seg[i.mem_operands] = &es;
8981 i.seg[i.mem_operands] = &cs;
8984 i.seg[i.mem_operands] = &ss;
8987 i.seg[i.mem_operands] = &ds;
8990 i.seg[i.mem_operands] = &fs;
8993 i.seg[i.mem_operands] = &gs;
8997 /* Skip the ':' and whitespace. */
8999 if (is_space_char (*op_string))
9002 if (!is_digit_char (*op_string)
9003 && !is_identifier_char (*op_string)
9004 && *op_string != '('
9005 && *op_string != ABSOLUTE_PREFIX)
9007 as_bad (_("bad memory operand `%s'"), op_string);
9010 /* Handle case of %es:*foo. */
9011 if (*op_string == ABSOLUTE_PREFIX)
9014 if (is_space_char (*op_string))
9016 i.types[this_operand].bitfield.jumpabsolute = 1;
9018 goto do_memory_reference;
9021 /* Handle vector operations. */
9022 if (*op_string == '{')
9024 op_string = check_VecOperations (op_string, NULL);
9025 if (op_string == NULL)
9031 as_bad (_("junk `%s' after register"), op_string);
9035 temp.bitfield.baseindex = 0;
9036 i.types[this_operand] = operand_type_or (i.types[this_operand],
9038 i.types[this_operand].bitfield.unspecified = 0;
9039 i.op[this_operand].regs = r;
9042 else if (*op_string == REGISTER_PREFIX)
9044 as_bad (_("bad register name `%s'"), op_string);
9047 else if (*op_string == IMMEDIATE_PREFIX)
9050 if (i.types[this_operand].bitfield.jumpabsolute)
9052 as_bad (_("immediate operand illegal with absolute jump"));
9055 if (!i386_immediate (op_string))
9058 else if (RC_SAE_immediate (operand_string))
9060 /* If it is a RC or SAE immediate, do nothing. */
9063 else if (is_digit_char (*op_string)
9064 || is_identifier_char (*op_string)
9065 || *op_string == '"'
9066 || *op_string == '(')
9068 /* This is a memory reference of some sort. */
9071 /* Start and end of displacement string expression (if found). */
9072 char *displacement_string_start;
9073 char *displacement_string_end;
9076 do_memory_reference:
9077 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9079 if ((i.mem_operands == 1
9080 && !current_templates->start->opcode_modifier.isstring)
9081 || i.mem_operands == 2)
9083 as_bad (_("too many memory references for `%s'"),
9084 current_templates->start->name);
9088 /* Check for base index form. We detect the base index form by
9089 looking for an ')' at the end of the operand, searching
9090 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9092 base_string = op_string + strlen (op_string);
9094 /* Handle vector operations. */
9095 vop_start = strchr (op_string, '{');
9096 if (vop_start && vop_start < base_string)
9098 if (check_VecOperations (vop_start, base_string) == NULL)
9100 base_string = vop_start;
9104 if (is_space_char (*base_string))
9107 /* If we only have a displacement, set-up for it to be parsed later. */
9108 displacement_string_start = op_string;
9109 displacement_string_end = base_string + 1;
9111 if (*base_string == ')')
9114 unsigned int parens_balanced = 1;
9115 /* We've already checked that the number of left & right ()'s are
9116 equal, so this loop will not be infinite. */
9120 if (*base_string == ')')
9122 if (*base_string == '(')
9125 while (parens_balanced);
9127 temp_string = base_string;
9129 /* Skip past '(' and whitespace. */
9131 if (is_space_char (*base_string))
9134 if (*base_string == ','
9135 || ((i.base_reg = parse_register (base_string, &end_op))
9138 displacement_string_end = temp_string;
9140 i.types[this_operand].bitfield.baseindex = 1;
9144 base_string = end_op;
9145 if (is_space_char (*base_string))
9149 /* There may be an index reg or scale factor here. */
9150 if (*base_string == ',')
9153 if (is_space_char (*base_string))
9156 if ((i.index_reg = parse_register (base_string, &end_op))
9159 base_string = end_op;
9160 if (is_space_char (*base_string))
9162 if (*base_string == ',')
9165 if (is_space_char (*base_string))
9168 else if (*base_string != ')')
9170 as_bad (_("expecting `,' or `)' "
9171 "after index register in `%s'"),
9176 else if (*base_string == REGISTER_PREFIX)
9178 end_op = strchr (base_string, ',');
9181 as_bad (_("bad register name `%s'"), base_string);
9185 /* Check for scale factor. */
9186 if (*base_string != ')')
9188 char *end_scale = i386_scale (base_string);
9193 base_string = end_scale;
9194 if (is_space_char (*base_string))
9196 if (*base_string != ')')
9198 as_bad (_("expecting `)' "
9199 "after scale factor in `%s'"),
9204 else if (!i.index_reg)
9206 as_bad (_("expecting index register or scale factor "
9207 "after `,'; got '%c'"),
9212 else if (*base_string != ')')
9214 as_bad (_("expecting `,' or `)' "
9215 "after base register in `%s'"),
9220 else if (*base_string == REGISTER_PREFIX)
9222 end_op = strchr (base_string, ',');
9225 as_bad (_("bad register name `%s'"), base_string);
9230 /* If there's an expression beginning the operand, parse it,
9231 assuming displacement_string_start and
9232 displacement_string_end are meaningful. */
9233 if (displacement_string_start != displacement_string_end)
9235 if (!i386_displacement (displacement_string_start,
9236 displacement_string_end))
9240 /* Special case for (%dx) while doing input/output op. */
9242 && operand_type_equal (&i.base_reg->reg_type,
9243 ®16_inoutportreg)
9245 && i.log2_scale_factor == 0
9246 && i.seg[i.mem_operands] == 0
9247 && !operand_type_check (i.types[this_operand], disp))
9249 i.types[this_operand] = inoutportreg;
9253 if (i386_index_check (operand_string) == 0)
9255 i.types[this_operand].bitfield.mem = 1;
9256 if (i.mem_operands == 0)
9257 i.memop1_string = xstrdup (operand_string);
9262 /* It's not a memory operand; argh! */
9263 as_bad (_("invalid char %s beginning operand %d `%s'"),
9264 output_invalid (*op_string),
9269 return 1; /* Normal return. */
9272 /* Calculate the maximum variable size (i.e., excluding fr_fix)
9273 that an rs_machine_dependent frag may reach. */
9276 i386_frag_max_var (fragS *frag)
9278 /* The only relaxable frags are for jumps.
9279 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9280 gas_assert (frag->fr_type == rs_machine_dependent);
9281 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9284 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9286 elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
9288 /* STT_GNU_IFUNC symbol must go through PLT. */
9289 if ((symbol_get_bfdsym (fr_symbol)->flags
9290 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9293 if (!S_IS_EXTERNAL (fr_symbol))
9294 /* Symbol may be weak or local. */
9295 return !S_IS_WEAK (fr_symbol);
9297 /* Global symbols with non-default visibility can't be preempted. */
9298 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9301 if (fr_var != NO_RELOC)
9302 switch ((enum bfd_reloc_code_real) fr_var)
9304 case BFD_RELOC_386_PLT32:
9305 case BFD_RELOC_X86_64_PLT32:
9306 /* Symbol with PLT relocation may be preempted. */
9312 /* Global symbols with default visibility in a shared library may be
9313 preempted by another definition. */
9318 /* md_estimate_size_before_relax()
9320 Called just before relax() for rs_machine_dependent frags. The x86
9321 assembler uses these frags to handle variable size jump
9324 Any symbol that is now undefined will not become defined.
9325 Return the correct fr_subtype in the frag.
9326 Return the initial "guess for variable size of frag" to caller.
9327 The guess is actually the growth beyond the fixed part. Whatever
9328 we do to grow the fixed or variable part contributes to our
9332 md_estimate_size_before_relax (fragS *fragP, segT segment)
9334 /* We've already got fragP->fr_subtype right; all we have to do is
9335 check for un-relaxable symbols. On an ELF system, we can't relax
9336 an externally visible symbol, because it may be overridden by a
9338 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
9339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9341 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9344 #if defined (OBJ_COFF) && defined (TE_PE)
9345 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
9346 && S_IS_WEAK (fragP->fr_symbol))
9350 /* Symbol is undefined in this segment, or we need to keep a
9351 reloc so that weak symbols can be overridden. */
9352 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
9353 enum bfd_reloc_code_real reloc_type;
9354 unsigned char *opcode;
9357 if (fragP->fr_var != NO_RELOC)
9358 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
9360 reloc_type = BFD_RELOC_16_PCREL;
9361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9362 else if (need_plt32_p (fragP->fr_symbol))
9363 reloc_type = BFD_RELOC_X86_64_PLT32;
9366 reloc_type = BFD_RELOC_32_PCREL;
9368 old_fr_fix = fragP->fr_fix;
9369 opcode = (unsigned char *) fragP->fr_opcode;
9371 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
9374 /* Make jmp (0xeb) a (d)word displacement jump. */
9376 fragP->fr_fix += size;
9377 fix_new (fragP, old_fr_fix, size,
9379 fragP->fr_offset, 1,
9385 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
9387 /* Negate the condition, and branch past an
9388 unconditional jump. */
9391 /* Insert an unconditional jump. */
9393 /* We added two extra opcode bytes, and have a two byte
9395 fragP->fr_fix += 2 + 2;
9396 fix_new (fragP, old_fr_fix + 2, 2,
9398 fragP->fr_offset, 1,
9405 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9410 fixP = fix_new (fragP, old_fr_fix, 1,
9412 fragP->fr_offset, 1,
9414 fixP->fx_signed = 1;
9418 /* This changes the byte-displacement jump 0x7N
9419 to the (d)word-displacement jump 0x0f,0x8N. */
9420 opcode[1] = opcode[0] + 0x10;
9421 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9422 /* We've added an opcode byte. */
9423 fragP->fr_fix += 1 + size;
9424 fix_new (fragP, old_fr_fix + 1, size,
9426 fragP->fr_offset, 1,
9431 BAD_CASE (fragP->fr_subtype);
9435 return fragP->fr_fix - old_fr_fix;
9438 /* Guess size depending on current relax state. Initially the relax
9439 state will correspond to a short jump and we return 1, because
9440 the variable part of the frag (the branch offset) is one byte
9441 long. However, we can relax a section more than once and in that
9442 case we must either set fr_subtype back to the unrelaxed state,
9443 or return the value for the appropriate branch. */
9444 return md_relax_table[fragP->fr_subtype].rlx_length;
9447 /* Called after relax() is finished.
9449 In: Address of frag.
9450 fr_type == rs_machine_dependent.
9451 fr_subtype is what the address relaxed to.
9453 Out: Any fixSs and constants are set up.
9454 Caller will turn frag into a ".space 0". */
9457 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9460 unsigned char *opcode;
9461 unsigned char *where_to_put_displacement = NULL;
9462 offsetT target_address;
9463 offsetT opcode_address;
9464 unsigned int extension = 0;
9465 offsetT displacement_from_opcode_start;
9467 opcode = (unsigned char *) fragP->fr_opcode;
9469 /* Address we want to reach in file space. */
9470 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9472 /* Address opcode resides at in file space. */
9473 opcode_address = fragP->fr_address + fragP->fr_fix;
9475 /* Displacement from opcode start to fill into instruction. */
9476 displacement_from_opcode_start = target_address - opcode_address;
9478 if ((fragP->fr_subtype & BIG) == 0)
9480 /* Don't have to change opcode. */
9481 extension = 1; /* 1 opcode + 1 displacement */
9482 where_to_put_displacement = &opcode[1];
9486 if (no_cond_jump_promotion
9487 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9488 as_warn_where (fragP->fr_file, fragP->fr_line,
9489 _("long jump required"));
9491 switch (fragP->fr_subtype)
9493 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9494 extension = 4; /* 1 opcode + 4 displacement */
9496 where_to_put_displacement = &opcode[1];
9499 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9500 extension = 2; /* 1 opcode + 2 displacement */
9502 where_to_put_displacement = &opcode[1];
9505 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9506 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9507 extension = 5; /* 2 opcode + 4 displacement */
9508 opcode[1] = opcode[0] + 0x10;
9509 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9510 where_to_put_displacement = &opcode[2];
9513 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9514 extension = 3; /* 2 opcode + 2 displacement */
9515 opcode[1] = opcode[0] + 0x10;
9516 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9517 where_to_put_displacement = &opcode[2];
9520 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9525 where_to_put_displacement = &opcode[3];
9529 BAD_CASE (fragP->fr_subtype);
9534 /* If size if less then four we are sure that the operand fits,
9535 but if it's 4, then it could be that the displacement is larger
9537 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9539 && ((addressT) (displacement_from_opcode_start - extension
9540 + ((addressT) 1 << 31))
9541 > (((addressT) 2 << 31) - 1)))
9543 as_bad_where (fragP->fr_file, fragP->fr_line,
9544 _("jump target out of range"));
9545 /* Make us emit 0. */
9546 displacement_from_opcode_start = extension;
9548 /* Now put displacement after opcode. */
9549 md_number_to_chars ((char *) where_to_put_displacement,
9550 (valueT) (displacement_from_opcode_start - extension),
9551 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9552 fragP->fr_fix += extension;
9555 /* Apply a fixup (fixP) to segment data, once it has been determined
9556 by our caller that we have all the info we need to fix it up.
9558 Parameter valP is the pointer to the value of the bits.
9560 On the 386, immediates, displacements, and data pointers are all in
9561 the same (little-endian) format, so we don't need to care about which
9565 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9567 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9568 valueT value = *valP;
9570 #if !defined (TE_Mach)
9573 switch (fixP->fx_r_type)
9579 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9582 case BFD_RELOC_X86_64_32S:
9583 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9586 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9589 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9594 if (fixP->fx_addsy != NULL
9595 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9596 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9597 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9598 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
9599 && !use_rela_relocations)
9601 /* This is a hack. There should be a better way to handle this.
9602 This covers for the fact that bfd_install_relocation will
9603 subtract the current location (for partial_inplace, PC relative
9604 relocations); see more below. */
9608 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9611 value += fixP->fx_where + fixP->fx_frag->fr_address;
9613 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9616 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9619 || (symbol_section_p (fixP->fx_addsy)
9620 && sym_seg != absolute_section))
9621 && !generic_force_reloc (fixP))
9623 /* Yes, we add the values in twice. This is because
9624 bfd_install_relocation subtracts them out again. I think
9625 bfd_install_relocation is broken, but I don't dare change
9627 value += fixP->fx_where + fixP->fx_frag->fr_address;
9631 #if defined (OBJ_COFF) && defined (TE_PE)
9632 /* For some reason, the PE format does not store a
9633 section address offset for a PC relative symbol. */
9634 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9635 || S_IS_WEAK (fixP->fx_addsy))
9636 value += md_pcrel_from (fixP);
9639 #if defined (OBJ_COFF) && defined (TE_PE)
9640 if (fixP->fx_addsy != NULL
9641 && S_IS_WEAK (fixP->fx_addsy)
9642 /* PR 16858: Do not modify weak function references. */
9643 && ! fixP->fx_pcrel)
9645 #if !defined (TE_PEP)
9646 /* For x86 PE weak function symbols are neither PC-relative
9647 nor do they set S_IS_FUNCTION. So the only reliable way
9648 to detect them is to check the flags of their containing
9650 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9651 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9655 value -= S_GET_VALUE (fixP->fx_addsy);
9659 /* Fix a few things - the dynamic linker expects certain values here,
9660 and we must not disappoint it. */
9661 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9662 if (IS_ELF && fixP->fx_addsy)
9663 switch (fixP->fx_r_type)
9665 case BFD_RELOC_386_PLT32:
9666 case BFD_RELOC_X86_64_PLT32:
9667 /* Make the jump instruction point to the address of the operand. At
9668 runtime we merely add the offset to the actual PLT entry. */
9672 case BFD_RELOC_386_TLS_GD:
9673 case BFD_RELOC_386_TLS_LDM:
9674 case BFD_RELOC_386_TLS_IE_32:
9675 case BFD_RELOC_386_TLS_IE:
9676 case BFD_RELOC_386_TLS_GOTIE:
9677 case BFD_RELOC_386_TLS_GOTDESC:
9678 case BFD_RELOC_X86_64_TLSGD:
9679 case BFD_RELOC_X86_64_TLSLD:
9680 case BFD_RELOC_X86_64_GOTTPOFF:
9681 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9682 value = 0; /* Fully resolved at runtime. No addend. */
9684 case BFD_RELOC_386_TLS_LE:
9685 case BFD_RELOC_386_TLS_LDO_32:
9686 case BFD_RELOC_386_TLS_LE_32:
9687 case BFD_RELOC_X86_64_DTPOFF32:
9688 case BFD_RELOC_X86_64_DTPOFF64:
9689 case BFD_RELOC_X86_64_TPOFF32:
9690 case BFD_RELOC_X86_64_TPOFF64:
9691 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9694 case BFD_RELOC_386_TLS_DESC_CALL:
9695 case BFD_RELOC_X86_64_TLSDESC_CALL:
9696 value = 0; /* Fully resolved at runtime. No addend. */
9697 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9701 case BFD_RELOC_VTABLE_INHERIT:
9702 case BFD_RELOC_VTABLE_ENTRY:
9709 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9711 #endif /* !defined (TE_Mach) */
9713 /* Are we finished with this relocation now? */
9714 if (fixP->fx_addsy == NULL)
9716 #if defined (OBJ_COFF) && defined (TE_PE)
9717 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9720 /* Remember value for tc_gen_reloc. */
9721 fixP->fx_addnumber = value;
9722 /* Clear out the frag for now. */
9726 else if (use_rela_relocations)
9728 fixP->fx_no_overflow = 1;
9729 /* Remember value for tc_gen_reloc. */
9730 fixP->fx_addnumber = value;
9734 md_number_to_chars (p, value, fixP->fx_size);
9738 md_atof (int type, char *litP, int *sizeP)
9740 /* This outputs the LITTLENUMs in REVERSE order;
9741 in accord with the bigendian 386. */
9742 return ieee_md_atof (type, litP, sizeP, FALSE);
9745 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9748 output_invalid (int c)
9751 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9754 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9755 "(0x%x)", (unsigned char) c);
9756 return output_invalid_buf;
9759 /* REG_STRING starts *before* REGISTER_PREFIX. */
9761 static const reg_entry *
9762 parse_real_register (char *reg_string, char **end_op)
9764 char *s = reg_string;
9766 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9769 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9770 if (*s == REGISTER_PREFIX)
9773 if (is_space_char (*s))
9777 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9779 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9780 return (const reg_entry *) NULL;
9784 /* For naked regs, make sure that we are not dealing with an identifier.
9785 This prevents confusing an identifier like `eax_var' with register
9787 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9788 return (const reg_entry *) NULL;
9792 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9794 /* Handle floating point regs, allowing spaces in the (i) part. */
9795 if (r == i386_regtab /* %st is first entry of table */)
9797 if (is_space_char (*s))
9802 if (is_space_char (*s))
9804 if (*s >= '0' && *s <= '7')
9808 if (is_space_char (*s))
9813 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9818 /* We have "%st(" then garbage. */
9819 return (const reg_entry *) NULL;
9823 if (r == NULL || allow_pseudo_reg)
9826 if (operand_type_all_zero (&r->reg_type))
9827 return (const reg_entry *) NULL;
9829 if ((r->reg_type.bitfield.dword
9830 || r->reg_type.bitfield.sreg3
9831 || r->reg_type.bitfield.control
9832 || r->reg_type.bitfield.debug
9833 || r->reg_type.bitfield.test)
9834 && !cpu_arch_flags.bitfield.cpui386)
9835 return (const reg_entry *) NULL;
9837 if (r->reg_type.bitfield.tbyte
9838 && !cpu_arch_flags.bitfield.cpu8087
9839 && !cpu_arch_flags.bitfield.cpu287
9840 && !cpu_arch_flags.bitfield.cpu387)
9841 return (const reg_entry *) NULL;
9843 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
9844 return (const reg_entry *) NULL;
9846 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
9847 return (const reg_entry *) NULL;
9849 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
9850 return (const reg_entry *) NULL;
9852 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
9853 return (const reg_entry *) NULL;
9855 if (r->reg_type.bitfield.regmask
9856 && !cpu_arch_flags.bitfield.cpuregmask)
9857 return (const reg_entry *) NULL;
9859 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9860 if (!allow_index_reg
9861 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9862 return (const reg_entry *) NULL;
9864 /* Upper 16 vector register is only available with VREX in 64bit
9866 if ((r->reg_flags & RegVRex))
9868 if (i.vec_encoding == vex_encoding_default)
9869 i.vec_encoding = vex_encoding_evex;
9871 if (!cpu_arch_flags.bitfield.cpuvrex
9872 || i.vec_encoding != vex_encoding_evex
9873 || flag_code != CODE_64BIT)
9874 return (const reg_entry *) NULL;
9877 if (((r->reg_flags & (RegRex64 | RegRex))
9878 || r->reg_type.bitfield.qword)
9879 && (!cpu_arch_flags.bitfield.cpulm
9880 || !operand_type_equal (&r->reg_type, &control))
9881 && flag_code != CODE_64BIT)
9882 return (const reg_entry *) NULL;
9884 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9885 return (const reg_entry *) NULL;
9890 /* REG_STRING starts *before* REGISTER_PREFIX. */
9892 static const reg_entry *
9893 parse_register (char *reg_string, char **end_op)
9897 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9898 r = parse_real_register (reg_string, end_op);
9903 char *save = input_line_pointer;
9907 input_line_pointer = reg_string;
9908 c = get_symbol_name (®_string);
9909 symbolP = symbol_find (reg_string);
9910 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9912 const expressionS *e = symbol_get_value_expression (symbolP);
9914 know (e->X_op == O_register);
9915 know (e->X_add_number >= 0
9916 && (valueT) e->X_add_number < i386_regtab_size);
9917 r = i386_regtab + e->X_add_number;
9918 if ((r->reg_flags & RegVRex))
9919 i.vec_encoding = vex_encoding_evex;
9920 *end_op = input_line_pointer;
9922 *input_line_pointer = c;
9923 input_line_pointer = save;
9929 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9932 char *end = input_line_pointer;
9935 r = parse_register (name, &input_line_pointer);
9936 if (r && end <= input_line_pointer)
9938 *nextcharP = *input_line_pointer;
9939 *input_line_pointer = 0;
9940 e->X_op = O_register;
9941 e->X_add_number = r - i386_regtab;
9944 input_line_pointer = end;
9946 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9950 md_operand (expressionS *e)
9955 switch (*input_line_pointer)
9957 case REGISTER_PREFIX:
9958 r = parse_real_register (input_line_pointer, &end);
9961 e->X_op = O_register;
9962 e->X_add_number = r - i386_regtab;
9963 input_line_pointer = end;
9968 gas_assert (intel_syntax);
9969 end = input_line_pointer++;
9971 if (*input_line_pointer == ']')
9973 ++input_line_pointer;
9974 e->X_op_symbol = make_expr_symbol (e);
9975 e->X_add_symbol = NULL;
9976 e->X_add_number = 0;
9982 input_line_pointer = end;
9989 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9990 const char *md_shortopts = "kVQ:sqn";
9992 const char *md_shortopts = "qn";
9995 #define OPTION_32 (OPTION_MD_BASE + 0)
9996 #define OPTION_64 (OPTION_MD_BASE + 1)
9997 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9998 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9999 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
10000 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10001 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10002 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10003 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
10004 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
10005 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
10006 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
10007 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10008 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10009 #define OPTION_X32 (OPTION_MD_BASE + 14)
10010 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
10011 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10012 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
10013 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
10014 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
10015 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
10016 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
10017 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10018 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
10019 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
10020 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
10022 struct option md_longopts[] =
10024 {"32", no_argument, NULL, OPTION_32},
10025 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10026 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10027 {"64", no_argument, NULL, OPTION_64},
10029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10030 {"x32", no_argument, NULL, OPTION_X32},
10031 {"mshared", no_argument, NULL, OPTION_MSHARED},
10033 {"divide", no_argument, NULL, OPTION_DIVIDE},
10034 {"march", required_argument, NULL, OPTION_MARCH},
10035 {"mtune", required_argument, NULL, OPTION_MTUNE},
10036 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10037 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10038 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10039 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10040 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
10041 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
10042 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
10043 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
10044 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
10045 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
10046 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10047 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
10048 # if defined (TE_PE) || defined (TE_PEP)
10049 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10051 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
10052 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
10053 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
10054 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
10055 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10056 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
10057 {NULL, no_argument, NULL, 0}
10059 size_t md_longopts_size = sizeof (md_longopts);
10062 md_parse_option (int c, const char *arg)
10065 char *arch, *next, *saved;
10070 optimize_align_code = 0;
10074 quiet_warnings = 1;
10077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10079 should be emitted or not. FIXME: Not implemented. */
10083 /* -V: SVR4 argument to print version ID. */
10085 print_version_id ();
10088 /* -k: Ignore for FreeBSD compatibility. */
10093 /* -s: On i386 Solaris, this tells the native assembler to use
10094 .stab instead of .stab.excl. We always use .stab anyhow. */
10097 case OPTION_MSHARED:
10101 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10102 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10105 const char **list, **l;
10107 list = bfd_target_list ();
10108 for (l = list; *l != NULL; l++)
10109 if (CONST_STRNEQ (*l, "elf64-x86-64")
10110 || strcmp (*l, "coff-x86-64") == 0
10111 || strcmp (*l, "pe-x86-64") == 0
10112 || strcmp (*l, "pei-x86-64") == 0
10113 || strcmp (*l, "mach-o-x86-64") == 0)
10115 default_arch = "x86_64";
10119 as_fatal (_("no compiled in support for x86_64"));
10125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10129 const char **list, **l;
10131 list = bfd_target_list ();
10132 for (l = list; *l != NULL; l++)
10133 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10135 default_arch = "x86_64:32";
10139 as_fatal (_("no compiled in support for 32bit x86_64"));
10143 as_fatal (_("32bit x86_64 is only supported for ELF"));
10148 default_arch = "i386";
10151 case OPTION_DIVIDE:
10152 #ifdef SVR4_COMMENT_CHARS
10157 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
10159 for (s = i386_comment_chars; *s != '\0'; s++)
10163 i386_comment_chars = n;
10169 saved = xstrdup (arg);
10171 /* Allow -march=+nosse. */
10177 as_fatal (_("invalid -march= option: `%s'"), arg);
10178 next = strchr (arch, '+');
10181 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10183 if (strcmp (arch, cpu_arch [j].name) == 0)
10186 if (! cpu_arch[j].flags.bitfield.cpui386)
10189 cpu_arch_name = cpu_arch[j].name;
10190 cpu_sub_arch_name = NULL;
10191 cpu_arch_flags = cpu_arch[j].flags;
10192 cpu_arch_isa = cpu_arch[j].type;
10193 cpu_arch_isa_flags = cpu_arch[j].flags;
10194 if (!cpu_arch_tune_set)
10196 cpu_arch_tune = cpu_arch_isa;
10197 cpu_arch_tune_flags = cpu_arch_isa_flags;
10201 else if (*cpu_arch [j].name == '.'
10202 && strcmp (arch, cpu_arch [j].name + 1) == 0)
10204 /* ISA extension. */
10205 i386_cpu_flags flags;
10207 flags = cpu_flags_or (cpu_arch_flags,
10208 cpu_arch[j].flags);
10210 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10212 if (cpu_sub_arch_name)
10214 char *name = cpu_sub_arch_name;
10215 cpu_sub_arch_name = concat (name,
10217 (const char *) NULL);
10221 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
10222 cpu_arch_flags = flags;
10223 cpu_arch_isa_flags = flags;
10229 if (j >= ARRAY_SIZE (cpu_arch))
10231 /* Disable an ISA extension. */
10232 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10233 if (strcmp (arch, cpu_noarch [j].name) == 0)
10235 i386_cpu_flags flags;
10237 flags = cpu_flags_and_not (cpu_arch_flags,
10238 cpu_noarch[j].flags);
10239 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10241 if (cpu_sub_arch_name)
10243 char *name = cpu_sub_arch_name;
10244 cpu_sub_arch_name = concat (arch,
10245 (const char *) NULL);
10249 cpu_sub_arch_name = xstrdup (arch);
10250 cpu_arch_flags = flags;
10251 cpu_arch_isa_flags = flags;
10256 if (j >= ARRAY_SIZE (cpu_noarch))
10257 j = ARRAY_SIZE (cpu_arch);
10260 if (j >= ARRAY_SIZE (cpu_arch))
10261 as_fatal (_("invalid -march= option: `%s'"), arg);
10265 while (next != NULL);
10271 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10272 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10274 if (strcmp (arg, cpu_arch [j].name) == 0)
10276 cpu_arch_tune_set = 1;
10277 cpu_arch_tune = cpu_arch [j].type;
10278 cpu_arch_tune_flags = cpu_arch[j].flags;
10282 if (j >= ARRAY_SIZE (cpu_arch))
10283 as_fatal (_("invalid -mtune= option: `%s'"), arg);
10286 case OPTION_MMNEMONIC:
10287 if (strcasecmp (arg, "att") == 0)
10288 intel_mnemonic = 0;
10289 else if (strcasecmp (arg, "intel") == 0)
10290 intel_mnemonic = 1;
10292 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
10295 case OPTION_MSYNTAX:
10296 if (strcasecmp (arg, "att") == 0)
10298 else if (strcasecmp (arg, "intel") == 0)
10301 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
10304 case OPTION_MINDEX_REG:
10305 allow_index_reg = 1;
10308 case OPTION_MNAKED_REG:
10309 allow_naked_reg = 1;
10312 case OPTION_MOLD_GCC:
10316 case OPTION_MSSE2AVX:
10320 case OPTION_MSSE_CHECK:
10321 if (strcasecmp (arg, "error") == 0)
10322 sse_check = check_error;
10323 else if (strcasecmp (arg, "warning") == 0)
10324 sse_check = check_warning;
10325 else if (strcasecmp (arg, "none") == 0)
10326 sse_check = check_none;
10328 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
10331 case OPTION_MOPERAND_CHECK:
10332 if (strcasecmp (arg, "error") == 0)
10333 operand_check = check_error;
10334 else if (strcasecmp (arg, "warning") == 0)
10335 operand_check = check_warning;
10336 else if (strcasecmp (arg, "none") == 0)
10337 operand_check = check_none;
10339 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10342 case OPTION_MAVXSCALAR:
10343 if (strcasecmp (arg, "128") == 0)
10344 avxscalar = vex128;
10345 else if (strcasecmp (arg, "256") == 0)
10346 avxscalar = vex256;
10348 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
10351 case OPTION_MADD_BND_PREFIX:
10352 add_bnd_prefix = 1;
10355 case OPTION_MEVEXLIG:
10356 if (strcmp (arg, "128") == 0)
10357 evexlig = evexl128;
10358 else if (strcmp (arg, "256") == 0)
10359 evexlig = evexl256;
10360 else if (strcmp (arg, "512") == 0)
10361 evexlig = evexl512;
10363 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10366 case OPTION_MEVEXRCIG:
10367 if (strcmp (arg, "rne") == 0)
10369 else if (strcmp (arg, "rd") == 0)
10371 else if (strcmp (arg, "ru") == 0)
10373 else if (strcmp (arg, "rz") == 0)
10376 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10379 case OPTION_MEVEXWIG:
10380 if (strcmp (arg, "0") == 0)
10382 else if (strcmp (arg, "1") == 0)
10385 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10388 # if defined (TE_PE) || defined (TE_PEP)
10389 case OPTION_MBIG_OBJ:
10394 case OPTION_MOMIT_LOCK_PREFIX:
10395 if (strcasecmp (arg, "yes") == 0)
10396 omit_lock_prefix = 1;
10397 else if (strcasecmp (arg, "no") == 0)
10398 omit_lock_prefix = 0;
10400 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10403 case OPTION_MFENCE_AS_LOCK_ADD:
10404 if (strcasecmp (arg, "yes") == 0)
10406 else if (strcasecmp (arg, "no") == 0)
10409 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10412 case OPTION_MRELAX_RELOCATIONS:
10413 if (strcasecmp (arg, "yes") == 0)
10414 generate_relax_relocations = 1;
10415 else if (strcasecmp (arg, "no") == 0)
10416 generate_relax_relocations = 0;
10418 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10421 case OPTION_MAMD64:
10425 case OPTION_MINTEL64:
10435 #define MESSAGE_TEMPLATE \
10439 output_message (FILE *stream, char *p, char *message, char *start,
10440 int *left_p, const char *name, int len)
10442 int size = sizeof (MESSAGE_TEMPLATE);
10443 int left = *left_p;
10445 /* Reserve 2 spaces for ", " or ",\0" */
10448 /* Check if there is any room. */
10456 p = mempcpy (p, name, len);
10460 /* Output the current message now and start a new one. */
10463 fprintf (stream, "%s\n", message);
10465 left = size - (start - message) - len - 2;
10467 gas_assert (left >= 0);
10469 p = mempcpy (p, name, len);
10477 show_arch (FILE *stream, int ext, int check)
10479 static char message[] = MESSAGE_TEMPLATE;
10480 char *start = message + 27;
10482 int size = sizeof (MESSAGE_TEMPLATE);
10489 left = size - (start - message);
10490 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10492 /* Should it be skipped? */
10493 if (cpu_arch [j].skip)
10496 name = cpu_arch [j].name;
10497 len = cpu_arch [j].len;
10500 /* It is an extension. Skip if we aren't asked to show it. */
10511 /* It is an processor. Skip if we show only extension. */
10514 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10516 /* It is an impossible processor - skip. */
10520 p = output_message (stream, p, message, start, &left, name, len);
10523 /* Display disabled extensions. */
10525 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10527 name = cpu_noarch [j].name;
10528 len = cpu_noarch [j].len;
10529 p = output_message (stream, p, message, start, &left, name,
10534 fprintf (stream, "%s\n", message);
10538 md_show_usage (FILE *stream)
10540 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10541 fprintf (stream, _("\
10543 -V print assembler version number\n\
10546 fprintf (stream, _("\
10547 -n Do not optimize code alignment\n\
10548 -q quieten some warnings\n"));
10549 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10550 fprintf (stream, _("\
10553 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10554 || defined (TE_PE) || defined (TE_PEP))
10555 fprintf (stream, _("\
10556 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10558 #ifdef SVR4_COMMENT_CHARS
10559 fprintf (stream, _("\
10560 --divide do not treat `/' as a comment character\n"));
10562 fprintf (stream, _("\
10563 --divide ignored\n"));
10565 fprintf (stream, _("\
10566 -march=CPU[,+EXTENSION...]\n\
10567 generate code for CPU and EXTENSION, CPU is one of:\n"));
10568 show_arch (stream, 0, 1);
10569 fprintf (stream, _("\
10570 EXTENSION is combination of:\n"));
10571 show_arch (stream, 1, 0);
10572 fprintf (stream, _("\
10573 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10574 show_arch (stream, 0, 0);
10575 fprintf (stream, _("\
10576 -msse2avx encode SSE instructions with VEX prefix\n"));
10577 fprintf (stream, _("\
10578 -msse-check=[none|error|warning]\n\
10579 check SSE instructions\n"));
10580 fprintf (stream, _("\
10581 -moperand-check=[none|error|warning]\n\
10582 check operand combinations for validity\n"));
10583 fprintf (stream, _("\
10584 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10586 fprintf (stream, _("\
10587 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10589 fprintf (stream, _("\
10590 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10591 for EVEX.W bit ignored instructions\n"));
10592 fprintf (stream, _("\
10593 -mevexrcig=[rne|rd|ru|rz]\n\
10594 encode EVEX instructions with specific EVEX.RC value\n\
10595 for SAE-only ignored instructions\n"));
10596 fprintf (stream, _("\
10597 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10598 fprintf (stream, _("\
10599 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10600 fprintf (stream, _("\
10601 -mindex-reg support pseudo index registers\n"));
10602 fprintf (stream, _("\
10603 -mnaked-reg don't require `%%' prefix for registers\n"));
10604 fprintf (stream, _("\
10605 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10606 fprintf (stream, _("\
10607 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10608 fprintf (stream, _("\
10609 -mshared disable branch optimization for shared code\n"));
10610 # if defined (TE_PE) || defined (TE_PEP)
10611 fprintf (stream, _("\
10612 -mbig-obj generate big object files\n"));
10614 fprintf (stream, _("\
10615 -momit-lock-prefix=[no|yes]\n\
10616 strip all lock prefixes\n"));
10617 fprintf (stream, _("\
10618 -mfence-as-lock-add=[no|yes]\n\
10619 encode lfence, mfence and sfence as\n\
10620 lock addl $0x0, (%%{re}sp)\n"));
10621 fprintf (stream, _("\
10622 -mrelax-relocations=[no|yes]\n\
10623 generate relax relocations\n"));
10624 fprintf (stream, _("\
10625 -mamd64 accept only AMD64 ISA\n"));
10626 fprintf (stream, _("\
10627 -mintel64 accept only Intel64 ISA\n"));
10630 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10631 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10632 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10634 /* Pick the target format to use. */
10637 i386_target_format (void)
10639 if (!strncmp (default_arch, "x86_64", 6))
10641 update_code_flag (CODE_64BIT, 1);
10642 if (default_arch[6] == '\0')
10643 x86_elf_abi = X86_64_ABI;
10645 x86_elf_abi = X86_64_X32_ABI;
10647 else if (!strcmp (default_arch, "i386"))
10648 update_code_flag (CODE_32BIT, 1);
10649 else if (!strcmp (default_arch, "iamcu"))
10651 update_code_flag (CODE_32BIT, 1);
10652 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10654 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10655 cpu_arch_name = "iamcu";
10656 cpu_sub_arch_name = NULL;
10657 cpu_arch_flags = iamcu_flags;
10658 cpu_arch_isa = PROCESSOR_IAMCU;
10659 cpu_arch_isa_flags = iamcu_flags;
10660 if (!cpu_arch_tune_set)
10662 cpu_arch_tune = cpu_arch_isa;
10663 cpu_arch_tune_flags = cpu_arch_isa_flags;
10666 else if (cpu_arch_isa != PROCESSOR_IAMCU)
10667 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10671 as_fatal (_("unknown architecture"));
10673 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10674 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10675 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10676 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10678 switch (OUTPUT_FLAVOR)
10680 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10681 case bfd_target_aout_flavour:
10682 return AOUT_TARGET_FORMAT;
10684 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10685 # if defined (TE_PE) || defined (TE_PEP)
10686 case bfd_target_coff_flavour:
10687 if (flag_code == CODE_64BIT)
10688 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10691 # elif defined (TE_GO32)
10692 case bfd_target_coff_flavour:
10693 return "coff-go32";
10695 case bfd_target_coff_flavour:
10696 return "coff-i386";
10699 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10700 case bfd_target_elf_flavour:
10702 const char *format;
10704 switch (x86_elf_abi)
10707 format = ELF_TARGET_FORMAT;
10710 use_rela_relocations = 1;
10712 format = ELF_TARGET_FORMAT64;
10714 case X86_64_X32_ABI:
10715 use_rela_relocations = 1;
10717 disallow_64bit_reloc = 1;
10718 format = ELF_TARGET_FORMAT32;
10721 if (cpu_arch_isa == PROCESSOR_L1OM)
10723 if (x86_elf_abi != X86_64_ABI)
10724 as_fatal (_("Intel L1OM is 64bit only"));
10725 return ELF_TARGET_L1OM_FORMAT;
10727 else if (cpu_arch_isa == PROCESSOR_K1OM)
10729 if (x86_elf_abi != X86_64_ABI)
10730 as_fatal (_("Intel K1OM is 64bit only"));
10731 return ELF_TARGET_K1OM_FORMAT;
10733 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10735 if (x86_elf_abi != I386_ABI)
10736 as_fatal (_("Intel MCU is 32bit only"));
10737 return ELF_TARGET_IAMCU_FORMAT;
10743 #if defined (OBJ_MACH_O)
10744 case bfd_target_mach_o_flavour:
10745 if (flag_code == CODE_64BIT)
10747 use_rela_relocations = 1;
10749 return "mach-o-x86-64";
10752 return "mach-o-i386";
10760 #endif /* OBJ_MAYBE_ more than one */
10763 md_undefined_symbol (char *name)
10765 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10766 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10767 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10768 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10772 if (symbol_find (name))
10773 as_bad (_("GOT already in symbol table"));
10774 GOT_symbol = symbol_new (name, undefined_section,
10775 (valueT) 0, &zero_address_frag);
10782 /* Round up a section size to the appropriate boundary. */
10785 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10787 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10788 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10790 /* For a.out, force the section size to be aligned. If we don't do
10791 this, BFD will align it for us, but it will not write out the
10792 final bytes of the section. This may be a bug in BFD, but it is
10793 easier to fix it here since that is how the other a.out targets
10797 align = bfd_get_section_alignment (stdoutput, segment);
10798 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
10805 /* On the i386, PC-relative offsets are relative to the start of the
10806 next instruction. That is, the address of the offset, plus its
10807 size, since the offset is always the last part of the insn. */
10810 md_pcrel_from (fixS *fixP)
10812 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10818 s_bss (int ignore ATTRIBUTE_UNUSED)
10822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10824 obj_elf_section_change_hook ();
10826 temp = get_absolute_expression ();
10827 subseg_set (bss_section, (subsegT) temp);
10828 demand_empty_rest_of_line ();
10834 i386_validate_fix (fixS *fixp)
10836 if (fixp->fx_subsy)
10838 if (fixp->fx_subsy == GOT_symbol)
10840 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10844 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10845 if (fixp->fx_tcbit2)
10846 fixp->fx_r_type = (fixp->fx_tcbit
10847 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10848 : BFD_RELOC_X86_64_GOTPCRELX);
10851 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10856 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10858 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10860 fixp->fx_subsy = 0;
10863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10864 else if (!object_64bit)
10866 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10867 && fixp->fx_tcbit2)
10868 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10874 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10877 bfd_reloc_code_real_type code;
10879 switch (fixp->fx_r_type)
10881 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10882 case BFD_RELOC_SIZE32:
10883 case BFD_RELOC_SIZE64:
10884 if (S_IS_DEFINED (fixp->fx_addsy)
10885 && !S_IS_EXTERNAL (fixp->fx_addsy))
10887 /* Resolve size relocation against local symbol to size of
10888 the symbol plus addend. */
10889 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10890 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10891 && !fits_in_unsigned_long (value))
10892 as_bad_where (fixp->fx_file, fixp->fx_line,
10893 _("symbol size computation overflow"));
10894 fixp->fx_addsy = NULL;
10895 fixp->fx_subsy = NULL;
10896 md_apply_fix (fixp, (valueT *) &value, NULL);
10900 /* Fall through. */
10902 case BFD_RELOC_X86_64_PLT32:
10903 case BFD_RELOC_X86_64_GOT32:
10904 case BFD_RELOC_X86_64_GOTPCREL:
10905 case BFD_RELOC_X86_64_GOTPCRELX:
10906 case BFD_RELOC_X86_64_REX_GOTPCRELX:
10907 case BFD_RELOC_386_PLT32:
10908 case BFD_RELOC_386_GOT32:
10909 case BFD_RELOC_386_GOT32X:
10910 case BFD_RELOC_386_GOTOFF:
10911 case BFD_RELOC_386_GOTPC:
10912 case BFD_RELOC_386_TLS_GD:
10913 case BFD_RELOC_386_TLS_LDM:
10914 case BFD_RELOC_386_TLS_LDO_32:
10915 case BFD_RELOC_386_TLS_IE_32:
10916 case BFD_RELOC_386_TLS_IE:
10917 case BFD_RELOC_386_TLS_GOTIE:
10918 case BFD_RELOC_386_TLS_LE_32:
10919 case BFD_RELOC_386_TLS_LE:
10920 case BFD_RELOC_386_TLS_GOTDESC:
10921 case BFD_RELOC_386_TLS_DESC_CALL:
10922 case BFD_RELOC_X86_64_TLSGD:
10923 case BFD_RELOC_X86_64_TLSLD:
10924 case BFD_RELOC_X86_64_DTPOFF32:
10925 case BFD_RELOC_X86_64_DTPOFF64:
10926 case BFD_RELOC_X86_64_GOTTPOFF:
10927 case BFD_RELOC_X86_64_TPOFF32:
10928 case BFD_RELOC_X86_64_TPOFF64:
10929 case BFD_RELOC_X86_64_GOTOFF64:
10930 case BFD_RELOC_X86_64_GOTPC32:
10931 case BFD_RELOC_X86_64_GOT64:
10932 case BFD_RELOC_X86_64_GOTPCREL64:
10933 case BFD_RELOC_X86_64_GOTPC64:
10934 case BFD_RELOC_X86_64_GOTPLT64:
10935 case BFD_RELOC_X86_64_PLTOFF64:
10936 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10937 case BFD_RELOC_X86_64_TLSDESC_CALL:
10938 case BFD_RELOC_RVA:
10939 case BFD_RELOC_VTABLE_ENTRY:
10940 case BFD_RELOC_VTABLE_INHERIT:
10942 case BFD_RELOC_32_SECREL:
10944 code = fixp->fx_r_type;
10946 case BFD_RELOC_X86_64_32S:
10947 if (!fixp->fx_pcrel)
10949 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10950 code = fixp->fx_r_type;
10953 /* Fall through. */
10955 if (fixp->fx_pcrel)
10957 switch (fixp->fx_size)
10960 as_bad_where (fixp->fx_file, fixp->fx_line,
10961 _("can not do %d byte pc-relative relocation"),
10963 code = BFD_RELOC_32_PCREL;
10965 case 1: code = BFD_RELOC_8_PCREL; break;
10966 case 2: code = BFD_RELOC_16_PCREL; break;
10967 case 4: code = BFD_RELOC_32_PCREL; break;
10969 case 8: code = BFD_RELOC_64_PCREL; break;
10975 switch (fixp->fx_size)
10978 as_bad_where (fixp->fx_file, fixp->fx_line,
10979 _("can not do %d byte relocation"),
10981 code = BFD_RELOC_32;
10983 case 1: code = BFD_RELOC_8; break;
10984 case 2: code = BFD_RELOC_16; break;
10985 case 4: code = BFD_RELOC_32; break;
10987 case 8: code = BFD_RELOC_64; break;
10994 if ((code == BFD_RELOC_32
10995 || code == BFD_RELOC_32_PCREL
10996 || code == BFD_RELOC_X86_64_32S)
10998 && fixp->fx_addsy == GOT_symbol)
11001 code = BFD_RELOC_386_GOTPC;
11003 code = BFD_RELOC_X86_64_GOTPC32;
11005 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11007 && fixp->fx_addsy == GOT_symbol)
11009 code = BFD_RELOC_X86_64_GOTPC64;
11012 rel = XNEW (arelent);
11013 rel->sym_ptr_ptr = XNEW (asymbol *);
11014 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11016 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
11018 if (!use_rela_relocations)
11020 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11021 vtable entry to be used in the relocation's section offset. */
11022 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11023 rel->address = fixp->fx_offset;
11024 #if defined (OBJ_COFF) && defined (TE_PE)
11025 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11026 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11031 /* Use the rela in 64bit mode. */
11034 if (disallow_64bit_reloc)
11037 case BFD_RELOC_X86_64_DTPOFF64:
11038 case BFD_RELOC_X86_64_TPOFF64:
11039 case BFD_RELOC_64_PCREL:
11040 case BFD_RELOC_X86_64_GOTOFF64:
11041 case BFD_RELOC_X86_64_GOT64:
11042 case BFD_RELOC_X86_64_GOTPCREL64:
11043 case BFD_RELOC_X86_64_GOTPC64:
11044 case BFD_RELOC_X86_64_GOTPLT64:
11045 case BFD_RELOC_X86_64_PLTOFF64:
11046 as_bad_where (fixp->fx_file, fixp->fx_line,
11047 _("cannot represent relocation type %s in x32 mode"),
11048 bfd_get_reloc_code_name (code));
11054 if (!fixp->fx_pcrel)
11055 rel->addend = fixp->fx_offset;
11059 case BFD_RELOC_X86_64_PLT32:
11060 case BFD_RELOC_X86_64_GOT32:
11061 case BFD_RELOC_X86_64_GOTPCREL:
11062 case BFD_RELOC_X86_64_GOTPCRELX:
11063 case BFD_RELOC_X86_64_REX_GOTPCRELX:
11064 case BFD_RELOC_X86_64_TLSGD:
11065 case BFD_RELOC_X86_64_TLSLD:
11066 case BFD_RELOC_X86_64_GOTTPOFF:
11067 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11068 case BFD_RELOC_X86_64_TLSDESC_CALL:
11069 rel->addend = fixp->fx_offset - fixp->fx_size;
11072 rel->addend = (section->vma
11074 + fixp->fx_addnumber
11075 + md_pcrel_from (fixp));
11080 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11081 if (rel->howto == NULL)
11083 as_bad_where (fixp->fx_file, fixp->fx_line,
11084 _("cannot represent relocation type %s"),
11085 bfd_get_reloc_code_name (code));
11086 /* Set howto to a garbage value so that we can keep going. */
11087 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
11088 gas_assert (rel->howto != NULL);
11094 #include "tc-i386-intel.c"
11097 tc_x86_parse_to_dw2regnum (expressionS *exp)
11099 int saved_naked_reg;
11100 char saved_register_dot;
11102 saved_naked_reg = allow_naked_reg;
11103 allow_naked_reg = 1;
11104 saved_register_dot = register_chars['.'];
11105 register_chars['.'] = '.';
11106 allow_pseudo_reg = 1;
11107 expression_and_evaluate (exp);
11108 allow_pseudo_reg = 0;
11109 register_chars['.'] = saved_register_dot;
11110 allow_naked_reg = saved_naked_reg;
11112 if (exp->X_op == O_register && exp->X_add_number >= 0)
11114 if ((addressT) exp->X_add_number < i386_regtab_size)
11116 exp->X_op = O_constant;
11117 exp->X_add_number = i386_regtab[exp->X_add_number]
11118 .dw2_regnum[flag_code >> 1];
11121 exp->X_op = O_illegal;
11126 tc_x86_frame_initial_instructions (void)
11128 static unsigned int sp_regno[2];
11130 if (!sp_regno[flag_code >> 1])
11132 char *saved_input = input_line_pointer;
11133 char sp[][4] = {"esp", "rsp"};
11136 input_line_pointer = sp[flag_code >> 1];
11137 tc_x86_parse_to_dw2regnum (&exp);
11138 gas_assert (exp.X_op == O_constant);
11139 sp_regno[flag_code >> 1] = exp.X_add_number;
11140 input_line_pointer = saved_input;
11143 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11144 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
11148 x86_dwarf2_addr_size (void)
11150 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11151 if (x86_elf_abi == X86_64_X32_ABI)
11154 return bfd_arch_bits_per_address (stdoutput) / 8;
11158 i386_elf_section_type (const char *str, size_t len)
11160 if (flag_code == CODE_64BIT
11161 && len == sizeof ("unwind") - 1
11162 && strncmp (str, "unwind", 6) == 0)
11163 return SHT_X86_64_UNWIND;
11170 i386_solaris_fix_up_eh_frame (segT sec)
11172 if (flag_code == CODE_64BIT)
11173 elf_section_type (sec) = SHT_X86_64_UNWIND;
11179 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11183 exp.X_op = O_secrel;
11184 exp.X_add_symbol = symbol;
11185 exp.X_add_number = 0;
11186 emit_expr (&exp, size);
11190 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11191 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11194 x86_64_section_letter (int letter, const char **ptr_msg)
11196 if (flag_code == CODE_64BIT)
11199 return SHF_X86_64_LARGE;
11201 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
11204 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
11209 x86_64_section_word (char *str, size_t len)
11211 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
11212 return SHF_X86_64_LARGE;
11218 handle_large_common (int small ATTRIBUTE_UNUSED)
11220 if (flag_code != CODE_64BIT)
11222 s_comm_internal (0, elf_common_parse);
11223 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11227 static segT lbss_section;
11228 asection *saved_com_section_ptr = elf_com_section_ptr;
11229 asection *saved_bss_section = bss_section;
11231 if (lbss_section == NULL)
11233 flagword applicable;
11234 segT seg = now_seg;
11235 subsegT subseg = now_subseg;
11237 /* The .lbss section is for local .largecomm symbols. */
11238 lbss_section = subseg_new (".lbss", 0);
11239 applicable = bfd_applicable_section_flags (stdoutput);
11240 bfd_set_section_flags (stdoutput, lbss_section,
11241 applicable & SEC_ALLOC);
11242 seg_info (lbss_section)->bss = 1;
11244 subseg_set (seg, subseg);
11247 elf_com_section_ptr = &_bfd_elf_large_com_section;
11248 bss_section = lbss_section;
11250 s_comm_internal (0, elf_common_parse);
11252 elf_com_section_ptr = saved_com_section_ptr;
11253 bss_section = saved_bss_section;
11256 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */