1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
36 #include "elf/x86-64.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
46 #ifndef SCALE1_WHEN_NO_INDEX
47 /* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51 #define SCALE1_WHEN_NO_INDEX 1
55 #define DEFAULT_ARCH "i386"
60 #define INLINE __inline__
66 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70 static INLINE int fits_in_signed_word PARAMS ((offsetT));
71 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72 static INLINE int fits_in_signed_long PARAMS ((offsetT));
73 static int smallest_imm_type PARAMS ((offsetT));
74 static offsetT offset_in_range PARAMS ((offsetT, int));
75 static int add_prefix PARAMS ((unsigned int));
76 static void set_code_flag PARAMS ((int));
77 static void set_16bit_gcc_code_flag PARAMS ((int));
78 static void set_intel_syntax PARAMS ((int));
79 static void set_cpu_arch PARAMS ((int));
81 static void pe_directive_secrel PARAMS ((int));
83 static void signed_cons PARAMS ((int));
84 static char *output_invalid PARAMS ((int c));
85 static int i386_operand PARAMS ((char *operand_string));
86 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87 static const reg_entry *parse_register PARAMS ((char *reg_string,
89 static char *parse_insn PARAMS ((char *, char *));
90 static char *parse_operands PARAMS ((char *, const char *));
91 static void swap_operands PARAMS ((void));
92 static void optimize_imm PARAMS ((void));
93 static void optimize_disp PARAMS ((void));
94 static int match_template PARAMS ((void));
95 static int check_string PARAMS ((void));
96 static int process_suffix PARAMS ((void));
97 static int check_byte_reg PARAMS ((void));
98 static int check_long_reg PARAMS ((void));
99 static int check_qword_reg PARAMS ((void));
100 static int check_word_reg PARAMS ((void));
101 static int finalize_imm PARAMS ((void));
102 static int process_operands PARAMS ((void));
103 static const seg_entry *build_modrm_byte PARAMS ((void));
104 static void output_insn PARAMS ((void));
105 static void output_branch PARAMS ((void));
106 static void output_jump PARAMS ((void));
107 static void output_interseg_jump PARAMS ((void));
108 static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110 static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
113 static void s_bss PARAMS ((int));
115 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116 static void handle_large_common (int small ATTRIBUTE_UNUSED);
119 static const char *default_arch = DEFAULT_ARCH;
121 /* 'md_assemble ()' gathers together information and puts it into a
128 const reg_entry *regs;
133 /* TM holds the template for the insn were currently assembling. */
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
140 /* OPERANDS gives the number of given operands. */
141 unsigned int operands;
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148 /* TYPES [i] is the type (see above #defines) which tells us how to
149 use OP[i] for the corresponding operand. */
150 unsigned int types[MAX_OPERANDS];
152 /* Displacement expression, immediate expression, or register for each
154 union i386_op op[MAX_OPERANDS];
156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158 #define Operand_PCrel 1
160 /* Relocation type for operand */
161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
169 /* SEG gives the seg_entries of this insn. They are zero unless
170 explicit segment overrides are given. */
171 const seg_entry *seg[2];
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
186 typedef struct _i386_insn i386_insn;
188 /* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
190 const char extra_symbol_chars[] = "*%-(["
199 #if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
201 && !defined (TE_GNU) \
202 && !defined (TE_LINUX) \
203 && !defined (TE_NETWARE) \
204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
206 /* This array holds the chars that always start a comment. If the
207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209 const char *i386_comment_chars = "#/";
210 #define SVR4_COMMENT_CHARS 1
211 #define PREFIX_SEPARATOR '\\'
214 const char *i386_comment_chars = "#";
215 #define PREFIX_SEPARATOR '/'
218 /* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
222 first line of the input file. This is because the compiler outputs
223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
225 '/' isn't otherwise defined. */
226 const char line_comment_chars[] = "#/";
228 const char line_separator_chars[] = ";";
230 /* Chars that can be used to separate mant from exp in floating point
232 const char EXP_CHARS[] = "eE";
234 /* Chars that mean this number is a floating point constant
237 const char FLT_CHARS[] = "fFdDxX";
239 /* Tables for lexical analysis. */
240 static char mnemonic_chars[256];
241 static char register_chars[256];
242 static char operand_chars[256];
243 static char identifier_chars[256];
244 static char digit_chars[256];
246 /* Lexical macros. */
247 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248 #define is_operand_char(x) (operand_chars[(unsigned char) x])
249 #define is_register_char(x) (register_chars[(unsigned char) x])
250 #define is_space_char(x) ((x) == ' ')
251 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252 #define is_digit_char(x) (digit_chars[(unsigned char) x])
254 /* All non-digit non-letter characters that may occur in an operand. */
255 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257 /* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
260 assembler instruction). */
261 static char save_stack[32];
262 static char *save_stack_p;
263 #define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265 #define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
268 /* The instruction we're assembling. */
271 /* Possible templates for current insn. */
272 static const templates *current_templates;
274 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
275 static expressionS disp_expressions[2], im_expressions[2];
277 /* Current operand we are working on. */
278 static int this_operand;
280 /* We support four different modes. FLAG_CODE variable is used to distinguish
287 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
289 static enum flag_code flag_code;
290 static unsigned int object_64bit;
291 static int use_rela_relocations = 0;
293 /* The names used to print error messages. */
294 static const char *flag_code_names[] =
301 /* 1 for intel syntax,
303 static int intel_syntax = 0;
305 /* 1 if register prefix % not required. */
306 static int allow_naked_reg = 0;
308 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311 static char stackop_size = '\0';
313 /* Non-zero to optimize code alignment. */
314 int optimize_align_code = 1;
316 /* Non-zero to quieten some warnings. */
317 static int quiet_warnings = 0;
320 static const char *cpu_arch_name = NULL;
321 static const char *cpu_sub_arch_name = NULL;
323 /* CPU feature flags. */
324 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
326 /* If set, conditional jumps are not automatically promoted to handle
327 larger than a byte offset. */
328 static unsigned int no_cond_jump_promotion = 0;
330 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
331 static symbolS *GOT_symbol;
333 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
334 unsigned int x86_dwarf2_return_column;
336 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
337 int x86_cie_data_alignment;
339 /* Interface to relax_segment.
340 There are 3 major relax states for 386 jump insns because the
341 different types of jumps add different sizes to frags when we're
342 figuring out what sort of jump to choose to reach a given label. */
345 #define UNCOND_JUMP 0
347 #define COND_JUMP86 2
352 #define SMALL16 (SMALL | CODE16)
354 #define BIG16 (BIG | CODE16)
358 #define INLINE __inline__
364 #define ENCODE_RELAX_STATE(type, size) \
365 ((relax_substateT) (((type) << 2) | (size)))
366 #define TYPE_FROM_RELAX_STATE(s) \
368 #define DISP_SIZE_FROM_RELAX_STATE(s) \
369 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
371 /* This table is used by relax_frag to promote short jumps to long
372 ones where necessary. SMALL (short) jumps may be promoted to BIG
373 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
374 don't allow a short jump in a 32 bit code segment to be promoted to
375 a 16 bit offset jump because it's slower (requires data size
376 prefix), and doesn't work, unless the destination is in the bottom
377 64k of the code segment (The top 16 bits of eip are zeroed). */
379 const relax_typeS md_relax_table[] =
382 1) most positive reach of this state,
383 2) most negative reach of this state,
384 3) how many bytes this mode will have in the variable part of the frag
385 4) which index into the table to try if we can't fit into this one. */
387 /* UNCOND_JUMP states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
390 /* dword jmp adds 4 bytes to frag:
391 0 extra opcode bytes, 4 displacement bytes. */
393 /* word jmp adds 2 byte2 to frag:
394 0 extra opcode bytes, 2 displacement bytes. */
397 /* COND_JUMP states. */
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
400 /* dword conditionals adds 5 bytes to frag:
401 1 extra opcode byte, 4 displacement bytes. */
403 /* word conditionals add 3 bytes to frag:
404 1 extra opcode byte, 2 displacement bytes. */
407 /* COND_JUMP86 states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
413 /* word conditionals add 4 bytes to frag:
414 1 displacement byte and a 3 byte long branch insn. */
418 static const arch_entry cpu_arch[] = {
420 {"i186", Cpu086|Cpu186 },
421 {"i286", Cpu086|Cpu186|Cpu286 },
422 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
423 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
424 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
425 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
426 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
427 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
428 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
429 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
430 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
431 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
432 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
433 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
434 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
435 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
436 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
438 {".sse", CpuMMX|CpuMMX2|CpuSSE },
439 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
440 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
441 {".3dnow", CpuMMX|Cpu3dnow },
442 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
443 {".padlock", CpuPadLock },
444 {".pacifica", CpuSVME },
449 const pseudo_typeS md_pseudo_table[] =
451 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
452 {"align", s_align_bytes, 0},
454 {"align", s_align_ptwo, 0},
456 {"arch", set_cpu_arch, 0},
460 {"ffloat", float_cons, 'f'},
461 {"dfloat", float_cons, 'd'},
462 {"tfloat", float_cons, 'x'},
464 {"slong", signed_cons, 4},
465 {"noopt", s_ignore, 0},
466 {"optim", s_ignore, 0},
467 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
468 {"code16", set_code_flag, CODE_16BIT},
469 {"code32", set_code_flag, CODE_32BIT},
470 {"code64", set_code_flag, CODE_64BIT},
471 {"intel_syntax", set_intel_syntax, 1},
472 {"att_syntax", set_intel_syntax, 0},
473 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
474 {"largecomm", handle_large_common, 0},
476 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
477 {"loc", dwarf2_directive_loc, 0},
478 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
481 {"secrel32", pe_directive_secrel, 0},
486 /* For interface with expression (). */
487 extern char *input_line_pointer;
489 /* Hash table for instruction mnemonic lookup. */
490 static struct hash_control *op_hash;
492 /* Hash table for register lookup. */
493 static struct hash_control *reg_hash;
496 i386_align_code (fragP, count)
500 /* Various efficient no-op patterns for aligning code labels.
501 Note: Don't try to assemble the instructions in the comments.
502 0L and 0w are not legal. */
503 static const char f32_1[] =
505 static const char f32_2[] =
506 {0x89,0xf6}; /* movl %esi,%esi */
507 static const char f32_3[] =
508 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
509 static const char f32_4[] =
510 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
511 static const char f32_5[] =
513 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
514 static const char f32_6[] =
515 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
516 static const char f32_7[] =
517 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
518 static const char f32_8[] =
520 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
521 static const char f32_9[] =
522 {0x89,0xf6, /* movl %esi,%esi */
523 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
524 static const char f32_10[] =
525 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
526 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
527 static const char f32_11[] =
528 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
529 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
530 static const char f32_12[] =
531 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
532 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
533 static const char f32_13[] =
534 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
535 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
536 static const char f32_14[] =
537 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
538 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
539 static const char f32_15[] =
540 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
541 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
542 static const char f16_3[] =
543 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
544 static const char f16_4[] =
545 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
546 static const char f16_5[] =
548 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
549 static const char f16_6[] =
550 {0x89,0xf6, /* mov %si,%si */
551 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
552 static const char f16_7[] =
553 {0x8d,0x74,0x00, /* lea 0(%si),%si */
554 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
555 static const char f16_8[] =
556 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
557 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
558 static const char *const f32_patt[] = {
559 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
560 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
562 static const char *const f16_patt[] = {
563 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
564 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
567 if (count <= 0 || count > 15)
570 /* The recommended way to pad 64bit code is to use NOPs preceded by
571 maximally four 0x66 prefixes. Balance the size of nops. */
572 if (flag_code == CODE_64BIT)
575 int nnops = (count + 3) / 4;
576 int len = count / nnops;
577 int remains = count - nnops * len;
580 for (i = 0; i < remains; i++)
582 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
583 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
586 for (; i < nnops; i++)
588 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
589 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
594 if (flag_code == CODE_16BIT)
596 memcpy (fragP->fr_literal + fragP->fr_fix,
597 f16_patt[count - 1], count);
599 /* Adjust jump offset. */
600 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
603 memcpy (fragP->fr_literal + fragP->fr_fix,
604 f32_patt[count - 1], count);
605 fragP->fr_var = count;
608 static INLINE unsigned int
609 mode_from_disp_size (t)
612 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
616 fits_in_signed_byte (num)
619 return (num >= -128) && (num <= 127);
623 fits_in_unsigned_byte (num)
626 return (num & 0xff) == num;
630 fits_in_unsigned_word (num)
633 return (num & 0xffff) == num;
637 fits_in_signed_word (num)
640 return (-32768 <= num) && (num <= 32767);
643 fits_in_signed_long (num)
644 offsetT num ATTRIBUTE_UNUSED;
649 return (!(((offsetT) -1 << 31) & num)
650 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
652 } /* fits_in_signed_long() */
654 fits_in_unsigned_long (num)
655 offsetT num ATTRIBUTE_UNUSED;
660 return (num & (((offsetT) 2 << 31) - 1)) == num;
662 } /* fits_in_unsigned_long() */
665 smallest_imm_type (num)
668 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
670 /* This code is disabled on the 486 because all the Imm1 forms
671 in the opcode table are slower on the i486. They're the
672 versions with the implicitly specified single-position
673 displacement, which has another syntax if you really want to
676 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
678 return (fits_in_signed_byte (num)
679 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
680 : fits_in_unsigned_byte (num)
681 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
682 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
683 ? (Imm16 | Imm32 | Imm32S | Imm64)
684 : fits_in_signed_long (num)
685 ? (Imm32 | Imm32S | Imm64)
686 : fits_in_unsigned_long (num)
692 offset_in_range (val, size)
700 case 1: mask = ((addressT) 1 << 8) - 1; break;
701 case 2: mask = ((addressT) 1 << 16) - 1; break;
702 case 4: mask = ((addressT) 2 << 31) - 1; break;
704 case 8: mask = ((addressT) 2 << 63) - 1; break;
709 /* If BFD64, sign extend val. */
710 if (!use_rela_relocations)
711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
716 char buf1[40], buf2[40];
718 sprint_value (buf1, val);
719 sprint_value (buf2, val & mask);
720 as_warn (_("%s shortened to %s"), buf1, buf2);
725 /* Returns 0 if attempting to add a prefix where one from the same
726 class already exists, 1 if non rep/repne added, 2 if rep/repne
735 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
736 && flag_code == CODE_64BIT)
744 case CS_PREFIX_OPCODE:
745 case DS_PREFIX_OPCODE:
746 case ES_PREFIX_OPCODE:
747 case FS_PREFIX_OPCODE:
748 case GS_PREFIX_OPCODE:
749 case SS_PREFIX_OPCODE:
753 case REPNE_PREFIX_OPCODE:
754 case REPE_PREFIX_OPCODE:
757 case LOCK_PREFIX_OPCODE:
765 case ADDR_PREFIX_OPCODE:
769 case DATA_PREFIX_OPCODE:
774 if (i.prefix[q] != 0)
776 as_bad (_("same type of prefix used twice"));
781 i.prefix[q] = prefix;
786 set_code_flag (value)
790 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
791 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
792 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
794 as_bad (_("64bit mode not supported on this CPU."));
796 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
798 as_bad (_("32bit mode not supported on this CPU."));
804 set_16bit_gcc_code_flag (new_code_flag)
807 flag_code = new_code_flag;
808 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
809 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
810 stackop_size = LONG_MNEM_SUFFIX;
814 set_intel_syntax (syntax_flag)
817 /* Find out if register prefixing is specified. */
818 int ask_naked_reg = 0;
821 if (!is_end_of_line[(unsigned char) *input_line_pointer])
823 char *string = input_line_pointer;
824 int e = get_symbol_end ();
826 if (strcmp (string, "prefix") == 0)
828 else if (strcmp (string, "noprefix") == 0)
831 as_bad (_("bad argument to syntax directive."));
832 *input_line_pointer = e;
834 demand_empty_rest_of_line ();
836 intel_syntax = syntax_flag;
838 if (ask_naked_reg == 0)
839 allow_naked_reg = (intel_syntax
840 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
842 allow_naked_reg = (ask_naked_reg < 0);
844 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
845 identifier_chars['$'] = intel_syntax ? '$' : 0;
850 int dummy ATTRIBUTE_UNUSED;
854 if (!is_end_of_line[(unsigned char) *input_line_pointer])
856 char *string = input_line_pointer;
857 int e = get_symbol_end ();
860 for (i = 0; cpu_arch[i].name; i++)
862 if (strcmp (string, cpu_arch[i].name) == 0)
866 cpu_arch_name = cpu_arch[i].name;
867 cpu_sub_arch_name = NULL;
868 cpu_arch_flags = (cpu_arch[i].flags
869 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
872 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
874 cpu_sub_arch_name = cpu_arch[i].name;
875 cpu_arch_flags |= cpu_arch[i].flags;
877 *input_line_pointer = e;
878 demand_empty_rest_of_line ();
882 if (!cpu_arch[i].name)
883 as_bad (_("no such architecture: `%s'"), string);
885 *input_line_pointer = e;
888 as_bad (_("missing cpu architecture"));
890 no_cond_jump_promotion = 0;
891 if (*input_line_pointer == ','
892 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
894 char *string = ++input_line_pointer;
895 int e = get_symbol_end ();
897 if (strcmp (string, "nojumps") == 0)
898 no_cond_jump_promotion = 1;
899 else if (strcmp (string, "jumps") == 0)
902 as_bad (_("no such architecture modifier: `%s'"), string);
904 *input_line_pointer = e;
907 demand_empty_rest_of_line ();
913 if (!strcmp (default_arch, "x86_64"))
914 return bfd_mach_x86_64;
915 else if (!strcmp (default_arch, "i386"))
916 return bfd_mach_i386_i386;
918 as_fatal (_("Unknown architecture"));
924 const char *hash_err;
926 /* Initialize op_hash hash table. */
927 op_hash = hash_new ();
930 const template *optab;
931 templates *core_optab;
933 /* Setup for loop. */
935 core_optab = (templates *) xmalloc (sizeof (templates));
936 core_optab->start = optab;
941 if (optab->name == NULL
942 || strcmp (optab->name, (optab - 1)->name) != 0)
944 /* different name --> ship out current template list;
945 add to hash table; & begin anew. */
946 core_optab->end = optab;
947 hash_err = hash_insert (op_hash,
952 as_fatal (_("Internal Error: Can't hash %s: %s"),
956 if (optab->name == NULL)
958 core_optab = (templates *) xmalloc (sizeof (templates));
959 core_optab->start = optab;
964 /* Initialize reg_hash hash table. */
965 reg_hash = hash_new ();
967 const reg_entry *regtab;
969 for (regtab = i386_regtab;
970 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
973 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
975 as_fatal (_("Internal Error: Can't hash %s: %s"),
981 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
986 for (c = 0; c < 256; c++)
991 mnemonic_chars[c] = c;
992 register_chars[c] = c;
993 operand_chars[c] = c;
995 else if (ISLOWER (c))
997 mnemonic_chars[c] = c;
998 register_chars[c] = c;
999 operand_chars[c] = c;
1001 else if (ISUPPER (c))
1003 mnemonic_chars[c] = TOLOWER (c);
1004 register_chars[c] = mnemonic_chars[c];
1005 operand_chars[c] = c;
1008 if (ISALPHA (c) || ISDIGIT (c))
1009 identifier_chars[c] = c;
1012 identifier_chars[c] = c;
1013 operand_chars[c] = c;
1018 identifier_chars['@'] = '@';
1021 identifier_chars['?'] = '?';
1022 operand_chars['?'] = '?';
1024 digit_chars['-'] = '-';
1025 mnemonic_chars['-'] = '-';
1026 identifier_chars['_'] = '_';
1027 identifier_chars['.'] = '.';
1029 for (p = operand_special_chars; *p != '\0'; p++)
1030 operand_chars[(unsigned char) *p] = *p;
1033 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 record_alignment (text_section, 2);
1037 record_alignment (data_section, 2);
1038 record_alignment (bss_section, 2);
1042 if (flag_code == CODE_64BIT)
1044 x86_dwarf2_return_column = 16;
1045 x86_cie_data_alignment = -8;
1049 x86_dwarf2_return_column = 8;
1050 x86_cie_data_alignment = -4;
1055 i386_print_statistics (file)
1058 hash_print_statistics (file, "i386 opcode", op_hash);
1059 hash_print_statistics (file, "i386 register", reg_hash);
1064 /* Debugging routines for md_assemble. */
1065 static void pi PARAMS ((char *, i386_insn *));
1066 static void pte PARAMS ((template *));
1067 static void pt PARAMS ((unsigned int));
1068 static void pe PARAMS ((expressionS *));
1069 static void ps PARAMS ((symbolS *));
1078 fprintf (stdout, "%s: template ", line);
1080 fprintf (stdout, " address: base %s index %s scale %x\n",
1081 x->base_reg ? x->base_reg->reg_name : "none",
1082 x->index_reg ? x->index_reg->reg_name : "none",
1083 x->log2_scale_factor);
1084 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1085 x->rm.mode, x->rm.reg, x->rm.regmem);
1086 fprintf (stdout, " sib: base %x index %x scale %x\n",
1087 x->sib.base, x->sib.index, x->sib.scale);
1088 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1089 (x->rex & REX_MODE64) != 0,
1090 (x->rex & REX_EXTX) != 0,
1091 (x->rex & REX_EXTY) != 0,
1092 (x->rex & REX_EXTZ) != 0);
1093 for (i = 0; i < x->operands; i++)
1095 fprintf (stdout, " #%d: ", i + 1);
1097 fprintf (stdout, "\n");
1099 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1100 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1101 if (x->types[i] & Imm)
1103 if (x->types[i] & Disp)
1104 pe (x->op[i].disps);
1113 fprintf (stdout, " %d operands ", t->operands);
1114 fprintf (stdout, "opcode %x ", t->base_opcode);
1115 if (t->extension_opcode != None)
1116 fprintf (stdout, "ext %x ", t->extension_opcode);
1117 if (t->opcode_modifier & D)
1118 fprintf (stdout, "D");
1119 if (t->opcode_modifier & W)
1120 fprintf (stdout, "W");
1121 fprintf (stdout, "\n");
1122 for (i = 0; i < t->operands; i++)
1124 fprintf (stdout, " #%d type ", i + 1);
1125 pt (t->operand_types[i]);
1126 fprintf (stdout, "\n");
1134 fprintf (stdout, " operation %d\n", e->X_op);
1135 fprintf (stdout, " add_number %ld (%lx)\n",
1136 (long) e->X_add_number, (long) e->X_add_number);
1137 if (e->X_add_symbol)
1139 fprintf (stdout, " add_symbol ");
1140 ps (e->X_add_symbol);
1141 fprintf (stdout, "\n");
1145 fprintf (stdout, " op_symbol ");
1146 ps (e->X_op_symbol);
1147 fprintf (stdout, "\n");
1155 fprintf (stdout, "%s type %s%s",
1157 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1158 segment_name (S_GET_SEGMENT (s)));
1167 static const type_names[] =
1180 { BaseIndex, "BaseIndex" },
1184 { Disp32S, "d32s" },
1186 { InOutPortReg, "InOutPortReg" },
1187 { ShiftCount, "ShiftCount" },
1188 { Control, "control reg" },
1189 { Test, "test reg" },
1190 { Debug, "debug reg" },
1191 { FloatReg, "FReg" },
1192 { FloatAcc, "FAcc" },
1196 { JumpAbsolute, "Jump Absolute" },
1207 const struct type_name *ty;
1209 for (ty = type_names; ty->mask; ty++)
1211 fprintf (stdout, "%s, ", ty->tname);
1215 #endif /* DEBUG386 */
1217 static bfd_reloc_code_real_type
1218 reloc (unsigned int size,
1221 bfd_reloc_code_real_type other)
1223 if (other != NO_RELOC)
1225 reloc_howto_type *reloc;
1230 case BFD_RELOC_X86_64_TPOFF32:
1231 other = BFD_RELOC_X86_64_TPOFF64;
1233 case BFD_RELOC_X86_64_DTPOFF32:
1234 other = BFD_RELOC_X86_64_DTPOFF64;
1240 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1241 if (size == 4 && flag_code != CODE_64BIT)
1244 reloc = bfd_reloc_type_lookup (stdoutput, other);
1246 as_bad (_("unknown relocation (%u)"), other);
1247 else if (size != bfd_get_reloc_size (reloc))
1248 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1249 bfd_get_reloc_size (reloc),
1251 else if (pcrel && !reloc->pc_relative)
1252 as_bad (_("non-pc-relative relocation for pc-relative field"));
1253 else if ((reloc->complain_on_overflow == complain_overflow_signed
1255 || (reloc->complain_on_overflow == complain_overflow_unsigned
1257 as_bad (_("relocated field and relocation type differ in signedness"));
1266 as_bad (_("there are no unsigned pc-relative relocations"));
1269 case 1: return BFD_RELOC_8_PCREL;
1270 case 2: return BFD_RELOC_16_PCREL;
1271 case 4: return BFD_RELOC_32_PCREL;
1272 case 8: return BFD_RELOC_64_PCREL;
1274 as_bad (_("cannot do %u byte pc-relative relocation"), size);
1281 case 4: return BFD_RELOC_X86_64_32S;
1286 case 1: return BFD_RELOC_8;
1287 case 2: return BFD_RELOC_16;
1288 case 4: return BFD_RELOC_32;
1289 case 8: return BFD_RELOC_64;
1291 as_bad (_("cannot do %s %u byte relocation"),
1292 sign > 0 ? "signed" : "unsigned", size);
1296 return BFD_RELOC_NONE;
1299 /* Here we decide which fixups can be adjusted to make them relative to
1300 the beginning of the section instead of the symbol. Basically we need
1301 to make sure that the dynamic relocations are done correctly, so in
1302 some cases we force the original symbol to be used. */
1305 tc_i386_fix_adjustable (fixP)
1306 fixS *fixP ATTRIBUTE_UNUSED;
1308 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1312 /* Don't adjust pc-relative references to merge sections in 64-bit
1314 if (use_rela_relocations
1315 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1319 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1320 and changed later by validate_fix. */
1321 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1322 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1325 /* adjust_reloc_syms doesn't know about the GOT. */
1326 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1327 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1328 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1329 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1330 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1331 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1332 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1333 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1334 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1335 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1336 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1337 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1338 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1339 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1340 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1341 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1342 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1343 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
1344 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1345 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1346 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1347 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
1348 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1349 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1355 static int intel_float_operand PARAMS ((const char *mnemonic));
1358 intel_float_operand (mnemonic)
1359 const char *mnemonic;
1361 /* Note that the value returned is meaningful only for opcodes with (memory)
1362 operands, hence the code here is free to improperly handle opcodes that
1363 have no operands (for better performance and smaller code). */
1365 if (mnemonic[0] != 'f')
1366 return 0; /* non-math */
1368 switch (mnemonic[1])
1370 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1371 the fs segment override prefix not currently handled because no
1372 call path can make opcodes without operands get here */
1374 return 2 /* integer op */;
1376 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1377 return 3; /* fldcw/fldenv */
1380 if (mnemonic[2] != 'o' /* fnop */)
1381 return 3; /* non-waiting control op */
1384 if (mnemonic[2] == 's')
1385 return 3; /* frstor/frstpm */
1388 if (mnemonic[2] == 'a')
1389 return 3; /* fsave */
1390 if (mnemonic[2] == 't')
1392 switch (mnemonic[3])
1394 case 'c': /* fstcw */
1395 case 'd': /* fstdw */
1396 case 'e': /* fstenv */
1397 case 's': /* fsts[gw] */
1403 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1404 return 0; /* fxsave/fxrstor are not really math ops */
1411 /* This is the guts of the machine-dependent assembler. LINE points to a
1412 machine dependent instruction. This function is supposed to emit
1413 the frags/bytes it assembles to. */
1420 char mnemonic[MAX_MNEM_SIZE];
1422 /* Initialize globals. */
1423 memset (&i, '\0', sizeof (i));
1424 for (j = 0; j < MAX_OPERANDS; j++)
1425 i.reloc[j] = NO_RELOC;
1426 memset (disp_expressions, '\0', sizeof (disp_expressions));
1427 memset (im_expressions, '\0', sizeof (im_expressions));
1428 save_stack_p = save_stack;
1430 /* First parse an instruction mnemonic & call i386_operand for the operands.
1431 We assume that the scrubber has arranged it so that line[0] is the valid
1432 start of a (possibly prefixed) mnemonic. */
1434 line = parse_insn (line, mnemonic);
1438 line = parse_operands (line, mnemonic);
1442 /* Now we've parsed the mnemonic into a set of templates, and have the
1443 operands at hand. */
1445 /* All intel opcodes have reversed operands except for "bound" and
1446 "enter". We also don't reverse intersegment "jmp" and "call"
1447 instructions with 2 immediate operands so that the immediate segment
1448 precedes the offset, as it does when in AT&T mode. "enter" and the
1449 intersegment "jmp" and "call" instructions are the only ones that
1450 have two immediate operands. */
1451 if (intel_syntax && i.operands > 1
1452 && (strcmp (mnemonic, "bound") != 0)
1453 && (strcmp (mnemonic, "invlpga") != 0)
1454 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1460 /* Don't optimize displacement for movabs since it only takes 64bit
1463 && (flag_code != CODE_64BIT
1464 || strcmp (mnemonic, "movabs") != 0))
1467 /* Next, we find a template that matches the given insn,
1468 making sure the overlap of the given operands types is consistent
1469 with the template operand types. */
1471 if (!match_template ())
1476 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1478 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1479 i.tm.base_opcode ^= FloatR;
1481 /* Zap movzx and movsx suffix. The suffix may have been set from
1482 "word ptr" or "byte ptr" on the source operand, but we'll use
1483 the suffix later to choose the destination register. */
1484 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1486 if (i.reg_operands < 2
1488 && (~i.tm.opcode_modifier
1495 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1501 if (i.tm.opcode_modifier & FWait)
1502 if (!add_prefix (FWAIT_OPCODE))
1505 /* Check string instruction segment overrides. */
1506 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1508 if (!check_string ())
1512 if (!process_suffix ())
1515 /* Make still unresolved immediate matches conform to size of immediate
1516 given in i.suffix. */
1517 if (!finalize_imm ())
1520 if (i.types[0] & Imm1)
1521 i.imm_operands = 0; /* kludge for shift insns. */
1522 if (i.types[0] & ImplicitRegister)
1524 if (i.types[1] & ImplicitRegister)
1526 if (i.types[2] & ImplicitRegister)
1529 if (i.tm.opcode_modifier & ImmExt)
1533 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1535 /* These Intel Prescott New Instructions have the fixed
1536 operands with an opcode suffix which is coded in the same
1537 place as an 8-bit immediate field would be. Here we check
1538 those operands and remove them afterwards. */
1541 for (x = 0; x < i.operands; x++)
1542 if (i.op[x].regs->reg_num != x)
1543 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1544 i.op[x].regs->reg_name, x + 1, i.tm.name);
1548 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1549 opcode suffix which is coded in the same place as an 8-bit
1550 immediate field would be. Here we fake an 8-bit immediate
1551 operand from the opcode suffix stored in tm.extension_opcode. */
1553 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1555 exp = &im_expressions[i.imm_operands++];
1556 i.op[i.operands].imms = exp;
1557 i.types[i.operands++] = Imm8;
1558 exp->X_op = O_constant;
1559 exp->X_add_number = i.tm.extension_opcode;
1560 i.tm.extension_opcode = None;
1563 /* For insns with operands there are more diddles to do to the opcode. */
1566 if (!process_operands ())
1569 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1571 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1572 as_warn (_("translating to `%sp'"), i.tm.name);
1575 /* Handle conversion of 'int $3' --> special int3 insn. */
1576 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1578 i.tm.base_opcode = INT3_OPCODE;
1582 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1583 && i.op[0].disps->X_op == O_constant)
1585 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1586 the absolute address given by the constant. Since ix86 jumps and
1587 calls are pc relative, we need to generate a reloc. */
1588 i.op[0].disps->X_add_symbol = &abs_symbol;
1589 i.op[0].disps->X_op = O_symbol;
1592 if ((i.tm.opcode_modifier & Rex64) != 0)
1593 i.rex |= REX_MODE64;
1595 /* For 8 bit registers we need an empty rex prefix. Also if the
1596 instruction already has a prefix, we need to convert old
1597 registers to new ones. */
1599 if (((i.types[0] & Reg8) != 0
1600 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1601 || ((i.types[1] & Reg8) != 0
1602 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1603 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1608 i.rex |= REX_OPCODE;
1609 for (x = 0; x < 2; x++)
1611 /* Look for 8 bit operand that uses old registers. */
1612 if ((i.types[x] & Reg8) != 0
1613 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1615 /* In case it is "hi" register, give up. */
1616 if (i.op[x].regs->reg_num > 3)
1617 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
1618 i.op[x].regs->reg_name);
1620 /* Otherwise it is equivalent to the extended register.
1621 Since the encoding doesn't change this is merely
1622 cosmetic cleanup for debug output. */
1624 i.op[x].regs = i.op[x].regs + 8;
1630 add_prefix (REX_OPCODE | i.rex);
1632 /* We are ready to output the insn. */
1637 parse_insn (line, mnemonic)
1642 char *token_start = l;
1647 /* Non-zero if we found a prefix only acceptable with string insns. */
1648 const char *expecting_string_instruction = NULL;
1653 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1656 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1658 as_bad (_("no such instruction: `%s'"), token_start);
1663 if (!is_space_char (*l)
1664 && *l != END_OF_INSN
1666 || (*l != PREFIX_SEPARATOR
1669 as_bad (_("invalid character %s in mnemonic"),
1670 output_invalid (*l));
1673 if (token_start == l)
1675 if (!intel_syntax && *l == PREFIX_SEPARATOR)
1676 as_bad (_("expecting prefix; got nothing"));
1678 as_bad (_("expecting mnemonic; got nothing"));
1682 /* Look up instruction (or prefix) via hash table. */
1683 current_templates = hash_find (op_hash, mnemonic);
1685 if (*l != END_OF_INSN
1686 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1687 && current_templates
1688 && (current_templates->start->opcode_modifier & IsPrefix))
1690 if (current_templates->start->cpu_flags
1691 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1693 as_bad ((flag_code != CODE_64BIT
1694 ? _("`%s' is only supported in 64-bit mode")
1695 : _("`%s' is not supported in 64-bit mode")),
1696 current_templates->start->name);
1699 /* If we are in 16-bit mode, do not allow addr16 or data16.
1700 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1701 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1702 && flag_code != CODE_64BIT
1703 && (((current_templates->start->opcode_modifier & Size32) != 0)
1704 ^ (flag_code == CODE_16BIT)))
1706 as_bad (_("redundant %s prefix"),
1707 current_templates->start->name);
1710 /* Add prefix, checking for repeated prefixes. */
1711 switch (add_prefix (current_templates->start->base_opcode))
1716 expecting_string_instruction = current_templates->start->name;
1719 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1726 if (!current_templates)
1728 /* See if we can get a match by trimming off a suffix. */
1731 case WORD_MNEM_SUFFIX:
1732 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1733 i.suffix = SHORT_MNEM_SUFFIX;
1735 case BYTE_MNEM_SUFFIX:
1736 case QWORD_MNEM_SUFFIX:
1737 i.suffix = mnem_p[-1];
1739 current_templates = hash_find (op_hash, mnemonic);
1741 case SHORT_MNEM_SUFFIX:
1742 case LONG_MNEM_SUFFIX:
1745 i.suffix = mnem_p[-1];
1747 current_templates = hash_find (op_hash, mnemonic);
1755 if (intel_float_operand (mnemonic) == 1)
1756 i.suffix = SHORT_MNEM_SUFFIX;
1758 i.suffix = LONG_MNEM_SUFFIX;
1760 current_templates = hash_find (op_hash, mnemonic);
1764 if (!current_templates)
1766 as_bad (_("no such instruction: `%s'"), token_start);
1771 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1773 /* Check for a branch hint. We allow ",pt" and ",pn" for
1774 predict taken and predict not taken respectively.
1775 I'm not sure that branch hints actually do anything on loop
1776 and jcxz insns (JumpByte) for current Pentium4 chips. They
1777 may work in the future and it doesn't hurt to accept them
1779 if (l[0] == ',' && l[1] == 'p')
1783 if (!add_prefix (DS_PREFIX_OPCODE))
1787 else if (l[2] == 'n')
1789 if (!add_prefix (CS_PREFIX_OPCODE))
1795 /* Any other comma loses. */
1798 as_bad (_("invalid character %s in mnemonic"),
1799 output_invalid (*l));
1803 /* Check if instruction is supported on specified architecture. */
1805 for (t = current_templates->start; t < current_templates->end; ++t)
1807 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1808 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1810 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1813 if (!(supported & 2))
1815 as_bad (flag_code == CODE_64BIT
1816 ? _("`%s' is not supported in 64-bit mode")
1817 : _("`%s' is only supported in 64-bit mode"),
1818 current_templates->start->name);
1821 if (!(supported & 1))
1823 as_warn (_("`%s' is not supported on `%s%s'"),
1824 current_templates->start->name,
1826 cpu_sub_arch_name ? cpu_sub_arch_name : "");
1828 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1830 as_warn (_("use .code16 to ensure correct addressing mode"));
1833 /* Check for rep/repne without a string instruction. */
1834 if (expecting_string_instruction)
1836 static templates override;
1838 for (t = current_templates->start; t < current_templates->end; ++t)
1839 if (t->opcode_modifier & IsString)
1841 if (t >= current_templates->end)
1843 as_bad (_("expecting string instruction after `%s'"),
1844 expecting_string_instruction);
1847 for (override.start = t; t < current_templates->end; ++t)
1848 if (!(t->opcode_modifier & IsString))
1851 current_templates = &override;
1858 parse_operands (l, mnemonic)
1860 const char *mnemonic;
1864 /* 1 if operand is pending after ','. */
1865 unsigned int expecting_operand = 0;
1867 /* Non-zero if operand parens not balanced. */
1868 unsigned int paren_not_balanced;
1870 while (*l != END_OF_INSN)
1872 /* Skip optional white space before operand. */
1873 if (is_space_char (*l))
1875 if (!is_operand_char (*l) && *l != END_OF_INSN)
1877 as_bad (_("invalid character %s before operand %d"),
1878 output_invalid (*l),
1882 token_start = l; /* after white space */
1883 paren_not_balanced = 0;
1884 while (paren_not_balanced || *l != ',')
1886 if (*l == END_OF_INSN)
1888 if (paren_not_balanced)
1891 as_bad (_("unbalanced parenthesis in operand %d."),
1894 as_bad (_("unbalanced brackets in operand %d."),
1899 break; /* we are done */
1901 else if (!is_operand_char (*l) && !is_space_char (*l))
1903 as_bad (_("invalid character %s in operand %d"),
1904 output_invalid (*l),
1911 ++paren_not_balanced;
1913 --paren_not_balanced;
1918 ++paren_not_balanced;
1920 --paren_not_balanced;
1924 if (l != token_start)
1925 { /* Yes, we've read in another operand. */
1926 unsigned int operand_ok;
1927 this_operand = i.operands++;
1928 if (i.operands > MAX_OPERANDS)
1930 as_bad (_("spurious operands; (%d operands/instruction max)"),
1934 /* Now parse operand adding info to 'i' as we go along. */
1935 END_STRING_AND_SAVE (l);
1939 i386_intel_operand (token_start,
1940 intel_float_operand (mnemonic));
1942 operand_ok = i386_operand (token_start);
1944 RESTORE_END_STRING (l);
1950 if (expecting_operand)
1952 expecting_operand_after_comma:
1953 as_bad (_("expecting operand after ','; got nothing"));
1958 as_bad (_("expecting operand before ','; got nothing"));
1963 /* Now *l must be either ',' or END_OF_INSN. */
1966 if (*++l == END_OF_INSN)
1968 /* Just skip it, if it's \n complain. */
1969 goto expecting_operand_after_comma;
1971 expecting_operand = 1;
1980 union i386_op temp_op;
1981 unsigned int temp_type;
1982 enum bfd_reloc_code_real temp_reloc;
1986 if (i.operands == 2)
1991 else if (i.operands == 3)
1996 temp_type = i.types[xchg2];
1997 i.types[xchg2] = i.types[xchg1];
1998 i.types[xchg1] = temp_type;
1999 temp_op = i.op[xchg2];
2000 i.op[xchg2] = i.op[xchg1];
2001 i.op[xchg1] = temp_op;
2002 temp_reloc = i.reloc[xchg2];
2003 i.reloc[xchg2] = i.reloc[xchg1];
2004 i.reloc[xchg1] = temp_reloc;
2006 if (i.mem_operands == 2)
2008 const seg_entry *temp_seg;
2009 temp_seg = i.seg[0];
2010 i.seg[0] = i.seg[1];
2011 i.seg[1] = temp_seg;
2015 /* Try to ensure constant immediates are represented in the smallest
2020 char guess_suffix = 0;
2024 guess_suffix = i.suffix;
2025 else if (i.reg_operands)
2027 /* Figure out a suffix from the last register operand specified.
2028 We can't do this properly yet, ie. excluding InOutPortReg,
2029 but the following works for instructions with immediates.
2030 In any case, we can't set i.suffix yet. */
2031 for (op = i.operands; --op >= 0;)
2032 if (i.types[op] & Reg)
2034 if (i.types[op] & Reg8)
2035 guess_suffix = BYTE_MNEM_SUFFIX;
2036 else if (i.types[op] & Reg16)
2037 guess_suffix = WORD_MNEM_SUFFIX;
2038 else if (i.types[op] & Reg32)
2039 guess_suffix = LONG_MNEM_SUFFIX;
2040 else if (i.types[op] & Reg64)
2041 guess_suffix = QWORD_MNEM_SUFFIX;
2045 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2046 guess_suffix = WORD_MNEM_SUFFIX;
2048 for (op = i.operands; --op >= 0;)
2049 if (i.types[op] & Imm)
2051 switch (i.op[op].imms->X_op)
2054 /* If a suffix is given, this operand may be shortened. */
2055 switch (guess_suffix)
2057 case LONG_MNEM_SUFFIX:
2058 i.types[op] |= Imm32 | Imm64;
2060 case WORD_MNEM_SUFFIX:
2061 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2063 case BYTE_MNEM_SUFFIX:
2064 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2068 /* If this operand is at most 16 bits, convert it
2069 to a signed 16 bit number before trying to see
2070 whether it will fit in an even smaller size.
2071 This allows a 16-bit operand such as $0xffe0 to
2072 be recognised as within Imm8S range. */
2073 if ((i.types[op] & Imm16)
2074 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
2076 i.op[op].imms->X_add_number =
2077 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2079 if ((i.types[op] & Imm32)
2080 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2083 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2084 ^ ((offsetT) 1 << 31))
2085 - ((offsetT) 1 << 31));
2087 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
2089 /* We must avoid matching of Imm32 templates when 64bit
2090 only immediate is available. */
2091 if (guess_suffix == QWORD_MNEM_SUFFIX)
2092 i.types[op] &= ~Imm32;
2099 /* Symbols and expressions. */
2101 /* Convert symbolic operand to proper sizes for matching, but don't
2102 prevent matching a set of insns that only supports sizes other
2103 than those matching the insn suffix. */
2105 unsigned int mask, allowed = 0;
2108 for (t = current_templates->start; t < current_templates->end; ++t)
2109 allowed |= t->operand_types[op];
2110 switch (guess_suffix)
2112 case QWORD_MNEM_SUFFIX:
2113 mask = Imm64 | Imm32S;
2115 case LONG_MNEM_SUFFIX:
2118 case WORD_MNEM_SUFFIX:
2121 case BYTE_MNEM_SUFFIX:
2129 i.types[op] &= mask;
2136 /* Try to use the smallest displacement type too. */
2142 for (op = i.operands; --op >= 0;)
2143 if (i.types[op] & Disp)
2145 if (i.op[op].disps->X_op == O_constant)
2147 offsetT disp = i.op[op].disps->X_add_number;
2149 if ((i.types[op] & Disp16)
2150 && (disp & ~(offsetT) 0xffff) == 0)
2152 /* If this operand is at most 16 bits, convert
2153 to a signed 16 bit number and don't use 64bit
2155 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2156 i.types[op] &= ~Disp64;
2158 if ((i.types[op] & Disp32)
2159 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2161 /* If this operand is at most 32 bits, convert
2162 to a signed 32 bit number and don't use 64bit
2164 disp &= (((offsetT) 2 << 31) - 1);
2165 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2166 i.types[op] &= ~Disp64;
2168 if (!disp && (i.types[op] & BaseIndex))
2170 i.types[op] &= ~Disp;
2174 else if (flag_code == CODE_64BIT)
2176 if (fits_in_signed_long (disp))
2178 i.types[op] &= ~Disp64;
2179 i.types[op] |= Disp32S;
2181 if (fits_in_unsigned_long (disp))
2182 i.types[op] |= Disp32;
2184 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2185 && fits_in_signed_byte (disp))
2186 i.types[op] |= Disp8;
2189 /* We only support 64bit displacement on constants. */
2190 i.types[op] &= ~Disp64;
2197 /* Points to template once we've found it. */
2199 unsigned int overlap0, overlap1, overlap2;
2200 unsigned int found_reverse_match;
2203 #define MATCH(overlap, given, template) \
2204 ((overlap & ~JumpAbsolute) \
2205 && (((given) & (BaseIndex | JumpAbsolute)) \
2206 == ((overlap) & (BaseIndex | JumpAbsolute))))
2208 /* If given types r0 and r1 are registers they must be of the same type
2209 unless the expected operand type register overlap is null.
2210 Note that Acc in a template matches every size of reg. */
2211 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2212 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2213 || ((g0) & Reg) == ((g1) & Reg) \
2214 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2219 found_reverse_match = 0;
2220 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2222 : (i.suffix == WORD_MNEM_SUFFIX
2224 : (i.suffix == SHORT_MNEM_SUFFIX
2226 : (i.suffix == LONG_MNEM_SUFFIX
2228 : (i.suffix == QWORD_MNEM_SUFFIX
2230 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2231 ? No_xSuf : 0))))));
2233 t = current_templates->start;
2234 if (i.suffix == QWORD_MNEM_SUFFIX
2235 && flag_code != CODE_64BIT
2237 ? !(t->opcode_modifier & IgnoreSize)
2238 && !intel_float_operand (t->name)
2239 : intel_float_operand (t->name) != 2)
2240 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2241 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2242 && (t->base_opcode != 0x0fc7
2243 || t->extension_opcode != 1 /* cmpxchg8b */))
2244 t = current_templates->end;
2245 for (; t < current_templates->end; t++)
2247 /* Must have right number of operands. */
2248 if (i.operands != t->operands)
2251 /* Check the suffix, except for some instructions in intel mode. */
2252 if ((t->opcode_modifier & suffix_check)
2254 && (t->opcode_modifier & IgnoreSize)))
2257 /* Do not verify operands when there are none. */
2258 else if (!t->operands)
2260 if (t->cpu_flags & ~cpu_arch_flags)
2262 /* We've found a match; break out of loop. */
2266 overlap0 = i.types[0] & t->operand_types[0];
2267 switch (t->operands)
2270 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2275 overlap1 = i.types[1] & t->operand_types[1];
2276 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2277 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2278 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2279 t->operand_types[0],
2280 overlap1, i.types[1],
2281 t->operand_types[1]))
2283 /* Check if other direction is valid ... */
2284 if ((t->opcode_modifier & (D | FloatD)) == 0)
2287 /* Try reversing direction of operands. */
2288 overlap0 = i.types[0] & t->operand_types[1];
2289 overlap1 = i.types[1] & t->operand_types[0];
2290 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2291 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2292 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2293 t->operand_types[1],
2294 overlap1, i.types[1],
2295 t->operand_types[0]))
2297 /* Does not match either direction. */
2300 /* found_reverse_match holds which of D or FloatDR
2302 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2304 /* Found a forward 2 operand match here. */
2305 else if (t->operands == 3)
2307 /* Here we make use of the fact that there are no
2308 reverse match 3 operand instructions, and all 3
2309 operand instructions only need to be checked for
2310 register consistency between operands 2 and 3. */
2311 overlap2 = i.types[2] & t->operand_types[2];
2312 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2313 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2314 t->operand_types[1],
2315 overlap2, i.types[2],
2316 t->operand_types[2]))
2320 /* Found either forward/reverse 2 or 3 operand match here:
2321 slip through to break. */
2323 if (t->cpu_flags & ~cpu_arch_flags)
2325 found_reverse_match = 0;
2328 /* We've found a match; break out of loop. */
2332 if (t == current_templates->end)
2334 /* We found no match. */
2335 as_bad (_("suffix or operands invalid for `%s'"),
2336 current_templates->start->name);
2340 if (!quiet_warnings)
2343 && ((i.types[0] & JumpAbsolute)
2344 != (t->operand_types[0] & JumpAbsolute)))
2346 as_warn (_("indirect %s without `*'"), t->name);
2349 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2350 == (IsPrefix | IgnoreSize))
2352 /* Warn them that a data or address size prefix doesn't
2353 affect assembly of the next line of code. */
2354 as_warn (_("stand-alone `%s' prefix"), t->name);
2358 /* Copy the template we found. */
2360 if (found_reverse_match)
2362 /* If we found a reverse match we must alter the opcode
2363 direction bit. found_reverse_match holds bits to change
2364 (different for int & float insns). */
2366 i.tm.base_opcode ^= found_reverse_match;
2368 i.tm.operand_types[0] = t->operand_types[1];
2369 i.tm.operand_types[1] = t->operand_types[0];
2378 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2379 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2381 if (i.seg[0] != NULL && i.seg[0] != &es)
2383 as_bad (_("`%s' operand %d must use `%%es' segment"),
2388 /* There's only ever one segment override allowed per instruction.
2389 This instruction possibly has a legal segment override on the
2390 second operand, so copy the segment to where non-string
2391 instructions store it, allowing common code. */
2392 i.seg[0] = i.seg[1];
2394 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2396 if (i.seg[1] != NULL && i.seg[1] != &es)
2398 as_bad (_("`%s' operand %d must use `%%es' segment"),
2408 process_suffix (void)
2410 /* If matched instruction specifies an explicit instruction mnemonic
2412 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2414 if (i.tm.opcode_modifier & Size16)
2415 i.suffix = WORD_MNEM_SUFFIX;
2416 else if (i.tm.opcode_modifier & Size64)
2417 i.suffix = QWORD_MNEM_SUFFIX;
2419 i.suffix = LONG_MNEM_SUFFIX;
2421 else if (i.reg_operands)
2423 /* If there's no instruction mnemonic suffix we try to invent one
2424 based on register operands. */
2427 /* We take i.suffix from the last register operand specified,
2428 Destination register type is more significant than source
2432 for (op = i.operands; --op >= 0;)
2433 if ((i.types[op] & Reg)
2434 && !(i.tm.operand_types[op] & InOutPortReg))
2436 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2437 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2438 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2443 else if (i.suffix == BYTE_MNEM_SUFFIX)
2445 if (!check_byte_reg ())
2448 else if (i.suffix == LONG_MNEM_SUFFIX)
2450 if (!check_long_reg ())
2453 else if (i.suffix == QWORD_MNEM_SUFFIX)
2455 if (!check_qword_reg ())
2458 else if (i.suffix == WORD_MNEM_SUFFIX)
2460 if (!check_word_reg ())
2463 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2464 /* Do nothing if the instruction is going to ignore the prefix. */
2469 else if ((i.tm.opcode_modifier & DefaultSize)
2471 /* exclude fldenv/frstor/fsave/fstenv */
2472 && (i.tm.opcode_modifier & No_sSuf))
2474 i.suffix = stackop_size;
2476 else if (intel_syntax
2478 && ((i.tm.operand_types[0] & JumpAbsolute)
2479 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2480 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2481 && i.tm.extension_opcode <= 3)))
2486 if (!(i.tm.opcode_modifier & No_qSuf))
2488 i.suffix = QWORD_MNEM_SUFFIX;
2492 if (!(i.tm.opcode_modifier & No_lSuf))
2493 i.suffix = LONG_MNEM_SUFFIX;
2496 if (!(i.tm.opcode_modifier & No_wSuf))
2497 i.suffix = WORD_MNEM_SUFFIX;
2506 if (i.tm.opcode_modifier & W)
2508 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2514 unsigned int suffixes = ~i.tm.opcode_modifier
2522 if ((i.tm.opcode_modifier & W)
2523 || ((suffixes & (suffixes - 1))
2524 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2526 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2532 /* Change the opcode based on the operand size given by i.suffix;
2533 We don't need to change things for byte insns. */
2535 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2537 /* It's not a byte, select word/dword operation. */
2538 if (i.tm.opcode_modifier & W)
2540 if (i.tm.opcode_modifier & ShortForm)
2541 i.tm.base_opcode |= 8;
2543 i.tm.base_opcode |= 1;
2546 /* Now select between word & dword operations via the operand
2547 size prefix, except for instructions that will ignore this
2549 if (i.suffix != QWORD_MNEM_SUFFIX
2550 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2551 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2552 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2553 || (flag_code == CODE_64BIT
2554 && (i.tm.opcode_modifier & JumpByte))))
2556 unsigned int prefix = DATA_PREFIX_OPCODE;
2558 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2559 prefix = ADDR_PREFIX_OPCODE;
2561 if (!add_prefix (prefix))
2565 /* Set mode64 for an operand. */
2566 if (i.suffix == QWORD_MNEM_SUFFIX
2567 && flag_code == CODE_64BIT
2568 && (i.tm.opcode_modifier & NoRex64) == 0)
2569 i.rex |= REX_MODE64;
2571 /* Size floating point instruction. */
2572 if (i.suffix == LONG_MNEM_SUFFIX)
2573 if (i.tm.opcode_modifier & FloatMF)
2574 i.tm.base_opcode ^= 4;
2581 check_byte_reg (void)
2585 for (op = i.operands; --op >= 0;)
2587 /* If this is an eight bit register, it's OK. If it's the 16 or
2588 32 bit version of an eight bit register, we will just use the
2589 low portion, and that's OK too. */
2590 if (i.types[op] & Reg8)
2593 /* movzx and movsx should not generate this warning. */
2595 && (i.tm.base_opcode == 0xfb7
2596 || i.tm.base_opcode == 0xfb6
2597 || i.tm.base_opcode == 0x63
2598 || i.tm.base_opcode == 0xfbe
2599 || i.tm.base_opcode == 0xfbf))
2602 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
2604 /* Prohibit these changes in the 64bit mode, since the
2605 lowering is more complicated. */
2606 if (flag_code == CODE_64BIT
2607 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2609 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2610 i.op[op].regs->reg_name,
2614 #if REGISTER_WARNINGS
2616 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2617 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2618 (i.op[op].regs + (i.types[op] & Reg16
2619 ? REGNAM_AL - REGNAM_AX
2620 : REGNAM_AL - REGNAM_EAX))->reg_name,
2621 i.op[op].regs->reg_name,
2626 /* Any other register is bad. */
2627 if (i.types[op] & (Reg | RegMMX | RegXMM
2629 | Control | Debug | Test
2630 | FloatReg | FloatAcc))
2632 as_bad (_("`%%%s' not allowed with `%s%c'"),
2633 i.op[op].regs->reg_name,
2647 for (op = i.operands; --op >= 0;)
2648 /* Reject eight bit registers, except where the template requires
2649 them. (eg. movzb) */
2650 if ((i.types[op] & Reg8) != 0
2651 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2653 as_bad (_("`%%%s' not allowed with `%s%c'"),
2654 i.op[op].regs->reg_name,
2659 /* Warn if the e prefix on a general reg is missing. */
2660 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2661 && (i.types[op] & Reg16) != 0
2662 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2664 /* Prohibit these changes in the 64bit mode, since the
2665 lowering is more complicated. */
2666 if (flag_code == CODE_64BIT)
2668 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2669 i.op[op].regs->reg_name,
2673 #if REGISTER_WARNINGS
2675 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2676 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2677 i.op[op].regs->reg_name,
2681 /* Warn if the r prefix on a general reg is missing. */
2682 else if ((i.types[op] & Reg64) != 0
2683 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2685 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2686 i.op[op].regs->reg_name,
2698 for (op = i.operands; --op >= 0; )
2699 /* Reject eight bit registers, except where the template requires
2700 them. (eg. movzb) */
2701 if ((i.types[op] & Reg8) != 0
2702 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2704 as_bad (_("`%%%s' not allowed with `%s%c'"),
2705 i.op[op].regs->reg_name,
2710 /* Warn if the e prefix on a general reg is missing. */
2711 else if (((i.types[op] & Reg16) != 0
2712 || (i.types[op] & Reg32) != 0)
2713 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2715 /* Prohibit these changes in the 64bit mode, since the
2716 lowering is more complicated. */
2717 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2718 i.op[op].regs->reg_name,
2729 for (op = i.operands; --op >= 0;)
2730 /* Reject eight bit registers, except where the template requires
2731 them. (eg. movzb) */
2732 if ((i.types[op] & Reg8) != 0
2733 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2735 as_bad (_("`%%%s' not allowed with `%s%c'"),
2736 i.op[op].regs->reg_name,
2741 /* Warn if the e prefix on a general reg is present. */
2742 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2743 && (i.types[op] & Reg32) != 0
2744 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2746 /* Prohibit these changes in the 64bit mode, since the
2747 lowering is more complicated. */
2748 if (flag_code == CODE_64BIT)
2750 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2751 i.op[op].regs->reg_name,
2756 #if REGISTER_WARNINGS
2757 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2758 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2759 i.op[op].regs->reg_name,
2769 unsigned int overlap0, overlap1, overlap2;
2771 overlap0 = i.types[0] & i.tm.operand_types[0];
2772 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
2773 && overlap0 != Imm8 && overlap0 != Imm8S
2774 && overlap0 != Imm16 && overlap0 != Imm32S
2775 && overlap0 != Imm32 && overlap0 != Imm64)
2779 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2781 : (i.suffix == WORD_MNEM_SUFFIX
2783 : (i.suffix == QWORD_MNEM_SUFFIX
2787 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2788 || overlap0 == (Imm16 | Imm32)
2789 || overlap0 == (Imm16 | Imm32S))
2791 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2794 if (overlap0 != Imm8 && overlap0 != Imm8S
2795 && overlap0 != Imm16 && overlap0 != Imm32S
2796 && overlap0 != Imm32 && overlap0 != Imm64)
2798 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2802 i.types[0] = overlap0;
2804 overlap1 = i.types[1] & i.tm.operand_types[1];
2805 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
2806 && overlap1 != Imm8 && overlap1 != Imm8S
2807 && overlap1 != Imm16 && overlap1 != Imm32S
2808 && overlap1 != Imm32 && overlap1 != Imm64)
2812 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2814 : (i.suffix == WORD_MNEM_SUFFIX
2816 : (i.suffix == QWORD_MNEM_SUFFIX
2820 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2821 || overlap1 == (Imm16 | Imm32)
2822 || overlap1 == (Imm16 | Imm32S))
2824 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2827 if (overlap1 != Imm8 && overlap1 != Imm8S
2828 && overlap1 != Imm16 && overlap1 != Imm32S
2829 && overlap1 != Imm32 && overlap1 != Imm64)
2831 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2835 i.types[1] = overlap1;
2837 overlap2 = i.types[2] & i.tm.operand_types[2];
2838 assert ((overlap2 & Imm) == 0);
2839 i.types[2] = overlap2;
2847 /* Default segment register this instruction will use for memory
2848 accesses. 0 means unknown. This is only for optimizing out
2849 unnecessary segment overrides. */
2850 const seg_entry *default_seg = 0;
2852 /* The imul $imm, %reg instruction is converted into
2853 imul $imm, %reg, %reg, and the clr %reg instruction
2854 is converted into xor %reg, %reg. */
2855 if (i.tm.opcode_modifier & regKludge)
2857 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2858 /* Pretend we saw the extra register operand. */
2859 assert (i.op[first_reg_op + 1].regs == 0);
2860 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2861 i.types[first_reg_op + 1] = i.types[first_reg_op];
2865 if (i.tm.opcode_modifier & ShortForm)
2867 /* The register or float register operand is in operand 0 or 1. */
2868 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2869 /* Register goes in low 3 bits of opcode. */
2870 i.tm.base_opcode |= i.op[op].regs->reg_num;
2871 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2873 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2875 /* Warn about some common errors, but press on regardless.
2876 The first case can be generated by gcc (<= 2.8.1). */
2877 if (i.operands == 2)
2879 /* Reversed arguments on faddp, fsubp, etc. */
2880 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2881 i.op[1].regs->reg_name,
2882 i.op[0].regs->reg_name);
2886 /* Extraneous `l' suffix on fp insn. */
2887 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2888 i.op[0].regs->reg_name);
2892 else if (i.tm.opcode_modifier & Modrm)
2894 /* The opcode is completed (modulo i.tm.extension_opcode which
2895 must be put into the modrm byte). Now, we make the modrm and
2896 index base bytes based on all the info we've collected. */
2898 default_seg = build_modrm_byte ();
2900 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2902 if (i.tm.base_opcode == POP_SEG_SHORT
2903 && i.op[0].regs->reg_num == 1)
2905 as_bad (_("you can't `pop %%cs'"));
2908 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2909 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2912 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2916 else if ((i.tm.opcode_modifier & IsString) != 0)
2918 /* For the string instructions that allow a segment override
2919 on one of their operands, the default segment is ds. */
2923 if ((i.tm.base_opcode == 0x8d /* lea */
2924 || (i.tm.cpu_flags & CpuSVME))
2925 && i.seg[0] && !quiet_warnings)
2926 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
2928 /* If a segment was explicitly specified, and the specified segment
2929 is not the default, use an opcode prefix to select it. If we
2930 never figured out what the default segment is, then default_seg
2931 will be zero at this point, and the specified segment prefix will
2933 if ((i.seg[0]) && (i.seg[0] != default_seg))
2935 if (!add_prefix (i.seg[0]->seg_prefix))
2941 static const seg_entry *
2944 const seg_entry *default_seg = 0;
2946 /* i.reg_operands MUST be the number of real register operands;
2947 implicit registers do not count. */
2948 if (i.reg_operands == 2)
2950 unsigned int source, dest;
2951 source = ((i.types[0]
2952 & (Reg | RegMMX | RegXMM
2954 | Control | Debug | Test))
2959 /* One of the register operands will be encoded in the i.tm.reg
2960 field, the other in the combined i.tm.mode and i.tm.regmem
2961 fields. If no form of this instruction supports a memory
2962 destination operand, then we assume the source operand may
2963 sometimes be a memory operand and so we need to store the
2964 destination in the i.rm.reg field. */
2965 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2967 i.rm.reg = i.op[dest].regs->reg_num;
2968 i.rm.regmem = i.op[source].regs->reg_num;
2969 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2971 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2976 i.rm.reg = i.op[source].regs->reg_num;
2977 i.rm.regmem = i.op[dest].regs->reg_num;
2978 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2980 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2983 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2985 if (!((i.types[0] | i.types[1]) & Control))
2987 i.rex &= ~(REX_EXTX | REX_EXTZ);
2988 add_prefix (LOCK_PREFIX_OPCODE);
2992 { /* If it's not 2 reg operands... */
2995 unsigned int fake_zero_displacement = 0;
2996 unsigned int op = ((i.types[0] & AnyMem)
2998 : (i.types[1] & AnyMem) ? 1 : 2);
3002 if (i.base_reg == 0)
3005 if (!i.disp_operands)
3006 fake_zero_displacement = 1;
3007 if (i.index_reg == 0)
3009 /* Operand is just <disp> */
3010 if (flag_code == CODE_64BIT)
3012 /* 64bit mode overwrites the 32bit absolute
3013 addressing by RIP relative addressing and
3014 absolute addressing is encoded by one of the
3015 redundant SIB forms. */
3016 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3017 i.sib.base = NO_BASE_REGISTER;
3018 i.sib.index = NO_INDEX_REGISTER;
3019 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3021 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3023 i.rm.regmem = NO_BASE_REGISTER_16;
3024 i.types[op] = Disp16;
3028 i.rm.regmem = NO_BASE_REGISTER;
3029 i.types[op] = Disp32;
3032 else /* !i.base_reg && i.index_reg */
3034 i.sib.index = i.index_reg->reg_num;
3035 i.sib.base = NO_BASE_REGISTER;
3036 i.sib.scale = i.log2_scale_factor;
3037 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3038 i.types[op] &= ~Disp;
3039 if (flag_code != CODE_64BIT)
3040 i.types[op] |= Disp32; /* Must be 32 bit */
3042 i.types[op] |= Disp32S;
3043 if ((i.index_reg->reg_flags & RegRex) != 0)
3047 /* RIP addressing for 64bit mode. */
3048 else if (i.base_reg->reg_type == BaseIndex)
3050 i.rm.regmem = NO_BASE_REGISTER;
3051 i.types[op] &= ~ Disp;
3052 i.types[op] |= Disp32S;
3053 i.flags[op] = Operand_PCrel;
3054 if (! i.disp_operands)
3055 fake_zero_displacement = 1;
3057 else if (i.base_reg->reg_type & Reg16)
3059 switch (i.base_reg->reg_num)
3062 if (i.index_reg == 0)
3064 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3065 i.rm.regmem = i.index_reg->reg_num - 6;
3069 if (i.index_reg == 0)
3072 if ((i.types[op] & Disp) == 0)
3074 /* fake (%bp) into 0(%bp) */
3075 i.types[op] |= Disp8;
3076 fake_zero_displacement = 1;
3079 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3080 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3082 default: /* (%si) -> 4 or (%di) -> 5 */
3083 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3085 i.rm.mode = mode_from_disp_size (i.types[op]);
3087 else /* i.base_reg and 32/64 bit mode */
3089 if (flag_code == CODE_64BIT
3090 && (i.types[op] & Disp))
3091 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3093 i.rm.regmem = i.base_reg->reg_num;
3094 if ((i.base_reg->reg_flags & RegRex) != 0)
3096 i.sib.base = i.base_reg->reg_num;
3097 /* x86-64 ignores REX prefix bit here to avoid decoder
3099 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3102 if (i.disp_operands == 0)
3104 fake_zero_displacement = 1;
3105 i.types[op] |= Disp8;
3108 else if (i.base_reg->reg_num == ESP_REG_NUM)
3112 i.sib.scale = i.log2_scale_factor;
3113 if (i.index_reg == 0)
3115 /* <disp>(%esp) becomes two byte modrm with no index
3116 register. We've already stored the code for esp
3117 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3118 Any base register besides %esp will not use the
3119 extra modrm byte. */
3120 i.sib.index = NO_INDEX_REGISTER;
3121 #if !SCALE1_WHEN_NO_INDEX
3122 /* Another case where we force the second modrm byte. */
3123 if (i.log2_scale_factor)
3124 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3129 i.sib.index = i.index_reg->reg_num;
3130 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3131 if ((i.index_reg->reg_flags & RegRex) != 0)
3134 i.rm.mode = mode_from_disp_size (i.types[op]);
3137 if (fake_zero_displacement)
3139 /* Fakes a zero displacement assuming that i.types[op]
3140 holds the correct displacement size. */
3143 assert (i.op[op].disps == 0);
3144 exp = &disp_expressions[i.disp_operands++];
3145 i.op[op].disps = exp;
3146 exp->X_op = O_constant;
3147 exp->X_add_number = 0;
3148 exp->X_add_symbol = (symbolS *) 0;
3149 exp->X_op_symbol = (symbolS *) 0;
3153 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3154 (if any) based on i.tm.extension_opcode. Again, we must be
3155 careful to make sure that segment/control/debug/test/MMX
3156 registers are coded into the i.rm.reg field. */
3161 & (Reg | RegMMX | RegXMM
3163 | Control | Debug | Test))
3166 & (Reg | RegMMX | RegXMM
3168 | Control | Debug | Test))
3171 /* If there is an extension opcode to put here, the register
3172 number must be put into the regmem field. */
3173 if (i.tm.extension_opcode != None)
3175 i.rm.regmem = i.op[op].regs->reg_num;
3176 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3181 i.rm.reg = i.op[op].regs->reg_num;
3182 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3186 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3187 must set it to 3 to indicate this is a register operand
3188 in the regmem field. */
3189 if (!i.mem_operands)
3193 /* Fill in i.rm.reg field with extension opcode (if any). */
3194 if (i.tm.extension_opcode != None)
3195 i.rm.reg = i.tm.extension_opcode;
3206 relax_substateT subtype;
3211 if (flag_code == CODE_16BIT)
3215 if (i.prefix[DATA_PREFIX] != 0)
3221 /* Pentium4 branch hints. */
3222 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3223 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3228 if (i.prefix[REX_PREFIX] != 0)
3234 if (i.prefixes != 0 && !intel_syntax)
3235 as_warn (_("skipping prefixes on this instruction"));
3237 /* It's always a symbol; End frag & setup for relax.
3238 Make sure there is enough room in this frag for the largest
3239 instruction we may generate in md_convert_frag. This is 2
3240 bytes for the opcode and room for the prefix and largest
3242 frag_grow (prefix + 2 + 4);
3243 /* Prefix and 1 opcode byte go in fr_fix. */
3244 p = frag_more (prefix + 1);
3245 if (i.prefix[DATA_PREFIX] != 0)
3246 *p++ = DATA_PREFIX_OPCODE;
3247 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3248 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3249 *p++ = i.prefix[SEG_PREFIX];
3250 if (i.prefix[REX_PREFIX] != 0)
3251 *p++ = i.prefix[REX_PREFIX];
3252 *p = i.tm.base_opcode;
3254 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3255 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3256 else if ((cpu_arch_flags & Cpu386) != 0)
3257 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3259 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3262 sym = i.op[0].disps->X_add_symbol;
3263 off = i.op[0].disps->X_add_number;
3265 if (i.op[0].disps->X_op != O_constant
3266 && i.op[0].disps->X_op != O_symbol)
3268 /* Handle complex expressions. */
3269 sym = make_expr_symbol (i.op[0].disps);
3273 /* 1 possible extra opcode + 4 byte displacement go in var part.
3274 Pass reloc in fr_var. */
3275 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3285 if (i.tm.opcode_modifier & JumpByte)
3287 /* This is a loop or jecxz type instruction. */
3289 if (i.prefix[ADDR_PREFIX] != 0)
3291 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3294 /* Pentium4 branch hints. */
3295 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3296 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3298 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3307 if (flag_code == CODE_16BIT)
3310 if (i.prefix[DATA_PREFIX] != 0)
3312 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3322 if (i.prefix[REX_PREFIX] != 0)
3324 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3328 if (i.prefixes != 0 && !intel_syntax)
3329 as_warn (_("skipping prefixes on this instruction"));
3331 p = frag_more (1 + size);
3332 *p++ = i.tm.base_opcode;
3334 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3335 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3337 /* All jumps handled here are signed, but don't use a signed limit
3338 check for 32 and 16 bit jumps as we want to allow wrap around at
3339 4G and 64k respectively. */
3341 fixP->fx_signed = 1;
3345 output_interseg_jump ()
3353 if (flag_code == CODE_16BIT)
3357 if (i.prefix[DATA_PREFIX] != 0)
3363 if (i.prefix[REX_PREFIX] != 0)
3373 if (i.prefixes != 0 && !intel_syntax)
3374 as_warn (_("skipping prefixes on this instruction"));
3376 /* 1 opcode; 2 segment; offset */
3377 p = frag_more (prefix + 1 + 2 + size);
3379 if (i.prefix[DATA_PREFIX] != 0)
3380 *p++ = DATA_PREFIX_OPCODE;
3382 if (i.prefix[REX_PREFIX] != 0)
3383 *p++ = i.prefix[REX_PREFIX];
3385 *p++ = i.tm.base_opcode;
3386 if (i.op[1].imms->X_op == O_constant)
3388 offsetT n = i.op[1].imms->X_add_number;
3391 && !fits_in_unsigned_word (n)
3392 && !fits_in_signed_word (n))
3394 as_bad (_("16-bit jump out of range"));
3397 md_number_to_chars (p, n, size);
3400 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3401 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3402 if (i.op[0].imms->X_op != O_constant)
3403 as_bad (_("can't handle non absolute segment in `%s'"),
3405 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3411 fragS *insn_start_frag;
3412 offsetT insn_start_off;
3414 /* Tie dwarf2 debug info to the address at the start of the insn.
3415 We can't do this after the insn has been output as the current
3416 frag may have been closed off. eg. by frag_var. */
3417 dwarf2_emit_insn (0);
3419 insn_start_frag = frag_now;
3420 insn_start_off = frag_now_fix ();
3423 if (i.tm.opcode_modifier & Jump)
3425 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3427 else if (i.tm.opcode_modifier & JumpInterSegment)
3428 output_interseg_jump ();
3431 /* Output normal instructions here. */
3435 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3436 more higher byte to specify a prefix the instruction
3438 if ((i.tm.base_opcode & 0xff0000) != 0)
3440 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3442 unsigned int prefix;
3443 prefix = (i.tm.base_opcode >> 16) & 0xff;
3445 if (prefix != REPE_PREFIX_OPCODE
3446 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3447 add_prefix (prefix);
3450 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
3453 /* The prefix bytes. */
3455 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3461 md_number_to_chars (p, (valueT) *q, 1);
3465 /* Now the opcode; be careful about word order here! */
3466 if (fits_in_unsigned_byte (i.tm.base_opcode))
3468 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3474 /* Put out high byte first: can't use md_number_to_chars! */
3475 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3476 *p = i.tm.base_opcode & 0xff;
3479 /* Now the modrm byte and sib byte (if present). */
3480 if (i.tm.opcode_modifier & Modrm)
3483 md_number_to_chars (p,
3484 (valueT) (i.rm.regmem << 0
3488 /* If i.rm.regmem == ESP (4)
3489 && i.rm.mode != (Register mode)
3491 ==> need second modrm byte. */
3492 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3494 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3497 md_number_to_chars (p,
3498 (valueT) (i.sib.base << 0
3500 | i.sib.scale << 6),
3505 if (i.disp_operands)
3506 output_disp (insn_start_frag, insn_start_off);
3509 output_imm (insn_start_frag, insn_start_off);
3517 #endif /* DEBUG386 */
3521 output_disp (insn_start_frag, insn_start_off)
3522 fragS *insn_start_frag;
3523 offsetT insn_start_off;
3528 for (n = 0; n < i.operands; n++)
3530 if (i.types[n] & Disp)
3532 if (i.op[n].disps->X_op == O_constant)
3538 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3541 if (i.types[n] & Disp8)
3543 if (i.types[n] & Disp64)
3546 val = offset_in_range (i.op[n].disps->X_add_number,
3548 p = frag_more (size);
3549 md_number_to_chars (p, val, size);
3553 enum bfd_reloc_code_real reloc_type;
3556 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3558 /* The PC relative address is computed relative
3559 to the instruction boundary, so in case immediate
3560 fields follows, we need to adjust the value. */
3561 if (pcrel && i.imm_operands)
3566 for (n1 = 0; n1 < i.operands; n1++)
3567 if (i.types[n1] & Imm)
3569 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3572 if (i.types[n1] & (Imm8 | Imm8S))
3574 if (i.types[n1] & Imm64)
3579 /* We should find the immediate. */
3580 if (n1 == i.operands)
3582 i.op[n].disps->X_add_number -= imm_size;
3585 if (i.types[n] & Disp32S)
3588 if (i.types[n] & (Disp16 | Disp64))
3591 if (i.types[n] & Disp64)
3595 p = frag_more (size);
3596 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3598 && GOT_symbol == i.op[n].disps->X_add_symbol
3599 && (((reloc_type == BFD_RELOC_32
3600 || reloc_type == BFD_RELOC_X86_64_32S)
3601 && (i.op[n].disps->X_op == O_symbol
3602 || (i.op[n].disps->X_op == O_add
3603 && ((symbol_get_value_expression
3604 (i.op[n].disps->X_op_symbol)->X_op)
3606 || reloc_type == BFD_RELOC_32_PCREL))
3610 if (insn_start_frag == frag_now)
3611 add = (p - frag_now->fr_literal) - insn_start_off;
3616 add = insn_start_frag->fr_fix - insn_start_off;
3617 for (fr = insn_start_frag->fr_next;
3618 fr && fr != frag_now; fr = fr->fr_next)
3620 add += p - frag_now->fr_literal;
3624 reloc_type = BFD_RELOC_386_GOTPC;
3626 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3627 i.op[n].disps->X_add_number += add;
3629 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3630 i.op[n].disps, pcrel, reloc_type);
3637 output_imm (insn_start_frag, insn_start_off)
3638 fragS *insn_start_frag;
3639 offsetT insn_start_off;
3644 for (n = 0; n < i.operands; n++)
3646 if (i.types[n] & Imm)
3648 if (i.op[n].imms->X_op == O_constant)
3654 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3657 if (i.types[n] & (Imm8 | Imm8S))
3659 else if (i.types[n] & Imm64)
3662 val = offset_in_range (i.op[n].imms->X_add_number,
3664 p = frag_more (size);
3665 md_number_to_chars (p, val, size);
3669 /* Not absolute_section.
3670 Need a 32-bit fixup (don't support 8bit
3671 non-absolute imms). Try to support other
3673 enum bfd_reloc_code_real reloc_type;
3677 if ((i.types[n] & (Imm32S))
3678 && (i.suffix == QWORD_MNEM_SUFFIX
3679 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
3681 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3684 if (i.types[n] & (Imm8 | Imm8S))
3686 if (i.types[n] & Imm64)
3690 p = frag_more (size);
3691 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3693 /* This is tough to explain. We end up with this one if we
3694 * have operands that look like
3695 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3696 * obtain the absolute address of the GOT, and it is strongly
3697 * preferable from a performance point of view to avoid using
3698 * a runtime relocation for this. The actual sequence of
3699 * instructions often look something like:
3704 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3706 * The call and pop essentially return the absolute address
3707 * of the label .L66 and store it in %ebx. The linker itself
3708 * will ultimately change the first operand of the addl so
3709 * that %ebx points to the GOT, but to keep things simple, the
3710 * .o file must have this operand set so that it generates not
3711 * the absolute address of .L66, but the absolute address of
3712 * itself. This allows the linker itself simply treat a GOTPC
3713 * relocation as asking for a pcrel offset to the GOT to be
3714 * added in, and the addend of the relocation is stored in the
3715 * operand field for the instruction itself.
3717 * Our job here is to fix the operand so that it would add
3718 * the correct offset so that %ebx would point to itself. The
3719 * thing that is tricky is that .-.L66 will point to the
3720 * beginning of the instruction, so we need to further modify
3721 * the operand so that it will point to itself. There are
3722 * other cases where you have something like:
3724 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3726 * and here no correction would be required. Internally in
3727 * the assembler we treat operands of this form as not being
3728 * pcrel since the '.' is explicitly mentioned, and I wonder
3729 * whether it would simplify matters to do it this way. Who
3730 * knows. In earlier versions of the PIC patches, the
3731 * pcrel_adjust field was used to store the correction, but
3732 * since the expression is not pcrel, I felt it would be
3733 * confusing to do it this way. */
3735 if ((reloc_type == BFD_RELOC_32
3736 || reloc_type == BFD_RELOC_X86_64_32S)
3738 && GOT_symbol == i.op[n].imms->X_add_symbol
3739 && (i.op[n].imms->X_op == O_symbol
3740 || (i.op[n].imms->X_op == O_add
3741 && ((symbol_get_value_expression
3742 (i.op[n].imms->X_op_symbol)->X_op)
3747 if (insn_start_frag == frag_now)
3748 add = (p - frag_now->fr_literal) - insn_start_off;
3753 add = insn_start_frag->fr_fix - insn_start_off;
3754 for (fr = insn_start_frag->fr_next;
3755 fr && fr != frag_now; fr = fr->fr_next)
3757 add += p - frag_now->fr_literal;
3761 reloc_type = BFD_RELOC_386_GOTPC;
3763 reloc_type = BFD_RELOC_X86_64_GOTPC32;
3764 i.op[n].imms->X_add_number += add;
3766 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3767 i.op[n].imms, 0, reloc_type);
3773 /* x86_cons_fix_new is called via the expression parsing code when a
3774 reloc is needed. We use this hook to get the correct .got reloc. */
3775 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3776 static int cons_sign = -1;
3779 x86_cons_fix_new (fragS *frag,
3784 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3786 got_reloc = NO_RELOC;
3789 if (exp->X_op == O_secrel)
3791 exp->X_op = O_symbol;
3792 r = BFD_RELOC_32_SECREL;
3796 fix_new_exp (frag, off, len, exp, 0, r);
3799 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3800 # define lex_got(reloc, adjust, types) NULL
3802 /* Parse operands of the form
3803 <symbol>@GOTOFF+<nnn>
3804 and similar .plt or .got references.
3806 If we find one, set up the correct relocation in RELOC and copy the
3807 input string, minus the `@GOTOFF' into a malloc'd buffer for
3808 parsing by the calling routine. Return this buffer, and if ADJUST
3809 is non-null set it to the length of the string we removed from the
3810 input line. Otherwise return NULL. */
3812 lex_got (enum bfd_reloc_code_real *reloc,
3814 unsigned int *types)
3816 static const struct {
3818 const enum bfd_reloc_code_real rel[2];
3819 const unsigned int types64;
3821 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3822 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3823 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3824 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3825 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3826 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3827 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3828 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3829 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3830 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3831 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3832 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
3833 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
3841 for (cp = input_line_pointer; *cp != '@'; cp++)
3842 if (is_end_of_line[(unsigned char) *cp])
3845 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3849 len = strlen (gotrel[j].str);
3850 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3852 if (gotrel[j].rel[object_64bit] != 0)
3855 char *tmpbuf, *past_reloc;
3857 *reloc = gotrel[j].rel[object_64bit];
3863 if (flag_code != CODE_64BIT)
3864 *types = Imm32|Disp32;
3866 *types = gotrel[j].types64;
3869 if (GOT_symbol == NULL)
3870 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3872 /* Replace the relocation token with ' ', so that
3873 errors like foo@GOTOFF1 will be detected. */
3875 /* The length of the first part of our input line. */
3876 first = cp - input_line_pointer;
3878 /* The second part goes from after the reloc token until
3879 (and including) an end_of_line char. Don't use strlen
3880 here as the end_of_line char may not be a NUL. */
3881 past_reloc = cp + 1 + len;
3882 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3884 second = cp - past_reloc;
3886 /* Allocate and copy string. The trailing NUL shouldn't
3887 be necessary, but be safe. */
3888 tmpbuf = xmalloc (first + second + 2);
3889 memcpy (tmpbuf, input_line_pointer, first);
3890 tmpbuf[first] = ' ';
3891 memcpy (tmpbuf + first + 1, past_reloc, second);
3892 tmpbuf[first + second + 1] = '\0';
3896 as_bad (_("@%s reloc is not supported with %d-bit output format"),
3897 gotrel[j].str, 1 << (5 + object_64bit));
3902 /* Might be a symbol version string. Don't as_bad here. */
3907 x86_cons (exp, size)
3911 if (size == 4 || (object_64bit && size == 8))
3913 /* Handle @GOTOFF and the like in an expression. */
3915 char *gotfree_input_line;
3918 save = input_line_pointer;
3919 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
3920 if (gotfree_input_line)
3921 input_line_pointer = gotfree_input_line;
3925 if (gotfree_input_line)
3927 /* expression () has merrily parsed up to the end of line,
3928 or a comma - in the wrong buffer. Transfer how far
3929 input_line_pointer has moved to the right buffer. */
3930 input_line_pointer = (save
3931 + (input_line_pointer - gotfree_input_line)
3933 free (gotfree_input_line);
3941 static void signed_cons (int size)
3943 if (flag_code == CODE_64BIT)
3951 pe_directive_secrel (dummy)
3952 int dummy ATTRIBUTE_UNUSED;
3959 if (exp.X_op == O_symbol)
3960 exp.X_op = O_secrel;
3962 emit_expr (&exp, 4);
3964 while (*input_line_pointer++ == ',');
3966 input_line_pointer--;
3967 demand_empty_rest_of_line ();
3971 static int i386_immediate PARAMS ((char *));
3974 i386_immediate (imm_start)
3977 char *save_input_line_pointer;
3978 char *gotfree_input_line;
3981 unsigned int types = ~0U;
3983 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3985 as_bad (_("only 1 or 2 immediate operands are allowed"));
3989 exp = &im_expressions[i.imm_operands++];
3990 i.op[this_operand].imms = exp;
3992 if (is_space_char (*imm_start))
3995 save_input_line_pointer = input_line_pointer;
3996 input_line_pointer = imm_start;
3998 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
3999 if (gotfree_input_line)
4000 input_line_pointer = gotfree_input_line;
4002 exp_seg = expression (exp);
4005 if (*input_line_pointer)
4006 as_bad (_("junk `%s' after expression"), input_line_pointer);
4008 input_line_pointer = save_input_line_pointer;
4009 if (gotfree_input_line)
4010 free (gotfree_input_line);
4012 if (exp->X_op == O_absent || exp->X_op == O_big)
4014 /* Missing or bad expr becomes absolute 0. */
4015 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
4017 exp->X_op = O_constant;
4018 exp->X_add_number = 0;
4019 exp->X_add_symbol = (symbolS *) 0;
4020 exp->X_op_symbol = (symbolS *) 0;
4022 else if (exp->X_op == O_constant)
4024 /* Size it properly later. */
4025 i.types[this_operand] |= Imm64;
4026 /* If BFD64, sign extend val. */
4027 if (!use_rela_relocations)
4028 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4029 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
4031 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4032 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
4033 && exp_seg != absolute_section
4034 && exp_seg != text_section
4035 && exp_seg != data_section
4036 && exp_seg != bss_section
4037 && exp_seg != undefined_section
4038 && !bfd_is_com_section (exp_seg))
4040 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4046 /* This is an address. The size of the address will be
4047 determined later, depending on destination register,
4048 suffix, or the default for the section. */
4049 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
4050 i.types[this_operand] &= types;
4056 static char *i386_scale PARAMS ((char *));
4063 char *save = input_line_pointer;
4065 input_line_pointer = scale;
4066 val = get_absolute_expression ();
4071 i.log2_scale_factor = 0;
4074 i.log2_scale_factor = 1;
4077 i.log2_scale_factor = 2;
4080 i.log2_scale_factor = 3;
4084 char sep = *input_line_pointer;
4086 *input_line_pointer = '\0';
4087 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4089 *input_line_pointer = sep;
4090 input_line_pointer = save;
4094 if (i.log2_scale_factor != 0 && i.index_reg == 0)
4096 as_warn (_("scale factor of %d without an index register"),
4097 1 << i.log2_scale_factor);
4098 #if SCALE1_WHEN_NO_INDEX
4099 i.log2_scale_factor = 0;
4102 scale = input_line_pointer;
4103 input_line_pointer = save;
4107 static int i386_displacement PARAMS ((char *, char *));
4110 i386_displacement (disp_start, disp_end)
4116 char *save_input_line_pointer;
4117 char *gotfree_input_line;
4118 int bigdisp, override;
4119 unsigned int types = Disp;
4121 if ((i.types[this_operand] & JumpAbsolute)
4122 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4125 override = (i.prefix[ADDR_PREFIX] != 0);
4129 /* For PC-relative branches, the width of the displacement
4130 is dependent upon data size, not address size. */
4132 override = (i.prefix[DATA_PREFIX] != 0);
4134 if (flag_code == CODE_64BIT)
4137 bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX)
4141 bigdisp = Disp64 | Disp32S | Disp32;
4148 override = (i.suffix == (flag_code != CODE_16BIT
4150 : LONG_MNEM_SUFFIX));
4153 if ((flag_code == CODE_16BIT) ^ override)
4156 i.types[this_operand] |= bigdisp;
4158 exp = &disp_expressions[i.disp_operands];
4159 i.op[this_operand].disps = exp;
4161 save_input_line_pointer = input_line_pointer;
4162 input_line_pointer = disp_start;
4163 END_STRING_AND_SAVE (disp_end);
4165 #ifndef GCC_ASM_O_HACK
4166 #define GCC_ASM_O_HACK 0
4169 END_STRING_AND_SAVE (disp_end + 1);
4170 if ((i.types[this_operand] & BaseIndex) != 0
4171 && displacement_string_end[-1] == '+')
4173 /* This hack is to avoid a warning when using the "o"
4174 constraint within gcc asm statements.
4177 #define _set_tssldt_desc(n,addr,limit,type) \
4178 __asm__ __volatile__ ( \
4180 "movw %w1,2+%0\n\t" \
4182 "movb %b1,4+%0\n\t" \
4183 "movb %4,5+%0\n\t" \
4184 "movb $0,6+%0\n\t" \
4185 "movb %h1,7+%0\n\t" \
4187 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4189 This works great except that the output assembler ends
4190 up looking a bit weird if it turns out that there is
4191 no offset. You end up producing code that looks like:
4204 So here we provide the missing zero. */
4206 *displacement_string_end = '0';
4209 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
4210 if (gotfree_input_line)
4211 input_line_pointer = gotfree_input_line;
4213 exp_seg = expression (exp);
4216 if (*input_line_pointer)
4217 as_bad (_("junk `%s' after expression"), input_line_pointer);
4219 RESTORE_END_STRING (disp_end + 1);
4221 RESTORE_END_STRING (disp_end);
4222 input_line_pointer = save_input_line_pointer;
4223 if (gotfree_input_line)
4224 free (gotfree_input_line);
4226 /* We do this to make sure that the section symbol is in
4227 the symbol table. We will ultimately change the relocation
4228 to be relative to the beginning of the section. */
4229 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4230 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4231 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4233 if (exp->X_op != O_symbol)
4235 as_bad (_("bad expression used with @%s"),
4236 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4242 if (S_IS_LOCAL (exp->X_add_symbol)
4243 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4244 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
4245 exp->X_op = O_subtract;
4246 exp->X_op_symbol = GOT_symbol;
4247 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
4248 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
4249 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4250 i.reloc[this_operand] = BFD_RELOC_64;
4252 i.reloc[this_operand] = BFD_RELOC_32;
4255 if (exp->X_op == O_absent || exp->X_op == O_big)
4257 /* Missing or bad expr becomes absolute 0. */
4258 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
4260 exp->X_op = O_constant;
4261 exp->X_add_number = 0;
4262 exp->X_add_symbol = (symbolS *) 0;
4263 exp->X_op_symbol = (symbolS *) 0;
4266 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4267 if (exp->X_op != O_constant
4268 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4269 && exp_seg != absolute_section
4270 && exp_seg != text_section
4271 && exp_seg != data_section
4272 && exp_seg != bss_section
4273 && exp_seg != undefined_section
4274 && !bfd_is_com_section (exp_seg))
4276 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4281 if (!(i.types[this_operand] & ~Disp))
4282 i.types[this_operand] &= types;
4287 static int i386_index_check PARAMS ((const char *));
4289 /* Make sure the memory operand we've been dealt is valid.
4290 Return 1 on success, 0 on a failure. */
4293 i386_index_check (operand_string)
4294 const char *operand_string;
4297 #if INFER_ADDR_PREFIX
4303 if ((current_templates->start->cpu_flags & CpuSVME)
4304 && current_templates->end[-1].operand_types[0] == AnyMem)
4306 /* Memory operands of SVME insns are special in that they only allow
4307 rAX as their memory address and ignore any segment override. */
4310 /* SKINIT is even more restrictive: it always requires EAX. */
4311 if (strcmp (current_templates->start->name, "skinit") == 0)
4313 else if (flag_code == CODE_64BIT)
4314 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4316 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4320 || !(i.base_reg->reg_type & Acc)
4321 || !(i.base_reg->reg_type & RegXX)
4323 || (i.types[0] & Disp))
4326 else if (flag_code == CODE_64BIT)
4328 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4331 && ((i.base_reg->reg_type & RegXX) == 0)
4332 && (i.base_reg->reg_type != BaseIndex
4335 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4336 != (RegXX | BaseIndex))))
4341 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4345 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4346 != (Reg16 | BaseIndex)))
4348 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4349 != (Reg16 | BaseIndex))
4351 && i.base_reg->reg_num < 6
4352 && i.index_reg->reg_num >= 6
4353 && i.log2_scale_factor == 0))))
4360 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4362 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4363 != (Reg32 | BaseIndex))))
4369 #if INFER_ADDR_PREFIX
4370 if (i.prefix[ADDR_PREFIX] == 0)
4372 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4374 /* Change the size of any displacement too. At most one of
4375 Disp16 or Disp32 is set.
4376 FIXME. There doesn't seem to be any real need for separate
4377 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4378 Removing them would probably clean up the code quite a lot. */
4379 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
4380 i.types[this_operand] ^= (Disp16 | Disp32);
4385 as_bad (_("`%s' is not a valid base/index expression"),
4389 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4391 flag_code_names[flag_code]);
4396 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4400 i386_operand (operand_string)
4401 char *operand_string;
4405 char *op_string = operand_string;
4407 if (is_space_char (*op_string))
4410 /* We check for an absolute prefix (differentiating,
4411 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4412 if (*op_string == ABSOLUTE_PREFIX)
4415 if (is_space_char (*op_string))
4417 i.types[this_operand] |= JumpAbsolute;
4420 /* Check if operand is a register. */
4421 if ((r = parse_register (op_string, &end_op)) != NULL)
4423 /* Check for a segment override by searching for ':' after a
4424 segment register. */
4426 if (is_space_char (*op_string))
4428 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4433 i.seg[i.mem_operands] = &es;
4436 i.seg[i.mem_operands] = &cs;
4439 i.seg[i.mem_operands] = &ss;
4442 i.seg[i.mem_operands] = &ds;
4445 i.seg[i.mem_operands] = &fs;
4448 i.seg[i.mem_operands] = &gs;
4452 /* Skip the ':' and whitespace. */
4454 if (is_space_char (*op_string))
4457 if (!is_digit_char (*op_string)
4458 && !is_identifier_char (*op_string)
4459 && *op_string != '('
4460 && *op_string != ABSOLUTE_PREFIX)
4462 as_bad (_("bad memory operand `%s'"), op_string);
4465 /* Handle case of %es:*foo. */
4466 if (*op_string == ABSOLUTE_PREFIX)
4469 if (is_space_char (*op_string))
4471 i.types[this_operand] |= JumpAbsolute;
4473 goto do_memory_reference;
4477 as_bad (_("junk `%s' after register"), op_string);
4480 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4481 i.op[this_operand].regs = r;
4484 else if (*op_string == REGISTER_PREFIX)
4486 as_bad (_("bad register name `%s'"), op_string);
4489 else if (*op_string == IMMEDIATE_PREFIX)
4492 if (i.types[this_operand] & JumpAbsolute)
4494 as_bad (_("immediate operand illegal with absolute jump"));
4497 if (!i386_immediate (op_string))
4500 else if (is_digit_char (*op_string)
4501 || is_identifier_char (*op_string)
4502 || *op_string == '(')
4504 /* This is a memory reference of some sort. */
4507 /* Start and end of displacement string expression (if found). */
4508 char *displacement_string_start;
4509 char *displacement_string_end;
4511 do_memory_reference:
4512 if ((i.mem_operands == 1
4513 && (current_templates->start->opcode_modifier & IsString) == 0)
4514 || i.mem_operands == 2)
4516 as_bad (_("too many memory references for `%s'"),
4517 current_templates->start->name);
4521 /* Check for base index form. We detect the base index form by
4522 looking for an ')' at the end of the operand, searching
4523 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4525 base_string = op_string + strlen (op_string);
4528 if (is_space_char (*base_string))
4531 /* If we only have a displacement, set-up for it to be parsed later. */
4532 displacement_string_start = op_string;
4533 displacement_string_end = base_string + 1;
4535 if (*base_string == ')')
4538 unsigned int parens_balanced = 1;
4539 /* We've already checked that the number of left & right ()'s are
4540 equal, so this loop will not be infinite. */
4544 if (*base_string == ')')
4546 if (*base_string == '(')
4549 while (parens_balanced);
4551 temp_string = base_string;
4553 /* Skip past '(' and whitespace. */
4555 if (is_space_char (*base_string))
4558 if (*base_string == ','
4559 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
4561 displacement_string_end = temp_string;
4563 i.types[this_operand] |= BaseIndex;
4567 base_string = end_op;
4568 if (is_space_char (*base_string))
4572 /* There may be an index reg or scale factor here. */
4573 if (*base_string == ',')
4576 if (is_space_char (*base_string))
4579 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
4581 base_string = end_op;
4582 if (is_space_char (*base_string))
4584 if (*base_string == ',')
4587 if (is_space_char (*base_string))
4590 else if (*base_string != ')')
4592 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4597 else if (*base_string == REGISTER_PREFIX)
4599 as_bad (_("bad register name `%s'"), base_string);
4603 /* Check for scale factor. */
4604 if (*base_string != ')')
4606 char *end_scale = i386_scale (base_string);
4611 base_string = end_scale;
4612 if (is_space_char (*base_string))
4614 if (*base_string != ')')
4616 as_bad (_("expecting `)' after scale factor in `%s'"),
4621 else if (!i.index_reg)
4623 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4628 else if (*base_string != ')')
4630 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4635 else if (*base_string == REGISTER_PREFIX)
4637 as_bad (_("bad register name `%s'"), base_string);
4642 /* If there's an expression beginning the operand, parse it,
4643 assuming displacement_string_start and
4644 displacement_string_end are meaningful. */
4645 if (displacement_string_start != displacement_string_end)
4647 if (!i386_displacement (displacement_string_start,
4648 displacement_string_end))
4652 /* Special case for (%dx) while doing input/output op. */
4654 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4656 && i.log2_scale_factor == 0
4657 && i.seg[i.mem_operands] == 0
4658 && (i.types[this_operand] & Disp) == 0)
4660 i.types[this_operand] = InOutPortReg;
4664 if (i386_index_check (operand_string) == 0)
4670 /* It's not a memory operand; argh! */
4671 as_bad (_("invalid char %s beginning operand %d `%s'"),
4672 output_invalid (*op_string),
4677 return 1; /* Normal return. */
4680 /* md_estimate_size_before_relax()
4682 Called just before relax() for rs_machine_dependent frags. The x86
4683 assembler uses these frags to handle variable size jump
4686 Any symbol that is now undefined will not become defined.
4687 Return the correct fr_subtype in the frag.
4688 Return the initial "guess for variable size of frag" to caller.
4689 The guess is actually the growth beyond the fixed part. Whatever
4690 we do to grow the fixed or variable part contributes to our
4694 md_estimate_size_before_relax (fragP, segment)
4698 /* We've already got fragP->fr_subtype right; all we have to do is
4699 check for un-relaxable symbols. On an ELF system, we can't relax
4700 an externally visible symbol, because it may be overridden by a
4702 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4703 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4705 && (S_IS_EXTERNAL (fragP->fr_symbol)
4706 || S_IS_WEAK (fragP->fr_symbol)))
4710 /* Symbol is undefined in this segment, or we need to keep a
4711 reloc so that weak symbols can be overridden. */
4712 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4713 enum bfd_reloc_code_real reloc_type;
4714 unsigned char *opcode;
4717 if (fragP->fr_var != NO_RELOC)
4718 reloc_type = fragP->fr_var;
4720 reloc_type = BFD_RELOC_16_PCREL;
4722 reloc_type = BFD_RELOC_32_PCREL;
4724 old_fr_fix = fragP->fr_fix;
4725 opcode = (unsigned char *) fragP->fr_opcode;
4727 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4730 /* Make jmp (0xeb) a (d)word displacement jump. */
4732 fragP->fr_fix += size;
4733 fix_new (fragP, old_fr_fix, size,
4735 fragP->fr_offset, 1,
4741 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4743 /* Negate the condition, and branch past an
4744 unconditional jump. */
4747 /* Insert an unconditional jump. */
4749 /* We added two extra opcode bytes, and have a two byte
4751 fragP->fr_fix += 2 + 2;
4752 fix_new (fragP, old_fr_fix + 2, 2,
4754 fragP->fr_offset, 1,
4761 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4766 fixP = fix_new (fragP, old_fr_fix, 1,
4768 fragP->fr_offset, 1,
4770 fixP->fx_signed = 1;
4774 /* This changes the byte-displacement jump 0x7N
4775 to the (d)word-displacement jump 0x0f,0x8N. */
4776 opcode[1] = opcode[0] + 0x10;
4777 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4778 /* We've added an opcode byte. */
4779 fragP->fr_fix += 1 + size;
4780 fix_new (fragP, old_fr_fix + 1, size,
4782 fragP->fr_offset, 1,
4787 BAD_CASE (fragP->fr_subtype);
4791 return fragP->fr_fix - old_fr_fix;
4794 /* Guess size depending on current relax state. Initially the relax
4795 state will correspond to a short jump and we return 1, because
4796 the variable part of the frag (the branch offset) is one byte
4797 long. However, we can relax a section more than once and in that
4798 case we must either set fr_subtype back to the unrelaxed state,
4799 or return the value for the appropriate branch. */
4800 return md_relax_table[fragP->fr_subtype].rlx_length;
4803 /* Called after relax() is finished.
4805 In: Address of frag.
4806 fr_type == rs_machine_dependent.
4807 fr_subtype is what the address relaxed to.
4809 Out: Any fixSs and constants are set up.
4810 Caller will turn frag into a ".space 0". */
4813 md_convert_frag (abfd, sec, fragP)
4814 bfd *abfd ATTRIBUTE_UNUSED;
4815 segT sec ATTRIBUTE_UNUSED;
4818 unsigned char *opcode;
4819 unsigned char *where_to_put_displacement = NULL;
4820 offsetT target_address;
4821 offsetT opcode_address;
4822 unsigned int extension = 0;
4823 offsetT displacement_from_opcode_start;
4825 opcode = (unsigned char *) fragP->fr_opcode;
4827 /* Address we want to reach in file space. */
4828 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4830 /* Address opcode resides at in file space. */
4831 opcode_address = fragP->fr_address + fragP->fr_fix;
4833 /* Displacement from opcode start to fill into instruction. */
4834 displacement_from_opcode_start = target_address - opcode_address;
4836 if ((fragP->fr_subtype & BIG) == 0)
4838 /* Don't have to change opcode. */
4839 extension = 1; /* 1 opcode + 1 displacement */
4840 where_to_put_displacement = &opcode[1];
4844 if (no_cond_jump_promotion
4845 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4846 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4848 switch (fragP->fr_subtype)
4850 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4851 extension = 4; /* 1 opcode + 4 displacement */
4853 where_to_put_displacement = &opcode[1];
4856 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4857 extension = 2; /* 1 opcode + 2 displacement */
4859 where_to_put_displacement = &opcode[1];
4862 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4863 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4864 extension = 5; /* 2 opcode + 4 displacement */
4865 opcode[1] = opcode[0] + 0x10;
4866 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4867 where_to_put_displacement = &opcode[2];
4870 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4871 extension = 3; /* 2 opcode + 2 displacement */
4872 opcode[1] = opcode[0] + 0x10;
4873 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4874 where_to_put_displacement = &opcode[2];
4877 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4882 where_to_put_displacement = &opcode[3];
4886 BAD_CASE (fragP->fr_subtype);
4891 /* Now put displacement after opcode. */
4892 md_number_to_chars ((char *) where_to_put_displacement,
4893 (valueT) (displacement_from_opcode_start - extension),
4894 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4895 fragP->fr_fix += extension;
4898 /* Size of byte displacement jmp. */
4899 int md_short_jump_size = 2;
4901 /* Size of dword displacement jmp. */
4902 int md_long_jump_size = 5;
4905 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4907 addressT from_addr, to_addr;
4908 fragS *frag ATTRIBUTE_UNUSED;
4909 symbolS *to_symbol ATTRIBUTE_UNUSED;
4913 offset = to_addr - (from_addr + 2);
4914 /* Opcode for byte-disp jump. */
4915 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4916 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4920 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4922 addressT from_addr, to_addr;
4923 fragS *frag ATTRIBUTE_UNUSED;
4924 symbolS *to_symbol ATTRIBUTE_UNUSED;
4928 offset = to_addr - (from_addr + 5);
4929 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4930 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4933 /* Apply a fixup (fixS) to segment data, once it has been determined
4934 by our caller that we have all the info we need to fix it up.
4936 On the 386, immediates, displacements, and data pointers are all in
4937 the same (little-endian) format, so we don't need to care about which
4941 md_apply_fix (fixP, valP, seg)
4942 /* The fix we're to put in. */
4944 /* Pointer to the value of the bits. */
4946 /* Segment fix is from. */
4947 segT seg ATTRIBUTE_UNUSED;
4949 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4950 valueT value = *valP;
4952 #if !defined (TE_Mach)
4955 switch (fixP->fx_r_type)
4961 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4964 case BFD_RELOC_X86_64_32S:
4965 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4968 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4971 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4976 if (fixP->fx_addsy != NULL
4977 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4978 || fixP->fx_r_type == BFD_RELOC_64_PCREL
4979 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4980 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4981 && !use_rela_relocations)
4983 /* This is a hack. There should be a better way to handle this.
4984 This covers for the fact that bfd_install_relocation will
4985 subtract the current location (for partial_inplace, PC relative
4986 relocations); see more below. */
4990 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4993 value += fixP->fx_where + fixP->fx_frag->fr_address;
4995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4998 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
5001 || (symbol_section_p (fixP->fx_addsy)
5002 && sym_seg != absolute_section))
5003 && !generic_force_reloc (fixP))
5005 /* Yes, we add the values in twice. This is because
5006 bfd_install_relocation subtracts them out again. I think
5007 bfd_install_relocation is broken, but I don't dare change
5009 value += fixP->fx_where + fixP->fx_frag->fr_address;
5013 #if defined (OBJ_COFF) && defined (TE_PE)
5014 /* For some reason, the PE format does not store a
5015 section address offset for a PC relative symbol. */
5016 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
5017 || S_IS_WEAK (fixP->fx_addsy))
5018 value += md_pcrel_from (fixP);
5022 /* Fix a few things - the dynamic linker expects certain values here,
5023 and we must not disappoint it. */
5024 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5025 if (IS_ELF && fixP->fx_addsy)
5026 switch (fixP->fx_r_type)
5028 case BFD_RELOC_386_PLT32:
5029 case BFD_RELOC_X86_64_PLT32:
5030 /* Make the jump instruction point to the address of the operand. At
5031 runtime we merely add the offset to the actual PLT entry. */
5035 case BFD_RELOC_386_TLS_GD:
5036 case BFD_RELOC_386_TLS_LDM:
5037 case BFD_RELOC_386_TLS_IE_32:
5038 case BFD_RELOC_386_TLS_IE:
5039 case BFD_RELOC_386_TLS_GOTIE:
5040 case BFD_RELOC_X86_64_TLSGD:
5041 case BFD_RELOC_X86_64_TLSLD:
5042 case BFD_RELOC_X86_64_GOTTPOFF:
5043 value = 0; /* Fully resolved at runtime. No addend. */
5045 case BFD_RELOC_386_TLS_LE:
5046 case BFD_RELOC_386_TLS_LDO_32:
5047 case BFD_RELOC_386_TLS_LE_32:
5048 case BFD_RELOC_X86_64_DTPOFF32:
5049 case BFD_RELOC_X86_64_DTPOFF64:
5050 case BFD_RELOC_X86_64_TPOFF32:
5051 case BFD_RELOC_X86_64_TPOFF64:
5052 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5055 case BFD_RELOC_386_GOT32:
5056 case BFD_RELOC_X86_64_GOT32:
5057 value = 0; /* Fully resolved at runtime. No addend. */
5060 case BFD_RELOC_VTABLE_INHERIT:
5061 case BFD_RELOC_VTABLE_ENTRY:
5068 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
5070 #endif /* !defined (TE_Mach) */
5072 /* Are we finished with this relocation now? */
5073 if (fixP->fx_addsy == NULL)
5075 else if (use_rela_relocations)
5077 fixP->fx_no_overflow = 1;
5078 /* Remember value for tc_gen_reloc. */
5079 fixP->fx_addnumber = value;
5083 md_number_to_chars (p, value, fixP->fx_size);
5086 #define MAX_LITTLENUMS 6
5088 /* Turn the string pointed to by litP into a floating point constant
5089 of type TYPE, and emit the appropriate bytes. The number of
5090 LITTLENUMS emitted is stored in *SIZEP. An error message is
5091 returned, or NULL on OK. */
5094 md_atof (type, litP, sizeP)
5100 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5101 LITTLENUM_TYPE *wordP;
5123 return _("Bad call to md_atof ()");
5125 t = atof_ieee (input_line_pointer, type, words);
5127 input_line_pointer = t;
5129 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5130 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5131 the bigendian 386. */
5132 for (wordP = words + prec - 1; prec--;)
5134 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5135 litP += sizeof (LITTLENUM_TYPE);
5140 static char output_invalid_buf[8];
5147 sprintf (output_invalid_buf, "'%c'", c);
5149 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5150 return output_invalid_buf;
5153 /* REG_STRING starts *before* REGISTER_PREFIX. */
5155 static const reg_entry *
5156 parse_real_register (char *reg_string, char **end_op)
5158 char *s = reg_string;
5160 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5163 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5164 if (*s == REGISTER_PREFIX)
5167 if (is_space_char (*s))
5171 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
5173 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
5174 return (const reg_entry *) NULL;
5178 /* For naked regs, make sure that we are not dealing with an identifier.
5179 This prevents confusing an identifier like `eax_var' with register
5181 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5182 return (const reg_entry *) NULL;
5186 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5188 /* Handle floating point regs, allowing spaces in the (i) part. */
5189 if (r == i386_regtab /* %st is first entry of table */)
5191 if (is_space_char (*s))
5196 if (is_space_char (*s))
5198 if (*s >= '0' && *s <= '7')
5200 r = &i386_float_regtab[*s - '0'];
5202 if (is_space_char (*s))
5210 /* We have "%st(" then garbage. */
5211 return (const reg_entry *) NULL;
5216 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
5217 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
5218 && flag_code != CODE_64BIT)
5219 return (const reg_entry *) NULL;
5224 /* REG_STRING starts *before* REGISTER_PREFIX. */
5226 static const reg_entry *
5227 parse_register (char *reg_string, char **end_op)
5231 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5232 r = parse_real_register (reg_string, end_op);
5237 char *save = input_line_pointer;
5241 input_line_pointer = reg_string;
5242 c = get_symbol_end ();
5243 symbolP = symbol_find (reg_string);
5244 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5246 const expressionS *e = symbol_get_value_expression (symbolP);
5248 know (e->X_op == O_register);
5249 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5250 r = i386_regtab + e->X_add_number;
5251 *end_op = input_line_pointer;
5253 *input_line_pointer = c;
5254 input_line_pointer = save;
5260 i386_parse_name (char *name, expressionS *e, char *nextcharP)
5263 char *end = input_line_pointer;
5266 r = parse_register (name, &input_line_pointer);
5267 if (r && end <= input_line_pointer)
5269 *nextcharP = *input_line_pointer;
5270 *input_line_pointer = 0;
5271 e->X_op = O_register;
5272 e->X_add_number = r - i386_regtab;
5275 input_line_pointer = end;
5281 md_operand (expressionS *e)
5283 if (*input_line_pointer == REGISTER_PREFIX)
5286 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5290 e->X_op = O_register;
5291 e->X_add_number = r - i386_regtab;
5292 input_line_pointer = end;
5298 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5299 const char *md_shortopts = "kVQ:sqn";
5301 const char *md_shortopts = "qn";
5304 #define OPTION_32 (OPTION_MD_BASE + 0)
5305 #define OPTION_64 (OPTION_MD_BASE + 1)
5306 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
5308 struct option md_longopts[] = {
5309 {"32", no_argument, NULL, OPTION_32},
5310 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5311 {"64", no_argument, NULL, OPTION_64},
5313 {"divide", no_argument, NULL, OPTION_DIVIDE},
5314 {NULL, no_argument, NULL, 0}
5316 size_t md_longopts_size = sizeof (md_longopts);
5319 md_parse_option (c, arg)
5321 char *arg ATTRIBUTE_UNUSED;
5326 optimize_align_code = 0;
5333 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5334 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5335 should be emitted or not. FIXME: Not implemented. */
5339 /* -V: SVR4 argument to print version ID. */
5341 print_version_id ();
5344 /* -k: Ignore for FreeBSD compatibility. */
5349 /* -s: On i386 Solaris, this tells the native assembler to use
5350 .stab instead of .stab.excl. We always use .stab anyhow. */
5355 const char **list, **l;
5357 list = bfd_target_list ();
5358 for (l = list; *l != NULL; l++)
5359 if (strcmp (*l, "elf64-x86-64") == 0)
5361 default_arch = "x86_64";
5365 as_fatal (_("No compiled in support for x86_64"));
5372 default_arch = "i386";
5376 #ifdef SVR4_COMMENT_CHARS
5381 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5383 for (s = i386_comment_chars; *s != '\0'; s++)
5387 i386_comment_chars = n;
5399 md_show_usage (stream)
5402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5403 fprintf (stream, _("\
5405 -V print assembler version number\n\
5408 fprintf (stream, _("\
5409 -n Do not optimize code alignment\n\
5410 -q quieten some warnings\n"));
5411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5412 fprintf (stream, _("\
5415 #ifdef SVR4_COMMENT_CHARS
5416 fprintf (stream, _("\
5417 --divide do not treat `/' as a comment character\n"));
5419 fprintf (stream, _("\
5420 --divide ignored\n"));
5424 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5425 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5427 /* Pick the target format to use. */
5430 i386_target_format ()
5432 if (!strcmp (default_arch, "x86_64"))
5433 set_code_flag (CODE_64BIT);
5434 else if (!strcmp (default_arch, "i386"))
5435 set_code_flag (CODE_32BIT);
5437 as_fatal (_("Unknown architecture"));
5438 switch (OUTPUT_FLAVOR)
5440 #ifdef OBJ_MAYBE_AOUT
5441 case bfd_target_aout_flavour:
5442 return AOUT_TARGET_FORMAT;
5444 #ifdef OBJ_MAYBE_COFF
5445 case bfd_target_coff_flavour:
5448 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
5449 case bfd_target_elf_flavour:
5451 if (flag_code == CODE_64BIT)
5454 use_rela_relocations = 1;
5456 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5465 #endif /* OBJ_MAYBE_ more than one */
5467 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5468 void i386_elf_emit_arch_note ()
5470 if (IS_ELF && cpu_arch_name != NULL)
5473 asection *seg = now_seg;
5474 subsegT subseg = now_subseg;
5475 Elf_Internal_Note i_note;
5476 Elf_External_Note e_note;
5477 asection *note_secp;
5480 /* Create the .note section. */
5481 note_secp = subseg_new (".note", 0);
5482 bfd_set_section_flags (stdoutput,
5484 SEC_HAS_CONTENTS | SEC_READONLY);
5486 /* Process the arch string. */
5487 len = strlen (cpu_arch_name);
5489 i_note.namesz = len + 1;
5491 i_note.type = NT_ARCH;
5492 p = frag_more (sizeof (e_note.namesz));
5493 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5494 p = frag_more (sizeof (e_note.descsz));
5495 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5496 p = frag_more (sizeof (e_note.type));
5497 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5498 p = frag_more (len + 1);
5499 strcpy (p, cpu_arch_name);
5501 frag_align (2, 0, 0);
5503 subseg_set (seg, subseg);
5509 md_undefined_symbol (name)
5512 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5513 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5514 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5515 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5519 if (symbol_find (name))
5520 as_bad (_("GOT already in symbol table"));
5521 GOT_symbol = symbol_new (name, undefined_section,
5522 (valueT) 0, &zero_address_frag);
5529 /* Round up a section size to the appropriate boundary. */
5532 md_section_align (segment, size)
5533 segT segment ATTRIBUTE_UNUSED;
5536 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5537 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5539 /* For a.out, force the section size to be aligned. If we don't do
5540 this, BFD will align it for us, but it will not write out the
5541 final bytes of the section. This may be a bug in BFD, but it is
5542 easier to fix it here since that is how the other a.out targets
5546 align = bfd_get_section_alignment (stdoutput, segment);
5547 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5554 /* On the i386, PC-relative offsets are relative to the start of the
5555 next instruction. That is, the address of the offset, plus its
5556 size, since the offset is always the last part of the insn. */
5559 md_pcrel_from (fixP)
5562 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5569 int ignore ATTRIBUTE_UNUSED;
5573 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5575 obj_elf_section_change_hook ();
5577 temp = get_absolute_expression ();
5578 subseg_set (bss_section, (subsegT) temp);
5579 demand_empty_rest_of_line ();
5585 i386_validate_fix (fixp)
5588 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5590 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5594 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5599 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5601 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
5608 tc_gen_reloc (section, fixp)
5609 asection *section ATTRIBUTE_UNUSED;
5613 bfd_reloc_code_real_type code;
5615 switch (fixp->fx_r_type)
5617 case BFD_RELOC_X86_64_PLT32:
5618 case BFD_RELOC_X86_64_GOT32:
5619 case BFD_RELOC_X86_64_GOTPCREL:
5620 case BFD_RELOC_386_PLT32:
5621 case BFD_RELOC_386_GOT32:
5622 case BFD_RELOC_386_GOTOFF:
5623 case BFD_RELOC_386_GOTPC:
5624 case BFD_RELOC_386_TLS_GD:
5625 case BFD_RELOC_386_TLS_LDM:
5626 case BFD_RELOC_386_TLS_LDO_32:
5627 case BFD_RELOC_386_TLS_IE_32:
5628 case BFD_RELOC_386_TLS_IE:
5629 case BFD_RELOC_386_TLS_GOTIE:
5630 case BFD_RELOC_386_TLS_LE_32:
5631 case BFD_RELOC_386_TLS_LE:
5632 case BFD_RELOC_X86_64_TLSGD:
5633 case BFD_RELOC_X86_64_TLSLD:
5634 case BFD_RELOC_X86_64_DTPOFF32:
5635 case BFD_RELOC_X86_64_DTPOFF64:
5636 case BFD_RELOC_X86_64_GOTTPOFF:
5637 case BFD_RELOC_X86_64_TPOFF32:
5638 case BFD_RELOC_X86_64_TPOFF64:
5639 case BFD_RELOC_X86_64_GOTOFF64:
5640 case BFD_RELOC_X86_64_GOTPC32:
5642 case BFD_RELOC_VTABLE_ENTRY:
5643 case BFD_RELOC_VTABLE_INHERIT:
5645 case BFD_RELOC_32_SECREL:
5647 code = fixp->fx_r_type;
5649 case BFD_RELOC_X86_64_32S:
5650 if (!fixp->fx_pcrel)
5652 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5653 code = fixp->fx_r_type;
5659 switch (fixp->fx_size)
5662 as_bad_where (fixp->fx_file, fixp->fx_line,
5663 _("can not do %d byte pc-relative relocation"),
5665 code = BFD_RELOC_32_PCREL;
5667 case 1: code = BFD_RELOC_8_PCREL; break;
5668 case 2: code = BFD_RELOC_16_PCREL; break;
5669 case 4: code = BFD_RELOC_32_PCREL; break;
5671 case 8: code = BFD_RELOC_64_PCREL; break;
5677 switch (fixp->fx_size)
5680 as_bad_where (fixp->fx_file, fixp->fx_line,
5681 _("can not do %d byte relocation"),
5683 code = BFD_RELOC_32;
5685 case 1: code = BFD_RELOC_8; break;
5686 case 2: code = BFD_RELOC_16; break;
5687 case 4: code = BFD_RELOC_32; break;
5689 case 8: code = BFD_RELOC_64; break;
5696 if ((code == BFD_RELOC_32
5697 || code == BFD_RELOC_32_PCREL
5698 || code == BFD_RELOC_X86_64_32S)
5700 && fixp->fx_addsy == GOT_symbol)
5703 code = BFD_RELOC_386_GOTPC;
5705 code = BFD_RELOC_X86_64_GOTPC32;
5708 rel = (arelent *) xmalloc (sizeof (arelent));
5709 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5710 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5712 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5714 if (!use_rela_relocations)
5716 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5717 vtable entry to be used in the relocation's section offset. */
5718 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5719 rel->address = fixp->fx_offset;
5723 /* Use the rela in 64bit mode. */
5726 if (!fixp->fx_pcrel)
5727 rel->addend = fixp->fx_offset;
5731 case BFD_RELOC_X86_64_PLT32:
5732 case BFD_RELOC_X86_64_GOT32:
5733 case BFD_RELOC_X86_64_GOTPCREL:
5734 case BFD_RELOC_X86_64_TLSGD:
5735 case BFD_RELOC_X86_64_TLSLD:
5736 case BFD_RELOC_X86_64_GOTTPOFF:
5737 rel->addend = fixp->fx_offset - fixp->fx_size;
5740 rel->addend = (section->vma
5742 + fixp->fx_addnumber
5743 + md_pcrel_from (fixp));
5748 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5749 if (rel->howto == NULL)
5751 as_bad_where (fixp->fx_file, fixp->fx_line,
5752 _("cannot represent relocation type %s"),
5753 bfd_get_reloc_code_name (code));
5754 /* Set howto to a garbage value so that we can keep going. */
5755 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5756 assert (rel->howto != NULL);
5763 /* Parse operands using Intel syntax. This implements a recursive descent
5764 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5767 FIXME: We do not recognize the full operand grammar defined in the MASM
5768 documentation. In particular, all the structure/union and
5769 high-level macro operands are missing.
5771 Uppercase words are terminals, lower case words are non-terminals.
5772 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5773 bars '|' denote choices. Most grammar productions are implemented in
5774 functions called 'intel_<production>'.
5776 Initial production is 'expr'.
5782 binOp & | AND | \| | OR | ^ | XOR
5784 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5786 constant digits [[ radixOverride ]]
5788 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
5826 => expr expr cmpOp e04
5829 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5830 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5832 hexdigit a | b | c | d | e | f
5833 | A | B | C | D | E | F
5839 mulOp * | / | % | MOD | << | SHL | >> | SHR
5843 register specialRegister
5847 segmentRegister CS | DS | ES | FS | GS | SS
5849 specialRegister CR0 | CR2 | CR3 | CR4
5850 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5851 | TR3 | TR4 | TR5 | TR6 | TR7
5853 We simplify the grammar in obvious places (e.g., register parsing is
5854 done by calling parse_register) and eliminate immediate left recursion
5855 to implement a recursive-descent parser.
5859 expr' cmpOp e04 expr'
5910 /* Parsing structure for the intel syntax parser. Used to implement the
5911 semantic actions for the operand grammar. */
5912 struct intel_parser_s
5914 char *op_string; /* The string being parsed. */
5915 int got_a_float; /* Whether the operand is a float. */
5916 int op_modifier; /* Operand modifier. */
5917 int is_mem; /* 1 if operand is memory reference. */
5918 int in_offset; /* >=1 if parsing operand of offset. */
5919 int in_bracket; /* >=1 if parsing operand in brackets. */
5920 const reg_entry *reg; /* Last register reference found. */
5921 char *disp; /* Displacement string being built. */
5922 char *next_operand; /* Resume point when splitting operands. */
5925 static struct intel_parser_s intel_parser;
5927 /* Token structure for parsing intel syntax. */
5930 int code; /* Token code. */
5931 const reg_entry *reg; /* Register entry for register tokens. */
5932 char *str; /* String representation. */
5935 static struct intel_token cur_token, prev_token;
5937 /* Token codes for the intel parser. Since T_SHORT is already used
5938 by COFF, undefine it first to prevent a warning. */
5957 /* Prototypes for intel parser functions. */
5958 static int intel_match_token PARAMS ((int code));
5959 static void intel_get_token PARAMS ((void));
5960 static void intel_putback_token PARAMS ((void));
5961 static int intel_expr PARAMS ((void));
5962 static int intel_e04 PARAMS ((void));
5963 static int intel_e05 PARAMS ((void));
5964 static int intel_e06 PARAMS ((void));
5965 static int intel_e09 PARAMS ((void));
5966 static int intel_bracket_expr PARAMS ((void));
5967 static int intel_e10 PARAMS ((void));
5968 static int intel_e11 PARAMS ((void));
5971 i386_intel_operand (operand_string, got_a_float)
5972 char *operand_string;
5978 p = intel_parser.op_string = xstrdup (operand_string);
5979 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5983 /* Initialize token holders. */
5984 cur_token.code = prev_token.code = T_NIL;
5985 cur_token.reg = prev_token.reg = NULL;
5986 cur_token.str = prev_token.str = NULL;
5988 /* Initialize parser structure. */
5989 intel_parser.got_a_float = got_a_float;
5990 intel_parser.op_modifier = 0;
5991 intel_parser.is_mem = 0;
5992 intel_parser.in_offset = 0;
5993 intel_parser.in_bracket = 0;
5994 intel_parser.reg = NULL;
5995 intel_parser.disp[0] = '\0';
5996 intel_parser.next_operand = NULL;
5998 /* Read the first token and start the parser. */
6000 ret = intel_expr ();
6005 if (cur_token.code != T_NIL)
6007 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6008 current_templates->start->name, cur_token.str);
6011 /* If we found a memory reference, hand it over to i386_displacement
6012 to fill in the rest of the operand fields. */
6013 else if (intel_parser.is_mem)
6015 if ((i.mem_operands == 1
6016 && (current_templates->start->opcode_modifier & IsString) == 0)
6017 || i.mem_operands == 2)
6019 as_bad (_("too many memory references for '%s'"),
6020 current_templates->start->name);
6025 char *s = intel_parser.disp;
6028 if (!quiet_warnings && intel_parser.is_mem < 0)
6029 /* See the comments in intel_bracket_expr. */
6030 as_warn (_("Treating `%s' as memory reference"), operand_string);
6032 /* Add the displacement expression. */
6034 ret = i386_displacement (s, s + strlen (s));
6037 /* Swap base and index in 16-bit memory operands like
6038 [si+bx]. Since i386_index_check is also used in AT&T
6039 mode we have to do that here. */
6042 && (i.base_reg->reg_type & Reg16)
6043 && (i.index_reg->reg_type & Reg16)
6044 && i.base_reg->reg_num >= 6
6045 && i.index_reg->reg_num < 6)
6047 const reg_entry *base = i.index_reg;
6049 i.index_reg = i.base_reg;
6052 ret = i386_index_check (operand_string);
6057 /* Constant and OFFSET expressions are handled by i386_immediate. */
6058 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
6059 || intel_parser.reg == NULL)
6060 ret = i386_immediate (intel_parser.disp);
6062 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6064 if (!ret || !intel_parser.next_operand)
6066 intel_parser.op_string = intel_parser.next_operand;
6067 this_operand = i.operands++;
6071 free (intel_parser.disp);
6076 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6080 expr' cmpOp e04 expr'
6085 /* XXX Implement the comparison operators. */
6086 return intel_e04 ();
6103 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6104 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
6106 if (cur_token.code == '+')
6108 else if (cur_token.code == '-')
6109 nregs = NUM_ADDRESS_REGS;
6113 strcat (intel_parser.disp, cur_token.str);
6114 intel_match_token (cur_token.code);
6125 int nregs = ~NUM_ADDRESS_REGS;
6132 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6136 str[0] = cur_token.code;
6138 strcat (intel_parser.disp, str);
6143 intel_match_token (cur_token.code);
6148 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6149 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6160 int nregs = ~NUM_ADDRESS_REGS;
6167 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6171 str[0] = cur_token.code;
6173 strcat (intel_parser.disp, str);
6175 else if (cur_token.code == T_SHL)
6176 strcat (intel_parser.disp, "<<");
6177 else if (cur_token.code == T_SHR)
6178 strcat (intel_parser.disp, ">>");
6182 intel_match_token (cur_token.code);
6187 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6188 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6206 int nregs = ~NUM_ADDRESS_REGS;
6211 /* Don't consume constants here. */
6212 if (cur_token.code == '+' || cur_token.code == '-')
6214 /* Need to look one token ahead - if the next token
6215 is a constant, the current token is its sign. */
6218 intel_match_token (cur_token.code);
6219 next_code = cur_token.code;
6220 intel_putback_token ();
6221 if (next_code == T_CONST)
6225 /* e09 OFFSET e09 */
6226 if (cur_token.code == T_OFFSET)
6229 ++intel_parser.in_offset;
6233 else if (cur_token.code == T_SHORT)
6234 intel_parser.op_modifier |= 1 << T_SHORT;
6237 else if (cur_token.code == '+')
6238 strcat (intel_parser.disp, "+");
6243 else if (cur_token.code == '-' || cur_token.code == '~')
6249 str[0] = cur_token.code;
6251 strcat (intel_parser.disp, str);
6258 intel_match_token (cur_token.code);
6266 /* e09' PTR e10 e09' */
6267 if (cur_token.code == T_PTR)
6271 if (prev_token.code == T_BYTE)
6272 suffix = BYTE_MNEM_SUFFIX;
6274 else if (prev_token.code == T_WORD)
6276 if (current_templates->start->name[0] == 'l'
6277 && current_templates->start->name[2] == 's'
6278 && current_templates->start->name[3] == 0)
6279 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6280 else if (intel_parser.got_a_float == 2) /* "fi..." */
6281 suffix = SHORT_MNEM_SUFFIX;
6283 suffix = WORD_MNEM_SUFFIX;
6286 else if (prev_token.code == T_DWORD)
6288 if (current_templates->start->name[0] == 'l'
6289 && current_templates->start->name[2] == 's'
6290 && current_templates->start->name[3] == 0)
6291 suffix = WORD_MNEM_SUFFIX;
6292 else if (flag_code == CODE_16BIT
6293 && (current_templates->start->opcode_modifier
6294 & (Jump | JumpDword)))
6295 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6296 else if (intel_parser.got_a_float == 1) /* "f..." */
6297 suffix = SHORT_MNEM_SUFFIX;
6299 suffix = LONG_MNEM_SUFFIX;
6302 else if (prev_token.code == T_FWORD)
6304 if (current_templates->start->name[0] == 'l'
6305 && current_templates->start->name[2] == 's'
6306 && current_templates->start->name[3] == 0)
6307 suffix = LONG_MNEM_SUFFIX;
6308 else if (!intel_parser.got_a_float)
6310 if (flag_code == CODE_16BIT)
6311 add_prefix (DATA_PREFIX_OPCODE);
6312 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6315 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6318 else if (prev_token.code == T_QWORD)
6320 if (intel_parser.got_a_float == 1) /* "f..." */
6321 suffix = LONG_MNEM_SUFFIX;
6323 suffix = QWORD_MNEM_SUFFIX;
6326 else if (prev_token.code == T_TBYTE)
6328 if (intel_parser.got_a_float == 1)
6329 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6331 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6334 else if (prev_token.code == T_XMMWORD)
6336 /* XXX ignored for now, but accepted since gcc uses it */
6342 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6346 /* Operands for jump/call using 'ptr' notation denote absolute
6348 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6349 i.types[this_operand] |= JumpAbsolute;
6351 if (current_templates->start->base_opcode == 0x8d /* lea */)
6355 else if (i.suffix != suffix)
6357 as_bad (_("Conflicting operand modifiers"));
6363 /* e09' : e10 e09' */
6364 else if (cur_token.code == ':')
6366 if (prev_token.code != T_REG)
6368 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6369 segment/group identifier (which we don't have), using comma
6370 as the operand separator there is even less consistent, since
6371 there all branches only have a single operand. */
6372 if (this_operand != 0
6373 || intel_parser.in_offset
6374 || intel_parser.in_bracket
6375 || (!(current_templates->start->opcode_modifier
6376 & (Jump|JumpDword|JumpInterSegment))
6377 && !(current_templates->start->operand_types[0]
6379 return intel_match_token (T_NIL);
6380 /* Remember the start of the 2nd operand and terminate 1st
6382 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6383 another expression), but it gets at least the simplest case
6384 (a plain number or symbol on the left side) right. */
6385 intel_parser.next_operand = intel_parser.op_string;
6386 *--intel_parser.op_string = '\0';
6387 return intel_match_token (':');
6395 intel_match_token (cur_token.code);
6401 --intel_parser.in_offset;
6404 if (NUM_ADDRESS_REGS > nregs)
6406 as_bad (_("Invalid operand to `OFFSET'"));
6409 intel_parser.op_modifier |= 1 << T_OFFSET;
6412 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6413 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6418 intel_bracket_expr ()
6420 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6421 const char *start = intel_parser.op_string;
6424 if (i.op[this_operand].regs)
6425 return intel_match_token (T_NIL);
6427 intel_match_token ('[');
6429 /* Mark as a memory operand only if it's not already known to be an
6430 offset expression. If it's an offset expression, we need to keep
6432 if (!intel_parser.in_offset)
6434 ++intel_parser.in_bracket;
6436 /* Operands for jump/call inside brackets denote absolute addresses. */
6437 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6438 i.types[this_operand] |= JumpAbsolute;
6440 /* Unfortunately gas always diverged from MASM in a respect that can't
6441 be easily fixed without risking to break code sequences likely to be
6442 encountered (the testsuite even check for this): MASM doesn't consider
6443 an expression inside brackets unconditionally as a memory reference.
6444 When that is e.g. a constant, an offset expression, or the sum of the
6445 two, this is still taken as a constant load. gas, however, always
6446 treated these as memory references. As a compromise, we'll try to make
6447 offset expressions inside brackets work the MASM way (since that's
6448 less likely to be found in real world code), but make constants alone
6449 continue to work the traditional gas way. In either case, issue a
6451 intel_parser.op_modifier &= ~was_offset;
6454 strcat (intel_parser.disp, "[");
6456 /* Add a '+' to the displacement string if necessary. */
6457 if (*intel_parser.disp != '\0'
6458 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6459 strcat (intel_parser.disp, "+");
6462 && (len = intel_parser.op_string - start - 1,
6463 intel_match_token (']')))
6465 /* Preserve brackets when the operand is an offset expression. */
6466 if (intel_parser.in_offset)
6467 strcat (intel_parser.disp, "]");
6470 --intel_parser.in_bracket;
6471 if (i.base_reg || i.index_reg)
6472 intel_parser.is_mem = 1;
6473 if (!intel_parser.is_mem)
6475 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6476 /* Defer the warning until all of the operand was parsed. */
6477 intel_parser.is_mem = -1;
6478 else if (!quiet_warnings)
6479 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6482 intel_parser.op_modifier |= was_offset;
6499 while (cur_token.code == '[')
6501 if (!intel_bracket_expr ())
6526 switch (cur_token.code)
6530 intel_match_token ('(');
6531 strcat (intel_parser.disp, "(");
6533 if (intel_expr () && intel_match_token (')'))
6535 strcat (intel_parser.disp, ")");
6542 return intel_bracket_expr ();
6547 strcat (intel_parser.disp, cur_token.str);
6548 intel_match_token (cur_token.code);
6550 /* Mark as a memory operand only if it's not already known to be an
6551 offset expression. */
6552 if (!intel_parser.in_offset)
6553 intel_parser.is_mem = 1;
6560 const reg_entry *reg = intel_parser.reg = cur_token.reg;
6562 intel_match_token (T_REG);
6564 /* Check for segment change. */
6565 if (cur_token.code == ':')
6567 if (!(reg->reg_type & (SReg2 | SReg3)))
6569 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6572 else if (i.seg[i.mem_operands])
6573 as_warn (_("Extra segment override ignored"));
6576 if (!intel_parser.in_offset)
6577 intel_parser.is_mem = 1;
6578 switch (reg->reg_num)
6581 i.seg[i.mem_operands] = &es;
6584 i.seg[i.mem_operands] = &cs;
6587 i.seg[i.mem_operands] = &ss;
6590 i.seg[i.mem_operands] = &ds;
6593 i.seg[i.mem_operands] = &fs;
6596 i.seg[i.mem_operands] = &gs;
6602 /* Not a segment register. Check for register scaling. */
6603 else if (cur_token.code == '*')
6605 if (!intel_parser.in_bracket)
6607 as_bad (_("Register scaling only allowed in memory operands"));
6611 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6612 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6613 else if (i.index_reg)
6614 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6616 /* What follows must be a valid scale. */
6617 intel_match_token ('*');
6619 i.types[this_operand] |= BaseIndex;
6621 /* Set the scale after setting the register (otherwise,
6622 i386_scale will complain) */
6623 if (cur_token.code == '+' || cur_token.code == '-')
6625 char *str, sign = cur_token.code;
6626 intel_match_token (cur_token.code);
6627 if (cur_token.code != T_CONST)
6629 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6633 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6634 strcpy (str + 1, cur_token.str);
6636 if (!i386_scale (str))
6640 else if (!i386_scale (cur_token.str))
6642 intel_match_token (cur_token.code);
6645 /* No scaling. If this is a memory operand, the register is either a
6646 base register (first occurrence) or an index register (second
6648 else if (intel_parser.in_bracket)
6653 else if (!i.index_reg)
6657 as_bad (_("Too many register references in memory operand"));
6661 i.types[this_operand] |= BaseIndex;
6664 /* It's neither base nor index. */
6665 else if (!intel_parser.in_offset && !intel_parser.is_mem)
6667 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6668 i.op[this_operand].regs = reg;
6673 as_bad (_("Invalid use of register"));
6677 /* Since registers are not part of the displacement string (except
6678 when we're parsing offset operands), we may need to remove any
6679 preceding '+' from the displacement string. */
6680 if (*intel_parser.disp != '\0'
6681 && !intel_parser.in_offset)
6683 char *s = intel_parser.disp;
6684 s += strlen (s) - 1;
6707 intel_match_token (cur_token.code);
6709 if (cur_token.code == T_PTR)
6712 /* It must have been an identifier. */
6713 intel_putback_token ();
6714 cur_token.code = T_ID;
6720 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
6724 /* The identifier represents a memory reference only if it's not
6725 preceded by an offset modifier and if it's not an equate. */
6726 symbolP = symbol_find(cur_token.str);
6727 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6728 intel_parser.is_mem = 1;
6736 char *save_str, sign = 0;
6738 /* Allow constants that start with `+' or `-'. */
6739 if (cur_token.code == '-' || cur_token.code == '+')
6741 sign = cur_token.code;
6742 intel_match_token (cur_token.code);
6743 if (cur_token.code != T_CONST)
6745 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6751 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6752 strcpy (save_str + !!sign, cur_token.str);
6756 /* Get the next token to check for register scaling. */
6757 intel_match_token (cur_token.code);
6759 /* Check if this constant is a scaling factor for an index register. */
6760 if (cur_token.code == '*')
6762 if (intel_match_token ('*') && cur_token.code == T_REG)
6764 const reg_entry *reg = cur_token.reg;
6766 if (!intel_parser.in_bracket)
6768 as_bad (_("Register scaling only allowed in memory operands"));
6772 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6773 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6774 else if (i.index_reg)
6775 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6777 /* The constant is followed by `* reg', so it must be
6780 i.types[this_operand] |= BaseIndex;
6782 /* Set the scale after setting the register (otherwise,
6783 i386_scale will complain) */
6784 if (!i386_scale (save_str))
6786 intel_match_token (T_REG);
6788 /* Since registers are not part of the displacement
6789 string, we may need to remove any preceding '+' from
6790 the displacement string. */
6791 if (*intel_parser.disp != '\0')
6793 char *s = intel_parser.disp;
6794 s += strlen (s) - 1;
6804 /* The constant was not used for register scaling. Since we have
6805 already consumed the token following `*' we now need to put it
6806 back in the stream. */
6807 intel_putback_token ();
6810 /* Add the constant to the displacement string. */
6811 strcat (intel_parser.disp, save_str);
6818 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6822 /* Match the given token against cur_token. If they match, read the next
6823 token from the operand string. */
6825 intel_match_token (code)
6828 if (cur_token.code == code)
6835 as_bad (_("Unexpected token `%s'"), cur_token.str);
6840 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6845 const reg_entry *reg;
6846 struct intel_token new_token;
6848 new_token.code = T_NIL;
6849 new_token.reg = NULL;
6850 new_token.str = NULL;
6852 /* Free the memory allocated to the previous token and move
6853 cur_token to prev_token. */
6855 free (prev_token.str);
6857 prev_token = cur_token;
6859 /* Skip whitespace. */
6860 while (is_space_char (*intel_parser.op_string))
6861 intel_parser.op_string++;
6863 /* Return an empty token if we find nothing else on the line. */
6864 if (*intel_parser.op_string == '\0')
6866 cur_token = new_token;
6870 /* The new token cannot be larger than the remainder of the operand
6872 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
6873 new_token.str[0] = '\0';
6875 if (strchr ("0123456789", *intel_parser.op_string))
6877 char *p = new_token.str;
6878 char *q = intel_parser.op_string;
6879 new_token.code = T_CONST;
6881 /* Allow any kind of identifier char to encompass floating point and
6882 hexadecimal numbers. */
6883 while (is_identifier_char (*q))
6887 /* Recognize special symbol names [0-9][bf]. */
6888 if (strlen (intel_parser.op_string) == 2
6889 && (intel_parser.op_string[1] == 'b'
6890 || intel_parser.op_string[1] == 'f'))
6891 new_token.code = T_ID;
6894 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
6896 size_t len = end_op - intel_parser.op_string;
6898 new_token.code = T_REG;
6899 new_token.reg = reg;
6901 memcpy (new_token.str, intel_parser.op_string, len);
6902 new_token.str[len] = '\0';
6905 else if (is_identifier_char (*intel_parser.op_string))
6907 char *p = new_token.str;
6908 char *q = intel_parser.op_string;
6910 /* A '.' or '$' followed by an identifier char is an identifier.
6911 Otherwise, it's operator '.' followed by an expression. */
6912 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6914 new_token.code = '.';
6915 new_token.str[0] = '.';
6916 new_token.str[1] = '\0';
6920 while (is_identifier_char (*q) || *q == '@')
6924 if (strcasecmp (new_token.str, "NOT") == 0)
6925 new_token.code = '~';
6927 else if (strcasecmp (new_token.str, "MOD") == 0)
6928 new_token.code = '%';
6930 else if (strcasecmp (new_token.str, "AND") == 0)
6931 new_token.code = '&';
6933 else if (strcasecmp (new_token.str, "OR") == 0)
6934 new_token.code = '|';
6936 else if (strcasecmp (new_token.str, "XOR") == 0)
6937 new_token.code = '^';
6939 else if (strcasecmp (new_token.str, "SHL") == 0)
6940 new_token.code = T_SHL;
6942 else if (strcasecmp (new_token.str, "SHR") == 0)
6943 new_token.code = T_SHR;
6945 else if (strcasecmp (new_token.str, "BYTE") == 0)
6946 new_token.code = T_BYTE;
6948 else if (strcasecmp (new_token.str, "WORD") == 0)
6949 new_token.code = T_WORD;
6951 else if (strcasecmp (new_token.str, "DWORD") == 0)
6952 new_token.code = T_DWORD;
6954 else if (strcasecmp (new_token.str, "FWORD") == 0)
6955 new_token.code = T_FWORD;
6957 else if (strcasecmp (new_token.str, "QWORD") == 0)
6958 new_token.code = T_QWORD;
6960 else if (strcasecmp (new_token.str, "TBYTE") == 0
6961 /* XXX remove (gcc still uses it) */
6962 || strcasecmp (new_token.str, "XWORD") == 0)
6963 new_token.code = T_TBYTE;
6965 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6966 || strcasecmp (new_token.str, "OWORD") == 0)
6967 new_token.code = T_XMMWORD;
6969 else if (strcasecmp (new_token.str, "PTR") == 0)
6970 new_token.code = T_PTR;
6972 else if (strcasecmp (new_token.str, "SHORT") == 0)
6973 new_token.code = T_SHORT;
6975 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6977 new_token.code = T_OFFSET;
6979 /* ??? This is not mentioned in the MASM grammar but gcc
6980 makes use of it with -mintel-syntax. OFFSET may be
6981 followed by FLAT: */
6982 if (strncasecmp (q, " FLAT:", 6) == 0)
6983 strcat (new_token.str, " FLAT:");
6986 /* ??? This is not mentioned in the MASM grammar. */
6987 else if (strcasecmp (new_token.str, "FLAT") == 0)
6989 new_token.code = T_OFFSET;
6991 strcat (new_token.str, ":");
6993 as_bad (_("`:' expected"));
6997 new_token.code = T_ID;
7001 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7003 new_token.code = *intel_parser.op_string;
7004 new_token.str[0] = *intel_parser.op_string;
7005 new_token.str[1] = '\0';
7008 else if (strchr ("<>", *intel_parser.op_string)
7009 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7011 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7012 new_token.str[0] = *intel_parser.op_string;
7013 new_token.str[1] = *intel_parser.op_string;
7014 new_token.str[2] = '\0';
7018 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
7020 intel_parser.op_string += strlen (new_token.str);
7021 cur_token = new_token;
7024 /* Put cur_token back into the token stream and make cur_token point to
7027 intel_putback_token ()
7029 if (cur_token.code != T_NIL)
7031 intel_parser.op_string -= strlen (cur_token.str);
7032 free (cur_token.str);
7034 cur_token = prev_token;
7036 /* Forget prev_token. */
7037 prev_token.code = T_NIL;
7038 prev_token.reg = NULL;
7039 prev_token.str = NULL;
7043 tc_x86_regname_to_dw2regnum (const char *regname)
7045 unsigned int regnum;
7046 unsigned int regnames_count;
7047 static const char *const regnames_32[] =
7049 "eax", "ecx", "edx", "ebx",
7050 "esp", "ebp", "esi", "edi",
7051 "eip", "eflags", NULL,
7052 "st0", "st1", "st2", "st3",
7053 "st4", "st5", "st6", "st7",
7055 "xmm0", "xmm1", "xmm2", "xmm3",
7056 "xmm4", "xmm5", "xmm6", "xmm7",
7057 "mm0", "mm1", "mm2", "mm3",
7058 "mm4", "mm5", "mm6", "mm7",
7059 "fcw", "fsw", "mxcsr",
7060 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7063 static const char *const regnames_64[] =
7065 "rax", "rdx", "rcx", "rbx",
7066 "rsi", "rdi", "rbp", "rsp",
7067 "r8", "r9", "r10", "r11",
7068 "r12", "r13", "r14", "r15",
7070 "xmm0", "xmm1", "xmm2", "xmm3",
7071 "xmm4", "xmm5", "xmm6", "xmm7",
7072 "xmm8", "xmm9", "xmm10", "xmm11",
7073 "xmm12", "xmm13", "xmm14", "xmm15",
7074 "st0", "st1", "st2", "st3",
7075 "st4", "st5", "st6", "st7",
7076 "mm0", "mm1", "mm2", "mm3",
7077 "mm4", "mm5", "mm6", "mm7",
7079 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7080 "fs.base", "gs.base", NULL, NULL,
7082 "mxcsr", "fcw", "fsw"
7084 const char *const *regnames;
7086 if (flag_code == CODE_64BIT)
7088 regnames = regnames_64;
7089 regnames_count = ARRAY_SIZE (regnames_64);
7093 regnames = regnames_32;
7094 regnames_count = ARRAY_SIZE (regnames_32);
7097 for (regnum = 0; regnum < regnames_count; regnum++)
7098 if (regnames[regnum] != NULL
7099 && strcmp (regname, regnames[regnum]) == 0)
7106 tc_x86_frame_initial_instructions (void)
7108 static unsigned int sp_regno;
7111 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7114 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7115 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
7119 i386_elf_section_type (const char *str, size_t len)
7121 if (flag_code == CODE_64BIT
7122 && len == sizeof ("unwind") - 1
7123 && strncmp (str, "unwind", 6) == 0)
7124 return SHT_X86_64_UNWIND;
7131 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7135 expr.X_op = O_secrel;
7136 expr.X_add_symbol = symbol;
7137 expr.X_add_number = 0;
7138 emit_expr (&expr, size);
7142 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7143 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7146 x86_64_section_letter (int letter, char **ptr_msg)
7148 if (flag_code == CODE_64BIT)
7151 return SHF_X86_64_LARGE;
7153 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
7156 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
7161 x86_64_section_word (char *str, size_t len)
7163 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7164 return SHF_X86_64_LARGE;
7170 handle_large_common (int small ATTRIBUTE_UNUSED)
7172 if (flag_code != CODE_64BIT)
7174 s_comm_internal (0, elf_common_parse);
7175 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7179 static segT lbss_section;
7180 asection *saved_com_section_ptr = elf_com_section_ptr;
7181 asection *saved_bss_section = bss_section;
7183 if (lbss_section == NULL)
7185 flagword applicable;
7187 subsegT subseg = now_subseg;
7189 /* The .lbss section is for local .largecomm symbols. */
7190 lbss_section = subseg_new (".lbss", 0);
7191 applicable = bfd_applicable_section_flags (stdoutput);
7192 bfd_set_section_flags (stdoutput, lbss_section,
7193 applicable & SEC_ALLOC);
7194 seg_info (lbss_section)->bss = 1;
7196 subseg_set (seg, subseg);
7199 elf_com_section_ptr = &_bfd_elf_large_com_section;
7200 bss_section = lbss_section;
7202 s_comm_internal (0, elf_common_parse);
7204 elf_com_section_ptr = saved_com_section_ptr;
7205 bss_section = saved_bss_section;
7208 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */