1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c);
147 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
149 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS *);
154 static int i386_intel_parse_name (const char *, expressionS *);
155 static const reg_entry *parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry *build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS *, offsetT);
174 static void output_disp (fragS *, offsetT);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED);
182 static const char *default_arch = DEFAULT_ARCH;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry *regs;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types[MAX_OPERANDS];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op[MAX_OPERANDS];
229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry *seg[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
262 typedef struct _i386_insn i386_insn;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars = "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars = "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars[] = "#/";
304 const char line_separator_chars[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars[256];
317 static char register_chars[256];
318 static char operand_chars[256];
319 static char identifier_chars[256];
320 static char digit_chars[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack[32];
338 static char *save_stack_p;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates *current_templates;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
354 /* Current operand we are working on. */
355 static int this_operand = -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code;
366 static unsigned int object_64bit;
367 static int use_rela_relocations = 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names[] =
377 /* 1 for intel syntax,
379 static int intel_syntax = 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic = !SYSV386_COMPAT;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc = OLDGCC_COMPAT;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg = 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg = 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg = 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix = "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size = '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code = 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings = 0;
420 static const char *cpu_arch_name = NULL;
421 static char *cpu_sub_arch_name = NULL;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set = 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion = 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS *GOT_symbol;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch[] =
538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
544 { "i186", PROCESSOR_UNKNOWN,
546 { "i286", PROCESSOR_UNKNOWN,
548 { "i386", PROCESSOR_I386,
550 { "i486", PROCESSOR_I486,
552 { "i586", PROCESSOR_PENTIUM,
554 { "i686", PROCESSOR_PENTIUMPRO,
556 { "pentium", PROCESSOR_PENTIUM,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
564 { "pentium4", PROCESSOR_PENTIUM4,
566 { "prescott", PROCESSOR_NOCONA,
568 { "nocona", PROCESSOR_NOCONA,
570 { "yonah", PROCESSOR_CORE,
572 { "core", PROCESSOR_CORE,
574 { "merom", PROCESSOR_CORE2,
576 { "core2", PROCESSOR_CORE2,
578 { "corei7", PROCESSOR_COREI7,
580 { "k6", PROCESSOR_K6,
582 { "k6_2", PROCESSOR_K6,
584 { "athlon", PROCESSOR_ATHLON,
586 { "sledgehammer", PROCESSOR_K8,
588 { "opteron", PROCESSOR_K8,
590 { "k8", PROCESSOR_K8,
592 { "amdfam10", PROCESSOR_AMDFAM10,
593 CPU_AMDFAM10_FLAGS },
594 { ".mmx", PROCESSOR_UNKNOWN,
596 { ".sse", PROCESSOR_UNKNOWN,
598 { ".sse2", PROCESSOR_UNKNOWN,
600 { ".sse3", PROCESSOR_UNKNOWN,
602 { ".ssse3", PROCESSOR_UNKNOWN,
604 { ".sse4.1", PROCESSOR_UNKNOWN,
606 { ".sse4.2", PROCESSOR_UNKNOWN,
608 { ".sse4", PROCESSOR_UNKNOWN,
610 { ".avx", PROCESSOR_UNKNOWN,
612 { ".vmx", PROCESSOR_UNKNOWN,
614 { ".smx", PROCESSOR_UNKNOWN,
616 { ".xsave", PROCESSOR_UNKNOWN,
618 { ".aes", PROCESSOR_UNKNOWN,
620 { ".pclmul", PROCESSOR_UNKNOWN,
622 { ".clmul", PROCESSOR_UNKNOWN,
624 { ".fma", PROCESSOR_UNKNOWN,
626 { ".fma4", PROCESSOR_UNKNOWN,
628 { ".movbe", PROCESSOR_UNKNOWN,
630 { ".ept", PROCESSOR_UNKNOWN,
632 { ".clflush", PROCESSOR_UNKNOWN,
634 { ".syscall", PROCESSOR_UNKNOWN,
636 { ".rdtscp", PROCESSOR_UNKNOWN,
638 { ".3dnow", PROCESSOR_UNKNOWN,
640 { ".3dnowa", PROCESSOR_UNKNOWN,
642 { ".padlock", PROCESSOR_UNKNOWN,
644 { ".pacifica", PROCESSOR_UNKNOWN,
646 { ".svme", PROCESSOR_UNKNOWN,
648 { ".sse4a", PROCESSOR_UNKNOWN,
650 { ".abm", PROCESSOR_UNKNOWN,
655 /* Like s_lcomm_internal in gas/read.c but the alignment string
656 is allowed to be optional. */
659 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
666 && *input_line_pointer == ',')
668 align = parse_align (needs_align - 1);
670 if (align == (addressT) -1)
685 bss_alloc (symbolP, size, align);
690 pe_lcomm (int needs_align)
692 s_comm_internal (needs_align * 2, pe_lcomm_internal);
696 const pseudo_typeS md_pseudo_table[] =
698 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
699 {"align", s_align_bytes, 0},
701 {"align", s_align_ptwo, 0},
703 {"arch", set_cpu_arch, 0},
707 {"lcomm", pe_lcomm, 1},
709 {"ffloat", float_cons, 'f'},
710 {"dfloat", float_cons, 'd'},
711 {"tfloat", float_cons, 'x'},
713 {"slong", signed_cons, 4},
714 {"noopt", s_ignore, 0},
715 {"optim", s_ignore, 0},
716 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
717 {"code16", set_code_flag, CODE_16BIT},
718 {"code32", set_code_flag, CODE_32BIT},
719 {"code64", set_code_flag, CODE_64BIT},
720 {"intel_syntax", set_intel_syntax, 1},
721 {"att_syntax", set_intel_syntax, 0},
722 {"intel_mnemonic", set_intel_mnemonic, 1},
723 {"att_mnemonic", set_intel_mnemonic, 0},
724 {"allow_index_reg", set_allow_index_reg, 1},
725 {"disallow_index_reg", set_allow_index_reg, 0},
726 {"sse_check", set_sse_check, 0},
727 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
728 {"largecomm", handle_large_common, 0},
730 {"file", (void (*) (int)) dwarf2_directive_file, 0},
731 {"loc", dwarf2_directive_loc, 0},
732 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
735 {"secrel32", pe_directive_secrel, 0},
740 /* For interface with expression (). */
741 extern char *input_line_pointer;
743 /* Hash table for instruction mnemonic lookup. */
744 static struct hash_control *op_hash;
746 /* Hash table for register lookup. */
747 static struct hash_control *reg_hash;
750 i386_align_code (fragS *fragP, int count)
752 /* Various efficient no-op patterns for aligning code labels.
753 Note: Don't try to assemble the instructions in the comments.
754 0L and 0w are not legal. */
755 static const char f32_1[] =
757 static const char f32_2[] =
758 {0x66,0x90}; /* xchg %ax,%ax */
759 static const char f32_3[] =
760 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
761 static const char f32_4[] =
762 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
763 static const char f32_5[] =
765 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
766 static const char f32_6[] =
767 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
768 static const char f32_7[] =
769 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
770 static const char f32_8[] =
772 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
773 static const char f32_9[] =
774 {0x89,0xf6, /* movl %esi,%esi */
775 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
776 static const char f32_10[] =
777 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
778 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
779 static const char f32_11[] =
780 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
781 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
782 static const char f32_12[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
784 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
785 static const char f32_13[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
787 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
788 static const char f32_14[] =
789 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
790 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
791 static const char f16_3[] =
792 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
793 static const char f16_4[] =
794 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
795 static const char f16_5[] =
797 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
798 static const char f16_6[] =
799 {0x89,0xf6, /* mov %si,%si */
800 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
801 static const char f16_7[] =
802 {0x8d,0x74,0x00, /* lea 0(%si),%si */
803 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
804 static const char f16_8[] =
805 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
806 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
807 static const char jump_31[] =
808 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
810 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
811 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
812 static const char *const f32_patt[] = {
813 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
814 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
816 static const char *const f16_patt[] = {
817 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
820 static const char alt_3[] =
822 /* nopl 0(%[re]ax) */
823 static const char alt_4[] =
824 {0x0f,0x1f,0x40,0x00};
825 /* nopl 0(%[re]ax,%[re]ax,1) */
826 static const char alt_5[] =
827 {0x0f,0x1f,0x44,0x00,0x00};
828 /* nopw 0(%[re]ax,%[re]ax,1) */
829 static const char alt_6[] =
830 {0x66,0x0f,0x1f,0x44,0x00,0x00};
831 /* nopl 0L(%[re]ax) */
832 static const char alt_7[] =
833 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
834 /* nopl 0L(%[re]ax,%[re]ax,1) */
835 static const char alt_8[] =
836 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* nopw 0L(%[re]ax,%[re]ax,1) */
838 static const char alt_9[] =
839 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
840 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
841 static const char alt_10[] =
842 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 nopw %cs:0L(%[re]ax,%[re]ax,1) */
845 static const char alt_long_11[] =
847 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
850 nopw %cs:0L(%[re]ax,%[re]ax,1) */
851 static const char alt_long_12[] =
854 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_13[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_14[] =
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 nopw %cs:0L(%[re]ax,%[re]ax,1) */
881 static const char alt_long_15[] =
887 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1)
889 nopw 0(%[re]ax,%[re]ax,1) */
890 static const char alt_short_11[] =
891 {0x0f,0x1f,0x44,0x00,0x00,
892 0x66,0x0f,0x1f,0x44,0x00,0x00};
893 /* nopw 0(%[re]ax,%[re]ax,1)
894 nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_short_12[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00,
897 0x66,0x0f,0x1f,0x44,0x00,0x00};
898 /* nopw 0(%[re]ax,%[re]ax,1)
900 static const char alt_short_13[] =
901 {0x66,0x0f,0x1f,0x44,0x00,0x00,
902 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
905 static const char alt_short_14[] =
906 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
907 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
909 nopl 0L(%[re]ax,%[re]ax,1) */
910 static const char alt_short_15[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
912 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 static const char *const alt_short_patt[] = {
914 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
915 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
916 alt_short_14, alt_short_15
918 static const char *const alt_long_patt[] = {
919 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
920 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
921 alt_long_14, alt_long_15
924 /* Only align for at least a positive non-zero boundary. */
925 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
928 /* We need to decide which NOP sequence to use for 32bit and
929 64bit. When -mtune= is used:
931 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
932 PROCESSOR_GENERIC32, f32_patt will be used.
933 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
934 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
935 PROCESSOR_GENERIC64, alt_long_patt will be used.
936 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
937 PROCESSOR_AMDFAM10, alt_short_patt will be used.
939 When -mtune= isn't used, alt_long_patt will be used if
940 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
943 When -march= or .arch is used, we can't use anything beyond
944 cpu_arch_isa_flags. */
946 if (flag_code == CODE_16BIT)
950 memcpy (fragP->fr_literal + fragP->fr_fix,
952 /* Adjust jump offset. */
953 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
956 memcpy (fragP->fr_literal + fragP->fr_fix,
957 f16_patt[count - 1], count);
961 const char *const *patt = NULL;
963 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
965 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
966 switch (cpu_arch_tune)
968 case PROCESSOR_UNKNOWN:
969 /* We use cpu_arch_isa_flags to check if we SHOULD
970 optimize for Cpu686. */
971 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
972 patt = alt_long_patt;
976 case PROCESSOR_PENTIUMPRO:
977 case PROCESSOR_PENTIUM4:
978 case PROCESSOR_NOCONA:
980 case PROCESSOR_CORE2:
981 case PROCESSOR_COREI7:
982 case PROCESSOR_GENERIC64:
983 patt = alt_long_patt;
986 case PROCESSOR_ATHLON:
988 case PROCESSOR_AMDFAM10:
989 patt = alt_short_patt;
993 case PROCESSOR_PENTIUM:
994 case PROCESSOR_GENERIC32:
1001 switch (fragP->tc_frag_data.tune)
1003 case PROCESSOR_UNKNOWN:
1004 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1005 PROCESSOR_UNKNOWN. */
1009 case PROCESSOR_I386:
1010 case PROCESSOR_I486:
1011 case PROCESSOR_PENTIUM:
1013 case PROCESSOR_ATHLON:
1015 case PROCESSOR_AMDFAM10:
1016 case PROCESSOR_GENERIC32:
1017 /* We use cpu_arch_isa_flags to check if we CAN optimize
1019 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1020 patt = alt_short_patt;
1024 case PROCESSOR_PENTIUMPRO:
1025 case PROCESSOR_PENTIUM4:
1026 case PROCESSOR_NOCONA:
1027 case PROCESSOR_CORE:
1028 case PROCESSOR_CORE2:
1029 case PROCESSOR_COREI7:
1030 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
1031 patt = alt_long_patt;
1035 case PROCESSOR_GENERIC64:
1036 patt = alt_long_patt;
1041 if (patt == f32_patt)
1043 /* If the padding is less than 15 bytes, we use the normal
1044 ones. Otherwise, we use a jump instruction and adjust
1047 memcpy (fragP->fr_literal + fragP->fr_fix,
1048 patt[count - 1], count);
1051 memcpy (fragP->fr_literal + fragP->fr_fix,
1053 /* Adjust jump offset. */
1054 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1059 /* Maximum length of an instruction is 15 byte. If the
1060 padding is greater than 15 bytes and we don't use jump,
1061 we have to break it into smaller pieces. */
1062 int padding = count;
1063 while (padding > 15)
1066 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1071 memcpy (fragP->fr_literal + fragP->fr_fix,
1072 patt [padding - 1], padding);
1075 fragP->fr_var = count;
1079 operand_type_all_zero (const union i386_operand_type *x)
1081 switch (ARRAY_SIZE(x->array))
1090 return !x->array[0];
1097 operand_type_set (union i386_operand_type *x, unsigned int v)
1099 switch (ARRAY_SIZE(x->array))
1114 operand_type_equal (const union i386_operand_type *x,
1115 const union i386_operand_type *y)
1117 switch (ARRAY_SIZE(x->array))
1120 if (x->array[2] != y->array[2])
1123 if (x->array[1] != y->array[1])
1126 return x->array[0] == y->array[0];
1134 cpu_flags_all_zero (const union i386_cpu_flags *x)
1136 switch (ARRAY_SIZE(x->array))
1145 return !x->array[0];
1152 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1154 switch (ARRAY_SIZE(x->array))
1169 cpu_flags_equal (const union i386_cpu_flags *x,
1170 const union i386_cpu_flags *y)
1172 switch (ARRAY_SIZE(x->array))
1175 if (x->array[2] != y->array[2])
1178 if (x->array[1] != y->array[1])
1181 return x->array[0] == y->array[0];
1189 cpu_flags_check_cpu64 (i386_cpu_flags f)
1191 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1192 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1195 static INLINE i386_cpu_flags
1196 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1198 switch (ARRAY_SIZE (x.array))
1201 x.array [2] &= y.array [2];
1203 x.array [1] &= y.array [1];
1205 x.array [0] &= y.array [0];
1213 static INLINE i386_cpu_flags
1214 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1216 switch (ARRAY_SIZE (x.array))
1219 x.array [2] |= y.array [2];
1221 x.array [1] |= y.array [1];
1223 x.array [0] |= y.array [0];
1231 #define CPU_FLAGS_ARCH_MATCH 0x1
1232 #define CPU_FLAGS_64BIT_MATCH 0x2
1233 #define CPU_FLAGS_AES_MATCH 0x4
1234 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1235 #define CPU_FLAGS_AVX_MATCH 0x10
1237 #define CPU_FLAGS_32BIT_MATCH \
1238 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1239 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1240 #define CPU_FLAGS_PERFECT_MATCH \
1241 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1243 /* Return CPU flags match bits. */
1246 cpu_flags_match (const template *t)
1248 i386_cpu_flags x = t->cpu_flags;
1249 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1251 x.bitfield.cpu64 = 0;
1252 x.bitfield.cpuno64 = 0;
1254 if (cpu_flags_all_zero (&x))
1256 /* This instruction is available on all archs. */
1257 match |= CPU_FLAGS_32BIT_MATCH;
1261 /* This instruction is available only on some archs. */
1262 i386_cpu_flags cpu = cpu_arch_flags;
1264 cpu.bitfield.cpu64 = 0;
1265 cpu.bitfield.cpuno64 = 0;
1266 cpu = cpu_flags_and (x, cpu);
1267 if (!cpu_flags_all_zero (&cpu))
1269 if (x.bitfield.cpuavx)
1271 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1272 if (cpu.bitfield.cpuavx)
1274 /* Check SSE2AVX. */
1275 if (!t->opcode_modifier.sse2avx|| sse2avx)
1277 match |= (CPU_FLAGS_ARCH_MATCH
1278 | CPU_FLAGS_AVX_MATCH);
1280 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1281 match |= CPU_FLAGS_AES_MATCH;
1283 if (!x.bitfield.cpupclmul
1284 || cpu.bitfield.cpupclmul)
1285 match |= CPU_FLAGS_PCLMUL_MATCH;
1289 match |= CPU_FLAGS_ARCH_MATCH;
1292 match |= CPU_FLAGS_32BIT_MATCH;
1298 static INLINE i386_operand_type
1299 operand_type_and (i386_operand_type x, i386_operand_type y)
1301 switch (ARRAY_SIZE (x.array))
1304 x.array [2] &= y.array [2];
1306 x.array [1] &= y.array [1];
1308 x.array [0] &= y.array [0];
1316 static INLINE i386_operand_type
1317 operand_type_or (i386_operand_type x, i386_operand_type y)
1319 switch (ARRAY_SIZE (x.array))
1322 x.array [2] |= y.array [2];
1324 x.array [1] |= y.array [1];
1326 x.array [0] |= y.array [0];
1334 static INLINE i386_operand_type
1335 operand_type_xor (i386_operand_type x, i386_operand_type y)
1337 switch (ARRAY_SIZE (x.array))
1340 x.array [2] ^= y.array [2];
1342 x.array [1] ^= y.array [1];
1344 x.array [0] ^= y.array [0];
1352 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1353 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1354 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1355 static const i386_operand_type inoutportreg
1356 = OPERAND_TYPE_INOUTPORTREG;
1357 static const i386_operand_type reg16_inoutportreg
1358 = OPERAND_TYPE_REG16_INOUTPORTREG;
1359 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1360 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1361 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1362 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1363 static const i386_operand_type anydisp
1364 = OPERAND_TYPE_ANYDISP;
1365 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1366 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1367 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1368 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1369 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1370 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1371 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1372 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1373 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1374 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1375 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1386 operand_type_check (i386_operand_type t, enum operand_type c)
1391 return (t.bitfield.reg8
1394 || t.bitfield.reg64);
1397 return (t.bitfield.imm8
1401 || t.bitfield.imm32s
1402 || t.bitfield.imm64);
1405 return (t.bitfield.disp8
1406 || t.bitfield.disp16
1407 || t.bitfield.disp32
1408 || t.bitfield.disp32s
1409 || t.bitfield.disp64);
1412 return (t.bitfield.disp8
1413 || t.bitfield.disp16
1414 || t.bitfield.disp32
1415 || t.bitfield.disp32s
1416 || t.bitfield.disp64
1417 || t.bitfield.baseindex);
1426 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1427 operand J for instruction template T. */
1430 match_reg_size (const template *t, unsigned int j)
1432 return !((i.types[j].bitfield.byte
1433 && !t->operand_types[j].bitfield.byte)
1434 || (i.types[j].bitfield.word
1435 && !t->operand_types[j].bitfield.word)
1436 || (i.types[j].bitfield.dword
1437 && !t->operand_types[j].bitfield.dword)
1438 || (i.types[j].bitfield.qword
1439 && !t->operand_types[j].bitfield.qword));
1442 /* Return 1 if there is no conflict in any size on operand J for
1443 instruction template T. */
1446 match_mem_size (const template *t, unsigned int j)
1448 return (match_reg_size (t, j)
1449 && !((i.types[j].bitfield.unspecified
1450 && !t->operand_types[j].bitfield.unspecified)
1451 || (i.types[j].bitfield.fword
1452 && !t->operand_types[j].bitfield.fword)
1453 || (i.types[j].bitfield.tbyte
1454 && !t->operand_types[j].bitfield.tbyte)
1455 || (i.types[j].bitfield.xmmword
1456 && !t->operand_types[j].bitfield.xmmword)
1457 || (i.types[j].bitfield.ymmword
1458 && !t->operand_types[j].bitfield.ymmword)));
1461 /* Return 1 if there is no size conflict on any operands for
1462 instruction template T. */
1465 operand_size_match (const template *t)
1470 /* Don't check jump instructions. */
1471 if (t->opcode_modifier.jump
1472 || t->opcode_modifier.jumpbyte
1473 || t->opcode_modifier.jumpdword
1474 || t->opcode_modifier.jumpintersegment)
1477 /* Check memory and accumulator operand size. */
1478 for (j = 0; j < i.operands; j++)
1480 if (t->operand_types[j].bitfield.anysize)
1483 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1489 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1497 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1500 /* Check reverse. */
1501 gas_assert (i.operands == 2);
1504 for (j = 0; j < 2; j++)
1506 if (t->operand_types[j].bitfield.acc
1507 && !match_reg_size (t, j ? 0 : 1))
1513 if (i.types[j].bitfield.mem
1514 && !match_mem_size (t, j ? 0 : 1))
1525 operand_type_match (i386_operand_type overlap,
1526 i386_operand_type given)
1528 i386_operand_type temp = overlap;
1530 temp.bitfield.jumpabsolute = 0;
1531 temp.bitfield.unspecified = 0;
1532 temp.bitfield.byte = 0;
1533 temp.bitfield.word = 0;
1534 temp.bitfield.dword = 0;
1535 temp.bitfield.fword = 0;
1536 temp.bitfield.qword = 0;
1537 temp.bitfield.tbyte = 0;
1538 temp.bitfield.xmmword = 0;
1539 temp.bitfield.ymmword = 0;
1540 if (operand_type_all_zero (&temp))
1543 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1544 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1547 /* If given types g0 and g1 are registers they must be of the same type
1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1552 operand_type_register_match (i386_operand_type m0,
1553 i386_operand_type g0,
1554 i386_operand_type t0,
1555 i386_operand_type m1,
1556 i386_operand_type g1,
1557 i386_operand_type t1)
1559 if (!operand_type_check (g0, reg))
1562 if (!operand_type_check (g1, reg))
1565 if (g0.bitfield.reg8 == g1.bitfield.reg8
1566 && g0.bitfield.reg16 == g1.bitfield.reg16
1567 && g0.bitfield.reg32 == g1.bitfield.reg32
1568 && g0.bitfield.reg64 == g1.bitfield.reg64)
1571 if (m0.bitfield.acc)
1573 t0.bitfield.reg8 = 1;
1574 t0.bitfield.reg16 = 1;
1575 t0.bitfield.reg32 = 1;
1576 t0.bitfield.reg64 = 1;
1579 if (m1.bitfield.acc)
1581 t1.bitfield.reg8 = 1;
1582 t1.bitfield.reg16 = 1;
1583 t1.bitfield.reg32 = 1;
1584 t1.bitfield.reg64 = 1;
1587 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1588 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1589 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1590 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1593 static INLINE unsigned int
1594 mode_from_disp_size (i386_operand_type t)
1596 if (t.bitfield.disp8)
1598 else if (t.bitfield.disp16
1599 || t.bitfield.disp32
1600 || t.bitfield.disp32s)
1607 fits_in_signed_byte (offsetT num)
1609 return (num >= -128) && (num <= 127);
1613 fits_in_unsigned_byte (offsetT num)
1615 return (num & 0xff) == num;
1619 fits_in_unsigned_word (offsetT num)
1621 return (num & 0xffff) == num;
1625 fits_in_signed_word (offsetT num)
1627 return (-32768 <= num) && (num <= 32767);
1631 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1636 return (!(((offsetT) -1 << 31) & num)
1637 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1639 } /* fits_in_signed_long() */
1642 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1647 return (num & (((offsetT) 2 << 31) - 1)) == num;
1649 } /* fits_in_unsigned_long() */
1651 static i386_operand_type
1652 smallest_imm_type (offsetT num)
1654 i386_operand_type t;
1656 operand_type_set (&t, 0);
1657 t.bitfield.imm64 = 1;
1659 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1661 /* This code is disabled on the 486 because all the Imm1 forms
1662 in the opcode table are slower on the i486. They're the
1663 versions with the implicitly specified single-position
1664 displacement, which has another syntax if you really want to
1666 t.bitfield.imm1 = 1;
1667 t.bitfield.imm8 = 1;
1668 t.bitfield.imm8s = 1;
1669 t.bitfield.imm16 = 1;
1670 t.bitfield.imm32 = 1;
1671 t.bitfield.imm32s = 1;
1673 else if (fits_in_signed_byte (num))
1675 t.bitfield.imm8 = 1;
1676 t.bitfield.imm8s = 1;
1677 t.bitfield.imm16 = 1;
1678 t.bitfield.imm32 = 1;
1679 t.bitfield.imm32s = 1;
1681 else if (fits_in_unsigned_byte (num))
1683 t.bitfield.imm8 = 1;
1684 t.bitfield.imm16 = 1;
1685 t.bitfield.imm32 = 1;
1686 t.bitfield.imm32s = 1;
1688 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1690 t.bitfield.imm16 = 1;
1691 t.bitfield.imm32 = 1;
1692 t.bitfield.imm32s = 1;
1694 else if (fits_in_signed_long (num))
1696 t.bitfield.imm32 = 1;
1697 t.bitfield.imm32s = 1;
1699 else if (fits_in_unsigned_long (num))
1700 t.bitfield.imm32 = 1;
1706 offset_in_range (offsetT val, int size)
1712 case 1: mask = ((addressT) 1 << 8) - 1; break;
1713 case 2: mask = ((addressT) 1 << 16) - 1; break;
1714 case 4: mask = ((addressT) 2 << 31) - 1; break;
1716 case 8: mask = ((addressT) 2 << 63) - 1; break;
1721 /* If BFD64, sign extend val. */
1722 if (!use_rela_relocations)
1723 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1724 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1726 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1728 char buf1[40], buf2[40];
1730 sprint_value (buf1, val);
1731 sprint_value (buf2, val & mask);
1732 as_warn (_("%s shortened to %s"), buf1, buf2);
1737 /* Returns 0 if attempting to add a prefix where one from the same
1738 class already exists, 1 if non rep/repne added, 2 if rep/repne
1741 add_prefix (unsigned int prefix)
1746 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1747 && flag_code == CODE_64BIT)
1749 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1750 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1751 && (prefix & (REX_R | REX_X | REX_B))))
1762 case CS_PREFIX_OPCODE:
1763 case DS_PREFIX_OPCODE:
1764 case ES_PREFIX_OPCODE:
1765 case FS_PREFIX_OPCODE:
1766 case GS_PREFIX_OPCODE:
1767 case SS_PREFIX_OPCODE:
1771 case REPNE_PREFIX_OPCODE:
1772 case REPE_PREFIX_OPCODE:
1775 case LOCK_PREFIX_OPCODE:
1783 case ADDR_PREFIX_OPCODE:
1787 case DATA_PREFIX_OPCODE:
1791 if (i.prefix[q] != 0)
1799 i.prefix[q] |= prefix;
1802 as_bad (_("same type of prefix used twice"));
1808 set_code_flag (int value)
1811 if (flag_code == CODE_64BIT)
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
1821 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1823 as_bad (_("64bit mode not supported on this CPU."));
1825 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1827 as_bad (_("32bit mode not supported on this CPU."));
1829 stackop_size = '\0';
1833 set_16bit_gcc_code_flag (int new_code_flag)
1835 flag_code = new_code_flag;
1836 if (flag_code != CODE_16BIT)
1838 cpu_arch_flags.bitfield.cpu64 = 0;
1839 cpu_arch_flags.bitfield.cpuno64 = 1;
1840 stackop_size = LONG_MNEM_SUFFIX;
1844 set_intel_syntax (int syntax_flag)
1846 /* Find out if register prefixing is specified. */
1847 int ask_naked_reg = 0;
1850 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1852 char *string = input_line_pointer;
1853 int e = get_symbol_end ();
1855 if (strcmp (string, "prefix") == 0)
1857 else if (strcmp (string, "noprefix") == 0)
1860 as_bad (_("bad argument to syntax directive."));
1861 *input_line_pointer = e;
1863 demand_empty_rest_of_line ();
1865 intel_syntax = syntax_flag;
1867 if (ask_naked_reg == 0)
1868 allow_naked_reg = (intel_syntax
1869 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
1871 allow_naked_reg = (ask_naked_reg < 0);
1873 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
1875 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1876 identifier_chars['$'] = intel_syntax ? '$' : 0;
1877 register_prefix = allow_naked_reg ? "" : "%";
1881 set_intel_mnemonic (int mnemonic_flag)
1883 intel_mnemonic = mnemonic_flag;
1887 set_allow_index_reg (int flag)
1889 allow_index_reg = flag;
1893 set_sse_check (int dummy ATTRIBUTE_UNUSED)
1897 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1899 char *string = input_line_pointer;
1900 int e = get_symbol_end ();
1902 if (strcmp (string, "none") == 0)
1903 sse_check = sse_check_none;
1904 else if (strcmp (string, "warning") == 0)
1905 sse_check = sse_check_warning;
1906 else if (strcmp (string, "error") == 0)
1907 sse_check = sse_check_error;
1909 as_bad (_("bad argument to sse_check directive."));
1910 *input_line_pointer = e;
1913 as_bad (_("missing argument for sse_check directive"));
1915 demand_empty_rest_of_line ();
1919 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
1923 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1925 char *string = input_line_pointer;
1926 int e = get_symbol_end ();
1928 i386_cpu_flags flags;
1930 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
1932 if (strcmp (string, cpu_arch[i].name) == 0)
1936 cpu_arch_name = cpu_arch[i].name;
1937 cpu_sub_arch_name = NULL;
1938 cpu_arch_flags = cpu_arch[i].flags;
1939 if (flag_code == CODE_64BIT)
1941 cpu_arch_flags.bitfield.cpu64 = 1;
1942 cpu_arch_flags.bitfield.cpuno64 = 0;
1946 cpu_arch_flags.bitfield.cpu64 = 0;
1947 cpu_arch_flags.bitfield.cpuno64 = 1;
1949 cpu_arch_isa = cpu_arch[i].type;
1950 cpu_arch_isa_flags = cpu_arch[i].flags;
1951 if (!cpu_arch_tune_set)
1953 cpu_arch_tune = cpu_arch_isa;
1954 cpu_arch_tune_flags = cpu_arch_isa_flags;
1959 flags = cpu_flags_or (cpu_arch_flags,
1961 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
1963 if (cpu_sub_arch_name)
1965 char *name = cpu_sub_arch_name;
1966 cpu_sub_arch_name = concat (name,
1968 (const char *) NULL);
1972 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
1973 cpu_arch_flags = flags;
1975 *input_line_pointer = e;
1976 demand_empty_rest_of_line ();
1980 if (i >= ARRAY_SIZE (cpu_arch))
1981 as_bad (_("no such architecture: `%s'"), string);
1983 *input_line_pointer = e;
1986 as_bad (_("missing cpu architecture"));
1988 no_cond_jump_promotion = 0;
1989 if (*input_line_pointer == ','
1990 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
1992 char *string = ++input_line_pointer;
1993 int e = get_symbol_end ();
1995 if (strcmp (string, "nojumps") == 0)
1996 no_cond_jump_promotion = 1;
1997 else if (strcmp (string, "jumps") == 0)
2000 as_bad (_("no such architecture modifier: `%s'"), string);
2002 *input_line_pointer = e;
2005 demand_empty_rest_of_line ();
2011 if (!strcmp (default_arch, "x86_64"))
2012 return bfd_mach_x86_64;
2013 else if (!strcmp (default_arch, "i386"))
2014 return bfd_mach_i386_i386;
2016 as_fatal (_("Unknown architecture"));
2022 const char *hash_err;
2024 /* Initialize op_hash hash table. */
2025 op_hash = hash_new ();
2028 const template *optab;
2029 templates *core_optab;
2031 /* Setup for loop. */
2033 core_optab = (templates *) xmalloc (sizeof (templates));
2034 core_optab->start = optab;
2039 if (optab->name == NULL
2040 || strcmp (optab->name, (optab - 1)->name) != 0)
2042 /* different name --> ship out current template list;
2043 add to hash table; & begin anew. */
2044 core_optab->end = optab;
2045 hash_err = hash_insert (op_hash,
2047 (void *) core_optab);
2050 as_fatal (_("Internal Error: Can't hash %s: %s"),
2054 if (optab->name == NULL)
2056 core_optab = (templates *) xmalloc (sizeof (templates));
2057 core_optab->start = optab;
2062 /* Initialize reg_hash hash table. */
2063 reg_hash = hash_new ();
2065 const reg_entry *regtab;
2066 unsigned int regtab_size = i386_regtab_size;
2068 for (regtab = i386_regtab; regtab_size--; regtab++)
2070 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2072 as_fatal (_("Internal Error: Can't hash %s: %s"),
2078 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2083 for (c = 0; c < 256; c++)
2088 mnemonic_chars[c] = c;
2089 register_chars[c] = c;
2090 operand_chars[c] = c;
2092 else if (ISLOWER (c))
2094 mnemonic_chars[c] = c;
2095 register_chars[c] = c;
2096 operand_chars[c] = c;
2098 else if (ISUPPER (c))
2100 mnemonic_chars[c] = TOLOWER (c);
2101 register_chars[c] = mnemonic_chars[c];
2102 operand_chars[c] = c;
2105 if (ISALPHA (c) || ISDIGIT (c))
2106 identifier_chars[c] = c;
2109 identifier_chars[c] = c;
2110 operand_chars[c] = c;
2115 identifier_chars['@'] = '@';
2118 identifier_chars['?'] = '?';
2119 operand_chars['?'] = '?';
2121 digit_chars['-'] = '-';
2122 mnemonic_chars['_'] = '_';
2123 mnemonic_chars['-'] = '-';
2124 mnemonic_chars['.'] = '.';
2125 identifier_chars['_'] = '_';
2126 identifier_chars['.'] = '.';
2128 for (p = operand_special_chars; *p != '\0'; p++)
2129 operand_chars[(unsigned char) *p] = *p;
2132 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2135 record_alignment (text_section, 2);
2136 record_alignment (data_section, 2);
2137 record_alignment (bss_section, 2);
2141 if (flag_code == CODE_64BIT)
2143 x86_dwarf2_return_column = 16;
2144 x86_cie_data_alignment = -8;
2148 x86_dwarf2_return_column = 8;
2149 x86_cie_data_alignment = -4;
2154 i386_print_statistics (FILE *file)
2156 hash_print_statistics (file, "i386 opcode", op_hash);
2157 hash_print_statistics (file, "i386 register", reg_hash);
2162 /* Debugging routines for md_assemble. */
2163 static void pte (template *);
2164 static void pt (i386_operand_type);
2165 static void pe (expressionS *);
2166 static void ps (symbolS *);
2169 pi (char *line, i386_insn *x)
2173 fprintf (stdout, "%s: template ", line);
2175 fprintf (stdout, " address: base %s index %s scale %x\n",
2176 x->base_reg ? x->base_reg->reg_name : "none",
2177 x->index_reg ? x->index_reg->reg_name : "none",
2178 x->log2_scale_factor);
2179 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2180 x->rm.mode, x->rm.reg, x->rm.regmem);
2181 fprintf (stdout, " sib: base %x index %x scale %x\n",
2182 x->sib.base, x->sib.index, x->sib.scale);
2183 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2184 (x->rex & REX_W) != 0,
2185 (x->rex & REX_R) != 0,
2186 (x->rex & REX_X) != 0,
2187 (x->rex & REX_B) != 0);
2188 for (i = 0; i < x->operands; i++)
2190 fprintf (stdout, " #%d: ", i + 1);
2192 fprintf (stdout, "\n");
2193 if (x->types[i].bitfield.reg8
2194 || x->types[i].bitfield.reg16
2195 || x->types[i].bitfield.reg32
2196 || x->types[i].bitfield.reg64
2197 || x->types[i].bitfield.regmmx
2198 || x->types[i].bitfield.regxmm
2199 || x->types[i].bitfield.regymm
2200 || x->types[i].bitfield.sreg2
2201 || x->types[i].bitfield.sreg3
2202 || x->types[i].bitfield.control
2203 || x->types[i].bitfield.debug
2204 || x->types[i].bitfield.test)
2205 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
2206 if (operand_type_check (x->types[i], imm))
2208 if (operand_type_check (x->types[i], disp))
2209 pe (x->op[i].disps);
2217 fprintf (stdout, " %d operands ", t->operands);
2218 fprintf (stdout, "opcode %x ", t->base_opcode);
2219 if (t->extension_opcode != None)
2220 fprintf (stdout, "ext %x ", t->extension_opcode);
2221 if (t->opcode_modifier.d)
2222 fprintf (stdout, "D");
2223 if (t->opcode_modifier.w)
2224 fprintf (stdout, "W");
2225 fprintf (stdout, "\n");
2226 for (i = 0; i < t->operands; i++)
2228 fprintf (stdout, " #%d type ", i + 1);
2229 pt (t->operand_types[i]);
2230 fprintf (stdout, "\n");
2237 fprintf (stdout, " operation %d\n", e->X_op);
2238 fprintf (stdout, " add_number %ld (%lx)\n",
2239 (long) e->X_add_number, (long) e->X_add_number);
2240 if (e->X_add_symbol)
2242 fprintf (stdout, " add_symbol ");
2243 ps (e->X_add_symbol);
2244 fprintf (stdout, "\n");
2248 fprintf (stdout, " op_symbol ");
2249 ps (e->X_op_symbol);
2250 fprintf (stdout, "\n");
2257 fprintf (stdout, "%s type %s%s",
2259 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2260 segment_name (S_GET_SEGMENT (s)));
2263 static struct type_name
2265 i386_operand_type mask;
2268 const type_names[] =
2270 { OPERAND_TYPE_REG8, "r8" },
2271 { OPERAND_TYPE_REG16, "r16" },
2272 { OPERAND_TYPE_REG32, "r32" },
2273 { OPERAND_TYPE_REG64, "r64" },
2274 { OPERAND_TYPE_IMM8, "i8" },
2275 { OPERAND_TYPE_IMM8, "i8s" },
2276 { OPERAND_TYPE_IMM16, "i16" },
2277 { OPERAND_TYPE_IMM32, "i32" },
2278 { OPERAND_TYPE_IMM32S, "i32s" },
2279 { OPERAND_TYPE_IMM64, "i64" },
2280 { OPERAND_TYPE_IMM1, "i1" },
2281 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2282 { OPERAND_TYPE_DISP8, "d8" },
2283 { OPERAND_TYPE_DISP16, "d16" },
2284 { OPERAND_TYPE_DISP32, "d32" },
2285 { OPERAND_TYPE_DISP32S, "d32s" },
2286 { OPERAND_TYPE_DISP64, "d64" },
2287 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2288 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2289 { OPERAND_TYPE_CONTROL, "control reg" },
2290 { OPERAND_TYPE_TEST, "test reg" },
2291 { OPERAND_TYPE_DEBUG, "debug reg" },
2292 { OPERAND_TYPE_FLOATREG, "FReg" },
2293 { OPERAND_TYPE_FLOATACC, "FAcc" },
2294 { OPERAND_TYPE_SREG2, "SReg2" },
2295 { OPERAND_TYPE_SREG3, "SReg3" },
2296 { OPERAND_TYPE_ACC, "Acc" },
2297 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2298 { OPERAND_TYPE_REGMMX, "rMMX" },
2299 { OPERAND_TYPE_REGXMM, "rXMM" },
2300 { OPERAND_TYPE_REGYMM, "rYMM" },
2301 { OPERAND_TYPE_ESSEG, "es" },
2305 pt (i386_operand_type t)
2308 i386_operand_type a;
2310 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2312 a = operand_type_and (t, type_names[j].mask);
2313 if (!operand_type_all_zero (&a))
2314 fprintf (stdout, "%s, ", type_names[j].name);
2319 #endif /* DEBUG386 */
2321 static bfd_reloc_code_real_type
2322 reloc (unsigned int size,
2325 bfd_reloc_code_real_type other)
2327 if (other != NO_RELOC)
2329 reloc_howto_type *reloc;
2334 case BFD_RELOC_X86_64_GOT32:
2335 return BFD_RELOC_X86_64_GOT64;
2337 case BFD_RELOC_X86_64_PLTOFF64:
2338 return BFD_RELOC_X86_64_PLTOFF64;
2340 case BFD_RELOC_X86_64_GOTPC32:
2341 other = BFD_RELOC_X86_64_GOTPC64;
2343 case BFD_RELOC_X86_64_GOTPCREL:
2344 other = BFD_RELOC_X86_64_GOTPCREL64;
2346 case BFD_RELOC_X86_64_TPOFF32:
2347 other = BFD_RELOC_X86_64_TPOFF64;
2349 case BFD_RELOC_X86_64_DTPOFF32:
2350 other = BFD_RELOC_X86_64_DTPOFF64;
2356 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2357 if (size == 4 && flag_code != CODE_64BIT)
2360 reloc = bfd_reloc_type_lookup (stdoutput, other);
2362 as_bad (_("unknown relocation (%u)"), other);
2363 else if (size != bfd_get_reloc_size (reloc))
2364 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2365 bfd_get_reloc_size (reloc),
2367 else if (pcrel && !reloc->pc_relative)
2368 as_bad (_("non-pc-relative relocation for pc-relative field"));
2369 else if ((reloc->complain_on_overflow == complain_overflow_signed
2371 || (reloc->complain_on_overflow == complain_overflow_unsigned
2373 as_bad (_("relocated field and relocation type differ in signedness"));
2382 as_bad (_("there are no unsigned pc-relative relocations"));
2385 case 1: return BFD_RELOC_8_PCREL;
2386 case 2: return BFD_RELOC_16_PCREL;
2387 case 4: return BFD_RELOC_32_PCREL;
2388 case 8: return BFD_RELOC_64_PCREL;
2390 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2397 case 4: return BFD_RELOC_X86_64_32S;
2402 case 1: return BFD_RELOC_8;
2403 case 2: return BFD_RELOC_16;
2404 case 4: return BFD_RELOC_32;
2405 case 8: return BFD_RELOC_64;
2407 as_bad (_("cannot do %s %u byte relocation"),
2408 sign > 0 ? "signed" : "unsigned", size);
2414 /* Here we decide which fixups can be adjusted to make them relative to
2415 the beginning of the section instead of the symbol. Basically we need
2416 to make sure that the dynamic relocations are done correctly, so in
2417 some cases we force the original symbol to be used. */
2420 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2422 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2426 /* Don't adjust pc-relative references to merge sections in 64-bit
2428 if (use_rela_relocations
2429 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2433 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2434 and changed later by validate_fix. */
2435 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2436 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2439 /* adjust_reloc_syms doesn't know about the GOT. */
2440 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2441 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2442 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2443 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2444 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2445 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2446 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2447 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2448 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2449 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2450 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2451 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2452 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2453 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2454 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2455 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2456 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2457 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2458 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2459 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2460 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2461 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2462 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2463 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2464 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2465 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2466 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2467 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2470 if (fixP->fx_addsy != NULL
2471 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2478 intel_float_operand (const char *mnemonic)
2480 /* Note that the value returned is meaningful only for opcodes with (memory)
2481 operands, hence the code here is free to improperly handle opcodes that
2482 have no operands (for better performance and smaller code). */
2484 if (mnemonic[0] != 'f')
2485 return 0; /* non-math */
2487 switch (mnemonic[1])
2489 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2490 the fs segment override prefix not currently handled because no
2491 call path can make opcodes without operands get here */
2493 return 2 /* integer op */;
2495 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2496 return 3; /* fldcw/fldenv */
2499 if (mnemonic[2] != 'o' /* fnop */)
2500 return 3; /* non-waiting control op */
2503 if (mnemonic[2] == 's')
2504 return 3; /* frstor/frstpm */
2507 if (mnemonic[2] == 'a')
2508 return 3; /* fsave */
2509 if (mnemonic[2] == 't')
2511 switch (mnemonic[3])
2513 case 'c': /* fstcw */
2514 case 'd': /* fstdw */
2515 case 'e': /* fstenv */
2516 case 's': /* fsts[gw] */
2522 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2523 return 0; /* fxsave/fxrstor are not really math ops */
2530 /* Build the VEX prefix. */
2533 build_vex_prefix (const template *t)
2535 unsigned int register_specifier;
2536 unsigned int implied_prefix;
2537 unsigned int vector_length;
2539 /* Check register specifier. */
2540 if (i.vex.register_specifier)
2542 register_specifier = i.vex.register_specifier->reg_num;
2543 if ((i.vex.register_specifier->reg_flags & RegRex))
2544 register_specifier += 8;
2545 register_specifier = ~register_specifier & 0xf;
2548 register_specifier = 0xf;
2550 /* Use 2-byte VEX prefix by swappping destination and source
2553 && i.operands == i.reg_operands
2554 && i.tm.opcode_modifier.vex0f
2555 && i.tm.opcode_modifier.s
2558 unsigned int xchg = i.operands - 1;
2559 union i386_op temp_op;
2560 i386_operand_type temp_type;
2562 temp_type = i.types[xchg];
2563 i.types[xchg] = i.types[0];
2564 i.types[0] = temp_type;
2565 temp_op = i.op[xchg];
2566 i.op[xchg] = i.op[0];
2569 gas_assert (i.rm.mode == 3);
2573 i.rm.regmem = i.rm.reg;
2576 /* Use the next insn. */
2580 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2582 switch ((i.tm.base_opcode >> 8) & 0xff)
2587 case DATA_PREFIX_OPCODE:
2590 case REPE_PREFIX_OPCODE:
2593 case REPNE_PREFIX_OPCODE:
2600 /* Use 2-byte VEX prefix if possible. */
2601 if (i.tm.opcode_modifier.vex0f
2602 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2604 /* 2-byte VEX prefix. */
2608 i.vex.bytes[0] = 0xc5;
2610 /* Check the REX.R bit. */
2611 r = (i.rex & REX_R) ? 0 : 1;
2612 i.vex.bytes[1] = (r << 7
2613 | register_specifier << 3
2614 | vector_length << 2
2619 /* 3-byte VEX prefix. */
2622 if (i.tm.opcode_modifier.vex0f)
2624 else if (i.tm.opcode_modifier.vex0f38)
2626 else if (i.tm.opcode_modifier.vex0f3a)
2632 i.vex.bytes[0] = 0xc4;
2634 /* The high 3 bits of the second VEX byte are 1's compliment
2635 of RXB bits from REX. */
2636 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2638 /* Check the REX.W bit. */
2639 w = (i.rex & REX_W) ? 1 : 0;
2640 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2645 if (i.tm.opcode_modifier.vexw1)
2649 i.vex.bytes[2] = (w << 7
2650 | register_specifier << 3
2651 | vector_length << 2
2657 process_immext (void)
2661 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2663 /* SSE3 Instructions have the fixed operands with an opcode
2664 suffix which is coded in the same place as an 8-bit immediate
2665 field would be. Here we check those operands and remove them
2669 for (x = 0; x < i.operands; x++)
2670 if (i.op[x].regs->reg_num != x)
2671 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2672 register_prefix, i.op[x].regs->reg_name, x + 1,
2678 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2679 which is coded in the same place as an 8-bit immediate field
2680 would be. Here we fake an 8-bit immediate operand from the
2681 opcode suffix stored in tm.extension_opcode.
2683 AVX instructions also use this encoding, for some of
2684 3 argument instructions. */
2686 gas_assert (i.imm_operands == 0
2688 || (i.tm.opcode_modifier.vex
2689 && i.operands <= 4)));
2691 exp = &im_expressions[i.imm_operands++];
2692 i.op[i.operands].imms = exp;
2693 i.types[i.operands] = imm8;
2695 exp->X_op = O_constant;
2696 exp->X_add_number = i.tm.extension_opcode;
2697 i.tm.extension_opcode = None;
2700 /* This is the guts of the machine-dependent assembler. LINE points to a
2701 machine dependent instruction. This function is supposed to emit
2702 the frags/bytes it assembles to. */
2705 md_assemble (char *line)
2708 char mnemonic[MAX_MNEM_SIZE];
2711 /* Initialize globals. */
2712 memset (&i, '\0', sizeof (i));
2713 for (j = 0; j < MAX_OPERANDS; j++)
2714 i.reloc[j] = NO_RELOC;
2715 memset (disp_expressions, '\0', sizeof (disp_expressions));
2716 memset (im_expressions, '\0', sizeof (im_expressions));
2717 save_stack_p = save_stack;
2719 /* First parse an instruction mnemonic & call i386_operand for the operands.
2720 We assume that the scrubber has arranged it so that line[0] is the valid
2721 start of a (possibly prefixed) mnemonic. */
2723 line = parse_insn (line, mnemonic);
2727 line = parse_operands (line, mnemonic);
2732 /* Now we've parsed the mnemonic into a set of templates, and have the
2733 operands at hand. */
2735 /* All intel opcodes have reversed operands except for "bound" and
2736 "enter". We also don't reverse intersegment "jmp" and "call"
2737 instructions with 2 immediate operands so that the immediate segment
2738 precedes the offset, as it does when in AT&T mode. */
2741 && (strcmp (mnemonic, "bound") != 0)
2742 && (strcmp (mnemonic, "invlpga") != 0)
2743 && !(operand_type_check (i.types[0], imm)
2744 && operand_type_check (i.types[1], imm)))
2747 /* The order of the immediates should be reversed
2748 for 2 immediates extrq and insertq instructions */
2749 if (i.imm_operands == 2
2750 && (strcmp (mnemonic, "extrq") == 0
2751 || strcmp (mnemonic, "insertq") == 0))
2752 swap_2_operands (0, 1);
2757 /* Don't optimize displacement for movabs since it only takes 64bit
2760 && (flag_code != CODE_64BIT
2761 || strcmp (mnemonic, "movabs") != 0))
2764 /* Next, we find a template that matches the given insn,
2765 making sure the overlap of the given operands types is consistent
2766 with the template operand types. */
2768 if (!(t = match_template ()))
2771 if (sse_check != sse_check_none
2772 && !i.tm.opcode_modifier.noavx
2773 && (i.tm.cpu_flags.bitfield.cpusse
2774 || i.tm.cpu_flags.bitfield.cpusse2
2775 || i.tm.cpu_flags.bitfield.cpusse3
2776 || i.tm.cpu_flags.bitfield.cpussse3
2777 || i.tm.cpu_flags.bitfield.cpusse4_1
2778 || i.tm.cpu_flags.bitfield.cpusse4_2))
2780 (sse_check == sse_check_warning
2782 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2785 /* Zap movzx and movsx suffix. The suffix has been set from
2786 "word ptr" or "byte ptr" on the source operand in Intel syntax
2787 or extracted from mnemonic in AT&T syntax. But we'll use
2788 the destination register to choose the suffix for encoding. */
2789 if ((i.tm.base_opcode & ~9) == 0x0fb6)
2791 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2792 there is no suffix, the default will be byte extension. */
2793 if (i.reg_operands != 2
2796 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2801 if (i.tm.opcode_modifier.fwait)
2802 if (!add_prefix (FWAIT_OPCODE))
2805 /* Check string instruction segment overrides. */
2806 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
2808 if (!check_string ())
2810 i.disp_operands = 0;
2813 if (!process_suffix ())
2816 /* Make still unresolved immediate matches conform to size of immediate
2817 given in i.suffix. */
2818 if (!finalize_imm ())
2821 if (i.types[0].bitfield.imm1)
2822 i.imm_operands = 0; /* kludge for shift insns. */
2824 /* We only need to check those implicit registers for instructions
2825 with 3 operands or less. */
2826 if (i.operands <= 3)
2827 for (j = 0; j < i.operands; j++)
2828 if (i.types[j].bitfield.inoutportreg
2829 || i.types[j].bitfield.shiftcount
2830 || i.types[j].bitfield.acc
2831 || i.types[j].bitfield.floatacc)
2834 /* ImmExt should be processed after SSE2AVX. */
2835 if (!i.tm.opcode_modifier.sse2avx
2836 && i.tm.opcode_modifier.immext)
2839 /* For insns with operands there are more diddles to do to the opcode. */
2842 if (!process_operands ())
2845 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
2847 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2848 as_warn (_("translating to `%sp'"), i.tm.name);
2851 if (i.tm.opcode_modifier.vex)
2852 build_vex_prefix (t);
2854 /* Handle conversion of 'int $3' --> special int3 insn. */
2855 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2857 i.tm.base_opcode = INT3_OPCODE;
2861 if ((i.tm.opcode_modifier.jump
2862 || i.tm.opcode_modifier.jumpbyte
2863 || i.tm.opcode_modifier.jumpdword)
2864 && i.op[0].disps->X_op == O_constant)
2866 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2867 the absolute address given by the constant. Since ix86 jumps and
2868 calls are pc relative, we need to generate a reloc. */
2869 i.op[0].disps->X_add_symbol = &abs_symbol;
2870 i.op[0].disps->X_op = O_symbol;
2873 if (i.tm.opcode_modifier.rex64)
2876 /* For 8 bit registers we need an empty rex prefix. Also if the
2877 instruction already has a prefix, we need to convert old
2878 registers to new ones. */
2880 if ((i.types[0].bitfield.reg8
2881 && (i.op[0].regs->reg_flags & RegRex64) != 0)
2882 || (i.types[1].bitfield.reg8
2883 && (i.op[1].regs->reg_flags & RegRex64) != 0)
2884 || ((i.types[0].bitfield.reg8
2885 || i.types[1].bitfield.reg8)
2890 i.rex |= REX_OPCODE;
2891 for (x = 0; x < 2; x++)
2893 /* Look for 8 bit operand that uses old registers. */
2894 if (i.types[x].bitfield.reg8
2895 && (i.op[x].regs->reg_flags & RegRex64) == 0)
2897 /* In case it is "hi" register, give up. */
2898 if (i.op[x].regs->reg_num > 3)
2899 as_bad (_("can't encode register '%s%s' in an "
2900 "instruction requiring REX prefix."),
2901 register_prefix, i.op[x].regs->reg_name);
2903 /* Otherwise it is equivalent to the extended register.
2904 Since the encoding doesn't change this is merely
2905 cosmetic cleanup for debug output. */
2907 i.op[x].regs = i.op[x].regs + 8;
2913 add_prefix (REX_OPCODE | i.rex);
2915 /* We are ready to output the insn. */
2920 parse_insn (char *line, char *mnemonic)
2923 char *token_start = l;
2929 /* Non-zero if we found a prefix only acceptable with string insns. */
2930 const char *expecting_string_instruction = NULL;
2935 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2940 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
2942 as_bad (_("no such instruction: `%s'"), token_start);
2947 if (!is_space_char (*l)
2948 && *l != END_OF_INSN
2950 || (*l != PREFIX_SEPARATOR
2953 as_bad (_("invalid character %s in mnemonic"),
2954 output_invalid (*l));
2957 if (token_start == l)
2959 if (!intel_syntax && *l == PREFIX_SEPARATOR)
2960 as_bad (_("expecting prefix; got nothing"));
2962 as_bad (_("expecting mnemonic; got nothing"));
2966 /* Look up instruction (or prefix) via hash table. */
2967 current_templates = hash_find (op_hash, mnemonic);
2969 if (*l != END_OF_INSN
2970 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2971 && current_templates
2972 && current_templates->start->opcode_modifier.isprefix)
2974 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2976 as_bad ((flag_code != CODE_64BIT
2977 ? _("`%s' is only supported in 64-bit mode")
2978 : _("`%s' is not supported in 64-bit mode")),
2979 current_templates->start->name);
2982 /* If we are in 16-bit mode, do not allow addr16 or data16.
2983 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2984 if ((current_templates->start->opcode_modifier.size16
2985 || current_templates->start->opcode_modifier.size32)
2986 && flag_code != CODE_64BIT
2987 && (current_templates->start->opcode_modifier.size32
2988 ^ (flag_code == CODE_16BIT)))
2990 as_bad (_("redundant %s prefix"),
2991 current_templates->start->name);
2994 /* Add prefix, checking for repeated prefixes. */
2995 switch (add_prefix (current_templates->start->base_opcode))
3000 expecting_string_instruction = current_templates->start->name;
3003 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3010 if (!current_templates)
3012 /* Check if we should swap operand in encoding. */
3013 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3019 current_templates = hash_find (op_hash, mnemonic);
3022 if (!current_templates)
3025 /* See if we can get a match by trimming off a suffix. */
3028 case WORD_MNEM_SUFFIX:
3029 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3030 i.suffix = SHORT_MNEM_SUFFIX;
3032 case BYTE_MNEM_SUFFIX:
3033 case QWORD_MNEM_SUFFIX:
3034 i.suffix = mnem_p[-1];
3036 current_templates = hash_find (op_hash, mnemonic);
3038 case SHORT_MNEM_SUFFIX:
3039 case LONG_MNEM_SUFFIX:
3042 i.suffix = mnem_p[-1];
3044 current_templates = hash_find (op_hash, mnemonic);
3052 if (intel_float_operand (mnemonic) == 1)
3053 i.suffix = SHORT_MNEM_SUFFIX;
3055 i.suffix = LONG_MNEM_SUFFIX;
3057 current_templates = hash_find (op_hash, mnemonic);
3061 if (!current_templates)
3063 as_bad (_("no such instruction: `%s'"), token_start);
3068 if (current_templates->start->opcode_modifier.jump
3069 || current_templates->start->opcode_modifier.jumpbyte)
3071 /* Check for a branch hint. We allow ",pt" and ",pn" for
3072 predict taken and predict not taken respectively.
3073 I'm not sure that branch hints actually do anything on loop
3074 and jcxz insns (JumpByte) for current Pentium4 chips. They
3075 may work in the future and it doesn't hurt to accept them
3077 if (l[0] == ',' && l[1] == 'p')
3081 if (!add_prefix (DS_PREFIX_OPCODE))
3085 else if (l[2] == 'n')
3087 if (!add_prefix (CS_PREFIX_OPCODE))
3093 /* Any other comma loses. */
3096 as_bad (_("invalid character %s in mnemonic"),
3097 output_invalid (*l));
3101 /* Check if instruction is supported on specified architecture. */
3103 for (t = current_templates->start; t < current_templates->end; ++t)
3105 supported |= cpu_flags_match (t);
3106 if (supported == CPU_FLAGS_PERFECT_MATCH)
3110 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3112 as_bad (flag_code == CODE_64BIT
3113 ? _("`%s' is not supported in 64-bit mode")
3114 : _("`%s' is only supported in 64-bit mode"),
3115 current_templates->start->name);
3118 if (supported != CPU_FLAGS_PERFECT_MATCH)
3120 as_bad (_("`%s' is not supported on `%s%s'"),
3121 current_templates->start->name,
3122 cpu_arch_name ? cpu_arch_name : default_arch,
3123 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3128 if (!cpu_arch_flags.bitfield.cpui386
3129 && (flag_code != CODE_16BIT))
3131 as_warn (_("use .code16 to ensure correct addressing mode"));
3134 /* Check for rep/repne without a string instruction. */
3135 if (expecting_string_instruction)
3137 static templates override;
3139 for (t = current_templates->start; t < current_templates->end; ++t)
3140 if (t->opcode_modifier.isstring)
3142 if (t >= current_templates->end)
3144 as_bad (_("expecting string instruction after `%s'"),
3145 expecting_string_instruction);
3148 for (override.start = t; t < current_templates->end; ++t)
3149 if (!t->opcode_modifier.isstring)
3152 current_templates = &override;
3159 parse_operands (char *l, const char *mnemonic)
3163 /* 1 if operand is pending after ','. */
3164 unsigned int expecting_operand = 0;
3166 /* Non-zero if operand parens not balanced. */
3167 unsigned int paren_not_balanced;
3169 while (*l != END_OF_INSN)
3171 /* Skip optional white space before operand. */
3172 if (is_space_char (*l))
3174 if (!is_operand_char (*l) && *l != END_OF_INSN)
3176 as_bad (_("invalid character %s before operand %d"),
3177 output_invalid (*l),
3181 token_start = l; /* after white space */
3182 paren_not_balanced = 0;
3183 while (paren_not_balanced || *l != ',')
3185 if (*l == END_OF_INSN)
3187 if (paren_not_balanced)
3190 as_bad (_("unbalanced parenthesis in operand %d."),
3193 as_bad (_("unbalanced brackets in operand %d."),
3198 break; /* we are done */
3200 else if (!is_operand_char (*l) && !is_space_char (*l))
3202 as_bad (_("invalid character %s in operand %d"),
3203 output_invalid (*l),
3210 ++paren_not_balanced;
3212 --paren_not_balanced;
3217 ++paren_not_balanced;
3219 --paren_not_balanced;
3223 if (l != token_start)
3224 { /* Yes, we've read in another operand. */
3225 unsigned int operand_ok;
3226 this_operand = i.operands++;
3227 i.types[this_operand].bitfield.unspecified = 1;
3228 if (i.operands > MAX_OPERANDS)
3230 as_bad (_("spurious operands; (%d operands/instruction max)"),
3234 /* Now parse operand adding info to 'i' as we go along. */
3235 END_STRING_AND_SAVE (l);
3239 i386_intel_operand (token_start,
3240 intel_float_operand (mnemonic));
3242 operand_ok = i386_att_operand (token_start);
3244 RESTORE_END_STRING (l);
3250 if (expecting_operand)
3252 expecting_operand_after_comma:
3253 as_bad (_("expecting operand after ','; got nothing"));
3258 as_bad (_("expecting operand before ','; got nothing"));
3263 /* Now *l must be either ',' or END_OF_INSN. */
3266 if (*++l == END_OF_INSN)
3268 /* Just skip it, if it's \n complain. */
3269 goto expecting_operand_after_comma;
3271 expecting_operand = 1;
3278 swap_2_operands (int xchg1, int xchg2)
3280 union i386_op temp_op;
3281 i386_operand_type temp_type;
3282 enum bfd_reloc_code_real temp_reloc;
3284 temp_type = i.types[xchg2];
3285 i.types[xchg2] = i.types[xchg1];
3286 i.types[xchg1] = temp_type;
3287 temp_op = i.op[xchg2];
3288 i.op[xchg2] = i.op[xchg1];
3289 i.op[xchg1] = temp_op;
3290 temp_reloc = i.reloc[xchg2];
3291 i.reloc[xchg2] = i.reloc[xchg1];
3292 i.reloc[xchg1] = temp_reloc;
3296 swap_operands (void)
3302 swap_2_operands (1, i.operands - 2);
3305 swap_2_operands (0, i.operands - 1);
3311 if (i.mem_operands == 2)
3313 const seg_entry *temp_seg;
3314 temp_seg = i.seg[0];
3315 i.seg[0] = i.seg[1];
3316 i.seg[1] = temp_seg;
3320 /* Try to ensure constant immediates are represented in the smallest
3325 char guess_suffix = 0;
3329 guess_suffix = i.suffix;
3330 else if (i.reg_operands)
3332 /* Figure out a suffix from the last register operand specified.
3333 We can't do this properly yet, ie. excluding InOutPortReg,
3334 but the following works for instructions with immediates.
3335 In any case, we can't set i.suffix yet. */
3336 for (op = i.operands; --op >= 0;)
3337 if (i.types[op].bitfield.reg8)
3339 guess_suffix = BYTE_MNEM_SUFFIX;
3342 else if (i.types[op].bitfield.reg16)
3344 guess_suffix = WORD_MNEM_SUFFIX;
3347 else if (i.types[op].bitfield.reg32)
3349 guess_suffix = LONG_MNEM_SUFFIX;
3352 else if (i.types[op].bitfield.reg64)
3354 guess_suffix = QWORD_MNEM_SUFFIX;
3358 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3359 guess_suffix = WORD_MNEM_SUFFIX;
3361 for (op = i.operands; --op >= 0;)
3362 if (operand_type_check (i.types[op], imm))
3364 switch (i.op[op].imms->X_op)
3367 /* If a suffix is given, this operand may be shortened. */
3368 switch (guess_suffix)
3370 case LONG_MNEM_SUFFIX:
3371 i.types[op].bitfield.imm32 = 1;
3372 i.types[op].bitfield.imm64 = 1;
3374 case WORD_MNEM_SUFFIX:
3375 i.types[op].bitfield.imm16 = 1;
3376 i.types[op].bitfield.imm32 = 1;
3377 i.types[op].bitfield.imm32s = 1;
3378 i.types[op].bitfield.imm64 = 1;
3380 case BYTE_MNEM_SUFFIX:
3381 i.types[op].bitfield.imm8 = 1;
3382 i.types[op].bitfield.imm8s = 1;
3383 i.types[op].bitfield.imm16 = 1;
3384 i.types[op].bitfield.imm32 = 1;
3385 i.types[op].bitfield.imm32s = 1;
3386 i.types[op].bitfield.imm64 = 1;
3390 /* If this operand is at most 16 bits, convert it
3391 to a signed 16 bit number before trying to see
3392 whether it will fit in an even smaller size.
3393 This allows a 16-bit operand such as $0xffe0 to
3394 be recognised as within Imm8S range. */
3395 if ((i.types[op].bitfield.imm16)
3396 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3398 i.op[op].imms->X_add_number =
3399 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3401 if ((i.types[op].bitfield.imm32)
3402 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3405 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3406 ^ ((offsetT) 1 << 31))
3407 - ((offsetT) 1 << 31));
3410 = operand_type_or (i.types[op],
3411 smallest_imm_type (i.op[op].imms->X_add_number));
3413 /* We must avoid matching of Imm32 templates when 64bit
3414 only immediate is available. */
3415 if (guess_suffix == QWORD_MNEM_SUFFIX)
3416 i.types[op].bitfield.imm32 = 0;
3423 /* Symbols and expressions. */
3425 /* Convert symbolic operand to proper sizes for matching, but don't
3426 prevent matching a set of insns that only supports sizes other
3427 than those matching the insn suffix. */
3429 i386_operand_type mask, allowed;
3432 operand_type_set (&mask, 0);
3433 operand_type_set (&allowed, 0);
3435 for (t = current_templates->start;
3436 t < current_templates->end;
3438 allowed = operand_type_or (allowed,
3439 t->operand_types[op]);
3440 switch (guess_suffix)
3442 case QWORD_MNEM_SUFFIX:
3443 mask.bitfield.imm64 = 1;
3444 mask.bitfield.imm32s = 1;
3446 case LONG_MNEM_SUFFIX:
3447 mask.bitfield.imm32 = 1;
3449 case WORD_MNEM_SUFFIX:
3450 mask.bitfield.imm16 = 1;
3452 case BYTE_MNEM_SUFFIX:
3453 mask.bitfield.imm8 = 1;
3458 allowed = operand_type_and (mask, allowed);
3459 if (!operand_type_all_zero (&allowed))
3460 i.types[op] = operand_type_and (i.types[op], mask);
3467 /* Try to use the smallest displacement type too. */
3469 optimize_disp (void)
3473 for (op = i.operands; --op >= 0;)
3474 if (operand_type_check (i.types[op], disp))
3476 if (i.op[op].disps->X_op == O_constant)
3478 offsetT disp = i.op[op].disps->X_add_number;
3480 if (i.types[op].bitfield.disp16
3481 && (disp & ~(offsetT) 0xffff) == 0)
3483 /* If this operand is at most 16 bits, convert
3484 to a signed 16 bit number and don't use 64bit
3486 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
3487 i.types[op].bitfield.disp64 = 0;
3489 if (i.types[op].bitfield.disp32
3490 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3492 /* If this operand is at most 32 bits, convert
3493 to a signed 32 bit number and don't use 64bit
3495 disp &= (((offsetT) 2 << 31) - 1);
3496 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3497 i.types[op].bitfield.disp64 = 0;
3499 if (!disp && i.types[op].bitfield.baseindex)
3501 i.types[op].bitfield.disp8 = 0;
3502 i.types[op].bitfield.disp16 = 0;
3503 i.types[op].bitfield.disp32 = 0;
3504 i.types[op].bitfield.disp32s = 0;
3505 i.types[op].bitfield.disp64 = 0;
3509 else if (flag_code == CODE_64BIT)
3511 if (fits_in_signed_long (disp))
3513 i.types[op].bitfield.disp64 = 0;
3514 i.types[op].bitfield.disp32s = 1;
3516 if (fits_in_unsigned_long (disp))
3517 i.types[op].bitfield.disp32 = 1;
3519 if ((i.types[op].bitfield.disp32
3520 || i.types[op].bitfield.disp32s
3521 || i.types[op].bitfield.disp16)
3522 && fits_in_signed_byte (disp))
3523 i.types[op].bitfield.disp8 = 1;
3525 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3526 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3528 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3529 i.op[op].disps, 0, i.reloc[op]);
3530 i.types[op].bitfield.disp8 = 0;
3531 i.types[op].bitfield.disp16 = 0;
3532 i.types[op].bitfield.disp32 = 0;
3533 i.types[op].bitfield.disp32s = 0;
3534 i.types[op].bitfield.disp64 = 0;
3537 /* We only support 64bit displacement on constants. */
3538 i.types[op].bitfield.disp64 = 0;
3542 static const template *
3543 match_template (void)
3545 /* Points to template once we've found it. */
3547 i386_operand_type overlap0, overlap1, overlap2, overlap3;
3548 i386_operand_type overlap4;
3549 unsigned int found_reverse_match;
3550 i386_opcode_modifier suffix_check;
3551 i386_operand_type operand_types [MAX_OPERANDS];
3552 int addr_prefix_disp;
3554 unsigned int found_cpu_match;
3555 unsigned int check_register;
3557 #if MAX_OPERANDS != 5
3558 # error "MAX_OPERANDS must be 5."
3561 found_reverse_match = 0;
3562 addr_prefix_disp = -1;
3564 memset (&suffix_check, 0, sizeof (suffix_check));
3565 if (i.suffix == BYTE_MNEM_SUFFIX)
3566 suffix_check.no_bsuf = 1;
3567 else if (i.suffix == WORD_MNEM_SUFFIX)
3568 suffix_check.no_wsuf = 1;
3569 else if (i.suffix == SHORT_MNEM_SUFFIX)
3570 suffix_check.no_ssuf = 1;
3571 else if (i.suffix == LONG_MNEM_SUFFIX)
3572 suffix_check.no_lsuf = 1;
3573 else if (i.suffix == QWORD_MNEM_SUFFIX)
3574 suffix_check.no_qsuf = 1;
3575 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3576 suffix_check.no_ldsuf = 1;
3578 for (t = current_templates->start; t < current_templates->end; t++)
3580 addr_prefix_disp = -1;
3582 /* Must have right number of operands. */
3583 if (i.operands != t->operands)
3586 /* Check processor support. */
3587 found_cpu_match = (cpu_flags_match (t)
3588 == CPU_FLAGS_PERFECT_MATCH);
3589 if (!found_cpu_match)
3592 /* Check old gcc support. */
3593 if (!old_gcc && t->opcode_modifier.oldgcc)
3596 /* Check AT&T mnemonic. */
3597 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
3600 /* Check AT&T syntax Intel syntax. */
3601 if ((intel_syntax && t->opcode_modifier.attsyntax)
3602 || (!intel_syntax && t->opcode_modifier.intelsyntax))
3605 /* Check the suffix, except for some instructions in intel mode. */
3606 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3607 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3608 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3609 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3610 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3611 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3612 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
3615 if (!operand_size_match (t))
3618 for (j = 0; j < MAX_OPERANDS; j++)
3619 operand_types[j] = t->operand_types[j];
3621 /* In general, don't allow 64-bit operands in 32-bit mode. */
3622 if (i.suffix == QWORD_MNEM_SUFFIX
3623 && flag_code != CODE_64BIT
3625 ? (!t->opcode_modifier.ignoresize
3626 && !intel_float_operand (t->name))
3627 : intel_float_operand (t->name) != 2)
3628 && ((!operand_types[0].bitfield.regmmx
3629 && !operand_types[0].bitfield.regxmm
3630 && !operand_types[0].bitfield.regymm)
3631 || (!operand_types[t->operands > 1].bitfield.regmmx
3632 && !!operand_types[t->operands > 1].bitfield.regxmm
3633 && !!operand_types[t->operands > 1].bitfield.regymm))
3634 && (t->base_opcode != 0x0fc7
3635 || t->extension_opcode != 1 /* cmpxchg8b */))
3638 /* In general, don't allow 32-bit operands on pre-386. */
3639 else if (i.suffix == LONG_MNEM_SUFFIX
3640 && !cpu_arch_flags.bitfield.cpui386
3642 ? (!t->opcode_modifier.ignoresize
3643 && !intel_float_operand (t->name))
3644 : intel_float_operand (t->name) != 2)
3645 && ((!operand_types[0].bitfield.regmmx
3646 && !operand_types[0].bitfield.regxmm)
3647 || (!operand_types[t->operands > 1].bitfield.regmmx
3648 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3651 /* Do not verify operands when there are none. */
3655 /* We've found a match; break out of loop. */
3659 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3660 into Disp32/Disp16/Disp32 operand. */
3661 if (i.prefix[ADDR_PREFIX] != 0)
3663 /* There should be only one Disp operand. */
3667 for (j = 0; j < MAX_OPERANDS; j++)
3669 if (operand_types[j].bitfield.disp16)
3671 addr_prefix_disp = j;
3672 operand_types[j].bitfield.disp32 = 1;
3673 operand_types[j].bitfield.disp16 = 0;
3679 for (j = 0; j < MAX_OPERANDS; j++)
3681 if (operand_types[j].bitfield.disp32)
3683 addr_prefix_disp = j;
3684 operand_types[j].bitfield.disp32 = 0;
3685 operand_types[j].bitfield.disp16 = 1;
3691 for (j = 0; j < MAX_OPERANDS; j++)
3693 if (operand_types[j].bitfield.disp64)
3695 addr_prefix_disp = j;
3696 operand_types[j].bitfield.disp64 = 0;
3697 operand_types[j].bitfield.disp32 = 1;
3705 /* We check register size only if size of operands can be
3706 encoded the canonical way. */
3707 check_register = t->opcode_modifier.w;
3708 overlap0 = operand_type_and (i.types[0], operand_types[0]);
3709 switch (t->operands)
3712 if (!operand_type_match (overlap0, i.types[0]))
3716 /* xchg %eax, %eax is a special case. It is an aliase for nop
3717 only in 32bit mode and we can use opcode 0x90. In 64bit
3718 mode, we can't use 0x90 for xchg %eax, %eax since it should
3719 zero-extend %eax to %rax. */
3720 if (flag_code == CODE_64BIT
3721 && t->base_opcode == 0x90
3722 && operand_type_equal (&i.types [0], &acc32)
3723 && operand_type_equal (&i.types [1], &acc32))
3727 /* If we swap operand in encoding, we either match
3728 the next one or reverse direction of operands. */
3729 if (t->opcode_modifier.s)
3731 else if (t->opcode_modifier.d)
3736 /* If we swap operand in encoding, we match the next one. */
3737 if (i.swap_operand && t->opcode_modifier.s)
3741 overlap1 = operand_type_and (i.types[1], operand_types[1]);
3742 if (!operand_type_match (overlap0, i.types[0])
3743 || !operand_type_match (overlap1, i.types[1])
3745 && !operand_type_register_match (overlap0, i.types[0],
3747 overlap1, i.types[1],
3750 /* Check if other direction is valid ... */
3751 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
3755 /* Try reversing direction of operands. */
3756 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3757 overlap1 = operand_type_and (i.types[1], operand_types[0]);
3758 if (!operand_type_match (overlap0, i.types[0])
3759 || !operand_type_match (overlap1, i.types[1])
3761 && !operand_type_register_match (overlap0,
3768 /* Does not match either direction. */
3771 /* found_reverse_match holds which of D or FloatDR
3773 if (t->opcode_modifier.d)
3774 found_reverse_match = Opcode_D;
3775 else if (t->opcode_modifier.floatd)
3776 found_reverse_match = Opcode_FloatD;
3778 found_reverse_match = 0;
3779 if (t->opcode_modifier.floatr)
3780 found_reverse_match |= Opcode_FloatR;
3784 /* Found a forward 2 operand match here. */
3785 switch (t->operands)
3788 overlap4 = operand_type_and (i.types[4],
3791 overlap3 = operand_type_and (i.types[3],
3794 overlap2 = operand_type_and (i.types[2],
3799 switch (t->operands)
3802 if (!operand_type_match (overlap4, i.types[4])
3803 || !operand_type_register_match (overlap3,
3811 if (!operand_type_match (overlap3, i.types[3])
3813 && !operand_type_register_match (overlap2,
3821 /* Here we make use of the fact that there are no
3822 reverse match 3 operand instructions, and all 3
3823 operand instructions only need to be checked for
3824 register consistency between operands 2 and 3. */
3825 if (!operand_type_match (overlap2, i.types[2])
3827 && !operand_type_register_match (overlap1,
3837 /* Found either forward/reverse 2, 3 or 4 operand match here:
3838 slip through to break. */
3840 if (!found_cpu_match)
3842 found_reverse_match = 0;
3846 /* We've found a match; break out of loop. */
3850 if (t == current_templates->end)
3852 /* We found no match. */
3854 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3855 current_templates->start->name);
3857 as_bad (_("suffix or operands invalid for `%s'"),
3858 current_templates->start->name);
3862 if (!quiet_warnings)
3865 && (i.types[0].bitfield.jumpabsolute
3866 != operand_types[0].bitfield.jumpabsolute))
3868 as_warn (_("indirect %s without `*'"), t->name);
3871 if (t->opcode_modifier.isprefix
3872 && t->opcode_modifier.ignoresize)
3874 /* Warn them that a data or address size prefix doesn't
3875 affect assembly of the next line of code. */
3876 as_warn (_("stand-alone `%s' prefix"), t->name);
3880 /* Copy the template we found. */
3883 if (addr_prefix_disp != -1)
3884 i.tm.operand_types[addr_prefix_disp]
3885 = operand_types[addr_prefix_disp];
3887 if (found_reverse_match)
3889 /* If we found a reverse match we must alter the opcode
3890 direction bit. found_reverse_match holds bits to change
3891 (different for int & float insns). */
3893 i.tm.base_opcode ^= found_reverse_match;
3895 i.tm.operand_types[0] = operand_types[1];
3896 i.tm.operand_types[1] = operand_types[0];
3905 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3906 if (i.tm.operand_types[mem_op].bitfield.esseg)
3908 if (i.seg[0] != NULL && i.seg[0] != &es)
3910 as_bad (_("`%s' operand %d must use `%ses' segment"),
3916 /* There's only ever one segment override allowed per instruction.
3917 This instruction possibly has a legal segment override on the
3918 second operand, so copy the segment to where non-string
3919 instructions store it, allowing common code. */
3920 i.seg[0] = i.seg[1];
3922 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
3924 if (i.seg[1] != NULL && i.seg[1] != &es)
3926 as_bad (_("`%s' operand %d must use `%ses' segment"),
3937 process_suffix (void)
3939 /* If matched instruction specifies an explicit instruction mnemonic
3941 if (i.tm.opcode_modifier.size16)
3942 i.suffix = WORD_MNEM_SUFFIX;
3943 else if (i.tm.opcode_modifier.size32)
3944 i.suffix = LONG_MNEM_SUFFIX;
3945 else if (i.tm.opcode_modifier.size64)
3946 i.suffix = QWORD_MNEM_SUFFIX;
3947 else if (i.reg_operands)
3949 /* If there's no instruction mnemonic suffix we try to invent one
3950 based on register operands. */
3953 /* We take i.suffix from the last register operand specified,
3954 Destination register type is more significant than source
3955 register type. crc32 in SSE4.2 prefers source register
3957 if (i.tm.base_opcode == 0xf20f38f1)
3959 if (i.types[0].bitfield.reg16)
3960 i.suffix = WORD_MNEM_SUFFIX;
3961 else if (i.types[0].bitfield.reg32)
3962 i.suffix = LONG_MNEM_SUFFIX;
3963 else if (i.types[0].bitfield.reg64)
3964 i.suffix = QWORD_MNEM_SUFFIX;
3966 else if (i.tm.base_opcode == 0xf20f38f0)
3968 if (i.types[0].bitfield.reg8)
3969 i.suffix = BYTE_MNEM_SUFFIX;
3976 if (i.tm.base_opcode == 0xf20f38f1
3977 || i.tm.base_opcode == 0xf20f38f0)
3979 /* We have to know the operand size for crc32. */
3980 as_bad (_("ambiguous memory operand size for `%s`"),
3985 for (op = i.operands; --op >= 0;)
3986 if (!i.tm.operand_types[op].bitfield.inoutportreg)
3988 if (i.types[op].bitfield.reg8)
3990 i.suffix = BYTE_MNEM_SUFFIX;
3993 else if (i.types[op].bitfield.reg16)
3995 i.suffix = WORD_MNEM_SUFFIX;
3998 else if (i.types[op].bitfield.reg32)
4000 i.suffix = LONG_MNEM_SUFFIX;
4003 else if (i.types[op].bitfield.reg64)
4005 i.suffix = QWORD_MNEM_SUFFIX;
4011 else if (i.suffix == BYTE_MNEM_SUFFIX)
4013 if (!check_byte_reg ())
4016 else if (i.suffix == LONG_MNEM_SUFFIX)
4018 if (!check_long_reg ())
4021 else if (i.suffix == QWORD_MNEM_SUFFIX)
4024 && i.tm.opcode_modifier.ignoresize
4025 && i.tm.opcode_modifier.no_qsuf)
4027 else if (!check_qword_reg ())
4030 else if (i.suffix == WORD_MNEM_SUFFIX)
4032 if (!check_word_reg ())
4035 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4036 || i.suffix == YMMWORD_MNEM_SUFFIX)
4038 /* Skip if the instruction has x/y suffix. match_template
4039 should check if it is a valid suffix. */
4041 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
4042 /* Do nothing if the instruction is going to ignore the prefix. */
4047 else if (i.tm.opcode_modifier.defaultsize
4049 /* exclude fldenv/frstor/fsave/fstenv */
4050 && i.tm.opcode_modifier.no_ssuf)
4052 i.suffix = stackop_size;
4054 else if (intel_syntax
4056 && (i.tm.operand_types[0].bitfield.jumpabsolute
4057 || i.tm.opcode_modifier.jumpbyte
4058 || i.tm.opcode_modifier.jumpintersegment
4059 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4060 && i.tm.extension_opcode <= 3)))
4065 if (!i.tm.opcode_modifier.no_qsuf)
4067 i.suffix = QWORD_MNEM_SUFFIX;
4071 if (!i.tm.opcode_modifier.no_lsuf)
4072 i.suffix = LONG_MNEM_SUFFIX;
4075 if (!i.tm.opcode_modifier.no_wsuf)
4076 i.suffix = WORD_MNEM_SUFFIX;
4085 if (i.tm.opcode_modifier.w)
4087 as_bad (_("no instruction mnemonic suffix given and "
4088 "no register operands; can't size instruction"));
4094 unsigned int suffixes;
4096 suffixes = !i.tm.opcode_modifier.no_bsuf;
4097 if (!i.tm.opcode_modifier.no_wsuf)
4099 if (!i.tm.opcode_modifier.no_lsuf)
4101 if (!i.tm.opcode_modifier.no_ldsuf)
4103 if (!i.tm.opcode_modifier.no_ssuf)
4105 if (!i.tm.opcode_modifier.no_qsuf)
4108 /* There are more than suffix matches. */
4109 if (i.tm.opcode_modifier.w
4110 || ((suffixes & (suffixes - 1))
4111 && !i.tm.opcode_modifier.defaultsize
4112 && !i.tm.opcode_modifier.ignoresize))
4114 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4120 /* Change the opcode based on the operand size given by i.suffix;
4121 We don't need to change things for byte insns. */
4124 && i.suffix != BYTE_MNEM_SUFFIX
4125 && i.suffix != XMMWORD_MNEM_SUFFIX
4126 && i.suffix != YMMWORD_MNEM_SUFFIX)
4128 /* It's not a byte, select word/dword operation. */
4129 if (i.tm.opcode_modifier.w)
4131 if (i.tm.opcode_modifier.shortform)
4132 i.tm.base_opcode |= 8;
4134 i.tm.base_opcode |= 1;
4137 /* Now select between word & dword operations via the operand
4138 size prefix, except for instructions that will ignore this
4140 if (i.tm.opcode_modifier.addrprefixop0)
4142 /* The address size override prefix changes the size of the
4144 if ((flag_code == CODE_32BIT
4145 && i.op->regs[0].reg_type.bitfield.reg16)
4146 || (flag_code != CODE_32BIT
4147 && i.op->regs[0].reg_type.bitfield.reg32))
4148 if (!add_prefix (ADDR_PREFIX_OPCODE))
4151 else if (i.suffix != QWORD_MNEM_SUFFIX
4152 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
4153 && !i.tm.opcode_modifier.ignoresize
4154 && !i.tm.opcode_modifier.floatmf
4155 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4156 || (flag_code == CODE_64BIT
4157 && i.tm.opcode_modifier.jumpbyte)))
4159 unsigned int prefix = DATA_PREFIX_OPCODE;
4161 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
4162 prefix = ADDR_PREFIX_OPCODE;
4164 if (!add_prefix (prefix))
4168 /* Set mode64 for an operand. */
4169 if (i.suffix == QWORD_MNEM_SUFFIX
4170 && flag_code == CODE_64BIT
4171 && !i.tm.opcode_modifier.norex64)
4173 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4174 need rex64. cmpxchg8b is also a special case. */
4175 if (! (i.operands == 2
4176 && i.tm.base_opcode == 0x90
4177 && i.tm.extension_opcode == None
4178 && operand_type_equal (&i.types [0], &acc64)
4179 && operand_type_equal (&i.types [1], &acc64))
4180 && ! (i.operands == 1
4181 && i.tm.base_opcode == 0xfc7
4182 && i.tm.extension_opcode == 1
4183 && !operand_type_check (i.types [0], reg)
4184 && operand_type_check (i.types [0], anymem)))
4188 /* Size floating point instruction. */
4189 if (i.suffix == LONG_MNEM_SUFFIX)
4190 if (i.tm.opcode_modifier.floatmf)
4191 i.tm.base_opcode ^= 4;
4198 check_byte_reg (void)
4202 for (op = i.operands; --op >= 0;)
4204 /* If this is an eight bit register, it's OK. If it's the 16 or
4205 32 bit version of an eight bit register, we will just use the
4206 low portion, and that's OK too. */
4207 if (i.types[op].bitfield.reg8)
4210 /* Don't generate this warning if not needed. */
4211 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
4214 /* crc32 doesn't generate this warning. */
4215 if (i.tm.base_opcode == 0xf20f38f0)
4218 if ((i.types[op].bitfield.reg16
4219 || i.types[op].bitfield.reg32
4220 || i.types[op].bitfield.reg64)
4221 && i.op[op].regs->reg_num < 4)
4223 /* Prohibit these changes in the 64bit mode, since the
4224 lowering is more complicated. */
4225 if (flag_code == CODE_64BIT
4226 && !i.tm.operand_types[op].bitfield.inoutportreg)
4228 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4229 register_prefix, i.op[op].regs->reg_name,
4233 #if REGISTER_WARNINGS
4235 && !i.tm.operand_types[op].bitfield.inoutportreg)
4236 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4238 (i.op[op].regs + (i.types[op].bitfield.reg16
4239 ? REGNAM_AL - REGNAM_AX
4240 : REGNAM_AL - REGNAM_EAX))->reg_name,
4242 i.op[op].regs->reg_name,
4247 /* Any other register is bad. */
4248 if (i.types[op].bitfield.reg16
4249 || i.types[op].bitfield.reg32
4250 || i.types[op].bitfield.reg64
4251 || i.types[op].bitfield.regmmx
4252 || i.types[op].bitfield.regxmm
4253 || i.types[op].bitfield.regymm
4254 || i.types[op].bitfield.sreg2
4255 || i.types[op].bitfield.sreg3
4256 || i.types[op].bitfield.control
4257 || i.types[op].bitfield.debug
4258 || i.types[op].bitfield.test
4259 || i.types[op].bitfield.floatreg
4260 || i.types[op].bitfield.floatacc)
4262 as_bad (_("`%s%s' not allowed with `%s%c'"),
4264 i.op[op].regs->reg_name,
4274 check_long_reg (void)
4278 for (op = i.operands; --op >= 0;)
4279 /* Reject eight bit registers, except where the template requires
4280 them. (eg. movzb) */
4281 if (i.types[op].bitfield.reg8
4282 && (i.tm.operand_types[op].bitfield.reg16
4283 || i.tm.operand_types[op].bitfield.reg32
4284 || i.tm.operand_types[op].bitfield.acc))
4286 as_bad (_("`%s%s' not allowed with `%s%c'"),
4288 i.op[op].regs->reg_name,
4293 /* Warn if the e prefix on a general reg is missing. */
4294 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4295 && i.types[op].bitfield.reg16
4296 && (i.tm.operand_types[op].bitfield.reg32
4297 || i.tm.operand_types[op].bitfield.acc))
4299 /* Prohibit these changes in the 64bit mode, since the
4300 lowering is more complicated. */
4301 if (flag_code == CODE_64BIT)
4303 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4304 register_prefix, i.op[op].regs->reg_name,
4308 #if REGISTER_WARNINGS
4310 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4312 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
4314 i.op[op].regs->reg_name,
4318 /* Warn if the r prefix on a general reg is missing. */
4319 else if (i.types[op].bitfield.reg64
4320 && (i.tm.operand_types[op].bitfield.reg32
4321 || i.tm.operand_types[op].bitfield.acc))
4324 && i.tm.opcode_modifier.toqword
4325 && !i.types[0].bitfield.regxmm)
4327 /* Convert to QWORD. We want REX byte. */
4328 i.suffix = QWORD_MNEM_SUFFIX;
4332 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4333 register_prefix, i.op[op].regs->reg_name,
4342 check_qword_reg (void)
4346 for (op = i.operands; --op >= 0; )
4347 /* Reject eight bit registers, except where the template requires
4348 them. (eg. movzb) */
4349 if (i.types[op].bitfield.reg8
4350 && (i.tm.operand_types[op].bitfield.reg16
4351 || i.tm.operand_types[op].bitfield.reg32
4352 || i.tm.operand_types[op].bitfield.acc))
4354 as_bad (_("`%s%s' not allowed with `%s%c'"),
4356 i.op[op].regs->reg_name,
4361 /* Warn if the e prefix on a general reg is missing. */
4362 else if ((i.types[op].bitfield.reg16
4363 || i.types[op].bitfield.reg32)
4364 && (i.tm.operand_types[op].bitfield.reg32
4365 || i.tm.operand_types[op].bitfield.acc))
4367 /* Prohibit these changes in the 64bit mode, since the
4368 lowering is more complicated. */
4370 && i.tm.opcode_modifier.todword
4371 && !i.types[0].bitfield.regxmm)
4373 /* Convert to DWORD. We don't want REX byte. */
4374 i.suffix = LONG_MNEM_SUFFIX;
4378 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4379 register_prefix, i.op[op].regs->reg_name,
4388 check_word_reg (void)
4391 for (op = i.operands; --op >= 0;)
4392 /* Reject eight bit registers, except where the template requires
4393 them. (eg. movzb) */
4394 if (i.types[op].bitfield.reg8
4395 && (i.tm.operand_types[op].bitfield.reg16
4396 || i.tm.operand_types[op].bitfield.reg32
4397 || i.tm.operand_types[op].bitfield.acc))
4399 as_bad (_("`%s%s' not allowed with `%s%c'"),
4401 i.op[op].regs->reg_name,
4406 /* Warn if the e prefix on a general reg is present. */
4407 else if ((!quiet_warnings || flag_code == CODE_64BIT)
4408 && i.types[op].bitfield.reg32
4409 && (i.tm.operand_types[op].bitfield.reg16
4410 || i.tm.operand_types[op].bitfield.acc))
4412 /* Prohibit these changes in the 64bit mode, since the
4413 lowering is more complicated. */
4414 if (flag_code == CODE_64BIT)
4416 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4417 register_prefix, i.op[op].regs->reg_name,
4422 #if REGISTER_WARNINGS
4423 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4425 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
4427 i.op[op].regs->reg_name,
4435 update_imm (unsigned int j)
4437 i386_operand_type overlap;
4439 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
4440 if ((overlap.bitfield.imm8
4441 || overlap.bitfield.imm8s
4442 || overlap.bitfield.imm16
4443 || overlap.bitfield.imm32
4444 || overlap.bitfield.imm32s
4445 || overlap.bitfield.imm64)
4446 && !operand_type_equal (&overlap, &imm8)
4447 && !operand_type_equal (&overlap, &imm8s)
4448 && !operand_type_equal (&overlap, &imm16)
4449 && !operand_type_equal (&overlap, &imm32)
4450 && !operand_type_equal (&overlap, &imm32s)
4451 && !operand_type_equal (&overlap, &imm64))
4455 i386_operand_type temp;
4457 operand_type_set (&temp, 0);
4458 if (i.suffix == BYTE_MNEM_SUFFIX)
4460 temp.bitfield.imm8 = overlap.bitfield.imm8;
4461 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4463 else if (i.suffix == WORD_MNEM_SUFFIX)
4464 temp.bitfield.imm16 = overlap.bitfield.imm16;
4465 else if (i.suffix == QWORD_MNEM_SUFFIX)
4467 temp.bitfield.imm64 = overlap.bitfield.imm64;
4468 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4471 temp.bitfield.imm32 = overlap.bitfield.imm32;
4474 else if (operand_type_equal (&overlap, &imm16_32_32s)
4475 || operand_type_equal (&overlap, &imm16_32)
4476 || operand_type_equal (&overlap, &imm16_32s))
4478 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4483 if (!operand_type_equal (&overlap, &imm8)
4484 && !operand_type_equal (&overlap, &imm8s)
4485 && !operand_type_equal (&overlap, &imm16)
4486 && !operand_type_equal (&overlap, &imm32)
4487 && !operand_type_equal (&overlap, &imm32s)
4488 && !operand_type_equal (&overlap, &imm64))
4490 as_bad (_("no instruction mnemonic suffix given; "
4491 "can't determine immediate size"));
4495 i.types[j] = overlap;
4505 for (j = 0; j < 2; j++)
4506 if (update_imm (j) == 0)
4509 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
4510 gas_assert (operand_type_check (i.types[2], imm) == 0);
4516 bad_implicit_operand (int xmm)
4518 const char *reg = xmm ? "xmm0" : "ymm0";
4520 as_bad (_("the last operand of `%s' must be `%s%s'"),
4521 i.tm.name, register_prefix, reg);
4523 as_bad (_("the first operand of `%s' must be `%s%s'"),
4524 i.tm.name, register_prefix, reg);
4529 process_operands (void)
4531 /* Default segment register this instruction will use for memory
4532 accesses. 0 means unknown. This is only for optimizing out
4533 unnecessary segment overrides. */
4534 const seg_entry *default_seg = 0;
4536 if (i.tm.opcode_modifier.sse2avx
4537 && (i.tm.opcode_modifier.vexnds
4538 || i.tm.opcode_modifier.vexndd))
4540 unsigned int dup = i.operands;
4541 unsigned int dest = dup - 1;
4544 /* The destination must be an xmm register. */
4545 gas_assert (i.reg_operands
4546 && MAX_OPERANDS > dup
4547 && operand_type_equal (&i.types[dest], ®xmm));
4549 if (i.tm.opcode_modifier.firstxmm0)
4551 /* The first operand is implicit and must be xmm0. */
4552 gas_assert (operand_type_equal (&i.types[0], ®xmm));
4553 if (i.op[0].regs->reg_num != 0)
4554 return bad_implicit_operand (1);
4556 if (i.tm.opcode_modifier.vex3sources)
4558 /* Keep xmm0 for instructions with VEX prefix and 3
4564 /* We remove the first xmm0 and keep the number of
4565 operands unchanged, which in fact duplicates the
4567 for (j = 1; j < i.operands; j++)
4569 i.op[j - 1] = i.op[j];
4570 i.types[j - 1] = i.types[j];
4571 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4575 else if (i.tm.opcode_modifier.implicit1stxmm0)
4577 gas_assert ((MAX_OPERANDS - 1) > dup
4578 && i.tm.opcode_modifier.vex3sources);
4580 /* Add the implicit xmm0 for instructions with VEX prefix
4582 for (j = i.operands; j > 0; j--)
4584 i.op[j] = i.op[j - 1];
4585 i.types[j] = i.types[j - 1];
4586 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4589 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4590 i.types[0] = regxmm;
4591 i.tm.operand_types[0] = regxmm;
4594 i.reg_operands += 2;
4599 i.op[dup] = i.op[dest];
4600 i.types[dup] = i.types[dest];
4601 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4610 i.op[dup] = i.op[dest];
4611 i.types[dup] = i.types[dest];
4612 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4615 if (i.tm.opcode_modifier.immext)
4618 else if (i.tm.opcode_modifier.firstxmm0)
4622 /* The first operand is implicit and must be xmm0/ymm0. */
4623 gas_assert (i.reg_operands
4624 && (operand_type_equal (&i.types[0], ®xmm)
4625 || operand_type_equal (&i.types[0], ®ymm)));
4626 if (i.op[0].regs->reg_num != 0)
4627 return bad_implicit_operand (i.types[0].bitfield.regxmm);
4629 for (j = 1; j < i.operands; j++)
4631 i.op[j - 1] = i.op[j];
4632 i.types[j - 1] = i.types[j];
4634 /* We need to adjust fields in i.tm since they are used by
4635 build_modrm_byte. */
4636 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4643 else if (i.tm.opcode_modifier.regkludge)
4645 /* The imul $imm, %reg instruction is converted into
4646 imul $imm, %reg, %reg, and the clr %reg instruction
4647 is converted into xor %reg, %reg. */
4649 unsigned int first_reg_op;
4651 if (operand_type_check (i.types[0], reg))
4655 /* Pretend we saw the extra register operand. */
4656 gas_assert (i.reg_operands == 1
4657 && i.op[first_reg_op + 1].regs == 0);
4658 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4659 i.types[first_reg_op + 1] = i.types[first_reg_op];
4664 if (i.tm.opcode_modifier.shortform)
4666 if (i.types[0].bitfield.sreg2
4667 || i.types[0].bitfield.sreg3)
4669 if (i.tm.base_opcode == POP_SEG_SHORT
4670 && i.op[0].regs->reg_num == 1)
4672 as_bad (_("you can't `pop %scs'"), register_prefix);
4675 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4676 if ((i.op[0].regs->reg_flags & RegRex) != 0)
4681 /* The register or float register operand is in operand
4685 if (i.types[0].bitfield.floatreg
4686 || operand_type_check (i.types[0], reg))
4690 /* Register goes in low 3 bits of opcode. */
4691 i.tm.base_opcode |= i.op[op].regs->reg_num;
4692 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4694 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
4696 /* Warn about some common errors, but press on regardless.
4697 The first case can be generated by gcc (<= 2.8.1). */
4698 if (i.operands == 2)
4700 /* Reversed arguments on faddp, fsubp, etc. */
4701 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4702 register_prefix, i.op[!intel_syntax].regs->reg_name,
4703 register_prefix, i.op[intel_syntax].regs->reg_name);
4707 /* Extraneous `l' suffix on fp insn. */
4708 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4709 register_prefix, i.op[0].regs->reg_name);
4714 else if (i.tm.opcode_modifier.modrm)
4716 /* The opcode is completed (modulo i.tm.extension_opcode which
4717 must be put into the modrm byte). Now, we make the modrm and
4718 index base bytes based on all the info we've collected. */
4720 default_seg = build_modrm_byte ();
4722 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
4726 else if (i.tm.opcode_modifier.isstring)
4728 /* For the string instructions that allow a segment override
4729 on one of their operands, the default segment is ds. */
4733 if (i.tm.base_opcode == 0x8d /* lea */
4736 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
4738 /* If a segment was explicitly specified, and the specified segment
4739 is not the default, use an opcode prefix to select it. If we
4740 never figured out what the default segment is, then default_seg
4741 will be zero at this point, and the specified segment prefix will
4743 if ((i.seg[0]) && (i.seg[0] != default_seg))
4745 if (!add_prefix (i.seg[0]->seg_prefix))
4751 static const seg_entry *
4752 build_modrm_byte (void)
4754 const seg_entry *default_seg = 0;
4755 unsigned int source, dest;
4758 /* The first operand of instructions with VEX prefix and 3 sources
4759 must be VEX_Imm4. */
4760 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4763 unsigned int nds, reg;
4765 if (i.tm.opcode_modifier.veximmext
4766 && i.tm.opcode_modifier.immext)
4768 dest = i.operands - 2;
4769 gas_assert (dest == 3);
4772 dest = i.operands - 1;
4775 /* This instruction must have 4 register operands
4776 or 3 register operands plus 1 memory operand.
4777 It must have VexNDS and VexImmExt. */
4778 gas_assert ((i.reg_operands == 4
4779 || (i.reg_operands == 3 && i.mem_operands == 1))
4780 && i.tm.opcode_modifier.vexnds
4781 && i.tm.opcode_modifier.veximmext
4782 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
4783 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)));
4785 /* Generate an 8bit immediate operand to encode the register
4787 expressionS *exp = &im_expressions[i.imm_operands++];
4788 i.op[i.operands].imms = exp;
4789 i.types[i.operands] = imm8;
4791 /* If VexW1 is set, the first operand is the source and
4792 the second operand is encoded in the immediate operand. */
4793 if (i.tm.opcode_modifier.vexw1)
4803 /* FMA4 swaps REG and NDS. */
4804 if (i.tm.cpu_flags.bitfield.cpufma4)
4811 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], ®xmm)
4812 || operand_type_equal (&i.tm.operand_types[reg],
4814 && (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
4815 || operand_type_equal (&i.tm.operand_types[nds],
4817 exp->X_op = O_constant;
4819 = ((i.op[reg].regs->reg_num
4820 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
4821 i.vex.register_specifier = i.op[nds].regs;
4826 /* i.reg_operands MUST be the number of real register operands;
4827 implicit registers do not count. If there are 3 register
4828 operands, it must be a instruction with VexNDS. For a
4829 instruction with VexNDD, the destination register is encoded
4830 in VEX prefix. If there are 4 register operands, it must be
4831 a instruction with VEX prefix and 3 sources. */
4832 if (i.mem_operands == 0
4833 && ((i.reg_operands == 2
4834 && !i.tm.opcode_modifier.vexndd)
4835 || (i.reg_operands == 3
4836 && i.tm.opcode_modifier.vexnds)
4837 || (i.reg_operands == 4 && vex_3_sources)))
4845 /* When there are 3 operands, one of them may be immediate,
4846 which may be the first or the last operand. Otherwise,
4847 the first operand must be shift count register (cl) or it
4848 is an instruction with VexNDS. */
4849 gas_assert (i.imm_operands == 1
4850 || (i.imm_operands == 0
4851 && (i.tm.opcode_modifier.vexnds
4852 || i.types[0].bitfield.shiftcount)));
4853 if (operand_type_check (i.types[0], imm)
4854 || i.types[0].bitfield.shiftcount)
4860 /* When there are 4 operands, the first two must be 8bit
4861 immediate operands. The source operand will be the 3rd
4864 For instructions with VexNDS, if the first operand
4865 an imm8, the source operand is the 2nd one. If the last
4866 operand is imm8, the source operand is the first one. */
4867 gas_assert ((i.imm_operands == 2
4868 && i.types[0].bitfield.imm8
4869 && i.types[1].bitfield.imm8)
4870 || (i.tm.opcode_modifier.vexnds
4871 && i.imm_operands == 1
4872 && (i.types[0].bitfield.imm8
4873 || i.types[i.operands - 1].bitfield.imm8)));
4874 if (i.tm.opcode_modifier.vexnds)
4876 if (i.types[0].bitfield.imm8)
4894 if (i.tm.opcode_modifier.vexnds)
4896 /* For instructions with VexNDS, the register-only
4897 source operand must be XMM or YMM register. It is
4898 encoded in VEX prefix. We need to clear RegMem bit
4899 before calling operand_type_equal. */
4900 i386_operand_type op = i.tm.operand_types[dest];
4901 op.bitfield.regmem = 0;
4902 if ((dest + 1) >= i.operands
4903 || (!operand_type_equal (&op, ®xmm)
4904 && !operand_type_equal (&op, ®ymm)))
4906 i.vex.register_specifier = i.op[dest].regs;
4912 /* One of the register operands will be encoded in the i.tm.reg
4913 field, the other in the combined i.tm.mode and i.tm.regmem
4914 fields. If no form of this instruction supports a memory
4915 destination operand, then we assume the source operand may
4916 sometimes be a memory operand and so we need to store the
4917 destination in the i.rm.reg field. */
4918 if (!i.tm.operand_types[dest].bitfield.regmem
4919 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
4921 i.rm.reg = i.op[dest].regs->reg_num;
4922 i.rm.regmem = i.op[source].regs->reg_num;
4923 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4925 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4930 i.rm.reg = i.op[source].regs->reg_num;
4931 i.rm.regmem = i.op[dest].regs->reg_num;
4932 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
4934 if ((i.op[source].regs->reg_flags & RegRex) != 0)
4937 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
4939 if (!i.types[0].bitfield.control
4940 && !i.types[1].bitfield.control)
4942 i.rex &= ~(REX_R | REX_B);
4943 add_prefix (LOCK_PREFIX_OPCODE);
4947 { /* If it's not 2 reg operands... */
4952 unsigned int fake_zero_displacement = 0;
4955 for (op = 0; op < i.operands; op++)
4956 if (operand_type_check (i.types[op], anymem))
4958 gas_assert (op < i.operands);
4962 if (i.base_reg == 0)
4965 if (!i.disp_operands)
4966 fake_zero_displacement = 1;
4967 if (i.index_reg == 0)
4969 /* Operand is just <disp> */
4970 if (flag_code == CODE_64BIT)
4972 /* 64bit mode overwrites the 32bit absolute
4973 addressing by RIP relative addressing and
4974 absolute addressing is encoded by one of the
4975 redundant SIB forms. */
4976 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4977 i.sib.base = NO_BASE_REGISTER;
4978 i.sib.index = NO_INDEX_REGISTER;
4979 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
4980 ? disp32s : disp32);
4982 else if ((flag_code == CODE_16BIT)
4983 ^ (i.prefix[ADDR_PREFIX] != 0))
4985 i.rm.regmem = NO_BASE_REGISTER_16;
4986 i.types[op] = disp16;
4990 i.rm.regmem = NO_BASE_REGISTER;
4991 i.types[op] = disp32;
4994 else /* !i.base_reg && i.index_reg */
4996 if (i.index_reg->reg_num == RegEiz
4997 || i.index_reg->reg_num == RegRiz)
4998 i.sib.index = NO_INDEX_REGISTER;
5000 i.sib.index = i.index_reg->reg_num;
5001 i.sib.base = NO_BASE_REGISTER;
5002 i.sib.scale = i.log2_scale_factor;
5003 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5004 i.types[op].bitfield.disp8 = 0;
5005 i.types[op].bitfield.disp16 = 0;
5006 i.types[op].bitfield.disp64 = 0;
5007 if (flag_code != CODE_64BIT)
5009 /* Must be 32 bit */
5010 i.types[op].bitfield.disp32 = 1;
5011 i.types[op].bitfield.disp32s = 0;
5015 i.types[op].bitfield.disp32 = 0;
5016 i.types[op].bitfield.disp32s = 1;
5018 if ((i.index_reg->reg_flags & RegRex) != 0)
5022 /* RIP addressing for 64bit mode. */
5023 else if (i.base_reg->reg_num == RegRip ||
5024 i.base_reg->reg_num == RegEip)
5026 i.rm.regmem = NO_BASE_REGISTER;
5027 i.types[op].bitfield.disp8 = 0;
5028 i.types[op].bitfield.disp16 = 0;
5029 i.types[op].bitfield.disp32 = 0;
5030 i.types[op].bitfield.disp32s = 1;
5031 i.types[op].bitfield.disp64 = 0;
5032 i.flags[op] |= Operand_PCrel;
5033 if (! i.disp_operands)
5034 fake_zero_displacement = 1;
5036 else if (i.base_reg->reg_type.bitfield.reg16)
5038 switch (i.base_reg->reg_num)
5041 if (i.index_reg == 0)
5043 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5044 i.rm.regmem = i.index_reg->reg_num - 6;
5048 if (i.index_reg == 0)
5051 if (operand_type_check (i.types[op], disp) == 0)
5053 /* fake (%bp) into 0(%bp) */
5054 i.types[op].bitfield.disp8 = 1;
5055 fake_zero_displacement = 1;
5058 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5059 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5061 default: /* (%si) -> 4 or (%di) -> 5 */
5062 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5064 i.rm.mode = mode_from_disp_size (i.types[op]);
5066 else /* i.base_reg and 32/64 bit mode */
5068 if (flag_code == CODE_64BIT
5069 && operand_type_check (i.types[op], disp))
5071 i386_operand_type temp;
5072 operand_type_set (&temp, 0);
5073 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5075 if (i.prefix[ADDR_PREFIX] == 0)
5076 i.types[op].bitfield.disp32s = 1;
5078 i.types[op].bitfield.disp32 = 1;
5081 i.rm.regmem = i.base_reg->reg_num;
5082 if ((i.base_reg->reg_flags & RegRex) != 0)
5084 i.sib.base = i.base_reg->reg_num;
5085 /* x86-64 ignores REX prefix bit here to avoid decoder
5087 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5090 if (i.disp_operands == 0)
5092 fake_zero_displacement = 1;
5093 i.types[op].bitfield.disp8 = 1;
5096 else if (i.base_reg->reg_num == ESP_REG_NUM)
5100 i.sib.scale = i.log2_scale_factor;
5101 if (i.index_reg == 0)
5103 /* <disp>(%esp) becomes two byte modrm with no index
5104 register. We've already stored the code for esp
5105 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5106 Any base register besides %esp will not use the
5107 extra modrm byte. */
5108 i.sib.index = NO_INDEX_REGISTER;
5112 if (i.index_reg->reg_num == RegEiz
5113 || i.index_reg->reg_num == RegRiz)
5114 i.sib.index = NO_INDEX_REGISTER;
5116 i.sib.index = i.index_reg->reg_num;
5117 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5118 if ((i.index_reg->reg_flags & RegRex) != 0)
5123 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5124 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5127 i.rm.mode = mode_from_disp_size (i.types[op]);
5130 if (fake_zero_displacement)
5132 /* Fakes a zero displacement assuming that i.types[op]
5133 holds the correct displacement size. */
5136 gas_assert (i.op[op].disps == 0);
5137 exp = &disp_expressions[i.disp_operands++];
5138 i.op[op].disps = exp;
5139 exp->X_op = O_constant;
5140 exp->X_add_number = 0;
5141 exp->X_add_symbol = (symbolS *) 0;
5142 exp->X_op_symbol = (symbolS *) 0;
5150 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5151 (if any) based on i.tm.extension_opcode. Again, we must be
5152 careful to make sure that segment/control/debug/test/MMX
5153 registers are coded into the i.rm.reg field. */
5157 unsigned int vex_reg = ~0;
5159 for (op = 0; op < i.operands; op++)
5160 if (i.types[op].bitfield.reg8
5161 || i.types[op].bitfield.reg16
5162 || i.types[op].bitfield.reg32
5163 || i.types[op].bitfield.reg64
5164 || i.types[op].bitfield.regmmx
5165 || i.types[op].bitfield.regxmm
5166 || i.types[op].bitfield.regymm
5167 || i.types[op].bitfield.sreg2
5168 || i.types[op].bitfield.sreg3
5169 || i.types[op].bitfield.control
5170 || i.types[op].bitfield.debug
5171 || i.types[op].bitfield.test)
5176 else if (i.tm.opcode_modifier.vexnds)
5178 /* For instructions with VexNDS, the register-only
5179 source operand is encoded in VEX prefix. */
5180 gas_assert (mem != (unsigned int) ~0);
5185 gas_assert (op < i.operands);
5190 gas_assert (vex_reg < i.operands);
5193 else if (i.tm.opcode_modifier.vexndd)
5195 /* For instructions with VexNDD, there should be
5196 no memory operand and the register destination
5197 is encoded in VEX prefix. */
5198 gas_assert (i.mem_operands == 0
5199 && (op + 2) == i.operands);
5203 gas_assert (op < i.operands);
5205 if (vex_reg != (unsigned int) ~0)
5207 gas_assert (i.reg_operands == 2);
5209 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5211 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5214 i.vex.register_specifier = i.op[vex_reg].regs;
5217 /* If there is an extension opcode to put here, the
5218 register number must be put into the regmem field. */
5219 if (i.tm.extension_opcode != None)
5221 i.rm.regmem = i.op[op].regs->reg_num;
5222 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5227 i.rm.reg = i.op[op].regs->reg_num;
5228 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5232 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5233 must set it to 3 to indicate this is a register operand
5234 in the regmem field. */
5235 if (!i.mem_operands)
5239 /* Fill in i.rm.reg field with extension opcode (if any). */
5240 if (i.tm.extension_opcode != None)
5241 i.rm.reg = i.tm.extension_opcode;
5247 output_branch (void)
5252 relax_substateT subtype;
5257 if (flag_code == CODE_16BIT)
5261 if (i.prefix[DATA_PREFIX] != 0)
5267 /* Pentium4 branch hints. */
5268 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5269 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5274 if (i.prefix[REX_PREFIX] != 0)
5280 if (i.prefixes != 0 && !intel_syntax)
5281 as_warn (_("skipping prefixes on this instruction"));
5283 /* It's always a symbol; End frag & setup for relax.
5284 Make sure there is enough room in this frag for the largest
5285 instruction we may generate in md_convert_frag. This is 2
5286 bytes for the opcode and room for the prefix and largest
5288 frag_grow (prefix + 2 + 4);
5289 /* Prefix and 1 opcode byte go in fr_fix. */
5290 p = frag_more (prefix + 1);
5291 if (i.prefix[DATA_PREFIX] != 0)
5292 *p++ = DATA_PREFIX_OPCODE;
5293 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5294 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5295 *p++ = i.prefix[SEG_PREFIX];
5296 if (i.prefix[REX_PREFIX] != 0)
5297 *p++ = i.prefix[REX_PREFIX];
5298 *p = i.tm.base_opcode;
5300 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5301 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
5302 else if (cpu_arch_flags.bitfield.cpui386)
5303 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5305 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5308 sym = i.op[0].disps->X_add_symbol;
5309 off = i.op[0].disps->X_add_number;
5311 if (i.op[0].disps->X_op != O_constant
5312 && i.op[0].disps->X_op != O_symbol)
5314 /* Handle complex expressions. */
5315 sym = make_expr_symbol (i.op[0].disps);
5319 /* 1 possible extra opcode + 4 byte displacement go in var part.
5320 Pass reloc in fr_var. */
5321 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5331 if (i.tm.opcode_modifier.jumpbyte)
5333 /* This is a loop or jecxz type instruction. */
5335 if (i.prefix[ADDR_PREFIX] != 0)
5337 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5340 /* Pentium4 branch hints. */
5341 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5342 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5344 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5353 if (flag_code == CODE_16BIT)
5356 if (i.prefix[DATA_PREFIX] != 0)
5358 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5368 if (i.prefix[REX_PREFIX] != 0)
5370 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5374 if (i.prefixes != 0 && !intel_syntax)
5375 as_warn (_("skipping prefixes on this instruction"));
5377 p = frag_more (1 + size);
5378 *p++ = i.tm.base_opcode;
5380 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5381 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5383 /* All jumps handled here are signed, but don't use a signed limit
5384 check for 32 and 16 bit jumps as we want to allow wrap around at
5385 4G and 64k respectively. */
5387 fixP->fx_signed = 1;
5391 output_interseg_jump (void)
5399 if (flag_code == CODE_16BIT)
5403 if (i.prefix[DATA_PREFIX] != 0)
5409 if (i.prefix[REX_PREFIX] != 0)
5419 if (i.prefixes != 0 && !intel_syntax)
5420 as_warn (_("skipping prefixes on this instruction"));
5422 /* 1 opcode; 2 segment; offset */
5423 p = frag_more (prefix + 1 + 2 + size);
5425 if (i.prefix[DATA_PREFIX] != 0)
5426 *p++ = DATA_PREFIX_OPCODE;
5428 if (i.prefix[REX_PREFIX] != 0)
5429 *p++ = i.prefix[REX_PREFIX];
5431 *p++ = i.tm.base_opcode;
5432 if (i.op[1].imms->X_op == O_constant)
5434 offsetT n = i.op[1].imms->X_add_number;
5437 && !fits_in_unsigned_word (n)
5438 && !fits_in_signed_word (n))
5440 as_bad (_("16-bit jump out of range"));
5443 md_number_to_chars (p, n, size);
5446 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5447 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5448 if (i.op[0].imms->X_op != O_constant)
5449 as_bad (_("can't handle non absolute segment in `%s'"),
5451 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5457 fragS *insn_start_frag;
5458 offsetT insn_start_off;
5460 /* Tie dwarf2 debug info to the address at the start of the insn.
5461 We can't do this after the insn has been output as the current
5462 frag may have been closed off. eg. by frag_var. */
5463 dwarf2_emit_insn (0);
5465 insn_start_frag = frag_now;
5466 insn_start_off = frag_now_fix ();
5469 if (i.tm.opcode_modifier.jump)
5471 else if (i.tm.opcode_modifier.jumpbyte
5472 || i.tm.opcode_modifier.jumpdword)
5474 else if (i.tm.opcode_modifier.jumpintersegment)
5475 output_interseg_jump ();
5478 /* Output normal instructions here. */
5482 unsigned int prefix;
5484 /* Since the VEX prefix contains the implicit prefix, we don't
5485 need the explicit prefix. */
5486 if (!i.tm.opcode_modifier.vex)
5488 switch (i.tm.opcode_length)
5491 if (i.tm.base_opcode & 0xff000000)
5493 prefix = (i.tm.base_opcode >> 24) & 0xff;
5498 if ((i.tm.base_opcode & 0xff0000) != 0)
5500 prefix = (i.tm.base_opcode >> 16) & 0xff;
5501 if (i.tm.cpu_flags.bitfield.cpupadlock)
5504 if (prefix != REPE_PREFIX_OPCODE
5505 || (i.prefix[LOCKREP_PREFIX]
5506 != REPE_PREFIX_OPCODE))
5507 add_prefix (prefix);
5510 add_prefix (prefix);
5519 /* The prefix bytes. */
5520 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5522 FRAG_APPEND_1_CHAR (*q);
5525 if (i.tm.opcode_modifier.vex)
5527 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5532 /* REX byte is encoded in VEX prefix. */
5536 FRAG_APPEND_1_CHAR (*q);
5539 /* There should be no other prefixes for instructions
5544 /* Now the VEX prefix. */
5545 p = frag_more (i.vex.length);
5546 for (j = 0; j < i.vex.length; j++)
5547 p[j] = i.vex.bytes[j];
5550 /* Now the opcode; be careful about word order here! */
5551 if (i.tm.opcode_length == 1)
5553 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5557 switch (i.tm.opcode_length)
5561 *p++ = (i.tm.base_opcode >> 16) & 0xff;
5571 /* Put out high byte first: can't use md_number_to_chars! */
5572 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5573 *p = i.tm.base_opcode & 0xff;
5576 /* Now the modrm byte and sib byte (if present). */
5577 if (i.tm.opcode_modifier.modrm)
5579 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5582 /* If i.rm.regmem == ESP (4)
5583 && i.rm.mode != (Register mode)
5585 ==> need second modrm byte. */
5586 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5588 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
5589 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5591 | i.sib.scale << 6));
5594 if (i.disp_operands)
5595 output_disp (insn_start_frag, insn_start_off);
5598 output_imm (insn_start_frag, insn_start_off);
5604 pi ("" /*line*/, &i);
5606 #endif /* DEBUG386 */
5609 /* Return the size of the displacement operand N. */
5612 disp_size (unsigned int n)
5615 if (i.types[n].bitfield.disp64)
5617 else if (i.types[n].bitfield.disp8)
5619 else if (i.types[n].bitfield.disp16)
5624 /* Return the size of the immediate operand N. */
5627 imm_size (unsigned int n)
5630 if (i.types[n].bitfield.imm64)
5632 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5634 else if (i.types[n].bitfield.imm16)
5640 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
5645 for (n = 0; n < i.operands; n++)
5647 if (operand_type_check (i.types[n], disp))
5649 if (i.op[n].disps->X_op == O_constant)
5651 int size = disp_size (n);
5654 val = offset_in_range (i.op[n].disps->X_add_number,
5656 p = frag_more (size);
5657 md_number_to_chars (p, val, size);
5661 enum bfd_reloc_code_real reloc_type;
5662 int size = disp_size (n);
5663 int sign = i.types[n].bitfield.disp32s;
5664 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5666 /* We can't have 8 bit displacement here. */
5667 gas_assert (!i.types[n].bitfield.disp8);
5669 /* The PC relative address is computed relative
5670 to the instruction boundary, so in case immediate
5671 fields follows, we need to adjust the value. */
5672 if (pcrel && i.imm_operands)
5677 for (n1 = 0; n1 < i.operands; n1++)
5678 if (operand_type_check (i.types[n1], imm))
5680 /* Only one immediate is allowed for PC
5681 relative address. */
5682 gas_assert (sz == 0);
5684 i.op[n].disps->X_add_number -= sz;
5686 /* We should find the immediate. */
5687 gas_assert (sz != 0);
5690 p = frag_more (size);
5691 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
5693 && GOT_symbol == i.op[n].disps->X_add_symbol
5694 && (((reloc_type == BFD_RELOC_32
5695 || reloc_type == BFD_RELOC_X86_64_32S
5696 || (reloc_type == BFD_RELOC_64
5698 && (i.op[n].disps->X_op == O_symbol
5699 || (i.op[n].disps->X_op == O_add
5700 && ((symbol_get_value_expression
5701 (i.op[n].disps->X_op_symbol)->X_op)
5703 || reloc_type == BFD_RELOC_32_PCREL))
5707 if (insn_start_frag == frag_now)
5708 add = (p - frag_now->fr_literal) - insn_start_off;
5713 add = insn_start_frag->fr_fix - insn_start_off;
5714 for (fr = insn_start_frag->fr_next;
5715 fr && fr != frag_now; fr = fr->fr_next)
5717 add += p - frag_now->fr_literal;
5722 reloc_type = BFD_RELOC_386_GOTPC;
5723 i.op[n].imms->X_add_number += add;
5725 else if (reloc_type == BFD_RELOC_64)
5726 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5728 /* Don't do the adjustment for x86-64, as there
5729 the pcrel addressing is relative to the _next_
5730 insn, and that is taken care of in other code. */
5731 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5733 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5734 i.op[n].disps, pcrel, reloc_type);
5741 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
5746 for (n = 0; n < i.operands; n++)
5748 if (operand_type_check (i.types[n], imm))
5750 if (i.op[n].imms->X_op == O_constant)
5752 int size = imm_size (n);
5755 val = offset_in_range (i.op[n].imms->X_add_number,
5757 p = frag_more (size);
5758 md_number_to_chars (p, val, size);
5762 /* Not absolute_section.
5763 Need a 32-bit fixup (don't support 8bit
5764 non-absolute imms). Try to support other
5766 enum bfd_reloc_code_real reloc_type;
5767 int size = imm_size (n);
5770 if (i.types[n].bitfield.imm32s
5771 && (i.suffix == QWORD_MNEM_SUFFIX
5772 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
5777 p = frag_more (size);
5778 reloc_type = reloc (size, 0, sign, i.reloc[n]);
5780 /* This is tough to explain. We end up with this one if we
5781 * have operands that look like
5782 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5783 * obtain the absolute address of the GOT, and it is strongly
5784 * preferable from a performance point of view to avoid using
5785 * a runtime relocation for this. The actual sequence of
5786 * instructions often look something like:
5791 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5793 * The call and pop essentially return the absolute address
5794 * of the label .L66 and store it in %ebx. The linker itself
5795 * will ultimately change the first operand of the addl so
5796 * that %ebx points to the GOT, but to keep things simple, the
5797 * .o file must have this operand set so that it generates not
5798 * the absolute address of .L66, but the absolute address of
5799 * itself. This allows the linker itself simply treat a GOTPC
5800 * relocation as asking for a pcrel offset to the GOT to be
5801 * added in, and the addend of the relocation is stored in the
5802 * operand field for the instruction itself.
5804 * Our job here is to fix the operand so that it would add
5805 * the correct offset so that %ebx would point to itself. The
5806 * thing that is tricky is that .-.L66 will point to the
5807 * beginning of the instruction, so we need to further modify
5808 * the operand so that it will point to itself. There are
5809 * other cases where you have something like:
5811 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5813 * and here no correction would be required. Internally in
5814 * the assembler we treat operands of this form as not being
5815 * pcrel since the '.' is explicitly mentioned, and I wonder
5816 * whether it would simplify matters to do it this way. Who
5817 * knows. In earlier versions of the PIC patches, the
5818 * pcrel_adjust field was used to store the correction, but
5819 * since the expression is not pcrel, I felt it would be
5820 * confusing to do it this way. */
5822 if ((reloc_type == BFD_RELOC_32
5823 || reloc_type == BFD_RELOC_X86_64_32S
5824 || reloc_type == BFD_RELOC_64)
5826 && GOT_symbol == i.op[n].imms->X_add_symbol
5827 && (i.op[n].imms->X_op == O_symbol
5828 || (i.op[n].imms->X_op == O_add
5829 && ((symbol_get_value_expression
5830 (i.op[n].imms->X_op_symbol)->X_op)
5835 if (insn_start_frag == frag_now)
5836 add = (p - frag_now->fr_literal) - insn_start_off;
5841 add = insn_start_frag->fr_fix - insn_start_off;
5842 for (fr = insn_start_frag->fr_next;
5843 fr && fr != frag_now; fr = fr->fr_next)
5845 add += p - frag_now->fr_literal;
5849 reloc_type = BFD_RELOC_386_GOTPC;
5851 reloc_type = BFD_RELOC_X86_64_GOTPC32;
5853 reloc_type = BFD_RELOC_X86_64_GOTPC64;
5854 i.op[n].imms->X_add_number += add;
5856 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5857 i.op[n].imms, 0, reloc_type);
5863 /* x86_cons_fix_new is called via the expression parsing code when a
5864 reloc is needed. We use this hook to get the correct .got reloc. */
5865 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5866 static int cons_sign = -1;
5869 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
5872 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5874 got_reloc = NO_RELOC;
5877 if (exp->X_op == O_secrel)
5879 exp->X_op = O_symbol;
5880 r = BFD_RELOC_32_SECREL;
5884 fix_new_exp (frag, off, len, exp, 0, r);
5887 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5888 # define lex_got(reloc, adjust, types) NULL
5890 /* Parse operands of the form
5891 <symbol>@GOTOFF+<nnn>
5892 and similar .plt or .got references.
5894 If we find one, set up the correct relocation in RELOC and copy the
5895 input string, minus the `@GOTOFF' into a malloc'd buffer for
5896 parsing by the calling routine. Return this buffer, and if ADJUST
5897 is non-null set it to the length of the string we removed from the
5898 input line. Otherwise return NULL. */
5900 lex_got (enum bfd_reloc_code_real *reloc,
5902 i386_operand_type *types)
5904 /* Some of the relocations depend on the size of what field is to
5905 be relocated. But in our callers i386_immediate and i386_displacement
5906 we don't yet know the operand size (this will be set by insn
5907 matching). Hence we record the word32 relocation here,
5908 and adjust the reloc according to the real size in reloc(). */
5909 static const struct {
5911 const enum bfd_reloc_code_real rel[2];
5912 const i386_operand_type types64;
5915 BFD_RELOC_X86_64_PLTOFF64 },
5916 OPERAND_TYPE_IMM64 },
5917 { "PLT", { BFD_RELOC_386_PLT32,
5918 BFD_RELOC_X86_64_PLT32 },
5919 OPERAND_TYPE_IMM32_32S_DISP32 },
5921 BFD_RELOC_X86_64_GOTPLT64 },
5922 OPERAND_TYPE_IMM64_DISP64 },
5923 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5924 BFD_RELOC_X86_64_GOTOFF64 },
5925 OPERAND_TYPE_IMM64_DISP64 },
5927 BFD_RELOC_X86_64_GOTPCREL },
5928 OPERAND_TYPE_IMM32_32S_DISP32 },
5929 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5930 BFD_RELOC_X86_64_TLSGD },
5931 OPERAND_TYPE_IMM32_32S_DISP32 },
5932 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5934 OPERAND_TYPE_NONE },
5936 BFD_RELOC_X86_64_TLSLD },
5937 OPERAND_TYPE_IMM32_32S_DISP32 },
5938 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5939 BFD_RELOC_X86_64_GOTTPOFF },
5940 OPERAND_TYPE_IMM32_32S_DISP32 },
5941 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5942 BFD_RELOC_X86_64_TPOFF32 },
5943 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5944 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5946 OPERAND_TYPE_NONE },
5947 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5948 BFD_RELOC_X86_64_DTPOFF32 },
5950 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
5951 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5953 OPERAND_TYPE_NONE },
5954 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5956 OPERAND_TYPE_NONE },
5957 { "GOT", { BFD_RELOC_386_GOT32,
5958 BFD_RELOC_X86_64_GOT32 },
5959 OPERAND_TYPE_IMM32_32S_64_DISP32 },
5960 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5961 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
5962 OPERAND_TYPE_IMM32_32S_DISP32 },
5963 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5964 BFD_RELOC_X86_64_TLSDESC_CALL },
5965 OPERAND_TYPE_IMM32_32S_DISP32 },
5973 for (cp = input_line_pointer; *cp != '@'; cp++)
5974 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
5977 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
5981 len = strlen (gotrel[j].str);
5982 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
5984 if (gotrel[j].rel[object_64bit] != 0)
5987 char *tmpbuf, *past_reloc;
5989 *reloc = gotrel[j].rel[object_64bit];
5995 if (flag_code != CODE_64BIT)
5997 types->bitfield.imm32 = 1;
5998 types->bitfield.disp32 = 1;
6001 *types = gotrel[j].types64;
6004 if (GOT_symbol == NULL)
6005 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6007 /* The length of the first part of our input line. */
6008 first = cp - input_line_pointer;
6010 /* The second part goes from after the reloc token until
6011 (and including) an end_of_line char or comma. */
6012 past_reloc = cp + 1 + len;
6014 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6016 second = cp + 1 - past_reloc;
6018 /* Allocate and copy string. The trailing NUL shouldn't
6019 be necessary, but be safe. */
6020 tmpbuf = xmalloc (first + second + 2);
6021 memcpy (tmpbuf, input_line_pointer, first);
6022 if (second != 0 && *past_reloc != ' ')
6023 /* Replace the relocation token with ' ', so that
6024 errors like foo@GOTOFF1 will be detected. */
6025 tmpbuf[first++] = ' ';
6026 memcpy (tmpbuf + first, past_reloc, second);
6027 tmpbuf[first + second] = '\0';
6031 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6032 gotrel[j].str, 1 << (5 + object_64bit));
6037 /* Might be a symbol version string. Don't as_bad here. */
6042 x86_cons (expressionS *exp, int size)
6044 intel_syntax = -intel_syntax;
6046 if (size == 4 || (object_64bit && size == 8))
6048 /* Handle @GOTOFF and the like in an expression. */
6050 char *gotfree_input_line;
6053 save = input_line_pointer;
6054 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
6055 if (gotfree_input_line)
6056 input_line_pointer = gotfree_input_line;
6060 if (gotfree_input_line)
6062 /* expression () has merrily parsed up to the end of line,
6063 or a comma - in the wrong buffer. Transfer how far
6064 input_line_pointer has moved to the right buffer. */
6065 input_line_pointer = (save
6066 + (input_line_pointer - gotfree_input_line)
6068 free (gotfree_input_line);
6069 if (exp->X_op == O_constant
6070 || exp->X_op == O_absent
6071 || exp->X_op == O_illegal
6072 || exp->X_op == O_register
6073 || exp->X_op == O_big)
6075 char c = *input_line_pointer;
6076 *input_line_pointer = 0;
6077 as_bad (_("missing or invalid expression `%s'"), save);
6078 *input_line_pointer = c;
6085 intel_syntax = -intel_syntax;
6088 i386_intel_simplify (exp);
6092 static void signed_cons (int size)
6094 if (flag_code == CODE_64BIT)
6102 pe_directive_secrel (dummy)
6103 int dummy ATTRIBUTE_UNUSED;
6110 if (exp.X_op == O_symbol)
6111 exp.X_op = O_secrel;
6113 emit_expr (&exp, 4);
6115 while (*input_line_pointer++ == ',');
6117 input_line_pointer--;
6118 demand_empty_rest_of_line ();
6123 i386_immediate (char *imm_start)
6125 char *save_input_line_pointer;
6126 char *gotfree_input_line;
6129 i386_operand_type types;
6131 operand_type_set (&types, ~0);
6133 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6135 as_bad (_("at most %d immediate operands are allowed"),
6136 MAX_IMMEDIATE_OPERANDS);
6140 exp = &im_expressions[i.imm_operands++];
6141 i.op[this_operand].imms = exp;
6143 if (is_space_char (*imm_start))
6146 save_input_line_pointer = input_line_pointer;
6147 input_line_pointer = imm_start;
6149 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6150 if (gotfree_input_line)
6151 input_line_pointer = gotfree_input_line;
6153 exp_seg = expression (exp);
6156 if (*input_line_pointer)
6157 as_bad (_("junk `%s' after expression"), input_line_pointer);
6159 input_line_pointer = save_input_line_pointer;
6160 if (gotfree_input_line)
6162 free (gotfree_input_line);
6164 if (exp->X_op == O_constant || exp->X_op == O_register)
6165 exp->X_op = O_illegal;
6168 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6172 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6173 i386_operand_type types, const char *imm_start)
6175 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
6177 as_bad (_("missing or invalid immediate expression `%s'"),
6181 else if (exp->X_op == O_constant)
6183 /* Size it properly later. */
6184 i.types[this_operand].bitfield.imm64 = 1;
6185 /* If BFD64, sign extend val. */
6186 if (!use_rela_relocations
6187 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6189 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
6191 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6192 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
6193 && exp_seg != absolute_section
6194 && exp_seg != text_section
6195 && exp_seg != data_section
6196 && exp_seg != bss_section
6197 && exp_seg != undefined_section
6198 && !bfd_is_com_section (exp_seg))
6200 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6204 else if (!intel_syntax && exp->X_op == O_register)
6206 as_bad (_("illegal immediate register operand %s"), imm_start);
6211 /* This is an address. The size of the address will be
6212 determined later, depending on destination register,
6213 suffix, or the default for the section. */
6214 i.types[this_operand].bitfield.imm8 = 1;
6215 i.types[this_operand].bitfield.imm16 = 1;
6216 i.types[this_operand].bitfield.imm32 = 1;
6217 i.types[this_operand].bitfield.imm32s = 1;
6218 i.types[this_operand].bitfield.imm64 = 1;
6219 i.types[this_operand] = operand_type_and (i.types[this_operand],
6227 i386_scale (char *scale)
6230 char *save = input_line_pointer;
6232 input_line_pointer = scale;
6233 val = get_absolute_expression ();
6238 i.log2_scale_factor = 0;
6241 i.log2_scale_factor = 1;
6244 i.log2_scale_factor = 2;
6247 i.log2_scale_factor = 3;
6251 char sep = *input_line_pointer;
6253 *input_line_pointer = '\0';
6254 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6256 *input_line_pointer = sep;
6257 input_line_pointer = save;
6261 if (i.log2_scale_factor != 0 && i.index_reg == 0)
6263 as_warn (_("scale factor of %d without an index register"),
6264 1 << i.log2_scale_factor);
6265 i.log2_scale_factor = 0;
6267 scale = input_line_pointer;
6268 input_line_pointer = save;
6273 i386_displacement (char *disp_start, char *disp_end)
6277 char *save_input_line_pointer;
6278 char *gotfree_input_line;
6280 i386_operand_type bigdisp, types = anydisp;
6283 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6285 as_bad (_("at most %d displacement operands are allowed"),
6286 MAX_MEMORY_OPERANDS);
6290 operand_type_set (&bigdisp, 0);
6291 if ((i.types[this_operand].bitfield.jumpabsolute)
6292 || (!current_templates->start->opcode_modifier.jump
6293 && !current_templates->start->opcode_modifier.jumpdword))
6295 bigdisp.bitfield.disp32 = 1;
6296 override = (i.prefix[ADDR_PREFIX] != 0);
6297 if (flag_code == CODE_64BIT)
6301 bigdisp.bitfield.disp32s = 1;
6302 bigdisp.bitfield.disp64 = 1;
6305 else if ((flag_code == CODE_16BIT) ^ override)
6307 bigdisp.bitfield.disp32 = 0;
6308 bigdisp.bitfield.disp16 = 1;
6313 /* For PC-relative branches, the width of the displacement
6314 is dependent upon data size, not address size. */
6315 override = (i.prefix[DATA_PREFIX] != 0);
6316 if (flag_code == CODE_64BIT)
6318 if (override || i.suffix == WORD_MNEM_SUFFIX)
6319 bigdisp.bitfield.disp16 = 1;
6322 bigdisp.bitfield.disp32 = 1;
6323 bigdisp.bitfield.disp32s = 1;
6329 override = (i.suffix == (flag_code != CODE_16BIT
6331 : LONG_MNEM_SUFFIX));
6332 bigdisp.bitfield.disp32 = 1;
6333 if ((flag_code == CODE_16BIT) ^ override)
6335 bigdisp.bitfield.disp32 = 0;
6336 bigdisp.bitfield.disp16 = 1;
6340 i.types[this_operand] = operand_type_or (i.types[this_operand],
6343 exp = &disp_expressions[i.disp_operands];
6344 i.op[this_operand].disps = exp;
6346 save_input_line_pointer = input_line_pointer;
6347 input_line_pointer = disp_start;
6348 END_STRING_AND_SAVE (disp_end);
6350 #ifndef GCC_ASM_O_HACK
6351 #define GCC_ASM_O_HACK 0
6354 END_STRING_AND_SAVE (disp_end + 1);
6355 if (i.types[this_operand].bitfield.baseIndex
6356 && displacement_string_end[-1] == '+')
6358 /* This hack is to avoid a warning when using the "o"
6359 constraint within gcc asm statements.
6362 #define _set_tssldt_desc(n,addr,limit,type) \
6363 __asm__ __volatile__ ( \
6365 "movw %w1,2+%0\n\t" \
6367 "movb %b1,4+%0\n\t" \
6368 "movb %4,5+%0\n\t" \
6369 "movb $0,6+%0\n\t" \
6370 "movb %h1,7+%0\n\t" \
6372 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6374 This works great except that the output assembler ends
6375 up looking a bit weird if it turns out that there is
6376 no offset. You end up producing code that looks like:
6389 So here we provide the missing zero. */
6391 *displacement_string_end = '0';
6394 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
6395 if (gotfree_input_line)
6396 input_line_pointer = gotfree_input_line;
6398 exp_seg = expression (exp);
6401 if (*input_line_pointer)
6402 as_bad (_("junk `%s' after expression"), input_line_pointer);
6404 RESTORE_END_STRING (disp_end + 1);
6406 input_line_pointer = save_input_line_pointer;
6407 if (gotfree_input_line)
6409 free (gotfree_input_line);
6411 if (exp->X_op == O_constant || exp->X_op == O_register)
6412 exp->X_op = O_illegal;
6415 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6417 RESTORE_END_STRING (disp_end);
6423 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6424 i386_operand_type types, const char *disp_start)
6426 i386_operand_type bigdisp;
6429 /* We do this to make sure that the section symbol is in
6430 the symbol table. We will ultimately change the relocation
6431 to be relative to the beginning of the section. */
6432 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
6433 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6434 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6436 if (exp->X_op != O_symbol)
6439 if (S_IS_LOCAL (exp->X_add_symbol)
6440 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6441 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
6442 exp->X_op = O_subtract;
6443 exp->X_op_symbol = GOT_symbol;
6444 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
6445 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
6446 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6447 i.reloc[this_operand] = BFD_RELOC_64;
6449 i.reloc[this_operand] = BFD_RELOC_32;
6452 else if (exp->X_op == O_absent
6453 || exp->X_op == O_illegal
6454 || exp->X_op == O_big)
6457 as_bad (_("missing or invalid displacement expression `%s'"),
6462 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6463 else if (exp->X_op != O_constant
6464 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6465 && exp_seg != absolute_section
6466 && exp_seg != text_section
6467 && exp_seg != data_section
6468 && exp_seg != bss_section
6469 && exp_seg != undefined_section
6470 && !bfd_is_com_section (exp_seg))
6472 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
6477 /* Check if this is a displacement only operand. */
6478 bigdisp = i.types[this_operand];
6479 bigdisp.bitfield.disp8 = 0;
6480 bigdisp.bitfield.disp16 = 0;
6481 bigdisp.bitfield.disp32 = 0;
6482 bigdisp.bitfield.disp32s = 0;
6483 bigdisp.bitfield.disp64 = 0;
6484 if (operand_type_all_zero (&bigdisp))
6485 i.types[this_operand] = operand_type_and (i.types[this_operand],
6491 /* Make sure the memory operand we've been dealt is valid.
6492 Return 1 on success, 0 on a failure. */
6495 i386_index_check (const char *operand_string)
6498 const char *kind = "base/index";
6499 #if INFER_ADDR_PREFIX
6505 if (current_templates->start->opcode_modifier.isstring
6506 && !current_templates->start->opcode_modifier.immext
6507 && (current_templates->end[-1].opcode_modifier.isstring
6510 /* Memory operands of string insns are special in that they only allow
6511 a single register (rDI, rSI, or rBX) as their memory address. */
6512 unsigned int expected;
6514 kind = "string address";
6516 if (current_templates->start->opcode_modifier.w)
6518 i386_operand_type type = current_templates->end[-1].operand_types[0];
6520 if (!type.bitfield.baseindex
6521 || ((!i.mem_operands != !intel_syntax)
6522 && current_templates->end[-1].operand_types[1]
6523 .bitfield.baseindex))
6524 type = current_templates->end[-1].operand_types[1];
6525 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6528 expected = 3 /* rBX */;
6530 if (!i.base_reg || i.index_reg
6531 || operand_type_check (i.types[this_operand], disp))
6533 else if (!(flag_code == CODE_64BIT
6534 ? i.prefix[ADDR_PREFIX]
6535 ? i.base_reg->reg_type.bitfield.reg32
6536 : i.base_reg->reg_type.bitfield.reg64
6537 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6538 ? i.base_reg->reg_type.bitfield.reg32
6539 : i.base_reg->reg_type.bitfield.reg16))
6541 else if (i.base_reg->reg_num != expected)
6548 for (j = 0; j < i386_regtab_size; ++j)
6549 if ((flag_code == CODE_64BIT
6550 ? i.prefix[ADDR_PREFIX]
6551 ? i386_regtab[j].reg_type.bitfield.reg32
6552 : i386_regtab[j].reg_type.bitfield.reg64
6553 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6554 ? i386_regtab[j].reg_type.bitfield.reg32
6555 : i386_regtab[j].reg_type.bitfield.reg16)
6556 && i386_regtab[j].reg_num == expected)
6558 gas_assert (j < i386_regtab_size);
6559 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6561 intel_syntax ? '[' : '(',
6563 i386_regtab[j].reg_name,
6564 intel_syntax ? ']' : ')');
6568 else if (flag_code == CODE_64BIT)
6571 && ((i.prefix[ADDR_PREFIX] == 0
6572 && !i.base_reg->reg_type.bitfield.reg64)
6573 || (i.prefix[ADDR_PREFIX]
6574 && !i.base_reg->reg_type.bitfield.reg32))
6576 || i.base_reg->reg_num !=
6577 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
6579 && (!i.index_reg->reg_type.bitfield.baseindex
6580 || (i.prefix[ADDR_PREFIX] == 0
6581 && i.index_reg->reg_num != RegRiz
6582 && !i.index_reg->reg_type.bitfield.reg64
6584 || (i.prefix[ADDR_PREFIX]
6585 && i.index_reg->reg_num != RegEiz
6586 && !i.index_reg->reg_type.bitfield.reg32))))
6591 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6595 && (!i.base_reg->reg_type.bitfield.reg16
6596 || !i.base_reg->reg_type.bitfield.baseindex))
6598 && (!i.index_reg->reg_type.bitfield.reg16
6599 || !i.index_reg->reg_type.bitfield.baseindex
6601 && i.base_reg->reg_num < 6
6602 && i.index_reg->reg_num >= 6
6603 && i.log2_scale_factor == 0))))
6610 && !i.base_reg->reg_type.bitfield.reg32)
6612 && ((!i.index_reg->reg_type.bitfield.reg32
6613 && i.index_reg->reg_num != RegEiz)
6614 || !i.index_reg->reg_type.bitfield.baseindex)))
6620 #if INFER_ADDR_PREFIX
6621 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
6623 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6625 /* Change the size of any displacement too. At most one of
6626 Disp16 or Disp32 is set.
6627 FIXME. There doesn't seem to be any real need for separate
6628 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6629 Removing them would probably clean up the code quite a lot. */
6630 if (flag_code != CODE_64BIT
6631 && (i.types[this_operand].bitfield.disp16
6632 || i.types[this_operand].bitfield.disp32))
6633 i.types[this_operand]
6634 = operand_type_xor (i.types[this_operand], disp16_32);
6639 as_bad (_("`%s' is not a valid %s expression"),
6644 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6646 flag_code_names[i.prefix[ADDR_PREFIX]
6647 ? flag_code == CODE_32BIT
6656 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6660 i386_att_operand (char *operand_string)
6664 char *op_string = operand_string;
6666 if (is_space_char (*op_string))
6669 /* We check for an absolute prefix (differentiating,
6670 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6671 if (*op_string == ABSOLUTE_PREFIX)
6674 if (is_space_char (*op_string))
6676 i.types[this_operand].bitfield.jumpabsolute = 1;
6679 /* Check if operand is a register. */
6680 if ((r = parse_register (op_string, &end_op)) != NULL)
6682 i386_operand_type temp;
6684 /* Check for a segment override by searching for ':' after a
6685 segment register. */
6687 if (is_space_char (*op_string))
6689 if (*op_string == ':'
6690 && (r->reg_type.bitfield.sreg2
6691 || r->reg_type.bitfield.sreg3))
6696 i.seg[i.mem_operands] = &es;
6699 i.seg[i.mem_operands] = &cs;
6702 i.seg[i.mem_operands] = &ss;
6705 i.seg[i.mem_operands] = &ds;
6708 i.seg[i.mem_operands] = &fs;
6711 i.seg[i.mem_operands] = &gs;
6715 /* Skip the ':' and whitespace. */
6717 if (is_space_char (*op_string))
6720 if (!is_digit_char (*op_string)
6721 && !is_identifier_char (*op_string)
6722 && *op_string != '('
6723 && *op_string != ABSOLUTE_PREFIX)
6725 as_bad (_("bad memory operand `%s'"), op_string);
6728 /* Handle case of %es:*foo. */
6729 if (*op_string == ABSOLUTE_PREFIX)
6732 if (is_space_char (*op_string))
6734 i.types[this_operand].bitfield.jumpabsolute = 1;
6736 goto do_memory_reference;
6740 as_bad (_("junk `%s' after register"), op_string);
6744 temp.bitfield.baseindex = 0;
6745 i.types[this_operand] = operand_type_or (i.types[this_operand],
6747 i.types[this_operand].bitfield.unspecified = 0;
6748 i.op[this_operand].regs = r;
6751 else if (*op_string == REGISTER_PREFIX)
6753 as_bad (_("bad register name `%s'"), op_string);
6756 else if (*op_string == IMMEDIATE_PREFIX)
6759 if (i.types[this_operand].bitfield.jumpabsolute)
6761 as_bad (_("immediate operand illegal with absolute jump"));
6764 if (!i386_immediate (op_string))
6767 else if (is_digit_char (*op_string)
6768 || is_identifier_char (*op_string)
6769 || *op_string == '(')
6771 /* This is a memory reference of some sort. */
6774 /* Start and end of displacement string expression (if found). */
6775 char *displacement_string_start;
6776 char *displacement_string_end;
6778 do_memory_reference:
6779 if ((i.mem_operands == 1
6780 && !current_templates->start->opcode_modifier.isstring)
6781 || i.mem_operands == 2)
6783 as_bad (_("too many memory references for `%s'"),
6784 current_templates->start->name);
6788 /* Check for base index form. We detect the base index form by
6789 looking for an ')' at the end of the operand, searching
6790 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6792 base_string = op_string + strlen (op_string);
6795 if (is_space_char (*base_string))
6798 /* If we only have a displacement, set-up for it to be parsed later. */
6799 displacement_string_start = op_string;
6800 displacement_string_end = base_string + 1;
6802 if (*base_string == ')')
6805 unsigned int parens_balanced = 1;
6806 /* We've already checked that the number of left & right ()'s are
6807 equal, so this loop will not be infinite. */
6811 if (*base_string == ')')
6813 if (*base_string == '(')
6816 while (parens_balanced);
6818 temp_string = base_string;
6820 /* Skip past '(' and whitespace. */
6822 if (is_space_char (*base_string))
6825 if (*base_string == ','
6826 || ((i.base_reg = parse_register (base_string, &end_op))
6829 displacement_string_end = temp_string;
6831 i.types[this_operand].bitfield.baseindex = 1;
6835 base_string = end_op;
6836 if (is_space_char (*base_string))
6840 /* There may be an index reg or scale factor here. */
6841 if (*base_string == ',')
6844 if (is_space_char (*base_string))
6847 if ((i.index_reg = parse_register (base_string, &end_op))
6850 base_string = end_op;
6851 if (is_space_char (*base_string))
6853 if (*base_string == ',')
6856 if (is_space_char (*base_string))
6859 else if (*base_string != ')')
6861 as_bad (_("expecting `,' or `)' "
6862 "after index register in `%s'"),
6867 else if (*base_string == REGISTER_PREFIX)
6869 as_bad (_("bad register name `%s'"), base_string);
6873 /* Check for scale factor. */
6874 if (*base_string != ')')
6876 char *end_scale = i386_scale (base_string);
6881 base_string = end_scale;
6882 if (is_space_char (*base_string))
6884 if (*base_string != ')')
6886 as_bad (_("expecting `)' "
6887 "after scale factor in `%s'"),
6892 else if (!i.index_reg)
6894 as_bad (_("expecting index register or scale factor "
6895 "after `,'; got '%c'"),
6900 else if (*base_string != ')')
6902 as_bad (_("expecting `,' or `)' "
6903 "after base register in `%s'"),
6908 else if (*base_string == REGISTER_PREFIX)
6910 as_bad (_("bad register name `%s'"), base_string);
6915 /* If there's an expression beginning the operand, parse it,
6916 assuming displacement_string_start and
6917 displacement_string_end are meaningful. */
6918 if (displacement_string_start != displacement_string_end)
6920 if (!i386_displacement (displacement_string_start,
6921 displacement_string_end))
6925 /* Special case for (%dx) while doing input/output op. */
6927 && operand_type_equal (&i.base_reg->reg_type,
6928 ®16_inoutportreg)
6930 && i.log2_scale_factor == 0
6931 && i.seg[i.mem_operands] == 0
6932 && !operand_type_check (i.types[this_operand], disp))
6934 i.types[this_operand] = inoutportreg;
6938 if (i386_index_check (operand_string) == 0)
6940 i.types[this_operand].bitfield.mem = 1;
6945 /* It's not a memory operand; argh! */
6946 as_bad (_("invalid char %s beginning operand %d `%s'"),
6947 output_invalid (*op_string),
6952 return 1; /* Normal return. */
6955 /* md_estimate_size_before_relax()
6957 Called just before relax() for rs_machine_dependent frags. The x86
6958 assembler uses these frags to handle variable size jump
6961 Any symbol that is now undefined will not become defined.
6962 Return the correct fr_subtype in the frag.
6963 Return the initial "guess for variable size of frag" to caller.
6964 The guess is actually the growth beyond the fixed part. Whatever
6965 we do to grow the fixed or variable part contributes to our
6969 md_estimate_size_before_relax (fragP, segment)
6973 /* We've already got fragP->fr_subtype right; all we have to do is
6974 check for un-relaxable symbols. On an ELF system, we can't relax
6975 an externally visible symbol, because it may be overridden by a
6977 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6978 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6980 && (S_IS_EXTERNAL (fragP->fr_symbol)
6981 || S_IS_WEAK (fragP->fr_symbol)
6982 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
6983 & BSF_GNU_INDIRECT_FUNCTION))))
6985 #if defined (OBJ_COFF) && defined (TE_PE)
6986 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
6987 && S_IS_WEAK (fragP->fr_symbol))
6991 /* Symbol is undefined in this segment, or we need to keep a
6992 reloc so that weak symbols can be overridden. */
6993 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
6994 enum bfd_reloc_code_real reloc_type;
6995 unsigned char *opcode;
6998 if (fragP->fr_var != NO_RELOC)
6999 reloc_type = fragP->fr_var;
7001 reloc_type = BFD_RELOC_16_PCREL;
7003 reloc_type = BFD_RELOC_32_PCREL;
7005 old_fr_fix = fragP->fr_fix;
7006 opcode = (unsigned char *) fragP->fr_opcode;
7008 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
7011 /* Make jmp (0xeb) a (d)word displacement jump. */
7013 fragP->fr_fix += size;
7014 fix_new (fragP, old_fr_fix, size,
7016 fragP->fr_offset, 1,
7022 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
7024 /* Negate the condition, and branch past an
7025 unconditional jump. */
7028 /* Insert an unconditional jump. */
7030 /* We added two extra opcode bytes, and have a two byte
7032 fragP->fr_fix += 2 + 2;
7033 fix_new (fragP, old_fr_fix + 2, 2,
7035 fragP->fr_offset, 1,
7042 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7047 fixP = fix_new (fragP, old_fr_fix, 1,
7049 fragP->fr_offset, 1,
7051 fixP->fx_signed = 1;
7055 /* This changes the byte-displacement jump 0x7N
7056 to the (d)word-displacement jump 0x0f,0x8N. */
7057 opcode[1] = opcode[0] + 0x10;
7058 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7059 /* We've added an opcode byte. */
7060 fragP->fr_fix += 1 + size;
7061 fix_new (fragP, old_fr_fix + 1, size,
7063 fragP->fr_offset, 1,
7068 BAD_CASE (fragP->fr_subtype);
7072 return fragP->fr_fix - old_fr_fix;
7075 /* Guess size depending on current relax state. Initially the relax
7076 state will correspond to a short jump and we return 1, because
7077 the variable part of the frag (the branch offset) is one byte
7078 long. However, we can relax a section more than once and in that
7079 case we must either set fr_subtype back to the unrelaxed state,
7080 or return the value for the appropriate branch. */
7081 return md_relax_table[fragP->fr_subtype].rlx_length;
7084 /* Called after relax() is finished.
7086 In: Address of frag.
7087 fr_type == rs_machine_dependent.
7088 fr_subtype is what the address relaxed to.
7090 Out: Any fixSs and constants are set up.
7091 Caller will turn frag into a ".space 0". */
7094 md_convert_frag (abfd, sec, fragP)
7095 bfd *abfd ATTRIBUTE_UNUSED;
7096 segT sec ATTRIBUTE_UNUSED;
7099 unsigned char *opcode;
7100 unsigned char *where_to_put_displacement = NULL;
7101 offsetT target_address;
7102 offsetT opcode_address;
7103 unsigned int extension = 0;
7104 offsetT displacement_from_opcode_start;
7106 opcode = (unsigned char *) fragP->fr_opcode;
7108 /* Address we want to reach in file space. */
7109 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
7111 /* Address opcode resides at in file space. */
7112 opcode_address = fragP->fr_address + fragP->fr_fix;
7114 /* Displacement from opcode start to fill into instruction. */
7115 displacement_from_opcode_start = target_address - opcode_address;
7117 if ((fragP->fr_subtype & BIG) == 0)
7119 /* Don't have to change opcode. */
7120 extension = 1; /* 1 opcode + 1 displacement */
7121 where_to_put_displacement = &opcode[1];
7125 if (no_cond_jump_promotion
7126 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
7127 as_warn_where (fragP->fr_file, fragP->fr_line,
7128 _("long jump required"));
7130 switch (fragP->fr_subtype)
7132 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7133 extension = 4; /* 1 opcode + 4 displacement */
7135 where_to_put_displacement = &opcode[1];
7138 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7139 extension = 2; /* 1 opcode + 2 displacement */
7141 where_to_put_displacement = &opcode[1];
7144 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7145 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7146 extension = 5; /* 2 opcode + 4 displacement */
7147 opcode[1] = opcode[0] + 0x10;
7148 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7149 where_to_put_displacement = &opcode[2];
7152 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7153 extension = 3; /* 2 opcode + 2 displacement */
7154 opcode[1] = opcode[0] + 0x10;
7155 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7156 where_to_put_displacement = &opcode[2];
7159 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7164 where_to_put_displacement = &opcode[3];
7168 BAD_CASE (fragP->fr_subtype);
7173 /* If size if less then four we are sure that the operand fits,
7174 but if it's 4, then it could be that the displacement is larger
7176 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7178 && ((addressT) (displacement_from_opcode_start - extension
7179 + ((addressT) 1 << 31))
7180 > (((addressT) 2 << 31) - 1)))
7182 as_bad_where (fragP->fr_file, fragP->fr_line,
7183 _("jump target out of range"));
7184 /* Make us emit 0. */
7185 displacement_from_opcode_start = extension;
7187 /* Now put displacement after opcode. */
7188 md_number_to_chars ((char *) where_to_put_displacement,
7189 (valueT) (displacement_from_opcode_start - extension),
7190 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
7191 fragP->fr_fix += extension;
7194 /* Apply a fixup (fixS) to segment data, once it has been determined
7195 by our caller that we have all the info we need to fix it up.
7197 On the 386, immediates, displacements, and data pointers are all in
7198 the same (little-endian) format, so we don't need to care about which
7202 md_apply_fix (fixP, valP, seg)
7203 /* The fix we're to put in. */
7205 /* Pointer to the value of the bits. */
7207 /* Segment fix is from. */
7208 segT seg ATTRIBUTE_UNUSED;
7210 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
7211 valueT value = *valP;
7213 #if !defined (TE_Mach)
7216 switch (fixP->fx_r_type)
7222 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7225 case BFD_RELOC_X86_64_32S:
7226 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7229 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7232 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7237 if (fixP->fx_addsy != NULL
7238 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
7239 || fixP->fx_r_type == BFD_RELOC_64_PCREL
7240 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7241 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7242 && !use_rela_relocations)
7244 /* This is a hack. There should be a better way to handle this.
7245 This covers for the fact that bfd_install_relocation will
7246 subtract the current location (for partial_inplace, PC relative
7247 relocations); see more below. */
7251 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7254 value += fixP->fx_where + fixP->fx_frag->fr_address;
7256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7259 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
7262 || (symbol_section_p (fixP->fx_addsy)
7263 && sym_seg != absolute_section))
7264 && !TC_FORCE_RELOCATION (fixP))
7266 /* Yes, we add the values in twice. This is because
7267 bfd_install_relocation subtracts them out again. I think
7268 bfd_install_relocation is broken, but I don't dare change
7270 value += fixP->fx_where + fixP->fx_frag->fr_address;
7274 #if defined (OBJ_COFF) && defined (TE_PE)
7275 /* For some reason, the PE format does not store a
7276 section address offset for a PC relative symbol. */
7277 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7278 || S_IS_WEAK (fixP->fx_addsy))
7279 value += md_pcrel_from (fixP);
7282 #if defined (OBJ_COFF) && defined (TE_PE)
7283 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7285 value -= S_GET_VALUE (fixP->fx_addsy);
7289 /* Fix a few things - the dynamic linker expects certain values here,
7290 and we must not disappoint it. */
7291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7292 if (IS_ELF && fixP->fx_addsy)
7293 switch (fixP->fx_r_type)
7295 case BFD_RELOC_386_PLT32:
7296 case BFD_RELOC_X86_64_PLT32:
7297 /* Make the jump instruction point to the address of the operand. At
7298 runtime we merely add the offset to the actual PLT entry. */
7302 case BFD_RELOC_386_TLS_GD:
7303 case BFD_RELOC_386_TLS_LDM:
7304 case BFD_RELOC_386_TLS_IE_32:
7305 case BFD_RELOC_386_TLS_IE:
7306 case BFD_RELOC_386_TLS_GOTIE:
7307 case BFD_RELOC_386_TLS_GOTDESC:
7308 case BFD_RELOC_X86_64_TLSGD:
7309 case BFD_RELOC_X86_64_TLSLD:
7310 case BFD_RELOC_X86_64_GOTTPOFF:
7311 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7312 value = 0; /* Fully resolved at runtime. No addend. */
7314 case BFD_RELOC_386_TLS_LE:
7315 case BFD_RELOC_386_TLS_LDO_32:
7316 case BFD_RELOC_386_TLS_LE_32:
7317 case BFD_RELOC_X86_64_DTPOFF32:
7318 case BFD_RELOC_X86_64_DTPOFF64:
7319 case BFD_RELOC_X86_64_TPOFF32:
7320 case BFD_RELOC_X86_64_TPOFF64:
7321 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7324 case BFD_RELOC_386_TLS_DESC_CALL:
7325 case BFD_RELOC_X86_64_TLSDESC_CALL:
7326 value = 0; /* Fully resolved at runtime. No addend. */
7327 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7331 case BFD_RELOC_386_GOT32:
7332 case BFD_RELOC_X86_64_GOT32:
7333 value = 0; /* Fully resolved at runtime. No addend. */
7336 case BFD_RELOC_VTABLE_INHERIT:
7337 case BFD_RELOC_VTABLE_ENTRY:
7344 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7346 #endif /* !defined (TE_Mach) */
7348 /* Are we finished with this relocation now? */
7349 if (fixP->fx_addsy == NULL)
7351 #if defined (OBJ_COFF) && defined (TE_PE)
7352 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7355 /* Remember value for tc_gen_reloc. */
7356 fixP->fx_addnumber = value;
7357 /* Clear out the frag for now. */
7361 else if (use_rela_relocations)
7363 fixP->fx_no_overflow = 1;
7364 /* Remember value for tc_gen_reloc. */
7365 fixP->fx_addnumber = value;
7369 md_number_to_chars (p, value, fixP->fx_size);
7373 md_atof (int type, char *litP, int *sizeP)
7375 /* This outputs the LITTLENUMs in REVERSE order;
7376 in accord with the bigendian 386. */
7377 return ieee_md_atof (type, litP, sizeP, FALSE);
7380 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
7383 output_invalid (int c)
7386 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7389 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7390 "(0x%x)", (unsigned char) c);
7391 return output_invalid_buf;
7394 /* REG_STRING starts *before* REGISTER_PREFIX. */
7396 static const reg_entry *
7397 parse_real_register (char *reg_string, char **end_op)
7399 char *s = reg_string;
7401 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7404 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7405 if (*s == REGISTER_PREFIX)
7408 if (is_space_char (*s))
7412 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
7414 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
7415 return (const reg_entry *) NULL;
7419 /* For naked regs, make sure that we are not dealing with an identifier.
7420 This prevents confusing an identifier like `eax_var' with register
7422 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7423 return (const reg_entry *) NULL;
7427 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7429 /* Handle floating point regs, allowing spaces in the (i) part. */
7430 if (r == i386_regtab /* %st is first entry of table */)
7432 if (is_space_char (*s))
7437 if (is_space_char (*s))
7439 if (*s >= '0' && *s <= '7')
7443 if (is_space_char (*s))
7448 r = hash_find (reg_hash, "st(0)");
7453 /* We have "%st(" then garbage. */
7454 return (const reg_entry *) NULL;
7458 if (r == NULL || allow_pseudo_reg)
7461 if (operand_type_all_zero (&r->reg_type))
7462 return (const reg_entry *) NULL;
7464 if ((r->reg_type.bitfield.reg32
7465 || r->reg_type.bitfield.sreg3
7466 || r->reg_type.bitfield.control
7467 || r->reg_type.bitfield.debug
7468 || r->reg_type.bitfield.test)
7469 && !cpu_arch_flags.bitfield.cpui386)
7470 return (const reg_entry *) NULL;
7472 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7473 return (const reg_entry *) NULL;
7475 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7476 return (const reg_entry *) NULL;
7478 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7479 return (const reg_entry *) NULL;
7481 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7482 if (!allow_index_reg
7483 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7484 return (const reg_entry *) NULL;
7486 if (((r->reg_flags & (RegRex64 | RegRex))
7487 || r->reg_type.bitfield.reg64)
7488 && (!cpu_arch_flags.bitfield.cpulm
7489 || !operand_type_equal (&r->reg_type, &control))
7490 && flag_code != CODE_64BIT)
7491 return (const reg_entry *) NULL;
7493 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7494 return (const reg_entry *) NULL;
7499 /* REG_STRING starts *before* REGISTER_PREFIX. */
7501 static const reg_entry *
7502 parse_register (char *reg_string, char **end_op)
7506 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7507 r = parse_real_register (reg_string, end_op);
7512 char *save = input_line_pointer;
7516 input_line_pointer = reg_string;
7517 c = get_symbol_end ();
7518 symbolP = symbol_find (reg_string);
7519 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7521 const expressionS *e = symbol_get_value_expression (symbolP);
7523 know (e->X_op == O_register);
7524 know (e->X_add_number >= 0
7525 && (valueT) e->X_add_number < i386_regtab_size);
7526 r = i386_regtab + e->X_add_number;
7527 *end_op = input_line_pointer;
7529 *input_line_pointer = c;
7530 input_line_pointer = save;
7536 i386_parse_name (char *name, expressionS *e, char *nextcharP)
7539 char *end = input_line_pointer;
7542 r = parse_register (name, &input_line_pointer);
7543 if (r && end <= input_line_pointer)
7545 *nextcharP = *input_line_pointer;
7546 *input_line_pointer = 0;
7547 e->X_op = O_register;
7548 e->X_add_number = r - i386_regtab;
7551 input_line_pointer = end;
7553 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
7557 md_operand (expressionS *e)
7562 switch (*input_line_pointer)
7564 case REGISTER_PREFIX:
7565 r = parse_real_register (input_line_pointer, &end);
7568 e->X_op = O_register;
7569 e->X_add_number = r - i386_regtab;
7570 input_line_pointer = end;
7575 gas_assert (intel_syntax);
7576 end = input_line_pointer++;
7578 if (*input_line_pointer == ']')
7580 ++input_line_pointer;
7581 e->X_op_symbol = make_expr_symbol (e);
7582 e->X_add_symbol = NULL;
7583 e->X_add_number = 0;
7589 input_line_pointer = end;
7596 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7597 const char *md_shortopts = "kVQ:sqn";
7599 const char *md_shortopts = "qn";
7602 #define OPTION_32 (OPTION_MD_BASE + 0)
7603 #define OPTION_64 (OPTION_MD_BASE + 1)
7604 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7605 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7606 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7607 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7608 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7609 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7610 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7611 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7612 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7613 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7615 struct option md_longopts[] =
7617 {"32", no_argument, NULL, OPTION_32},
7618 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7619 || defined (TE_PE) || defined (TE_PEP))
7620 {"64", no_argument, NULL, OPTION_64},
7622 {"divide", no_argument, NULL, OPTION_DIVIDE},
7623 {"march", required_argument, NULL, OPTION_MARCH},
7624 {"mtune", required_argument, NULL, OPTION_MTUNE},
7625 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7626 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7627 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7628 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7629 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
7630 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
7631 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7632 {NULL, no_argument, NULL, 0}
7634 size_t md_longopts_size = sizeof (md_longopts);
7637 md_parse_option (int c, char *arg)
7645 optimize_align_code = 0;
7652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7653 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7654 should be emitted or not. FIXME: Not implemented. */
7658 /* -V: SVR4 argument to print version ID. */
7660 print_version_id ();
7663 /* -k: Ignore for FreeBSD compatibility. */
7668 /* -s: On i386 Solaris, this tells the native assembler to use
7669 .stab instead of .stab.excl. We always use .stab anyhow. */
7672 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7673 || defined (TE_PE) || defined (TE_PEP))
7676 const char **list, **l;
7678 list = bfd_target_list ();
7679 for (l = list; *l != NULL; l++)
7680 if (CONST_STRNEQ (*l, "elf64-x86-64")
7681 || strcmp (*l, "coff-x86-64") == 0
7682 || strcmp (*l, "pe-x86-64") == 0
7683 || strcmp (*l, "pei-x86-64") == 0)
7685 default_arch = "x86_64";
7689 as_fatal (_("No compiled in support for x86_64"));
7696 default_arch = "i386";
7700 #ifdef SVR4_COMMENT_CHARS
7705 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7707 for (s = i386_comment_chars; *s != '\0'; s++)
7711 i386_comment_chars = n;
7717 arch = xstrdup (arg);
7721 as_fatal (_("Invalid -march= option: `%s'"), arg);
7722 next = strchr (arch, '+');
7725 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7727 if (strcmp (arch, cpu_arch [i].name) == 0)
7730 cpu_arch_name = cpu_arch[i].name;
7731 cpu_sub_arch_name = NULL;
7732 cpu_arch_flags = cpu_arch[i].flags;
7733 cpu_arch_isa = cpu_arch[i].type;
7734 cpu_arch_isa_flags = cpu_arch[i].flags;
7735 if (!cpu_arch_tune_set)
7737 cpu_arch_tune = cpu_arch_isa;
7738 cpu_arch_tune_flags = cpu_arch_isa_flags;
7742 else if (*cpu_arch [i].name == '.'
7743 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7745 /* ISA entension. */
7746 i386_cpu_flags flags;
7747 flags = cpu_flags_or (cpu_arch_flags,
7749 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
7751 if (cpu_sub_arch_name)
7753 char *name = cpu_sub_arch_name;
7754 cpu_sub_arch_name = concat (name,
7756 (const char *) NULL);
7760 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7761 cpu_arch_flags = flags;
7767 if (i >= ARRAY_SIZE (cpu_arch))
7768 as_fatal (_("Invalid -march= option: `%s'"), arg);
7772 while (next != NULL );
7777 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7778 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7780 if (strcmp (arg, cpu_arch [i].name) == 0)
7782 cpu_arch_tune_set = 1;
7783 cpu_arch_tune = cpu_arch [i].type;
7784 cpu_arch_tune_flags = cpu_arch[i].flags;
7788 if (i >= ARRAY_SIZE (cpu_arch))
7789 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7792 case OPTION_MMNEMONIC:
7793 if (strcasecmp (arg, "att") == 0)
7795 else if (strcasecmp (arg, "intel") == 0)
7798 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7801 case OPTION_MSYNTAX:
7802 if (strcasecmp (arg, "att") == 0)
7804 else if (strcasecmp (arg, "intel") == 0)
7807 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7810 case OPTION_MINDEX_REG:
7811 allow_index_reg = 1;
7814 case OPTION_MNAKED_REG:
7815 allow_naked_reg = 1;
7818 case OPTION_MOLD_GCC:
7822 case OPTION_MSSE2AVX:
7826 case OPTION_MSSE_CHECK:
7827 if (strcasecmp (arg, "error") == 0)
7828 sse_check = sse_check_error;
7829 else if (strcasecmp (arg, "warning") == 0)
7830 sse_check = sse_check_warning;
7831 else if (strcasecmp (arg, "none") == 0)
7832 sse_check = sse_check_none;
7834 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7844 md_show_usage (stream)
7847 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7848 fprintf (stream, _("\
7850 -V print assembler version number\n\
7853 fprintf (stream, _("\
7854 -n Do not optimize code alignment\n\
7855 -q quieten some warnings\n"));
7856 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7857 fprintf (stream, _("\
7860 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7861 || defined (TE_PE) || defined (TE_PEP))
7862 fprintf (stream, _("\
7863 --32/--64 generate 32bit/64bit code\n"));
7865 #ifdef SVR4_COMMENT_CHARS
7866 fprintf (stream, _("\
7867 --divide do not treat `/' as a comment character\n"));
7869 fprintf (stream, _("\
7870 --divide ignored\n"));
7872 fprintf (stream, _("\
7873 -march=CPU[,+EXTENSION...]\n\
7874 generate code for CPU and EXTENSION, CPU is one of:\n\
7875 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7876 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7877 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7878 generic32, generic64\n\
7879 EXTENSION is combination of:\n\
7880 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7881 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7882 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7883 svme, abm, padlock, fma4\n"));
7884 fprintf (stream, _("\
7885 -mtune=CPU optimize for CPU, CPU is one of:\n\
7886 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7887 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7888 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7889 generic32, generic64\n"));
7890 fprintf (stream, _("\
7891 -msse2avx encode SSE instructions with VEX prefix\n"));
7892 fprintf (stream, _("\
7893 -msse-check=[none|error|warning]\n\
7894 check SSE instructions\n"));
7895 fprintf (stream, _("\
7896 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7897 fprintf (stream, _("\
7898 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7899 fprintf (stream, _("\
7900 -mindex-reg support pseudo index registers\n"));
7901 fprintf (stream, _("\
7902 -mnaked-reg don't require `%%' prefix for registers\n"));
7903 fprintf (stream, _("\
7904 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7907 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7908 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7909 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
7911 /* Pick the target format to use. */
7914 i386_target_format (void)
7916 if (!strcmp (default_arch, "x86_64"))
7918 set_code_flag (CODE_64BIT);
7919 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7921 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7922 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7923 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7924 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7925 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7926 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7927 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
7928 cpu_arch_isa_flags.bitfield.cpummx= 1;
7929 cpu_arch_isa_flags.bitfield.cpusse = 1;
7930 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7932 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7934 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7935 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7936 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7937 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7938 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7939 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7940 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
7941 cpu_arch_tune_flags.bitfield.cpummx= 1;
7942 cpu_arch_tune_flags.bitfield.cpusse = 1;
7943 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7946 else if (!strcmp (default_arch, "i386"))
7948 set_code_flag (CODE_32BIT);
7949 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
7951 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7952 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7953 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7955 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
7957 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7958 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7959 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7963 as_fatal (_("Unknown architecture"));
7964 switch (OUTPUT_FLAVOR)
7966 #if defined (TE_PE) || defined (TE_PEP)
7967 case bfd_target_coff_flavour:
7968 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
7970 #ifdef OBJ_MAYBE_AOUT
7971 case bfd_target_aout_flavour:
7972 return AOUT_TARGET_FORMAT;
7974 #ifdef OBJ_MAYBE_COFF
7975 case bfd_target_coff_flavour:
7978 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7979 case bfd_target_elf_flavour:
7981 if (flag_code == CODE_64BIT)
7984 use_rela_relocations = 1;
7986 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
7989 #if defined (OBJ_MACH_O)
7990 case bfd_target_mach_o_flavour:
7991 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
7999 #endif /* OBJ_MAYBE_ more than one */
8001 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8003 i386_elf_emit_arch_note (void)
8005 if (IS_ELF && cpu_arch_name != NULL)
8008 asection *seg = now_seg;
8009 subsegT subseg = now_subseg;
8010 Elf_Internal_Note i_note;
8011 Elf_External_Note e_note;
8012 asection *note_secp;
8015 /* Create the .note section. */
8016 note_secp = subseg_new (".note", 0);
8017 bfd_set_section_flags (stdoutput,
8019 SEC_HAS_CONTENTS | SEC_READONLY);
8021 /* Process the arch string. */
8022 len = strlen (cpu_arch_name);
8024 i_note.namesz = len + 1;
8026 i_note.type = NT_ARCH;
8027 p = frag_more (sizeof (e_note.namesz));
8028 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8029 p = frag_more (sizeof (e_note.descsz));
8030 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8031 p = frag_more (sizeof (e_note.type));
8032 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8033 p = frag_more (len + 1);
8034 strcpy (p, cpu_arch_name);
8036 frag_align (2, 0, 0);
8038 subseg_set (seg, subseg);
8044 md_undefined_symbol (name)
8047 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8048 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8049 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8050 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
8054 if (symbol_find (name))
8055 as_bad (_("GOT already in symbol table"));
8056 GOT_symbol = symbol_new (name, undefined_section,
8057 (valueT) 0, &zero_address_frag);
8064 /* Round up a section size to the appropriate boundary. */
8067 md_section_align (segment, size)
8068 segT segment ATTRIBUTE_UNUSED;
8071 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8072 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8074 /* For a.out, force the section size to be aligned. If we don't do
8075 this, BFD will align it for us, but it will not write out the
8076 final bytes of the section. This may be a bug in BFD, but it is
8077 easier to fix it here since that is how the other a.out targets
8081 align = bfd_get_section_alignment (stdoutput, segment);
8082 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8089 /* On the i386, PC-relative offsets are relative to the start of the
8090 next instruction. That is, the address of the offset, plus its
8091 size, since the offset is always the last part of the insn. */
8094 md_pcrel_from (fixS *fixP)
8096 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8102 s_bss (int ignore ATTRIBUTE_UNUSED)
8106 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8108 obj_elf_section_change_hook ();
8110 temp = get_absolute_expression ();
8111 subseg_set (bss_section, (subsegT) temp);
8112 demand_empty_rest_of_line ();
8118 i386_validate_fix (fixS *fixp)
8120 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8122 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8126 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8131 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8133 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
8140 tc_gen_reloc (section, fixp)
8141 asection *section ATTRIBUTE_UNUSED;
8145 bfd_reloc_code_real_type code;
8147 switch (fixp->fx_r_type)
8149 case BFD_RELOC_X86_64_PLT32:
8150 case BFD_RELOC_X86_64_GOT32:
8151 case BFD_RELOC_X86_64_GOTPCREL:
8152 case BFD_RELOC_386_PLT32:
8153 case BFD_RELOC_386_GOT32:
8154 case BFD_RELOC_386_GOTOFF:
8155 case BFD_RELOC_386_GOTPC:
8156 case BFD_RELOC_386_TLS_GD:
8157 case BFD_RELOC_386_TLS_LDM:
8158 case BFD_RELOC_386_TLS_LDO_32:
8159 case BFD_RELOC_386_TLS_IE_32:
8160 case BFD_RELOC_386_TLS_IE:
8161 case BFD_RELOC_386_TLS_GOTIE:
8162 case BFD_RELOC_386_TLS_LE_32:
8163 case BFD_RELOC_386_TLS_LE:
8164 case BFD_RELOC_386_TLS_GOTDESC:
8165 case BFD_RELOC_386_TLS_DESC_CALL:
8166 case BFD_RELOC_X86_64_TLSGD:
8167 case BFD_RELOC_X86_64_TLSLD:
8168 case BFD_RELOC_X86_64_DTPOFF32:
8169 case BFD_RELOC_X86_64_DTPOFF64:
8170 case BFD_RELOC_X86_64_GOTTPOFF:
8171 case BFD_RELOC_X86_64_TPOFF32:
8172 case BFD_RELOC_X86_64_TPOFF64:
8173 case BFD_RELOC_X86_64_GOTOFF64:
8174 case BFD_RELOC_X86_64_GOTPC32:
8175 case BFD_RELOC_X86_64_GOT64:
8176 case BFD_RELOC_X86_64_GOTPCREL64:
8177 case BFD_RELOC_X86_64_GOTPC64:
8178 case BFD_RELOC_X86_64_GOTPLT64:
8179 case BFD_RELOC_X86_64_PLTOFF64:
8180 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8181 case BFD_RELOC_X86_64_TLSDESC_CALL:
8183 case BFD_RELOC_VTABLE_ENTRY:
8184 case BFD_RELOC_VTABLE_INHERIT:
8186 case BFD_RELOC_32_SECREL:
8188 code = fixp->fx_r_type;
8190 case BFD_RELOC_X86_64_32S:
8191 if (!fixp->fx_pcrel)
8193 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8194 code = fixp->fx_r_type;
8200 switch (fixp->fx_size)
8203 as_bad_where (fixp->fx_file, fixp->fx_line,
8204 _("can not do %d byte pc-relative relocation"),
8206 code = BFD_RELOC_32_PCREL;
8208 case 1: code = BFD_RELOC_8_PCREL; break;
8209 case 2: code = BFD_RELOC_16_PCREL; break;
8210 case 4: code = BFD_RELOC_32_PCREL; break;
8212 case 8: code = BFD_RELOC_64_PCREL; break;
8218 switch (fixp->fx_size)
8221 as_bad_where (fixp->fx_file, fixp->fx_line,
8222 _("can not do %d byte relocation"),
8224 code = BFD_RELOC_32;
8226 case 1: code = BFD_RELOC_8; break;
8227 case 2: code = BFD_RELOC_16; break;
8228 case 4: code = BFD_RELOC_32; break;
8230 case 8: code = BFD_RELOC_64; break;
8237 if ((code == BFD_RELOC_32
8238 || code == BFD_RELOC_32_PCREL
8239 || code == BFD_RELOC_X86_64_32S)
8241 && fixp->fx_addsy == GOT_symbol)
8244 code = BFD_RELOC_386_GOTPC;
8246 code = BFD_RELOC_X86_64_GOTPC32;
8248 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8250 && fixp->fx_addsy == GOT_symbol)
8252 code = BFD_RELOC_X86_64_GOTPC64;
8255 rel = (arelent *) xmalloc (sizeof (arelent));
8256 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8257 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
8259 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
8261 if (!use_rela_relocations)
8263 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8264 vtable entry to be used in the relocation's section offset. */
8265 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8266 rel->address = fixp->fx_offset;
8267 #if defined (OBJ_COFF) && defined (TE_PE)
8268 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8269 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8274 /* Use the rela in 64bit mode. */
8277 if (!fixp->fx_pcrel)
8278 rel->addend = fixp->fx_offset;
8282 case BFD_RELOC_X86_64_PLT32:
8283 case BFD_RELOC_X86_64_GOT32:
8284 case BFD_RELOC_X86_64_GOTPCREL:
8285 case BFD_RELOC_X86_64_TLSGD:
8286 case BFD_RELOC_X86_64_TLSLD:
8287 case BFD_RELOC_X86_64_GOTTPOFF:
8288 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8289 case BFD_RELOC_X86_64_TLSDESC_CALL:
8290 rel->addend = fixp->fx_offset - fixp->fx_size;
8293 rel->addend = (section->vma
8295 + fixp->fx_addnumber
8296 + md_pcrel_from (fixp));
8301 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8302 if (rel->howto == NULL)
8304 as_bad_where (fixp->fx_file, fixp->fx_line,
8305 _("cannot represent relocation type %s"),
8306 bfd_get_reloc_code_name (code));
8307 /* Set howto to a garbage value so that we can keep going. */
8308 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8309 gas_assert (rel->howto != NULL);
8315 #include "tc-i386-intel.c"
8318 tc_x86_parse_to_dw2regnum (expressionS *exp)
8320 int saved_naked_reg;
8321 char saved_register_dot;
8323 saved_naked_reg = allow_naked_reg;
8324 allow_naked_reg = 1;
8325 saved_register_dot = register_chars['.'];
8326 register_chars['.'] = '.';
8327 allow_pseudo_reg = 1;
8328 expression_and_evaluate (exp);
8329 allow_pseudo_reg = 0;
8330 register_chars['.'] = saved_register_dot;
8331 allow_naked_reg = saved_naked_reg;
8333 if (exp->X_op == O_register && exp->X_add_number >= 0)
8335 if ((addressT) exp->X_add_number < i386_regtab_size)
8337 exp->X_op = O_constant;
8338 exp->X_add_number = i386_regtab[exp->X_add_number]
8339 .dw2_regnum[flag_code >> 1];
8342 exp->X_op = O_illegal;
8347 tc_x86_frame_initial_instructions (void)
8349 static unsigned int sp_regno[2];
8351 if (!sp_regno[flag_code >> 1])
8353 char *saved_input = input_line_pointer;
8354 char sp[][4] = {"esp", "rsp"};
8357 input_line_pointer = sp[flag_code >> 1];
8358 tc_x86_parse_to_dw2regnum (&exp);
8359 gas_assert (exp.X_op == O_constant);
8360 sp_regno[flag_code >> 1] = exp.X_add_number;
8361 input_line_pointer = saved_input;
8364 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
8365 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
8369 i386_elf_section_type (const char *str, size_t len)
8371 if (flag_code == CODE_64BIT
8372 && len == sizeof ("unwind") - 1
8373 && strncmp (str, "unwind", 6) == 0)
8374 return SHT_X86_64_UNWIND;
8381 i386_solaris_fix_up_eh_frame (segT sec)
8383 if (flag_code == CODE_64BIT)
8384 elf_section_type (sec) = SHT_X86_64_UNWIND;
8390 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8394 expr.X_op = O_secrel;
8395 expr.X_add_symbol = symbol;
8396 expr.X_add_number = 0;
8397 emit_expr (&expr, size);
8401 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8402 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8405 x86_64_section_letter (int letter, char **ptr_msg)
8407 if (flag_code == CODE_64BIT)
8410 return SHF_X86_64_LARGE;
8412 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8415 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
8420 x86_64_section_word (char *str, size_t len)
8422 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
8423 return SHF_X86_64_LARGE;
8429 handle_large_common (int small ATTRIBUTE_UNUSED)
8431 if (flag_code != CODE_64BIT)
8433 s_comm_internal (0, elf_common_parse);
8434 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8438 static segT lbss_section;
8439 asection *saved_com_section_ptr = elf_com_section_ptr;
8440 asection *saved_bss_section = bss_section;
8442 if (lbss_section == NULL)
8444 flagword applicable;
8446 subsegT subseg = now_subseg;
8448 /* The .lbss section is for local .largecomm symbols. */
8449 lbss_section = subseg_new (".lbss", 0);
8450 applicable = bfd_applicable_section_flags (stdoutput);
8451 bfd_set_section_flags (stdoutput, lbss_section,
8452 applicable & SEC_ALLOC);
8453 seg_info (lbss_section)->bss = 1;
8455 subseg_set (seg, subseg);
8458 elf_com_section_ptr = &_bfd_elf_large_com_section;
8459 bss_section = lbss_section;
8461 s_comm_internal (0, elf_common_parse);
8463 elf_com_section_ptr = saved_com_section_ptr;
8464 bss_section = saved_bss_section;
8467 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */