1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2014 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
29 #include "safe-ctype.h"
31 #include "dwarf2dbg.h"
32 #include "dw2gencfi.h"
33 #include "elf/x86-64.h"
34 #include "opcodes/i386-init.h"
36 #ifndef REGISTER_WARNINGS
37 #define REGISTER_WARNINGS 1
40 #ifndef INFER_ADDR_PREFIX
41 #define INFER_ADDR_PREFIX 1
45 #define DEFAULT_ARCH "i386"
50 #define INLINE __inline__
56 /* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
66 #define HLE_PREFIX REP_PREFIX
67 #define BND_PREFIX REP_PREFIX
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 #define ZMMWORD_MNEM_SUFFIX 'z'
87 /* Intel Syntax. Use a non-ascii letter since since it never appears
89 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
91 #define END_OF_INSN '\0'
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
102 const insn_template *start;
103 const insn_template *end;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
116 /* x86-64 extension prefix. */
117 typedef int rex_byte;
119 /* 386 opcode byte to code indirect addressing. */
128 /* x86 arch names, types and features */
131 const char *name; /* arch name */
132 unsigned int len; /* arch string length */
133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
135 unsigned int skip; /* show_arch should skip this. */
136 unsigned int negated; /* turn off indicated flags. */
140 static void update_code_flag (int, int);
141 static void set_code_flag (int);
142 static void set_16bit_gcc_code_flag (int);
143 static void set_intel_syntax (int);
144 static void set_intel_mnemonic (int);
145 static void set_allow_index_reg (int);
146 static void set_check (int);
147 static void set_cpu_arch (int);
149 static void pe_directive_secrel (int);
151 static void signed_cons (int);
152 static char *output_invalid (int c);
153 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
155 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
157 static int i386_att_operand (char *);
158 static int i386_intel_operand (char *, int);
159 static int i386_intel_simplify (expressionS *);
160 static int i386_intel_parse_name (const char *, expressionS *);
161 static const reg_entry *parse_register (char *, char **);
162 static char *parse_insn (char *, char *);
163 static char *parse_operands (char *, const char *);
164 static void swap_operands (void);
165 static void swap_2_operands (int, int);
166 static void optimize_imm (void);
167 static void optimize_disp (void);
168 static const insn_template *match_template (void);
169 static int check_string (void);
170 static int process_suffix (void);
171 static int check_byte_reg (void);
172 static int check_long_reg (void);
173 static int check_qword_reg (void);
174 static int check_word_reg (void);
175 static int finalize_imm (void);
176 static int process_operands (void);
177 static const seg_entry *build_modrm_byte (void);
178 static void output_insn (void);
179 static void output_imm (fragS *, offsetT);
180 static void output_disp (fragS *, offsetT);
182 static void s_bss (int);
184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
185 static void handle_large_common (int small ATTRIBUTE_UNUSED);
188 static const char *default_arch = DEFAULT_ARCH;
190 /* This struct describes rounding control and SAE in the instruction. */
204 static struct RC_Operation rc_op;
206 /* The struct describes masking, applied to OPERAND in the instruction.
207 MASK is a pointer to the corresponding mask register. ZEROING tells
208 whether merging or zeroing mask is used. */
209 struct Mask_Operation
211 const reg_entry *mask;
212 unsigned int zeroing;
213 /* The operand where this operation is associated. */
217 static struct Mask_Operation mask_op;
219 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
221 struct Broadcast_Operation
223 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
226 /* Index of broadcasted operand. */
230 static struct Broadcast_Operation broadcast_op;
235 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
236 unsigned char bytes[4];
238 /* Destination or source register specifier. */
239 const reg_entry *register_specifier;
242 /* 'md_assemble ()' gathers together information and puts it into a
249 const reg_entry *regs;
254 operand_size_mismatch,
255 operand_type_mismatch,
256 register_type_mismatch,
257 number_of_operands_mismatch,
258 invalid_instruction_suffix,
261 unsupported_with_intel_mnemonic,
264 invalid_vsib_address,
265 invalid_vector_register_set,
266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_not_on_src_operand,
271 mask_not_on_destination,
274 rc_sae_operand_not_last_imm,
275 invalid_register_operand,
281 /* TM holds the template for the insn were currently assembling. */
284 /* SUFFIX holds the instruction size suffix for byte, word, dword
285 or qword, if given. */
288 /* OPERANDS gives the number of given operands. */
289 unsigned int operands;
291 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
292 of given register, displacement, memory operands and immediate
294 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
296 /* TYPES [i] is the type (see above #defines) which tells us how to
297 use OP[i] for the corresponding operand. */
298 i386_operand_type types[MAX_OPERANDS];
300 /* Displacement expression, immediate expression, or register for each
302 union i386_op op[MAX_OPERANDS];
304 /* Flags for operands. */
305 unsigned int flags[MAX_OPERANDS];
306 #define Operand_PCrel 1
308 /* Relocation type for operand */
309 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
311 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
312 the base index byte below. */
313 const reg_entry *base_reg;
314 const reg_entry *index_reg;
315 unsigned int log2_scale_factor;
317 /* SEG gives the seg_entries of this insn. They are zero unless
318 explicit segment overrides are given. */
319 const seg_entry *seg[2];
321 /* PREFIX holds all the given prefix opcodes (usually null).
322 PREFIXES is the number of prefix opcodes. */
323 unsigned int prefixes;
324 unsigned char prefix[MAX_PREFIXES];
326 /* RM and SIB are the modrm byte and the sib byte where the
327 addressing modes of this insn are encoded. */
334 /* Masking attributes. */
335 struct Mask_Operation *mask;
337 /* Rounding control and SAE attributes. */
338 struct RC_Operation *rounding;
340 /* Broadcasting attributes. */
341 struct Broadcast_Operation *broadcast;
343 /* Compressed disp8*N attribute. */
344 unsigned int memshift;
346 /* Swap operand in encoding. */
347 unsigned int swap_operand;
349 /* Prefer 8bit or 32bit displacement in encoding. */
352 disp_encoding_default = 0,
358 const char *rep_prefix;
361 const char *hle_prefix;
363 /* Have BND prefix. */
364 const char *bnd_prefix;
366 /* Need VREX to support upper 16 registers. */
370 enum i386_error error;
373 typedef struct _i386_insn i386_insn;
375 /* Link RC type with corresponding string, that'll be looked for in
384 static const struct RC_name RC_NamesTable[] =
386 { rne, STRING_COMMA_LEN ("rn-sae") },
387 { rd, STRING_COMMA_LEN ("rd-sae") },
388 { ru, STRING_COMMA_LEN ("ru-sae") },
389 { rz, STRING_COMMA_LEN ("rz-sae") },
390 { saeonly, STRING_COMMA_LEN ("sae") },
393 /* List of chars besides those in app.c:symbol_chars that can start an
394 operand. Used to prevent the scrubber eating vital white-space. */
395 const char extra_symbol_chars[] = "*%-([{"
404 #if (defined (TE_I386AIX) \
405 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
406 && !defined (TE_GNU) \
407 && !defined (TE_LINUX) \
408 && !defined (TE_NACL) \
409 && !defined (TE_NETWARE) \
410 && !defined (TE_FreeBSD) \
411 && !defined (TE_DragonFly) \
412 && !defined (TE_NetBSD)))
413 /* This array holds the chars that always start a comment. If the
414 pre-processor is disabled, these aren't very useful. The option
415 --divide will remove '/' from this list. */
416 const char *i386_comment_chars = "#/";
417 #define SVR4_COMMENT_CHARS 1
418 #define PREFIX_SEPARATOR '\\'
421 const char *i386_comment_chars = "#";
422 #define PREFIX_SEPARATOR '/'
425 /* This array holds the chars that only start a comment at the beginning of
426 a line. If the line seems to have the form '# 123 filename'
427 .line and .file directives will appear in the pre-processed output.
428 Note that input_file.c hand checks for '#' at the beginning of the
429 first line of the input file. This is because the compiler outputs
430 #NO_APP at the beginning of its output.
431 Also note that comments started like this one will always work if
432 '/' isn't otherwise defined. */
433 const char line_comment_chars[] = "#/";
435 const char line_separator_chars[] = ";";
437 /* Chars that can be used to separate mant from exp in floating point
439 const char EXP_CHARS[] = "eE";
441 /* Chars that mean this number is a floating point constant
444 const char FLT_CHARS[] = "fFdDxX";
446 /* Tables for lexical analysis. */
447 static char mnemonic_chars[256];
448 static char register_chars[256];
449 static char operand_chars[256];
450 static char identifier_chars[256];
451 static char digit_chars[256];
453 /* Lexical macros. */
454 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
455 #define is_operand_char(x) (operand_chars[(unsigned char) x])
456 #define is_register_char(x) (register_chars[(unsigned char) x])
457 #define is_space_char(x) ((x) == ' ')
458 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
459 #define is_digit_char(x) (digit_chars[(unsigned char) x])
461 /* All non-digit non-letter characters that may occur in an operand. */
462 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
464 /* md_assemble() always leaves the strings it's passed unaltered. To
465 effect this we maintain a stack of saved characters that we've smashed
466 with '\0's (indicating end of strings for various sub-fields of the
467 assembler instruction). */
468 static char save_stack[32];
469 static char *save_stack_p;
470 #define END_STRING_AND_SAVE(s) \
471 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
472 #define RESTORE_END_STRING(s) \
473 do { *(s) = *--save_stack_p; } while (0)
475 /* The instruction we're assembling. */
478 /* Possible templates for current insn. */
479 static const templates *current_templates;
481 /* Per instruction expressionS buffers: max displacements & immediates. */
482 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
483 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
485 /* Current operand we are working on. */
486 static int this_operand = -1;
488 /* We support four different modes. FLAG_CODE variable is used to distinguish
496 static enum flag_code flag_code;
497 static unsigned int object_64bit;
498 static unsigned int disallow_64bit_reloc;
499 static int use_rela_relocations = 0;
501 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
502 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
503 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
505 /* The ELF ABI to use. */
513 static enum x86_elf_abi x86_elf_abi = I386_ABI;
516 #if defined (TE_PE) || defined (TE_PEP)
517 /* Use big object file format. */
518 static int use_big_obj = 0;
521 /* 1 for intel syntax,
523 static int intel_syntax = 0;
525 /* 1 for intel mnemonic,
526 0 if att mnemonic. */
527 static int intel_mnemonic = !SYSV386_COMPAT;
529 /* 1 if support old (<= 2.8.1) versions of gcc. */
530 static int old_gcc = OLDGCC_COMPAT;
532 /* 1 if pseudo registers are permitted. */
533 static int allow_pseudo_reg = 0;
535 /* 1 if register prefix % not required. */
536 static int allow_naked_reg = 0;
538 /* 1 if the assembler should add BND prefix for all control-tranferring
539 instructions supporting it, even if this prefix wasn't specified
541 static int add_bnd_prefix = 0;
543 /* 1 if pseudo index register, eiz/riz, is allowed . */
544 static int allow_index_reg = 0;
546 /* 1 if the assembler should ignore LOCK prefix, even if it was
547 specified explicitly. */
548 static int omit_lock_prefix = 0;
550 static enum check_kind
556 sse_check, operand_check = check_warning;
558 /* Register prefix used for error message. */
559 static const char *register_prefix = "%";
561 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
562 leave, push, and pop instructions so that gcc has the same stack
563 frame as in 32 bit mode. */
564 static char stackop_size = '\0';
566 /* Non-zero to optimize code alignment. */
567 int optimize_align_code = 1;
569 /* Non-zero to quieten some warnings. */
570 static int quiet_warnings = 0;
573 static const char *cpu_arch_name = NULL;
574 static char *cpu_sub_arch_name = NULL;
576 /* CPU feature flags. */
577 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
579 /* If we have selected a cpu we are generating instructions for. */
580 static int cpu_arch_tune_set = 0;
582 /* Cpu we are generating instructions for. */
583 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
585 /* CPU feature flags of cpu we are generating instructions for. */
586 static i386_cpu_flags cpu_arch_tune_flags;
588 /* CPU instruction set architecture used. */
589 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
591 /* CPU feature flags of instruction set architecture used. */
592 i386_cpu_flags cpu_arch_isa_flags;
594 /* If set, conditional jumps are not automatically promoted to handle
595 larger than a byte offset. */
596 static unsigned int no_cond_jump_promotion = 0;
598 /* Encode SSE instructions with VEX prefix. */
599 static unsigned int sse2avx;
601 /* Encode scalar AVX instructions with specific vector length. */
608 /* Encode scalar EVEX LIG instructions with specific vector length. */
616 /* Encode EVEX WIG instructions with specific evex.w. */
623 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
624 static enum rc_type evexrcig = rne;
626 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
627 static symbolS *GOT_symbol;
629 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
630 unsigned int x86_dwarf2_return_column;
632 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
633 int x86_cie_data_alignment;
635 /* Interface to relax_segment.
636 There are 3 major relax states for 386 jump insns because the
637 different types of jumps add different sizes to frags when we're
638 figuring out what sort of jump to choose to reach a given label. */
641 #define UNCOND_JUMP 0
643 #define COND_JUMP86 2
648 #define SMALL16 (SMALL | CODE16)
650 #define BIG16 (BIG | CODE16)
654 #define INLINE __inline__
660 #define ENCODE_RELAX_STATE(type, size) \
661 ((relax_substateT) (((type) << 2) | (size)))
662 #define TYPE_FROM_RELAX_STATE(s) \
664 #define DISP_SIZE_FROM_RELAX_STATE(s) \
665 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
667 /* This table is used by relax_frag to promote short jumps to long
668 ones where necessary. SMALL (short) jumps may be promoted to BIG
669 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
670 don't allow a short jump in a 32 bit code segment to be promoted to
671 a 16 bit offset jump because it's slower (requires data size
672 prefix), and doesn't work, unless the destination is in the bottom
673 64k of the code segment (The top 16 bits of eip are zeroed). */
675 const relax_typeS md_relax_table[] =
678 1) most positive reach of this state,
679 2) most negative reach of this state,
680 3) how many bytes this mode will have in the variable part of the frag
681 4) which index into the table to try if we can't fit into this one. */
683 /* UNCOND_JUMP states. */
684 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
686 /* dword jmp adds 4 bytes to frag:
687 0 extra opcode bytes, 4 displacement bytes. */
689 /* word jmp adds 2 byte2 to frag:
690 0 extra opcode bytes, 2 displacement bytes. */
693 /* COND_JUMP states. */
694 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
696 /* dword conditionals adds 5 bytes to frag:
697 1 extra opcode byte, 4 displacement bytes. */
699 /* word conditionals add 3 bytes to frag:
700 1 extra opcode byte, 2 displacement bytes. */
703 /* COND_JUMP86 states. */
704 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
706 /* dword conditionals adds 5 bytes to frag:
707 1 extra opcode byte, 4 displacement bytes. */
709 /* word conditionals add 4 bytes to frag:
710 1 displacement byte and a 3 byte long branch insn. */
714 static const arch_entry cpu_arch[] =
716 /* Do not replace the first two entries - i386_target_format()
717 relies on them being there in this order. */
718 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
719 CPU_GENERIC32_FLAGS, 0, 0 },
720 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
721 CPU_GENERIC64_FLAGS, 0, 0 },
722 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
723 CPU_NONE_FLAGS, 0, 0 },
724 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
725 CPU_I186_FLAGS, 0, 0 },
726 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
727 CPU_I286_FLAGS, 0, 0 },
728 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
729 CPU_I386_FLAGS, 0, 0 },
730 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
731 CPU_I486_FLAGS, 0, 0 },
732 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
733 CPU_I586_FLAGS, 0, 0 },
734 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
735 CPU_I686_FLAGS, 0, 0 },
736 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
737 CPU_I586_FLAGS, 0, 0 },
738 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
739 CPU_PENTIUMPRO_FLAGS, 0, 0 },
740 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
741 CPU_P2_FLAGS, 0, 0 },
742 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
743 CPU_P3_FLAGS, 0, 0 },
744 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
745 CPU_P4_FLAGS, 0, 0 },
746 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
747 CPU_CORE_FLAGS, 0, 0 },
748 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
749 CPU_NOCONA_FLAGS, 0, 0 },
750 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
751 CPU_CORE_FLAGS, 1, 0 },
752 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
753 CPU_CORE_FLAGS, 0, 0 },
754 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
755 CPU_CORE2_FLAGS, 1, 0 },
756 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
757 CPU_CORE2_FLAGS, 0, 0 },
758 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
759 CPU_COREI7_FLAGS, 0, 0 },
760 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
761 CPU_L1OM_FLAGS, 0, 0 },
762 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
763 CPU_K1OM_FLAGS, 0, 0 },
764 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
765 CPU_K6_FLAGS, 0, 0 },
766 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
767 CPU_K6_2_FLAGS, 0, 0 },
768 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
769 CPU_ATHLON_FLAGS, 0, 0 },
770 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
771 CPU_K8_FLAGS, 1, 0 },
772 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
773 CPU_K8_FLAGS, 0, 0 },
774 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
775 CPU_K8_FLAGS, 0, 0 },
776 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
777 CPU_AMDFAM10_FLAGS, 0, 0 },
778 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
779 CPU_BDVER1_FLAGS, 0, 0 },
780 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
781 CPU_BDVER2_FLAGS, 0, 0 },
782 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
783 CPU_BDVER3_FLAGS, 0, 0 },
784 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
785 CPU_BDVER4_FLAGS, 0, 0 },
786 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
787 CPU_BTVER1_FLAGS, 0, 0 },
788 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
789 CPU_BTVER2_FLAGS, 0, 0 },
790 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
791 CPU_8087_FLAGS, 0, 0 },
792 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
793 CPU_287_FLAGS, 0, 0 },
794 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
795 CPU_387_FLAGS, 0, 0 },
796 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
797 CPU_ANY87_FLAGS, 0, 1 },
798 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
799 CPU_MMX_FLAGS, 0, 0 },
800 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
801 CPU_3DNOWA_FLAGS, 0, 1 },
802 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
803 CPU_SSE_FLAGS, 0, 0 },
804 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
805 CPU_SSE2_FLAGS, 0, 0 },
806 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
807 CPU_SSE3_FLAGS, 0, 0 },
808 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
809 CPU_SSSE3_FLAGS, 0, 0 },
810 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
811 CPU_SSE4_1_FLAGS, 0, 0 },
812 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
813 CPU_SSE4_2_FLAGS, 0, 0 },
814 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
815 CPU_SSE4_2_FLAGS, 0, 0 },
816 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
817 CPU_ANY_SSE_FLAGS, 0, 1 },
818 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
819 CPU_AVX_FLAGS, 0, 0 },
820 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
821 CPU_AVX2_FLAGS, 0, 0 },
822 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
823 CPU_AVX512F_FLAGS, 0, 0 },
824 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
825 CPU_AVX512CD_FLAGS, 0, 0 },
826 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
827 CPU_AVX512ER_FLAGS, 0, 0 },
828 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
829 CPU_AVX512PF_FLAGS, 0, 0 },
830 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
831 CPU_AVX512DQ_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
833 CPU_AVX512BW_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
835 CPU_AVX512VL_FLAGS, 0, 0 },
836 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
837 CPU_ANY_AVX_FLAGS, 0, 1 },
838 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
839 CPU_VMX_FLAGS, 0, 0 },
840 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
841 CPU_VMFUNC_FLAGS, 0, 0 },
842 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
843 CPU_SMX_FLAGS, 0, 0 },
844 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
845 CPU_XSAVE_FLAGS, 0, 0 },
846 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
847 CPU_XSAVEOPT_FLAGS, 0, 0 },
848 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
849 CPU_XSAVEC_FLAGS, 0, 0 },
850 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
851 CPU_XSAVES_FLAGS, 0, 0 },
852 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
853 CPU_AES_FLAGS, 0, 0 },
854 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
855 CPU_PCLMUL_FLAGS, 0, 0 },
856 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
857 CPU_PCLMUL_FLAGS, 1, 0 },
858 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
859 CPU_FSGSBASE_FLAGS, 0, 0 },
860 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
861 CPU_RDRND_FLAGS, 0, 0 },
862 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
863 CPU_F16C_FLAGS, 0, 0 },
864 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
865 CPU_BMI2_FLAGS, 0, 0 },
866 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
867 CPU_FMA_FLAGS, 0, 0 },
868 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
869 CPU_FMA4_FLAGS, 0, 0 },
870 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
871 CPU_XOP_FLAGS, 0, 0 },
872 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
873 CPU_LWP_FLAGS, 0, 0 },
874 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
875 CPU_MOVBE_FLAGS, 0, 0 },
876 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
877 CPU_CX16_FLAGS, 0, 0 },
878 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
879 CPU_EPT_FLAGS, 0, 0 },
880 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
881 CPU_LZCNT_FLAGS, 0, 0 },
882 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
883 CPU_HLE_FLAGS, 0, 0 },
884 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
885 CPU_RTM_FLAGS, 0, 0 },
886 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
887 CPU_INVPCID_FLAGS, 0, 0 },
888 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
889 CPU_CLFLUSH_FLAGS, 0, 0 },
890 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
891 CPU_NOP_FLAGS, 0, 0 },
892 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
893 CPU_SYSCALL_FLAGS, 0, 0 },
894 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
895 CPU_RDTSCP_FLAGS, 0, 0 },
896 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
897 CPU_3DNOW_FLAGS, 0, 0 },
898 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
899 CPU_3DNOWA_FLAGS, 0, 0 },
900 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
901 CPU_PADLOCK_FLAGS, 0, 0 },
902 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
903 CPU_SVME_FLAGS, 1, 0 },
904 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
905 CPU_SVME_FLAGS, 0, 0 },
906 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
907 CPU_SSE4A_FLAGS, 0, 0 },
908 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
909 CPU_ABM_FLAGS, 0, 0 },
910 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
911 CPU_BMI_FLAGS, 0, 0 },
912 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
913 CPU_TBM_FLAGS, 0, 0 },
914 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
915 CPU_ADX_FLAGS, 0, 0 },
916 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
917 CPU_RDSEED_FLAGS, 0, 0 },
918 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
919 CPU_PRFCHW_FLAGS, 0, 0 },
920 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
921 CPU_SMAP_FLAGS, 0, 0 },
922 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
923 CPU_MPX_FLAGS, 0, 0 },
924 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
925 CPU_SHA_FLAGS, 0, 0 },
926 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
927 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
928 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
929 CPU_PREFETCHWT1_FLAGS, 0, 0 },
930 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
931 CPU_SE1_FLAGS, 0, 0 },
932 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
933 CPU_CLWB_FLAGS, 0, 0 },
934 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
935 CPU_PCOMMIT_FLAGS, 0, 0 },
936 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
937 CPU_AVX512IFMA_FLAGS, 0, 0 },
941 /* Like s_lcomm_internal in gas/read.c but the alignment string
942 is allowed to be optional. */
945 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
952 && *input_line_pointer == ',')
954 align = parse_align (needs_align - 1);
956 if (align == (addressT) -1)
971 bss_alloc (symbolP, size, align);
976 pe_lcomm (int needs_align)
978 s_comm_internal (needs_align * 2, pe_lcomm_internal);
982 const pseudo_typeS md_pseudo_table[] =
984 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
985 {"align", s_align_bytes, 0},
987 {"align", s_align_ptwo, 0},
989 {"arch", set_cpu_arch, 0},
993 {"lcomm", pe_lcomm, 1},
995 {"ffloat", float_cons, 'f'},
996 {"dfloat", float_cons, 'd'},
997 {"tfloat", float_cons, 'x'},
999 {"slong", signed_cons, 4},
1000 {"noopt", s_ignore, 0},
1001 {"optim", s_ignore, 0},
1002 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1003 {"code16", set_code_flag, CODE_16BIT},
1004 {"code32", set_code_flag, CODE_32BIT},
1005 {"code64", set_code_flag, CODE_64BIT},
1006 {"intel_syntax", set_intel_syntax, 1},
1007 {"att_syntax", set_intel_syntax, 0},
1008 {"intel_mnemonic", set_intel_mnemonic, 1},
1009 {"att_mnemonic", set_intel_mnemonic, 0},
1010 {"allow_index_reg", set_allow_index_reg, 1},
1011 {"disallow_index_reg", set_allow_index_reg, 0},
1012 {"sse_check", set_check, 0},
1013 {"operand_check", set_check, 1},
1014 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1015 {"largecomm", handle_large_common, 0},
1017 {"file", (void (*) (int)) dwarf2_directive_file, 0},
1018 {"loc", dwarf2_directive_loc, 0},
1019 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
1022 {"secrel32", pe_directive_secrel, 0},
1027 /* For interface with expression (). */
1028 extern char *input_line_pointer;
1030 /* Hash table for instruction mnemonic lookup. */
1031 static struct hash_control *op_hash;
1033 /* Hash table for register lookup. */
1034 static struct hash_control *reg_hash;
1037 i386_align_code (fragS *fragP, int count)
1039 /* Various efficient no-op patterns for aligning code labels.
1040 Note: Don't try to assemble the instructions in the comments.
1041 0L and 0w are not legal. */
1042 static const char f32_1[] =
1044 static const char f32_2[] =
1045 {0x66,0x90}; /* xchg %ax,%ax */
1046 static const char f32_3[] =
1047 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1048 static const char f32_4[] =
1049 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1050 static const char f32_5[] =
1052 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1053 static const char f32_6[] =
1054 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1055 static const char f32_7[] =
1056 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1057 static const char f32_8[] =
1059 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1060 static const char f32_9[] =
1061 {0x89,0xf6, /* movl %esi,%esi */
1062 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1063 static const char f32_10[] =
1064 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1065 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1066 static const char f32_11[] =
1067 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1068 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1069 static const char f32_12[] =
1070 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1071 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1072 static const char f32_13[] =
1073 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_14[] =
1076 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f16_3[] =
1079 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1080 static const char f16_4[] =
1081 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1082 static const char f16_5[] =
1084 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1085 static const char f16_6[] =
1086 {0x89,0xf6, /* mov %si,%si */
1087 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1088 static const char f16_7[] =
1089 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1090 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1091 static const char f16_8[] =
1092 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1093 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1094 static const char jump_31[] =
1095 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1096 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1097 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1098 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1099 static const char *const f32_patt[] = {
1100 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1101 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1103 static const char *const f16_patt[] = {
1104 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1106 /* nopl (%[re]ax) */
1107 static const char alt_3[] =
1109 /* nopl 0(%[re]ax) */
1110 static const char alt_4[] =
1111 {0x0f,0x1f,0x40,0x00};
1112 /* nopl 0(%[re]ax,%[re]ax,1) */
1113 static const char alt_5[] =
1114 {0x0f,0x1f,0x44,0x00,0x00};
1115 /* nopw 0(%[re]ax,%[re]ax,1) */
1116 static const char alt_6[] =
1117 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1118 /* nopl 0L(%[re]ax) */
1119 static const char alt_7[] =
1120 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1121 /* nopl 0L(%[re]ax,%[re]ax,1) */
1122 static const char alt_8[] =
1123 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 /* nopw 0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_9[] =
1126 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1127 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1128 static const char alt_10[] =
1129 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1131 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1132 static const char alt_long_11[] =
1134 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1137 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1138 static const char alt_long_12[] =
1141 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_long_13[] =
1150 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1155 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1156 static const char alt_long_14[] =
1161 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1168 static const char alt_long_15[] =
1174 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1175 /* nopl 0(%[re]ax,%[re]ax,1)
1176 nopw 0(%[re]ax,%[re]ax,1) */
1177 static const char alt_short_11[] =
1178 {0x0f,0x1f,0x44,0x00,0x00,
1179 0x66,0x0f,0x1f,0x44,0x00,0x00};
1180 /* nopw 0(%[re]ax,%[re]ax,1)
1181 nopw 0(%[re]ax,%[re]ax,1) */
1182 static const char alt_short_12[] =
1183 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1184 0x66,0x0f,0x1f,0x44,0x00,0x00};
1185 /* nopw 0(%[re]ax,%[re]ax,1)
1187 static const char alt_short_13[] =
1188 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1189 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1192 static const char alt_short_14[] =
1193 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1194 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1196 nopl 0L(%[re]ax,%[re]ax,1) */
1197 static const char alt_short_15[] =
1198 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1199 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1200 static const char *const alt_short_patt[] = {
1201 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1202 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1203 alt_short_14, alt_short_15
1205 static const char *const alt_long_patt[] = {
1206 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1207 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1208 alt_long_14, alt_long_15
1211 /* Only align for at least a positive non-zero boundary. */
1212 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1215 /* We need to decide which NOP sequence to use for 32bit and
1216 64bit. When -mtune= is used:
1218 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1219 PROCESSOR_GENERIC32, f32_patt will be used.
1220 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1221 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1222 PROCESSOR_GENERIC64, alt_long_patt will be used.
1223 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1224 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1227 When -mtune= isn't used, alt_long_patt will be used if
1228 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1231 When -march= or .arch is used, we can't use anything beyond
1232 cpu_arch_isa_flags. */
1234 if (flag_code == CODE_16BIT)
1238 memcpy (fragP->fr_literal + fragP->fr_fix,
1240 /* Adjust jump offset. */
1241 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1244 memcpy (fragP->fr_literal + fragP->fr_fix,
1245 f16_patt[count - 1], count);
1249 const char *const *patt = NULL;
1251 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1253 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1254 switch (cpu_arch_tune)
1256 case PROCESSOR_UNKNOWN:
1257 /* We use cpu_arch_isa_flags to check if we SHOULD
1258 optimize with nops. */
1259 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1260 patt = alt_long_patt;
1264 case PROCESSOR_PENTIUM4:
1265 case PROCESSOR_NOCONA:
1266 case PROCESSOR_CORE:
1267 case PROCESSOR_CORE2:
1268 case PROCESSOR_COREI7:
1269 case PROCESSOR_L1OM:
1270 case PROCESSOR_K1OM:
1271 case PROCESSOR_GENERIC64:
1272 patt = alt_long_patt;
1275 case PROCESSOR_ATHLON:
1277 case PROCESSOR_AMDFAM10:
1280 patt = alt_short_patt;
1282 case PROCESSOR_I386:
1283 case PROCESSOR_I486:
1284 case PROCESSOR_PENTIUM:
1285 case PROCESSOR_PENTIUMPRO:
1286 case PROCESSOR_GENERIC32:
1293 switch (fragP->tc_frag_data.tune)
1295 case PROCESSOR_UNKNOWN:
1296 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1297 PROCESSOR_UNKNOWN. */
1301 case PROCESSOR_I386:
1302 case PROCESSOR_I486:
1303 case PROCESSOR_PENTIUM:
1305 case PROCESSOR_ATHLON:
1307 case PROCESSOR_AMDFAM10:
1310 case PROCESSOR_GENERIC32:
1311 /* We use cpu_arch_isa_flags to check if we CAN optimize
1313 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1314 patt = alt_short_patt;
1318 case PROCESSOR_PENTIUMPRO:
1319 case PROCESSOR_PENTIUM4:
1320 case PROCESSOR_NOCONA:
1321 case PROCESSOR_CORE:
1322 case PROCESSOR_CORE2:
1323 case PROCESSOR_COREI7:
1324 case PROCESSOR_L1OM:
1325 case PROCESSOR_K1OM:
1326 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1327 patt = alt_long_patt;
1331 case PROCESSOR_GENERIC64:
1332 patt = alt_long_patt;
1337 if (patt == f32_patt)
1339 /* If the padding is less than 15 bytes, we use the normal
1340 ones. Otherwise, we use a jump instruction and adjust
1344 /* For 64bit, the limit is 3 bytes. */
1345 if (flag_code == CODE_64BIT
1346 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1351 memcpy (fragP->fr_literal + fragP->fr_fix,
1352 patt[count - 1], count);
1355 memcpy (fragP->fr_literal + fragP->fr_fix,
1357 /* Adjust jump offset. */
1358 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1363 /* Maximum length of an instruction is 15 byte. If the
1364 padding is greater than 15 bytes and we don't use jump,
1365 we have to break it into smaller pieces. */
1366 int padding = count;
1367 while (padding > 15)
1370 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1375 memcpy (fragP->fr_literal + fragP->fr_fix,
1376 patt [padding - 1], padding);
1379 fragP->fr_var = count;
1383 operand_type_all_zero (const union i386_operand_type *x)
1385 switch (ARRAY_SIZE(x->array))
1394 return !x->array[0];
1401 operand_type_set (union i386_operand_type *x, unsigned int v)
1403 switch (ARRAY_SIZE(x->array))
1418 operand_type_equal (const union i386_operand_type *x,
1419 const union i386_operand_type *y)
1421 switch (ARRAY_SIZE(x->array))
1424 if (x->array[2] != y->array[2])
1427 if (x->array[1] != y->array[1])
1430 return x->array[0] == y->array[0];
1438 cpu_flags_all_zero (const union i386_cpu_flags *x)
1440 switch (ARRAY_SIZE(x->array))
1449 return !x->array[0];
1456 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1458 switch (ARRAY_SIZE(x->array))
1473 cpu_flags_equal (const union i386_cpu_flags *x,
1474 const union i386_cpu_flags *y)
1476 switch (ARRAY_SIZE(x->array))
1479 if (x->array[2] != y->array[2])
1482 if (x->array[1] != y->array[1])
1485 return x->array[0] == y->array[0];
1493 cpu_flags_check_cpu64 (i386_cpu_flags f)
1495 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1496 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1499 static INLINE i386_cpu_flags
1500 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1502 switch (ARRAY_SIZE (x.array))
1505 x.array [2] &= y.array [2];
1507 x.array [1] &= y.array [1];
1509 x.array [0] &= y.array [0];
1517 static INLINE i386_cpu_flags
1518 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1520 switch (ARRAY_SIZE (x.array))
1523 x.array [2] |= y.array [2];
1525 x.array [1] |= y.array [1];
1527 x.array [0] |= y.array [0];
1535 static INLINE i386_cpu_flags
1536 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1538 switch (ARRAY_SIZE (x.array))
1541 x.array [2] &= ~y.array [2];
1543 x.array [1] &= ~y.array [1];
1545 x.array [0] &= ~y.array [0];
1553 #define CPU_FLAGS_ARCH_MATCH 0x1
1554 #define CPU_FLAGS_64BIT_MATCH 0x2
1555 #define CPU_FLAGS_AES_MATCH 0x4
1556 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1557 #define CPU_FLAGS_AVX_MATCH 0x10
1559 #define CPU_FLAGS_32BIT_MATCH \
1560 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1561 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1562 #define CPU_FLAGS_PERFECT_MATCH \
1563 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1565 /* Return CPU flags match bits. */
1568 cpu_flags_match (const insn_template *t)
1570 i386_cpu_flags x = t->cpu_flags;
1571 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1573 x.bitfield.cpu64 = 0;
1574 x.bitfield.cpuno64 = 0;
1576 if (cpu_flags_all_zero (&x))
1578 /* This instruction is available on all archs. */
1579 match |= CPU_FLAGS_32BIT_MATCH;
1583 /* This instruction is available only on some archs. */
1584 i386_cpu_flags cpu = cpu_arch_flags;
1586 cpu.bitfield.cpu64 = 0;
1587 cpu.bitfield.cpuno64 = 0;
1588 cpu = cpu_flags_and (x, cpu);
1589 if (!cpu_flags_all_zero (&cpu))
1591 if (x.bitfield.cpuavx)
1593 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1594 if (cpu.bitfield.cpuavx)
1596 /* Check SSE2AVX. */
1597 if (!t->opcode_modifier.sse2avx|| sse2avx)
1599 match |= (CPU_FLAGS_ARCH_MATCH
1600 | CPU_FLAGS_AVX_MATCH);
1602 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1603 match |= CPU_FLAGS_AES_MATCH;
1605 if (!x.bitfield.cpupclmul
1606 || cpu.bitfield.cpupclmul)
1607 match |= CPU_FLAGS_PCLMUL_MATCH;
1611 match |= CPU_FLAGS_ARCH_MATCH;
1614 match |= CPU_FLAGS_32BIT_MATCH;
1620 static INLINE i386_operand_type
1621 operand_type_and (i386_operand_type x, i386_operand_type y)
1623 switch (ARRAY_SIZE (x.array))
1626 x.array [2] &= y.array [2];
1628 x.array [1] &= y.array [1];
1630 x.array [0] &= y.array [0];
1638 static INLINE i386_operand_type
1639 operand_type_or (i386_operand_type x, i386_operand_type y)
1641 switch (ARRAY_SIZE (x.array))
1644 x.array [2] |= y.array [2];
1646 x.array [1] |= y.array [1];
1648 x.array [0] |= y.array [0];
1656 static INLINE i386_operand_type
1657 operand_type_xor (i386_operand_type x, i386_operand_type y)
1659 switch (ARRAY_SIZE (x.array))
1662 x.array [2] ^= y.array [2];
1664 x.array [1] ^= y.array [1];
1666 x.array [0] ^= y.array [0];
1674 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1675 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1676 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1677 static const i386_operand_type inoutportreg
1678 = OPERAND_TYPE_INOUTPORTREG;
1679 static const i386_operand_type reg16_inoutportreg
1680 = OPERAND_TYPE_REG16_INOUTPORTREG;
1681 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1682 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1683 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1684 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1685 static const i386_operand_type anydisp
1686 = OPERAND_TYPE_ANYDISP;
1687 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1688 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1689 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1690 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1691 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1692 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1693 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1694 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1695 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1696 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1697 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1698 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1699 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1700 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1711 operand_type_check (i386_operand_type t, enum operand_type c)
1716 return (t.bitfield.reg8
1719 || t.bitfield.reg64);
1722 return (t.bitfield.imm8
1726 || t.bitfield.imm32s
1727 || t.bitfield.imm64);
1730 return (t.bitfield.disp8
1731 || t.bitfield.disp16
1732 || t.bitfield.disp32
1733 || t.bitfield.disp32s
1734 || t.bitfield.disp64);
1737 return (t.bitfield.disp8
1738 || t.bitfield.disp16
1739 || t.bitfield.disp32
1740 || t.bitfield.disp32s
1741 || t.bitfield.disp64
1742 || t.bitfield.baseindex);
1751 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1752 operand J for instruction template T. */
1755 match_reg_size (const insn_template *t, unsigned int j)
1757 return !((i.types[j].bitfield.byte
1758 && !t->operand_types[j].bitfield.byte)
1759 || (i.types[j].bitfield.word
1760 && !t->operand_types[j].bitfield.word)
1761 || (i.types[j].bitfield.dword
1762 && !t->operand_types[j].bitfield.dword)
1763 || (i.types[j].bitfield.qword
1764 && !t->operand_types[j].bitfield.qword));
1767 /* Return 1 if there is no conflict in any size on operand J for
1768 instruction template T. */
1771 match_mem_size (const insn_template *t, unsigned int j)
1773 return (match_reg_size (t, j)
1774 && !((i.types[j].bitfield.unspecified
1775 && !t->operand_types[j].bitfield.unspecified)
1776 || (i.types[j].bitfield.fword
1777 && !t->operand_types[j].bitfield.fword)
1778 || (i.types[j].bitfield.tbyte
1779 && !t->operand_types[j].bitfield.tbyte)
1780 || (i.types[j].bitfield.xmmword
1781 && !t->operand_types[j].bitfield.xmmword)
1782 || (i.types[j].bitfield.ymmword
1783 && !t->operand_types[j].bitfield.ymmword)
1784 || (i.types[j].bitfield.zmmword
1785 && !t->operand_types[j].bitfield.zmmword)));
1788 /* Return 1 if there is no size conflict on any operands for
1789 instruction template T. */
1792 operand_size_match (const insn_template *t)
1797 /* Don't check jump instructions. */
1798 if (t->opcode_modifier.jump
1799 || t->opcode_modifier.jumpbyte
1800 || t->opcode_modifier.jumpdword
1801 || t->opcode_modifier.jumpintersegment)
1804 /* Check memory and accumulator operand size. */
1805 for (j = 0; j < i.operands; j++)
1807 if (t->operand_types[j].bitfield.anysize)
1810 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1816 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1825 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1828 i.error = operand_size_mismatch;
1832 /* Check reverse. */
1833 gas_assert (i.operands == 2);
1836 for (j = 0; j < 2; j++)
1838 if (t->operand_types[j].bitfield.acc
1839 && !match_reg_size (t, j ? 0 : 1))
1842 if (i.types[j].bitfield.mem
1843 && !match_mem_size (t, j ? 0 : 1))
1851 operand_type_match (i386_operand_type overlap,
1852 i386_operand_type given)
1854 i386_operand_type temp = overlap;
1856 temp.bitfield.jumpabsolute = 0;
1857 temp.bitfield.unspecified = 0;
1858 temp.bitfield.byte = 0;
1859 temp.bitfield.word = 0;
1860 temp.bitfield.dword = 0;
1861 temp.bitfield.fword = 0;
1862 temp.bitfield.qword = 0;
1863 temp.bitfield.tbyte = 0;
1864 temp.bitfield.xmmword = 0;
1865 temp.bitfield.ymmword = 0;
1866 temp.bitfield.zmmword = 0;
1867 if (operand_type_all_zero (&temp))
1870 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1871 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1875 i.error = operand_type_mismatch;
1879 /* If given types g0 and g1 are registers they must be of the same type
1880 unless the expected operand type register overlap is null.
1881 Note that Acc in a template matches every size of reg. */
1884 operand_type_register_match (i386_operand_type m0,
1885 i386_operand_type g0,
1886 i386_operand_type t0,
1887 i386_operand_type m1,
1888 i386_operand_type g1,
1889 i386_operand_type t1)
1891 if (!operand_type_check (g0, reg))
1894 if (!operand_type_check (g1, reg))
1897 if (g0.bitfield.reg8 == g1.bitfield.reg8
1898 && g0.bitfield.reg16 == g1.bitfield.reg16
1899 && g0.bitfield.reg32 == g1.bitfield.reg32
1900 && g0.bitfield.reg64 == g1.bitfield.reg64)
1903 if (m0.bitfield.acc)
1905 t0.bitfield.reg8 = 1;
1906 t0.bitfield.reg16 = 1;
1907 t0.bitfield.reg32 = 1;
1908 t0.bitfield.reg64 = 1;
1911 if (m1.bitfield.acc)
1913 t1.bitfield.reg8 = 1;
1914 t1.bitfield.reg16 = 1;
1915 t1.bitfield.reg32 = 1;
1916 t1.bitfield.reg64 = 1;
1919 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1920 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1921 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1922 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1925 i.error = register_type_mismatch;
1930 static INLINE unsigned int
1931 register_number (const reg_entry *r)
1933 unsigned int nr = r->reg_num;
1935 if (r->reg_flags & RegRex)
1941 static INLINE unsigned int
1942 mode_from_disp_size (i386_operand_type t)
1944 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1946 else if (t.bitfield.disp16
1947 || t.bitfield.disp32
1948 || t.bitfield.disp32s)
1955 fits_in_signed_byte (addressT num)
1957 return num + 0x80 <= 0xff;
1961 fits_in_unsigned_byte (addressT num)
1967 fits_in_unsigned_word (addressT num)
1969 return num <= 0xffff;
1973 fits_in_signed_word (addressT num)
1975 return num + 0x8000 <= 0xffff;
1979 fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
1984 return num + 0x80000000 <= 0xffffffff;
1986 } /* fits_in_signed_long() */
1989 fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
1994 return num <= 0xffffffff;
1996 } /* fits_in_unsigned_long() */
1999 fits_in_vec_disp8 (offsetT num)
2001 int shift = i.memshift;
2007 mask = (1 << shift) - 1;
2009 /* Return 0 if NUM isn't properly aligned. */
2013 /* Check if NUM will fit in 8bit after shift. */
2014 return fits_in_signed_byte (num >> shift);
2018 fits_in_imm4 (offsetT num)
2020 return (num & 0xf) == num;
2023 static i386_operand_type
2024 smallest_imm_type (offsetT num)
2026 i386_operand_type t;
2028 operand_type_set (&t, 0);
2029 t.bitfield.imm64 = 1;
2031 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2033 /* This code is disabled on the 486 because all the Imm1 forms
2034 in the opcode table are slower on the i486. They're the
2035 versions with the implicitly specified single-position
2036 displacement, which has another syntax if you really want to
2038 t.bitfield.imm1 = 1;
2039 t.bitfield.imm8 = 1;
2040 t.bitfield.imm8s = 1;
2041 t.bitfield.imm16 = 1;
2042 t.bitfield.imm32 = 1;
2043 t.bitfield.imm32s = 1;
2045 else if (fits_in_signed_byte (num))
2047 t.bitfield.imm8 = 1;
2048 t.bitfield.imm8s = 1;
2049 t.bitfield.imm16 = 1;
2050 t.bitfield.imm32 = 1;
2051 t.bitfield.imm32s = 1;
2053 else if (fits_in_unsigned_byte (num))
2055 t.bitfield.imm8 = 1;
2056 t.bitfield.imm16 = 1;
2057 t.bitfield.imm32 = 1;
2058 t.bitfield.imm32s = 1;
2060 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2062 t.bitfield.imm16 = 1;
2063 t.bitfield.imm32 = 1;
2064 t.bitfield.imm32s = 1;
2066 else if (fits_in_signed_long (num))
2068 t.bitfield.imm32 = 1;
2069 t.bitfield.imm32s = 1;
2071 else if (fits_in_unsigned_long (num))
2072 t.bitfield.imm32 = 1;
2078 offset_in_range (offsetT val, int size)
2084 case 1: mask = ((addressT) 1 << 8) - 1; break;
2085 case 2: mask = ((addressT) 1 << 16) - 1; break;
2086 case 4: mask = ((addressT) 2 << 31) - 1; break;
2088 case 8: mask = ((addressT) 2 << 63) - 1; break;
2094 /* If BFD64, sign extend val for 32bit address mode. */
2095 if (flag_code != CODE_64BIT
2096 || i.prefix[ADDR_PREFIX])
2097 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2098 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2101 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2103 char buf1[40], buf2[40];
2105 sprint_value (buf1, val);
2106 sprint_value (buf2, val & mask);
2107 as_warn (_("%s shortened to %s"), buf1, buf2);
2121 a. PREFIX_EXIST if attempting to add a prefix where one from the
2122 same class already exists.
2123 b. PREFIX_LOCK if lock prefix is added.
2124 c. PREFIX_REP if rep/repne prefix is added.
2125 d. PREFIX_OTHER if other prefix is added.
2128 static enum PREFIX_GROUP
2129 add_prefix (unsigned int prefix)
2131 enum PREFIX_GROUP ret = PREFIX_OTHER;
2134 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2135 && flag_code == CODE_64BIT)
2137 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2138 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2139 && (prefix & (REX_R | REX_X | REX_B))))
2150 case CS_PREFIX_OPCODE:
2151 case DS_PREFIX_OPCODE:
2152 case ES_PREFIX_OPCODE:
2153 case FS_PREFIX_OPCODE:
2154 case GS_PREFIX_OPCODE:
2155 case SS_PREFIX_OPCODE:
2159 case REPNE_PREFIX_OPCODE:
2160 case REPE_PREFIX_OPCODE:
2165 case LOCK_PREFIX_OPCODE:
2174 case ADDR_PREFIX_OPCODE:
2178 case DATA_PREFIX_OPCODE:
2182 if (i.prefix[q] != 0)
2190 i.prefix[q] |= prefix;
2193 as_bad (_("same type of prefix used twice"));
2199 update_code_flag (int value, int check)
2201 PRINTF_LIKE ((*as_error));
2203 flag_code = (enum flag_code) value;
2204 if (flag_code == CODE_64BIT)
2206 cpu_arch_flags.bitfield.cpu64 = 1;
2207 cpu_arch_flags.bitfield.cpuno64 = 0;
2211 cpu_arch_flags.bitfield.cpu64 = 0;
2212 cpu_arch_flags.bitfield.cpuno64 = 1;
2214 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2217 as_error = as_fatal;
2220 (*as_error) (_("64bit mode not supported on `%s'."),
2221 cpu_arch_name ? cpu_arch_name : default_arch);
2223 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2226 as_error = as_fatal;
2229 (*as_error) (_("32bit mode not supported on `%s'."),
2230 cpu_arch_name ? cpu_arch_name : default_arch);
2232 stackop_size = '\0';
2236 set_code_flag (int value)
2238 update_code_flag (value, 0);
2242 set_16bit_gcc_code_flag (int new_code_flag)
2244 flag_code = (enum flag_code) new_code_flag;
2245 if (flag_code != CODE_16BIT)
2247 cpu_arch_flags.bitfield.cpu64 = 0;
2248 cpu_arch_flags.bitfield.cpuno64 = 1;
2249 stackop_size = LONG_MNEM_SUFFIX;
2253 set_intel_syntax (int syntax_flag)
2255 /* Find out if register prefixing is specified. */
2256 int ask_naked_reg = 0;
2259 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2261 char *string = input_line_pointer;
2262 int e = get_symbol_end ();
2264 if (strcmp (string, "prefix") == 0)
2266 else if (strcmp (string, "noprefix") == 0)
2269 as_bad (_("bad argument to syntax directive."));
2270 *input_line_pointer = e;
2272 demand_empty_rest_of_line ();
2274 intel_syntax = syntax_flag;
2276 if (ask_naked_reg == 0)
2277 allow_naked_reg = (intel_syntax
2278 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2280 allow_naked_reg = (ask_naked_reg < 0);
2282 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2284 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2285 identifier_chars['$'] = intel_syntax ? '$' : 0;
2286 register_prefix = allow_naked_reg ? "" : "%";
2290 set_intel_mnemonic (int mnemonic_flag)
2292 intel_mnemonic = mnemonic_flag;
2296 set_allow_index_reg (int flag)
2298 allow_index_reg = flag;
2302 set_check (int what)
2304 enum check_kind *kind;
2309 kind = &operand_check;
2320 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2322 char *string = input_line_pointer;
2323 int e = get_symbol_end ();
2325 if (strcmp (string, "none") == 0)
2327 else if (strcmp (string, "warning") == 0)
2328 *kind = check_warning;
2329 else if (strcmp (string, "error") == 0)
2330 *kind = check_error;
2332 as_bad (_("bad argument to %s_check directive."), str);
2333 *input_line_pointer = e;
2336 as_bad (_("missing argument for %s_check directive"), str);
2338 demand_empty_rest_of_line ();
2342 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2343 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2345 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2346 static const char *arch;
2348 /* Intel LIOM is only supported on ELF. */
2354 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2355 use default_arch. */
2356 arch = cpu_arch_name;
2358 arch = default_arch;
2361 /* If we are targeting Intel L1OM, we must enable it. */
2362 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2363 || new_flag.bitfield.cpul1om)
2366 /* If we are targeting Intel K1OM, we must enable it. */
2367 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2368 || new_flag.bitfield.cpuk1om)
2371 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2376 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2380 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2382 char *string = input_line_pointer;
2383 int e = get_symbol_end ();
2385 i386_cpu_flags flags;
2387 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2389 if (strcmp (string, cpu_arch[j].name) == 0)
2391 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2395 cpu_arch_name = cpu_arch[j].name;
2396 cpu_sub_arch_name = NULL;
2397 cpu_arch_flags = cpu_arch[j].flags;
2398 if (flag_code == CODE_64BIT)
2400 cpu_arch_flags.bitfield.cpu64 = 1;
2401 cpu_arch_flags.bitfield.cpuno64 = 0;
2405 cpu_arch_flags.bitfield.cpu64 = 0;
2406 cpu_arch_flags.bitfield.cpuno64 = 1;
2408 cpu_arch_isa = cpu_arch[j].type;
2409 cpu_arch_isa_flags = cpu_arch[j].flags;
2410 if (!cpu_arch_tune_set)
2412 cpu_arch_tune = cpu_arch_isa;
2413 cpu_arch_tune_flags = cpu_arch_isa_flags;
2418 if (!cpu_arch[j].negated)
2419 flags = cpu_flags_or (cpu_arch_flags,
2422 flags = cpu_flags_and_not (cpu_arch_flags,
2424 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2426 if (cpu_sub_arch_name)
2428 char *name = cpu_sub_arch_name;
2429 cpu_sub_arch_name = concat (name,
2431 (const char *) NULL);
2435 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2436 cpu_arch_flags = flags;
2437 cpu_arch_isa_flags = flags;
2439 *input_line_pointer = e;
2440 demand_empty_rest_of_line ();
2444 if (j >= ARRAY_SIZE (cpu_arch))
2445 as_bad (_("no such architecture: `%s'"), string);
2447 *input_line_pointer = e;
2450 as_bad (_("missing cpu architecture"));
2452 no_cond_jump_promotion = 0;
2453 if (*input_line_pointer == ','
2454 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2456 char *string = ++input_line_pointer;
2457 int e = get_symbol_end ();
2459 if (strcmp (string, "nojumps") == 0)
2460 no_cond_jump_promotion = 1;
2461 else if (strcmp (string, "jumps") == 0)
2464 as_bad (_("no such architecture modifier: `%s'"), string);
2466 *input_line_pointer = e;
2469 demand_empty_rest_of_line ();
2472 enum bfd_architecture
2475 if (cpu_arch_isa == PROCESSOR_L1OM)
2477 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2478 || flag_code != CODE_64BIT)
2479 as_fatal (_("Intel L1OM is 64bit ELF only"));
2480 return bfd_arch_l1om;
2482 else if (cpu_arch_isa == PROCESSOR_K1OM)
2484 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2485 || flag_code != CODE_64BIT)
2486 as_fatal (_("Intel K1OM is 64bit ELF only"));
2487 return bfd_arch_k1om;
2490 return bfd_arch_i386;
2496 if (!strncmp (default_arch, "x86_64", 6))
2498 if (cpu_arch_isa == PROCESSOR_L1OM)
2500 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2501 || default_arch[6] != '\0')
2502 as_fatal (_("Intel L1OM is 64bit ELF only"));
2503 return bfd_mach_l1om;
2505 else if (cpu_arch_isa == PROCESSOR_K1OM)
2507 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2508 || default_arch[6] != '\0')
2509 as_fatal (_("Intel K1OM is 64bit ELF only"));
2510 return bfd_mach_k1om;
2512 else if (default_arch[6] == '\0')
2513 return bfd_mach_x86_64;
2515 return bfd_mach_x64_32;
2517 else if (!strcmp (default_arch, "i386"))
2518 return bfd_mach_i386_i386;
2520 as_fatal (_("unknown architecture"));
2526 const char *hash_err;
2528 /* Initialize op_hash hash table. */
2529 op_hash = hash_new ();
2532 const insn_template *optab;
2533 templates *core_optab;
2535 /* Setup for loop. */
2537 core_optab = (templates *) xmalloc (sizeof (templates));
2538 core_optab->start = optab;
2543 if (optab->name == NULL
2544 || strcmp (optab->name, (optab - 1)->name) != 0)
2546 /* different name --> ship out current template list;
2547 add to hash table; & begin anew. */
2548 core_optab->end = optab;
2549 hash_err = hash_insert (op_hash,
2551 (void *) core_optab);
2554 as_fatal (_("can't hash %s: %s"),
2558 if (optab->name == NULL)
2560 core_optab = (templates *) xmalloc (sizeof (templates));
2561 core_optab->start = optab;
2566 /* Initialize reg_hash hash table. */
2567 reg_hash = hash_new ();
2569 const reg_entry *regtab;
2570 unsigned int regtab_size = i386_regtab_size;
2572 for (regtab = i386_regtab; regtab_size--; regtab++)
2574 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2576 as_fatal (_("can't hash %s: %s"),
2582 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2587 for (c = 0; c < 256; c++)
2592 mnemonic_chars[c] = c;
2593 register_chars[c] = c;
2594 operand_chars[c] = c;
2596 else if (ISLOWER (c))
2598 mnemonic_chars[c] = c;
2599 register_chars[c] = c;
2600 operand_chars[c] = c;
2602 else if (ISUPPER (c))
2604 mnemonic_chars[c] = TOLOWER (c);
2605 register_chars[c] = mnemonic_chars[c];
2606 operand_chars[c] = c;
2608 else if (c == '{' || c == '}')
2609 operand_chars[c] = c;
2611 if (ISALPHA (c) || ISDIGIT (c))
2612 identifier_chars[c] = c;
2615 identifier_chars[c] = c;
2616 operand_chars[c] = c;
2621 identifier_chars['@'] = '@';
2624 identifier_chars['?'] = '?';
2625 operand_chars['?'] = '?';
2627 digit_chars['-'] = '-';
2628 mnemonic_chars['_'] = '_';
2629 mnemonic_chars['-'] = '-';
2630 mnemonic_chars['.'] = '.';
2631 identifier_chars['_'] = '_';
2632 identifier_chars['.'] = '.';
2634 for (p = operand_special_chars; *p != '\0'; p++)
2635 operand_chars[(unsigned char) *p] = *p;
2638 if (flag_code == CODE_64BIT)
2640 #if defined (OBJ_COFF) && defined (TE_PE)
2641 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2644 x86_dwarf2_return_column = 16;
2646 x86_cie_data_alignment = -8;
2650 x86_dwarf2_return_column = 8;
2651 x86_cie_data_alignment = -4;
2656 i386_print_statistics (FILE *file)
2658 hash_print_statistics (file, "i386 opcode", op_hash);
2659 hash_print_statistics (file, "i386 register", reg_hash);
2664 /* Debugging routines for md_assemble. */
2665 static void pte (insn_template *);
2666 static void pt (i386_operand_type);
2667 static void pe (expressionS *);
2668 static void ps (symbolS *);
2671 pi (char *line, i386_insn *x)
2675 fprintf (stdout, "%s: template ", line);
2677 fprintf (stdout, " address: base %s index %s scale %x\n",
2678 x->base_reg ? x->base_reg->reg_name : "none",
2679 x->index_reg ? x->index_reg->reg_name : "none",
2680 x->log2_scale_factor);
2681 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2682 x->rm.mode, x->rm.reg, x->rm.regmem);
2683 fprintf (stdout, " sib: base %x index %x scale %x\n",
2684 x->sib.base, x->sib.index, x->sib.scale);
2685 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2686 (x->rex & REX_W) != 0,
2687 (x->rex & REX_R) != 0,
2688 (x->rex & REX_X) != 0,
2689 (x->rex & REX_B) != 0);
2690 for (j = 0; j < x->operands; j++)
2692 fprintf (stdout, " #%d: ", j + 1);
2694 fprintf (stdout, "\n");
2695 if (x->types[j].bitfield.reg8
2696 || x->types[j].bitfield.reg16
2697 || x->types[j].bitfield.reg32
2698 || x->types[j].bitfield.reg64
2699 || x->types[j].bitfield.regmmx
2700 || x->types[j].bitfield.regxmm
2701 || x->types[j].bitfield.regymm
2702 || x->types[j].bitfield.regzmm
2703 || x->types[j].bitfield.sreg2
2704 || x->types[j].bitfield.sreg3
2705 || x->types[j].bitfield.control
2706 || x->types[j].bitfield.debug
2707 || x->types[j].bitfield.test)
2708 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2709 if (operand_type_check (x->types[j], imm))
2711 if (operand_type_check (x->types[j], disp))
2712 pe (x->op[j].disps);
2717 pte (insn_template *t)
2720 fprintf (stdout, " %d operands ", t->operands);
2721 fprintf (stdout, "opcode %x ", t->base_opcode);
2722 if (t->extension_opcode != None)
2723 fprintf (stdout, "ext %x ", t->extension_opcode);
2724 if (t->opcode_modifier.d)
2725 fprintf (stdout, "D");
2726 if (t->opcode_modifier.w)
2727 fprintf (stdout, "W");
2728 fprintf (stdout, "\n");
2729 for (j = 0; j < t->operands; j++)
2731 fprintf (stdout, " #%d type ", j + 1);
2732 pt (t->operand_types[j]);
2733 fprintf (stdout, "\n");
2740 fprintf (stdout, " operation %d\n", e->X_op);
2741 fprintf (stdout, " add_number %ld (%lx)\n",
2742 (long) e->X_add_number, (long) e->X_add_number);
2743 if (e->X_add_symbol)
2745 fprintf (stdout, " add_symbol ");
2746 ps (e->X_add_symbol);
2747 fprintf (stdout, "\n");
2751 fprintf (stdout, " op_symbol ");
2752 ps (e->X_op_symbol);
2753 fprintf (stdout, "\n");
2760 fprintf (stdout, "%s type %s%s",
2762 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2763 segment_name (S_GET_SEGMENT (s)));
2766 static struct type_name
2768 i386_operand_type mask;
2771 const type_names[] =
2773 { OPERAND_TYPE_REG8, "r8" },
2774 { OPERAND_TYPE_REG16, "r16" },
2775 { OPERAND_TYPE_REG32, "r32" },
2776 { OPERAND_TYPE_REG64, "r64" },
2777 { OPERAND_TYPE_IMM8, "i8" },
2778 { OPERAND_TYPE_IMM8, "i8s" },
2779 { OPERAND_TYPE_IMM16, "i16" },
2780 { OPERAND_TYPE_IMM32, "i32" },
2781 { OPERAND_TYPE_IMM32S, "i32s" },
2782 { OPERAND_TYPE_IMM64, "i64" },
2783 { OPERAND_TYPE_IMM1, "i1" },
2784 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2785 { OPERAND_TYPE_DISP8, "d8" },
2786 { OPERAND_TYPE_DISP16, "d16" },
2787 { OPERAND_TYPE_DISP32, "d32" },
2788 { OPERAND_TYPE_DISP32S, "d32s" },
2789 { OPERAND_TYPE_DISP64, "d64" },
2790 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2791 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2792 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2793 { OPERAND_TYPE_CONTROL, "control reg" },
2794 { OPERAND_TYPE_TEST, "test reg" },
2795 { OPERAND_TYPE_DEBUG, "debug reg" },
2796 { OPERAND_TYPE_FLOATREG, "FReg" },
2797 { OPERAND_TYPE_FLOATACC, "FAcc" },
2798 { OPERAND_TYPE_SREG2, "SReg2" },
2799 { OPERAND_TYPE_SREG3, "SReg3" },
2800 { OPERAND_TYPE_ACC, "Acc" },
2801 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2802 { OPERAND_TYPE_REGMMX, "rMMX" },
2803 { OPERAND_TYPE_REGXMM, "rXMM" },
2804 { OPERAND_TYPE_REGYMM, "rYMM" },
2805 { OPERAND_TYPE_REGZMM, "rZMM" },
2806 { OPERAND_TYPE_REGMASK, "Mask reg" },
2807 { OPERAND_TYPE_ESSEG, "es" },
2811 pt (i386_operand_type t)
2814 i386_operand_type a;
2816 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2818 a = operand_type_and (t, type_names[j].mask);
2819 if (!operand_type_all_zero (&a))
2820 fprintf (stdout, "%s, ", type_names[j].name);
2825 #endif /* DEBUG386 */
2827 static bfd_reloc_code_real_type
2828 reloc (unsigned int size,
2832 bfd_reloc_code_real_type other)
2834 if (other != NO_RELOC)
2836 reloc_howto_type *rel;
2841 case BFD_RELOC_X86_64_GOT32:
2842 return BFD_RELOC_X86_64_GOT64;
2844 case BFD_RELOC_X86_64_PLTOFF64:
2845 return BFD_RELOC_X86_64_PLTOFF64;
2847 case BFD_RELOC_X86_64_GOTPC32:
2848 other = BFD_RELOC_X86_64_GOTPC64;
2850 case BFD_RELOC_X86_64_GOTPCREL:
2851 other = BFD_RELOC_X86_64_GOTPCREL64;
2853 case BFD_RELOC_X86_64_TPOFF32:
2854 other = BFD_RELOC_X86_64_TPOFF64;
2856 case BFD_RELOC_X86_64_DTPOFF32:
2857 other = BFD_RELOC_X86_64_DTPOFF64;
2863 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2864 if (other == BFD_RELOC_SIZE32)
2867 other = BFD_RELOC_SIZE64;
2870 as_bad (_("there are no pc-relative size relocations"));
2876 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2877 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2880 rel = bfd_reloc_type_lookup (stdoutput, other);
2882 as_bad (_("unknown relocation (%u)"), other);
2883 else if (size != bfd_get_reloc_size (rel))
2884 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2885 bfd_get_reloc_size (rel),
2887 else if (pcrel && !rel->pc_relative)
2888 as_bad (_("non-pc-relative relocation for pc-relative field"));
2889 else if ((rel->complain_on_overflow == complain_overflow_signed
2891 || (rel->complain_on_overflow == complain_overflow_unsigned
2893 as_bad (_("relocated field and relocation type differ in signedness"));
2902 as_bad (_("there are no unsigned pc-relative relocations"));
2905 case 1: return BFD_RELOC_8_PCREL;
2906 case 2: return BFD_RELOC_16_PCREL;
2907 case 4: return (bnd_prefix && object_64bit
2908 ? BFD_RELOC_X86_64_PC32_BND
2909 : BFD_RELOC_32_PCREL);
2910 case 8: return BFD_RELOC_64_PCREL;
2912 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2919 case 4: return BFD_RELOC_X86_64_32S;
2924 case 1: return BFD_RELOC_8;
2925 case 2: return BFD_RELOC_16;
2926 case 4: return BFD_RELOC_32;
2927 case 8: return BFD_RELOC_64;
2929 as_bad (_("cannot do %s %u byte relocation"),
2930 sign > 0 ? "signed" : "unsigned", size);
2936 /* Here we decide which fixups can be adjusted to make them relative to
2937 the beginning of the section instead of the symbol. Basically we need
2938 to make sure that the dynamic relocations are done correctly, so in
2939 some cases we force the original symbol to be used. */
2942 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2944 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2948 /* Don't adjust pc-relative references to merge sections in 64-bit
2950 if (use_rela_relocations
2951 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2955 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2956 and changed later by validate_fix. */
2957 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2958 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2961 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2962 for size relocations. */
2963 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2964 || fixP->fx_r_type == BFD_RELOC_SIZE64
2965 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2966 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2967 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2968 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2969 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2970 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2971 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2972 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2973 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2974 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2975 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2976 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2977 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2978 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2979 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2980 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2981 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2982 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2983 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2984 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2985 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2986 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2987 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2988 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2989 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2990 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2991 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2992 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2999 intel_float_operand (const char *mnemonic)
3001 /* Note that the value returned is meaningful only for opcodes with (memory)
3002 operands, hence the code here is free to improperly handle opcodes that
3003 have no operands (for better performance and smaller code). */
3005 if (mnemonic[0] != 'f')
3006 return 0; /* non-math */
3008 switch (mnemonic[1])
3010 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3011 the fs segment override prefix not currently handled because no
3012 call path can make opcodes without operands get here */
3014 return 2 /* integer op */;
3016 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3017 return 3; /* fldcw/fldenv */
3020 if (mnemonic[2] != 'o' /* fnop */)
3021 return 3; /* non-waiting control op */
3024 if (mnemonic[2] == 's')
3025 return 3; /* frstor/frstpm */
3028 if (mnemonic[2] == 'a')
3029 return 3; /* fsave */
3030 if (mnemonic[2] == 't')
3032 switch (mnemonic[3])
3034 case 'c': /* fstcw */
3035 case 'd': /* fstdw */
3036 case 'e': /* fstenv */
3037 case 's': /* fsts[gw] */
3043 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3044 return 0; /* fxsave/fxrstor are not really math ops */
3051 /* Build the VEX prefix. */
3054 build_vex_prefix (const insn_template *t)
3056 unsigned int register_specifier;
3057 unsigned int implied_prefix;
3058 unsigned int vector_length;
3060 /* Check register specifier. */
3061 if (i.vex.register_specifier)
3063 register_specifier =
3064 ~register_number (i.vex.register_specifier) & 0xf;
3065 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3068 register_specifier = 0xf;
3070 /* Use 2-byte VEX prefix by swappping destination and source
3073 && i.operands == i.reg_operands
3074 && i.tm.opcode_modifier.vexopcode == VEX0F
3075 && i.tm.opcode_modifier.s
3078 unsigned int xchg = i.operands - 1;
3079 union i386_op temp_op;
3080 i386_operand_type temp_type;
3082 temp_type = i.types[xchg];
3083 i.types[xchg] = i.types[0];
3084 i.types[0] = temp_type;
3085 temp_op = i.op[xchg];
3086 i.op[xchg] = i.op[0];
3089 gas_assert (i.rm.mode == 3);
3093 i.rm.regmem = i.rm.reg;
3096 /* Use the next insn. */
3100 if (i.tm.opcode_modifier.vex == VEXScalar)
3101 vector_length = avxscalar;
3103 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3105 switch ((i.tm.base_opcode >> 8) & 0xff)
3110 case DATA_PREFIX_OPCODE:
3113 case REPE_PREFIX_OPCODE:
3116 case REPNE_PREFIX_OPCODE:
3123 /* Use 2-byte VEX prefix if possible. */
3124 if (i.tm.opcode_modifier.vexopcode == VEX0F
3125 && i.tm.opcode_modifier.vexw != VEXW1
3126 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3128 /* 2-byte VEX prefix. */
3132 i.vex.bytes[0] = 0xc5;
3134 /* Check the REX.R bit. */
3135 r = (i.rex & REX_R) ? 0 : 1;
3136 i.vex.bytes[1] = (r << 7
3137 | register_specifier << 3
3138 | vector_length << 2
3143 /* 3-byte VEX prefix. */
3148 switch (i.tm.opcode_modifier.vexopcode)
3152 i.vex.bytes[0] = 0xc4;
3156 i.vex.bytes[0] = 0xc4;
3160 i.vex.bytes[0] = 0xc4;
3164 i.vex.bytes[0] = 0x8f;
3168 i.vex.bytes[0] = 0x8f;
3172 i.vex.bytes[0] = 0x8f;
3178 /* The high 3 bits of the second VEX byte are 1's compliment
3179 of RXB bits from REX. */
3180 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3182 /* Check the REX.W bit. */
3183 w = (i.rex & REX_W) ? 1 : 0;
3184 if (i.tm.opcode_modifier.vexw == VEXW1)
3187 i.vex.bytes[2] = (w << 7
3188 | register_specifier << 3
3189 | vector_length << 2
3194 /* Build the EVEX prefix. */
3197 build_evex_prefix (void)
3199 unsigned int register_specifier;
3200 unsigned int implied_prefix;
3202 rex_byte vrex_used = 0;
3204 /* Check register specifier. */
3205 if (i.vex.register_specifier)
3207 gas_assert ((i.vrex & REX_X) == 0);
3209 register_specifier = i.vex.register_specifier->reg_num;
3210 if ((i.vex.register_specifier->reg_flags & RegRex))
3211 register_specifier += 8;
3212 /* The upper 16 registers are encoded in the fourth byte of the
3214 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3215 i.vex.bytes[3] = 0x8;
3216 register_specifier = ~register_specifier & 0xf;
3220 register_specifier = 0xf;
3222 /* Encode upper 16 vector index register in the fourth byte of
3224 if (!(i.vrex & REX_X))
3225 i.vex.bytes[3] = 0x8;
3230 switch ((i.tm.base_opcode >> 8) & 0xff)
3235 case DATA_PREFIX_OPCODE:
3238 case REPE_PREFIX_OPCODE:
3241 case REPNE_PREFIX_OPCODE:
3248 /* 4 byte EVEX prefix. */
3250 i.vex.bytes[0] = 0x62;
3253 switch (i.tm.opcode_modifier.vexopcode)
3269 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3271 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3273 /* The fifth bit of the second EVEX byte is 1's compliment of the
3274 REX_R bit in VREX. */
3275 if (!(i.vrex & REX_R))
3276 i.vex.bytes[1] |= 0x10;
3280 if ((i.reg_operands + i.imm_operands) == i.operands)
3282 /* When all operands are registers, the REX_X bit in REX is not
3283 used. We reuse it to encode the upper 16 registers, which is
3284 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3285 as 1's compliment. */
3286 if ((i.vrex & REX_B))
3289 i.vex.bytes[1] &= ~0x40;
3293 /* EVEX instructions shouldn't need the REX prefix. */
3294 i.vrex &= ~vrex_used;
3295 gas_assert (i.vrex == 0);
3297 /* Check the REX.W bit. */
3298 w = (i.rex & REX_W) ? 1 : 0;
3299 if (i.tm.opcode_modifier.vexw)
3301 if (i.tm.opcode_modifier.vexw == VEXW1)
3304 /* If w is not set it means we are dealing with WIG instruction. */
3307 if (evexwig == evexw1)
3311 /* Encode the U bit. */
3312 implied_prefix |= 0x4;
3314 /* The third byte of the EVEX prefix. */
3315 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3317 /* The fourth byte of the EVEX prefix. */
3318 /* The zeroing-masking bit. */
3319 if (i.mask && i.mask->zeroing)
3320 i.vex.bytes[3] |= 0x80;
3322 /* Don't always set the broadcast bit if there is no RC. */
3325 /* Encode the vector length. */
3326 unsigned int vec_length;
3328 switch (i.tm.opcode_modifier.evex)
3330 case EVEXLIG: /* LL' is ignored */
3331 vec_length = evexlig << 5;
3334 vec_length = 0 << 5;
3337 vec_length = 1 << 5;
3340 vec_length = 2 << 5;
3346 i.vex.bytes[3] |= vec_length;
3347 /* Encode the broadcast bit. */
3349 i.vex.bytes[3] |= 0x10;
3353 if (i.rounding->type != saeonly)
3354 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3356 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
3359 if (i.mask && i.mask->mask)
3360 i.vex.bytes[3] |= i.mask->mask->reg_num;
3364 process_immext (void)
3368 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3371 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3372 with an opcode suffix which is coded in the same place as an
3373 8-bit immediate field would be.
3374 Here we check those operands and remove them afterwards. */
3377 for (x = 0; x < i.operands; x++)
3378 if (register_number (i.op[x].regs) != x)
3379 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3380 register_prefix, i.op[x].regs->reg_name, x + 1,
3386 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3387 which is coded in the same place as an 8-bit immediate field
3388 would be. Here we fake an 8-bit immediate operand from the
3389 opcode suffix stored in tm.extension_opcode.
3391 AVX instructions also use this encoding, for some of
3392 3 argument instructions. */
3394 gas_assert (i.imm_operands <= 1
3396 || ((i.tm.opcode_modifier.vex
3397 || i.tm.opcode_modifier.evex)
3398 && i.operands <= 4)));
3400 exp = &im_expressions[i.imm_operands++];
3401 i.op[i.operands].imms = exp;
3402 i.types[i.operands] = imm8;
3404 exp->X_op = O_constant;
3405 exp->X_add_number = i.tm.extension_opcode;
3406 i.tm.extension_opcode = None;
3413 switch (i.tm.opcode_modifier.hleprefixok)
3418 as_bad (_("invalid instruction `%s' after `%s'"),
3419 i.tm.name, i.hle_prefix);
3422 if (i.prefix[LOCK_PREFIX])
3424 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3428 case HLEPrefixRelease:
3429 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3431 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3435 if (i.mem_operands == 0
3436 || !operand_type_check (i.types[i.operands - 1], anymem))
3438 as_bad (_("memory destination needed for instruction `%s'"
3439 " after `xrelease'"), i.tm.name);
3446 /* This is the guts of the machine-dependent assembler. LINE points to a
3447 machine dependent instruction. This function is supposed to emit
3448 the frags/bytes it assembles to. */
3451 md_assemble (char *line)
3454 char mnemonic[MAX_MNEM_SIZE];
3455 const insn_template *t;
3457 /* Initialize globals. */
3458 memset (&i, '\0', sizeof (i));
3459 for (j = 0; j < MAX_OPERANDS; j++)
3460 i.reloc[j] = NO_RELOC;
3461 memset (disp_expressions, '\0', sizeof (disp_expressions));
3462 memset (im_expressions, '\0', sizeof (im_expressions));
3463 save_stack_p = save_stack;
3465 /* First parse an instruction mnemonic & call i386_operand for the operands.
3466 We assume that the scrubber has arranged it so that line[0] is the valid
3467 start of a (possibly prefixed) mnemonic. */
3469 line = parse_insn (line, mnemonic);
3473 line = parse_operands (line, mnemonic);
3478 /* Now we've parsed the mnemonic into a set of templates, and have the
3479 operands at hand. */
3481 /* All intel opcodes have reversed operands except for "bound" and
3482 "enter". We also don't reverse intersegment "jmp" and "call"
3483 instructions with 2 immediate operands so that the immediate segment
3484 precedes the offset, as it does when in AT&T mode. */
3487 && (strcmp (mnemonic, "bound") != 0)
3488 && (strcmp (mnemonic, "invlpga") != 0)
3489 && !(operand_type_check (i.types[0], imm)
3490 && operand_type_check (i.types[1], imm)))
3493 /* The order of the immediates should be reversed
3494 for 2 immediates extrq and insertq instructions */
3495 if (i.imm_operands == 2
3496 && (strcmp (mnemonic, "extrq") == 0
3497 || strcmp (mnemonic, "insertq") == 0))
3498 swap_2_operands (0, 1);
3503 /* Don't optimize displacement for movabs since it only takes 64bit
3506 && i.disp_encoding != disp_encoding_32bit
3507 && (flag_code != CODE_64BIT
3508 || strcmp (mnemonic, "movabs") != 0))
3511 /* Next, we find a template that matches the given insn,
3512 making sure the overlap of the given operands types is consistent
3513 with the template operand types. */
3515 if (!(t = match_template ()))
3518 if (sse_check != check_none
3519 && !i.tm.opcode_modifier.noavx
3520 && (i.tm.cpu_flags.bitfield.cpusse
3521 || i.tm.cpu_flags.bitfield.cpusse2
3522 || i.tm.cpu_flags.bitfield.cpusse3
3523 || i.tm.cpu_flags.bitfield.cpussse3
3524 || i.tm.cpu_flags.bitfield.cpusse4_1
3525 || i.tm.cpu_flags.bitfield.cpusse4_2))
3527 (sse_check == check_warning
3529 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3532 /* Zap movzx and movsx suffix. The suffix has been set from
3533 "word ptr" or "byte ptr" on the source operand in Intel syntax
3534 or extracted from mnemonic in AT&T syntax. But we'll use
3535 the destination register to choose the suffix for encoding. */
3536 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3538 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3539 there is no suffix, the default will be byte extension. */
3540 if (i.reg_operands != 2
3543 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3548 if (i.tm.opcode_modifier.fwait)
3549 if (!add_prefix (FWAIT_OPCODE))
3552 /* Check if REP prefix is OK. */
3553 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3555 as_bad (_("invalid instruction `%s' after `%s'"),
3556 i.tm.name, i.rep_prefix);
3560 /* Check for lock without a lockable instruction. Destination operand
3561 must be memory unless it is xchg (0x86). */
3562 if (i.prefix[LOCK_PREFIX]
3563 && (!i.tm.opcode_modifier.islockable
3564 || i.mem_operands == 0
3565 || (i.tm.base_opcode != 0x86
3566 && !operand_type_check (i.types[i.operands - 1], anymem))))
3568 as_bad (_("expecting lockable instruction after `lock'"));
3572 /* Check if HLE prefix is OK. */
3573 if (i.hle_prefix && !check_hle ())
3576 /* Check BND prefix. */
3577 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3578 as_bad (_("expecting valid branch instruction after `bnd'"));
3580 if (i.tm.cpu_flags.bitfield.cpumpx
3581 && flag_code == CODE_64BIT
3582 && i.prefix[ADDR_PREFIX])
3583 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3585 /* Insert BND prefix. */
3587 && i.tm.opcode_modifier.bndprefixok
3588 && !i.prefix[BND_PREFIX])
3589 add_prefix (BND_PREFIX_OPCODE);
3591 /* Check string instruction segment overrides. */
3592 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3594 if (!check_string ())
3596 i.disp_operands = 0;
3599 if (!process_suffix ())
3602 /* Update operand types. */
3603 for (j = 0; j < i.operands; j++)
3604 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3606 /* Make still unresolved immediate matches conform to size of immediate
3607 given in i.suffix. */
3608 if (!finalize_imm ())
3611 if (i.types[0].bitfield.imm1)
3612 i.imm_operands = 0; /* kludge for shift insns. */
3614 /* We only need to check those implicit registers for instructions
3615 with 3 operands or less. */
3616 if (i.operands <= 3)
3617 for (j = 0; j < i.operands; j++)
3618 if (i.types[j].bitfield.inoutportreg
3619 || i.types[j].bitfield.shiftcount
3620 || i.types[j].bitfield.acc
3621 || i.types[j].bitfield.floatacc)
3624 /* ImmExt should be processed after SSE2AVX. */
3625 if (!i.tm.opcode_modifier.sse2avx
3626 && i.tm.opcode_modifier.immext)
3629 /* For insns with operands there are more diddles to do to the opcode. */
3632 if (!process_operands ())
3635 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3637 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3638 as_warn (_("translating to `%sp'"), i.tm.name);
3641 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3643 if (flag_code == CODE_16BIT)
3645 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3650 if (i.tm.opcode_modifier.vex)
3651 build_vex_prefix (t);
3653 build_evex_prefix ();
3656 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3657 instructions may define INT_OPCODE as well, so avoid this corner
3658 case for those instructions that use MODRM. */
3659 if (i.tm.base_opcode == INT_OPCODE
3660 && !i.tm.opcode_modifier.modrm
3661 && i.op[0].imms->X_add_number == 3)
3663 i.tm.base_opcode = INT3_OPCODE;
3667 if ((i.tm.opcode_modifier.jump
3668 || i.tm.opcode_modifier.jumpbyte
3669 || i.tm.opcode_modifier.jumpdword)
3670 && i.op[0].disps->X_op == O_constant)
3672 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3673 the absolute address given by the constant. Since ix86 jumps and
3674 calls are pc relative, we need to generate a reloc. */
3675 i.op[0].disps->X_add_symbol = &abs_symbol;
3676 i.op[0].disps->X_op = O_symbol;
3679 if (i.tm.opcode_modifier.rex64)
3682 /* For 8 bit registers we need an empty rex prefix. Also if the
3683 instruction already has a prefix, we need to convert old
3684 registers to new ones. */
3686 if ((i.types[0].bitfield.reg8
3687 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3688 || (i.types[1].bitfield.reg8
3689 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3690 || ((i.types[0].bitfield.reg8
3691 || i.types[1].bitfield.reg8)
3696 i.rex |= REX_OPCODE;
3697 for (x = 0; x < 2; x++)
3699 /* Look for 8 bit operand that uses old registers. */
3700 if (i.types[x].bitfield.reg8
3701 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3703 /* In case it is "hi" register, give up. */
3704 if (i.op[x].regs->reg_num > 3)
3705 as_bad (_("can't encode register '%s%s' in an "
3706 "instruction requiring REX prefix."),
3707 register_prefix, i.op[x].regs->reg_name);
3709 /* Otherwise it is equivalent to the extended register.
3710 Since the encoding doesn't change this is merely
3711 cosmetic cleanup for debug output. */
3713 i.op[x].regs = i.op[x].regs + 8;
3719 add_prefix (REX_OPCODE | i.rex);
3721 /* We are ready to output the insn. */
3726 parse_insn (char *line, char *mnemonic)
3729 char *token_start = l;
3732 const insn_template *t;
3738 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3743 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3745 as_bad (_("no such instruction: `%s'"), token_start);
3750 if (!is_space_char (*l)
3751 && *l != END_OF_INSN
3753 || (*l != PREFIX_SEPARATOR
3756 as_bad (_("invalid character %s in mnemonic"),
3757 output_invalid (*l));
3760 if (token_start == l)
3762 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3763 as_bad (_("expecting prefix; got nothing"));
3765 as_bad (_("expecting mnemonic; got nothing"));
3769 /* Look up instruction (or prefix) via hash table. */
3770 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3772 if (*l != END_OF_INSN
3773 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3774 && current_templates
3775 && current_templates->start->opcode_modifier.isprefix)
3777 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3779 as_bad ((flag_code != CODE_64BIT
3780 ? _("`%s' is only supported in 64-bit mode")
3781 : _("`%s' is not supported in 64-bit mode")),
3782 current_templates->start->name);
3785 /* If we are in 16-bit mode, do not allow addr16 or data16.
3786 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3787 if ((current_templates->start->opcode_modifier.size16
3788 || current_templates->start->opcode_modifier.size32)
3789 && flag_code != CODE_64BIT
3790 && (current_templates->start->opcode_modifier.size32
3791 ^ (flag_code == CODE_16BIT)))
3793 as_bad (_("redundant %s prefix"),
3794 current_templates->start->name);
3797 /* Add prefix, checking for repeated prefixes. */
3798 switch (add_prefix (current_templates->start->base_opcode))
3803 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3804 i.hle_prefix = current_templates->start->name;
3805 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3806 i.bnd_prefix = current_templates->start->name;
3808 i.rep_prefix = current_templates->start->name;
3813 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3820 if (!current_templates)
3822 /* Check if we should swap operand or force 32bit displacement in
3824 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3826 else if (mnem_p - 3 == dot_p
3829 i.disp_encoding = disp_encoding_8bit;
3830 else if (mnem_p - 4 == dot_p
3834 i.disp_encoding = disp_encoding_32bit;
3839 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3842 if (!current_templates)
3845 /* See if we can get a match by trimming off a suffix. */
3848 case WORD_MNEM_SUFFIX:
3849 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3850 i.suffix = SHORT_MNEM_SUFFIX;
3852 case BYTE_MNEM_SUFFIX:
3853 case QWORD_MNEM_SUFFIX:
3854 i.suffix = mnem_p[-1];
3856 current_templates = (const templates *) hash_find (op_hash,
3859 case SHORT_MNEM_SUFFIX:
3860 case LONG_MNEM_SUFFIX:
3863 i.suffix = mnem_p[-1];
3865 current_templates = (const templates *) hash_find (op_hash,
3874 if (intel_float_operand (mnemonic) == 1)
3875 i.suffix = SHORT_MNEM_SUFFIX;
3877 i.suffix = LONG_MNEM_SUFFIX;
3879 current_templates = (const templates *) hash_find (op_hash,
3884 if (!current_templates)
3886 as_bad (_("no such instruction: `%s'"), token_start);
3891 if (current_templates->start->opcode_modifier.jump
3892 || current_templates->start->opcode_modifier.jumpbyte)
3894 /* Check for a branch hint. We allow ",pt" and ",pn" for
3895 predict taken and predict not taken respectively.
3896 I'm not sure that branch hints actually do anything on loop
3897 and jcxz insns (JumpByte) for current Pentium4 chips. They
3898 may work in the future and it doesn't hurt to accept them
3900 if (l[0] == ',' && l[1] == 'p')
3904 if (!add_prefix (DS_PREFIX_OPCODE))
3908 else if (l[2] == 'n')
3910 if (!add_prefix (CS_PREFIX_OPCODE))
3916 /* Any other comma loses. */
3919 as_bad (_("invalid character %s in mnemonic"),
3920 output_invalid (*l));
3924 /* Check if instruction is supported on specified architecture. */
3926 for (t = current_templates->start; t < current_templates->end; ++t)
3928 supported |= cpu_flags_match (t);
3929 if (supported == CPU_FLAGS_PERFECT_MATCH)
3933 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3935 as_bad (flag_code == CODE_64BIT
3936 ? _("`%s' is not supported in 64-bit mode")
3937 : _("`%s' is only supported in 64-bit mode"),
3938 current_templates->start->name);
3941 if (supported != CPU_FLAGS_PERFECT_MATCH)
3943 as_bad (_("`%s' is not supported on `%s%s'"),
3944 current_templates->start->name,
3945 cpu_arch_name ? cpu_arch_name : default_arch,
3946 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3951 if (!cpu_arch_flags.bitfield.cpui386
3952 && (flag_code != CODE_16BIT))
3954 as_warn (_("use .code16 to ensure correct addressing mode"));
3961 parse_operands (char *l, const char *mnemonic)
3965 /* 1 if operand is pending after ','. */
3966 unsigned int expecting_operand = 0;
3968 /* Non-zero if operand parens not balanced. */
3969 unsigned int paren_not_balanced;
3971 while (*l != END_OF_INSN)
3973 /* Skip optional white space before operand. */
3974 if (is_space_char (*l))
3976 if (!is_operand_char (*l) && *l != END_OF_INSN)
3978 as_bad (_("invalid character %s before operand %d"),
3979 output_invalid (*l),
3983 token_start = l; /* after white space */
3984 paren_not_balanced = 0;
3985 while (paren_not_balanced || *l != ',')
3987 if (*l == END_OF_INSN)
3989 if (paren_not_balanced)
3992 as_bad (_("unbalanced parenthesis in operand %d."),
3995 as_bad (_("unbalanced brackets in operand %d."),
4000 break; /* we are done */
4002 else if (!is_operand_char (*l) && !is_space_char (*l))
4004 as_bad (_("invalid character %s in operand %d"),
4005 output_invalid (*l),
4012 ++paren_not_balanced;
4014 --paren_not_balanced;
4019 ++paren_not_balanced;
4021 --paren_not_balanced;
4025 if (l != token_start)
4026 { /* Yes, we've read in another operand. */
4027 unsigned int operand_ok;
4028 this_operand = i.operands++;
4029 i.types[this_operand].bitfield.unspecified = 1;
4030 if (i.operands > MAX_OPERANDS)
4032 as_bad (_("spurious operands; (%d operands/instruction max)"),
4036 /* Now parse operand adding info to 'i' as we go along. */
4037 END_STRING_AND_SAVE (l);
4041 i386_intel_operand (token_start,
4042 intel_float_operand (mnemonic));
4044 operand_ok = i386_att_operand (token_start);
4046 RESTORE_END_STRING (l);
4052 if (expecting_operand)
4054 expecting_operand_after_comma:
4055 as_bad (_("expecting operand after ','; got nothing"));
4060 as_bad (_("expecting operand before ','; got nothing"));
4065 /* Now *l must be either ',' or END_OF_INSN. */
4068 if (*++l == END_OF_INSN)
4070 /* Just skip it, if it's \n complain. */
4071 goto expecting_operand_after_comma;
4073 expecting_operand = 1;
4080 swap_2_operands (int xchg1, int xchg2)
4082 union i386_op temp_op;
4083 i386_operand_type temp_type;
4084 enum bfd_reloc_code_real temp_reloc;
4086 temp_type = i.types[xchg2];
4087 i.types[xchg2] = i.types[xchg1];
4088 i.types[xchg1] = temp_type;
4089 temp_op = i.op[xchg2];
4090 i.op[xchg2] = i.op[xchg1];
4091 i.op[xchg1] = temp_op;
4092 temp_reloc = i.reloc[xchg2];
4093 i.reloc[xchg2] = i.reloc[xchg1];
4094 i.reloc[xchg1] = temp_reloc;
4098 if (i.mask->operand == xchg1)
4099 i.mask->operand = xchg2;
4100 else if (i.mask->operand == xchg2)
4101 i.mask->operand = xchg1;
4105 if (i.broadcast->operand == xchg1)
4106 i.broadcast->operand = xchg2;
4107 else if (i.broadcast->operand == xchg2)
4108 i.broadcast->operand = xchg1;
4112 if (i.rounding->operand == xchg1)
4113 i.rounding->operand = xchg2;
4114 else if (i.rounding->operand == xchg2)
4115 i.rounding->operand = xchg1;
4120 swap_operands (void)
4126 swap_2_operands (1, i.operands - 2);
4129 swap_2_operands (0, i.operands - 1);
4135 if (i.mem_operands == 2)
4137 const seg_entry *temp_seg;
4138 temp_seg = i.seg[0];
4139 i.seg[0] = i.seg[1];
4140 i.seg[1] = temp_seg;
4144 /* Try to ensure constant immediates are represented in the smallest
4149 char guess_suffix = 0;
4153 guess_suffix = i.suffix;
4154 else if (i.reg_operands)
4156 /* Figure out a suffix from the last register operand specified.
4157 We can't do this properly yet, ie. excluding InOutPortReg,
4158 but the following works for instructions with immediates.
4159 In any case, we can't set i.suffix yet. */
4160 for (op = i.operands; --op >= 0;)
4161 if (i.types[op].bitfield.reg8)
4163 guess_suffix = BYTE_MNEM_SUFFIX;
4166 else if (i.types[op].bitfield.reg16)
4168 guess_suffix = WORD_MNEM_SUFFIX;
4171 else if (i.types[op].bitfield.reg32)
4173 guess_suffix = LONG_MNEM_SUFFIX;
4176 else if (i.types[op].bitfield.reg64)
4178 guess_suffix = QWORD_MNEM_SUFFIX;
4182 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4183 guess_suffix = WORD_MNEM_SUFFIX;
4185 for (op = i.operands; --op >= 0;)
4186 if (operand_type_check (i.types[op], imm))
4188 switch (i.op[op].imms->X_op)
4191 /* If a suffix is given, this operand may be shortened. */
4192 switch (guess_suffix)
4194 case LONG_MNEM_SUFFIX:
4195 i.types[op].bitfield.imm32 = 1;
4196 i.types[op].bitfield.imm64 = 1;
4198 case WORD_MNEM_SUFFIX:
4199 i.types[op].bitfield.imm16 = 1;
4200 i.types[op].bitfield.imm32 = 1;
4201 i.types[op].bitfield.imm32s = 1;
4202 i.types[op].bitfield.imm64 = 1;
4204 case BYTE_MNEM_SUFFIX:
4205 i.types[op].bitfield.imm8 = 1;
4206 i.types[op].bitfield.imm8s = 1;
4207 i.types[op].bitfield.imm16 = 1;
4208 i.types[op].bitfield.imm32 = 1;
4209 i.types[op].bitfield.imm32s = 1;
4210 i.types[op].bitfield.imm64 = 1;
4214 /* If this operand is at most 16 bits, convert it
4215 to a signed 16 bit number before trying to see
4216 whether it will fit in an even smaller size.
4217 This allows a 16-bit operand such as $0xffe0 to
4218 be recognised as within Imm8S range. */
4219 if ((i.types[op].bitfield.imm16)
4220 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4222 i.op[op].imms->X_add_number =
4223 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4225 if ((i.types[op].bitfield.imm32)
4226 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4229 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4230 ^ ((offsetT) 1 << 31))
4231 - ((offsetT) 1 << 31));
4234 = operand_type_or (i.types[op],
4235 smallest_imm_type (i.op[op].imms->X_add_number));
4237 /* We must avoid matching of Imm32 templates when 64bit
4238 only immediate is available. */
4239 if (guess_suffix == QWORD_MNEM_SUFFIX)
4240 i.types[op].bitfield.imm32 = 0;
4247 /* Symbols and expressions. */
4249 /* Convert symbolic operand to proper sizes for matching, but don't
4250 prevent matching a set of insns that only supports sizes other
4251 than those matching the insn suffix. */
4253 i386_operand_type mask, allowed;
4254 const insn_template *t;
4256 operand_type_set (&mask, 0);
4257 operand_type_set (&allowed, 0);
4259 for (t = current_templates->start;
4260 t < current_templates->end;
4262 allowed = operand_type_or (allowed,
4263 t->operand_types[op]);
4264 switch (guess_suffix)
4266 case QWORD_MNEM_SUFFIX:
4267 mask.bitfield.imm64 = 1;
4268 mask.bitfield.imm32s = 1;
4270 case LONG_MNEM_SUFFIX:
4271 mask.bitfield.imm32 = 1;
4273 case WORD_MNEM_SUFFIX:
4274 mask.bitfield.imm16 = 1;
4276 case BYTE_MNEM_SUFFIX:
4277 mask.bitfield.imm8 = 1;
4282 allowed = operand_type_and (mask, allowed);
4283 if (!operand_type_all_zero (&allowed))
4284 i.types[op] = operand_type_and (i.types[op], mask);
4291 /* Try to use the smallest displacement type too. */
4293 optimize_disp (void)
4297 for (op = i.operands; --op >= 0;)
4298 if (operand_type_check (i.types[op], disp))
4300 if (i.op[op].disps->X_op == O_constant)
4302 offsetT op_disp = i.op[op].disps->X_add_number;
4304 if (i.types[op].bitfield.disp16
4305 && (op_disp & ~(offsetT) 0xffff) == 0)
4307 /* If this operand is at most 16 bits, convert
4308 to a signed 16 bit number and don't use 64bit
4310 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4311 i.types[op].bitfield.disp64 = 0;
4313 if (i.types[op].bitfield.disp32
4314 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4316 /* If this operand is at most 32 bits, convert
4317 to a signed 32 bit number and don't use 64bit
4319 op_disp &= (((offsetT) 2 << 31) - 1);
4320 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4321 i.types[op].bitfield.disp64 = 0;
4323 if (!op_disp && i.types[op].bitfield.baseindex)
4325 i.types[op].bitfield.disp8 = 0;
4326 i.types[op].bitfield.disp16 = 0;
4327 i.types[op].bitfield.disp32 = 0;
4328 i.types[op].bitfield.disp32s = 0;
4329 i.types[op].bitfield.disp64 = 0;
4333 else if (flag_code == CODE_64BIT)
4335 if (fits_in_signed_long (op_disp))
4337 i.types[op].bitfield.disp64 = 0;
4338 i.types[op].bitfield.disp32s = 1;
4340 if (i.prefix[ADDR_PREFIX]
4341 && fits_in_unsigned_long (op_disp))
4342 i.types[op].bitfield.disp32 = 1;
4344 if ((i.types[op].bitfield.disp32
4345 || i.types[op].bitfield.disp32s
4346 || i.types[op].bitfield.disp16)
4347 && fits_in_signed_byte (op_disp))
4348 i.types[op].bitfield.disp8 = 1;
4350 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4351 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4353 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4354 i.op[op].disps, 0, i.reloc[op]);
4355 i.types[op].bitfield.disp8 = 0;
4356 i.types[op].bitfield.disp16 = 0;
4357 i.types[op].bitfield.disp32 = 0;
4358 i.types[op].bitfield.disp32s = 0;
4359 i.types[op].bitfield.disp64 = 0;
4362 /* We only support 64bit displacement on constants. */
4363 i.types[op].bitfield.disp64 = 0;
4367 /* Check if operands are valid for the instruction. */
4370 check_VecOperands (const insn_template *t)
4374 /* Without VSIB byte, we can't have a vector register for index. */
4375 if (!t->opcode_modifier.vecsib
4377 && (i.index_reg->reg_type.bitfield.regxmm
4378 || i.index_reg->reg_type.bitfield.regymm
4379 || i.index_reg->reg_type.bitfield.regzmm))
4381 i.error = unsupported_vector_index_register;
4385 /* Check if default mask is allowed. */
4386 if (t->opcode_modifier.nodefmask
4387 && (!i.mask || i.mask->mask->reg_num == 0))
4389 i.error = no_default_mask;
4393 /* For VSIB byte, we need a vector register for index, and all vector
4394 registers must be distinct. */
4395 if (t->opcode_modifier.vecsib)
4398 || !((t->opcode_modifier.vecsib == VecSIB128
4399 && i.index_reg->reg_type.bitfield.regxmm)
4400 || (t->opcode_modifier.vecsib == VecSIB256
4401 && i.index_reg->reg_type.bitfield.regymm)
4402 || (t->opcode_modifier.vecsib == VecSIB512
4403 && i.index_reg->reg_type.bitfield.regzmm)))
4405 i.error = invalid_vsib_address;
4409 gas_assert (i.reg_operands == 2 || i.mask);
4410 if (i.reg_operands == 2 && !i.mask)
4412 gas_assert (i.types[0].bitfield.regxmm
4413 || i.types[0].bitfield.regymm);
4414 gas_assert (i.types[2].bitfield.regxmm
4415 || i.types[2].bitfield.regymm);
4416 if (operand_check == check_none)
4418 if (register_number (i.op[0].regs)
4419 != register_number (i.index_reg)
4420 && register_number (i.op[2].regs)
4421 != register_number (i.index_reg)
4422 && register_number (i.op[0].regs)
4423 != register_number (i.op[2].regs))
4425 if (operand_check == check_error)
4427 i.error = invalid_vector_register_set;
4430 as_warn (_("mask, index, and destination registers should be distinct"));
4432 else if (i.reg_operands == 1 && i.mask)
4434 if ((i.types[1].bitfield.regymm
4435 || i.types[1].bitfield.regzmm)
4436 && (register_number (i.op[1].regs)
4437 == register_number (i.index_reg)))
4439 if (operand_check == check_error)
4441 i.error = invalid_vector_register_set;
4444 if (operand_check != check_none)
4445 as_warn (_("index and destination registers should be distinct"));
4450 /* Check if broadcast is supported by the instruction and is applied
4451 to the memory operand. */
4454 int broadcasted_opnd_size;
4456 /* Check if specified broadcast is supported in this instruction,
4457 and it's applied to memory operand of DWORD or QWORD type,
4458 depending on VecESize. */
4459 if (i.broadcast->type != t->opcode_modifier.broadcast
4460 || !i.types[i.broadcast->operand].bitfield.mem
4461 || (t->opcode_modifier.vecesize == 0
4462 && !i.types[i.broadcast->operand].bitfield.dword
4463 && !i.types[i.broadcast->operand].bitfield.unspecified)
4464 || (t->opcode_modifier.vecesize == 1
4465 && !i.types[i.broadcast->operand].bitfield.qword
4466 && !i.types[i.broadcast->operand].bitfield.unspecified))
4469 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4470 if (i.broadcast->type == BROADCAST_1TO16)
4471 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4472 else if (i.broadcast->type == BROADCAST_1TO8)
4473 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4474 else if (i.broadcast->type == BROADCAST_1TO4)
4475 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4476 else if (i.broadcast->type == BROADCAST_1TO2)
4477 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
4481 if ((broadcasted_opnd_size == 256
4482 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4483 || (broadcasted_opnd_size == 512
4484 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4487 i.error = unsupported_broadcast;
4491 /* If broadcast is supported in this instruction, we need to check if
4492 operand of one-element size isn't specified without broadcast. */
4493 else if (t->opcode_modifier.broadcast && i.mem_operands)
4495 /* Find memory operand. */
4496 for (op = 0; op < i.operands; op++)
4497 if (operand_type_check (i.types[op], anymem))
4499 gas_assert (op < i.operands);
4500 /* Check size of the memory operand. */
4501 if ((t->opcode_modifier.vecesize == 0
4502 && i.types[op].bitfield.dword)
4503 || (t->opcode_modifier.vecesize == 1
4504 && i.types[op].bitfield.qword))
4506 i.error = broadcast_needed;
4511 /* Check if requested masking is supported. */
4513 && (!t->opcode_modifier.masking
4515 && t->opcode_modifier.masking == MERGING_MASKING)))
4517 i.error = unsupported_masking;
4521 /* Check if masking is applied to dest operand. */
4522 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4524 i.error = mask_not_on_destination;
4531 if ((i.rounding->type != saeonly
4532 && !t->opcode_modifier.staticrounding)
4533 || (i.rounding->type == saeonly
4534 && (t->opcode_modifier.staticrounding
4535 || !t->opcode_modifier.sae)))
4537 i.error = unsupported_rc_sae;
4540 /* If the instruction has several immediate operands and one of
4541 them is rounding, the rounding operand should be the last
4542 immediate operand. */
4543 if (i.imm_operands > 1
4544 && i.rounding->operand != (int) (i.imm_operands - 1))
4546 i.error = rc_sae_operand_not_last_imm;
4551 /* Check vector Disp8 operand. */
4552 if (t->opcode_modifier.disp8memshift)
4555 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4557 i.memshift = t->opcode_modifier.disp8memshift;
4559 for (op = 0; op < i.operands; op++)
4560 if (operand_type_check (i.types[op], disp)
4561 && i.op[op].disps->X_op == O_constant)
4563 offsetT value = i.op[op].disps->X_add_number;
4564 int vec_disp8_ok = fits_in_vec_disp8 (value);
4565 if (t->operand_types [op].bitfield.vec_disp8)
4568 i.types[op].bitfield.vec_disp8 = 1;
4571 /* Vector insn can only have Vec_Disp8/Disp32 in
4572 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4574 i.types[op].bitfield.disp8 = 0;
4575 if (flag_code != CODE_16BIT)
4576 i.types[op].bitfield.disp16 = 0;
4579 else if (flag_code != CODE_16BIT)
4581 /* One form of this instruction supports vector Disp8.
4582 Try vector Disp8 if we need to use Disp32. */
4583 if (vec_disp8_ok && !fits_in_signed_byte (value))
4585 i.error = try_vector_disp8;
4597 /* Check if operands are valid for the instruction. Update VEX
4601 VEX_check_operands (const insn_template *t)
4603 /* VREX is only valid with EVEX prefix. */
4604 if (i.need_vrex && !t->opcode_modifier.evex)
4606 i.error = invalid_register_operand;
4610 if (!t->opcode_modifier.vex)
4613 /* Only check VEX_Imm4, which must be the first operand. */
4614 if (t->operand_types[0].bitfield.vec_imm4)
4616 if (i.op[0].imms->X_op != O_constant
4617 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4623 /* Turn off Imm8 so that update_imm won't complain. */
4624 i.types[0] = vec_imm4;
4630 static const insn_template *
4631 match_template (void)
4633 /* Points to template once we've found it. */
4634 const insn_template *t;
4635 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4636 i386_operand_type overlap4;
4637 unsigned int found_reverse_match;
4638 i386_opcode_modifier suffix_check;
4639 i386_operand_type operand_types [MAX_OPERANDS];
4640 int addr_prefix_disp;
4642 unsigned int found_cpu_match;
4643 unsigned int check_register;
4644 enum i386_error specific_error = 0;
4646 #if MAX_OPERANDS != 5
4647 # error "MAX_OPERANDS must be 5."
4650 found_reverse_match = 0;
4651 addr_prefix_disp = -1;
4653 memset (&suffix_check, 0, sizeof (suffix_check));
4654 if (i.suffix == BYTE_MNEM_SUFFIX)
4655 suffix_check.no_bsuf = 1;
4656 else if (i.suffix == WORD_MNEM_SUFFIX)
4657 suffix_check.no_wsuf = 1;
4658 else if (i.suffix == SHORT_MNEM_SUFFIX)
4659 suffix_check.no_ssuf = 1;
4660 else if (i.suffix == LONG_MNEM_SUFFIX)
4661 suffix_check.no_lsuf = 1;
4662 else if (i.suffix == QWORD_MNEM_SUFFIX)
4663 suffix_check.no_qsuf = 1;
4664 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4665 suffix_check.no_ldsuf = 1;
4667 /* Must have right number of operands. */
4668 i.error = number_of_operands_mismatch;
4670 for (t = current_templates->start; t < current_templates->end; t++)
4672 addr_prefix_disp = -1;
4674 if (i.operands != t->operands)
4677 /* Check processor support. */
4678 i.error = unsupported;
4679 found_cpu_match = (cpu_flags_match (t)
4680 == CPU_FLAGS_PERFECT_MATCH);
4681 if (!found_cpu_match)
4684 /* Check old gcc support. */
4685 i.error = old_gcc_only;
4686 if (!old_gcc && t->opcode_modifier.oldgcc)
4689 /* Check AT&T mnemonic. */
4690 i.error = unsupported_with_intel_mnemonic;
4691 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4694 /* Check AT&T/Intel syntax. */
4695 i.error = unsupported_syntax;
4696 if ((intel_syntax && t->opcode_modifier.attsyntax)
4697 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4700 /* Check the suffix, except for some instructions in intel mode. */
4701 i.error = invalid_instruction_suffix;
4702 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4703 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4704 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4705 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4706 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4707 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4708 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4711 if (!operand_size_match (t))
4714 for (j = 0; j < MAX_OPERANDS; j++)
4715 operand_types[j] = t->operand_types[j];
4717 /* In general, don't allow 64-bit operands in 32-bit mode. */
4718 if (i.suffix == QWORD_MNEM_SUFFIX
4719 && flag_code != CODE_64BIT
4721 ? (!t->opcode_modifier.ignoresize
4722 && !intel_float_operand (t->name))
4723 : intel_float_operand (t->name) != 2)
4724 && ((!operand_types[0].bitfield.regmmx
4725 && !operand_types[0].bitfield.regxmm
4726 && !operand_types[0].bitfield.regymm
4727 && !operand_types[0].bitfield.regzmm)
4728 || (!operand_types[t->operands > 1].bitfield.regmmx
4729 && operand_types[t->operands > 1].bitfield.regxmm
4730 && operand_types[t->operands > 1].bitfield.regymm
4731 && operand_types[t->operands > 1].bitfield.regzmm))
4732 && (t->base_opcode != 0x0fc7
4733 || t->extension_opcode != 1 /* cmpxchg8b */))
4736 /* In general, don't allow 32-bit operands on pre-386. */
4737 else if (i.suffix == LONG_MNEM_SUFFIX
4738 && !cpu_arch_flags.bitfield.cpui386
4740 ? (!t->opcode_modifier.ignoresize
4741 && !intel_float_operand (t->name))
4742 : intel_float_operand (t->name) != 2)
4743 && ((!operand_types[0].bitfield.regmmx
4744 && !operand_types[0].bitfield.regxmm)
4745 || (!operand_types[t->operands > 1].bitfield.regmmx
4746 && operand_types[t->operands > 1].bitfield.regxmm)))
4749 /* Do not verify operands when there are none. */
4753 /* We've found a match; break out of loop. */
4757 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4758 into Disp32/Disp16/Disp32 operand. */
4759 if (i.prefix[ADDR_PREFIX] != 0)
4761 /* There should be only one Disp operand. */
4765 for (j = 0; j < MAX_OPERANDS; j++)
4767 if (operand_types[j].bitfield.disp16)
4769 addr_prefix_disp = j;
4770 operand_types[j].bitfield.disp32 = 1;
4771 operand_types[j].bitfield.disp16 = 0;
4777 for (j = 0; j < MAX_OPERANDS; j++)
4779 if (operand_types[j].bitfield.disp32)
4781 addr_prefix_disp = j;
4782 operand_types[j].bitfield.disp32 = 0;
4783 operand_types[j].bitfield.disp16 = 1;
4789 for (j = 0; j < MAX_OPERANDS; j++)
4791 if (operand_types[j].bitfield.disp64)
4793 addr_prefix_disp = j;
4794 operand_types[j].bitfield.disp64 = 0;
4795 operand_types[j].bitfield.disp32 = 1;
4803 /* We check register size if needed. */
4804 check_register = t->opcode_modifier.checkregsize;
4805 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4806 switch (t->operands)
4809 if (!operand_type_match (overlap0, i.types[0]))
4813 /* xchg %eax, %eax is a special case. It is an aliase for nop
4814 only in 32bit mode and we can use opcode 0x90. In 64bit
4815 mode, we can't use 0x90 for xchg %eax, %eax since it should
4816 zero-extend %eax to %rax. */
4817 if (flag_code == CODE_64BIT
4818 && t->base_opcode == 0x90
4819 && operand_type_equal (&i.types [0], &acc32)
4820 && operand_type_equal (&i.types [1], &acc32))
4824 /* If we swap operand in encoding, we either match
4825 the next one or reverse direction of operands. */
4826 if (t->opcode_modifier.s)
4828 else if (t->opcode_modifier.d)
4833 /* If we swap operand in encoding, we match the next one. */
4834 if (i.swap_operand && t->opcode_modifier.s)
4838 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4839 if (!operand_type_match (overlap0, i.types[0])
4840 || !operand_type_match (overlap1, i.types[1])
4842 && !operand_type_register_match (overlap0, i.types[0],
4844 overlap1, i.types[1],
4847 /* Check if other direction is valid ... */
4848 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4852 /* Try reversing direction of operands. */
4853 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4854 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4855 if (!operand_type_match (overlap0, i.types[0])
4856 || !operand_type_match (overlap1, i.types[1])
4858 && !operand_type_register_match (overlap0,
4865 /* Does not match either direction. */
4868 /* found_reverse_match holds which of D or FloatDR
4870 if (t->opcode_modifier.d)
4871 found_reverse_match = Opcode_D;
4872 else if (t->opcode_modifier.floatd)
4873 found_reverse_match = Opcode_FloatD;
4875 found_reverse_match = 0;
4876 if (t->opcode_modifier.floatr)
4877 found_reverse_match |= Opcode_FloatR;
4881 /* Found a forward 2 operand match here. */
4882 switch (t->operands)
4885 overlap4 = operand_type_and (i.types[4],
4888 overlap3 = operand_type_and (i.types[3],
4891 overlap2 = operand_type_and (i.types[2],
4896 switch (t->operands)
4899 if (!operand_type_match (overlap4, i.types[4])
4900 || !operand_type_register_match (overlap3,
4908 if (!operand_type_match (overlap3, i.types[3])
4910 && !operand_type_register_match (overlap2,
4918 /* Here we make use of the fact that there are no
4919 reverse match 3 operand instructions, and all 3
4920 operand instructions only need to be checked for
4921 register consistency between operands 2 and 3. */
4922 if (!operand_type_match (overlap2, i.types[2])
4924 && !operand_type_register_match (overlap1,
4934 /* Found either forward/reverse 2, 3 or 4 operand match here:
4935 slip through to break. */
4937 if (!found_cpu_match)
4939 found_reverse_match = 0;
4943 /* Check if vector and VEX operands are valid. */
4944 if (check_VecOperands (t) || VEX_check_operands (t))
4946 specific_error = i.error;
4950 /* We've found a match; break out of loop. */
4954 if (t == current_templates->end)
4956 /* We found no match. */
4957 const char *err_msg;
4958 switch (specific_error ? specific_error : i.error)
4962 case operand_size_mismatch:
4963 err_msg = _("operand size mismatch");
4965 case operand_type_mismatch:
4966 err_msg = _("operand type mismatch");
4968 case register_type_mismatch:
4969 err_msg = _("register type mismatch");
4971 case number_of_operands_mismatch:
4972 err_msg = _("number of operands mismatch");
4974 case invalid_instruction_suffix:
4975 err_msg = _("invalid instruction suffix");
4978 err_msg = _("constant doesn't fit in 4 bits");
4981 err_msg = _("only supported with old gcc");
4983 case unsupported_with_intel_mnemonic:
4984 err_msg = _("unsupported with Intel mnemonic");
4986 case unsupported_syntax:
4987 err_msg = _("unsupported syntax");
4990 as_bad (_("unsupported instruction `%s'"),
4991 current_templates->start->name);
4993 case invalid_vsib_address:
4994 err_msg = _("invalid VSIB address");
4996 case invalid_vector_register_set:
4997 err_msg = _("mask, index, and destination registers must be distinct");
4999 case unsupported_vector_index_register:
5000 err_msg = _("unsupported vector index register");
5002 case unsupported_broadcast:
5003 err_msg = _("unsupported broadcast");
5005 case broadcast_not_on_src_operand:
5006 err_msg = _("broadcast not on source memory operand");
5008 case broadcast_needed:
5009 err_msg = _("broadcast is needed for operand of such type");
5011 case unsupported_masking:
5012 err_msg = _("unsupported masking");
5014 case mask_not_on_destination:
5015 err_msg = _("mask not on destination operand");
5017 case no_default_mask:
5018 err_msg = _("default mask isn't allowed");
5020 case unsupported_rc_sae:
5021 err_msg = _("unsupported static rounding/sae");
5023 case rc_sae_operand_not_last_imm:
5025 err_msg = _("RC/SAE operand must precede immediate operands");
5027 err_msg = _("RC/SAE operand must follow immediate operands");
5029 case invalid_register_operand:
5030 err_msg = _("invalid register operand");
5033 as_bad (_("%s for `%s'"), err_msg,
5034 current_templates->start->name);
5038 if (!quiet_warnings)
5041 && (i.types[0].bitfield.jumpabsolute
5042 != operand_types[0].bitfield.jumpabsolute))
5044 as_warn (_("indirect %s without `*'"), t->name);
5047 if (t->opcode_modifier.isprefix
5048 && t->opcode_modifier.ignoresize)
5050 /* Warn them that a data or address size prefix doesn't
5051 affect assembly of the next line of code. */
5052 as_warn (_("stand-alone `%s' prefix"), t->name);
5056 /* Copy the template we found. */
5059 if (addr_prefix_disp != -1)
5060 i.tm.operand_types[addr_prefix_disp]
5061 = operand_types[addr_prefix_disp];
5063 if (found_reverse_match)
5065 /* If we found a reverse match we must alter the opcode
5066 direction bit. found_reverse_match holds bits to change
5067 (different for int & float insns). */
5069 i.tm.base_opcode ^= found_reverse_match;
5071 i.tm.operand_types[0] = operand_types[1];
5072 i.tm.operand_types[1] = operand_types[0];
5081 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5082 if (i.tm.operand_types[mem_op].bitfield.esseg)
5084 if (i.seg[0] != NULL && i.seg[0] != &es)
5086 as_bad (_("`%s' operand %d must use `%ses' segment"),
5092 /* There's only ever one segment override allowed per instruction.
5093 This instruction possibly has a legal segment override on the
5094 second operand, so copy the segment to where non-string
5095 instructions store it, allowing common code. */
5096 i.seg[0] = i.seg[1];
5098 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5100 if (i.seg[1] != NULL && i.seg[1] != &es)
5102 as_bad (_("`%s' operand %d must use `%ses' segment"),
5113 process_suffix (void)
5115 /* If matched instruction specifies an explicit instruction mnemonic
5117 if (i.tm.opcode_modifier.size16)
5118 i.suffix = WORD_MNEM_SUFFIX;
5119 else if (i.tm.opcode_modifier.size32)
5120 i.suffix = LONG_MNEM_SUFFIX;
5121 else if (i.tm.opcode_modifier.size64)
5122 i.suffix = QWORD_MNEM_SUFFIX;
5123 else if (i.reg_operands)
5125 /* If there's no instruction mnemonic suffix we try to invent one
5126 based on register operands. */
5129 /* We take i.suffix from the last register operand specified,
5130 Destination register type is more significant than source
5131 register type. crc32 in SSE4.2 prefers source register
5133 if (i.tm.base_opcode == 0xf20f38f1)
5135 if (i.types[0].bitfield.reg16)
5136 i.suffix = WORD_MNEM_SUFFIX;
5137 else if (i.types[0].bitfield.reg32)
5138 i.suffix = LONG_MNEM_SUFFIX;
5139 else if (i.types[0].bitfield.reg64)
5140 i.suffix = QWORD_MNEM_SUFFIX;
5142 else if (i.tm.base_opcode == 0xf20f38f0)
5144 if (i.types[0].bitfield.reg8)
5145 i.suffix = BYTE_MNEM_SUFFIX;
5152 if (i.tm.base_opcode == 0xf20f38f1
5153 || i.tm.base_opcode == 0xf20f38f0)
5155 /* We have to know the operand size for crc32. */
5156 as_bad (_("ambiguous memory operand size for `%s`"),
5161 for (op = i.operands; --op >= 0;)
5162 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5164 if (i.types[op].bitfield.reg8)
5166 i.suffix = BYTE_MNEM_SUFFIX;
5169 else if (i.types[op].bitfield.reg16)
5171 i.suffix = WORD_MNEM_SUFFIX;
5174 else if (i.types[op].bitfield.reg32)
5176 i.suffix = LONG_MNEM_SUFFIX;
5179 else if (i.types[op].bitfield.reg64)
5181 i.suffix = QWORD_MNEM_SUFFIX;
5187 else if (i.suffix == BYTE_MNEM_SUFFIX)
5190 && i.tm.opcode_modifier.ignoresize
5191 && i.tm.opcode_modifier.no_bsuf)
5193 else if (!check_byte_reg ())
5196 else if (i.suffix == LONG_MNEM_SUFFIX)
5199 && i.tm.opcode_modifier.ignoresize
5200 && i.tm.opcode_modifier.no_lsuf)
5202 else if (!check_long_reg ())
5205 else if (i.suffix == QWORD_MNEM_SUFFIX)
5208 && i.tm.opcode_modifier.ignoresize
5209 && i.tm.opcode_modifier.no_qsuf)
5211 else if (!check_qword_reg ())
5214 else if (i.suffix == WORD_MNEM_SUFFIX)
5217 && i.tm.opcode_modifier.ignoresize
5218 && i.tm.opcode_modifier.no_wsuf)
5220 else if (!check_word_reg ())
5223 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5224 || i.suffix == YMMWORD_MNEM_SUFFIX
5225 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5227 /* Skip if the instruction has x/y/z suffix. match_template
5228 should check if it is a valid suffix. */
5230 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5231 /* Do nothing if the instruction is going to ignore the prefix. */
5236 else if (i.tm.opcode_modifier.defaultsize
5238 /* exclude fldenv/frstor/fsave/fstenv */
5239 && i.tm.opcode_modifier.no_ssuf)
5241 i.suffix = stackop_size;
5243 else if (intel_syntax
5245 && (i.tm.operand_types[0].bitfield.jumpabsolute
5246 || i.tm.opcode_modifier.jumpbyte
5247 || i.tm.opcode_modifier.jumpintersegment
5248 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5249 && i.tm.extension_opcode <= 3)))
5254 if (!i.tm.opcode_modifier.no_qsuf)
5256 i.suffix = QWORD_MNEM_SUFFIX;
5260 if (!i.tm.opcode_modifier.no_lsuf)
5261 i.suffix = LONG_MNEM_SUFFIX;
5264 if (!i.tm.opcode_modifier.no_wsuf)
5265 i.suffix = WORD_MNEM_SUFFIX;
5274 if (i.tm.opcode_modifier.w)
5276 as_bad (_("no instruction mnemonic suffix given and "
5277 "no register operands; can't size instruction"));
5283 unsigned int suffixes;
5285 suffixes = !i.tm.opcode_modifier.no_bsuf;
5286 if (!i.tm.opcode_modifier.no_wsuf)
5288 if (!i.tm.opcode_modifier.no_lsuf)
5290 if (!i.tm.opcode_modifier.no_ldsuf)
5292 if (!i.tm.opcode_modifier.no_ssuf)
5294 if (!i.tm.opcode_modifier.no_qsuf)
5297 /* There are more than suffix matches. */
5298 if (i.tm.opcode_modifier.w
5299 || ((suffixes & (suffixes - 1))
5300 && !i.tm.opcode_modifier.defaultsize
5301 && !i.tm.opcode_modifier.ignoresize))
5303 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5309 /* Change the opcode based on the operand size given by i.suffix;
5310 We don't need to change things for byte insns. */
5313 && i.suffix != BYTE_MNEM_SUFFIX
5314 && i.suffix != XMMWORD_MNEM_SUFFIX
5315 && i.suffix != YMMWORD_MNEM_SUFFIX
5316 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5318 /* It's not a byte, select word/dword operation. */
5319 if (i.tm.opcode_modifier.w)
5321 if (i.tm.opcode_modifier.shortform)
5322 i.tm.base_opcode |= 8;
5324 i.tm.base_opcode |= 1;
5327 /* Now select between word & dword operations via the operand
5328 size prefix, except for instructions that will ignore this
5330 if (i.tm.opcode_modifier.addrprefixop0)
5332 /* The address size override prefix changes the size of the
5334 if ((flag_code == CODE_32BIT
5335 && i.op->regs[0].reg_type.bitfield.reg16)
5336 || (flag_code != CODE_32BIT
5337 && i.op->regs[0].reg_type.bitfield.reg32))
5338 if (!add_prefix (ADDR_PREFIX_OPCODE))
5341 else if (i.suffix != QWORD_MNEM_SUFFIX
5342 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5343 && !i.tm.opcode_modifier.ignoresize
5344 && !i.tm.opcode_modifier.floatmf
5345 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5346 || (flag_code == CODE_64BIT
5347 && i.tm.opcode_modifier.jumpbyte)))
5349 unsigned int prefix = DATA_PREFIX_OPCODE;
5351 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5352 prefix = ADDR_PREFIX_OPCODE;
5354 if (!add_prefix (prefix))
5358 /* Set mode64 for an operand. */
5359 if (i.suffix == QWORD_MNEM_SUFFIX
5360 && flag_code == CODE_64BIT
5361 && !i.tm.opcode_modifier.norex64)
5363 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5364 need rex64. cmpxchg8b is also a special case. */
5365 if (! (i.operands == 2
5366 && i.tm.base_opcode == 0x90
5367 && i.tm.extension_opcode == None
5368 && operand_type_equal (&i.types [0], &acc64)
5369 && operand_type_equal (&i.types [1], &acc64))
5370 && ! (i.operands == 1
5371 && i.tm.base_opcode == 0xfc7
5372 && i.tm.extension_opcode == 1
5373 && !operand_type_check (i.types [0], reg)
5374 && operand_type_check (i.types [0], anymem)))
5378 /* Size floating point instruction. */
5379 if (i.suffix == LONG_MNEM_SUFFIX)
5380 if (i.tm.opcode_modifier.floatmf)
5381 i.tm.base_opcode ^= 4;
5388 check_byte_reg (void)
5392 for (op = i.operands; --op >= 0;)
5394 /* If this is an eight bit register, it's OK. If it's the 16 or
5395 32 bit version of an eight bit register, we will just use the
5396 low portion, and that's OK too. */
5397 if (i.types[op].bitfield.reg8)
5400 /* I/O port address operands are OK too. */
5401 if (i.tm.operand_types[op].bitfield.inoutportreg)
5404 /* crc32 doesn't generate this warning. */
5405 if (i.tm.base_opcode == 0xf20f38f0)
5408 if ((i.types[op].bitfield.reg16
5409 || i.types[op].bitfield.reg32
5410 || i.types[op].bitfield.reg64)
5411 && i.op[op].regs->reg_num < 4
5412 /* Prohibit these changes in 64bit mode, since the lowering
5413 would be more complicated. */
5414 && flag_code != CODE_64BIT)
5416 #if REGISTER_WARNINGS
5417 if (!quiet_warnings)
5418 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5420 (i.op[op].regs + (i.types[op].bitfield.reg16
5421 ? REGNAM_AL - REGNAM_AX
5422 : REGNAM_AL - REGNAM_EAX))->reg_name,
5424 i.op[op].regs->reg_name,
5429 /* Any other register is bad. */
5430 if (i.types[op].bitfield.reg16
5431 || i.types[op].bitfield.reg32
5432 || i.types[op].bitfield.reg64
5433 || i.types[op].bitfield.regmmx
5434 || i.types[op].bitfield.regxmm
5435 || i.types[op].bitfield.regymm
5436 || i.types[op].bitfield.regzmm
5437 || i.types[op].bitfield.sreg2
5438 || i.types[op].bitfield.sreg3
5439 || i.types[op].bitfield.control
5440 || i.types[op].bitfield.debug
5441 || i.types[op].bitfield.test
5442 || i.types[op].bitfield.floatreg
5443 || i.types[op].bitfield.floatacc)
5445 as_bad (_("`%s%s' not allowed with `%s%c'"),
5447 i.op[op].regs->reg_name,
5457 check_long_reg (void)
5461 for (op = i.operands; --op >= 0;)
5462 /* Reject eight bit registers, except where the template requires
5463 them. (eg. movzb) */
5464 if (i.types[op].bitfield.reg8
5465 && (i.tm.operand_types[op].bitfield.reg16
5466 || i.tm.operand_types[op].bitfield.reg32
5467 || i.tm.operand_types[op].bitfield.acc))
5469 as_bad (_("`%s%s' not allowed with `%s%c'"),
5471 i.op[op].regs->reg_name,
5476 /* Warn if the e prefix on a general reg is missing. */
5477 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5478 && i.types[op].bitfield.reg16
5479 && (i.tm.operand_types[op].bitfield.reg32
5480 || i.tm.operand_types[op].bitfield.acc))
5482 /* Prohibit these changes in the 64bit mode, since the
5483 lowering is more complicated. */
5484 if (flag_code == CODE_64BIT)
5486 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5487 register_prefix, i.op[op].regs->reg_name,
5491 #if REGISTER_WARNINGS
5492 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5494 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5495 register_prefix, i.op[op].regs->reg_name, i.suffix);
5498 /* Warn if the r prefix on a general reg is present. */
5499 else if (i.types[op].bitfield.reg64
5500 && (i.tm.operand_types[op].bitfield.reg32
5501 || i.tm.operand_types[op].bitfield.acc))
5504 && i.tm.opcode_modifier.toqword
5505 && !i.types[0].bitfield.regxmm)
5507 /* Convert to QWORD. We want REX byte. */
5508 i.suffix = QWORD_MNEM_SUFFIX;
5512 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5513 register_prefix, i.op[op].regs->reg_name,
5522 check_qword_reg (void)
5526 for (op = i.operands; --op >= 0; )
5527 /* Reject eight bit registers, except where the template requires
5528 them. (eg. movzb) */
5529 if (i.types[op].bitfield.reg8
5530 && (i.tm.operand_types[op].bitfield.reg16
5531 || i.tm.operand_types[op].bitfield.reg32
5532 || i.tm.operand_types[op].bitfield.acc))
5534 as_bad (_("`%s%s' not allowed with `%s%c'"),
5536 i.op[op].regs->reg_name,
5541 /* Warn if the r prefix on a general reg is missing. */
5542 else if ((i.types[op].bitfield.reg16
5543 || i.types[op].bitfield.reg32)
5544 && (i.tm.operand_types[op].bitfield.reg32
5545 || i.tm.operand_types[op].bitfield.acc))
5547 /* Prohibit these changes in the 64bit mode, since the
5548 lowering is more complicated. */
5550 && i.tm.opcode_modifier.todword
5551 && !i.types[0].bitfield.regxmm)
5553 /* Convert to DWORD. We don't want REX byte. */
5554 i.suffix = LONG_MNEM_SUFFIX;
5558 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5559 register_prefix, i.op[op].regs->reg_name,
5568 check_word_reg (void)
5571 for (op = i.operands; --op >= 0;)
5572 /* Reject eight bit registers, except where the template requires
5573 them. (eg. movzb) */
5574 if (i.types[op].bitfield.reg8
5575 && (i.tm.operand_types[op].bitfield.reg16
5576 || i.tm.operand_types[op].bitfield.reg32
5577 || i.tm.operand_types[op].bitfield.acc))
5579 as_bad (_("`%s%s' not allowed with `%s%c'"),
5581 i.op[op].regs->reg_name,
5586 /* Warn if the e or r prefix on a general reg is present. */
5587 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5588 && (i.types[op].bitfield.reg32
5589 || i.types[op].bitfield.reg64)
5590 && (i.tm.operand_types[op].bitfield.reg16
5591 || i.tm.operand_types[op].bitfield.acc))
5593 /* Prohibit these changes in the 64bit mode, since the
5594 lowering is more complicated. */
5595 if (flag_code == CODE_64BIT)
5597 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5598 register_prefix, i.op[op].regs->reg_name,
5602 #if REGISTER_WARNINGS
5603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5605 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5606 register_prefix, i.op[op].regs->reg_name, i.suffix);
5613 update_imm (unsigned int j)
5615 i386_operand_type overlap = i.types[j];
5616 if ((overlap.bitfield.imm8
5617 || overlap.bitfield.imm8s
5618 || overlap.bitfield.imm16
5619 || overlap.bitfield.imm32
5620 || overlap.bitfield.imm32s
5621 || overlap.bitfield.imm64)
5622 && !operand_type_equal (&overlap, &imm8)
5623 && !operand_type_equal (&overlap, &imm8s)
5624 && !operand_type_equal (&overlap, &imm16)
5625 && !operand_type_equal (&overlap, &imm32)
5626 && !operand_type_equal (&overlap, &imm32s)
5627 && !operand_type_equal (&overlap, &imm64))
5631 i386_operand_type temp;
5633 operand_type_set (&temp, 0);
5634 if (i.suffix == BYTE_MNEM_SUFFIX)
5636 temp.bitfield.imm8 = overlap.bitfield.imm8;
5637 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5639 else if (i.suffix == WORD_MNEM_SUFFIX)
5640 temp.bitfield.imm16 = overlap.bitfield.imm16;
5641 else if (i.suffix == QWORD_MNEM_SUFFIX)
5643 temp.bitfield.imm64 = overlap.bitfield.imm64;
5644 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5647 temp.bitfield.imm32 = overlap.bitfield.imm32;
5650 else if (operand_type_equal (&overlap, &imm16_32_32s)
5651 || operand_type_equal (&overlap, &imm16_32)
5652 || operand_type_equal (&overlap, &imm16_32s))
5654 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5659 if (!operand_type_equal (&overlap, &imm8)
5660 && !operand_type_equal (&overlap, &imm8s)
5661 && !operand_type_equal (&overlap, &imm16)
5662 && !operand_type_equal (&overlap, &imm32)
5663 && !operand_type_equal (&overlap, &imm32s)
5664 && !operand_type_equal (&overlap, &imm64))
5666 as_bad (_("no instruction mnemonic suffix given; "
5667 "can't determine immediate size"));
5671 i.types[j] = overlap;
5681 /* Update the first 2 immediate operands. */
5682 n = i.operands > 2 ? 2 : i.operands;
5685 for (j = 0; j < n; j++)
5686 if (update_imm (j) == 0)
5689 /* The 3rd operand can't be immediate operand. */
5690 gas_assert (operand_type_check (i.types[2], imm) == 0);
5697 bad_implicit_operand (int xmm)
5699 const char *ireg = xmm ? "xmm0" : "ymm0";
5702 as_bad (_("the last operand of `%s' must be `%s%s'"),
5703 i.tm.name, register_prefix, ireg);
5705 as_bad (_("the first operand of `%s' must be `%s%s'"),
5706 i.tm.name, register_prefix, ireg);
5711 process_operands (void)
5713 /* Default segment register this instruction will use for memory
5714 accesses. 0 means unknown. This is only for optimizing out
5715 unnecessary segment overrides. */
5716 const seg_entry *default_seg = 0;
5718 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5720 unsigned int dupl = i.operands;
5721 unsigned int dest = dupl - 1;
5724 /* The destination must be an xmm register. */
5725 gas_assert (i.reg_operands
5726 && MAX_OPERANDS > dupl
5727 && operand_type_equal (&i.types[dest], ®xmm));
5729 if (i.tm.opcode_modifier.firstxmm0)
5731 /* The first operand is implicit and must be xmm0. */
5732 gas_assert (operand_type_equal (&i.types[0], ®xmm));
5733 if (register_number (i.op[0].regs) != 0)
5734 return bad_implicit_operand (1);
5736 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5738 /* Keep xmm0 for instructions with VEX prefix and 3
5744 /* We remove the first xmm0 and keep the number of
5745 operands unchanged, which in fact duplicates the
5747 for (j = 1; j < i.operands; j++)
5749 i.op[j - 1] = i.op[j];
5750 i.types[j - 1] = i.types[j];
5751 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5755 else if (i.tm.opcode_modifier.implicit1stxmm0)
5757 gas_assert ((MAX_OPERANDS - 1) > dupl
5758 && (i.tm.opcode_modifier.vexsources
5761 /* Add the implicit xmm0 for instructions with VEX prefix
5763 for (j = i.operands; j > 0; j--)
5765 i.op[j] = i.op[j - 1];
5766 i.types[j] = i.types[j - 1];
5767 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5770 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5771 i.types[0] = regxmm;
5772 i.tm.operand_types[0] = regxmm;
5775 i.reg_operands += 2;
5780 i.op[dupl] = i.op[dest];
5781 i.types[dupl] = i.types[dest];
5782 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5791 i.op[dupl] = i.op[dest];
5792 i.types[dupl] = i.types[dest];
5793 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5796 if (i.tm.opcode_modifier.immext)
5799 else if (i.tm.opcode_modifier.firstxmm0)
5803 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5804 gas_assert (i.reg_operands
5805 && (operand_type_equal (&i.types[0], ®xmm)
5806 || operand_type_equal (&i.types[0], ®ymm)
5807 || operand_type_equal (&i.types[0], ®zmm)));
5808 if (register_number (i.op[0].regs) != 0)
5809 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5811 for (j = 1; j < i.operands; j++)
5813 i.op[j - 1] = i.op[j];
5814 i.types[j - 1] = i.types[j];
5816 /* We need to adjust fields in i.tm since they are used by
5817 build_modrm_byte. */
5818 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5825 else if (i.tm.opcode_modifier.regkludge)
5827 /* The imul $imm, %reg instruction is converted into
5828 imul $imm, %reg, %reg, and the clr %reg instruction
5829 is converted into xor %reg, %reg. */
5831 unsigned int first_reg_op;
5833 if (operand_type_check (i.types[0], reg))
5837 /* Pretend we saw the extra register operand. */
5838 gas_assert (i.reg_operands == 1
5839 && i.op[first_reg_op + 1].regs == 0);
5840 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5841 i.types[first_reg_op + 1] = i.types[first_reg_op];
5846 if (i.tm.opcode_modifier.shortform)
5848 if (i.types[0].bitfield.sreg2
5849 || i.types[0].bitfield.sreg3)
5851 if (i.tm.base_opcode == POP_SEG_SHORT
5852 && i.op[0].regs->reg_num == 1)
5854 as_bad (_("you can't `pop %scs'"), register_prefix);
5857 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5858 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5863 /* The register or float register operand is in operand
5867 if (i.types[0].bitfield.floatreg
5868 || operand_type_check (i.types[0], reg))
5872 /* Register goes in low 3 bits of opcode. */
5873 i.tm.base_opcode |= i.op[op].regs->reg_num;
5874 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5876 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5878 /* Warn about some common errors, but press on regardless.
5879 The first case can be generated by gcc (<= 2.8.1). */
5880 if (i.operands == 2)
5882 /* Reversed arguments on faddp, fsubp, etc. */
5883 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5884 register_prefix, i.op[!intel_syntax].regs->reg_name,
5885 register_prefix, i.op[intel_syntax].regs->reg_name);
5889 /* Extraneous `l' suffix on fp insn. */
5890 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5891 register_prefix, i.op[0].regs->reg_name);
5896 else if (i.tm.opcode_modifier.modrm)
5898 /* The opcode is completed (modulo i.tm.extension_opcode which
5899 must be put into the modrm byte). Now, we make the modrm and
5900 index base bytes based on all the info we've collected. */
5902 default_seg = build_modrm_byte ();
5904 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5908 else if (i.tm.opcode_modifier.isstring)
5910 /* For the string instructions that allow a segment override
5911 on one of their operands, the default segment is ds. */
5915 if (i.tm.base_opcode == 0x8d /* lea */
5918 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5920 /* If a segment was explicitly specified, and the specified segment
5921 is not the default, use an opcode prefix to select it. If we
5922 never figured out what the default segment is, then default_seg
5923 will be zero at this point, and the specified segment prefix will
5925 if ((i.seg[0]) && (i.seg[0] != default_seg))
5927 if (!add_prefix (i.seg[0]->seg_prefix))
5933 static const seg_entry *
5934 build_modrm_byte (void)
5936 const seg_entry *default_seg = 0;
5937 unsigned int source, dest;
5940 /* The first operand of instructions with VEX prefix and 3 sources
5941 must be VEX_Imm4. */
5942 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5945 unsigned int nds, reg_slot;
5948 if (i.tm.opcode_modifier.veximmext
5949 && i.tm.opcode_modifier.immext)
5951 dest = i.operands - 2;
5952 gas_assert (dest == 3);
5955 dest = i.operands - 1;
5958 /* There are 2 kinds of instructions:
5959 1. 5 operands: 4 register operands or 3 register operands
5960 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5961 VexW0 or VexW1. The destination must be either XMM, YMM or
5963 2. 4 operands: 4 register operands or 3 register operands
5964 plus 1 memory operand, VexXDS, and VexImmExt */
5965 gas_assert ((i.reg_operands == 4
5966 || (i.reg_operands == 3 && i.mem_operands == 1))
5967 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5968 && (i.tm.opcode_modifier.veximmext
5969 || (i.imm_operands == 1
5970 && i.types[0].bitfield.vec_imm4
5971 && (i.tm.opcode_modifier.vexw == VEXW0
5972 || i.tm.opcode_modifier.vexw == VEXW1)
5973 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5974 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)
5975 || operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
5977 if (i.imm_operands == 0)
5979 /* When there is no immediate operand, generate an 8bit
5980 immediate operand to encode the first operand. */
5981 exp = &im_expressions[i.imm_operands++];
5982 i.op[i.operands].imms = exp;
5983 i.types[i.operands] = imm8;
5985 /* If VexW1 is set, the first operand is the source and
5986 the second operand is encoded in the immediate operand. */
5987 if (i.tm.opcode_modifier.vexw == VEXW1)
5998 /* FMA swaps REG and NDS. */
5999 if (i.tm.cpu_flags.bitfield.cpufma)
6007 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6009 || operand_type_equal (&i.tm.operand_types[reg_slot],
6011 || operand_type_equal (&i.tm.operand_types[reg_slot],
6013 exp->X_op = O_constant;
6014 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
6015 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6019 unsigned int imm_slot;
6021 if (i.tm.opcode_modifier.vexw == VEXW0)
6023 /* If VexW0 is set, the third operand is the source and
6024 the second operand is encoded in the immediate
6031 /* VexW1 is set, the second operand is the source and
6032 the third operand is encoded in the immediate
6038 if (i.tm.opcode_modifier.immext)
6040 /* When ImmExt is set, the immdiate byte is the last
6042 imm_slot = i.operands - 1;
6050 /* Turn on Imm8 so that output_imm will generate it. */
6051 i.types[imm_slot].bitfield.imm8 = 1;
6054 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6056 || operand_type_equal (&i.tm.operand_types[reg_slot],
6058 || operand_type_equal (&i.tm.operand_types[reg_slot],
6060 i.op[imm_slot].imms->X_add_number
6061 |= register_number (i.op[reg_slot].regs) << 4;
6062 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6065 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
6066 || operand_type_equal (&i.tm.operand_types[nds],
6068 || operand_type_equal (&i.tm.operand_types[nds],
6070 i.vex.register_specifier = i.op[nds].regs;
6075 /* i.reg_operands MUST be the number of real register operands;
6076 implicit registers do not count. If there are 3 register
6077 operands, it must be a instruction with VexNDS. For a
6078 instruction with VexNDD, the destination register is encoded
6079 in VEX prefix. If there are 4 register operands, it must be
6080 a instruction with VEX prefix and 3 sources. */
6081 if (i.mem_operands == 0
6082 && ((i.reg_operands == 2
6083 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6084 || (i.reg_operands == 3
6085 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6086 || (i.reg_operands == 4 && vex_3_sources)))
6094 /* When there are 3 operands, one of them may be immediate,
6095 which may be the first or the last operand. Otherwise,
6096 the first operand must be shift count register (cl) or it
6097 is an instruction with VexNDS. */
6098 gas_assert (i.imm_operands == 1
6099 || (i.imm_operands == 0
6100 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6101 || i.types[0].bitfield.shiftcount)));
6102 if (operand_type_check (i.types[0], imm)
6103 || i.types[0].bitfield.shiftcount)
6109 /* When there are 4 operands, the first two must be 8bit
6110 immediate operands. The source operand will be the 3rd
6113 For instructions with VexNDS, if the first operand
6114 an imm8, the source operand is the 2nd one. If the last
6115 operand is imm8, the source operand is the first one. */
6116 gas_assert ((i.imm_operands == 2
6117 && i.types[0].bitfield.imm8
6118 && i.types[1].bitfield.imm8)
6119 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6120 && i.imm_operands == 1
6121 && (i.types[0].bitfield.imm8
6122 || i.types[i.operands - 1].bitfield.imm8
6124 if (i.imm_operands == 2)
6128 if (i.types[0].bitfield.imm8)
6135 if (i.tm.opcode_modifier.evex)
6137 /* For EVEX instructions, when there are 5 operands, the
6138 first one must be immediate operand. If the second one
6139 is immediate operand, the source operand is the 3th
6140 one. If the last one is immediate operand, the source
6141 operand is the 2nd one. */
6142 gas_assert (i.imm_operands == 2
6143 && i.tm.opcode_modifier.sae
6144 && operand_type_check (i.types[0], imm));
6145 if (operand_type_check (i.types[1], imm))
6147 else if (operand_type_check (i.types[4], imm))
6161 /* RC/SAE operand could be between DEST and SRC. That happens
6162 when one operand is GPR and the other one is XMM/YMM/ZMM
6164 if (i.rounding && i.rounding->operand == (int) dest)
6167 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6169 /* For instructions with VexNDS, the register-only source
6170 operand must be 32/64bit integer, XMM, YMM or ZMM
6171 register. It is encoded in VEX prefix. We need to
6172 clear RegMem bit before calling operand_type_equal. */
6174 i386_operand_type op;
6177 /* Check register-only source operand when two source
6178 operands are swapped. */
6179 if (!i.tm.operand_types[source].bitfield.baseindex
6180 && i.tm.operand_types[dest].bitfield.baseindex)
6188 op = i.tm.operand_types[vvvv];
6189 op.bitfield.regmem = 0;
6190 if ((dest + 1) >= i.operands
6191 || (!op.bitfield.reg32
6192 && op.bitfield.reg64
6193 && !operand_type_equal (&op, ®xmm)
6194 && !operand_type_equal (&op, ®ymm)
6195 && !operand_type_equal (&op, ®zmm)
6196 && !operand_type_equal (&op, ®mask)))
6198 i.vex.register_specifier = i.op[vvvv].regs;
6204 /* One of the register operands will be encoded in the i.tm.reg
6205 field, the other in the combined i.tm.mode and i.tm.regmem
6206 fields. If no form of this instruction supports a memory
6207 destination operand, then we assume the source operand may
6208 sometimes be a memory operand and so we need to store the
6209 destination in the i.rm.reg field. */
6210 if (!i.tm.operand_types[dest].bitfield.regmem
6211 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6213 i.rm.reg = i.op[dest].regs->reg_num;
6214 i.rm.regmem = i.op[source].regs->reg_num;
6215 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6217 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6219 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6221 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6226 i.rm.reg = i.op[source].regs->reg_num;
6227 i.rm.regmem = i.op[dest].regs->reg_num;
6228 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6230 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6232 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6234 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6237 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6239 if (!i.types[0].bitfield.control
6240 && !i.types[1].bitfield.control)
6242 i.rex &= ~(REX_R | REX_B);
6243 add_prefix (LOCK_PREFIX_OPCODE);
6247 { /* If it's not 2 reg operands... */
6252 unsigned int fake_zero_displacement = 0;
6255 for (op = 0; op < i.operands; op++)
6256 if (operand_type_check (i.types[op], anymem))
6258 gas_assert (op < i.operands);
6260 if (i.tm.opcode_modifier.vecsib)
6262 if (i.index_reg->reg_num == RegEiz
6263 || i.index_reg->reg_num == RegRiz)
6266 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6269 i.sib.base = NO_BASE_REGISTER;
6270 i.sib.scale = i.log2_scale_factor;
6271 /* No Vec_Disp8 if there is no base. */
6272 i.types[op].bitfield.vec_disp8 = 0;
6273 i.types[op].bitfield.disp8 = 0;
6274 i.types[op].bitfield.disp16 = 0;
6275 i.types[op].bitfield.disp64 = 0;
6276 if (flag_code != CODE_64BIT)
6278 /* Must be 32 bit */
6279 i.types[op].bitfield.disp32 = 1;
6280 i.types[op].bitfield.disp32s = 0;
6284 i.types[op].bitfield.disp32 = 0;
6285 i.types[op].bitfield.disp32s = 1;
6288 i.sib.index = i.index_reg->reg_num;
6289 if ((i.index_reg->reg_flags & RegRex) != 0)
6291 if ((i.index_reg->reg_flags & RegVRex) != 0)
6297 if (i.base_reg == 0)
6300 if (!i.disp_operands)
6302 fake_zero_displacement = 1;
6303 /* Instructions with VSIB byte need 32bit displacement
6304 if there is no base register. */
6305 if (i.tm.opcode_modifier.vecsib)
6306 i.types[op].bitfield.disp32 = 1;
6308 if (i.index_reg == 0)
6310 gas_assert (!i.tm.opcode_modifier.vecsib);
6311 /* Operand is just <disp> */
6312 if (flag_code == CODE_64BIT)
6314 /* 64bit mode overwrites the 32bit absolute
6315 addressing by RIP relative addressing and
6316 absolute addressing is encoded by one of the
6317 redundant SIB forms. */
6318 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6319 i.sib.base = NO_BASE_REGISTER;
6320 i.sib.index = NO_INDEX_REGISTER;
6321 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6322 ? disp32s : disp32);
6324 else if ((flag_code == CODE_16BIT)
6325 ^ (i.prefix[ADDR_PREFIX] != 0))
6327 i.rm.regmem = NO_BASE_REGISTER_16;
6328 i.types[op] = disp16;
6332 i.rm.regmem = NO_BASE_REGISTER;
6333 i.types[op] = disp32;
6336 else if (!i.tm.opcode_modifier.vecsib)
6338 /* !i.base_reg && i.index_reg */
6339 if (i.index_reg->reg_num == RegEiz
6340 || i.index_reg->reg_num == RegRiz)
6341 i.sib.index = NO_INDEX_REGISTER;
6343 i.sib.index = i.index_reg->reg_num;
6344 i.sib.base = NO_BASE_REGISTER;
6345 i.sib.scale = i.log2_scale_factor;
6346 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6347 /* No Vec_Disp8 if there is no base. */
6348 i.types[op].bitfield.vec_disp8 = 0;
6349 i.types[op].bitfield.disp8 = 0;
6350 i.types[op].bitfield.disp16 = 0;
6351 i.types[op].bitfield.disp64 = 0;
6352 if (flag_code != CODE_64BIT)
6354 /* Must be 32 bit */
6355 i.types[op].bitfield.disp32 = 1;
6356 i.types[op].bitfield.disp32s = 0;
6360 i.types[op].bitfield.disp32 = 0;
6361 i.types[op].bitfield.disp32s = 1;
6363 if ((i.index_reg->reg_flags & RegRex) != 0)
6367 /* RIP addressing for 64bit mode. */
6368 else if (i.base_reg->reg_num == RegRip ||
6369 i.base_reg->reg_num == RegEip)
6371 gas_assert (!i.tm.opcode_modifier.vecsib);
6372 i.rm.regmem = NO_BASE_REGISTER;
6373 i.types[op].bitfield.disp8 = 0;
6374 i.types[op].bitfield.disp16 = 0;
6375 i.types[op].bitfield.disp32 = 0;
6376 i.types[op].bitfield.disp32s = 1;
6377 i.types[op].bitfield.disp64 = 0;
6378 i.types[op].bitfield.vec_disp8 = 0;
6379 i.flags[op] |= Operand_PCrel;
6380 if (! i.disp_operands)
6381 fake_zero_displacement = 1;
6383 else if (i.base_reg->reg_type.bitfield.reg16)
6385 gas_assert (!i.tm.opcode_modifier.vecsib);
6386 switch (i.base_reg->reg_num)
6389 if (i.index_reg == 0)
6391 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6392 i.rm.regmem = i.index_reg->reg_num - 6;
6396 if (i.index_reg == 0)
6399 if (operand_type_check (i.types[op], disp) == 0)
6401 /* fake (%bp) into 0(%bp) */
6402 if (i.tm.operand_types[op].bitfield.vec_disp8)
6403 i.types[op].bitfield.vec_disp8 = 1;
6405 i.types[op].bitfield.disp8 = 1;
6406 fake_zero_displacement = 1;
6409 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6410 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6412 default: /* (%si) -> 4 or (%di) -> 5 */
6413 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6415 i.rm.mode = mode_from_disp_size (i.types[op]);
6417 else /* i.base_reg and 32/64 bit mode */
6419 if (flag_code == CODE_64BIT
6420 && operand_type_check (i.types[op], disp))
6422 i386_operand_type temp;
6423 operand_type_set (&temp, 0);
6424 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6425 temp.bitfield.vec_disp8
6426 = i.types[op].bitfield.vec_disp8;
6428 if (i.prefix[ADDR_PREFIX] == 0)
6429 i.types[op].bitfield.disp32s = 1;
6431 i.types[op].bitfield.disp32 = 1;
6434 if (!i.tm.opcode_modifier.vecsib)
6435 i.rm.regmem = i.base_reg->reg_num;
6436 if ((i.base_reg->reg_flags & RegRex) != 0)
6438 i.sib.base = i.base_reg->reg_num;
6439 /* x86-64 ignores REX prefix bit here to avoid decoder
6441 if (!(i.base_reg->reg_flags & RegRex)
6442 && (i.base_reg->reg_num == EBP_REG_NUM
6443 || i.base_reg->reg_num == ESP_REG_NUM))
6445 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6447 fake_zero_displacement = 1;
6448 if (i.tm.operand_types [op].bitfield.vec_disp8)
6449 i.types[op].bitfield.vec_disp8 = 1;
6451 i.types[op].bitfield.disp8 = 1;
6453 i.sib.scale = i.log2_scale_factor;
6454 if (i.index_reg == 0)
6456 gas_assert (!i.tm.opcode_modifier.vecsib);
6457 /* <disp>(%esp) becomes two byte modrm with no index
6458 register. We've already stored the code for esp
6459 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6460 Any base register besides %esp will not use the
6461 extra modrm byte. */
6462 i.sib.index = NO_INDEX_REGISTER;
6464 else if (!i.tm.opcode_modifier.vecsib)
6466 if (i.index_reg->reg_num == RegEiz
6467 || i.index_reg->reg_num == RegRiz)
6468 i.sib.index = NO_INDEX_REGISTER;
6470 i.sib.index = i.index_reg->reg_num;
6471 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6472 if ((i.index_reg->reg_flags & RegRex) != 0)
6477 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6478 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6482 if (!fake_zero_displacement
6486 fake_zero_displacement = 1;
6487 if (i.disp_encoding == disp_encoding_8bit)
6488 i.types[op].bitfield.disp8 = 1;
6490 i.types[op].bitfield.disp32 = 1;
6492 i.rm.mode = mode_from_disp_size (i.types[op]);
6496 if (fake_zero_displacement)
6498 /* Fakes a zero displacement assuming that i.types[op]
6499 holds the correct displacement size. */
6502 gas_assert (i.op[op].disps == 0);
6503 exp = &disp_expressions[i.disp_operands++];
6504 i.op[op].disps = exp;
6505 exp->X_op = O_constant;
6506 exp->X_add_number = 0;
6507 exp->X_add_symbol = (symbolS *) 0;
6508 exp->X_op_symbol = (symbolS *) 0;
6516 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6518 if (operand_type_check (i.types[0], imm))
6519 i.vex.register_specifier = NULL;
6522 /* VEX.vvvv encodes one of the sources when the first
6523 operand is not an immediate. */
6524 if (i.tm.opcode_modifier.vexw == VEXW0)
6525 i.vex.register_specifier = i.op[0].regs;
6527 i.vex.register_specifier = i.op[1].regs;
6530 /* Destination is a XMM register encoded in the ModRM.reg
6532 i.rm.reg = i.op[2].regs->reg_num;
6533 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6536 /* ModRM.rm and VEX.B encodes the other source. */
6537 if (!i.mem_operands)
6541 if (i.tm.opcode_modifier.vexw == VEXW0)
6542 i.rm.regmem = i.op[1].regs->reg_num;
6544 i.rm.regmem = i.op[0].regs->reg_num;
6546 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6550 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6552 i.vex.register_specifier = i.op[2].regs;
6553 if (!i.mem_operands)
6556 i.rm.regmem = i.op[1].regs->reg_num;
6557 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6561 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6562 (if any) based on i.tm.extension_opcode. Again, we must be
6563 careful to make sure that segment/control/debug/test/MMX
6564 registers are coded into the i.rm.reg field. */
6565 else if (i.reg_operands)
6568 unsigned int vex_reg = ~0;
6570 for (op = 0; op < i.operands; op++)
6571 if (i.types[op].bitfield.reg8
6572 || i.types[op].bitfield.reg16
6573 || i.types[op].bitfield.reg32
6574 || i.types[op].bitfield.reg64
6575 || i.types[op].bitfield.regmmx
6576 || i.types[op].bitfield.regxmm
6577 || i.types[op].bitfield.regymm
6578 || i.types[op].bitfield.regbnd
6579 || i.types[op].bitfield.regzmm
6580 || i.types[op].bitfield.regmask
6581 || i.types[op].bitfield.sreg2
6582 || i.types[op].bitfield.sreg3
6583 || i.types[op].bitfield.control
6584 || i.types[op].bitfield.debug
6585 || i.types[op].bitfield.test)
6590 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6592 /* For instructions with VexNDS, the register-only
6593 source operand is encoded in VEX prefix. */
6594 gas_assert (mem != (unsigned int) ~0);
6599 gas_assert (op < i.operands);
6603 /* Check register-only source operand when two source
6604 operands are swapped. */
6605 if (!i.tm.operand_types[op].bitfield.baseindex
6606 && i.tm.operand_types[op + 1].bitfield.baseindex)
6610 gas_assert (mem == (vex_reg + 1)
6611 && op < i.operands);
6616 gas_assert (vex_reg < i.operands);
6620 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6622 /* For instructions with VexNDD, the register destination
6623 is encoded in VEX prefix. */
6624 if (i.mem_operands == 0)
6626 /* There is no memory operand. */
6627 gas_assert ((op + 2) == i.operands);
6632 /* There are only 2 operands. */
6633 gas_assert (op < 2 && i.operands == 2);
6638 gas_assert (op < i.operands);
6640 if (vex_reg != (unsigned int) ~0)
6642 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6644 if (type->bitfield.reg32 != 1
6645 && type->bitfield.reg64 != 1
6646 && !operand_type_equal (type, ®xmm)
6647 && !operand_type_equal (type, ®ymm)
6648 && !operand_type_equal (type, ®zmm)
6649 && !operand_type_equal (type, ®mask))
6652 i.vex.register_specifier = i.op[vex_reg].regs;
6655 /* Don't set OP operand twice. */
6658 /* If there is an extension opcode to put here, the
6659 register number must be put into the regmem field. */
6660 if (i.tm.extension_opcode != None)
6662 i.rm.regmem = i.op[op].regs->reg_num;
6663 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6665 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6670 i.rm.reg = i.op[op].regs->reg_num;
6671 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6673 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6678 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6679 must set it to 3 to indicate this is a register operand
6680 in the regmem field. */
6681 if (!i.mem_operands)
6685 /* Fill in i.rm.reg field with extension opcode (if any). */
6686 if (i.tm.extension_opcode != None)
6687 i.rm.reg = i.tm.extension_opcode;
6693 output_branch (void)
6699 relax_substateT subtype;
6703 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6704 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6707 if (i.prefix[DATA_PREFIX] != 0)
6713 /* Pentium4 branch hints. */
6714 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6715 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6720 if (i.prefix[REX_PREFIX] != 0)
6726 /* BND prefixed jump. */
6727 if (i.prefix[BND_PREFIX] != 0)
6729 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6733 if (i.prefixes != 0 && !intel_syntax)
6734 as_warn (_("skipping prefixes on this instruction"));
6736 /* It's always a symbol; End frag & setup for relax.
6737 Make sure there is enough room in this frag for the largest
6738 instruction we may generate in md_convert_frag. This is 2
6739 bytes for the opcode and room for the prefix and largest
6741 frag_grow (prefix + 2 + 4);
6742 /* Prefix and 1 opcode byte go in fr_fix. */
6743 p = frag_more (prefix + 1);
6744 if (i.prefix[DATA_PREFIX] != 0)
6745 *p++ = DATA_PREFIX_OPCODE;
6746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6748 *p++ = i.prefix[SEG_PREFIX];
6749 if (i.prefix[REX_PREFIX] != 0)
6750 *p++ = i.prefix[REX_PREFIX];
6751 *p = i.tm.base_opcode;
6753 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6754 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6755 else if (cpu_arch_flags.bitfield.cpui386)
6756 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6758 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6761 sym = i.op[0].disps->X_add_symbol;
6762 off = i.op[0].disps->X_add_number;
6764 if (i.op[0].disps->X_op != O_constant
6765 && i.op[0].disps->X_op != O_symbol)
6767 /* Handle complex expressions. */
6768 sym = make_expr_symbol (i.op[0].disps);
6772 /* 1 possible extra opcode + 4 byte displacement go in var part.
6773 Pass reloc in fr_var. */
6774 frag_var (rs_machine_dependent, 5,
6776 || i.reloc[0] != NO_RELOC
6777 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6779 : BFD_RELOC_X86_64_PC32_BND),
6780 subtype, sym, off, p);
6790 if (i.tm.opcode_modifier.jumpbyte)
6792 /* This is a loop or jecxz type instruction. */
6794 if (i.prefix[ADDR_PREFIX] != 0)
6796 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6799 /* Pentium4 branch hints. */
6800 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6801 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6803 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6812 if (flag_code == CODE_16BIT)
6815 if (i.prefix[DATA_PREFIX] != 0)
6817 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6827 if (i.prefix[REX_PREFIX] != 0)
6829 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6833 /* BND prefixed jump. */
6834 if (i.prefix[BND_PREFIX] != 0)
6836 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6840 if (i.prefixes != 0 && !intel_syntax)
6841 as_warn (_("skipping prefixes on this instruction"));
6843 p = frag_more (i.tm.opcode_length + size);
6844 switch (i.tm.opcode_length)
6847 *p++ = i.tm.base_opcode >> 8;
6849 *p++ = i.tm.base_opcode;
6855 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6856 i.op[0].disps, 1, reloc (size, 1, 1,
6857 (i.bnd_prefix != NULL
6861 /* All jumps handled here are signed, but don't use a signed limit
6862 check for 32 and 16 bit jumps as we want to allow wrap around at
6863 4G and 64k respectively. */
6865 fixP->fx_signed = 1;
6869 output_interseg_jump (void)
6877 if (flag_code == CODE_16BIT)
6881 if (i.prefix[DATA_PREFIX] != 0)
6887 if (i.prefix[REX_PREFIX] != 0)
6897 if (i.prefixes != 0 && !intel_syntax)
6898 as_warn (_("skipping prefixes on this instruction"));
6900 /* 1 opcode; 2 segment; offset */
6901 p = frag_more (prefix + 1 + 2 + size);
6903 if (i.prefix[DATA_PREFIX] != 0)
6904 *p++ = DATA_PREFIX_OPCODE;
6906 if (i.prefix[REX_PREFIX] != 0)
6907 *p++ = i.prefix[REX_PREFIX];
6909 *p++ = i.tm.base_opcode;
6910 if (i.op[1].imms->X_op == O_constant)
6912 offsetT n = i.op[1].imms->X_add_number;
6915 && !fits_in_unsigned_word (n)
6916 && !fits_in_signed_word (n))
6918 as_bad (_("16-bit jump out of range"));
6921 md_number_to_chars (p, n, size);
6924 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6925 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
6926 if (i.op[0].imms->X_op != O_constant)
6927 as_bad (_("can't handle non absolute segment in `%s'"),
6929 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6935 fragS *insn_start_frag;
6936 offsetT insn_start_off;
6938 /* Tie dwarf2 debug info to the address at the start of the insn.
6939 We can't do this after the insn has been output as the current
6940 frag may have been closed off. eg. by frag_var. */
6941 dwarf2_emit_insn (0);
6943 insn_start_frag = frag_now;
6944 insn_start_off = frag_now_fix ();
6947 if (i.tm.opcode_modifier.jump)
6949 else if (i.tm.opcode_modifier.jumpbyte
6950 || i.tm.opcode_modifier.jumpdword)
6952 else if (i.tm.opcode_modifier.jumpintersegment)
6953 output_interseg_jump ();
6956 /* Output normal instructions here. */
6960 unsigned int prefix;
6962 /* Some processors fail on LOCK prefix. This options makes
6963 assembler ignore LOCK prefix and serves as a workaround. */
6964 if (omit_lock_prefix)
6966 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6968 i.prefix[LOCK_PREFIX] = 0;
6971 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6972 don't need the explicit prefix. */
6973 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6975 switch (i.tm.opcode_length)
6978 if (i.tm.base_opcode & 0xff000000)
6980 prefix = (i.tm.base_opcode >> 24) & 0xff;
6985 if ((i.tm.base_opcode & 0xff0000) != 0)
6987 prefix = (i.tm.base_opcode >> 16) & 0xff;
6988 if (i.tm.cpu_flags.bitfield.cpupadlock)
6991 if (prefix != REPE_PREFIX_OPCODE
6992 || (i.prefix[REP_PREFIX]
6993 != REPE_PREFIX_OPCODE))
6994 add_prefix (prefix);
6997 add_prefix (prefix);
7006 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7007 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7008 R_X86_64_GOTTPOFF relocation so that linker can safely
7009 perform IE->LE optimization. */
7010 if (x86_elf_abi == X86_64_X32_ABI
7012 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7013 && i.prefix[REX_PREFIX] == 0)
7014 add_prefix (REX_OPCODE);
7017 /* The prefix bytes. */
7018 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7020 FRAG_APPEND_1_CHAR (*q);
7024 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7029 /* REX byte is encoded in VEX prefix. */
7033 FRAG_APPEND_1_CHAR (*q);
7036 /* There should be no other prefixes for instructions
7041 /* For EVEX instructions i.vrex should become 0 after
7042 build_evex_prefix. For VEX instructions upper 16 registers
7043 aren't available, so VREX should be 0. */
7046 /* Now the VEX prefix. */
7047 p = frag_more (i.vex.length);
7048 for (j = 0; j < i.vex.length; j++)
7049 p[j] = i.vex.bytes[j];
7052 /* Now the opcode; be careful about word order here! */
7053 if (i.tm.opcode_length == 1)
7055 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7059 switch (i.tm.opcode_length)
7063 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7064 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7068 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7078 /* Put out high byte first: can't use md_number_to_chars! */
7079 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7080 *p = i.tm.base_opcode & 0xff;
7083 /* Now the modrm byte and sib byte (if present). */
7084 if (i.tm.opcode_modifier.modrm)
7086 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7089 /* If i.rm.regmem == ESP (4)
7090 && i.rm.mode != (Register mode)
7092 ==> need second modrm byte. */
7093 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7095 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7096 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7098 | i.sib.scale << 6));
7101 if (i.disp_operands)
7102 output_disp (insn_start_frag, insn_start_off);
7105 output_imm (insn_start_frag, insn_start_off);
7111 pi ("" /*line*/, &i);
7113 #endif /* DEBUG386 */
7116 /* Return the size of the displacement operand N. */
7119 disp_size (unsigned int n)
7123 /* Vec_Disp8 has to be 8bit. */
7124 if (i.types[n].bitfield.vec_disp8)
7126 else if (i.types[n].bitfield.disp64)
7128 else if (i.types[n].bitfield.disp8)
7130 else if (i.types[n].bitfield.disp16)
7135 /* Return the size of the immediate operand N. */
7138 imm_size (unsigned int n)
7141 if (i.types[n].bitfield.imm64)
7143 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7145 else if (i.types[n].bitfield.imm16)
7151 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7156 for (n = 0; n < i.operands; n++)
7158 if (i.types[n].bitfield.vec_disp8
7159 || operand_type_check (i.types[n], disp))
7161 if (i.op[n].disps->X_op == O_constant)
7163 int size = disp_size (n);
7164 offsetT val = i.op[n].disps->X_add_number;
7166 if (i.types[n].bitfield.vec_disp8)
7168 val = offset_in_range (val, size);
7169 p = frag_more (size);
7170 md_number_to_chars (p, val, size);
7174 enum bfd_reloc_code_real reloc_type;
7175 int size = disp_size (n);
7176 int sign = i.types[n].bitfield.disp32s;
7177 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7179 /* We can't have 8 bit displacement here. */
7180 gas_assert (!i.types[n].bitfield.disp8);
7182 /* The PC relative address is computed relative
7183 to the instruction boundary, so in case immediate
7184 fields follows, we need to adjust the value. */
7185 if (pcrel && i.imm_operands)
7190 for (n1 = 0; n1 < i.operands; n1++)
7191 if (operand_type_check (i.types[n1], imm))
7193 /* Only one immediate is allowed for PC
7194 relative address. */
7195 gas_assert (sz == 0);
7197 i.op[n].disps->X_add_number -= sz;
7199 /* We should find the immediate. */
7200 gas_assert (sz != 0);
7203 p = frag_more (size);
7204 reloc_type = reloc (size, pcrel, sign,
7205 (i.bnd_prefix != NULL
7209 && GOT_symbol == i.op[n].disps->X_add_symbol
7210 && (((reloc_type == BFD_RELOC_32
7211 || reloc_type == BFD_RELOC_X86_64_32S
7212 || (reloc_type == BFD_RELOC_64
7214 && (i.op[n].disps->X_op == O_symbol
7215 || (i.op[n].disps->X_op == O_add
7216 && ((symbol_get_value_expression
7217 (i.op[n].disps->X_op_symbol)->X_op)
7219 || reloc_type == BFD_RELOC_32_PCREL))
7223 if (insn_start_frag == frag_now)
7224 add = (p - frag_now->fr_literal) - insn_start_off;
7229 add = insn_start_frag->fr_fix - insn_start_off;
7230 for (fr = insn_start_frag->fr_next;
7231 fr && fr != frag_now; fr = fr->fr_next)
7233 add += p - frag_now->fr_literal;
7238 reloc_type = BFD_RELOC_386_GOTPC;
7239 i.op[n].imms->X_add_number += add;
7241 else if (reloc_type == BFD_RELOC_64)
7242 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7244 /* Don't do the adjustment for x86-64, as there
7245 the pcrel addressing is relative to the _next_
7246 insn, and that is taken care of in other code. */
7247 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7249 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7250 i.op[n].disps, pcrel, reloc_type);
7257 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7262 for (n = 0; n < i.operands; n++)
7264 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7265 if (i.rounding && (int) n == i.rounding->operand)
7268 if (operand_type_check (i.types[n], imm))
7270 if (i.op[n].imms->X_op == O_constant)
7272 int size = imm_size (n);
7275 val = offset_in_range (i.op[n].imms->X_add_number,
7277 p = frag_more (size);
7278 md_number_to_chars (p, val, size);
7282 /* Not absolute_section.
7283 Need a 32-bit fixup (don't support 8bit
7284 non-absolute imms). Try to support other
7286 enum bfd_reloc_code_real reloc_type;
7287 int size = imm_size (n);
7290 if (i.types[n].bitfield.imm32s
7291 && (i.suffix == QWORD_MNEM_SUFFIX
7292 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7297 p = frag_more (size);
7298 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
7300 /* This is tough to explain. We end up with this one if we
7301 * have operands that look like
7302 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7303 * obtain the absolute address of the GOT, and it is strongly
7304 * preferable from a performance point of view to avoid using
7305 * a runtime relocation for this. The actual sequence of
7306 * instructions often look something like:
7311 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7313 * The call and pop essentially return the absolute address
7314 * of the label .L66 and store it in %ebx. The linker itself
7315 * will ultimately change the first operand of the addl so
7316 * that %ebx points to the GOT, but to keep things simple, the
7317 * .o file must have this operand set so that it generates not
7318 * the absolute address of .L66, but the absolute address of
7319 * itself. This allows the linker itself simply treat a GOTPC
7320 * relocation as asking for a pcrel offset to the GOT to be
7321 * added in, and the addend of the relocation is stored in the
7322 * operand field for the instruction itself.
7324 * Our job here is to fix the operand so that it would add
7325 * the correct offset so that %ebx would point to itself. The
7326 * thing that is tricky is that .-.L66 will point to the
7327 * beginning of the instruction, so we need to further modify
7328 * the operand so that it will point to itself. There are
7329 * other cases where you have something like:
7331 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7333 * and here no correction would be required. Internally in
7334 * the assembler we treat operands of this form as not being
7335 * pcrel since the '.' is explicitly mentioned, and I wonder
7336 * whether it would simplify matters to do it this way. Who
7337 * knows. In earlier versions of the PIC patches, the
7338 * pcrel_adjust field was used to store the correction, but
7339 * since the expression is not pcrel, I felt it would be
7340 * confusing to do it this way. */
7342 if ((reloc_type == BFD_RELOC_32
7343 || reloc_type == BFD_RELOC_X86_64_32S
7344 || reloc_type == BFD_RELOC_64)
7346 && GOT_symbol == i.op[n].imms->X_add_symbol
7347 && (i.op[n].imms->X_op == O_symbol
7348 || (i.op[n].imms->X_op == O_add
7349 && ((symbol_get_value_expression
7350 (i.op[n].imms->X_op_symbol)->X_op)
7355 if (insn_start_frag == frag_now)
7356 add = (p - frag_now->fr_literal) - insn_start_off;
7361 add = insn_start_frag->fr_fix - insn_start_off;
7362 for (fr = insn_start_frag->fr_next;
7363 fr && fr != frag_now; fr = fr->fr_next)
7365 add += p - frag_now->fr_literal;
7369 reloc_type = BFD_RELOC_386_GOTPC;
7371 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7373 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7374 i.op[n].imms->X_add_number += add;
7376 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7377 i.op[n].imms, 0, reloc_type);
7383 /* x86_cons_fix_new is called via the expression parsing code when a
7384 reloc is needed. We use this hook to get the correct .got reloc. */
7385 static int cons_sign = -1;
7388 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7389 expressionS *exp, bfd_reloc_code_real_type r)
7391 r = reloc (len, 0, cons_sign, 0, r);
7394 if (exp->X_op == O_secrel)
7396 exp->X_op = O_symbol;
7397 r = BFD_RELOC_32_SECREL;
7401 fix_new_exp (frag, off, len, exp, 0, r);
7404 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7405 purpose of the `.dc.a' internal pseudo-op. */
7408 x86_address_bytes (void)
7410 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7412 return stdoutput->arch_info->bits_per_address / 8;
7415 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7417 # define lex_got(reloc, adjust, types, bnd_prefix) NULL
7419 /* Parse operands of the form
7420 <symbol>@GOTOFF+<nnn>
7421 and similar .plt or .got references.
7423 If we find one, set up the correct relocation in RELOC and copy the
7424 input string, minus the `@GOTOFF' into a malloc'd buffer for
7425 parsing by the calling routine. Return this buffer, and if ADJUST
7426 is non-null set it to the length of the string we removed from the
7427 input line. Otherwise return NULL. */
7429 lex_got (enum bfd_reloc_code_real *rel,
7431 i386_operand_type *types,
7434 /* Some of the relocations depend on the size of what field is to
7435 be relocated. But in our callers i386_immediate and i386_displacement
7436 we don't yet know the operand size (this will be set by insn
7437 matching). Hence we record the word32 relocation here,
7438 and adjust the reloc according to the real size in reloc(). */
7439 static const struct {
7442 const enum bfd_reloc_code_real rel[2];
7443 const i386_operand_type types64;
7445 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7446 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7448 OPERAND_TYPE_IMM32_64 },
7450 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7451 BFD_RELOC_X86_64_PLTOFF64 },
7452 OPERAND_TYPE_IMM64 },
7453 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7454 BFD_RELOC_X86_64_PLT32 },
7455 OPERAND_TYPE_IMM32_32S_DISP32 },
7456 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7457 BFD_RELOC_X86_64_GOTPLT64 },
7458 OPERAND_TYPE_IMM64_DISP64 },
7459 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7460 BFD_RELOC_X86_64_GOTOFF64 },
7461 OPERAND_TYPE_IMM64_DISP64 },
7462 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7463 BFD_RELOC_X86_64_GOTPCREL },
7464 OPERAND_TYPE_IMM32_32S_DISP32 },
7465 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7466 BFD_RELOC_X86_64_TLSGD },
7467 OPERAND_TYPE_IMM32_32S_DISP32 },
7468 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7469 _dummy_first_bfd_reloc_code_real },
7470 OPERAND_TYPE_NONE },
7471 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7472 BFD_RELOC_X86_64_TLSLD },
7473 OPERAND_TYPE_IMM32_32S_DISP32 },
7474 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7475 BFD_RELOC_X86_64_GOTTPOFF },
7476 OPERAND_TYPE_IMM32_32S_DISP32 },
7477 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7478 BFD_RELOC_X86_64_TPOFF32 },
7479 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7480 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7481 _dummy_first_bfd_reloc_code_real },
7482 OPERAND_TYPE_NONE },
7483 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7484 BFD_RELOC_X86_64_DTPOFF32 },
7485 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7486 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7487 _dummy_first_bfd_reloc_code_real },
7488 OPERAND_TYPE_NONE },
7489 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7490 _dummy_first_bfd_reloc_code_real },
7491 OPERAND_TYPE_NONE },
7492 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7493 BFD_RELOC_X86_64_GOT32 },
7494 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7495 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7496 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7497 OPERAND_TYPE_IMM32_32S_DISP32 },
7498 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7499 BFD_RELOC_X86_64_TLSDESC_CALL },
7500 OPERAND_TYPE_IMM32_32S_DISP32 },
7505 #if defined (OBJ_MAYBE_ELF)
7510 for (cp = input_line_pointer; *cp != '@'; cp++)
7511 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7514 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7516 int len = gotrel[j].len;
7517 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7519 if (gotrel[j].rel[object_64bit] != 0)
7522 char *tmpbuf, *past_reloc;
7524 *rel = gotrel[j].rel[object_64bit];
7528 if (flag_code != CODE_64BIT)
7530 types->bitfield.imm32 = 1;
7531 types->bitfield.disp32 = 1;
7534 *types = gotrel[j].types64;
7537 if (j != 0 && GOT_symbol == NULL)
7538 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7540 /* The length of the first part of our input line. */
7541 first = cp - input_line_pointer;
7543 /* The second part goes from after the reloc token until
7544 (and including) an end_of_line char or comma. */
7545 past_reloc = cp + 1 + len;
7547 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7549 second = cp + 1 - past_reloc;
7551 /* Allocate and copy string. The trailing NUL shouldn't
7552 be necessary, but be safe. */
7553 tmpbuf = (char *) xmalloc (first + second + 2);
7554 memcpy (tmpbuf, input_line_pointer, first);
7555 if (second != 0 && *past_reloc != ' ')
7556 /* Replace the relocation token with ' ', so that
7557 errors like foo@GOTOFF1 will be detected. */
7558 tmpbuf[first++] = ' ';
7560 /* Increment length by 1 if the relocation token is
7565 memcpy (tmpbuf + first, past_reloc, second);
7566 tmpbuf[first + second] = '\0';
7567 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7568 *rel = BFD_RELOC_X86_64_PLT32_BND;
7572 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7573 gotrel[j].str, 1 << (5 + object_64bit));
7578 /* Might be a symbol version string. Don't as_bad here. */
7587 /* Parse operands of the form
7588 <symbol>@SECREL32+<nnn>
7590 If we find one, set up the correct relocation in RELOC and copy the
7591 input string, minus the `@SECREL32' into a malloc'd buffer for
7592 parsing by the calling routine. Return this buffer, and if ADJUST
7593 is non-null set it to the length of the string we removed from the
7594 input line. Otherwise return NULL.
7596 This function is copied from the ELF version above adjusted for PE targets. */
7599 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7600 int *adjust ATTRIBUTE_UNUSED,
7601 i386_operand_type *types,
7602 int bnd_prefix ATTRIBUTE_UNUSED)
7608 const enum bfd_reloc_code_real rel[2];
7609 const i386_operand_type types64;
7613 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7614 BFD_RELOC_32_SECREL },
7615 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7621 for (cp = input_line_pointer; *cp != '@'; cp++)
7622 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7625 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7627 int len = gotrel[j].len;
7629 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7631 if (gotrel[j].rel[object_64bit] != 0)
7634 char *tmpbuf, *past_reloc;
7636 *rel = gotrel[j].rel[object_64bit];
7642 if (flag_code != CODE_64BIT)
7644 types->bitfield.imm32 = 1;
7645 types->bitfield.disp32 = 1;
7648 *types = gotrel[j].types64;
7651 /* The length of the first part of our input line. */
7652 first = cp - input_line_pointer;
7654 /* The second part goes from after the reloc token until
7655 (and including) an end_of_line char or comma. */
7656 past_reloc = cp + 1 + len;
7658 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7660 second = cp + 1 - past_reloc;
7662 /* Allocate and copy string. The trailing NUL shouldn't
7663 be necessary, but be safe. */
7664 tmpbuf = (char *) xmalloc (first + second + 2);
7665 memcpy (tmpbuf, input_line_pointer, first);
7666 if (second != 0 && *past_reloc != ' ')
7667 /* Replace the relocation token with ' ', so that
7668 errors like foo@SECLREL321 will be detected. */
7669 tmpbuf[first++] = ' ';
7670 memcpy (tmpbuf + first, past_reloc, second);
7671 tmpbuf[first + second] = '\0';
7675 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7676 gotrel[j].str, 1 << (5 + object_64bit));
7681 /* Might be a symbol version string. Don't as_bad here. */
7687 bfd_reloc_code_real_type
7688 x86_cons (expressionS *exp, int size)
7690 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7692 intel_syntax = -intel_syntax;
7695 if (size == 4 || (object_64bit && size == 8))
7697 /* Handle @GOTOFF and the like in an expression. */
7699 char *gotfree_input_line;
7702 save = input_line_pointer;
7703 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
7704 if (gotfree_input_line)
7705 input_line_pointer = gotfree_input_line;
7709 if (gotfree_input_line)
7711 /* expression () has merrily parsed up to the end of line,
7712 or a comma - in the wrong buffer. Transfer how far
7713 input_line_pointer has moved to the right buffer. */
7714 input_line_pointer = (save
7715 + (input_line_pointer - gotfree_input_line)
7717 free (gotfree_input_line);
7718 if (exp->X_op == O_constant
7719 || exp->X_op == O_absent
7720 || exp->X_op == O_illegal
7721 || exp->X_op == O_register
7722 || exp->X_op == O_big)
7724 char c = *input_line_pointer;
7725 *input_line_pointer = 0;
7726 as_bad (_("missing or invalid expression `%s'"), save);
7727 *input_line_pointer = c;
7734 intel_syntax = -intel_syntax;
7737 i386_intel_simplify (exp);
7743 signed_cons (int size)
7745 if (flag_code == CODE_64BIT)
7753 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7760 if (exp.X_op == O_symbol)
7761 exp.X_op = O_secrel;
7763 emit_expr (&exp, 4);
7765 while (*input_line_pointer++ == ',');
7767 input_line_pointer--;
7768 demand_empty_rest_of_line ();
7772 /* Handle Vector operations. */
7775 check_VecOperations (char *op_string, char *op_end)
7777 const reg_entry *mask;
7782 && (op_end == NULL || op_string < op_end))
7785 if (*op_string == '{')
7789 /* Check broadcasts. */
7790 if (strncmp (op_string, "1to", 3) == 0)
7795 goto duplicated_vec_op;
7798 if (*op_string == '8')
7799 bcst_type = BROADCAST_1TO8;
7800 else if (*op_string == '4')
7801 bcst_type = BROADCAST_1TO4;
7802 else if (*op_string == '2')
7803 bcst_type = BROADCAST_1TO2;
7804 else if (*op_string == '1'
7805 && *(op_string+1) == '6')
7807 bcst_type = BROADCAST_1TO16;
7812 as_bad (_("Unsupported broadcast: `%s'"), saved);
7817 broadcast_op.type = bcst_type;
7818 broadcast_op.operand = this_operand;
7819 i.broadcast = &broadcast_op;
7821 /* Check masking operation. */
7822 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7824 /* k0 can't be used for write mask. */
7825 if (mask->reg_num == 0)
7827 as_bad (_("`%s' can't be used for write mask"),
7834 mask_op.mask = mask;
7835 mask_op.zeroing = 0;
7836 mask_op.operand = this_operand;
7842 goto duplicated_vec_op;
7844 i.mask->mask = mask;
7846 /* Only "{z}" is allowed here. No need to check
7847 zeroing mask explicitly. */
7848 if (i.mask->operand != this_operand)
7850 as_bad (_("invalid write mask `%s'"), saved);
7857 /* Check zeroing-flag for masking operation. */
7858 else if (*op_string == 'z')
7862 mask_op.mask = NULL;
7863 mask_op.zeroing = 1;
7864 mask_op.operand = this_operand;
7869 if (i.mask->zeroing)
7872 as_bad (_("duplicated `%s'"), saved);
7876 i.mask->zeroing = 1;
7878 /* Only "{%k}" is allowed here. No need to check mask
7879 register explicitly. */
7880 if (i.mask->operand != this_operand)
7882 as_bad (_("invalid zeroing-masking `%s'"),
7891 goto unknown_vec_op;
7893 if (*op_string != '}')
7895 as_bad (_("missing `}' in `%s'"), saved);
7902 /* We don't know this one. */
7903 as_bad (_("unknown vector operation: `%s'"), saved);
7911 i386_immediate (char *imm_start)
7913 char *save_input_line_pointer;
7914 char *gotfree_input_line;
7917 i386_operand_type types;
7919 operand_type_set (&types, ~0);
7921 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7923 as_bad (_("at most %d immediate operands are allowed"),
7924 MAX_IMMEDIATE_OPERANDS);
7928 exp = &im_expressions[i.imm_operands++];
7929 i.op[this_operand].imms = exp;
7931 if (is_space_char (*imm_start))
7934 save_input_line_pointer = input_line_pointer;
7935 input_line_pointer = imm_start;
7937 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7938 (i.bnd_prefix != NULL
7939 || add_bnd_prefix));
7940 if (gotfree_input_line)
7941 input_line_pointer = gotfree_input_line;
7943 exp_seg = expression (exp);
7947 /* Handle vector operations. */
7948 if (*input_line_pointer == '{')
7950 input_line_pointer = check_VecOperations (input_line_pointer,
7952 if (input_line_pointer == NULL)
7956 if (*input_line_pointer)
7957 as_bad (_("junk `%s' after expression"), input_line_pointer);
7959 input_line_pointer = save_input_line_pointer;
7960 if (gotfree_input_line)
7962 free (gotfree_input_line);
7964 if (exp->X_op == O_constant || exp->X_op == O_register)
7965 exp->X_op = O_illegal;
7968 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7972 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7973 i386_operand_type types, const char *imm_start)
7975 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7978 as_bad (_("missing or invalid immediate expression `%s'"),
7982 else if (exp->X_op == O_constant)
7984 /* Size it properly later. */
7985 i.types[this_operand].bitfield.imm64 = 1;
7986 /* If not 64bit, sign extend val. */
7987 if (flag_code != CODE_64BIT
7988 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7990 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7992 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7993 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7994 && exp_seg != absolute_section
7995 && exp_seg != text_section
7996 && exp_seg != data_section
7997 && exp_seg != bss_section
7998 && exp_seg != undefined_section
7999 && !bfd_is_com_section (exp_seg))
8001 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8005 else if (!intel_syntax && exp_seg == reg_section)
8008 as_bad (_("illegal immediate register operand %s"), imm_start);
8013 /* This is an address. The size of the address will be
8014 determined later, depending on destination register,
8015 suffix, or the default for the section. */
8016 i.types[this_operand].bitfield.imm8 = 1;
8017 i.types[this_operand].bitfield.imm16 = 1;
8018 i.types[this_operand].bitfield.imm32 = 1;
8019 i.types[this_operand].bitfield.imm32s = 1;
8020 i.types[this_operand].bitfield.imm64 = 1;
8021 i.types[this_operand] = operand_type_and (i.types[this_operand],
8029 i386_scale (char *scale)
8032 char *save = input_line_pointer;
8034 input_line_pointer = scale;
8035 val = get_absolute_expression ();
8040 i.log2_scale_factor = 0;
8043 i.log2_scale_factor = 1;
8046 i.log2_scale_factor = 2;
8049 i.log2_scale_factor = 3;
8053 char sep = *input_line_pointer;
8055 *input_line_pointer = '\0';
8056 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8058 *input_line_pointer = sep;
8059 input_line_pointer = save;
8063 if (i.log2_scale_factor != 0 && i.index_reg == 0)
8065 as_warn (_("scale factor of %d without an index register"),
8066 1 << i.log2_scale_factor);
8067 i.log2_scale_factor = 0;
8069 scale = input_line_pointer;
8070 input_line_pointer = save;
8075 i386_displacement (char *disp_start, char *disp_end)
8079 char *save_input_line_pointer;
8080 char *gotfree_input_line;
8082 i386_operand_type bigdisp, types = anydisp;
8085 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8087 as_bad (_("at most %d displacement operands are allowed"),
8088 MAX_MEMORY_OPERANDS);
8092 operand_type_set (&bigdisp, 0);
8093 if ((i.types[this_operand].bitfield.jumpabsolute)
8094 || (!current_templates->start->opcode_modifier.jump
8095 && !current_templates->start->opcode_modifier.jumpdword))
8097 bigdisp.bitfield.disp32 = 1;
8098 override = (i.prefix[ADDR_PREFIX] != 0);
8099 if (flag_code == CODE_64BIT)
8103 bigdisp.bitfield.disp32s = 1;
8104 bigdisp.bitfield.disp64 = 1;
8107 else if ((flag_code == CODE_16BIT) ^ override)
8109 bigdisp.bitfield.disp32 = 0;
8110 bigdisp.bitfield.disp16 = 1;
8115 /* For PC-relative branches, the width of the displacement
8116 is dependent upon data size, not address size. */
8117 override = (i.prefix[DATA_PREFIX] != 0);
8118 if (flag_code == CODE_64BIT)
8120 if (override || i.suffix == WORD_MNEM_SUFFIX)
8121 bigdisp.bitfield.disp16 = 1;
8124 bigdisp.bitfield.disp32 = 1;
8125 bigdisp.bitfield.disp32s = 1;
8131 override = (i.suffix == (flag_code != CODE_16BIT
8133 : LONG_MNEM_SUFFIX));
8134 bigdisp.bitfield.disp32 = 1;
8135 if ((flag_code == CODE_16BIT) ^ override)
8137 bigdisp.bitfield.disp32 = 0;
8138 bigdisp.bitfield.disp16 = 1;
8142 i.types[this_operand] = operand_type_or (i.types[this_operand],
8145 exp = &disp_expressions[i.disp_operands];
8146 i.op[this_operand].disps = exp;
8148 save_input_line_pointer = input_line_pointer;
8149 input_line_pointer = disp_start;
8150 END_STRING_AND_SAVE (disp_end);
8152 #ifndef GCC_ASM_O_HACK
8153 #define GCC_ASM_O_HACK 0
8156 END_STRING_AND_SAVE (disp_end + 1);
8157 if (i.types[this_operand].bitfield.baseIndex
8158 && displacement_string_end[-1] == '+')
8160 /* This hack is to avoid a warning when using the "o"
8161 constraint within gcc asm statements.
8164 #define _set_tssldt_desc(n,addr,limit,type) \
8165 __asm__ __volatile__ ( \
8167 "movw %w1,2+%0\n\t" \
8169 "movb %b1,4+%0\n\t" \
8170 "movb %4,5+%0\n\t" \
8171 "movb $0,6+%0\n\t" \
8172 "movb %h1,7+%0\n\t" \
8174 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8176 This works great except that the output assembler ends
8177 up looking a bit weird if it turns out that there is
8178 no offset. You end up producing code that looks like:
8191 So here we provide the missing zero. */
8193 *displacement_string_end = '0';
8196 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8197 (i.bnd_prefix != NULL
8198 || add_bnd_prefix));
8199 if (gotfree_input_line)
8200 input_line_pointer = gotfree_input_line;
8202 exp_seg = expression (exp);
8205 if (*input_line_pointer)
8206 as_bad (_("junk `%s' after expression"), input_line_pointer);
8208 RESTORE_END_STRING (disp_end + 1);
8210 input_line_pointer = save_input_line_pointer;
8211 if (gotfree_input_line)
8213 free (gotfree_input_line);
8215 if (exp->X_op == O_constant || exp->X_op == O_register)
8216 exp->X_op = O_illegal;
8219 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8221 RESTORE_END_STRING (disp_end);
8227 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8228 i386_operand_type types, const char *disp_start)
8230 i386_operand_type bigdisp;
8233 /* We do this to make sure that the section symbol is in
8234 the symbol table. We will ultimately change the relocation
8235 to be relative to the beginning of the section. */
8236 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8237 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8238 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8240 if (exp->X_op != O_symbol)
8243 if (S_IS_LOCAL (exp->X_add_symbol)
8244 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8245 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8246 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8247 exp->X_op = O_subtract;
8248 exp->X_op_symbol = GOT_symbol;
8249 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8250 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8251 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8252 i.reloc[this_operand] = BFD_RELOC_64;
8254 i.reloc[this_operand] = BFD_RELOC_32;
8257 else if (exp->X_op == O_absent
8258 || exp->X_op == O_illegal
8259 || exp->X_op == O_big)
8262 as_bad (_("missing or invalid displacement expression `%s'"),
8267 else if (flag_code == CODE_64BIT
8268 && !i.prefix[ADDR_PREFIX]
8269 && exp->X_op == O_constant)
8271 /* Since displacement is signed extended to 64bit, don't allow
8272 disp32 and turn off disp32s if they are out of range. */
8273 i.types[this_operand].bitfield.disp32 = 0;
8274 if (!fits_in_signed_long (exp->X_add_number))
8276 i.types[this_operand].bitfield.disp32s = 0;
8277 if (i.types[this_operand].bitfield.baseindex)
8279 as_bad (_("0x%lx out range of signed 32bit displacement"),
8280 (long) exp->X_add_number);
8286 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8287 else if (exp->X_op != O_constant
8288 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8289 && exp_seg != absolute_section
8290 && exp_seg != text_section
8291 && exp_seg != data_section
8292 && exp_seg != bss_section
8293 && exp_seg != undefined_section
8294 && !bfd_is_com_section (exp_seg))
8296 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8301 /* Check if this is a displacement only operand. */
8302 bigdisp = i.types[this_operand];
8303 bigdisp.bitfield.disp8 = 0;
8304 bigdisp.bitfield.disp16 = 0;
8305 bigdisp.bitfield.disp32 = 0;
8306 bigdisp.bitfield.disp32s = 0;
8307 bigdisp.bitfield.disp64 = 0;
8308 if (operand_type_all_zero (&bigdisp))
8309 i.types[this_operand] = operand_type_and (i.types[this_operand],
8315 /* Make sure the memory operand we've been dealt is valid.
8316 Return 1 on success, 0 on a failure. */
8319 i386_index_check (const char *operand_string)
8321 const char *kind = "base/index";
8322 enum flag_code addr_mode;
8324 if (i.prefix[ADDR_PREFIX])
8325 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8328 addr_mode = flag_code;
8330 #if INFER_ADDR_PREFIX
8331 if (i.mem_operands == 0)
8333 /* Infer address prefix from the first memory operand. */
8334 const reg_entry *addr_reg = i.base_reg;
8336 if (addr_reg == NULL)
8337 addr_reg = i.index_reg;
8341 if (addr_reg->reg_num == RegEip
8342 || addr_reg->reg_num == RegEiz
8343 || addr_reg->reg_type.bitfield.reg32)
8344 addr_mode = CODE_32BIT;
8345 else if (flag_code != CODE_64BIT
8346 && addr_reg->reg_type.bitfield.reg16)
8347 addr_mode = CODE_16BIT;
8349 if (addr_mode != flag_code)
8351 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8353 /* Change the size of any displacement too. At most one
8354 of Disp16 or Disp32 is set.
8355 FIXME. There doesn't seem to be any real need for
8356 separate Disp16 and Disp32 flags. The same goes for
8357 Imm16 and Imm32. Removing them would probably clean
8358 up the code quite a lot. */
8359 if (flag_code != CODE_64BIT
8360 && (i.types[this_operand].bitfield.disp16
8361 || i.types[this_operand].bitfield.disp32))
8362 i.types[this_operand]
8363 = operand_type_xor (i.types[this_operand], disp16_32);
8370 if (current_templates->start->opcode_modifier.isstring
8371 && !current_templates->start->opcode_modifier.immext
8372 && (current_templates->end[-1].opcode_modifier.isstring
8375 /* Memory operands of string insns are special in that they only allow
8376 a single register (rDI, rSI, or rBX) as their memory address. */
8377 const reg_entry *expected_reg;
8378 static const char *di_si[][2] =
8384 static const char *bx[] = { "ebx", "bx", "rbx" };
8386 kind = "string address";
8388 if (current_templates->start->opcode_modifier.w)
8390 i386_operand_type type = current_templates->end[-1].operand_types[0];
8392 if (!type.bitfield.baseindex
8393 || ((!i.mem_operands != !intel_syntax)
8394 && current_templates->end[-1].operand_types[1]
8395 .bitfield.baseindex))
8396 type = current_templates->end[-1].operand_types[1];
8397 expected_reg = hash_find (reg_hash,
8398 di_si[addr_mode][type.bitfield.esseg]);
8402 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8404 if (i.base_reg != expected_reg
8406 || operand_type_check (i.types[this_operand], disp))
8408 /* The second memory operand must have the same size as
8412 && !((addr_mode == CODE_64BIT
8413 && i.base_reg->reg_type.bitfield.reg64)
8414 || (addr_mode == CODE_32BIT
8415 ? i.base_reg->reg_type.bitfield.reg32
8416 : i.base_reg->reg_type.bitfield.reg16)))
8419 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8421 intel_syntax ? '[' : '(',
8423 expected_reg->reg_name,
8424 intel_syntax ? ']' : ')');
8431 as_bad (_("`%s' is not a valid %s expression"),
8432 operand_string, kind);
8437 if (addr_mode != CODE_16BIT)
8439 /* 32-bit/64-bit checks. */
8441 && (addr_mode == CODE_64BIT
8442 ? !i.base_reg->reg_type.bitfield.reg64
8443 : !i.base_reg->reg_type.bitfield.reg32)
8445 || (i.base_reg->reg_num
8446 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8448 && !i.index_reg->reg_type.bitfield.regxmm
8449 && !i.index_reg->reg_type.bitfield.regymm
8450 && !i.index_reg->reg_type.bitfield.regzmm
8451 && ((addr_mode == CODE_64BIT
8452 ? !(i.index_reg->reg_type.bitfield.reg64
8453 || i.index_reg->reg_num == RegRiz)
8454 : !(i.index_reg->reg_type.bitfield.reg32
8455 || i.index_reg->reg_num == RegEiz))
8456 || !i.index_reg->reg_type.bitfield.baseindex)))
8461 /* 16-bit checks. */
8463 && (!i.base_reg->reg_type.bitfield.reg16
8464 || !i.base_reg->reg_type.bitfield.baseindex))
8466 && (!i.index_reg->reg_type.bitfield.reg16
8467 || !i.index_reg->reg_type.bitfield.baseindex
8469 && i.base_reg->reg_num < 6
8470 && i.index_reg->reg_num >= 6
8471 && i.log2_scale_factor == 0))))
8478 /* Handle vector immediates. */
8481 RC_SAE_immediate (const char *imm_start)
8483 unsigned int match_found, j;
8484 const char *pstr = imm_start;
8492 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8494 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8498 rc_op.type = RC_NamesTable[j].type;
8499 rc_op.operand = this_operand;
8500 i.rounding = &rc_op;
8504 as_bad (_("duplicated `%s'"), imm_start);
8507 pstr += RC_NamesTable[j].len;
8517 as_bad (_("Missing '}': '%s'"), imm_start);
8520 /* RC/SAE immediate string should contain nothing more. */;
8523 as_bad (_("Junk after '}': '%s'"), imm_start);
8527 exp = &im_expressions[i.imm_operands++];
8528 i.op[this_operand].imms = exp;
8530 exp->X_op = O_constant;
8531 exp->X_add_number = 0;
8532 exp->X_add_symbol = (symbolS *) 0;
8533 exp->X_op_symbol = (symbolS *) 0;
8535 i.types[this_operand].bitfield.imm8 = 1;
8539 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8543 i386_att_operand (char *operand_string)
8547 char *op_string = operand_string;
8549 if (is_space_char (*op_string))
8552 /* We check for an absolute prefix (differentiating,
8553 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8554 if (*op_string == ABSOLUTE_PREFIX)
8557 if (is_space_char (*op_string))
8559 i.types[this_operand].bitfield.jumpabsolute = 1;
8562 /* Check if operand is a register. */
8563 if ((r = parse_register (op_string, &end_op)) != NULL)
8565 i386_operand_type temp;
8567 /* Check for a segment override by searching for ':' after a
8568 segment register. */
8570 if (is_space_char (*op_string))
8572 if (*op_string == ':'
8573 && (r->reg_type.bitfield.sreg2
8574 || r->reg_type.bitfield.sreg3))
8579 i.seg[i.mem_operands] = &es;
8582 i.seg[i.mem_operands] = &cs;
8585 i.seg[i.mem_operands] = &ss;
8588 i.seg[i.mem_operands] = &ds;
8591 i.seg[i.mem_operands] = &fs;
8594 i.seg[i.mem_operands] = &gs;
8598 /* Skip the ':' and whitespace. */
8600 if (is_space_char (*op_string))
8603 if (!is_digit_char (*op_string)
8604 && !is_identifier_char (*op_string)
8605 && *op_string != '('
8606 && *op_string != ABSOLUTE_PREFIX)
8608 as_bad (_("bad memory operand `%s'"), op_string);
8611 /* Handle case of %es:*foo. */
8612 if (*op_string == ABSOLUTE_PREFIX)
8615 if (is_space_char (*op_string))
8617 i.types[this_operand].bitfield.jumpabsolute = 1;
8619 goto do_memory_reference;
8622 /* Handle vector operations. */
8623 if (*op_string == '{')
8625 op_string = check_VecOperations (op_string, NULL);
8626 if (op_string == NULL)
8632 as_bad (_("junk `%s' after register"), op_string);
8636 temp.bitfield.baseindex = 0;
8637 i.types[this_operand] = operand_type_or (i.types[this_operand],
8639 i.types[this_operand].bitfield.unspecified = 0;
8640 i.op[this_operand].regs = r;
8643 else if (*op_string == REGISTER_PREFIX)
8645 as_bad (_("bad register name `%s'"), op_string);
8648 else if (*op_string == IMMEDIATE_PREFIX)
8651 if (i.types[this_operand].bitfield.jumpabsolute)
8653 as_bad (_("immediate operand illegal with absolute jump"));
8656 if (!i386_immediate (op_string))
8659 else if (RC_SAE_immediate (operand_string))
8661 /* If it is a RC or SAE immediate, do nothing. */
8664 else if (is_digit_char (*op_string)
8665 || is_identifier_char (*op_string)
8666 || *op_string == '(')
8668 /* This is a memory reference of some sort. */
8671 /* Start and end of displacement string expression (if found). */
8672 char *displacement_string_start;
8673 char *displacement_string_end;
8676 do_memory_reference:
8677 if ((i.mem_operands == 1
8678 && !current_templates->start->opcode_modifier.isstring)
8679 || i.mem_operands == 2)
8681 as_bad (_("too many memory references for `%s'"),
8682 current_templates->start->name);
8686 /* Check for base index form. We detect the base index form by
8687 looking for an ')' at the end of the operand, searching
8688 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8690 base_string = op_string + strlen (op_string);
8692 /* Handle vector operations. */
8693 vop_start = strchr (op_string, '{');
8694 if (vop_start && vop_start < base_string)
8696 if (check_VecOperations (vop_start, base_string) == NULL)
8698 base_string = vop_start;
8702 if (is_space_char (*base_string))
8705 /* If we only have a displacement, set-up for it to be parsed later. */
8706 displacement_string_start = op_string;
8707 displacement_string_end = base_string + 1;
8709 if (*base_string == ')')
8712 unsigned int parens_balanced = 1;
8713 /* We've already checked that the number of left & right ()'s are
8714 equal, so this loop will not be infinite. */
8718 if (*base_string == ')')
8720 if (*base_string == '(')
8723 while (parens_balanced);
8725 temp_string = base_string;
8727 /* Skip past '(' and whitespace. */
8729 if (is_space_char (*base_string))
8732 if (*base_string == ','
8733 || ((i.base_reg = parse_register (base_string, &end_op))
8736 displacement_string_end = temp_string;
8738 i.types[this_operand].bitfield.baseindex = 1;
8742 base_string = end_op;
8743 if (is_space_char (*base_string))
8747 /* There may be an index reg or scale factor here. */
8748 if (*base_string == ',')
8751 if (is_space_char (*base_string))
8754 if ((i.index_reg = parse_register (base_string, &end_op))
8757 base_string = end_op;
8758 if (is_space_char (*base_string))
8760 if (*base_string == ',')
8763 if (is_space_char (*base_string))
8766 else if (*base_string != ')')
8768 as_bad (_("expecting `,' or `)' "
8769 "after index register in `%s'"),
8774 else if (*base_string == REGISTER_PREFIX)
8776 end_op = strchr (base_string, ',');
8779 as_bad (_("bad register name `%s'"), base_string);
8783 /* Check for scale factor. */
8784 if (*base_string != ')')
8786 char *end_scale = i386_scale (base_string);
8791 base_string = end_scale;
8792 if (is_space_char (*base_string))
8794 if (*base_string != ')')
8796 as_bad (_("expecting `)' "
8797 "after scale factor in `%s'"),
8802 else if (!i.index_reg)
8804 as_bad (_("expecting index register or scale factor "
8805 "after `,'; got '%c'"),
8810 else if (*base_string != ')')
8812 as_bad (_("expecting `,' or `)' "
8813 "after base register in `%s'"),
8818 else if (*base_string == REGISTER_PREFIX)
8820 end_op = strchr (base_string, ',');
8823 as_bad (_("bad register name `%s'"), base_string);
8828 /* If there's an expression beginning the operand, parse it,
8829 assuming displacement_string_start and
8830 displacement_string_end are meaningful. */
8831 if (displacement_string_start != displacement_string_end)
8833 if (!i386_displacement (displacement_string_start,
8834 displacement_string_end))
8838 /* Special case for (%dx) while doing input/output op. */
8840 && operand_type_equal (&i.base_reg->reg_type,
8841 ®16_inoutportreg)
8843 && i.log2_scale_factor == 0
8844 && i.seg[i.mem_operands] == 0
8845 && !operand_type_check (i.types[this_operand], disp))
8847 i.types[this_operand] = inoutportreg;
8851 if (i386_index_check (operand_string) == 0)
8853 i.types[this_operand].bitfield.mem = 1;
8858 /* It's not a memory operand; argh! */
8859 as_bad (_("invalid char %s beginning operand %d `%s'"),
8860 output_invalid (*op_string),
8865 return 1; /* Normal return. */
8868 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8869 that an rs_machine_dependent frag may reach. */
8872 i386_frag_max_var (fragS *frag)
8874 /* The only relaxable frags are for jumps.
8875 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8876 gas_assert (frag->fr_type == rs_machine_dependent);
8877 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8880 /* md_estimate_size_before_relax()
8882 Called just before relax() for rs_machine_dependent frags. The x86
8883 assembler uses these frags to handle variable size jump
8886 Any symbol that is now undefined will not become defined.
8887 Return the correct fr_subtype in the frag.
8888 Return the initial "guess for variable size of frag" to caller.
8889 The guess is actually the growth beyond the fixed part. Whatever
8890 we do to grow the fixed or variable part contributes to our
8894 md_estimate_size_before_relax (fragS *fragP, segT segment)
8896 /* We've already got fragP->fr_subtype right; all we have to do is
8897 check for un-relaxable symbols. On an ELF system, we can't relax
8898 an externally visible symbol, because it may be overridden by a
8900 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8901 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8903 && (S_IS_EXTERNAL (fragP->fr_symbol)
8904 || S_IS_WEAK (fragP->fr_symbol)
8905 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8906 & BSF_GNU_INDIRECT_FUNCTION))))
8908 #if defined (OBJ_COFF) && defined (TE_PE)
8909 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8910 && S_IS_WEAK (fragP->fr_symbol))
8914 /* Symbol is undefined in this segment, or we need to keep a
8915 reloc so that weak symbols can be overridden. */
8916 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8917 enum bfd_reloc_code_real reloc_type;
8918 unsigned char *opcode;
8921 if (fragP->fr_var != NO_RELOC)
8922 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8924 reloc_type = BFD_RELOC_16_PCREL;
8926 reloc_type = BFD_RELOC_32_PCREL;
8928 old_fr_fix = fragP->fr_fix;
8929 opcode = (unsigned char *) fragP->fr_opcode;
8931 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8934 /* Make jmp (0xeb) a (d)word displacement jump. */
8936 fragP->fr_fix += size;
8937 fix_new (fragP, old_fr_fix, size,
8939 fragP->fr_offset, 1,
8945 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8947 /* Negate the condition, and branch past an
8948 unconditional jump. */
8951 /* Insert an unconditional jump. */
8953 /* We added two extra opcode bytes, and have a two byte
8955 fragP->fr_fix += 2 + 2;
8956 fix_new (fragP, old_fr_fix + 2, 2,
8958 fragP->fr_offset, 1,
8965 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8970 fixP = fix_new (fragP, old_fr_fix, 1,
8972 fragP->fr_offset, 1,
8974 fixP->fx_signed = 1;
8978 /* This changes the byte-displacement jump 0x7N
8979 to the (d)word-displacement jump 0x0f,0x8N. */
8980 opcode[1] = opcode[0] + 0x10;
8981 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8982 /* We've added an opcode byte. */
8983 fragP->fr_fix += 1 + size;
8984 fix_new (fragP, old_fr_fix + 1, size,
8986 fragP->fr_offset, 1,
8991 BAD_CASE (fragP->fr_subtype);
8995 return fragP->fr_fix - old_fr_fix;
8998 /* Guess size depending on current relax state. Initially the relax
8999 state will correspond to a short jump and we return 1, because
9000 the variable part of the frag (the branch offset) is one byte
9001 long. However, we can relax a section more than once and in that
9002 case we must either set fr_subtype back to the unrelaxed state,
9003 or return the value for the appropriate branch. */
9004 return md_relax_table[fragP->fr_subtype].rlx_length;
9007 /* Called after relax() is finished.
9009 In: Address of frag.
9010 fr_type == rs_machine_dependent.
9011 fr_subtype is what the address relaxed to.
9013 Out: Any fixSs and constants are set up.
9014 Caller will turn frag into a ".space 0". */
9017 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9020 unsigned char *opcode;
9021 unsigned char *where_to_put_displacement = NULL;
9022 offsetT target_address;
9023 offsetT opcode_address;
9024 unsigned int extension = 0;
9025 offsetT displacement_from_opcode_start;
9027 opcode = (unsigned char *) fragP->fr_opcode;
9029 /* Address we want to reach in file space. */
9030 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
9032 /* Address opcode resides at in file space. */
9033 opcode_address = fragP->fr_address + fragP->fr_fix;
9035 /* Displacement from opcode start to fill into instruction. */
9036 displacement_from_opcode_start = target_address - opcode_address;
9038 if ((fragP->fr_subtype & BIG) == 0)
9040 /* Don't have to change opcode. */
9041 extension = 1; /* 1 opcode + 1 displacement */
9042 where_to_put_displacement = &opcode[1];
9046 if (no_cond_jump_promotion
9047 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
9048 as_warn_where (fragP->fr_file, fragP->fr_line,
9049 _("long jump required"));
9051 switch (fragP->fr_subtype)
9053 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9054 extension = 4; /* 1 opcode + 4 displacement */
9056 where_to_put_displacement = &opcode[1];
9059 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9060 extension = 2; /* 1 opcode + 2 displacement */
9062 where_to_put_displacement = &opcode[1];
9065 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9066 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9067 extension = 5; /* 2 opcode + 4 displacement */
9068 opcode[1] = opcode[0] + 0x10;
9069 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9070 where_to_put_displacement = &opcode[2];
9073 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9074 extension = 3; /* 2 opcode + 2 displacement */
9075 opcode[1] = opcode[0] + 0x10;
9076 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9077 where_to_put_displacement = &opcode[2];
9080 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9085 where_to_put_displacement = &opcode[3];
9089 BAD_CASE (fragP->fr_subtype);
9094 /* If size if less then four we are sure that the operand fits,
9095 but if it's 4, then it could be that the displacement is larger
9097 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9099 && ((addressT) (displacement_from_opcode_start - extension
9100 + ((addressT) 1 << 31))
9101 > (((addressT) 2 << 31) - 1)))
9103 as_bad_where (fragP->fr_file, fragP->fr_line,
9104 _("jump target out of range"));
9105 /* Make us emit 0. */
9106 displacement_from_opcode_start = extension;
9108 /* Now put displacement after opcode. */
9109 md_number_to_chars ((char *) where_to_put_displacement,
9110 (valueT) (displacement_from_opcode_start - extension),
9111 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9112 fragP->fr_fix += extension;
9115 /* Apply a fixup (fixP) to segment data, once it has been determined
9116 by our caller that we have all the info we need to fix it up.
9118 Parameter valP is the pointer to the value of the bits.
9120 On the 386, immediates, displacements, and data pointers are all in
9121 the same (little-endian) format, so we don't need to care about which
9125 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9127 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9128 valueT value = *valP;
9130 #if !defined (TE_Mach)
9133 switch (fixP->fx_r_type)
9139 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9142 case BFD_RELOC_X86_64_32S:
9143 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9146 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9149 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9154 if (fixP->fx_addsy != NULL
9155 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9156 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9157 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9158 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9159 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
9160 && !use_rela_relocations)
9162 /* This is a hack. There should be a better way to handle this.
9163 This covers for the fact that bfd_install_relocation will
9164 subtract the current location (for partial_inplace, PC relative
9165 relocations); see more below. */
9169 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9172 value += fixP->fx_where + fixP->fx_frag->fr_address;
9174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9177 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9180 || (symbol_section_p (fixP->fx_addsy)
9181 && sym_seg != absolute_section))
9182 && !generic_force_reloc (fixP))
9184 /* Yes, we add the values in twice. This is because
9185 bfd_install_relocation subtracts them out again. I think
9186 bfd_install_relocation is broken, but I don't dare change
9188 value += fixP->fx_where + fixP->fx_frag->fr_address;
9192 #if defined (OBJ_COFF) && defined (TE_PE)
9193 /* For some reason, the PE format does not store a
9194 section address offset for a PC relative symbol. */
9195 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9196 || S_IS_WEAK (fixP->fx_addsy))
9197 value += md_pcrel_from (fixP);
9200 #if defined (OBJ_COFF) && defined (TE_PE)
9201 if (fixP->fx_addsy != NULL
9202 && S_IS_WEAK (fixP->fx_addsy)
9203 /* PR 16858: Do not modify weak function references. */
9204 && ! fixP->fx_pcrel)
9206 #if !defined (TE_PEP)
9207 /* For x86 PE weak function symbols are neither PC-relative
9208 nor do they set S_IS_FUNCTION. So the only reliable way
9209 to detect them is to check the flags of their containing
9211 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9212 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9216 value -= S_GET_VALUE (fixP->fx_addsy);
9220 /* Fix a few things - the dynamic linker expects certain values here,
9221 and we must not disappoint it. */
9222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9223 if (IS_ELF && fixP->fx_addsy)
9224 switch (fixP->fx_r_type)
9226 case BFD_RELOC_386_PLT32:
9227 case BFD_RELOC_X86_64_PLT32:
9228 case BFD_RELOC_X86_64_PLT32_BND:
9229 /* Make the jump instruction point to the address of the operand. At
9230 runtime we merely add the offset to the actual PLT entry. */
9234 case BFD_RELOC_386_TLS_GD:
9235 case BFD_RELOC_386_TLS_LDM:
9236 case BFD_RELOC_386_TLS_IE_32:
9237 case BFD_RELOC_386_TLS_IE:
9238 case BFD_RELOC_386_TLS_GOTIE:
9239 case BFD_RELOC_386_TLS_GOTDESC:
9240 case BFD_RELOC_X86_64_TLSGD:
9241 case BFD_RELOC_X86_64_TLSLD:
9242 case BFD_RELOC_X86_64_GOTTPOFF:
9243 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9244 value = 0; /* Fully resolved at runtime. No addend. */
9246 case BFD_RELOC_386_TLS_LE:
9247 case BFD_RELOC_386_TLS_LDO_32:
9248 case BFD_RELOC_386_TLS_LE_32:
9249 case BFD_RELOC_X86_64_DTPOFF32:
9250 case BFD_RELOC_X86_64_DTPOFF64:
9251 case BFD_RELOC_X86_64_TPOFF32:
9252 case BFD_RELOC_X86_64_TPOFF64:
9253 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9256 case BFD_RELOC_386_TLS_DESC_CALL:
9257 case BFD_RELOC_X86_64_TLSDESC_CALL:
9258 value = 0; /* Fully resolved at runtime. No addend. */
9259 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9263 case BFD_RELOC_386_GOT32:
9264 case BFD_RELOC_X86_64_GOT32:
9265 value = 0; /* Fully resolved at runtime. No addend. */
9268 case BFD_RELOC_VTABLE_INHERIT:
9269 case BFD_RELOC_VTABLE_ENTRY:
9276 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9278 #endif /* !defined (TE_Mach) */
9280 /* Are we finished with this relocation now? */
9281 if (fixP->fx_addsy == NULL)
9283 #if defined (OBJ_COFF) && defined (TE_PE)
9284 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9287 /* Remember value for tc_gen_reloc. */
9288 fixP->fx_addnumber = value;
9289 /* Clear out the frag for now. */
9293 else if (use_rela_relocations)
9295 fixP->fx_no_overflow = 1;
9296 /* Remember value for tc_gen_reloc. */
9297 fixP->fx_addnumber = value;
9301 md_number_to_chars (p, value, fixP->fx_size);
9305 md_atof (int type, char *litP, int *sizeP)
9307 /* This outputs the LITTLENUMs in REVERSE order;
9308 in accord with the bigendian 386. */
9309 return ieee_md_atof (type, litP, sizeP, FALSE);
9312 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9315 output_invalid (int c)
9318 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9321 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9322 "(0x%x)", (unsigned char) c);
9323 return output_invalid_buf;
9326 /* REG_STRING starts *before* REGISTER_PREFIX. */
9328 static const reg_entry *
9329 parse_real_register (char *reg_string, char **end_op)
9331 char *s = reg_string;
9333 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9336 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9337 if (*s == REGISTER_PREFIX)
9340 if (is_space_char (*s))
9344 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9346 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9347 return (const reg_entry *) NULL;
9351 /* For naked regs, make sure that we are not dealing with an identifier.
9352 This prevents confusing an identifier like `eax_var' with register
9354 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9355 return (const reg_entry *) NULL;
9359 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9361 /* Handle floating point regs, allowing spaces in the (i) part. */
9362 if (r == i386_regtab /* %st is first entry of table */)
9364 if (is_space_char (*s))
9369 if (is_space_char (*s))
9371 if (*s >= '0' && *s <= '7')
9375 if (is_space_char (*s))
9380 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9385 /* We have "%st(" then garbage. */
9386 return (const reg_entry *) NULL;
9390 if (r == NULL || allow_pseudo_reg)
9393 if (operand_type_all_zero (&r->reg_type))
9394 return (const reg_entry *) NULL;
9396 if ((r->reg_type.bitfield.reg32
9397 || r->reg_type.bitfield.sreg3
9398 || r->reg_type.bitfield.control
9399 || r->reg_type.bitfield.debug
9400 || r->reg_type.bitfield.test)
9401 && !cpu_arch_flags.bitfield.cpui386)
9402 return (const reg_entry *) NULL;
9404 if (r->reg_type.bitfield.floatreg
9405 && !cpu_arch_flags.bitfield.cpu8087
9406 && !cpu_arch_flags.bitfield.cpu287
9407 && !cpu_arch_flags.bitfield.cpu387)
9408 return (const reg_entry *) NULL;
9410 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9411 return (const reg_entry *) NULL;
9413 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9414 return (const reg_entry *) NULL;
9416 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9417 return (const reg_entry *) NULL;
9419 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9420 && !cpu_arch_flags.bitfield.cpuavx512f)
9421 return (const reg_entry *) NULL;
9423 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9424 if (!allow_index_reg
9425 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9426 return (const reg_entry *) NULL;
9428 /* Upper 16 vector register is only available with VREX in 64bit
9430 if ((r->reg_flags & RegVRex))
9432 if (!cpu_arch_flags.bitfield.cpuvrex
9433 || flag_code != CODE_64BIT)
9434 return (const reg_entry *) NULL;
9439 if (((r->reg_flags & (RegRex64 | RegRex))
9440 || r->reg_type.bitfield.reg64)
9441 && (!cpu_arch_flags.bitfield.cpulm
9442 || !operand_type_equal (&r->reg_type, &control))
9443 && flag_code != CODE_64BIT)
9444 return (const reg_entry *) NULL;
9446 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9447 return (const reg_entry *) NULL;
9452 /* REG_STRING starts *before* REGISTER_PREFIX. */
9454 static const reg_entry *
9455 parse_register (char *reg_string, char **end_op)
9459 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9460 r = parse_real_register (reg_string, end_op);
9465 char *save = input_line_pointer;
9469 input_line_pointer = reg_string;
9470 c = get_symbol_end ();
9471 symbolP = symbol_find (reg_string);
9472 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9474 const expressionS *e = symbol_get_value_expression (symbolP);
9476 know (e->X_op == O_register);
9477 know (e->X_add_number >= 0
9478 && (valueT) e->X_add_number < i386_regtab_size);
9479 r = i386_regtab + e->X_add_number;
9480 if ((r->reg_flags & RegVRex))
9482 *end_op = input_line_pointer;
9484 *input_line_pointer = c;
9485 input_line_pointer = save;
9491 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9494 char *end = input_line_pointer;
9497 r = parse_register (name, &input_line_pointer);
9498 if (r && end <= input_line_pointer)
9500 *nextcharP = *input_line_pointer;
9501 *input_line_pointer = 0;
9502 e->X_op = O_register;
9503 e->X_add_number = r - i386_regtab;
9506 input_line_pointer = end;
9508 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9512 md_operand (expressionS *e)
9517 switch (*input_line_pointer)
9519 case REGISTER_PREFIX:
9520 r = parse_real_register (input_line_pointer, &end);
9523 e->X_op = O_register;
9524 e->X_add_number = r - i386_regtab;
9525 input_line_pointer = end;
9530 gas_assert (intel_syntax);
9531 end = input_line_pointer++;
9533 if (*input_line_pointer == ']')
9535 ++input_line_pointer;
9536 e->X_op_symbol = make_expr_symbol (e);
9537 e->X_add_symbol = NULL;
9538 e->X_add_number = 0;
9544 input_line_pointer = end;
9551 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9552 const char *md_shortopts = "kVQ:sqn";
9554 const char *md_shortopts = "qn";
9557 #define OPTION_32 (OPTION_MD_BASE + 0)
9558 #define OPTION_64 (OPTION_MD_BASE + 1)
9559 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9560 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9561 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9562 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9563 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9564 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9565 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9566 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9567 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9568 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9569 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9570 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9571 #define OPTION_X32 (OPTION_MD_BASE + 14)
9572 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9573 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9574 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9575 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
9576 #define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
9577 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
9579 struct option md_longopts[] =
9581 {"32", no_argument, NULL, OPTION_32},
9582 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9583 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9584 {"64", no_argument, NULL, OPTION_64},
9586 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9587 {"x32", no_argument, NULL, OPTION_X32},
9589 {"divide", no_argument, NULL, OPTION_DIVIDE},
9590 {"march", required_argument, NULL, OPTION_MARCH},
9591 {"mtune", required_argument, NULL, OPTION_MTUNE},
9592 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9593 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9594 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9595 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9596 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9597 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9598 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9599 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9600 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9601 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9602 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9603 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9604 # if defined (TE_PE) || defined (TE_PEP)
9605 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9607 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
9608 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
9609 {NULL, no_argument, NULL, 0}
9611 size_t md_longopts_size = sizeof (md_longopts);
9614 md_parse_option (int c, char *arg)
9622 optimize_align_code = 0;
9629 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9630 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9631 should be emitted or not. FIXME: Not implemented. */
9635 /* -V: SVR4 argument to print version ID. */
9637 print_version_id ();
9640 /* -k: Ignore for FreeBSD compatibility. */
9645 /* -s: On i386 Solaris, this tells the native assembler to use
9646 .stab instead of .stab.excl. We always use .stab anyhow. */
9649 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9650 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9653 const char **list, **l;
9655 list = bfd_target_list ();
9656 for (l = list; *l != NULL; l++)
9657 if (CONST_STRNEQ (*l, "elf64-x86-64")
9658 || strcmp (*l, "coff-x86-64") == 0
9659 || strcmp (*l, "pe-x86-64") == 0
9660 || strcmp (*l, "pei-x86-64") == 0
9661 || strcmp (*l, "mach-o-x86-64") == 0)
9663 default_arch = "x86_64";
9667 as_fatal (_("no compiled in support for x86_64"));
9673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9677 const char **list, **l;
9679 list = bfd_target_list ();
9680 for (l = list; *l != NULL; l++)
9681 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9683 default_arch = "x86_64:32";
9687 as_fatal (_("no compiled in support for 32bit x86_64"));
9691 as_fatal (_("32bit x86_64 is only supported for ELF"));
9696 default_arch = "i386";
9700 #ifdef SVR4_COMMENT_CHARS
9705 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9707 for (s = i386_comment_chars; *s != '\0'; s++)
9711 i386_comment_chars = n;
9717 arch = xstrdup (arg);
9721 as_fatal (_("invalid -march= option: `%s'"), arg);
9722 next = strchr (arch, '+');
9725 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9727 if (strcmp (arch, cpu_arch [j].name) == 0)
9730 if (! cpu_arch[j].flags.bitfield.cpui386)
9733 cpu_arch_name = cpu_arch[j].name;
9734 cpu_sub_arch_name = NULL;
9735 cpu_arch_flags = cpu_arch[j].flags;
9736 cpu_arch_isa = cpu_arch[j].type;
9737 cpu_arch_isa_flags = cpu_arch[j].flags;
9738 if (!cpu_arch_tune_set)
9740 cpu_arch_tune = cpu_arch_isa;
9741 cpu_arch_tune_flags = cpu_arch_isa_flags;
9745 else if (*cpu_arch [j].name == '.'
9746 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9748 /* ISA entension. */
9749 i386_cpu_flags flags;
9751 if (!cpu_arch[j].negated)
9752 flags = cpu_flags_or (cpu_arch_flags,
9755 flags = cpu_flags_and_not (cpu_arch_flags,
9757 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9759 if (cpu_sub_arch_name)
9761 char *name = cpu_sub_arch_name;
9762 cpu_sub_arch_name = concat (name,
9764 (const char *) NULL);
9768 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9769 cpu_arch_flags = flags;
9770 cpu_arch_isa_flags = flags;
9776 if (j >= ARRAY_SIZE (cpu_arch))
9777 as_fatal (_("invalid -march= option: `%s'"), arg);
9781 while (next != NULL );
9786 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9787 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9789 if (strcmp (arg, cpu_arch [j].name) == 0)
9791 cpu_arch_tune_set = 1;
9792 cpu_arch_tune = cpu_arch [j].type;
9793 cpu_arch_tune_flags = cpu_arch[j].flags;
9797 if (j >= ARRAY_SIZE (cpu_arch))
9798 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9801 case OPTION_MMNEMONIC:
9802 if (strcasecmp (arg, "att") == 0)
9804 else if (strcasecmp (arg, "intel") == 0)
9807 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9810 case OPTION_MSYNTAX:
9811 if (strcasecmp (arg, "att") == 0)
9813 else if (strcasecmp (arg, "intel") == 0)
9816 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9819 case OPTION_MINDEX_REG:
9820 allow_index_reg = 1;
9823 case OPTION_MNAKED_REG:
9824 allow_naked_reg = 1;
9827 case OPTION_MOLD_GCC:
9831 case OPTION_MSSE2AVX:
9835 case OPTION_MSSE_CHECK:
9836 if (strcasecmp (arg, "error") == 0)
9837 sse_check = check_error;
9838 else if (strcasecmp (arg, "warning") == 0)
9839 sse_check = check_warning;
9840 else if (strcasecmp (arg, "none") == 0)
9841 sse_check = check_none;
9843 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9846 case OPTION_MOPERAND_CHECK:
9847 if (strcasecmp (arg, "error") == 0)
9848 operand_check = check_error;
9849 else if (strcasecmp (arg, "warning") == 0)
9850 operand_check = check_warning;
9851 else if (strcasecmp (arg, "none") == 0)
9852 operand_check = check_none;
9854 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9857 case OPTION_MAVXSCALAR:
9858 if (strcasecmp (arg, "128") == 0)
9860 else if (strcasecmp (arg, "256") == 0)
9863 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9866 case OPTION_MADD_BND_PREFIX:
9870 case OPTION_MEVEXLIG:
9871 if (strcmp (arg, "128") == 0)
9873 else if (strcmp (arg, "256") == 0)
9875 else if (strcmp (arg, "512") == 0)
9878 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9881 case OPTION_MEVEXRCIG:
9882 if (strcmp (arg, "rne") == 0)
9884 else if (strcmp (arg, "rd") == 0)
9886 else if (strcmp (arg, "ru") == 0)
9888 else if (strcmp (arg, "rz") == 0)
9891 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9894 case OPTION_MEVEXWIG:
9895 if (strcmp (arg, "0") == 0)
9897 else if (strcmp (arg, "1") == 0)
9900 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9903 # if defined (TE_PE) || defined (TE_PEP)
9904 case OPTION_MBIG_OBJ:
9909 case OPTION_OMIT_LOCK_PREFIX:
9910 if (strcasecmp (arg, "yes") == 0)
9911 omit_lock_prefix = 1;
9912 else if (strcasecmp (arg, "no") == 0)
9913 omit_lock_prefix = 0;
9915 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9924 #define MESSAGE_TEMPLATE \
9928 show_arch (FILE *stream, int ext, int check)
9930 static char message[] = MESSAGE_TEMPLATE;
9931 char *start = message + 27;
9933 int size = sizeof (MESSAGE_TEMPLATE);
9940 left = size - (start - message);
9941 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9943 /* Should it be skipped? */
9944 if (cpu_arch [j].skip)
9947 name = cpu_arch [j].name;
9948 len = cpu_arch [j].len;
9951 /* It is an extension. Skip if we aren't asked to show it. */
9962 /* It is an processor. Skip if we show only extension. */
9965 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9967 /* It is an impossible processor - skip. */
9971 /* Reserve 2 spaces for ", " or ",\0" */
9974 /* Check if there is any room. */
9982 p = mempcpy (p, name, len);
9986 /* Output the current message now and start a new one. */
9989 fprintf (stream, "%s\n", message);
9991 left = size - (start - message) - len - 2;
9993 gas_assert (left >= 0);
9995 p = mempcpy (p, name, len);
10000 fprintf (stream, "%s\n", message);
10004 md_show_usage (FILE *stream)
10006 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10007 fprintf (stream, _("\
10009 -V print assembler version number\n\
10012 fprintf (stream, _("\
10013 -n Do not optimize code alignment\n\
10014 -q quieten some warnings\n"));
10015 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10016 fprintf (stream, _("\
10019 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10020 || defined (TE_PE) || defined (TE_PEP))
10021 fprintf (stream, _("\
10022 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
10024 #ifdef SVR4_COMMENT_CHARS
10025 fprintf (stream, _("\
10026 --divide do not treat `/' as a comment character\n"));
10028 fprintf (stream, _("\
10029 --divide ignored\n"));
10031 fprintf (stream, _("\
10032 -march=CPU[,+EXTENSION...]\n\
10033 generate code for CPU and EXTENSION, CPU is one of:\n"));
10034 show_arch (stream, 0, 1);
10035 fprintf (stream, _("\
10036 EXTENSION is combination of:\n"));
10037 show_arch (stream, 1, 0);
10038 fprintf (stream, _("\
10039 -mtune=CPU optimize for CPU, CPU is one of:\n"));
10040 show_arch (stream, 0, 0);
10041 fprintf (stream, _("\
10042 -msse2avx encode SSE instructions with VEX prefix\n"));
10043 fprintf (stream, _("\
10044 -msse-check=[none|error|warning]\n\
10045 check SSE instructions\n"));
10046 fprintf (stream, _("\
10047 -moperand-check=[none|error|warning]\n\
10048 check operand combinations for validity\n"));
10049 fprintf (stream, _("\
10050 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10052 fprintf (stream, _("\
10053 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10055 fprintf (stream, _("\
10056 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10057 for EVEX.W bit ignored instructions\n"));
10058 fprintf (stream, _("\
10059 -mevexrcig=[rne|rd|ru|rz]\n\
10060 encode EVEX instructions with specific EVEX.RC value\n\
10061 for SAE-only ignored instructions\n"));
10062 fprintf (stream, _("\
10063 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10064 fprintf (stream, _("\
10065 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10066 fprintf (stream, _("\
10067 -mindex-reg support pseudo index registers\n"));
10068 fprintf (stream, _("\
10069 -mnaked-reg don't require `%%' prefix for registers\n"));
10070 fprintf (stream, _("\
10071 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
10072 fprintf (stream, _("\
10073 -madd-bnd-prefix add BND prefix for all valid branches\n"));
10074 # if defined (TE_PE) || defined (TE_PEP)
10075 fprintf (stream, _("\
10076 -mbig-obj generate big object files\n"));
10078 fprintf (stream, _("\
10079 -momit-lock-prefix=[no|yes]\n\
10080 strip all lock prefixes\n"));
10083 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
10084 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10085 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
10087 /* Pick the target format to use. */
10090 i386_target_format (void)
10092 if (!strncmp (default_arch, "x86_64", 6))
10094 update_code_flag (CODE_64BIT, 1);
10095 if (default_arch[6] == '\0')
10096 x86_elf_abi = X86_64_ABI;
10098 x86_elf_abi = X86_64_X32_ABI;
10100 else if (!strcmp (default_arch, "i386"))
10101 update_code_flag (CODE_32BIT, 1);
10103 as_fatal (_("unknown architecture"));
10105 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10106 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10107 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10108 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10110 switch (OUTPUT_FLAVOR)
10112 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
10113 case bfd_target_aout_flavour:
10114 return AOUT_TARGET_FORMAT;
10116 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10117 # if defined (TE_PE) || defined (TE_PEP)
10118 case bfd_target_coff_flavour:
10119 if (flag_code == CODE_64BIT)
10120 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10123 # elif defined (TE_GO32)
10124 case bfd_target_coff_flavour:
10125 return "coff-go32";
10127 case bfd_target_coff_flavour:
10128 return "coff-i386";
10131 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10132 case bfd_target_elf_flavour:
10134 const char *format;
10136 switch (x86_elf_abi)
10139 format = ELF_TARGET_FORMAT;
10142 use_rela_relocations = 1;
10144 format = ELF_TARGET_FORMAT64;
10146 case X86_64_X32_ABI:
10147 use_rela_relocations = 1;
10149 disallow_64bit_reloc = 1;
10150 format = ELF_TARGET_FORMAT32;
10153 if (cpu_arch_isa == PROCESSOR_L1OM)
10155 if (x86_elf_abi != X86_64_ABI)
10156 as_fatal (_("Intel L1OM is 64bit only"));
10157 return ELF_TARGET_L1OM_FORMAT;
10159 if (cpu_arch_isa == PROCESSOR_K1OM)
10161 if (x86_elf_abi != X86_64_ABI)
10162 as_fatal (_("Intel K1OM is 64bit only"));
10163 return ELF_TARGET_K1OM_FORMAT;
10169 #if defined (OBJ_MACH_O)
10170 case bfd_target_mach_o_flavour:
10171 if (flag_code == CODE_64BIT)
10173 use_rela_relocations = 1;
10175 return "mach-o-x86-64";
10178 return "mach-o-i386";
10186 #endif /* OBJ_MAYBE_ more than one */
10188 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10190 i386_elf_emit_arch_note (void)
10192 if (IS_ELF && cpu_arch_name != NULL)
10195 asection *seg = now_seg;
10196 subsegT subseg = now_subseg;
10197 Elf_Internal_Note i_note;
10198 Elf_External_Note e_note;
10199 asection *note_secp;
10202 /* Create the .note section. */
10203 note_secp = subseg_new (".note", 0);
10204 bfd_set_section_flags (stdoutput,
10206 SEC_HAS_CONTENTS | SEC_READONLY);
10208 /* Process the arch string. */
10209 len = strlen (cpu_arch_name);
10211 i_note.namesz = len + 1;
10213 i_note.type = NT_ARCH;
10214 p = frag_more (sizeof (e_note.namesz));
10215 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10216 p = frag_more (sizeof (e_note.descsz));
10217 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10218 p = frag_more (sizeof (e_note.type));
10219 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10220 p = frag_more (len + 1);
10221 strcpy (p, cpu_arch_name);
10223 frag_align (2, 0, 0);
10225 subseg_set (seg, subseg);
10231 md_undefined_symbol (char *name)
10233 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10234 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10235 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10236 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10240 if (symbol_find (name))
10241 as_bad (_("GOT already in symbol table"));
10242 GOT_symbol = symbol_new (name, undefined_section,
10243 (valueT) 0, &zero_address_frag);
10250 /* Round up a section size to the appropriate boundary. */
10253 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10255 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10256 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10258 /* For a.out, force the section size to be aligned. If we don't do
10259 this, BFD will align it for us, but it will not write out the
10260 final bytes of the section. This may be a bug in BFD, but it is
10261 easier to fix it here since that is how the other a.out targets
10265 align = bfd_get_section_alignment (stdoutput, segment);
10266 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10273 /* On the i386, PC-relative offsets are relative to the start of the
10274 next instruction. That is, the address of the offset, plus its
10275 size, since the offset is always the last part of the insn. */
10278 md_pcrel_from (fixS *fixP)
10280 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10286 s_bss (int ignore ATTRIBUTE_UNUSED)
10290 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10292 obj_elf_section_change_hook ();
10294 temp = get_absolute_expression ();
10295 subseg_set (bss_section, (subsegT) temp);
10296 demand_empty_rest_of_line ();
10302 i386_validate_fix (fixS *fixp)
10304 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10306 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10310 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10315 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10317 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10319 fixp->fx_subsy = 0;
10324 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10327 bfd_reloc_code_real_type code;
10329 switch (fixp->fx_r_type)
10331 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10332 case BFD_RELOC_SIZE32:
10333 case BFD_RELOC_SIZE64:
10334 if (S_IS_DEFINED (fixp->fx_addsy)
10335 && !S_IS_EXTERNAL (fixp->fx_addsy))
10337 /* Resolve size relocation against local symbol to size of
10338 the symbol plus addend. */
10339 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10340 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10341 && !fits_in_unsigned_long (value))
10342 as_bad_where (fixp->fx_file, fixp->fx_line,
10343 _("symbol size computation overflow"));
10344 fixp->fx_addsy = NULL;
10345 fixp->fx_subsy = NULL;
10346 md_apply_fix (fixp, (valueT *) &value, NULL);
10351 case BFD_RELOC_X86_64_PLT32:
10352 case BFD_RELOC_X86_64_PLT32_BND:
10353 case BFD_RELOC_X86_64_GOT32:
10354 case BFD_RELOC_X86_64_GOTPCREL:
10355 case BFD_RELOC_386_PLT32:
10356 case BFD_RELOC_386_GOT32:
10357 case BFD_RELOC_386_GOTOFF:
10358 case BFD_RELOC_386_GOTPC:
10359 case BFD_RELOC_386_TLS_GD:
10360 case BFD_RELOC_386_TLS_LDM:
10361 case BFD_RELOC_386_TLS_LDO_32:
10362 case BFD_RELOC_386_TLS_IE_32:
10363 case BFD_RELOC_386_TLS_IE:
10364 case BFD_RELOC_386_TLS_GOTIE:
10365 case BFD_RELOC_386_TLS_LE_32:
10366 case BFD_RELOC_386_TLS_LE:
10367 case BFD_RELOC_386_TLS_GOTDESC:
10368 case BFD_RELOC_386_TLS_DESC_CALL:
10369 case BFD_RELOC_X86_64_TLSGD:
10370 case BFD_RELOC_X86_64_TLSLD:
10371 case BFD_RELOC_X86_64_DTPOFF32:
10372 case BFD_RELOC_X86_64_DTPOFF64:
10373 case BFD_RELOC_X86_64_GOTTPOFF:
10374 case BFD_RELOC_X86_64_TPOFF32:
10375 case BFD_RELOC_X86_64_TPOFF64:
10376 case BFD_RELOC_X86_64_GOTOFF64:
10377 case BFD_RELOC_X86_64_GOTPC32:
10378 case BFD_RELOC_X86_64_GOT64:
10379 case BFD_RELOC_X86_64_GOTPCREL64:
10380 case BFD_RELOC_X86_64_GOTPC64:
10381 case BFD_RELOC_X86_64_GOTPLT64:
10382 case BFD_RELOC_X86_64_PLTOFF64:
10383 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10384 case BFD_RELOC_X86_64_TLSDESC_CALL:
10385 case BFD_RELOC_RVA:
10386 case BFD_RELOC_VTABLE_ENTRY:
10387 case BFD_RELOC_VTABLE_INHERIT:
10389 case BFD_RELOC_32_SECREL:
10391 code = fixp->fx_r_type;
10393 case BFD_RELOC_X86_64_32S:
10394 if (!fixp->fx_pcrel)
10396 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10397 code = fixp->fx_r_type;
10401 if (fixp->fx_pcrel)
10403 switch (fixp->fx_size)
10406 as_bad_where (fixp->fx_file, fixp->fx_line,
10407 _("can not do %d byte pc-relative relocation"),
10409 code = BFD_RELOC_32_PCREL;
10411 case 1: code = BFD_RELOC_8_PCREL; break;
10412 case 2: code = BFD_RELOC_16_PCREL; break;
10414 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10415 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10418 case 8: code = BFD_RELOC_64_PCREL; break;
10424 switch (fixp->fx_size)
10427 as_bad_where (fixp->fx_file, fixp->fx_line,
10428 _("can not do %d byte relocation"),
10430 code = BFD_RELOC_32;
10432 case 1: code = BFD_RELOC_8; break;
10433 case 2: code = BFD_RELOC_16; break;
10434 case 4: code = BFD_RELOC_32; break;
10436 case 8: code = BFD_RELOC_64; break;
10443 if ((code == BFD_RELOC_32
10444 || code == BFD_RELOC_32_PCREL
10445 || code == BFD_RELOC_X86_64_32S)
10447 && fixp->fx_addsy == GOT_symbol)
10450 code = BFD_RELOC_386_GOTPC;
10452 code = BFD_RELOC_X86_64_GOTPC32;
10454 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10456 && fixp->fx_addsy == GOT_symbol)
10458 code = BFD_RELOC_X86_64_GOTPC64;
10461 rel = (arelent *) xmalloc (sizeof (arelent));
10462 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10463 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10465 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10467 if (!use_rela_relocations)
10469 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10470 vtable entry to be used in the relocation's section offset. */
10471 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10472 rel->address = fixp->fx_offset;
10473 #if defined (OBJ_COFF) && defined (TE_PE)
10474 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10475 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10480 /* Use the rela in 64bit mode. */
10483 if (disallow_64bit_reloc)
10486 case BFD_RELOC_X86_64_DTPOFF64:
10487 case BFD_RELOC_X86_64_TPOFF64:
10488 case BFD_RELOC_64_PCREL:
10489 case BFD_RELOC_X86_64_GOTOFF64:
10490 case BFD_RELOC_X86_64_GOT64:
10491 case BFD_RELOC_X86_64_GOTPCREL64:
10492 case BFD_RELOC_X86_64_GOTPC64:
10493 case BFD_RELOC_X86_64_GOTPLT64:
10494 case BFD_RELOC_X86_64_PLTOFF64:
10495 as_bad_where (fixp->fx_file, fixp->fx_line,
10496 _("cannot represent relocation type %s in x32 mode"),
10497 bfd_get_reloc_code_name (code));
10503 if (!fixp->fx_pcrel)
10504 rel->addend = fixp->fx_offset;
10508 case BFD_RELOC_X86_64_PLT32:
10509 case BFD_RELOC_X86_64_PLT32_BND:
10510 case BFD_RELOC_X86_64_GOT32:
10511 case BFD_RELOC_X86_64_GOTPCREL:
10512 case BFD_RELOC_X86_64_TLSGD:
10513 case BFD_RELOC_X86_64_TLSLD:
10514 case BFD_RELOC_X86_64_GOTTPOFF:
10515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10516 case BFD_RELOC_X86_64_TLSDESC_CALL:
10517 rel->addend = fixp->fx_offset - fixp->fx_size;
10520 rel->addend = (section->vma
10522 + fixp->fx_addnumber
10523 + md_pcrel_from (fixp));
10528 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10529 if (rel->howto == NULL)
10531 as_bad_where (fixp->fx_file, fixp->fx_line,
10532 _("cannot represent relocation type %s"),
10533 bfd_get_reloc_code_name (code));
10534 /* Set howto to a garbage value so that we can keep going. */
10535 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10536 gas_assert (rel->howto != NULL);
10542 #include "tc-i386-intel.c"
10545 tc_x86_parse_to_dw2regnum (expressionS *exp)
10547 int saved_naked_reg;
10548 char saved_register_dot;
10550 saved_naked_reg = allow_naked_reg;
10551 allow_naked_reg = 1;
10552 saved_register_dot = register_chars['.'];
10553 register_chars['.'] = '.';
10554 allow_pseudo_reg = 1;
10555 expression_and_evaluate (exp);
10556 allow_pseudo_reg = 0;
10557 register_chars['.'] = saved_register_dot;
10558 allow_naked_reg = saved_naked_reg;
10560 if (exp->X_op == O_register && exp->X_add_number >= 0)
10562 if ((addressT) exp->X_add_number < i386_regtab_size)
10564 exp->X_op = O_constant;
10565 exp->X_add_number = i386_regtab[exp->X_add_number]
10566 .dw2_regnum[flag_code >> 1];
10569 exp->X_op = O_illegal;
10574 tc_x86_frame_initial_instructions (void)
10576 static unsigned int sp_regno[2];
10578 if (!sp_regno[flag_code >> 1])
10580 char *saved_input = input_line_pointer;
10581 char sp[][4] = {"esp", "rsp"};
10584 input_line_pointer = sp[flag_code >> 1];
10585 tc_x86_parse_to_dw2regnum (&exp);
10586 gas_assert (exp.X_op == O_constant);
10587 sp_regno[flag_code >> 1] = exp.X_add_number;
10588 input_line_pointer = saved_input;
10591 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10592 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10596 x86_dwarf2_addr_size (void)
10598 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10599 if (x86_elf_abi == X86_64_X32_ABI)
10602 return bfd_arch_bits_per_address (stdoutput) / 8;
10606 i386_elf_section_type (const char *str, size_t len)
10608 if (flag_code == CODE_64BIT
10609 && len == sizeof ("unwind") - 1
10610 && strncmp (str, "unwind", 6) == 0)
10611 return SHT_X86_64_UNWIND;
10618 i386_solaris_fix_up_eh_frame (segT sec)
10620 if (flag_code == CODE_64BIT)
10621 elf_section_type (sec) = SHT_X86_64_UNWIND;
10627 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10631 exp.X_op = O_secrel;
10632 exp.X_add_symbol = symbol;
10633 exp.X_add_number = 0;
10634 emit_expr (&exp, size);
10638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10639 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10642 x86_64_section_letter (int letter, char **ptr_msg)
10644 if (flag_code == CODE_64BIT)
10647 return SHF_X86_64_LARGE;
10649 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10652 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10657 x86_64_section_word (char *str, size_t len)
10659 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10660 return SHF_X86_64_LARGE;
10666 handle_large_common (int small ATTRIBUTE_UNUSED)
10668 if (flag_code != CODE_64BIT)
10670 s_comm_internal (0, elf_common_parse);
10671 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10675 static segT lbss_section;
10676 asection *saved_com_section_ptr = elf_com_section_ptr;
10677 asection *saved_bss_section = bss_section;
10679 if (lbss_section == NULL)
10681 flagword applicable;
10682 segT seg = now_seg;
10683 subsegT subseg = now_subseg;
10685 /* The .lbss section is for local .largecomm symbols. */
10686 lbss_section = subseg_new (".lbss", 0);
10687 applicable = bfd_applicable_section_flags (stdoutput);
10688 bfd_set_section_flags (stdoutput, lbss_section,
10689 applicable & SEC_ALLOC);
10690 seg_info (lbss_section)->bss = 1;
10692 subseg_set (seg, subseg);
10695 elf_com_section_ptr = &_bfd_elf_large_com_section;
10696 bss_section = lbss_section;
10698 s_comm_internal (0, elf_common_parse);
10700 elf_com_section_ptr = saved_com_section_ptr;
10701 bss_section = saved_bss_section;
10704 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */