1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
3 Copyright (C) 1997 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d30v.h"
28 const char comment_chars[] = ";";
29 const char line_comment_chars[] = "#";
30 const char line_separator_chars[] = "";
31 const char *md_shortopts = "OnN";
32 const char EXP_CHARS[] = "eE";
33 const char FLT_CHARS[] = "dD";
35 #define NOP_MULTIPLY 1
37 static int warn_nops = 0;
38 static int Optimizing = 0;
44 typedef enum _exec_type
46 EXEC_UNKNOWN, /* no order specified */
47 EXEC_PARALLEL, /* done in parallel */
48 EXEC_SEQ, /* sequential */
49 EXEC_REVSEQ /* reverse sequential */
53 #define MAX_INSN_FIXUPS (5)
60 bfd_reloc_code_real_type reloc;
63 typedef struct _fixups
66 struct d30v_fixup fix[MAX_INSN_FIXUPS];
70 static Fixups FixUps[2];
71 static Fixups *fixups;
73 /* Whether current and previous instruction is a word multiply. */
78 #define NOP_LEFT ((long long)NOP << 32)
79 #define NOP_RIGHT ((long long)NOP)
80 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
83 static int reg_name_search PARAMS ((char *name));
84 static int register_name PARAMS ((expressionS *expressionP));
85 static int check_range PARAMS ((unsigned long num, int bits, int flags));
86 static int postfix PARAMS ((char *p));
87 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d30v_operand *op, int rel_flag));
88 static int get_operands PARAMS ((expressionS exp[], int cmp_hack));
89 static struct d30v_format *find_format PARAMS ((struct d30v_opcode *opcode,
90 expressionS ops[],int fsize, int cmp_hack));
91 static long long build_insn PARAMS ((struct d30v_insn *opcode, expressionS *opers));
92 static void write_long PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx));
93 static void write_1_short PARAMS ((struct d30v_insn *opcode, long long insn, Fixups *fx));
94 static int write_2_short PARAMS ((struct d30v_insn *opcode1, long long insn1,
95 struct d30v_insn *opcode2, long long insn2, exec_type_enum exec_type, Fixups *fx));
96 static long long do_assemble PARAMS ((char *str, struct d30v_insn *opcode));
97 static int parallel_ok PARAMS ((struct d30v_insn *opcode1, unsigned long insn1,
98 struct d30v_insn *opcode2, unsigned long insn2,
99 exec_type_enum exec_type));
100 static void d30v_number_to_chars PARAMS ((char *buf, long long value, int nbytes));
101 static void check_size PARAMS ((long value, int bits, char *file, int line));
103 struct option md_longopts[] = {
104 {NULL, no_argument, NULL, 0}
106 size_t md_longopts_size = sizeof(md_longopts);
109 /* The target specific pseudo-ops which we support. */
110 const pseudo_typeS md_pseudo_table[] =
113 { "hword", cons, 2 },
117 /* Opcode hash table. */
118 static struct hash_control *d30v_hash;
120 /* reg_name_search does a binary search of the pre_defined_registers
121 array to see if "name" is a valid regiter name. Returns the register
122 number from the array on success, or -1 on failure. */
125 reg_name_search (name)
128 int middle, low, high;
132 high = reg_name_cnt() - 1;
136 middle = (low + high) / 2;
137 cmp = strcasecmp (name, pre_defined_registers[middle].name);
143 return pre_defined_registers[middle].value;
149 /* register_name() checks the string at input_line_pointer
150 to see if it is a valid register name */
153 register_name (expressionP)
154 expressionS *expressionP;
157 char c, *p = input_line_pointer;
159 while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
166 /* look to see if it's in the register table */
167 reg_number = reg_name_search (input_line_pointer);
170 expressionP->X_op = O_register;
171 /* temporarily store a pointer to the string here */
172 expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
173 expressionP->X_add_number = reg_number;
174 input_line_pointer = p;
184 check_range (num, bits, flags)
192 /* don't bother checking 32-bit values */
196 if (flags & OPERAND_SIGNED)
198 max = (1 << (bits - 1))-1;
199 min = - (1 << (bits - 1));
200 if (((long)num > max) || ((long)num < min))
205 max = (1 << bits) - 1;
207 if ((num > max) || (num < min))
215 md_show_usage (stream)
218 fprintf(stream, "\nD30V options:\n\
219 -O Make adjacent short instructions parallel if possible.\n\
220 -n Warn about all NOPs inserted by the assembler.\n\
221 -N Warn about NOPs inserted after word multiplies.\n");
225 md_parse_option (c, arg)
231 /* Optimize. Will attempt to parallelize operations */
236 /* Warn about all NOPS that the assembler inserts. */
241 /* Warn about the NOPS that the assembler inserts because of the
244 warn_nops = NOP_MULTIPLY;
254 md_undefined_symbol (name)
260 /* Turn a string in input_line_pointer into a floating point constant of type
261 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
262 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
265 md_atof (type, litP, sizeP)
271 LITTLENUM_TYPE words[4];
285 return "bad call to md_atof";
288 t = atof_ieee (input_line_pointer, type, words);
290 input_line_pointer = t;
294 for (i = 0; i < prec; i++)
296 md_number_to_chars (litP, (valueT) words[i], 2);
303 md_convert_frag (abfd, sec, fragP)
312 md_section_align (seg, addr)
316 int align = bfd_get_section_alignment (stdoutput, seg);
317 return ((addr + (1 << align) - 1) & (-1 << align));
324 struct d30v_opcode *opcode;
325 d30v_hash = hash_new();
327 /* Insert opcode names into a hash table. */
328 for (opcode = (struct d30v_opcode *)d30v_opcode_table; opcode->name; opcode++)
329 hash_insert (d30v_hash, opcode->name, (char *) opcode);
332 FixUps[0].next = &FixUps[1];
333 FixUps[1].next = &FixUps[0];
337 /* this function removes the postincrement or postdecrement
338 operator ( '+' or '-' ) from an expression */
340 static int postfix (p)
343 while (*p != '-' && *p != '+')
345 if (*p==0 || *p=='\n' || *p=='\r' || *p==' ' || *p==',')
365 static bfd_reloc_code_real_type
366 get_reloc (op, rel_flag)
367 struct d30v_operand *op;
373 if (op->flags & OPERAND_SHIFT)
374 return BFD_RELOC_D30V_9_PCREL;
376 return BFD_RELOC_D30V_6;
379 if (!(op->flags & OPERAND_SHIFT))
380 as_warn("unexpected 12-bit reloc type");
381 if (rel_flag == RELOC_PCREL)
382 return BFD_RELOC_D30V_15_PCREL;
384 return BFD_RELOC_D30V_15;
386 if (!(op->flags & OPERAND_SHIFT))
387 as_warn("unexpected 18-bit reloc type");
388 if (rel_flag == RELOC_PCREL)
389 return BFD_RELOC_D30V_21_PCREL;
391 return BFD_RELOC_D30V_21;
393 if (rel_flag == RELOC_PCREL)
394 return BFD_RELOC_D30V_32_PCREL;
396 return BFD_RELOC_D30V_32;
402 /* get_operands parses a string of operands and returns
403 an array of expressions */
406 get_operands (exp, cmp_hack)
410 char *p = input_line_pointer;
416 exp[numops].X_op = O_absent;
417 exp[numops++].X_add_number = cmp_hack - 1;
422 while (*p == ' ' || *p == '\t' || *p == ',')
424 if (*p==0 || *p=='\n' || *p=='\r')
430 exp[numops].X_op = O_absent;
434 exp[numops].X_add_number = OPERAND_ATPAR;
440 exp[numops].X_add_number = OPERAND_ATMINUS;
444 exp[numops].X_add_number = OPERAND_ATSIGN;
453 /* just skip the trailing paren */
458 input_line_pointer = p;
460 /* check to see if it might be a register name */
461 if (!register_name (&exp[numops]))
463 /* parse as an expression */
464 expression (&exp[numops]);
467 if (exp[numops].X_op == O_illegal)
468 as_bad ("illegal operand");
469 else if (exp[numops].X_op == O_absent)
470 as_bad ("missing operand");
473 p = input_line_pointer;
477 case -1: /* postdecrement mode */
478 exp[numops].X_op = O_absent;
479 exp[numops++].X_add_number = OPERAND_MINUS;
481 case 1: /* postincrement mode */
482 exp[numops].X_op = O_absent;
483 exp[numops++].X_add_number = OPERAND_PLUS;
489 exp[numops].X_op = 0;
493 /* build_insn generates the instruction. It does everything */
494 /* but write the FM bits. */
497 build_insn (opcode, opers)
498 struct d30v_insn *opcode;
501 int i, length, bits, shift, flags;
502 unsigned int number, id=0;
504 struct d30v_opcode *op = opcode->op;
505 struct d30v_format *form = opcode->form;
507 insn = opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
509 for (i=0; form->operands[i]; i++)
511 flags = d30v_operand_table[form->operands[i]].flags;
513 /* must be a register or number */
514 if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM) &&
515 !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
518 bits = d30v_operand_table[form->operands[i]].bits;
519 if (flags & OPERAND_SHIFT)
522 length = d30v_operand_table[form->operands[i]].length;
523 shift = 12 - d30v_operand_table[form->operands[i]].position;
524 if (opers[i].X_op != O_symbol)
525 number = opers[i].X_add_number;
528 if (flags & OPERAND_REG)
530 /* check for mvfsys or mvtsys control registers */
531 if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
534 id = (number & 0x7f) - MAX_CONTROL_REG;
537 else if (number & OPERAND_FLAG)
539 id = 3; /* number is a flag register */
543 else if (flags & OPERAND_SPECIAL)
548 if (opers[i].X_op != O_register && opers[i].X_op != O_constant && !(flags & OPERAND_NAME))
550 /* now create a fixup */
552 if (fixups->fc >= MAX_INSN_FIXUPS)
553 as_fatal ("too many fixups");
555 fixups->fix[fixups->fc].reloc =
556 get_reloc((struct d30v_operand *)&d30v_operand_table[form->operands[i]], op->reloc_flag);
557 fixups->fix[fixups->fc].size = 4;
558 fixups->fix[fixups->fc].exp = opers[i];
559 fixups->fix[fixups->fc].operand = form->operands[i];
560 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
561 fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
563 fixups->fix[fixups->fc].pcrel = op->reloc_flag;
567 /* truncate to the proper number of bits */
568 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
569 as_bad("operand out of range: %d",number);
571 number &= 0x7FFFFFFF >> (31 - bits);
572 if (flags & OPERAND_SHIFT)
576 /* it's a LONG instruction */
577 insn |= (number >> 26); /* top 6 bits */
578 insn <<= 32; /* shift the first word over */
579 insn |= ((number & 0x03FC0000) << 2); /* next 8 bits */
580 insn |= number & 0x0003FFFF; /* bottom 18 bits */
583 insn |= number << shift;
589 /* write out a long form instruction */
591 write_long (opcode, insn, fx)
592 struct d30v_insn *opcode;
597 char *f = frag_more(8);
600 d30v_number_to_chars (f, insn, 8);
602 for (i=0; i < fx->fc; i++)
604 if (fx->fix[i].reloc)
606 where = f - frag_now->fr_literal;
607 fix_new_exp (frag_now,
619 /* write out a short form instruction by itself */
621 write_1_short (opcode, insn, fx)
622 struct d30v_insn *opcode;
626 char *f = frag_more(8);
629 if (warn_nops == NOP_ALL)
630 as_warn ("NOP inserted");
632 /* the other container needs to be NOP */
633 /* according to 4.3.1: for FM=00, sub-instructions performed only
634 by IU cannot be encoded in L-container. */
635 if (opcode->op->unit == IU)
636 insn |= FM00 | NOP_LEFT; /* right container */
638 insn = FM00 | (insn << 32) | NOP_RIGHT; /* left container */
640 d30v_number_to_chars (f, insn, 8);
642 for (i=0; i < fx->fc; i++)
644 if (fx->fix[i].reloc)
646 where = f - frag_now->fr_literal;
647 fix_new_exp (frag_now,
658 /* write out a short form instruction if possible */
659 /* return number of instructions not written out */
661 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
662 struct d30v_insn *opcode1, *opcode2;
663 long long insn1, insn2;
664 exec_type_enum exec_type;
667 long long insn = NOP2;
671 if(exec_type != EXEC_PARALLEL && (opcode1->op->flags_used == FLAG_JSR))
673 /* subroutines must be called from 32-bit boundaries */
674 /* so the return address will be correct */
675 write_1_short (opcode1, insn1, fx->next);
681 case EXEC_UNKNOWN: /* order not specified */
682 if (Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
685 exec_type = EXEC_PARALLEL;
686 if (opcode1->op->unit == IU)
687 insn = FM00 | (insn2 << 32) | insn1;
688 else if (opcode2->op->unit == MU)
689 insn = FM00 | (insn2 << 32) | insn1;
692 insn = FM00 | (insn1 << 32) | insn2;
696 else if (opcode1->op->unit == IU)
698 /* reverse sequential */
699 insn = FM10 | (insn2 << 32) | insn1;
700 exec_type = EXEC_REVSEQ;
705 insn = FM01 | (insn1 << 32) | insn2;
707 exec_type = EXEC_SEQ;
711 case EXEC_PARALLEL: /* parallel */
712 if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
713 as_fatal ("Instructions may not be executed in parallel");
714 else if (opcode1->op->unit == IU)
716 if (opcode2->op->unit == IU)
717 as_fatal ("Two IU instructions may not be executed in parallel");
718 as_warn ("Swapping instruction order");
719 insn = FM00 | (insn2 << 32) | insn1;
721 else if (opcode2->op->unit == MU)
723 if (opcode1->op->unit == MU)
724 as_fatal ("Two MU instructions may not be executed in parallel");
725 as_warn ("Swapping instruction order");
726 insn = FM00 | (insn2 << 32) | insn1;
730 insn = FM00 | (insn1 << 32) | insn2;
735 case EXEC_SEQ: /* sequential */
736 if (opcode1->op->unit == IU)
737 as_fatal ("IU instruction may not be in the left container");
738 insn = FM01 | (insn1 << 32) | insn2;
742 case EXEC_REVSEQ: /* reverse sequential */
743 if (opcode2->op->unit == MU)
744 as_fatal ("MU instruction may not be in the right container");
745 insn = FM10 | (insn1 << 32) | insn2;
750 as_fatal("unknown execution type passed to write_2_short()");
753 /* printf("writing out %llx\n",insn); */
755 d30v_number_to_chars (f, insn, 8);
757 /* If the previous instruction was a 32-bit multiply but it is put into a
758 parallel container, mark the current instruction as being a 32-bit
760 if (prev_mul32_p && exec_type == EXEC_PARALLEL)
765 for (i=0; i < fx->fc; i++)
767 if (fx->fix[i].reloc)
769 where = (f - frag_now->fr_literal) + 4*j;
771 fix_new_exp (frag_now,
786 /* Check 2 instructions and determine if they can be safely */
787 /* executed in parallel. Returns 1 if they can be. */
789 parallel_ok (op1, insn1, op2, insn2, exec_type)
790 struct d30v_insn *op1, *op2;
791 unsigned long insn1, insn2;
792 exec_type_enum exec_type;
794 int i, j, shift, regno, bits, ecc;
795 unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
796 unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
797 struct d30v_format *f;
798 struct d30v_opcode *op;
800 /* section 4.3: both instructions must not be IU or MU only */
801 if ((op1->op->unit == IU && op2->op->unit == IU)
802 || (op1->op->unit == MU && op2->op->unit == MU))
805 /* first instruction must not be a jump to safely optimize, unless this
806 is an explicit parallel operation. */
807 if (exec_type != EXEC_PARALLEL
808 && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
811 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
812 then it is safe to allow the two to be done as parallel ops, since only
813 one will ever be executed at a time. */
814 if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
815 || (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
816 || (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
817 || (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
822 [2] a0, a1, flag registers */
824 for (j = 0; j < 2; j++)
841 mod_reg[j][0] = mod_reg[j][1] = 0;
842 mod_reg[j][2] = (op->flags_set & FLAG_ALL);
843 used_reg[j][0] = used_reg[j][1] = 0;
844 used_reg[j][2] = (op->flags_used & FLAG_ALL);
846 /* BSR/JSR always sets R62 */
847 if (op->flags_used & FLAG_JSR)
848 mod_reg[j][1] = (1L << (62-32));
850 /* conditional execution affects the flags_used */
855 used_reg[j][2] |= flag_reg[j] = FLAG_0;
860 used_reg[j][2] |= flag_reg[j] = FLAG_1;
865 used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
869 for (i = 0; f->operands[i]; i++)
871 flags = d30v_operand_table[f->operands[i]].flags;
872 shift = 12 - d30v_operand_table[f->operands[i]].position;
873 bits = d30v_operand_table[f->operands[i]].bits;
877 mask = 0x7FFFFFFF >> (31 - bits);
879 if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
881 /* this is a post-increment or post-decrement */
882 /* the previous register needs to be marked as modified */
884 shift = 12 - d30v_operand_table[f->operands[i-1]].position;
885 regno = (ins >> shift) & 0x3f;
887 mod_reg[j][1] |= 1L << (regno - 32);
889 mod_reg[j][0] |= 1L << regno;
891 else if (flags & OPERAND_REG)
893 regno = (ins >> shift) & mask;
894 /* the memory write functions don't have a destination register */
895 if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
897 /* MODIFIED registers and flags */
898 if (flags & OPERAND_ACC)
901 mod_reg[j][2] |= FLAG_A0;
903 mod_reg[j][2] |= FLAG_A1;
907 else if (flags & OPERAND_FLAG)
908 mod_reg[j][2] |= 1L << regno;
909 else if (!(flags & OPERAND_CONTROL))
913 /* need to check if there are two destination */
914 /* registers, for example ld2w */
915 if (flags & OPERAND_2REG)
920 for (r = regno; r <= regno + z; r++)
923 mod_reg[j][1] |= 1L << (r - 32);
925 mod_reg[j][0] |= 1L << r;
931 /* USED, but not modified registers and flags */
932 if (flags & OPERAND_ACC)
935 used_reg[j][2] |= FLAG_A0;
937 used_reg[j][2] |= FLAG_A1;
941 else if (flags & OPERAND_FLAG)
942 used_reg[j][2] |= 1L << regno;
943 else if (!(flags & OPERAND_CONTROL))
947 /* need to check if there are two source */
948 /* registers, for example st2w */
949 if (flags & OPERAND_2REG)
954 for (r = regno; r <= regno + z; r++)
957 used_reg[j][1] |= 1L << (r - 32);
959 used_reg[j][0] |= 1L << r;
967 flags_set1 = op1->op->flags_set;
968 flags_set2 = op2->op->flags_set;
969 flags_used1 = op1->op->flags_used;
970 flags_used2 = op2->op->flags_used;
972 /* ST2W/ST4HB combined with ADDppp/SUBppp is illegal. */
973 if (((flags_set1 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD)
974 && (flags_used2 & FLAG_ADDSUBppp) != 0)
975 || ((flags_set2 & (FLAG_MEM | FLAG_2WORD)) == (FLAG_MEM | FLAG_2WORD)
976 && (flags_used1 & FLAG_ADDSUBppp) != 0))
979 /* Load instruction combined with half-word multiply is illegal. */
980 if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
981 || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
984 /* Specifically allow add || add by removing carry, overflow bits dependency.
985 This is safe, even if an addc follows since the IU takes the argument in
986 the right container, and it writes its results last.
987 However, don't paralellize add followed by addc or sub followed by
990 if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
991 && (used_reg[0][2] & ~flag_reg[0]) == 0
992 && (used_reg[1][2] & ~flag_reg[1]) == 0
993 && op1->op->unit == EITHER && op2->op->unit == EITHER)
995 mod_reg[0][2] = mod_reg[1][2] = 0;
998 for(j = 0; j < 3; j++)
1000 /* If the second instruction depends on the first, we obviously
1001 cannot parallelize. Note, the mod flag implies use, so
1002 check that as well. */
1003 if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
1012 /* This is the main entry point for the machine-dependent assembler. str points to a
1013 machine-dependent instruction. This function is supposed to emit the frags/bytes
1014 it assembles to. For the D30V, it mostly handles the special VLIW parsing and packing
1015 and leaves the difficult stuff to do_assemble(). */
1017 static long long prev_insn = -1;
1018 static struct d30v_insn prev_opcode;
1019 static subsegT prev_subseg;
1020 static segT prev_seg = 0;
1026 struct d30v_insn opcode;
1028 exec_type_enum extype = EXEC_UNKNOWN; /* execution type; parallel, etc */
1029 static exec_type_enum etype = EXEC_UNKNOWN; /* saved extype. used for multiline instructions */
1032 if ( (prev_insn != -1) && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1035 if (etype == EXEC_UNKNOWN)
1037 /* look for the special multiple instruction separators */
1038 str2 = strstr (str, "||");
1040 extype = EXEC_PARALLEL;
1043 str2 = strstr (str, "->");
1048 str2 = strstr (str, "<-");
1050 extype = EXEC_REVSEQ;
1053 /* str2 points to the separator, if one */
1058 /* if two instructions are present and we already have one saved
1059 then first write it out */
1062 /* assemble first instruction and save it */
1063 prev_insn = do_assemble (str, &prev_opcode);
1064 if (prev_insn == -1)
1065 as_fatal ("cannot assemble instruction ");
1066 if (prev_opcode.form->form >= LONG)
1067 as_fatal ("First opcode is long. Unable to mix instructions as specified.");
1068 fixups = fixups->next;
1073 insn = do_assemble (str, &opcode);
1081 as_fatal ("cannot assemble instruction ");
1090 /* Word multiply instructions must not be followed by either a load or a
1091 16-bit multiply instruction in the next cycle. */
1092 if (prev_mul32_p && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1094 /* However, load and multiply should able to be combined in a parallel
1095 operation, so check for that first. */
1098 && (opcode.op->flags_used & FLAG_MEM)
1099 && opcode.form->form < LONG
1100 && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
1101 && parallel_ok (&prev_opcode, (long)prev_insn,
1102 &opcode, (long)insn, extype)
1103 && write_2_short (&prev_opcode, (long)prev_insn,
1104 &opcode, (long)insn, extype, fixups) == 0)
1106 /* no instructions saved */
1111 /* Can't parallelize, flush current instruction and emit a word of NOPS */
1118 d30v_number_to_chars (f, NOP2, 8);
1119 if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
1120 as_warn ("word of NOPs added between word multiply and %s",
1121 ((opcode.op->flags_used & FLAG_MEM)
1123 : "16-bit multiply"));
1127 /* if this is a long instruction, write it and any previous short instruction */
1128 if (opcode.form->form >= LONG)
1131 as_fatal("Unable to mix instructions as specified");
1133 write_long (&opcode, insn, fixups);
1138 if ((prev_insn != -1) &&
1139 (write_2_short (&prev_opcode, (long)prev_insn, &opcode, (long)insn, extype, fixups) == 0))
1141 /* no instructions saved */
1148 as_fatal("Unable to mix instructions as specified");
1149 /* save off last instruction so it may be packed on next pass */
1150 memcpy(&prev_opcode, &opcode, sizeof(prev_opcode));
1153 prev_subseg = now_subseg;
1154 fixups = fixups->next;
1159 /* do_assemble assembles a single instruction and returns an opcode */
1160 /* it returns -1 (an invalid opcode) on error */
1163 do_assemble (str, opcode)
1165 struct d30v_insn *opcode;
1167 unsigned char *op_start, *save;
1168 unsigned char *op_end;
1170 int cmp_hack, nlen = 0, fsize = 0;
1171 expressionS myops[6];
1174 /* Drop leading whitespace */
1178 /* find the opcode end */
1179 for (op_start = op_end = (unsigned char *) (str);
1183 && !is_end_of_line[*op_end] && *op_end != ' ';
1186 name[nlen] = tolower(op_start[nlen]);
1195 /* if there is an execution condition code, handle it */
1199 while ( (i < ECC_MAX) && strncasecmp(d30v_ecc_names[i],op_end+1,2))
1205 strncpy(tmp,op_end+1,2);
1207 as_fatal ("unknown condition code: %s",tmp);
1210 /* printf("condition code=%d\n",i); */
1215 opcode->ecc = ECC_AL;
1218 /* CMP and CMPU change their name based on condition codes */
1219 if (!strncmp(name,"cmp",3))
1222 char **str = (char **)d30v_cc_names;
1228 for(i=1; *str && strncmp(*str,&name[p],2); i++, str++)
1231 /* cmpu only supports some condition codes */
1237 as_fatal ("cmpu doesn't support condition code %s",&name[p]);
1244 as_fatal ("unknown condition code: %s",&name[p]);
1253 /* printf("cmp_hack=%d\n",cmp_hack); */
1255 /* need to look for .s or .l */
1256 if (name[nlen-2] == '.')
1258 switch (name[nlen-1])
1261 fsize = FORCE_SHORT;
1270 /* find the first opcode with the proper name */
1271 opcode->op = (struct d30v_opcode *)hash_find (d30v_hash, name);
1272 if (opcode->op == NULL)
1273 as_fatal ("unknown opcode: %s",name);
1275 save = input_line_pointer;
1276 input_line_pointer = op_end;
1277 while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
1280 if (strcmp(opcode->op->name,name))
1283 input_line_pointer = save;
1285 insn = build_insn (opcode, myops);
1287 /* Propigate multiply status */
1290 prev_mul32_p = cur_mul32_p;
1291 cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
1298 /* find_format() gets a pointer to an entry in the format table. */
1299 /* It must look at all formats for an opcode and use the operands */
1300 /* to choose the correct one. Returns NULL on error. */
1302 static struct d30v_format *
1303 find_format (opcode, myops, fsize, cmp_hack)
1304 struct d30v_opcode *opcode;
1305 expressionS myops[];
1309 int numops, match, index, i=0, j, k;
1310 struct d30v_format *fm;
1312 /* get all the operands and save them as expressions */
1313 numops = get_operands (myops, cmp_hack);
1315 while ((index = opcode->format[i++]) != 0)
1317 if ((fsize == FORCE_SHORT) && (index >= LONG))
1320 if ((fsize == FORCE_LONG) && (index < LONG))
1323 fm = (struct d30v_format *)&d30v_format_table[index];
1325 while (fm->form == index)
1328 /* now check the operands for compatibility */
1329 for (j = 0; match && fm->operands[j]; j++)
1331 int flags = d30v_operand_table[fm->operands[j]].flags;
1332 int X_op = myops[j].X_op;
1333 int num = myops[j].X_add_number;
1335 if ( flags & OPERAND_SPECIAL )
1339 else if (flags & OPERAND_REG)
1341 if ((X_op != O_register)
1342 || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
1343 || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
1344 || ((flags & OPERAND_CONTROL)
1345 && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
1351 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS)))
1352 || ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS)))
1353 || ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS)))
1354 || ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR)))
1355 || ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
1359 else if (flags & OPERAND_NUM)
1361 /* a number can be a constant or symbol expression */
1362 if (fm->form >= LONG)
1364 /* If we're testing for a LONG format, either fits */
1365 if (X_op != O_constant && X_op != O_symbol)
1368 else if ((fm->form < LONG) && (((fsize == FORCE_SHORT) && (X_op == O_symbol)) ||
1369 (fm->form == SHORT_D2 && j == 0)))
1371 /* This is the tricky part. Will the constant or symbol */
1372 /* fit into the space in the current format? */
1373 else if (X_op == O_constant)
1375 if (check_range (num, d30v_operand_table[fm->operands[j]].bits, flags))
1378 else if (X_op == O_symbol && S_IS_DEFINED(myops[j].X_add_symbol) &&
1379 (S_GET_SEGMENT(myops[j].X_add_symbol) == now_seg) &&
1380 opcode->reloc_flag == RELOC_PCREL)
1382 /* if the symbol is defined, see if the value will fit */
1383 /* into the form we're considering */
1386 /* calculate the current address by running through the previous frags */
1387 /* and adding our current offset */
1388 for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next)
1389 value += f->fr_fix + f->fr_offset;
1390 value = S_GET_VALUE(myops[j].X_add_symbol) - value -
1391 (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal);
1392 if (check_range (value, d30v_operand_table[fm->operands[j]].bits, flags))
1399 /* printf("through the loop: match=%d\n",match); */
1400 /* we're only done if the operands matched so far AND there
1401 are no more to check */
1402 if (match && myops[j].X_op==0)
1405 fm = (struct d30v_format *)&d30v_format_table[++k];
1407 /* printf("trying another format: i=%d\n",i); */
1412 /* if while processing a fixup, a reloc really needs to be created */
1413 /* then it is done here */
1416 tc_gen_reloc (seg, fixp)
1421 reloc = (arelent *) xmalloc (sizeof (arelent));
1422 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1423 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1424 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1425 if (reloc->howto == (reloc_howto_type *) NULL)
1427 as_bad_where (fixp->fx_file, fixp->fx_line,
1428 "reloc %d not supported by object file format", (int)fixp->fx_r_type);
1431 reloc->addend = fixp->fx_addnumber;
1436 md_estimate_size_before_relax (fragp, seg)
1445 md_pcrel_from_section (fixp, sec)
1449 if (fixp->fx_addsy != (symbolS *)NULL && (!S_IS_DEFINED (fixp->fx_addsy) ||
1450 (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1452 return fixp->fx_frag->fr_address + fixp->fx_where;
1456 md_apply_fix3 (fixp, valuep, seg)
1462 unsigned long insn, insn2;
1465 if (fixp->fx_addsy == (symbolS *) NULL)
1470 else if (fixp->fx_pcrel)
1476 value = fixp->fx_offset;
1477 if (fixp->fx_subsy != (symbolS *) NULL)
1479 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1480 value -= S_GET_VALUE (fixp->fx_subsy);
1483 /* We don't actually support subtracting a symbol. */
1484 as_bad_where (fixp->fx_file, fixp->fx_line,
1485 "expression too complex");
1490 /* Fetch the instruction, insert the fully resolved operand
1491 value, and stuff the instruction back again. */
1492 where = fixp->fx_frag->fr_literal + fixp->fx_where;
1493 insn = bfd_getb32 ((unsigned char *) where);
1495 switch (fixp->fx_r_type)
1497 case BFD_RELOC_D30V_6:
1498 check_size (value, 6, fixp->fx_file, fixp->fx_line);
1499 insn |= value & 0x3F;
1500 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1503 case BFD_RELOC_D30V_9_PCREL:
1504 if (fixp->fx_where & 0x7)
1509 fixp->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
1511 check_size (value, 9, fixp->fx_file, fixp->fx_line);
1512 insn |= ((value >> 3) & 0x3F) << 12;
1513 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1516 case BFD_RELOC_D30V_15:
1517 check_size (value, 15, fixp->fx_file, fixp->fx_line);
1518 insn |= (value >> 3) & 0xFFF;
1519 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1522 case BFD_RELOC_D30V_15_PCREL:
1523 if (fixp->fx_where & 0x7)
1528 fixp->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
1530 check_size (value, 15, fixp->fx_file, fixp->fx_line);
1531 insn |= (value >> 3) & 0xFFF;
1532 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1535 case BFD_RELOC_D30V_21:
1536 check_size (value, 21, fixp->fx_file, fixp->fx_line);
1537 insn |= (value >> 3) & 0x3FFFF;
1538 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1541 case BFD_RELOC_D30V_21_PCREL:
1542 if (fixp->fx_where & 0x7)
1547 fixp->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
1549 check_size (value, 21, fixp->fx_file, fixp->fx_line);
1550 insn |= (value >> 3) & 0x3FFFF;
1551 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1554 case BFD_RELOC_D30V_32:
1555 insn2 = bfd_getb32 ((unsigned char *) where + 4);
1556 insn |= (value >> 26) & 0x3F; /* top 6 bits */
1557 insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
1558 insn2 |= value & 0x0003FFFF; /* bottom 18 bits */
1559 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1560 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
1563 case BFD_RELOC_D30V_32_PCREL:
1564 insn2 = bfd_getb32 ((unsigned char *) where + 4);
1565 insn |= (value >> 26) & 0x3F; /* top 6 bits */
1566 insn2 |= ((value & 0x03FC0000) << 2); /* next 8 bits */
1567 insn2 |= value & 0x0003FFFF; /* bottom 18 bits */
1568 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1569 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
1573 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1577 as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type);
1583 /* d30v_cleanup() is called after the assembler has finished parsing the input
1584 file or after a label is defined. Because the D30V assembler sometimes saves short
1585 instructions to see if it can package them with the next instruction, there may
1586 be a short instruction that still needs written. */
1593 if (prev_insn != -1)
1596 subseg = now_subseg;
1597 subseg_set (prev_seg, prev_subseg);
1598 write_1_short (&prev_opcode, (long)prev_insn, fixups->next);
1599 subseg_set (seg, subseg);
1607 d30v_number_to_chars (buf, value, n)
1608 char *buf; /* Return 'nbytes' of chars here. */
1609 long long value; /* The value of the bits. */
1610 int n; /* Number of bytes in the output. */
1614 buf[n] = value & 0xff;
1620 /* This function is called at the start of every line. */
1621 /* it checks to see if the first character is a '.' */
1622 /* which indicates the start of a pseudo-op. If it is, */
1623 /* then write out any unwritten instructions */
1628 char *c = input_line_pointer;
1638 check_size (value, bits, file, line)
1651 max = (1 << (bits - 1)) - 1;
1654 as_bad_where (file, line,"value too large to fit in %d bits",bits);