1 /* tc-d30v.c -- Assembler code for the Mitsubishi D30V
2 Copyright (C) 1997-2018 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to
18 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
19 Boston, MA 02110-1301, USA. */
22 #include "safe-ctype.h"
24 #include "opcode/d30v.h"
25 #include "dwarf2dbg.h"
27 const char comment_chars[] = ";";
28 const char line_comment_chars[] = "#";
29 const char line_separator_chars[] = "";
30 const char *md_shortopts = "OnNcC";
31 const char EXP_CHARS[] = "eE";
32 const char FLT_CHARS[] = "dD";
42 #define NOP_MULTIPLY 1
44 static int warn_nops = 0;
45 static int Optimizing = 0;
46 static int warn_register_name_conflicts = 1;
52 typedef enum _exec_type
54 EXEC_UNKNOWN, /* No order specified. */
55 EXEC_PARALLEL, /* Done in parallel (FM=00). */
56 EXEC_SEQ, /* Sequential (FM=01). */
57 EXEC_REVSEQ /* Reverse sequential (FM=10). */
61 #define MAX_INSN_FIXUPS 5
69 bfd_reloc_code_real_type reloc;
72 typedef struct _fixups
75 struct d30v_fixup fix[MAX_INSN_FIXUPS];
79 static Fixups FixUps[2];
80 static Fixups *fixups;
82 /* Whether current and previous instruction are word multiply insns. */
83 static int cur_mul32_p = 0;
84 static int prev_mul32_p = 0;
86 /* The flag_explicitly_parallel is true iff the instruction being assembled
87 has been explicitly written as a parallel short-instruction pair by the
88 human programmer. It is used in parallel_ok () to distinguish between
89 those dangerous parallelizations attempted by the human, which are to be
90 allowed, and those attempted by the assembler, which are not. It is set
91 from md_assemble (). */
92 static int flag_explicitly_parallel = 0;
93 static int flag_xp_state = 0;
95 /* Whether current and previous left sub-instruction disables
96 execution of right sub-instruction. */
97 static int cur_left_kills_right_p = 0;
98 static int prev_left_kills_right_p = 0;
100 /* The known current alignment of the current section. */
101 static int d30v_current_align;
102 static segT d30v_current_align_seg;
104 /* The last seen label in the current section. This is used to auto-align
105 labels preceding instructions. */
106 static symbolS *d30v_last_label;
109 #define NOP_LEFT ((long long) NOP << 32)
110 #define NOP_RIGHT ((long long) NOP)
111 #define NOP2 (FM00 | NOP_LEFT | NOP_RIGHT)
113 struct option md_longopts[] =
115 {NULL, no_argument, NULL, 0}
118 size_t md_longopts_size = sizeof (md_longopts);
120 /* Opcode hash table. */
121 static struct hash_control *d30v_hash;
123 /* Do a binary search of the pre_defined_registers array to see if
124 NAME is a valid register name. Return the register number from the
125 array on success, or -1 on failure. */
128 reg_name_search (char *name)
130 int middle, low, high;
134 high = reg_name_cnt () - 1;
138 middle = (low + high) / 2;
139 cmp = strcasecmp (name, pre_defined_registers[middle].name);
146 if (symbol_find (name) != NULL)
148 if (warn_register_name_conflicts)
149 as_warn (_("Register name %s conflicts with symbol of the same name"),
153 return pre_defined_registers[middle].value;
161 /* Check the string at input_line_pointer to see if it is a valid
165 register_name (expressionS *expressionP)
168 char c, *p = input_line_pointer;
170 while (*p && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
177 /* Look to see if it's in the register table. */
178 reg_number = reg_name_search (input_line_pointer);
181 expressionP->X_op = O_register;
182 /* Temporarily store a pointer to the string here. */
183 expressionP->X_op_symbol = (symbolS *) input_line_pointer;
184 expressionP->X_add_number = reg_number;
185 input_line_pointer = p;
194 check_range (unsigned long num, int bits, int flags)
198 /* Don't bother checking 32-bit values. */
201 if (sizeof (unsigned long) * CHAR_BIT == 32)
204 /* We don't record signed or unsigned for 32-bit quantities.
206 min = -((unsigned long) 1 << (bits - 1));
207 max = ((unsigned long) 1 << bits) - 1;
208 return (long) num < min || (long) num > max;
211 if (flags & OPERAND_SHIFT)
213 /* We know that all shifts are right by three bits. */
216 if (flags & OPERAND_SIGNED)
218 unsigned long sign_bit = ((unsigned long) -1L >> 4) + 1;
219 num = (num ^ sign_bit) - sign_bit;
223 if (flags & OPERAND_SIGNED)
225 max = ((unsigned long) 1 << (bits - 1)) - 1;
226 min = - ((unsigned long) 1 << (bits - 1));
227 return (long) num > max || (long) num < min;
231 max = ((unsigned long) 1 << bits) - 1;
232 return num > (unsigned long) max;
237 md_show_usage (FILE *stream)
239 fprintf (stream, _("\nD30V options:\n\
240 -O Make adjacent short instructions parallel if possible.\n\
241 -n Warn about all NOPs inserted by the assembler.\n\
242 -N Warn about NOPs inserted after word multiplies.\n\
243 -c Warn about symbols whose names match register names.\n\
244 -C Opposite of -C. -c is the default.\n"));
248 md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED)
252 /* Optimize. Will attempt to parallelize operations. */
257 /* Warn about all NOPS that the assembler inserts. */
262 /* Warn about the NOPS that the assembler inserts because of the
265 warn_nops = NOP_MULTIPLY;
269 warn_register_name_conflicts = 1;
273 warn_register_name_conflicts = 0;
283 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
289 md_atof (int type, char *litP, int *sizeP)
291 return ieee_md_atof (type, litP, sizeP, TRUE);
295 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
296 asection *sec ATTRIBUTE_UNUSED,
297 fragS *fragP ATTRIBUTE_UNUSED)
303 md_section_align (asection *seg, valueT addr)
305 int align = bfd_get_section_alignment (stdoutput, seg);
306 return ((addr + (1 << align) - 1) & -(1 << align));
312 struct d30v_opcode *opcode;
313 d30v_hash = hash_new ();
315 /* Insert opcode names into a hash table. */
316 for (opcode = (struct d30v_opcode *) d30v_opcode_table; opcode->name; opcode++)
317 hash_insert (d30v_hash, opcode->name, (char *) opcode);
320 FixUps[0].next = &FixUps[1];
321 FixUps[1].next = &FixUps[0];
323 d30v_current_align_seg = now_seg;
326 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
327 from an expression. */
332 while (*p != '-' && *p != '+')
334 if (*p == 0 || *p == '\n' || *p == '\r' || *p == ' ' || *p == ',')
354 static bfd_reloc_code_real_type
355 get_reloc (const struct d30v_operand *op, int rel_flag)
360 if (op->flags & OPERAND_SHIFT)
361 return BFD_RELOC_D30V_9_PCREL;
363 return BFD_RELOC_D30V_6;
366 if (!(op->flags & OPERAND_SHIFT))
367 as_warn (_("unexpected 12-bit reloc type"));
368 if (rel_flag == RELOC_PCREL)
369 return BFD_RELOC_D30V_15_PCREL;
371 return BFD_RELOC_D30V_15;
373 if (!(op->flags & OPERAND_SHIFT))
374 as_warn (_("unexpected 18-bit reloc type"));
375 if (rel_flag == RELOC_PCREL)
376 return BFD_RELOC_D30V_21_PCREL;
378 return BFD_RELOC_D30V_21;
380 if (rel_flag == RELOC_PCREL)
381 return BFD_RELOC_D30V_32_PCREL;
383 return BFD_RELOC_D30V_32;
389 /* Parse a string of operands and return an array of expressions. */
392 get_operands (expressionS exp[], int cmp_hack)
394 char *p = input_line_pointer;
400 exp[numops].X_op = O_absent;
401 exp[numops++].X_add_number = cmp_hack - 1;
406 while (*p == ' ' || *p == '\t' || *p == ',')
409 if (*p == 0 || *p == '\n' || *p == '\r')
415 exp[numops].X_op = O_absent;
419 exp[numops].X_add_number = OPERAND_ATPAR;
425 exp[numops].X_add_number = OPERAND_ATMINUS;
429 exp[numops].X_add_number = OPERAND_ATSIGN;
438 /* Just skip the trailing paren. */
443 input_line_pointer = p;
445 /* Check to see if it might be a register name. */
446 if (!register_name (&exp[numops]))
448 /* Parse as an expression. */
449 expression (&exp[numops]);
452 if (exp[numops].X_op == O_illegal)
453 as_bad (_("illegal operand"));
454 else if (exp[numops].X_op == O_absent)
455 as_bad (_("missing operand"));
458 p = input_line_pointer;
463 /* Postdecrement mode. */
464 exp[numops].X_op = O_absent;
465 exp[numops++].X_add_number = OPERAND_MINUS;
468 /* Postincrement mode. */
469 exp[numops].X_op = O_absent;
470 exp[numops++].X_add_number = OPERAND_PLUS;
476 exp[numops].X_op = 0;
481 /* Generate the instruction.
482 It does everything but write the FM bits. */
485 build_insn (struct d30v_insn *opcode, expressionS *opers)
487 int i, bits, shift, flags;
488 unsigned long number, id = 0;
490 struct d30v_opcode *op = opcode->op;
491 struct d30v_format *form = opcode->form;
494 opcode->ecc << 28 | op->op1 << 25 | op->op2 << 20 | form->modifier << 18;
496 for (i = 0; form->operands[i]; i++)
498 flags = d30v_operand_table[form->operands[i]].flags;
500 /* Must be a register or number. */
501 if (!(flags & OPERAND_REG) && !(flags & OPERAND_NUM)
502 && !(flags & OPERAND_NAME) && !(flags & OPERAND_SPECIAL))
505 bits = d30v_operand_table[form->operands[i]].bits;
506 if (flags & OPERAND_SHIFT)
509 shift = 12 - d30v_operand_table[form->operands[i]].position;
510 if (opers[i].X_op != O_symbol)
511 number = opers[i].X_add_number;
514 if (flags & OPERAND_REG)
516 /* Check for mvfsys or mvtsys control registers. */
517 if (flags & OPERAND_CONTROL && (number & 0x7f) > MAX_CONTROL_REG)
520 id = (number & 0x7f) - MAX_CONTROL_REG;
523 else if (number & OPERAND_FLAG)
524 /* NUMBER is a flag register. */
529 else if (flags & OPERAND_SPECIAL)
532 if (opers[i].X_op != O_register && opers[i].X_op != O_constant
533 && !(flags & OPERAND_NAME))
535 /* Now create a fixup. */
536 if (fixups->fc >= MAX_INSN_FIXUPS)
537 as_fatal (_("too many fixups"));
539 fixups->fix[fixups->fc].reloc =
540 get_reloc (d30v_operand_table + form->operands[i], op->reloc_flag);
541 fixups->fix[fixups->fc].size = 4;
542 fixups->fix[fixups->fc].exp = opers[i];
543 fixups->fix[fixups->fc].operand = form->operands[i];
544 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_D30V_9_PCREL)
545 fixups->fix[fixups->fc].pcrel = RELOC_PCREL;
547 fixups->fix[fixups->fc].pcrel = op->reloc_flag;
551 /* Truncate to the proper number of bits. */
552 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
553 as_bad (_("operand out of range: %ld"), number);
555 number &= 0x7FFFFFFF >> (31 - bits);
556 if (flags & OPERAND_SHIFT)
560 /* It's a LONG instruction. */
561 insn |= ((number & 0xffffffff) >> 26); /* Top 6 bits. */
562 insn <<= 32; /* Shift the first word over. */
563 insn |= ((number & 0x03FC0000) << 2); /* Next 8 bits. */
564 insn |= number & 0x0003FFFF; /* Bottom 18 bits. */
567 insn |= number << shift;
574 d30v_number_to_chars (char *buf, /* Return 'nbytes' of chars here. */
575 long long value, /* The value of the bits. */
576 int n) /* Number of bytes in the output. */
580 buf[n] = value & 0xff;
585 /* Write out a long form instruction. */
588 write_long (struct d30v_insn *opcode ATTRIBUTE_UNUSED,
593 char *f = frag_more (8);
595 dwarf2_emit_insn (8);
597 d30v_number_to_chars (f, insn, 8);
599 for (i = 0; i < fx->fc; i++)
601 if (fx->fix[i].reloc)
603 where = f - frag_now->fr_literal;
604 fix_new_exp (frag_now, where, fx->fix[i].size, &(fx->fix[i].exp),
605 fx->fix[i].pcrel, fx->fix[i].reloc);
612 /* Write out a short form instruction by itself. */
615 write_1_short (struct d30v_insn *opcode,
620 char *f = frag_more (8);
623 dwarf2_emit_insn (8);
624 if (warn_nops == NOP_ALL)
625 as_warn (_("%s NOP inserted"), use_sequential ?
626 _("sequential") : _("parallel"));
628 /* The other container needs to be NOP. */
631 /* Use a sequential NOP rather than a parallel one,
632 as the current instruction is a FLAG_MUL32 type one
633 and the next instruction is a load. */
635 /* According to 4.3.1: for FM=01, sub-instructions performed
636 only by IU cannot be encoded in L-container. */
637 if (opcode->op->unit == IU)
638 /* Right then left. */
639 insn |= FM10 | NOP_LEFT;
641 /* Left then right. */
642 insn = FM01 | (insn << 32) | NOP_RIGHT;
646 /* According to 4.3.1: for FM=00, sub-instructions performed
647 only by IU cannot be encoded in L-container. */
648 if (opcode->op->unit == IU)
649 /* Right container. */
650 insn |= FM00 | NOP_LEFT;
652 /* Left container. */
653 insn = FM00 | (insn << 32) | NOP_RIGHT;
656 d30v_number_to_chars (f, insn, 8);
658 for (i = 0; i < fx->fc; i++)
660 if (fx->fix[i].reloc)
662 where = f - frag_now->fr_literal;
663 fix_new_exp (frag_now,
675 /* Check 2 instructions and determine if they can be safely
676 executed in parallel. Return 1 if they can be. */
679 parallel_ok (struct d30v_insn *op1,
681 struct d30v_insn *op2,
683 exec_type_enum exec_type)
685 int i, j, shift, regno, bits, ecc;
686 unsigned long flags, mask, flags_set1, flags_set2, flags_used1, flags_used2;
687 unsigned long ins, mod_reg[2][3], used_reg[2][3], flag_reg[2];
688 struct d30v_format *f;
689 struct d30v_opcode *op;
691 /* Section 4.3: Both instructions must not be IU or MU only. */
692 if ((op1->op->unit == IU && op2->op->unit == IU)
693 || (op1->op->unit == MU && op2->op->unit == MU))
696 /* First instruction must not be a jump to safely optimize, unless this
697 is an explicit parallel operation. */
698 if (exec_type != EXEC_PARALLEL
699 && (op1->op->flags_used & (FLAG_JMP | FLAG_JSR)))
702 /* If one instruction is /TX or /XT and the other is /FX or /XF respectively,
703 then it is safe to allow the two to be done as parallel ops, since only
704 one will ever be executed at a time. */
705 if ((op1->ecc == ECC_TX && op2->ecc == ECC_FX)
706 || (op1->ecc == ECC_FX && op2->ecc == ECC_TX)
707 || (op1->ecc == ECC_XT && op2->ecc == ECC_XF)
708 || (op1->ecc == ECC_XF && op2->ecc == ECC_XT))
713 [2] a0, a1, flag registers. */
714 for (j = 0; j < 2; j++)
732 mod_reg[j][0] = mod_reg[j][1] = 0;
733 used_reg[j][0] = used_reg[j][1] = 0;
735 if (flag_explicitly_parallel)
737 /* For human specified parallel instructions we have been asked
738 to ignore the possibility that both instructions could modify
739 bits in the PSW, so we initialise the mod & used arrays to 0.
740 We have been asked, however, to refuse to allow parallel
741 instructions which explicitly set the same flag register,
742 eg "cmpne f0,r1,0x10 || cmpeq f0, r5, 0x2", so further on we test
743 for the use of a flag register and set a bit in the mod or used
744 array appropriately. */
750 mod_reg[j][2] = (op->flags_set & FLAG_ALL);
751 used_reg[j][2] = (op->flags_used & FLAG_ALL);
754 /* BSR/JSR always sets R62. */
755 if (op->flags_used & FLAG_JSR)
756 mod_reg[j][1] = (1L << (62 - 32));
758 /* Conditional execution affects the flags_used. */
763 used_reg[j][2] |= flag_reg[j] = FLAG_0;
768 used_reg[j][2] |= flag_reg[j] = FLAG_1;
773 used_reg[j][2] |= flag_reg[j] = (FLAG_0 | FLAG_1);
777 for (i = 0; f->operands[i]; i++)
779 flags = d30v_operand_table[f->operands[i]].flags;
780 shift = 12 - d30v_operand_table[f->operands[i]].position;
781 bits = d30v_operand_table[f->operands[i]].bits;
785 mask = 0x7FFFFFFF >> (31 - bits);
787 if ((flags & OPERAND_PLUS) || (flags & OPERAND_MINUS))
789 /* This is a post-increment or post-decrement.
790 The previous register needs to be marked as modified. */
791 shift = 12 - d30v_operand_table[f->operands[i - 1]].position;
792 regno = (ins >> shift) & 0x3f;
794 mod_reg[j][1] |= 1L << (regno - 32);
796 mod_reg[j][0] |= 1L << regno;
798 else if (flags & OPERAND_REG)
800 regno = (ins >> shift) & mask;
801 /* The memory write functions don't have a destination
803 if ((flags & OPERAND_DEST) && !(op->flags_set & FLAG_MEM))
805 /* MODIFIED registers and flags. */
806 if (flags & OPERAND_ACC)
809 mod_reg[j][2] |= FLAG_A0;
811 mod_reg[j][2] |= FLAG_A1;
815 else if (flags & OPERAND_FLAG)
816 mod_reg[j][2] |= 1L << regno;
817 else if (!(flags & OPERAND_CONTROL))
821 /* Need to check if there are two destination
822 registers, for example ld2w. */
823 if (flags & OPERAND_2REG)
828 for (r = regno; r <= regno + z; r++)
831 mod_reg[j][1] |= 1L << (r - 32);
833 mod_reg[j][0] |= 1L << r;
839 /* USED, but not modified registers and flags. */
840 if (flags & OPERAND_ACC)
843 used_reg[j][2] |= FLAG_A0;
845 used_reg[j][2] |= FLAG_A1;
849 else if (flags & OPERAND_FLAG)
850 used_reg[j][2] |= 1L << regno;
851 else if (!(flags & OPERAND_CONTROL))
855 /* Need to check if there are two source
856 registers, for example st2w. */
857 if (flags & OPERAND_2REG)
862 for (r = regno; r <= regno + z; r++)
865 used_reg[j][1] |= 1L << (r - 32);
867 used_reg[j][0] |= 1L << r;
875 flags_set1 = op1->op->flags_set;
876 flags_set2 = op2->op->flags_set;
877 flags_used1 = op1->op->flags_used;
878 flags_used2 = op2->op->flags_used;
880 /* Check for illegal combinations with ADDppp/SUBppp. */
881 if (((flags_set1 & FLAG_NOT_WITH_ADDSUBppp) != 0
882 && (flags_used2 & FLAG_ADDSUBppp) != 0)
883 || ((flags_set2 & FLAG_NOT_WITH_ADDSUBppp) != 0
884 && (flags_used1 & FLAG_ADDSUBppp) != 0))
887 /* Load instruction combined with half-word multiply is illegal. */
888 if (((flags_used1 & FLAG_MEM) != 0 && (flags_used2 & FLAG_MUL16))
889 || ((flags_used2 & FLAG_MEM) != 0 && (flags_used1 & FLAG_MUL16)))
892 /* Specifically allow add || add by removing carry, overflow bits dependency.
893 This is safe, even if an addc follows since the IU takes the argument in
894 the right container, and it writes its results last.
895 However, don't paralellize add followed by addc or sub followed by
897 if (mod_reg[0][2] == FLAG_CVVA && mod_reg[1][2] == FLAG_CVVA
898 && (used_reg[0][2] & ~flag_reg[0]) == 0
899 && (used_reg[1][2] & ~flag_reg[1]) == 0
900 && op1->op->unit == EITHER && op2->op->unit == EITHER)
902 mod_reg[0][2] = mod_reg[1][2] = 0;
905 for (j = 0; j < 3; j++)
907 /* If the second instruction depends on the first, we obviously
908 cannot parallelize. Note, the mod flag implies use, so
909 check that as well. */
910 /* If flag_explicitly_parallel is set, then the case of the
911 second instruction using a register the first instruction
912 modifies is assumed to be okay; we trust the human. We
913 don't trust the human if both instructions modify the same
914 register but we do trust the human if they modify the same
916 /* We have now been requested not to trust the human if the
917 instructions modify the same flag registers either. */
918 if (flag_explicitly_parallel)
920 if ((mod_reg[0][j] & mod_reg[1][j]) != 0)
924 if ((mod_reg[0][j] & (mod_reg[1][j] | used_reg[1][j])) != 0)
931 /* Write out a short form instruction if possible.
932 Return number of instructions not written out. */
935 write_2_short (struct d30v_insn *opcode1,
937 struct d30v_insn *opcode2,
939 exec_type_enum exec_type,
942 long long insn = NOP2;
946 if (exec_type == EXEC_SEQ
947 && (opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR))
948 && ((opcode1->op->flags_used & FLAG_DELAY) == 0)
949 && ((opcode1->ecc == ECC_AL) || ! Optimizing))
951 /* Unconditional, non-delayed branches kill instructions in
952 the right bin. Conditional branches don't always but if
953 we are not optimizing, then we have been asked to produce
954 an error about such constructs. For the purposes of this
955 test, subroutine calls are considered to be branches. */
956 write_1_short (opcode1, insn1, fx->next, FALSE);
960 /* Note: we do not have to worry about subroutine calls occurring
961 in the right hand container. The return address is always
962 aligned to the next 64 bit boundary, be that 64 or 32 bit away. */
965 case EXEC_UNKNOWN: /* Order not specified. */
967 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type)
968 && ! ( (opcode1->op->unit == EITHER_BUT_PREFER_MU
969 || opcode1->op->unit == MU)
971 ( opcode2->op->unit == EITHER_BUT_PREFER_MU
972 || opcode2->op->unit == MU)))
975 exec_type = EXEC_PARALLEL;
977 if (opcode1->op->unit == IU
978 || opcode2->op->unit == MU
979 || opcode2->op->unit == EITHER_BUT_PREFER_MU)
980 insn = FM00 | (insn2 << 32) | insn1;
983 insn = FM00 | (insn1 << 32) | insn2;
987 else if ((opcode1->op->flags_used & (FLAG_JMP | FLAG_JSR)
988 && ((opcode1->op->flags_used & FLAG_DELAY) == 0))
989 || opcode1->op->flags_used & FLAG_RP)
991 /* We must emit (non-delayed) branch type instructions
992 on their own with nothing in the right container. */
993 /* We must treat repeat instructions likewise, since the
994 following instruction has to be separate from the repeat
995 in order to be repeated. */
996 write_1_short (opcode1, insn1, fx->next, FALSE);
999 else if (prev_left_kills_right_p)
1001 /* The left instruction kills the right slot, so we
1002 must leave it empty. */
1003 write_1_short (opcode1, insn1, fx->next, FALSE);
1006 else if (opcode1->op->unit == IU)
1008 if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1010 /* Case 103810 is a request from Mitsubishi that opcodes
1011 with EITHER_BUT_PREFER_MU should not be executed in
1012 reverse sequential order. */
1013 write_1_short (opcode1, insn1, fx->next, FALSE);
1017 /* Reverse sequential. */
1018 insn = FM10 | (insn2 << 32) | insn1;
1019 exec_type = EXEC_REVSEQ;
1024 insn = FM01 | (insn1 << 32) | insn2;
1026 exec_type = EXEC_SEQ;
1030 case EXEC_PARALLEL: /* Parallel. */
1031 flag_explicitly_parallel = flag_xp_state;
1032 if (! parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
1033 as_bad (_("Instructions may not be executed in parallel"));
1034 else if (opcode1->op->unit == IU)
1036 if (opcode2->op->unit == IU)
1037 as_bad (_("Two IU instructions may not be executed in parallel"));
1038 as_warn (_("Swapping instruction order"));
1039 insn = FM00 | (insn2 << 32) | insn1;
1041 else if (opcode2->op->unit == MU)
1043 if (opcode1->op->unit == MU)
1044 as_bad (_("Two MU instructions may not be executed in parallel"));
1045 else if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1046 as_warn (_("Executing %s in IU may not work"), opcode1->op->name);
1047 as_warn (_("Swapping instruction order"));
1048 insn = FM00 | (insn2 << 32) | insn1;
1052 if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1053 as_warn (_("Executing %s in IU may not work in parallel execution"),
1056 insn = FM00 | (insn1 << 32) | insn2;
1059 flag_explicitly_parallel = 0;
1062 case EXEC_SEQ: /* Sequential. */
1063 if (opcode1->op->unit == IU)
1064 as_bad (_("IU instruction may not be in the left container"));
1065 if (prev_left_kills_right_p)
1066 as_bad (_("special left instruction `%s' kills instruction "
1067 "`%s' in right container"),
1068 opcode1->op->name, opcode2->op->name);
1069 insn = FM01 | (insn1 << 32) | insn2;
1073 case EXEC_REVSEQ: /* Reverse sequential. */
1074 if (opcode2->op->unit == MU)
1075 as_bad (_("MU instruction may not be in the right container"));
1076 if (opcode1->op->unit == EITHER_BUT_PREFER_MU)
1077 as_warn (_("Executing %s in reverse serial with %s may not work"),
1078 opcode1->op->name, opcode2->op->name);
1079 else if (opcode2->op->unit == EITHER_BUT_PREFER_MU)
1080 as_warn (_("Executing %s in IU in reverse serial may not work"),
1082 insn = FM10 | (insn1 << 32) | insn2;
1087 as_fatal (_("unknown execution type passed to write_2_short()"));
1091 dwarf2_emit_insn (8);
1092 d30v_number_to_chars (f, insn, 8);
1094 /* If the previous instruction was a 32-bit multiply but it is put into a
1095 parallel container, mark the current instruction as being a 32-bit
1097 if (prev_mul32_p && exec_type == EXEC_PARALLEL)
1100 for (j = 0; j < 2; j++)
1102 for (i = 0; i < fx->fc; i++)
1104 if (fx->fix[i].reloc)
1106 where = (f - frag_now->fr_literal) + 4 * j;
1108 fix_new_exp (frag_now,
1124 /* Get a pointer to an entry in the format table.
1125 It must look at all formats for an opcode and use the operands
1126 to choose the correct one. Return NULL on error. */
1128 static struct d30v_format *
1129 find_format (struct d30v_opcode *opcode,
1130 expressionS myops[],
1134 int match, opcode_index, i = 0, j, k;
1135 struct d30v_format *fm;
1140 /* Get all the operands and save them as expressions. */
1141 get_operands (myops, cmp_hack);
1143 while ((opcode_index = opcode->format[i++]) != 0)
1145 if (fsize == FORCE_SHORT && opcode_index >= LONG)
1148 if (fsize == FORCE_LONG && opcode_index < LONG)
1151 fm = (struct d30v_format *) &d30v_format_table[opcode_index];
1153 while (fm->form == opcode_index)
1156 /* Now check the operands for compatibility. */
1157 for (j = 0; match && fm->operands[j]; j++)
1159 int flags = d30v_operand_table[fm->operands[j]].flags;
1160 int bits = d30v_operand_table[fm->operands[j]].bits;
1161 operatorT X_op = myops[j].X_op;
1162 int num = myops[j].X_add_number;
1164 if (flags & OPERAND_SPECIAL)
1166 else if (X_op == O_illegal)
1168 else if (flags & OPERAND_REG)
1170 if (X_op != O_register
1171 || ((flags & OPERAND_ACC) && !(num & OPERAND_ACC))
1172 || (!(flags & OPERAND_ACC) && (num & OPERAND_ACC))
1173 || ((flags & OPERAND_FLAG) && !(num & OPERAND_FLAG))
1174 || (!(flags & (OPERAND_FLAG | OPERAND_CONTROL)) && (num & OPERAND_FLAG))
1175 || ((flags & OPERAND_CONTROL)
1176 && !(num & (OPERAND_CONTROL | OPERAND_FLAG))))
1179 else if (((flags & OPERAND_MINUS)
1180 && (X_op != O_absent || num != OPERAND_MINUS))
1181 || ((flags & OPERAND_PLUS)
1182 && (X_op != O_absent || num != OPERAND_PLUS))
1183 || ((flags & OPERAND_ATMINUS)
1184 && (X_op != O_absent || num != OPERAND_ATMINUS))
1185 || ((flags & OPERAND_ATPAR)
1186 && (X_op != O_absent || num != OPERAND_ATPAR))
1187 || ((flags & OPERAND_ATSIGN)
1188 && (X_op != O_absent || num != OPERAND_ATSIGN)))
1190 else if (flags & OPERAND_NUM)
1192 /* A number can be a constant or symbol expression. */
1194 /* If we have found a register name, but that name
1195 also matches a symbol, then re-parse the name as
1197 if (X_op == O_register
1198 && symbol_find ((char *) myops[j].X_op_symbol))
1200 input_line_pointer = (char *) myops[j].X_op_symbol;
1201 expression (&myops[j]);
1204 /* Turn an expression into a symbol for later resolution. */
1205 if (X_op != O_absent && X_op != O_constant
1206 && X_op != O_symbol && X_op != O_register
1209 symbolS *sym = make_expr_symbol (&myops[j]);
1210 myops[j].X_op = X_op = O_symbol;
1211 myops[j].X_add_symbol = sym;
1212 myops[j].X_add_number = num = 0;
1215 if (fm->form >= LONG)
1217 /* If we're testing for a LONG format, either fits. */
1218 if (X_op != O_constant && X_op != O_symbol)
1221 else if (fm->form < LONG
1222 && ((fsize == FORCE_SHORT && X_op == O_symbol)
1223 || (fm->form == SHORT_D2 && j == 0)))
1226 /* This is the tricky part. Will the constant or symbol
1227 fit into the space in the current format? */
1228 else if (X_op == O_constant)
1230 if (check_range (num, bits, flags))
1233 else if (X_op == O_symbol
1234 && S_IS_DEFINED (myops[j].X_add_symbol)
1235 && S_GET_SEGMENT (myops[j].X_add_symbol) == now_seg
1236 && opcode->reloc_flag == RELOC_PCREL)
1238 /* If the symbol is defined, see if the value will fit
1239 into the form we're considering. */
1243 /* Calculate the current address by running through the
1244 previous frags and adding our current offset. */
1245 value = frag_now_fix_octets ();
1246 for (f = frchain_now->frch_root; f; f = f->fr_next)
1247 value += f->fr_fix + f->fr_offset;
1248 value = S_GET_VALUE (myops[j].X_add_symbol) - value;
1249 if (check_range (value, bits, flags))
1256 /* We're only done if the operands matched so far AND there
1257 are no more to check. */
1258 if (match && myops[j].X_op == 0)
1260 /* Final check - issue a warning if an odd numbered register
1261 is used as the first register in an instruction that reads
1262 or writes 2 registers. */
1264 for (j = 0; fm->operands[j]; j++)
1265 if (myops[j].X_op == O_register
1266 && (myops[j].X_add_number & 1)
1267 && (d30v_operand_table[fm->operands[j]].flags & OPERAND_2REG))
1268 as_warn (_("Odd numbered register used as target of multi-register instruction"));
1272 fm = (struct d30v_format *) &d30v_format_table[++k];
1278 /* Assemble a single instruction and return an opcode.
1279 Return -1 (an invalid opcode) on error. */
1281 #define NAME_BUF_LEN 20
1284 do_assemble (char *str,
1285 struct d30v_insn *opcode,
1292 char name[NAME_BUF_LEN];
1295 int fsize = (shortp ? FORCE_SHORT : 0);
1296 expressionS myops[6];
1299 /* Drop leading whitespace. */
1303 /* Find the opcode end. */
1304 for (op_start = op_end = str;
1306 && nlen < (NAME_BUF_LEN - 1)
1308 && !is_end_of_line[(unsigned char) *op_end] && *op_end != ' ';
1311 name[nlen] = TOLOWER (op_start[nlen]);
1320 /* If there is an execution condition code, handle it. */
1324 while ((i < ECC_MAX) && strncasecmp (d30v_ecc_names[i], op_end + 1, 2))
1330 strncpy (tmp, op_end + 1, 2);
1332 as_bad (_("unknown condition code: %s"), tmp);
1339 opcode->ecc = ECC_AL;
1341 /* CMP and CMPU change their name based on condition codes. */
1342 if (!strncmp (name, "cmp", 3))
1345 char **d30v_str = (char **) d30v_cc_names;
1352 for (i = 1; *d30v_str && strncmp (*d30v_str, &name[p], 2); i++, d30v_str++)
1355 /* cmpu only supports some condition codes. */
1361 as_bad (_("cmpu doesn't support condition code %s"), &name[p]);
1368 as_bad (_("unknown condition code: %s"), &name[p]);
1377 /* Need to look for .s or .l. */
1378 if (name[nlen - 2] == '.')
1380 switch (name[nlen - 1])
1383 fsize = FORCE_SHORT;
1392 /* Find the first opcode with the proper name. */
1393 opcode->op = (struct d30v_opcode *) hash_find (d30v_hash, name);
1394 if (opcode->op == NULL)
1396 as_bad (_("unknown opcode: %s"), name);
1400 save = input_line_pointer;
1401 input_line_pointer = op_end;
1402 while (!(opcode->form = find_format (opcode->op, myops, fsize, cmp_hack)))
1405 if (opcode->op->name == NULL || strcmp (opcode->op->name, name))
1407 as_bad (_("operands for opcode `%s' do not match any valid format"),
1412 input_line_pointer = save;
1414 insn = build_insn (opcode, myops);
1416 /* Propagate multiply status. */
1419 if (is_parallel && prev_mul32_p)
1423 prev_mul32_p = cur_mul32_p;
1424 cur_mul32_p = (opcode->op->flags_used & FLAG_MUL32) != 0;
1428 /* Propagate left_kills_right status. */
1431 prev_left_kills_right_p = cur_left_kills_right_p;
1433 if (opcode->op->flags_set & FLAG_LKR)
1435 cur_left_kills_right_p = 1;
1437 if (strcmp (opcode->op->name, "mvtsys") == 0)
1439 /* Left kills right for only mvtsys only for
1440 PSW/PSWH/PSWL/flags target. */
1441 if ((myops[0].X_op == O_register) &&
1442 ((myops[0].X_add_number == OPERAND_CONTROL) || /* psw */
1443 (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+2) || /* pswh */
1444 (myops[0].X_add_number == OPERAND_CONTROL+MAX_CONTROL_REG+1) || /* pswl */
1445 (myops[0].X_add_number == OPERAND_FLAG+0) || /* f0 */
1446 (myops[0].X_add_number == OPERAND_FLAG+1) || /* f1 */
1447 (myops[0].X_add_number == OPERAND_FLAG+2) || /* f2 */
1448 (myops[0].X_add_number == OPERAND_FLAG+3) || /* f3 */
1449 (myops[0].X_add_number == OPERAND_FLAG+4) || /* f4 */
1450 (myops[0].X_add_number == OPERAND_FLAG+5) || /* f5 */
1451 (myops[0].X_add_number == OPERAND_FLAG+6) || /* f6 */
1452 (myops[0].X_add_number == OPERAND_FLAG+7))) /* f7 */
1454 cur_left_kills_right_p = 1;
1458 /* Other mvtsys target registers don't kill right
1460 cur_left_kills_right_p = 0;
1465 cur_left_kills_right_p = 0;
1471 /* Called internally to handle all alignment needs. This takes care
1472 of eliding calls to frag_align if'n the cached current alignment
1473 says we've already got it, as well as taking care of the auto-aligning
1477 d30v_align (int n, char *pfill, symbolS *label)
1479 /* The front end is prone to changing segments out from under us
1480 temporarily when -g is in effect. */
1481 int switched_seg_p = (d30v_current_align_seg != now_seg);
1483 /* Do not assume that if 'd30v_current_align >= n' and
1484 '! switched_seg_p' that it is safe to avoid performing
1485 this alignment request. The alignment of the current frag
1486 can be changed under our feet, for example by a .ascii
1487 directive in the source code. cf testsuite/gas/d30v/reloc.s */
1488 d30v_cleanup (FALSE);
1493 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
1495 static char const nop[4] = { 0x00, 0xf0, 0x00, 0x00 };
1497 /* First, make sure we're on a four-byte boundary, in case
1498 someone has been putting .byte values the text section. */
1499 if (d30v_current_align < 2 || switched_seg_p)
1500 frag_align (2, 0, 0);
1501 frag_align_pattern (n, nop, sizeof nop, 0);
1504 frag_align (n, 0, 0);
1507 frag_align (n, *pfill, 0);
1509 if (!switched_seg_p)
1510 d30v_current_align = n;
1515 int label_seen = FALSE;
1516 struct frag *old_frag;
1520 gas_assert (S_GET_SEGMENT (label) == now_seg);
1522 old_frag = symbol_get_frag (label);
1523 old_value = S_GET_VALUE (label);
1524 new_value = (valueT) frag_now_fix ();
1526 /* It is possible to have more than one label at a particular
1527 address, especially if debugging is enabled, so we must
1528 take care to adjust all the labels at this address in this
1529 fragment. To save time we search from the end of the symbol
1530 list, backwards, since the symbols we are interested in are
1531 almost certainly the ones that were most recently added.
1532 Also to save time we stop searching once we have seen at least
1533 one matching label, and we encounter a label that is no longer
1534 in the target fragment. Note, this search is guaranteed to
1535 find at least one match when sym == label, so no special case
1536 code is necessary. */
1537 for (sym = symbol_lastP; sym != NULL; sym = symbol_previous (sym))
1539 if (symbol_get_frag (sym) == old_frag
1540 && S_GET_VALUE (sym) == old_value)
1543 symbol_set_frag (sym, frag_now);
1544 S_SET_VALUE (sym, new_value);
1546 else if (label_seen && symbol_get_frag (sym) != old_frag)
1551 record_alignment (now_seg, n);
1554 /* This is the main entry point for the machine-dependent assembler.
1555 STR points to a machine-dependent instruction. This function is
1556 supposed to emit the frags/bytes it assembles to. For the D30V, it
1557 mostly handles the special VLIW parsing and packing and leaves the
1558 difficult stuff to do_assemble (). */
1560 static long long prev_insn = -1;
1561 static struct d30v_insn prev_opcode;
1562 static subsegT prev_subseg;
1563 static segT prev_seg = 0;
1566 md_assemble (char *str)
1568 struct d30v_insn opcode;
1570 /* Execution type; parallel, etc. */
1571 exec_type_enum extype = EXEC_UNKNOWN;
1572 /* Saved extype. Used for multiline instructions. */
1573 static exec_type_enum etype = EXEC_UNKNOWN;
1576 if ((prev_insn != -1) && prev_seg
1577 && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1578 d30v_cleanup (FALSE);
1580 if (d30v_current_align < 3)
1581 d30v_align (3, NULL, d30v_last_label);
1582 else if (d30v_current_align > 3)
1583 d30v_current_align = 3;
1584 d30v_last_label = NULL;
1586 flag_explicitly_parallel = 0;
1588 if (etype == EXEC_UNKNOWN)
1590 /* Look for the special multiple instruction separators. */
1591 str2 = strstr (str, "||");
1594 extype = EXEC_PARALLEL;
1599 str2 = strstr (str, "->");
1604 str2 = strstr (str, "<-");
1606 extype = EXEC_REVSEQ;
1610 /* STR2 points to the separator, if one. */
1615 /* If two instructions are present and we already have one saved,
1616 then first write it out. */
1617 d30v_cleanup (FALSE);
1619 /* Assemble first instruction and save it. */
1620 prev_insn = do_assemble (str, &prev_opcode, 1, 0);
1621 if (prev_insn == -1)
1622 as_bad (_("Cannot assemble instruction"));
1623 if (prev_opcode.form != NULL && prev_opcode.form->form >= LONG)
1624 as_bad (_("First opcode is long. Unable to mix instructions as specified."));
1625 fixups = fixups->next;
1628 prev_subseg = now_subseg;
1632 insn = do_assemble (str, &opcode,
1633 (extype != EXEC_UNKNOWN || etype != EXEC_UNKNOWN),
1634 extype == EXEC_PARALLEL);
1637 if (extype != EXEC_UNKNOWN)
1639 as_bad (_("Cannot assemble instruction"));
1643 if (etype != EXEC_UNKNOWN)
1646 etype = EXEC_UNKNOWN;
1649 /* Word multiply instructions must not be followed by either a load or a
1650 16-bit multiply instruction in the next cycle. */
1651 if ( (extype != EXEC_REVSEQ)
1653 && (opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1655 /* However, load and multiply should able to be combined in a parallel
1656 operation, so check for that first. */
1658 && (opcode.op->flags_used & FLAG_MEM)
1659 && opcode.form->form < LONG
1660 && (extype == EXEC_PARALLEL || (Optimizing && extype == EXEC_UNKNOWN))
1661 && parallel_ok (&prev_opcode, (long) prev_insn,
1662 &opcode, (long) insn, extype)
1663 && write_2_short (&prev_opcode, (long) prev_insn,
1664 &opcode, (long) insn, extype, fixups) == 0)
1666 /* No instructions saved. */
1672 /* Can't parallelize, flush previous instruction and emit a
1673 word of NOPS, unless the previous instruction is a NOP,
1674 in which case just flush it, as this will generate a word
1677 if (prev_insn != -1 && (strcmp (prev_opcode.op->name, "nop") == 0))
1678 d30v_cleanup (FALSE);
1683 if (prev_insn != -1)
1684 d30v_cleanup (TRUE);
1688 dwarf2_emit_insn (8);
1689 d30v_number_to_chars (f, NOP2, 8);
1691 if (warn_nops == NOP_ALL || warn_nops == NOP_MULTIPLY)
1693 if (opcode.op->flags_used & FLAG_MEM)
1694 as_warn (_("word of NOPs added between word multiply and load"));
1696 as_warn (_("word of NOPs added between word multiply and 16-bit multiply"));
1701 extype = EXEC_UNKNOWN;
1704 else if ( (extype == EXEC_REVSEQ)
1706 && (prev_opcode.op->flags_used & (FLAG_MEM | FLAG_MUL16)))
1708 /* Can't parallelize, flush current instruction and add a
1710 write_1_short (&opcode, (long) insn, fixups->next->next, TRUE);
1712 /* Make the previous instruction the current one. */
1713 extype = EXEC_UNKNOWN;
1716 now_subseg = prev_subseg;
1718 cur_mul32_p = prev_mul32_p;
1720 memcpy (&opcode, &prev_opcode, sizeof (prev_opcode));
1723 /* If this is a long instruction, write it and any previous short
1725 if (opcode.form->form >= LONG)
1727 if (extype != EXEC_UNKNOWN)
1728 as_bad (_("Instruction uses long version, so it cannot be mixed as specified"));
1729 d30v_cleanup (FALSE);
1730 write_long (&opcode, insn, fixups);
1733 else if ((prev_insn != -1)
1735 (&prev_opcode, (long) prev_insn, &opcode,
1736 (long) insn, extype, fixups) == 0))
1738 /* No instructions saved. */
1743 if (extype != EXEC_UNKNOWN)
1744 as_bad (_("Unable to mix instructions as specified"));
1746 /* Save off last instruction so it may be packed on next pass. */
1747 memcpy (&prev_opcode, &opcode, sizeof (prev_opcode));
1750 prev_subseg = now_subseg;
1751 fixups = fixups->next;
1752 prev_mul32_p = cur_mul32_p;
1756 /* If while processing a fixup, a reloc really needs to be created,
1757 then it is done here. */
1760 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1763 reloc = XNEW (arelent);
1764 reloc->sym_ptr_ptr = XNEW (asymbol *);
1765 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1766 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1767 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1768 if (reloc->howto == NULL)
1770 as_bad_where (fixp->fx_file, fixp->fx_line,
1771 _("reloc %d not supported by object file format"),
1772 (int) fixp->fx_r_type);
1781 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1782 asection *seg ATTRIBUTE_UNUSED)
1789 md_pcrel_from_section (fixS *fixp, segT sec)
1791 if (fixp->fx_addsy != (symbolS *) NULL
1792 && (!S_IS_DEFINED (fixp->fx_addsy)
1793 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1795 return fixp->fx_frag->fr_address + fixp->fx_where;
1798 /* Called after the assembler has finished parsing the input file or
1799 after a label is defined. Because the D30V assembler sometimes
1800 saves short instructions to see if it can package them with the
1801 next instruction, there may be a short instruction that still needs
1805 d30v_cleanup (int use_sequential)
1810 if (prev_insn != -1)
1813 subseg = now_subseg;
1814 subseg_set (prev_seg, prev_subseg);
1815 write_1_short (&prev_opcode, (long) prev_insn, fixups->next,
1817 subseg_set (seg, subseg);
1820 prev_mul32_p = FALSE;
1826 /* This function is called at the start of every line. It checks to
1827 see if the first character is a '.', which indicates the start of a
1828 pseudo-op. If it is, then write out any unwritten instructions. */
1831 d30v_start_line (void)
1833 char *c = input_line_pointer;
1835 while (ISSPACE (*c))
1839 d30v_cleanup (FALSE);
1843 check_size (long value, int bits, const char *file, int line)
1852 max = (1 << (bits - 1)) - 1;
1855 as_bad_where (file, line, _("value too large to fit in %d bits"), bits);
1858 /* d30v_frob_label() is called when after a label is recognized. */
1861 d30v_frob_label (symbolS *lab)
1863 /* Emit any pending instructions. */
1864 d30v_cleanup (FALSE);
1866 /* Update the label's address with the current output pointer. */
1867 symbol_set_frag (lab, frag_now);
1868 S_SET_VALUE (lab, (valueT) frag_now_fix ());
1870 /* Record this label for future adjustment after we find out what
1871 kind of data it references, and the required alignment therewith. */
1872 d30v_last_label = lab;
1874 dwarf2_emit_label (lab);
1877 /* Hook into cons for capturing alignment changes. */
1880 d30v_cons_align (int size)
1884 /* Don't specially align anything in debug sections. */
1885 if ((now_seg->flags & SEC_ALLOC) == 0
1886 || strcmp (now_seg->name, ".eh_frame") == 0)
1890 while ((size >>= 1) != 0)
1893 if (d30v_current_align < log_size)
1894 d30v_align (log_size, (char *) NULL, NULL);
1895 else if (d30v_current_align > log_size)
1896 d30v_current_align = log_size;
1897 d30v_last_label = NULL;
1901 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1904 unsigned long insn, insn2;
1907 if (fixP->fx_addsy == (symbolS *) NULL)
1910 /* We don't support subtracting a symbol. */
1911 if (fixP->fx_subsy != (symbolS *) NULL)
1912 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1914 /* Fetch the instruction, insert the fully resolved operand
1915 value, and stuff the instruction back again. */
1916 where = fixP->fx_frag->fr_literal + fixP->fx_where;
1917 insn = bfd_getb32 ((unsigned char *) where);
1919 switch (fixP->fx_r_type)
1921 case BFD_RELOC_8: /* Check for a bad .byte directive. */
1922 if (fixP->fx_addsy != NULL)
1923 as_bad (_("line %d: unable to place address of symbol '%s' into a byte"),
1924 fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1925 else if (((unsigned)value) > 0xff)
1926 as_bad (_("line %d: unable to place value %lx into a byte"),
1927 fixP->fx_line, value);
1929 *(unsigned char *) where = value;
1932 case BFD_RELOC_16: /* Check for a bad .short directive. */
1933 if (fixP->fx_addsy != NULL)
1934 as_bad (_("line %d: unable to place address of symbol '%s' into a short"),
1935 fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1936 else if (((unsigned)value) > 0xffff)
1937 as_bad (_("line %d: unable to place value %lx into a short"),
1938 fixP->fx_line, value);
1940 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1943 case BFD_RELOC_64: /* Check for a bad .quad directive. */
1944 if (fixP->fx_addsy != NULL)
1945 as_bad (_("line %d: unable to place address of symbol '%s' into a quad"),
1946 fixP->fx_line, S_GET_NAME (fixP->fx_addsy));
1949 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1950 bfd_putb32 (0, ((unsigned char *) where) + 4);
1954 case BFD_RELOC_D30V_6:
1955 check_size (value, 6, fixP->fx_file, fixP->fx_line);
1956 insn |= value & 0x3F;
1957 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1960 case BFD_RELOC_D30V_9_PCREL:
1961 if (fixP->fx_where & 0x7)
1966 fixP->fx_r_type = BFD_RELOC_D30V_9_PCREL_R;
1968 check_size (value, 9, fixP->fx_file, fixP->fx_line);
1969 insn |= ((value >> 3) & 0x3F) << 12;
1970 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1973 case BFD_RELOC_D30V_15:
1974 check_size (value, 15, fixP->fx_file, fixP->fx_line);
1975 insn |= (value >> 3) & 0xFFF;
1976 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1979 case BFD_RELOC_D30V_15_PCREL:
1980 if (fixP->fx_where & 0x7)
1985 fixP->fx_r_type = BFD_RELOC_D30V_15_PCREL_R;
1987 check_size (value, 15, fixP->fx_file, fixP->fx_line);
1988 insn |= (value >> 3) & 0xFFF;
1989 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1992 case BFD_RELOC_D30V_21:
1993 check_size (value, 21, fixP->fx_file, fixP->fx_line);
1994 insn |= (value >> 3) & 0x3FFFF;
1995 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1998 case BFD_RELOC_D30V_21_PCREL:
1999 if (fixP->fx_where & 0x7)
2004 fixP->fx_r_type = BFD_RELOC_D30V_21_PCREL_R;
2006 check_size (value, 21, fixP->fx_file, fixP->fx_line);
2007 insn |= (value >> 3) & 0x3FFFF;
2008 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2011 case BFD_RELOC_D30V_32:
2012 insn2 = bfd_getb32 ((unsigned char *) where + 4);
2013 insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
2014 insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
2015 insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
2016 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2017 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2020 case BFD_RELOC_D30V_32_PCREL:
2021 insn2 = bfd_getb32 ((unsigned char *) where + 4);
2022 insn |= (value >> 26) & 0x3F; /* Top 6 bits. */
2023 insn2 |= ((value & 0x03FC0000) << 2); /* Next 8 bits. */
2024 insn2 |= value & 0x0003FFFF; /* Bottom 18 bits. */
2025 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
2026 bfd_putb32 ((bfd_vma) insn2, (unsigned char *) where + 4);
2030 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
2034 as_bad (_("line %d: unknown relocation type: 0x%x"),
2035 fixP->fx_line, fixP->fx_r_type);
2039 /* Handle the .align pseudo-op. This aligns to a power of two. We
2040 hook here to latch the current alignment. */
2043 s_d30v_align (int ignore ATTRIBUTE_UNUSED)
2046 char fill, *pfill = NULL;
2047 long max_alignment = 15;
2049 align = get_absolute_expression ();
2050 if (align > max_alignment)
2052 align = max_alignment;
2053 as_warn (_("Alignment too large: %d assumed"), align);
2057 as_warn (_("Alignment negative: 0 assumed"));
2061 if (*input_line_pointer == ',')
2063 input_line_pointer++;
2064 fill = get_absolute_expression ();
2068 d30v_last_label = NULL;
2069 d30v_align (align, pfill, NULL);
2071 demand_empty_rest_of_line ();
2074 /* Handle the .text pseudo-op. This is like the usual one, but it
2075 clears the saved last label and resets known alignment. */
2082 d30v_last_label = NULL;
2083 d30v_current_align = 0;
2084 d30v_current_align_seg = now_seg;
2087 /* Handle the .data pseudo-op. This is like the usual one, but it
2088 clears the saved last label and resets known alignment. */
2094 d30v_last_label = NULL;
2095 d30v_current_align = 0;
2096 d30v_current_align_seg = now_seg;
2099 /* Handle the .section pseudo-op. This is like the usual one, but it
2100 clears the saved last label and resets known alignment. */
2103 s_d30v_section (int ignore)
2105 obj_elf_section (ignore);
2106 d30v_last_label = NULL;
2107 d30v_current_align = 0;
2108 d30v_current_align_seg = now_seg;
2111 /* The target specific pseudo-ops which we support. */
2112 const pseudo_typeS md_pseudo_table[] =
2114 { "word", cons, 4 },
2115 { "hword", cons, 2 },
2116 { "align", s_d30v_align, 0 },
2117 { "text", s_d30v_text, 0 },
2118 { "data", s_d30v_data, 0 },
2119 { "section", s_d30v_section, 0 },
2120 { "section.s", s_d30v_section, 0 },
2121 { "sect", s_d30v_section, 0 },
2122 { "sect.s", s_d30v_section, 0 },