1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars[] = "#;";
30 const char line_comment_chars[] = "#";
31 const char line_separator_chars[] = "";
32 const char *md_shortopts = "";
33 const char EXP_CHARS[] = "eE";
34 const char FLT_CHARS[] = "dD";
38 #define MAX_INSN_FIXUPS (5)
42 bfd_reloc_code_real_type reloc;
45 typedef struct _fixups
48 struct d10v_fixup fix[MAX_INSN_FIXUPS];
52 static Fixups FixUps[2];
53 static Fixups *fixups;
56 static int reg_name_search PARAMS ((char *name));
57 static int register_name PARAMS ((expressionS *expressionP));
58 static int check_range PARAMS ((unsigned long num, int bits, int flags));
59 static int postfix PARAMS ((char *p));
60 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
61 static int get_operands PARAMS ((expressionS exp[]));
62 static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
63 static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
64 static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
65 static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
66 struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
67 static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
68 static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
69 offsetT value, int left));
72 struct option md_longopts[] = {
73 {NULL, no_argument, NULL, 0}
75 size_t md_longopts_size = sizeof(md_longopts);
77 /* The target specific pseudo-ops which we support. */
78 const pseudo_typeS md_pseudo_table[] =
83 /* Opcode hash table. */
84 static struct hash_control *d10v_hash;
86 /* reg_name_search does a binary search of the pre_defined_registers
87 array to see if "name" is a valid regiter name. Returns the register
88 number from the array on success, or -1 on failure. */
91 reg_name_search (name)
94 int middle, low, high;
98 high = reg_name_cnt() - 1;
102 middle = (low + high) / 2;
103 cmp = strcasecmp (name, pre_defined_registers[middle].name);
109 return pre_defined_registers[middle].value;
115 /* register_name() checks the string at input_line_pointer
116 to see if it is a valid register name */
119 register_name (expressionP)
120 expressionS *expressionP;
123 char c, *p = input_line_pointer;
125 while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
132 /* look to see if it's in the register table */
133 reg_number = reg_name_search (input_line_pointer);
136 expressionP->X_op = O_register;
137 /* temporarily store a pointer to the string here */
138 expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
139 expressionP->X_add_number = reg_number;
140 input_line_pointer = p;
150 check_range (num, bits, flags)
158 if (flags & OPERAND_SHIFT)
160 /* all special shift operands are unsigned */
161 /* and <= 16. We allow 0 for now. */
168 if (flags & OPERAND_SIGNED)
170 bit1 = (1 << (bits - 1));
175 num = ((num & (bit1 | max))^(~max))+bit1;
178 min = - (1 << (bits - 1));
179 if (((long)num > max) || ((long)num < min))
184 max = (1 << bits) - 1;
186 if ((num > max) || (num < min))
195 md_show_usage (stream)
198 fprintf(stream, "D10V options:\n\
203 md_parse_option (c, arg)
211 md_undefined_symbol (name)
218 md_atof (type, litp, sizep)
227 md_convert_frag (abfd, sec, fragP)
232 printf ("call to md_convert_frag \n");
237 md_section_align (seg, addr)
241 int align = bfd_get_section_alignment (stdoutput, seg);
242 return ((addr + (1 << align) - 1) & (-1 << align));
249 char *prev_name = "";
250 struct d10v_opcode *opcode;
251 d10v_hash = hash_new();
253 /* Insert unique names into hash table. The D10v instruction set
254 has many identical opcode names that have different opcodes based
255 on the operands. This hash table then provides a quick index to
256 the first opcode with a particular name in the opcode table. */
258 for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
260 if (strcmp (prev_name, opcode->name))
262 prev_name = (char *)opcode->name;
263 hash_insert (d10v_hash, opcode->name, (char *) opcode);
268 FixUps[0].next = &FixUps[1];
269 FixUps[1].next = &FixUps[0];
273 /* this function removes the postincrement or postdecrement
274 operator ( '+' or '-' ) from an expression */
276 static int postfix (p)
279 while (*p != '-' && *p != '+')
281 if (*p==0 || *p=='\n' || *p=='\r')
301 static bfd_reloc_code_real_type
303 struct d10v_operand *op;
307 /* printf("get_reloc: bits=%d address=%d\n",bits,op->flags & OPERAND_ADDR); */
311 if (op->flags & OPERAND_ADDR)
314 return (BFD_RELOC_D10V_10_PCREL_R);
316 return (BFD_RELOC_D10V_18_PCREL);
319 return (BFD_RELOC_16);
322 /* get_operands parses a string of operands and returns
323 an array of expressions */
329 char *p = input_line_pointer;
335 while (*p == ' ' || *p == '\t' || *p == ',')
337 if (*p==0 || *p=='\n' || *p=='\r')
343 exp[numops].X_op = O_absent;
347 exp[numops].X_add_number = OPERAND_ATPAR;
352 exp[numops].X_add_number = OPERAND_ATMINUS;
356 exp[numops].X_add_number = OPERAND_ATSIGN;
365 /* just skip the trailing paren */
370 input_line_pointer = p;
373 /* check to see if it might be a register name */
374 if (!register_name (&exp[numops]))
376 /* parse as an expression */
377 expression (&exp[numops]);
380 if (exp[numops].X_op == O_illegal)
381 as_bad ("illegal operand");
382 else if (exp[numops].X_op == O_absent)
383 as_bad ("missing operand");
386 p = input_line_pointer;
391 case -1: /* postdecrement mode */
392 exp[numops].X_op = O_absent;
393 exp[numops++].X_add_number = OPERAND_MINUS;
395 case 1: /* postincrement mode */
396 exp[numops].X_op = O_absent;
397 exp[numops++].X_add_number = OPERAND_PLUS;
401 exp[numops].X_op = 0;
406 d10v_insert_operand (insn, op_type, value, left)
414 shift = d10v_operands[op_type].shift;
418 bits = d10v_operands[op_type].bits;
420 /* truncate to the proper number of bits */
421 if (check_range (value, bits, d10v_operands[op_type].flags))
422 as_bad("operand out of range: %d",value);
424 value &= 0x7FFFFFFF >> (31 - bits);
425 insn |= (value << shift);
431 /* build_insn takes a pointer to the opcode entry in the opcode table
432 and the array of operand expressions and returns the instruction */
435 build_insn (opcode, opers, insn)
436 struct d10v_opcode *opcode;
440 int i, bits, shift, flags, format;
443 /* the insn argument is only used for the DIVS kludge */
448 insn = opcode->opcode;
449 format = opcode->format;
452 for (i=0;opcode->operands[i];i++)
454 flags = d10v_operands[opcode->operands[i]].flags;
455 bits = d10v_operands[opcode->operands[i]].bits;
456 shift = d10v_operands[opcode->operands[i]].shift;
457 number = opers[i].X_add_number;
459 if (flags & OPERAND_REG)
461 number &= REGISTER_MASK;
462 if (format == LONG_L)
466 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
468 /* now create a fixup */
471 printf("need a fixup: ");
472 print_expr_1(stdout,&opers[i]);
476 if (fixups->fc >= MAX_INSN_FIXUPS)
477 as_fatal ("too many fixups");
478 fixups->fix[fixups->fc].exp = opers[i];
480 /* put the operand number here for now. We can look up
481 the reloc type and/or fixup the instruction in md_apply_fix() */
482 fixups->fix[fixups->fc].reloc = opcode->operands[i];
486 /* truncate to the proper number of bits */
487 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
488 as_bad("operand out of range: %d",number);
489 number &= 0x7FFFFFFF >> (31 - bits);
490 insn = insn | (number << shift);
493 /* kludge: for DIVS, we need to put the operands in twice */
494 /* on the second pass, format is changed to LONG_R to force */
495 /* the second set of operands to not be shifted over 15 */
496 if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
497 insn = build_insn (opcode, opers, insn);
502 /* write out a long form instruction */
504 write_long (opcode, insn, fx)
505 struct d10v_opcode *opcode;
510 char *f = frag_more(4);
513 /* printf("INSN: %08x\n",insn); */
514 number_to_chars_bigendian (f, insn, 4);
516 for (i=0; i < fx->fc; i++)
518 if (get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]))
521 printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
522 print_expr_1(stdout,&(fx->fix[i].exp));
526 fix_new_exp (frag_now,
527 f - frag_now->fr_literal,
538 /* write out a short form instruction by itself */
540 write_1_short (opcode, insn, fx)
541 struct d10v_opcode *opcode;
545 char *f = frag_more(4);
548 if (opcode->exec_type == PARONLY)
549 as_fatal ("Instruction must be executed in parallel with another instruction.");
551 /* the other container needs to be NOP */
552 /* according to 4.3.1: for FM=00, sub-instructions performed only
553 by IU cannot be encoded in L-container. */
554 if (opcode->unit == IU)
555 insn |= FM00 | (NOP << 15); /* right container */
557 insn = FM00 | (insn << 15) | NOP; /* left container */
559 /* printf("INSN: %08x\n",insn); */
560 number_to_chars_bigendian (f, insn, 4);
561 for (i=0; i < fx->fc; i++)
563 bfd_reloc_code_real_type reloc;
564 reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]);
568 printf("fix_new_exp: where:%x size:4\n ",f - frag_now->fr_literal);
569 print_expr_1(stdout,&(fx->fix[i].exp));
573 /* if it's an R reloc, we may have to switch it to L */
574 if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
575 fx->fix[i].reloc |= 1024;
577 fix_new_exp (frag_now,
578 f - frag_now->fr_literal,
588 /* write out a short form instruction if possible */
589 /* return number of instructions not written out */
591 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
592 struct d10v_opcode *opcode1, *opcode2;
593 unsigned long insn1, insn2;
601 if ( (exec_type != 1) && ((opcode1->exec_type == PARONLY)
602 || (opcode2->exec_type == PARONLY)))
603 as_fatal("Instruction must be executed in parallel");
605 if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
606 as_fatal ("Long instructions may not be combined.");
608 if(opcode1->exec_type == BRANCH_LINK)
610 /* subroutines must be called from 32-bit boundaries */
611 /* so the return address will be correct */
612 write_1_short (opcode1, insn1, fx->next);
619 if (opcode1->unit == IU)
621 /* reverse sequential */
622 insn = FM10 | (insn2 << 15) | insn1;
626 insn = FM01 | (insn1 << 15) | insn2;
630 case 1: /* parallel */
631 if (opcode1->exec_type == SEQ || opcode2->exec_type == SEQ)
632 as_fatal ("One of these instructions may not be executed in parallel.");
634 if (opcode1->unit == IU)
636 if (opcode2->unit == IU)
637 as_fatal ("Two IU instructions may not be executed in parallel");
638 as_warn ("Swapping instruction order");
639 insn = FM00 | (insn2 << 15) | insn1;
642 else if (opcode2->unit == MU)
644 if (opcode1->unit == MU)
645 as_fatal ("Two MU instructions may not be executed in parallel");
646 as_warn ("Swapping instruction order");
647 insn = FM00 | (insn2 << 15) | insn1;
651 insn = FM00 | (insn1 << 15) | insn2;
654 case 2: /* sequential */
655 if (opcode1->unit == IU)
656 as_fatal ("IU instruction may not be in the left container");
657 insn = FM01 | (insn1 << 15) | insn2;
660 case 3: /* reverse sequential */
661 if (opcode2->unit == MU)
662 as_fatal ("MU instruction may not be in the right container");
663 insn = FM10 | (insn1 << 15) | insn2;
666 as_fatal("unknown execution type passed to write_2_short()");
669 /* printf("INSN: %08x\n",insn); */
671 number_to_chars_bigendian (f, insn, 4);
675 bfd_reloc_code_real_type reloc;
676 for (i=0; i < fx->fc; i++)
678 reloc = get_reloc((struct d10v_operand *)&d10v_operands[fx->fix[i].reloc]);
681 if ( (reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
682 fx->fix[i].reloc |= 1024;
685 printf("fix_new_exp: where:%x reloc:%d\n ",f - frag_now->fr_literal,fx->fix[i].reloc);
686 print_expr_1(stdout,&(fx->fix[i].exp));
689 fix_new_exp (frag_now,
690 f - frag_now->fr_literal,
705 /* This is the main entry point for the machine-dependent assembler. str points to a
706 machine-dependent instruction. This function is supposed to emit the frags/bytes
707 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
708 and leaves the difficult stuff to do_assemble().
711 static unsigned long prev_insn;
712 static struct d10v_opcode *prev_opcode = 0;
713 static subsegT prev_subseg;
714 static segT prev_seg;
720 struct d10v_opcode *opcode;
722 int extype=0; /* execution type; parallel, etc */
723 static int etype=0; /* saved extype. used for multiline instructions */
726 /* printf("md_assemble: str=%s\n",str); */
730 /* look for the special multiple instruction separators */
731 str2 = strstr (str, "||");
736 str2 = strstr (str, "->");
741 str2 = strstr (str, "<-");
746 /* str2 points to the separator, if one */
751 /* if two instructions are present and we already have one saved
752 then first write it out */
754 write_1_short (prev_opcode, prev_insn, fixups->next);
756 /* assemble first instruction and save it */
757 prev_insn = do_assemble (str, &prev_opcode);
759 as_fatal ("can't find opcode ");
760 fixups = fixups->next;
765 insn = do_assemble (str, &opcode);
773 as_fatal ("can't find opcode ");
782 /* if this is a long instruction, write it and any previous short instruction */
783 if (opcode->format & LONG_OPCODE)
786 as_fatal("Unable to mix instructions as specified");
789 write_1_short (prev_opcode, prev_insn, fixups->next);
792 write_long (opcode, insn, fixups);
797 if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
799 /* no instructions saved */
805 as_fatal("Unable to mix instructions as specified");
806 /* save off last instruction so it may be packed on next pass */
807 prev_opcode = opcode;
810 prev_subseg = now_subseg;
811 fixups = fixups->next;
816 /* do_assemble assembles a single instruction and returns an opcode */
817 /* it returns -1 (an invalid opcode) on error */
820 do_assemble (str, opcode)
822 struct d10v_opcode **opcode;
824 struct d10v_opcode *next_opcode;
825 unsigned char *op_start, *save;
826 unsigned char *op_end;
828 int nlen = 0, i, match, numops;
829 expressionS myops[6];
832 /* printf("do_assemble: str=%s\n",str); */
834 /* Drop leading whitespace */
838 /* find the opcode end */
839 for (op_start = op_end = (unsigned char *) (str);
842 && !is_end_of_line[*op_end] && *op_end != ' ';
845 name[nlen] = op_start[nlen];
853 /* find the first opcode with the proper name */
854 *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
856 as_fatal ("unknown opcode: %s",name);
858 save = input_line_pointer;
859 input_line_pointer = op_end;
861 /* get all the operands and save them as expressions */
862 numops = get_operands (myops);
864 /* now see if the operand is a fake. If so, find the correct size */
865 /* instruction, if possible */
867 if ((*opcode)->format == OPCODE_FAKE)
869 int opnum = (*opcode)->operands[0];
870 if (myops[opnum].X_op == O_constant)
872 next_opcode=(*opcode)+1;
873 for (i=0; (*opcode)->operands[i+1]; i++)
875 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
876 int flags = d10v_operands[next_opcode->operands[opnum]].flags;
877 if (!check_range (myops[opnum].X_add_number, bits, flags))
887 /* not a constant, so use a long instruction */
888 next_opcode = (*opcode)+2;
892 *opcode = next_opcode;
894 as_fatal ("value out of range");
898 /* now search the opcode table table for one with operands */
899 /* that matches what we've got */
903 for (i = 0; (*opcode)->operands[i]; i++)
905 int flags = d10v_operands[(*opcode)->operands[i]].flags;
906 int X_op = myops[i].X_op;
907 int num = myops[i].X_add_number;
915 if (flags & OPERAND_REG)
917 if ((X_op != O_register) ||
918 ((flags & OPERAND_ACC) != (num & OPERAND_ACC)) ||
919 ((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) ||
920 ((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL)))
927 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
928 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
929 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
930 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
931 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
939 /* we're only done if the operands matched AND there
940 are no more to check */
941 if (match && myops[i].X_op==0)
944 next_opcode = (*opcode)+1;
945 if (next_opcode->opcode == 0)
947 if (strcmp(next_opcode->name, (*opcode)->name))
949 (*opcode) = next_opcode;
955 as_bad ("bad opcode or operands");
959 /* Check that all registers that are required to be even are. */
960 /* Also, if any operands were marked as registers, but were really symbols */
962 for (i=0; (*opcode)->operands[i]; i++)
964 if ((d10v_operands[(*opcode)->operands[i]].flags & OPERAND_EVEN) &&
965 (myops[i].X_add_number & 1))
966 as_fatal("Register number must be EVEN");
967 if (myops[i].X_op == O_register)
969 if (!(d10v_operands[(*opcode)->operands[i]].flags & OPERAND_REG))
971 myops[i].X_op = O_symbol;
972 myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
973 myops[i].X_add_number = 0;
974 myops[i].X_op_symbol = NULL;
979 input_line_pointer = save;
981 /* at this point, we have "opcode" pointing to the opcode entry in the
982 d10v opcode table, with myops filled out with the operands. */
983 insn = build_insn ((*opcode), myops, 0);
984 /* printf("sub-insn = %lx\n",insn); */
990 /* if while processing a fixup, a reloc really needs to be created */
991 /* then it is done here */
994 tc_gen_reloc (seg, fixp)
999 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1000 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1001 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1002 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1003 if (reloc->howto == (reloc_howto_type *) NULL)
1005 as_bad_where (fixp->fx_file, fixp->fx_line,
1006 "reloc %d not supported by object file format", (int)fixp->fx_r_type);
1009 reloc->addend = fixp->fx_addnumber;
1010 /* printf("tc_gen_reloc: addr=%x addend=%x\n", reloc->address, reloc->addend); */
1015 md_estimate_size_before_relax (fragp, seg)
1024 md_pcrel_from_section (fixp, sec)
1029 /* return fixp->fx_frag->fr_address + fixp->fx_where; */
1033 md_apply_fix3 (fixp, valuep, seg)
1044 if (fixp->fx_addsy == (symbolS *) NULL)
1049 else if (fixp->fx_pcrel)
1053 value = fixp->fx_offset;
1054 if (fixp->fx_subsy != (symbolS *) NULL)
1056 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1057 value -= S_GET_VALUE (fixp->fx_subsy);
1060 /* We don't actually support subtracting a symbol. */
1061 as_bad_where (fixp->fx_file, fixp->fx_line,
1062 "expression too complex");
1067 /* printf("md_apply_fix: value=0x%x type=%d\n", value, fixp->fx_r_type); */
1069 op_type = fixp->fx_r_type;
1073 fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1077 fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
1079 /* Fetch the instruction, insert the fully resolved operand
1080 value, and stuff the instruction back again. */
1081 where = fixp->fx_frag->fr_literal + fixp->fx_where;
1082 insn = bfd_getb32 ((unsigned char *) where);
1084 switch (fixp->fx_r_type)
1086 case BFD_RELOC_D10V_10_PCREL_L:
1087 case BFD_RELOC_D10V_10_PCREL_R:
1088 case BFD_RELOC_D10V_18_PCREL:
1089 /* instruction addresses are always right-shifted by 2
1091 if (!fixp->fx_pcrel)
1092 value -= fixp->fx_where;
1097 /* printf(" insn=%x value=%x where=%x pcrel=%x\n",insn,value,fixp->fx_where,fixp->fx_pcrel); */
1099 insn = d10v_insert_operand (insn, op_type, (offsetT)value, left);
1101 /* printf(" new insn=%x\n",insn); */
1103 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1108 fixp->fx_addnumber = value;
1113 /* d10v_cleanup() is called after the assembler has finished parsing the input
1114 file or after a label is defined. Because the D10V assembler sometimes saves short
1115 instructions to see if it can package them with the next instruction, there may
1116 be a short instruction that still needs written. */
1124 if ( prev_opcode && (done || (now_seg == prev_seg) && (now_subseg == prev_subseg)))
1127 subseg = now_subseg;
1128 subseg_set (prev_seg, prev_subseg);
1129 write_1_short (prev_opcode, prev_insn, fixups);
1130 subseg_set (seg, subseg);