1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
30 const char comment_chars[] = ";";
31 const char line_comment_chars[] = "#";
32 const char line_separator_chars[] = "";
33 const char *md_shortopts = "O";
34 const char EXP_CHARS[] = "eE";
35 const char FLT_CHARS[] = "dD";
39 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
40 && (X)->X_op_symbol != NULL \
41 && symbol_constant_p ((X)->X_op_symbol) \
42 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
43 #define AT_WORD_RIGHT_SHIFT 2
46 #define MAX_INSN_FIXUPS (5)
53 bfd_reloc_code_real_type reloc;
56 typedef struct _fixups
59 struct d10v_fixup fix[MAX_INSN_FIXUPS];
63 static Fixups FixUps[2];
64 static Fixups *fixups;
66 static int do_not_ignore_hash = 0;
68 typedef int packing_type;
69 #define PACK_UNSPEC (0) /* Packing order not specified. */
70 #define PACK_PARALLEL (1) /* "||" */
71 #define PACK_LEFT_RIGHT (2) /* "->" */
72 #define PACK_RIGHT_LEFT (3) /* "<-" */
73 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
75 /* True if instruction swapping warnings should be inhibited.
77 static boolean flag_warn_suppress_instructionswap;
79 /* True if instruction packing should be performed when --gstabs is specified.
80 --gstabs-packing, --no-gstabs-packing. */
81 static boolean flag_allow_gstabs_packing = 1;
83 /* Local functions. */
84 static int reg_name_search PARAMS ((char *name));
85 static int register_name PARAMS ((expressionS *expressionP));
86 static int check_range PARAMS ((unsigned long num, int bits, int flags));
87 static int postfix PARAMS ((char *p));
88 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
89 static int get_operands PARAMS ((expressionS exp[]));
90 static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
91 static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
92 static void write_long PARAMS ((unsigned long insn, Fixups *fx));
93 static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
94 static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
95 struct d10v_opcode *opcode2, unsigned long insn2, packing_type exec_type, Fixups *fx));
96 static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
97 static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
98 offsetT value, int left, fixS *fix));
99 static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
100 struct d10v_opcode *opcode2, unsigned long insn2,
101 packing_type exec_type));
102 static symbolS * find_symbol_matching_register PARAMS ((expressionS *));
104 struct option md_longopts[] =
106 #define OPTION_NOWARNSWAP (OPTION_MD_BASE)
107 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
108 #define OPTION_GSTABSPACKING (OPTION_MD_BASE + 1)
109 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING},
110 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
111 #define OPTION_NOGSTABSPACKING (OPTION_MD_BASE + 2)
112 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING},
113 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
114 {NULL, no_argument, NULL, 0}
117 size_t md_longopts_size = sizeof (md_longopts);
119 static void d10v_dot_word PARAMS ((int));
121 /* The target specific pseudo-ops which we support. */
122 const pseudo_typeS md_pseudo_table[] =
124 { "word", d10v_dot_word, 2 },
128 /* Opcode hash table. */
129 static struct hash_control *d10v_hash;
131 /* Do a binary search of the d10v_predefined_registers array to see if
132 NAME is a valid regiter name. Return the register number from the
133 array on success, or -1 on failure. */
136 reg_name_search (name)
139 int middle, low, high;
143 high = d10v_reg_name_cnt () - 1;
147 middle = (low + high) / 2;
148 cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
154 return d10v_predefined_registers[middle].value;
160 /* Check the string at input_line_pointer
161 to see if it is a valid register name. */
164 register_name (expressionP)
165 expressionS *expressionP;
168 char c, *p = input_line_pointer;
171 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
178 /* Look to see if it's in the register table. */
179 reg_number = reg_name_search (input_line_pointer);
182 expressionP->X_op = O_register;
183 /* Temporarily store a pointer to the string here. */
184 expressionP->X_op_symbol = (symbolS *) input_line_pointer;
185 expressionP->X_add_number = reg_number;
186 input_line_pointer = p;
195 check_range (num, bits, flags)
203 /* Don't bother checking 16-bit values. */
207 if (flags & OPERAND_SHIFT)
209 /* All special shift operands are unsigned and <= 16.
210 We allow 0 for now. */
217 if (flags & OPERAND_SIGNED)
219 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
220 if (flags & RESTRICTED_NUM3)
222 if ((long) num < -2 || (long) num > 3)
227 max = (1 << (bits - 1)) - 1;
228 min = - (1 << (bits - 1));
229 if (((long) num > max) || ((long) num < min))
235 max = (1 << bits) - 1;
237 if (((long) num > max) || ((long) num < min))
244 md_show_usage (stream)
247 fprintf (stream, _("D10V options:\n\
248 -O Optimize. Will do some operations in parallel.\n\
249 --gstabs-packing Pack adjacent short instructions together even\n\
250 when --gstabs is specified. On by default.\n\
251 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
252 instructions together.\n"));
256 md_parse_option (c, arg)
258 char *arg ATTRIBUTE_UNUSED;
263 /* Optimize. Will attempt to parallelize operations. */
266 case OPTION_NOWARNSWAP:
267 flag_warn_suppress_instructionswap = 1;
269 case OPTION_GSTABSPACKING:
270 flag_allow_gstabs_packing = 1;
272 case OPTION_NOGSTABSPACKING:
273 flag_allow_gstabs_packing = 0;
282 md_undefined_symbol (name)
283 char *name ATTRIBUTE_UNUSED;
288 /* Turn a string in input_line_pointer into a floating point constant
289 of type TYPE, and store the appropriate bytes in *LITP. The number
290 of LITTLENUMS emitted is stored in *SIZEP. An error message is
291 returned, or NULL on OK. */
294 md_atof (type, litP, sizeP)
300 LITTLENUM_TYPE words[4];
314 return _("bad call to md_atof");
317 t = atof_ieee (input_line_pointer, type, words);
319 input_line_pointer = t;
323 for (i = 0; i < prec; i++)
325 md_number_to_chars (litP, (valueT) words[i], 2);
332 md_convert_frag (abfd, sec, fragP)
333 bfd *abfd ATTRIBUTE_UNUSED;
334 asection *sec ATTRIBUTE_UNUSED;
335 fragS *fragP ATTRIBUTE_UNUSED;
341 md_section_align (seg, addr)
345 int align = bfd_get_section_alignment (stdoutput, seg);
346 return ((addr + (1 << align) - 1) & (-1 << align));
352 char *prev_name = "";
353 struct d10v_opcode *opcode;
354 d10v_hash = hash_new ();
356 /* Insert unique names into hash table. The D10v instruction set
357 has many identical opcode names that have different opcodes based
358 on the operands. This hash table then provides a quick index to
359 the first opcode with a particular name in the opcode table. */
361 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
363 if (strcmp (prev_name, opcode->name))
365 prev_name = (char *) opcode->name;
366 hash_insert (d10v_hash, opcode->name, (char *) opcode);
371 FixUps[0].next = &FixUps[1];
372 FixUps[1].next = &FixUps[0];
375 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
376 from an expression. */
382 while (*p != '-' && *p != '+')
384 if (*p == 0 || *p == '\n' || *p == '\r')
403 static bfd_reloc_code_real_type
405 struct d10v_operand *op;
412 if (op->flags & OPERAND_ADDR)
415 return (BFD_RELOC_D10V_10_PCREL_R);
417 return (BFD_RELOC_D10V_18_PCREL);
420 return (BFD_RELOC_16);
423 /* Parse a string of operands. Return an array of expressions. */
429 char *p = input_line_pointer;
436 while (*p == ' ' || *p == '\t' || *p == ',')
438 if (*p == 0 || *p == '\n' || *p == '\r')
446 exp[numops].X_op = O_absent;
450 exp[numops].X_add_number = OPERAND_ATPAR;
455 exp[numops].X_add_number = OPERAND_ATMINUS;
459 exp[numops].X_add_number = OPERAND_ATSIGN;
468 /* Just skip the trailing paren. */
473 input_line_pointer = p;
475 /* Check to see if it might be a register name. */
476 if (!register_name (&exp[numops]))
478 /* Parse as an expression. */
481 /* Any expression that involves the indirect addressing
482 cannot also involve immediate addressing. Therefore
483 the use of the hash character is illegal. */
484 int save = do_not_ignore_hash;
485 do_not_ignore_hash = 1;
487 expression (&exp[numops]);
489 do_not_ignore_hash = save;
492 expression (&exp[numops]);
495 if (strncasecmp (input_line_pointer, "@word", 5) == 0)
497 input_line_pointer += 5;
498 if (exp[numops].X_op == O_register)
500 /* If it looked like a register name but was followed by
501 "@word" then it was really a symbol, so change it to
503 exp[numops].X_op = O_symbol;
504 exp[numops].X_add_symbol =
505 symbol_find_or_make ((char *) exp[numops].X_op_symbol);
508 /* Check for identifier@word+constant. */
509 if (*input_line_pointer == '-' || *input_line_pointer == '+')
512 expression (&new_exp);
513 exp[numops].X_add_number = new_exp.X_add_number;
516 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
519 memset (&new_exp, 0, sizeof new_exp);
520 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
521 new_exp.X_op = O_constant;
522 new_exp.X_unsigned = 1;
523 exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
524 exp[numops].X_op = O_right_shift;
527 know (AT_WORD_P (&exp[numops]));
530 if (exp[numops].X_op == O_illegal)
531 as_bad (_("illegal operand"));
532 else if (exp[numops].X_op == O_absent)
533 as_bad (_("missing operand"));
536 p = input_line_pointer;
541 case -1: /* Postdecrement mode. */
542 exp[numops].X_op = O_absent;
543 exp[numops++].X_add_number = OPERAND_MINUS;
545 case 1: /* Postincrement mode. */
546 exp[numops].X_op = O_absent;
547 exp[numops++].X_add_number = OPERAND_PLUS;
551 exp[numops].X_op = 0;
556 d10v_insert_operand (insn, op_type, value, left, fix)
565 shift = d10v_operands[op_type].shift;
569 bits = d10v_operands[op_type].bits;
571 /* Truncate to the proper number of bits. */
572 if (check_range (value, bits, d10v_operands[op_type].flags))
573 as_bad_where (fix->fx_file, fix->fx_line,
574 _("operand out of range: %d"), value);
576 value &= 0x7FFFFFFF >> (31 - bits);
577 insn |= (value << shift);
582 /* Take a pointer to the opcode entry in the opcode table and the
583 array of operand expressions. Return the instruction. */
586 build_insn (opcode, opers, insn)
587 struct d10v_opcode *opcode;
591 int i, bits, shift, flags, format;
592 unsigned long number;
594 /* The insn argument is only used for the DIVS kludge. */
599 insn = opcode->opcode;
600 format = opcode->format;
603 for (i = 0; opcode->operands[i]; i++)
605 flags = d10v_operands[opcode->operands[i]].flags;
606 bits = d10v_operands[opcode->operands[i]].bits;
607 shift = d10v_operands[opcode->operands[i]].shift;
608 number = opers[i].X_add_number;
610 if (flags & OPERAND_REG)
612 number &= REGISTER_MASK;
613 if (format == LONG_L)
617 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
619 /* Now create a fixup. */
621 if (fixups->fc >= MAX_INSN_FIXUPS)
622 as_fatal (_("too many fixups"));
624 if (AT_WORD_P (&opers[i]))
626 /* Reconize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
627 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
628 opers[i].X_op = O_symbol;
629 opers[i].X_op_symbol = NULL; /* Should free it. */
630 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
631 that, it is aligned with the symbol's value. Later,
632 BFD_RELOC_D10V_18 will right shift (symbol_value +
634 number <<= AT_WORD_RIGHT_SHIFT;
635 opers[i].X_add_number = number;
638 fixups->fix[fixups->fc].reloc =
639 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
641 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
642 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
643 fixups->fix[fixups->fc].size = 2;
645 fixups->fix[fixups->fc].size = 4;
647 fixups->fix[fixups->fc].exp = opers[i];
648 fixups->fix[fixups->fc].operand = opcode->operands[i];
649 fixups->fix[fixups->fc].pcrel =
650 (flags & OPERAND_ADDR) ? true : false;
654 /* Truncate to the proper number of bits. */
655 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
656 as_bad (_("operand out of range: %d"), number);
657 number &= 0x7FFFFFFF >> (31 - bits);
658 insn = insn | (number << shift);
661 /* kludge: for DIVS, we need to put the operands in twice */
662 /* on the second pass, format is changed to LONG_R to force
663 the second set of operands to not be shifted over 15. */
664 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
665 insn = build_insn (opcode, opers, insn);
670 /* Write out a long form instruction. */
673 write_long (insn, fx)
678 char *f = frag_more (4);
681 number_to_chars_bigendian (f, insn, 4);
683 for (i = 0; i < fx->fc; i++)
685 if (fx->fix[i].reloc)
687 where = f - frag_now->fr_literal;
688 if (fx->fix[i].size == 2)
691 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
692 fx->fix[i].operand |= 4096;
694 fix_new_exp (frag_now,
699 fx->fix[i].operand|2048);
705 /* Write out a short form instruction by itself. */
708 write_1_short (opcode, insn, fx)
709 struct d10v_opcode *opcode;
713 char *f = frag_more (4);
716 if (opcode->exec_type & PARONLY)
717 as_fatal (_("Instruction must be executed in parallel with another instruction."));
719 /* The other container needs to be NOP. */
720 /* According to 4.3.1: for FM=00, sub-instructions performed only
721 by IU cannot be encoded in L-container. */
722 if (opcode->unit == IU)
723 insn |= FM00 | (NOP << 15); /* Right container. */
725 insn = FM00 | (insn << 15) | NOP; /* Left container. */
727 number_to_chars_bigendian (f, insn, 4);
728 for (i = 0; i < fx->fc; i++)
730 if (fx->fix[i].reloc)
732 where = f - frag_now->fr_literal;
733 if (fx->fix[i].size == 2)
736 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
737 fx->fix[i].operand |= 4096;
739 /* If it's an R reloc, we may have to switch it to L. */
740 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
741 && (opcode->unit != IU))
742 fx->fix[i].operand |= 1024;
744 fix_new_exp (frag_now,
749 fx->fix[i].operand|2048);
755 /* Expects two short instructions.
756 If possible, writes out both as a single packed instruction.
757 Otherwise, writes out the first one, packed with a NOP.
758 Returns number of instructions not written out. */
761 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
762 struct d10v_opcode *opcode1, *opcode2;
763 unsigned long insn1, insn2;
764 packing_type exec_type;
771 if ((exec_type != PACK_PARALLEL)
772 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
773 as_fatal (_("Instruction must be executed in parallel"));
775 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
776 as_fatal (_("Long instructions may not be combined."));
780 case PACK_UNSPEC: /* Order not specified. */
781 if (opcode1->exec_type & ALONE)
783 /* Case of a short branch on a separate GAS line.
785 write_1_short (opcode1, insn1, fx->next);
789 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
792 if (opcode1->unit == IU)
793 insn = FM00 | (insn2 << 15) | insn1;
794 else if (opcode2->unit == MU)
795 insn = FM00 | (insn2 << 15) | insn1;
798 insn = FM00 | (insn1 << 15) | insn2;
799 /* Advance over dummy fixup since packed insn1 in L. */
803 else if (opcode1->unit == IU)
804 /* Reverse sequential with IU opcode1 on right and done first. */
805 insn = FM10 | (insn2 << 15) | insn1;
808 /* Sequential with non-IU opcode1 on left and done first. */
809 insn = FM01 | (insn1 << 15) | insn2;
810 /* Advance over dummy fixup since packed insn1 in L. */
816 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
818 (_("One of these instructions may not be executed in parallel."));
819 if (opcode1->unit == IU)
821 if (opcode2->unit == IU)
822 as_fatal (_("Two IU instructions may not be executed in parallel"));
823 if (!flag_warn_suppress_instructionswap)
824 as_warn (_("Swapping instruction order"));
825 insn = FM00 | (insn2 << 15) | insn1;
827 else if (opcode2->unit == MU)
829 if (opcode1->unit == MU)
830 as_fatal (_("Two MU instructions may not be executed in parallel"));
831 if (!flag_warn_suppress_instructionswap)
832 as_warn (_("Swapping instruction order"));
833 insn = FM00 | (insn2 << 15) | insn1;
837 insn = FM00 | (insn1 << 15) | insn2;
838 /* Advance over dummy fixup since packed insn1 in L. */
843 case PACK_LEFT_RIGHT:
844 if (opcode1->unit != IU)
845 insn = FM01 | (insn1 << 15) | insn2;
846 else if (opcode2->unit == MU || opcode2->unit == EITHER)
848 if (!flag_warn_suppress_instructionswap)
849 as_warn (_("Swapping instruction order"));
850 insn = FM10 | (insn2 << 15) | insn1;
853 as_fatal (_("IU instruction may not be in the left container"));
854 if (opcode1->exec_type & ALONE)
855 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
856 /* Advance over dummy fixup. */
860 case PACK_RIGHT_LEFT:
861 if (opcode2->unit != MU)
862 insn = FM10 | (insn1 << 15) | insn2;
863 else if (opcode1->unit == IU || opcode1->unit == EITHER)
865 if (!flag_warn_suppress_instructionswap)
866 as_warn (_("Swapping instruction order"));
867 insn = FM01 | (insn2 << 15) | insn1;
870 as_fatal (_("MU instruction may not be in the right container"));
871 if (opcode2->exec_type & ALONE)
872 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
873 /* Advance over dummy fixup. */
878 as_fatal (_("unknown execution type passed to write_2_short()"));
882 number_to_chars_bigendian (f, insn, 4);
884 /* Process fixup chains.
885 Note that the packing code above advanced fx conditionally.
886 dlindsay@cygnus.com: There's something subtle going on here involving
887 _dummy_first_bfd_reloc_code_real. This is related to the
888 difference between BFD_RELOC_D10V_10_PCREL_R and _L, ie whether
889 a fixup is done in the L or R container. A bug in this code
890 can pass Plum Hall fine, yet still affect hand-written assembler. */
892 for (j = 0; j < 2; j++)
894 for (i = 0; i < fx->fc; i++)
896 if (fx->fix[i].reloc)
898 where = f - frag_now->fr_literal;
899 if (fx->fix[i].size == 2)
902 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0))
903 fx->fix[i].operand |= 1024;
905 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
906 fx->fix[i].operand |= 4096;
908 fix_new_exp (frag_now,
913 fx->fix[i].operand|2048);
922 /* Check 2 instructions and determine if they can be safely
923 executed in parallel. Return 1 if they can be. */
926 parallel_ok (op1, insn1, op2, insn2, exec_type)
927 struct d10v_opcode *op1, *op2;
928 unsigned long insn1, insn2;
929 packing_type exec_type;
931 int i, j, flags, mask, shift, regno;
932 unsigned long ins, mod[2], used[2];
933 struct d10v_opcode *op;
935 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
936 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
937 || (op1->unit == BOTH) || (op2->unit == BOTH)
938 || (op1->unit == IU && op2->unit == IU)
939 || (op1->unit == MU && op2->unit == MU))
942 /* If this is auto parallization, and either instruction is a branch,
944 if (exec_type == PACK_UNSPEC
945 && (op1->exec_type & ALONE || op2->exec_type & ALONE))
948 /* The idea here is to create two sets of bitmasks (mod and used)
949 which indicate which registers are modified or used by each
950 instruction. The operation can only be done in parallel if
951 instruction 1 and instruction 2 modify different registers, and
952 the first instruction does not modify registers that the second
953 is using (The second instruction can modify registers that the
954 first is using as they are only written back after the first
955 instruction has completed). Accesses to control registers, PSW,
956 and memory are treated as accesses to a single register. So if
957 both instructions write memory or if the first instruction writes
958 memory and the second reads, then they cannot be done in
959 parallel. Likewise, if the first instruction mucks with the psw
960 and the second reads the PSW (which includes C, F0, and F1), then
961 they cannot operate safely in parallel. */
963 /* The bitmasks (mod and used) look like this (bit 31 = MSB). */
966 /* cr (not psw) 18 */
970 for (j = 0; j < 2; j++)
982 mod[j] = used[j] = 0;
983 if (op->exec_type & BRANCH_LINK)
986 for (i = 0; op->operands[i]; i++)
988 flags = d10v_operands[op->operands[i]].flags;
989 shift = d10v_operands[op->operands[i]].shift;
990 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
991 if (flags & OPERAND_REG)
993 regno = (ins >> shift) & mask;
994 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
996 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
1003 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
1006 if (flags & OPERAND_DEST)
1008 mod[j] |= 1 << regno;
1009 if (flags & OPERAND_EVEN)
1010 mod[j] |= 1 << (regno + 1);
1014 used[j] |= 1 << regno;
1015 if (flags & OPERAND_EVEN)
1016 used[j] |= 1 << (regno + 1);
1018 /* Auto inc/dec also modifies the register. */
1019 if (op->operands[i + 1] != 0
1020 && (d10v_operands[op->operands[i + 1]].flags
1021 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
1022 mod[j] |= 1 << regno;
1025 else if (flags & OPERAND_ATMINUS)
1027 /* SP implicitly used/modified. */
1032 if (op->exec_type & RMEM)
1034 else if (op->exec_type & WMEM)
1036 else if (op->exec_type & RF0)
1038 else if (op->exec_type & WF0)
1040 else if (op->exec_type & WCAR)
1043 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
1048 /* This is the main entry point for the machine-dependent assembler.
1049 STR points to a machine-dependent instruction. This function is
1050 supposed to emit the frags/bytes it assembles to. For the D10V, it
1051 mostly handles the special VLIW parsing and packing and leaves the
1052 difficult stuff to do_assemble(). */
1054 static unsigned long prev_insn;
1055 static struct d10v_opcode *prev_opcode = 0;
1056 static subsegT prev_subseg;
1057 static segT prev_seg = 0;;
1063 /* etype is saved extype. For multi-line instructions. */
1065 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
1067 struct d10v_opcode *opcode;
1071 if (etype == PACK_UNSPEC)
1073 /* Look for the special multiple instruction separators. */
1074 str2 = strstr (str, "||");
1076 extype = PACK_PARALLEL;
1079 str2 = strstr (str, "->");
1081 extype = PACK_LEFT_RIGHT;
1084 str2 = strstr (str, "<-");
1086 extype = PACK_RIGHT_LEFT;
1089 /* STR2 points to the separator, if there is one. */
1094 /* If two instructions are present and we already have one saved,
1095 then first write out the saved one. */
1098 /* Assemble first instruction and save it. */
1099 prev_insn = do_assemble (str, &prev_opcode);
1101 prev_subseg = now_subseg;
1102 if (prev_insn == (unsigned long) -1)
1103 as_fatal (_("can't find opcode "));
1104 fixups = fixups->next;
1109 insn = do_assemble (str, &opcode);
1110 if (insn == (unsigned long) -1)
1112 if (extype != PACK_UNSPEC)
1117 as_fatal (_("can't find opcode "));
1120 if (etype != PACK_UNSPEC)
1123 etype = PACK_UNSPEC;
1126 /* If this is a long instruction, write it and any previous short
1128 if (opcode->format & LONG_OPCODE)
1130 if (extype != PACK_UNSPEC)
1131 as_fatal (_("Unable to mix instructions as specified"));
1133 write_long (insn, fixups);
1140 && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1144 && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
1146 /* No instructions saved. */
1151 if (extype != PACK_UNSPEC)
1152 as_fatal (_("Unable to mix instructions as specified"));
1153 /* Save last instruction so it may be packed on next pass. */
1154 prev_opcode = opcode;
1157 prev_subseg = now_subseg;
1158 fixups = fixups->next;
1162 /* Assemble a single instruction.
1163 Return an opcode, or -1 (an invalid opcode) on error. */
1165 static unsigned long
1166 do_assemble (str, opcode)
1168 struct d10v_opcode **opcode;
1170 unsigned char *op_start, *save;
1171 unsigned char *op_end;
1174 expressionS myops[6];
1177 /* Drop leading whitespace. */
1181 /* Find the opcode end. */
1182 for (op_start = op_end = (unsigned char *) (str);
1185 && !is_end_of_line[*op_end] && *op_end != ' ';
1188 name[nlen] = tolower (op_start[nlen]);
1196 /* Find the first opcode with the proper name. */
1197 *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
1198 if (*opcode == NULL)
1199 as_fatal (_("unknown opcode: %s"), name);
1201 save = input_line_pointer;
1202 input_line_pointer = op_end;
1203 *opcode = find_opcode (*opcode, myops);
1206 input_line_pointer = save;
1208 insn = build_insn ((*opcode), myops, 0);
1212 /* Find the symbol which has the same name as the register in EXP. */
1215 find_symbol_matching_register (exp)
1220 if (exp->X_op != O_register)
1223 /* Find the name of the register. */
1224 for (i = d10v_reg_name_cnt (); i--;)
1225 if (d10v_predefined_registers[i].value == exp->X_add_number)
1231 /* Now see if a symbol has been defined with the same name. */
1232 return symbol_find (d10v_predefined_registers[i].name);
1235 /* Get a pointer to an entry in the opcode table.
1236 The function must look at all opcodes with the same name and use
1237 the operands to choose the correct opcode. */
1239 static struct d10v_opcode *
1240 find_opcode (opcode, myops)
1241 struct d10v_opcode *opcode;
1242 expressionS myops[];
1245 struct d10v_opcode *next_opcode;
1247 /* Get all the operands and save them as expressions. */
1248 get_operands (myops);
1250 /* Now see if the operand is a fake. If so, find the correct size
1251 instruction, if possible. */
1252 if (opcode->format == OPCODE_FAKE)
1254 int opnum = opcode->operands[0];
1257 if (myops[opnum].X_op == O_register)
1259 myops[opnum].X_op = O_symbol;
1260 myops[opnum].X_add_symbol =
1261 symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
1262 myops[opnum].X_add_number = 0;
1263 myops[opnum].X_op_symbol = NULL;
1266 next_opcode = opcode + 1;
1268 /* If the first operand is supposed to be a register, make sure
1269 we got a valid one. */
1270 flags = d10v_operands[next_opcode->operands[0]].flags;
1271 if (flags & OPERAND_REG)
1273 int X_op = myops[0].X_op;
1274 int num = myops[0].X_add_number;
1276 if (X_op != O_register
1278 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1279 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL)))
1281 as_bad (_("bad opcode or operands"));
1286 if (myops[opnum].X_op == O_constant
1287 || (myops[opnum].X_op == O_symbol
1288 && S_IS_DEFINED (myops[opnum].X_add_symbol)
1289 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
1291 for (i = 0; opcode->operands[i + 1]; i++)
1293 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1294 int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1295 if (flags & OPERAND_ADDR)
1298 if (myops[opnum].X_op == O_constant)
1300 if (!check_range (myops[opnum].X_add_number, bits, flags))
1307 unsigned long current_position;
1308 unsigned long symbol_position;
1309 unsigned long value;
1310 boolean found_symbol;
1312 /* Calculate the address of the current instruction
1313 and the address of the symbol. Do this by summing
1314 the offsets of previous frags until we reach the
1315 frag containing the symbol, and the current frag. */
1316 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
1317 found_symbol = false;
1320 obstack_next_free (&frchain_now->frch_obstack)
1321 - frag_now->fr_literal;
1322 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
1324 for (f = frchain_now->frch_root; f; f = f->fr_next)
1326 current_position += f->fr_fix + f->fr_offset;
1329 found_symbol = true;
1332 symbol_position += f->fr_fix + f->fr_offset;
1335 value = symbol_position;
1337 if (flags & OPERAND_ADDR)
1338 value -= current_position;
1340 if (AT_WORD_P (&myops[opnum]))
1345 if (!check_range (value, bits, flags))
1349 else if (!check_range (value, bits, flags))
1354 as_fatal (_("value out of range"));
1358 /* Not a constant, so use a long instruction. */
1365 /* Now search the opcode table table for one with operands
1366 that matches what we've got. */
1370 for (i = 0; opcode->operands[i]; i++)
1372 int flags = d10v_operands[opcode->operands[i]].flags;
1373 int X_op = myops[i].X_op;
1374 int num = myops[i].X_add_number;
1382 if (flags & OPERAND_REG)
1384 if ((X_op != O_register)
1386 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1387 | OPERAND_FFLAG | OPERAND_CFLAG
1388 | OPERAND_CONTROL)))
1395 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1396 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1397 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1398 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1399 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
1405 /* Unfortunatly, for the indirect operand in
1406 instructions such as ``ldb r1, @(c,r14)'' this
1407 function can be passed X_op == O_register (because
1408 'c' is a valid register name). However we cannot
1409 just ignore the case when X_op == O_register but
1410 flags & OPERAND_REG is null, so we check to see if a
1411 symbol of the same name as the register exists. If
1412 the symbol does exist, then the parser was unable to
1413 distinguish the two cases and we fix things here.
1416 if (!(flags & OPERAND_REG) && (X_op == O_register))
1418 symbolS *sym = find_symbol_matching_register (&myops[i]);
1422 myops[i].X_op = X_op = O_symbol;
1423 myops[i].X_add_symbol = sym;
1427 (_("illegal operand - register name found where none expected"));
1431 /* We're only done if the operands matched so far AND there
1432 are no more to check. */
1433 if (match && myops[i].X_op == 0)
1438 next_opcode = opcode + 1;
1440 if (next_opcode->opcode == 0)
1443 if (strcmp (next_opcode->name, opcode->name))
1446 opcode = next_opcode;
1452 as_bad (_("bad opcode or operands"));
1456 /* Check that all registers that are required to be even are.
1457 Also, if any operands were marked as registers, but were really symbols,
1459 for (i = 0; opcode->operands[i]; i++)
1461 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1462 (myops[i].X_add_number & 1))
1463 as_fatal (_("Register number must be EVEN"));
1464 if (myops[i].X_op == O_register)
1466 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1468 myops[i].X_op = O_symbol;
1469 myops[i].X_add_symbol =
1470 symbol_find_or_make ((char *) myops[i].X_op_symbol);
1471 myops[i].X_add_number = 0;
1472 myops[i].X_op_symbol = NULL;
1479 /* If while processing a fixup, a reloc really needs to be created.
1480 Then it is done here. */
1483 tc_gen_reloc (seg, fixp)
1484 asection *seg ATTRIBUTE_UNUSED;
1488 reloc = (arelent *) xmalloc (sizeof (arelent));
1489 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1490 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1491 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1492 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1493 if (reloc->howto == (reloc_howto_type *) NULL)
1495 as_bad_where (fixp->fx_file, fixp->fx_line,
1496 _("reloc %d not supported by object file format"),
1497 (int) fixp->fx_r_type);
1501 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1502 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1503 reloc->address = fixp->fx_offset;
1505 reloc->addend = fixp->fx_addnumber;
1511 md_estimate_size_before_relax (fragp, seg)
1512 fragS *fragp ATTRIBUTE_UNUSED;
1513 asection *seg ATTRIBUTE_UNUSED;
1520 md_pcrel_from_section (fixp, sec)
1524 if (fixp->fx_addsy != (symbolS *) NULL
1525 && (!S_IS_DEFINED (fixp->fx_addsy)
1526 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1528 return fixp->fx_frag->fr_address + fixp->fx_where;
1532 md_apply_fix3 (fixp, valuep, seg)
1535 segT seg ATTRIBUTE_UNUSED;
1543 if (fixp->fx_addsy == (symbolS *) NULL)
1548 else if (fixp->fx_pcrel)
1552 value = fixp->fx_offset;
1553 if (fixp->fx_subsy != (symbolS *) NULL)
1555 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1556 value -= S_GET_VALUE (fixp->fx_subsy);
1559 /* We don't actually support subtracting a symbol. */
1560 as_bad_where (fixp->fx_file, fixp->fx_line,
1561 _("expression too complex"));
1566 op_type = fixp->fx_r_type;
1573 fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1576 else if (op_type & 4096)
1579 fixp->fx_r_type = BFD_RELOC_D10V_18;
1583 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
1586 /* Fetch the instruction, insert the fully resolved operand
1587 value, and stuff the instruction back again. */
1588 where = fixp->fx_frag->fr_literal + fixp->fx_where;
1589 insn = bfd_getb32 ((unsigned char *) where);
1591 switch (fixp->fx_r_type)
1593 case BFD_RELOC_D10V_10_PCREL_L:
1594 case BFD_RELOC_D10V_10_PCREL_R:
1595 case BFD_RELOC_D10V_18_PCREL:
1596 case BFD_RELOC_D10V_18:
1597 /* Instruction addresses are always right-shifted by 2. */
1598 value >>= AT_WORD_RIGHT_SHIFT;
1599 if (fixp->fx_size == 2)
1600 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1603 struct d10v_opcode *rep, *repi;
1605 rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
1606 repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
1607 if ((insn & FM11) == FM11
1608 && ( (repi != NULL && (insn & repi->mask) == (unsigned) repi->opcode)
1609 || (rep != NULL && (insn & rep->mask) == (unsigned) rep->opcode))
1612 (_("line %d: rep or repi must include at least 4 instructions"),
1615 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixp);
1616 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1620 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1623 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1626 case BFD_RELOC_VTABLE_INHERIT:
1627 case BFD_RELOC_VTABLE_ENTRY:
1632 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1633 fixp->fx_line, fixp->fx_r_type);
1638 /* d10v_cleanup() is called after the assembler has finished parsing
1639 the input file, when a label is read from the input file, or when a
1640 stab directive is output. Because the D10V assembler sometimes
1641 saves short instructions to see if it can package them with the
1642 next instruction, there may be a short instruction that still needs
1645 NOTE: accesses a global, etype.
1646 NOTE: invoked by various macros such as md_cleanup: see. */
1654 /* If cleanup was invoked because the assembler encountered, e.g., a
1655 user label, we write out the pending instruction, if any. If it
1656 was invoked because the assembler is outputting a piece of line
1657 debugging information, though, we write out the pending
1658 instruction only if the --no-gstabs-packing command line switch
1659 has been specified. */
1661 && etype == PACK_UNSPEC
1662 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
1665 subseg = now_subseg;
1668 subseg_set (prev_seg, prev_subseg);
1670 write_1_short (prev_opcode, prev_insn, fixups->next);
1672 subseg_set (seg, subseg);
1678 /* Like normal .word, except support @word. */
1679 /* Clobbers input_line_pointer, checks end-of-line. */
1682 d10v_dot_word (dummy)
1683 int dummy ATTRIBUTE_UNUSED;
1688 if (is_it_end_of_statement ())
1690 demand_empty_rest_of_line ();
1697 if (!strncasecmp (input_line_pointer, "@word", 5))
1699 exp.X_add_number = 0;
1700 input_line_pointer += 5;
1703 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1704 &exp, 0, BFD_RELOC_D10V_18);
1707 emit_expr (&exp, 2);
1709 while (*input_line_pointer++ == ',');
1711 input_line_pointer--; /* Put terminator back into stream. */
1712 demand_empty_rest_of_line ();
1715 /* Mitsubishi asked that we support some old syntax that apparently
1716 had immediate operands starting with '#'. This is in some of their
1717 sample code but is not documented (although it appears in some
1718 examples in their assembler manual). For now, we'll solve this
1719 compatibility problem by simply ignoring any '#' at the beginning
1722 /* Operands that begin with '#' should fall through to here. */
1726 md_operand (expressionP)
1727 expressionS *expressionP;
1729 if (*input_line_pointer == '#' && ! do_not_ignore_hash)
1731 input_line_pointer++;
1732 expression (expressionP);
1737 d10v_fix_adjustable (fixP)
1740 if (fixP->fx_addsy == NULL)
1743 /* Prevent all adjustments to global symbols. */
1744 if (S_IS_EXTERN (fixP->fx_addsy))
1746 if (S_IS_WEAK (fixP->fx_addsy))
1749 /* We need the symbol name for the VTABLE entries. */
1750 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1751 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1758 d10v_force_relocation (fixp)
1761 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1762 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)