1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
3 Copyright (C) 1996 Free Software Foundation.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "opcode/d10v.h"
29 const char comment_chars[] = ";";
30 const char line_comment_chars[] = "#";
31 const char line_separator_chars[] = "";
32 const char *md_shortopts = "O";
33 const char EXP_CHARS[] = "eE";
34 const char FLT_CHARS[] = "dD";
41 #define MAX_INSN_FIXUPS (5)
48 bfd_reloc_code_real_type reloc;
51 typedef struct _fixups
54 struct d10v_fixup fix[MAX_INSN_FIXUPS];
58 static Fixups FixUps[2];
59 static Fixups *fixups;
62 static int reg_name_search PARAMS ((char *name));
63 static int register_name PARAMS ((expressionS *expressionP));
64 static int check_range PARAMS ((unsigned long num, int bits, int flags));
65 static int postfix PARAMS ((char *p));
66 static bfd_reloc_code_real_type get_reloc PARAMS ((struct d10v_operand *op));
67 static int get_operands PARAMS ((expressionS exp[]));
68 static struct d10v_opcode *find_opcode PARAMS ((struct d10v_opcode *opcode, expressionS ops[]));
69 static unsigned long build_insn PARAMS ((struct d10v_opcode *opcode, expressionS *opers, unsigned long insn));
70 static void write_long PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
71 static void write_1_short PARAMS ((struct d10v_opcode *opcode, unsigned long insn, Fixups *fx));
72 static int write_2_short PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
73 struct d10v_opcode *opcode2, unsigned long insn2, int exec_type, Fixups *fx));
74 static unsigned long do_assemble PARAMS ((char *str, struct d10v_opcode **opcode));
75 static unsigned long d10v_insert_operand PARAMS (( unsigned long insn, int op_type,
76 offsetT value, int left, fixS *fix));
77 static int parallel_ok PARAMS ((struct d10v_opcode *opcode1, unsigned long insn1,
78 struct d10v_opcode *opcode2, unsigned long insn2,
81 struct option md_longopts[] = {
82 {NULL, no_argument, NULL, 0}
84 size_t md_longopts_size = sizeof(md_longopts);
86 static void d10v_dot_word PARAMS ((int));
88 /* The target specific pseudo-ops which we support. */
89 const pseudo_typeS md_pseudo_table[] =
91 { "word", d10v_dot_word, 2 },
95 /* Opcode hash table. */
96 static struct hash_control *d10v_hash;
98 /* reg_name_search does a binary search of the pre_defined_registers
99 array to see if "name" is a valid regiter name. Returns the register
100 number from the array on success, or -1 on failure. */
103 reg_name_search (name)
106 int middle, low, high;
110 high = reg_name_cnt() - 1;
114 middle = (low + high) / 2;
115 cmp = strcasecmp (name, pre_defined_registers[middle].name);
121 return pre_defined_registers[middle].value;
127 /* register_name() checks the string at input_line_pointer
128 to see if it is a valid register name */
131 register_name (expressionP)
132 expressionS *expressionP;
135 char c, *p = input_line_pointer;
137 while (*p && *p!='\n' && *p!='\r' && *p !=',' && *p!=' ' && *p!=')')
144 /* look to see if it's in the register table */
145 reg_number = reg_name_search (input_line_pointer);
148 expressionP->X_op = O_register;
149 /* temporarily store a pointer to the string here */
150 expressionP->X_op_symbol = (struct symbol *)input_line_pointer;
151 expressionP->X_add_number = reg_number;
152 input_line_pointer = p;
162 check_range (num, bits, flags)
170 /* don't bother checking 16-bit values */
174 if (flags & OPERAND_SHIFT)
176 /* all special shift operands are unsigned */
177 /* and <= 16. We allow 0 for now. */
184 if (flags & OPERAND_SIGNED)
186 max = (1 << (bits - 1))-1;
187 min = - (1 << (bits - 1));
188 if (((long)num > max) || ((long)num < min))
193 max = (1 << bits) - 1;
195 if ((num > max) || (num < min))
203 md_show_usage (stream)
206 fprintf(stream, "D10V options:\n\
207 -O optimize. Will do some operations in parallel.\n");
211 md_parse_option (c, arg)
218 /* Optimize. Will attempt to parallelize operations */
228 md_undefined_symbol (name)
234 /* Turn a string in input_line_pointer into a floating point constant of type
235 type, and store the appropriate bytes in *litP. The number of LITTLENUMS
236 emitted is stored in *sizeP . An error message is returned, or NULL on OK.
239 md_atof (type, litP, sizeP)
245 LITTLENUM_TYPE words[4];
259 return "bad call to md_atof";
262 t = atof_ieee (input_line_pointer, type, words);
264 input_line_pointer = t;
268 for (i = 0; i < prec; i++)
270 md_number_to_chars (litP, (valueT) words[i], 2);
277 md_convert_frag (abfd, sec, fragP)
286 md_section_align (seg, addr)
290 int align = bfd_get_section_alignment (stdoutput, seg);
291 return ((addr + (1 << align) - 1) & (-1 << align));
298 char *prev_name = "";
299 struct d10v_opcode *opcode;
300 d10v_hash = hash_new();
302 /* Insert unique names into hash table. The D10v instruction set
303 has many identical opcode names that have different opcodes based
304 on the operands. This hash table then provides a quick index to
305 the first opcode with a particular name in the opcode table. */
307 for (opcode = (struct d10v_opcode *)d10v_opcodes; opcode->name; opcode++)
309 if (strcmp (prev_name, opcode->name))
311 prev_name = (char *)opcode->name;
312 hash_insert (d10v_hash, opcode->name, (char *) opcode);
317 FixUps[0].next = &FixUps[1];
318 FixUps[1].next = &FixUps[0];
322 /* this function removes the postincrement or postdecrement
323 operator ( '+' or '-' ) from an expression */
325 static int postfix (p)
328 while (*p != '-' && *p != '+')
330 if (*p==0 || *p=='\n' || *p=='\r')
350 static bfd_reloc_code_real_type
352 struct d10v_operand *op;
359 if (op->flags & OPERAND_ADDR)
362 return (BFD_RELOC_D10V_10_PCREL_R);
364 return (BFD_RELOC_D10V_18_PCREL);
367 return (BFD_RELOC_16);
371 /* get_operands parses a string of operands and returns
372 an array of expressions */
378 char *p = input_line_pointer;
384 while (*p == ' ' || *p == '\t' || *p == ',')
386 if (*p==0 || *p=='\n' || *p=='\r')
392 exp[numops].X_op = O_absent;
396 exp[numops].X_add_number = OPERAND_ATPAR;
401 exp[numops].X_add_number = OPERAND_ATMINUS;
405 exp[numops].X_add_number = OPERAND_ATSIGN;
414 /* just skip the trailing paren */
419 input_line_pointer = p;
421 /* check to see if it might be a register name */
422 if (!register_name (&exp[numops]))
424 /* parse as an expression */
425 expression (&exp[numops]);
428 if (!strncasecmp (input_line_pointer, "@word", 5))
430 if (exp[numops].X_op == O_register)
432 /* if it looked like a register name but was followed by "@word" */
433 /* then it was really a symbol, so change it to one */
434 exp[numops].X_op = O_symbol;
435 exp[numops].X_add_symbol = symbol_find_or_make ((char *)exp[numops].X_op_symbol);
436 exp[numops].X_op_symbol = NULL;
438 exp[numops].X_add_number = AT_WORD;
439 input_line_pointer += 5;
442 if (exp[numops].X_op == O_illegal)
443 as_bad ("illegal operand");
444 else if (exp[numops].X_op == O_absent)
445 as_bad ("missing operand");
448 p = input_line_pointer;
453 case -1: /* postdecrement mode */
454 exp[numops].X_op = O_absent;
455 exp[numops++].X_add_number = OPERAND_MINUS;
457 case 1: /* postincrement mode */
458 exp[numops].X_op = O_absent;
459 exp[numops++].X_add_number = OPERAND_PLUS;
463 exp[numops].X_op = 0;
468 d10v_insert_operand (insn, op_type, value, left, fix)
477 shift = d10v_operands[op_type].shift;
481 bits = d10v_operands[op_type].bits;
483 /* truncate to the proper number of bits */
484 if (check_range (value, bits, d10v_operands[op_type].flags))
485 as_bad_where (fix->fx_file, fix->fx_line, "operand out of range: %d", value);
487 value &= 0x7FFFFFFF >> (31 - bits);
488 insn |= (value << shift);
494 /* build_insn takes a pointer to the opcode entry in the opcode table
495 and the array of operand expressions and returns the instruction */
498 build_insn (opcode, opers, insn)
499 struct d10v_opcode *opcode;
503 int i, bits, shift, flags, format;
506 /* the insn argument is only used for the DIVS kludge */
511 insn = opcode->opcode;
512 format = opcode->format;
515 for (i=0;opcode->operands[i];i++)
517 flags = d10v_operands[opcode->operands[i]].flags;
518 bits = d10v_operands[opcode->operands[i]].bits;
519 shift = d10v_operands[opcode->operands[i]].shift;
520 number = opers[i].X_add_number;
522 if (flags & OPERAND_REG)
524 number &= REGISTER_MASK;
525 if (format == LONG_L)
529 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
531 /* now create a fixup */
533 if (fixups->fc >= MAX_INSN_FIXUPS)
534 as_fatal ("too many fixups");
536 if (opers[i].X_op == O_symbol && number == AT_WORD)
538 number = opers[i].X_add_number = 0;
539 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
541 fixups->fix[fixups->fc].reloc =
542 get_reloc((struct d10v_operand *)&d10v_operands[opcode->operands[i]]);
544 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
545 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
546 fixups->fix[fixups->fc].size = 2;
548 fixups->fix[fixups->fc].size = 4;
550 fixups->fix[fixups->fc].exp = opers[i];
551 fixups->fix[fixups->fc].operand = opcode->operands[i];
552 fixups->fix[fixups->fc].pcrel = (flags & OPERAND_ADDR) ? true : false;
556 /* truncate to the proper number of bits */
557 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
558 as_bad("operand out of range: %d",number);
559 number &= 0x7FFFFFFF >> (31 - bits);
560 insn = insn | (number << shift);
563 /* kludge: for DIVS, we need to put the operands in twice */
564 /* on the second pass, format is changed to LONG_R to force */
565 /* the second set of operands to not be shifted over 15 */
566 if ((opcode->opcode == OPCODE_DIVS) && (format==LONG_L))
567 insn = build_insn (opcode, opers, insn);
572 /* write out a long form instruction */
574 write_long (opcode, insn, fx)
575 struct d10v_opcode *opcode;
580 char *f = frag_more(4);
583 number_to_chars_bigendian (f, insn, 4);
585 for (i=0; i < fx->fc; i++)
587 if (fx->fix[i].reloc)
589 where = f - frag_now->fr_literal;
590 if (fx->fix[i].size == 2)
593 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
594 fx->fix[i].operand |= 4096;
596 fix_new_exp (frag_now,
601 fx->fix[i].operand|2048);
608 /* write out a short form instruction by itself */
610 write_1_short (opcode, insn, fx)
611 struct d10v_opcode *opcode;
615 char *f = frag_more(4);
618 if (opcode->exec_type & PARONLY)
619 as_fatal ("Instruction must be executed in parallel with another instruction.");
621 /* the other container needs to be NOP */
622 /* according to 4.3.1: for FM=00, sub-instructions performed only
623 by IU cannot be encoded in L-container. */
624 if (opcode->unit == IU)
625 insn |= FM00 | (NOP << 15); /* right container */
627 insn = FM00 | (insn << 15) | NOP; /* left container */
629 number_to_chars_bigendian (f, insn, 4);
630 for (i=0; i < fx->fc; i++)
632 if (fx->fix[i].reloc)
634 where = f - frag_now->fr_literal;
635 if (fx->fix[i].size == 2)
638 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
639 fx->fix[i].operand |= 4096;
641 /* if it's an R reloc, we may have to switch it to L */
642 if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (opcode->unit != IU) )
643 fx->fix[i].operand |= 1024;
645 fix_new_exp (frag_now,
650 fx->fix[i].operand|2048);
656 /* write out a short form instruction if possible */
657 /* return number of instructions not written out */
659 write_2_short (opcode1, insn1, opcode2, insn2, exec_type, fx)
660 struct d10v_opcode *opcode1, *opcode2;
661 unsigned long insn1, insn2;
669 if ( (exec_type != 1) && ((opcode1->exec_type & PARONLY)
670 || (opcode2->exec_type & PARONLY)))
671 as_fatal("Instruction must be executed in parallel");
673 if ( (opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
674 as_fatal ("Long instructions may not be combined.");
676 if(opcode1->exec_type & BRANCH_LINK && opcode2->exec_type != PARONLY)
678 /* subroutines must be called from 32-bit boundaries */
679 /* so the return address will be correct */
680 write_1_short (opcode1, insn1, fx->next);
686 case 0: /* order not specified */
687 if ( Optimizing && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
690 if (opcode1->unit == IU)
691 insn = FM00 | (insn2 << 15) | insn1;
692 else if (opcode2->unit == MU)
693 insn = FM00 | (insn2 << 15) | insn1;
696 insn = FM00 | (insn1 << 15) | insn2;
700 else if (opcode1->unit == IU)
702 /* reverse sequential */
703 insn = FM10 | (insn2 << 15) | insn1;
708 insn = FM01 | (insn1 << 15) | insn2;
712 case 1: /* parallel */
713 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
714 as_fatal ("One of these instructions may not be executed in parallel.");
716 if (opcode1->unit == IU)
718 if (opcode2->unit == IU)
719 as_fatal ("Two IU instructions may not be executed in parallel");
720 as_warn ("Swapping instruction order");
721 insn = FM00 | (insn2 << 15) | insn1;
723 else if (opcode2->unit == MU)
725 if (opcode1->unit == MU)
726 as_fatal ("Two MU instructions may not be executed in parallel");
727 as_warn ("Swapping instruction order");
728 insn = FM00 | (insn2 << 15) | insn1;
732 insn = FM00 | (insn1 << 15) | insn2;
736 case 2: /* sequential */
737 if (opcode1->unit == IU)
738 as_fatal ("IU instruction may not be in the left container");
739 insn = FM01 | (insn1 << 15) | insn2;
742 case 3: /* reverse sequential */
743 if (opcode2->unit == MU)
744 as_fatal ("MU instruction may not be in the right container");
745 insn = FM10 | (insn1 << 15) | insn2;
749 as_fatal("unknown execution type passed to write_2_short()");
753 number_to_chars_bigendian (f, insn, 4);
757 for (i=0; i < fx->fc; i++)
759 if (fx->fix[i].reloc)
761 where = f - frag_now->fr_literal;
762 if (fx->fix[i].size == 2)
765 if ( (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R) && (j == 0) )
766 fx->fix[i].operand |= 1024;
768 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
769 fx->fix[i].operand |= 4096;
771 fix_new_exp (frag_now,
776 fx->fix[i].operand|2048);
786 /* Check 2 instructions and determine if they can be safely */
787 /* executed in parallel. Returns 1 if they can be. */
789 parallel_ok (op1, insn1, op2, insn2, exec_type)
790 struct d10v_opcode *op1, *op2;
791 unsigned long insn1, insn2;
794 int i, j, flags, mask, shift, regno;
795 unsigned long ins, mod[2], used[2];
796 struct d10v_opcode *op;
798 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
799 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
800 || (op1->unit == BOTH) || (op2->unit == BOTH)
801 || (op1->unit == IU && op2->unit == IU)
802 || (op1->unit == MU && op2->unit == MU))
805 /* If the first instruction is a branch and this is auto parallazation,
806 don't combine with any second instruction. */
807 if (exec_type == 0 && (op1->exec_type & BRANCH) != 0)
810 /* The idea here is to create two sets of bitmasks (mod and used) */
811 /* which indicate which registers are modified or used by each instruction. */
812 /* The operation can only be done in parallel if instruction 1 and instruction 2 */
813 /* modify different registers, and neither instruction modifies any registers */
814 /* the other is using. Accesses to control registers, PSW, and memory are treated */
815 /* as accesses to a single register. So if both instructions write memory or one */
816 /* instruction writes memory and the other reads, then they cannot be done in parallel. */
817 /* Likewise, if one instruction mucks with the psw and the other reads the PSW */
818 /* (which includes C, F0, and F1), then they cannot operate safely in parallel. */
820 /* the bitmasks (mod and used) look like this (bit 31 = MSB) */
823 /* cr (not psw) 18 */
839 mod[j] = used[j] = 0;
840 if (op->exec_type & BRANCH_LINK)
843 for (i = 0; op->operands[i]; i++)
845 flags = d10v_operands[op->operands[i]].flags;
846 shift = d10v_operands[op->operands[i]].shift;
847 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
848 if (flags & OPERAND_REG)
850 regno = (ins >> shift) & mask;
851 if (flags & OPERAND_ACC)
853 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
860 else if (flags & OPERAND_FLAG)
863 if ( flags & OPERAND_DEST )
865 mod[j] |= 1 << regno;
866 if (flags & OPERAND_EVEN)
867 mod[j] |= 1 << (regno + 1);
871 used[j] |= 1 << regno ;
872 if (flags & OPERAND_EVEN)
873 used[j] |= 1 << (regno + 1);
877 if (op->exec_type & RMEM)
879 else if (op->exec_type & WMEM)
881 else if (op->exec_type & RF0)
883 else if (op->exec_type & WF0)
885 else if (op->exec_type & WCAR)
888 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0 && (mod[1] & used[0]) == 0)
894 /* This is the main entry point for the machine-dependent assembler. str points to a
895 machine-dependent instruction. This function is supposed to emit the frags/bytes
896 it assembles to. For the D10V, it mostly handles the special VLIW parsing and packing
897 and leaves the difficult stuff to do_assemble().
900 static unsigned long prev_insn;
901 static struct d10v_opcode *prev_opcode = 0;
902 static subsegT prev_subseg;
903 static segT prev_seg = 0;;
909 struct d10v_opcode *opcode;
911 int extype=0; /* execution type; parallel, etc */
912 static int etype=0; /* saved extype. used for multiline instructions */
917 /* look for the special multiple instruction separators */
918 str2 = strstr (str, "||");
923 str2 = strstr (str, "->");
928 str2 = strstr (str, "<-");
933 /* str2 points to the separator, if one */
938 /* if two instructions are present and we already have one saved
939 then first write it out */
942 /* assemble first instruction and save it */
943 prev_insn = do_assemble (str, &prev_opcode);
945 as_fatal ("can't find opcode ");
946 fixups = fixups->next;
951 insn = do_assemble (str, &opcode);
959 as_fatal ("can't find opcode ");
968 /* if this is a long instruction, write it and any previous short instruction */
969 if (opcode->format & LONG_OPCODE)
972 as_fatal("Unable to mix instructions as specified");
974 write_long (opcode, insn, fixups);
979 if (prev_opcode && prev_seg && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
982 if (prev_opcode && (write_2_short (prev_opcode, prev_insn, opcode, insn, extype, fixups) == 0))
984 /* no instructions saved */
990 as_fatal("Unable to mix instructions as specified");
991 /* save off last instruction so it may be packed on next pass */
992 prev_opcode = opcode;
995 prev_subseg = now_subseg;
996 fixups = fixups->next;
1001 /* do_assemble assembles a single instruction and returns an opcode */
1002 /* it returns -1 (an invalid opcode) on error */
1004 static unsigned long
1005 do_assemble (str, opcode)
1007 struct d10v_opcode **opcode;
1009 unsigned char *op_start, *save;
1010 unsigned char *op_end;
1013 expressionS myops[6];
1016 /* Drop leading whitespace */
1020 /* find the opcode end */
1021 for (op_start = op_end = (unsigned char *) (str);
1024 && !is_end_of_line[*op_end] && *op_end != ' ';
1027 name[nlen] = tolower(op_start[nlen]);
1035 /* find the first opcode with the proper name */
1036 *opcode = (struct d10v_opcode *)hash_find (d10v_hash, name);
1037 if (*opcode == NULL)
1038 as_fatal ("unknown opcode: %s",name);
1040 save = input_line_pointer;
1041 input_line_pointer = op_end;
1042 *opcode = find_opcode (*opcode, myops);
1045 input_line_pointer = save;
1047 insn = build_insn ((*opcode), myops, 0);
1051 /* find_opcode() gets a pointer to an entry in the opcode table. */
1052 /* It must look at all opcodes with the same name and use the operands */
1053 /* to choose the correct opcode. */
1055 static struct d10v_opcode *
1056 find_opcode (opcode, myops)
1057 struct d10v_opcode *opcode;
1058 expressionS myops[];
1061 struct d10v_opcode *next_opcode;
1063 /* get all the operands and save them as expressions */
1064 get_operands (myops);
1066 /* now see if the operand is a fake. If so, find the correct size */
1067 /* instruction, if possible */
1068 if (opcode->format == OPCODE_FAKE)
1070 int opnum = opcode->operands[0];
1072 if (myops[opnum].X_op == O_register)
1074 myops[opnum].X_op = O_symbol;
1075 myops[opnum].X_add_symbol = symbol_find_or_make ((char *)myops[opnum].X_op_symbol);
1076 myops[opnum].X_add_number = 0;
1077 myops[opnum].X_op_symbol = NULL;
1080 if (myops[opnum].X_op == O_constant || (myops[opnum].X_op == O_symbol &&
1081 S_IS_DEFINED(myops[opnum].X_add_symbol) &&
1082 (S_GET_SEGMENT(myops[opnum].X_add_symbol) == now_seg)))
1084 next_opcode=opcode+1;
1085 for (i=0; opcode->operands[i+1]; i++)
1087 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1088 int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1089 if (flags & OPERAND_ADDR)
1091 if (myops[opnum].X_op == O_constant)
1093 if (!check_range (myops[opnum].X_add_number, bits, flags))
1100 /* calculate the current address by running through the previous frags */
1101 /* and adding our current offset */
1102 for (value = 0, f = frchain_now->frch_root; f; f = f->fr_next)
1103 value += f->fr_fix + f->fr_offset;
1105 if (flags & OPERAND_ADDR)
1106 value = S_GET_VALUE(myops[opnum].X_add_symbol) - value -
1107 (obstack_next_free(&frchain_now->frch_obstack) - frag_now->fr_literal);
1109 value = S_GET_VALUE(myops[opnum].X_add_symbol);
1111 if (myops[opnum].X_add_number == AT_WORD)
1116 if (!check_range (value, bits, flags))
1120 else if (!check_range (value, bits, flags))
1125 as_fatal ("value out of range");
1129 /* not a constant, so use a long instruction */
1136 /* now search the opcode table table for one with operands */
1137 /* that matches what we've got */
1141 for (i = 0; opcode->operands[i]; i++)
1143 int flags = d10v_operands[opcode->operands[i]].flags;
1144 int X_op = myops[i].X_op;
1145 int num = myops[i].X_add_number;
1153 if (flags & OPERAND_REG)
1155 if ((X_op != O_register) ||
1156 ((flags & OPERAND_ACC) != (num & OPERAND_ACC)) ||
1157 ((flags & OPERAND_FLAG) != (num & OPERAND_FLAG)) ||
1158 ((flags & OPERAND_CONTROL) != (num & OPERAND_CONTROL)))
1165 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1166 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1167 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1168 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1169 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || (num != OPERAND_ATSIGN))))
1175 /* we're only done if the operands matched so far AND there
1176 are no more to check */
1177 if (match && myops[i].X_op==0)
1182 next_opcode = opcode+1;
1183 if (next_opcode->opcode == 0)
1185 if (strcmp(next_opcode->name, opcode->name))
1187 opcode = next_opcode;
1193 as_bad ("bad opcode or operands");
1197 /* Check that all registers that are required to be even are. */
1198 /* Also, if any operands were marked as registers, but were really symbols */
1199 /* fix that here. */
1200 for (i=0; opcode->operands[i]; i++)
1202 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1203 (myops[i].X_add_number & 1))
1204 as_fatal("Register number must be EVEN");
1205 if (myops[i].X_op == O_register)
1207 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1209 myops[i].X_op = O_symbol;
1210 myops[i].X_add_symbol = symbol_find_or_make ((char *)myops[i].X_op_symbol);
1211 myops[i].X_add_number = 0;
1212 myops[i].X_op_symbol = NULL;
1219 /* if while processing a fixup, a reloc really needs to be created */
1220 /* then it is done here */
1223 tc_gen_reloc (seg, fixp)
1228 reloc = (arelent *) bfd_alloc_by_size_t (stdoutput, sizeof (arelent));
1229 reloc->sym_ptr_ptr = &fixp->fx_addsy->bsym;
1230 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1231 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1232 if (reloc->howto == (reloc_howto_type *) NULL)
1234 as_bad_where (fixp->fx_file, fixp->fx_line,
1235 "reloc %d not supported by object file format", (int)fixp->fx_r_type);
1238 reloc->addend = fixp->fx_addnumber;
1243 md_estimate_size_before_relax (fragp, seg)
1252 md_pcrel_from_section (fixp, sec)
1256 if (fixp->fx_addsy != (symbolS *)NULL && !S_IS_DEFINED (fixp->fx_addsy))
1258 return fixp->fx_frag->fr_address + fixp->fx_where;
1262 md_apply_fix3 (fixp, valuep, seg)
1273 if (fixp->fx_addsy == (symbolS *) NULL)
1278 else if (fixp->fx_pcrel)
1282 value = fixp->fx_offset;
1283 if (fixp->fx_subsy != (symbolS *) NULL)
1285 if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section)
1286 value -= S_GET_VALUE (fixp->fx_subsy);
1289 /* We don't actually support subtracting a symbol. */
1290 as_bad_where (fixp->fx_file, fixp->fx_line,
1291 "expression too complex");
1296 op_type = fixp->fx_r_type;
1303 fixp->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1306 else if (op_type & 4096)
1309 fixp->fx_r_type = BFD_RELOC_D10V_18;
1312 fixp->fx_r_type = get_reloc((struct d10v_operand *)&d10v_operands[op_type]);
1315 /* Fetch the instruction, insert the fully resolved operand
1316 value, and stuff the instruction back again. */
1317 where = fixp->fx_frag->fr_literal + fixp->fx_where;
1318 insn = bfd_getb32 ((unsigned char *) where);
1320 switch (fixp->fx_r_type)
1322 case BFD_RELOC_D10V_10_PCREL_L:
1323 case BFD_RELOC_D10V_10_PCREL_R:
1324 case BFD_RELOC_D10V_18_PCREL:
1325 case BFD_RELOC_D10V_18:
1326 /* instruction addresses are always right-shifted by 2 */
1328 if (fixp->fx_size == 2)
1329 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1332 insn = d10v_insert_operand (insn, op_type, (offsetT)value, left, fixp);
1333 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1337 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1340 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1343 as_fatal ("line %d: unknown relocation type: 0x%x",fixp->fx_line,fixp->fx_r_type);
1348 /* d10v_cleanup() is called after the assembler has finished parsing the input
1349 file or after a label is defined. Because the D10V assembler sometimes saves short
1350 instructions to see if it can package them with the next instruction, there may
1351 be a short instruction that still needs written. */
1361 subseg = now_subseg;
1362 subseg_set (prev_seg, prev_subseg);
1363 write_1_short (prev_opcode, prev_insn, fixups->next);
1364 subseg_set (seg, subseg);
1370 /* Like normal .word, except support @word */
1371 /* clobbers input_line_pointer, checks end-of-line. */
1373 d10v_dot_word (nbytes)
1374 register int nbytes; /* 1=.byte, 2=.word, 4=.long */
1377 bfd_reloc_code_real_type reloc;
1381 if (is_it_end_of_statement ())
1383 demand_empty_rest_of_line ();
1390 if (!strncasecmp (input_line_pointer, "@word", 5))
1392 exp.X_add_number = 0;
1393 input_line_pointer += 5;
1396 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1397 &exp, 0, BFD_RELOC_D10V_18);
1400 emit_expr (&exp, 2);
1402 while (*input_line_pointer++ == ',');
1404 input_line_pointer--; /* Put terminator back into stream. */
1405 demand_empty_rest_of_line ();
1409 /* Mitsubishi asked that we support some old syntax that apparently */
1410 /* had immediate operands starting with '#'. This is in some of their */
1411 /* sample code but is not documented (although it appears in some */
1412 /* examples in their assembler manual). For now, we'll solve this */
1413 /* compatibility problem by simply ignoring any '#' at the beginning */
1414 /* of an operand. */
1416 /* operands that begin with '#' should fall through to here */
1420 md_operand (expressionP)
1421 expressionS *expressionP;
1423 if (*input_line_pointer == '#')
1425 input_line_pointer++;
1426 expression (expressionP);