1 /* tc-d10v.c -- Assembler code for the Mitsubishi D10V
2 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "safe-ctype.h"
26 #include "opcode/d10v.h"
29 const char comment_chars[] = ";";
30 const char line_comment_chars[] = "#";
31 const char line_separator_chars[] = "";
32 const char *md_shortopts = "O";
33 const char EXP_CHARS[] = "eE";
34 const char FLT_CHARS[] = "dD";
38 #define AT_WORD_P(X) ((X)->X_op == O_right_shift \
39 && (X)->X_op_symbol != NULL \
40 && symbol_constant_p ((X)->X_op_symbol) \
41 && S_GET_VALUE ((X)->X_op_symbol) == AT_WORD_RIGHT_SHIFT)
42 #define AT_WORD_RIGHT_SHIFT 2
45 #define MAX_INSN_FIXUPS 5
53 bfd_reloc_code_real_type reloc;
56 typedef struct _fixups
59 struct d10v_fixup fix[MAX_INSN_FIXUPS];
63 static Fixups FixUps[2];
64 static Fixups *fixups;
66 static int do_not_ignore_hash = 0;
68 typedef int packing_type;
69 #define PACK_UNSPEC (0) /* Packing order not specified. */
70 #define PACK_PARALLEL (1) /* "||" */
71 #define PACK_LEFT_RIGHT (2) /* "->" */
72 #define PACK_RIGHT_LEFT (3) /* "<-" */
73 static packing_type etype = PACK_UNSPEC; /* Used by d10v_cleanup. */
75 /* TRUE if instruction swapping warnings should be inhibited.
77 static bfd_boolean flag_warn_suppress_instructionswap;
79 /* TRUE if instruction packing should be performed when --gstabs is specified.
80 --gstabs-packing, --no-gstabs-packing. */
81 static bfd_boolean flag_allow_gstabs_packing = 1;
83 /* Local functions. */
87 OPTION_NOWARNSWAP = OPTION_MD_BASE,
89 OPTION_NOGSTABSPACKING
92 struct option md_longopts[] =
94 {"nowarnswap", no_argument, NULL, OPTION_NOWARNSWAP},
95 {"gstabspacking", no_argument, NULL, OPTION_GSTABSPACKING},
96 {"gstabs-packing", no_argument, NULL, OPTION_GSTABSPACKING},
97 {"nogstabspacking", no_argument, NULL, OPTION_NOGSTABSPACKING},
98 {"no-gstabs-packing", no_argument, NULL, OPTION_NOGSTABSPACKING},
99 {NULL, no_argument, NULL, 0}
102 size_t md_longopts_size = sizeof (md_longopts);
104 /* Opcode hash table. */
105 static struct hash_control *d10v_hash;
107 /* Do a binary search of the d10v_predefined_registers array to see if
108 NAME is a valid regiter name. Return the register number from the
109 array on success, or -1 on failure. */
112 reg_name_search (char *name)
114 int middle, low, high;
118 high = d10v_reg_name_cnt () - 1;
122 middle = (low + high) / 2;
123 cmp = strcasecmp (name, d10v_predefined_registers[middle].name);
129 return d10v_predefined_registers[middle].value;
135 /* Check the string at input_line_pointer
136 to see if it is a valid register name. */
139 register_name (expressionS *expressionP)
142 char c, *p = input_line_pointer;
145 && *p != '\n' && *p != '\r' && *p != ',' && *p != ' ' && *p != ')')
152 /* Look to see if it's in the register table. */
153 reg_number = reg_name_search (input_line_pointer);
156 expressionP->X_op = O_register;
157 /* Temporarily store a pointer to the string here. */
158 expressionP->X_op_symbol = (symbolS *) input_line_pointer;
159 expressionP->X_add_number = reg_number;
160 input_line_pointer = p;
169 check_range (unsigned long num, int bits, int flags)
174 /* Don't bother checking 16-bit values. */
178 if (flags & OPERAND_SHIFT)
180 /* All special shift operands are unsigned and <= 16.
181 We allow 0 for now. */
188 if (flags & OPERAND_SIGNED)
190 /* Signed 3-bit integers are restricted to the (-2, 3) range. */
191 if (flags & RESTRICTED_NUM3)
193 if ((long) num < -2 || (long) num > 3)
198 max = (1 << (bits - 1)) - 1;
199 min = - (1 << (bits - 1));
200 if (((long) num > max) || ((long) num < min))
206 max = (1 << bits) - 1;
208 if (((long) num > max) || ((long) num < min))
215 md_show_usage (FILE *stream)
217 fprintf (stream, _("D10V options:\n\
218 -O Optimize. Will do some operations in parallel.\n\
219 --gstabs-packing Pack adjacent short instructions together even\n\
220 when --gstabs is specified. On by default.\n\
221 --no-gstabs-packing If --gstabs is specified, do not pack adjacent\n\
222 instructions together.\n"));
226 md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
231 /* Optimize. Will attempt to parallelize operations. */
234 case OPTION_NOWARNSWAP:
235 flag_warn_suppress_instructionswap = 1;
237 case OPTION_GSTABSPACKING:
238 flag_allow_gstabs_packing = 1;
240 case OPTION_NOGSTABSPACKING:
241 flag_allow_gstabs_packing = 0;
250 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
255 /* Turn a string in input_line_pointer into a floating point constant
256 of type TYPE, and store the appropriate bytes in *LITP. The number
257 of LITTLENUMS emitted is stored in *SIZEP. An error message is
258 returned, or NULL on OK. */
261 md_atof (int type, char *litP, int *sizeP)
264 LITTLENUM_TYPE words[4];
278 return _("bad call to md_atof");
281 t = atof_ieee (input_line_pointer, type, words);
283 input_line_pointer = t;
287 for (i = 0; i < prec; i++)
289 md_number_to_chars (litP, (valueT) words[i], 2);
296 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
297 asection *sec ATTRIBUTE_UNUSED,
298 fragS *fragP ATTRIBUTE_UNUSED)
304 md_section_align (asection *seg, valueT addr)
306 int align = bfd_get_section_alignment (stdoutput, seg);
307 return ((addr + (1 << align) - 1) & (-1 << align));
313 char *prev_name = "";
314 struct d10v_opcode *opcode;
315 d10v_hash = hash_new ();
317 /* Insert unique names into hash table. The D10v instruction set
318 has many identical opcode names that have different opcodes based
319 on the operands. This hash table then provides a quick index to
320 the first opcode with a particular name in the opcode table. */
322 for (opcode = (struct d10v_opcode *) d10v_opcodes; opcode->name; opcode++)
324 if (strcmp (prev_name, opcode->name))
326 prev_name = (char *) opcode->name;
327 hash_insert (d10v_hash, opcode->name, (char *) opcode);
332 FixUps[0].next = &FixUps[1];
333 FixUps[1].next = &FixUps[0];
336 /* Remove the postincrement or postdecrement operator ( '+' or '-' )
337 from an expression. */
342 while (*p != '-' && *p != '+')
344 if (*p == 0 || *p == '\n' || *p == '\r')
363 static bfd_reloc_code_real_type
364 get_reloc (struct d10v_operand *op)
371 if (op->flags & OPERAND_ADDR)
374 return BFD_RELOC_D10V_10_PCREL_R;
376 return BFD_RELOC_D10V_18_PCREL;
382 /* Parse a string of operands. Return an array of expressions. */
385 get_operands (expressionS exp[])
387 char *p = input_line_pointer;
394 while (*p == ' ' || *p == '\t' || *p == ',')
396 if (*p == 0 || *p == '\n' || *p == '\r')
404 exp[numops].X_op = O_absent;
408 exp[numops].X_add_number = OPERAND_ATPAR;
413 exp[numops].X_add_number = OPERAND_ATMINUS;
417 exp[numops].X_add_number = OPERAND_ATSIGN;
421 exp[numops].X_op = O_absent;
422 exp[numops].X_add_number = OPERAND_PLUS;
433 /* Just skip the trailing paren. */
438 input_line_pointer = p;
440 /* Check to see if it might be a register name. */
441 if (!register_name (&exp[numops]))
443 /* Parse as an expression. */
446 /* Any expression that involves the indirect addressing
447 cannot also involve immediate addressing. Therefore
448 the use of the hash character is illegal. */
449 int save = do_not_ignore_hash;
450 do_not_ignore_hash = 1;
452 expression (&exp[numops]);
454 do_not_ignore_hash = save;
457 expression (&exp[numops]);
460 if (strncasecmp (input_line_pointer, "@word", 5) == 0)
462 input_line_pointer += 5;
463 if (exp[numops].X_op == O_register)
465 /* If it looked like a register name but was followed by
466 "@word" then it was really a symbol, so change it to
468 exp[numops].X_op = O_symbol;
469 exp[numops].X_add_symbol =
470 symbol_find_or_make ((char *) exp[numops].X_op_symbol);
473 /* Check for identifier@word+constant. */
474 if (*input_line_pointer == '-' || *input_line_pointer == '+')
477 expression (&new_exp);
478 exp[numops].X_add_number = new_exp.X_add_number;
481 /* Convert expr into a right shift by AT_WORD_RIGHT_SHIFT. */
484 memset (&new_exp, 0, sizeof new_exp);
485 new_exp.X_add_number = AT_WORD_RIGHT_SHIFT;
486 new_exp.X_op = O_constant;
487 new_exp.X_unsigned = 1;
488 exp[numops].X_op_symbol = make_expr_symbol (&new_exp);
489 exp[numops].X_op = O_right_shift;
492 know (AT_WORD_P (&exp[numops]));
495 if (exp[numops].X_op == O_illegal)
496 as_bad (_("illegal operand"));
497 else if (exp[numops].X_op == O_absent)
498 as_bad (_("missing operand"));
501 p = input_line_pointer;
506 case -1: /* Postdecrement mode. */
507 exp[numops].X_op = O_absent;
508 exp[numops++].X_add_number = OPERAND_MINUS;
510 case 1: /* Postincrement mode. */
511 exp[numops].X_op = O_absent;
512 exp[numops++].X_add_number = OPERAND_PLUS;
516 exp[numops].X_op = 0;
521 d10v_insert_operand (unsigned long insn,
529 shift = d10v_operands[op_type].shift;
533 bits = d10v_operands[op_type].bits;
535 /* Truncate to the proper number of bits. */
536 if (check_range (value, bits, d10v_operands[op_type].flags))
537 as_bad_where (fix->fx_file, fix->fx_line,
538 _("operand out of range: %ld"), (long) value);
540 value &= 0x7FFFFFFF >> (31 - bits);
541 insn |= (value << shift);
546 /* Take a pointer to the opcode entry in the opcode table and the
547 array of operand expressions. Return the instruction. */
550 build_insn (struct d10v_opcode *opcode,
554 int i, bits, shift, flags, format;
555 unsigned long number;
557 /* The insn argument is only used for the DIVS kludge. */
562 insn = opcode->opcode;
563 format = opcode->format;
566 for (i = 0; opcode->operands[i]; i++)
568 flags = d10v_operands[opcode->operands[i]].flags;
569 bits = d10v_operands[opcode->operands[i]].bits;
570 shift = d10v_operands[opcode->operands[i]].shift;
571 number = opers[i].X_add_number;
573 if (flags & OPERAND_REG)
575 number &= REGISTER_MASK;
576 if (format == LONG_L)
580 if (opers[i].X_op != O_register && opers[i].X_op != O_constant)
582 /* Now create a fixup. */
584 if (fixups->fc >= MAX_INSN_FIXUPS)
585 as_fatal (_("too many fixups"));
587 if (AT_WORD_P (&opers[i]))
589 /* Recognize XXX>>1+N aka XXX@word+N as special (AT_WORD). */
590 fixups->fix[fixups->fc].reloc = BFD_RELOC_D10V_18;
591 opers[i].X_op = O_symbol;
592 opers[i].X_op_symbol = NULL; /* Should free it. */
593 /* number is left shifted by AT_WORD_RIGHT_SHIFT so
594 that, it is aligned with the symbol's value. Later,
595 BFD_RELOC_D10V_18 will right shift (symbol_value +
597 number <<= AT_WORD_RIGHT_SHIFT;
598 opers[i].X_add_number = number;
602 fixups->fix[fixups->fc].reloc =
603 get_reloc ((struct d10v_operand *) &d10v_operands[opcode->operands[i]]);
605 /* Check that an immediate was passed to ops that expect one. */
606 if ((flags & OPERAND_NUM)
607 && (fixups->fix[fixups->fc].reloc == 0))
608 as_bad (_("operand is not an immediate"));
611 if (fixups->fix[fixups->fc].reloc == BFD_RELOC_16 ||
612 fixups->fix[fixups->fc].reloc == BFD_RELOC_D10V_18)
613 fixups->fix[fixups->fc].size = 2;
615 fixups->fix[fixups->fc].size = 4;
617 fixups->fix[fixups->fc].exp = opers[i];
618 fixups->fix[fixups->fc].operand = opcode->operands[i];
619 fixups->fix[fixups->fc].pcrel =
620 (flags & OPERAND_ADDR) ? TRUE : FALSE;
624 /* Truncate to the proper number of bits. */
625 if ((opers[i].X_op == O_constant) && check_range (number, bits, flags))
626 as_bad (_("operand out of range: %lu"), number);
627 number &= 0x7FFFFFFF >> (31 - bits);
628 insn = insn | (number << shift);
631 /* kludge: for DIVS, we need to put the operands in twice on the second
632 pass, format is changed to LONG_R to force the second set of operands
633 to not be shifted over 15. */
634 if ((opcode->opcode == OPCODE_DIVS) && (format == LONG_L))
635 insn = build_insn (opcode, opers, insn);
640 /* Write out a long form instruction. */
643 write_long (unsigned long insn, Fixups *fx)
646 char *f = frag_more (4);
649 number_to_chars_bigendian (f, insn, 4);
651 for (i = 0; i < fx->fc; i++)
653 if (fx->fix[i].reloc)
655 where = f - frag_now->fr_literal;
656 if (fx->fix[i].size == 2)
659 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
660 fx->fix[i].operand |= 4096;
662 fix_new_exp (frag_now,
667 fx->fix[i].operand|2048);
673 /* Write out a short form instruction by itself. */
676 write_1_short (struct d10v_opcode *opcode,
680 char *f = frag_more (4);
683 if (opcode->exec_type & PARONLY)
684 as_fatal (_("Instruction must be executed in parallel with another instruction."));
686 /* The other container needs to be NOP.
687 According to 4.3.1: for FM=00, sub-instructions performed only by IU
688 cannot be encoded in L-container. */
689 if (opcode->unit == IU)
690 insn |= FM00 | (NOP << 15); /* Right container. */
692 insn = FM00 | (insn << 15) | NOP; /* Left container. */
694 number_to_chars_bigendian (f, insn, 4);
695 for (i = 0; i < fx->fc; i++)
697 if (fx->fix[i].reloc)
699 where = f - frag_now->fr_literal;
700 if (fx->fix[i].size == 2)
703 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
704 fx->fix[i].operand |= 4096;
706 /* If it's an R reloc, we may have to switch it to L. */
707 if ((fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R)
708 && (opcode->unit != IU))
709 fx->fix[i].operand |= 1024;
711 fix_new_exp (frag_now,
716 fx->fix[i].operand|2048);
722 /* Determine if there are any resource conflicts among two manually
723 parallelized instructions. Some of this was lifted from parallel_ok. */
726 check_resource_conflict (struct d10v_opcode *op1,
728 struct d10v_opcode *op2,
731 int i, j, flags, mask, shift, regno;
732 unsigned long ins, mod[2];
733 struct d10v_opcode *op;
735 if ((op1->exec_type & SEQ)
736 || ! ((op1->exec_type & PAR) || (op1->exec_type & PARONLY)))
738 as_warn (_("packing conflict: %s must dispatch sequentially"),
743 if ((op2->exec_type & SEQ)
744 || ! ((op2->exec_type & PAR) || (op2->exec_type & PARONLY)))
746 as_warn (_("packing conflict: %s must dispatch sequentially"),
751 /* See if both instructions write to the same resource.
753 The idea here is to create two sets of bitmasks (mod and used) which
754 indicate which registers are modified or used by each instruction.
755 The operation can only be done in parallel if neither instruction
756 modifies the same register. Accesses to control registers and memory
757 are treated as accesses to a single register. So if both instructions
758 write memory or if the first instruction writes memory and the second
759 reads, then they cannot be done in parallel. We treat reads to the PSW
760 (which includes C, F0, and F1) in isolation. So simultaneously writing
761 C and F0 in two different sub-instructions is permitted. */
763 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
772 for (j = 0; j < 2; j++)
785 if (op->exec_type & BRANCH_LINK)
788 for (i = 0; op->operands[i]; i++)
790 flags = d10v_operands[op->operands[i]].flags;
791 shift = d10v_operands[op->operands[i]].shift;
792 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
793 if (flags & OPERAND_REG)
795 regno = (ins >> shift) & mask;
796 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
798 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc */
805 else if (flags & OPERAND_FFLAG)
807 else if (flags & OPERAND_CFLAG)
810 if (flags & OPERAND_DEST
811 /* Auto inc/dec also modifies the register. */
812 || (op->operands[i + 1] != 0
813 && (d10v_operands[op->operands[i + 1]].flags
814 & (OPERAND_PLUS | OPERAND_MINUS)) != 0))
816 mod[j] |= 1 << regno;
817 if (flags & OPERAND_EVEN)
818 mod[j] |= 1 << (regno + 1);
821 else if (flags & OPERAND_ATMINUS)
823 /* SP implicitly used/modified. */
828 if (op->exec_type & WMEM)
830 else if (op->exec_type & WF0)
832 else if (op->exec_type & WCAR)
836 if ((mod[0] & mod[1]) == 0)
843 for (j = 0; j <= 15; j++)
845 as_warn (_("resource conflict (R%d)"), j);
846 for (j = 16; j <= 17; j++)
848 as_warn (_("resource conflict (A%d)"), j - 16);
850 as_warn (_("resource conflict (PSW)"));
852 as_warn (_("resource conflict (C flag)"));
854 as_warn (_("resource conflict (F flag)"));
858 /* Check 2 instructions and determine if they can be safely
859 executed in parallel. Return 1 if they can be. */
862 parallel_ok (struct d10v_opcode *op1,
864 struct d10v_opcode *op2,
866 packing_type exec_type)
868 int i, j, flags, mask, shift, regno;
869 unsigned long ins, mod[2], used[2];
870 struct d10v_opcode *op;
872 if ((op1->exec_type & SEQ) != 0 || (op2->exec_type & SEQ) != 0
873 || (op1->exec_type & PAR) == 0 || (op2->exec_type & PAR) == 0
874 || (op1->unit == BOTH) || (op2->unit == BOTH)
875 || (op1->unit == IU && op2->unit == IU)
876 || (op1->unit == MU && op2->unit == MU))
879 /* If this is auto parallelization, and the first instruction is a
880 branch or should not be packed, then don't parallelize. */
881 if (exec_type == PACK_UNSPEC
882 && (op1->exec_type & (ALONE | BRANCH)))
885 /* The idea here is to create two sets of bitmasks (mod and used)
886 which indicate which registers are modified or used by each
887 instruction. The operation can only be done in parallel if
888 instruction 1 and instruction 2 modify different registers, and
889 the first instruction does not modify registers that the second
890 is using (The second instruction can modify registers that the
891 first is using as they are only written back after the first
892 instruction has completed). Accesses to control registers, PSW,
893 and memory are treated as accesses to a single register. So if
894 both instructions write memory or if the first instruction writes
895 memory and the second reads, then they cannot be done in
896 parallel. Likewise, if the first instruction mucks with the psw
897 and the second reads the PSW (which includes C, F0, and F1), then
898 they cannot operate safely in parallel. */
900 /* The bitmasks (mod and used) look like this (bit 31 = MSB).
907 for (j = 0; j < 2; j++)
919 mod[j] = used[j] = 0;
920 if (op->exec_type & BRANCH_LINK)
923 for (i = 0; op->operands[i]; i++)
925 flags = d10v_operands[op->operands[i]].flags;
926 shift = d10v_operands[op->operands[i]].shift;
927 mask = 0x7FFFFFFF >> (31 - d10v_operands[op->operands[i]].bits);
928 if (flags & OPERAND_REG)
930 regno = (ins >> shift) & mask;
931 if (flags & (OPERAND_ACC0 | OPERAND_ACC1))
933 else if (flags & OPERAND_CONTROL) /* mvtc or mvfc. */
940 else if (flags & (OPERAND_FFLAG | OPERAND_CFLAG))
943 if (flags & OPERAND_DEST)
945 mod[j] |= 1 << regno;
946 if (flags & OPERAND_EVEN)
947 mod[j] |= 1 << (regno + 1);
951 used[j] |= 1 << regno;
952 if (flags & OPERAND_EVEN)
953 used[j] |= 1 << (regno + 1);
955 /* Auto inc/dec also modifies the register. */
956 if (op->operands[i + 1] != 0
957 && (d10v_operands[op->operands[i + 1]].flags
958 & (OPERAND_PLUS | OPERAND_MINUS)) != 0)
959 mod[j] |= 1 << regno;
962 else if (flags & OPERAND_ATMINUS)
964 /* SP implicitly used/modified. */
969 if (op->exec_type & RMEM)
971 else if (op->exec_type & WMEM)
973 else if (op->exec_type & RF0)
975 else if (op->exec_type & WF0)
977 else if (op->exec_type & WCAR)
980 if ((mod[0] & mod[1]) == 0 && (mod[0] & used[1]) == 0)
985 /* Expects two short instructions.
986 If possible, writes out both as a single packed instruction.
987 Otherwise, writes out the first one, packed with a NOP.
988 Returns number of instructions not written out. */
991 write_2_short (struct d10v_opcode *opcode1,
993 struct d10v_opcode *opcode2,
995 packing_type exec_type,
1002 if ((exec_type != PACK_PARALLEL)
1003 && ((opcode1->exec_type & PARONLY) || (opcode2->exec_type & PARONLY)))
1004 as_fatal (_("Instruction must be executed in parallel"));
1006 if ((opcode1->format & LONG_OPCODE) || (opcode2->format & LONG_OPCODE))
1007 as_fatal (_("Long instructions may not be combined."));
1011 case PACK_UNSPEC: /* Order not specified. */
1012 if (opcode1->exec_type & ALONE)
1014 /* Case of a short branch on a separate GAS line. Pack with NOP. */
1015 write_1_short (opcode1, insn1, fx->next);
1019 && parallel_ok (opcode1, insn1, opcode2, insn2, exec_type))
1022 if (opcode1->unit == IU)
1023 insn = FM00 | (insn2 << 15) | insn1;
1024 else if (opcode2->unit == MU)
1025 insn = FM00 | (insn2 << 15) | insn1;
1027 insn = FM00 | (insn1 << 15) | insn2;
1029 else if (opcode1->unit == IU)
1030 /* Reverse sequential with IU opcode1 on right and done first. */
1031 insn = FM10 | (insn2 << 15) | insn1;
1033 /* Sequential with non-IU opcode1 on left and done first. */
1034 insn = FM01 | (insn1 << 15) | insn2;
1038 if (opcode1->exec_type & SEQ || opcode2->exec_type & SEQ)
1040 (_("One of these instructions may not be executed in parallel."));
1041 if (opcode1->unit == IU)
1043 if (opcode2->unit == IU)
1044 as_fatal (_("Two IU instructions may not be executed in parallel"));
1045 if (!flag_warn_suppress_instructionswap)
1046 as_warn (_("Swapping instruction order"));
1047 insn = FM00 | (insn2 << 15) | insn1;
1049 else if (opcode2->unit == MU)
1051 if (opcode1->unit == MU)
1052 as_fatal (_("Two MU instructions may not be executed in parallel"));
1053 if (!flag_warn_suppress_instructionswap)
1054 as_warn (_("Swapping instruction order"));
1055 insn = FM00 | (insn2 << 15) | insn1;
1058 insn = FM00 | (insn1 << 15) | insn2;
1059 check_resource_conflict (opcode1, insn1, opcode2, insn2);
1062 case PACK_LEFT_RIGHT:
1063 if (opcode1->unit != IU)
1064 insn = FM01 | (insn1 << 15) | insn2;
1065 else if (opcode2->unit == MU || opcode2->unit == EITHER)
1067 if (!flag_warn_suppress_instructionswap)
1068 as_warn (_("Swapping instruction order"));
1069 insn = FM10 | (insn2 << 15) | insn1;
1072 as_fatal (_("IU instruction may not be in the left container"));
1073 if (opcode1->exec_type & ALONE)
1074 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1077 case PACK_RIGHT_LEFT:
1078 if (opcode2->unit != MU)
1079 insn = FM10 | (insn1 << 15) | insn2;
1080 else if (opcode1->unit == IU || opcode1->unit == EITHER)
1082 if (!flag_warn_suppress_instructionswap)
1083 as_warn (_("Swapping instruction order"));
1084 insn = FM01 | (insn2 << 15) | insn1;
1087 as_fatal (_("MU instruction may not be in the right container"));
1088 if (opcode2->exec_type & ALONE)
1089 as_warn (_("Instruction in R container is squashed by flow control instruction in L container."));
1093 as_fatal (_("unknown execution type passed to write_2_short()"));
1097 number_to_chars_bigendian (f, insn, 4);
1099 /* Process fixup chains. fx refers to insn2 when j == 0, and to
1100 insn1 when j == 1. Yes, it's reversed. */
1102 for (j = 0; j < 2; j++)
1104 for (i = 0; i < fx->fc; i++)
1106 if (fx->fix[i].reloc)
1108 where = f - frag_now->fr_literal;
1109 if (fx->fix[i].size == 2)
1112 if (fx->fix[i].reloc == BFD_RELOC_D10V_10_PCREL_R
1113 /* A BFD_RELOC_D10V_10_PCREL_R relocation applied to
1114 the instruction in the L container has to be
1115 adjusted to BDF_RELOC_D10V_10_PCREL_L. When
1116 j==0, we're processing insn2's operands, so we
1117 want to mark the operand if insn2 is *not* in the
1118 R container. When j==1, we're processing insn1's
1119 operands, so we want to mark the operand if insn2
1120 *is* in the R container. Note that, if two
1121 instructions are identical, we're never going to
1122 swap them, so the test is safe. */
1123 && j == ((insn & 0x7fff) == insn2))
1124 fx->fix[i].operand |= 1024;
1126 if (fx->fix[i].reloc == BFD_RELOC_D10V_18)
1127 fx->fix[i].operand |= 4096;
1129 fix_new_exp (frag_now,
1134 fx->fix[i].operand|2048);
1143 /* This is the main entry point for the machine-dependent assembler.
1144 str points to a machine-dependent instruction. This function is
1145 supposed to emit the frags/bytes it assembles to. For the D10V, it
1146 mostly handles the special VLIW parsing and packing and leaves the
1147 difficult stuff to do_assemble(). */
1149 static unsigned long prev_insn;
1150 static struct d10v_opcode *prev_opcode = 0;
1151 static subsegT prev_subseg;
1152 static segT prev_seg = 0;;
1154 /* Find the symbol which has the same name as the register in exp. */
1157 find_symbol_matching_register (expressionS *exp)
1161 if (exp->X_op != O_register)
1164 /* Find the name of the register. */
1165 for (i = d10v_reg_name_cnt (); i--;)
1166 if (d10v_predefined_registers[i].value == exp->X_add_number)
1172 /* Now see if a symbol has been defined with the same name. */
1173 return symbol_find (d10v_predefined_registers[i].name);
1176 /* Get a pointer to an entry in the opcode table.
1177 The function must look at all opcodes with the same name and use
1178 the operands to choose the correct opcode. */
1180 static struct d10v_opcode *
1181 find_opcode (struct d10v_opcode *opcode, expressionS myops[])
1184 struct d10v_opcode *next_opcode;
1186 /* Get all the operands and save them as expressions. */
1187 get_operands (myops);
1189 /* Now see if the operand is a fake. If so, find the correct size
1190 instruction, if possible. */
1191 if (opcode->format == OPCODE_FAKE)
1193 int opnum = opcode->operands[0];
1196 if (myops[opnum].X_op == O_register)
1198 myops[opnum].X_op = O_symbol;
1199 myops[opnum].X_add_symbol =
1200 symbol_find_or_make ((char *) myops[opnum].X_op_symbol);
1201 myops[opnum].X_add_number = 0;
1202 myops[opnum].X_op_symbol = NULL;
1205 next_opcode = opcode + 1;
1207 /* If the first operand is supposed to be a register, make sure
1208 we got a valid one. */
1209 flags = d10v_operands[next_opcode->operands[0]].flags;
1210 if (flags & OPERAND_REG)
1212 int X_op = myops[0].X_op;
1213 int num = myops[0].X_add_number;
1215 if (X_op != O_register
1217 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1218 | OPERAND_FFLAG | OPERAND_CFLAG | OPERAND_CONTROL))
1219 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1221 as_bad (_("bad opcode or operands"));
1226 if (myops[opnum].X_op == O_constant
1227 || (myops[opnum].X_op == O_symbol
1228 && S_IS_DEFINED (myops[opnum].X_add_symbol)
1229 && (S_GET_SEGMENT (myops[opnum].X_add_symbol) == now_seg)))
1231 for (i = 0; opcode->operands[i + 1]; i++)
1233 int bits = d10v_operands[next_opcode->operands[opnum]].bits;
1234 int flags = d10v_operands[next_opcode->operands[opnum]].flags;
1235 if (flags & OPERAND_ADDR)
1238 if (myops[opnum].X_op == O_constant)
1240 if (!check_range (myops[opnum].X_add_number, bits, flags))
1247 unsigned long current_position;
1248 unsigned long symbol_position;
1249 unsigned long value;
1250 bfd_boolean found_symbol;
1252 /* Calculate the address of the current instruction
1253 and the address of the symbol. Do this by summing
1254 the offsets of previous frags until we reach the
1255 frag containing the symbol, and the current frag. */
1256 sym_frag = symbol_get_frag (myops[opnum].X_add_symbol);
1257 found_symbol = FALSE;
1260 obstack_next_free (&frchain_now->frch_obstack)
1261 - frag_now->fr_literal;
1262 symbol_position = S_GET_VALUE (myops[opnum].X_add_symbol);
1264 for (f = frchain_now->frch_root; f; f = f->fr_next)
1266 current_position += f->fr_fix + f->fr_offset;
1269 found_symbol = TRUE;
1272 symbol_position += f->fr_fix + f->fr_offset;
1275 value = symbol_position;
1277 if (flags & OPERAND_ADDR)
1278 value -= current_position;
1280 if (AT_WORD_P (&myops[opnum]))
1285 if (!check_range (value, bits, flags))
1289 else if (!check_range (value, bits, flags))
1295 if (opcode->operands [i + 1] == 0)
1296 as_fatal (_("value out of range"));
1298 opcode = next_opcode;
1301 /* Not a constant, so use a long instruction. */
1307 /* Now search the opcode table table for one with operands
1308 that matches what we've got. */
1312 for (i = 0; opcode->operands[i]; i++)
1314 int flags = d10v_operands[opcode->operands[i]].flags;
1315 int X_op = myops[i].X_op;
1316 int num = myops[i].X_add_number;
1324 if (flags & OPERAND_REG)
1326 if ((X_op != O_register)
1328 & (OPERAND_GPR | OPERAND_ACC0 | OPERAND_ACC1
1329 | OPERAND_FFLAG | OPERAND_CFLAG
1331 || ((flags & OPERAND_SP) && ! (num & OPERAND_SP)))
1338 if (((flags & OPERAND_MINUS) && ((X_op != O_absent) || (num != OPERAND_MINUS))) ||
1339 ((flags & OPERAND_PLUS) && ((X_op != O_absent) || (num != OPERAND_PLUS))) ||
1340 ((flags & OPERAND_ATMINUS) && ((X_op != O_absent) || (num != OPERAND_ATMINUS))) ||
1341 ((flags & OPERAND_ATPAR) && ((X_op != O_absent) || (num != OPERAND_ATPAR))) ||
1342 ((flags & OPERAND_ATSIGN) && ((X_op != O_absent) || ((num != OPERAND_ATSIGN) && (num != OPERAND_ATPAR)))))
1348 /* Unfortunately, for the indirect operand in instructions such
1349 as ``ldb r1, @(c,r14)'' this function can be passed
1350 X_op == O_register (because 'c' is a valid register name).
1351 However we cannot just ignore the case when X_op == O_register
1352 but flags & OPERAND_REG is null, so we check to see if a symbol
1353 of the same name as the register exists. If the symbol does
1354 exist, then the parser was unable to distinguish the two cases
1355 and we fix things here. (Ref: PR14826) */
1357 if (!(flags & OPERAND_REG) && (X_op == O_register))
1361 sym = find_symbol_matching_register (& myops[i]);
1365 myops[i].X_op = X_op = O_symbol;
1366 myops[i].X_add_symbol = sym;
1370 (_("illegal operand - register name found where none expected"));
1374 /* We're only done if the operands matched so far AND there
1375 are no more to check. */
1376 if (match && myops[i].X_op == 0)
1381 next_opcode = opcode + 1;
1383 if (next_opcode->opcode == 0)
1386 if (strcmp (next_opcode->name, opcode->name))
1389 opcode = next_opcode;
1394 as_bad (_("bad opcode or operands"));
1398 /* Check that all registers that are required to be even are.
1399 Also, if any operands were marked as registers, but were really symbols,
1401 for (i = 0; opcode->operands[i]; i++)
1403 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_EVEN) &&
1404 (myops[i].X_add_number & 1))
1405 as_fatal (_("Register number must be EVEN"));
1406 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_NOSP)
1407 && (myops[i].X_add_number & OPERAND_SP))
1408 as_bad (_("Unsupported use of sp"));
1409 if (myops[i].X_op == O_register)
1411 if (!(d10v_operands[opcode->operands[i]].flags & OPERAND_REG))
1413 myops[i].X_op = O_symbol;
1414 myops[i].X_add_symbol =
1415 symbol_find_or_make ((char *) myops[i].X_op_symbol);
1416 myops[i].X_add_number = 0;
1417 myops[i].X_op_symbol = NULL;
1420 if ((d10v_operands[opcode->operands[i]].flags & OPERAND_CONTROL)
1421 && (myops[i].X_add_number == OPERAND_CONTROL + 4
1422 || myops[i].X_add_number == OPERAND_CONTROL + 5
1423 || myops[i].X_add_number == OPERAND_CONTROL + 6
1424 || myops[i].X_add_number == OPERAND_CONTROL + 12
1425 || myops[i].X_add_number == OPERAND_CONTROL + 13
1426 || myops[i].X_add_number == OPERAND_CONTROL + 15))
1427 as_warn (_("cr%ld is a reserved control register"),
1428 myops[i].X_add_number - OPERAND_CONTROL);
1433 /* Assemble a single instruction.
1434 Return an opcode, or -1 (an invalid opcode) on error. */
1436 static unsigned long
1437 do_assemble (char *str, struct d10v_opcode **opcode)
1439 unsigned char *op_start, *op_end;
1443 expressionS myops[6];
1446 /* Drop leading whitespace. */
1450 /* Find the opcode end. */
1451 for (op_start = op_end = (unsigned char *) str;
1452 *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' ';
1455 name[nlen] = TOLOWER (op_start[nlen]);
1463 /* Find the first opcode with the proper name. */
1464 *opcode = (struct d10v_opcode *) hash_find (d10v_hash, name);
1465 if (*opcode == NULL)
1466 as_fatal (_("unknown opcode: %s"), name);
1468 save = input_line_pointer;
1469 input_line_pointer = (char *) op_end;
1470 *opcode = find_opcode (*opcode, myops);
1473 input_line_pointer = save;
1475 insn = build_insn ((*opcode), myops, 0);
1479 /* If while processing a fixup, a reloc really needs to be created.
1480 Then it is done here. */
1483 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp)
1486 reloc = xmalloc (sizeof (arelent));
1487 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1488 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1489 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1490 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1491 if (reloc->howto == (reloc_howto_type *) NULL)
1493 as_bad_where (fixp->fx_file, fixp->fx_line,
1494 _("reloc %d not supported by object file format"),
1495 (int) fixp->fx_r_type);
1499 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1500 reloc->address = fixp->fx_offset;
1508 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
1509 asection *seg ATTRIBUTE_UNUSED)
1516 md_pcrel_from_section (fixS *fixp, segT sec)
1518 if (fixp->fx_addsy != (symbolS *) NULL
1519 && (!S_IS_DEFINED (fixp->fx_addsy)
1520 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1522 return fixp->fx_frag->fr_address + fixp->fx_where;
1526 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
1534 if (fixP->fx_addsy == (symbolS *) NULL)
1537 /* We don't actually support subtracting a symbol. */
1538 if (fixP->fx_subsy != (symbolS *) NULL)
1539 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1541 op_type = fixP->fx_r_type;
1548 fixP->fx_r_type = BFD_RELOC_D10V_10_PCREL_L;
1551 else if (op_type & 4096)
1554 fixP->fx_r_type = BFD_RELOC_D10V_18;
1558 get_reloc ((struct d10v_operand *) &d10v_operands[op_type]);
1561 /* Fetch the instruction, insert the fully resolved operand
1562 value, and stuff the instruction back again. */
1563 where = fixP->fx_frag->fr_literal + fixP->fx_where;
1564 insn = bfd_getb32 ((unsigned char *) where);
1566 switch (fixP->fx_r_type)
1568 case BFD_RELOC_D10V_10_PCREL_L:
1569 case BFD_RELOC_D10V_10_PCREL_R:
1570 case BFD_RELOC_D10V_18_PCREL:
1571 /* If the fix is relative to a global symbol, not a section
1572 symbol, then ignore the offset.
1573 XXX - Do we have to worry about branches to a symbol + offset ? */
1574 if (fixP->fx_addsy != NULL
1575 && S_IS_EXTERN (fixP->fx_addsy) )
1577 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
1578 segment_info_type *segf = seg_info(fseg);
1580 if ( segf && segf->sym != fixP->fx_addsy)
1584 case BFD_RELOC_D10V_18:
1585 /* Instruction addresses are always right-shifted by 2. */
1586 value >>= AT_WORD_RIGHT_SHIFT;
1587 if (fixP->fx_size == 2)
1588 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1591 struct d10v_opcode *rep, *repi;
1593 rep = (struct d10v_opcode *) hash_find (d10v_hash, "rep");
1594 repi = (struct d10v_opcode *) hash_find (d10v_hash, "repi");
1595 if ((insn & FM11) == FM11
1597 && (insn & repi->mask) == (unsigned) repi->opcode)
1599 && (insn & rep->mask) == (unsigned) rep->opcode))
1602 (_("line %d: rep or repi must include at least 4 instructions"),
1605 d10v_insert_operand (insn, op_type, (offsetT) value, left, fixP);
1606 bfd_putb32 ((bfd_vma) insn, (unsigned char *) where);
1610 bfd_putb32 ((bfd_vma) value, (unsigned char *) where);
1613 bfd_putb16 ((bfd_vma) value, (unsigned char *) where);
1616 case BFD_RELOC_VTABLE_INHERIT:
1617 case BFD_RELOC_VTABLE_ENTRY:
1622 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1623 fixP->fx_line, fixP->fx_r_type);
1627 /* d10v_cleanup() is called after the assembler has finished parsing
1628 the input file, when a label is read from the input file, or when a
1629 stab directive is output. Because the D10V assembler sometimes
1630 saves short instructions to see if it can package them with the
1631 next instruction, there may be a short instruction that still needs
1634 NOTE: accesses a global, etype.
1635 NOTE: invoked by various macros such as md_cleanup: see. */
1643 /* If cleanup was invoked because the assembler encountered, e.g., a
1644 user label, we write out the pending instruction, if any. If it
1645 was invoked because the assembler is outputting a piece of line
1646 debugging information, though, we write out the pending
1647 instruction only if the --no-gstabs-packing command line switch
1648 has been specified. */
1650 && etype == PACK_UNSPEC
1651 && (! outputting_stabs_line_debug || ! flag_allow_gstabs_packing))
1654 subseg = now_subseg;
1657 subseg_set (prev_seg, prev_subseg);
1659 write_1_short (prev_opcode, prev_insn, fixups->next);
1660 subseg_set (seg, subseg);
1666 /* Like normal .word, except support @word.
1667 Clobbers input_line_pointer, checks end-of-line. */
1670 d10v_dot_word (int dummy ATTRIBUTE_UNUSED)
1675 if (is_it_end_of_statement ())
1677 demand_empty_rest_of_line ();
1684 if (!strncasecmp (input_line_pointer, "@word", 5))
1686 exp.X_add_number = 0;
1687 input_line_pointer += 5;
1690 fix_new_exp (frag_now, p - frag_now->fr_literal, 2,
1691 &exp, 0, BFD_RELOC_D10V_18);
1694 emit_expr (&exp, 2);
1696 while (*input_line_pointer++ == ',');
1698 input_line_pointer--; /* Put terminator back into stream. */
1699 demand_empty_rest_of_line ();
1702 /* Mitsubishi asked that we support some old syntax that apparently
1703 had immediate operands starting with '#'. This is in some of their
1704 sample code but is not documented (although it appears in some
1705 examples in their assembler manual). For now, we'll solve this
1706 compatibility problem by simply ignoring any '#' at the beginning
1709 /* Operands that begin with '#' should fall through to here.
1713 md_operand (expressionS *expressionP)
1715 if (*input_line_pointer == '#' && ! do_not_ignore_hash)
1717 input_line_pointer++;
1718 expression (expressionP);
1723 d10v_fix_adjustable (fixS *fixP)
1725 /* We need the symbol name for the VTABLE entries. */
1726 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1727 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1733 /* The target specific pseudo-ops which we support. */
1734 const pseudo_typeS md_pseudo_table[] =
1736 { "word", d10v_dot_word, 2 },
1741 md_assemble (char *str)
1743 /* etype is saved extype. For multi-line instructions. */
1744 packing_type extype = PACK_UNSPEC; /* Parallel, etc. */
1745 struct d10v_opcode *opcode;
1749 if (etype == PACK_UNSPEC)
1751 /* Look for the special multiple instruction separators. */
1752 str2 = strstr (str, "||");
1754 extype = PACK_PARALLEL;
1757 str2 = strstr (str, "->");
1759 extype = PACK_LEFT_RIGHT;
1762 str2 = strstr (str, "<-");
1764 extype = PACK_RIGHT_LEFT;
1768 /* str2 points to the separator, if there is one. */
1773 /* If two instructions are present and we already have one saved,
1774 then first write out the saved one. */
1777 /* Assemble first instruction and save it. */
1778 prev_insn = do_assemble (str, &prev_opcode);
1780 prev_subseg = now_subseg;
1781 if (prev_insn == (unsigned long) -1)
1782 as_fatal (_("can't find opcode "));
1783 fixups = fixups->next;
1788 insn = do_assemble (str, &opcode);
1789 if (insn == (unsigned long) -1)
1791 if (extype != PACK_UNSPEC)
1796 as_fatal (_("can't find opcode "));
1799 if (etype != PACK_UNSPEC)
1802 etype = PACK_UNSPEC;
1805 /* If this is a long instruction, write it and any previous short
1807 if (opcode->format & LONG_OPCODE)
1809 if (extype != PACK_UNSPEC)
1810 as_fatal (_("Unable to mix instructions as specified"));
1812 write_long (insn, fixups);
1819 && ((prev_seg != now_seg) || (prev_subseg != now_subseg)))
1823 && (0 == write_2_short (prev_opcode, prev_insn, opcode, insn, extype,
1826 /* No instructions saved. */
1831 if (extype != PACK_UNSPEC)
1832 as_fatal (_("Unable to mix instructions as specified"));
1833 /* Save last instruction so it may be packed on next pass. */
1834 prev_opcode = opcode;
1837 prev_subseg = now_subseg;
1838 fixups = fixups->next;