1 /* tc-crx.c -- Assembler code for the CRX CPU core.
2 Copyright 2004 Free Software Foundation, Inc.
4 Contributed by Tomer Levi, NSC, Israel.
5 Originally written for GAS 2.12 by Tomer Levi, NSC, Israel.
6 Updates, BFDizing, GNUifying and ELF support by Tomer Levi.
8 This file is part of GAS, the GNU Assembler.
10 GAS is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GAS is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GAS; see the file COPYING. If not, write to the
22 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
23 MA 02111-1307, USA. */
26 #include "safe-ctype.h"
27 #include "dwarf2dbg.h"
28 #include "opcode/crx.h"
33 /* Word is considered here as a 16-bit unsigned short int. */
37 /* Register is 4-bit size. */
40 /* Maximum size of a single instruction (in words). */
41 #define INSN_MAX_SIZE 3
43 /* Maximum bits which may be set in a `mask16' operand. */
44 #define MAX_REGS_IN_MASK16 8
46 /* Escape to 16-bit immediate. */
48 /* Escape to 32-bit immediate. */
51 /* Utility macros for string comparison. */
52 #define streq(a, b) (strcmp (a, b) == 0)
53 #define strneq(a, b, c) (strncmp (a, b, c) == 0)
55 /* A mask to set n_bits starting from offset offs. */
56 #define SET_BITS_MASK(offs,n_bits) ((((1 << (n_bits)) - 1) << (offs)))
57 /* A mask to clear n_bits starting from offset offs. */
58 #define CLEAR_BITS_MASK(offs,n_bits) (~(((1 << (n_bits)) - 1) << (offs)))
60 /* Get the argument type for each operand of a given instruction. */
61 #define GET_ACTUAL_TYPE \
62 for (i = 0; i < insn->nargs; i++) \
63 atyp_act[i] = getarg_type (instruction->operands[i].op_type)
65 /* Get the size (in bits) for each operand of a given instruction. */
66 #define GET_ACTUAL_SIZE \
67 for (i = 0; i < insn->nargs; i++) \
68 bits_act[i] = getbits (instruction->operands[i].op_type)
70 /* Non-zero if OP is instruction with no operands. */
71 #define NO_OPERANDS_INST(OP) \
72 (streq (OP, "di") || streq (OP, "nop") \
73 || streq (OP, "retx") || streq (OP, "ei") \
74 || streq (OP, "wait") || streq (OP, "eiwait"))
76 /* Print a number NUM, shifted by SHIFT bytes, into a location
77 pointed by index BYTE of array 'output_opcode'. */
78 #define CRX_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM << SHIFT)
80 /* Opcode mnemonics hash table. */
81 static struct hash_control *crx_inst_hash;
82 /* CRX registers hash table. */
83 static struct hash_control *reg_hash;
84 /* CRX coprocessor registers hash table. */
85 static struct hash_control *copreg_hash;
86 /* Current instruction we're assembling. */
87 const inst *instruction;
89 /* Initialize global variables. */
90 long output_opcode[2];
91 /* Nonzero means a relocatable symbol. */
93 /* Nonzero means a constant's bit-size was already set. */
95 /* Nonzero means a negative constant. */
97 /* Nonzero means a CST4 instruction. */
99 /* A copy of the original instruction (used in error messages). */
100 char ins_parse[MAX_INST_LEN];
101 /* Holds the current processed argument number. */
102 int processing_arg_number;
104 /* Generic assembler global variables which must be defined by all targets. */
106 /* Characters which always start a comment. */
107 const char comment_chars[] = "#";
109 /* Characters which start a comment at the beginning of a line. */
110 const char line_comment_chars[] = "#";
112 /* This array holds machine specific line separator characters. */
113 const char line_separator_chars[] = ";";
115 /* Chars that can be used to separate mant from exp in floating point nums. */
116 const char EXP_CHARS[] = "eE";
118 /* Chars that mean this number is a floating point constant as in 0f12.456 */
119 const char FLT_CHARS[] = "f'";
121 /* Target-specific multicharacter options, not const-declared at usage. */
122 const char *md_shortopts = "";
123 struct option md_longopts[] =
125 {NULL, no_argument, NULL, 0}
127 size_t md_longopts_size = sizeof (md_longopts);
129 /* This table describes all the machine specific pseudo-ops
130 the assembler has to support. The fields are:
131 *** Pseudo-op name without dot.
132 *** Function to call to execute this pseudo-op.
133 *** Integer arg to pass to the function. */
135 const pseudo_typeS md_pseudo_table[] =
137 /* In CRX machine, align is in bytes (not a ptwo boundary). */
138 {"align", s_align_bytes, 0},
142 const relax_typeS md_relax_table[] =
145 {0xfa, -0x100, 2, 1}, /* 8 */
146 {0xfffe, -0x10000, 4, 2}, /* 16 */
147 {0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
150 {0xfffe, -0x10000, 4, 4}, /* 16 */
151 {0xfffffffe, -0xfffffffe, 6, 0}, /* 32 */
154 {0xfe, -0x100, 4, 6}, /* 8 */
155 {0xfffffe, -0x1000000, 6, 0} /* 24 */
158 static void reset_vars (char *, ins *);
159 static reg get_register (char *);
160 static copreg get_copregister (char *);
161 static void get_number_of_bits (ins *, int);
162 static argtype getarg_type (operand_type);
163 static int getbits (operand_type);
164 static int get_flags (operand_type);
165 static int get_number_of_operands (void);
166 static void get_operandtype (char *, int, ins *);
167 static int gettrap (char *);
168 static void handle_LoadStor (char *);
169 static int get_cinv_parameters (char *);
170 static unsigned long getconstant (unsigned long, int);
171 static int getreg_image (reg);
172 static void parse_operands (ins *, char *);
173 static void parse_insn (ins *, char *);
174 static void print_operand (int, int, argument *);
175 static void print_constant (int, int, argument *);
176 static int exponent2scale (int);
177 static void mask_const (unsigned long *, int);
178 static void mask_reg (int, unsigned short *);
179 static int process_label_constant (char *, ins *, int);
180 static void set_indexmode_parameters (char *, ins *, int);
181 static void set_cons_rparams (char *, ins *, int);
182 static char * preprocess_reglist (char *, int *);
183 static int assemble_insn (char *, ins *);
184 static void print_insn (ins *);
186 /* Return the bit size for a given operand. */
189 getbits (operand_type op)
192 return crx_optab[op].bit_size;
197 /* Return the argument type of a given operand. */
200 getarg_type (operand_type op)
203 return crx_optab[op].arg_type;
208 /* Return the flags of a given operand. */
211 get_flags (operand_type op)
214 return crx_optab[op].flags;
219 /* Get the core processor register 'reg_name'. */
222 get_register (char *reg_name)
224 const reg_entry *reg;
226 reg = (const reg_entry *) hash_find (reg_hash, reg_name);
229 return reg->value.reg_val;
234 /* Get the coprocessor register 'copreg_name'. */
237 get_copregister (char *copreg_name)
239 const reg_entry *copreg;
241 copreg = (const reg_entry *) hash_find (copreg_hash, copreg_name);
244 return copreg->value.copreg_val;
246 return nullcopregister;
249 /* Mask a constant to the number of bits it is to be mapped to. */
252 mask_const (unsigned long int *t, int size)
254 *t &= (((LONGLONG)1 << size) - 1);
257 /* Round up a section size to the appropriate boundary. */
260 md_section_align (segT seg, valueT val)
262 /* Round .text section to a multiple of 2. */
263 if (seg == text_section)
264 return (val + 1) & ~1;
268 /* Parse an operand that is machine-specific (remove '*'). */
271 md_operand (expressionS * exp)
273 char c = *input_line_pointer;
278 input_line_pointer++;
286 /* Reset global variables before parsing a new instruction. */
289 reset_vars (char *op, ins *crx_ins)
293 processing_arg_number = relocatable = size_was_set
294 = signflag = cst4flag = 0;
295 memset (& output_opcode, '\0', sizeof (output_opcode));
297 /* Memset the 'signflag' field in every argument. */
298 for (i = 0; i < MAX_OPERANDS; i++)
299 crx_ins->arg[i].signflag = 0;
301 /* Save a copy of the original OP (used in error messages). */
302 strcpy (ins_parse, op);
305 /* This macro decides whether a particular reloc is an entry in a
306 switch table. It is used when relaxing, because the linker needs
307 to know about all such entries so that it can adjust them if
310 #define SWITCH_TABLE(fix) \
311 ( (fix)->fx_addsy != NULL \
312 && (fix)->fx_subsy != NULL \
313 && S_GET_SEGMENT ((fix)->fx_addsy) == \
314 S_GET_SEGMENT ((fix)->fx_subsy) \
315 && S_GET_SEGMENT (fix->fx_addsy) != undefined_section \
316 && ( (fix)->fx_r_type == BFD_RELOC_CRX_NUM8 \
317 || (fix)->fx_r_type == BFD_RELOC_CRX_NUM16 \
318 || (fix)->fx_r_type == BFD_RELOC_CRX_NUM32))
320 /* See whether we need to force a relocation into the output file.
321 This is used to force out switch and PC relative relocations when
325 crx_force_relocation (fixS *fix)
327 if (generic_force_reloc (fix) || SWITCH_TABLE (fix))
333 /* Generate a relocation entry for a fixup. */
336 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
340 reloc = xmalloc (sizeof (arelent));
341 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
342 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
343 reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
344 reloc->addend = fixP->fx_offset;
346 if (fixP->fx_subsy != NULL)
348 if (SWITCH_TABLE (fixP))
350 /* Keep the current difference in the addend. */
351 reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
352 - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
354 switch (fixP->fx_r_type)
356 case BFD_RELOC_CRX_NUM8:
357 fixP->fx_r_type = BFD_RELOC_CRX_SWITCH8;
359 case BFD_RELOC_CRX_NUM16:
360 fixP->fx_r_type = BFD_RELOC_CRX_SWITCH16;
362 case BFD_RELOC_CRX_NUM32:
363 fixP->fx_r_type = BFD_RELOC_CRX_SWITCH32;
372 /* We only resolve difference expressions in the same section. */
373 as_bad_where (fixP->fx_file, fixP->fx_line,
374 _("can't resolve `%s' {%s section} - `%s' {%s section}"),
375 fixP->fx_addsy ? S_GET_NAME (fixP->fx_addsy) : "0",
376 segment_name (fixP->fx_addsy
377 ? S_GET_SEGMENT (fixP->fx_addsy)
379 S_GET_NAME (fixP->fx_subsy),
380 segment_name (S_GET_SEGMENT (fixP->fx_addsy)));
384 assert ((int) fixP->fx_r_type > 0);
385 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
387 if (reloc->howto == (reloc_howto_type *) NULL)
389 as_bad_where (fixP->fx_file, fixP->fx_line,
390 _("internal error: reloc %d (`%s') not supported by object file format"),
392 bfd_get_reloc_code_name (fixP->fx_r_type));
395 assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
400 /* Prepare machine-dependent frags for relaxation. */
403 md_estimate_size_before_relax (fragS *fragp, asection *seg)
405 /* If symbol is undefined or located in a different section,
406 select the largest supported relocation. */
407 relax_substateT subtype;
408 relax_substateT rlx_state[] = {0, 2,
412 for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
414 if (fragp->fr_subtype == rlx_state[subtype]
415 && (!S_IS_DEFINED (fragp->fr_symbol)
416 || seg != S_GET_SEGMENT (fragp->fr_symbol)))
418 fragp->fr_subtype = rlx_state[subtype + 1];
423 if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
426 return md_relax_table[fragp->fr_subtype].rlx_length;
430 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
432 /* 'opcode' points to the start of the instruction, whether
433 we need to change the instruction's fixed encoding. */
434 char *opcode = fragP->fr_literal + fragP->fr_fix;
435 bfd_reloc_code_real_type reloc;
437 subseg_change (sec, 0);
439 switch (fragP->fr_subtype)
442 reloc = BFD_RELOC_CRX_REL8;
446 reloc = BFD_RELOC_CRX_REL16;
450 reloc = BFD_RELOC_CRX_REL32;
453 reloc = BFD_RELOC_CRX_REL16;
457 reloc = BFD_RELOC_CRX_REL32;
460 reloc = BFD_RELOC_CRX_REL8_CMP;
464 reloc = BFD_RELOC_CRX_REL24;
471 fix_new (fragP, fragP->fr_fix,
472 bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
473 fragP->fr_symbol, fragP->fr_offset, 1, reloc);
475 fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
478 /* Process machine-dependent command line options. Called once for
479 each option on the command line that the machine-independent part of
480 GAS does not understand. */
483 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
488 /* Machine-dependent usage-output. */
491 md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
496 /* Turn a string in input_line_pointer into a floating point constant
497 of type TYPE, and store the appropriate bytes in *LITP. The number
498 of LITTLENUMS emitted is stored in *SIZEP. An error message is
499 returned, or NULL on OK. */
502 md_atof (int type, char *litP, int *sizeP)
505 LITTLENUM_TYPE words[4];
521 return _("bad call to md_atof");
524 t = atof_ieee (input_line_pointer, type, words);
526 input_line_pointer = t;
530 if (! target_big_endian)
532 for (i = prec - 1; i >= 0; i--)
534 md_number_to_chars (litP, (valueT) words[i], 2);
540 for (i = 0; i < prec; i++)
542 md_number_to_chars (litP, (valueT) words[i], 2);
550 /* Apply a fixS (fixup of an instruction or data that we didn't have
551 enough info to complete immediately) to the data in a frag.
552 Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
553 relaxation of debug sections, this function is called only when
554 fixuping relocations of debug sections. */
557 md_apply_fix3 (fixS *fixP, valueT *valP, segT seg)
560 char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
563 switch (fixP->fx_r_type)
565 case BFD_RELOC_CRX_NUM8:
566 bfd_put_8 (stdoutput, (unsigned char) val, buf);
568 case BFD_RELOC_CRX_NUM16:
569 bfd_put_16 (stdoutput, val, buf);
571 case BFD_RELOC_CRX_NUM32:
572 bfd_put_32 (stdoutput, val, buf);
575 /* We shouldn't ever get here because linkrelax is nonzero. */
582 if (fixP->fx_addsy == NULL
583 && fixP->fx_pcrel == 0)
586 if (fixP->fx_pcrel == 1
587 && fixP->fx_addsy != NULL
588 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
592 /* The location from which a PC relative jump should be calculated,
593 given a PC relative reloc. */
596 md_pcrel_from (fixS *fixp)
598 return fixp->fx_frag->fr_address + fixp->fx_where;
601 /* This function is called once, at assembler startup time. This should
602 set up all the tables, etc that the MD part of the assembler needs. */
607 const char *hashret = NULL;
610 /* Set up a hash table for the instructions. */
611 if ((crx_inst_hash = hash_new ()) == NULL)
612 as_fatal (_("Virtual memory exhausted"));
614 while (crx_instruction[i].mnemonic != NULL)
616 const char *mnemonic = crx_instruction[i].mnemonic;
618 hashret = hash_insert (crx_inst_hash, mnemonic,
619 (PTR) &crx_instruction[i]);
621 if (hashret != NULL && *hashret != '\0')
622 as_fatal (_("Can't hash `%s': %s\n"), crx_instruction[i].mnemonic,
623 *hashret == 0 ? _("(unknown reason)") : hashret);
625 /* Insert unique names into hash table. The CRX instruction set
626 has many identical opcode names that have different opcodes based
627 on the operands. This hash table then provides a quick index to
628 the first opcode with a particular name in the opcode table. */
633 while (crx_instruction[i].mnemonic != NULL
634 && streq (crx_instruction[i].mnemonic, mnemonic));
637 /* Initialize reg_hash hash table. */
638 if ((reg_hash = hash_new ()) == NULL)
639 as_fatal (_("Virtual memory exhausted"));
642 const reg_entry *regtab;
644 for (regtab = crx_regtab;
645 regtab < (crx_regtab + NUMREGS); regtab++)
647 hashret = hash_insert (reg_hash, regtab->name, (PTR) regtab);
649 as_fatal (_("Internal Error: Can't hash %s: %s"),
655 /* Initialize copreg_hash hash table. */
656 if ((copreg_hash = hash_new ()) == NULL)
657 as_fatal (_("Virtual memory exhausted"));
660 const reg_entry *copregtab;
662 for (copregtab = crx_copregtab; copregtab < (crx_copregtab + NUMCOPREGS);
665 hashret = hash_insert (copreg_hash, copregtab->name, (PTR) copregtab);
667 as_fatal (_("Internal Error: Can't hash %s: %s"),
672 /* Set linkrelax here to avoid fixups in most sections. */
676 /* Get the number of bits corresponding to a constant -
677 here we check for possible overflow cases. */
680 get_number_of_bits (ins * crx_ins, int op_num)
683 unsigned long int temp = crx_ins->arg[op_num].constant;
684 const cst4_entry *cst4_op;
686 /* If the constant's size was already set - nothing to do. */
690 /* Already dealt with negative numbers in process_label_constants. */
697 /* Arithmetic instructions :
698 16-bit positive signed immediate -->> represent as 32-bit. */
699 if (IS_INSN_TYPE (ARITH_INS) && !relocatable && !signflag)
703 crx_ins->arg[op_num].size = 32;
707 /* Index addressing mode :
708 6-bit positive signed immediate -->> represent as 22-bit. */
709 if (IS_INSN_TYPE (LD_STOR_INS)
710 || IS_INSN_TYPE (STOR_IMM_INS)
711 || IS_INSN_TYPE (CSTBIT_INS))
713 if (!signflag && crx_ins->arg[op_num].type == arg_icr)
717 crx_ins->arg[op_num].size = 22;
721 as_bad (_("Offset out of range in Instruction `%s'"), ins_parse);
724 /* load/stor instructions :
725 16-bit positive signed immediate -->> represent as 32-bit. */
726 if (IS_INSN_TYPE (LD_STOR_INS))
728 if (!signflag && crx_ins->arg[op_num].type == arg_cr)
732 crx_ins->arg[op_num].size = 32;
736 as_bad (_("Offset out of range in Instruction `%s'"), ins_parse);
739 /* Post-increment mode :
740 12-bit positive signed immediate -->> represent as 28-bit. */
741 if (IS_INSN_TYPE (CSTBIT_INS)
742 || IS_INSN_TYPE (LD_STOR_INS_INC)
743 || IS_INSN_TYPE (STOR_IMM_INS))
745 if (!signflag && crx_ins->arg[op_num].type == arg_cr)
749 crx_ins->arg[op_num].size = 28;
750 if (IS_INSN_TYPE (LD_STOR_INS_INC))
751 as_bad (_("Offset out of range in Instruction `%s'"), ins_parse);
754 if (IS_INSN_TYPE (CSTBIT_INS) || IS_INSN_TYPE (STOR_IMM_INS))
757 as_bad (_("Offset out of range in Instruction `%s'"), ins_parse);
763 /* Handle negative cst4 mapping for arithmetic/cmp&br operations. */
764 if (signflag && !relocatable
765 && ((IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS))
766 || ((IS_INSN_TYPE (CMPBR_INS) && op_num == 0))))
768 for (cst4_op = cst4_map; cst4_op < (cst4_map + cst4_maps); cst4_op++)
770 if (crx_ins->arg[op_num].constant == (unsigned int)(-cst4_op->value))
772 crx_ins->arg[op_num].size = 4;
773 crx_ins->arg[op_num].constant = cst4_op->binary;
774 crx_ins->arg[op_num].signflag = 0;
779 /* Because of the cst4 mapping -- -1 and -4 already handled above
780 as well as for relocatable cases. */
781 if (signflag && IS_INSN_TYPE (ARITH_BYTE_INS))
785 if (crx_ins->arg[op_num].constant <= 0xffff)
786 crx_ins->arg[op_num].size = 16;
788 /* Setting to 18 so that there is no match. */
789 crx_ins->arg[op_num].size = 18;
792 crx_ins->arg[op_num].size = 16;
796 if (signflag && IS_INSN_TYPE (ARITH_INS))
798 /* For all immediates which can be expressed in less than 16 bits. */
799 if (crx_ins->arg[op_num].constant <= 0xffff && !relocatable)
801 crx_ins->arg[op_num].size = 16;
804 /* Either it is relocatable or not representable in 16 bits. */
805 if (crx_ins->arg[op_num].constant < 0xffffffff || relocatable)
807 crx_ins->arg[op_num].size = 32;
810 crx_ins->arg[op_num].size = 33;
814 if (signflag && !relocatable)
818 crx_ins->arg[op_num].size = cnt_bits;
820 /* Checking for Error Conditions. */
821 if (IS_INSN_TYPE (ARITH_INS) && !signflag)
824 as_bad (_("Cannot represent Immediate in %d bits in Instruction `%s'"),
825 cnt_bits, ins_parse);
827 else if (IS_INSN_TYPE (ARITH_BYTE_INS) && !signflag)
830 as_bad (_("Cannot represent Immediate in %d bits in Instruction `%s'"),
831 cnt_bits, ins_parse);
835 /* Handle the constants -immediate/absolute values and
836 Labels (jump targets/Memory locations). */
839 process_label_constant (char *str, ins * crx_ins, int number)
842 unsigned long int temp, cnt;
843 const cst4_entry *cst4_op;
845 int constant_val = 0;
846 save = input_line_pointer;
854 else if (str[0] == '+')
857 input_line_pointer = str;
859 expression (&crx_ins->exp);
861 switch (crx_ins->exp.X_op)
865 /* Missing or bad expr becomes absolute 0. */
866 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
868 crx_ins->exp.X_op = O_constant;
869 crx_ins->exp.X_add_number = 0;
870 crx_ins->exp.X_add_symbol = (symbolS *) 0;
871 crx_ins->exp.X_op_symbol = (symbolS *) 0;
875 crx_ins->arg[number].constant = crx_ins->exp.X_add_number;
876 constant_val = crx_ins->exp.X_add_number;
877 if ((IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
883 unsigned int jump_value = 0;
884 int BR_MASK = 0, BR_SIZE = 0;
891 strncat (temp_str, str, strlen (str));
892 temp64 = strtoll (temp_str, (char **) &ptr,0);
895 as_bad (_("Odd Offset in displacement in Instruction `%s'"),
898 /* Determine the branch size. */
899 jump_value = (unsigned int)temp64 & 0xFFFFFFFF;
900 if (((jump_value & 0xFFFFFF00) == 0xFFFFFF00)
901 || ((jump_value & 0xFFFFFF00) == 0x0))
907 if (((jump_value & 0xFF000000) == 0xFF000000)
908 || ((jump_value & 0xFF000000) == 0x0))
913 jump_value = jump_value >> 1;
914 crx_ins->arg[number].constant = jump_value & BR_MASK;
915 crx_ins->arg[number].size = BR_SIZE;
917 crx_ins->arg[number].signflag = signflag;
918 input_line_pointer = save;
919 return crx_ins->exp.X_op;
922 if (IS_INSN_TYPE (BRANCH_INS)
923 || IS_INSN_MNEMONIC ("bal")
924 || IS_INSN_TYPE (DCR_BRANCH_INS))
929 unsigned int jump_value = 0;
930 int BR_MASK = 0, BR_SIZE = 0;
938 strncat (temp_str, str, strlen (str));
939 temp64 = strtoll (temp_str, (char **) &ptr,0);
942 as_bad (_("Odd Offset in displacement in Instruction `%s'"),
945 /* Determine the branch size. */
946 jump_value = (unsigned int)temp64 & 0xFFFFFFFF;
947 if (!IS_INSN_MNEMONIC ("bal") && !IS_INSN_TYPE (DCR_BRANCH_INS)
948 && (((jump_value & 0xFFFFFF00) == 0xFFFFFF00)
949 || ((jump_value & 0xFFFFFF00) == 0x0)))
954 else if (((jump_value & 0xFFFF0000) == 0xFFFF0000)
955 || ((jump_value & 0xFFFF0000) == 0x0))
962 BR_MASK = 0xFFFFFFFF;
965 jump_value = jump_value >> 1;
966 crx_ins->arg[number].constant = jump_value & BR_MASK;
967 crx_ins->arg[number].size = BR_SIZE;
969 crx_ins->arg[number].signflag = signflag;
970 input_line_pointer = save;
971 return crx_ins->exp.X_op;
973 /* Fix for movd $0xF12344, r0 -- signflag has to be set. */
974 if (constant_val < 0 && signflag != 1
975 && !IS_INSN_TYPE (LD_STOR_INS) && !IS_INSN_TYPE (LD_STOR_INS_INC)
976 && !IS_INSN_TYPE (CSTBIT_INS) && !IS_INSN_TYPE (STOR_IMM_INS)
977 && !IS_INSN_TYPE (BRANCH_INS) && !IS_INSN_MNEMONIC ("bal"))
979 crx_ins->arg[number].constant =
980 ~(crx_ins->arg[number].constant) + 1;
983 /* For load/store instruction when the value is in the offset part. */
984 if (constant_val < 0 && signflag != 1
985 && (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (LD_STOR_INS_INC)
986 || IS_INSN_TYPE (CSTBIT_INS) || IS_INSN_TYPE (STOR_IMM_INS)))
988 if (crx_ins->arg[number].type == arg_cr
989 || crx_ins->arg[number].type == arg_icr)
991 crx_ins->arg[number].constant =
992 ~(crx_ins->arg[number].constant) + 1;
998 /* Signflag in never set in case of load store instructions
999 Mapping in case of only the arithinsn case. */
1000 if ((crx_ins->arg[number].constant != 1
1001 && crx_ins->arg[number].constant != 4)
1002 || (!IS_INSN_TYPE (ARITH_INS)
1003 && !IS_INSN_TYPE (ARITH_BYTE_INS)
1004 && !IS_INSN_TYPE (CMPBR_INS)))
1006 /* Counting the number of bits required to represent
1009 temp = crx_ins->arg[number].constant - 1;
1015 crx_ins->arg[number].size = cnt + 1;
1016 crx_ins->arg[number].constant =
1017 ~(crx_ins->arg[number].constant) + 1;
1018 if (IS_INSN_TYPE (ARITH_INS) || IS_INSN_TYPE (ARITH_BYTE_INS))
1023 temp64 = strtoull (str, (char **) &ptr, 0);
1025 crx_ins->arg[number].size = 5;
1027 if (IS_INSN_TYPE (ARITH_INS))
1029 if (crx_ins->arg[number].size > 32
1030 || (temp64 > ULONG_MAX))
1032 if (crx_ins->arg[number].size > 32)
1033 as_bad (_("In Instruction `%s': Immediate size is \
1034 %lu bits cannot be accomodated"),
1035 ins_parse, cnt + 1);
1037 if (temp64 > ULONG_MAX)
1038 as_bad (_("Value given more than 32 bits in \
1039 Instruction `%s'"), ins_parse);
1042 if (IS_INSN_TYPE (ARITH_BYTE_INS))
1044 if (crx_ins->arg[number].size > 16
1045 || !((temp64 & 0xFFFF0000) == 0xFFFF0000
1046 || (temp64 & 0xFFFF0000) == 0x0))
1048 if (crx_ins->arg[number].size > 16)
1049 as_bad (_("In Instruction `%s': Immediate size is \
1050 %lu bits cannot be accomodated"),
1051 ins_parse, cnt + 1);
1053 if (!((temp64 & 0xFFFF0000) == 0xFFFF0000
1054 || (temp64 & 0xFFFF0000) == 0x0))
1055 as_bad (_("Value given more than 16 bits in \
1056 Instruction `%s'"), ins_parse);
1060 if (IS_INSN_TYPE (LD_STOR_INS) && crx_ins->arg[number].type == arg_cr)
1062 /* Cases handled ---
1063 dispub4/dispuw4/dispud4 and for load store dispubwd4
1064 is applicable only. */
1065 if (crx_ins->arg[number].size <= 4)
1066 crx_ins->arg[number].size = 5;
1068 /* Argument number is checked to distinguish between
1069 immediate and displacement in cmpbranch and bcopcond. */
1070 if ((IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
1073 if (crx_ins->arg[number].size != 32)
1074 crx_ins->arg[number].constant =
1075 crx_ins->arg[number].constant >> 1;
1078 mask_const (&crx_ins->arg[number].constant,
1079 (int) crx_ins->arg[number].size);
1084 /* Argument number is checked to distinguish between
1085 immediate and displacement in cmpbranch and bcopcond. */
1086 if (((IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
1088 || IS_INSN_TYPE (BRANCH_NEQ_INS))
1090 if (IS_INSN_TYPE (BRANCH_NEQ_INS))
1092 if (crx_ins->arg[number].constant == 0)
1093 as_bad (_("Instruction `%s' has Zero offset"), ins_parse);
1096 if (crx_ins->arg[number].constant % 2 != 0)
1097 as_bad (_("Instruction `%s' has odd offset"), ins_parse);
1099 if (IS_INSN_TYPE (BRANCH_NEQ_INS))
1101 if (crx_ins->arg[number].constant > 32
1102 || crx_ins->arg[number].constant < 2)
1103 as_bad (_("Instruction `%s' has illegal offset (%ld)"),
1104 ins_parse, crx_ins->arg[number].constant);
1106 crx_ins->arg[number].constant -= 2;
1109 crx_ins->arg[number].constant =
1110 crx_ins->arg[number].constant >> 1;
1111 get_number_of_bits (crx_ins, number);
1114 /* Compare branch argument number zero to be compared -
1116 if (IS_INSN_TYPE (CMPBR_INS) && number == 0)
1118 for (cst4_op = cst4_map; cst4_op < (cst4_map + cst4_maps); cst4_op++)
1120 if (crx_ins->arg[number].constant == (unsigned int)cst4_op->value)
1122 crx_ins->arg[number].constant = cst4_op->binary;
1128 as_bad (_("Instruction `%s' has invalid imm value as an \
1129 operand"), ins_parse);
1136 crx_ins->arg[number].constant = 0;
1137 crx_ins->rtype = BFD_RELOC_NONE;
1140 switch (crx_ins->arg[number].type)
1143 /* Have to consider various cases here. */
1144 if (IS_INSN_TYPE (LD_STOR_INS_INC))
1145 /* 'load/stor <num>(reg)+'. */
1146 crx_ins->rtype = BFD_RELOC_CRX_REGREL12;
1147 else if (IS_INSN_TYPE (CSTBIT_INS)
1148 || IS_INSN_TYPE (STOR_IMM_INS))
1149 /* 'stor imm' and '[stc]bit'. */
1150 crx_ins->rtype = BFD_RELOC_CRX_REGREL28;
1152 /* General load/stor instruction. */
1153 crx_ins->rtype = BFD_RELOC_CRX_REGREL32;
1156 /* Index Mode 22 bits relocation. */
1157 crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
1160 /* Absolute types. */
1161 /* Case for jumps...dx types. */
1163 if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
1164 crx_ins->rtype = BFD_RELOC_CRX_REL16;
1165 else if (IS_INSN_TYPE (BRANCH_INS))
1166 crx_ins->rtype = BFD_RELOC_CRX_REL8;
1167 else if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (STOR_IMM_INS)
1168 || IS_INSN_TYPE (CSTBIT_INS))
1169 crx_ins->rtype = BFD_RELOC_CRX_ABS32;
1170 else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
1171 crx_ins->rtype = BFD_RELOC_CRX_REL4;
1172 else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
1173 crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
1177 if (IS_INSN_TYPE (ARITH_INS))
1178 crx_ins->rtype = BFD_RELOC_CRX_IMM32;
1179 else if (IS_INSN_TYPE (ARITH_BYTE_INS))
1180 crx_ins->rtype = BFD_RELOC_CRX_IMM16;
1185 crx_ins->arg[number].size = (bfd_reloc_type_lookup (stdoutput, crx_ins->rtype))->bitsize;
1192 input_line_pointer = save;
1193 crx_ins->arg[number].signflag = signflag;
1194 return crx_ins->exp.X_op;
1197 /* Get the values of the scale to be encoded -
1198 used for the scaled index mode of addressing. */
1201 exponent2scale (int val)
1205 /* If 'val' is 0, the following 'for' will be an endless loop. */
1209 for (exponent = 0; (val != 1); val >>= 1, exponent++)
1215 /* This is used to set the index mode parameters. Used to set the attributes of
1216 an indexmode type of operand. op_num is the operand number. */
1219 set_indexmode_parameters (char *operand, ins * crx_ins, int op_num)
1221 char address_str[30];
1222 char scale_str[MAX_OPERANDS];
1224 char reg_name[MAX_REGNAME_LEN];
1225 char regindex_name[MAX_REGNAME_LEN];
1227 int reg_counter = 0, addr_cnt = 0, temp_int_val = 0;
1229 switch (crx_ins->arg[op_num].type)
1232 while (operand[i] != '(')
1234 address_str[addr_cnt++] = operand[i];
1237 address_str[addr_cnt] = '\0';
1238 process_label_constant (address_str, crx_ins, op_num);
1241 while (operand[i] != ',' && operand[i] != ' ')
1243 reg_name[reg_counter++] = operand[i];
1246 reg_name[reg_counter] = '\0';
1247 if ((crx_ins->arg[op_num].r = get_register (reg_name)) == nullregister)
1248 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1249 reg_name, ins_parse);
1252 while (operand[i] == ' ')
1256 while (operand[i] != ')' && operand[i] != ',')
1258 regindex_name[reg_counter++] = operand[i];
1261 regindex_name[reg_counter] = '\0';
1263 if ((crx_ins->arg[op_num].i_r = get_register (regindex_name))
1265 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1266 regindex_name, ins_parse);
1268 /* Setting the scale parameters. */
1269 while (operand[i] == ' ')
1272 if (operand[i] == ')')
1273 crx_ins->arg[op_num].scale = 0;
1276 if (operand[i] == ',')
1279 while (operand[i] != ' ' && operand[i] != ')')
1281 scale_str[scale_cnt++] = operand[i];
1285 scale_str[scale_cnt] = '\0';
1286 /* Preprocess the scale string. */
1287 if (strstr (scale_str, "0x") != NULL
1288 || strstr (scale_str, "0X") != NULL)
1290 sscanf (scale_str, "%x", &temp_int_val);
1291 memset (&scale_str, '\0', sizeof (scale_str));
1292 sprintf (scale_str, "%d", temp_int_val);
1294 /* Preprocess over. */
1295 temp_int_val = atoi (scale_str);
1297 if (temp_int_val != 1 && temp_int_val != 2
1298 && temp_int_val != 4 && temp_int_val != 8)
1299 as_bad (_("Illegal Scale - `%s'"), scale_str);
1301 crx_ins->arg[op_num].scale = exponent2scale (temp_int_val);
1309 /* Parsing the operands of types
1313 - offset(rbase)+ (post-increment mode). */
1316 set_cons_rparams (char *operand, ins * crx_ins, int op_num)
1318 int i = 0, reg_count = 0;
1319 char reg_name[MAX_REGNAME_LEN];
1320 int change_flag = 0;
1322 if (crx_ins->arg[op_num].type == arg_dc)
1325 switch (crx_ins->arg[op_num].type)
1327 case arg_sc: /* Case *+347. */
1328 case arg_dc: /* Case $18. */
1330 case arg_c:/* Case where its a simple constant. */
1331 process_label_constant (operand + i, crx_ins, op_num);
1332 crx_ins->arg[op_num].type = arg_c;
1334 case arg_dcr: /* Case $9(r13). */
1336 case arg_cr: /* Case 9(r13. */
1337 while (operand[i] != '(')
1340 process_label_constant (operand, crx_ins, op_num);
1345 while (operand[i] != ')')
1347 reg_name[reg_count] = operand[i];
1351 reg_name[reg_count] = '\0';
1352 if ((crx_ins->arg[op_num].r = get_register (reg_name)) == nullregister)
1353 as_bad (_("Illegal register `%s' in Instruction `%s'"),
1354 reg_name, ins_parse);
1356 if (crx_ins->arg[op_num].type != arg_rbase)
1357 crx_ins->arg[op_num].type = arg_cr;
1362 if (change_flag == 1)
1363 crx_ins->arg[op_num].type = arg_ic;
1366 /* This is used to get the operand attributes -
1367 operand - current operand to be used
1368 number - operand number
1369 crx_ins - current assembled instruction. */
1372 get_operandtype (char *operand, int number, ins * crx_ins)
1378 /* When it is a register. */
1387 /* Check whether this is a general processor register. */
1388 ret_val = get_register (operand);
1389 if (ret_val != nullregister)
1391 crx_ins->arg[number].type = arg_r;
1392 crx_ins->arg[number].r = ret_val;
1393 crx_ins->arg[number].size = REG_SIZE;
1397 /* Check whether this is a core [special] coprocessor register. */
1398 ret_val = get_copregister (operand);
1399 if (ret_val != nullcopregister)
1401 crx_ins->arg[number].type = arg_copr;
1403 crx_ins->arg[number].type = arg_copsr;
1404 crx_ins->arg[number].cr = ret_val;
1405 crx_ins->arg[number].size = REG_SIZE;
1409 if (strchr (operand, '(') != NULL)
1411 if (strchr (operand, ',') != NULL
1412 && (strchr (operand, ',') > strchr (operand, '(')))
1414 crx_ins->arg[number].type = arg_icr;
1415 crx_ins->arg[number].constant = 0;
1416 set_indexmode_parameters (operand, crx_ins, number);
1417 get_number_of_bits (crx_ins, number);
1421 crx_ins->arg[number].type = arg_cr;
1424 crx_ins->arg[number].type = arg_c;
1425 crx_ins->arg[number].constant = 0;
1426 set_cons_rparams (operand, crx_ins, number);
1427 get_number_of_bits (crx_ins, number);
1432 if (strchr (operand, '(') != NULL)
1433 crx_ins->arg[number].type = arg_dcr;
1435 crx_ins->arg[number].type = arg_dc;
1436 crx_ins->arg[number].constant = 0;
1437 set_cons_rparams (operand, crx_ins, number);
1438 get_number_of_bits (crx_ins, number);
1442 crx_ins->arg[number].type = arg_rbase;
1443 set_cons_rparams (operand, crx_ins, number);
1444 crx_ins->arg[number].size = REG_SIZE;
1447 crx_ins->arg[number].type = arg_sc;
1448 crx_ins->arg[number].constant = 0;
1449 set_cons_rparams (operand, crx_ins, number);
1450 get_number_of_bits (crx_ins, number);
1464 if (strchr (operand, '(') != NULL)
1466 if (strchr (operand, ',') != NULL
1467 && (strchr (operand, ',') > strchr (operand, '(')))
1469 crx_ins->arg[number].type = arg_icr;
1470 crx_ins->arg[number].constant = 0;
1471 set_indexmode_parameters (operand, crx_ins, number);
1472 get_number_of_bits (crx_ins, number);
1476 crx_ins->arg[number].type = arg_cr;
1479 crx_ins->arg[number].type = arg_c;
1480 crx_ins->arg[number].constant = 0;
1481 set_cons_rparams (operand, crx_ins, number);
1482 get_number_of_bits (crx_ins, number);
1485 if (strchr (operand, '(') != NULL)
1487 if (strchr (operand, ',') != NULL
1488 && (strchr (operand, ',') > strchr (operand, '(')))
1490 crx_ins->arg[number].type = arg_icr;
1491 crx_ins->arg[number].constant = 0;
1492 set_indexmode_parameters (operand, crx_ins, number);
1493 get_number_of_bits (crx_ins, number);
1497 crx_ins->arg[number].type = arg_cr;
1500 crx_ins->arg[number].type = arg_c;
1501 crx_ins->arg[number].constant = 0;
1502 set_cons_rparams (operand, crx_ins, number);
1503 get_number_of_bits (crx_ins, number);
1508 /* Operands are parsed over here, separated into various operands. Each operand
1509 is then analyzed to fillup the fields in the crx_ins data structure. */
1512 parse_operands (ins * crx_ins, char *operands)
1514 char *operandS; /* Operands string. */
1515 char *operandH, *operandT; /* Single operand head/tail pointers. */
1516 int allocated = 0; /* Indicates a new operands string was allocated. */
1517 char *operand[MAX_OPERANDS]; /* Separating the operands. */
1518 int op_num = 0; /* Current operand number we are parsing. */
1519 int bracket_flag = 0; /* Indicates a bracket '(' was found. */
1520 int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */
1522 /* Preprocess the list of registers, if necessary. */
1523 operandS = operandH = operandT = (INST_HAS_REG_LIST) ?
1524 preprocess_reglist (operands, &allocated) : operands;
1526 while (*operandT != '\0')
1528 if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
1531 operand[op_num++] = strdup (operandH);
1532 operandH = operandT;
1536 if (*operandT == ' ')
1537 as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
1539 if (*operandT == '(')
1541 else if (*operandT == '[')
1542 sq_bracket_flag = 1;
1544 if (*operandT == ')')
1549 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1551 else if (*operandT == ']')
1553 if (sq_bracket_flag)
1554 sq_bracket_flag = 0;
1556 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1559 if (bracket_flag == 1 && *operandT == ')')
1561 else if (sq_bracket_flag == 1 && *operandT == ']')
1562 sq_bracket_flag = 0;
1567 /* Adding the last operand. */
1568 operand[op_num++] = strdup (operandH);
1569 crx_ins->nargs = op_num;
1571 /* Verifying correct syntax of operands (all brackets should be closed). */
1572 if (bracket_flag || sq_bracket_flag)
1573 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
1575 /* Now to recongnize the operand types. */
1576 for (op_num = 0; op_num < crx_ins->nargs; op_num++)
1578 get_operandtype (operand[op_num], op_num, crx_ins);
1579 free (operand[op_num]);
1586 /* Get the trap index in dispatch table, given its name.
1587 This routine is used by assembling the 'excp' instruction. */
1592 const trap_entry *trap;
1594 for (trap = crx_traps; trap < (crx_traps + NUMTRAPS); trap++)
1595 if (strcasecmp (trap->name, s) == 0)
1598 as_bad (_("Unknown exception: `%s'"), s);
1602 /* Post-Increment instructions, as well as Store-Immediate instructions, are a
1603 sub-group within load/stor instruction groups.
1604 Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
1605 advance the instruction pointer to the start of that sub-group (that is, up
1606 to the first instruction of that type).
1607 Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS. */
1610 handle_LoadStor (char *operands)
1612 /* Post-Increment instructions precede Store-Immediate instructions in
1613 CRX instruction table, hence they are handled before.
1614 This synchronization should be kept. */
1616 /* Assuming Post-Increment insn has the following format :
1617 'MNEMONIC DISP(REG)+, REG' (e.g. 'loadw 12(r5)+, r6').
1618 LD_STOR_INS_INC are the only store insns containing a plus sign (+). */
1619 if (strstr (operands, ")+") != NULL)
1621 while (! IS_INSN_TYPE (LD_STOR_INS_INC))
1626 /* Assuming Store-Immediate insn has the following format :
1627 'MNEMONIC $DISP, ...' (e.g. 'storb $1, 12(r5)').
1628 STOR_IMM_INS are the only store insns containing a dollar sign ($). */
1629 if (strstr (operands, "$") != NULL)
1630 while (! IS_INSN_TYPE (STOR_IMM_INS))
1634 /* Top level module where instruction parsing starts.
1635 crx_ins - data structure holds some information.
1636 operands - holds the operands part of the whole instruction. */
1639 parse_insn (ins *insn, char *operands)
1641 /* Handle 'excp'/'cinv' */
1642 if (IS_INSN_MNEMONIC ("excp") || IS_INSN_MNEMONIC ("cinv"))
1645 insn->arg[0].type = arg_ic;
1646 insn->arg[0].size = 4;
1647 insn->arg[0].constant = IS_INSN_MNEMONIC ("excp") ?
1648 gettrap (operands) : get_cinv_parameters (operands);
1652 /* Handle load/stor unique instructions before parsing. */
1653 if (IS_INSN_TYPE (LD_STOR_INS))
1654 handle_LoadStor (operands);
1656 if (operands != NULL)
1657 parse_operands (insn, operands);
1660 /* Cinv instruction requires special handling. */
1663 get_cinv_parameters (char * operand)
1666 int d_used = 0, i_used = 0, u_used = 0, b_used = 0;
1670 if (*p == ',' || *p == ' ')
1682 as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
1685 return ((b_used ? 8 : 0)
1688 + (u_used ? 1 : 0));
1691 /* Retrieve the opcode image of a given register.
1692 If the register is illegal for the current instruction,
1696 getreg_image (reg r)
1698 const reg_entry *reg;
1700 int is_procreg = 0; /* Nonzero means argument should be processor reg. */
1702 if (((IS_INSN_MNEMONIC ("mtpr")) && (processing_arg_number == 1))
1703 || ((IS_INSN_MNEMONIC ("mfpr")) && (processing_arg_number == 0)) )
1706 /* Check whether the register is in registers table. */
1708 reg = &crx_regtab[r];
1709 /* Check whether the register is in coprocessor registers table. */
1710 else if (r < MAX_COPREG)
1711 reg = &crx_copregtab[r-MAX_REG];
1712 /* Register not found. */
1715 as_bad (_("Unknown register: `%d'"), r);
1719 reg_name = reg->name;
1721 /* Issue a error message when register is illegal. */
1723 as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
1724 reg_name, ins_parse); \
1730 if (is_procreg || (instruction->flags & USER_REG))
1735 case CRX_CFG_REGTYPE:
1748 case CRX_CS_REGTYPE:
1758 /* Routine used to get the binary-string equivalent of a integer constant
1759 which currently require currbits to represent itself to be extended to
1762 static unsigned long int
1763 getconstant (unsigned long int x, int nbits)
1766 unsigned long int temp = x;
1774 /* Escape sequence to next 16bit immediate. */
1776 as_bad (_("Value `%ld' truncated to fit `%d' bits in instruction `%s'"),
1781 x |= SET_BITS_MASK (cnt, nbits - cnt);
1783 x &= CLEAR_BITS_MASK (cnt, nbits - cnt);
1786 /* The following expression avoids overflow if
1787 'nbits' is the number of bits in 'bfd_vma'. */
1788 return (x & ((((1 << (nbits - 1)) - 1) << 1) | 1));
1791 /* Print a constant value to 'output_opcode':
1792 ARG holds the operand's type and value.
1793 SHIFT represents the location of the operand to be print into.
1794 NBITS determines the size (in bits) of the constant. */
1797 print_constant (int nbits, int shift, argument *arg)
1799 unsigned long mask = 0;
1801 long constant = getconstant (arg->constant, nbits);
1809 /* mask the upper part of the constant, that is, the bits
1810 going to the lowest byte of output_opcode[0].
1811 The upper part of output_opcode[1] is always filled,
1812 therefore it is always masked with 0xFFFF. */
1813 mask = (1 << (nbits - 16)) - 1;
1814 /* Divide the constant between two consecutive words :
1816 +---------+---------+---------+---------+
1817 | | X X X X | X X X X | |
1818 +---------+---------+---------+---------+
1819 output_opcode[0] output_opcode[1] */
1821 CRX_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
1822 CRX_PRINT (1, (constant & 0xFFFF), WORD_SHIFT);
1827 /* Special case - in arg_cr, the SHIFT represents the location
1828 of the REGISTER, not the constant, which is itself not shifted. */
1829 if (arg->type == arg_cr)
1831 CRX_PRINT (0, constant, 0);
1835 /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
1836 always filling the upper part of output_opcode[1]. If we mistakenly
1837 write it to output_opcode[0], the constant prefix (that is, 'match')
1840 +---------+---------+---------+---------+
1841 | 'match' | | X X X X | |
1842 +---------+---------+---------+---------+
1843 output_opcode[0] output_opcode[1] */
1845 if ((instruction->size > 2) && (shift == WORD_SHIFT))
1846 CRX_PRINT (1, constant, WORD_SHIFT);
1848 CRX_PRINT (0, constant, shift);
1852 CRX_PRINT (0, constant, shift);
1857 /* Print an operand to 'output_opcode', which later on will be
1858 printed to the object file:
1859 ARG holds the operand's type, size and value.
1860 SHIFT represents the printing location of operand.
1861 NBITS determines the size (in bits) of a constant operand. */
1864 print_operand (int nbits, int shift, argument *arg)
1869 CRX_PRINT (0, getreg_image (arg->r), shift);
1873 if (arg->cr < c0 || arg->cr > c15)
1874 as_bad (_("Illegal Co-processor register in Instruction `%s' "),
1876 CRX_PRINT (0, getreg_image (arg->cr), shift);
1880 if (arg->cr < cs0 || arg->cr > cs15)
1881 as_bad (_("Illegal Co-processor special register in Instruction `%s' "),
1883 CRX_PRINT (0, getreg_image (arg->cr), shift);
1887 print_constant (nbits, shift, arg);
1892 +--------------------------------+
1893 | r_base | r_idx | scl| disp |
1894 +--------------------------------+ */
1895 CRX_PRINT (0, getreg_image (arg->r), 12);
1896 CRX_PRINT (0, getreg_image (arg->i_r), 8);
1897 CRX_PRINT (0, arg->scale, 6);
1898 print_constant (nbits, shift, arg);
1902 CRX_PRINT (0, getreg_image (arg->r), shift);
1906 /* case base_cst4. */
1907 if ((instruction->flags & DISPU4MAP) && cst4flag)
1908 output_opcode[0] |= (getconstant (arg->constant, nbits)
1909 << (shift + REG_SIZE));
1911 /* rbase_disps<NN> and other such cases. */
1912 print_constant (nbits, shift, arg);
1913 /* Add the register argument to the output_opcode. */
1914 CRX_PRINT (0, getreg_image (arg->r), shift);
1918 print_constant (nbits, shift, arg);
1926 /* Retrieve the number of operands for the current assembled instruction. */
1929 get_number_of_operands (void)
1933 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
1938 /* Assemble a single instruction :
1939 Instruction has been parsed and all operand values set appropriately.
1940 Algorithm for assembling -
1941 For instruction to be assembled:
1942 Step 1: Find instruction in the array crx_instruction with same mnemonic.
1943 Step 2: Find instruction with same operand types.
1944 Step 3: If (size_of_operands) match then done, else increment the
1945 array_index and goto Step3.
1946 Step 4: Cannot assemble
1947 Returns 1 upon success, 0 upon failure. */
1950 assemble_insn (char *mnemonic, ins *insn)
1952 /* Argument type of each operand in the instruction we are looking for. */
1953 argtype atyp[MAX_OPERANDS];
1954 /* Argument type of each operand in the current instruction. */
1955 argtype atyp_act[MAX_OPERANDS];
1956 /* Size (in bits) of each operand in the instruction we are looking for. */
1957 int bits[MAX_OPERANDS];
1958 /* Size (in bits) of each operand in the current instruction. */
1959 int bits_act[MAX_OPERANDS];
1960 /* Location (in bits) of each operand in the current instruction. */
1961 int shift_act[MAX_OPERANDS];
1962 /* Instruction type to match. */
1966 int dispu4map_type = 0;
1967 int changed_already = 0;
1968 unsigned int temp_value = 0;
1970 /* A pointer to the argument's constant value. */
1971 unsigned long int *cons;
1972 /* Pointer to loop over all cst4_map entries. */
1973 const cst4_entry *cst4_op;
1975 /* Instruction has no operands -> copy only the constant opcode. */
1976 if (insn->nargs == 0)
1978 output_opcode[0] = BIN (instruction->match, instruction->match_bits);
1982 /* Find instruction with same number of operands. */
1983 while (get_number_of_operands () != insn->nargs
1984 && IS_INSN_MNEMONIC (mnemonic))
1987 if (!IS_INSN_MNEMONIC (mnemonic))
1990 /* Initialize argument type and size of each given operand. */
1991 for (i = 0; i < insn->nargs; i++)
1993 atyp[i] = insn->arg[i].type;
1994 bits[i] = insn->arg[i].size;
1997 /* Initialize argument type and size of each operand in current inst. */
2001 /* In some case, same mnemonic can appear with different instruction types.
2002 For example, 'storb' is supported with 3 different types :
2003 LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
2004 We assume that when reaching this point, the instruction type was
2005 pre-determined. We need to make sure that the type stays the same
2006 during a search for matching instruction. */
2007 ins_type = CRX_INS_TYPE(instruction->flags);
2010 /* Check we didn't get to end of table. */
2011 && instruction->mnemonic != NULL
2012 /* Check that the actual mnemonic is still available. */
2013 && IS_INSN_MNEMONIC (mnemonic)
2014 /* Check that the instruction type wasn't changed. */
2015 && IS_INSN_TYPE(ins_type))
2017 /* Check for argement type compatibility. */
2018 for (i = 0; i < insn->nargs; i++)
2020 if (atyp_act[i] == atyp[i])
2031 for (i = 0; i < insn->nargs; i++)
2033 if ((get_flags (instruction->operands[i].op_type) & OPERAND_UNSIGNED)
2034 && (insn->arg[i].signflag))
2044 /* Try again with next instruction. */
2052 /* Check for size compatibility. */
2053 for (i = 0; i < insn->nargs; i++)
2055 if (bits[i] > bits_act[i])
2057 /* Actual size is too small - try again. */
2070 /* Full match is found. */
2077 /* We haven't found a match - instruction can't be assembled. */
2080 /* Full match - print the final image. */
2082 /* If the post-increment address mode is used and the load/store
2083 source register is the same as rbase, the result of the
2084 instruction is undefined. */
2085 if (IS_INSN_TYPE (LD_STOR_INS_INC))
2087 /* Enough to verify that one of the arguments is a simple reg. */
2088 if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
2089 if (insn->arg[0].r == insn->arg[1].r)
2090 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
2094 /* Optimization: Omit a zero displacement in bit operations,
2095 saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)'). */
2096 if (IS_INSN_TYPE (CSTBIT_INS) && !relocatable)
2098 if ((instruction->operands[1].op_type == rbase_disps12)
2099 && (insn->arg[1].constant == 0))
2106 /* Some instruction assume the stack pointer as rptr operand.
2107 Issue an error when the register to be loaded is also SP. */
2108 if (instruction->flags & NO_SP)
2110 if (getreg_image (insn->arg[0].r) == getreg_image (sp))
2111 as_bad (_("`%s' has undefined result"), ins_parse);
2114 /* If the rptr register is specified as one of the registers to be loaded,
2115 the final contents of rptr are undefined. Thus, we issue an error. */
2116 if (instruction->flags & NO_RPTR)
2118 if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
2119 as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
2120 getreg_image (insn->arg[0].r));
2123 /* Handle positive constants. */
2126 if ((instruction->flags & DISPU4MAP) && !relocatable)
2128 /* Get the map type of the instruction. */
2129 instrtype = instruction->flags & REVERSE_MATCH ? 0 : 1;
2130 cons = &insn->arg[instrtype].constant;
2131 dispu4map_type = instruction->flags & DISPU4MAP;
2133 switch (dispu4map_type)
2136 /* 14 and 15 are reserved escape sequences of dispub4. */
2137 if (*cons == 14 || *cons == 15)
2145 /* Mapping has to be done. */
2146 if (*cons <= 15 && *cons % 2 != 0)
2151 else if (*cons > 15 && *cons < 27 && *cons % 2 == 0)
2156 if (*cons < 27 && *cons % 2 == 0)
2161 /* Mapping has to be done. */
2162 if (*cons <= 15 && *cons % 4 != 0)
2167 else if (*cons > 15 && *cons < 53 && *cons % 4 == 0)
2172 if (*cons < 53 && *cons % 4 == 0)
2176 as_bad (_("Invalid DISPU4 type"));
2181 /* Check whether a cst4 mapping has to be done. */
2182 if ((instruction->flags & CST4MAP) && !relocatable)
2184 /* 'const' equals reserved escape sequences -->>
2185 represent as i16. */
2186 if (insn->arg[0].constant == ESC_16
2187 || insn->arg[0].constant == ESC_32)
2194 /* Loop over cst4_map entries. */
2195 for (cst4_op = cst4_map; cst4_op < (cst4_map + cst4_maps);
2198 /* 'const' equals a binary, which is already mapped
2199 by a different value -->> represent as i16. */
2200 if (insn->arg[0].constant == (unsigned int)cst4_op->binary
2201 && cst4_op->binary != cst4_op->value)
2206 /* 'const' equals a value bigger than 16 -->> map to
2207 its binary and represent as cst4. */
2208 else if (insn->arg[0].constant == (unsigned int)cst4_op->value
2209 && insn->arg[0].constant >= 16)
2212 insn->arg[0].constant = cst4_op->binary;
2219 /* Special check for 'addub 0, r0' instruction -
2220 The opcode '0000 0000 0000 0000' is not allowed. */
2221 if (IS_INSN_MNEMONIC ("addub"))
2223 if ((instruction->operands[0].op_type == cst4)
2224 && instruction->operands[1].op_type == regr)
2226 if (insn->arg[0].constant == 0 && insn->arg[1].r == r0)
2230 if ((IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS)
2231 || IS_INSN_TYPE (STOR_IMM_INS)) & !relocatable)
2233 instrtype = instruction->flags & REVERSE_MATCH ? 0 : 1;
2234 changed_already = 0;
2235 /* Convert 32 bits accesses to 16 bits accesses. */
2236 if (instruction->operands[instrtype].op_type == abs32)
2238 if ((insn->arg[instrtype].constant & 0xFFFF0000) == 0xFFFF0000)
2241 insn->arg[instrtype].constant =
2242 insn->arg[instrtype].constant & 0xFFFF;
2243 insn->arg[instrtype].size = 16;
2244 changed_already = 1;
2248 /* Convert 16 bits accesses to 32 bits accesses. */
2249 if (instruction->operands[instrtype].op_type == abs16
2250 && changed_already != 1)
2253 insn->arg[instrtype].constant =
2254 insn->arg[instrtype].constant & 0xFFFF;
2255 insn->arg[instrtype].size = 32;
2258 changed_already = 0;
2262 for (i = 0; i < insn->nargs; i++)
2264 /* Mark a CST4 argument, if exists. */
2265 if (get_flags (instruction->operands[i].op_type) & OPERAND_CST4)
2268 /* Handle reserved escape sequences. */
2269 if ((get_flags (instruction->operands[i].op_type) & OPERAND_ESC)
2272 /* 0x7e and 0x7f are reserved escape sequences of dispe9. */
2273 if (insn->arg[i].constant == 0x7e || insn->arg[i].constant == 0x7f)
2275 /* Use a disps17 for these values. */
2282 /* First, copy the instruction's opcode. */
2283 output_opcode[0] = BIN (instruction->match, instruction->match_bits);
2285 /* Swap the argument values in case bcop instructions. */
2286 if (IS_INSN_TYPE (COP_BRANCH_INS))
2288 temp_value = insn->arg[0].constant;
2289 insn->arg[0].constant = insn->arg[1].constant;
2290 insn->arg[1].constant = temp_value;
2293 for (i = 0; i < insn->nargs; i++)
2295 shift_act[i] = instruction->operands[i].shift;
2296 signflag = insn->arg[i].signflag;
2297 processing_arg_number = i;
2298 print_operand (bits_act[i], shift_act[i], &insn->arg[i]);
2305 /* Set the appropriate bit for register 'r' in 'mask'.
2306 This indicates that this register is loaded or stored by
2310 mask_reg (int r, unsigned short int *mask)
2312 if ((reg)r > (reg)sp)
2314 as_bad (_("Invalid Register in Register List"));
2321 /* Preprocess register list - create a 16-bit mask with one bit for each
2322 of the 16 general purpose registers. If a bit is set, it indicates
2323 that this register is loaded or stored by the instruction. */
2326 preprocess_reglist (char *param, int *allocated)
2328 char reg_name[MAX_REGNAME_LEN]; /* Current parsed register name. */
2329 char *regP; /* Pointer to 'reg_name' string. */
2330 int reg_counter = 0; /* Count number of parsed registers. */
2331 unsigned short int mask = 0; /* Mask for 16 general purpose registers. */
2332 char *new_param; /* New created operands string. */
2333 char *paramP = param; /* Pointer to original opearands string. */
2334 char maskstring[10]; /* Array to print the mask as a string. */
2335 int hi_found = 0, lo_found = 0; /* Boolean flags for hi/lo registers. */
2339 /* If 'param' is already in form of a number, no need to preprocess. */
2340 if (strchr (paramP, '{') == NULL)
2343 /* Verifying correct syntax of operand. */
2344 if (strchr (paramP, '}') == NULL)
2345 as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
2347 while (*paramP++ != '{');
2349 new_param = (char *)xcalloc (MAX_INST_LEN, sizeof (char));
2351 strncpy (new_param, param, paramP - param - 1);
2353 while (*paramP != '}')
2356 memset (®_name, '\0', sizeof (reg_name));
2358 while (ISALNUM (*paramP))
2361 strncpy (reg_name, regP, paramP - regP);
2363 /* Coprocessor register c<N>. */
2364 if (IS_INSN_TYPE (COP_REG_INS))
2366 if (((cr = get_copregister (reg_name)) == nullcopregister)
2367 || (crx_copregtab[cr-MAX_REG].type != CRX_C_REGTYPE))
2368 as_fatal (_("Illegal register `%s' in cop-register list"), reg_name);
2369 mask_reg (getreg_image (cr - c0), &mask);
2371 /* Coprocessor Special register cs<N>. */
2372 else if (IS_INSN_TYPE (COPS_REG_INS))
2374 if (((cr = get_copregister (reg_name)) == nullcopregister)
2375 || (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
2376 as_fatal (_("Illegal register `%s' in cop-special-register list"),
2378 mask_reg (getreg_image (cr - cs0), &mask);
2380 /* User register u<N>. */
2381 else if (instruction->flags & USER_REG)
2383 if (streq(reg_name, "uhi"))
2388 else if (streq(reg_name, "ulo"))
2393 else if (((r = get_register (reg_name)) == nullregister)
2394 || (crx_regtab[r].type != CRX_U_REGTYPE))
2395 as_fatal (_("Illegal register `%s' in user register list"), reg_name);
2397 mask_reg (getreg_image (r - u0), &mask);
2399 /* General purpose register r<N>. */
2402 if (streq(reg_name, "hi"))
2407 else if (streq(reg_name, "lo"))
2412 else if (((r = get_register (reg_name)) == nullregister)
2413 || (crx_regtab[r].type != CRX_R_REGTYPE))
2414 as_fatal (_("Illegal register `%s' in register list"), reg_name);
2416 mask_reg (getreg_image (r - r0), &mask);
2419 if (++reg_counter > MAX_REGS_IN_MASK16)
2420 as_bad (_("Maximum %d bits may be set in `mask16' operand"),
2421 MAX_REGS_IN_MASK16);
2424 while (!ISALNUM (*paramP) && *paramP != '}')
2428 if (*++paramP != '\0')
2429 as_warn (_("rest of line ignored; first ignored character is `%c'"),
2432 switch (hi_found + lo_found)
2435 /* At least one register should be specified. */
2437 as_bad (_("Illegal `mask16' operand, operation is undefined - `%s'"),
2442 /* HI can't be specified without LO (and vise-versa). */
2443 as_bad (_("HI/LO registers should be specified together"));
2447 /* HI/LO registers mustn't be masked with additional registers. */
2449 as_bad (_("HI/LO registers should be specified without additional registers"));
2455 sprintf (maskstring, "$0x%x", mask);
2456 strcat (new_param, maskstring);
2460 /* Print the instruction.
2461 Handle also cases where the instruction is relaxable/relocatable. */
2464 print_insn (ins *insn)
2466 unsigned int i, j, insn_size;
2468 unsigned short words[4];
2470 /* Arrange the insn encodings in a WORD size array. */
2471 for (i = 0, j = 0; i < 2; i++)
2473 words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
2474 words[j++] = output_opcode[i] & 0xFFFF;
2477 /* Handle relaxtion. */
2478 if ((instruction->flags & RELAXABLE) && relocatable)
2482 /* Write the maximal instruction size supported. */
2483 insn_size = INSN_MAX_SIZE;
2486 if (IS_INSN_TYPE (BRANCH_INS))
2489 else if (IS_INSN_TYPE (DCR_BRANCH_INS) || IS_INSN_MNEMONIC ("bal"))
2492 else if (IS_INSN_TYPE (CMPBR_INS))
2497 this_frag = frag_var (rs_machine_dependent, insn_size * 2,
2499 insn->exp.X_add_symbol,
2500 insn->exp.X_add_number,
2505 insn_size = instruction->size;
2506 this_frag = frag_more (insn_size * 2);
2508 /* Handle relocation. */
2509 if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
2511 reloc_howto_type *reloc_howto;
2514 reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
2519 size = bfd_get_reloc_size (reloc_howto);
2521 if (size < 1 || size > 4)
2524 fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
2525 size, &insn->exp, reloc_howto->pc_relative,
2530 /* Write the instruction encoding to frag. */
2531 for (i = 0; i < insn_size; i++)
2533 md_number_to_chars (this_frag, (valueT) words[i], 2);
2538 /* This is the guts of the machine-dependent assembler. OP points to a
2539 machine dependent instruction. This function is supposed to emit
2540 the frags/bytes it assembles to. */
2543 md_assemble (char *op)
2549 /* Reset global variables for a new instruction. */
2550 reset_vars (op, &crx_ins);
2552 /* Strip the mnemonic. */
2553 for (param = op; *param != 0 && !ISSPACE (*param); param++)
2558 /* Find the instruction. */
2559 instruction = (const inst *) hash_find (crx_inst_hash, op);
2560 if (instruction == NULL)
2562 as_bad (_("Unknown opcode: `%s'"), op);
2566 /* Tie dwarf2 debug info to the address at the start of the insn. */
2567 dwarf2_emit_insn (0);
2569 if (NO_OPERANDS_INST (op))
2570 /* Handle instructions with no operands. */
2573 /* Parse the instruction's operands. */
2574 parse_insn (&crx_ins, param);
2576 /* Assemble the instruction. */
2577 if (assemble_insn (op, &crx_ins) == 0)
2579 as_bad (_("Illegal operands in instruction : `%s'"), ins_parse);
2583 /* Print the instruction. */
2584 print_insn (&crx_ins);