1 /* tc-bfin.c -- Assembler for the ADI Blackfin.
2 Copyright 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
5 This file is part of GAS, the GNU Assembler.
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 #include "struc-symbol.h"
24 #include "bfin-defs.h"
26 #include "safe-ctype.h"
28 #include "dwarf2dbg.h"
31 #include "elf/common.h"
34 extern int yyparse (void);
35 struct yy_buffer_state;
36 typedef struct yy_buffer_state *YY_BUFFER_STATE;
37 extern YY_BUFFER_STATE yy_scan_string (const char *yy_str);
38 extern void yy_delete_buffer (YY_BUFFER_STATE b);
39 static parse_state parse (char *line);
41 /* Global variables. */
42 struct bfin_insn *insn;
45 extern struct obstack mempool;
48 /* Flags to set in the elf header */
49 #define DEFAULT_FLAGS 0
52 # define DEFAULT_FDPIC EF_BFIN_FDPIC
54 # define DEFAULT_FDPIC 0
57 static flagword bfin_flags = DEFAULT_FLAGS | DEFAULT_FDPIC;
58 static const char *bfin_pic_flag = DEFAULT_FDPIC ? "-mfdpic" : (const char *)0;
67 static const struct bfin_reg_entry bfin_reg_info[] = {
189 {"sftreset", REG_sftreset},
190 {"omode", REG_omode},
191 {"excause", REG_excause},
192 {"emucause", REG_emucause},
193 {"idle_req", REG_idle_req},
194 {"hwerrcause", REG_hwerrcause},
198 {"ASTAT", REG_ASTAT},
204 {"CYCLES", REG_CYCLES},
205 {"CYCLES2", REG_CYCLES2},
207 {"SEQSTAT", REG_SEQSTAT},
208 {"SYSCFG", REG_SYSCFG},
213 {"EMUDAT", REG_EMUDAT},
217 /* Blackfin specific function to handle FD-PIC pointer initializations. */
220 bfin_pic_ptr (int nbytes)
228 #ifdef md_flush_pending_output
229 md_flush_pending_output ();
232 if (is_it_end_of_statement ())
234 demand_empty_rest_of_line ();
239 md_cons_align (nbytes);
244 bfd_reloc_code_real_type reloc_type = BFD_RELOC_BFIN_FUNCDESC;
246 if (strncasecmp (input_line_pointer, "funcdesc(", 9) == 0)
248 input_line_pointer += 9;
250 if (*input_line_pointer == ')')
251 input_line_pointer++;
253 as_bad (_("missing ')'"));
256 error ("missing funcdesc in picptr");
260 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
263 while (*input_line_pointer++ == ',');
265 input_line_pointer--; /* Put terminator back into stream. */
266 demand_empty_rest_of_line ();
270 bfin_s_bss (int ignore ATTRIBUTE_UNUSED)
274 temp = get_absolute_expression ();
275 subseg_set (bss_section, (subsegT) temp);
276 demand_empty_rest_of_line ();
279 const pseudo_typeS md_pseudo_table[] = {
280 {"align", s_align_bytes, 0},
283 {"picptr", bfin_pic_ptr, 4},
284 {"code", obj_elf_section, 0},
289 {"pdata", s_ignore, 0},
290 {"var", s_ignore, 0},
291 {"bss", bfin_s_bss, 0},
295 /* Characters that are used to denote comments and line separators. */
296 const char comment_chars[] = "";
297 const char line_comment_chars[] = "#";
298 const char line_separator_chars[] = ";";
300 /* Characters that can be used to separate the mantissa from the
301 exponent in floating point numbers. */
302 const char EXP_CHARS[] = "eE";
304 /* Characters that mean this number is a floating point constant.
305 As in 0f12.456 or 0d1.2345e12. */
306 const char FLT_CHARS[] = "fFdDxX";
308 typedef enum bfin_cpu_type
342 bfin_cpu_t bfin_cpu_type = BFIN_CPU_UNKNOWN;
343 /* -msi-revision support. There are three special values:
344 -1 -msi-revision=none.
345 0xffff -msi-revision=any. */
346 int bfin_si_revision;
348 unsigned int bfin_anomaly_checks = 0;
355 unsigned int anomaly_checks;
358 struct bfin_cpu bfin_cpus[] =
360 {"bf512", BFIN_CPU_BF512, 0x0001, AC_05000074},
361 {"bf512", BFIN_CPU_BF512, 0x0000, AC_05000074},
363 {"bf514", BFIN_CPU_BF514, 0x0001, AC_05000074},
364 {"bf514", BFIN_CPU_BF514, 0x0000, AC_05000074},
366 {"bf516", BFIN_CPU_BF516, 0x0001, AC_05000074},
367 {"bf516", BFIN_CPU_BF516, 0x0000, AC_05000074},
369 {"bf518", BFIN_CPU_BF518, 0x0001, AC_05000074},
370 {"bf518", BFIN_CPU_BF518, 0x0000, AC_05000074},
372 {"bf522", BFIN_CPU_BF522, 0x0002, AC_05000074},
373 {"bf522", BFIN_CPU_BF522, 0x0001, AC_05000074},
374 {"bf522", BFIN_CPU_BF522, 0x0000, AC_05000074},
376 {"bf523", BFIN_CPU_BF523, 0x0002, AC_05000074},
377 {"bf523", BFIN_CPU_BF523, 0x0001, AC_05000074},
378 {"bf523", BFIN_CPU_BF523, 0x0000, AC_05000074},
380 {"bf524", BFIN_CPU_BF524, 0x0002, AC_05000074},
381 {"bf524", BFIN_CPU_BF524, 0x0001, AC_05000074},
382 {"bf524", BFIN_CPU_BF524, 0x0000, AC_05000074},
384 {"bf525", BFIN_CPU_BF525, 0x0002, AC_05000074},
385 {"bf525", BFIN_CPU_BF525, 0x0001, AC_05000074},
386 {"bf525", BFIN_CPU_BF525, 0x0000, AC_05000074},
388 {"bf526", BFIN_CPU_BF526, 0x0002, AC_05000074},
389 {"bf526", BFIN_CPU_BF526, 0x0001, AC_05000074},
390 {"bf526", BFIN_CPU_BF526, 0x0000, AC_05000074},
392 {"bf527", BFIN_CPU_BF527, 0x0002, AC_05000074},
393 {"bf527", BFIN_CPU_BF527, 0x0001, AC_05000074},
394 {"bf527", BFIN_CPU_BF527, 0x0000, AC_05000074},
396 {"bf531", BFIN_CPU_BF531, 0x0006, AC_05000074},
397 {"bf531", BFIN_CPU_BF531, 0x0005, AC_05000074},
398 {"bf531", BFIN_CPU_BF531, 0x0004, AC_05000074},
399 {"bf531", BFIN_CPU_BF531, 0x0003, AC_05000074},
401 {"bf532", BFIN_CPU_BF532, 0x0006, AC_05000074},
402 {"bf532", BFIN_CPU_BF532, 0x0005, AC_05000074},
403 {"bf532", BFIN_CPU_BF532, 0x0004, AC_05000074},
404 {"bf532", BFIN_CPU_BF532, 0x0003, AC_05000074},
406 {"bf533", BFIN_CPU_BF533, 0x0006, AC_05000074},
407 {"bf533", BFIN_CPU_BF533, 0x0005, AC_05000074},
408 {"bf533", BFIN_CPU_BF533, 0x0004, AC_05000074},
409 {"bf533", BFIN_CPU_BF533, 0x0003, AC_05000074},
411 {"bf534", BFIN_CPU_BF534, 0x0003, AC_05000074},
412 {"bf534", BFIN_CPU_BF534, 0x0002, AC_05000074},
413 {"bf534", BFIN_CPU_BF534, 0x0001, AC_05000074},
415 {"bf536", BFIN_CPU_BF536, 0x0003, AC_05000074},
416 {"bf536", BFIN_CPU_BF536, 0x0002, AC_05000074},
417 {"bf536", BFIN_CPU_BF536, 0x0001, AC_05000074},
419 {"bf537", BFIN_CPU_BF537, 0x0003, AC_05000074},
420 {"bf537", BFIN_CPU_BF537, 0x0002, AC_05000074},
421 {"bf537", BFIN_CPU_BF537, 0x0001, AC_05000074},
423 {"bf538", BFIN_CPU_BF538, 0x0005, AC_05000074},
424 {"bf538", BFIN_CPU_BF538, 0x0004, AC_05000074},
425 {"bf538", BFIN_CPU_BF538, 0x0003, AC_05000074},
426 {"bf538", BFIN_CPU_BF538, 0x0002, AC_05000074},
428 {"bf539", BFIN_CPU_BF539, 0x0005, AC_05000074},
429 {"bf539", BFIN_CPU_BF539, 0x0004, AC_05000074},
430 {"bf539", BFIN_CPU_BF539, 0x0003, AC_05000074},
431 {"bf539", BFIN_CPU_BF539, 0x0002, AC_05000074},
433 {"bf542m", BFIN_CPU_BF542M, 0x0003, AC_05000074},
435 {"bf542", BFIN_CPU_BF542, 0x0002, AC_05000074},
436 {"bf542", BFIN_CPU_BF542, 0x0001, AC_05000074},
437 {"bf542", BFIN_CPU_BF542, 0x0000, AC_05000074},
439 {"bf544m", BFIN_CPU_BF544M, 0x0003, AC_05000074},
441 {"bf544", BFIN_CPU_BF544, 0x0002, AC_05000074},
442 {"bf544", BFIN_CPU_BF544, 0x0001, AC_05000074},
443 {"bf544", BFIN_CPU_BF544, 0x0000, AC_05000074},
445 {"bf547m", BFIN_CPU_BF547M, 0x0003, AC_05000074},
447 {"bf547", BFIN_CPU_BF547, 0x0002, AC_05000074},
448 {"bf547", BFIN_CPU_BF547, 0x0001, AC_05000074},
449 {"bf547", BFIN_CPU_BF547, 0x0000, AC_05000074},
451 {"bf548m", BFIN_CPU_BF548M, 0x0003, AC_05000074},
453 {"bf548", BFIN_CPU_BF548, 0x0002, AC_05000074},
454 {"bf548", BFIN_CPU_BF548, 0x0001, AC_05000074},
455 {"bf548", BFIN_CPU_BF548, 0x0000, AC_05000074},
457 {"bf549m", BFIN_CPU_BF549M, 0x0003, AC_05000074},
459 {"bf549", BFIN_CPU_BF549, 0x0002, AC_05000074},
460 {"bf549", BFIN_CPU_BF549, 0x0001, AC_05000074},
461 {"bf549", BFIN_CPU_BF549, 0x0000, AC_05000074},
463 {"bf561", BFIN_CPU_BF561, 0x0005, AC_05000074},
464 {"bf561", BFIN_CPU_BF561, 0x0003, AC_05000074},
465 {"bf561", BFIN_CPU_BF561, 0x0002, AC_05000074},
470 /* Define bfin-specific command-line options (there are none). */
471 const char *md_shortopts = "";
473 #define OPTION_FDPIC (OPTION_MD_BASE)
474 #define OPTION_NOPIC (OPTION_MD_BASE + 1)
475 #define OPTION_MCPU (OPTION_MD_BASE + 2)
477 struct option md_longopts[] =
479 { "mcpu", required_argument, NULL, OPTION_MCPU },
480 { "mfdpic", no_argument, NULL, OPTION_FDPIC },
481 { "mnopic", no_argument, NULL, OPTION_NOPIC },
482 { "mno-fdpic", no_argument, NULL, OPTION_NOPIC },
483 { NULL, no_argument, NULL, 0 },
486 size_t md_longopts_size = sizeof (md_longopts);
490 md_parse_option (int c ATTRIBUTE_UNUSED, char *arg ATTRIBUTE_UNUSED)
503 while ((p = bfin_cpus[i].name) != NULL)
505 if (strncmp (arg, p, strlen (p)) == 0)
512 error ("-mcpu=%s is not valid", arg);
516 bfin_cpu_type = bfin_cpus[i].type;
518 q = arg + strlen (p);
522 bfin_si_revision = bfin_cpus[i].si_revision;
523 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
525 else if (strcmp (q, "-none") == 0)
526 bfin_si_revision = -1;
527 else if (strcmp (q, "-any") == 0)
529 bfin_si_revision = 0xffff;
530 while (bfin_cpus[i].type == bfin_cpu_type)
532 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
538 unsigned int si_major, si_minor;
541 rev_len = strlen (q);
543 if (sscanf (q, "-%u.%u%n", &si_major, &si_minor, &n) != 2
545 || si_major > 0xff || si_minor > 0xff)
547 invalid_silicon_revision:
548 error ("-mcpu=%s has invalid silicon revision", arg);
552 bfin_si_revision = (si_major << 8) | si_minor;
554 while (bfin_cpus[i].type == bfin_cpu_type
555 && bfin_cpus[i].si_revision != bfin_si_revision)
558 if (bfin_cpus[i].type != bfin_cpu_type)
559 goto invalid_silicon_revision;
561 bfin_anomaly_checks |= bfin_cpus[i].anomaly_checks;
568 bfin_flags |= EF_BFIN_FDPIC;
569 bfin_pic_flag = "-mfdpic";
573 bfin_flags &= ~(EF_BFIN_FDPIC);
582 md_show_usage (FILE * stream ATTRIBUTE_UNUSED)
584 fprintf (stream, _(" BFIN specific command line options:\n"));
587 /* Perform machine-specific initializations. */
591 /* Set the ELF flags if desired. */
593 bfd_set_private_flags (stdoutput, bfin_flags);
595 /* Set the default machine type. */
596 if (!bfd_set_arch_mach (stdoutput, bfd_arch_bfin, 0))
597 as_warn (_("Could not set architecture and machine."));
599 /* Ensure that lines can begin with '(', for multiple
600 register stack pops. */
601 lex_type ['('] = LEX_BEGIN_NAME;
604 record_alignment (text_section, 2);
605 record_alignment (data_section, 2);
606 record_alignment (bss_section, 2);
610 obstack_init (&mempool);
613 extern int debug_codeselection;
614 debug_codeselection = 1;
620 /* Perform the main parsing, and assembly of the input here. Also,
621 call the required routines for alignment and fixups here.
622 This is called for every line that contains real assembly code. */
625 md_assemble (char *line)
628 extern char *current_inputline;
630 struct bfin_insn *tmp_insn;
632 static size_t buffer_len = 0;
636 if (len + 2 > buffer_len)
639 free (current_inputline);
640 buffer_len = len + 40;
641 current_inputline = xmalloc (buffer_len);
643 memcpy (current_inputline, line, len);
644 current_inputline[len] = ';';
645 current_inputline[len + 1] = '\0';
647 state = parse (current_inputline);
648 if (state == NO_INSN_GENERATED)
651 for (insn_size = 0, tmp_insn = insn; tmp_insn; tmp_insn = tmp_insn->next)
652 if (!tmp_insn->reloc || !tmp_insn->exp->symbol)
656 toP = frag_more (insn_size);
658 last_insn_size = insn_size;
665 if (insn->reloc && insn->exp->symbol)
667 char *prev_toP = toP - 2;
670 case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
671 case BFD_RELOC_24_PCREL:
672 case BFD_RELOC_BFIN_16_LOW:
673 case BFD_RELOC_BFIN_16_HIGH:
680 /* Following if condition checks for the arithmetic relocations.
681 If the case then it doesn't required to generate the code.
682 It has been assumed that, their ID will be contiguous. */
683 if ((BFD_ARELOC_BFIN_PUSH <= insn->reloc
684 && BFD_ARELOC_BFIN_COMP >= insn->reloc)
685 || insn->reloc == BFD_RELOC_BFIN_16_IMM)
689 if (insn->reloc == BFD_ARELOC_BFIN_CONST
690 || insn->reloc == BFD_ARELOC_BFIN_PUSH)
694 (prev_toP - frag_now->fr_literal),
695 size, insn->exp->symbol, insn->exp->value,
696 insn->pcrel, insn->reloc);
700 md_number_to_chars (toP, insn->value, 2);
706 printf (" %02x%02x", ((unsigned char *) &insn->value)[0],
707 ((unsigned char *) &insn->value)[1]);
713 dwarf2_emit_insn (insn_size);
717 /* Parse one line of instructions, and generate opcode for it.
718 To parse the line, YACC and LEX are used, because the instruction set
719 syntax doesn't confirm to the AT&T assembly syntax.
720 To call a YACC & LEX generated parser, we must provide the input via
721 a FILE stream, otherwise stdin is used by default. Below the input
722 to the function will be put into a temporary file, then the generated
723 parser uses the temporary file for parsing. */
729 YY_BUFFER_STATE buffstate;
731 buffstate = yy_scan_string (line);
733 /* our lex requires setting the start state to keyword
734 every line as the first word may be a keyword.
735 Fixes a bug where we could not have keywords as labels. */
738 /* Call yyparse here. */
740 if (state == SEMANTIC_ERROR)
742 as_bad (_("Parse failed."));
746 yy_delete_buffer (buffstate);
750 /* We need to handle various expressions properly.
751 Such as, [SP--] = 34, concerned by md_assemble(). */
754 md_operand (expressionS * expressionP)
756 if (*input_line_pointer == '[')
758 as_tsktsk ("We found a '['!");
759 input_line_pointer++;
760 expression (expressionP);
764 /* Handle undefined symbols. */
766 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
768 return (symbolS *) 0;
772 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
773 segT segment ATTRIBUTE_UNUSED)
778 /* Convert from target byte order to host byte order. */
781 md_chars_to_number (char *val, int n)
785 for (retval = 0; n--;)
794 md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED)
796 char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
798 long value = *valueP;
801 switch (fixP->fx_r_type)
803 case BFD_RELOC_BFIN_GOT:
804 case BFD_RELOC_BFIN_GOT17M4:
805 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
806 fixP->fx_no_overflow = 1;
807 newval = md_chars_to_number (where, 2);
808 newval |= 0x0 & 0x7f;
809 md_number_to_chars (where, newval, 2);
812 case BFD_RELOC_BFIN_10_PCREL:
815 if (value < -1024 || value > 1022)
816 as_bad_where (fixP->fx_file, fixP->fx_line,
817 _("pcrel too far BFD_RELOC_BFIN_10"));
819 /* 11 bit offset even numbered, so we remove right bit. */
821 newval = md_chars_to_number (where, 2);
822 newval |= value & 0x03ff;
823 md_number_to_chars (where, newval, 2);
826 case BFD_RELOC_BFIN_12_PCREL_JUMP:
827 case BFD_RELOC_BFIN_12_PCREL_JUMP_S:
828 case BFD_RELOC_12_PCREL:
832 if (value < -4096 || value > 4094)
833 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_12"));
834 /* 13 bit offset even numbered, so we remove right bit. */
836 newval = md_chars_to_number (where, 2);
837 newval |= value & 0xfff;
838 md_number_to_chars (where, newval, 2);
841 case BFD_RELOC_BFIN_16_LOW:
842 case BFD_RELOC_BFIN_16_HIGH:
843 fixP->fx_done = FALSE;
846 case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
847 case BFD_RELOC_BFIN_24_PCREL_CALL_X:
848 case BFD_RELOC_24_PCREL:
852 if (value < -16777216 || value > 16777214)
853 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_24"));
855 /* 25 bit offset even numbered, so we remove right bit. */
859 md_number_to_chars (where - 2, value >> 16, 1);
860 md_number_to_chars (where, value, 1);
861 md_number_to_chars (where + 1, value >> 8, 1);
864 case BFD_RELOC_BFIN_5_PCREL: /* LSETUP (a, b) : "a" */
867 if (value < 4 || value > 30)
868 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_5"));
870 newval = md_chars_to_number (where, 1);
871 newval = (newval & 0xf0) | (value & 0xf);
872 md_number_to_chars (where, newval, 1);
875 case BFD_RELOC_BFIN_11_PCREL: /* LSETUP (a, b) : "b" */
879 if (value < 4 || value > 2046)
880 as_bad_where (fixP->fx_file, fixP->fx_line, _("pcrel too far BFD_RELOC_BFIN_11_PCREL"));
881 /* 11 bit unsigned even, so we remove right bit. */
883 newval = md_chars_to_number (where, 2);
884 newval |= value & 0x03ff;
885 md_number_to_chars (where, newval, 2);
889 if (value < -0x80 || value >= 0x7f)
890 as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_8"));
891 md_number_to_chars (where, value, 1);
894 case BFD_RELOC_BFIN_16_IMM:
896 if (value < -0x8000 || value >= 0x7fff)
897 as_bad_where (fixP->fx_file, fixP->fx_line, _("rel too far BFD_RELOC_16"));
898 md_number_to_chars (where, value, 2);
902 md_number_to_chars (where, value, 4);
905 case BFD_RELOC_BFIN_PLTPC:
906 md_number_to_chars (where, value, 2);
909 case BFD_RELOC_BFIN_FUNCDESC:
910 case BFD_RELOC_VTABLE_INHERIT:
911 case BFD_RELOC_VTABLE_ENTRY:
912 fixP->fx_done = FALSE;
916 if ((BFD_ARELOC_BFIN_PUSH > fixP->fx_r_type) || (BFD_ARELOC_BFIN_COMP < fixP->fx_r_type))
918 fprintf (stderr, "Relocation %d not handled in gas." " Contact support.\n", fixP->fx_r_type);
924 fixP->fx_done = TRUE;
928 /* Round up a section size to the appropriate boundary. */
930 md_section_align (segment, size)
934 int boundary = bfd_get_section_alignment (stdoutput, segment);
935 return ((size + (1 << boundary) - 1) & (-1 << boundary));
940 md_atof (int type, char * litP, int * sizeP)
942 return ieee_md_atof (type, litP, sizeP, FALSE);
946 /* If while processing a fixup, a reloc really needs to be created
947 then it is done here. */
950 tc_gen_reloc (seg, fixp)
951 asection *seg ATTRIBUTE_UNUSED;
956 reloc = (arelent *) xmalloc (sizeof (arelent));
957 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
958 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
959 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
961 reloc->addend = fixp->fx_offset;
962 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
964 if (reloc->howto == (reloc_howto_type *) NULL)
966 as_bad_where (fixp->fx_file, fixp->fx_line,
967 /* xgettext:c-format. */
968 _("reloc %d not supported by object file format"),
969 (int) fixp->fx_r_type);
979 /* The location from which a PC relative jump should be calculated,
980 given a PC relative reloc. */
983 md_pcrel_from_section (fixP, sec)
987 if (fixP->fx_addsy != (symbolS *) NULL
988 && (!S_IS_DEFINED (fixP->fx_addsy)
989 || S_GET_SEGMENT (fixP->fx_addsy) != sec))
991 /* The symbol is undefined (or is defined but not in this section).
992 Let the linker figure it out. */
995 return fixP->fx_frag->fr_address + fixP->fx_where;
998 /* Return true if the fix can be handled by GAS, false if it must
999 be passed through to the linker. */
1002 bfin_fix_adjustable (fixS *fixP)
1004 switch (fixP->fx_r_type)
1006 /* Adjust_reloc_syms doesn't know about the GOT. */
1007 case BFD_RELOC_BFIN_GOT:
1008 case BFD_RELOC_BFIN_PLTPC:
1009 /* We need the symbol name for the VTABLE entries. */
1010 case BFD_RELOC_VTABLE_INHERIT:
1011 case BFD_RELOC_VTABLE_ENTRY:
1020 /* Handle the LOOP_BEGIN and LOOP_END statements.
1021 Parse the Loop_Begin/Loop_End and create a label. */
1023 bfin_start_line_hook ()
1025 bfd_boolean maybe_begin = FALSE;
1026 bfd_boolean maybe_end = FALSE;
1028 char *c1, *label_name;
1029 symbolS *line_label;
1030 char *c = input_line_pointer;
1033 while (ISSPACE (*c))
1040 /* Look for Loop_Begin or Loop_End statements. */
1042 if (*c != 'L' && *c != 'l')
1046 if (*c != 'O' && *c != 'o')
1050 if (*c != 'O' && *c != 'o')
1054 if (*c != 'P' && *c != 'p')
1062 if (*c == 'E' || *c == 'e')
1064 else if (*c == 'B' || *c == 'b')
1072 if (*c != 'N' && *c != 'n')
1076 if (*c != 'D' && *c != 'd')
1083 if (*c != 'E' && *c != 'e')
1087 if (*c != 'G' && *c != 'g')
1091 if (*c != 'I' && *c != 'i')
1095 if (*c != 'N' && *c != 'n')
1100 while (ISSPACE (*c)) c++;
1102 while (ISALPHA (*c) || ISDIGIT (*c) || *c == '_') c++;
1104 if (input_line_pointer[-1] == '\n')
1105 bump_line_counters ();
1108 bump_line_counters ();
1110 input_line_pointer = c;
1113 label_name = (char *) xmalloc ((c - c1) + strlen ("__END") + 5);
1115 strcat (label_name, "L$L$");
1116 strncat (label_name, c1, c-c1);
1117 strcat (label_name, "__END");
1119 else /* maybe_begin. */
1121 label_name = (char *) xmalloc ((c - c1) + strlen ("__BEGIN") + 5);
1123 strcat (label_name, "L$L$");
1124 strncat (label_name, c1, c-c1);
1125 strcat (label_name, "__BEGIN");
1128 line_label = colon (label_name);
1130 /* Loop_End follows the last instruction in the loop.
1131 Adjust label address. */
1133 ((struct local_symbol *) line_label)->lsy_value -= last_insn_size;
1136 /* Special extra functions that help bfin-parse.y perform its job. */
1138 struct obstack mempool;
1141 conscode (INSTR_T head, INSTR_T tail)
1150 conctcode (INSTR_T head, INSTR_T tail)
1152 INSTR_T temp = (head);
1163 note_reloc (INSTR_T code, Expr_Node * symbol, int reloc, int pcrel)
1165 /* Assert that the symbol is not an operator. */
1166 gas_assert (symbol->type == Expr_Node_Reloc);
1168 return note_reloc1 (code, symbol->value.s_value, reloc, pcrel);
1173 note_reloc1 (INSTR_T code, const char *symbol, int reloc, int pcrel)
1175 code->reloc = reloc;
1176 code->exp = mkexpr (0, symbol_find_or_make (symbol));
1177 code->pcrel = pcrel;
1182 note_reloc2 (INSTR_T code, const char *symbol, int reloc, int value, int pcrel)
1184 code->reloc = reloc;
1185 code->exp = mkexpr (value, symbol_find_or_make (symbol));
1186 code->pcrel = pcrel;
1191 gencode (unsigned long x)
1193 INSTR_T cell = obstack_alloc (&mempool, sizeof (struct bfin_insn));
1194 memset (cell, 0, sizeof (struct bfin_insn));
1206 return obstack_alloc (&mempool, n);
1210 Expr_Node_Create (Expr_Node_Type type,
1211 Expr_Node_Value value,
1212 Expr_Node *Left_Child,
1213 Expr_Node *Right_Child)
1217 Expr_Node *node = (Expr_Node *) allocate (sizeof (Expr_Node));
1219 node->value = value;
1220 node->Left_Child = Left_Child;
1221 node->Right_Child = Right_Child;
1225 static const char *con = ".__constant";
1226 static const char *op = ".__operator";
1227 static INSTR_T Expr_Node_Gen_Reloc_R (Expr_Node * head);
1228 INSTR_T Expr_Node_Gen_Reloc (Expr_Node *head, int parent_reloc);
1231 Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
1233 /* Top level reloction expression generator VDSP style.
1234 If the relocation is just by itself, generate one item
1235 else generate this convoluted expression. */
1237 INSTR_T note = NULL_CODE;
1238 INSTR_T note1 = NULL_CODE;
1239 int pcrel = 1; /* Is the parent reloc pcrelative?
1240 This calculation here and HOWTO should match. */
1244 /* If it's 32 bit quantity then 16bit code needs to be added. */
1247 if (head->type == Expr_Node_Constant)
1249 /* If note1 is not null code, we have to generate a right
1250 aligned value for the constant. Otherwise the reloc is
1251 a part of the basic command and the yacc file
1253 value = head->value.i_value;
1255 switch (parent_reloc)
1257 /* Some relocations will need to allocate extra words. */
1258 case BFD_RELOC_BFIN_16_IMM:
1259 case BFD_RELOC_BFIN_16_LOW:
1260 case BFD_RELOC_BFIN_16_HIGH:
1261 note1 = conscode (gencode (value), NULL_CODE);
1264 case BFD_RELOC_BFIN_PLTPC:
1265 note1 = conscode (gencode (value), NULL_CODE);
1269 case BFD_RELOC_BFIN_GOT:
1270 case BFD_RELOC_BFIN_GOT17M4:
1271 case BFD_RELOC_BFIN_FUNCDESC_GOT17M4:
1272 note1 = conscode (gencode (value), NULL_CODE);
1275 case BFD_RELOC_24_PCREL:
1276 case BFD_RELOC_BFIN_24_PCREL_JUMP_L:
1277 case BFD_RELOC_BFIN_24_PCREL_CALL_X:
1278 /* These offsets are even numbered pcrel. */
1279 note1 = conscode (gencode (value >> 1), NULL_CODE);
1285 if (head->type == Expr_Node_Constant)
1287 else if (head->type == Expr_Node_Reloc)
1289 note = note_reloc1 (gencode (0), head->value.s_value, parent_reloc, pcrel);
1290 if (note1 != NULL_CODE)
1291 note = conscode (note1, note);
1293 else if (head->type == Expr_Node_Binop
1294 && (head->value.op_value == Expr_Op_Type_Add
1295 || head->value.op_value == Expr_Op_Type_Sub)
1296 && head->Left_Child->type == Expr_Node_Reloc
1297 && head->Right_Child->type == Expr_Node_Constant)
1299 int val = head->Right_Child->value.i_value;
1300 if (head->value.op_value == Expr_Op_Type_Sub)
1302 note = conscode (note_reloc2 (gencode (0), head->Left_Child->value.s_value,
1303 parent_reloc, val, 0),
1305 if (note1 != NULL_CODE)
1306 note = conscode (note1, note);
1310 /* Call the recursive function. */
1311 note = note_reloc1 (gencode (0), op, parent_reloc, pcrel);
1312 if (note1 != NULL_CODE)
1313 note = conscode (note1, note);
1314 note = conctcode (Expr_Node_Gen_Reloc_R (head), note);
1320 Expr_Node_Gen_Reloc_R (Expr_Node * head)
1328 case Expr_Node_Constant:
1329 note = conscode (note_reloc2 (gencode (0), con, BFD_ARELOC_BFIN_CONST, head->value.i_value, 0), NULL_CODE);
1331 case Expr_Node_Reloc:
1332 note = conscode (note_reloc (gencode (0), head, BFD_ARELOC_BFIN_PUSH, 0), NULL_CODE);
1334 case Expr_Node_Binop:
1335 note1 = conctcode (Expr_Node_Gen_Reloc_R (head->Left_Child), Expr_Node_Gen_Reloc_R (head->Right_Child));
1336 switch (head->value.op_value)
1338 case Expr_Op_Type_Add:
1339 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_ADD, 0), NULL_CODE));
1341 case Expr_Op_Type_Sub:
1342 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_SUB, 0), NULL_CODE));
1344 case Expr_Op_Type_Mult:
1345 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MULT, 0), NULL_CODE));
1347 case Expr_Op_Type_Div:
1348 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_DIV, 0), NULL_CODE));
1350 case Expr_Op_Type_Mod:
1351 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_MOD, 0), NULL_CODE));
1353 case Expr_Op_Type_Lshift:
1354 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LSHIFT, 0), NULL_CODE));
1356 case Expr_Op_Type_Rshift:
1357 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_RSHIFT, 0), NULL_CODE));
1359 case Expr_Op_Type_BAND:
1360 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_AND, 0), NULL_CODE));
1362 case Expr_Op_Type_BOR:
1363 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_OR, 0), NULL_CODE));
1365 case Expr_Op_Type_BXOR:
1366 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_XOR, 0), NULL_CODE));
1368 case Expr_Op_Type_LAND:
1369 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LAND, 0), NULL_CODE));
1371 case Expr_Op_Type_LOR:
1372 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_LOR, 0), NULL_CODE));
1375 fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1380 case Expr_Node_Unop:
1381 note1 = conscode (Expr_Node_Gen_Reloc_R (head->Left_Child), NULL_CODE);
1382 switch (head->value.op_value)
1384 case Expr_Op_Type_NEG:
1385 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_NEG, 0), NULL_CODE));
1387 case Expr_Op_Type_COMP:
1388 note = conctcode (note1, conscode (note_reloc1 (gencode (0), op, BFD_ARELOC_BFIN_COMP, 0), NULL_CODE));
1391 fprintf (stderr, "%s:%d:Unknown operator found for arithmetic" " relocation", __FILE__, __LINE__);
1395 fprintf (stderr, "%s:%d:Unknown node expression found during " "arithmetic relocation generation", __FILE__, __LINE__);
1400 /* Blackfin opcode generation. */
1402 /* These functions are called by the generated parser
1403 (from bfin-parse.y), the register type classification
1404 happens in bfin-lex.l. */
1406 #include "bfin-aux.h"
1407 #include "opcode/bfin.h"
1409 #define INIT(t) t c_code = init_##t
1410 #define ASSIGN(x) c_code.opcode |= ((x & c_code.mask_##x)<<c_code.bits_##x)
1411 #define ASSIGN_R(x) c_code.opcode |= (((x ? (x->regno & CODE_MASK) : 0) & c_code.mask_##x)<<c_code.bits_##x)
1413 #define HI(x) ((x >> 16) & 0xffff)
1414 #define LO(x) ((x ) & 0xffff)
1416 #define GROUP(x) ((x->regno & CLASS_MASK) >> 4)
1418 #define GEN_OPCODE32() \
1419 conscode (gencode (HI (c_code.opcode)), \
1420 conscode (gencode (LO (c_code.opcode)), NULL_CODE))
1422 #define GEN_OPCODE16() \
1423 conscode (gencode (c_code.opcode), NULL_CODE)
1426 /* 32 BIT INSTRUCTIONS. */
1429 /* DSP32 instruction generation. */
1432 bfin_gen_dsp32mac (int op1, int MM, int mmod, int w1, int P,
1433 int h01, int h11, int h00, int h10, int op0,
1434 REG_T dst, REG_T src0, REG_T src1, int w0)
1450 /* If we have full reg assignments, mask out LSB to encode
1451 single or simultaneous even/odd register moves. */
1461 return GEN_OPCODE32 ();
1465 bfin_gen_dsp32mult (int op1, int MM, int mmod, int w1, int P,
1466 int h01, int h11, int h00, int h10, int op0,
1467 REG_T dst, REG_T src0, REG_T src1, int w0)
1492 return GEN_OPCODE32 ();
1496 bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x,
1497 REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
1511 return GEN_OPCODE32 ();
1515 bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0,
1516 REG_T src1, int sop, int HLs)
1528 return GEN_OPCODE32 ();
1532 bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag,
1533 REG_T src1, int sop, int HLs)
1535 INIT (DSP32ShiftImm);
1545 return GEN_OPCODE32 ();
1551 bfin_gen_loopsetup (Expr_Node * psoffset, REG_T c, int rop,
1552 Expr_Node * peoffset, REG_T reg)
1554 int soffset, eoffset;
1557 soffset = (EXPR_VALUE (psoffset) >> 1);
1559 eoffset = (EXPR_VALUE (peoffset) >> 1);
1566 conscode (gencode (HI (c_code.opcode)),
1567 conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL),
1568 conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL))));
1575 bfin_gen_calla (Expr_Node * addr, int S)
1583 case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
1584 case 1 : reloc = BFD_RELOC_24_PCREL; break;
1585 case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
1591 val = EXPR_VALUE (addr) >> 1;
1592 high_val = val >> 16;
1594 return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
1595 Expr_Node_Gen_Reloc (addr, reloc));
1599 bfin_gen_linkage (int R, int framesize)
1606 return GEN_OPCODE32 ();
1610 /* Load and Store. */
1613 bfin_gen_ldimmhalf (REG_T reg, int H, int S, int Z, Expr_Node * phword, int reloc)
1616 unsigned val = EXPR_VALUE (phword);
1624 grp = (GROUP (reg));
1628 return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
1630 else if (reloc == 1)
1632 return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
1639 return GEN_OPCODE32 ();
1643 bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int W, int sz, int Z, Expr_Node * poffset)
1647 if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1649 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1660 if (poffset->type != Expr_Node_Constant)
1662 /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
1663 /* distinguish between R0 = [P5 + symbol@GOT] and
1664 P5 = [P5 + _current_shared_library_p5_offset_]
1666 if (poffset->type == Expr_Node_Reloc
1667 && !strcmp (poffset->value.s_value,
1668 "_current_shared_library_p5_offset_"))
1670 return conscode (gencode (HI (c_code.opcode)),
1671 Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16));
1673 else if (poffset->type != Expr_Node_GOT_Reloc)
1676 return conscode (gencode (HI (c_code.opcode)),
1677 Expr_Node_Gen_Reloc(poffset->Left_Child,
1678 poffset->value.i_value));
1684 { /* load/store access size */
1685 case 0: /* 32 bit */
1686 value = EXPR_VALUE (poffset) >> 2;
1688 case 1: /* 16 bit */
1689 value = EXPR_VALUE (poffset) >> 1;
1692 value = EXPR_VALUE (poffset);
1698 offset = (value & 0xffff);
1700 return GEN_OPCODE32 ();
1706 bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int Z, int W)
1710 if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
1712 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1723 return GEN_OPCODE16 ();
1727 bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node * poffset, int W, int op)
1734 if (!IS_PREG (*ptr))
1736 fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
1744 value = EXPR_VALUE (poffset) >> 1;
1748 value = EXPR_VALUE (poffset) >> 2;
1760 return GEN_OPCODE16 ();
1764 bfin_gen_ldstiifp (REG_T sreg, Expr_Node * poffset, int W)
1766 /* Set bit 4 if it's a Preg. */
1767 int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0);
1768 int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1;
1774 return GEN_OPCODE16 ();
1778 bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int W, REG_T idx)
1788 return GEN_OPCODE16 ();
1792 bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int W, int m)
1802 return GEN_OPCODE16 ();
1806 bfin_gen_logi2op (int opc, int src, int dst)
1814 return GEN_OPCODE16 ();
1818 bfin_gen_brcc (int T, int B, Expr_Node * poffset)
1825 offset = ((EXPR_VALUE (poffset) >> 1));
1827 return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL));
1831 bfin_gen_ujump (Expr_Node * poffset)
1836 offset = ((EXPR_VALUE (poffset) >> 1));
1839 return conscode (gencode (c_code.opcode),
1840 Expr_Node_Gen_Reloc (
1841 poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S));
1845 bfin_gen_alu2op (REG_T dst, REG_T src, int opc)
1853 return GEN_OPCODE16 ();
1857 bfin_gen_compi2opd (REG_T dst, int src, int op)
1865 return GEN_OPCODE16 ();
1869 bfin_gen_compi2opp (REG_T dst, int src, int op)
1877 return GEN_OPCODE16 ();
1881 bfin_gen_dagmodik (REG_T i, int op)
1888 return GEN_OPCODE16 ();
1892 bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
1901 return GEN_OPCODE16 ();
1905 bfin_gen_ptr2op (REG_T dst, REG_T src, int opc)
1913 return GEN_OPCODE16 ();
1917 bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
1926 return GEN_OPCODE16 ();
1930 bfin_gen_ccflag (REG_T x, int y, int opc, int I, int G)
1940 return GEN_OPCODE16 ();
1944 bfin_gen_ccmv (REG_T src, REG_T dst, int T)
1957 return GEN_OPCODE16 ();
1961 bfin_gen_cc2stat (int cbit, int op, int D)
1969 return GEN_OPCODE16 ();
1973 bfin_gen_regmv (REG_T src, REG_T dst)
1986 return GEN_OPCODE16 ();
1990 bfin_gen_cc2dreg (int op, REG_T reg)
1997 return GEN_OPCODE16 ();
2001 bfin_gen_progctrl (int prgfunc, int poprnd)
2008 return GEN_OPCODE16 ();
2012 bfin_gen_cactrl (REG_T reg, int a, int op)
2020 return GEN_OPCODE16 ();
2024 bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int W)
2026 INIT (PushPopMultiple);
2034 return GEN_OPCODE16 ();
2038 bfin_gen_pushpopreg (REG_T reg, int W)
2044 grp = (GROUP (reg));
2048 return GEN_OPCODE16 ();
2051 /* Pseudo Debugging Support. */
2054 bfin_gen_pseudodbg (int fn, int reg, int grp)
2062 return GEN_OPCODE16 ();
2066 bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
2068 INIT (PseudoDbg_Assert);
2074 return GEN_OPCODE32 ();
2077 /* Multiple instruction generation. */
2080 bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
2084 /* If it's a 0, convert into MNOP. */
2088 SET_MULTI_INSTRUCTION_BIT (dsp32);
2092 dsp32 = gencode (0xc803);
2093 walk = gencode (0x1800);
2099 dsp16_grp1 = gencode (0x0000);
2104 dsp16_grp2 = gencode (0x0000);
2107 walk->next = dsp16_grp1;
2108 dsp16_grp1->next = dsp16_grp2;
2109 dsp16_grp2->next = NULL_CODE;
2115 bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
2117 const char *loopsym;
2118 char *lbeginsym, *lendsym;
2119 Expr_Node_Value lbeginval, lendval;
2120 Expr_Node *lbegin, *lend;
2122 loopsym = expr->value.s_value;
2123 lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 5);
2124 lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 5);
2129 strcat (lbeginsym, "L$L$");
2130 strcat (lbeginsym, loopsym);
2131 strcat (lbeginsym, "__BEGIN");
2133 strcat (lendsym, "L$L$");
2134 strcat (lendsym, loopsym);
2135 strcat (lendsym, "__END");
2137 lbeginval.s_value = lbeginsym;
2138 lendval.s_value = lendsym;
2140 lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
2141 lend = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
2143 symbol_remove (symbol_find (loopsym), &symbol_rootP, &symbol_lastP);
2145 return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
2149 bfin_eol_in_insn (char *line)
2151 /* Allow a new-line to appear in the middle of a multi-issue instruction. */
2158 /* A semi-colon followed by a newline is always the end of a line. */
2159 if (line[-1] == ';')
2162 if (line[-1] == '|')
2165 /* If the || is on the next line, there might be leading whitespace. */
2167 while (*temp == ' ' || *temp == '\t') temp++;
2176 bfin_start_label (char *s, char *ptr)
2180 if (*s == '(' || *s == '[')
2189 bfin_force_relocation (struct fix *fixp)
2191 if (fixp->fx_r_type ==BFD_RELOC_BFIN_16_LOW
2192 || fixp->fx_r_type == BFD_RELOC_BFIN_16_HIGH)
2195 return generic_force_reloc (fixp);
2198 /* This is a stripped down version of the disassembler. The only thing it
2199 does is return a mask of registers modified by an instruction. Only
2200 instructions that can occur in a parallel-issue bundle are handled, and
2201 only the registers that can cause a conflict are recorded. */
2203 #define DREG_MASK(n) (0x101 << (n))
2204 #define DREGH_MASK(n) (0x100 << (n))
2205 #define DREGL_MASK(n) (0x001 << (n))
2206 #define IREG_MASK(n) (1 << ((n) + 16))
2209 decode_ProgCtrl_0 (int iw0)
2217 decode_LDSTpmod_0 (int iw0)
2220 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2221 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
2222 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2223 int W = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
2224 int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
2225 int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
2226 int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
2227 int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
2229 if (aop == 1 && W == 0 && idx == ptr)
2230 return DREGL_MASK (reg);
2231 else if (aop == 2 && W == 0 && idx == ptr)
2232 return DREGH_MASK (reg);
2233 else if (aop == 1 && W == 1 && idx == ptr)
2235 else if (aop == 2 && W == 1 && idx == ptr)
2237 else if (aop == 0 && W == 0)
2238 return DREG_MASK (reg);
2239 else if (aop == 1 && W == 0)
2240 return DREGL_MASK (reg);
2241 else if (aop == 2 && W == 0)
2242 return DREGH_MASK (reg);
2243 else if (aop == 3 && W == 0)
2244 return DREG_MASK (reg);
2245 else if (aop == 3 && W == 1)
2246 return DREG_MASK (reg);
2247 else if (aop == 0 && W == 1)
2249 else if (aop == 1 && W == 1)
2251 else if (aop == 2 && W == 1)
2260 decode_dagMODim_0 (int iw0)
2263 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2264 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
2265 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2266 int i = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
2267 int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
2269 if (op == 0 || op == 1)
2270 return IREG_MASK (i);
2278 decode_dagMODik_0 (int iw0)
2281 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2282 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
2283 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2284 int i = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
2285 return IREG_MASK (i);
2290 decode_dspLDST_0 (int iw0)
2293 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2294 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
2295 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2296 int i = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
2297 int m = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
2298 int W = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
2299 int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
2300 int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
2302 if (aop == 0 && W == 0 && m == 0)
2303 return DREG_MASK (reg) | IREG_MASK (i);
2304 else if (aop == 0 && W == 0 && m == 1)
2305 return DREGL_MASK (reg) | IREG_MASK (i);
2306 else if (aop == 0 && W == 0 && m == 2)
2307 return DREGH_MASK (reg) | IREG_MASK (i);
2308 else if (aop == 1 && W == 0 && m == 0)
2309 return DREG_MASK (reg) | IREG_MASK (i);
2310 else if (aop == 1 && W == 0 && m == 1)
2311 return DREGL_MASK (reg) | IREG_MASK (i);
2312 else if (aop == 1 && W == 0 && m == 2)
2313 return DREGH_MASK (reg) | IREG_MASK (i);
2314 else if (aop == 2 && W == 0 && m == 0)
2315 return DREG_MASK (reg);
2316 else if (aop == 2 && W == 0 && m == 1)
2317 return DREGL_MASK (reg);
2318 else if (aop == 2 && W == 0 && m == 2)
2319 return DREGH_MASK (reg);
2320 else if (aop == 0 && W == 1 && m == 0)
2321 return IREG_MASK (i);
2322 else if (aop == 0 && W == 1 && m == 1)
2323 return IREG_MASK (i);
2324 else if (aop == 0 && W == 1 && m == 2)
2325 return IREG_MASK (i);
2326 else if (aop == 1 && W == 1 && m == 0)
2327 return IREG_MASK (i);
2328 else if (aop == 1 && W == 1 && m == 1)
2329 return IREG_MASK (i);
2330 else if (aop == 1 && W == 1 && m == 2)
2331 return IREG_MASK (i);
2332 else if (aop == 2 && W == 1 && m == 0)
2334 else if (aop == 2 && W == 1 && m == 1)
2336 else if (aop == 2 && W == 1 && m == 2)
2338 else if (aop == 3 && W == 0)
2339 return DREG_MASK (reg) | IREG_MASK (i);
2340 else if (aop == 3 && W == 1)
2341 return IREG_MASK (i);
2348 decode_LDST_0 (int iw0)
2351 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2352 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
2353 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2354 int Z = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
2355 int W = ((iw0 >> LDST_W_bits) & LDST_W_mask);
2356 int sz = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
2357 int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
2358 int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
2360 if (aop == 0 && sz == 0 && Z == 0 && W == 0)
2361 return DREG_MASK (reg);
2362 else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
2364 else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
2365 return DREG_MASK (reg);
2366 else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
2367 return DREG_MASK (reg);
2368 else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
2369 return DREG_MASK (reg);
2370 else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
2371 return DREG_MASK (reg);
2372 else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
2373 return DREG_MASK (reg);
2374 else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
2376 else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
2377 return DREG_MASK (reg);
2378 else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
2379 return DREG_MASK (reg);
2380 else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
2381 return DREG_MASK (reg);
2382 else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
2383 return DREG_MASK (reg);
2384 else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
2385 return DREG_MASK (reg);
2386 else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
2388 else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
2389 return DREG_MASK (reg);
2390 else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
2391 return DREG_MASK (reg);
2392 else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
2393 return DREG_MASK (reg);
2394 else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
2395 return DREG_MASK (reg);
2396 else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
2398 else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
2400 else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
2402 else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
2404 else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
2406 else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
2408 else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
2410 else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
2412 else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
2414 else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
2416 else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
2418 else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
2425 decode_LDSTiiFP_0 (int iw0)
2428 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2429 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
2430 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2431 int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
2432 int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
2435 return reg < 8 ? DREG_MASK (reg) : 0;
2441 decode_LDSTii_0 (int iw0)
2444 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2445 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
2446 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2447 int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
2448 int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
2449 int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
2451 if (W == 0 && op != 3)
2452 return DREG_MASK (reg);
2453 else if (W == 0 && op == 3)
2455 else if (W == 1 && op == 0)
2457 else if (W == 1 && op == 1)
2459 else if (W == 1 && op == 3)
2466 decode_dsp32mac_0 (int iw0, int iw1)
2470 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2471 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
2472 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2473 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2474 int op1 = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
2475 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2476 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2477 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2478 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2479 int MM = ((iw1 >> DSP32Mac_MM_bits) & DSP32Mac_MM_mask);
2480 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2481 int op0 = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
2483 if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
2489 if ((w1 || w0) && mmod == M_W32)
2492 if (((1 << mmod) & (P ? 0x131b : 0x1b5f)) == 0)
2495 if (w1 == 1 || op1 != 3)
2500 return DREG_MASK (dst + 1);
2502 return DREGH_MASK (dst);
2506 if (w0 == 1 || op0 != 3)
2511 return DREG_MASK (dst);
2513 return DREGL_MASK (dst);
2521 decode_dsp32mult_0 (int iw0, int iw1)
2524 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2525 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
2526 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
2527 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2528 int w1 = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
2529 int P = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
2530 int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
2531 int w0 = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
2532 int dst = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
2535 if (w1 == 0 && w0 == 0)
2538 if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
2544 return DREG_MASK (dst | 1);
2546 return DREGH_MASK (dst);
2552 return DREG_MASK (dst);
2554 return DREGL_MASK (dst);
2561 decode_dsp32alu_0 (int iw0, int iw1)
2564 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2565 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
2566 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
2567 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2568 int s = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
2569 int x = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
2570 int aop = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
2571 int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
2572 int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
2573 int HL = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
2574 int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
2576 if (aop == 0 && aopcde == 9 && s == 0)
2578 else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
2580 else if (aop >= x * 2 && aopcde == 5)
2581 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2582 else if (HL == 0 && aopcde == 2)
2583 return DREGL_MASK (dst0);
2584 else if (HL == 1 && aopcde == 2)
2585 return DREGH_MASK (dst0);
2586 else if (HL == 0 && aopcde == 3)
2587 return DREGL_MASK (dst0);
2588 else if (HL == 1 && aopcde == 3)
2589 return DREGH_MASK (dst0);
2591 else if (aop == 0 && aopcde == 9 && s == 1)
2593 else if (aop == 1 && aopcde == 9 && s == 0)
2595 else if (aop == 2 && aopcde == 9 && s == 1)
2597 else if (aop == 3 && aopcde == 9 && s == 0)
2599 else if (aopcde == 8)
2601 else if (aop == 0 && aopcde == 11)
2602 return DREG_MASK (dst0);
2603 else if (aop == 1 && aopcde == 11)
2604 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2605 else if (aopcde == 11)
2607 else if (aopcde == 22)
2608 return DREG_MASK (dst0);
2610 else if ((aop == 0 || aop == 1) && aopcde == 14)
2612 else if (aop == 3 && HL == 0 && aopcde == 14)
2615 else if (aop == 3 && HL == 0 && aopcde == 15)
2616 return DREG_MASK (dst0);
2618 else if (aop == 1 && aopcde == 16)
2621 else if (aop == 0 && aopcde == 16)
2624 else if (aop == 3 && HL == 0 && aopcde == 16)
2627 else if (aop == 3 && HL == 0 && aopcde == 7)
2628 return DREG_MASK (dst0);
2629 else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 7)
2630 return DREG_MASK (dst0);
2632 else if (aop == 0 && aopcde == 12)
2633 return DREG_MASK (dst0);
2634 else if (aop == 1 && aopcde == 12)
2635 return DREG_MASK (dst0) | DREG_MASK (dst1);
2636 else if (aop == 3 && aopcde == 12)
2637 return HL ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2639 else if (aopcde == 0)
2640 return DREG_MASK (dst0);
2641 else if (aopcde == 1)
2642 return DREG_MASK (dst0) | DREG_MASK (dst1);
2644 else if (aop == 0 && aopcde == 10)
2645 return DREGL_MASK (dst0);
2646 else if (aop == 1 && aopcde == 10)
2647 return DREGL_MASK (dst0);
2649 else if ((aop == 1 || aop == 0) && aopcde == 4)
2650 return DREG_MASK (dst0);
2651 else if (aop == 2 && aopcde == 4)
2652 return DREG_MASK (dst0) | DREG_MASK (dst1);
2654 else if (aop == 0 && aopcde == 17)
2655 return DREG_MASK (dst0) | DREG_MASK (dst1);
2656 else if (aop == 1 && aopcde == 17)
2657 return DREG_MASK (dst0) | DREG_MASK (dst1);
2658 else if (aop == 0 && aopcde == 18)
2660 else if (aop == 3 && aopcde == 18)
2663 else if ((aop == 0 || aop == 1 || aop == 2) && aopcde == 6)
2664 return DREG_MASK (dst0);
2666 else if ((aop == 0 || aop == 1) && aopcde == 20)
2667 return DREG_MASK (dst0);
2669 else if ((aop == 0 || aop == 1) && aopcde == 21)
2670 return DREG_MASK (dst0) | DREG_MASK (dst1);
2672 else if (aop == 0 && aopcde == 23 && HL == 1)
2673 return DREG_MASK (dst0);
2674 else if (aop == 0 && aopcde == 23 && HL == 0)
2675 return DREG_MASK (dst0);
2677 else if (aop == 0 && aopcde == 24)
2678 return DREG_MASK (dst0);
2679 else if (aop == 1 && aopcde == 24)
2680 return DREG_MASK (dst0) | DREG_MASK (dst1);
2681 else if (aopcde == 13)
2682 return DREG_MASK (dst0) | DREG_MASK (dst1);
2690 decode_dsp32shift_0 (int iw0, int iw1)
2693 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2694 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
2695 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
2696 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2697 int HLs = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
2698 int sop = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
2699 int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
2700 int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
2701 int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
2702 int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
2704 if (sop == 0 && sopcde == 0)
2705 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2706 else if (sop == 1 && sopcde == 0)
2707 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2708 else if (sop == 2 && sopcde == 0)
2709 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2710 else if (sop == 0 && sopcde == 3)
2712 else if (sop == 1 && sopcde == 3)
2714 else if (sop == 2 && sopcde == 3)
2716 else if (sop == 3 && sopcde == 3)
2717 return DREG_MASK (dst0);
2718 else if (sop == 0 && sopcde == 1)
2719 return DREG_MASK (dst0);
2720 else if (sop == 1 && sopcde == 1)
2721 return DREG_MASK (dst0);
2722 else if (sop == 2 && sopcde == 1)
2723 return DREG_MASK (dst0);
2724 else if (sopcde == 2)
2725 return DREG_MASK (dst0);
2726 else if (sopcde == 4)
2727 return DREG_MASK (dst0);
2728 else if (sop == 0 && sopcde == 5)
2729 return DREGL_MASK (dst0);
2730 else if (sop == 1 && sopcde == 5)
2731 return DREGL_MASK (dst0);
2732 else if (sop == 2 && sopcde == 5)
2733 return DREGL_MASK (dst0);
2734 else if (sop == 0 && sopcde == 6)
2735 return DREGL_MASK (dst0);
2736 else if (sop == 1 && sopcde == 6)
2737 return DREGL_MASK (dst0);
2738 else if (sop == 3 && sopcde == 6)
2739 return DREGL_MASK (dst0);
2740 else if (sop == 0 && sopcde == 7)
2741 return DREGL_MASK (dst0);
2742 else if (sop == 1 && sopcde == 7)
2743 return DREGL_MASK (dst0);
2744 else if (sop == 2 && sopcde == 7)
2745 return DREGL_MASK (dst0);
2746 else if (sop == 3 && sopcde == 7)
2747 return DREGL_MASK (dst0);
2748 else if (sop == 0 && sopcde == 8)
2749 return DREG_MASK (src0) | DREG_MASK (src1);
2752 OUTS (outf, "BITMUX (");
2753 OUTS (outf, dregs (src0));
2755 OUTS (outf, dregs (src1));
2756 OUTS (outf, ", A0) (ASR)");
2759 else if (sop == 1 && sopcde == 8)
2760 return DREG_MASK (src0) | DREG_MASK (src1);
2763 OUTS (outf, "BITMUX (");
2764 OUTS (outf, dregs (src0));
2766 OUTS (outf, dregs (src1));
2767 OUTS (outf, ", A0) (ASL)");
2770 else if (sopcde == 9)
2771 return sop < 2 ? DREGL_MASK (dst0) : DREG_MASK (dst0);
2772 else if (sopcde == 10)
2773 return DREG_MASK (dst0);
2774 else if (sop == 0 && sopcde == 11)
2775 return DREGL_MASK (dst0);
2776 else if (sop == 1 && sopcde == 11)
2777 return DREGL_MASK (dst0);
2778 else if (sop == 0 && sopcde == 12)
2780 else if (sop == 1 && sopcde == 12)
2781 return DREGL_MASK (dst0);
2782 else if (sop == 0 && sopcde == 13)
2783 return DREG_MASK (dst0);
2784 else if (sop == 1 && sopcde == 13)
2785 return DREG_MASK (dst0);
2786 else if (sop == 2 && sopcde == 13)
2787 return DREG_MASK (dst0);
2793 decode_dsp32shiftimm_0 (int iw0, int iw1)
2796 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
2797 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
2798 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
2799 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+ */
2800 int sop = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
2801 int bit8 = ((iw1 >> 8) & 0x1);
2802 int dst0 = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
2803 int sopcde = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
2804 int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
2807 if (sop == 0 && sopcde == 0)
2808 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2809 else if (sop == 1 && sopcde == 0 && bit8 == 0)
2810 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2811 else if (sop == 1 && sopcde == 0 && bit8 == 1)
2812 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2813 else if (sop == 2 && sopcde == 0 && bit8 == 0)
2814 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2815 else if (sop == 2 && sopcde == 0 && bit8 == 1)
2816 return HLs & 2 ? DREGH_MASK (dst0) : DREGL_MASK (dst0);
2817 else if (sop == 2 && sopcde == 3 && HLs == 1)
2819 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
2821 else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
2823 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
2825 else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
2827 else if (sop == 1 && sopcde == 3 && HLs == 0)
2829 else if (sop == 1 && sopcde == 3 && HLs == 1)
2831 else if (sop == 2 && sopcde == 3 && HLs == 0)
2833 else if (sop == 1 && sopcde == 1 && bit8 == 0)
2834 return DREG_MASK (dst0);
2835 else if (sop == 1 && sopcde == 1 && bit8 == 1)
2836 return DREG_MASK (dst0);
2837 else if (sop == 2 && sopcde == 1 && bit8 == 1)
2838 return DREG_MASK (dst0);
2839 else if (sop == 2 && sopcde == 1 && bit8 == 0)
2840 return DREG_MASK (dst0);
2841 else if (sop == 0 && sopcde == 1)
2842 return DREG_MASK (dst0);
2843 else if (sop == 1 && sopcde == 2)
2844 return DREG_MASK (dst0);
2845 else if (sop == 2 && sopcde == 2 && bit8 == 1)
2846 return DREG_MASK (dst0);
2847 else if (sop == 2 && sopcde == 2 && bit8 == 0)
2848 return DREG_MASK (dst0);
2849 else if (sop == 3 && sopcde == 2)
2850 return DREG_MASK (dst0);
2851 else if (sop == 0 && sopcde == 2)
2852 return DREG_MASK (dst0);
2858 insn_regmask (int iw0, int iw1)
2860 if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
2861 return 0; /* MNOP */
2862 else if ((iw0 & 0xff00) == 0x0000)
2863 return decode_ProgCtrl_0 (iw0);
2864 else if ((iw0 & 0xffc0) == 0x0240)
2866 else if ((iw0 & 0xff80) == 0x0100)
2868 else if ((iw0 & 0xfe00) == 0x0400)
2870 else if ((iw0 & 0xfe00) == 0x0600)
2872 else if ((iw0 & 0xf800) == 0x0800)
2874 else if ((iw0 & 0xffe0) == 0x0200)
2876 else if ((iw0 & 0xff00) == 0x0300)
2878 else if ((iw0 & 0xf000) == 0x1000)
2880 else if ((iw0 & 0xf000) == 0x2000)
2882 else if ((iw0 & 0xf000) == 0x3000)
2884 else if ((iw0 & 0xfc00) == 0x4000)
2886 else if ((iw0 & 0xfe00) == 0x4400)
2888 else if ((iw0 & 0xf800) == 0x4800)
2890 else if ((iw0 & 0xf000) == 0x5000)
2892 else if ((iw0 & 0xf800) == 0x6000)
2894 else if ((iw0 & 0xf800) == 0x6800)
2896 else if ((iw0 & 0xf000) == 0x8000)
2897 return decode_LDSTpmod_0 (iw0);
2898 else if ((iw0 & 0xff60) == 0x9e60)
2899 return decode_dagMODim_0 (iw0);
2900 else if ((iw0 & 0xfff0) == 0x9f60)
2901 return decode_dagMODik_0 (iw0);
2902 else if ((iw0 & 0xfc00) == 0x9c00)
2903 return decode_dspLDST_0 (iw0);
2904 else if ((iw0 & 0xf000) == 0x9000)
2905 return decode_LDST_0 (iw0);
2906 else if ((iw0 & 0xfc00) == 0xb800)
2907 return decode_LDSTiiFP_0 (iw0);
2908 else if ((iw0 & 0xe000) == 0xA000)
2909 return decode_LDSTii_0 (iw0);
2910 else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
2912 else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
2914 else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
2916 else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
2918 else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
2920 else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
2921 return decode_dsp32mac_0 (iw0, iw1);
2922 else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
2923 return decode_dsp32mult_0 (iw0, iw1);
2924 else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
2925 return decode_dsp32alu_0 (iw0, iw1);
2926 else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
2927 return decode_dsp32shift_0 (iw0, iw1);
2928 else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
2929 return decode_dsp32shiftimm_0 (iw0, iw1);
2930 else if ((iw0 & 0xff00) == 0xf800)
2932 else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)