1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2017 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "struc-symbol.h"
27 #include "dwarf2dbg.h"
28 #include "dw2gencfi.h"
30 #include "elf32-avr.h"
32 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
33 struct avr_property_record_link
35 struct avr_property_record record;
36 struct avr_property_record_link *next;
42 const char * constraints;
44 int insn_size; /* In words. */
46 unsigned int bin_opcode;
49 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
50 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
52 struct avr_opcodes_s avr_opcodes[] =
54 #include "opcode/avr.h"
55 {NULL, NULL, NULL, 0, 0, 0}
59 /* Stuff for the `__gcc_isr' pseudo instruction.
61 Purpose of the pseudo instruction is to emit more efficient ISR prologues
62 and epilogues than GCC currently does. GCC has no explicit (on RTL level)
63 modelling of SREG, TMP_REG or ZERO_REG. These regs are used implicitly
64 during instruction printing. That doesn't hurt too much for ordinary
65 functions, however for small ISRs there might be some overhead.
67 As implementing http://gcc.gnu.org/PR20296 would imply an almost complete
68 rewite of GCC's AVR back-end (which might pop up less optimized code in
69 other places), we provide a pseudo-instruction which is resolved by GAS
70 into ISR prologue / epilogue as expected by GCC.
72 Using GAS for this purpose has the additional benefit that it can scan
73 code emit by inline asm which is opaque to GCC.
75 The pseudo-instruction is only supposed to handle the starting of
76 prologue and the ending of epilogues (without RETI) which deal with
77 SREG, TMP_REG and ZERO_REG and one additional, optional general purpose
80 __gcc_isr consists of 3 different "chunks":
83 Chunk 1 (ISR_CHUNK_Prologue)
84 Start the ISR code. Will be replaced by ISR prologue by next Done chunk.
85 Must be the 1st chunk in a file or follow a Done chunk from previous
86 ISR (which has been patched already).
88 It will finish the current frag and emit a new frag of
89 type rs_machine_dependent, subtype ISR_CHUNK_Prologue.
92 Chunk 2 (ISR_CHUNK_Epilogue)
93 Will be replaced by ISR epilogue by next Done chunk. Must follow
94 chunk 1 (Prologue) or chunk 2 (Epilogue). Functions might come
95 without epilogue or with more than one epilogue, and even code
96 located statically after the last epilogue might belong to a function.
98 It will finish the current frag and emit a new frag of
99 type rs_machine_dependent, subtype ISR_CHUNK_Epilogue.
102 Chunk 0 (ISR_CHUNK_Done)
103 Must follow chunk 1 (Prologue) or chunk 2 (Epilogue) and finishes
104 the ISR code. Only GCC can know where a function's code ends.
106 It triggers the patch-up of all rs_machine_dependent frags in the
107 current frag chain and turns them into ordinary rs_fill code frags.
109 If Rx is a register > ZERO_REG then GCC also wants to push / pop Rx.
110 If neither TMP_REG nor ZERO_REG are needed, Rx will be used in
111 the push / pop sequence avoiding the need for TMP_REG / ZERO_REG.
112 If Rx <= ZERO_REG then GCC doesn't assume anything about Rx.
116 o GCC takes care of code that is opaque to GAS like tail calls
119 o Using SEI / CLI does not count as clobbering SREG. This is
120 because a final RETI will restore the I-flag.
122 o Using OUT or ST* is supposed not to clobber SREG. Sequences like
124 IN-SREG + CLI + Atomic-Code + OUT-SREG
126 will still work as expected because the scan will reveal any
127 clobber of SREG other than I-flag and emit PUSH / POP of SREG.
133 ISR_CHUNK_Prologue = 1,
134 ISR_CHUNK_Epilogue = 2
139 /* Previous __gcc_isr chunk (one of the enums above)
140 and it's location for diagnostics. */
144 /* Replacer for __gcc_isr.n_pushed once we know how many regs are
145 pushed by the Prologue chunk. */
146 symbolS *sym_n_pushed;
148 /* Set and used during parse from chunk 1 (Prologue) up to chunk 0 (Done).
149 Set by `avr_update_gccisr' and used by `avr_patch_gccisr_frag'. */
155 static void avr_gccisr_operands (struct avr_opcodes_s*, char**);
156 static void avr_update_gccisr (struct avr_opcodes_s*, int, int);
157 static struct avr_opcodes_s *avr_gccisr_opcode;
159 const char comment_chars[] = ";";
160 const char line_comment_chars[] = "#";
161 const char line_separator_chars[] = "$";
163 const char *md_shortopts = "m:";
171 /* XXX - devices that don't seem to exist (renamed, replaced with larger
172 ones, or planned but never produced), left here for compatibility. */
174 static struct mcu_type_s mcu_types[] =
176 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
177 /* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
178 but set to AVR_ISA_AVR25 for some following version
179 of GCC (from 4.3) for backward compatibility. */
180 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
181 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
182 /* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
183 but set to AVR_ISA_AVR3_ALL for some following version
184 of GCC (from 4.3) for backward compatibility. */
185 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
186 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
187 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
188 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
189 /* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
190 but set to AVR_ISA_AVR51 for some following version
191 of GCC (from 4.3) for backward compatibility. */
192 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
193 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
194 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
195 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
196 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
197 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
198 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
199 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
200 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
201 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
202 {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
203 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
204 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
205 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
206 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
207 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
208 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
209 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
210 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
211 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
212 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
213 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
214 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
215 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
216 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
217 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
218 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
219 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
220 {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25},
221 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
222 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
223 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
224 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
225 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
226 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
227 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
228 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
229 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
230 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
231 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
232 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
233 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
234 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
235 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
236 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
237 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
238 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
239 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
240 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
241 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
242 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
243 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
244 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
245 {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25},
246 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
247 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
248 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
249 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
250 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
251 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
252 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
253 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
254 {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35},
255 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
256 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
257 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
258 {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35},
259 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
260 {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4},
261 {"atmega8a", AVR_ISA_M8, bfd_mach_avr4},
262 {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4},
263 {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4},
264 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
265 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
266 {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4},
267 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
268 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
269 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
270 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
271 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
272 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
273 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
274 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
275 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
276 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
277 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
278 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
279 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
280 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
281 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
282 {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5},
283 {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5},
284 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
285 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
286 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
287 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
288 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
289 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
290 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
291 {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5},
292 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
293 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
294 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
295 {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5},
296 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
297 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
298 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
299 {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5},
300 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
301 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
302 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
303 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
304 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
305 {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5},
306 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
307 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
308 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
309 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
310 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
311 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
312 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
313 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
314 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
315 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
316 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
317 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
318 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
319 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
320 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
321 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
322 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
323 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
324 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
325 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
326 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
327 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
328 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
329 {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5},
330 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
331 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
332 {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5},
333 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
334 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
335 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
336 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
337 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
338 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
339 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
340 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
341 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
342 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
343 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
344 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
345 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
346 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
347 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
348 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
349 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
350 {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
351 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
352 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
353 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
354 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
355 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
356 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
357 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
358 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
359 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
360 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
361 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
362 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
363 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
364 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
365 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
366 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
367 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
368 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
369 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
370 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
371 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
372 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
373 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
374 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
375 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
376 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
377 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
378 {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51},
379 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
380 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
381 {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51},
382 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
383 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
384 {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
385 {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
386 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
387 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
388 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
389 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
390 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
391 {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
392 {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
393 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
394 {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
395 {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
396 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
397 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
398 {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
399 {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
400 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
401 {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
402 {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
403 {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
404 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
405 {"attiny212", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
406 {"attiny214", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
407 {"attiny412", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
408 {"attiny414", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
409 {"attiny416", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
410 {"attiny417", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
411 {"attiny814", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
412 {"attiny816", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
413 {"attiny817", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
414 {"attiny1614", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
415 {"attiny1616", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
416 {"attiny1617", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
417 {"attiny3214", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
418 {"attiny3216", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
419 {"attiny3217", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
420 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
421 {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
422 {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
423 {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
424 {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
425 {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
426 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
427 {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
428 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
429 {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
430 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
431 {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
432 {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
433 {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
434 {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
435 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
436 {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
437 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
438 {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
439 {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
440 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
441 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
442 {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
443 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
444 {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
445 {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
446 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
447 {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
448 {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
449 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
450 {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
451 {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
452 {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
453 {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
454 {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
455 {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
456 {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
457 {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
462 /* Current MCU type. */
463 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
464 static struct mcu_type_s specified_mcu;
465 static struct mcu_type_s * avr_mcu = & default_mcu;
467 /* AVR target-specific switches. */
470 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
471 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
472 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
473 int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not)
474 relocations for linker relaxation. */
475 int have_gccisr; /* Whether "__gcc_isr" is a known (pseudo) insn. */
478 static struct avr_opt_s avr_opt = { 0, 0, 0, 0, 0 };
480 const char EXP_CHARS[] = "eE";
481 const char FLT_CHARS[] = "dD";
483 static void avr_set_arch (int);
485 /* The target specific pseudo-ops which we support. */
486 const pseudo_typeS md_pseudo_table[] =
488 {"arch", avr_set_arch, 0},
492 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
494 #define EXP_MOD_NAME(i) exp_mod[i].name
495 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
496 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
497 #define HAVE_PM_P(i) exp_mod[i].have_pm
502 bfd_reloc_code_real_type reloc;
503 bfd_reloc_code_real_type neg_reloc;
507 static struct exp_mod_s exp_mod[] =
509 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
510 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
511 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
512 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
513 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
514 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
515 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
516 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
519 /* A union used to store indices into the exp_mod[] array
520 in a hash table which expects void * data types. */
527 /* Opcode hash table. */
528 static struct hash_control *avr_hash;
530 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
531 static struct hash_control *avr_mod_hash;
533 /* Whether some opcode does not change SREG. */
534 static struct hash_control *avr_no_sreg_hash;
536 static const char* const avr_no_sreg[] =
539 "ldi", "swap", "mov", "movw",
540 /* Special instructions. I-Flag will be restored by RETI, and we don't
541 consider I-Flag as being clobbered when changed. */
542 "sei", "cli", "reti", "brie", "brid",
543 "nop", "wdr", "sleep",
545 "ld", "ldd", "lds", "pop", "in", "lpm", "elpm",
546 "st", "std", "sts", "push", "out",
547 /* Jumps and Calls. Calls might call code that changes SREG.
548 GCC has to filter out ABI calls. The non-ABI transparent calls
549 must use [R]CALL and are filtered out now by not mentioning them. */
550 "rjmp", "jmp", "ijmp", "ret",
551 /* Skipping. Branches need SREG to be set, hence we regard them
552 as if they changed SREG and don't list them here. */
553 "sbrc", "sbrs", "sbic", "sbis", "cpse",
554 /* I/O Manipulation */
556 /* Read-Modify-Write */
557 "lac", "las", "lat", "xch"
560 #define OPTION_MMCU 'm'
563 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
568 OPTION_NO_LINK_RELAX,
572 struct option md_longopts[] =
574 { "mmcu", required_argument, NULL, OPTION_MMCU },
575 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
576 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
577 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
578 { "mrmw", no_argument, NULL, OPTION_ISA_RMW },
579 { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX },
580 { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX },
581 { "mgcc-isr", no_argument, NULL, OPTION_HAVE_GCCISR },
582 { NULL, no_argument, NULL, 0 }
585 size_t md_longopts_size = sizeof (md_longopts);
587 /* Display nicely formatted list of known MCU names. */
590 show_mcu_list (FILE *stream)
594 fprintf (stream, _("Known MCU names:"));
597 for (i = 0; mcu_types[i].name; i++)
599 int len = strlen (mcu_types[i].name);
604 fprintf (stream, " %s", mcu_types[i].name);
607 fprintf (stream, "\n %s", mcu_types[i].name);
612 fprintf (stream, "\n");
618 while (*s == ' ' || *s == '\t')
623 /* Extract one word from FROM and copy it to TO. */
626 extract_word (char *from, char *to, int limit)
631 /* Drop leading whitespace. */
632 from = skip_space (from);
635 /* Find the op code end. */
636 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
638 to[size++] = *op_end++;
639 if (size + 1 >= limit)
648 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
649 asection *seg ATTRIBUTE_UNUSED)
656 md_show_usage (FILE *stream)
659 _("AVR Assembler options:\n"
660 " -mmcu=[avr-name] select microcontroller variant\n"
661 " [avr-name] can be:\n"
662 " avr1 - classic AVR core without data RAM\n"
663 " avr2 - classic AVR core with up to 8K program memory\n"
664 " avr25 - classic AVR core with up to 8K program memory\n"
665 " plus the MOVW instruction\n"
666 " avr3 - classic AVR core with up to 64K program memory\n"
667 " avr31 - classic AVR core with up to 128K program memory\n"
668 " avr35 - classic AVR core with up to 64K program memory\n"
669 " plus the MOVW instruction\n"
670 " avr4 - enhanced AVR core with up to 8K program memory\n"
671 " avr5 - enhanced AVR core with up to 64K program memory\n"
672 " avr51 - enhanced AVR core with up to 128K program memory\n"
673 " avr6 - enhanced AVR core with up to 256K program memory\n"
674 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
675 " avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM\n"
676 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
677 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
678 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
679 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
680 " avrtiny - AVR Tiny core with 16 gp registers\n"));
682 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
683 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
684 " (default for avr4, avr5)\n"
685 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
686 " (default for avr3, avr5)\n"
687 " -mrmw accept Read-Modify-Write instructions\n"
688 " -mlink-relax generate relocations for linker relaxation (default)\n"
689 " -mno-link-relax don't generate relocations for linker relaxation.\n"
690 " -mgcc-isr accept the __gcc_isr pseudo-instruction.\n"
692 show_mcu_list (stream);
696 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
700 input_line_pointer = extract_word (input_line_pointer, str, 20);
701 md_parse_option (OPTION_MMCU, str);
702 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
706 md_parse_option (int c, const char *arg)
714 for (i = 0; mcu_types[i].name; ++i)
715 if (strcasecmp (mcu_types[i].name, arg) == 0)
718 if (!mcu_types[i].name)
720 show_mcu_list (stderr);
721 as_fatal (_("unknown MCU: %s\n"), arg);
724 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
725 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
726 as .arch ... in the asm output at the same time. */
727 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
729 specified_mcu.name = mcu_types[i].name;
730 specified_mcu.isa |= mcu_types[i].isa;
731 specified_mcu.mach = mcu_types[i].mach;
732 avr_mcu = &specified_mcu;
735 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
736 avr_mcu->name, mcu_types[i].name);
739 case OPTION_ALL_OPCODES:
740 avr_opt.all_opcodes = 1;
742 case OPTION_NO_SKIP_BUG:
743 avr_opt.no_skip_bug = 1;
749 specified_mcu.isa |= AVR_ISA_RMW;
751 case OPTION_LINK_RELAX:
752 avr_opt.no_link_relax = 0;
754 case OPTION_NO_LINK_RELAX:
755 avr_opt.no_link_relax = 1;
757 case OPTION_HAVE_GCCISR:
758 avr_opt.have_gccisr = 1;
766 /* Implement `md_undefined_symbol' */
767 /* If we are in `__gcc_isr' chunk, pop up `__gcc_isr.n_pushed.<NUM>'
768 instead of `__gcc_isr.n_pushed'. This will be resolved by the Done
769 chunk in `avr_patch_gccisr_frag' to the number of PUSHes produced by
770 the Prologue chunk. */
773 avr_undefined_symbol (char *name)
775 if (ISR_CHUNK_Done != avr_isr.prev_chunk
776 && 0 == strcmp (name, "__gcc_isr.n_pushed"))
778 if (!avr_isr.sym_n_pushed)
780 static unsigned suffix;
782 sprintf (xname, "%s.%03u", name, (++suffix) % 1000);
783 avr_isr.sym_n_pushed = symbol_new (xname, undefined_section,
784 (valueT) 0, &zero_address_frag);
786 return avr_isr.sym_n_pushed;
793 md_atof (int type, char *litP, int *sizeP)
795 return ieee_md_atof (type, litP, sizeP, FALSE);
799 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
800 asection *sec ATTRIBUTE_UNUSED,
801 fragS *fragP ATTRIBUTE_UNUSED)
810 struct avr_opcodes_s *opcode;
812 avr_hash = hash_new ();
814 /* Insert unique names into hash table. This hash table then provides a
815 quick index to the first opcode with a particular name in the opcode
817 for (opcode = avr_opcodes; opcode->name; opcode++)
818 hash_insert (avr_hash, opcode->name, (char *) opcode);
820 avr_mod_hash = hash_new ();
822 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
827 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
830 avr_no_sreg_hash = hash_new ();
832 for (i = 0; i < ARRAY_SIZE (avr_no_sreg); ++i)
834 gas_assert (hash_find (avr_hash, avr_no_sreg[i]));
835 hash_insert (avr_no_sreg_hash, avr_no_sreg[i], (char*) 4 /* dummy */);
838 avr_gccisr_opcode = (struct avr_opcodes_s*) hash_find (avr_hash, "__gcc_isr");
839 gas_assert (avr_gccisr_opcode);
841 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
842 linkrelax = !avr_opt.no_link_relax;
845 /* Resolve STR as a constant expression and return the result.
846 If result greater than MAX then error. */
849 avr_get_constant (char *str, int max)
853 str = skip_space (str);
854 input_line_pointer = str;
857 if (ex.X_op != O_constant)
858 as_bad (_("constant value required"));
860 if (ex.X_add_number > max || ex.X_add_number < 0)
861 as_bad (_("number must be positive and less than %d"), max + 1);
863 return ex.X_add_number;
866 /* Parse for ldd/std offset. */
869 avr_offset_expression (expressionS *exp)
871 char *str = input_line_pointer;
876 str = extract_word (str, op, sizeof (op));
878 input_line_pointer = tmp;
881 /* Warn about expressions that fail to use lo8 (). */
882 if (exp->X_op == O_constant)
884 int x = exp->X_add_number;
886 if (x < -255 || x > 255)
887 as_warn (_("constant out of 8-bit range: %d"), x);
891 /* Parse ordinary expression. */
894 parse_exp (char *s, expressionS *op)
896 input_line_pointer = s;
898 if (op->X_op == O_absent)
899 as_bad (_("missing operand"));
900 return input_line_pointer;
903 /* Parse special expressions (needed for LDI command):
908 where xx is: hh, hi, lo. */
910 static bfd_reloc_code_real_type
911 avr_ldi_expression (expressionS *exp)
913 char *str = input_line_pointer;
917 int linker_stubs_should_be_generated = 0;
921 str = extract_word (str, op, sizeof (op));
927 m.ptr = hash_find (avr_mod_hash, op);
935 str = skip_space (str);
939 bfd_reloc_code_real_type reloc_to_return;
944 if (strncmp ("pm(", str, 3) == 0
945 || strncmp ("gs(",str,3) == 0
946 || strncmp ("-(gs(",str,5) == 0
947 || strncmp ("-(pm(", str, 5) == 0)
955 as_bad (_("illegal expression"));
957 if (str[0] == 'g' || str[2] == 'g')
958 linker_stubs_should_be_generated = 1;
970 if (*str == '-' && *(str + 1) == '(')
977 input_line_pointer = str;
982 if (*input_line_pointer != ')')
984 as_bad (_("`)' required"));
987 input_line_pointer++;
992 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
993 if (linker_stubs_should_be_generated)
995 switch (reloc_to_return)
997 case BFD_RELOC_AVR_LO8_LDI_PM:
998 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
1000 case BFD_RELOC_AVR_HI8_LDI_PM:
1001 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
1005 /* PR 5523: Do not generate a warning here,
1006 legitimate code can trigger this case. */
1010 return reloc_to_return;
1015 input_line_pointer = tmp;
1018 /* Warn about expressions that fail to use lo8 (). */
1019 if (exp->X_op == O_constant)
1021 int x = exp->X_add_number;
1023 if (x < -255 || x > 255)
1024 as_warn (_("constant out of 8-bit range: %d"), x);
1027 return BFD_RELOC_AVR_LDI;
1030 /* Parse one instruction operand.
1031 Return operand bitmask. Also fixups can be generated. */
1034 avr_operand (struct avr_opcodes_s *opcode,
1040 expressionS op_expr;
1041 unsigned int op_mask = 0;
1042 char *str = skip_space (*line);
1046 /* Any register operand. */
1053 char * old_str = str;
1057 str = extract_word (str, r_name, sizeof (r_name));
1058 for (lower = r_name; *lower; ++lower)
1060 if (*lower >= 'A' && *lower <= 'Z')
1061 *lower += 'a' - 'A';
1064 if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0)
1065 /* Single-digit register number, ie r0-r9. */
1066 op_mask = r_name[1] - '0';
1067 else if (r_name[0] == 'r' && ISDIGIT (r_name[1])
1068 && ISDIGIT (r_name[2]) && r_name[3] == 0)
1069 /* Double-digit register number, ie r10 - r32. */
1070 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
1071 else if (r_name[0] >= 'x' && r_name[0] <= 'z'
1072 && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0)
1073 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
1074 op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26;
1075 else if ((*op == 'v' || *op == 'w')
1076 && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0)
1077 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
1078 op_mask = (r_name[0] - 'x') * 2 + 26;
1081 /* Numeric or symbolic constant register number. */
1082 op_mask = avr_get_constant (old_str, 31);
1083 str = input_line_pointer;
1090 if (avr_mcu->mach == bfd_mach_avrtiny)
1092 if (op_mask < 16 || op_mask > 31)
1094 as_bad (_("register name or number from 16 to 31 required"));
1098 else if (op_mask > 31)
1100 as_bad (_("register name or number from 0 to 31 required"));
1107 if (op_mask < 16 || op_mask > 23)
1108 as_bad (_("register r16-r23 required"));
1114 as_bad (_("register number above 15 required"));
1120 as_bad (_("even register number required"));
1125 if ((op_mask & 1) || op_mask < 24)
1126 as_bad (_("register r24, r26, r28 or r30 required"));
1127 op_mask = (op_mask - 24) >> 1;
1138 str = skip_space (str + 1);
1147 as_bad (_("pointer register (X, Y or Z) required"));
1149 str = skip_space (str + 1);
1154 as_bad (_("cannot both predecrement and postincrement"));
1158 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
1159 registers, no predecrement, no postincrement. */
1160 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
1161 && !(avr_mcu->isa & AVR_ISA_SRAM))
1162 as_bad (_("addressing mode not supported"));
1168 as_bad (_("can't predecrement"));
1170 if (! (*str == 'z' || *str == 'Z'))
1171 as_bad (_("pointer register Z required"));
1173 str = skip_space (str + 1);
1179 for (s = opcode->opcode; *s; ++s)
1182 op_mask |= (1 << (15 - (s - opcode->opcode)));
1186 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1187 if (!avr_opt.all_opcodes
1188 && (op_mask & 0x0001)
1189 && !(avr_mcu->isa & AVR_ISA_MOVW))
1190 as_bad (_("postincrement not supported"));
1195 char c = TOLOWER (*str++);
1200 as_bad (_("pointer register (Y or Z) required"));
1201 str = skip_space (str);
1204 input_line_pointer = str;
1205 avr_offset_expression (& op_expr);
1206 str = input_line_pointer;
1207 fix_new_exp (frag_now, where, 3,
1208 &op_expr, FALSE, BFD_RELOC_AVR_6);
1214 str = parse_exp (str, &op_expr);
1215 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1216 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
1220 str = parse_exp (str, &op_expr);
1221 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1222 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
1226 str = parse_exp (str, &op_expr);
1227 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1228 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
1232 str = parse_exp (str, &op_expr);
1233 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
1234 &op_expr, FALSE, BFD_RELOC_16);
1238 str = parse_exp (str, &op_expr);
1239 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1240 &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
1245 bfd_reloc_code_real_type r_type;
1247 input_line_pointer = str;
1248 r_type = avr_ldi_expression (&op_expr);
1249 str = input_line_pointer;
1250 fix_new_exp (frag_now, where, 3,
1251 &op_expr, FALSE, r_type);
1259 x = ~avr_get_constant (str, 255);
1260 str = input_line_pointer;
1261 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
1269 x = avr_get_constant (str, 255);
1270 str = input_line_pointer;
1276 input_line_pointer = str;
1277 avr_offset_expression (& op_expr);
1278 str = input_line_pointer;
1279 fix_new_exp (frag_now, where, 3,
1280 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
1288 x = avr_get_constant (str, 7);
1289 str = input_line_pointer;
1297 str = parse_exp (str, &op_expr);
1298 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1299 &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
1303 str = parse_exp (str, &op_expr);
1304 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1305 &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
1312 x = avr_get_constant (str, 15);
1313 str = input_line_pointer;
1314 op_mask |= (x << 4);
1322 as_bad (_("unknown constraint `%c'"), *op);
1329 /* Parse instruction operands.
1330 Return binary opcode. */
1333 avr_operands (struct avr_opcodes_s *opcode, char **line)
1335 const char *op = opcode->constraints;
1336 unsigned int bin = opcode->bin_opcode;
1337 char *frag = frag_more (opcode->insn_size * 2);
1339 int where = frag - frag_now->fr_literal;
1340 static unsigned int prev = 0; /* Previous opcode. */
1344 /* Opcode have operands. */
1347 unsigned int reg1 = 0;
1348 unsigned int reg2 = 0;
1349 int reg1_present = 0;
1350 int reg2_present = 0;
1352 /* Parse first operand. */
1353 if (REGISTER_P (*op))
1355 reg1 = avr_operand (opcode, where, op, &str, ®no1);
1358 /* Parse second operand. */
1372 if (REGISTER_P (*op))
1375 str = skip_space (str);
1377 as_bad (_("`,' required"));
1378 str = skip_space (str);
1380 reg2 = avr_operand (opcode, where, op, &str, ®no2);
1383 if (reg1_present && reg2_present)
1384 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1385 else if (reg2_present)
1393 if (avr_opt.have_gccisr)
1394 avr_update_gccisr (opcode, regno1, regno2);
1396 /* Detect undefined combinations (like ld r31,Z+). */
1397 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1398 as_warn (_("undefined combination of operands"));
1400 if (opcode->insn_size == 2)
1402 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1403 (AVR core bug, fixed in the newer devices). */
1404 if (!(avr_opt.no_skip_bug ||
1405 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1406 && AVR_SKIP_P (prev))
1407 as_warn (_("skipping two-word instruction"));
1409 bfd_putl32 ((bfd_vma) bin, frag);
1412 bfd_putl16 ((bfd_vma) bin, frag);
1419 /* GAS will call this function for each section at the end of the assembly,
1420 to permit the CPU backend to adjust the alignment of a section. */
1423 md_section_align (asection *seg, valueT addr)
1425 int align = bfd_get_section_alignment (stdoutput, seg);
1426 return ((addr + (1 << align) - 1) & (-1UL << align));
1429 /* If you define this macro, it should return the offset between the
1430 address of a PC relative fixup and the position from which the PC
1431 relative adjustment should be made. On many processors, the base
1432 of a PC relative instruction is the next instruction, so this
1433 macro would return the length of an instruction. */
1436 md_pcrel_from_section (fixS *fixp, segT sec)
1438 if (fixp->fx_addsy != (symbolS *) NULL
1439 && (!S_IS_DEFINED (fixp->fx_addsy)
1440 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1443 return fixp->fx_frag->fr_address + fixp->fx_where;
1447 relaxable_section (asection *sec)
1449 return ((sec->flags & SEC_DEBUGGING) == 0
1450 && (sec->flags & SEC_CODE) != 0
1451 && (sec->flags & SEC_ALLOC) != 0);
1454 /* Does whatever the xtensa port does. */
1456 avr_validate_fix_sub (fixS *fix)
1458 segT add_symbol_segment, sub_symbol_segment;
1460 /* The difference of two symbols should be resolved by the assembler when
1461 linkrelax is not set. If the linker may relax the section containing
1462 the symbols, then an Xtensa DIFF relocation must be generated so that
1463 the linker knows to adjust the difference value. */
1464 if (!linkrelax || fix->fx_addsy == NULL)
1467 /* Make sure both symbols are in the same segment, and that segment is
1468 "normal" and relaxable. If the segment is not "normal", then the
1469 fix is not valid. If the segment is not "relaxable", then the fix
1470 should have been handled earlier. */
1471 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
1472 if (! SEG_NORMAL (add_symbol_segment) ||
1473 ! relaxable_section (add_symbol_segment))
1476 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
1477 return (sub_symbol_segment == add_symbol_segment);
1480 /* TC_FORCE_RELOCATION hook */
1482 /* If linkrelax is turned on, and the symbol to relocate
1483 against is in a relaxable segment, don't compute the value -
1484 generate a relocation instead. */
1486 avr_force_relocation (fixS *fix)
1488 if (linkrelax && fix->fx_addsy
1489 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
1492 return generic_force_reloc (fix);
1495 /* GAS will call this for each fixup. It should store the correct
1496 value in the object file. */
1499 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1501 unsigned char *where;
1505 if (fixP->fx_addsy == (symbolS *) NULL)
1508 else if (fixP->fx_pcrel)
1510 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1512 if (s == seg || s == absolute_section)
1514 value += S_GET_VALUE (fixP->fx_addsy);
1518 else if (linkrelax && fixP->fx_subsy)
1520 /* For a subtraction relocation expression, generate one
1521 of the DIFF relocs, with the value being the difference.
1522 Note that a sym1 - sym2 expression is adjusted into a
1523 section_start_sym + sym4_offset_from_section_start - sym1
1524 expression. fixP->fx_addsy holds the section start symbol,
1525 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1526 holds sym1. Calculate the current difference and write value,
1527 but leave fx_offset as is - during relaxation,
1528 fx_offset - value gives sym1's value. */
1530 switch (fixP->fx_r_type)
1533 fixP->fx_r_type = BFD_RELOC_AVR_DIFF8;
1536 fixP->fx_r_type = BFD_RELOC_AVR_DIFF16;
1539 fixP->fx_r_type = BFD_RELOC_AVR_DIFF32;
1542 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1546 value = S_GET_VALUE (fixP->fx_addsy) +
1547 fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
1550 fixP->fx_subsy = NULL;
1552 /* We don't actually support subtracting a symbol. */
1553 if (fixP->fx_subsy != (symbolS *) NULL)
1554 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1556 /* For the DIFF relocs, write the value into the object file while still
1557 keeping fx_done FALSE, as both the difference (recorded in the object file)
1558 and the sym offset (part of fixP) are needed at link relax time. */
1559 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1560 switch (fixP->fx_r_type)
1563 fixP->fx_no_overflow = 1;
1565 case BFD_RELOC_AVR_7_PCREL:
1566 case BFD_RELOC_AVR_13_PCREL:
1570 case BFD_RELOC_AVR_DIFF8:
1573 case BFD_RELOC_AVR_DIFF16:
1574 bfd_putl16 ((bfd_vma) value, where);
1576 case BFD_RELOC_AVR_DIFF32:
1577 bfd_putl32 ((bfd_vma) value, where);
1579 case BFD_RELOC_AVR_CALL:
1585 /* Fetch the instruction, insert the fully resolved operand
1586 value, and stuff the instruction back again. */
1587 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1588 insn = bfd_getl16 (where);
1590 switch (fixP->fx_r_type)
1592 case BFD_RELOC_AVR_7_PCREL:
1594 as_bad_where (fixP->fx_file, fixP->fx_line,
1595 _("odd address operand: %ld"), value);
1597 /* Instruction addresses are always right-shifted by 1. */
1599 --value; /* Correct PC. */
1601 if (value < -64 || value > 63)
1602 as_bad_where (fixP->fx_file, fixP->fx_line,
1603 _("operand out of range: %ld"), value);
1604 value = (value << 3) & 0x3f8;
1605 bfd_putl16 ((bfd_vma) (value | insn), where);
1608 case BFD_RELOC_AVR_13_PCREL:
1610 as_bad_where (fixP->fx_file, fixP->fx_line,
1611 _("odd address operand: %ld"), value);
1613 /* Instruction addresses are always right-shifted by 1. */
1615 --value; /* Correct PC. */
1617 if (value < -2048 || value > 2047)
1619 /* No wrap for devices with >8K of program memory. */
1620 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1621 as_bad_where (fixP->fx_file, fixP->fx_line,
1622 _("operand out of range: %ld"), value);
1626 bfd_putl16 ((bfd_vma) (value | insn), where);
1630 bfd_putl32 ((bfd_vma) value, where);
1634 bfd_putl16 ((bfd_vma) value, where);
1638 if (value > 255 || value < -128)
1639 as_warn_where (fixP->fx_file, fixP->fx_line,
1640 _("operand out of range: %ld"), value);
1644 case BFD_RELOC_AVR_16_PM:
1645 bfd_putl16 ((bfd_vma) (value >> 1), where);
1648 case BFD_RELOC_AVR_LDI:
1650 as_bad_where (fixP->fx_file, fixP->fx_line,
1651 _("operand out of range: %ld"), value);
1652 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1655 case BFD_RELOC_AVR_LDS_STS_16:
1656 if ((value < 0x40) || (value > 0xBF))
1657 as_warn_where (fixP->fx_file, fixP->fx_line,
1658 _("operand out of range: 0x%lx"),
1659 (unsigned long)value);
1660 insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
1661 bfd_putl16 ((bfd_vma) insn, where);
1664 case BFD_RELOC_AVR_6:
1665 if ((value > 63) || (value < 0))
1666 as_bad_where (fixP->fx_file, fixP->fx_line,
1667 _("operand out of range: %ld"), value);
1668 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
1669 | ((value & (1 << 5)) << 8)), where);
1672 case BFD_RELOC_AVR_6_ADIW:
1673 if ((value > 63) || (value < 0))
1674 as_bad_where (fixP->fx_file, fixP->fx_line,
1675 _("operand out of range: %ld"), value);
1676 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1679 case BFD_RELOC_AVR_LO8_LDI:
1680 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1683 case BFD_RELOC_AVR_HI8_LDI:
1684 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1687 case BFD_RELOC_AVR_MS8_LDI:
1688 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1691 case BFD_RELOC_AVR_HH8_LDI:
1692 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1695 case BFD_RELOC_AVR_LO8_LDI_NEG:
1696 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1699 case BFD_RELOC_AVR_HI8_LDI_NEG:
1700 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1703 case BFD_RELOC_AVR_MS8_LDI_NEG:
1704 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1707 case BFD_RELOC_AVR_HH8_LDI_NEG:
1708 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1711 case BFD_RELOC_AVR_LO8_LDI_PM:
1712 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1715 case BFD_RELOC_AVR_HI8_LDI_PM:
1716 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1719 case BFD_RELOC_AVR_HH8_LDI_PM:
1720 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1723 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1724 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1727 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1728 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1731 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1732 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1735 case BFD_RELOC_AVR_CALL:
1739 x = bfd_getl16 (where);
1741 as_bad_where (fixP->fx_file, fixP->fx_line,
1742 _("odd address operand: %ld"), value);
1744 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1745 bfd_putl16 ((bfd_vma) x, where);
1746 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1750 case BFD_RELOC_AVR_8_LO:
1751 *where = 0xff & value;
1754 case BFD_RELOC_AVR_8_HI:
1755 *where = 0xff & (value >> 8);
1758 case BFD_RELOC_AVR_8_HLO:
1759 *where = 0xff & (value >> 16);
1763 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1764 fixP->fx_line, fixP->fx_r_type);
1767 case BFD_RELOC_AVR_PORT6:
1769 as_bad_where (fixP->fx_file, fixP->fx_line,
1770 _("operand out of range: %ld"), value);
1771 bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where);
1774 case BFD_RELOC_AVR_PORT5:
1776 as_bad_where (fixP->fx_file, fixP->fx_line,
1777 _("operand out of range: %ld"), value);
1778 bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where);
1784 switch ((int) fixP->fx_r_type)
1786 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1787 case -BFD_RELOC_AVR_HI8_LDI:
1788 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1789 case -BFD_RELOC_AVR_LO8_LDI:
1790 as_bad_where (fixP->fx_file, fixP->fx_line,
1791 _("only constant expression allowed"));
1800 /* GAS will call this to generate a reloc, passing the resulting reloc
1801 to `bfd_install_relocation'. This currently works poorly, as
1802 `bfd_install_relocation' often does the wrong thing, and instances of
1803 `tc_gen_reloc' have been written to work around the problems, which
1804 in turns makes it difficult to fix `bfd_install_relocation'. */
1806 /* If while processing a fixup, a reloc really needs to be created
1807 then it is done here. */
1810 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1814 bfd_reloc_code_real_type code = fixp->fx_r_type;
1816 if (fixp->fx_subsy != NULL)
1818 as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
1822 reloc = XNEW (arelent);
1824 reloc->sym_ptr_ptr = XNEW (asymbol *);
1825 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1827 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1829 if ((fixp->fx_r_type == BFD_RELOC_32) && (fixp->fx_pcrel))
1831 if (seg->use_rela_p)
1832 fixp->fx_offset -= md_pcrel_from_section (fixp, seg);
1834 fixp->fx_offset = reloc->address;
1836 code = BFD_RELOC_32_PCREL;
1839 reloc->addend = fixp->fx_offset;
1841 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1843 if (reloc->howto == (reloc_howto_type *) NULL)
1845 as_bad_where (fixp->fx_file, fixp->fx_line,
1846 _("reloc %d not supported by object file format"),
1847 (int) fixp->fx_r_type);
1851 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1852 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1853 reloc->address = fixp->fx_offset;
1860 md_assemble (char *str)
1862 struct avr_opcodes_s *opcode;
1865 str = skip_space (extract_word (str, op, sizeof (op)));
1868 as_bad (_("can't find opcode "));
1870 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1872 if (opcode && !avr_opt.all_opcodes)
1874 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1875 specified by the user. If not look for other instructions
1876 specifications with same mnemonic who's ISA bits matches.
1878 This requires include/opcode/avr.h to have the instructions with
1879 same mnemonic to be specified in sequence. */
1881 while ((opcode->isa & avr_mcu->isa) != opcode->isa)
1885 if (opcode->name && strcmp(op, opcode->name))
1887 as_bad (_("illegal opcode %s for mcu %s"),
1888 opcode->name, avr_mcu->name);
1896 as_bad (_("unknown opcode `%s'"), op);
1900 if (opcode == avr_gccisr_opcode
1901 && !avr_opt.have_gccisr)
1903 as_bad (_("pseudo instruction `%s' not supported"), op);
1907 /* Special case for opcodes with optional operands (lpm, elpm) -
1908 version with operands exists in avr_opcodes[] in the next entry. */
1910 if (*str && *opcode->constraints == '?')
1913 dwarf2_emit_insn (0);
1915 /* We used to set input_line_pointer to the result of get_operands,
1916 but that is wrong. Our caller assumes we don't change it. */
1918 char *t = input_line_pointer;
1920 if (opcode == avr_gccisr_opcode)
1921 avr_gccisr_operands (opcode, &str);
1923 avr_operands (opcode, &str);
1924 if (*skip_space (str))
1925 as_bad (_("garbage at end of line"));
1926 input_line_pointer = t;
1930 const exp_mod_data_t exp_mod_data[] =
1932 /* Default, must be first. */
1933 { "", 0, BFD_RELOC_16, "" },
1934 /* Divides by 2 to get word address. Generate Stub. */
1935 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1936 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1937 /* The following are used together with avr-gcc's __memx address space
1938 in order to initialize a 24-bit pointer variable with a 24-bit address.
1939 For address in flash, hlo8 will contain the flash segment if the
1940 symbol is located in flash. If the symbol is located in RAM; hlo8
1941 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1942 addresses linearize address space. */
1943 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1944 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
1945 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1946 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
1949 /* Parse special CONS expression: pm (expression) or alternatively
1950 gs (expression). These are used for addressing program memory. Moreover,
1951 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1953 const exp_mod_data_t *
1954 avr_parse_cons_expression (expressionS *exp, int nbytes)
1959 tmp = input_line_pointer = skip_space (input_line_pointer);
1961 /* The first entry of exp_mod_data[] contains an entry if no
1962 expression modifier is present. Skip it. */
1964 for (i = 0; i < ARRAY_SIZE (exp_mod_data); i++)
1966 const exp_mod_data_t *pexp = &exp_mod_data[i];
1967 int len = strlen (pexp->name);
1969 if (nbytes == pexp->nbytes
1970 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
1972 input_line_pointer = skip_space (input_line_pointer + len);
1974 if (*input_line_pointer == '(')
1976 input_line_pointer = skip_space (input_line_pointer + 1);
1979 if (*input_line_pointer == ')')
1981 ++input_line_pointer;
1986 as_bad (_("`)' required"));
1987 return &exp_mod_data[0];
1991 input_line_pointer = tmp;
1998 return &exp_mod_data[0];
2002 avr_cons_fix_new (fragS *frag,
2006 const exp_mod_data_t *pexp_mod_data)
2010 switch (pexp_mod_data->reloc)
2014 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
2015 else if (nbytes == 2)
2016 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
2017 else if (nbytes == 4)
2018 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
2023 case BFD_RELOC_AVR_16_PM:
2024 case BFD_RELOC_AVR_8_LO:
2025 case BFD_RELOC_AVR_8_HI:
2026 case BFD_RELOC_AVR_8_HLO:
2027 if (nbytes == pexp_mod_data->nbytes)
2028 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
2035 as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
2039 mcu_has_3_byte_pc (void)
2041 int mach = avr_mcu->mach;
2043 return mach == bfd_mach_avr6
2044 || mach == bfd_mach_avrxmega6
2045 || mach == bfd_mach_avrxmega7;
2049 tc_cfi_frame_initial_instructions (void)
2051 /* AVR6 pushes 3 bytes for calls. */
2052 int return_size = (mcu_has_3_byte_pc () ? 3 : 2);
2054 /* The CFA is the caller's stack location before the call insn. */
2055 /* Note that the stack pointer is dwarf register number 32. */
2056 cfi_add_CFA_def_cfa (32, return_size);
2058 /* Note that AVR consistently uses post-decrement, which means that things
2059 do not line up the same way as for targets that use pre-decrement. */
2060 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
2064 avr_allow_local_subtract (expressionS * left,
2065 expressionS * right,
2068 /* If we are not in relaxation mode, subtraction is OK. */
2072 /* If the symbols are not in a code section then they are OK. */
2073 if ((section->flags & SEC_CODE) == 0)
2076 if (left->X_add_symbol == right->X_add_symbol)
2079 /* We have to assume that there may be instructions between the
2080 two symbols and that relaxation may increase the distance between
2086 avr_elf_final_processing (void)
2089 elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED;
2092 /* Write out the header of a .avr.prop section into the area pointed to by
2093 DATA. The RECORD_COUNT will be placed in the header as the number of
2094 records that are to follow.
2095 The area DATA must be big enough the receive the header, which is
2096 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
2099 avr_output_property_section_header (char *data,
2100 unsigned int record_count)
2102 char *orig_data = data;
2104 md_number_to_chars (data, AVR_PROPERTY_RECORDS_VERSION, 1);
2106 /* There's space for a single byte flags field, but right now there's
2107 nothing to go in here, so just set the value to zero. */
2108 md_number_to_chars (data, 0, 1);
2110 md_number_to_chars (data, record_count, 2);
2113 gas_assert (data - orig_data == AVR_PROPERTY_SECTION_HEADER_SIZE);
2118 /* Return the number of bytes required to store RECORD into the .avr.prop
2119 section. The size returned is the compressed size that corresponds to
2120 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
2123 avr_record_size (const struct avr_property_record *record)
2125 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
2129 switch (record->type)
2132 size += 0; /* No extra information. */
2135 case RECORD_ORG_AND_FILL:
2136 size += 4; /* A 4-byte fill value. */
2140 size += 4; /* A 4-byte alignment value. */
2143 case RECORD_ALIGN_AND_FILL:
2144 size += 8; /* A 4-byte alignment, and 4-byte fill value. */
2148 as_fatal (_("unknown record type %d (in %s)"),
2149 record->type, __PRETTY_FUNCTION__);
2155 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
2156 to hold all of the .avr.prop content, FRAG_PTR points to the next
2157 writable location. The data area must be big enough to hold all of the
2158 records. The size of the data written out for this RECORD must match
2159 the size from AVR_RECORD_SIZE. */
2162 avr_output_property_record (char * const frag_base, char *frag_ptr,
2163 const struct avr_property_record *record)
2167 char *init_frag_ptr = frag_ptr;
2169 where = frag_ptr - frag_base;
2170 fix = fix_new (frag_now, where, 4,
2171 section_symbol (record->section),
2172 record->offset, FALSE, BFD_RELOC_32);
2173 fix->fx_file = "<internal>";
2177 md_number_to_chars (frag_ptr, (bfd_byte) record->type, 1);
2180 /* Write out the rest of the data. */
2181 switch (record->type)
2186 case RECORD_ORG_AND_FILL:
2187 md_number_to_chars (frag_ptr, record->data.org.fill, 4);
2192 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
2196 case RECORD_ALIGN_AND_FILL:
2197 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
2198 md_number_to_chars (frag_ptr + 4, record->data.align.fill, 4);
2203 as_fatal (_("unknown record type %d (in %s)"),
2204 record->type, __PRETTY_FUNCTION__);
2207 gas_assert (frag_ptr - init_frag_ptr == avr_record_size (record));
2212 /* Create the section to hold the AVR property information. Return the
2216 avr_create_property_section (void)
2219 flagword flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY);
2220 const char *section_name = AVR_PROPERTY_RECORD_SECTION_NAME;
2222 sec = bfd_make_section (stdoutput, section_name);
2224 as_fatal (_("Failed to create property section `%s'\n"), section_name);
2225 bfd_set_section_flags (stdoutput, sec, flags);
2226 sec->output_section = sec;
2230 /* This hook is called when alignment is performed, and allows us to
2231 capture the details of both .org and .align directives. */
2234 avr_handle_align (fragS *fragP)
2238 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2239 start of a section, and will be handled by the standard section
2240 alignment mechanism. */
2241 if ((fragP->fr_type == rs_align
2242 || fragP->fr_type == rs_align_code)
2243 && fragP->fr_offset > 0)
2245 char *p = fragP->fr_literal + fragP->fr_fix;
2247 fragP->tc_frag_data.is_align = TRUE;
2248 fragP->tc_frag_data.alignment = fragP->fr_offset;
2249 fragP->tc_frag_data.fill = *p;
2250 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2253 if (fragP->fr_type == rs_org && fragP->fr_offset > 0)
2255 char *p = fragP->fr_literal + fragP->fr_fix;
2257 fragP->tc_frag_data.is_org = TRUE;
2258 fragP->tc_frag_data.fill = *p;
2259 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2264 /* Return TRUE if this section is not one for which we need to record
2265 information in the avr property section. */
2268 exclude_section_from_property_tables (segT sec)
2270 /* Only generate property information for sections on which linker
2271 relaxation could be performed. */
2272 return !relaxable_section (sec);
2275 /* Create a property record for fragment FRAGP from section SEC and place
2276 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2277 into a linked list by the caller. */
2279 static struct avr_property_record_link *
2280 create_record_for_frag (segT sec, fragS *fragP)
2282 struct avr_property_record_link *prop_rec_link;
2284 prop_rec_link = XCNEW (struct avr_property_record_link);
2285 gas_assert (fragP->fr_next != NULL);
2287 if (fragP->tc_frag_data.is_org)
2289 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2290 prop_rec_link->record.section = sec;
2292 if (fragP->tc_frag_data.has_fill)
2294 prop_rec_link->record.data.org.fill = fragP->tc_frag_data.fill;
2295 prop_rec_link->record.type = RECORD_ORG_AND_FILL;
2298 prop_rec_link->record.type = RECORD_ORG;
2302 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2303 prop_rec_link->record.section = sec;
2305 gas_assert (fragP->tc_frag_data.is_align);
2306 if (fragP->tc_frag_data.has_fill)
2308 prop_rec_link->record.data.align.fill = fragP->tc_frag_data.fill;
2309 prop_rec_link->record.type = RECORD_ALIGN_AND_FILL;
2312 prop_rec_link->record.type = RECORD_ALIGN;
2313 prop_rec_link->record.data.align.bytes = fragP->tc_frag_data.alignment;
2316 return prop_rec_link;
2319 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2320 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2321 the last list item created. */
2323 static struct avr_property_record_link **
2324 append_records_for_section (segT sec,
2325 struct avr_property_record_link **next_ptr)
2327 segment_info_type *seginfo = seg_info (sec);
2330 if (seginfo && seginfo->frchainP)
2332 for (fragP = seginfo->frchainP->frch_root;
2334 fragP = fragP->fr_next)
2336 if (fragP->tc_frag_data.is_align
2337 || fragP->tc_frag_data.is_org)
2339 /* Create a single new entry. */
2340 struct avr_property_record_link *new_link
2341 = create_record_for_frag (sec, fragP);
2343 *next_ptr = new_link;
2344 next_ptr = &new_link->next;
2352 /* Create the AVR property section and fill it with records of .org and
2353 .align directives that were used. The section is only created if it
2354 will actually have any content. */
2357 avr_create_and_fill_property_section (void)
2361 struct avr_property_record_link *r_list, **next_ptr;
2362 char *frag_ptr, *frag_base;
2363 bfd_size_type sec_size;
2364 struct avr_property_record_link *rec;
2365 unsigned int record_count;
2367 /* First walk over all sections. For sections on which linker
2368 relaxation could be applied, extend the record list. The record list
2369 holds information that the linker will need to know. */
2374 for (seclist = &stdoutput->sections;
2375 seclist && *seclist;
2376 seclist = &(*seclist)->next)
2378 segT sec = *seclist;
2380 if (exclude_section_from_property_tables (sec))
2383 next_ptr = append_records_for_section (sec, next_ptr);
2386 /* Create property section and ensure the size is correct. We've already
2387 passed the point where gas could size this for us. */
2388 sec_size = AVR_PROPERTY_SECTION_HEADER_SIZE;
2390 for (rec = r_list; rec != NULL; rec = rec->next)
2393 sec_size += avr_record_size (&rec->record);
2396 if (record_count == 0)
2399 prop_sec = avr_create_property_section ();
2400 bfd_set_section_size (stdoutput, prop_sec, sec_size);
2402 subseg_set (prop_sec, 0);
2403 frag_base = frag_more (sec_size);
2406 avr_output_property_section_header (frag_base, record_count);
2408 for (rec = r_list; rec != NULL; rec = rec->next)
2409 frag_ptr = avr_output_property_record (frag_base, frag_ptr, &rec->record);
2411 frag_wane (frag_now);
2413 frag_wane (frag_now);
2416 /* We're using this hook to build up the AVR property section. It's called
2417 late in the assembly process which suits our needs. */
2419 avr_post_relax_hook (void)
2421 avr_create_and_fill_property_section ();
2425 /* Accumulate information about instruction sequence to `avr_isr':
2426 wheter TMP_REG, ZERO_REG and SREG might be touched. Used during parse.
2427 REG1 is either -1 or a register number used by the instruction as input
2428 or output operand. Similar for REG2. */
2431 avr_update_gccisr (struct avr_opcodes_s *opcode, int reg1, int reg2)
2433 const int tiny_p = avr_mcu->mach == bfd_mach_avrtiny;
2434 const int reg_tmp = tiny_p ? 16 : 0;
2435 const int reg_zero = 1 + reg_tmp;
2437 if (ISR_CHUNK_Done == avr_isr.prev_chunk
2438 || (avr_isr.need_sreg
2439 && avr_isr.need_reg_tmp
2440 && avr_isr.need_reg_zero))
2442 /* Nothing (more) to do */
2446 /* SREG: Look up instructions that don't clobber SREG. */
2448 if (!avr_isr.need_sreg
2449 && !hash_find (avr_no_sreg_hash, opcode->name))
2451 avr_isr.need_sreg = 1;
2454 /* Handle explicit register operands. Record *any* use as clobber.
2455 This is because TMP_REG and ZERO_REG are not global and using
2456 them makes no sense without a previous set. */
2458 avr_isr.need_reg_tmp |= reg1 == reg_tmp || reg2 == reg_tmp;
2459 avr_isr.need_reg_zero |= reg1 == reg_zero || reg2 == reg_zero;
2461 /* Handle implicit register operands and some opaque stuff. */
2463 if (strstr (opcode->name, "lpm")
2464 && '?' == *opcode->constraints)
2466 avr_isr.need_reg_tmp = 1;
2469 if (strstr (opcode->name, "call")
2470 || strstr (opcode->name, "mul")
2471 || 0 == strcmp (opcode->name, "des")
2472 || (0 == strcmp (opcode->name, "movw")
2473 && (reg1 == reg_tmp || reg2 == reg_tmp)))
2475 avr_isr.need_reg_tmp = 1;
2476 avr_isr.need_reg_zero = 1;
2481 /* Emit some 1-word instruction to **PWHERE and advance *PWHERE by the number
2482 of octets written. INSN specifies the desired instruction and REG is the
2483 register used by it. This function is only used with restricted subset of
2484 instructions as might be emit by `__gcc_isr'. IN / OUT will use SREG
2488 avr_emit_insn (const char *insn, int reg, char **pwhere)
2490 const int sreg = 0x3f;
2492 const struct avr_opcodes_s *op
2493 = (struct avr_opcodes_s*) hash_find (avr_hash, insn);
2495 /* We only have to deal with: IN, OUT, PUSH, POP, CLR, LDI 0. All of
2496 these deal with at least one Reg and are 1-word instructions. */
2498 gas_assert (op && 1 == op->insn_size);
2499 gas_assert (reg >= 0 && reg <= 31);
2501 if (strchr (op->constraints, 'r'))
2503 bin = op->bin_opcode | (reg << 4);
2505 else if (strchr (op->constraints, 'd'))
2507 gas_assert (reg >= 16);
2508 bin = op->bin_opcode | ((reg & 0xf) << 4);
2513 if (strchr (op->constraints, 'P'))
2515 bin |= ((sreg & 0x30) << 5) | (sreg & 0x0f);
2517 else if (0 == strcmp ("r=r", op->constraints))
2519 bin |= ((reg & 0x10) << 5) | (reg & 0x0f);
2522 gas_assert (0 == strcmp ("r", op->constraints)
2523 || 0 == strcmp ("ldi", op->name));
2525 bfd_putl16 ((bfd_vma) bin, *pwhere);
2526 (*pwhere) += 2 * op->insn_size;
2530 /* Turn rs_machine_dependent frag *FR into an ordinary rs_fill code frag,
2531 using information gathered in `avr_isr'. REG is the register number as
2532 supplied by Done chunk "__gcc_isr 0,REG". */
2535 avr_patch_gccisr_frag (fragS *fr, int reg)
2539 char *where = fr->fr_literal;
2540 const int tiny_p = avr_mcu->mach == bfd_mach_avrtiny;
2541 const int reg_tmp = tiny_p ? 16 : 0;
2542 const int reg_zero = 1 + reg_tmp;
2544 /* Clearing ZERO_REG on non-Tiny needs CLR which clobbers SREG. */
2546 avr_isr.need_sreg |= !tiny_p && avr_isr.need_reg_zero;
2548 /* A working register to PUSH / POP the SREG. We might use the register
2549 as supplied by ISR_CHUNK_Done for that purpose as GCC wants to push
2550 it anyways. If GCC passes ZERO_REG or TMP_REG, it has no clue (and
2551 no additional regs to safe) and we use that reg. */
2554 = avr_isr.need_reg_tmp ? reg_tmp
2555 : avr_isr.need_reg_zero ? reg_zero
2556 : avr_isr.need_sreg ? reg
2557 : reg > reg_zero ? reg
2562 /* Non-empty prologue / epilogue */
2564 if (ISR_CHUNK_Prologue == fr->fr_subtype)
2566 avr_emit_insn ("push", treg, &where);
2569 if (avr_isr.need_sreg)
2571 avr_emit_insn ("in", treg, &where);
2572 avr_emit_insn ("push", treg, &where);
2576 if (avr_isr.need_reg_zero)
2578 if (reg_zero != treg)
2580 avr_emit_insn ("push", reg_zero, &where);
2583 avr_emit_insn (tiny_p ? "ldi" : "clr", reg_zero, &where);
2586 if (reg > reg_zero && reg != treg)
2588 avr_emit_insn ("push", reg, &where);
2592 else if (ISR_CHUNK_Epilogue == fr->fr_subtype)
2594 /* Same logic as in Prologue but in reverse order and with counter
2595 parts of either instruction: POP instead of PUSH and OUT instead
2596 of IN. Clearing ZERO_REG has no couter part. */
2598 if (reg > reg_zero && reg != treg)
2599 avr_emit_insn ("pop", reg, &where);
2601 if (avr_isr.need_reg_zero
2602 && reg_zero != treg)
2603 avr_emit_insn ("pop", reg_zero, &where);
2605 if (avr_isr.need_sreg)
2607 avr_emit_insn ("pop", treg, &where);
2608 avr_emit_insn ("out", treg, &where);
2611 avr_emit_insn ("pop", treg, &where);
2617 if (ISR_CHUNK_Prologue == fr->fr_subtype
2618 && avr_isr.sym_n_pushed)
2620 symbolS *sy = avr_isr.sym_n_pushed;
2621 /* Turn magic `__gcc_isr.n_pushed' into its now known value. */
2623 sy->sy_value.X_op = O_constant;
2624 sy->sy_value.X_add_number = n_pushed;
2625 S_SET_SEGMENT (sy, expr_section);
2626 avr_isr.sym_n_pushed = NULL;
2629 /* Turn frag into ordinary code frag of now known size. */
2632 fr->fr_fix = (offsetT) (where - fr->fr_literal);
2633 gas_assert (fr->fr_fix <= fr->fr_offset);
2635 fr->fr_type = rs_fill;
2640 /* Implements `__gcc_isr' pseudo-instruction. For Prologue and Epilogue
2641 chunks, emit a new rs_machine_dependent frag. For Done chunks, traverse
2642 the current segment and patch all rs_machine_dependent frags to become
2643 appropriate rs_fill code frags. If chunks are seen in an odd ordering,
2644 throw an error instead. */
2647 avr_gccisr_operands (struct avr_opcodes_s *opcode, char **line)
2653 gas_assert (avr_opt.have_gccisr);
2655 /* We only use operands "N" and "r" which don't pop new fix-ups. */
2657 /* 1st operand: Which chunk of __gcc_isr: 0...2. */
2659 chunk = avr_operand (opcode, -1, "N", &str, NULL);
2660 if (chunk < 0 || chunk > 2)
2661 as_bad (_("%s requires value 0-2 as operand 1"), opcode->name);
2663 if (ISR_CHUNK_Done == chunk)
2665 /* 2nd operand: A register to push / pop. */
2667 str = skip_space (str);
2668 if (*str == '\0' || *str++ != ',')
2669 as_bad (_("`,' required"));
2671 avr_operand (opcode, -1, "r", &str, ®);
2676 /* Chunks must follow in a specific order:
2677 - Prologue: Exactly one
2678 - Epilogue: Any number
2679 - Done: Exactly one. */
2680 bad |= ISR_CHUNK_Prologue == chunk && avr_isr.prev_chunk != ISR_CHUNK_Done;
2681 bad |= ISR_CHUNK_Epilogue == chunk && avr_isr.prev_chunk == ISR_CHUNK_Done;
2682 bad |= ISR_CHUNK_Done == chunk && avr_isr.prev_chunk == ISR_CHUNK_Done;
2686 as_bad (_("`%s %d' after `%s %d' from %s:%u"), opcode->name, chunk,
2687 opcode->name, avr_isr.prev_chunk, avr_isr.file, avr_isr.line);
2689 as_bad (_("`%s %d' but no chunk open yet"), opcode->name, chunk);
2694 /* The longest sequence (prologue) might have up to 6 insns (words):
2703 unsigned int size = 2 * 6;
2708 case ISR_CHUNK_Prologue:
2709 avr_isr.need_reg_tmp = 0;
2710 avr_isr.need_reg_zero = 0;
2711 avr_isr.need_sreg = 0;
2712 avr_isr.sym_n_pushed = NULL;
2715 case ISR_CHUNK_Epilogue:
2716 /* Emit a new rs_machine_dependent fragment into the fragment chain.
2717 It will be patched and cleaned up once we see the matching
2719 frag_wane (frag_now);
2723 frag_now->fr_var = 1;
2724 frag_now->fr_offset = size;
2725 frag_now->fr_fix = 0;
2726 frag_now->fr_type = rs_machine_dependent;
2727 frag_now->fr_subtype = chunk;
2731 case ISR_CHUNK_Done:
2732 /* Traverse all frags of the current subseg and turn ones of type
2733 rs_machine_dependent into ordinary code as expected by GCC. */
2735 for (fr = frchain_now->frch_root; fr; fr = fr->fr_next)
2736 if (fr->fr_type == rs_machine_dependent)
2737 avr_patch_gccisr_frag (fr, reg);
2746 avr_isr.prev_chunk = chunk;
2747 avr_isr.file = as_where (&avr_isr.line);
2751 /* Callback used by the function below. Diagnose any dangling stuff from
2752 `__gcc_isr', i.e. frags of type rs_machine_dependent. Such frags should
2753 have been resolved during parse by ISR_CHUNK_Done. If such a frag is
2754 seen, report an error and turn it into something harmless. */
2757 avr_check_gccisr_done (bfd *abfd ATTRIBUTE_UNUSED,
2759 void *xxx ATTRIBUTE_UNUSED)
2761 segment_info_type *info = seg_info (section);
2763 if (SEG_NORMAL (section)
2764 /* BFD may have introduced its own sections without using
2765 subseg_new, so it is possible that seg_info is NULL. */
2771 for (frch = info->frchainP; frch; frch = frch->frch_next)
2772 for (fr = frch->frch_root; fr; fr = fr->fr_next)
2773 if (fr->fr_type == rs_machine_dependent)
2776 as_bad_where (avr_isr.file, avr_isr.line,
2777 _("dangling `__gcc_isr %d'"), avr_isr.prev_chunk);
2778 else if (!had_errors())
2779 as_bad (_("dangling `__gcc_isr'"));
2781 avr_isr.file = NULL;
2783 /* Avoid Internal errors due to rs_machine_dependent in the
2784 remainder: Turn frag into something harmless. */
2788 fr->fr_type = rs_fill;
2795 /* Implement `md_pre_output_hook' */
2796 /* Run over all relevant sections and diagnose any dangling `__gcc_isr'.
2797 This runs after parsing all inputs but before relaxing and writing. */
2800 avr_pre_output_hook (void)
2802 if (avr_opt.have_gccisr)
2803 bfd_map_over_sections (stdoutput, avr_check_gccisr_done, NULL);