1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010, 2012 Free Software Foundation, Inc.
5 Contributed by Denis Chertykov <denisc@overta.ru>
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
22 Boston, MA 02110-1301, USA. */
25 #include "safe-ctype.h"
27 #include "dw2gencfi.h"
35 int insn_size; /* In words. */
37 unsigned int bin_opcode;
40 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
41 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
43 struct avr_opcodes_s avr_opcodes[] =
45 #include "opcode/avr.h"
46 {NULL, NULL, NULL, 0, 0, 0}
49 const char comment_chars[] = ";";
50 const char line_comment_chars[] = "#";
51 const char line_separator_chars[] = "$";
53 const char *md_shortopts = "m:";
61 /* XXX - devices that don't seem to exist (renamed, replaced with larger
62 ones, or planned but never produced), left here for compatibility. */
64 static struct mcu_type_s mcu_types[] =
66 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
67 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
68 but set to AVR_ISA_AVR25 for some following version
69 of GCC (from 4.3) for backward compatibility. */
70 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
71 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
72 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
73 but set to AVR_ISA_AVR3_ALL for some following version
74 of GCC (from 4.3) for backward compatibility. */
75 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
76 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
77 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
78 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
79 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
80 but set to AVR_ISA_AVR51 for some following version
81 of GCC (from 4.3) for backward compatibility. */
82 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
83 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
84 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
85 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
86 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
87 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
88 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
89 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
90 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
91 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
92 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
93 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
94 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
95 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
96 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
97 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
98 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
99 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
100 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
101 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
102 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
103 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
104 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
105 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
106 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
107 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
108 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
109 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
110 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
111 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
112 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
113 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
114 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
115 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
116 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
117 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
118 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
119 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
120 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
121 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
122 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
123 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
124 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
125 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
126 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
127 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
128 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
129 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
130 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
131 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
132 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
133 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
134 {"ata6289", AVR_ISA_AVR25, bfd_mach_avr25},
135 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
136 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
137 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
138 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
139 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
140 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
141 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
142 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
143 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
144 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
145 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
146 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
147 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
148 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
149 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
150 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
151 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
152 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
153 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
154 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
155 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
156 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
157 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
158 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
159 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
160 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
161 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
162 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
163 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
164 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
165 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
166 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
167 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
168 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
169 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
170 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
171 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
172 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
173 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
174 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
175 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
176 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
177 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
178 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
179 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
180 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
181 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
182 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
183 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
184 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
185 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
186 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
187 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
188 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
189 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
190 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
191 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
192 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
193 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
194 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
195 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
196 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
197 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
198 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
199 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
200 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
201 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
202 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
203 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
204 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
205 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
206 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
207 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
208 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
209 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
210 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
211 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
212 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
213 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
214 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
215 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
216 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
217 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
218 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
219 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
220 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
221 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
222 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
223 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
224 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
225 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
226 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
227 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
228 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
229 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
230 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
231 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
232 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
233 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
234 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
235 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
236 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
237 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
238 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
239 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
240 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
241 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
242 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
243 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
244 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
245 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
246 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
247 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
248 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
249 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
250 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
251 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
252 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
253 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
254 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
255 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
256 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
257 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
258 {"atxmega16x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
259 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
260 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
261 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
262 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
263 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
264 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
265 {"atxmega64a1u",AVR_ISA_XMEGA, bfd_mach_avrxmega5},
266 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
267 {"atxmega128b1", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
268 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
269 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
270 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
271 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
272 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
273 {"atxmega256a3bu",AVR_ISA_XMEGA,bfd_mach_avrxmega6},
274 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
275 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
276 {"atxmega128a1u", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
280 /* Current MCU type. */
281 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
282 static struct mcu_type_s * avr_mcu = & default_mcu;
284 /* AVR target-specific switches. */
287 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
288 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
289 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
292 static struct avr_opt_s avr_opt = { 0, 0, 0 };
294 const char EXP_CHARS[] = "eE";
295 const char FLT_CHARS[] = "dD";
297 static void avr_set_arch (int);
299 /* The target specific pseudo-ops which we support. */
300 const pseudo_typeS md_pseudo_table[] =
302 {"arch", avr_set_arch, 0},
306 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
308 #define EXP_MOD_NAME(i) exp_mod[i].name
309 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
310 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
311 #define HAVE_PM_P(i) exp_mod[i].have_pm
316 bfd_reloc_code_real_type reloc;
317 bfd_reloc_code_real_type neg_reloc;
321 static struct exp_mod_s exp_mod[] =
323 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
324 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
325 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
326 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
327 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
328 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
329 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
330 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
333 /* A union used to store indicies into the exp_mod[] array
334 in a hash table which expects void * data types. */
341 /* Opcode hash table. */
342 static struct hash_control *avr_hash;
344 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
345 static struct hash_control *avr_mod_hash;
347 #define OPTION_MMCU 'm'
350 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
355 struct option md_longopts[] =
357 { "mmcu", required_argument, NULL, OPTION_MMCU },
358 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
359 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
360 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
361 { NULL, no_argument, NULL, 0 }
364 size_t md_longopts_size = sizeof (md_longopts);
366 /* Display nicely formatted list of known MCU names. */
369 show_mcu_list (FILE *stream)
373 fprintf (stream, _("Known MCU names:"));
376 for (i = 0; mcu_types[i].name; i++)
378 int len = strlen (mcu_types[i].name);
383 fprintf (stream, " %s", mcu_types[i].name);
386 fprintf (stream, "\n %s", mcu_types[i].name);
391 fprintf (stream, "\n");
397 while (*s == ' ' || *s == '\t')
402 /* Extract one word from FROM and copy it to TO. */
405 extract_word (char *from, char *to, int limit)
410 /* Drop leading whitespace. */
411 from = skip_space (from);
414 /* Find the op code end. */
415 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
417 to[size++] = *op_end++;
418 if (size + 1 >= limit)
427 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
428 asection *seg ATTRIBUTE_UNUSED)
435 md_show_usage (FILE *stream)
438 _("AVR Assembler options:\n"
439 " -mmcu=[avr-name] select microcontroller variant\n"
440 " [avr-name] can be:\n"
441 " avr1 - classic AVR core without data RAM\n"
442 " avr2 - classic AVR core with up to 8K program memory\n"
443 " avr25 - classic AVR core with up to 8K program memory\n"
444 " plus the MOVW instruction\n"
445 " avr3 - classic AVR core with up to 64K program memory\n"
446 " avr31 - classic AVR core with up to 128K program memory\n"
447 " avr35 - classic AVR core with up to 64K program memory\n"
448 " plus the MOVW instruction\n"
449 " avr4 - enhanced AVR core with up to 8K program memory\n"
450 " avr5 - enhanced AVR core with up to 64K program memory\n"
451 " avr51 - enhanced AVR core with up to 128K program memory\n"
452 " avr6 - enhanced AVR core with up to 256K program memory\n"
453 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
454 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
455 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
456 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
457 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
458 " or immediate microcontroller name.\n"));
460 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
461 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
462 " (default for avr4, avr5)\n"
463 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
464 " (default for avr3, avr5)\n"));
465 show_mcu_list (stream);
469 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
473 input_line_pointer = extract_word (input_line_pointer, str, 20);
474 md_parse_option (OPTION_MMCU, str);
475 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
479 md_parse_option (int c, char *arg)
486 char *s = alloca (strlen (arg) + 1);
493 *t = TOLOWER (*arg1++);
497 for (i = 0; mcu_types[i].name; ++i)
498 if (strcmp (mcu_types[i].name, s) == 0)
501 if (!mcu_types[i].name)
503 show_mcu_list (stderr);
504 as_fatal (_("unknown MCU: %s\n"), arg);
507 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
508 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
509 as .arch ... in the asm output at the same time. */
510 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
511 avr_mcu = &mcu_types[i];
513 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
514 avr_mcu->name, mcu_types[i].name);
517 case OPTION_ALL_OPCODES:
518 avr_opt.all_opcodes = 1;
520 case OPTION_NO_SKIP_BUG:
521 avr_opt.no_skip_bug = 1;
532 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
538 md_atof (int type, char *litP, int *sizeP)
540 return ieee_md_atof (type, litP, sizeP, FALSE);
544 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
545 asection *sec ATTRIBUTE_UNUSED,
546 fragS *fragP ATTRIBUTE_UNUSED)
555 struct avr_opcodes_s *opcode;
557 avr_hash = hash_new ();
559 /* Insert unique names into hash table. This hash table then provides a
560 quick index to the first opcode with a particular name in the opcode
562 for (opcode = avr_opcodes; opcode->name; opcode++)
563 hash_insert (avr_hash, opcode->name, (char *) opcode);
565 avr_mod_hash = hash_new ();
567 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
572 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
575 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
578 /* Resolve STR as a constant expression and return the result.
579 If result greater than MAX then error. */
582 avr_get_constant (char *str, int max)
586 str = skip_space (str);
587 input_line_pointer = str;
590 if (ex.X_op != O_constant)
591 as_bad (_("constant value required"));
593 if (ex.X_add_number > max || ex.X_add_number < 0)
594 as_bad (_("number must be positive and less than %d"), max + 1);
596 return ex.X_add_number;
599 /* Parse for ldd/std offset. */
602 avr_offset_expression (expressionS *exp)
604 char *str = input_line_pointer;
609 str = extract_word (str, op, sizeof (op));
611 input_line_pointer = tmp;
614 /* Warn about expressions that fail to use lo8 (). */
615 if (exp->X_op == O_constant)
617 int x = exp->X_add_number;
619 if (x < -255 || x > 255)
620 as_warn (_("constant out of 8-bit range: %d"), x);
624 /* Parse ordinary expression. */
627 parse_exp (char *s, expressionS *op)
629 input_line_pointer = s;
631 if (op->X_op == O_absent)
632 as_bad (_("missing operand"));
633 return input_line_pointer;
636 /* Parse special expressions (needed for LDI command):
641 where xx is: hh, hi, lo. */
643 static bfd_reloc_code_real_type
644 avr_ldi_expression (expressionS *exp)
646 char *str = input_line_pointer;
650 int linker_stubs_should_be_generated = 0;
654 str = extract_word (str, op, sizeof (op));
660 m.ptr = hash_find (avr_mod_hash, op);
668 str = skip_space (str);
672 bfd_reloc_code_real_type reloc_to_return;
677 if (strncmp ("pm(", str, 3) == 0
678 || strncmp ("gs(",str,3) == 0
679 || strncmp ("-(gs(",str,5) == 0
680 || strncmp ("-(pm(", str, 5) == 0)
688 as_bad (_("illegal expression"));
690 if (str[0] == 'g' || str[2] == 'g')
691 linker_stubs_should_be_generated = 1;
703 if (*str == '-' && *(str + 1) == '(')
710 input_line_pointer = str;
715 if (*input_line_pointer != ')')
717 as_bad (_("`)' required"));
720 input_line_pointer++;
725 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
726 if (linker_stubs_should_be_generated)
728 switch (reloc_to_return)
730 case BFD_RELOC_AVR_LO8_LDI_PM:
731 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
733 case BFD_RELOC_AVR_HI8_LDI_PM:
734 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
738 /* PR 5523: Do not generate a warning here,
739 legitimate code can trigger this case. */
743 return reloc_to_return;
748 input_line_pointer = tmp;
751 /* Warn about expressions that fail to use lo8 (). */
752 if (exp->X_op == O_constant)
754 int x = exp->X_add_number;
756 if (x < -255 || x > 255)
757 as_warn (_("constant out of 8-bit range: %d"), x);
760 return BFD_RELOC_AVR_LDI;
763 /* Parse one instruction operand.
764 Return operand bitmask. Also fixups can be generated. */
767 avr_operand (struct avr_opcodes_s *opcode,
773 unsigned int op_mask = 0;
774 char *str = skip_space (*line);
778 /* Any register operand. */
784 if (*str == 'r' || *str == 'R')
788 str = extract_word (str, r_name, sizeof (r_name));
790 if (ISDIGIT (r_name[1]))
792 if (r_name[2] == '\0')
793 op_mask = r_name[1] - '0';
794 else if (r_name[1] != '0'
795 && ISDIGIT (r_name[2])
796 && r_name[3] == '\0')
797 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
802 op_mask = avr_get_constant (str, 31);
803 str = input_line_pointer;
811 if (op_mask < 16 || op_mask > 23)
812 as_bad (_("register r16-r23 required"));
818 as_bad (_("register number above 15 required"));
824 as_bad (_("even register number required"));
829 if ((op_mask & 1) || op_mask < 24)
830 as_bad (_("register r24, r26, r28 or r30 required"));
831 op_mask = (op_mask - 24) >> 1;
836 as_bad (_("register name or number from 0 to 31 required"));
845 str = skip_space (str + 1);
854 as_bad (_("pointer register (X, Y or Z) required"));
856 str = skip_space (str + 1);
861 as_bad (_("cannot both predecrement and postincrement"));
865 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
866 registers, no predecrement, no postincrement. */
867 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
868 && !(avr_mcu->isa & AVR_ISA_SRAM))
869 as_bad (_("addressing mode not supported"));
875 as_bad (_("can't predecrement"));
877 if (! (*str == 'z' || *str == 'Z'))
878 as_bad (_("pointer register Z required"));
880 str = skip_space (str + 1);
886 for (s = opcode->opcode; *s; ++s)
889 op_mask |= (1 << (15 - (s - opcode->opcode)));
893 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
894 if (!avr_opt.all_opcodes
895 && (op_mask & 0x0001)
896 && !(avr_mcu->isa & AVR_ISA_MOVW))
897 as_bad (_("postincrement not supported"));
902 char c = TOLOWER (*str++);
907 as_bad (_("pointer register (Y or Z) required"));
908 str = skip_space (str);
911 input_line_pointer = str;
912 avr_offset_expression (& op_expr);
913 str = input_line_pointer;
914 fix_new_exp (frag_now, where, 3,
915 &op_expr, FALSE, BFD_RELOC_AVR_6);
921 str = parse_exp (str, &op_expr);
922 fix_new_exp (frag_now, where, opcode->insn_size * 2,
923 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
927 str = parse_exp (str, &op_expr);
928 fix_new_exp (frag_now, where, opcode->insn_size * 2,
929 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
933 str = parse_exp (str, &op_expr);
934 fix_new_exp (frag_now, where, opcode->insn_size * 2,
935 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
939 str = parse_exp (str, &op_expr);
940 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
941 &op_expr, FALSE, BFD_RELOC_16);
946 bfd_reloc_code_real_type r_type;
948 input_line_pointer = str;
949 r_type = avr_ldi_expression (&op_expr);
950 str = input_line_pointer;
951 fix_new_exp (frag_now, where, 3,
952 &op_expr, FALSE, r_type);
960 x = ~avr_get_constant (str, 255);
961 str = input_line_pointer;
962 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
967 input_line_pointer = str;
968 avr_offset_expression (& op_expr);
969 str = input_line_pointer;
970 fix_new_exp (frag_now, where, 3,
971 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
979 x = avr_get_constant (str, 7);
980 str = input_line_pointer;
991 x = avr_get_constant (str, 63);
992 str = input_line_pointer;
993 op_mask |= (x & 0xf) | ((x & 0x30) << 5);
1001 x = avr_get_constant (str, 31);
1002 str = input_line_pointer;
1011 x = avr_get_constant (str, 15);
1012 str = input_line_pointer;
1013 op_mask |= (x << 4);
1021 as_bad (_("unknown constraint `%c'"), *op);
1028 /* Parse instruction operands.
1029 Return binary opcode. */
1032 avr_operands (struct avr_opcodes_s *opcode, char **line)
1034 char *op = opcode->constraints;
1035 unsigned int bin = opcode->bin_opcode;
1036 char *frag = frag_more (opcode->insn_size * 2);
1038 int where = frag - frag_now->fr_literal;
1039 static unsigned int prev = 0; /* Previous opcode. */
1041 /* Opcode have operands. */
1044 unsigned int reg1 = 0;
1045 unsigned int reg2 = 0;
1046 int reg1_present = 0;
1047 int reg2_present = 0;
1049 /* Parse first operand. */
1050 if (REGISTER_P (*op))
1052 reg1 = avr_operand (opcode, where, op, &str);
1055 /* Parse second operand. */
1068 if (REGISTER_P (*op))
1071 str = skip_space (str);
1073 as_bad (_("`,' required"));
1074 str = skip_space (str);
1076 reg2 = avr_operand (opcode, where, op, &str);
1079 if (reg1_present && reg2_present)
1080 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1081 else if (reg2_present)
1089 /* Detect undefined combinations (like ld r31,Z+). */
1090 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1091 as_warn (_("undefined combination of operands"));
1093 if (opcode->insn_size == 2)
1095 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1096 (AVR core bug, fixed in the newer devices). */
1097 if (!(avr_opt.no_skip_bug ||
1098 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1099 && AVR_SKIP_P (prev))
1100 as_warn (_("skipping two-word instruction"));
1102 bfd_putl32 ((bfd_vma) bin, frag);
1105 bfd_putl16 ((bfd_vma) bin, frag);
1112 /* GAS will call this function for each section at the end of the assembly,
1113 to permit the CPU backend to adjust the alignment of a section. */
1116 md_section_align (asection *seg, valueT addr)
1118 int align = bfd_get_section_alignment (stdoutput, seg);
1119 return ((addr + (1 << align) - 1) & (-1 << align));
1122 /* If you define this macro, it should return the offset between the
1123 address of a PC relative fixup and the position from which the PC
1124 relative adjustment should be made. On many processors, the base
1125 of a PC relative instruction is the next instruction, so this
1126 macro would return the length of an instruction. */
1129 md_pcrel_from_section (fixS *fixp, segT sec)
1131 if (fixp->fx_addsy != (symbolS *) NULL
1132 && (!S_IS_DEFINED (fixp->fx_addsy)
1133 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1136 return fixp->fx_frag->fr_address + fixp->fx_where;
1139 /* GAS will call this for each fixup. It should store the correct
1140 value in the object file. */
1143 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1145 unsigned char *where;
1149 if (fixP->fx_addsy == (symbolS *) NULL)
1152 else if (fixP->fx_pcrel)
1154 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1156 if (s == seg || s == absolute_section)
1158 value += S_GET_VALUE (fixP->fx_addsy);
1163 /* We don't actually support subtracting a symbol. */
1164 if (fixP->fx_subsy != (symbolS *) NULL)
1165 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1167 switch (fixP->fx_r_type)
1170 fixP->fx_no_overflow = 1;
1172 case BFD_RELOC_AVR_7_PCREL:
1173 case BFD_RELOC_AVR_13_PCREL:
1176 case BFD_RELOC_AVR_CALL:
1182 /* Fetch the instruction, insert the fully resolved operand
1183 value, and stuff the instruction back again. */
1184 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1185 insn = bfd_getl16 (where);
1187 switch (fixP->fx_r_type)
1189 case BFD_RELOC_AVR_7_PCREL:
1191 as_bad_where (fixP->fx_file, fixP->fx_line,
1192 _("odd address operand: %ld"), value);
1194 /* Instruction addresses are always right-shifted by 1. */
1196 --value; /* Correct PC. */
1198 if (value < -64 || value > 63)
1199 as_bad_where (fixP->fx_file, fixP->fx_line,
1200 _("operand out of range: %ld"), value);
1201 value = (value << 3) & 0x3f8;
1202 bfd_putl16 ((bfd_vma) (value | insn), where);
1205 case BFD_RELOC_AVR_13_PCREL:
1207 as_bad_where (fixP->fx_file, fixP->fx_line,
1208 _("odd address operand: %ld"), value);
1210 /* Instruction addresses are always right-shifted by 1. */
1212 --value; /* Correct PC. */
1214 if (value < -2048 || value > 2047)
1216 /* No wrap for devices with >8K of program memory. */
1217 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1218 as_bad_where (fixP->fx_file, fixP->fx_line,
1219 _("operand out of range: %ld"), value);
1223 bfd_putl16 ((bfd_vma) (value | insn), where);
1227 bfd_putl32 ((bfd_vma) value, where);
1231 bfd_putl16 ((bfd_vma) value, where);
1235 if (value > 255 || value < -128)
1236 as_warn_where (fixP->fx_file, fixP->fx_line,
1237 _("operand out of range: %ld"), value);
1241 case BFD_RELOC_AVR_16_PM:
1242 bfd_putl16 ((bfd_vma) (value >> 1), where);
1245 case BFD_RELOC_AVR_LDI:
1247 as_bad_where (fixP->fx_file, fixP->fx_line,
1248 _("operand out of range: %ld"), value);
1249 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1252 case BFD_RELOC_AVR_6:
1253 if ((value > 63) || (value < 0))
1254 as_bad_where (fixP->fx_file, fixP->fx_line,
1255 _("operand out of range: %ld"), value);
1256 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) | ((value & (1 << 5)) << 8)), where);
1259 case BFD_RELOC_AVR_6_ADIW:
1260 if ((value > 63) || (value < 0))
1261 as_bad_where (fixP->fx_file, fixP->fx_line,
1262 _("operand out of range: %ld"), value);
1263 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1266 case BFD_RELOC_AVR_LO8_LDI:
1267 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1270 case BFD_RELOC_AVR_HI8_LDI:
1271 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1274 case BFD_RELOC_AVR_MS8_LDI:
1275 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1278 case BFD_RELOC_AVR_HH8_LDI:
1279 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1282 case BFD_RELOC_AVR_LO8_LDI_NEG:
1283 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1286 case BFD_RELOC_AVR_HI8_LDI_NEG:
1287 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1290 case BFD_RELOC_AVR_MS8_LDI_NEG:
1291 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1294 case BFD_RELOC_AVR_HH8_LDI_NEG:
1295 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1298 case BFD_RELOC_AVR_LO8_LDI_PM:
1299 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1302 case BFD_RELOC_AVR_HI8_LDI_PM:
1303 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1306 case BFD_RELOC_AVR_HH8_LDI_PM:
1307 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1310 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1311 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1314 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1315 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1318 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1319 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1322 case BFD_RELOC_AVR_CALL:
1326 x = bfd_getl16 (where);
1328 as_bad_where (fixP->fx_file, fixP->fx_line,
1329 _("odd address operand: %ld"), value);
1331 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1332 bfd_putl16 ((bfd_vma) x, where);
1333 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1337 case BFD_RELOC_AVR_8_LO:
1338 *where = 0xff & value;
1341 case BFD_RELOC_AVR_8_HI:
1342 *where = 0xff & (value >> 8);
1345 case BFD_RELOC_AVR_8_HLO:
1346 *where = 0xff & (value >> 16);
1350 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1351 fixP->fx_line, fixP->fx_r_type);
1357 switch ((int) fixP->fx_r_type)
1359 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1360 case -BFD_RELOC_AVR_HI8_LDI:
1361 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1362 case -BFD_RELOC_AVR_LO8_LDI:
1363 as_bad_where (fixP->fx_file, fixP->fx_line,
1364 _("only constant expression allowed"));
1373 /* GAS will call this to generate a reloc, passing the resulting reloc
1374 to `bfd_install_relocation'. This currently works poorly, as
1375 `bfd_install_relocation' often does the wrong thing, and instances of
1376 `tc_gen_reloc' have been written to work around the problems, which
1377 in turns makes it difficult to fix `bfd_install_relocation'. */
1379 /* If while processing a fixup, a reloc really needs to be created
1380 then it is done here. */
1383 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1388 if (fixp->fx_addsy && fixp->fx_subsy)
1392 if ((S_GET_SEGMENT (fixp->fx_addsy) != S_GET_SEGMENT (fixp->fx_subsy))
1393 || S_GET_SEGMENT (fixp->fx_addsy) == undefined_section)
1395 as_bad_where (fixp->fx_file, fixp->fx_line,
1396 "Difference of symbols in different sections is not supported");
1400 /* We are dealing with two symbols defined in the same section.
1401 Let us fix-up them here. */
1402 value += S_GET_VALUE (fixp->fx_addsy);
1403 value -= S_GET_VALUE (fixp->fx_subsy);
1405 /* When fx_addsy and fx_subsy both are zero, md_apply_fix
1406 only takes it's second operands for the fixup value. */
1407 fixp->fx_addsy = NULL;
1408 fixp->fx_subsy = NULL;
1409 md_apply_fix (fixp, (valueT *) &value, NULL);
1414 reloc = xmalloc (sizeof (arelent));
1416 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
1417 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1419 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1420 reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type);
1421 if (reloc->howto == (reloc_howto_type *) NULL)
1423 as_bad_where (fixp->fx_file, fixp->fx_line,
1424 _("reloc %d not supported by object file format"),
1425 (int) fixp->fx_r_type);
1429 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1430 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1431 reloc->address = fixp->fx_offset;
1433 reloc->addend = fixp->fx_offset;
1439 md_assemble (char *str)
1441 struct avr_opcodes_s *opcode;
1444 str = skip_space (extract_word (str, op, sizeof (op)));
1447 as_bad (_("can't find opcode "));
1449 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1453 as_bad (_("unknown opcode `%s'"), op);
1457 /* Special case for opcodes with optional operands (lpm, elpm) -
1458 version with operands exists in avr_opcodes[] in the next entry. */
1460 if (*str && *opcode->constraints == '?')
1463 if (!avr_opt.all_opcodes && (opcode->isa & avr_mcu->isa) != opcode->isa)
1464 as_bad (_("illegal opcode %s for mcu %s"), opcode->name, avr_mcu->name);
1466 dwarf2_emit_insn (0);
1468 /* We used to set input_line_pointer to the result of get_operands,
1469 but that is wrong. Our caller assumes we don't change it. */
1471 char *t = input_line_pointer;
1473 avr_operands (opcode, &str);
1474 if (*skip_space (str))
1475 as_bad (_("garbage at end of line"));
1476 input_line_pointer = t;
1482 /* Name of the expression modifier allowed with .byte, .word, etc. */
1485 /* Only allowed with n bytes of data. */
1488 /* Associated RELOC. */
1489 bfd_reloc_code_real_type reloc;
1491 /* Part of the error message. */
1495 static const exp_mod_data_t exp_mod_data[] =
1497 /* Default, must be first. */
1498 { "", 0, BFD_RELOC_16, "" },
1499 /* Divides by 2 to get word address. Generate Stub. */
1500 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1501 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1502 /* The following are used together with avr-gcc's __memx address space
1503 in order to initialize a 24-bit pointer variable with a 24-bit address.
1504 For address in flash, hlo8 will contain the flash segment if the
1505 symbol is located in flash. If the symbol is located in RAM; hlo8
1506 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1507 addresses linearize address space. */
1508 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1509 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
1510 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1511 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
1513 { NULL, 0, 0, NULL }
1516 /* Data to pass between `avr_parse_cons_expression' and `avr_cons_fix_new'. */
1517 static const exp_mod_data_t *pexp_mod_data = &exp_mod_data[0];
1519 /* Parse special CONS expression: pm (expression) or alternatively
1520 gs (expression). These are used for addressing program memory. Moreover,
1521 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1524 avr_parse_cons_expression (expressionS *exp, int nbytes)
1526 const exp_mod_data_t *pexp = &exp_mod_data[0];
1529 pexp_mod_data = pexp;
1531 tmp = input_line_pointer = skip_space (input_line_pointer);
1533 /* The first entry of exp_mod_data[] contains an entry if no
1534 expression modifier is present. Skip it. */
1536 for (pexp++; pexp->name; pexp++)
1538 int len = strlen (pexp->name);
1540 if (nbytes == pexp->nbytes
1541 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
1543 input_line_pointer = skip_space (input_line_pointer + len);
1545 if (*input_line_pointer == '(')
1547 input_line_pointer = skip_space (input_line_pointer + 1);
1548 pexp_mod_data = pexp;
1551 if (*input_line_pointer == ')')
1552 ++input_line_pointer;
1555 as_bad (_("`)' required"));
1556 pexp_mod_data = &exp_mod_data[0];
1562 input_line_pointer = tmp;
1572 avr_cons_fix_new (fragS *frag,
1579 switch (pexp_mod_data->reloc)
1583 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
1584 else if (nbytes == 2)
1585 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
1586 else if (nbytes == 4)
1587 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
1592 case BFD_RELOC_AVR_16_PM:
1593 case BFD_RELOC_AVR_8_LO:
1594 case BFD_RELOC_AVR_8_HI:
1595 case BFD_RELOC_AVR_8_HLO:
1596 if (nbytes == pexp_mod_data->nbytes)
1597 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
1604 as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
1606 pexp_mod_data = &exp_mod_data[0];
1610 tc_cfi_frame_initial_instructions (void)
1612 /* AVR6 pushes 3 bytes for calls. */
1613 int return_size = (avr_mcu->mach == bfd_mach_avr6 ? 3 : 2);
1615 /* The CFA is the caller's stack location before the call insn. */
1616 /* Note that the stack pointer is dwarf register number 32. */
1617 cfi_add_CFA_def_cfa (32, return_size);
1619 /* Note that AVR consistently uses post-decrement, which means that things
1620 do not line up the same way as for targers that use pre-decrement. */
1621 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);