1 /* tc-avr.c -- Assembler code for the ATMEL AVR
3 Copyright (C) 1999-2017 Free Software Foundation, Inc.
4 Contributed by Denis Chertykov <denisc@overta.ru>
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 #include "safe-ctype.h"
26 #include "dwarf2dbg.h"
27 #include "dw2gencfi.h"
29 #include "elf32-avr.h"
31 /* For building a linked list of AVR_PROPERTY_RECORD structures. */
32 struct avr_property_record_link
34 struct avr_property_record record;
35 struct avr_property_record_link *next;
41 const char * constraints;
43 int insn_size; /* In words. */
45 unsigned int bin_opcode;
48 #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \
49 {#NAME, CONSTR, OPCODE, SIZE, ISA, BIN},
51 struct avr_opcodes_s avr_opcodes[] =
53 #include "opcode/avr.h"
54 {NULL, NULL, NULL, 0, 0, 0}
57 const char comment_chars[] = ";";
58 const char line_comment_chars[] = "#";
59 const char line_separator_chars[] = "$";
61 const char *md_shortopts = "m:";
69 /* XXX - devices that don't seem to exist (renamed, replaced with larger
70 ones, or planned but never produced), left here for compatibility. */
72 static struct mcu_type_s mcu_types[] =
74 {"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
75 /* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
76 but set to AVR_ISA_AVR25 for some following version
77 of GCC (from 4.3) for backward compatibility. */
78 {"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
79 {"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
80 /* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
81 but set to AVR_ISA_AVR3_ALL for some following version
82 of GCC (from 4.3) for backward compatibility. */
83 {"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
84 {"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
85 {"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
86 {"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
87 /* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
88 but set to AVR_ISA_AVR51 for some following version
89 of GCC (from 4.3) for backward compatibility. */
90 {"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
91 {"avr51", AVR_ISA_AVR51, bfd_mach_avr51},
92 {"avr6", AVR_ISA_AVR6, bfd_mach_avr6},
93 {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1},
94 {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
95 {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3},
96 {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
97 {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
98 {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
99 {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
100 {"avrtiny", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
101 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1},
102 {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1},
103 {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1},
104 {"attiny15", AVR_ISA_AVR1, bfd_mach_avr1},
105 {"attiny28", AVR_ISA_AVR1, bfd_mach_avr1},
106 {"at90s2313", AVR_ISA_AVR2, bfd_mach_avr2},
107 {"at90s2323", AVR_ISA_AVR2, bfd_mach_avr2},
108 {"at90s2333", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 4433 */
109 {"at90s2343", AVR_ISA_AVR2, bfd_mach_avr2},
110 {"attiny22", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 2343 */
111 {"attiny26", AVR_ISA_2xxe, bfd_mach_avr2},
112 {"at90s4414", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8515 */
113 {"at90s4433", AVR_ISA_AVR2, bfd_mach_avr2},
114 {"at90s4434", AVR_ISA_AVR2, bfd_mach_avr2}, /* XXX -> 8535 */
115 {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2},
116 {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2},
117 {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2},
118 {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25},
119 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25},
120 {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25},
121 {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25},
122 {"attiny2313a",AVR_ISA_AVR25, bfd_mach_avr25},
123 {"attiny24", AVR_ISA_AVR25, bfd_mach_avr25},
124 {"attiny24a", AVR_ISA_AVR25, bfd_mach_avr25},
125 {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25},
126 {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25},
127 {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25},
128 {"attiny84", AVR_ISA_AVR25, bfd_mach_avr25},
129 {"attiny84a", AVR_ISA_AVR25, bfd_mach_avr25},
130 {"attiny25", AVR_ISA_AVR25, bfd_mach_avr25},
131 {"attiny45", AVR_ISA_AVR25, bfd_mach_avr25},
132 {"attiny85", AVR_ISA_AVR25, bfd_mach_avr25},
133 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25},
134 {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25},
135 {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25},
136 {"attiny461a", AVR_ISA_AVR25, bfd_mach_avr25},
137 {"attiny861", AVR_ISA_AVR25, bfd_mach_avr25},
138 {"attiny861a", AVR_ISA_AVR25, bfd_mach_avr25},
139 {"attiny87", AVR_ISA_AVR25, bfd_mach_avr25},
140 {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25},
141 {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25},
142 {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25},
143 {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25},
144 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25},
145 {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3},
146 {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3},
147 {"atmega103", AVR_ISA_AVR31, bfd_mach_avr31},
148 {"at43usb320", AVR_ISA_AVR31, bfd_mach_avr31},
149 {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35},
150 {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35},
151 {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35},
152 {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35},
153 {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35},
154 {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35},
155 {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35},
156 {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35},
157 {"atmega8", AVR_ISA_M8, bfd_mach_avr4},
158 {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4},
159 {"atmega8a", AVR_ISA_M8, bfd_mach_avr4},
160 {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4},
161 {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4},
162 {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4},
163 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4},
164 {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4},
165 {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4},
166 {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4},
167 {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4},
168 {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4},
169 {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4},
170 {"atmega8515", AVR_ISA_M8, bfd_mach_avr4},
171 {"atmega8535", AVR_ISA_M8, bfd_mach_avr4},
172 {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4},
173 {"at90pwm1", AVR_ISA_AVR4, bfd_mach_avr4},
174 {"at90pwm2", AVR_ISA_AVR4, bfd_mach_avr4},
175 {"at90pwm2b", AVR_ISA_AVR4, bfd_mach_avr4},
176 {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4},
177 {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4},
178 {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4},
179 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
180 {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5},
181 {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5},
182 {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5},
183 {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5},
184 {"atmega161", AVR_ISA_M161, bfd_mach_avr5},
185 {"atmega162", AVR_ISA_AVR5, bfd_mach_avr5},
186 {"atmega163", AVR_ISA_M161, bfd_mach_avr5},
187 {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5},
188 {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5},
189 {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5},
190 {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5},
191 {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5},
192 {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5},
193 {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5},
194 {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5},
195 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5},
196 {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5},
197 {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5},
198 {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5},
199 {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5},
200 {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5},
201 {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5},
202 {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5},
203 {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5},
204 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5},
205 {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5},
206 {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5},
207 {"atmega324pa",AVR_ISA_AVR5, bfd_mach_avr5},
208 {"atmega325", AVR_ISA_AVR5, bfd_mach_avr5},
209 {"atmega325a", AVR_ISA_AVR5, bfd_mach_avr5},
210 {"atmega325p", AVR_ISA_AVR5, bfd_mach_avr5},
211 {"atmega325pa",AVR_ISA_AVR5, bfd_mach_avr5},
212 {"atmega3250", AVR_ISA_AVR5, bfd_mach_avr5},
213 {"atmega3250a",AVR_ISA_AVR5, bfd_mach_avr5},
214 {"atmega3250p",AVR_ISA_AVR5, bfd_mach_avr5},
215 {"atmega3250pa",AVR_ISA_AVR5, bfd_mach_avr5},
216 {"atmega328", AVR_ISA_AVR5, bfd_mach_avr5},
217 {"atmega328p", AVR_ISA_AVR5, bfd_mach_avr5},
218 {"atmega329", AVR_ISA_AVR5, bfd_mach_avr5},
219 {"atmega329a", AVR_ISA_AVR5, bfd_mach_avr5},
220 {"atmega329p", AVR_ISA_AVR5, bfd_mach_avr5},
221 {"atmega329pa",AVR_ISA_AVR5, bfd_mach_avr5},
222 {"atmega3290", AVR_ISA_AVR5, bfd_mach_avr5},
223 {"atmega3290a",AVR_ISA_AVR5, bfd_mach_avr5},
224 {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5},
225 {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5},
226 {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5},
227 {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5},
228 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
229 {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5},
230 {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5},
231 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5},
232 {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5},
233 {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5},
234 {"atmega644p", AVR_ISA_AVR5, bfd_mach_avr5},
235 {"atmega644pa",AVR_ISA_AVR5, bfd_mach_avr5},
236 {"atmega645", AVR_ISA_AVR5, bfd_mach_avr5},
237 {"atmega645a", AVR_ISA_AVR5, bfd_mach_avr5},
238 {"atmega645p", AVR_ISA_AVR5, bfd_mach_avr5},
239 {"atmega649", AVR_ISA_AVR5, bfd_mach_avr5},
240 {"atmega649a", AVR_ISA_AVR5, bfd_mach_avr5},
241 {"atmega649p", AVR_ISA_AVR5, bfd_mach_avr5},
242 {"atmega6450", AVR_ISA_AVR5, bfd_mach_avr5},
243 {"atmega6450a",AVR_ISA_AVR5, bfd_mach_avr5},
244 {"atmega6450p",AVR_ISA_AVR5, bfd_mach_avr5},
245 {"atmega6490", AVR_ISA_AVR5, bfd_mach_avr5},
246 {"atmega6490a",AVR_ISA_AVR5, bfd_mach_avr5},
247 {"atmega6490p",AVR_ISA_AVR5, bfd_mach_avr5},
248 {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
249 {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5},
250 {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5},
251 {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5},
252 {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5},
253 {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
254 {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5},
255 {"atmega32hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5},
256 {"atmega64hve",AVR_ISA_AVR5, bfd_mach_avr5},
257 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5},
258 {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5},
259 {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5},
260 {"at90pwm216", AVR_ISA_AVR5, bfd_mach_avr5},
261 {"at90pwm316", AVR_ISA_AVR5, bfd_mach_avr5},
262 {"atmega32c1", AVR_ISA_AVR5, bfd_mach_avr5},
263 {"atmega64c1", AVR_ISA_AVR5, bfd_mach_avr5},
264 {"atmega16m1", AVR_ISA_AVR5, bfd_mach_avr5},
265 {"atmega32m1", AVR_ISA_AVR5, bfd_mach_avr5},
266 {"atmega64m1", AVR_ISA_AVR5, bfd_mach_avr5},
267 {"atmega16u4", AVR_ISA_AVR5, bfd_mach_avr5},
268 {"atmega32u4", AVR_ISA_AVR5, bfd_mach_avr5},
269 {"atmega32u6", AVR_ISA_AVR5, bfd_mach_avr5},
270 {"at90usb646", AVR_ISA_AVR5, bfd_mach_avr5},
271 {"at90usb647", AVR_ISA_AVR5, bfd_mach_avr5},
272 {"at90scr100", AVR_ISA_AVR5, bfd_mach_avr5},
273 {"at94k", AVR_ISA_94K, bfd_mach_avr5},
274 {"m3000", AVR_ISA_AVR5, bfd_mach_avr5},
275 {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51},
276 {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51},
277 {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51},
278 {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51},
279 {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51},
280 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51},
281 {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51},
282 {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
283 {"atmega1284rfr2",AVR_ISA_AVR51, bfd_mach_avr51},
284 {"at90can128", AVR_ISA_AVR51, bfd_mach_avr51},
285 {"at90usb1286",AVR_ISA_AVR51, bfd_mach_avr51},
286 {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51},
287 {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6},
288 {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6},
289 {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
290 {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6},
291 {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
292 {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
293 {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
294 {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
295 {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
296 {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
297 {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2},
298 {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
299 {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
300 {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
301 {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
302 {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2},
303 {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
304 {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
305 {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
306 {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
307 {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
308 {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4},
309 {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
310 {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4},
311 {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5},
312 {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5},
313 {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
314 {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
315 {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
316 {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
317 {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
318 {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
319 {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
320 {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
321 {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
322 {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
323 {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
324 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
325 {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
326 {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6},
327 {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6},
328 {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
329 {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
330 {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6},
331 {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6},
332 {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7},
333 {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
334 {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7},
335 {"attiny4", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
336 {"attiny5", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
337 {"attiny9", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
338 {"attiny10", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
339 {"attiny20", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
340 {"attiny40", AVR_ISA_AVRTINY, bfd_mach_avrtiny},
345 /* Current MCU type. */
346 static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2};
347 static struct mcu_type_s specified_mcu;
348 static struct mcu_type_s * avr_mcu = & default_mcu;
350 /* AVR target-specific switches. */
353 int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */
354 int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */
355 int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */
356 int no_link_relax; /* -mno-link-relax / -mlink-relax: generate (or not)
357 relocations for linker relaxation. */
360 static struct avr_opt_s avr_opt = { 0, 0, 0, 0 };
362 const char EXP_CHARS[] = "eE";
363 const char FLT_CHARS[] = "dD";
365 static void avr_set_arch (int);
367 /* The target specific pseudo-ops which we support. */
368 const pseudo_typeS md_pseudo_table[] =
370 {"arch", avr_set_arch, 0},
374 #define LDI_IMMEDIATE(x) (((x) & 0xf) | (((x) << 4) & 0xf00))
376 #define EXP_MOD_NAME(i) exp_mod[i].name
377 #define EXP_MOD_RELOC(i) exp_mod[i].reloc
378 #define EXP_MOD_NEG_RELOC(i) exp_mod[i].neg_reloc
379 #define HAVE_PM_P(i) exp_mod[i].have_pm
384 bfd_reloc_code_real_type reloc;
385 bfd_reloc_code_real_type neg_reloc;
389 static struct exp_mod_s exp_mod[] =
391 {"hh8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 1},
392 {"pm_hh8", BFD_RELOC_AVR_HH8_LDI_PM, BFD_RELOC_AVR_HH8_LDI_PM_NEG, 0},
393 {"hi8", BFD_RELOC_AVR_HI8_LDI, BFD_RELOC_AVR_HI8_LDI_NEG, 1},
394 {"pm_hi8", BFD_RELOC_AVR_HI8_LDI_PM, BFD_RELOC_AVR_HI8_LDI_PM_NEG, 0},
395 {"lo8", BFD_RELOC_AVR_LO8_LDI, BFD_RELOC_AVR_LO8_LDI_NEG, 1},
396 {"pm_lo8", BFD_RELOC_AVR_LO8_LDI_PM, BFD_RELOC_AVR_LO8_LDI_PM_NEG, 0},
397 {"hlo8", BFD_RELOC_AVR_HH8_LDI, BFD_RELOC_AVR_HH8_LDI_NEG, 0},
398 {"hhi8", BFD_RELOC_AVR_MS8_LDI, BFD_RELOC_AVR_MS8_LDI_NEG, 0},
401 /* A union used to store indices into the exp_mod[] array
402 in a hash table which expects void * data types. */
409 /* Opcode hash table. */
410 static struct hash_control *avr_hash;
412 /* Reloc modifiers hash control (hh8,hi8,lo8,pm_xx). */
413 static struct hash_control *avr_mod_hash;
415 #define OPTION_MMCU 'm'
418 OPTION_ALL_OPCODES = OPTION_MD_BASE + 1,
426 struct option md_longopts[] =
428 { "mmcu", required_argument, NULL, OPTION_MMCU },
429 { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES },
430 { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG },
431 { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP },
432 { "mrmw", no_argument, NULL, OPTION_ISA_RMW },
433 { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX },
434 { "mno-link-relax", no_argument, NULL, OPTION_NO_LINK_RELAX },
435 { NULL, no_argument, NULL, 0 }
438 size_t md_longopts_size = sizeof (md_longopts);
440 /* Display nicely formatted list of known MCU names. */
443 show_mcu_list (FILE *stream)
447 fprintf (stream, _("Known MCU names:"));
450 for (i = 0; mcu_types[i].name; i++)
452 int len = strlen (mcu_types[i].name);
457 fprintf (stream, " %s", mcu_types[i].name);
460 fprintf (stream, "\n %s", mcu_types[i].name);
465 fprintf (stream, "\n");
471 while (*s == ' ' || *s == '\t')
476 /* Extract one word from FROM and copy it to TO. */
479 extract_word (char *from, char *to, int limit)
484 /* Drop leading whitespace. */
485 from = skip_space (from);
488 /* Find the op code end. */
489 for (op_end = from; *op_end != 0 && is_part_of_name (*op_end);)
491 to[size++] = *op_end++;
492 if (size + 1 >= limit)
501 md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED,
502 asection *seg ATTRIBUTE_UNUSED)
509 md_show_usage (FILE *stream)
512 _("AVR Assembler options:\n"
513 " -mmcu=[avr-name] select microcontroller variant\n"
514 " [avr-name] can be:\n"
515 " avr1 - classic AVR core without data RAM\n"
516 " avr2 - classic AVR core with up to 8K program memory\n"
517 " avr25 - classic AVR core with up to 8K program memory\n"
518 " plus the MOVW instruction\n"
519 " avr3 - classic AVR core with up to 64K program memory\n"
520 " avr31 - classic AVR core with up to 128K program memory\n"
521 " avr35 - classic AVR core with up to 64K program memory\n"
522 " plus the MOVW instruction\n"
523 " avr4 - enhanced AVR core with up to 8K program memory\n"
524 " avr5 - enhanced AVR core with up to 64K program memory\n"
525 " avr51 - enhanced AVR core with up to 128K program memory\n"
526 " avr6 - enhanced AVR core with up to 256K program memory\n"
527 " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n"
528 " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n"
529 " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n"
530 " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n"
531 " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n"
532 " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n"
533 " avrtiny - AVR Tiny core with 16 gp registers\n"));
535 _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n"
536 " -mno-skip-bug disable warnings for skipping two-word instructions\n"
537 " (default for avr4, avr5)\n"
538 " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n"
539 " (default for avr3, avr5)\n"
540 " -mrmw accept Read-Modify-Write instructions\n"
541 " -mlink-relax generate relocations for linker relaxation (default)\n"
542 " -mno-link-relax don't generate relocations for linker relaxation.\n"
544 show_mcu_list (stream);
548 avr_set_arch (int dummy ATTRIBUTE_UNUSED)
552 input_line_pointer = extract_word (input_line_pointer, str, 20);
553 md_parse_option (OPTION_MMCU, str);
554 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
558 md_parse_option (int c, const char *arg)
566 for (i = 0; mcu_types[i].name; ++i)
567 if (strcasecmp (mcu_types[i].name, arg) == 0)
570 if (!mcu_types[i].name)
572 show_mcu_list (stderr);
573 as_fatal (_("unknown MCU: %s\n"), arg);
576 /* It is OK to redefine mcu type within the same avr[1-5] bfd machine
577 type - this for allows passing -mmcu=... via gcc ASM_SPEC as well
578 as .arch ... in the asm output at the same time. */
579 if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach)
581 specified_mcu.name = mcu_types[i].name;
582 specified_mcu.isa |= mcu_types[i].isa;
583 specified_mcu.mach = mcu_types[i].mach;
584 avr_mcu = &specified_mcu;
587 as_fatal (_("redefinition of mcu type `%s' to `%s'"),
588 avr_mcu->name, mcu_types[i].name);
591 case OPTION_ALL_OPCODES:
592 avr_opt.all_opcodes = 1;
594 case OPTION_NO_SKIP_BUG:
595 avr_opt.no_skip_bug = 1;
601 specified_mcu.isa |= AVR_ISA_RMW;
603 case OPTION_LINK_RELAX:
604 avr_opt.no_link_relax = 0;
606 case OPTION_NO_LINK_RELAX:
607 avr_opt.no_link_relax = 1;
615 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
621 md_atof (int type, char *litP, int *sizeP)
623 return ieee_md_atof (type, litP, sizeP, FALSE);
627 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
628 asection *sec ATTRIBUTE_UNUSED,
629 fragS *fragP ATTRIBUTE_UNUSED)
638 struct avr_opcodes_s *opcode;
640 avr_hash = hash_new ();
642 /* Insert unique names into hash table. This hash table then provides a
643 quick index to the first opcode with a particular name in the opcode
645 for (opcode = avr_opcodes; opcode->name; opcode++)
646 hash_insert (avr_hash, opcode->name, (char *) opcode);
648 avr_mod_hash = hash_new ();
650 for (i = 0; i < ARRAY_SIZE (exp_mod); ++i)
655 hash_insert (avr_mod_hash, EXP_MOD_NAME (i), m.ptr);
658 bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach);
659 linkrelax = !avr_opt.no_link_relax;
662 /* Resolve STR as a constant expression and return the result.
663 If result greater than MAX then error. */
666 avr_get_constant (char *str, int max)
670 str = skip_space (str);
671 input_line_pointer = str;
674 if (ex.X_op != O_constant)
675 as_bad (_("constant value required"));
677 if (ex.X_add_number > max || ex.X_add_number < 0)
678 as_bad (_("number must be positive and less than %d"), max + 1);
680 return ex.X_add_number;
683 /* Parse for ldd/std offset. */
686 avr_offset_expression (expressionS *exp)
688 char *str = input_line_pointer;
693 str = extract_word (str, op, sizeof (op));
695 input_line_pointer = tmp;
698 /* Warn about expressions that fail to use lo8 (). */
699 if (exp->X_op == O_constant)
701 int x = exp->X_add_number;
703 if (x < -255 || x > 255)
704 as_warn (_("constant out of 8-bit range: %d"), x);
708 /* Parse ordinary expression. */
711 parse_exp (char *s, expressionS *op)
713 input_line_pointer = s;
715 if (op->X_op == O_absent)
716 as_bad (_("missing operand"));
717 return input_line_pointer;
720 /* Parse special expressions (needed for LDI command):
725 where xx is: hh, hi, lo. */
727 static bfd_reloc_code_real_type
728 avr_ldi_expression (expressionS *exp)
730 char *str = input_line_pointer;
734 int linker_stubs_should_be_generated = 0;
738 str = extract_word (str, op, sizeof (op));
744 m.ptr = hash_find (avr_mod_hash, op);
752 str = skip_space (str);
756 bfd_reloc_code_real_type reloc_to_return;
761 if (strncmp ("pm(", str, 3) == 0
762 || strncmp ("gs(",str,3) == 0
763 || strncmp ("-(gs(",str,5) == 0
764 || strncmp ("-(pm(", str, 5) == 0)
772 as_bad (_("illegal expression"));
774 if (str[0] == 'g' || str[2] == 'g')
775 linker_stubs_should_be_generated = 1;
787 if (*str == '-' && *(str + 1) == '(')
794 input_line_pointer = str;
799 if (*input_line_pointer != ')')
801 as_bad (_("`)' required"));
804 input_line_pointer++;
809 neg_p ? EXP_MOD_NEG_RELOC (mod) : EXP_MOD_RELOC (mod);
810 if (linker_stubs_should_be_generated)
812 switch (reloc_to_return)
814 case BFD_RELOC_AVR_LO8_LDI_PM:
815 reloc_to_return = BFD_RELOC_AVR_LO8_LDI_GS;
817 case BFD_RELOC_AVR_HI8_LDI_PM:
818 reloc_to_return = BFD_RELOC_AVR_HI8_LDI_GS;
822 /* PR 5523: Do not generate a warning here,
823 legitimate code can trigger this case. */
827 return reloc_to_return;
832 input_line_pointer = tmp;
835 /* Warn about expressions that fail to use lo8 (). */
836 if (exp->X_op == O_constant)
838 int x = exp->X_add_number;
840 if (x < -255 || x > 255)
841 as_warn (_("constant out of 8-bit range: %d"), x);
844 return BFD_RELOC_AVR_LDI;
847 /* Parse one instruction operand.
848 Return operand bitmask. Also fixups can be generated. */
851 avr_operand (struct avr_opcodes_s *opcode,
857 unsigned int op_mask = 0;
858 char *str = skip_space (*line);
862 /* Any register operand. */
869 char * old_str = str;
873 str = extract_word (str, r_name, sizeof (r_name));
874 for (lower = r_name; *lower; ++lower)
876 if (*lower >= 'A' && *lower <= 'Z')
880 if (r_name[0] == 'r' && ISDIGIT (r_name[1]) && r_name[2] == 0)
881 /* Single-digit register number, ie r0-r9. */
882 op_mask = r_name[1] - '0';
883 else if (r_name[0] == 'r' && ISDIGIT (r_name[1])
884 && ISDIGIT (r_name[2]) && r_name[3] == 0)
885 /* Double-digit register number, ie r10 - r32. */
886 op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0';
887 else if (r_name[0] >= 'x' && r_name[0] <= 'z'
888 && (r_name[1] == 'l' || r_name[1] == 'h') && r_name[2] == 0)
889 /* Registers r26-r31 referred to by name, ie xl, xh, yl, yh, zl, zh. */
890 op_mask = (r_name[0] - 'x') * 2 + (r_name[1] == 'h') + 26;
891 else if ((*op == 'v' || *op == 'w')
892 && r_name[0] >= 'x' && r_name[0] <= 'z' && r_name[1] == 0)
893 /* For the movw and addiw instructions, refer to registers x, y and z by name. */
894 op_mask = (r_name[0] - 'x') * 2 + 26;
897 /* Numeric or symbolic constant register number. */
898 op_mask = avr_get_constant (old_str, 31);
899 str = input_line_pointer;
903 if (avr_mcu->mach == bfd_mach_avrtiny)
905 if (op_mask < 16 || op_mask > 31)
907 as_bad (_("register name or number from 16 to 31 required"));
911 else if (op_mask > 31)
913 as_bad (_("register name or number from 0 to 31 required"));
920 if (op_mask < 16 || op_mask > 23)
921 as_bad (_("register r16-r23 required"));
927 as_bad (_("register number above 15 required"));
933 as_bad (_("even register number required"));
938 if ((op_mask & 1) || op_mask < 24)
939 as_bad (_("register r24, r26, r28 or r30 required"));
940 op_mask = (op_mask - 24) >> 1;
951 str = skip_space (str + 1);
960 as_bad (_("pointer register (X, Y or Z) required"));
962 str = skip_space (str + 1);
967 as_bad (_("cannot both predecrement and postincrement"));
971 /* avr1 can do "ld r,Z" and "st Z,r" but no other pointer
972 registers, no predecrement, no postincrement. */
973 if (!avr_opt.all_opcodes && (op_mask & 0x100F)
974 && !(avr_mcu->isa & AVR_ISA_SRAM))
975 as_bad (_("addressing mode not supported"));
981 as_bad (_("can't predecrement"));
983 if (! (*str == 'z' || *str == 'Z'))
984 as_bad (_("pointer register Z required"));
986 str = skip_space (str + 1);
992 for (s = opcode->opcode; *s; ++s)
995 op_mask |= (1 << (15 - (s - opcode->opcode)));
999 /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */
1000 if (!avr_opt.all_opcodes
1001 && (op_mask & 0x0001)
1002 && !(avr_mcu->isa & AVR_ISA_MOVW))
1003 as_bad (_("postincrement not supported"));
1008 char c = TOLOWER (*str++);
1013 as_bad (_("pointer register (Y or Z) required"));
1014 str = skip_space (str);
1017 input_line_pointer = str;
1018 avr_offset_expression (& op_expr);
1019 str = input_line_pointer;
1020 fix_new_exp (frag_now, where, 3,
1021 &op_expr, FALSE, BFD_RELOC_AVR_6);
1027 str = parse_exp (str, &op_expr);
1028 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1029 &op_expr, FALSE, BFD_RELOC_AVR_CALL);
1033 str = parse_exp (str, &op_expr);
1034 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1035 &op_expr, TRUE, BFD_RELOC_AVR_13_PCREL);
1039 str = parse_exp (str, &op_expr);
1040 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1041 &op_expr, TRUE, BFD_RELOC_AVR_7_PCREL);
1045 str = parse_exp (str, &op_expr);
1046 fix_new_exp (frag_now, where + 2, opcode->insn_size * 2,
1047 &op_expr, FALSE, BFD_RELOC_16);
1051 str = parse_exp (str, &op_expr);
1052 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1053 &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16);
1058 bfd_reloc_code_real_type r_type;
1060 input_line_pointer = str;
1061 r_type = avr_ldi_expression (&op_expr);
1062 str = input_line_pointer;
1063 fix_new_exp (frag_now, where, 3,
1064 &op_expr, FALSE, r_type);
1072 x = ~avr_get_constant (str, 255);
1073 str = input_line_pointer;
1074 op_mask |= (x & 0xf) | ((x << 4) & 0xf00);
1079 input_line_pointer = str;
1080 avr_offset_expression (& op_expr);
1081 str = input_line_pointer;
1082 fix_new_exp (frag_now, where, 3,
1083 & op_expr, FALSE, BFD_RELOC_AVR_6_ADIW);
1091 x = avr_get_constant (str, 7);
1092 str = input_line_pointer;
1100 str = parse_exp (str, &op_expr);
1101 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1102 &op_expr, FALSE, BFD_RELOC_AVR_PORT6);
1106 str = parse_exp (str, &op_expr);
1107 fix_new_exp (frag_now, where, opcode->insn_size * 2,
1108 &op_expr, FALSE, BFD_RELOC_AVR_PORT5);
1115 x = avr_get_constant (str, 15);
1116 str = input_line_pointer;
1117 op_mask |= (x << 4);
1125 as_bad (_("unknown constraint `%c'"), *op);
1132 /* Parse instruction operands.
1133 Return binary opcode. */
1136 avr_operands (struct avr_opcodes_s *opcode, char **line)
1138 const char *op = opcode->constraints;
1139 unsigned int bin = opcode->bin_opcode;
1140 char *frag = frag_more (opcode->insn_size * 2);
1142 int where = frag - frag_now->fr_literal;
1143 static unsigned int prev = 0; /* Previous opcode. */
1145 /* Opcode have operands. */
1148 unsigned int reg1 = 0;
1149 unsigned int reg2 = 0;
1150 int reg1_present = 0;
1151 int reg2_present = 0;
1153 /* Parse first operand. */
1154 if (REGISTER_P (*op))
1156 reg1 = avr_operand (opcode, where, op, &str);
1159 /* Parse second operand. */
1172 if (REGISTER_P (*op))
1175 str = skip_space (str);
1177 as_bad (_("`,' required"));
1178 str = skip_space (str);
1180 reg2 = avr_operand (opcode, where, op, &str);
1183 if (reg1_present && reg2_present)
1184 reg2 = (reg2 & 0xf) | ((reg2 << 5) & 0x200);
1185 else if (reg2_present)
1193 /* Detect undefined combinations (like ld r31,Z+). */
1194 if (!avr_opt.all_opcodes && AVR_UNDEF_P (bin))
1195 as_warn (_("undefined combination of operands"));
1197 if (opcode->insn_size == 2)
1199 /* Warn if the previous opcode was cpse/sbic/sbis/sbrc/sbrs
1200 (AVR core bug, fixed in the newer devices). */
1201 if (!(avr_opt.no_skip_bug ||
1202 (avr_mcu->isa & (AVR_ISA_MUL | AVR_ISA_MOVW)))
1203 && AVR_SKIP_P (prev))
1204 as_warn (_("skipping two-word instruction"));
1206 bfd_putl32 ((bfd_vma) bin, frag);
1209 bfd_putl16 ((bfd_vma) bin, frag);
1216 /* GAS will call this function for each section at the end of the assembly,
1217 to permit the CPU backend to adjust the alignment of a section. */
1220 md_section_align (asection *seg, valueT addr)
1222 int align = bfd_get_section_alignment (stdoutput, seg);
1223 return ((addr + (1 << align) - 1) & (-1UL << align));
1226 /* If you define this macro, it should return the offset between the
1227 address of a PC relative fixup and the position from which the PC
1228 relative adjustment should be made. On many processors, the base
1229 of a PC relative instruction is the next instruction, so this
1230 macro would return the length of an instruction. */
1233 md_pcrel_from_section (fixS *fixp, segT sec)
1235 if (fixp->fx_addsy != (symbolS *) NULL
1236 && (!S_IS_DEFINED (fixp->fx_addsy)
1237 || (S_GET_SEGMENT (fixp->fx_addsy) != sec)))
1240 return fixp->fx_frag->fr_address + fixp->fx_where;
1244 relaxable_section (asection *sec)
1246 return ((sec->flags & SEC_DEBUGGING) == 0
1247 && (sec->flags & SEC_CODE) != 0
1248 && (sec->flags & SEC_ALLOC) != 0);
1251 /* Does whatever the xtensa port does. */
1253 avr_validate_fix_sub (fixS *fix)
1255 segT add_symbol_segment, sub_symbol_segment;
1257 /* The difference of two symbols should be resolved by the assembler when
1258 linkrelax is not set. If the linker may relax the section containing
1259 the symbols, then an Xtensa DIFF relocation must be generated so that
1260 the linker knows to adjust the difference value. */
1261 if (!linkrelax || fix->fx_addsy == NULL)
1264 /* Make sure both symbols are in the same segment, and that segment is
1265 "normal" and relaxable. If the segment is not "normal", then the
1266 fix is not valid. If the segment is not "relaxable", then the fix
1267 should have been handled earlier. */
1268 add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy);
1269 if (! SEG_NORMAL (add_symbol_segment) ||
1270 ! relaxable_section (add_symbol_segment))
1273 sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy);
1274 return (sub_symbol_segment == add_symbol_segment);
1277 /* TC_FORCE_RELOCATION hook */
1279 /* If linkrelax is turned on, and the symbol to relocate
1280 against is in a relaxable segment, don't compute the value -
1281 generate a relocation instead. */
1283 avr_force_relocation (fixS *fix)
1285 if (linkrelax && fix->fx_addsy
1286 && relaxable_section (S_GET_SEGMENT (fix->fx_addsy)))
1289 return generic_force_reloc (fix);
1292 /* GAS will call this for each fixup. It should store the correct
1293 value in the object file. */
1296 md_apply_fix (fixS *fixP, valueT * valP, segT seg)
1298 unsigned char *where;
1302 if (fixP->fx_addsy == (symbolS *) NULL)
1305 else if (fixP->fx_pcrel)
1307 segT s = S_GET_SEGMENT (fixP->fx_addsy);
1309 if (s == seg || s == absolute_section)
1311 value += S_GET_VALUE (fixP->fx_addsy);
1315 else if (linkrelax && fixP->fx_subsy)
1317 /* For a subtraction relocation expression, generate one
1318 of the DIFF relocs, with the value being the difference.
1319 Note that a sym1 - sym2 expression is adjusted into a
1320 section_start_sym + sym4_offset_from_section_start - sym1
1321 expression. fixP->fx_addsy holds the section start symbol,
1322 fixP->fx_offset holds sym2's offset, and fixP->fx_subsy
1323 holds sym1. Calculate the current difference and write value,
1324 but leave fx_offset as is - during relaxation,
1325 fx_offset - value gives sym1's value. */
1327 switch (fixP->fx_r_type)
1330 fixP->fx_r_type = BFD_RELOC_AVR_DIFF8;
1333 fixP->fx_r_type = BFD_RELOC_AVR_DIFF16;
1336 fixP->fx_r_type = BFD_RELOC_AVR_DIFF32;
1339 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1343 value = S_GET_VALUE (fixP->fx_addsy) +
1344 fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy);
1347 fixP->fx_subsy = NULL;
1349 /* We don't actually support subtracting a symbol. */
1350 if (fixP->fx_subsy != (symbolS *) NULL)
1351 as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex"));
1353 /* For the DIFF relocs, write the value into the object file while still
1354 keeping fx_done FALSE, as both the difference (recorded in the object file)
1355 and the sym offset (part of fixP) are needed at link relax time. */
1356 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1357 switch (fixP->fx_r_type)
1360 fixP->fx_no_overflow = 1;
1362 case BFD_RELOC_AVR_7_PCREL:
1363 case BFD_RELOC_AVR_13_PCREL:
1367 case BFD_RELOC_AVR_DIFF8:
1370 case BFD_RELOC_AVR_DIFF16:
1371 bfd_putl16 ((bfd_vma) value, where);
1373 case BFD_RELOC_AVR_DIFF32:
1374 bfd_putl32 ((bfd_vma) value, where);
1376 case BFD_RELOC_AVR_CALL:
1382 /* Fetch the instruction, insert the fully resolved operand
1383 value, and stuff the instruction back again. */
1384 where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where;
1385 insn = bfd_getl16 (where);
1387 switch (fixP->fx_r_type)
1389 case BFD_RELOC_AVR_7_PCREL:
1391 as_bad_where (fixP->fx_file, fixP->fx_line,
1392 _("odd address operand: %ld"), value);
1394 /* Instruction addresses are always right-shifted by 1. */
1396 --value; /* Correct PC. */
1398 if (value < -64 || value > 63)
1399 as_bad_where (fixP->fx_file, fixP->fx_line,
1400 _("operand out of range: %ld"), value);
1401 value = (value << 3) & 0x3f8;
1402 bfd_putl16 ((bfd_vma) (value | insn), where);
1405 case BFD_RELOC_AVR_13_PCREL:
1407 as_bad_where (fixP->fx_file, fixP->fx_line,
1408 _("odd address operand: %ld"), value);
1410 /* Instruction addresses are always right-shifted by 1. */
1412 --value; /* Correct PC. */
1414 if (value < -2048 || value > 2047)
1416 /* No wrap for devices with >8K of program memory. */
1417 if ((avr_mcu->isa & AVR_ISA_MEGA) || avr_opt.no_wrap)
1418 as_bad_where (fixP->fx_file, fixP->fx_line,
1419 _("operand out of range: %ld"), value);
1423 bfd_putl16 ((bfd_vma) (value | insn), where);
1427 bfd_putl32 ((bfd_vma) value, where);
1431 bfd_putl16 ((bfd_vma) value, where);
1435 if (value > 255 || value < -128)
1436 as_warn_where (fixP->fx_file, fixP->fx_line,
1437 _("operand out of range: %ld"), value);
1441 case BFD_RELOC_AVR_16_PM:
1442 bfd_putl16 ((bfd_vma) (value >> 1), where);
1445 case BFD_RELOC_AVR_LDI:
1447 as_bad_where (fixP->fx_file, fixP->fx_line,
1448 _("operand out of range: %ld"), value);
1449 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1452 case BFD_RELOC_AVR_LDS_STS_16:
1453 if ((value < 0x40) || (value > 0xBF))
1454 as_warn_where (fixP->fx_file, fixP->fx_line,
1455 _("operand out of range: 0x%lx"),
1456 (unsigned long)value);
1457 insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2));
1458 bfd_putl16 ((bfd_vma) insn, where);
1461 case BFD_RELOC_AVR_6:
1462 if ((value > 63) || (value < 0))
1463 as_bad_where (fixP->fx_file, fixP->fx_line,
1464 _("operand out of range: %ld"), value);
1465 bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7)
1466 | ((value & (1 << 5)) << 8)), where);
1469 case BFD_RELOC_AVR_6_ADIW:
1470 if ((value > 63) || (value < 0))
1471 as_bad_where (fixP->fx_file, fixP->fx_line,
1472 _("operand out of range: %ld"), value);
1473 bfd_putl16 ((bfd_vma) insn | (value & 0xf) | ((value & 0x30) << 2), where);
1476 case BFD_RELOC_AVR_LO8_LDI:
1477 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where);
1480 case BFD_RELOC_AVR_HI8_LDI:
1481 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 8), where);
1484 case BFD_RELOC_AVR_MS8_LDI:
1485 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 24), where);
1488 case BFD_RELOC_AVR_HH8_LDI:
1489 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 16), where);
1492 case BFD_RELOC_AVR_LO8_LDI_NEG:
1493 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value), where);
1496 case BFD_RELOC_AVR_HI8_LDI_NEG:
1497 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 8), where);
1500 case BFD_RELOC_AVR_MS8_LDI_NEG:
1501 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 24), where);
1504 case BFD_RELOC_AVR_HH8_LDI_NEG:
1505 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 16), where);
1508 case BFD_RELOC_AVR_LO8_LDI_PM:
1509 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 1), where);
1512 case BFD_RELOC_AVR_HI8_LDI_PM:
1513 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 9), where);
1516 case BFD_RELOC_AVR_HH8_LDI_PM:
1517 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value >> 17), where);
1520 case BFD_RELOC_AVR_LO8_LDI_PM_NEG:
1521 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 1), where);
1524 case BFD_RELOC_AVR_HI8_LDI_PM_NEG:
1525 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 9), where);
1528 case BFD_RELOC_AVR_HH8_LDI_PM_NEG:
1529 bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (-value >> 17), where);
1532 case BFD_RELOC_AVR_CALL:
1536 x = bfd_getl16 (where);
1538 as_bad_where (fixP->fx_file, fixP->fx_line,
1539 _("odd address operand: %ld"), value);
1541 x |= ((value & 0x10000) | ((value << 3) & 0x1f00000)) >> 16;
1542 bfd_putl16 ((bfd_vma) x, where);
1543 bfd_putl16 ((bfd_vma) (value & 0xffff), where + 2);
1547 case BFD_RELOC_AVR_8_LO:
1548 *where = 0xff & value;
1551 case BFD_RELOC_AVR_8_HI:
1552 *where = 0xff & (value >> 8);
1555 case BFD_RELOC_AVR_8_HLO:
1556 *where = 0xff & (value >> 16);
1560 as_fatal (_("line %d: unknown relocation type: 0x%x"),
1561 fixP->fx_line, fixP->fx_r_type);
1564 case BFD_RELOC_AVR_PORT6:
1566 as_bad_where (fixP->fx_file, fixP->fx_line,
1567 _("operand out of range: %ld"), value);
1568 bfd_putl16 ((bfd_vma) insn | ((value & 0x30) << 5) | (value & 0x0f), where);
1571 case BFD_RELOC_AVR_PORT5:
1573 as_bad_where (fixP->fx_file, fixP->fx_line,
1574 _("operand out of range: %ld"), value);
1575 bfd_putl16 ((bfd_vma) insn | ((value & 0x1f) << 3), where);
1581 switch ((int) fixP->fx_r_type)
1583 case -BFD_RELOC_AVR_HI8_LDI_NEG:
1584 case -BFD_RELOC_AVR_HI8_LDI:
1585 case -BFD_RELOC_AVR_LO8_LDI_NEG:
1586 case -BFD_RELOC_AVR_LO8_LDI:
1587 as_bad_where (fixP->fx_file, fixP->fx_line,
1588 _("only constant expression allowed"));
1597 /* GAS will call this to generate a reloc, passing the resulting reloc
1598 to `bfd_install_relocation'. This currently works poorly, as
1599 `bfd_install_relocation' often does the wrong thing, and instances of
1600 `tc_gen_reloc' have been written to work around the problems, which
1601 in turns makes it difficult to fix `bfd_install_relocation'. */
1603 /* If while processing a fixup, a reloc really needs to be created
1604 then it is done here. */
1607 tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED,
1611 bfd_reloc_code_real_type code = fixp->fx_r_type;
1613 if (fixp->fx_subsy != NULL)
1615 as_bad_where (fixp->fx_file, fixp->fx_line, _("expression too complex"));
1619 reloc = XNEW (arelent);
1621 reloc->sym_ptr_ptr = XNEW (asymbol *);
1622 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1624 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1626 if ((fixp->fx_r_type == BFD_RELOC_32) && (fixp->fx_pcrel))
1628 if (seg->use_rela_p)
1629 fixp->fx_offset -= md_pcrel_from_section (fixp, seg);
1631 fixp->fx_offset = reloc->address;
1633 code = BFD_RELOC_32_PCREL;
1636 reloc->addend = fixp->fx_offset;
1638 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1640 if (reloc->howto == (reloc_howto_type *) NULL)
1642 as_bad_where (fixp->fx_file, fixp->fx_line,
1643 _("reloc %d not supported by object file format"),
1644 (int) fixp->fx_r_type);
1648 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1649 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1650 reloc->address = fixp->fx_offset;
1657 md_assemble (char *str)
1659 struct avr_opcodes_s *opcode;
1662 str = skip_space (extract_word (str, op, sizeof (op)));
1665 as_bad (_("can't find opcode "));
1667 opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op);
1669 if (opcode && !avr_opt.all_opcodes)
1671 /* Check if the instruction's ISA bit is ON in the ISA bits of the part
1672 specified by the user. If not look for other instructions
1673 specifications with same mnemonic who's ISA bits matches.
1675 This requires include/opcode/avr.h to have the instructions with
1676 same mnenomic to be specified in sequence. */
1678 while ((opcode->isa & avr_mcu->isa) != opcode->isa)
1682 if (opcode->name && strcmp(op, opcode->name))
1684 as_bad (_("illegal opcode %s for mcu %s"),
1685 opcode->name, avr_mcu->name);
1693 as_bad (_("unknown opcode `%s'"), op);
1697 /* Special case for opcodes with optional operands (lpm, elpm) -
1698 version with operands exists in avr_opcodes[] in the next entry. */
1700 if (*str && *opcode->constraints == '?')
1703 dwarf2_emit_insn (0);
1705 /* We used to set input_line_pointer to the result of get_operands,
1706 but that is wrong. Our caller assumes we don't change it. */
1708 char *t = input_line_pointer;
1710 avr_operands (opcode, &str);
1711 if (*skip_space (str))
1712 as_bad (_("garbage at end of line"));
1713 input_line_pointer = t;
1717 const exp_mod_data_t exp_mod_data[] =
1719 /* Default, must be first. */
1720 { "", 0, BFD_RELOC_16, "" },
1721 /* Divides by 2 to get word address. Generate Stub. */
1722 { "gs", 2, BFD_RELOC_AVR_16_PM, "`gs' " },
1723 { "pm", 2, BFD_RELOC_AVR_16_PM, "`pm' " },
1724 /* The following are used together with avr-gcc's __memx address space
1725 in order to initialize a 24-bit pointer variable with a 24-bit address.
1726 For address in flash, hlo8 will contain the flash segment if the
1727 symbol is located in flash. If the symbol is located in RAM; hlo8
1728 will contain 0x80 which matches avr-gcc's notion of how 24-bit RAM/flash
1729 addresses linearize address space. */
1730 { "lo8", 1, BFD_RELOC_AVR_8_LO, "`lo8' " },
1731 { "hi8", 1, BFD_RELOC_AVR_8_HI, "`hi8' " },
1732 { "hlo8", 1, BFD_RELOC_AVR_8_HLO, "`hlo8' " },
1733 { "hh8", 1, BFD_RELOC_AVR_8_HLO, "`hh8' " },
1736 /* Parse special CONS expression: pm (expression) or alternatively
1737 gs (expression). These are used for addressing program memory. Moreover,
1738 define lo8 (expression), hi8 (expression) and hlo8 (expression). */
1740 const exp_mod_data_t *
1741 avr_parse_cons_expression (expressionS *exp, int nbytes)
1746 tmp = input_line_pointer = skip_space (input_line_pointer);
1748 /* The first entry of exp_mod_data[] contains an entry if no
1749 expression modifier is present. Skip it. */
1751 for (i = 0; i < ARRAY_SIZE (exp_mod_data); i++)
1753 const exp_mod_data_t *pexp = &exp_mod_data[i];
1754 int len = strlen (pexp->name);
1756 if (nbytes == pexp->nbytes
1757 && strncasecmp (input_line_pointer, pexp->name, len) == 0)
1759 input_line_pointer = skip_space (input_line_pointer + len);
1761 if (*input_line_pointer == '(')
1763 input_line_pointer = skip_space (input_line_pointer + 1);
1766 if (*input_line_pointer == ')')
1768 ++input_line_pointer;
1773 as_bad (_("`)' required"));
1774 return &exp_mod_data[0];
1778 input_line_pointer = tmp;
1785 return &exp_mod_data[0];
1789 avr_cons_fix_new (fragS *frag,
1793 const exp_mod_data_t *pexp_mod_data)
1797 switch (pexp_mod_data->reloc)
1801 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_8);
1802 else if (nbytes == 2)
1803 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_16);
1804 else if (nbytes == 4)
1805 fix_new_exp (frag, where, nbytes, exp, FALSE, BFD_RELOC_32);
1810 case BFD_RELOC_AVR_16_PM:
1811 case BFD_RELOC_AVR_8_LO:
1812 case BFD_RELOC_AVR_8_HI:
1813 case BFD_RELOC_AVR_8_HLO:
1814 if (nbytes == pexp_mod_data->nbytes)
1815 fix_new_exp (frag, where, nbytes, exp, FALSE, pexp_mod_data->reloc);
1822 as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
1826 mcu_has_3_byte_pc (void)
1828 int mach = avr_mcu->mach;
1830 return mach == bfd_mach_avr6
1831 || mach == bfd_mach_avrxmega6
1832 || mach == bfd_mach_avrxmega7;
1836 tc_cfi_frame_initial_instructions (void)
1838 /* AVR6 pushes 3 bytes for calls. */
1839 int return_size = (mcu_has_3_byte_pc () ? 3 : 2);
1841 /* The CFA is the caller's stack location before the call insn. */
1842 /* Note that the stack pointer is dwarf register number 32. */
1843 cfi_add_CFA_def_cfa (32, return_size);
1845 /* Note that AVR consistently uses post-decrement, which means that things
1846 do not line up the same way as for targers that use pre-decrement. */
1847 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
1851 avr_allow_local_subtract (expressionS * left,
1852 expressionS * right,
1855 /* If we are not in relaxation mode, subtraction is OK. */
1859 /* If the symbols are not in a code section then they are OK. */
1860 if ((section->flags & SEC_CODE) == 0)
1863 if (left->X_add_symbol == right->X_add_symbol)
1866 /* We have to assume that there may be instructions between the
1867 two symbols and that relaxation may increase the distance between
1873 avr_elf_final_processing (void)
1876 elf_elfheader (stdoutput)->e_flags |= EF_AVR_LINKRELAX_PREPARED;
1879 /* Write out the header of a .avr.prop section into the area pointed to by
1880 DATA. The RECORD_COUNT will be placed in the header as the number of
1881 records that are to follow.
1882 The area DATA must be big enough the receive the header, which is
1883 AVR_PROPERTY_SECTION_HEADER_SIZE bytes long. */
1886 avr_output_property_section_header (char *data,
1887 unsigned int record_count)
1889 char *orig_data = data;
1891 md_number_to_chars (data, AVR_PROPERTY_RECORDS_VERSION, 1);
1893 /* There's space for a single byte flags field, but right now there's
1894 nothing to go in here, so just set the value to zero. */
1895 md_number_to_chars (data, 0, 1);
1897 md_number_to_chars (data, record_count, 2);
1900 gas_assert (data - orig_data == AVR_PROPERTY_SECTION_HEADER_SIZE);
1905 /* Return the number of bytes required to store RECORD into the .avr.prop
1906 section. The size returned is the compressed size that corresponds to
1907 how the record will be written out in AVR_OUTPUT_PROPERTY_RECORD. */
1910 avr_record_size (const struct avr_property_record *record)
1912 /* The first 5 bytes are a 4-byte address, followed by a 1-byte type
1916 switch (record->type)
1919 size += 0; /* No extra information. */
1922 case RECORD_ORG_AND_FILL:
1923 size += 4; /* A 4-byte fill value. */
1927 size += 4; /* A 4-byte alignment value. */
1930 case RECORD_ALIGN_AND_FILL:
1931 size += 8; /* A 4-byte alignment, and 4-byte fill value. */
1935 as_fatal (_("unknown record type %d (in %s)"),
1936 record->type, __PRETTY_FUNCTION__);
1942 /* Write out RECORD. FRAG_BASE points to the start of the data area setup
1943 to hold all of the .avr.prop content, FRAG_PTR points to the next
1944 writable location. The data area must be big enough to hold all of the
1945 records. The size of the data written out for this RECORD must match
1946 the size from AVR_RECORD_SIZE. */
1949 avr_output_property_record (char * const frag_base, char *frag_ptr,
1950 const struct avr_property_record *record)
1954 char *init_frag_ptr = frag_ptr;
1956 where = frag_ptr - frag_base;
1957 fix = fix_new (frag_now, where, 4,
1958 section_symbol (record->section),
1959 record->offset, FALSE, BFD_RELOC_32);
1960 fix->fx_file = "<internal>";
1964 md_number_to_chars (frag_ptr, (bfd_byte) record->type, 1);
1967 /* Write out the rest of the data. */
1968 switch (record->type)
1973 case RECORD_ORG_AND_FILL:
1974 md_number_to_chars (frag_ptr, record->data.org.fill, 4);
1979 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1983 case RECORD_ALIGN_AND_FILL:
1984 md_number_to_chars (frag_ptr, record->data.align.bytes, 4);
1985 md_number_to_chars (frag_ptr + 4, record->data.align.fill, 4);
1990 as_fatal (_("unknown record type %d (in %s)"),
1991 record->type, __PRETTY_FUNCTION__);
1994 gas_assert (frag_ptr - init_frag_ptr == avr_record_size (record));
1999 /* Create the section to hold the AVR property information. Return the
2003 avr_create_property_section (void)
2006 flagword flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY);
2007 const char *section_name = AVR_PROPERTY_RECORD_SECTION_NAME;
2009 sec = bfd_make_section (stdoutput, section_name);
2011 as_fatal (_("Failed to create property section `%s'\n"), section_name);
2012 bfd_set_section_flags (stdoutput, sec, flags);
2013 sec->output_section = sec;
2017 /* This hook is called when alignment is performed, and allows us to
2018 capture the details of both .org and .align directives. */
2021 avr_handle_align (fragS *fragP)
2025 /* Ignore alignment requests at FR_ADDRESS 0, these are at the very
2026 start of a section, and will be handled by the standard section
2027 alignment mechanism. */
2028 if ((fragP->fr_type == rs_align
2029 || fragP->fr_type == rs_align_code)
2030 && fragP->fr_offset > 0)
2032 char *p = fragP->fr_literal + fragP->fr_fix;
2034 fragP->tc_frag_data.is_align = TRUE;
2035 fragP->tc_frag_data.alignment = fragP->fr_offset;
2036 fragP->tc_frag_data.fill = *p;
2037 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2040 if (fragP->fr_type == rs_org && fragP->fr_offset > 0)
2042 char *p = fragP->fr_literal + fragP->fr_fix;
2044 fragP->tc_frag_data.is_org = TRUE;
2045 fragP->tc_frag_data.fill = *p;
2046 fragP->tc_frag_data.has_fill = (fragP->tc_frag_data.fill != 0);
2051 /* Return TRUE if this section is not one for which we need to record
2052 information in the avr property section. */
2055 exclude_section_from_property_tables (segT sec)
2057 /* Only generate property information for sections on which linker
2058 relaxation could be performed. */
2059 return !relaxable_section (sec);
2062 /* Create a property record for fragment FRAGP from section SEC and place
2063 it into an AVR_PROPERTY_RECORD_LINK structure, which can then formed
2064 into a linked list by the caller. */
2066 static struct avr_property_record_link *
2067 create_record_for_frag (segT sec, fragS *fragP)
2069 struct avr_property_record_link *prop_rec_link;
2071 prop_rec_link = XCNEW (struct avr_property_record_link);
2072 gas_assert (fragP->fr_next != NULL);
2074 if (fragP->tc_frag_data.is_org)
2076 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2077 prop_rec_link->record.section = sec;
2079 if (fragP->tc_frag_data.has_fill)
2081 prop_rec_link->record.data.org.fill = fragP->tc_frag_data.fill;
2082 prop_rec_link->record.type = RECORD_ORG_AND_FILL;
2085 prop_rec_link->record.type = RECORD_ORG;
2089 prop_rec_link->record.offset = fragP->fr_next->fr_address;
2090 prop_rec_link->record.section = sec;
2092 gas_assert (fragP->tc_frag_data.is_align);
2093 if (fragP->tc_frag_data.has_fill)
2095 prop_rec_link->record.data.align.fill = fragP->tc_frag_data.fill;
2096 prop_rec_link->record.type = RECORD_ALIGN_AND_FILL;
2099 prop_rec_link->record.type = RECORD_ALIGN;
2100 prop_rec_link->record.data.align.bytes = fragP->tc_frag_data.alignment;
2103 return prop_rec_link;
2106 /* Build a list of AVR_PROPERTY_RECORD_LINK structures for section SEC, and
2107 merged them onto the list pointed to by NEXT_PTR. Return a pointer to
2108 the last list item created. */
2110 static struct avr_property_record_link **
2111 append_records_for_section (segT sec,
2112 struct avr_property_record_link **next_ptr)
2114 segment_info_type *seginfo = seg_info (sec);
2117 if (seginfo && seginfo->frchainP)
2119 for (fragP = seginfo->frchainP->frch_root;
2121 fragP = fragP->fr_next)
2123 if (fragP->tc_frag_data.is_align
2124 || fragP->tc_frag_data.is_org)
2126 /* Create a single new entry. */
2127 struct avr_property_record_link *new_link
2128 = create_record_for_frag (sec, fragP);
2130 *next_ptr = new_link;
2131 next_ptr = &new_link->next;
2139 /* Create the AVR property section and fill it with records of .org and
2140 .align directives that were used. The section is only created if it
2141 will actually have any content. */
2144 avr_create_and_fill_property_section (void)
2148 struct avr_property_record_link *r_list, **next_ptr;
2149 char *frag_ptr, *frag_base;
2150 bfd_size_type sec_size;
2151 struct avr_property_record_link *rec;
2152 unsigned int record_count;
2154 /* First walk over all sections. For sections on which linker
2155 relaxation could be applied, extend the record list. The record list
2156 holds information that the linker will need to know. */
2161 for (seclist = &stdoutput->sections;
2162 seclist && *seclist;
2163 seclist = &(*seclist)->next)
2165 segT sec = *seclist;
2167 if (exclude_section_from_property_tables (sec))
2170 next_ptr = append_records_for_section (sec, next_ptr);
2173 /* Create property section and ensure the size is correct. We've already
2174 passed the point where gas could size this for us. */
2175 sec_size = AVR_PROPERTY_SECTION_HEADER_SIZE;
2177 for (rec = r_list; rec != NULL; rec = rec->next)
2180 sec_size += avr_record_size (&rec->record);
2183 if (record_count == 0)
2186 prop_sec = avr_create_property_section ();
2187 bfd_set_section_size (stdoutput, prop_sec, sec_size);
2189 subseg_set (prop_sec, 0);
2190 frag_base = frag_more (sec_size);
2193 avr_output_property_section_header (frag_base, record_count);
2195 for (rec = r_list; rec != NULL; rec = rec->next)
2196 frag_ptr = avr_output_property_record (frag_base, frag_ptr, &rec->record);
2198 frag_wane (frag_now);
2200 frag_wane (frag_now);
2203 /* We're using this hook to build up the AVR property section. It's called
2204 late in the assembly process which suits our needs. */
2206 avr_post_relax_hook (void)
2208 avr_create_and_fill_property_section ();