1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
39 /* Types of processor to assemble for. */
40 #define ARM_1 0x00000001
41 #define ARM_2 0x00000002
42 #define ARM_3 0x00000004
44 #define ARM_6 0x00000008
45 #define ARM_7 ARM_6 /* same core instruction set */
46 #define ARM_8 ARM_6 /* same core instruction set */
47 #define ARM_9 ARM_6 /* same core instruction set */
48 #define ARM_CPU_MASK 0x0000000f
50 /* The following bitmasks control CPU extensions (ARM7 onwards): */
51 #define ARM_LONGMUL 0x00000010 /* allow long multiplies */
52 #define ARM_HALFWORD 0x00000020 /* allow half word loads */
53 #define ARM_THUMB 0x00000040 /* allow BX instruction */
54 #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */
55 #define ARM_EXT_V5E 0x00000200 /* "El Segundo" */
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7 */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core */
82 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
84 #define CPU_DEFAULT ARM_ALL
89 #define FPU_DEFAULT FPU_ALL
92 #define streq(a, b) (strcmp (a, b) == 0)
93 #define skip_whitespace(str) while (* (str) == ' ') ++ (str)
95 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
96 static int target_oabi = 0;
98 #if defined OBJ_COFF || defined OBJ_ELF
99 /* Flags stored in private area of BFD structure */
100 static boolean uses_apcs_26 = false;
101 static boolean support_interwork = false;
102 static boolean uses_apcs_float = false;
103 static boolean pic_code = false;
106 /* This array holds the chars that always start a comment. If the
107 pre-processor is disabled, these aren't very useful. */
108 CONST char comment_chars[] = "@";
110 /* This array holds the chars that only start a comment at the beginning of
111 a line. If the line seems to have the form '# 123 filename'
112 .line and .file directives will appear in the pre-processed output. */
113 /* Note that input_file.c hand checks for '#' at the beginning of the
114 first line of the input file. This is because the compiler outputs
115 #NO_APP at the beginning of its output. */
116 /* Also note that comments like this one will always work. */
117 CONST char line_comment_chars[] = "#";
120 CONST char line_separator_chars[] = ";";
122 CONST char line_separator_chars[] = "";
125 /* Chars that can be used to separate mant
126 from exp in floating point numbers. */
127 CONST char EXP_CHARS[] = "eE";
129 /* Chars that mean this number is a floating point constant */
133 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
135 /* Prefix characters that indicate the start of an immediate
137 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
140 symbolS * GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
143 CONST int md_reloc_size = 8; /* Size of relocation record */
145 static int thumb_mode = 0; /* 0: assemble for ARM, 1: assemble for Thumb,
146 2: assemble for Thumb even though target cpu
147 does not support thumb instructions. */
148 typedef struct arm_fix
156 unsigned long instruction;
161 bfd_reloc_code_real_type type;
171 CONST char * template;
175 static CONST struct asm_shift shift[] =
191 #define NO_SHIFT_RESTRICT 1
192 #define SHIFT_RESTRICT 0
194 #define NUM_FLOAT_VALS 8
196 CONST char * fp_const[] =
198 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
201 /* Number of littlenums required to hold an extended precision number. */
202 #define MAX_LITTLENUMS 6
204 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
214 #define CP_T_X 0x00008000
215 #define CP_T_Y 0x00400000
216 #define CP_T_Pre 0x01000000
217 #define CP_T_UD 0x00800000
218 #define CP_T_WB 0x00200000
220 #define CONDS_BIT (0x00100000)
221 #define LOAD_BIT (0x00100000)
222 #define TRANS_BIT (0x00200000)
226 CONST char * template;
230 /* This is to save a hash look-up in the common case. */
231 #define COND_ALWAYS 0xe0000000
233 static CONST struct asm_cond conds[] =
237 {"cs", 0x20000000}, {"hs", 0x20000000},
238 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
253 /* Warning: If the top bit of the set_bits is set, then the standard
254 instruction bitmask is ignored, and the new bitmask is taken from
258 CONST char * template; /* Basic flag string */
259 unsigned long set_bits; /* Bits to set */
262 static CONST struct asm_flg s_flag[] =
268 static CONST struct asm_flg ldr_flags[] =
272 {"bt", 0x00400000 | TRANS_BIT},
279 static CONST struct asm_flg str_flags[] =
283 {"bt", 0x00400000 | TRANS_BIT},
288 static CONST struct asm_flg byte_flag[] =
294 static CONST struct asm_flg cmp_flags[] =
301 static CONST struct asm_flg ldm_flags[] =
314 static CONST struct asm_flg stm_flags[] =
327 static CONST struct asm_flg lfm_flags[] =
334 static CONST struct asm_flg sfm_flags[] =
341 static CONST struct asm_flg round_flags[] =
349 /* The implementation of the FIX instruction is broken on some assemblers,
350 in that it accepts a precision specifier as well as a rounding specifier,
351 despite the fact that this is meaningless. To be more compatible, we
352 accept it as well, though of course it does not set any bits. */
353 static CONST struct asm_flg fix_flags[] =
370 static CONST struct asm_flg except_flag[] =
376 static CONST struct asm_flg cplong_flag[] =
384 CONST char * template;
385 unsigned long number;
388 #define PSR_FIELD_MASK 0x000f0000
390 #define PSR_FLAGS 0x00080000
391 #define PSR_CONTROL 0x00010000 /* Undocumented instruction, its use is discouraged by ARM */
392 #define PSR_ALL 0x00090000
401 static CONST struct asm_psr psrs[] =
405 {"cpsr_all", CPSR_ALL},
407 {"spsr_all", SPSR_ALL},
410 {"cpsr_flg", CPSR_FLG},
411 {"spsr_flg", SPSR_FLG},
414 {"cpsr_c", CPSR_CTL},
415 {"cpsr_ctl", CPSR_CTL},
416 {"spsr_c", SPSR_CTL},
417 {"spsr_ctl", SPSR_CTL}
420 /* Functions called by parser. */
421 /* ARM instructions */
422 static void do_arit PARAMS ((char *, unsigned long));
423 static void do_cmp PARAMS ((char *, unsigned long));
424 static void do_mov PARAMS ((char *, unsigned long));
425 static void do_ldst PARAMS ((char *, unsigned long));
426 static void do_ldmstm PARAMS ((char *, unsigned long));
427 static void do_branch PARAMS ((char *, unsigned long));
428 static void do_swi PARAMS ((char *, unsigned long));
429 /* Pseudo Op codes */
430 static void do_adr PARAMS ((char *, unsigned long));
431 static void do_adrl PARAMS ((char *, unsigned long));
432 static void do_nop PARAMS ((char *, unsigned long));
434 static void do_mul PARAMS ((char *, unsigned long));
435 static void do_mla PARAMS ((char *, unsigned long));
437 static void do_swap PARAMS ((char *, unsigned long));
439 static void do_msr PARAMS ((char *, unsigned long));
440 static void do_mrs PARAMS ((char *, unsigned long));
442 static void do_mull PARAMS ((char *, unsigned long));
444 static void do_bx PARAMS ((char *, unsigned long));
447 /* Coprocessor Instructions */
448 static void do_cdp PARAMS ((char *, unsigned long));
449 static void do_lstc PARAMS ((char *, unsigned long));
450 static void do_co_reg PARAMS ((char *, unsigned long));
451 static void do_fp_ctrl PARAMS ((char *, unsigned long));
452 static void do_fp_ldst PARAMS ((char *, unsigned long));
453 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
454 static void do_fp_dyadic PARAMS ((char *, unsigned long));
455 static void do_fp_monadic PARAMS ((char *, unsigned long));
456 static void do_fp_cmp PARAMS ((char *, unsigned long));
457 static void do_fp_from_reg PARAMS ((char *, unsigned long));
458 static void do_fp_to_reg PARAMS ((char *, unsigned long));
460 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
461 static int arm_reg_parse PARAMS ((char **));
462 static int arm_psr_parse PARAMS ((char **));
463 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
464 static int add_to_lit_pool PARAMS ((void));
465 static unsigned validate_immediate PARAMS ((unsigned));
466 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
467 static int validate_offset_imm PARAMS ((unsigned int, int));
468 static void opcode_select PARAMS ((int));
469 static void end_of_line PARAMS ((char *));
470 static int reg_required_here PARAMS ((char **, int));
471 static int psr_required_here PARAMS ((char **, int, int));
472 static int co_proc_number PARAMS ((char **));
473 static int cp_opc_expr PARAMS ((char **, int, int));
474 static int cp_reg_required_here PARAMS ((char **, int));
475 static int fp_reg_required_here PARAMS ((char **, int));
476 static int cp_address_offset PARAMS ((char **));
477 static int cp_address_required_here PARAMS ((char **));
478 static int my_get_float_expression PARAMS ((char **));
479 static int skip_past_comma PARAMS ((char **));
480 static int walk_no_bignums PARAMS ((symbolS *));
481 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
482 static int data_op2 PARAMS ((char **));
483 static int fp_op2 PARAMS ((char **));
484 static long reg_list PARAMS ((char **));
485 static void thumb_load_store PARAMS ((char *, int, int));
486 static int decode_shift PARAMS ((char **, int));
487 static int ldst_extend PARAMS ((char **, int));
488 static void thumb_add_sub PARAMS ((char *, int));
489 static void insert_reg PARAMS ((int));
490 static void thumb_shift PARAMS ((char *, int));
491 static void thumb_mov_compare PARAMS ((char *, int));
492 static void set_constant_flonums PARAMS ((void));
493 static valueT md_chars_to_number PARAMS ((char *, int));
494 static void insert_reg_alias PARAMS ((char *, int));
495 static void output_inst PARAMS ((void));
497 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
500 /* ARM instructions take 4bytes in the object file, Thumb instructions
504 /* LONGEST_INST is the longest basic instruction name without conditions or
505 flags. ARM7M has 4 of length 5. */
507 #define LONGEST_INST 5
512 CONST char * template; /* Basic string to match */
513 unsigned long value; /* Basic instruction code */
515 /* Compulsory suffix that must follow conds. If "", then the
516 instruction is not conditional and must have no suffix. */
517 CONST char * comp_suffix;
519 CONST struct asm_flg * flags; /* Bits to toggle if flag 'n' set */
520 unsigned long variants; /* Which CPU variants this exists for */
521 /* Function to call to parse args */
522 void (* parms) PARAMS ((char *, unsigned long));
525 static CONST struct asm_opcode insns[] =
527 /* ARM Instructions */
528 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
529 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
530 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
531 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
532 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
533 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
534 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
535 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
536 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
537 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
538 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
539 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
540 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
541 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
542 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
543 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
544 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
545 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
546 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
547 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
548 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
550 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
551 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
553 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
554 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
558 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
559 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
560 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
562 /* ARM 2 multiplies */
563 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
564 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
566 /* ARM 3 - swp instructions */
567 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
569 /* ARM 6 Coprocessor instructions */
570 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
571 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
572 /* ScottB: our code uses 0x0128f000 for msr.
573 NickC: but this is wrong because the bits 16 and 19 are handled
574 by the PSR_xxx defines above. */
576 /* ARM 7M long multiplies - need signed/unsigned flags! */
577 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
578 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
579 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
580 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
582 /* ARM THUMB interworking */
583 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
585 /* Floating point instructions */
586 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
587 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
588 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
589 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
590 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
591 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
592 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
593 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
594 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
595 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
596 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
597 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
598 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
599 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
600 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
601 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
602 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
603 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
604 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
605 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
606 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
607 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
608 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
609 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
610 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
611 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
612 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
613 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
614 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
615 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
616 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
617 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
618 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
619 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
620 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
621 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
622 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
623 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
624 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
625 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
626 be an optional suffix, but part of the instruction. To be compatible,
628 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
629 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
630 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
631 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
633 /* Generic copressor instructions. */
634 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
635 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
636 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
637 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
638 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
641 /* Defines for various bits that we will want to toggle. */
642 #define INST_IMMEDIATE 0x02000000
643 #define OFFSET_REG 0x02000000
644 #define HWOFFSET_IMM 0x00400000
645 #define SHIFT_BY_REG 0x00000010
646 #define PRE_INDEX 0x01000000
647 #define INDEX_UP 0x00800000
648 #define WRITE_BACK 0x00200000
649 #define LDM_TYPE_2_OR_3 0x00400000
651 #define LITERAL_MASK 0xf000f000
652 #define COND_MASK 0xf0000000
653 #define OPCODE_MASK 0xfe1fffff
654 #define DATA_OP_SHIFT 21
656 /* Codes to distinguish the arithmetic instructions. */
667 #define OPCODE_CMP 10
668 #define OPCODE_CMN 11
669 #define OPCODE_ORR 12
670 #define OPCODE_MOV 13
671 #define OPCODE_BIC 14
672 #define OPCODE_MVN 15
674 static void do_t_nop PARAMS ((char *));
675 static void do_t_arit PARAMS ((char *));
676 static void do_t_add PARAMS ((char *));
677 static void do_t_asr PARAMS ((char *));
678 static void do_t_branch9 PARAMS ((char *));
679 static void do_t_branch12 PARAMS ((char *));
680 static void do_t_branch23 PARAMS ((char *));
681 static void do_t_bx PARAMS ((char *));
682 static void do_t_compare PARAMS ((char *));
683 static void do_t_ldmstm PARAMS ((char *));
684 static void do_t_ldr PARAMS ((char *));
685 static void do_t_ldrb PARAMS ((char *));
686 static void do_t_ldrh PARAMS ((char *));
687 static void do_t_lds PARAMS ((char *));
688 static void do_t_lsl PARAMS ((char *));
689 static void do_t_lsr PARAMS ((char *));
690 static void do_t_mov PARAMS ((char *));
691 static void do_t_push_pop PARAMS ((char *));
692 static void do_t_str PARAMS ((char *));
693 static void do_t_strb PARAMS ((char *));
694 static void do_t_strh PARAMS ((char *));
695 static void do_t_sub PARAMS ((char *));
696 static void do_t_swi PARAMS ((char *));
697 static void do_t_adr PARAMS ((char *));
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ASR_I 0x1000
721 #define T_OPCODE_LSL_I 0x0000
722 #define T_OPCODE_LSR_I 0x0800
724 #define T_OPCODE_MOV_I8 0x2000
725 #define T_OPCODE_CMP_I8 0x2800
726 #define T_OPCODE_CMP_LR 0x4280
727 #define T_OPCODE_MOV_HR 0x4600
728 #define T_OPCODE_CMP_HR 0x4500
730 #define T_OPCODE_LDR_PC 0x4800
731 #define T_OPCODE_LDR_SP 0x9800
732 #define T_OPCODE_STR_SP 0x9000
733 #define T_OPCODE_LDR_IW 0x6800
734 #define T_OPCODE_STR_IW 0x6000
735 #define T_OPCODE_LDR_IH 0x8800
736 #define T_OPCODE_STR_IH 0x8000
737 #define T_OPCODE_LDR_IB 0x7800
738 #define T_OPCODE_STR_IB 0x7000
739 #define T_OPCODE_LDR_RW 0x5800
740 #define T_OPCODE_STR_RW 0x5000
741 #define T_OPCODE_LDR_RH 0x5a00
742 #define T_OPCODE_STR_RH 0x5200
743 #define T_OPCODE_LDR_RB 0x5c00
744 #define T_OPCODE_STR_RB 0x5400
746 #define T_OPCODE_PUSH 0xb400
747 #define T_OPCODE_POP 0xbc00
749 #define T_OPCODE_BRANCH 0xe7fe
751 static int thumb_reg PARAMS ((char ** str, int hi_lo));
753 #define THUMB_SIZE 2 /* Size of thumb instruction. */
754 #define THUMB_REG_LO 0x1
755 #define THUMB_REG_HI 0x2
756 #define THUMB_REG_ANY 0x3
758 #define THUMB_H1 0x0080
759 #define THUMB_H2 0x0040
766 #define THUMB_COMPARE 1
769 #define THUMB_STORE 1
771 #define THUMB_PP_PC_LR 0x0100
773 /* These three are used for immediate shifts, do not alter. */
775 #define THUMB_HALFWORD 1
780 CONST char * template; /* Basic string to match */
781 unsigned long value; /* Basic instruction code */
783 unsigned long variants; /* Which CPU variants this exists for */
784 void (* parms) PARAMS ((char *)); /* Function to call to parse args */
787 static CONST struct thumb_opcode tinsns[] =
789 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
790 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
791 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
792 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
793 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
794 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
795 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
796 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
797 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
798 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
799 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
800 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
801 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
802 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
803 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
804 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
805 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
806 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
807 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
808 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
809 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
810 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
811 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
812 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
813 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
814 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
815 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
816 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
817 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
818 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
819 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
820 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
821 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
822 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
823 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
824 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
825 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
826 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
827 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
828 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
829 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
830 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
831 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
832 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
833 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
834 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
835 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
836 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
837 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
838 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
839 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
840 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
841 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
842 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
843 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
845 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
846 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
855 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
856 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
857 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
863 /* These are the standard names. Users can add aliases with .req */
864 static CONST struct reg_entry reg_table[] =
866 /* Processor Register Numbers. */
867 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
868 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
869 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
870 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
871 /* APCS conventions. */
872 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
873 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
874 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
875 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
876 /* ATPCS additions to APCS conventions. */
877 {"wr", 7}, {"v8", 11},
879 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
880 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
881 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
882 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
883 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
884 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
885 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
886 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
887 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
888 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
889 /* ATPCS additions to float register names. */
890 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
891 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
892 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
893 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
894 /* FIXME: At some point we need to add VFP register names. */
895 /* Array terminator. */
899 #define BAD_ARGS _("Bad arguments to instruction")
900 #define BAD_PC _("r15 not allowed here")
901 #define BAD_FLAGS _("Instruction should not have flags")
902 #define BAD_COND _("Instruction is not conditional")
904 static struct hash_control * arm_ops_hsh = NULL;
905 static struct hash_control * arm_tops_hsh = NULL;
906 static struct hash_control * arm_cond_hsh = NULL;
907 static struct hash_control * arm_shift_hsh = NULL;
908 static struct hash_control * arm_reg_hsh = NULL;
909 static struct hash_control * arm_psr_hsh = NULL;
911 /* This table describes all the machine specific pseudo-ops the assembler
912 has to support. The fields are:
913 pseudo-op name without dot
914 function to call to execute this pseudo-op
915 Integer arg to pass to the function. */
917 static void s_req PARAMS ((int));
918 static void s_align PARAMS ((int));
919 static void s_bss PARAMS ((int));
920 static void s_even PARAMS ((int));
921 static void s_ltorg PARAMS ((int));
922 static void s_arm PARAMS ((int));
923 static void s_thumb PARAMS ((int));
924 static void s_code PARAMS ((int));
925 static void s_force_thumb PARAMS ((int));
926 static void s_thumb_func PARAMS ((int));
927 static void s_thumb_set PARAMS ((int));
928 static void arm_s_text PARAMS ((int));
929 static void arm_s_data PARAMS ((int));
931 static void arm_s_section PARAMS ((int));
932 static void s_arm_elf_cons PARAMS ((int));
935 static int my_get_expression PARAMS ((expressionS *, char **));
937 CONST pseudo_typeS md_pseudo_table[] =
939 { "req", s_req, 0 }, /* Never called becasue '.req' does not start line */
941 { "align", s_align, 0 },
943 { "thumb", s_thumb, 0 },
944 { "code", s_code, 0 },
945 { "force_thumb", s_force_thumb, 0 },
946 { "thumb_func", s_thumb_func, 0 },
947 { "thumb_set", s_thumb_set, 0 },
948 { "even", s_even, 0 },
949 { "ltorg", s_ltorg, 0 },
950 { "pool", s_ltorg, 0 },
951 /* Allow for the effect of section changes. */
952 { "text", arm_s_text, 0 },
953 { "data", arm_s_data, 0 },
955 { "section", arm_s_section, 0 },
956 { "section.s", arm_s_section, 0 },
957 { "sect", arm_s_section, 0 },
958 { "sect.s", arm_s_section, 0 },
959 { "word", s_arm_elf_cons, 4 },
960 { "long", s_arm_elf_cons, 4 },
964 { "extend", float_cons, 'x' },
965 { "ldouble", float_cons, 'x' },
966 { "packed", float_cons, 'p' },
970 /* Stuff needed to resolve the label ambiguity
980 symbolS * last_label_seen;
981 static int label_is_thumb_function_name = false;
985 #define MAX_LITERAL_POOL_SIZE 1024
987 typedef struct literalS
989 struct expressionS exp;
990 struct arm_it * inst;
993 literalT literals[MAX_LITERAL_POOL_SIZE];
994 int next_literal_pool_place = 0; /* Next free entry in the pool */
995 int lit_pool_num = 1; /* Next literal pool number */
996 symbolS * current_poolP = NULL;
1003 if (current_poolP == NULL)
1004 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1005 (valueT) 0, &zero_address_frag);
1007 /* Check if this literal value is already in the pool: */
1008 while (lit_count < next_literal_pool_place)
1010 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1011 && inst.reloc.exp.X_op == O_constant
1012 && literals[lit_count].exp.X_add_number
1013 == inst.reloc.exp.X_add_number
1014 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1019 if (lit_count == next_literal_pool_place) /* new entry */
1021 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1023 inst.error = _("Literal Pool Overflow");
1027 literals[next_literal_pool_place].exp = inst.reloc.exp;
1028 lit_count = next_literal_pool_place++;
1031 inst.reloc.exp.X_op = O_symbol;
1032 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1033 inst.reloc.exp.X_add_symbol = current_poolP;
1038 /* Can't use symbol_new here, so have to create a symbol and then at
1039 a later date assign it a value. Thats what these functions do. */
1041 symbol_locate (symbolP, name, segment, valu, frag)
1043 CONST char * name; /* It is copied, the caller can modify */
1044 segT segment; /* Segment identifier (SEG_<something>) */
1045 valueT valu; /* Symbol value */
1046 fragS * frag; /* Associated fragment */
1048 unsigned int name_length;
1049 char * preserved_copy_of_name;
1051 name_length = strlen (name) + 1; /* +1 for \0 */
1052 obstack_grow (¬es, name, name_length);
1053 preserved_copy_of_name = obstack_finish (¬es);
1054 #ifdef STRIP_UNDERSCORE
1055 if (preserved_copy_of_name[0] == '_')
1056 preserved_copy_of_name++;
1059 #ifdef tc_canonicalize_symbol_name
1060 preserved_copy_of_name =
1061 tc_canonicalize_symbol_name (preserved_copy_of_name);
1064 S_SET_NAME (symbolP, preserved_copy_of_name);
1066 S_SET_SEGMENT (symbolP, segment);
1067 S_SET_VALUE (symbolP, valu);
1068 symbol_clear_list_pointers(symbolP);
1070 symbol_set_frag (symbolP, frag);
1072 /* Link to end of symbol chain. */
1074 extern int symbol_table_frozen;
1075 if (symbol_table_frozen)
1079 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1081 obj_symbol_new_hook (symbolP);
1083 #ifdef tc_symbol_new_hook
1084 tc_symbol_new_hook (symbolP);
1088 verify_symbol_chain (symbol_rootP, symbol_lastP);
1089 #endif /* DEBUG_SYMS */
1092 /* Check that an immediate is valid, and if so,
1093 convert it to the right format. */
1095 validate_immediate (val)
1101 #define rotate_left(v, n) (v << n | v >> (32 - n))
1103 for (i = 0; i < 32; i += 2)
1104 if ((a = rotate_left (val, i)) <= 0xff)
1105 return a | (i << 7); /* 12-bit pack: [shift-cnt,const] */
1110 /* Check to see if an immediate can be computed as two seperate immediate
1111 values, added together. We already know that this value cannot be
1112 computed by just one ARM instruction. */
1114 validate_immediate_twopart (val, highpart)
1116 unsigned int * highpart;
1121 for (i = 0; i < 32; i += 2)
1122 if (((a = rotate_left (val, i)) & 0xff) != 0)
1128 * highpart = (a >> 8) | ((i + 24) << 7);
1130 else if (a & 0xff0000)
1135 * highpart = (a >> 16) | ((i + 16) << 7);
1139 assert (a & 0xff000000);
1141 * highpart = (a >> 24) | ((i + 8) << 7);
1144 return (a & 0xff) | (i << 7);
1151 validate_offset_imm (val, hwse)
1155 if ((hwse && val > 255) || val > 4095)
1163 int a ATTRIBUTE_UNUSED;
1165 as_bad (_("Invalid syntax for .req directive."));
1170 int ignore ATTRIBUTE_UNUSED;
1172 /* We don't support putting frags in the BSS segment, we fake it by
1173 marking in_bss, then looking at s_skip for clues?.. */
1174 subseg_set (bss_section, 0);
1175 demand_empty_rest_of_line ();
1180 int ignore ATTRIBUTE_UNUSED;
1182 if (!need_pass_2) /* Never make frag if expect extra pass. */
1183 frag_align (1, 0, 0);
1185 record_alignment (now_seg, 1);
1187 demand_empty_rest_of_line ();
1192 int ignored ATTRIBUTE_UNUSED;
1197 if (current_poolP == NULL)
1200 /* Align pool as you have word accesses */
1201 /* Only make a frag if we have to ... */
1203 frag_align (2, 0, 0);
1205 record_alignment (now_seg, 2);
1207 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1209 symbol_locate (current_poolP, sym_name, now_seg,
1210 (valueT) frag_now_fix (), frag_now);
1211 symbol_table_insert (current_poolP);
1213 ARM_SET_THUMB (current_poolP, thumb_mode);
1215 #if defined OBJ_COFF || defined OBJ_ELF
1216 ARM_SET_INTERWORK (current_poolP, support_interwork);
1219 while (lit_count < next_literal_pool_place)
1220 /* First output the expression in the instruction to the pool. */
1221 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1223 next_literal_pool_place = 0;
1224 current_poolP = NULL;
1228 s_align (unused) /* Same as s_align_ptwo but align 0 => align 2 */
1229 int unused ATTRIBUTE_UNUSED;
1232 register long temp_fill;
1233 long max_alignment = 15;
1235 temp = get_absolute_expression ();
1236 if (temp > max_alignment)
1237 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1240 as_bad (_("Alignment negative. 0 assumed."));
1244 if (*input_line_pointer == ',')
1246 input_line_pointer++;
1247 temp_fill = get_absolute_expression ();
1255 /* Only make a frag if we HAVE to. . . */
1256 if (temp && !need_pass_2)
1257 frag_align (temp, (int) temp_fill, 0);
1258 demand_empty_rest_of_line ();
1260 record_alignment (now_seg, temp);
1264 s_force_thumb (ignore)
1265 int ignore ATTRIBUTE_UNUSED;
1267 /* If we are not already in thumb mode go into it, EVEN if
1268 the target processor does not support thumb instructions.
1269 This is used by gcc/config/arm/lib1funcs.asm for example
1270 to compile interworking support functions even if the
1271 target processor should not support interworking. */
1277 record_alignment (now_seg, 1);
1280 demand_empty_rest_of_line ();
1284 s_thumb_func (ignore)
1285 int ignore ATTRIBUTE_UNUSED;
1287 /* The following label is the name/address of the start of a Thumb function.
1288 We need to know this for the interworking support. */
1290 label_is_thumb_function_name = true;
1292 demand_empty_rest_of_line ();
1295 /* Perform a .set directive, but also mark the alias as
1296 being a thumb function. */
1302 /* XXX the following is a duplicate of the code for s_set() in read.c
1303 We cannot just call that code as we need to get at the symbol that
1305 register char * name;
1306 register char delim;
1307 register char * end_name;
1308 register symbolS * symbolP;
1311 * Especial apologies for the random logic:
1312 * this just grew, and could be parsed much more simply!
1315 name = input_line_pointer;
1316 delim = get_symbol_end ();
1317 end_name = input_line_pointer;
1322 if (*input_line_pointer != ',')
1325 as_bad (_("Expected comma after name \"%s\""), name);
1327 ignore_rest_of_line ();
1331 input_line_pointer++;
1334 if (name[0] == '.' && name[1] == '\0')
1336 /* XXX - this should not happen to .thumb_set */
1340 if ((symbolP = symbol_find (name)) == NULL
1341 && (symbolP = md_undefined_symbol (name)) == NULL)
1344 /* When doing symbol listings, play games with dummy fragments living
1345 outside the normal fragment chain to record the file and line info
1347 if (listing & LISTING_SYMBOLS)
1349 extern struct list_info_struct * listing_tail;
1350 fragS * dummy_frag = (fragS *) xmalloc (sizeof(fragS));
1351 memset (dummy_frag, 0, sizeof(fragS));
1352 dummy_frag->fr_type = rs_fill;
1353 dummy_frag->line = listing_tail;
1354 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1355 dummy_frag->fr_symbol = symbolP;
1359 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1362 /* "set" symbols are local unless otherwise specified. */
1363 SF_SET_LOCAL (symbolP);
1364 #endif /* OBJ_COFF */
1365 } /* make a new symbol */
1367 symbol_table_insert (symbolP);
1372 && S_IS_DEFINED (symbolP)
1373 && S_GET_SEGMENT (symbolP) != reg_section)
1374 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1376 pseudo_set (symbolP);
1378 demand_empty_rest_of_line ();
1380 /* XXX Now we come to the Thumb specific bit of code. */
1382 THUMB_SET_FUNC (symbolP, 1);
1383 ARM_SET_THUMB (symbolP, 1);
1384 #if defined OBJ_ELF || defined OBJ_COFF
1385 ARM_SET_INTERWORK (symbolP, support_interwork);
1389 /* If we change section we must dump the literal pool first. */
1394 if (now_seg != text_section)
1398 obj_elf_text (ignore);
1408 if (flag_readonly_data_in_text)
1410 if (now_seg != text_section)
1413 else if (now_seg != data_section)
1417 obj_elf_data (ignore);
1425 arm_s_section (ignore)
1430 obj_elf_section (ignore);
1435 opcode_select (width)
1443 if (! (cpu_variant & ARM_THUMB))
1444 as_bad (_("selected processor does not support THUMB opcodes"));
1446 /* No need to force the alignment, since we will have been
1447 coming from ARM mode, which is word-aligned. */
1448 record_alignment (now_seg, 1);
1455 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1456 as_bad (_("selected processor does not support ARM opcodes"));
1459 frag_align (2, 0, 0);
1460 record_alignment (now_seg, 1);
1465 as_bad (_("invalid instruction size selected (%d)"), width);
1471 int ignore ATTRIBUTE_UNUSED;
1474 demand_empty_rest_of_line ();
1479 int ignore ATTRIBUTE_UNUSED;
1482 demand_empty_rest_of_line ();
1487 int unused ATTRIBUTE_UNUSED;
1491 temp = get_absolute_expression ();
1496 opcode_select (temp);
1500 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1508 skip_whitespace (str);
1511 inst.error = _("Garbage following instruction");
1515 skip_past_comma (str)
1521 while ((c = *p) == ' ' || c == ',')
1524 if (c == ',' && comma++)
1532 return comma ? SUCCESS : FAIL;
1535 /* A standard register must be given at this point.
1536 Shift is the place to put it in inst.instruction.
1537 Restores input start point on err.
1538 Returns the reg#, or FAIL. */
1540 reg_required_here (str, shift)
1544 static char buff [128]; /* XXX */
1546 char * start = *str;
1548 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1551 inst.instruction |= reg << shift;
1555 /* Restore the start point, we may have got a reg of the wrong class. */
1558 /* In the few cases where we might be able to accept something else
1559 this error can be overridden. */
1560 sprintf (buff, _("Register expected, not '%.100s'"), start);
1567 psr_required_here (str, cpsr, spsr)
1573 char * start = *str;
1574 psr = arm_psr_parse (str);
1576 if (psr == cpsr || psr == spsr)
1579 inst.instruction |= 1 << 22;
1584 /* In the few cases where we might be able to accept something else
1585 this error can be overridden. */
1586 inst.error = _("<psr(f)> expected");
1588 /* Restore the start point. */
1594 co_proc_number (str)
1597 int processor, pchar;
1599 skip_whitespace (* str);
1601 /* The data sheet seems to imply that just a number on its own is valid
1602 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1604 if (**str == 'p' || **str == 'P')
1608 if (pchar >= '0' && pchar <= '9')
1610 processor = pchar - '0';
1611 if (**str >= '0' && **str <= '9')
1613 processor = processor * 10 + *(*str)++ - '0';
1616 inst.error = _("Illegal co-processor number");
1623 inst.error = _("Bad or missing co-processor number");
1627 inst.instruction |= processor << 8;
1632 cp_opc_expr (str, where, length)
1639 skip_whitespace (* str);
1641 memset (&expr, '\0', sizeof (expr));
1643 if (my_get_expression (&expr, str))
1645 if (expr.X_op != O_constant)
1647 inst.error = _("bad or missing expression");
1651 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1653 inst.error = _("immediate co-processor expression too large");
1657 inst.instruction |= expr.X_add_number << where;
1662 cp_reg_required_here (str, where)
1667 char * start = *str;
1669 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1672 inst.instruction |= reg << where;
1676 /* In the few cases where we might be able to accept something else
1677 this error can be overridden. */
1678 inst.error = _("Co-processor register expected");
1680 /* Restore the start point. */
1686 fp_reg_required_here (str, where)
1691 char * start = *str;
1693 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1696 inst.instruction |= reg << where;
1700 /* In the few cases where we might be able to accept something else
1701 this error can be overridden. */
1702 inst.error = _("Floating point register expected");
1704 /* Restore the start point. */
1710 cp_address_offset (str)
1715 skip_whitespace (* str);
1717 if (! is_immediate_prefix (**str))
1719 inst.error = _("immediate expression expected");
1725 if (my_get_expression (& inst.reloc.exp, str))
1728 if (inst.reloc.exp.X_op == O_constant)
1730 offset = inst.reloc.exp.X_add_number;
1734 inst.error = _("co-processor address must be word aligned");
1738 if (offset > 1023 || offset < -1023)
1740 inst.error = _("offset too large");
1745 inst.instruction |= INDEX_UP;
1749 inst.instruction |= offset >> 2;
1752 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1758 cp_address_required_here (str)
1770 skip_whitespace (p);
1772 if ((reg = reg_required_here (& p, 16)) == FAIL)
1775 skip_whitespace (p);
1781 if (skip_past_comma (& p) == SUCCESS)
1784 write_back = WRITE_BACK;
1788 inst.error = _("pc may not be used in post-increment");
1792 if (cp_address_offset (& p) == FAIL)
1796 pre_inc = PRE_INDEX | INDEX_UP;
1800 /* '['Rn, #expr']'[!] */
1802 if (skip_past_comma (& p) == FAIL)
1804 inst.error = _("pre-indexed expression expected");
1808 pre_inc = PRE_INDEX;
1810 if (cp_address_offset (& p) == FAIL)
1813 skip_whitespace (p);
1817 inst.error = _("missing ]");
1821 skip_whitespace (p);
1827 inst.error = _("pc may not be used with write-back");
1832 write_back = WRITE_BACK;
1838 if (my_get_expression (&inst.reloc.exp, &p))
1841 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1842 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
1843 inst.reloc.pc_rel = 1;
1844 inst.instruction |= (REG_PC << 16);
1845 pre_inc = PRE_INDEX;
1848 inst.instruction |= write_back | pre_inc;
1856 unsigned long flags;
1858 /* Do nothing really. */
1859 inst.instruction |= flags; /* This is pointless. */
1867 unsigned long flags;
1869 /* Only one syntax. */
1870 skip_whitespace (str);
1872 if (reg_required_here (&str, 12) == FAIL)
1874 inst.error = BAD_ARGS;
1878 if (skip_past_comma (&str) == FAIL
1879 || psr_required_here (& str, CPSR_ALL, SPSR_ALL) == FAIL)
1881 inst.error = _("<psr> expected");
1885 inst.instruction |= flags;
1890 /* Three possible forms: "<psr>, Rm", "<psrf>, Rm", "<psrf>, #expression". */
1894 unsigned long flags;
1898 skip_whitespace (str);
1900 if (psr_required_here (&str, CPSR_ALL, SPSR_ALL) == SUCCESS)
1902 inst.instruction |= PSR_ALL;
1904 /* Sytax should be "<psr>, Rm" */
1905 if (skip_past_comma (&str) == FAIL
1906 || (reg = reg_required_here (&str, 0)) == FAIL)
1908 inst.error = BAD_ARGS;
1914 if (psr_required_here (& str, CPSR_FLG, SPSR_FLG) == SUCCESS)
1915 inst.instruction |= PSR_FLAGS;
1916 else if (psr_required_here (& str, CPSR_CTL, SPSR_CTL) == SUCCESS)
1917 inst.instruction |= PSR_CONTROL;
1920 inst.error = BAD_ARGS;
1924 if (skip_past_comma (&str) == FAIL)
1926 inst.error = BAD_ARGS;
1930 /* Syntax could be "<psrf>, rm", "<psrf>, #expression" */
1932 if ((reg = reg_required_here (& str, 0)) != FAIL)
1934 /* Immediate expression. */
1935 else if (is_immediate_prefix (* str))
1940 if (my_get_expression (& inst.reloc.exp, & str))
1942 inst.error = _("Register or shift expression expected");
1946 if (inst.reloc.exp.X_add_symbol)
1948 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
1949 inst.reloc.pc_rel = 0;
1953 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
1954 if (value == (unsigned) FAIL)
1956 inst.error = _("Invalid constant");
1960 inst.instruction |= value;
1963 flags |= INST_IMMEDIATE;
1967 inst.error = _("Error: unrecognised syntax for second argument to msr instruction");
1973 inst.instruction |= flags;
1978 /* Long Multiply Parser
1979 UMULL RdLo, RdHi, Rm, Rs
1980 SMULL RdLo, RdHi, Rm, Rs
1981 UMLAL RdLo, RdHi, Rm, Rs
1982 SMLAL RdLo, RdHi, Rm, Rs
1985 do_mull (str, flags)
1987 unsigned long flags;
1989 int rdlo, rdhi, rm, rs;
1991 /* Only one format "rdlo, rdhi, rm, rs" */
1992 skip_whitespace (str);
1994 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
1996 inst.error = BAD_ARGS;
2000 if (skip_past_comma (&str) == FAIL
2001 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2003 inst.error = BAD_ARGS;
2007 if (skip_past_comma (&str) == FAIL
2008 || (rm = reg_required_here (&str, 0)) == FAIL)
2010 inst.error = BAD_ARGS;
2014 /* rdhi, rdlo and rm must all be different */
2015 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2016 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2018 if (skip_past_comma (&str) == FAIL
2019 || (rs = reg_required_here (&str, 8)) == FAIL)
2021 inst.error = BAD_ARGS;
2025 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2027 inst.error = BAD_PC;
2031 inst.instruction |= flags;
2039 unsigned long flags;
2043 /* Only one format "rd, rm, rs" */
2044 skip_whitespace (str);
2046 if ((rd = reg_required_here (&str, 16)) == FAIL)
2048 inst.error = BAD_ARGS;
2054 inst.error = BAD_PC;
2058 if (skip_past_comma (&str) == FAIL
2059 || (rm = reg_required_here (&str, 0)) == FAIL)
2061 inst.error = BAD_ARGS;
2067 inst.error = BAD_PC;
2072 as_tsktsk (_("rd and rm should be different in mul"));
2074 if (skip_past_comma (&str) == FAIL
2075 || (rm = reg_required_here (&str, 8)) == FAIL)
2077 inst.error = BAD_ARGS;
2083 inst.error = BAD_PC;
2087 inst.instruction |= flags;
2095 unsigned long flags;
2099 /* Only one format "rd, rm, rs, rn" */
2100 skip_whitespace (str);
2102 if ((rd = reg_required_here (&str, 16)) == FAIL)
2104 inst.error = BAD_ARGS;
2110 inst.error = BAD_PC;
2114 if (skip_past_comma (&str) == FAIL
2115 || (rm = reg_required_here (&str, 0)) == FAIL)
2117 inst.error = BAD_ARGS;
2123 inst.error = BAD_PC;
2128 as_tsktsk (_("rd and rm should be different in mla"));
2130 if (skip_past_comma (&str) == FAIL
2131 || (rd = reg_required_here (&str, 8)) == FAIL
2132 || skip_past_comma (&str) == FAIL
2133 || (rm = reg_required_here (&str, 12)) == FAIL)
2135 inst.error = BAD_ARGS;
2139 if (rd == REG_PC || rm == REG_PC)
2141 inst.error = BAD_PC;
2145 inst.instruction |= flags;
2150 /* Returns the index into fp_values of a floating point number, or -1 if
2151 not in the table. */
2153 my_get_float_expression (str)
2156 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2162 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2163 /* Look for a raw floating point number */
2164 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2165 && (is_end_of_line [(int)(*save_in)] || *save_in == '\0'))
2167 for (i = 0; i < NUM_FLOAT_VALS; i++)
2169 for (j = 0; j < MAX_LITTLENUMS; j++)
2171 if (words[j] != fp_values[i][j])
2175 if (j == MAX_LITTLENUMS)
2183 /* Try and parse a more complex expression, this will probably fail
2184 unless the code uses a floating point prefix (eg "0f") */
2185 save_in = input_line_pointer;
2186 input_line_pointer = *str;
2187 if (expression (&exp) == absolute_section
2188 && exp.X_op == O_big
2189 && exp.X_add_number < 0)
2191 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2193 if (gen_to_words (words, 5, (long)15) == 0)
2195 for (i = 0; i < NUM_FLOAT_VALS; i++)
2197 for (j = 0; j < MAX_LITTLENUMS; j++)
2199 if (words[j] != fp_values[i][j])
2203 if (j == MAX_LITTLENUMS)
2205 *str = input_line_pointer;
2206 input_line_pointer = save_in;
2213 *str = input_line_pointer;
2214 input_line_pointer = save_in;
2218 /* Return true if anything in the expression is a bignum */
2220 walk_no_bignums (sp)
2223 if (symbol_get_value_expression (sp)->X_op == O_big)
2226 if (symbol_get_value_expression (sp)->X_add_symbol)
2228 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2229 || (symbol_get_value_expression (sp)->X_op_symbol
2230 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2237 my_get_expression (ep, str)
2244 save_in = input_line_pointer;
2245 input_line_pointer = *str;
2246 seg = expression (ep);
2249 if (seg != absolute_section
2250 && seg != text_section
2251 && seg != data_section
2252 && seg != bss_section
2253 && seg != undefined_section)
2255 inst.error = _("bad_segment");
2256 *str = input_line_pointer;
2257 input_line_pointer = save_in;
2262 /* Get rid of any bignums now, so that we don't generate an error for which
2263 we can't establish a line number later on. Big numbers are never valid
2264 in instructions, which is where this routine is always called. */
2265 if (ep->X_op == O_big
2266 || (ep->X_add_symbol
2267 && (walk_no_bignums (ep->X_add_symbol)
2269 && walk_no_bignums (ep->X_op_symbol)))))
2271 inst.error = _("Invalid constant");
2272 *str = input_line_pointer;
2273 input_line_pointer = save_in;
2277 *str = input_line_pointer;
2278 input_line_pointer = save_in;
2282 /* unrestrict should be one if <shift> <register> is permitted for this
2286 decode_shift (str, unrestrict)
2290 struct asm_shift * shft;
2294 skip_whitespace (* str);
2296 for (p = *str; isalpha (*p); p++)
2301 inst.error = _("Shift expression expected");
2307 shft = (struct asm_shift *) hash_find (arm_shift_hsh, *str);
2311 if (!strncmp (*str, "rrx", 3)
2312 || !strncmp (*str, "RRX", 3))
2315 inst.instruction |= shft->value;
2319 skip_whitespace (p);
2321 if (unrestrict && reg_required_here (&p, 8) != FAIL)
2323 inst.instruction |= shft->value | SHIFT_BY_REG;
2327 else if (is_immediate_prefix (* p))
2331 if (my_get_expression (&inst.reloc.exp, &p))
2334 /* Validate some simple #expressions */
2335 if (inst.reloc.exp.X_op == O_constant)
2337 unsigned num = inst.reloc.exp.X_add_number;
2339 /* Reject operations greater than 32, or lsl #32 */
2340 if (num > 32 || (num == 32 && shft->value == 0))
2342 inst.error = _("Invalid immediate shift");
2346 /* Shifts of zero should be converted to lsl (which is zero)*/
2353 /* Shifts of 32 are encoded as 0, for those shifts that
2358 inst.instruction |= (num << 7) | shft->value;
2363 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2364 inst.reloc.pc_rel = 0;
2365 inst.instruction |= shft->value;
2371 inst.error = unrestrict ? _("shift requires register or #expression")
2372 : _("shift requires #expression");
2378 inst.error = _("Shift expression expected");
2382 /* Do those data_ops which can take a negative immediate constant */
2383 /* by altering the instuction. A bit of a hack really */
2387 by inverting the second operand, and
2390 by negating the second operand.
2393 negate_data_op (instruction, value)
2394 unsigned long * instruction;
2395 unsigned long value;
2398 unsigned long negated, inverted;
2400 negated = validate_immediate (-value);
2401 inverted = validate_immediate (~value);
2403 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2407 case OPCODE_SUB: /* ADD <-> SUB */
2408 new_inst = OPCODE_ADD;
2413 new_inst = OPCODE_SUB;
2417 case OPCODE_CMP: /* CMP <-> CMN */
2418 new_inst = OPCODE_CMN;
2423 new_inst = OPCODE_CMP;
2427 /* Now Inverted ops */
2428 case OPCODE_MOV: /* MOV <-> MVN */
2429 new_inst = OPCODE_MVN;
2434 new_inst = OPCODE_MOV;
2438 case OPCODE_AND: /* AND <-> BIC */
2439 new_inst = OPCODE_BIC;
2444 new_inst = OPCODE_AND;
2448 case OPCODE_ADC: /* ADC <-> SBC */
2449 new_inst = OPCODE_SBC;
2454 new_inst = OPCODE_ADC;
2458 /* We cannot do anything */
2463 if (value == (unsigned) FAIL)
2466 *instruction &= OPCODE_MASK;
2467 *instruction |= new_inst << DATA_OP_SHIFT;
2478 skip_whitespace (* str);
2480 if (reg_required_here (str, 0) != FAIL)
2482 if (skip_past_comma (str) == SUCCESS)
2483 /* Shift operation on register. */
2484 return decode_shift (str, NO_SHIFT_RESTRICT);
2490 /* Immediate expression */
2491 if (is_immediate_prefix (**str))
2496 if (my_get_expression (&inst.reloc.exp, str))
2499 if (inst.reloc.exp.X_add_symbol)
2501 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2502 inst.reloc.pc_rel = 0;
2506 if (skip_past_comma (str) == SUCCESS)
2508 /* #x, y -- ie explicit rotation by Y */
2509 if (my_get_expression (&expr, str))
2512 if (expr.X_op != O_constant)
2514 inst.error = _("Constant expression expected");
2518 /* Rotate must be a multiple of 2 */
2519 if (((unsigned) expr.X_add_number) > 30
2520 || (expr.X_add_number & 1) != 0
2521 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2523 inst.error = _("Invalid constant");
2526 inst.instruction |= INST_IMMEDIATE;
2527 inst.instruction |= inst.reloc.exp.X_add_number;
2528 inst.instruction |= expr.X_add_number << 7;
2532 /* Implicit rotation, select a suitable one */
2533 value = validate_immediate (inst.reloc.exp.X_add_number);
2537 /* Can't be done, perhaps the code reads something like
2538 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok */
2539 if ((value = negate_data_op (&inst.instruction,
2540 inst.reloc.exp.X_add_number))
2543 inst.error = _("Invalid constant");
2548 inst.instruction |= value;
2551 inst.instruction |= INST_IMMEDIATE;
2556 inst.error = _("Register or shift expression expected");
2565 skip_whitespace (* str);
2567 if (fp_reg_required_here (str, 0) != FAIL)
2571 /* Immediate expression */
2572 if (*((*str)++) == '#')
2578 skip_whitespace (* str);
2580 /* First try and match exact strings, this is to guarantee that
2581 some formats will work even for cross assembly */
2583 for (i = 0; fp_const[i]; i++)
2585 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2589 *str += strlen (fp_const[i]);
2590 if (is_end_of_line[(int)**str] || **str == '\0')
2592 inst.instruction |= i + 8;
2599 /* Just because we didn't get a match doesn't mean that the
2600 constant isn't valid, just that it is in a format that we
2601 don't automatically recognize. Try parsing it with
2602 the standard expression routines. */
2603 if ((i = my_get_float_expression (str)) >= 0)
2605 inst.instruction |= i + 8;
2609 inst.error = _("Invalid floating point immediate expression");
2612 inst.error = _("Floating point register or immediate expression expected");
2618 do_arit (str, flags)
2620 unsigned long flags;
2622 skip_whitespace (str);
2624 if (reg_required_here (&str, 12) == FAIL
2625 || skip_past_comma (&str) == FAIL
2626 || reg_required_here (&str, 16) == FAIL
2627 || skip_past_comma (&str) == FAIL
2628 || data_op2 (&str) == FAIL)
2631 inst.error = BAD_ARGS;
2635 inst.instruction |= flags;
2643 unsigned long flags;
2645 /* This is a pseudo-op of the form "adr rd, label" to be converted
2646 into a relative address of the form "add rd, pc, #label-.-8". */
2647 skip_whitespace (str);
2649 if (reg_required_here (&str, 12) == FAIL
2650 || skip_past_comma (&str) == FAIL
2651 || my_get_expression (&inst.reloc.exp, &str))
2654 inst.error = BAD_ARGS;
2658 /* Frag hacking will turn this into a sub instruction if the offset turns
2659 out to be negative. */
2660 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2661 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2662 inst.reloc.pc_rel = 1;
2663 inst.instruction |= flags;
2669 do_adrl (str, flags)
2671 unsigned long flags;
2673 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2674 into a relative address of the form:
2675 add rd, pc, #low(label-.-8)"
2676 add rd, rd, #high(label-.-8)" */
2678 skip_whitespace (str);
2680 if (reg_required_here (& str, 12) == FAIL
2681 || skip_past_comma (& str) == FAIL
2682 || my_get_expression (& inst.reloc.exp, & str))
2685 inst.error = BAD_ARGS;
2691 /* Frag hacking will turn this into a sub instruction if the offset turns
2692 out to be negative. */
2693 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2694 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2695 inst.reloc.pc_rel = 1;
2696 inst.instruction |= flags;
2697 inst.size = INSN_SIZE * 2;
2705 unsigned long flags;
2707 skip_whitespace (str);
2709 if (reg_required_here (&str, 16) == FAIL)
2712 inst.error = BAD_ARGS;
2716 if (skip_past_comma (&str) == FAIL
2717 || data_op2 (&str) == FAIL)
2720 inst.error = BAD_ARGS;
2724 inst.instruction |= flags;
2725 if ((flags & 0x0000f000) == 0)
2726 inst.instruction |= CONDS_BIT;
2735 unsigned long flags;
2737 skip_whitespace (str);
2739 if (reg_required_here (&str, 12) == FAIL)
2742 inst.error = BAD_ARGS;
2746 if (skip_past_comma (&str) == FAIL
2747 || data_op2 (&str) == FAIL)
2750 inst.error = BAD_ARGS;
2754 inst.instruction |= flags;
2760 ldst_extend (str, hwse)
2771 if (my_get_expression (& inst.reloc.exp, str))
2774 if (inst.reloc.exp.X_op == O_constant)
2776 int value = inst.reloc.exp.X_add_number;
2778 if ((hwse && (value < -255 || value > 255))
2779 || (value < -4095 || value > 4095))
2781 inst.error = _("address offset too large");
2791 /* Halfword and signextension instructions have the
2792 immediate value split across bits 11..8 and bits 3..0 */
2794 inst.instruction |= add | HWOFFSET_IMM | ((value >> 4) << 8) | (value & 0xF);
2796 inst.instruction |= add | value;
2802 inst.instruction |= HWOFFSET_IMM;
2803 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
2806 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
2807 inst.reloc.pc_rel = 0;
2812 add = 0; /* and fall through */
2814 (*str)++; /* and fall through */
2816 if (reg_required_here (str, 0) == FAIL)
2820 inst.instruction |= add;
2823 inst.instruction |= add | OFFSET_REG;
2824 if (skip_past_comma (str) == SUCCESS)
2825 return decode_shift (str, SHIFT_RESTRICT);
2833 do_ldst (str, flags)
2835 unsigned long flags;
2842 /* This is not ideal, but it is the simplest way of dealing with the
2843 ARM7T halfword instructions (since they use a different
2844 encoding, but the same mnemonic): */
2845 halfword = (flags & 0x80000000) != 0;
2848 /* This is actually a load/store of a halfword, or a
2849 signed-extension load */
2850 if ((cpu_variant & ARM_HALFWORD) == 0)
2853 = _("Processor does not support halfwords or signed bytes");
2857 inst.instruction = (inst.instruction & COND_MASK)
2858 | (flags & ~COND_MASK);
2863 skip_whitespace (str);
2865 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
2868 inst.error = BAD_ARGS;
2872 if (skip_past_comma (& str) == FAIL)
2874 inst.error = _("Address expected");
2884 skip_whitespace (str);
2886 if ((reg = reg_required_here (&str, 16)) == FAIL)
2889 /* Conflicts can occur on stores as well as loads. */
2890 conflict_reg = (conflict_reg == reg);
2892 skip_whitespace (str);
2898 if (skip_past_comma (&str) == SUCCESS)
2900 /* [Rn],... (post inc) */
2901 if (ldst_extend (&str, halfword) == FAIL)
2904 as_warn (_("%s register same as write-back base"),
2905 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2911 inst.instruction |= HWOFFSET_IMM;
2913 skip_whitespace (str);
2918 as_warn (_("%s register same as write-back base"),
2919 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2921 inst.instruction |= WRITE_BACK;
2925 if (! (flags & TRANS_BIT))
2932 if (skip_past_comma (&str) == FAIL)
2934 inst.error = _("pre-indexed expression expected");
2939 if (ldst_extend (&str, halfword) == FAIL)
2942 skip_whitespace (str);
2946 inst.error = _("missing ]");
2950 skip_whitespace (str);
2955 as_warn (_("%s register same as write-back base"),
2956 (inst.instruction & LOAD_BIT) ? _("destination") : _("source") );
2958 inst.instruction |= WRITE_BACK;
2962 else if (*str == '=')
2964 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
2967 skip_whitespace (str);
2969 if (my_get_expression (&inst.reloc.exp, &str))
2972 if (inst.reloc.exp.X_op != O_constant
2973 && inst.reloc.exp.X_op != O_symbol)
2975 inst.error = _("Constant expression expected");
2979 if (inst.reloc.exp.X_op == O_constant
2980 && (value = validate_immediate(inst.reloc.exp.X_add_number)) != FAIL)
2982 /* This can be done with a mov instruction */
2983 inst.instruction &= LITERAL_MASK;
2984 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
2985 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
2991 /* Insert into literal pool */
2992 if (add_to_lit_pool () == FAIL)
2995 inst.error = _("literal pool insertion failed");
2999 /* Change the instruction exp to point to the pool */
3002 inst.instruction |= HWOFFSET_IMM;
3003 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3006 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3007 inst.reloc.pc_rel = 1;
3008 inst.instruction |= (REG_PC << 16);
3014 if (my_get_expression (&inst.reloc.exp, &str))
3019 inst.instruction |= HWOFFSET_IMM;
3020 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3023 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3025 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust */
3027 inst.reloc.pc_rel = 1;
3028 inst.instruction |= (REG_PC << 16);
3032 if (pre_inc && (flags & TRANS_BIT))
3033 inst.error = _("Pre-increment instruction with translate");
3035 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3048 /* We come back here if we get ranges concatenated by '+' or '|' */
3063 skip_whitespace (str);
3065 if ((reg = reg_required_here (& str, -1)) == FAIL)
3074 inst.error = _("Bad range in register list");
3078 for (i = cur_reg + 1; i < reg; i++)
3080 if (range & (1 << i))
3082 (_("Warning: Duplicated register (r%d) in register list"),
3090 if (range & (1 << reg))
3091 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3093 else if (reg <= cur_reg)
3094 as_tsktsk (_("Warning: Register range not in ascending order"));
3098 } while (skip_past_comma (&str) != FAIL
3099 || (in_range = 1, *str++ == '-'));
3101 skip_whitespace (str);
3105 inst.error = _("Missing `}'");
3113 if (my_get_expression (&expr, &str))
3116 if (expr.X_op == O_constant)
3118 if (expr.X_add_number
3119 != (expr.X_add_number & 0x0000ffff))
3121 inst.error = _("invalid register mask");
3125 if ((range & expr.X_add_number) != 0)
3127 int regno = range & expr.X_add_number;
3130 regno = (1 << regno) - 1;
3132 (_("Warning: Duplicated register (r%d) in register list"),
3136 range |= expr.X_add_number;
3140 if (inst.reloc.type != 0)
3142 inst.error = _("expression too complex");
3146 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3147 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3148 inst.reloc.pc_rel = 0;
3152 skip_whitespace (str);
3154 if (*str == '|' || *str == '+')
3159 } while (another_range);
3166 do_ldmstm (str, flags)
3168 unsigned long flags;
3173 skip_whitespace (str);
3175 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3178 if (base_reg == REG_PC)
3180 inst.error = _("r15 not allowed as base register");
3184 skip_whitespace (str);
3188 flags |= WRITE_BACK;
3192 if (skip_past_comma (&str) == FAIL
3193 || (range = reg_list (&str)) == FAIL)
3196 inst.error = BAD_ARGS;
3203 flags |= LDM_TYPE_2_OR_3;
3206 inst.instruction |= flags | range;
3214 unsigned long flags;
3216 skip_whitespace (str);
3218 /* Allow optional leading '#'. */
3219 if (is_immediate_prefix (*str))
3222 if (my_get_expression (& inst.reloc.exp, & str))
3225 inst.reloc.type = BFD_RELOC_ARM_SWI;
3226 inst.reloc.pc_rel = 0;
3227 inst.instruction |= flags;
3235 do_swap (str, flags)
3237 unsigned long flags;
3241 skip_whitespace (str);
3243 if ((reg = reg_required_here (&str, 12)) == FAIL)
3248 inst.error = _("r15 not allowed in swap");
3252 if (skip_past_comma (&str) == FAIL
3253 || (reg = reg_required_here (&str, 0)) == FAIL)
3256 inst.error = BAD_ARGS;
3262 inst.error = _("r15 not allowed in swap");
3266 if (skip_past_comma (&str) == FAIL
3269 inst.error = BAD_ARGS;
3273 skip_whitespace (str);
3275 if ((reg = reg_required_here (&str, 16)) == FAIL)
3280 inst.error = BAD_PC;
3284 skip_whitespace (str);
3288 inst.error = _("missing ]");
3292 inst.instruction |= flags;
3298 do_branch (str, flags)
3300 unsigned long flags ATTRIBUTE_UNUSED;
3302 if (my_get_expression (&inst.reloc.exp, &str))
3309 /* ScottB: February 5, 1998 */
3310 /* Check to see of PLT32 reloc required for the instruction. */
3312 /* arm_parse_reloc() works on input_line_pointer.
3313 We actually want to parse the operands to the branch instruction
3314 passed in 'str'. Save the input pointer and restore it later. */
3315 save_in = input_line_pointer;
3316 input_line_pointer = str;
3317 if (inst.reloc.exp.X_op == O_symbol
3319 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3321 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3322 inst.reloc.pc_rel = 0;
3323 /* Modify str to point to after parsed operands, otherwise
3324 end_of_line() will complain about the (PLT) left in str. */
3325 str = input_line_pointer;
3329 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3330 inst.reloc.pc_rel = 1;
3332 input_line_pointer = save_in;
3335 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3336 inst.reloc.pc_rel = 1;
3337 #endif /* OBJ_ELF */
3346 unsigned long flags ATTRIBUTE_UNUSED;
3350 skip_whitespace (str);
3352 if ((reg = reg_required_here (&str, 0)) == FAIL)
3354 inst.error = BAD_ARGS;
3359 inst.error = BAD_PC;
3367 unsigned long flags ATTRIBUTE_UNUSED;
3369 /* Co-processor data operation.
3370 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3371 skip_whitespace (str);
3373 if (co_proc_number (&str) == FAIL)
3376 inst.error = BAD_ARGS;
3380 if (skip_past_comma (&str) == FAIL
3381 || cp_opc_expr (&str, 20,4) == FAIL)
3384 inst.error = BAD_ARGS;
3388 if (skip_past_comma (&str) == FAIL
3389 || cp_reg_required_here (&str, 12) == FAIL)
3392 inst.error = BAD_ARGS;
3396 if (skip_past_comma (&str) == FAIL
3397 || cp_reg_required_here (&str, 16) == FAIL)
3400 inst.error = BAD_ARGS;
3404 if (skip_past_comma (&str) == FAIL
3405 || cp_reg_required_here (&str, 0) == FAIL)
3408 inst.error = BAD_ARGS;
3412 if (skip_past_comma (&str) == SUCCESS)
3414 if (cp_opc_expr (&str, 5, 3) == FAIL)
3417 inst.error = BAD_ARGS;
3427 do_lstc (str, flags)
3429 unsigned long flags;
3431 /* Co-processor register load/store.
3432 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3434 skip_whitespace (str);
3436 if (co_proc_number (&str) == FAIL)
3439 inst.error = BAD_ARGS;
3443 if (skip_past_comma (&str) == FAIL
3444 || cp_reg_required_here (&str, 12) == FAIL)
3447 inst.error = BAD_ARGS;
3451 if (skip_past_comma (&str) == FAIL
3452 || cp_address_required_here (&str) == FAIL)
3455 inst.error = BAD_ARGS;
3459 inst.instruction |= flags;
3465 do_co_reg (str, flags)
3467 unsigned long flags;
3469 /* Co-processor register transfer.
3470 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3472 skip_whitespace (str);
3474 if (co_proc_number (&str) == FAIL)
3477 inst.error = BAD_ARGS;
3481 if (skip_past_comma (&str) == FAIL
3482 || cp_opc_expr (&str, 21, 3) == FAIL)
3485 inst.error = BAD_ARGS;
3489 if (skip_past_comma (&str) == FAIL
3490 || reg_required_here (&str, 12) == FAIL)
3493 inst.error = BAD_ARGS;
3497 if (skip_past_comma (&str) == FAIL
3498 || cp_reg_required_here (&str, 16) == FAIL)
3501 inst.error = BAD_ARGS;
3505 if (skip_past_comma (&str) == FAIL
3506 || cp_reg_required_here (&str, 0) == FAIL)
3509 inst.error = BAD_ARGS;
3513 if (skip_past_comma (&str) == SUCCESS)
3515 if (cp_opc_expr (&str, 5, 3) == FAIL)
3518 inst.error = BAD_ARGS;
3524 inst.error = BAD_COND;
3532 do_fp_ctrl (str, flags)
3534 unsigned long flags ATTRIBUTE_UNUSED;
3536 /* FP control registers.
3537 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3539 skip_whitespace (str);
3541 if (reg_required_here (&str, 12) == FAIL)
3544 inst.error = BAD_ARGS;
3553 do_fp_ldst (str, flags)
3555 unsigned long flags ATTRIBUTE_UNUSED;
3557 skip_whitespace (str);
3559 switch (inst.suffix)
3564 inst.instruction |= CP_T_X;
3567 inst.instruction |= CP_T_Y;
3570 inst.instruction |= CP_T_X | CP_T_Y;
3576 if (fp_reg_required_here (&str, 12) == FAIL)
3579 inst.error = BAD_ARGS;
3583 if (skip_past_comma (&str) == FAIL
3584 || cp_address_required_here (&str) == FAIL)
3587 inst.error = BAD_ARGS;
3595 do_fp_ldmstm (str, flags)
3597 unsigned long flags;
3601 skip_whitespace (str);
3603 if (fp_reg_required_here (&str, 12) == FAIL)
3606 inst.error = BAD_ARGS;
3610 /* Get Number of registers to transfer */
3611 if (skip_past_comma (&str) == FAIL
3612 || my_get_expression (&inst.reloc.exp, &str))
3615 inst.error = _("constant expression expected");
3619 if (inst.reloc.exp.X_op != O_constant)
3621 inst.error = _("Constant value required for number of registers");
3625 num_regs = inst.reloc.exp.X_add_number;
3627 if (num_regs < 1 || num_regs > 4)
3629 inst.error = _("number of registers must be in the range [1:4]");
3636 inst.instruction |= CP_T_X;
3639 inst.instruction |= CP_T_Y;
3642 inst.instruction |= CP_T_Y | CP_T_X;
3656 /* The instruction specified "ea" or "fd", so we can only accept
3657 [Rn]{!}. The instruction does not really support stacking or
3658 unstacking, so we have to emulate these by setting appropriate
3659 bits and offsets. */
3660 if (skip_past_comma (&str) == FAIL
3664 inst.error = BAD_ARGS;
3669 skip_whitespace (str);
3671 if ((reg = reg_required_here (&str, 16)) == FAIL)
3674 skip_whitespace (str);
3678 inst.error = BAD_ARGS;
3689 inst.error = _("R15 not allowed as base register with write-back");
3696 if (flags & CP_T_Pre)
3699 offset = 3 * num_regs;
3705 /* Post-increment */
3709 offset = 3 * num_regs;
3713 /* No write-back, so convert this into a standard pre-increment
3714 instruction -- aesthetically more pleasing. */
3715 flags = CP_T_Pre | CP_T_UD;
3720 inst.instruction |= flags | offset;
3722 else if (skip_past_comma (&str) == FAIL
3723 || cp_address_required_here (&str) == FAIL)
3726 inst.error = BAD_ARGS;
3734 do_fp_dyadic (str, flags)
3736 unsigned long flags;
3738 skip_whitespace (str);
3740 switch (inst.suffix)
3745 inst.instruction |= 0x00000080;
3748 inst.instruction |= 0x00080000;
3754 if (fp_reg_required_here (&str, 12) == FAIL)
3757 inst.error = BAD_ARGS;
3761 if (skip_past_comma (&str) == FAIL
3762 || fp_reg_required_here (&str, 16) == FAIL)
3765 inst.error = BAD_ARGS;
3769 if (skip_past_comma (&str) == FAIL
3770 || fp_op2 (&str) == FAIL)
3773 inst.error = BAD_ARGS;
3777 inst.instruction |= flags;
3783 do_fp_monadic (str, flags)
3785 unsigned long flags;
3787 skip_whitespace (str);
3789 switch (inst.suffix)
3794 inst.instruction |= 0x00000080;
3797 inst.instruction |= 0x00080000;
3803 if (fp_reg_required_here (&str, 12) == FAIL)
3806 inst.error = BAD_ARGS;
3810 if (skip_past_comma (&str) == FAIL
3811 || fp_op2 (&str) == FAIL)
3814 inst.error = BAD_ARGS;
3818 inst.instruction |= flags;
3824 do_fp_cmp (str, flags)
3826 unsigned long flags;
3828 skip_whitespace (str);
3830 if (fp_reg_required_here (&str, 16) == FAIL)
3833 inst.error = BAD_ARGS;
3837 if (skip_past_comma (&str) == FAIL
3838 || fp_op2 (&str) == FAIL)
3841 inst.error = BAD_ARGS;
3845 inst.instruction |= flags;
3851 do_fp_from_reg (str, flags)
3853 unsigned long flags;
3855 skip_whitespace (str);
3857 switch (inst.suffix)
3862 inst.instruction |= 0x00000080;
3865 inst.instruction |= 0x00080000;
3871 if (fp_reg_required_here (&str, 16) == FAIL)
3874 inst.error = BAD_ARGS;
3878 if (skip_past_comma (&str) == FAIL
3879 || reg_required_here (&str, 12) == FAIL)
3882 inst.error = BAD_ARGS;
3886 inst.instruction |= flags;
3892 do_fp_to_reg (str, flags)
3894 unsigned long flags;
3896 skip_whitespace (str);
3898 if (reg_required_here (&str, 12) == FAIL)
3901 if (skip_past_comma (&str) == FAIL
3902 || fp_reg_required_here (&str, 0) == FAIL)
3905 inst.error = BAD_ARGS;
3909 inst.instruction |= flags;
3914 /* Thumb specific routines */
3916 /* Parse and validate that a register is of the right form, this saves
3917 repeated checking of this information in many similar cases.
3918 Unlike the 32-bit case we do not insert the register into the opcode
3919 here, since the position is often unknown until the full instruction
3922 thumb_reg (strp, hi_lo)
3928 if ((reg = reg_required_here (strp, -1)) == FAIL)
3936 inst.error = _("lo register required");
3944 inst.error = _("hi register required");
3956 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
3959 thumb_add_sub (str, subtract)
3963 int Rd, Rs, Rn = FAIL;
3965 skip_whitespace (str);
3967 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
3968 || skip_past_comma (&str) == FAIL)
3971 inst.error = BAD_ARGS;
3975 if (is_immediate_prefix (*str))
3979 if (my_get_expression (&inst.reloc.exp, &str))
3984 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
3987 if (skip_past_comma (&str) == FAIL)
3989 /* Two operand format, shuffle the registers and pretend there
3994 else if (is_immediate_prefix (*str))
3997 if (my_get_expression (&inst.reloc.exp, &str))
4000 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4004 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4005 for the latter case, EXPR contains the immediate that was found. */
4008 /* All register format. */
4009 if (Rd > 7 || Rs > 7 || Rn > 7)
4013 inst.error = _("dest and source1 must be the same register");
4017 /* Can't do this for SUB */
4020 inst.error = _("subtract valid only on lo regs");
4024 inst.instruction = (T_OPCODE_ADD_HI
4025 | (Rd > 7 ? THUMB_H1 : 0)
4026 | (Rn > 7 ? THUMB_H2 : 0));
4027 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4031 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4032 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4037 /* Immediate expression, now things start to get nasty. */
4039 /* First deal with HI regs, only very restricted cases allowed:
4040 Adjusting SP, and using PC or SP to get an address. */
4041 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4042 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4044 inst.error = _("invalid Hi register with immediate");
4048 if (inst.reloc.exp.X_op != O_constant)
4050 /* Value isn't known yet, all we can do is store all the fragments
4051 we know about in the instruction and let the reloc hacking
4053 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4054 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4058 int offset = inst.reloc.exp.X_add_number;
4068 /* Quick check, in case offset is MIN_INT */
4071 inst.error = _("immediate value out of range");
4080 if (offset & ~0x1fc)
4082 inst.error = _("invalid immediate value for stack adjust");
4085 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4086 inst.instruction |= offset >> 2;
4088 else if (Rs == REG_PC || Rs == REG_SP)
4091 || (offset & ~0x3fc))
4093 inst.error = _("invalid immediate for address calculation");
4096 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4098 inst.instruction |= (Rd << 8) | (offset >> 2);
4104 inst.error = _("immediate value out of range");
4107 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4108 inst.instruction |= (Rd << 8) | offset;
4114 inst.error = _("immediate value out of range");
4117 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4118 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4127 thumb_shift (str, shift)
4131 int Rd, Rs, Rn = FAIL;
4133 skip_whitespace (str);
4135 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4136 || skip_past_comma (&str) == FAIL)
4139 inst.error = BAD_ARGS;
4143 if (is_immediate_prefix (*str))
4145 /* Two operand immediate format, set Rs to Rd. */
4148 if (my_get_expression (&inst.reloc.exp, &str))
4153 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4156 if (skip_past_comma (&str) == FAIL)
4158 /* Two operand format, shuffle the registers and pretend there
4163 else if (is_immediate_prefix (*str))
4166 if (my_get_expression (&inst.reloc.exp, &str))
4169 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4173 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4174 for the latter case, EXPR contains the immediate that was found. */
4180 inst.error = _("source1 and dest must be same register");
4186 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4187 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4188 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4191 inst.instruction |= Rd | (Rn << 3);
4197 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4198 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4199 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4202 if (inst.reloc.exp.X_op != O_constant)
4204 /* Value isn't known yet, create a dummy reloc and let reloc
4205 hacking fix it up */
4207 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4211 unsigned shift_value = inst.reloc.exp.X_add_number;
4213 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4215 inst.error = _("Invalid immediate for shift");
4219 /* Shifts of zero are handled by converting to LSL */
4220 if (shift_value == 0)
4221 inst.instruction = T_OPCODE_LSL_I;
4223 /* Shifts of 32 are encoded as a shift of zero */
4224 if (shift_value == 32)
4227 inst.instruction |= shift_value << 6;
4230 inst.instruction |= Rd | (Rs << 3);
4237 thumb_mov_compare (str, move)
4243 skip_whitespace (str);
4245 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4246 || skip_past_comma (&str) == FAIL)
4249 inst.error = BAD_ARGS;
4253 if (is_immediate_prefix (*str))
4256 if (my_get_expression (&inst.reloc.exp, &str))
4259 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4264 if (Rs < 8 && Rd < 8)
4266 if (move == THUMB_MOVE)
4267 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4268 since a MOV instruction produces unpredictable results */
4269 inst.instruction = T_OPCODE_ADD_I3;
4271 inst.instruction = T_OPCODE_CMP_LR;
4272 inst.instruction |= Rd | (Rs << 3);
4276 if (move == THUMB_MOVE)
4277 inst.instruction = T_OPCODE_MOV_HR;
4279 inst.instruction = T_OPCODE_CMP_HR;
4282 inst.instruction |= THUMB_H1;
4285 inst.instruction |= THUMB_H2;
4287 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4294 inst.error = _("only lo regs allowed with immediate");
4298 if (move == THUMB_MOVE)
4299 inst.instruction = T_OPCODE_MOV_I8;
4301 inst.instruction = T_OPCODE_CMP_I8;
4303 inst.instruction |= Rd << 8;
4305 if (inst.reloc.exp.X_op != O_constant)
4306 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4309 unsigned value = inst.reloc.exp.X_add_number;
4313 inst.error = _("invalid immediate");
4317 inst.instruction |= value;
4325 thumb_load_store (str, load_store, size)
4330 int Rd, Rb, Ro = FAIL;
4332 skip_whitespace (str);
4334 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4335 || skip_past_comma (&str) == FAIL)
4338 inst.error = BAD_ARGS;
4345 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4348 if (skip_past_comma (&str) != FAIL)
4350 if (is_immediate_prefix (*str))
4353 if (my_get_expression (&inst.reloc.exp, &str))
4356 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4361 inst.reloc.exp.X_op = O_constant;
4362 inst.reloc.exp.X_add_number = 0;
4367 inst.error = _("expected ']'");
4372 else if (*str == '=')
4374 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op */
4377 skip_whitespace (str);
4379 if (my_get_expression (& inst.reloc.exp, & str))
4384 if ( inst.reloc.exp.X_op != O_constant
4385 && inst.reloc.exp.X_op != O_symbol)
4387 inst.error = "Constant expression expected";
4391 if (inst.reloc.exp.X_op == O_constant
4392 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4394 /* This can be done with a mov instruction */
4396 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4397 inst.instruction |= inst.reloc.exp.X_add_number;
4401 /* Insert into literal pool */
4402 if (add_to_lit_pool () == FAIL)
4405 inst.error = "literal pool insertion failed";
4409 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4410 inst.reloc.pc_rel = 1;
4411 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4412 inst.reloc.exp.X_add_number += 4; /* Adjust ARM pipeline offset to Thumb */
4418 if (my_get_expression (&inst.reloc.exp, &str))
4421 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4422 inst.reloc.pc_rel = 1;
4423 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset */
4424 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4429 if (Rb == REG_PC || Rb == REG_SP)
4431 if (size != THUMB_WORD)
4433 inst.error = _("byte or halfword not valid for base register");
4436 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4438 inst.error = _("R15 based store not allowed");
4441 else if (Ro != FAIL)
4443 inst.error = _("Invalid base register for register offset");
4448 inst.instruction = T_OPCODE_LDR_PC;
4449 else if (load_store == THUMB_LOAD)
4450 inst.instruction = T_OPCODE_LDR_SP;
4452 inst.instruction = T_OPCODE_STR_SP;
4454 inst.instruction |= Rd << 8;
4455 if (inst.reloc.exp.X_op == O_constant)
4457 unsigned offset = inst.reloc.exp.X_add_number;
4459 if (offset & ~0x3fc)
4461 inst.error = _("invalid offset");
4465 inst.instruction |= offset >> 2;
4468 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4472 inst.error = _("invalid base register in load/store");
4475 else if (Ro == FAIL)
4477 /* Immediate offset */
4478 if (size == THUMB_WORD)
4479 inst.instruction = (load_store == THUMB_LOAD
4480 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4481 else if (size == THUMB_HALFWORD)
4482 inst.instruction = (load_store == THUMB_LOAD
4483 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4485 inst.instruction = (load_store == THUMB_LOAD
4486 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4488 inst.instruction |= Rd | (Rb << 3);
4490 if (inst.reloc.exp.X_op == O_constant)
4492 unsigned offset = inst.reloc.exp.X_add_number;
4494 if (offset & ~(0x1f << size))
4496 inst.error = _("Invalid offset");
4499 inst.instruction |= (offset >> size) << 6;
4502 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4506 /* Register offset */
4507 if (size == THUMB_WORD)
4508 inst.instruction = (load_store == THUMB_LOAD
4509 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4510 else if (size == THUMB_HALFWORD)
4511 inst.instruction = (load_store == THUMB_LOAD
4512 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4514 inst.instruction = (load_store == THUMB_LOAD
4515 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4517 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4532 /* Handle the Format 4 instructions that do not have equivalents in other
4533 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4541 skip_whitespace (str);
4543 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4544 || skip_past_comma (&str) == FAIL
4545 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4547 inst.error = BAD_ARGS;
4551 if (skip_past_comma (&str) != FAIL)
4553 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4554 (It isn't allowed for CMP either, but that isn't handled by this
4556 if (inst.instruction == T_OPCODE_TST
4557 || inst.instruction == T_OPCODE_CMN
4558 || inst.instruction == T_OPCODE_NEG
4559 || inst.instruction == T_OPCODE_MVN)
4561 inst.error = BAD_ARGS;
4565 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4570 inst.error = _("dest and source1 one must be the same register");
4576 if (inst.instruction == T_OPCODE_MUL
4578 as_tsktsk (_("Rs and Rd must be different in MUL"));
4580 inst.instruction |= Rd | (Rs << 3);
4588 thumb_add_sub (str, 0);
4595 thumb_shift (str, THUMB_ASR);
4602 if (my_get_expression (&inst.reloc.exp, &str))
4604 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4605 inst.reloc.pc_rel = 1;
4613 if (my_get_expression (&inst.reloc.exp, &str))
4615 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4616 inst.reloc.pc_rel = 1;
4620 /* Find the real, Thumb encoded start of a Thumb function. */
4623 find_real_start (symbolP)
4627 const char * name = S_GET_NAME (symbolP);
4628 symbolS * new_target;
4630 /* This definiton must agree with the one in gcc/config/arm/thumb.c */
4631 #define STUB_NAME ".real_start_of"
4636 /* Names that start with '.' are local labels, not function entry points.
4637 The compiler may generate BL instructions to these labels because it
4638 needs to perform a branch to a far away location. */
4642 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4643 sprintf (real_start, "%s%s", STUB_NAME, name);
4645 new_target = symbol_find (real_start);
4647 if (new_target == NULL)
4649 as_warn ("Failed to find real start of function: %s\n", name);
4650 new_target = symbolP;
4663 if (my_get_expression (& inst.reloc.exp, & str))
4666 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4667 inst.reloc.pc_rel = 1;
4670 /* If the destination of the branch is a defined symbol which does not have
4671 the THUMB_FUNC attribute, then we must be calling a function which has
4672 the (interfacearm) attribute. We look for the Thumb entry point to that
4673 function and change the branch to refer to that function instead. */
4674 if ( inst.reloc.exp.X_op == O_symbol
4675 && inst.reloc.exp.X_add_symbol != NULL
4676 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4677 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4678 inst.reloc.exp.X_add_symbol = find_real_start (inst.reloc.exp.X_add_symbol);
4687 skip_whitespace (str);
4689 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4692 /* This sets THUMB_H2 from the top bit of reg. */
4693 inst.instruction |= reg << 3;
4695 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4696 should cause the alignment to be checked once it is known. This is
4697 because BX PC only works if the instruction is word aligned. */
4706 thumb_mov_compare (str, THUMB_COMPARE);
4716 skip_whitespace (str);
4718 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4722 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4726 if (skip_past_comma (&str) == FAIL
4727 || (range = reg_list (&str)) == FAIL)
4730 inst.error = BAD_ARGS;
4734 if (inst.reloc.type != BFD_RELOC_NONE)
4736 /* This really doesn't seem worth it. */
4737 inst.reloc.type = BFD_RELOC_NONE;
4738 inst.error = _("Expression too complex");
4744 inst.error = _("only lo-regs valid in load/store multiple");
4748 inst.instruction |= (Rb << 8) | range;
4756 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
4763 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
4770 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
4779 skip_whitespace (str);
4781 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4782 || skip_past_comma (&str) == FAIL
4784 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4785 || skip_past_comma (&str) == FAIL
4786 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4790 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
4794 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4802 thumb_shift (str, THUMB_LSL);
4809 thumb_shift (str, THUMB_LSR);
4816 thumb_mov_compare (str, THUMB_MOVE);
4825 skip_whitespace (str);
4827 if ((range = reg_list (&str)) == FAIL)
4830 inst.error = BAD_ARGS;
4834 if (inst.reloc.type != BFD_RELOC_NONE)
4836 /* This really doesn't seem worth it. */
4837 inst.reloc.type = BFD_RELOC_NONE;
4838 inst.error = _("Expression too complex");
4844 if ((inst.instruction == T_OPCODE_PUSH
4845 && (range & ~0xff) == 1 << REG_LR)
4846 || (inst.instruction == T_OPCODE_POP
4847 && (range & ~0xff) == 1 << REG_PC))
4849 inst.instruction |= THUMB_PP_PC_LR;
4854 inst.error = _("invalid register list to push/pop instruction");
4859 inst.instruction |= range;
4867 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
4874 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
4881 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
4888 thumb_add_sub (str, 1);
4895 skip_whitespace (str);
4897 if (my_get_expression (&inst.reloc.exp, &str))
4900 inst.reloc.type = BFD_RELOC_ARM_SWI;
4911 /* This is a pseudo-op of the form "adr rd, label" to be converted
4912 into a relative address of the form "add rd, pc, #label-.-4". */
4913 skip_whitespace (str);
4915 /* Store Rd in temporary location inside instruction. */
4916 if ((reg = reg_required_here (&str, 4)) == FAIL
4917 || (reg > 7) /* For Thumb reg must be r0..r7. */
4918 || skip_past_comma (&str) == FAIL
4919 || my_get_expression (&inst.reloc.exp, &str))
4922 inst.error = BAD_ARGS;
4926 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4927 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
4928 inst.reloc.pc_rel = 1;
4929 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
4938 int len = strlen (reg_table[entry].name) + 2;
4939 char * buf = (char *) xmalloc (len);
4940 char * buf2 = (char *) xmalloc (len);
4943 #ifdef REGISTER_PREFIX
4944 buf[i++] = REGISTER_PREFIX;
4947 strcpy (buf + i, reg_table[entry].name);
4949 for (i = 0; buf[i]; i++)
4950 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
4954 hash_insert (arm_reg_hsh, buf, (PTR) ®_table[entry]);
4955 hash_insert (arm_reg_hsh, buf2, (PTR) ®_table[entry]);
4959 insert_reg_alias (str, regnum)
4963 struct reg_entry *new =
4964 (struct reg_entry *)xmalloc (sizeof (struct reg_entry));
4965 char *name = xmalloc (strlen (str) + 1);
4969 new->number = regnum;
4971 hash_insert (arm_reg_hsh, name, (PTR) new);
4975 set_constant_flonums ()
4979 for (i = 0; i < NUM_FLOAT_VALS; i++)
4980 if (atof_ieee ((char *)fp_const[i], 'x', fp_values[i]) == NULL)
4990 if ( (arm_ops_hsh = hash_new ()) == NULL
4991 || (arm_tops_hsh = hash_new ()) == NULL
4992 || (arm_cond_hsh = hash_new ()) == NULL
4993 || (arm_shift_hsh = hash_new ()) == NULL
4994 || (arm_reg_hsh = hash_new ()) == NULL
4995 || (arm_psr_hsh = hash_new ()) == NULL)
4996 as_fatal (_("Virtual memory exhausted"));
4998 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
4999 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5000 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5001 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5002 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5003 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5004 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5005 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5006 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5007 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5009 for (i = 0; reg_table[i].name; i++)
5012 set_constant_flonums ();
5014 #if defined OBJ_COFF || defined OBJ_ELF
5016 unsigned int flags = 0;
5018 /* Set the flags in the private structure. */
5019 if (uses_apcs_26) flags |= F_APCS26;
5020 if (support_interwork) flags |= F_INTERWORK;
5021 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5022 if (pic_code) flags |= F_PIC;
5023 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5025 bfd_set_private_flags (stdoutput, flags);
5029 /* Record the CPU type as well. */
5030 switch (cpu_variant & ARM_CPU_MASK)
5033 mach = bfd_mach_arm_2;
5036 case ARM_3: /* Also ARM_250. */
5037 mach = bfd_mach_arm_2a;
5041 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5042 mach = bfd_mach_arm_4;
5045 case ARM_7: /* Also ARM_6. */
5046 mach = bfd_mach_arm_3;
5050 /* Catch special cases. */
5051 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5053 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5054 mach = bfd_mach_arm_5T;
5055 else if (cpu_variant & ARM_EXT_V5)
5056 mach = bfd_mach_arm_5;
5057 else if (cpu_variant & ARM_THUMB)
5058 mach = bfd_mach_arm_4T;
5059 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5060 mach = bfd_mach_arm_4;
5061 else if (cpu_variant & ARM_LONGMUL)
5062 mach = bfd_mach_arm_3M;
5065 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5068 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5069 for use in the a.out file, and stores them in the array pointed to by buf.
5070 This knows about the endian-ness of the target machine and does
5071 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5072 2 (short) and 4 (long) Floating numbers are put out as a series of
5073 LITTLENUMS (shorts, here at least). */
5075 md_number_to_chars (buf, val, n)
5080 if (target_big_endian)
5081 number_to_chars_bigendian (buf, val, n);
5083 number_to_chars_littleendian (buf, val, n);
5087 md_chars_to_number (buf, n)
5092 unsigned char * where = (unsigned char *) buf;
5094 if (target_big_endian)
5099 result |= (*where++ & 255);
5107 result |= (where[n] & 255);
5114 /* Turn a string in input_line_pointer into a floating point constant
5115 of type TYPE, and store the appropriate bytes in *litP. The number
5116 of LITTLENUMS emitted is stored in *sizeP . An error message is
5117 returned, or NULL on OK.
5119 Note that fp constants aren't represent in the normal way on the ARM.
5120 In big endian mode, things are as expected. However, in little endian
5121 mode fp constants are big-endian word-wise, and little-endian byte-wise
5122 within the words. For example, (double) 1.1 in big endian mode is
5123 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5124 the byte sequence 99 99 f1 3f 9a 99 99 99.
5126 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5129 md_atof (type, litP, sizeP)
5135 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5167 return _("Bad call to MD_ATOF()");
5170 t = atof_ieee (input_line_pointer, type, words);
5172 input_line_pointer = t;
5175 if (target_big_endian)
5177 for (i = 0; i < prec; i++)
5179 md_number_to_chars (litP, (valueT) words[i], 2);
5185 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5186 8 byte float the order is 1 0 3 2. */
5187 for (i = 0; i < prec; i += 2)
5189 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5190 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5198 /* The knowledge of the PC's pipeline offset is built into the insns themselves. */
5200 md_pcrel_from (fixP)
5204 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5205 && fixP->fx_subsy == NULL)
5208 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5210 /* PC relative addressing on the Thumb is slightly odd
5211 as the bottom two bits of the PC are forced to zero
5212 for the calculation. */
5213 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5217 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5218 so we un-adjust here to compensate for the accomodation. */
5219 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5221 return fixP->fx_where + fixP->fx_frag->fr_address;
5225 /* Round up a section size to the appropriate boundary. */
5227 md_section_align (segment, size)
5228 segT segment ATTRIBUTE_UNUSED;
5234 /* Round all sects to multiple of 4 */
5235 return (size + 3) & ~3;
5239 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE. Otherwise
5240 we have no need to default values of symbols. */
5244 md_undefined_symbol (name)
5248 if (name[0] == '_' && name[1] == 'G'
5249 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5253 if (symbol_find (name))
5254 as_bad ("GOT already in the symbol table");
5256 GOT_symbol = symbol_new (name, undefined_section,
5257 (valueT)0, & zero_address_frag);
5267 /* arm_reg_parse () := if it looks like a register, return its token and
5268 advance the pointer. */
5272 register char ** ccp;
5274 char * start = * ccp;
5277 struct reg_entry * reg;
5279 #ifdef REGISTER_PREFIX
5280 if (*start != REGISTER_PREFIX)
5285 #ifdef OPTIONAL_REGISTER_PREFIX
5286 if (*p == OPTIONAL_REGISTER_PREFIX)
5290 if (!isalpha (*p) || !is_name_beginner (*p))
5294 while (isalpha (c) || isdigit (c) || c == '_')
5298 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5312 register char ** ccp;
5314 char * start = * ccp;
5317 CONST struct asm_psr * psr;
5321 while (isalpha (c) || c == '_')
5325 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
5338 md_apply_fix3 (fixP, val, seg)
5343 offsetT value = * val;
5345 unsigned int newimm;
5348 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5349 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5351 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5353 /* Note whether this will delete the relocation. */
5354 #if 0 /* patch from REarnshaw to JDavis (disabled for the moment, since it doesn't work fully) */
5355 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5358 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5362 /* If this symbol is in a different section then we need to leave it for
5363 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5364 so we have to undo it's effects here. */
5367 if (fixP->fx_addsy != NULL
5368 && S_IS_DEFINED (fixP->fx_addsy)
5369 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5372 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5373 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5377 value += md_pcrel_from (fixP);
5381 fixP->fx_addnumber = value; /* Remember value for emit_reloc. */
5383 switch (fixP->fx_r_type)
5385 case BFD_RELOC_ARM_IMMEDIATE:
5386 newimm = validate_immediate (value);
5387 temp = md_chars_to_number (buf, INSN_SIZE);
5389 /* If the instruction will fail, see if we can fix things up by
5390 changing the opcode. */
5391 if (newimm == (unsigned int) FAIL
5392 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5394 as_bad_where (fixP->fx_file, fixP->fx_line,
5395 _("invalid constant (%lx) after fixup"),
5396 (unsigned long) value);
5400 newimm |= (temp & 0xfffff000);
5401 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5404 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5406 unsigned int highpart = 0;
5407 unsigned int newinsn = 0xe1a00000; /* nop */
5408 newimm = validate_immediate (value);
5409 temp = md_chars_to_number (buf, INSN_SIZE);
5411 /* If the instruction will fail, see if we can fix things up by
5412 changing the opcode. */
5413 if (newimm == (unsigned int) FAIL
5414 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5416 /* No ? OK - try using two ADD instructions to generate the value. */
5417 newimm = validate_immediate_twopart (value, & highpart);
5419 /* Yes - then make sure that the second instruction is also an add. */
5420 if (newimm != (unsigned int) FAIL)
5422 /* Still No ? Try using a negated value. */
5423 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5424 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5425 /* Otherwise - give up. */
5428 as_bad_where (fixP->fx_file, fixP->fx_line,
5429 _("Unable to compute ADRL instructions for PC offset of 0x%x"), value);
5433 /* Replace the first operand in the 2nd instruction (which is the PC)
5434 with the destination register. We have already added in the PC in the
5435 first instruction and we do not want to do it again. */
5436 newinsn &= ~ 0xf0000;
5437 newinsn |= ((newinsn & 0x0f000) << 4);
5440 newimm |= (temp & 0xfffff000);
5441 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5443 highpart |= (newinsn & 0xfffff000);
5444 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5448 case BFD_RELOC_ARM_OFFSET_IMM:
5454 if (validate_offset_imm (value, 0) == FAIL)
5456 as_bad_where (fixP->fx_file, fixP->fx_line,
5457 _("bad immediate value for offset (%ld)"), (long) value);
5461 newval = md_chars_to_number (buf, INSN_SIZE);
5462 newval &= 0xff7ff000;
5463 newval |= value | (sign ? INDEX_UP : 0);
5464 md_number_to_chars (buf, newval, INSN_SIZE);
5467 case BFD_RELOC_ARM_OFFSET_IMM8:
5468 case BFD_RELOC_ARM_HWLITERAL:
5474 if (validate_offset_imm (value, 1) == FAIL)
5476 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5477 as_bad_where (fixP->fx_file, fixP->fx_line,
5478 _("invalid literal constant: pool needs to be closer"));
5480 as_bad (_("bad immediate value for half-word offset (%ld)"),
5485 newval = md_chars_to_number (buf, INSN_SIZE);
5486 newval &= 0xff7ff0f0;
5487 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5488 md_number_to_chars (buf, newval, INSN_SIZE);
5491 case BFD_RELOC_ARM_LITERAL:
5497 if (validate_offset_imm (value, 0) == FAIL)
5499 as_bad_where (fixP->fx_file, fixP->fx_line,
5500 _("invalid literal constant: pool needs to be closer"));
5504 newval = md_chars_to_number (buf, INSN_SIZE);
5505 newval &= 0xff7ff000;
5506 newval |= value | (sign ? INDEX_UP : 0);
5507 md_number_to_chars (buf, newval, INSN_SIZE);
5510 case BFD_RELOC_ARM_SHIFT_IMM:
5511 newval = md_chars_to_number (buf, INSN_SIZE);
5512 if (((unsigned long) value) > 32
5514 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5516 as_bad_where (fixP->fx_file, fixP->fx_line,
5517 _("shift expression is too large"));
5522 newval &= ~0x60; /* Shifts of zero must be done as lsl */
5523 else if (value == 32)
5525 newval &= 0xfffff07f;
5526 newval |= (value & 0x1f) << 7;
5527 md_number_to_chars (buf, newval , INSN_SIZE);
5530 case BFD_RELOC_ARM_SWI:
5531 if (arm_data->thumb_mode)
5533 if (((unsigned long) value) > 0xff)
5534 as_bad_where (fixP->fx_file, fixP->fx_line,
5535 _("Invalid swi expression"));
5536 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5538 md_number_to_chars (buf, newval, THUMB_SIZE);
5542 if (((unsigned long) value) > 0x00ffffff)
5543 as_bad_where (fixP->fx_file, fixP->fx_line,
5544 _("Invalid swi expression"));
5545 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5547 md_number_to_chars (buf, newval , INSN_SIZE);
5551 case BFD_RELOC_ARM_MULTI:
5552 if (((unsigned long) value) > 0xffff)
5553 as_bad_where (fixP->fx_file, fixP->fx_line,
5554 _("Invalid expression in load/store multiple"));
5555 newval = value | md_chars_to_number (buf, INSN_SIZE);
5556 md_number_to_chars (buf, newval, INSN_SIZE);
5559 case BFD_RELOC_ARM_PCREL_BRANCH:
5560 newval = md_chars_to_number (buf, INSN_SIZE);
5562 /* Sign-extend a 24-bit number. */
5563 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5567 value = fixP->fx_offset;
5570 /* We are going to store value (shifted right by two) in the
5571 instruction, in a 24 bit, signed field. Thus we need to check
5572 that none of the top 8 bits of the shifted value (top 7 bits of
5573 the unshifted, unsigned value) are set, or that they are all set. */
5574 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5575 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5578 /* Normally we would be stuck at this point, since we cannot store
5579 the absolute address that is the destination of the branch in the
5580 24 bits of the branch instruction. If however, we happen to know
5581 that the destination of the branch is in the same section as the
5582 branch instruciton itself, then we can compute the relocation for
5583 ourselves and not have to bother the linker with it.
5585 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5586 because I have not worked out how to do this for OBJ_COFF or
5589 && fixP->fx_addsy != NULL
5590 && S_IS_DEFINED (fixP->fx_addsy)
5591 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5593 /* Get pc relative value to go into the branch. */
5596 /* Permit a backward branch provided that enough bits are set.
5597 Allow a forwards branch, provided that enough bits are clear. */
5598 if ((value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5599 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5603 if (! fixP->fx_done)
5605 as_bad_where (fixP->fx_file, fixP->fx_line,
5606 _("gas can't handle same-section branch dest >= 0x04000000"));
5610 value += SEXT24 (newval);
5612 if ((value & ~ ((offsetT) 0xffffff)) != 0
5613 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5614 as_bad_where (fixP->fx_file, fixP->fx_line,
5615 _("out of range branch"));
5617 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5618 md_number_to_chars (buf, newval, INSN_SIZE);
5621 case BFD_RELOC_ARM_PCREL_BLX:
5624 newval = md_chars_to_number (buf, INSN_SIZE);
5628 value = fixP->fx_offset;
5630 hbit = (value >> 1) & 1;
5631 value = (value >> 2) & 0x00ffffff;
5632 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5633 newval = value | (newval & 0xfe000000) | (hbit << 24);
5634 md_number_to_chars (buf, newval, INSN_SIZE);
5638 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* conditional branch */
5639 newval = md_chars_to_number (buf, THUMB_SIZE);
5641 addressT diff = (newval & 0xff) << 1;
5646 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5647 as_bad_where (fixP->fx_file, fixP->fx_line,
5648 _("Branch out of range"));
5649 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5651 md_number_to_chars (buf, newval, THUMB_SIZE);
5654 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* unconditional branch */
5655 newval = md_chars_to_number (buf, THUMB_SIZE);
5657 addressT diff = (newval & 0x7ff) << 1;
5662 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5663 as_bad_where (fixP->fx_file, fixP->fx_line,
5664 _("Branch out of range"));
5665 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5667 md_number_to_chars (buf, newval, THUMB_SIZE);
5670 case BFD_RELOC_THUMB_PCREL_BLX:
5671 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5676 newval = md_chars_to_number (buf, THUMB_SIZE);
5677 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5678 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5679 if (diff & 0x400000)
5682 value = fixP->fx_offset;
5685 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5686 as_bad_where (fixP->fx_file, fixP->fx_line,
5687 _("Branch with link out of range"));
5689 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5690 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5691 md_number_to_chars (buf, newval, THUMB_SIZE);
5692 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5697 if (fixP->fx_done || fixP->fx_pcrel)
5698 md_number_to_chars (buf, value, 1);
5700 else if (!target_oabi)
5702 value = fixP->fx_offset;
5703 md_number_to_chars (buf, value, 1);
5709 if (fixP->fx_done || fixP->fx_pcrel)
5710 md_number_to_chars (buf, value, 2);
5712 else if (!target_oabi)
5714 value = fixP->fx_offset;
5715 md_number_to_chars (buf, value, 2);
5721 case BFD_RELOC_ARM_GOT32:
5722 case BFD_RELOC_ARM_GOTOFF:
5723 md_number_to_chars (buf, 0, 4);
5729 if (fixP->fx_done || fixP->fx_pcrel)
5730 md_number_to_chars (buf, value, 4);
5732 else if (!target_oabi)
5734 value = fixP->fx_offset;
5735 md_number_to_chars (buf, value, 4);
5741 case BFD_RELOC_ARM_PLT32:
5742 /* It appears the instruction is fully prepared at this point. */
5746 case BFD_RELOC_ARM_GOTPC:
5747 md_number_to_chars (buf, value, 4);
5750 case BFD_RELOC_ARM_CP_OFF_IMM:
5752 if (value < -1023 || value > 1023 || (value & 3))
5753 as_bad_where (fixP->fx_file, fixP->fx_line,
5754 _("Illegal value for co-processor offset"));
5757 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5758 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5759 md_number_to_chars (buf, newval , INSN_SIZE);
5762 case BFD_RELOC_ARM_THUMB_OFFSET:
5763 newval = md_chars_to_number (buf, THUMB_SIZE);
5764 /* Exactly what ranges, and where the offset is inserted depends on
5765 the type of instruction, we can establish this from the top 4 bits */
5766 switch (newval >> 12)
5768 case 4: /* PC load */
5769 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5770 forced to zero for these loads, so we will need to round
5771 up the offset if the instruction address is not word
5772 aligned (since the final address produced must be, and
5773 we can only describe word-aligned immediate offsets). */
5775 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
5776 as_bad_where (fixP->fx_file, fixP->fx_line,
5777 _("Invalid offset, target not word aligned (0x%08X)"),
5778 (unsigned int)(fixP->fx_frag->fr_address + fixP->fx_where + value));
5780 if ((value + 2) & ~0x3fe)
5781 as_bad_where (fixP->fx_file, fixP->fx_line,
5782 _("Invalid offset, value too big (0x%08X)"), value);
5784 /* Round up, since pc will be rounded down. */
5785 newval |= (value + 2) >> 2;
5788 case 9: /* SP load/store */
5790 as_bad_where (fixP->fx_file, fixP->fx_line,
5791 _("Invalid offset, value too big (0x%08X)"), value);
5792 newval |= value >> 2;
5795 case 6: /* Word load/store */
5797 as_bad_where (fixP->fx_file, fixP->fx_line,
5798 _("Invalid offset, value too big (0x%08X)"), value);
5799 newval |= value << 4; /* 6 - 2 */
5802 case 7: /* Byte load/store */
5804 as_bad_where (fixP->fx_file, fixP->fx_line,
5805 _("Invalid offset, value too big (0x%08X)"), value);
5806 newval |= value << 6;
5809 case 8: /* Halfword load/store */
5811 as_bad_where (fixP->fx_file, fixP->fx_line,
5812 _("Invalid offset, value too big (0x%08X)"), value);
5813 newval |= value << 5; /* 6 - 1 */
5817 as_bad_where (fixP->fx_file, fixP->fx_line,
5818 "Unable to process relocation for thumb opcode: %lx",
5819 (unsigned long) newval);
5822 md_number_to_chars (buf, newval, THUMB_SIZE);
5825 case BFD_RELOC_ARM_THUMB_ADD:
5826 /* This is a complicated relocation, since we use it for all of
5827 the following immediate relocations:
5830 9bit ADD/SUB SP word-aligned
5831 10bit ADD PC/SP word-aligned
5833 The type of instruction being processed is encoded in the
5839 newval = md_chars_to_number (buf, THUMB_SIZE);
5841 int rd = (newval >> 4) & 0xf;
5842 int rs = newval & 0xf;
5843 int subtract = newval & 0x8000;
5848 as_bad_where (fixP->fx_file, fixP->fx_line,
5849 _("Invalid immediate for stack address calculation"));
5850 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
5851 newval |= value >> 2;
5853 else if (rs == REG_PC || rs == REG_SP)
5857 as_bad_where (fixP->fx_file, fixP->fx_line,
5858 _("Invalid immediate for address calculation (value = 0x%08lX)"),
5859 (unsigned long) value);
5860 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
5862 newval |= value >> 2;
5867 as_bad_where (fixP->fx_file, fixP->fx_line,
5868 _("Invalid 8bit immediate"));
5869 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
5870 newval |= (rd << 8) | value;
5875 as_bad_where (fixP->fx_file, fixP->fx_line,
5876 _("Invalid 3bit immediate"));
5877 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
5878 newval |= rd | (rs << 3) | (value << 6);
5881 md_number_to_chars (buf, newval , THUMB_SIZE);
5884 case BFD_RELOC_ARM_THUMB_IMM:
5885 newval = md_chars_to_number (buf, THUMB_SIZE);
5886 switch (newval >> 11)
5888 case 0x04: /* 8bit immediate MOV */
5889 case 0x05: /* 8bit immediate CMP */
5890 if (value < 0 || value > 255)
5891 as_bad_where (fixP->fx_file, fixP->fx_line,
5892 _("Invalid immediate: %ld is too large"),
5900 md_number_to_chars (buf, newval , THUMB_SIZE);
5903 case BFD_RELOC_ARM_THUMB_SHIFT:
5904 /* 5bit shift value (0..31) */
5905 if (value < 0 || value > 31)
5906 as_bad_where (fixP->fx_file, fixP->fx_line,
5907 _("Illegal Thumb shift value: %ld"), (long) value);
5908 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
5909 newval |= value << 6;
5910 md_number_to_chars (buf, newval , THUMB_SIZE);
5913 case BFD_RELOC_VTABLE_INHERIT:
5914 case BFD_RELOC_VTABLE_ENTRY:
5918 case BFD_RELOC_NONE:
5920 as_bad_where (fixP->fx_file, fixP->fx_line,
5921 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
5927 /* Translate internal representation of relocation info to BFD target
5930 tc_gen_reloc (section, fixp)
5931 asection * section ATTRIBUTE_UNUSED;
5935 bfd_reloc_code_real_type code;
5937 reloc = (arelent *) xmalloc (sizeof (arelent));
5939 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5940 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5941 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
5943 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
5945 if (fixp->fx_pcrel == 0)
5946 reloc->addend = fixp->fx_offset;
5948 reloc->addend = fixp->fx_offset = reloc->address;
5950 reloc->addend = fixp->fx_offset;
5953 switch (fixp->fx_r_type)
5958 code = BFD_RELOC_8_PCREL;
5965 code = BFD_RELOC_16_PCREL;
5972 code = BFD_RELOC_32_PCREL;
5976 case BFD_RELOC_ARM_PCREL_BRANCH:
5977 case BFD_RELOC_ARM_PCREL_BLX:
5979 case BFD_RELOC_THUMB_PCREL_BRANCH9:
5980 case BFD_RELOC_THUMB_PCREL_BRANCH12:
5981 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5982 case BFD_RELOC_THUMB_PCREL_BLX:
5983 case BFD_RELOC_VTABLE_ENTRY:
5984 case BFD_RELOC_VTABLE_INHERIT:
5985 code = fixp->fx_r_type;
5988 case BFD_RELOC_ARM_LITERAL:
5989 case BFD_RELOC_ARM_HWLITERAL:
5990 /* If this is called then the a literal has been referenced across
5991 a section boundary - possibly due to an implicit dump */
5992 as_bad_where (fixp->fx_file, fixp->fx_line,
5993 _("Literal referenced across section boundary (Implicit dump?)"));
5997 case BFD_RELOC_ARM_GOT32:
5998 case BFD_RELOC_ARM_GOTOFF:
5999 case BFD_RELOC_ARM_PLT32:
6000 code = fixp->fx_r_type;
6004 case BFD_RELOC_ARM_IMMEDIATE:
6005 as_bad_where (fixp->fx_file, fixp->fx_line,
6006 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6010 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6011 as_bad_where (fixp->fx_file, fixp->fx_line,
6012 _("ADRL used for a symbol not defined in the same file"),
6016 case BFD_RELOC_ARM_OFFSET_IMM:
6017 as_bad_where (fixp->fx_file, fixp->fx_line,
6018 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6025 switch (fixp->fx_r_type)
6027 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6028 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6029 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6030 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6031 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6032 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6033 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6034 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6035 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6036 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6037 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6038 default: type = _("<unknown>"); break;
6040 as_bad_where (fixp->fx_file, fixp->fx_line,
6041 _("Can not represent %s relocation in this object file format (%d)"),
6042 type, fixp->fx_pcrel);
6048 if (code == BFD_RELOC_32_PCREL
6050 && fixp->fx_addsy == GOT_symbol)
6052 code = BFD_RELOC_ARM_GOTPC;
6053 reloc->addend = fixp->fx_offset = reloc->address;
6057 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6059 if (reloc->howto == NULL)
6061 as_bad_where (fixp->fx_file, fixp->fx_line,
6062 _("Can not represent %s relocation in this object file format"),
6063 bfd_get_reloc_code_name (code));
6067 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6068 vtable entry to be used in the relocation's section offset. */
6069 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6070 reloc->address = fixp->fx_offset;
6076 md_estimate_size_before_relax (fragP, segtype)
6077 fragS * fragP ATTRIBUTE_UNUSED;
6078 segT segtype ATTRIBUTE_UNUSED;
6080 as_fatal (_("md_estimate_size_before_relax\n"));
6085 output_inst PARAMS ((void))
6091 as_bad (inst.error);
6095 to = frag_more (inst.size);
6097 if (thumb_mode && (inst.size > THUMB_SIZE))
6099 assert (inst.size == (2 * THUMB_SIZE));
6100 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6101 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6103 else if (inst.size > INSN_SIZE)
6105 assert (inst.size == (2 * INSN_SIZE));
6106 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6107 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6110 md_number_to_chars (to, inst.instruction, inst.size);
6112 if (inst.reloc.type != BFD_RELOC_NONE)
6113 fix_new_arm (frag_now, to - frag_now->fr_literal,
6114 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6129 /* Align the instruction.
6130 This may not be the right thing to do but ... */
6131 /* arm_align (2, 0); */
6132 listing_prev_line (); /* Defined in listing.h */
6134 /* Align the previous label if needed. */
6135 if (last_label_seen != NULL)
6137 symbol_set_frag (last_label_seen, frag_now);
6138 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6139 S_SET_SEGMENT (last_label_seen, now_seg);
6142 memset (&inst, '\0', sizeof (inst));
6143 inst.reloc.type = BFD_RELOC_NONE;
6145 skip_whitespace (str);
6147 /* Scan up to the end of the op-code, which must end in white space or
6149 for (start = p = str; *p != '\0'; p++)
6155 as_bad (_("No operator -- statement `%s'\n"), str);
6161 CONST struct thumb_opcode * opcode;
6165 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6170 /* Check that this instruction is supported for this CPU. */
6171 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6173 as_bad (_("selected processor does not support this opcode"));
6177 inst.instruction = opcode->value;
6178 inst.size = opcode->size;
6179 (*opcode->parms)(p);
6186 CONST struct asm_opcode * opcode;
6187 unsigned long cond_code;
6189 inst.size = INSN_SIZE;
6190 /* p now points to the end of the opcode, probably white space, but we
6191 have to break the opcode up in case it contains condionals and flags;
6192 keep trying with progressively smaller basic instructions until one
6193 matches, or we run out of opcode. */
6194 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6196 for (; q != str; q--)
6201 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6204 if (opcode && opcode->template)
6206 unsigned long flag_bits = 0;
6209 /* Check that this instruction is supported for this CPU. */
6210 if ((opcode->variants & cpu_variant) == 0)
6213 inst.instruction = opcode->value;
6214 if (q == p) /* Just a simple opcode. */
6216 if (opcode->comp_suffix)
6218 if (*opcode->comp_suffix != '\0')
6219 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6220 str, opcode->comp_suffix);
6222 /* Not a conditional instruction. */
6223 (*opcode->parms)(q, 0);
6227 /* A conditional instruction with default condition. */
6228 inst.instruction |= COND_ALWAYS;
6229 (*opcode->parms)(q, 0);
6235 /* Not just a simple opcode. Check if extra is a conditional. */
6239 CONST struct asm_cond *cond;
6243 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6247 if (cond->value == 0xf0000000)
6249 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6251 cond_code = cond->value;
6255 cond_code = COND_ALWAYS;
6258 cond_code = COND_ALWAYS;
6260 /* Apply the conditional, or complain it's not allowed. */
6261 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6263 /* Instruction isn't conditional */
6264 if (cond_code != COND_ALWAYS)
6266 as_bad (_("Opcode `%s' is unconditional\n"), str);
6271 /* Instruction is conditional: set the condition into it. */
6272 inst.instruction |= cond_code;
6275 /* If there is a compulsory suffix, it should come here, before
6276 any optional flags. */
6277 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6279 CONST char *s = opcode->comp_suffix;
6291 as_bad (_("Opcode `%s' must have suffix from <%s>\n"), str,
6292 opcode->comp_suffix);
6299 /* The remainder, if any should now be flags for the instruction;
6300 Scan these checking each one found with the opcode. */
6304 CONST struct asm_flg *flag = opcode->flags;
6313 for (flagno = 0; flag[flagno].template; flagno++)
6315 if (streq (r, flag[flagno].template))
6317 flag_bits |= flag[flagno].set_bits;
6323 if (! flag[flagno].template)
6330 (*opcode->parms) (p, flag_bits);
6340 /* It wasn't an instruction, but it might be a register alias of the form
6343 skip_whitespace (q);
6348 if (*q && !strncmp (q, ".req ", 4))
6351 char * copy_of_str = str;
6355 skip_whitespace (q);
6357 for (r = q; *r != '\0'; r++)
6367 regnum = arm_reg_parse (& q);
6370 reg = arm_reg_parse (& str);
6375 insert_reg_alias (str, regnum);
6377 as_warn (_("register '%s' does not exist\n"), q);
6379 else if (regnum != FAIL)
6382 as_warn (_("ignoring redefinition of register alias '%s'"),
6385 /* Do not warn about redefinitions to the same alias. */
6388 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6392 as_warn (_("ignoring incomplete .req pseuso op"));
6399 as_bad (_("bad instruction `%s'"), start);
6404 * Invocation line includes a switch not recognized by the base assembler.
6405 * See if it's a processor-specific option. These are:
6406 * Cpu variants, the arm part is optional:
6407 * -m[arm]1 Currently not supported.
6408 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6409 * -m[arm]3 Arm 3 processor
6410 * -m[arm]6[xx], Arm 6 processors
6411 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6412 * -m[arm]8[10] Arm 8 processors
6413 * -m[arm]9[20][tdmi] Arm 9 processors
6414 * -mstrongarm[110[0]] StrongARM processors
6415 * -m[arm]v[2345] Arm architectures
6416 * -mall All (except the ARM1)
6418 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6419 * -mfpe-old (No float load/store multiples)
6420 * -mno-fpu Disable all floating point instructions
6421 * Run-time endian selection:
6422 * -EB big endian cpu
6423 * -EL little endian cpu
6424 * ARM Procedure Calling Standard:
6425 * -mapcs-32 32 bit APCS
6426 * -mapcs-26 26 bit APCS
6427 * -mapcs-float Pass floats in float regs
6428 * -mapcs-reentrant Position independent code
6429 * -mthumb-interwork Code supports Arm/Thumb interworking
6430 * -moabi Old ELF ABI
6433 CONST char * md_shortopts = "m:k";
6434 struct option md_longopts[] =
6436 #ifdef ARM_BI_ENDIAN
6437 #define OPTION_EB (OPTION_MD_BASE + 0)
6438 {"EB", no_argument, NULL, OPTION_EB},
6439 #define OPTION_EL (OPTION_MD_BASE + 1)
6440 {"EL", no_argument, NULL, OPTION_EL},
6442 #define OPTION_OABI (OPTION_MD_BASE +2)
6443 {"oabi", no_argument, NULL, OPTION_OABI},
6446 {NULL, no_argument, NULL, 0}
6448 size_t md_longopts_size = sizeof (md_longopts);
6451 md_parse_option (c, arg)
6459 #ifdef ARM_BI_ENDIAN
6461 target_big_endian = 1;
6464 target_big_endian = 0;
6472 if (streq (str, "fpa10"))
6473 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6474 else if (streq (str, "fpa11"))
6475 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6476 else if (streq (str, "fpe-old"))
6477 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6483 if (streq (str, "no-fpu"))
6484 cpu_variant &= ~FPU_ALL;
6489 if (streq (str, "oabi"))
6495 /* Limit assembler to generating only Thumb instructions: */
6496 if (streq (str, "thumb"))
6498 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6499 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6502 else if (streq (str, "thumb-interwork"))
6504 if ((cpu_variant & ARM_THUMB) == 0)
6505 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6506 #if defined OBJ_COFF || defined OBJ_ELF
6507 support_interwork = true;
6515 if (streq (str, "all"))
6517 cpu_variant = ARM_ALL | FPU_ALL;
6520 #if defined OBJ_COFF || defined OBJ_ELF
6521 if (! strncmp (str, "apcs-", 5))
6523 /* GCC passes on all command line options starting "-mapcs-..."
6524 to us, so we must parse them here. */
6528 if (streq (str, "32"))
6530 uses_apcs_26 = false;
6533 else if (streq (str, "26"))
6535 uses_apcs_26 = true;
6538 else if (streq (str, "frame"))
6540 /* Stack frames are being generated - does not affect
6544 else if (streq (str, "stack-check"))
6546 /* Stack checking is being performed - does not affect
6547 linkage, but does require that the functions
6548 __rt_stkovf_split_small and __rt_stkovf_split_big be
6549 present in the final link. */
6553 else if (streq (str, "float"))
6555 /* Floating point arguments are being passed in the floating
6556 point registers. This does affect linking, since this
6557 version of the APCS is incompatible with the version that
6558 passes floating points in the integer registers. */
6560 uses_apcs_float = true;
6563 else if (streq (str, "reentrant"))
6565 /* Reentrant code has been generated. This does affect
6566 linking, since there is no point in linking reentrant/
6567 position independent code with absolute position code. */
6572 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6576 /* Strip off optional "arm" */
6577 if (! strncmp (str, "arm", 3))
6583 if (streq (str, "1"))
6584 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6590 if (streq (str, "2"))
6591 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6592 else if (streq (str, "250"))
6593 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6599 if (streq (str, "3"))
6600 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6606 switch (strtol (str, NULL, 10))
6613 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6621 switch (strtol (str, & str, 10)) /* Eat the processor name */
6634 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6640 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6644 cpu_variant |= ARM_LONGMUL;
6647 case 'f': /* fe => fp enabled cpu. */
6653 case 'c': /* Left over from 710c processor name. */
6654 case 'd': /* Debug */
6655 case 'i': /* Embedded ICE */
6656 /* Included for completeness in ARM processor naming. */
6666 if (streq (str, "8") || streq (str, "810"))
6667 cpu_variant = (cpu_variant & ~ARM_ANY)
6668 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6674 if (streq (str, "9"))
6675 cpu_variant = (cpu_variant & ~ARM_ANY)
6676 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6677 else if (streq (str, "920"))
6678 cpu_variant = (cpu_variant & ~ARM_ANY)
6679 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6680 else if (streq (str, "920t"))
6681 cpu_variant = (cpu_variant & ~ARM_ANY)
6682 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6683 else if (streq (str, "9tdmi"))
6684 cpu_variant = (cpu_variant & ~ARM_ANY)
6685 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6692 if (streq (str, "strongarm")
6693 || streq (str, "strongarm110")
6694 || streq (str, "strongarm1100"))
6695 cpu_variant = (cpu_variant & ~ARM_ANY)
6696 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6702 /* Select variant based on architecture rather than processor. */
6709 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6712 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6715 as_bad (_("Invalid architecture variant -m%s"), arg);
6721 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6725 case 'm': cpu_variant |= ARM_LONGMUL; break;
6728 as_bad (_("Invalid architecture variant -m%s"), arg);
6734 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6738 case 't': cpu_variant |= ARM_THUMB; break;
6741 as_bad (_("Invalid architecture variant -m%s"), arg);
6747 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6750 case 't': cpu_variant |= ARM_THUMB; break;
6751 case 'e': cpu_variant |= ARM_EXT_V5E; break;
6754 as_bad (_("Invalid architecture variant -m%s"), arg);
6760 as_bad (_("Invalid architecture variant -m%s"), arg);
6767 as_bad (_("Invalid processor variant -m%s"), arg);
6773 #if defined OBJ_ELF || defined OBJ_COFF
6791 ARM Specific Assembler Options:\n\
6792 -m[arm][<processor name>] select processor variant\n\
6793 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
6794 -mthumb only allow Thumb instructions\n\
6795 -mthumb-interwork mark the assembled code as supporting interworking\n\
6796 -mall allow any instruction\n\
6797 -mfpa10, -mfpa11 select floating point architecture\n\
6798 -mfpe-old don't allow floating-point multiple instructions\n\
6799 -mno-fpu don't allow any floating-point instructions.\n\
6800 -k generate PIC code.\n"));
6801 #if defined OBJ_COFF || defined OBJ_ELF
6803 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
6804 -mapcs-float floating point args are passed in FP regs\n\
6805 -mapcs-reentrant the code is position independent/reentrant\n"));
6809 -moabi support the old ELF ABI\n"));
6811 #ifdef ARM_BI_ENDIAN
6813 -EB assemble code for a big endian cpu\n\
6814 -EL assemble code for a little endian cpu\n"));
6818 /* We need to be able to fix up arbitrary expressions in some statements.
6819 This is so that we can handle symbols that are an arbitrary distance from
6820 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
6821 which returns part of an address in a form which will be valid for
6822 a data instruction. We do this by pushing the expression into a symbol
6823 in the expr_section, and creating a fix for that. */
6826 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
6835 arm_fix_data * arm_data;
6843 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
6847 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
6852 /* Mark whether the fix is to a THUMB instruction, or an ARM instruction */
6853 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
6854 new_fix->tc_fix_data = (PTR) arm_data;
6855 arm_data->thumb_mode = thumb_mode;
6861 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6863 cons_fix_new_arm (frag, where, size, exp)
6869 bfd_reloc_code_real_type type;
6874 * @@ Should look at CPU word size.
6879 type = BFD_RELOC_16;
6883 type = BFD_RELOC_32;
6886 type = BFD_RELOC_64;
6890 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
6893 /* A good place to do this, although this was probably not intended
6894 for this kind of use. We need to dump the literal pool before
6895 references are made to a null symbol pointer. */
6899 if (current_poolP == NULL)
6902 subseg_set (text_section, 0); /* Put it at the end of text section. */
6904 listing_prev_line ();
6908 arm_start_line_hook ()
6910 last_label_seen = NULL;
6914 arm_frob_label (sym)
6917 last_label_seen = sym;
6919 ARM_SET_THUMB (sym, thumb_mode);
6921 #if defined OBJ_COFF || defined OBJ_ELF
6922 ARM_SET_INTERWORK (sym, support_interwork);
6925 if (label_is_thumb_function_name)
6927 /* When the address of a Thumb function is taken the bottom
6928 bit of that address should be set. This will allow
6929 interworking between Arm and Thumb functions to work
6932 THUMB_SET_FUNC (sym, 1);
6934 label_is_thumb_function_name = false;
6938 /* Adjust the symbol table. This marks Thumb symbols as distinct from
6942 arm_adjust_symtab ()
6947 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6949 if (ARM_IS_THUMB (sym))
6951 if (THUMB_IS_FUNC (sym))
6953 /* Mark the symbol as a Thumb function. */
6954 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
6955 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
6956 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
6958 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
6959 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
6961 as_bad (_("%s: unexpected function type: %d"),
6962 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
6964 else switch (S_GET_STORAGE_CLASS (sym))
6967 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
6970 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
6973 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
6975 default: /* do nothing */
6980 if (ARM_IS_INTERWORK (sym))
6981 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
6988 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
6990 if (ARM_IS_THUMB (sym))
6992 elf_symbol_type * elf_sym;
6994 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
6995 bind = ELF_ST_BIND (elf_sym);
6997 /* If it's a .thumb_func, declare it as so,
6998 otherwise tag label as .code 16. */
6999 if (THUMB_IS_FUNC (sym))
7000 elf_sym->internal_elf_sym.st_info =
7001 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7003 elf_sym->internal_elf_sym.st_info =
7004 ELF_ST_INFO (bind, STT_ARM_16BIT);
7013 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7015 *input_line_pointer = '/';
7016 input_line_pointer += 5;
7017 *input_line_pointer = 0;
7025 arm_canonicalize_symbol_name (name)
7030 if (thumb_mode && (len = strlen (name)) > 5
7031 && streq (name + len - 5, "/data"))
7032 *(name + len - 5) = 0;
7038 arm_validate_fix (fixP)
7041 /* If the destination of the branch is a defined symbol which does not have
7042 the THUMB_FUNC attribute, then we must be calling a function which has
7043 the (interfacearm) attribute. We look for the Thumb entry point to that
7044 function and change the branch to refer to that function instead. */
7045 if ( fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7046 && fixP->fx_addsy != NULL
7047 && S_IS_DEFINED (fixP->fx_addsy)
7048 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7050 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7058 /* Relocations against Thumb function names must be left unadjusted,
7059 so that the linker can use this information to correctly set the
7060 bottom bit of their addresses. The MIPS version of this function
7061 also prevents relocations that are mips-16 specific, but I do not
7062 know why it does this.
7065 There is one other problem that ought to be addressed here, but
7066 which currently is not: Taking the address of a label (rather
7067 than a function) and then later jumping to that address. Such
7068 addresses also ought to have their bottom bit set (assuming that
7069 they reside in Thumb code), but at the moment they will not. */
7072 arm_fix_adjustable (fixP)
7075 if (fixP->fx_addsy == NULL)
7078 /* Prevent all adjustments to global symbols. */
7079 if (S_IS_EXTERN (fixP->fx_addsy))
7082 if (S_IS_WEAK (fixP->fx_addsy))
7085 if (THUMB_IS_FUNC (fixP->fx_addsy)
7086 && fixP->fx_subsy == NULL)
7089 /* We need the symbol name for the VTABLE entries */
7090 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7091 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7098 elf32_arm_target_format ()
7100 if (target_big_endian)
7102 return "elf32-bigarm-oabi";
7104 return "elf32-bigarm";
7107 return "elf32-littlearm-oabi";
7109 return "elf32-littlearm";
7113 armelf_frob_symbol (symp, puntp)
7117 elf_frob_symbol (symp, puntp);
7121 arm_force_relocation (fixp)
7124 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7125 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7126 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7127 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7128 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7129 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7135 static bfd_reloc_code_real_type
7145 bfd_reloc_code_real_type reloc;
7149 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7150 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7151 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7152 /* ScottB: Jan 30, 1998 */
7153 /* Added support for parsing "var(PLT)" branch instructions */
7154 /* generated by GCC for PLT relocs */
7155 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7156 { NULL, 0, BFD_RELOC_UNUSED }
7160 for (i = 0, ip = input_line_pointer;
7161 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7163 id[i] = tolower (*ip);
7165 for (i = 0; reloc_map[i].str; i++)
7166 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7169 input_line_pointer += reloc_map[i].len;
7171 return reloc_map[i].reloc;
7175 s_arm_elf_cons (nbytes)
7180 #ifdef md_flush_pending_output
7181 md_flush_pending_output ();
7184 if (is_it_end_of_statement ())
7186 demand_empty_rest_of_line ();
7190 #ifdef md_cons_align
7191 md_cons_align (nbytes);
7196 bfd_reloc_code_real_type reloc;
7200 if (exp.X_op == O_symbol
7201 && * input_line_pointer == '('
7202 && (reloc = arm_parse_reloc()) != BFD_RELOC_UNUSED)
7204 reloc_howto_type * howto = bfd_reloc_type_lookup (stdoutput, reloc);
7205 int size = bfd_get_reloc_size (howto);
7208 as_bad ("%s relocations do not fit in %d bytes",
7209 howto->name, nbytes);
7212 register char * p = frag_more ((int) nbytes);
7213 int offset = nbytes - size;
7215 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7220 emit_expr (& exp, (unsigned int) nbytes);
7222 while (*input_line_pointer++ == ',');
7224 input_line_pointer--; /* Put terminator back into stream. */
7225 demand_empty_rest_of_line ();
7228 #endif /* OBJ_ELF */