1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used;
136 static arm_feature_set thumb_arch_used;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26 = FALSE;
140 static int atpcs = FALSE;
141 static int support_interwork = FALSE;
142 static int uses_apcs_float = FALSE;
143 static int pic_code = FALSE;
144 static int fix_v4bx = FALSE;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated = TRUE;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax = FALSE;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set *legacy_cpu = NULL;
158 static const arm_feature_set *legacy_fpu = NULL;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set *mcpu_cpu_opt = NULL;
162 static arm_feature_set *mcpu_ext_opt = NULL;
163 static const arm_feature_set *mcpu_fpu_opt = NULL;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set *march_cpu_opt = NULL;
167 static arm_feature_set *march_ext_opt = NULL;
168 static const arm_feature_set *march_fpu_opt = NULL;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set *mfpu_opt = NULL;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default = FPU_DEFAULT;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
176 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
179 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
182 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
184 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
187 static const arm_feature_set cpu_default = CPU_DEFAULT;
190 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
191 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
192 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
198 static const arm_feature_set arm_ext_v4t_5 =
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
207 static const arm_feature_set arm_ext_v6_notm =
208 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
209 static const arm_feature_set arm_ext_v6_dsp =
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
211 static const arm_feature_set arm_ext_barrier =
212 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
213 static const arm_feature_set arm_ext_msr =
214 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
215 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
216 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
217 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
218 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
220 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
222 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
223 static const arm_feature_set arm_ext_m =
224 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
225 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
226 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
227 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
228 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
229 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
230 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
231 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
232 static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
233 static const arm_feature_set arm_ext_v8m_main =
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
235 /* Instructions in ARMv8-M only found in M profile architectures. */
236 static const arm_feature_set arm_ext_v8m_m_only =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
238 static const arm_feature_set arm_ext_v6t2_v8m =
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
240 /* Instructions shared between ARMv8-A and ARMv8-M. */
241 static const arm_feature_set arm_ext_atomics =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
244 /* DSP instructions Tag_DSP_extension refers to. */
245 static const arm_feature_set arm_ext_dsp =
246 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
248 static const arm_feature_set arm_ext_ras =
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
250 /* FP16 instructions. */
251 static const arm_feature_set arm_ext_fp16 =
252 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
253 static const arm_feature_set arm_ext_fp16_fml =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
255 static const arm_feature_set arm_ext_v8_2 =
256 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
257 static const arm_feature_set arm_ext_v8_3 =
258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
259 static const arm_feature_set arm_ext_sb =
260 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
261 static const arm_feature_set arm_ext_predres =
262 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
264 static const arm_feature_set arm_arch_any = ARM_ANY;
266 static const arm_feature_set fpu_any = FPU_ANY;
268 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
269 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
270 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
272 static const arm_feature_set arm_cext_iwmmxt2 =
273 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
274 static const arm_feature_set arm_cext_iwmmxt =
275 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
276 static const arm_feature_set arm_cext_xscale =
277 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
278 static const arm_feature_set arm_cext_maverick =
279 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
280 static const arm_feature_set fpu_fpa_ext_v1 =
281 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
282 static const arm_feature_set fpu_fpa_ext_v2 =
283 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
284 static const arm_feature_set fpu_vfp_ext_v1xd =
285 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
286 static const arm_feature_set fpu_vfp_ext_v1 =
287 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
288 static const arm_feature_set fpu_vfp_ext_v2 =
289 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
290 static const arm_feature_set fpu_vfp_ext_v3xd =
291 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
292 static const arm_feature_set fpu_vfp_ext_v3 =
293 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
294 static const arm_feature_set fpu_vfp_ext_d32 =
295 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
296 static const arm_feature_set fpu_neon_ext_v1 =
297 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
298 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
299 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
301 static const arm_feature_set fpu_vfp_fp16 =
302 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
303 static const arm_feature_set fpu_neon_ext_fma =
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
306 static const arm_feature_set fpu_vfp_ext_fma =
307 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
308 static const arm_feature_set fpu_vfp_ext_armv8 =
309 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
310 static const arm_feature_set fpu_vfp_ext_armv8xd =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
312 static const arm_feature_set fpu_neon_ext_armv8 =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
314 static const arm_feature_set fpu_crypto_ext_armv8 =
315 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
316 static const arm_feature_set crc_ext_armv8 =
317 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
318 static const arm_feature_set fpu_neon_ext_v8_1 =
319 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
320 static const arm_feature_set fpu_neon_ext_dotprod =
321 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
323 static int mfloat_abi_opt = -1;
324 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
326 static arm_feature_set selected_arch = ARM_ARCH_NONE;
327 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
329 static arm_feature_set selected_ext = ARM_ARCH_NONE;
330 /* Feature bits selected by the last -mcpu/-march or by the combination of the
331 last .cpu/.arch directive .arch_extension directives since that
333 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
334 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
335 static arm_feature_set selected_fpu = FPU_NONE;
336 /* Feature bits selected by the last .object_arch directive. */
337 static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
338 /* Must be long enough to hold any of the names in arm_cpus. */
339 static char selected_cpu_name[20];
341 extern FLONUM_TYPE generic_floating_point_number;
343 /* Return if no cpu was selected on command-line. */
345 no_cpu_selected (void)
347 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
352 static int meabi_flags = EABI_DEFAULT;
354 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
357 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
362 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
367 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
368 symbolS * GOT_symbol;
371 /* 0: assemble for ARM,
372 1: assemble for Thumb,
373 2: assemble for Thumb even though target CPU does not support thumb
375 static int thumb_mode = 0;
376 /* A value distinct from the possible values for thumb_mode that we
377 can use to record whether thumb_mode has been copied into the
378 tc_frag_data field of a frag. */
379 #define MODE_RECORDED (1 << 4)
381 /* Specifies the intrinsic IT insn behavior mode. */
382 enum implicit_it_mode
384 IMPLICIT_IT_MODE_NEVER = 0x00,
385 IMPLICIT_IT_MODE_ARM = 0x01,
386 IMPLICIT_IT_MODE_THUMB = 0x02,
387 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
389 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
391 /* If unified_syntax is true, we are processing the new unified
392 ARM/Thumb syntax. Important differences from the old ARM mode:
394 - Immediate operands do not require a # prefix.
395 - Conditional affixes always appear at the end of the
396 instruction. (For backward compatibility, those instructions
397 that formerly had them in the middle, continue to accept them
399 - The IT instruction may appear, and if it does is validated
400 against subsequent conditional affixes. It does not generate
403 Important differences from the old Thumb mode:
405 - Immediate operands do not require a # prefix.
406 - Most of the V6T2 instructions are only available in unified mode.
407 - The .N and .W suffixes are recognized and honored (it is an error
408 if they cannot be honored).
409 - All instructions set the flags if and only if they have an 's' affix.
410 - Conditional affixes may be used. They are validated against
411 preceding IT instructions. Unlike ARM mode, you cannot use a
412 conditional affix except in the scope of an IT instruction. */
414 static bfd_boolean unified_syntax = FALSE;
416 /* An immediate operand can start with #, and ld*, st*, pld operands
417 can contain [ and ]. We need to tell APP not to elide whitespace
418 before a [, which can appear as the first operand for pld.
419 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
420 const char arm_symbol_chars[] = "#[]{}";
435 enum neon_el_type type;
439 #define NEON_MAX_TYPE_ELS 4
443 struct neon_type_el el[NEON_MAX_TYPE_ELS];
447 enum it_instruction_type
452 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
453 if inside, should be the last one. */
454 NEUTRAL_IT_INSN, /* This could be either inside or outside,
455 i.e. BKPT and NOP. */
456 IT_INSN /* The IT insn has been parsed. */
459 /* The maximum number of operands we need. */
460 #define ARM_IT_MAX_OPERANDS 6
465 unsigned long instruction;
469 /* "uncond_value" is set to the value in place of the conditional field in
470 unconditional versions of the instruction, or -1 if nothing is
473 struct neon_type vectype;
474 /* This does not indicate an actual NEON instruction, only that
475 the mnemonic accepts neon-style type suffixes. */
477 /* Set to the opcode if the instruction needs relaxation.
478 Zero if the instruction is not relaxed. */
482 bfd_reloc_code_real_type type;
487 enum it_instruction_type it_insn_type;
493 struct neon_type_el vectype;
494 unsigned present : 1; /* Operand present. */
495 unsigned isreg : 1; /* Operand was a register. */
496 unsigned immisreg : 1; /* .imm field is a second register. */
497 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
498 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
499 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
500 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
501 instructions. This allows us to disambiguate ARM <-> vector insns. */
502 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
503 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
504 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
505 unsigned issingle : 1; /* Operand is VFP single-precision register. */
506 unsigned hasreloc : 1; /* Operand has relocation suffix. */
507 unsigned writeback : 1; /* Operand has trailing ! */
508 unsigned preind : 1; /* Preindexed address. */
509 unsigned postind : 1; /* Postindexed address. */
510 unsigned negative : 1; /* Index register was negated. */
511 unsigned shifted : 1; /* Shift applied to operation. */
512 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
513 } operands[ARM_IT_MAX_OPERANDS];
516 static struct arm_it inst;
518 #define NUM_FLOAT_VALS 8
520 const char * fp_const[] =
522 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
525 /* Number of littlenums required to hold an extended precision number. */
526 #define MAX_LITTLENUMS 6
528 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
538 #define CP_T_X 0x00008000
539 #define CP_T_Y 0x00400000
541 #define CONDS_BIT 0x00100000
542 #define LOAD_BIT 0x00100000
544 #define DOUBLE_LOAD_FLAG 0x00000001
548 const char * template_name;
552 #define COND_ALWAYS 0xE
556 const char * template_name;
560 struct asm_barrier_opt
562 const char * template_name;
564 const arm_feature_set arch;
567 /* The bit that distinguishes CPSR and SPSR. */
568 #define SPSR_BIT (1 << 22)
570 /* The individual PSR flag bits. */
571 #define PSR_c (1 << 16)
572 #define PSR_x (1 << 17)
573 #define PSR_s (1 << 18)
574 #define PSR_f (1 << 19)
579 bfd_reloc_code_real_type reloc;
584 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
585 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
590 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
593 /* Bits for DEFINED field in neon_typed_alias. */
594 #define NTA_HASTYPE 1
595 #define NTA_HASINDEX 2
597 struct neon_typed_alias
599 unsigned char defined;
601 struct neon_type_el eltype;
604 /* ARM register categories. This includes coprocessor numbers and various
605 architecture extensions' registers. Each entry should have an error message
606 in reg_expected_msgs below. */
634 /* Structure for a hash table entry for a register.
635 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
636 information which states whether a vector type or index is specified (for a
637 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
643 unsigned char builtin;
644 struct neon_typed_alias * neon;
647 /* Diagnostics used when we don't get a register of the expected type. */
648 const char * const reg_expected_msgs[] =
650 [REG_TYPE_RN] = N_("ARM register expected"),
651 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
652 [REG_TYPE_CN] = N_("co-processor register expected"),
653 [REG_TYPE_FN] = N_("FPA register expected"),
654 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
655 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
656 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
657 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
658 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
659 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
660 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
662 [REG_TYPE_VFC] = N_("VFP system register expected"),
663 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
664 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
665 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
666 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
667 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
668 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
669 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
670 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
671 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
672 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
673 [REG_TYPE_RNB] = N_("")
676 /* Some well known registers that we refer to directly elsewhere. */
682 /* ARM instructions take 4bytes in the object file, Thumb instructions
688 /* Basic string to match. */
689 const char * template_name;
691 /* Parameters to instruction. */
692 unsigned int operands[8];
694 /* Conditional tag - see opcode_lookup. */
695 unsigned int tag : 4;
697 /* Basic instruction code. */
698 unsigned int avalue : 28;
700 /* Thumb-format instruction code. */
703 /* Which architecture variant provides this instruction. */
704 const arm_feature_set * avariant;
705 const arm_feature_set * tvariant;
707 /* Function to call to encode instruction in ARM format. */
708 void (* aencode) (void);
710 /* Function to call to encode instruction in Thumb format. */
711 void (* tencode) (void);
714 /* Defines for various bits that we will want to toggle. */
715 #define INST_IMMEDIATE 0x02000000
716 #define OFFSET_REG 0x02000000
717 #define HWOFFSET_IMM 0x00400000
718 #define SHIFT_BY_REG 0x00000010
719 #define PRE_INDEX 0x01000000
720 #define INDEX_UP 0x00800000
721 #define WRITE_BACK 0x00200000
722 #define LDM_TYPE_2_OR_3 0x00400000
723 #define CPSI_MMOD 0x00020000
725 #define LITERAL_MASK 0xf000f000
726 #define OPCODE_MASK 0xfe1fffff
727 #define V4_STR_BIT 0x00000020
728 #define VLDR_VMOV_SAME 0x0040f000
730 #define T2_SUBS_PC_LR 0xf3de8f00
732 #define DATA_OP_SHIFT 21
733 #define SBIT_SHIFT 20
735 #define T2_OPCODE_MASK 0xfe1fffff
736 #define T2_DATA_OP_SHIFT 21
737 #define T2_SBIT_SHIFT 20
739 #define A_COND_MASK 0xf0000000
740 #define A_PUSH_POP_OP_MASK 0x0fff0000
742 /* Opcodes for pushing/poping registers to/from the stack. */
743 #define A1_OPCODE_PUSH 0x092d0000
744 #define A2_OPCODE_PUSH 0x052d0004
745 #define A2_OPCODE_POP 0x049d0004
747 /* Codes to distinguish the arithmetic instructions. */
758 #define OPCODE_CMP 10
759 #define OPCODE_CMN 11
760 #define OPCODE_ORR 12
761 #define OPCODE_MOV 13
762 #define OPCODE_BIC 14
763 #define OPCODE_MVN 15
765 #define T2_OPCODE_AND 0
766 #define T2_OPCODE_BIC 1
767 #define T2_OPCODE_ORR 2
768 #define T2_OPCODE_ORN 3
769 #define T2_OPCODE_EOR 4
770 #define T2_OPCODE_ADD 8
771 #define T2_OPCODE_ADC 10
772 #define T2_OPCODE_SBC 11
773 #define T2_OPCODE_SUB 13
774 #define T2_OPCODE_RSB 14
776 #define T_OPCODE_MUL 0x4340
777 #define T_OPCODE_TST 0x4200
778 #define T_OPCODE_CMN 0x42c0
779 #define T_OPCODE_NEG 0x4240
780 #define T_OPCODE_MVN 0x43c0
782 #define T_OPCODE_ADD_R3 0x1800
783 #define T_OPCODE_SUB_R3 0x1a00
784 #define T_OPCODE_ADD_HI 0x4400
785 #define T_OPCODE_ADD_ST 0xb000
786 #define T_OPCODE_SUB_ST 0xb080
787 #define T_OPCODE_ADD_SP 0xa800
788 #define T_OPCODE_ADD_PC 0xa000
789 #define T_OPCODE_ADD_I8 0x3000
790 #define T_OPCODE_SUB_I8 0x3800
791 #define T_OPCODE_ADD_I3 0x1c00
792 #define T_OPCODE_SUB_I3 0x1e00
794 #define T_OPCODE_ASR_R 0x4100
795 #define T_OPCODE_LSL_R 0x4080
796 #define T_OPCODE_LSR_R 0x40c0
797 #define T_OPCODE_ROR_R 0x41c0
798 #define T_OPCODE_ASR_I 0x1000
799 #define T_OPCODE_LSL_I 0x0000
800 #define T_OPCODE_LSR_I 0x0800
802 #define T_OPCODE_MOV_I8 0x2000
803 #define T_OPCODE_CMP_I8 0x2800
804 #define T_OPCODE_CMP_LR 0x4280
805 #define T_OPCODE_MOV_HR 0x4600
806 #define T_OPCODE_CMP_HR 0x4500
808 #define T_OPCODE_LDR_PC 0x4800
809 #define T_OPCODE_LDR_SP 0x9800
810 #define T_OPCODE_STR_SP 0x9000
811 #define T_OPCODE_LDR_IW 0x6800
812 #define T_OPCODE_STR_IW 0x6000
813 #define T_OPCODE_LDR_IH 0x8800
814 #define T_OPCODE_STR_IH 0x8000
815 #define T_OPCODE_LDR_IB 0x7800
816 #define T_OPCODE_STR_IB 0x7000
817 #define T_OPCODE_LDR_RW 0x5800
818 #define T_OPCODE_STR_RW 0x5000
819 #define T_OPCODE_LDR_RH 0x5a00
820 #define T_OPCODE_STR_RH 0x5200
821 #define T_OPCODE_LDR_RB 0x5c00
822 #define T_OPCODE_STR_RB 0x5400
824 #define T_OPCODE_PUSH 0xb400
825 #define T_OPCODE_POP 0xbc00
827 #define T_OPCODE_BRANCH 0xe000
829 #define THUMB_SIZE 2 /* Size of thumb instruction. */
830 #define THUMB_PP_PC_LR 0x0100
831 #define THUMB_LOAD_BIT 0x0800
832 #define THUMB2_LOAD_BIT 0x00100000
834 #define BAD_ARGS _("bad arguments to instruction")
835 #define BAD_SP _("r13 not allowed here")
836 #define BAD_PC _("r15 not allowed here")
837 #define BAD_COND _("instruction cannot be conditional")
838 #define BAD_OVERLAP _("registers may not be the same")
839 #define BAD_HIREG _("lo register required")
840 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
841 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
842 #define BAD_BRANCH _("branch must be last instruction in IT block")
843 #define BAD_NOT_IT _("instruction not allowed in IT block")
844 #define BAD_FPU _("selected FPU does not support instruction")
845 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
846 #define BAD_IT_COND _("incorrect condition in IT block")
847 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
848 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
849 #define BAD_PC_ADDRESSING \
850 _("cannot use register index with PC-relative addressing")
851 #define BAD_PC_WRITEBACK \
852 _("cannot use writeback with PC-relative addressing")
853 #define BAD_RANGE _("branch out of range")
854 #define BAD_FP16 _("selected processor does not support fp16 instruction")
855 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
856 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
858 static struct hash_control * arm_ops_hsh;
859 static struct hash_control * arm_cond_hsh;
860 static struct hash_control * arm_shift_hsh;
861 static struct hash_control * arm_psr_hsh;
862 static struct hash_control * arm_v7m_psr_hsh;
863 static struct hash_control * arm_reg_hsh;
864 static struct hash_control * arm_reloc_hsh;
865 static struct hash_control * arm_barrier_opt_hsh;
867 /* Stuff needed to resolve the label ambiguity
876 symbolS * last_label_seen;
877 static int label_is_thumb_function_name = FALSE;
879 /* Literal pool structure. Held on a per-section
880 and per-sub-section basis. */
882 #define MAX_LITERAL_POOL_SIZE 1024
883 typedef struct literal_pool
885 expressionS literals [MAX_LITERAL_POOL_SIZE];
886 unsigned int next_free_entry;
892 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
894 struct literal_pool * next;
895 unsigned int alignment;
898 /* Pointer to a linked list of literal pools. */
899 literal_pool * list_of_pools = NULL;
901 typedef enum asmfunc_states
904 WAITING_ASMFUNC_NAME,
908 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
911 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
913 static struct current_it now_it;
917 now_it_compatible (int cond)
919 return (cond & ~1) == (now_it.cc & ~1);
923 conditional_insn (void)
925 return inst.cond != COND_ALWAYS;
928 static int in_it_block (void);
930 static int handle_it_state (void);
932 static void force_automatic_it_block_close (void);
934 static void it_fsm_post_encode (void);
936 #define set_it_insn_type(type) \
939 inst.it_insn_type = type; \
940 if (handle_it_state () == FAIL) \
945 #define set_it_insn_type_nonvoid(type, failret) \
948 inst.it_insn_type = type; \
949 if (handle_it_state () == FAIL) \
954 #define set_it_insn_type_last() \
957 if (inst.cond == COND_ALWAYS) \
958 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
960 set_it_insn_type (INSIDE_IT_LAST_INSN); \
966 /* This array holds the chars that always start a comment. If the
967 pre-processor is disabled, these aren't very useful. */
968 char arm_comment_chars[] = "@";
970 /* This array holds the chars that only start a comment at the beginning of
971 a line. If the line seems to have the form '# 123 filename'
972 .line and .file directives will appear in the pre-processed output. */
973 /* Note that input_file.c hand checks for '#' at the beginning of the
974 first line of the input file. This is because the compiler outputs
975 #NO_APP at the beginning of its output. */
976 /* Also note that comments like this one will always work. */
977 const char line_comment_chars[] = "#";
979 char arm_line_separator_chars[] = ";";
981 /* Chars that can be used to separate mant
982 from exp in floating point numbers. */
983 const char EXP_CHARS[] = "eE";
985 /* Chars that mean this number is a floating point constant. */
989 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
991 /* Prefix characters that indicate the start of an immediate
993 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
995 /* Separator character handling. */
997 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1000 skip_past_char (char ** str, char c)
1002 /* PR gas/14987: Allow for whitespace before the expected character. */
1003 skip_whitespace (*str);
1014 #define skip_past_comma(str) skip_past_char (str, ',')
1016 /* Arithmetic expressions (possibly involving symbols). */
1018 /* Return TRUE if anything in the expression is a bignum. */
1021 walk_no_bignums (symbolS * sp)
1023 if (symbol_get_value_expression (sp)->X_op == O_big)
1026 if (symbol_get_value_expression (sp)->X_add_symbol)
1028 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1029 || (symbol_get_value_expression (sp)->X_op_symbol
1030 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1036 static bfd_boolean in_my_get_expression = FALSE;
1038 /* Third argument to my_get_expression. */
1039 #define GE_NO_PREFIX 0
1040 #define GE_IMM_PREFIX 1
1041 #define GE_OPT_PREFIX 2
1042 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1043 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1044 #define GE_OPT_PREFIX_BIG 3
1047 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1051 /* In unified syntax, all prefixes are optional. */
1053 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1056 switch (prefix_mode)
1058 case GE_NO_PREFIX: break;
1060 if (!is_immediate_prefix (**str))
1062 inst.error = _("immediate expression requires a # prefix");
1068 case GE_OPT_PREFIX_BIG:
1069 if (is_immediate_prefix (**str))
1076 memset (ep, 0, sizeof (expressionS));
1078 save_in = input_line_pointer;
1079 input_line_pointer = *str;
1080 in_my_get_expression = TRUE;
1082 in_my_get_expression = FALSE;
1084 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1086 /* We found a bad or missing expression in md_operand(). */
1087 *str = input_line_pointer;
1088 input_line_pointer = save_in;
1089 if (inst.error == NULL)
1090 inst.error = (ep->X_op == O_absent
1091 ? _("missing expression") :_("bad expression"));
1095 /* Get rid of any bignums now, so that we don't generate an error for which
1096 we can't establish a line number later on. Big numbers are never valid
1097 in instructions, which is where this routine is always called. */
1098 if (prefix_mode != GE_OPT_PREFIX_BIG
1099 && (ep->X_op == O_big
1100 || (ep->X_add_symbol
1101 && (walk_no_bignums (ep->X_add_symbol)
1103 && walk_no_bignums (ep->X_op_symbol))))))
1105 inst.error = _("invalid constant");
1106 *str = input_line_pointer;
1107 input_line_pointer = save_in;
1111 *str = input_line_pointer;
1112 input_line_pointer = save_in;
1116 /* Turn a string in input_line_pointer into a floating point constant
1117 of type TYPE, and store the appropriate bytes in *LITP. The number
1118 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1119 returned, or NULL on OK.
1121 Note that fp constants aren't represent in the normal way on the ARM.
1122 In big endian mode, things are as expected. However, in little endian
1123 mode fp constants are big-endian word-wise, and little-endian byte-wise
1124 within the words. For example, (double) 1.1 in big endian mode is
1125 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1126 the byte sequence 99 99 f1 3f 9a 99 99 99.
1128 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1131 md_atof (int type, char * litP, int * sizeP)
1134 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1166 return _("Unrecognized or unsupported floating point constant");
1169 t = atof_ieee (input_line_pointer, type, words);
1171 input_line_pointer = t;
1172 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1174 if (target_big_endian)
1176 for (i = 0; i < prec; i++)
1178 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1179 litP += sizeof (LITTLENUM_TYPE);
1184 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1185 for (i = prec - 1; i >= 0; i--)
1187 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1188 litP += sizeof (LITTLENUM_TYPE);
1191 /* For a 4 byte float the order of elements in `words' is 1 0.
1192 For an 8 byte float the order is 1 0 3 2. */
1193 for (i = 0; i < prec; i += 2)
1195 md_number_to_chars (litP, (valueT) words[i + 1],
1196 sizeof (LITTLENUM_TYPE));
1197 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1198 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1199 litP += 2 * sizeof (LITTLENUM_TYPE);
1206 /* We handle all bad expressions here, so that we can report the faulty
1207 instruction in the error message. */
1210 md_operand (expressionS * exp)
1212 if (in_my_get_expression)
1213 exp->X_op = O_illegal;
1216 /* Immediate values. */
1219 /* Generic immediate-value read function for use in directives.
1220 Accepts anything that 'expression' can fold to a constant.
1221 *val receives the number. */
1224 immediate_for_directive (int *val)
1227 exp.X_op = O_illegal;
1229 if (is_immediate_prefix (*input_line_pointer))
1231 input_line_pointer++;
1235 if (exp.X_op != O_constant)
1237 as_bad (_("expected #constant"));
1238 ignore_rest_of_line ();
1241 *val = exp.X_add_number;
1246 /* Register parsing. */
1248 /* Generic register parser. CCP points to what should be the
1249 beginning of a register name. If it is indeed a valid register
1250 name, advance CCP over it and return the reg_entry structure;
1251 otherwise return NULL. Does not issue diagnostics. */
1253 static struct reg_entry *
1254 arm_reg_parse_multi (char **ccp)
1258 struct reg_entry *reg;
1260 skip_whitespace (start);
1262 #ifdef REGISTER_PREFIX
1263 if (*start != REGISTER_PREFIX)
1267 #ifdef OPTIONAL_REGISTER_PREFIX
1268 if (*start == OPTIONAL_REGISTER_PREFIX)
1273 if (!ISALPHA (*p) || !is_name_beginner (*p))
1278 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1280 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1290 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1291 enum arm_reg_type type)
1293 /* Alternative syntaxes are accepted for a few register classes. */
1300 /* Generic coprocessor register names are allowed for these. */
1301 if (reg && reg->type == REG_TYPE_CN)
1306 /* For backward compatibility, a bare number is valid here. */
1308 unsigned long processor = strtoul (start, ccp, 10);
1309 if (*ccp != start && processor <= 15)
1314 case REG_TYPE_MMXWC:
1315 /* WC includes WCG. ??? I'm not sure this is true for all
1316 instructions that take WC registers. */
1317 if (reg && reg->type == REG_TYPE_MMXWCG)
1328 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1329 return value is the register number or FAIL. */
1332 arm_reg_parse (char **ccp, enum arm_reg_type type)
1335 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1338 /* Do not allow a scalar (reg+index) to parse as a register. */
1339 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1342 if (reg && reg->type == type)
1345 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1352 /* Parse a Neon type specifier. *STR should point at the leading '.'
1353 character. Does no verification at this stage that the type fits the opcode
1360 Can all be legally parsed by this function.
1362 Fills in neon_type struct pointer with parsed information, and updates STR
1363 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1364 type, FAIL if not. */
1367 parse_neon_type (struct neon_type *type, char **str)
1374 while (type->elems < NEON_MAX_TYPE_ELS)
1376 enum neon_el_type thistype = NT_untyped;
1377 unsigned thissize = -1u;
1384 /* Just a size without an explicit type. */
1388 switch (TOLOWER (*ptr))
1390 case 'i': thistype = NT_integer; break;
1391 case 'f': thistype = NT_float; break;
1392 case 'p': thistype = NT_poly; break;
1393 case 's': thistype = NT_signed; break;
1394 case 'u': thistype = NT_unsigned; break;
1396 thistype = NT_float;
1401 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1407 /* .f is an abbreviation for .f32. */
1408 if (thistype == NT_float && !ISDIGIT (*ptr))
1413 thissize = strtoul (ptr, &ptr, 10);
1415 if (thissize != 8 && thissize != 16 && thissize != 32
1418 as_bad (_("bad size %d in type specifier"), thissize);
1426 type->el[type->elems].type = thistype;
1427 type->el[type->elems].size = thissize;
1432 /* Empty/missing type is not a successful parse. */
1433 if (type->elems == 0)
1441 /* Errors may be set multiple times during parsing or bit encoding
1442 (particularly in the Neon bits), but usually the earliest error which is set
1443 will be the most meaningful. Avoid overwriting it with later (cascading)
1444 errors by calling this function. */
1447 first_error (const char *err)
1453 /* Parse a single type, e.g. ".s32", leading period included. */
1455 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1458 struct neon_type optype;
1462 if (parse_neon_type (&optype, &str) == SUCCESS)
1464 if (optype.elems == 1)
1465 *vectype = optype.el[0];
1468 first_error (_("only one type should be specified for operand"));
1474 first_error (_("vector type expected"));
1486 /* Special meanings for indices (which have a range of 0-7), which will fit into
1489 #define NEON_ALL_LANES 15
1490 #define NEON_INTERLEAVE_LANES 14
1492 /* Parse either a register or a scalar, with an optional type. Return the
1493 register number, and optionally fill in the actual type of the register
1494 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1495 type/index information in *TYPEINFO. */
1498 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1499 enum arm_reg_type *rtype,
1500 struct neon_typed_alias *typeinfo)
1503 struct reg_entry *reg = arm_reg_parse_multi (&str);
1504 struct neon_typed_alias atype;
1505 struct neon_type_el parsetype;
1509 atype.eltype.type = NT_invtype;
1510 atype.eltype.size = -1;
1512 /* Try alternate syntax for some types of register. Note these are mutually
1513 exclusive with the Neon syntax extensions. */
1516 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1524 /* Undo polymorphism when a set of register types may be accepted. */
1525 if ((type == REG_TYPE_NDQ
1526 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1527 || (type == REG_TYPE_VFSD
1528 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1529 || (type == REG_TYPE_NSDQ
1530 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1531 || reg->type == REG_TYPE_NQ))
1532 || (type == REG_TYPE_NSD
1533 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1534 || (type == REG_TYPE_MMXWC
1535 && (reg->type == REG_TYPE_MMXWCG)))
1536 type = (enum arm_reg_type) reg->type;
1538 if (type != reg->type)
1544 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1546 if ((atype.defined & NTA_HASTYPE) != 0)
1548 first_error (_("can't redefine type for operand"));
1551 atype.defined |= NTA_HASTYPE;
1552 atype.eltype = parsetype;
1555 if (skip_past_char (&str, '[') == SUCCESS)
1557 if (type != REG_TYPE_VFD
1558 && !(type == REG_TYPE_VFS
1559 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2)))
1561 first_error (_("only D registers may be indexed"));
1565 if ((atype.defined & NTA_HASINDEX) != 0)
1567 first_error (_("can't change index for operand"));
1571 atype.defined |= NTA_HASINDEX;
1573 if (skip_past_char (&str, ']') == SUCCESS)
1574 atype.index = NEON_ALL_LANES;
1579 my_get_expression (&exp, &str, GE_NO_PREFIX);
1581 if (exp.X_op != O_constant)
1583 first_error (_("constant expression required"));
1587 if (skip_past_char (&str, ']') == FAIL)
1590 atype.index = exp.X_add_number;
1605 /* Like arm_reg_parse, but allow allow the following extra features:
1606 - If RTYPE is non-zero, return the (possibly restricted) type of the
1607 register (e.g. Neon double or quad reg when either has been requested).
1608 - If this is a Neon vector type with additional type information, fill
1609 in the struct pointed to by VECTYPE (if non-NULL).
1610 This function will fault on encountering a scalar. */
1613 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1614 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1616 struct neon_typed_alias atype;
1618 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1623 /* Do not allow regname(... to parse as a register. */
1627 /* Do not allow a scalar (reg+index) to parse as a register. */
1628 if ((atype.defined & NTA_HASINDEX) != 0)
1630 first_error (_("register operand expected, but got scalar"));
1635 *vectype = atype.eltype;
1642 #define NEON_SCALAR_REG(X) ((X) >> 4)
1643 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1645 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1646 have enough information to be able to do a good job bounds-checking. So, we
1647 just do easy checks here, and do further checks later. */
1650 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1654 struct neon_typed_alias atype;
1655 enum arm_reg_type reg_type = REG_TYPE_VFD;
1658 reg_type = REG_TYPE_VFS;
1660 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1662 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1665 if (atype.index == NEON_ALL_LANES)
1667 first_error (_("scalar must have an index"));
1670 else if (atype.index >= 64 / elsize)
1672 first_error (_("scalar index out of range"));
1677 *type = atype.eltype;
1681 return reg * 16 + atype.index;
1684 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1687 parse_reg_list (char ** strp)
1689 char * str = * strp;
1693 /* We come back here if we get ranges concatenated by '+' or '|'. */
1696 skip_whitespace (str);
1710 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1712 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1722 first_error (_("bad range in register list"));
1726 for (i = cur_reg + 1; i < reg; i++)
1728 if (range & (1 << i))
1730 (_("Warning: duplicated register (r%d) in register list"),
1738 if (range & (1 << reg))
1739 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1741 else if (reg <= cur_reg)
1742 as_tsktsk (_("Warning: register range not in ascending order"));
1747 while (skip_past_comma (&str) != FAIL
1748 || (in_range = 1, *str++ == '-'));
1751 if (skip_past_char (&str, '}') == FAIL)
1753 first_error (_("missing `}'"));
1761 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1764 if (exp.X_op == O_constant)
1766 if (exp.X_add_number
1767 != (exp.X_add_number & 0x0000ffff))
1769 inst.error = _("invalid register mask");
1773 if ((range & exp.X_add_number) != 0)
1775 int regno = range & exp.X_add_number;
1778 regno = (1 << regno) - 1;
1780 (_("Warning: duplicated register (r%d) in register list"),
1784 range |= exp.X_add_number;
1788 if (inst.reloc.type != 0)
1790 inst.error = _("expression too complex");
1794 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1795 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1796 inst.reloc.pc_rel = 0;
1800 if (*str == '|' || *str == '+')
1806 while (another_range);
1812 /* Types of registers in a list. */
1821 /* Parse a VFP register list. If the string is invalid return FAIL.
1822 Otherwise return the number of registers, and set PBASE to the first
1823 register. Parses registers of type ETYPE.
1824 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1825 - Q registers can be used to specify pairs of D registers
1826 - { } can be omitted from around a singleton register list
1827 FIXME: This is not implemented, as it would require backtracking in
1830 This could be done (the meaning isn't really ambiguous), but doesn't
1831 fit in well with the current parsing framework.
1832 - 32 D registers may be used (also true for VFPv3).
1833 FIXME: Types are ignored in these register lists, which is probably a
1837 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1842 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1846 unsigned long mask = 0;
1849 if (skip_past_char (&str, '{') == FAIL)
1851 inst.error = _("expecting {");
1858 regtype = REG_TYPE_VFS;
1863 regtype = REG_TYPE_VFD;
1866 case REGLIST_NEON_D:
1867 regtype = REG_TYPE_NDQ;
1871 if (etype != REGLIST_VFP_S)
1873 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1874 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1878 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1881 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1888 base_reg = max_regs;
1892 int setmask = 1, addregs = 1;
1894 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1896 if (new_base == FAIL)
1898 first_error (_(reg_expected_msgs[regtype]));
1902 if (new_base >= max_regs)
1904 first_error (_("register out of range in list"));
1908 /* Note: a value of 2 * n is returned for the register Q<n>. */
1909 if (regtype == REG_TYPE_NQ)
1915 if (new_base < base_reg)
1916 base_reg = new_base;
1918 if (mask & (setmask << new_base))
1920 first_error (_("invalid register list"));
1924 if ((mask >> new_base) != 0 && ! warned)
1926 as_tsktsk (_("register list not in ascending order"));
1930 mask |= setmask << new_base;
1933 if (*str == '-') /* We have the start of a range expression */
1939 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1942 inst.error = gettext (reg_expected_msgs[regtype]);
1946 if (high_range >= max_regs)
1948 first_error (_("register out of range in list"));
1952 if (regtype == REG_TYPE_NQ)
1953 high_range = high_range + 1;
1955 if (high_range <= new_base)
1957 inst.error = _("register range not in ascending order");
1961 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1963 if (mask & (setmask << new_base))
1965 inst.error = _("invalid register list");
1969 mask |= setmask << new_base;
1974 while (skip_past_comma (&str) != FAIL);
1978 /* Sanity check -- should have raised a parse error above. */
1979 if (count == 0 || count > max_regs)
1984 /* Final test -- the registers must be consecutive. */
1986 for (i = 0; i < count; i++)
1988 if ((mask & (1u << i)) == 0)
1990 inst.error = _("non-contiguous register range");
2000 /* True if two alias types are the same. */
2003 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2011 if (a->defined != b->defined)
2014 if ((a->defined & NTA_HASTYPE) != 0
2015 && (a->eltype.type != b->eltype.type
2016 || a->eltype.size != b->eltype.size))
2019 if ((a->defined & NTA_HASINDEX) != 0
2020 && (a->index != b->index))
2026 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2027 The base register is put in *PBASE.
2028 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2030 The register stride (minus one) is put in bit 4 of the return value.
2031 Bits [6:5] encode the list length (minus one).
2032 The type of the list elements is put in *ELTYPE, if non-NULL. */
2034 #define NEON_LANE(X) ((X) & 0xf)
2035 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2036 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2039 parse_neon_el_struct_list (char **str, unsigned *pbase,
2040 struct neon_type_el *eltype)
2047 int leading_brace = 0;
2048 enum arm_reg_type rtype = REG_TYPE_NDQ;
2049 const char *const incr_error = _("register stride must be 1 or 2");
2050 const char *const type_error = _("mismatched element/structure types in list");
2051 struct neon_typed_alias firsttype;
2052 firsttype.defined = 0;
2053 firsttype.eltype.type = NT_invtype;
2054 firsttype.eltype.size = -1;
2055 firsttype.index = -1;
2057 if (skip_past_char (&ptr, '{') == SUCCESS)
2062 struct neon_typed_alias atype;
2063 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2067 first_error (_(reg_expected_msgs[rtype]));
2074 if (rtype == REG_TYPE_NQ)
2080 else if (reg_incr == -1)
2082 reg_incr = getreg - base_reg;
2083 if (reg_incr < 1 || reg_incr > 2)
2085 first_error (_(incr_error));
2089 else if (getreg != base_reg + reg_incr * count)
2091 first_error (_(incr_error));
2095 if (! neon_alias_types_same (&atype, &firsttype))
2097 first_error (_(type_error));
2101 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2105 struct neon_typed_alias htype;
2106 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2108 lane = NEON_INTERLEAVE_LANES;
2109 else if (lane != NEON_INTERLEAVE_LANES)
2111 first_error (_(type_error));
2116 else if (reg_incr != 1)
2118 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2122 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2125 first_error (_(reg_expected_msgs[rtype]));
2128 if (! neon_alias_types_same (&htype, &firsttype))
2130 first_error (_(type_error));
2133 count += hireg + dregs - getreg;
2137 /* If we're using Q registers, we can't use [] or [n] syntax. */
2138 if (rtype == REG_TYPE_NQ)
2144 if ((atype.defined & NTA_HASINDEX) != 0)
2148 else if (lane != atype.index)
2150 first_error (_(type_error));
2154 else if (lane == -1)
2155 lane = NEON_INTERLEAVE_LANES;
2156 else if (lane != NEON_INTERLEAVE_LANES)
2158 first_error (_(type_error));
2163 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2165 /* No lane set by [x]. We must be interleaving structures. */
2167 lane = NEON_INTERLEAVE_LANES;
2170 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2171 || (count > 1 && reg_incr == -1))
2173 first_error (_("error parsing element/structure list"));
2177 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2179 first_error (_("expected }"));
2187 *eltype = firsttype.eltype;
2192 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2195 /* Parse an explicit relocation suffix on an expression. This is
2196 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2197 arm_reloc_hsh contains no entries, so this function can only
2198 succeed if there is no () after the word. Returns -1 on error,
2199 BFD_RELOC_UNUSED if there wasn't any suffix. */
2202 parse_reloc (char **str)
2204 struct reloc_entry *r;
2208 return BFD_RELOC_UNUSED;
2213 while (*q && *q != ')' && *q != ',')
2218 if ((r = (struct reloc_entry *)
2219 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2226 /* Directives: register aliases. */
2228 static struct reg_entry *
2229 insert_reg_alias (char *str, unsigned number, int type)
2231 struct reg_entry *new_reg;
2234 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2236 if (new_reg->builtin)
2237 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2239 /* Only warn about a redefinition if it's not defined as the
2241 else if (new_reg->number != number || new_reg->type != type)
2242 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2247 name = xstrdup (str);
2248 new_reg = XNEW (struct reg_entry);
2250 new_reg->name = name;
2251 new_reg->number = number;
2252 new_reg->type = type;
2253 new_reg->builtin = FALSE;
2254 new_reg->neon = NULL;
2256 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2263 insert_neon_reg_alias (char *str, int number, int type,
2264 struct neon_typed_alias *atype)
2266 struct reg_entry *reg = insert_reg_alias (str, number, type);
2270 first_error (_("attempt to redefine typed alias"));
2276 reg->neon = XNEW (struct neon_typed_alias);
2277 *reg->neon = *atype;
2281 /* Look for the .req directive. This is of the form:
2283 new_register_name .req existing_register_name
2285 If we find one, or if it looks sufficiently like one that we want to
2286 handle any error here, return TRUE. Otherwise return FALSE. */
2289 create_register_alias (char * newname, char *p)
2291 struct reg_entry *old;
2292 char *oldname, *nbuf;
2295 /* The input scrubber ensures that whitespace after the mnemonic is
2296 collapsed to single spaces. */
2298 if (strncmp (oldname, " .req ", 6) != 0)
2302 if (*oldname == '\0')
2305 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2308 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2312 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2313 the desired alias name, and p points to its end. If not, then
2314 the desired alias name is in the global original_case_string. */
2315 #ifdef TC_CASE_SENSITIVE
2318 newname = original_case_string;
2319 nlen = strlen (newname);
2322 nbuf = xmemdup0 (newname, nlen);
2324 /* Create aliases under the new name as stated; an all-lowercase
2325 version of the new name; and an all-uppercase version of the new
2327 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2329 for (p = nbuf; *p; p++)
2332 if (strncmp (nbuf, newname, nlen))
2334 /* If this attempt to create an additional alias fails, do not bother
2335 trying to create the all-lower case alias. We will fail and issue
2336 a second, duplicate error message. This situation arises when the
2337 programmer does something like:
2340 The second .req creates the "Foo" alias but then fails to create
2341 the artificial FOO alias because it has already been created by the
2343 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2350 for (p = nbuf; *p; p++)
2353 if (strncmp (nbuf, newname, nlen))
2354 insert_reg_alias (nbuf, old->number, old->type);
2361 /* Create a Neon typed/indexed register alias using directives, e.g.:
2366 These typed registers can be used instead of the types specified after the
2367 Neon mnemonic, so long as all operands given have types. Types can also be
2368 specified directly, e.g.:
2369 vadd d0.s32, d1.s32, d2.s32 */
2372 create_neon_reg_alias (char *newname, char *p)
2374 enum arm_reg_type basetype;
2375 struct reg_entry *basereg;
2376 struct reg_entry mybasereg;
2377 struct neon_type ntype;
2378 struct neon_typed_alias typeinfo;
2379 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2382 typeinfo.defined = 0;
2383 typeinfo.eltype.type = NT_invtype;
2384 typeinfo.eltype.size = -1;
2385 typeinfo.index = -1;
2389 if (strncmp (p, " .dn ", 5) == 0)
2390 basetype = REG_TYPE_VFD;
2391 else if (strncmp (p, " .qn ", 5) == 0)
2392 basetype = REG_TYPE_NQ;
2401 basereg = arm_reg_parse_multi (&p);
2403 if (basereg && basereg->type != basetype)
2405 as_bad (_("bad type for register"));
2409 if (basereg == NULL)
2412 /* Try parsing as an integer. */
2413 my_get_expression (&exp, &p, GE_NO_PREFIX);
2414 if (exp.X_op != O_constant)
2416 as_bad (_("expression must be constant"));
2419 basereg = &mybasereg;
2420 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2426 typeinfo = *basereg->neon;
2428 if (parse_neon_type (&ntype, &p) == SUCCESS)
2430 /* We got a type. */
2431 if (typeinfo.defined & NTA_HASTYPE)
2433 as_bad (_("can't redefine the type of a register alias"));
2437 typeinfo.defined |= NTA_HASTYPE;
2438 if (ntype.elems != 1)
2440 as_bad (_("you must specify a single type only"));
2443 typeinfo.eltype = ntype.el[0];
2446 if (skip_past_char (&p, '[') == SUCCESS)
2449 /* We got a scalar index. */
2451 if (typeinfo.defined & NTA_HASINDEX)
2453 as_bad (_("can't redefine the index of a scalar alias"));
2457 my_get_expression (&exp, &p, GE_NO_PREFIX);
2459 if (exp.X_op != O_constant)
2461 as_bad (_("scalar index must be constant"));
2465 typeinfo.defined |= NTA_HASINDEX;
2466 typeinfo.index = exp.X_add_number;
2468 if (skip_past_char (&p, ']') == FAIL)
2470 as_bad (_("expecting ]"));
2475 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2476 the desired alias name, and p points to its end. If not, then
2477 the desired alias name is in the global original_case_string. */
2478 #ifdef TC_CASE_SENSITIVE
2479 namelen = nameend - newname;
2481 newname = original_case_string;
2482 namelen = strlen (newname);
2485 namebuf = xmemdup0 (newname, namelen);
2487 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2488 typeinfo.defined != 0 ? &typeinfo : NULL);
2490 /* Insert name in all uppercase. */
2491 for (p = namebuf; *p; p++)
2494 if (strncmp (namebuf, newname, namelen))
2495 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2496 typeinfo.defined != 0 ? &typeinfo : NULL);
2498 /* Insert name in all lowercase. */
2499 for (p = namebuf; *p; p++)
2502 if (strncmp (namebuf, newname, namelen))
2503 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2504 typeinfo.defined != 0 ? &typeinfo : NULL);
2510 /* Should never be called, as .req goes between the alias and the
2511 register name, not at the beginning of the line. */
2514 s_req (int a ATTRIBUTE_UNUSED)
2516 as_bad (_("invalid syntax for .req directive"));
2520 s_dn (int a ATTRIBUTE_UNUSED)
2522 as_bad (_("invalid syntax for .dn directive"));
2526 s_qn (int a ATTRIBUTE_UNUSED)
2528 as_bad (_("invalid syntax for .qn directive"));
2531 /* The .unreq directive deletes an alias which was previously defined
2532 by .req. For example:
2538 s_unreq (int a ATTRIBUTE_UNUSED)
2543 name = input_line_pointer;
2545 while (*input_line_pointer != 0
2546 && *input_line_pointer != ' '
2547 && *input_line_pointer != '\n')
2548 ++input_line_pointer;
2550 saved_char = *input_line_pointer;
2551 *input_line_pointer = 0;
2554 as_bad (_("invalid syntax for .unreq directive"));
2557 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2561 as_bad (_("unknown register alias '%s'"), name);
2562 else if (reg->builtin)
2563 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2570 hash_delete (arm_reg_hsh, name, FALSE);
2571 free ((char *) reg->name);
2576 /* Also locate the all upper case and all lower case versions.
2577 Do not complain if we cannot find one or the other as it
2578 was probably deleted above. */
2580 nbuf = strdup (name);
2581 for (p = nbuf; *p; p++)
2583 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2586 hash_delete (arm_reg_hsh, nbuf, FALSE);
2587 free ((char *) reg->name);
2593 for (p = nbuf; *p; p++)
2595 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2598 hash_delete (arm_reg_hsh, nbuf, FALSE);
2599 free ((char *) reg->name);
2609 *input_line_pointer = saved_char;
2610 demand_empty_rest_of_line ();
2613 /* Directives: Instruction set selection. */
2616 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2617 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2618 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2619 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2621 /* Create a new mapping symbol for the transition to STATE. */
2624 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2627 const char * symname;
2634 type = BSF_NO_FLAGS;
2638 type = BSF_NO_FLAGS;
2642 type = BSF_NO_FLAGS;
2648 symbolP = symbol_new (symname, now_seg, value, frag);
2649 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2654 THUMB_SET_FUNC (symbolP, 0);
2655 ARM_SET_THUMB (symbolP, 0);
2656 ARM_SET_INTERWORK (symbolP, support_interwork);
2660 THUMB_SET_FUNC (symbolP, 1);
2661 ARM_SET_THUMB (symbolP, 1);
2662 ARM_SET_INTERWORK (symbolP, support_interwork);
2670 /* Save the mapping symbols for future reference. Also check that
2671 we do not place two mapping symbols at the same offset within a
2672 frag. We'll handle overlap between frags in
2673 check_mapping_symbols.
2675 If .fill or other data filling directive generates zero sized data,
2676 the mapping symbol for the following code will have the same value
2677 as the one generated for the data filling directive. In this case,
2678 we replace the old symbol with the new one at the same address. */
2681 if (frag->tc_frag_data.first_map != NULL)
2683 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2684 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2686 frag->tc_frag_data.first_map = symbolP;
2688 if (frag->tc_frag_data.last_map != NULL)
2690 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2691 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2692 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2694 frag->tc_frag_data.last_map = symbolP;
2697 /* We must sometimes convert a region marked as code to data during
2698 code alignment, if an odd number of bytes have to be padded. The
2699 code mapping symbol is pushed to an aligned address. */
2702 insert_data_mapping_symbol (enum mstate state,
2703 valueT value, fragS *frag, offsetT bytes)
2705 /* If there was already a mapping symbol, remove it. */
2706 if (frag->tc_frag_data.last_map != NULL
2707 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2709 symbolS *symp = frag->tc_frag_data.last_map;
2713 know (frag->tc_frag_data.first_map == symp);
2714 frag->tc_frag_data.first_map = NULL;
2716 frag->tc_frag_data.last_map = NULL;
2717 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2720 make_mapping_symbol (MAP_DATA, value, frag);
2721 make_mapping_symbol (state, value + bytes, frag);
2724 static void mapping_state_2 (enum mstate state, int max_chars);
2726 /* Set the mapping state to STATE. Only call this when about to
2727 emit some STATE bytes to the file. */
2729 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2731 mapping_state (enum mstate state)
2733 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2735 if (mapstate == state)
2736 /* The mapping symbol has already been emitted.
2737 There is nothing else to do. */
2740 if (state == MAP_ARM || state == MAP_THUMB)
2742 All ARM instructions require 4-byte alignment.
2743 (Almost) all Thumb instructions require 2-byte alignment.
2745 When emitting instructions into any section, mark the section
2748 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2749 but themselves require 2-byte alignment; this applies to some
2750 PC- relative forms. However, these cases will involve implicit
2751 literal pool generation or an explicit .align >=2, both of
2752 which will cause the section to me marked with sufficient
2753 alignment. Thus, we don't handle those cases here. */
2754 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2756 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2757 /* This case will be evaluated later. */
2760 mapping_state_2 (state, 0);
2763 /* Same as mapping_state, but MAX_CHARS bytes have already been
2764 allocated. Put the mapping symbol that far back. */
2767 mapping_state_2 (enum mstate state, int max_chars)
2769 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2771 if (!SEG_NORMAL (now_seg))
2774 if (mapstate == state)
2775 /* The mapping symbol has already been emitted.
2776 There is nothing else to do. */
2779 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2780 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2782 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2783 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2786 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2789 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2790 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2794 #define mapping_state(x) ((void)0)
2795 #define mapping_state_2(x, y) ((void)0)
2798 /* Find the real, Thumb encoded start of a Thumb function. */
2802 find_real_start (symbolS * symbolP)
2805 const char * name = S_GET_NAME (symbolP);
2806 symbolS * new_target;
2808 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2809 #define STUB_NAME ".real_start_of"
2814 /* The compiler may generate BL instructions to local labels because
2815 it needs to perform a branch to a far away location. These labels
2816 do not have a corresponding ".real_start_of" label. We check
2817 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2818 the ".real_start_of" convention for nonlocal branches. */
2819 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2822 real_start = concat (STUB_NAME, name, NULL);
2823 new_target = symbol_find (real_start);
2826 if (new_target == NULL)
2828 as_warn (_("Failed to find real start of function: %s\n"), name);
2829 new_target = symbolP;
2837 opcode_select (int width)
2844 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2845 as_bad (_("selected processor does not support THUMB opcodes"));
2848 /* No need to force the alignment, since we will have been
2849 coming from ARM mode, which is word-aligned. */
2850 record_alignment (now_seg, 1);
2857 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2858 as_bad (_("selected processor does not support ARM opcodes"));
2863 frag_align (2, 0, 0);
2865 record_alignment (now_seg, 1);
2870 as_bad (_("invalid instruction size selected (%d)"), width);
2875 s_arm (int ignore ATTRIBUTE_UNUSED)
2878 demand_empty_rest_of_line ();
2882 s_thumb (int ignore ATTRIBUTE_UNUSED)
2885 demand_empty_rest_of_line ();
2889 s_code (int unused ATTRIBUTE_UNUSED)
2893 temp = get_absolute_expression ();
2898 opcode_select (temp);
2902 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2907 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2909 /* If we are not already in thumb mode go into it, EVEN if
2910 the target processor does not support thumb instructions.
2911 This is used by gcc/config/arm/lib1funcs.asm for example
2912 to compile interworking support functions even if the
2913 target processor should not support interworking. */
2917 record_alignment (now_seg, 1);
2920 demand_empty_rest_of_line ();
2924 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2928 /* The following label is the name/address of the start of a Thumb function.
2929 We need to know this for the interworking support. */
2930 label_is_thumb_function_name = TRUE;
2933 /* Perform a .set directive, but also mark the alias as
2934 being a thumb function. */
2937 s_thumb_set (int equiv)
2939 /* XXX the following is a duplicate of the code for s_set() in read.c
2940 We cannot just call that code as we need to get at the symbol that
2947 /* Especial apologies for the random logic:
2948 This just grew, and could be parsed much more simply!
2950 delim = get_symbol_name (& name);
2951 end_name = input_line_pointer;
2952 (void) restore_line_pointer (delim);
2954 if (*input_line_pointer != ',')
2957 as_bad (_("expected comma after name \"%s\""), name);
2959 ignore_rest_of_line ();
2963 input_line_pointer++;
2966 if (name[0] == '.' && name[1] == '\0')
2968 /* XXX - this should not happen to .thumb_set. */
2972 if ((symbolP = symbol_find (name)) == NULL
2973 && (symbolP = md_undefined_symbol (name)) == NULL)
2976 /* When doing symbol listings, play games with dummy fragments living
2977 outside the normal fragment chain to record the file and line info
2979 if (listing & LISTING_SYMBOLS)
2981 extern struct list_info_struct * listing_tail;
2982 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2984 memset (dummy_frag, 0, sizeof (fragS));
2985 dummy_frag->fr_type = rs_fill;
2986 dummy_frag->line = listing_tail;
2987 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2988 dummy_frag->fr_symbol = symbolP;
2992 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2995 /* "set" symbols are local unless otherwise specified. */
2996 SF_SET_LOCAL (symbolP);
2997 #endif /* OBJ_COFF */
2998 } /* Make a new symbol. */
3000 symbol_table_insert (symbolP);
3005 && S_IS_DEFINED (symbolP)
3006 && S_GET_SEGMENT (symbolP) != reg_section)
3007 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3009 pseudo_set (symbolP);
3011 demand_empty_rest_of_line ();
3013 /* XXX Now we come to the Thumb specific bit of code. */
3015 THUMB_SET_FUNC (symbolP, 1);
3016 ARM_SET_THUMB (symbolP, 1);
3017 #if defined OBJ_ELF || defined OBJ_COFF
3018 ARM_SET_INTERWORK (symbolP, support_interwork);
3022 /* Directives: Mode selection. */
3024 /* .syntax [unified|divided] - choose the new unified syntax
3025 (same for Arm and Thumb encoding, modulo slight differences in what
3026 can be represented) or the old divergent syntax for each mode. */
3028 s_syntax (int unused ATTRIBUTE_UNUSED)
3032 delim = get_symbol_name (& name);
3034 if (!strcasecmp (name, "unified"))
3035 unified_syntax = TRUE;
3036 else if (!strcasecmp (name, "divided"))
3037 unified_syntax = FALSE;
3040 as_bad (_("unrecognized syntax mode \"%s\""), name);
3043 (void) restore_line_pointer (delim);
3044 demand_empty_rest_of_line ();
3047 /* Directives: sectioning and alignment. */
3050 s_bss (int ignore ATTRIBUTE_UNUSED)
3052 /* We don't support putting frags in the BSS segment, we fake it by
3053 marking in_bss, then looking at s_skip for clues. */
3054 subseg_set (bss_section, 0);
3055 demand_empty_rest_of_line ();
3057 #ifdef md_elf_section_change_hook
3058 md_elf_section_change_hook ();
3063 s_even (int ignore ATTRIBUTE_UNUSED)
3065 /* Never make frag if expect extra pass. */
3067 frag_align (1, 0, 0);
3069 record_alignment (now_seg, 1);
3071 demand_empty_rest_of_line ();
3074 /* Directives: CodeComposer Studio. */
3076 /* .ref (for CodeComposer Studio syntax only). */
3078 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3080 if (codecomposer_syntax)
3081 ignore_rest_of_line ();
3083 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3086 /* If name is not NULL, then it is used for marking the beginning of a
3087 function, whereas if it is NULL then it means the function end. */
3089 asmfunc_debug (const char * name)
3091 static const char * last_name = NULL;
3095 gas_assert (last_name == NULL);
3098 if (debug_type == DEBUG_STABS)
3099 stabs_generate_asm_func (name, name);
3103 gas_assert (last_name != NULL);
3105 if (debug_type == DEBUG_STABS)
3106 stabs_generate_asm_endfunc (last_name, last_name);
3113 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3115 if (codecomposer_syntax)
3117 switch (asmfunc_state)
3119 case OUTSIDE_ASMFUNC:
3120 asmfunc_state = WAITING_ASMFUNC_NAME;
3123 case WAITING_ASMFUNC_NAME:
3124 as_bad (_(".asmfunc repeated."));
3127 case WAITING_ENDASMFUNC:
3128 as_bad (_(".asmfunc without function."));
3131 demand_empty_rest_of_line ();
3134 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3138 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3140 if (codecomposer_syntax)
3142 switch (asmfunc_state)
3144 case OUTSIDE_ASMFUNC:
3145 as_bad (_(".endasmfunc without a .asmfunc."));
3148 case WAITING_ASMFUNC_NAME:
3149 as_bad (_(".endasmfunc without function."));
3152 case WAITING_ENDASMFUNC:
3153 asmfunc_state = OUTSIDE_ASMFUNC;
3154 asmfunc_debug (NULL);
3157 demand_empty_rest_of_line ();
3160 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3164 s_ccs_def (int name)
3166 if (codecomposer_syntax)
3169 as_bad (_(".def pseudo-op only available with -mccs flag."));
3172 /* Directives: Literal pools. */
3174 static literal_pool *
3175 find_literal_pool (void)
3177 literal_pool * pool;
3179 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3181 if (pool->section == now_seg
3182 && pool->sub_section == now_subseg)
3189 static literal_pool *
3190 find_or_make_literal_pool (void)
3192 /* Next literal pool ID number. */
3193 static unsigned int latest_pool_num = 1;
3194 literal_pool * pool;
3196 pool = find_literal_pool ();
3200 /* Create a new pool. */
3201 pool = XNEW (literal_pool);
3205 pool->next_free_entry = 0;
3206 pool->section = now_seg;
3207 pool->sub_section = now_subseg;
3208 pool->next = list_of_pools;
3209 pool->symbol = NULL;
3210 pool->alignment = 2;
3212 /* Add it to the list. */
3213 list_of_pools = pool;
3216 /* New pools, and emptied pools, will have a NULL symbol. */
3217 if (pool->symbol == NULL)
3219 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3220 (valueT) 0, &zero_address_frag);
3221 pool->id = latest_pool_num ++;
3228 /* Add the literal in the global 'inst'
3229 structure to the relevant literal pool. */
3232 add_to_lit_pool (unsigned int nbytes)
3234 #define PADDING_SLOT 0x1
3235 #define LIT_ENTRY_SIZE_MASK 0xFF
3236 literal_pool * pool;
3237 unsigned int entry, pool_size = 0;
3238 bfd_boolean padding_slot_p = FALSE;
3244 imm1 = inst.operands[1].imm;
3245 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3246 : inst.reloc.exp.X_unsigned ? 0
3247 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3248 if (target_big_endian)
3251 imm2 = inst.operands[1].imm;
3255 pool = find_or_make_literal_pool ();
3257 /* Check if this literal value is already in the pool. */
3258 for (entry = 0; entry < pool->next_free_entry; entry ++)
3262 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3263 && (inst.reloc.exp.X_op == O_constant)
3264 && (pool->literals[entry].X_add_number
3265 == inst.reloc.exp.X_add_number)
3266 && (pool->literals[entry].X_md == nbytes)
3267 && (pool->literals[entry].X_unsigned
3268 == inst.reloc.exp.X_unsigned))
3271 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3272 && (inst.reloc.exp.X_op == O_symbol)
3273 && (pool->literals[entry].X_add_number
3274 == inst.reloc.exp.X_add_number)
3275 && (pool->literals[entry].X_add_symbol
3276 == inst.reloc.exp.X_add_symbol)
3277 && (pool->literals[entry].X_op_symbol
3278 == inst.reloc.exp.X_op_symbol)
3279 && (pool->literals[entry].X_md == nbytes))
3282 else if ((nbytes == 8)
3283 && !(pool_size & 0x7)
3284 && ((entry + 1) != pool->next_free_entry)
3285 && (pool->literals[entry].X_op == O_constant)
3286 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3287 && (pool->literals[entry].X_unsigned
3288 == inst.reloc.exp.X_unsigned)
3289 && (pool->literals[entry + 1].X_op == O_constant)
3290 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3291 && (pool->literals[entry + 1].X_unsigned
3292 == inst.reloc.exp.X_unsigned))
3295 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3296 if (padding_slot_p && (nbytes == 4))
3302 /* Do we need to create a new entry? */
3303 if (entry == pool->next_free_entry)
3305 if (entry >= MAX_LITERAL_POOL_SIZE)
3307 inst.error = _("literal pool overflow");
3313 /* For 8-byte entries, we align to an 8-byte boundary,
3314 and split it into two 4-byte entries, because on 32-bit
3315 host, 8-byte constants are treated as big num, thus
3316 saved in "generic_bignum" which will be overwritten
3317 by later assignments.
3319 We also need to make sure there is enough space for
3322 We also check to make sure the literal operand is a
3324 if (!(inst.reloc.exp.X_op == O_constant
3325 || inst.reloc.exp.X_op == O_big))
3327 inst.error = _("invalid type for literal pool");
3330 else if (pool_size & 0x7)
3332 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3334 inst.error = _("literal pool overflow");
3338 pool->literals[entry] = inst.reloc.exp;
3339 pool->literals[entry].X_op = O_constant;
3340 pool->literals[entry].X_add_number = 0;
3341 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3342 pool->next_free_entry += 1;
3345 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3347 inst.error = _("literal pool overflow");
3351 pool->literals[entry] = inst.reloc.exp;
3352 pool->literals[entry].X_op = O_constant;
3353 pool->literals[entry].X_add_number = imm1;
3354 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3355 pool->literals[entry++].X_md = 4;
3356 pool->literals[entry] = inst.reloc.exp;
3357 pool->literals[entry].X_op = O_constant;
3358 pool->literals[entry].X_add_number = imm2;
3359 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3360 pool->literals[entry].X_md = 4;
3361 pool->alignment = 3;
3362 pool->next_free_entry += 1;
3366 pool->literals[entry] = inst.reloc.exp;
3367 pool->literals[entry].X_md = 4;
3371 /* PR ld/12974: Record the location of the first source line to reference
3372 this entry in the literal pool. If it turns out during linking that the
3373 symbol does not exist we will be able to give an accurate line number for
3374 the (first use of the) missing reference. */
3375 if (debug_type == DEBUG_DWARF2)
3376 dwarf2_where (pool->locs + entry);
3378 pool->next_free_entry += 1;
3380 else if (padding_slot_p)
3382 pool->literals[entry] = inst.reloc.exp;
3383 pool->literals[entry].X_md = nbytes;
3386 inst.reloc.exp.X_op = O_symbol;
3387 inst.reloc.exp.X_add_number = pool_size;
3388 inst.reloc.exp.X_add_symbol = pool->symbol;
3394 tc_start_label_without_colon (void)
3396 bfd_boolean ret = TRUE;
3398 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3400 const char *label = input_line_pointer;
3402 while (!is_end_of_line[(int) label[-1]])
3407 as_bad (_("Invalid label '%s'"), label);
3411 asmfunc_debug (label);
3413 asmfunc_state = WAITING_ENDASMFUNC;
3419 /* Can't use symbol_new here, so have to create a symbol and then at
3420 a later date assign it a value. That's what these functions do. */
3423 symbol_locate (symbolS * symbolP,
3424 const char * name, /* It is copied, the caller can modify. */
3425 segT segment, /* Segment identifier (SEG_<something>). */
3426 valueT valu, /* Symbol value. */
3427 fragS * frag) /* Associated fragment. */
3430 char * preserved_copy_of_name;
3432 name_length = strlen (name) + 1; /* +1 for \0. */
3433 obstack_grow (¬es, name, name_length);
3434 preserved_copy_of_name = (char *) obstack_finish (¬es);
3436 #ifdef tc_canonicalize_symbol_name
3437 preserved_copy_of_name =
3438 tc_canonicalize_symbol_name (preserved_copy_of_name);
3441 S_SET_NAME (symbolP, preserved_copy_of_name);
3443 S_SET_SEGMENT (symbolP, segment);
3444 S_SET_VALUE (symbolP, valu);
3445 symbol_clear_list_pointers (symbolP);
3447 symbol_set_frag (symbolP, frag);
3449 /* Link to end of symbol chain. */
3451 extern int symbol_table_frozen;
3453 if (symbol_table_frozen)
3457 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3459 obj_symbol_new_hook (symbolP);
3461 #ifdef tc_symbol_new_hook
3462 tc_symbol_new_hook (symbolP);
3466 verify_symbol_chain (symbol_rootP, symbol_lastP);
3467 #endif /* DEBUG_SYMS */
3471 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3474 literal_pool * pool;
3477 pool = find_literal_pool ();
3479 || pool->symbol == NULL
3480 || pool->next_free_entry == 0)
3483 /* Align pool as you have word accesses.
3484 Only make a frag if we have to. */
3486 frag_align (pool->alignment, 0, 0);
3488 record_alignment (now_seg, 2);
3491 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3492 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3494 sprintf (sym_name, "$$lit_\002%x", pool->id);
3496 symbol_locate (pool->symbol, sym_name, now_seg,
3497 (valueT) frag_now_fix (), frag_now);
3498 symbol_table_insert (pool->symbol);
3500 ARM_SET_THUMB (pool->symbol, thumb_mode);
3502 #if defined OBJ_COFF || defined OBJ_ELF
3503 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3506 for (entry = 0; entry < pool->next_free_entry; entry ++)
3509 if (debug_type == DEBUG_DWARF2)
3510 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3512 /* First output the expression in the instruction to the pool. */
3513 emit_expr (&(pool->literals[entry]),
3514 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3517 /* Mark the pool as empty. */
3518 pool->next_free_entry = 0;
3519 pool->symbol = NULL;
3523 /* Forward declarations for functions below, in the MD interface
3525 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3526 static valueT create_unwind_entry (int);
3527 static void start_unwind_section (const segT, int);
3528 static void add_unwind_opcode (valueT, int);
3529 static void flush_pending_unwind (void);
3531 /* Directives: Data. */
3534 s_arm_elf_cons (int nbytes)
3538 #ifdef md_flush_pending_output
3539 md_flush_pending_output ();
3542 if (is_it_end_of_statement ())
3544 demand_empty_rest_of_line ();
3548 #ifdef md_cons_align
3549 md_cons_align (nbytes);
3552 mapping_state (MAP_DATA);
3556 char *base = input_line_pointer;
3560 if (exp.X_op != O_symbol)
3561 emit_expr (&exp, (unsigned int) nbytes);
3564 char *before_reloc = input_line_pointer;
3565 reloc = parse_reloc (&input_line_pointer);
3568 as_bad (_("unrecognized relocation suffix"));
3569 ignore_rest_of_line ();
3572 else if (reloc == BFD_RELOC_UNUSED)
3573 emit_expr (&exp, (unsigned int) nbytes);
3576 reloc_howto_type *howto = (reloc_howto_type *)
3577 bfd_reloc_type_lookup (stdoutput,
3578 (bfd_reloc_code_real_type) reloc);
3579 int size = bfd_get_reloc_size (howto);
3581 if (reloc == BFD_RELOC_ARM_PLT32)
3583 as_bad (_("(plt) is only valid on branch targets"));
3584 reloc = BFD_RELOC_UNUSED;
3589 as_bad (ngettext ("%s relocations do not fit in %d byte",
3590 "%s relocations do not fit in %d bytes",
3592 howto->name, nbytes);
3595 /* We've parsed an expression stopping at O_symbol.
3596 But there may be more expression left now that we
3597 have parsed the relocation marker. Parse it again.
3598 XXX Surely there is a cleaner way to do this. */
3599 char *p = input_line_pointer;
3601 char *save_buf = XNEWVEC (char, input_line_pointer - base);
3603 memcpy (save_buf, base, input_line_pointer - base);
3604 memmove (base + (input_line_pointer - before_reloc),
3605 base, before_reloc - base);
3607 input_line_pointer = base + (input_line_pointer-before_reloc);
3609 memcpy (base, save_buf, p - base);
3611 offset = nbytes - size;
3612 p = frag_more (nbytes);
3613 memset (p, 0, nbytes);
3614 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3615 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3621 while (*input_line_pointer++ == ',');
3623 /* Put terminator back into stream. */
3624 input_line_pointer --;
3625 demand_empty_rest_of_line ();
3628 /* Emit an expression containing a 32-bit thumb instruction.
3629 Implementation based on put_thumb32_insn. */
3632 emit_thumb32_expr (expressionS * exp)
3634 expressionS exp_high = *exp;
3636 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3637 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3638 exp->X_add_number &= 0xffff;
3639 emit_expr (exp, (unsigned int) THUMB_SIZE);
3642 /* Guess the instruction size based on the opcode. */
3645 thumb_insn_size (int opcode)
3647 if ((unsigned int) opcode < 0xe800u)
3649 else if ((unsigned int) opcode >= 0xe8000000u)
3656 emit_insn (expressionS *exp, int nbytes)
3660 if (exp->X_op == O_constant)
3665 size = thumb_insn_size (exp->X_add_number);
3669 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3671 as_bad (_(".inst.n operand too big. "\
3672 "Use .inst.w instead"));
3677 if (now_it.state == AUTOMATIC_IT_BLOCK)
3678 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3680 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3682 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3683 emit_thumb32_expr (exp);
3685 emit_expr (exp, (unsigned int) size);
3687 it_fsm_post_encode ();
3691 as_bad (_("cannot determine Thumb instruction size. " \
3692 "Use .inst.n/.inst.w instead"));
3695 as_bad (_("constant expression required"));
3700 /* Like s_arm_elf_cons but do not use md_cons_align and
3701 set the mapping state to MAP_ARM/MAP_THUMB. */
3704 s_arm_elf_inst (int nbytes)
3706 if (is_it_end_of_statement ())
3708 demand_empty_rest_of_line ();
3712 /* Calling mapping_state () here will not change ARM/THUMB,
3713 but will ensure not to be in DATA state. */
3716 mapping_state (MAP_THUMB);
3721 as_bad (_("width suffixes are invalid in ARM mode"));
3722 ignore_rest_of_line ();
3728 mapping_state (MAP_ARM);
3737 if (! emit_insn (& exp, nbytes))
3739 ignore_rest_of_line ();
3743 while (*input_line_pointer++ == ',');
3745 /* Put terminator back into stream. */
3746 input_line_pointer --;
3747 demand_empty_rest_of_line ();
3750 /* Parse a .rel31 directive. */
3753 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3760 if (*input_line_pointer == '1')
3761 highbit = 0x80000000;
3762 else if (*input_line_pointer != '0')
3763 as_bad (_("expected 0 or 1"));
3765 input_line_pointer++;
3766 if (*input_line_pointer != ',')
3767 as_bad (_("missing comma"));
3768 input_line_pointer++;
3770 #ifdef md_flush_pending_output
3771 md_flush_pending_output ();
3774 #ifdef md_cons_align
3778 mapping_state (MAP_DATA);
3783 md_number_to_chars (p, highbit, 4);
3784 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3785 BFD_RELOC_ARM_PREL31);
3787 demand_empty_rest_of_line ();
3790 /* Directives: AEABI stack-unwind tables. */
3792 /* Parse an unwind_fnstart directive. Simply records the current location. */
3795 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3797 demand_empty_rest_of_line ();
3798 if (unwind.proc_start)
3800 as_bad (_("duplicate .fnstart directive"));
3804 /* Mark the start of the function. */
3805 unwind.proc_start = expr_build_dot ();
3807 /* Reset the rest of the unwind info. */
3808 unwind.opcode_count = 0;
3809 unwind.table_entry = NULL;
3810 unwind.personality_routine = NULL;
3811 unwind.personality_index = -1;
3812 unwind.frame_size = 0;
3813 unwind.fp_offset = 0;
3814 unwind.fp_reg = REG_SP;
3816 unwind.sp_restored = 0;
3820 /* Parse a handlerdata directive. Creates the exception handling table entry
3821 for the function. */
3824 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3826 demand_empty_rest_of_line ();
3827 if (!unwind.proc_start)
3828 as_bad (MISSING_FNSTART);
3830 if (unwind.table_entry)
3831 as_bad (_("duplicate .handlerdata directive"));
3833 create_unwind_entry (1);
3836 /* Parse an unwind_fnend directive. Generates the index table entry. */
3839 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3844 unsigned int marked_pr_dependency;
3846 demand_empty_rest_of_line ();
3848 if (!unwind.proc_start)
3850 as_bad (_(".fnend directive without .fnstart"));
3854 /* Add eh table entry. */
3855 if (unwind.table_entry == NULL)
3856 val = create_unwind_entry (0);
3860 /* Add index table entry. This is two words. */
3861 start_unwind_section (unwind.saved_seg, 1);
3862 frag_align (2, 0, 0);
3863 record_alignment (now_seg, 2);
3865 ptr = frag_more (8);
3867 where = frag_now_fix () - 8;
3869 /* Self relative offset of the function start. */
3870 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3871 BFD_RELOC_ARM_PREL31);
3873 /* Indicate dependency on EHABI-defined personality routines to the
3874 linker, if it hasn't been done already. */
3875 marked_pr_dependency
3876 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3877 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3878 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3880 static const char *const name[] =
3882 "__aeabi_unwind_cpp_pr0",
3883 "__aeabi_unwind_cpp_pr1",
3884 "__aeabi_unwind_cpp_pr2"
3886 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3887 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3888 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3889 |= 1 << unwind.personality_index;
3893 /* Inline exception table entry. */
3894 md_number_to_chars (ptr + 4, val, 4);
3896 /* Self relative offset of the table entry. */
3897 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3898 BFD_RELOC_ARM_PREL31);
3900 /* Restore the original section. */
3901 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3903 unwind.proc_start = NULL;
3907 /* Parse an unwind_cantunwind directive. */
3910 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3912 demand_empty_rest_of_line ();
3913 if (!unwind.proc_start)
3914 as_bad (MISSING_FNSTART);
3916 if (unwind.personality_routine || unwind.personality_index != -1)
3917 as_bad (_("personality routine specified for cantunwind frame"));
3919 unwind.personality_index = -2;
3923 /* Parse a personalityindex directive. */
3926 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3930 if (!unwind.proc_start)
3931 as_bad (MISSING_FNSTART);
3933 if (unwind.personality_routine || unwind.personality_index != -1)
3934 as_bad (_("duplicate .personalityindex directive"));
3938 if (exp.X_op != O_constant
3939 || exp.X_add_number < 0 || exp.X_add_number > 15)
3941 as_bad (_("bad personality routine number"));
3942 ignore_rest_of_line ();
3946 unwind.personality_index = exp.X_add_number;
3948 demand_empty_rest_of_line ();
3952 /* Parse a personality directive. */
3955 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3959 if (!unwind.proc_start)
3960 as_bad (MISSING_FNSTART);
3962 if (unwind.personality_routine || unwind.personality_index != -1)
3963 as_bad (_("duplicate .personality directive"));
3965 c = get_symbol_name (& name);
3966 p = input_line_pointer;
3968 ++ input_line_pointer;
3969 unwind.personality_routine = symbol_find_or_make (name);
3971 demand_empty_rest_of_line ();
3975 /* Parse a directive saving core registers. */
3978 s_arm_unwind_save_core (void)
3984 range = parse_reg_list (&input_line_pointer);
3987 as_bad (_("expected register list"));
3988 ignore_rest_of_line ();
3992 demand_empty_rest_of_line ();
3994 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3995 into .unwind_save {..., sp...}. We aren't bothered about the value of
3996 ip because it is clobbered by calls. */
3997 if (unwind.sp_restored && unwind.fp_reg == 12
3998 && (range & 0x3000) == 0x1000)
4000 unwind.opcode_count--;
4001 unwind.sp_restored = 0;
4002 range = (range | 0x2000) & ~0x1000;
4003 unwind.pending_offset = 0;
4009 /* See if we can use the short opcodes. These pop a block of up to 8
4010 registers starting with r4, plus maybe r14. */
4011 for (n = 0; n < 8; n++)
4013 /* Break at the first non-saved register. */
4014 if ((range & (1 << (n + 4))) == 0)
4017 /* See if there are any other bits set. */
4018 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4020 /* Use the long form. */
4021 op = 0x8000 | ((range >> 4) & 0xfff);
4022 add_unwind_opcode (op, 2);
4026 /* Use the short form. */
4028 op = 0xa8; /* Pop r14. */
4030 op = 0xa0; /* Do not pop r14. */
4032 add_unwind_opcode (op, 1);
4039 op = 0xb100 | (range & 0xf);
4040 add_unwind_opcode (op, 2);
4043 /* Record the number of bytes pushed. */
4044 for (n = 0; n < 16; n++)
4046 if (range & (1 << n))
4047 unwind.frame_size += 4;
4052 /* Parse a directive saving FPA registers. */
4055 s_arm_unwind_save_fpa (int reg)
4061 /* Get Number of registers to transfer. */
4062 if (skip_past_comma (&input_line_pointer) != FAIL)
4065 exp.X_op = O_illegal;
4067 if (exp.X_op != O_constant)
4069 as_bad (_("expected , <constant>"));
4070 ignore_rest_of_line ();
4074 num_regs = exp.X_add_number;
4076 if (num_regs < 1 || num_regs > 4)
4078 as_bad (_("number of registers must be in the range [1:4]"));
4079 ignore_rest_of_line ();
4083 demand_empty_rest_of_line ();
4088 op = 0xb4 | (num_regs - 1);
4089 add_unwind_opcode (op, 1);
4094 op = 0xc800 | (reg << 4) | (num_regs - 1);
4095 add_unwind_opcode (op, 2);
4097 unwind.frame_size += num_regs * 12;
4101 /* Parse a directive saving VFP registers for ARMv6 and above. */
4104 s_arm_unwind_save_vfp_armv6 (void)
4109 int num_vfpv3_regs = 0;
4110 int num_regs_below_16;
4112 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4115 as_bad (_("expected register list"));
4116 ignore_rest_of_line ();
4120 demand_empty_rest_of_line ();
4122 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4123 than FSTMX/FLDMX-style ones). */
4125 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4127 num_vfpv3_regs = count;
4128 else if (start + count > 16)
4129 num_vfpv3_regs = start + count - 16;
4131 if (num_vfpv3_regs > 0)
4133 int start_offset = start > 16 ? start - 16 : 0;
4134 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4135 add_unwind_opcode (op, 2);
4138 /* Generate opcode for registers numbered in the range 0 .. 15. */
4139 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4140 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4141 if (num_regs_below_16 > 0)
4143 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4144 add_unwind_opcode (op, 2);
4147 unwind.frame_size += count * 8;
4151 /* Parse a directive saving VFP registers for pre-ARMv6. */
4154 s_arm_unwind_save_vfp (void)
4160 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
4163 as_bad (_("expected register list"));
4164 ignore_rest_of_line ();
4168 demand_empty_rest_of_line ();
4173 op = 0xb8 | (count - 1);
4174 add_unwind_opcode (op, 1);
4179 op = 0xb300 | (reg << 4) | (count - 1);
4180 add_unwind_opcode (op, 2);
4182 unwind.frame_size += count * 8 + 4;
4186 /* Parse a directive saving iWMMXt data registers. */
4189 s_arm_unwind_save_mmxwr (void)
4197 if (*input_line_pointer == '{')
4198 input_line_pointer++;
4202 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4206 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4211 as_tsktsk (_("register list not in ascending order"));
4214 if (*input_line_pointer == '-')
4216 input_line_pointer++;
4217 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4220 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4223 else if (reg >= hi_reg)
4225 as_bad (_("bad register range"));
4228 for (; reg < hi_reg; reg++)
4232 while (skip_past_comma (&input_line_pointer) != FAIL);
4234 skip_past_char (&input_line_pointer, '}');
4236 demand_empty_rest_of_line ();
4238 /* Generate any deferred opcodes because we're going to be looking at
4240 flush_pending_unwind ();
4242 for (i = 0; i < 16; i++)
4244 if (mask & (1 << i))
4245 unwind.frame_size += 8;
4248 /* Attempt to combine with a previous opcode. We do this because gcc
4249 likes to output separate unwind directives for a single block of
4251 if (unwind.opcode_count > 0)
4253 i = unwind.opcodes[unwind.opcode_count - 1];
4254 if ((i & 0xf8) == 0xc0)
4257 /* Only merge if the blocks are contiguous. */
4260 if ((mask & 0xfe00) == (1 << 9))
4262 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4263 unwind.opcode_count--;
4266 else if (i == 6 && unwind.opcode_count >= 2)
4268 i = unwind.opcodes[unwind.opcode_count - 2];
4272 op = 0xffff << (reg - 1);
4274 && ((mask & op) == (1u << (reg - 1))))
4276 op = (1 << (reg + i + 1)) - 1;
4277 op &= ~((1 << reg) - 1);
4279 unwind.opcode_count -= 2;
4286 /* We want to generate opcodes in the order the registers have been
4287 saved, ie. descending order. */
4288 for (reg = 15; reg >= -1; reg--)
4290 /* Save registers in blocks. */
4292 || !(mask & (1 << reg)))
4294 /* We found an unsaved reg. Generate opcodes to save the
4301 op = 0xc0 | (hi_reg - 10);
4302 add_unwind_opcode (op, 1);
4307 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4308 add_unwind_opcode (op, 2);
4317 ignore_rest_of_line ();
4321 s_arm_unwind_save_mmxwcg (void)
4328 if (*input_line_pointer == '{')
4329 input_line_pointer++;
4331 skip_whitespace (input_line_pointer);
4335 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4339 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4345 as_tsktsk (_("register list not in ascending order"));
4348 if (*input_line_pointer == '-')
4350 input_line_pointer++;
4351 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4354 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4357 else if (reg >= hi_reg)
4359 as_bad (_("bad register range"));
4362 for (; reg < hi_reg; reg++)
4366 while (skip_past_comma (&input_line_pointer) != FAIL);
4368 skip_past_char (&input_line_pointer, '}');
4370 demand_empty_rest_of_line ();
4372 /* Generate any deferred opcodes because we're going to be looking at
4374 flush_pending_unwind ();
4376 for (reg = 0; reg < 16; reg++)
4378 if (mask & (1 << reg))
4379 unwind.frame_size += 4;
4382 add_unwind_opcode (op, 2);
4385 ignore_rest_of_line ();
4389 /* Parse an unwind_save directive.
4390 If the argument is non-zero, this is a .vsave directive. */
4393 s_arm_unwind_save (int arch_v6)
4396 struct reg_entry *reg;
4397 bfd_boolean had_brace = FALSE;
4399 if (!unwind.proc_start)
4400 as_bad (MISSING_FNSTART);
4402 /* Figure out what sort of save we have. */
4403 peek = input_line_pointer;
4411 reg = arm_reg_parse_multi (&peek);
4415 as_bad (_("register expected"));
4416 ignore_rest_of_line ();
4425 as_bad (_("FPA .unwind_save does not take a register list"));
4426 ignore_rest_of_line ();
4429 input_line_pointer = peek;
4430 s_arm_unwind_save_fpa (reg->number);
4434 s_arm_unwind_save_core ();
4439 s_arm_unwind_save_vfp_armv6 ();
4441 s_arm_unwind_save_vfp ();
4444 case REG_TYPE_MMXWR:
4445 s_arm_unwind_save_mmxwr ();
4448 case REG_TYPE_MMXWCG:
4449 s_arm_unwind_save_mmxwcg ();
4453 as_bad (_(".unwind_save does not support this kind of register"));
4454 ignore_rest_of_line ();
4459 /* Parse an unwind_movsp directive. */
4462 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4468 if (!unwind.proc_start)
4469 as_bad (MISSING_FNSTART);
4471 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4474 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4475 ignore_rest_of_line ();
4479 /* Optional constant. */
4480 if (skip_past_comma (&input_line_pointer) != FAIL)
4482 if (immediate_for_directive (&offset) == FAIL)
4488 demand_empty_rest_of_line ();
4490 if (reg == REG_SP || reg == REG_PC)
4492 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4496 if (unwind.fp_reg != REG_SP)
4497 as_bad (_("unexpected .unwind_movsp directive"));
4499 /* Generate opcode to restore the value. */
4501 add_unwind_opcode (op, 1);
4503 /* Record the information for later. */
4504 unwind.fp_reg = reg;
4505 unwind.fp_offset = unwind.frame_size - offset;
4506 unwind.sp_restored = 1;
4509 /* Parse an unwind_pad directive. */
4512 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4516 if (!unwind.proc_start)
4517 as_bad (MISSING_FNSTART);
4519 if (immediate_for_directive (&offset) == FAIL)
4524 as_bad (_("stack increment must be multiple of 4"));
4525 ignore_rest_of_line ();
4529 /* Don't generate any opcodes, just record the details for later. */
4530 unwind.frame_size += offset;
4531 unwind.pending_offset += offset;
4533 demand_empty_rest_of_line ();
4536 /* Parse an unwind_setfp directive. */
4539 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4545 if (!unwind.proc_start)
4546 as_bad (MISSING_FNSTART);
4548 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4549 if (skip_past_comma (&input_line_pointer) == FAIL)
4552 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4554 if (fp_reg == FAIL || sp_reg == FAIL)
4556 as_bad (_("expected <reg>, <reg>"));
4557 ignore_rest_of_line ();
4561 /* Optional constant. */
4562 if (skip_past_comma (&input_line_pointer) != FAIL)
4564 if (immediate_for_directive (&offset) == FAIL)
4570 demand_empty_rest_of_line ();
4572 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4574 as_bad (_("register must be either sp or set by a previous"
4575 "unwind_movsp directive"));
4579 /* Don't generate any opcodes, just record the information for later. */
4580 unwind.fp_reg = fp_reg;
4582 if (sp_reg == REG_SP)
4583 unwind.fp_offset = unwind.frame_size - offset;
4585 unwind.fp_offset -= offset;
4588 /* Parse an unwind_raw directive. */
4591 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4594 /* This is an arbitrary limit. */
4595 unsigned char op[16];
4598 if (!unwind.proc_start)
4599 as_bad (MISSING_FNSTART);
4602 if (exp.X_op == O_constant
4603 && skip_past_comma (&input_line_pointer) != FAIL)
4605 unwind.frame_size += exp.X_add_number;
4609 exp.X_op = O_illegal;
4611 if (exp.X_op != O_constant)
4613 as_bad (_("expected <offset>, <opcode>"));
4614 ignore_rest_of_line ();
4620 /* Parse the opcode. */
4625 as_bad (_("unwind opcode too long"));
4626 ignore_rest_of_line ();
4628 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4630 as_bad (_("invalid unwind opcode"));
4631 ignore_rest_of_line ();
4634 op[count++] = exp.X_add_number;
4636 /* Parse the next byte. */
4637 if (skip_past_comma (&input_line_pointer) == FAIL)
4643 /* Add the opcode bytes in reverse order. */
4645 add_unwind_opcode (op[count], 1);
4647 demand_empty_rest_of_line ();
4651 /* Parse a .eabi_attribute directive. */
4654 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4656 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4658 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4659 attributes_set_explicitly[tag] = 1;
4662 /* Emit a tls fix for the symbol. */
4665 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4669 #ifdef md_flush_pending_output
4670 md_flush_pending_output ();
4673 #ifdef md_cons_align
4677 /* Since we're just labelling the code, there's no need to define a
4680 p = obstack_next_free (&frchain_now->frch_obstack);
4681 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4682 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4683 : BFD_RELOC_ARM_TLS_DESCSEQ);
4685 #endif /* OBJ_ELF */
4687 static void s_arm_arch (int);
4688 static void s_arm_object_arch (int);
4689 static void s_arm_cpu (int);
4690 static void s_arm_fpu (int);
4691 static void s_arm_arch_extension (int);
4696 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4703 if (exp.X_op == O_symbol)
4704 exp.X_op = O_secrel;
4706 emit_expr (&exp, 4);
4708 while (*input_line_pointer++ == ',');
4710 input_line_pointer--;
4711 demand_empty_rest_of_line ();
4715 /* This table describes all the machine specific pseudo-ops the assembler
4716 has to support. The fields are:
4717 pseudo-op name without dot
4718 function to call to execute this pseudo-op
4719 Integer arg to pass to the function. */
4721 const pseudo_typeS md_pseudo_table[] =
4723 /* Never called because '.req' does not start a line. */
4724 { "req", s_req, 0 },
4725 /* Following two are likewise never called. */
4728 { "unreq", s_unreq, 0 },
4729 { "bss", s_bss, 0 },
4730 { "align", s_align_ptwo, 2 },
4731 { "arm", s_arm, 0 },
4732 { "thumb", s_thumb, 0 },
4733 { "code", s_code, 0 },
4734 { "force_thumb", s_force_thumb, 0 },
4735 { "thumb_func", s_thumb_func, 0 },
4736 { "thumb_set", s_thumb_set, 0 },
4737 { "even", s_even, 0 },
4738 { "ltorg", s_ltorg, 0 },
4739 { "pool", s_ltorg, 0 },
4740 { "syntax", s_syntax, 0 },
4741 { "cpu", s_arm_cpu, 0 },
4742 { "arch", s_arm_arch, 0 },
4743 { "object_arch", s_arm_object_arch, 0 },
4744 { "fpu", s_arm_fpu, 0 },
4745 { "arch_extension", s_arm_arch_extension, 0 },
4747 { "word", s_arm_elf_cons, 4 },
4748 { "long", s_arm_elf_cons, 4 },
4749 { "inst.n", s_arm_elf_inst, 2 },
4750 { "inst.w", s_arm_elf_inst, 4 },
4751 { "inst", s_arm_elf_inst, 0 },
4752 { "rel31", s_arm_rel31, 0 },
4753 { "fnstart", s_arm_unwind_fnstart, 0 },
4754 { "fnend", s_arm_unwind_fnend, 0 },
4755 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4756 { "personality", s_arm_unwind_personality, 0 },
4757 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4758 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4759 { "save", s_arm_unwind_save, 0 },
4760 { "vsave", s_arm_unwind_save, 1 },
4761 { "movsp", s_arm_unwind_movsp, 0 },
4762 { "pad", s_arm_unwind_pad, 0 },
4763 { "setfp", s_arm_unwind_setfp, 0 },
4764 { "unwind_raw", s_arm_unwind_raw, 0 },
4765 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4766 { "tlsdescseq", s_arm_tls_descseq, 0 },
4770 /* These are used for dwarf. */
4774 /* These are used for dwarf2. */
4775 { "file", dwarf2_directive_file, 0 },
4776 { "loc", dwarf2_directive_loc, 0 },
4777 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4779 { "extend", float_cons, 'x' },
4780 { "ldouble", float_cons, 'x' },
4781 { "packed", float_cons, 'p' },
4783 {"secrel32", pe_directive_secrel, 0},
4786 /* These are for compatibility with CodeComposer Studio. */
4787 {"ref", s_ccs_ref, 0},
4788 {"def", s_ccs_def, 0},
4789 {"asmfunc", s_ccs_asmfunc, 0},
4790 {"endasmfunc", s_ccs_endasmfunc, 0},
4795 /* Parser functions used exclusively in instruction operands. */
4797 /* Generic immediate-value read function for use in insn parsing.
4798 STR points to the beginning of the immediate (the leading #);
4799 VAL receives the value; if the value is outside [MIN, MAX]
4800 issue an error. PREFIX_OPT is true if the immediate prefix is
4804 parse_immediate (char **str, int *val, int min, int max,
4805 bfd_boolean prefix_opt)
4809 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4810 if (exp.X_op != O_constant)
4812 inst.error = _("constant expression required");
4816 if (exp.X_add_number < min || exp.X_add_number > max)
4818 inst.error = _("immediate value out of range");
4822 *val = exp.X_add_number;
4826 /* Less-generic immediate-value read function with the possibility of loading a
4827 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4828 instructions. Puts the result directly in inst.operands[i]. */
4831 parse_big_immediate (char **str, int i, expressionS *in_exp,
4832 bfd_boolean allow_symbol_p)
4835 expressionS *exp_p = in_exp ? in_exp : &exp;
4838 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
4840 if (exp_p->X_op == O_constant)
4842 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
4843 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4844 O_constant. We have to be careful not to break compilation for
4845 32-bit X_add_number, though. */
4846 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4848 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4849 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4851 inst.operands[i].regisimm = 1;
4854 else if (exp_p->X_op == O_big
4855 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
4857 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4859 /* Bignums have their least significant bits in
4860 generic_bignum[0]. Make sure we put 32 bits in imm and
4861 32 bits in reg, in a (hopefully) portable way. */
4862 gas_assert (parts != 0);
4864 /* Make sure that the number is not too big.
4865 PR 11972: Bignums can now be sign-extended to the
4866 size of a .octa so check that the out of range bits
4867 are all zero or all one. */
4868 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
4870 LITTLENUM_TYPE m = -1;
4872 if (generic_bignum[parts * 2] != 0
4873 && generic_bignum[parts * 2] != m)
4876 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
4877 if (generic_bignum[j] != generic_bignum[j-1])
4881 inst.operands[i].imm = 0;
4882 for (j = 0; j < parts; j++, idx++)
4883 inst.operands[i].imm |= generic_bignum[idx]
4884 << (LITTLENUM_NUMBER_OF_BITS * j);
4885 inst.operands[i].reg = 0;
4886 for (j = 0; j < parts; j++, idx++)
4887 inst.operands[i].reg |= generic_bignum[idx]
4888 << (LITTLENUM_NUMBER_OF_BITS * j);
4889 inst.operands[i].regisimm = 1;
4891 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
4899 /* Returns the pseudo-register number of an FPA immediate constant,
4900 or FAIL if there isn't a valid constant here. */
4903 parse_fpa_immediate (char ** str)
4905 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4911 /* First try and match exact strings, this is to guarantee
4912 that some formats will work even for cross assembly. */
4914 for (i = 0; fp_const[i]; i++)
4916 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4920 *str += strlen (fp_const[i]);
4921 if (is_end_of_line[(unsigned char) **str])
4927 /* Just because we didn't get a match doesn't mean that the constant
4928 isn't valid, just that it is in a format that we don't
4929 automatically recognize. Try parsing it with the standard
4930 expression routines. */
4932 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4934 /* Look for a raw floating point number. */
4935 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4936 && is_end_of_line[(unsigned char) *save_in])
4938 for (i = 0; i < NUM_FLOAT_VALS; i++)
4940 for (j = 0; j < MAX_LITTLENUMS; j++)
4942 if (words[j] != fp_values[i][j])
4946 if (j == MAX_LITTLENUMS)
4954 /* Try and parse a more complex expression, this will probably fail
4955 unless the code uses a floating point prefix (eg "0f"). */
4956 save_in = input_line_pointer;
4957 input_line_pointer = *str;
4958 if (expression (&exp) == absolute_section
4959 && exp.X_op == O_big
4960 && exp.X_add_number < 0)
4962 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4964 #define X_PRECISION 5
4965 #define E_PRECISION 15L
4966 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
4968 for (i = 0; i < NUM_FLOAT_VALS; i++)
4970 for (j = 0; j < MAX_LITTLENUMS; j++)
4972 if (words[j] != fp_values[i][j])
4976 if (j == MAX_LITTLENUMS)
4978 *str = input_line_pointer;
4979 input_line_pointer = save_in;
4986 *str = input_line_pointer;
4987 input_line_pointer = save_in;
4988 inst.error = _("invalid FPA immediate expression");
4992 /* Returns 1 if a number has "quarter-precision" float format
4993 0baBbbbbbc defgh000 00000000 00000000. */
4996 is_quarter_float (unsigned imm)
4998 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4999 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5003 /* Detect the presence of a floating point or integer zero constant,
5007 parse_ifimm_zero (char **in)
5011 if (!is_immediate_prefix (**in))
5013 /* In unified syntax, all prefixes are optional. */
5014 if (!unified_syntax)
5020 /* Accept #0x0 as a synonym for #0. */
5021 if (strncmp (*in, "0x", 2) == 0)
5024 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5029 error_code = atof_generic (in, ".", EXP_CHARS,
5030 &generic_floating_point_number);
5033 && generic_floating_point_number.sign == '+'
5034 && (generic_floating_point_number.low
5035 > generic_floating_point_number.leader))
5041 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5042 0baBbbbbbc defgh000 00000000 00000000.
5043 The zero and minus-zero cases need special handling, since they can't be
5044 encoded in the "quarter-precision" float format, but can nonetheless be
5045 loaded as integer constants. */
5048 parse_qfloat_immediate (char **ccp, int *immed)
5052 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5053 int found_fpchar = 0;
5055 skip_past_char (&str, '#');
5057 /* We must not accidentally parse an integer as a floating-point number. Make
5058 sure that the value we parse is not an integer by checking for special
5059 characters '.' or 'e'.
5060 FIXME: This is a horrible hack, but doing better is tricky because type
5061 information isn't in a very usable state at parse time. */
5063 skip_whitespace (fpnum);
5065 if (strncmp (fpnum, "0x", 2) == 0)
5069 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5070 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5080 if ((str = atof_ieee (str, 's', words)) != NULL)
5082 unsigned fpword = 0;
5085 /* Our FP word must be 32 bits (single-precision FP). */
5086 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5088 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5092 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5105 /* Shift operands. */
5108 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5111 struct asm_shift_name
5114 enum shift_kind kind;
5117 /* Third argument to parse_shift. */
5118 enum parse_shift_mode
5120 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5121 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5122 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5123 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5124 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5127 /* Parse a <shift> specifier on an ARM data processing instruction.
5128 This has three forms:
5130 (LSL|LSR|ASL|ASR|ROR) Rs
5131 (LSL|LSR|ASL|ASR|ROR) #imm
5134 Note that ASL is assimilated to LSL in the instruction encoding, and
5135 RRX to ROR #0 (which cannot be written as such). */
5138 parse_shift (char **str, int i, enum parse_shift_mode mode)
5140 const struct asm_shift_name *shift_name;
5141 enum shift_kind shift;
5146 for (p = *str; ISALPHA (*p); p++)
5151 inst.error = _("shift expression expected");
5155 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5158 if (shift_name == NULL)
5160 inst.error = _("shift expression expected");
5164 shift = shift_name->kind;
5168 case NO_SHIFT_RESTRICT:
5169 case SHIFT_IMMEDIATE: break;
5171 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5172 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5174 inst.error = _("'LSL' or 'ASR' required");
5179 case SHIFT_LSL_IMMEDIATE:
5180 if (shift != SHIFT_LSL)
5182 inst.error = _("'LSL' required");
5187 case SHIFT_ASR_IMMEDIATE:
5188 if (shift != SHIFT_ASR)
5190 inst.error = _("'ASR' required");
5198 if (shift != SHIFT_RRX)
5200 /* Whitespace can appear here if the next thing is a bare digit. */
5201 skip_whitespace (p);
5203 if (mode == NO_SHIFT_RESTRICT
5204 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5206 inst.operands[i].imm = reg;
5207 inst.operands[i].immisreg = 1;
5209 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5212 inst.operands[i].shift_kind = shift;
5213 inst.operands[i].shifted = 1;
5218 /* Parse a <shifter_operand> for an ARM data processing instruction:
5221 #<immediate>, <rotate>
5225 where <shift> is defined by parse_shift above, and <rotate> is a
5226 multiple of 2 between 0 and 30. Validation of immediate operands
5227 is deferred to md_apply_fix. */
5230 parse_shifter_operand (char **str, int i)
5235 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5237 inst.operands[i].reg = value;
5238 inst.operands[i].isreg = 1;
5240 /* parse_shift will override this if appropriate */
5241 inst.reloc.exp.X_op = O_constant;
5242 inst.reloc.exp.X_add_number = 0;
5244 if (skip_past_comma (str) == FAIL)
5247 /* Shift operation on register. */
5248 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5251 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5254 if (skip_past_comma (str) == SUCCESS)
5256 /* #x, y -- ie explicit rotation by Y. */
5257 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5260 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
5262 inst.error = _("constant expression expected");
5266 value = exp.X_add_number;
5267 if (value < 0 || value > 30 || value % 2 != 0)
5269 inst.error = _("invalid rotation");
5272 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5274 inst.error = _("invalid constant");
5278 /* Encode as specified. */
5279 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5283 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5284 inst.reloc.pc_rel = 0;
5288 /* Group relocation information. Each entry in the table contains the
5289 textual name of the relocation as may appear in assembler source
5290 and must end with a colon.
5291 Along with this textual name are the relocation codes to be used if
5292 the corresponding instruction is an ALU instruction (ADD or SUB only),
5293 an LDR, an LDRS, or an LDC. */
5295 struct group_reloc_table_entry
5306 /* Varieties of non-ALU group relocation. */
5313 static struct group_reloc_table_entry group_reloc_table[] =
5314 { /* Program counter relative: */
5316 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5321 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5322 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5323 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5324 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5326 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5331 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5332 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5333 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5334 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5336 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5337 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5338 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5339 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5340 /* Section base relative */
5342 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5347 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5348 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5349 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5350 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5352 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5357 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5358 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5359 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5360 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5362 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5363 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5364 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5365 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5366 /* Absolute thumb alu relocations. */
5368 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5373 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5378 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5383 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5388 /* Given the address of a pointer pointing to the textual name of a group
5389 relocation as may appear in assembler source, attempt to find its details
5390 in group_reloc_table. The pointer will be updated to the character after
5391 the trailing colon. On failure, FAIL will be returned; SUCCESS
5392 otherwise. On success, *entry will be updated to point at the relevant
5393 group_reloc_table entry. */
5396 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5399 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5401 int length = strlen (group_reloc_table[i].name);
5403 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5404 && (*str)[length] == ':')
5406 *out = &group_reloc_table[i];
5407 *str += (length + 1);
5415 /* Parse a <shifter_operand> for an ARM data processing instruction
5416 (as for parse_shifter_operand) where group relocations are allowed:
5419 #<immediate>, <rotate>
5420 #:<group_reloc>:<expression>
5424 where <group_reloc> is one of the strings defined in group_reloc_table.
5425 The hashes are optional.
5427 Everything else is as for parse_shifter_operand. */
5429 static parse_operand_result
5430 parse_shifter_operand_group_reloc (char **str, int i)
5432 /* Determine if we have the sequence of characters #: or just :
5433 coming next. If we do, then we check for a group relocation.
5434 If we don't, punt the whole lot to parse_shifter_operand. */
5436 if (((*str)[0] == '#' && (*str)[1] == ':')
5437 || (*str)[0] == ':')
5439 struct group_reloc_table_entry *entry;
5441 if ((*str)[0] == '#')
5446 /* Try to parse a group relocation. Anything else is an error. */
5447 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5449 inst.error = _("unknown group relocation");
5450 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5453 /* We now have the group relocation table entry corresponding to
5454 the name in the assembler source. Next, we parse the expression. */
5455 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5456 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5458 /* Record the relocation type (always the ALU variant here). */
5459 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5460 gas_assert (inst.reloc.type != 0);
5462 return PARSE_OPERAND_SUCCESS;
5465 return parse_shifter_operand (str, i) == SUCCESS
5466 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5468 /* Never reached. */
5471 /* Parse a Neon alignment expression. Information is written to
5472 inst.operands[i]. We assume the initial ':' has been skipped.
5474 align .imm = align << 8, .immisalign=1, .preind=0 */
5475 static parse_operand_result
5476 parse_neon_alignment (char **str, int i)
5481 my_get_expression (&exp, &p, GE_NO_PREFIX);
5483 if (exp.X_op != O_constant)
5485 inst.error = _("alignment must be constant");
5486 return PARSE_OPERAND_FAIL;
5489 inst.operands[i].imm = exp.X_add_number << 8;
5490 inst.operands[i].immisalign = 1;
5491 /* Alignments are not pre-indexes. */
5492 inst.operands[i].preind = 0;
5495 return PARSE_OPERAND_SUCCESS;
5498 /* Parse all forms of an ARM address expression. Information is written
5499 to inst.operands[i] and/or inst.reloc.
5501 Preindexed addressing (.preind=1):
5503 [Rn, #offset] .reg=Rn .reloc.exp=offset
5504 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5505 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5506 .shift_kind=shift .reloc.exp=shift_imm
5508 These three may have a trailing ! which causes .writeback to be set also.
5510 Postindexed addressing (.postind=1, .writeback=1):
5512 [Rn], #offset .reg=Rn .reloc.exp=offset
5513 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5514 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5515 .shift_kind=shift .reloc.exp=shift_imm
5517 Unindexed addressing (.preind=0, .postind=0):
5519 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5523 [Rn]{!} shorthand for [Rn,#0]{!}
5524 =immediate .isreg=0 .reloc.exp=immediate
5525 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5527 It is the caller's responsibility to check for addressing modes not
5528 supported by the instruction, and to set inst.reloc.type. */
5530 static parse_operand_result
5531 parse_address_main (char **str, int i, int group_relocations,
5532 group_reloc_type group_type)
5537 if (skip_past_char (&p, '[') == FAIL)
5539 if (skip_past_char (&p, '=') == FAIL)
5541 /* Bare address - translate to PC-relative offset. */
5542 inst.reloc.pc_rel = 1;
5543 inst.operands[i].reg = REG_PC;
5544 inst.operands[i].isreg = 1;
5545 inst.operands[i].preind = 1;
5547 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5548 return PARSE_OPERAND_FAIL;
5550 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5551 /*allow_symbol_p=*/TRUE))
5552 return PARSE_OPERAND_FAIL;
5555 return PARSE_OPERAND_SUCCESS;
5558 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5559 skip_whitespace (p);
5561 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5563 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5564 return PARSE_OPERAND_FAIL;
5566 inst.operands[i].reg = reg;
5567 inst.operands[i].isreg = 1;
5569 if (skip_past_comma (&p) == SUCCESS)
5571 inst.operands[i].preind = 1;
5574 else if (*p == '-') p++, inst.operands[i].negative = 1;
5576 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5578 inst.operands[i].imm = reg;
5579 inst.operands[i].immisreg = 1;
5581 if (skip_past_comma (&p) == SUCCESS)
5582 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5583 return PARSE_OPERAND_FAIL;
5585 else if (skip_past_char (&p, ':') == SUCCESS)
5587 /* FIXME: '@' should be used here, but it's filtered out by generic
5588 code before we get to see it here. This may be subject to
5590 parse_operand_result result = parse_neon_alignment (&p, i);
5592 if (result != PARSE_OPERAND_SUCCESS)
5597 if (inst.operands[i].negative)
5599 inst.operands[i].negative = 0;
5603 if (group_relocations
5604 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5606 struct group_reloc_table_entry *entry;
5608 /* Skip over the #: or : sequence. */
5614 /* Try to parse a group relocation. Anything else is an
5616 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5618 inst.error = _("unknown group relocation");
5619 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5622 /* We now have the group relocation table entry corresponding to
5623 the name in the assembler source. Next, we parse the
5625 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5626 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5628 /* Record the relocation type. */
5632 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5636 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5640 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5647 if (inst.reloc.type == 0)
5649 inst.error = _("this group relocation is not allowed on this instruction");
5650 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5657 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5658 return PARSE_OPERAND_FAIL;
5659 /* If the offset is 0, find out if it's a +0 or -0. */
5660 if (inst.reloc.exp.X_op == O_constant
5661 && inst.reloc.exp.X_add_number == 0)
5663 skip_whitespace (q);
5667 skip_whitespace (q);
5670 inst.operands[i].negative = 1;
5675 else if (skip_past_char (&p, ':') == SUCCESS)
5677 /* FIXME: '@' should be used here, but it's filtered out by generic code
5678 before we get to see it here. This may be subject to change. */
5679 parse_operand_result result = parse_neon_alignment (&p, i);
5681 if (result != PARSE_OPERAND_SUCCESS)
5685 if (skip_past_char (&p, ']') == FAIL)
5687 inst.error = _("']' expected");
5688 return PARSE_OPERAND_FAIL;
5691 if (skip_past_char (&p, '!') == SUCCESS)
5692 inst.operands[i].writeback = 1;
5694 else if (skip_past_comma (&p) == SUCCESS)
5696 if (skip_past_char (&p, '{') == SUCCESS)
5698 /* [Rn], {expr} - unindexed, with option */
5699 if (parse_immediate (&p, &inst.operands[i].imm,
5700 0, 255, TRUE) == FAIL)
5701 return PARSE_OPERAND_FAIL;
5703 if (skip_past_char (&p, '}') == FAIL)
5705 inst.error = _("'}' expected at end of 'option' field");
5706 return PARSE_OPERAND_FAIL;
5708 if (inst.operands[i].preind)
5710 inst.error = _("cannot combine index with option");
5711 return PARSE_OPERAND_FAIL;
5714 return PARSE_OPERAND_SUCCESS;
5718 inst.operands[i].postind = 1;
5719 inst.operands[i].writeback = 1;
5721 if (inst.operands[i].preind)
5723 inst.error = _("cannot combine pre- and post-indexing");
5724 return PARSE_OPERAND_FAIL;
5728 else if (*p == '-') p++, inst.operands[i].negative = 1;
5730 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5732 /* We might be using the immediate for alignment already. If we
5733 are, OR the register number into the low-order bits. */
5734 if (inst.operands[i].immisalign)
5735 inst.operands[i].imm |= reg;
5737 inst.operands[i].imm = reg;
5738 inst.operands[i].immisreg = 1;
5740 if (skip_past_comma (&p) == SUCCESS)
5741 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5742 return PARSE_OPERAND_FAIL;
5748 if (inst.operands[i].negative)
5750 inst.operands[i].negative = 0;
5753 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5754 return PARSE_OPERAND_FAIL;
5755 /* If the offset is 0, find out if it's a +0 or -0. */
5756 if (inst.reloc.exp.X_op == O_constant
5757 && inst.reloc.exp.X_add_number == 0)
5759 skip_whitespace (q);
5763 skip_whitespace (q);
5766 inst.operands[i].negative = 1;
5772 /* If at this point neither .preind nor .postind is set, we have a
5773 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5774 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5776 inst.operands[i].preind = 1;
5777 inst.reloc.exp.X_op = O_constant;
5778 inst.reloc.exp.X_add_number = 0;
5781 return PARSE_OPERAND_SUCCESS;
5785 parse_address (char **str, int i)
5787 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5791 static parse_operand_result
5792 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5794 return parse_address_main (str, i, 1, type);
5797 /* Parse an operand for a MOVW or MOVT instruction. */
5799 parse_half (char **str)
5804 skip_past_char (&p, '#');
5805 if (strncasecmp (p, ":lower16:", 9) == 0)
5806 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5807 else if (strncasecmp (p, ":upper16:", 9) == 0)
5808 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5810 if (inst.reloc.type != BFD_RELOC_UNUSED)
5813 skip_whitespace (p);
5816 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5819 if (inst.reloc.type == BFD_RELOC_UNUSED)
5821 if (inst.reloc.exp.X_op != O_constant)
5823 inst.error = _("constant expression expected");
5826 if (inst.reloc.exp.X_add_number < 0
5827 || inst.reloc.exp.X_add_number > 0xffff)
5829 inst.error = _("immediate value out of range");
5837 /* Miscellaneous. */
5839 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5840 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5842 parse_psr (char **str, bfd_boolean lhs)
5845 unsigned long psr_field;
5846 const struct asm_psr *psr;
5848 bfd_boolean is_apsr = FALSE;
5849 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5851 /* PR gas/12698: If the user has specified -march=all then m_profile will
5852 be TRUE, but we want to ignore it in this case as we are building for any
5853 CPU type, including non-m variants. */
5854 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
5857 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5858 feature for ease of use and backwards compatibility. */
5860 if (strncasecmp (p, "SPSR", 4) == 0)
5863 goto unsupported_psr;
5865 psr_field = SPSR_BIT;
5867 else if (strncasecmp (p, "CPSR", 4) == 0)
5870 goto unsupported_psr;
5874 else if (strncasecmp (p, "APSR", 4) == 0)
5876 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5877 and ARMv7-R architecture CPUs. */
5886 while (ISALNUM (*p) || *p == '_');
5888 if (strncasecmp (start, "iapsr", 5) == 0
5889 || strncasecmp (start, "eapsr", 5) == 0
5890 || strncasecmp (start, "xpsr", 4) == 0
5891 || strncasecmp (start, "psr", 3) == 0)
5892 p = start + strcspn (start, "rR") + 1;
5894 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5900 /* If APSR is being written, a bitfield may be specified. Note that
5901 APSR itself is handled above. */
5902 if (psr->field <= 3)
5904 psr_field = psr->field;
5910 /* M-profile MSR instructions have the mask field set to "10", except
5911 *PSR variants which modify APSR, which may use a different mask (and
5912 have been handled already). Do that by setting the PSR_f field
5914 return psr->field | (lhs ? PSR_f : 0);
5917 goto unsupported_psr;
5923 /* A suffix follows. */
5929 while (ISALNUM (*p) || *p == '_');
5933 /* APSR uses a notation for bits, rather than fields. */
5934 unsigned int nzcvq_bits = 0;
5935 unsigned int g_bit = 0;
5938 for (bit = start; bit != p; bit++)
5940 switch (TOLOWER (*bit))
5943 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5947 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5951 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5955 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5959 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5963 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5967 inst.error = _("unexpected bit specified after APSR");
5972 if (nzcvq_bits == 0x1f)
5977 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5979 inst.error = _("selected processor does not "
5980 "support DSP extension");
5987 if ((nzcvq_bits & 0x20) != 0
5988 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5989 || (g_bit & 0x2) != 0)
5991 inst.error = _("bad bitmask specified after APSR");
5997 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
6002 psr_field |= psr->field;
6008 goto error; /* Garbage after "[CS]PSR". */
6010 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6011 is deprecated, but allow it anyway. */
6015 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6018 else if (!m_profile)
6019 /* These bits are never right for M-profile devices: don't set them
6020 (only code paths which read/write APSR reach here). */
6021 psr_field |= (PSR_c | PSR_f);
6027 inst.error = _("selected processor does not support requested special "
6028 "purpose register");
6032 inst.error = _("flag for {c}psr instruction expected");
6036 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6037 value suitable for splatting into the AIF field of the instruction. */
6040 parse_cps_flags (char **str)
6049 case '\0': case ',':
6052 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6053 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6054 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6057 inst.error = _("unrecognized CPS flag");
6062 if (saw_a_flag == 0)
6064 inst.error = _("missing CPS flags");
6072 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6073 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6076 parse_endian_specifier (char **str)
6081 if (strncasecmp (s, "BE", 2))
6083 else if (strncasecmp (s, "LE", 2))
6087 inst.error = _("valid endian specifiers are be or le");
6091 if (ISALNUM (s[2]) || s[2] == '_')
6093 inst.error = _("valid endian specifiers are be or le");
6098 return little_endian;
6101 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6102 value suitable for poking into the rotate field of an sxt or sxta
6103 instruction, or FAIL on error. */
6106 parse_ror (char **str)
6111 if (strncasecmp (s, "ROR", 3) == 0)
6115 inst.error = _("missing rotation field after comma");
6119 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6124 case 0: *str = s; return 0x0;
6125 case 8: *str = s; return 0x1;
6126 case 16: *str = s; return 0x2;
6127 case 24: *str = s; return 0x3;
6130 inst.error = _("rotation can only be 0, 8, 16, or 24");
6135 /* Parse a conditional code (from conds[] below). The value returned is in the
6136 range 0 .. 14, or FAIL. */
6138 parse_cond (char **str)
6141 const struct asm_cond *c;
6143 /* Condition codes are always 2 characters, so matching up to
6144 3 characters is sufficient. */
6149 while (ISALPHA (*q) && n < 3)
6151 cond[n] = TOLOWER (*q);
6156 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6159 inst.error = _("condition required");
6167 /* Record a use of the given feature. */
6169 record_feature_use (const arm_feature_set *feature)
6172 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6174 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6177 /* If the given feature is currently allowed, mark it as used and return TRUE.
6178 Return FALSE otherwise. */
6180 mark_feature_used (const arm_feature_set *feature)
6182 /* Ensure the option is currently allowed. */
6183 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6186 /* Add the appropriate architecture feature for the barrier option used. */
6187 record_feature_use (feature);
6192 /* Parse an option for a barrier instruction. Returns the encoding for the
6195 parse_barrier (char **str)
6198 const struct asm_barrier_opt *o;
6201 while (ISALPHA (*q))
6204 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6209 if (!mark_feature_used (&o->arch))
6216 /* Parse the operands of a table branch instruction. Similar to a memory
6219 parse_tb (char **str)
6224 if (skip_past_char (&p, '[') == FAIL)
6226 inst.error = _("'[' expected");
6230 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6232 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6235 inst.operands[0].reg = reg;
6237 if (skip_past_comma (&p) == FAIL)
6239 inst.error = _("',' expected");
6243 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6245 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6248 inst.operands[0].imm = reg;
6250 if (skip_past_comma (&p) == SUCCESS)
6252 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6254 if (inst.reloc.exp.X_add_number != 1)
6256 inst.error = _("invalid shift");
6259 inst.operands[0].shifted = 1;
6262 if (skip_past_char (&p, ']') == FAIL)
6264 inst.error = _("']' expected");
6271 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6272 information on the types the operands can take and how they are encoded.
6273 Up to four operands may be read; this function handles setting the
6274 ".present" field for each read operand itself.
6275 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6276 else returns FAIL. */
6279 parse_neon_mov (char **str, int *which_operand)
6281 int i = *which_operand, val;
6282 enum arm_reg_type rtype;
6284 struct neon_type_el optype;
6286 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6288 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6289 inst.operands[i].reg = val;
6290 inst.operands[i].isscalar = 1;
6291 inst.operands[i].vectype = optype;
6292 inst.operands[i++].present = 1;
6294 if (skip_past_comma (&ptr) == FAIL)
6297 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6300 inst.operands[i].reg = val;
6301 inst.operands[i].isreg = 1;
6302 inst.operands[i].present = 1;
6304 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6307 /* Cases 0, 1, 2, 3, 5 (D only). */
6308 if (skip_past_comma (&ptr) == FAIL)
6311 inst.operands[i].reg = val;
6312 inst.operands[i].isreg = 1;
6313 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6314 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6315 inst.operands[i].isvec = 1;
6316 inst.operands[i].vectype = optype;
6317 inst.operands[i++].present = 1;
6319 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6321 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6322 Case 13: VMOV <Sd>, <Rm> */
6323 inst.operands[i].reg = val;
6324 inst.operands[i].isreg = 1;
6325 inst.operands[i].present = 1;
6327 if (rtype == REG_TYPE_NQ)
6329 first_error (_("can't use Neon quad register here"));
6332 else if (rtype != REG_TYPE_VFS)
6335 if (skip_past_comma (&ptr) == FAIL)
6337 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6339 inst.operands[i].reg = val;
6340 inst.operands[i].isreg = 1;
6341 inst.operands[i].present = 1;
6344 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6347 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6348 Case 1: VMOV<c><q> <Dd>, <Dm>
6349 Case 8: VMOV.F32 <Sd>, <Sm>
6350 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6352 inst.operands[i].reg = val;
6353 inst.operands[i].isreg = 1;
6354 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6355 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6356 inst.operands[i].isvec = 1;
6357 inst.operands[i].vectype = optype;
6358 inst.operands[i].present = 1;
6360 if (skip_past_comma (&ptr) == SUCCESS)
6365 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6368 inst.operands[i].reg = val;
6369 inst.operands[i].isreg = 1;
6370 inst.operands[i++].present = 1;
6372 if (skip_past_comma (&ptr) == FAIL)
6375 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6378 inst.operands[i].reg = val;
6379 inst.operands[i].isreg = 1;
6380 inst.operands[i].present = 1;
6383 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6384 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6385 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6386 Case 10: VMOV.F32 <Sd>, #<imm>
6387 Case 11: VMOV.F64 <Dd>, #<imm> */
6388 inst.operands[i].immisfloat = 1;
6389 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6391 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6392 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6396 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6400 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6403 inst.operands[i].reg = val;
6404 inst.operands[i].isreg = 1;
6405 inst.operands[i++].present = 1;
6407 if (skip_past_comma (&ptr) == FAIL)
6410 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6412 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6413 inst.operands[i].reg = val;
6414 inst.operands[i].isscalar = 1;
6415 inst.operands[i].present = 1;
6416 inst.operands[i].vectype = optype;
6418 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6420 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6421 inst.operands[i].reg = val;
6422 inst.operands[i].isreg = 1;
6423 inst.operands[i++].present = 1;
6425 if (skip_past_comma (&ptr) == FAIL)
6428 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6431 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6435 inst.operands[i].reg = val;
6436 inst.operands[i].isreg = 1;
6437 inst.operands[i].isvec = 1;
6438 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6439 inst.operands[i].vectype = optype;
6440 inst.operands[i].present = 1;
6442 if (rtype == REG_TYPE_VFS)
6446 if (skip_past_comma (&ptr) == FAIL)
6448 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6451 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6454 inst.operands[i].reg = val;
6455 inst.operands[i].isreg = 1;
6456 inst.operands[i].isvec = 1;
6457 inst.operands[i].issingle = 1;
6458 inst.operands[i].vectype = optype;
6459 inst.operands[i].present = 1;
6462 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6466 inst.operands[i].reg = val;
6467 inst.operands[i].isreg = 1;
6468 inst.operands[i].isvec = 1;
6469 inst.operands[i].issingle = 1;
6470 inst.operands[i].vectype = optype;
6471 inst.operands[i].present = 1;
6476 first_error (_("parse error"));
6480 /* Successfully parsed the operands. Update args. */
6486 first_error (_("expected comma"));
6490 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6494 /* Use this macro when the operand constraints are different
6495 for ARM and THUMB (e.g. ldrd). */
6496 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6497 ((arm_operand) | ((thumb_operand) << 16))
6499 /* Matcher codes for parse_operands. */
6500 enum operand_parse_code
6502 OP_stop, /* end of line */
6504 OP_RR, /* ARM register */
6505 OP_RRnpc, /* ARM register, not r15 */
6506 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6507 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6508 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6509 optional trailing ! */
6510 OP_RRw, /* ARM register, not r15, optional trailing ! */
6511 OP_RCP, /* Coprocessor number */
6512 OP_RCN, /* Coprocessor register */
6513 OP_RF, /* FPA register */
6514 OP_RVS, /* VFP single precision register */
6515 OP_RVD, /* VFP double precision register (0..15) */
6516 OP_RND, /* Neon double precision register (0..31) */
6517 OP_RNQ, /* Neon quad precision register */
6518 OP_RVSD, /* VFP single or double precision register */
6519 OP_RNSD, /* Neon single or double precision register */
6520 OP_RNDQ, /* Neon double or quad precision register */
6521 OP_RNSDQ, /* Neon single, double or quad precision register */
6522 OP_RNSC, /* Neon scalar D[X] */
6523 OP_RVC, /* VFP control register */
6524 OP_RMF, /* Maverick F register */
6525 OP_RMD, /* Maverick D register */
6526 OP_RMFX, /* Maverick FX register */
6527 OP_RMDX, /* Maverick DX register */
6528 OP_RMAX, /* Maverick AX register */
6529 OP_RMDS, /* Maverick DSPSC register */
6530 OP_RIWR, /* iWMMXt wR register */
6531 OP_RIWC, /* iWMMXt wC register */
6532 OP_RIWG, /* iWMMXt wCG register */
6533 OP_RXA, /* XScale accumulator register */
6535 OP_REGLST, /* ARM register list */
6536 OP_VRSLST, /* VFP single-precision register list */
6537 OP_VRDLST, /* VFP double-precision register list */
6538 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6539 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6540 OP_NSTRLST, /* Neon element/structure list */
6542 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6543 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6544 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6545 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6546 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
6547 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6548 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6549 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6550 OP_VMOV, /* Neon VMOV operands. */
6551 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6552 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6553 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6555 OP_I0, /* immediate zero */
6556 OP_I7, /* immediate value 0 .. 7 */
6557 OP_I15, /* 0 .. 15 */
6558 OP_I16, /* 1 .. 16 */
6559 OP_I16z, /* 0 .. 16 */
6560 OP_I31, /* 0 .. 31 */
6561 OP_I31w, /* 0 .. 31, optional trailing ! */
6562 OP_I32, /* 1 .. 32 */
6563 OP_I32z, /* 0 .. 32 */
6564 OP_I63, /* 0 .. 63 */
6565 OP_I63s, /* -64 .. 63 */
6566 OP_I64, /* 1 .. 64 */
6567 OP_I64z, /* 0 .. 64 */
6568 OP_I255, /* 0 .. 255 */
6570 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6571 OP_I7b, /* 0 .. 7 */
6572 OP_I15b, /* 0 .. 15 */
6573 OP_I31b, /* 0 .. 31 */
6575 OP_SH, /* shifter operand */
6576 OP_SHG, /* shifter operand with possible group relocation */
6577 OP_ADDR, /* Memory address expression (any mode) */
6578 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6579 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6580 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6581 OP_EXP, /* arbitrary expression */
6582 OP_EXPi, /* same, with optional immediate prefix */
6583 OP_EXPr, /* same, with optional relocation suffix */
6584 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6585 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
6586 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6588 OP_CPSF, /* CPS flags */
6589 OP_ENDI, /* Endianness specifier */
6590 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6591 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6592 OP_COND, /* conditional code */
6593 OP_TB, /* Table branch. */
6595 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6597 OP_RRnpc_I0, /* ARM register or literal 0 */
6598 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
6599 OP_RR_EXi, /* ARM register or expression with imm prefix */
6600 OP_RF_IF, /* FPA register or immediate */
6601 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6602 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6604 /* Optional operands. */
6605 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6606 OP_oI31b, /* 0 .. 31 */
6607 OP_oI32b, /* 1 .. 32 */
6608 OP_oI32z, /* 0 .. 32 */
6609 OP_oIffffb, /* 0 .. 65535 */
6610 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6612 OP_oRR, /* ARM register */
6613 OP_oRRnpc, /* ARM register, not the PC */
6614 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6615 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6616 OP_oRND, /* Optional Neon double precision register */
6617 OP_oRNQ, /* Optional Neon quad precision register */
6618 OP_oRNDQ, /* Optional Neon double or quad precision register */
6619 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6620 OP_oSHll, /* LSL immediate */
6621 OP_oSHar, /* ASR immediate */
6622 OP_oSHllar, /* LSL or ASR immediate */
6623 OP_oROR, /* ROR 0/8/16/24 */
6624 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6626 /* Some pre-defined mixed (ARM/THUMB) operands. */
6627 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6628 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6629 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6631 OP_FIRST_OPTIONAL = OP_oI7b
6634 /* Generic instruction operand parser. This does no encoding and no
6635 semantic validation; it merely squirrels values away in the inst
6636 structure. Returns SUCCESS or FAIL depending on whether the
6637 specified grammar matched. */
6639 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6641 unsigned const int *upat = pattern;
6642 char *backtrack_pos = 0;
6643 const char *backtrack_error = 0;
6644 int i, val = 0, backtrack_index = 0;
6645 enum arm_reg_type rtype;
6646 parse_operand_result result;
6647 unsigned int op_parse_code;
6649 #define po_char_or_fail(chr) \
6652 if (skip_past_char (&str, chr) == FAIL) \
6657 #define po_reg_or_fail(regtype) \
6660 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6661 & inst.operands[i].vectype); \
6664 first_error (_(reg_expected_msgs[regtype])); \
6667 inst.operands[i].reg = val; \
6668 inst.operands[i].isreg = 1; \
6669 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6670 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6671 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6672 || rtype == REG_TYPE_VFD \
6673 || rtype == REG_TYPE_NQ); \
6677 #define po_reg_or_goto(regtype, label) \
6680 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6681 & inst.operands[i].vectype); \
6685 inst.operands[i].reg = val; \
6686 inst.operands[i].isreg = 1; \
6687 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6688 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6689 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6690 || rtype == REG_TYPE_VFD \
6691 || rtype == REG_TYPE_NQ); \
6695 #define po_imm_or_fail(min, max, popt) \
6698 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6700 inst.operands[i].imm = val; \
6704 #define po_scalar_or_goto(elsz, label) \
6707 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6710 inst.operands[i].reg = val; \
6711 inst.operands[i].isscalar = 1; \
6715 #define po_misc_or_fail(expr) \
6723 #define po_misc_or_fail_no_backtrack(expr) \
6727 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6728 backtrack_pos = 0; \
6729 if (result != PARSE_OPERAND_SUCCESS) \
6734 #define po_barrier_or_imm(str) \
6737 val = parse_barrier (&str); \
6738 if (val == FAIL && ! ISALPHA (*str)) \
6741 /* ISB can only take SY as an option. */ \
6742 || ((inst.instruction & 0xf0) == 0x60 \
6745 inst.error = _("invalid barrier type"); \
6746 backtrack_pos = 0; \
6752 skip_whitespace (str);
6754 for (i = 0; upat[i] != OP_stop; i++)
6756 op_parse_code = upat[i];
6757 if (op_parse_code >= 1<<16)
6758 op_parse_code = thumb ? (op_parse_code >> 16)
6759 : (op_parse_code & ((1<<16)-1));
6761 if (op_parse_code >= OP_FIRST_OPTIONAL)
6763 /* Remember where we are in case we need to backtrack. */
6764 gas_assert (!backtrack_pos);
6765 backtrack_pos = str;
6766 backtrack_error = inst.error;
6767 backtrack_index = i;
6770 if (i > 0 && (i > 1 || inst.operands[0].present))
6771 po_char_or_fail (',');
6773 switch (op_parse_code)
6781 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6782 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6783 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6784 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6785 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6786 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6788 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6790 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6792 /* Also accept generic coprocessor regs for unknown registers. */
6794 po_reg_or_fail (REG_TYPE_CN);
6796 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6797 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6798 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6799 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6800 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6801 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6802 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6803 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6804 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6805 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6807 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6808 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
6810 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6811 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6813 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6815 /* Neon scalar. Using an element size of 8 means that some invalid
6816 scalars are accepted here, so deal with those in later code. */
6817 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6821 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6824 po_imm_or_fail (0, 0, TRUE);
6829 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6834 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6837 if (parse_ifimm_zero (&str))
6838 inst.operands[i].imm = 0;
6842 = _("only floating point zero is allowed as immediate value");
6850 po_scalar_or_goto (8, try_rr);
6853 po_reg_or_fail (REG_TYPE_RN);
6859 po_scalar_or_goto (8, try_nsdq);
6862 po_reg_or_fail (REG_TYPE_NSDQ);
6868 po_scalar_or_goto (8, try_s_scalar);
6871 po_scalar_or_goto (4, try_nsd);
6874 po_reg_or_fail (REG_TYPE_NSD);
6880 po_scalar_or_goto (8, try_ndq);
6883 po_reg_or_fail (REG_TYPE_NDQ);
6889 po_scalar_or_goto (8, try_vfd);
6892 po_reg_or_fail (REG_TYPE_VFD);
6897 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6898 not careful then bad things might happen. */
6899 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6904 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6907 /* There's a possibility of getting a 64-bit immediate here, so
6908 we need special handling. */
6909 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6912 inst.error = _("immediate value is out of range");
6920 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6923 po_imm_or_fail (0, 63, TRUE);
6928 po_char_or_fail ('[');
6929 po_reg_or_fail (REG_TYPE_RN);
6930 po_char_or_fail (']');
6936 po_reg_or_fail (REG_TYPE_RN);
6937 if (skip_past_char (&str, '!') == SUCCESS)
6938 inst.operands[i].writeback = 1;
6942 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6943 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6944 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6945 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6946 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6947 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6948 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6949 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6950 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6951 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6952 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6953 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6955 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6957 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6958 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6960 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6961 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6962 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6963 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6965 /* Immediate variants */
6967 po_char_or_fail ('{');
6968 po_imm_or_fail (0, 255, TRUE);
6969 po_char_or_fail ('}');
6973 /* The expression parser chokes on a trailing !, so we have
6974 to find it first and zap it. */
6977 while (*s && *s != ',')
6982 inst.operands[i].writeback = 1;
6984 po_imm_or_fail (0, 31, TRUE);
6992 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6997 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
7002 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
7004 if (inst.reloc.exp.X_op == O_symbol)
7006 val = parse_reloc (&str);
7009 inst.error = _("unrecognized relocation suffix");
7012 else if (val != BFD_RELOC_UNUSED)
7014 inst.operands[i].imm = val;
7015 inst.operands[i].hasreloc = 1;
7020 /* Operand for MOVW or MOVT. */
7022 po_misc_or_fail (parse_half (&str));
7025 /* Register or expression. */
7026 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7027 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7029 /* Register or immediate. */
7030 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7031 I0: po_imm_or_fail (0, 0, FALSE); break;
7033 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7035 if (!is_immediate_prefix (*str))
7038 val = parse_fpa_immediate (&str);
7041 /* FPA immediates are encoded as registers 8-15.
7042 parse_fpa_immediate has already applied the offset. */
7043 inst.operands[i].reg = val;
7044 inst.operands[i].isreg = 1;
7047 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7048 I32z: po_imm_or_fail (0, 32, FALSE); break;
7050 /* Two kinds of register. */
7053 struct reg_entry *rege = arm_reg_parse_multi (&str);
7055 || (rege->type != REG_TYPE_MMXWR
7056 && rege->type != REG_TYPE_MMXWC
7057 && rege->type != REG_TYPE_MMXWCG))
7059 inst.error = _("iWMMXt data or control register expected");
7062 inst.operands[i].reg = rege->number;
7063 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7069 struct reg_entry *rege = arm_reg_parse_multi (&str);
7071 || (rege->type != REG_TYPE_MMXWC
7072 && rege->type != REG_TYPE_MMXWCG))
7074 inst.error = _("iWMMXt control register expected");
7077 inst.operands[i].reg = rege->number;
7078 inst.operands[i].isreg = 1;
7083 case OP_CPSF: val = parse_cps_flags (&str); break;
7084 case OP_ENDI: val = parse_endian_specifier (&str); break;
7085 case OP_oROR: val = parse_ror (&str); break;
7086 case OP_COND: val = parse_cond (&str); break;
7087 case OP_oBARRIER_I15:
7088 po_barrier_or_imm (str); break;
7090 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7096 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7097 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7099 inst.error = _("Banked registers are not available with this "
7105 val = parse_psr (&str, op_parse_code == OP_wPSR);
7109 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7112 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7114 if (strncasecmp (str, "APSR_", 5) == 0)
7121 case 'c': found = (found & 1) ? 16 : found | 1; break;
7122 case 'n': found = (found & 2) ? 16 : found | 2; break;
7123 case 'z': found = (found & 4) ? 16 : found | 4; break;
7124 case 'v': found = (found & 8) ? 16 : found | 8; break;
7125 default: found = 16;
7129 inst.operands[i].isvec = 1;
7130 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7131 inst.operands[i].reg = REG_PC;
7138 po_misc_or_fail (parse_tb (&str));
7141 /* Register lists. */
7143 val = parse_reg_list (&str);
7146 inst.operands[i].writeback = 1;
7152 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
7156 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
7160 /* Allow Q registers too. */
7161 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7166 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7168 inst.operands[i].issingle = 1;
7173 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7178 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7179 &inst.operands[i].vectype);
7182 /* Addressing modes */
7184 po_misc_or_fail (parse_address (&str, i));
7188 po_misc_or_fail_no_backtrack (
7189 parse_address_group_reloc (&str, i, GROUP_LDR));
7193 po_misc_or_fail_no_backtrack (
7194 parse_address_group_reloc (&str, i, GROUP_LDRS));
7198 po_misc_or_fail_no_backtrack (
7199 parse_address_group_reloc (&str, i, GROUP_LDC));
7203 po_misc_or_fail (parse_shifter_operand (&str, i));
7207 po_misc_or_fail_no_backtrack (
7208 parse_shifter_operand_group_reloc (&str, i));
7212 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7216 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7220 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7224 as_fatal (_("unhandled operand code %d"), op_parse_code);
7227 /* Various value-based sanity checks and shared operations. We
7228 do not signal immediate failures for the register constraints;
7229 this allows a syntax error to take precedence. */
7230 switch (op_parse_code)
7238 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7239 inst.error = BAD_PC;
7244 if (inst.operands[i].isreg)
7246 if (inst.operands[i].reg == REG_PC)
7247 inst.error = BAD_PC;
7248 else if (inst.operands[i].reg == REG_SP
7249 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7250 relaxed since ARMv8-A. */
7251 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7254 inst.error = BAD_SP;
7260 if (inst.operands[i].isreg
7261 && inst.operands[i].reg == REG_PC
7262 && (inst.operands[i].writeback || thumb))
7263 inst.error = BAD_PC;
7272 case OP_oBARRIER_I15:
7281 inst.operands[i].imm = val;
7288 /* If we get here, this operand was successfully parsed. */
7289 inst.operands[i].present = 1;
7293 inst.error = BAD_ARGS;
7298 /* The parse routine should already have set inst.error, but set a
7299 default here just in case. */
7301 inst.error = _("syntax error");
7305 /* Do not backtrack over a trailing optional argument that
7306 absorbed some text. We will only fail again, with the
7307 'garbage following instruction' error message, which is
7308 probably less helpful than the current one. */
7309 if (backtrack_index == i && backtrack_pos != str
7310 && upat[i+1] == OP_stop)
7313 inst.error = _("syntax error");
7317 /* Try again, skipping the optional argument at backtrack_pos. */
7318 str = backtrack_pos;
7319 inst.error = backtrack_error;
7320 inst.operands[backtrack_index].present = 0;
7321 i = backtrack_index;
7325 /* Check that we have parsed all the arguments. */
7326 if (*str != '\0' && !inst.error)
7327 inst.error = _("garbage following instruction");
7329 return inst.error ? FAIL : SUCCESS;
7332 #undef po_char_or_fail
7333 #undef po_reg_or_fail
7334 #undef po_reg_or_goto
7335 #undef po_imm_or_fail
7336 #undef po_scalar_or_fail
7337 #undef po_barrier_or_imm
7339 /* Shorthand macro for instruction encoding functions issuing errors. */
7340 #define constraint(expr, err) \
7351 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7352 instructions are unpredictable if these registers are used. This
7353 is the BadReg predicate in ARM's Thumb-2 documentation.
7355 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7356 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7357 #define reject_bad_reg(reg) \
7359 if (reg == REG_PC) \
7361 inst.error = BAD_PC; \
7364 else if (reg == REG_SP \
7365 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7367 inst.error = BAD_SP; \
7372 /* If REG is R13 (the stack pointer), warn that its use is
7374 #define warn_deprecated_sp(reg) \
7376 if (warn_on_deprecated && reg == REG_SP) \
7377 as_tsktsk (_("use of r13 is deprecated")); \
7380 /* Functions for operand encoding. ARM, then Thumb. */
7382 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7384 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7386 The only binary encoding difference is the Coprocessor number. Coprocessor
7387 9 is used for half-precision calculations or conversions. The format of the
7388 instruction is the same as the equivalent Coprocessor 10 instruction that
7389 exists for Single-Precision operation. */
7392 do_scalar_fp16_v82_encode (void)
7394 if (inst.cond != COND_ALWAYS)
7395 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7396 " the behaviour is UNPREDICTABLE"));
7397 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
7400 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
7401 mark_feature_used (&arm_ext_fp16);
7404 /* If VAL can be encoded in the immediate field of an ARM instruction,
7405 return the encoded form. Otherwise, return FAIL. */
7408 encode_arm_immediate (unsigned int val)
7415 for (i = 2; i < 32; i += 2)
7416 if ((a = rotate_left (val, i)) <= 0xff)
7417 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7422 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7423 return the encoded form. Otherwise, return FAIL. */
7425 encode_thumb32_immediate (unsigned int val)
7432 for (i = 1; i <= 24; i++)
7435 if ((val & ~(0xff << i)) == 0)
7436 return ((val >> i) & 0x7f) | ((32 - i) << 7);
7440 if (val == ((a << 16) | a))
7442 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7446 if (val == ((a << 16) | a))
7447 return 0x200 | (a >> 8);
7451 /* Encode a VFP SP or DP register number into inst.instruction. */
7454 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7456 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7459 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7462 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7465 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7470 first_error (_("D register out of range for selected VFP version"));
7478 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7482 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7486 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7490 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7494 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7498 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7506 /* Encode a <shift> in an ARM-format instruction. The immediate,
7507 if any, is handled by md_apply_fix. */
7509 encode_arm_shift (int i)
7511 /* register-shifted register. */
7512 if (inst.operands[i].immisreg)
7515 for (op_index = 0; op_index <= i; ++op_index)
7517 /* Check the operand only when it's presented. In pre-UAL syntax,
7518 if the destination register is the same as the first operand, two
7519 register form of the instruction can be used. */
7520 if (inst.operands[op_index].present && inst.operands[op_index].isreg
7521 && inst.operands[op_index].reg == REG_PC)
7522 as_warn (UNPRED_REG ("r15"));
7525 if (inst.operands[i].imm == REG_PC)
7526 as_warn (UNPRED_REG ("r15"));
7529 if (inst.operands[i].shift_kind == SHIFT_RRX)
7530 inst.instruction |= SHIFT_ROR << 5;
7533 inst.instruction |= inst.operands[i].shift_kind << 5;
7534 if (inst.operands[i].immisreg)
7536 inst.instruction |= SHIFT_BY_REG;
7537 inst.instruction |= inst.operands[i].imm << 8;
7540 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7545 encode_arm_shifter_operand (int i)
7547 if (inst.operands[i].isreg)
7549 inst.instruction |= inst.operands[i].reg;
7550 encode_arm_shift (i);
7554 inst.instruction |= INST_IMMEDIATE;
7555 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7556 inst.instruction |= inst.operands[i].imm;
7560 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7562 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7565 Generate an error if the operand is not a register. */
7566 constraint (!inst.operands[i].isreg,
7567 _("Instruction does not support =N addresses"));
7569 inst.instruction |= inst.operands[i].reg << 16;
7571 if (inst.operands[i].preind)
7575 inst.error = _("instruction does not accept preindexed addressing");
7578 inst.instruction |= PRE_INDEX;
7579 if (inst.operands[i].writeback)
7580 inst.instruction |= WRITE_BACK;
7583 else if (inst.operands[i].postind)
7585 gas_assert (inst.operands[i].writeback);
7587 inst.instruction |= WRITE_BACK;
7589 else /* unindexed - only for coprocessor */
7591 inst.error = _("instruction does not accept unindexed addressing");
7595 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7596 && (((inst.instruction & 0x000f0000) >> 16)
7597 == ((inst.instruction & 0x0000f000) >> 12)))
7598 as_warn ((inst.instruction & LOAD_BIT)
7599 ? _("destination register same as write-back base")
7600 : _("source register same as write-back base"));
7603 /* inst.operands[i] was set up by parse_address. Encode it into an
7604 ARM-format mode 2 load or store instruction. If is_t is true,
7605 reject forms that cannot be used with a T instruction (i.e. not
7608 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7610 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7612 encode_arm_addr_mode_common (i, is_t);
7614 if (inst.operands[i].immisreg)
7616 constraint ((inst.operands[i].imm == REG_PC
7617 || (is_pc && inst.operands[i].writeback)),
7619 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7620 inst.instruction |= inst.operands[i].imm;
7621 if (!inst.operands[i].negative)
7622 inst.instruction |= INDEX_UP;
7623 if (inst.operands[i].shifted)
7625 if (inst.operands[i].shift_kind == SHIFT_RRX)
7626 inst.instruction |= SHIFT_ROR << 5;
7629 inst.instruction |= inst.operands[i].shift_kind << 5;
7630 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7634 else /* immediate offset in inst.reloc */
7636 if (is_pc && !inst.reloc.pc_rel)
7638 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7640 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7641 cannot use PC in addressing.
7642 PC cannot be used in writeback addressing, either. */
7643 constraint ((is_t || inst.operands[i].writeback),
7646 /* Use of PC in str is deprecated for ARMv7. */
7647 if (warn_on_deprecated
7649 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7650 as_tsktsk (_("use of PC in this instruction is deprecated"));
7653 if (inst.reloc.type == BFD_RELOC_UNUSED)
7655 /* Prefer + for zero encoded value. */
7656 if (!inst.operands[i].negative)
7657 inst.instruction |= INDEX_UP;
7658 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7663 /* inst.operands[i] was set up by parse_address. Encode it into an
7664 ARM-format mode 3 load or store instruction. Reject forms that
7665 cannot be used with such instructions. If is_t is true, reject
7666 forms that cannot be used with a T instruction (i.e. not
7669 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7671 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7673 inst.error = _("instruction does not accept scaled register index");
7677 encode_arm_addr_mode_common (i, is_t);
7679 if (inst.operands[i].immisreg)
7681 constraint ((inst.operands[i].imm == REG_PC
7682 || (is_t && inst.operands[i].reg == REG_PC)),
7684 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7686 inst.instruction |= inst.operands[i].imm;
7687 if (!inst.operands[i].negative)
7688 inst.instruction |= INDEX_UP;
7690 else /* immediate offset in inst.reloc */
7692 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7693 && inst.operands[i].writeback),
7695 inst.instruction |= HWOFFSET_IMM;
7696 if (inst.reloc.type == BFD_RELOC_UNUSED)
7698 /* Prefer + for zero encoded value. */
7699 if (!inst.operands[i].negative)
7700 inst.instruction |= INDEX_UP;
7702 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7707 /* Write immediate bits [7:0] to the following locations:
7709 |28/24|23 19|18 16|15 4|3 0|
7710 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7712 This function is used by VMOV/VMVN/VORR/VBIC. */
7715 neon_write_immbits (unsigned immbits)
7717 inst.instruction |= immbits & 0xf;
7718 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7719 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7722 /* Invert low-order SIZE bits of XHI:XLO. */
7725 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7727 unsigned immlo = xlo ? *xlo : 0;
7728 unsigned immhi = xhi ? *xhi : 0;
7733 immlo = (~immlo) & 0xff;
7737 immlo = (~immlo) & 0xffff;
7741 immhi = (~immhi) & 0xffffffff;
7745 immlo = (~immlo) & 0xffffffff;
7759 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7763 neon_bits_same_in_bytes (unsigned imm)
7765 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7766 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7767 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7768 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7771 /* For immediate of above form, return 0bABCD. */
7774 neon_squash_bits (unsigned imm)
7776 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7777 | ((imm & 0x01000000) >> 21);
7780 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7783 neon_qfloat_bits (unsigned imm)
7785 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7788 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7789 the instruction. *OP is passed as the initial value of the op field, and
7790 may be set to a different value depending on the constant (i.e.
7791 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7792 MVN). If the immediate looks like a repeated pattern then also
7793 try smaller element sizes. */
7796 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7797 unsigned *immbits, int *op, int size,
7798 enum neon_el_type type)
7800 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7802 if (type == NT_float && !float_p)
7805 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
7807 if (size != 32 || *op == 1)
7809 *immbits = neon_qfloat_bits (immlo);
7815 if (neon_bits_same_in_bytes (immhi)
7816 && neon_bits_same_in_bytes (immlo))
7820 *immbits = (neon_squash_bits (immhi) << 4)
7821 | neon_squash_bits (immlo);
7832 if (immlo == (immlo & 0x000000ff))
7837 else if (immlo == (immlo & 0x0000ff00))
7839 *immbits = immlo >> 8;
7842 else if (immlo == (immlo & 0x00ff0000))
7844 *immbits = immlo >> 16;
7847 else if (immlo == (immlo & 0xff000000))
7849 *immbits = immlo >> 24;
7852 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7854 *immbits = (immlo >> 8) & 0xff;
7857 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7859 *immbits = (immlo >> 16) & 0xff;
7863 if ((immlo & 0xffff) != (immlo >> 16))
7870 if (immlo == (immlo & 0x000000ff))
7875 else if (immlo == (immlo & 0x0000ff00))
7877 *immbits = immlo >> 8;
7881 if ((immlo & 0xff) != (immlo >> 8))
7886 if (immlo == (immlo & 0x000000ff))
7888 /* Don't allow MVN with 8-bit immediate. */
7898 #if defined BFD_HOST_64_BIT
7899 /* Returns TRUE if double precision value V may be cast
7900 to single precision without loss of accuracy. */
7903 is_double_a_single (bfd_int64_t v)
7905 int exp = (int)((v >> 52) & 0x7FF);
7906 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7908 return (exp == 0 || exp == 0x7FF
7909 || (exp >= 1023 - 126 && exp <= 1023 + 127))
7910 && (mantissa & 0x1FFFFFFFl) == 0;
7913 /* Returns a double precision value casted to single precision
7914 (ignoring the least significant bits in exponent and mantissa). */
7917 double_to_single (bfd_int64_t v)
7919 int sign = (int) ((v >> 63) & 1l);
7920 int exp = (int) ((v >> 52) & 0x7FF);
7921 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
7927 exp = exp - 1023 + 127;
7936 /* No denormalized numbers. */
7942 return (sign << 31) | (exp << 23) | mantissa;
7944 #endif /* BFD_HOST_64_BIT */
7953 static void do_vfp_nsyn_opcode (const char *);
7955 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7956 Determine whether it can be performed with a move instruction; if
7957 it can, convert inst.instruction to that move instruction and
7958 return TRUE; if it can't, convert inst.instruction to a literal-pool
7959 load and return FALSE. If this is not a valid thing to do in the
7960 current context, set inst.error and return TRUE.
7962 inst.operands[i] describes the destination register. */
7965 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
7968 bfd_boolean thumb_p = (t == CONST_THUMB);
7969 bfd_boolean arm_p = (t == CONST_ARM);
7972 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7976 if ((inst.instruction & tbit) == 0)
7978 inst.error = _("invalid pseudo operation");
7982 if (inst.reloc.exp.X_op != O_constant
7983 && inst.reloc.exp.X_op != O_symbol
7984 && inst.reloc.exp.X_op != O_big)
7986 inst.error = _("constant expression expected");
7990 if (inst.reloc.exp.X_op == O_constant
7991 || inst.reloc.exp.X_op == O_big)
7993 #if defined BFD_HOST_64_BIT
7998 if (inst.reloc.exp.X_op == O_big)
8000 LITTLENUM_TYPE w[X_PRECISION];
8003 if (inst.reloc.exp.X_add_number == -1)
8005 gen_to_words (w, X_PRECISION, E_PRECISION);
8007 /* FIXME: Should we check words w[2..5] ? */
8012 #if defined BFD_HOST_64_BIT
8014 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8015 << LITTLENUM_NUMBER_OF_BITS)
8016 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8017 << LITTLENUM_NUMBER_OF_BITS)
8018 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8019 << LITTLENUM_NUMBER_OF_BITS)
8020 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8022 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8023 | (l[0] & LITTLENUM_MASK);
8027 v = inst.reloc.exp.X_add_number;
8029 if (!inst.operands[i].issingle)
8033 /* LDR should not use lead in a flag-setting instruction being
8034 chosen so we do not check whether movs can be used. */
8036 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8037 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8038 && inst.operands[i].reg != 13
8039 && inst.operands[i].reg != 15)
8041 /* Check if on thumb2 it can be done with a mov.w, mvn or
8042 movw instruction. */
8043 unsigned int newimm;
8044 bfd_boolean isNegated;
8046 newimm = encode_thumb32_immediate (v);
8047 if (newimm != (unsigned int) FAIL)
8051 newimm = encode_thumb32_immediate (~v);
8052 if (newimm != (unsigned int) FAIL)
8056 /* The number can be loaded with a mov.w or mvn
8058 if (newimm != (unsigned int) FAIL
8059 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8061 inst.instruction = (0xf04f0000 /* MOV.W. */
8062 | (inst.operands[i].reg << 8));
8063 /* Change to MOVN. */
8064 inst.instruction |= (isNegated ? 0x200000 : 0);
8065 inst.instruction |= (newimm & 0x800) << 15;
8066 inst.instruction |= (newimm & 0x700) << 4;
8067 inst.instruction |= (newimm & 0x0ff);
8070 /* The number can be loaded with a movw instruction. */
8071 else if ((v & ~0xFFFF) == 0
8072 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8074 int imm = v & 0xFFFF;
8076 inst.instruction = 0xf2400000; /* MOVW. */
8077 inst.instruction |= (inst.operands[i].reg << 8);
8078 inst.instruction |= (imm & 0xf000) << 4;
8079 inst.instruction |= (imm & 0x0800) << 15;
8080 inst.instruction |= (imm & 0x0700) << 4;
8081 inst.instruction |= (imm & 0x00ff);
8088 int value = encode_arm_immediate (v);
8092 /* This can be done with a mov instruction. */
8093 inst.instruction &= LITERAL_MASK;
8094 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8095 inst.instruction |= value & 0xfff;
8099 value = encode_arm_immediate (~ v);
8102 /* This can be done with a mvn instruction. */
8103 inst.instruction &= LITERAL_MASK;
8104 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8105 inst.instruction |= value & 0xfff;
8109 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8112 unsigned immbits = 0;
8113 unsigned immlo = inst.operands[1].imm;
8114 unsigned immhi = inst.operands[1].regisimm
8115 ? inst.operands[1].reg
8116 : inst.reloc.exp.X_unsigned
8118 : ((bfd_int64_t)((int) immlo)) >> 32;
8119 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8120 &op, 64, NT_invtype);
8124 neon_invert_size (&immlo, &immhi, 64);
8126 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8127 &op, 64, NT_invtype);
8132 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8138 /* Fill other bits in vmov encoding for both thumb and arm. */
8140 inst.instruction |= (0x7U << 29) | (0xF << 24);
8142 inst.instruction |= (0xFU << 28) | (0x1 << 25);
8143 neon_write_immbits (immbits);
8151 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8152 if (inst.operands[i].issingle
8153 && is_quarter_float (inst.operands[1].imm)
8154 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8156 inst.operands[1].imm =
8157 neon_qfloat_bits (v);
8158 do_vfp_nsyn_opcode ("fconsts");
8162 /* If our host does not support a 64-bit type then we cannot perform
8163 the following optimization. This mean that there will be a
8164 discrepancy between the output produced by an assembler built for
8165 a 32-bit-only host and the output produced from a 64-bit host, but
8166 this cannot be helped. */
8167 #if defined BFD_HOST_64_BIT
8168 else if (!inst.operands[1].issingle
8169 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8171 if (is_double_a_single (v)
8172 && is_quarter_float (double_to_single (v)))
8174 inst.operands[1].imm =
8175 neon_qfloat_bits (double_to_single (v));
8176 do_vfp_nsyn_opcode ("fconstd");
8184 if (add_to_lit_pool ((!inst.operands[i].isvec
8185 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8188 inst.operands[1].reg = REG_PC;
8189 inst.operands[1].isreg = 1;
8190 inst.operands[1].preind = 1;
8191 inst.reloc.pc_rel = 1;
8192 inst.reloc.type = (thumb_p
8193 ? BFD_RELOC_ARM_THUMB_OFFSET
8195 ? BFD_RELOC_ARM_HWLITERAL
8196 : BFD_RELOC_ARM_LITERAL));
8200 /* inst.operands[i] was set up by parse_address. Encode it into an
8201 ARM-format instruction. Reject all forms which cannot be encoded
8202 into a coprocessor load/store instruction. If wb_ok is false,
8203 reject use of writeback; if unind_ok is false, reject use of
8204 unindexed addressing. If reloc_override is not 0, use it instead
8205 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8206 (in which case it is preserved). */
8209 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8211 if (!inst.operands[i].isreg)
8214 if (! inst.operands[0].isvec)
8216 inst.error = _("invalid co-processor operand");
8219 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8223 inst.instruction |= inst.operands[i].reg << 16;
8225 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8227 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8229 gas_assert (!inst.operands[i].writeback);
8232 inst.error = _("instruction does not support unindexed addressing");
8235 inst.instruction |= inst.operands[i].imm;
8236 inst.instruction |= INDEX_UP;
8240 if (inst.operands[i].preind)
8241 inst.instruction |= PRE_INDEX;
8243 if (inst.operands[i].writeback)
8245 if (inst.operands[i].reg == REG_PC)
8247 inst.error = _("pc may not be used with write-back");
8252 inst.error = _("instruction does not support writeback");
8255 inst.instruction |= WRITE_BACK;
8259 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
8260 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
8261 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
8262 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
8265 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8267 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
8270 /* Prefer + for zero encoded value. */
8271 if (!inst.operands[i].negative)
8272 inst.instruction |= INDEX_UP;
8277 /* Functions for instruction encoding, sorted by sub-architecture.
8278 First some generics; their names are taken from the conventional
8279 bit positions for register arguments in ARM format instructions. */
8289 inst.instruction |= inst.operands[0].reg << 12;
8295 inst.instruction |= inst.operands[0].reg << 16;
8301 inst.instruction |= inst.operands[0].reg << 12;
8302 inst.instruction |= inst.operands[1].reg;
8308 inst.instruction |= inst.operands[0].reg;
8309 inst.instruction |= inst.operands[1].reg << 16;
8315 inst.instruction |= inst.operands[0].reg << 12;
8316 inst.instruction |= inst.operands[1].reg << 16;
8322 inst.instruction |= inst.operands[0].reg << 16;
8323 inst.instruction |= inst.operands[1].reg << 12;
8329 inst.instruction |= inst.operands[0].reg << 8;
8330 inst.instruction |= inst.operands[1].reg << 16;
8334 check_obsolete (const arm_feature_set *feature, const char *msg)
8336 if (ARM_CPU_IS_ANY (cpu_variant))
8338 as_tsktsk ("%s", msg);
8341 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8353 unsigned Rn = inst.operands[2].reg;
8354 /* Enforce restrictions on SWP instruction. */
8355 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8357 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8358 _("Rn must not overlap other operands"));
8360 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8362 if (!check_obsolete (&arm_ext_v8,
8363 _("swp{b} use is obsoleted for ARMv8 and later"))
8364 && warn_on_deprecated
8365 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8366 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8369 inst.instruction |= inst.operands[0].reg << 12;
8370 inst.instruction |= inst.operands[1].reg;
8371 inst.instruction |= Rn << 16;
8377 inst.instruction |= inst.operands[0].reg << 12;
8378 inst.instruction |= inst.operands[1].reg << 16;
8379 inst.instruction |= inst.operands[2].reg;
8385 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8386 constraint (((inst.reloc.exp.X_op != O_constant
8387 && inst.reloc.exp.X_op != O_illegal)
8388 || inst.reloc.exp.X_add_number != 0),
8390 inst.instruction |= inst.operands[0].reg;
8391 inst.instruction |= inst.operands[1].reg << 12;
8392 inst.instruction |= inst.operands[2].reg << 16;
8398 inst.instruction |= inst.operands[0].imm;
8404 inst.instruction |= inst.operands[0].reg << 12;
8405 encode_arm_cp_address (1, TRUE, TRUE, 0);
8408 /* ARM instructions, in alphabetical order by function name (except
8409 that wrapper functions appear immediately after the function they
8412 /* This is a pseudo-op of the form "adr rd, label" to be converted
8413 into a relative address of the form "add rd, pc, #label-.-8". */
8418 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8420 /* Frag hacking will turn this into a sub instruction if the offset turns
8421 out to be negative. */
8422 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8423 inst.reloc.pc_rel = 1;
8424 inst.reloc.exp.X_add_number -= 8;
8426 if (support_interwork
8427 && inst.reloc.exp.X_op == O_symbol
8428 && inst.reloc.exp.X_add_symbol != NULL
8429 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8430 && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8431 inst.reloc.exp.X_add_number |= 1;
8434 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8435 into a relative address of the form:
8436 add rd, pc, #low(label-.-8)"
8437 add rd, rd, #high(label-.-8)" */
8442 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8444 /* Frag hacking will turn this into a sub instruction if the offset turns
8445 out to be negative. */
8446 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
8447 inst.reloc.pc_rel = 1;
8448 inst.size = INSN_SIZE * 2;
8449 inst.reloc.exp.X_add_number -= 8;
8451 if (support_interwork
8452 && inst.reloc.exp.X_op == O_symbol
8453 && inst.reloc.exp.X_add_symbol != NULL
8454 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
8455 && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
8456 inst.reloc.exp.X_add_number |= 1;
8462 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8463 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
8465 if (!inst.operands[1].present)
8466 inst.operands[1].reg = inst.operands[0].reg;
8467 inst.instruction |= inst.operands[0].reg << 12;
8468 inst.instruction |= inst.operands[1].reg << 16;
8469 encode_arm_shifter_operand (2);
8475 if (inst.operands[0].present)
8476 inst.instruction |= inst.operands[0].imm;
8478 inst.instruction |= 0xf;
8484 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8485 constraint (msb > 32, _("bit-field extends past end of register"));
8486 /* The instruction encoding stores the LSB and MSB,
8487 not the LSB and width. */
8488 inst.instruction |= inst.operands[0].reg << 12;
8489 inst.instruction |= inst.operands[1].imm << 7;
8490 inst.instruction |= (msb - 1) << 16;
8498 /* #0 in second position is alternative syntax for bfc, which is
8499 the same instruction but with REG_PC in the Rm field. */
8500 if (!inst.operands[1].isreg)
8501 inst.operands[1].reg = REG_PC;
8503 msb = inst.operands[2].imm + inst.operands[3].imm;
8504 constraint (msb > 32, _("bit-field extends past end of register"));
8505 /* The instruction encoding stores the LSB and MSB,
8506 not the LSB and width. */
8507 inst.instruction |= inst.operands[0].reg << 12;
8508 inst.instruction |= inst.operands[1].reg;
8509 inst.instruction |= inst.operands[2].imm << 7;
8510 inst.instruction |= (msb - 1) << 16;
8516 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8517 _("bit-field extends past end of register"));
8518 inst.instruction |= inst.operands[0].reg << 12;
8519 inst.instruction |= inst.operands[1].reg;
8520 inst.instruction |= inst.operands[2].imm << 7;
8521 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8524 /* ARM V5 breakpoint instruction (argument parse)
8525 BKPT <16 bit unsigned immediate>
8526 Instruction is not conditional.
8527 The bit pattern given in insns[] has the COND_ALWAYS condition,
8528 and it is an error if the caller tried to override that. */
8533 /* Top 12 of 16 bits to bits 19:8. */
8534 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
8536 /* Bottom 4 of 16 bits to bits 3:0. */
8537 inst.instruction |= inst.operands[0].imm & 0xf;
8541 encode_branch (int default_reloc)
8543 if (inst.operands[0].hasreloc)
8545 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8546 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8547 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8548 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8549 ? BFD_RELOC_ARM_PLT32
8550 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
8553 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
8554 inst.reloc.pc_rel = 1;
8561 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8562 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8565 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8572 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8574 if (inst.cond == COND_ALWAYS)
8575 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8577 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8581 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8584 /* ARM V5 branch-link-exchange instruction (argument parse)
8585 BLX <target_addr> ie BLX(1)
8586 BLX{<condition>} <Rm> ie BLX(2)
8587 Unfortunately, there are two different opcodes for this mnemonic.
8588 So, the insns[].value is not used, and the code here zaps values
8589 into inst.instruction.
8590 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8595 if (inst.operands[0].isreg)
8597 /* Arg is a register; the opcode provided by insns[] is correct.
8598 It is not illegal to do "blx pc", just useless. */
8599 if (inst.operands[0].reg == REG_PC)
8600 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8602 inst.instruction |= inst.operands[0].reg;
8606 /* Arg is an address; this instruction cannot be executed
8607 conditionally, and the opcode must be adjusted.
8608 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8609 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8610 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8611 inst.instruction = 0xfa000000;
8612 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
8619 bfd_boolean want_reloc;
8621 if (inst.operands[0].reg == REG_PC)
8622 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8624 inst.instruction |= inst.operands[0].reg;
8625 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8626 it is for ARMv4t or earlier. */
8627 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8628 if (!ARM_FEATURE_ZERO (selected_object_arch)
8629 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
8633 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
8638 inst.reloc.type = BFD_RELOC_ARM_V4BX;
8642 /* ARM v5TEJ. Jump to Jazelle code. */
8647 if (inst.operands[0].reg == REG_PC)
8648 as_tsktsk (_("use of r15 in bxj is not really useful"));
8650 inst.instruction |= inst.operands[0].reg;
8653 /* Co-processor data operation:
8654 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8655 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8659 inst.instruction |= inst.operands[0].reg << 8;
8660 inst.instruction |= inst.operands[1].imm << 20;
8661 inst.instruction |= inst.operands[2].reg << 12;
8662 inst.instruction |= inst.operands[3].reg << 16;
8663 inst.instruction |= inst.operands[4].reg;
8664 inst.instruction |= inst.operands[5].imm << 5;
8670 inst.instruction |= inst.operands[0].reg << 16;
8671 encode_arm_shifter_operand (1);
8674 /* Transfer between coprocessor and ARM registers.
8675 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8680 No special properties. */
8682 struct deprecated_coproc_regs_s
8689 arm_feature_set deprecated;
8690 arm_feature_set obsoleted;
8691 const char *dep_msg;
8692 const char *obs_msg;
8695 #define DEPR_ACCESS_V8 \
8696 N_("This coprocessor register access is deprecated in ARMv8")
8698 /* Table of all deprecated coprocessor registers. */
8699 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8701 {15, 0, 7, 10, 5, /* CP15DMB. */
8702 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8703 DEPR_ACCESS_V8, NULL},
8704 {15, 0, 7, 10, 4, /* CP15DSB. */
8705 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8706 DEPR_ACCESS_V8, NULL},
8707 {15, 0, 7, 5, 4, /* CP15ISB. */
8708 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8709 DEPR_ACCESS_V8, NULL},
8710 {14, 6, 1, 0, 0, /* TEEHBR. */
8711 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8712 DEPR_ACCESS_V8, NULL},
8713 {14, 6, 0, 0, 0, /* TEECR. */
8714 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8715 DEPR_ACCESS_V8, NULL},
8718 #undef DEPR_ACCESS_V8
8720 static const size_t deprecated_coproc_reg_count =
8721 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8729 Rd = inst.operands[2].reg;
8732 if (inst.instruction == 0xee000010
8733 || inst.instruction == 0xfe000010)
8735 reject_bad_reg (Rd);
8736 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8738 constraint (Rd == REG_SP, BAD_SP);
8743 if (inst.instruction == 0xe000010)
8744 constraint (Rd == REG_PC, BAD_PC);
8747 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8749 const struct deprecated_coproc_regs_s *r =
8750 deprecated_coproc_regs + i;
8752 if (inst.operands[0].reg == r->cp
8753 && inst.operands[1].imm == r->opc1
8754 && inst.operands[3].reg == r->crn
8755 && inst.operands[4].reg == r->crm
8756 && inst.operands[5].imm == r->opc2)
8758 if (! ARM_CPU_IS_ANY (cpu_variant)
8759 && warn_on_deprecated
8760 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
8761 as_tsktsk ("%s", r->dep_msg);
8765 inst.instruction |= inst.operands[0].reg << 8;
8766 inst.instruction |= inst.operands[1].imm << 21;
8767 inst.instruction |= Rd << 12;
8768 inst.instruction |= inst.operands[3].reg << 16;
8769 inst.instruction |= inst.operands[4].reg;
8770 inst.instruction |= inst.operands[5].imm << 5;
8773 /* Transfer between coprocessor register and pair of ARM registers.
8774 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8779 Two XScale instructions are special cases of these:
8781 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8782 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8784 Result unpredictable if Rd or Rn is R15. */
8791 Rd = inst.operands[2].reg;
8792 Rn = inst.operands[3].reg;
8796 reject_bad_reg (Rd);
8797 reject_bad_reg (Rn);
8801 constraint (Rd == REG_PC, BAD_PC);
8802 constraint (Rn == REG_PC, BAD_PC);
8805 /* Only check the MRRC{2} variants. */
8806 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
8808 /* If Rd == Rn, error that the operation is
8809 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8810 constraint (Rd == Rn, BAD_OVERLAP);
8813 inst.instruction |= inst.operands[0].reg << 8;
8814 inst.instruction |= inst.operands[1].imm << 4;
8815 inst.instruction |= Rd << 12;
8816 inst.instruction |= Rn << 16;
8817 inst.instruction |= inst.operands[4].reg;
8823 inst.instruction |= inst.operands[0].imm << 6;
8824 if (inst.operands[1].present)
8826 inst.instruction |= CPSI_MMOD;
8827 inst.instruction |= inst.operands[1].imm;
8834 inst.instruction |= inst.operands[0].imm;
8840 unsigned Rd, Rn, Rm;
8842 Rd = inst.operands[0].reg;
8843 Rn = (inst.operands[1].present
8844 ? inst.operands[1].reg : Rd);
8845 Rm = inst.operands[2].reg;
8847 constraint ((Rd == REG_PC), BAD_PC);
8848 constraint ((Rn == REG_PC), BAD_PC);
8849 constraint ((Rm == REG_PC), BAD_PC);
8851 inst.instruction |= Rd << 16;
8852 inst.instruction |= Rn << 0;
8853 inst.instruction |= Rm << 8;
8859 /* There is no IT instruction in ARM mode. We
8860 process it to do the validation as if in
8861 thumb mode, just in case the code gets
8862 assembled for thumb using the unified syntax. */
8867 set_it_insn_type (IT_INSN);
8868 now_it.mask = (inst.instruction & 0xf) | 0x10;
8869 now_it.cc = inst.operands[0].imm;
8873 /* If there is only one register in the register list,
8874 then return its register number. Otherwise return -1. */
8876 only_one_reg_in_list (int range)
8878 int i = ffs (range) - 1;
8879 return (i > 15 || range != (1 << i)) ? -1 : i;
8883 encode_ldmstm(int from_push_pop_mnem)
8885 int base_reg = inst.operands[0].reg;
8886 int range = inst.operands[1].imm;
8889 inst.instruction |= base_reg << 16;
8890 inst.instruction |= range;
8892 if (inst.operands[1].writeback)
8893 inst.instruction |= LDM_TYPE_2_OR_3;
8895 if (inst.operands[0].writeback)
8897 inst.instruction |= WRITE_BACK;
8898 /* Check for unpredictable uses of writeback. */
8899 if (inst.instruction & LOAD_BIT)
8901 /* Not allowed in LDM type 2. */
8902 if ((inst.instruction & LDM_TYPE_2_OR_3)
8903 && ((range & (1 << REG_PC)) == 0))
8904 as_warn (_("writeback of base register is UNPREDICTABLE"));
8905 /* Only allowed if base reg not in list for other types. */
8906 else if (range & (1 << base_reg))
8907 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8911 /* Not allowed for type 2. */
8912 if (inst.instruction & LDM_TYPE_2_OR_3)
8913 as_warn (_("writeback of base register is UNPREDICTABLE"));
8914 /* Only allowed if base reg not in list, or first in list. */
8915 else if ((range & (1 << base_reg))
8916 && (range & ((1 << base_reg) - 1)))
8917 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8921 /* If PUSH/POP has only one register, then use the A2 encoding. */
8922 one_reg = only_one_reg_in_list (range);
8923 if (from_push_pop_mnem && one_reg >= 0)
8925 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8927 if (is_push && one_reg == 13 /* SP */)
8928 /* PR 22483: The A2 encoding cannot be used when
8929 pushing the stack pointer as this is UNPREDICTABLE. */
8932 inst.instruction &= A_COND_MASK;
8933 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8934 inst.instruction |= one_reg << 12;
8941 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8944 /* ARMv5TE load-consecutive (argument parse)
8953 constraint (inst.operands[0].reg % 2 != 0,
8954 _("first transfer register must be even"));
8955 constraint (inst.operands[1].present
8956 && inst.operands[1].reg != inst.operands[0].reg + 1,
8957 _("can only transfer two consecutive registers"));
8958 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8959 constraint (!inst.operands[2].isreg, _("'[' expected"));
8961 if (!inst.operands[1].present)
8962 inst.operands[1].reg = inst.operands[0].reg + 1;
8964 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8965 register and the first register written; we have to diagnose
8966 overlap between the base and the second register written here. */
8968 if (inst.operands[2].reg == inst.operands[1].reg
8969 && (inst.operands[2].writeback || inst.operands[2].postind))
8970 as_warn (_("base register written back, and overlaps "
8971 "second transfer register"));
8973 if (!(inst.instruction & V4_STR_BIT))
8975 /* For an index-register load, the index register must not overlap the
8976 destination (even if not write-back). */
8977 if (inst.operands[2].immisreg
8978 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8979 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8980 as_warn (_("index register overlaps transfer register"));
8982 inst.instruction |= inst.operands[0].reg << 12;
8983 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8989 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8990 || inst.operands[1].postind || inst.operands[1].writeback
8991 || inst.operands[1].immisreg || inst.operands[1].shifted
8992 || inst.operands[1].negative
8993 /* This can arise if the programmer has written
8995 or if they have mistakenly used a register name as the last
8998 It is very difficult to distinguish between these two cases
8999 because "rX" might actually be a label. ie the register
9000 name has been occluded by a symbol of the same name. So we
9001 just generate a general 'bad addressing mode' type error
9002 message and leave it up to the programmer to discover the
9003 true cause and fix their mistake. */
9004 || (inst.operands[1].reg == REG_PC),
9007 constraint (inst.reloc.exp.X_op != O_constant
9008 || inst.reloc.exp.X_add_number != 0,
9009 _("offset must be zero in ARM encoding"));
9011 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9013 inst.instruction |= inst.operands[0].reg << 12;
9014 inst.instruction |= inst.operands[1].reg << 16;
9015 inst.reloc.type = BFD_RELOC_UNUSED;
9021 constraint (inst.operands[0].reg % 2 != 0,
9022 _("even register required"));
9023 constraint (inst.operands[1].present
9024 && inst.operands[1].reg != inst.operands[0].reg + 1,
9025 _("can only load two consecutive registers"));
9026 /* If op 1 were present and equal to PC, this function wouldn't
9027 have been called in the first place. */
9028 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9030 inst.instruction |= inst.operands[0].reg << 12;
9031 inst.instruction |= inst.operands[2].reg << 16;
9034 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9035 which is not a multiple of four is UNPREDICTABLE. */
9037 check_ldr_r15_aligned (void)
9039 constraint (!(inst.operands[1].immisreg)
9040 && (inst.operands[0].reg == REG_PC
9041 && inst.operands[1].reg == REG_PC
9042 && (inst.reloc.exp.X_add_number & 0x3)),
9043 _("ldr to register 15 must be 4-byte aligned"));
9049 inst.instruction |= inst.operands[0].reg << 12;
9050 if (!inst.operands[1].isreg)
9051 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
9053 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
9054 check_ldr_r15_aligned ();
9060 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9062 if (inst.operands[1].preind)
9064 constraint (inst.reloc.exp.X_op != O_constant
9065 || inst.reloc.exp.X_add_number != 0,
9066 _("this instruction requires a post-indexed address"));
9068 inst.operands[1].preind = 0;
9069 inst.operands[1].postind = 1;
9070 inst.operands[1].writeback = 1;
9072 inst.instruction |= inst.operands[0].reg << 12;
9073 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9076 /* Halfword and signed-byte load/store operations. */
9081 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9082 inst.instruction |= inst.operands[0].reg << 12;
9083 if (!inst.operands[1].isreg)
9084 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
9086 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
9092 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9094 if (inst.operands[1].preind)
9096 constraint (inst.reloc.exp.X_op != O_constant
9097 || inst.reloc.exp.X_add_number != 0,
9098 _("this instruction requires a post-indexed address"));
9100 inst.operands[1].preind = 0;
9101 inst.operands[1].postind = 1;
9102 inst.operands[1].writeback = 1;
9104 inst.instruction |= inst.operands[0].reg << 12;
9105 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9108 /* Co-processor register load/store.
9109 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9113 inst.instruction |= inst.operands[0].reg << 8;
9114 inst.instruction |= inst.operands[1].reg << 12;
9115 encode_arm_cp_address (2, TRUE, TRUE, 0);
9121 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9122 if (inst.operands[0].reg == inst.operands[1].reg
9123 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
9124 && !(inst.instruction & 0x00400000))
9125 as_tsktsk (_("Rd and Rm should be different in mla"));
9127 inst.instruction |= inst.operands[0].reg << 16;
9128 inst.instruction |= inst.operands[1].reg;
9129 inst.instruction |= inst.operands[2].reg << 8;
9130 inst.instruction |= inst.operands[3].reg << 12;
9136 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9137 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9139 inst.instruction |= inst.operands[0].reg << 12;
9140 encode_arm_shifter_operand (1);
9143 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9150 top = (inst.instruction & 0x00400000) != 0;
9151 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
9152 _(":lower16: not allowed in this instruction"));
9153 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
9154 _(":upper16: not allowed in this instruction"));
9155 inst.instruction |= inst.operands[0].reg << 12;
9156 if (inst.reloc.type == BFD_RELOC_UNUSED)
9158 imm = inst.reloc.exp.X_add_number;
9159 /* The value is in two pieces: 0:11, 16:19. */
9160 inst.instruction |= (imm & 0x00000fff);
9161 inst.instruction |= (imm & 0x0000f000) << 4;
9166 do_vfp_nsyn_mrs (void)
9168 if (inst.operands[0].isvec)
9170 if (inst.operands[1].reg != 1)
9171 first_error (_("operand 1 must be FPSCR"));
9172 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9173 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9174 do_vfp_nsyn_opcode ("fmstat");
9176 else if (inst.operands[1].isvec)
9177 do_vfp_nsyn_opcode ("fmrx");
9185 do_vfp_nsyn_msr (void)
9187 if (inst.operands[0].isvec)
9188 do_vfp_nsyn_opcode ("fmxr");
9198 unsigned Rt = inst.operands[0].reg;
9200 if (thumb_mode && Rt == REG_SP)
9202 inst.error = BAD_SP;
9206 /* MVFR2 is only valid at ARMv8-A. */
9207 if (inst.operands[1].reg == 5)
9208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9211 /* APSR_ sets isvec. All other refs to PC are illegal. */
9212 if (!inst.operands[0].isvec && Rt == REG_PC)
9214 inst.error = BAD_PC;
9218 /* If we get through parsing the register name, we just insert the number
9219 generated into the instruction without further validation. */
9220 inst.instruction |= (inst.operands[1].reg << 16);
9221 inst.instruction |= (Rt << 12);
9227 unsigned Rt = inst.operands[1].reg;
9230 reject_bad_reg (Rt);
9231 else if (Rt == REG_PC)
9233 inst.error = BAD_PC;
9237 /* MVFR2 is only valid for ARMv8-A. */
9238 if (inst.operands[0].reg == 5)
9239 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9242 /* If we get through parsing the register name, we just insert the number
9243 generated into the instruction without further validation. */
9244 inst.instruction |= (inst.operands[0].reg << 16);
9245 inst.instruction |= (Rt << 12);
9253 if (do_vfp_nsyn_mrs () == SUCCESS)
9256 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9257 inst.instruction |= inst.operands[0].reg << 12;
9259 if (inst.operands[1].isreg)
9261 br = inst.operands[1].reg;
9262 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
9263 as_bad (_("bad register for mrs"));
9267 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9268 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9270 _("'APSR', 'CPSR' or 'SPSR' expected"));
9271 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9274 inst.instruction |= br;
9277 /* Two possible forms:
9278 "{C|S}PSR_<field>, Rm",
9279 "{C|S}PSR_f, #expression". */
9284 if (do_vfp_nsyn_msr () == SUCCESS)
9287 inst.instruction |= inst.operands[0].imm;
9288 if (inst.operands[1].isreg)
9289 inst.instruction |= inst.operands[1].reg;
9292 inst.instruction |= INST_IMMEDIATE;
9293 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
9294 inst.reloc.pc_rel = 0;
9301 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9303 if (!inst.operands[2].present)
9304 inst.operands[2].reg = inst.operands[0].reg;
9305 inst.instruction |= inst.operands[0].reg << 16;
9306 inst.instruction |= inst.operands[1].reg;
9307 inst.instruction |= inst.operands[2].reg << 8;
9309 if (inst.operands[0].reg == inst.operands[1].reg
9310 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9311 as_tsktsk (_("Rd and Rm should be different in mul"));
9314 /* Long Multiply Parser
9315 UMULL RdLo, RdHi, Rm, Rs
9316 SMULL RdLo, RdHi, Rm, Rs
9317 UMLAL RdLo, RdHi, Rm, Rs
9318 SMLAL RdLo, RdHi, Rm, Rs. */
9323 inst.instruction |= inst.operands[0].reg << 12;
9324 inst.instruction |= inst.operands[1].reg << 16;
9325 inst.instruction |= inst.operands[2].reg;
9326 inst.instruction |= inst.operands[3].reg << 8;
9328 /* rdhi and rdlo must be different. */
9329 if (inst.operands[0].reg == inst.operands[1].reg)
9330 as_tsktsk (_("rdhi and rdlo must be different"));
9332 /* rdhi, rdlo and rm must all be different before armv6. */
9333 if ((inst.operands[0].reg == inst.operands[2].reg
9334 || inst.operands[1].reg == inst.operands[2].reg)
9335 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9336 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9342 if (inst.operands[0].present
9343 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9345 /* Architectural NOP hints are CPSR sets with no bits selected. */
9346 inst.instruction &= 0xf0000000;
9347 inst.instruction |= 0x0320f000;
9348 if (inst.operands[0].present)
9349 inst.instruction |= inst.operands[0].imm;
9353 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9354 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9355 Condition defaults to COND_ALWAYS.
9356 Error if Rd, Rn or Rm are R15. */
9361 inst.instruction |= inst.operands[0].reg << 12;
9362 inst.instruction |= inst.operands[1].reg << 16;
9363 inst.instruction |= inst.operands[2].reg;
9364 if (inst.operands[3].present)
9365 encode_arm_shift (3);
9368 /* ARM V6 PKHTB (Argument Parse). */
9373 if (!inst.operands[3].present)
9375 /* If the shift specifier is omitted, turn the instruction
9376 into pkhbt rd, rm, rn. */
9377 inst.instruction &= 0xfff00010;
9378 inst.instruction |= inst.operands[0].reg << 12;
9379 inst.instruction |= inst.operands[1].reg;
9380 inst.instruction |= inst.operands[2].reg << 16;
9384 inst.instruction |= inst.operands[0].reg << 12;
9385 inst.instruction |= inst.operands[1].reg << 16;
9386 inst.instruction |= inst.operands[2].reg;
9387 encode_arm_shift (3);
9391 /* ARMv5TE: Preload-Cache
9392 MP Extensions: Preload for write
9396 Syntactically, like LDR with B=1, W=0, L=1. */
9401 constraint (!inst.operands[0].isreg,
9402 _("'[' expected after PLD mnemonic"));
9403 constraint (inst.operands[0].postind,
9404 _("post-indexed expression used in preload instruction"));
9405 constraint (inst.operands[0].writeback,
9406 _("writeback used in preload instruction"));
9407 constraint (!inst.operands[0].preind,
9408 _("unindexed addressing used in preload instruction"));
9409 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9412 /* ARMv7: PLI <addr_mode> */
9416 constraint (!inst.operands[0].isreg,
9417 _("'[' expected after PLI mnemonic"));
9418 constraint (inst.operands[0].postind,
9419 _("post-indexed expression used in preload instruction"));
9420 constraint (inst.operands[0].writeback,
9421 _("writeback used in preload instruction"));
9422 constraint (!inst.operands[0].preind,
9423 _("unindexed addressing used in preload instruction"));
9424 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9425 inst.instruction &= ~PRE_INDEX;
9431 constraint (inst.operands[0].writeback,
9432 _("push/pop do not support {reglist}^"));
9433 inst.operands[1] = inst.operands[0];
9434 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9435 inst.operands[0].isreg = 1;
9436 inst.operands[0].writeback = 1;
9437 inst.operands[0].reg = REG_SP;
9438 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
9441 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9442 word at the specified address and the following word
9444 Unconditionally executed.
9445 Error if Rn is R15. */
9450 inst.instruction |= inst.operands[0].reg << 16;
9451 if (inst.operands[0].writeback)
9452 inst.instruction |= WRITE_BACK;
9455 /* ARM V6 ssat (argument parse). */
9460 inst.instruction |= inst.operands[0].reg << 12;
9461 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9462 inst.instruction |= inst.operands[2].reg;
9464 if (inst.operands[3].present)
9465 encode_arm_shift (3);
9468 /* ARM V6 usat (argument parse). */
9473 inst.instruction |= inst.operands[0].reg << 12;
9474 inst.instruction |= inst.operands[1].imm << 16;
9475 inst.instruction |= inst.operands[2].reg;
9477 if (inst.operands[3].present)
9478 encode_arm_shift (3);
9481 /* ARM V6 ssat16 (argument parse). */
9486 inst.instruction |= inst.operands[0].reg << 12;
9487 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9488 inst.instruction |= inst.operands[2].reg;
9494 inst.instruction |= inst.operands[0].reg << 12;
9495 inst.instruction |= inst.operands[1].imm << 16;
9496 inst.instruction |= inst.operands[2].reg;
9499 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9500 preserving the other bits.
9502 setend <endian_specifier>, where <endian_specifier> is either
9508 if (warn_on_deprecated
9509 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9510 as_tsktsk (_("setend use is deprecated for ARMv8"));
9512 if (inst.operands[0].imm)
9513 inst.instruction |= 0x200;
9519 unsigned int Rm = (inst.operands[1].present
9520 ? inst.operands[1].reg
9521 : inst.operands[0].reg);
9523 inst.instruction |= inst.operands[0].reg << 12;
9524 inst.instruction |= Rm;
9525 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
9527 inst.instruction |= inst.operands[2].reg << 8;
9528 inst.instruction |= SHIFT_BY_REG;
9529 /* PR 12854: Error on extraneous shifts. */
9530 constraint (inst.operands[2].shifted,
9531 _("extraneous shift as part of operand to shift insn"));
9534 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
9540 inst.reloc.type = BFD_RELOC_ARM_SMC;
9541 inst.reloc.pc_rel = 0;
9547 inst.reloc.type = BFD_RELOC_ARM_HVC;
9548 inst.reloc.pc_rel = 0;
9554 inst.reloc.type = BFD_RELOC_ARM_SWI;
9555 inst.reloc.pc_rel = 0;
9561 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9562 _("selected processor does not support SETPAN instruction"));
9564 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
9570 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9571 _("selected processor does not support SETPAN instruction"));
9573 inst.instruction |= (inst.operands[0].imm << 3);
9576 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9577 SMLAxy{cond} Rd,Rm,Rs,Rn
9578 SMLAWy{cond} Rd,Rm,Rs,Rn
9579 Error if any register is R15. */
9584 inst.instruction |= inst.operands[0].reg << 16;
9585 inst.instruction |= inst.operands[1].reg;
9586 inst.instruction |= inst.operands[2].reg << 8;
9587 inst.instruction |= inst.operands[3].reg << 12;
9590 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9591 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9592 Error if any register is R15.
9593 Warning if Rdlo == Rdhi. */
9598 inst.instruction |= inst.operands[0].reg << 12;
9599 inst.instruction |= inst.operands[1].reg << 16;
9600 inst.instruction |= inst.operands[2].reg;
9601 inst.instruction |= inst.operands[3].reg << 8;
9603 if (inst.operands[0].reg == inst.operands[1].reg)
9604 as_tsktsk (_("rdhi and rdlo must be different"));
9607 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9608 SMULxy{cond} Rd,Rm,Rs
9609 Error if any register is R15. */
9614 inst.instruction |= inst.operands[0].reg << 16;
9615 inst.instruction |= inst.operands[1].reg;
9616 inst.instruction |= inst.operands[2].reg << 8;
9619 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9620 the same for both ARM and Thumb-2. */
9627 if (inst.operands[0].present)
9629 reg = inst.operands[0].reg;
9630 constraint (reg != REG_SP, _("SRS base register must be r13"));
9635 inst.instruction |= reg << 16;
9636 inst.instruction |= inst.operands[1].imm;
9637 if (inst.operands[0].writeback || inst.operands[1].writeback)
9638 inst.instruction |= WRITE_BACK;
9641 /* ARM V6 strex (argument parse). */
9646 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9647 || inst.operands[2].postind || inst.operands[2].writeback
9648 || inst.operands[2].immisreg || inst.operands[2].shifted
9649 || inst.operands[2].negative
9650 /* See comment in do_ldrex(). */
9651 || (inst.operands[2].reg == REG_PC),
9654 constraint (inst.operands[0].reg == inst.operands[1].reg
9655 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9657 constraint (inst.reloc.exp.X_op != O_constant
9658 || inst.reloc.exp.X_add_number != 0,
9659 _("offset must be zero in ARM encoding"));
9661 inst.instruction |= inst.operands[0].reg << 12;
9662 inst.instruction |= inst.operands[1].reg;
9663 inst.instruction |= inst.operands[2].reg << 16;
9664 inst.reloc.type = BFD_RELOC_UNUSED;
9670 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9671 || inst.operands[2].postind || inst.operands[2].writeback
9672 || inst.operands[2].immisreg || inst.operands[2].shifted
9673 || inst.operands[2].negative,
9676 constraint (inst.operands[0].reg == inst.operands[1].reg
9677 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9685 constraint (inst.operands[1].reg % 2 != 0,
9686 _("even register required"));
9687 constraint (inst.operands[2].present
9688 && inst.operands[2].reg != inst.operands[1].reg + 1,
9689 _("can only store two consecutive registers"));
9690 /* If op 2 were present and equal to PC, this function wouldn't
9691 have been called in the first place. */
9692 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
9694 constraint (inst.operands[0].reg == inst.operands[1].reg
9695 || inst.operands[0].reg == inst.operands[1].reg + 1
9696 || inst.operands[0].reg == inst.operands[3].reg,
9699 inst.instruction |= inst.operands[0].reg << 12;
9700 inst.instruction |= inst.operands[1].reg;
9701 inst.instruction |= inst.operands[3].reg << 16;
9708 constraint (inst.operands[0].reg == inst.operands[1].reg
9709 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9717 constraint (inst.operands[0].reg == inst.operands[1].reg
9718 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9723 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9724 extends it to 32-bits, and adds the result to a value in another
9725 register. You can specify a rotation by 0, 8, 16, or 24 bits
9726 before extracting the 16-bit value.
9727 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9728 Condition defaults to COND_ALWAYS.
9729 Error if any register uses R15. */
9734 inst.instruction |= inst.operands[0].reg << 12;
9735 inst.instruction |= inst.operands[1].reg << 16;
9736 inst.instruction |= inst.operands[2].reg;
9737 inst.instruction |= inst.operands[3].imm << 10;
9742 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9743 Condition defaults to COND_ALWAYS.
9744 Error if any register uses R15. */
9749 inst.instruction |= inst.operands[0].reg << 12;
9750 inst.instruction |= inst.operands[1].reg;
9751 inst.instruction |= inst.operands[2].imm << 10;
9754 /* VFP instructions. In a logical order: SP variant first, monad
9755 before dyad, arithmetic then move then load/store. */
9758 do_vfp_sp_monadic (void)
9760 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9761 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9765 do_vfp_sp_dyadic (void)
9767 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9768 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9769 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9773 do_vfp_sp_compare_z (void)
9775 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9779 do_vfp_dp_sp_cvt (void)
9781 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9782 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9786 do_vfp_sp_dp_cvt (void)
9788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9789 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9793 do_vfp_reg_from_sp (void)
9795 inst.instruction |= inst.operands[0].reg << 12;
9796 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9800 do_vfp_reg2_from_sp2 (void)
9802 constraint (inst.operands[2].imm != 2,
9803 _("only two consecutive VFP SP registers allowed here"));
9804 inst.instruction |= inst.operands[0].reg << 12;
9805 inst.instruction |= inst.operands[1].reg << 16;
9806 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9810 do_vfp_sp_from_reg (void)
9812 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
9813 inst.instruction |= inst.operands[1].reg << 12;
9817 do_vfp_sp2_from_reg2 (void)
9819 constraint (inst.operands[0].imm != 2,
9820 _("only two consecutive VFP SP registers allowed here"));
9821 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
9822 inst.instruction |= inst.operands[1].reg << 12;
9823 inst.instruction |= inst.operands[2].reg << 16;
9827 do_vfp_sp_ldst (void)
9829 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9830 encode_arm_cp_address (1, FALSE, TRUE, 0);
9834 do_vfp_dp_ldst (void)
9836 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9837 encode_arm_cp_address (1, FALSE, TRUE, 0);
9842 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
9844 if (inst.operands[0].writeback)
9845 inst.instruction |= WRITE_BACK;
9847 constraint (ldstm_type != VFP_LDSTMIA,
9848 _("this addressing mode requires base-register writeback"));
9849 inst.instruction |= inst.operands[0].reg << 16;
9850 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
9851 inst.instruction |= inst.operands[1].imm;
9855 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
9859 if (inst.operands[0].writeback)
9860 inst.instruction |= WRITE_BACK;
9862 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9863 _("this addressing mode requires base-register writeback"));
9865 inst.instruction |= inst.operands[0].reg << 16;
9866 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9868 count = inst.operands[1].imm << 1;
9869 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9872 inst.instruction |= count;
9876 do_vfp_sp_ldstmia (void)
9878 vfp_sp_ldstm (VFP_LDSTMIA);
9882 do_vfp_sp_ldstmdb (void)
9884 vfp_sp_ldstm (VFP_LDSTMDB);
9888 do_vfp_dp_ldstmia (void)
9890 vfp_dp_ldstm (VFP_LDSTMIA);
9894 do_vfp_dp_ldstmdb (void)
9896 vfp_dp_ldstm (VFP_LDSTMDB);
9900 do_vfp_xp_ldstmia (void)
9902 vfp_dp_ldstm (VFP_LDSTMIAX);
9906 do_vfp_xp_ldstmdb (void)
9908 vfp_dp_ldstm (VFP_LDSTMDBX);
9912 do_vfp_dp_rd_rm (void)
9914 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9915 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9919 do_vfp_dp_rn_rd (void)
9921 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9922 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9926 do_vfp_dp_rd_rn (void)
9928 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9929 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9933 do_vfp_dp_rd_rn_rm (void)
9935 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9936 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9937 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9943 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9947 do_vfp_dp_rm_rd_rn (void)
9949 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9950 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9951 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9954 /* VFPv3 instructions. */
9956 do_vfp_sp_const (void)
9958 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9959 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9960 inst.instruction |= (inst.operands[1].imm & 0x0f);
9964 do_vfp_dp_const (void)
9966 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9967 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9968 inst.instruction |= (inst.operands[1].imm & 0x0f);
9972 vfp_conv (int srcsize)
9974 int immbits = srcsize - inst.operands[1].imm;
9976 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9978 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9979 i.e. immbits must be in range 0 - 16. */
9980 inst.error = _("immediate value out of range, expected range [0, 16]");
9983 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9985 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9986 i.e. immbits must be in range 0 - 31. */
9987 inst.error = _("immediate value out of range, expected range [1, 32]");
9991 inst.instruction |= (immbits & 1) << 5;
9992 inst.instruction |= (immbits >> 1);
9996 do_vfp_sp_conv_16 (void)
9998 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10003 do_vfp_dp_conv_16 (void)
10005 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10010 do_vfp_sp_conv_32 (void)
10012 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10017 do_vfp_dp_conv_32 (void)
10019 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10023 /* FPA instructions. Also in a logical order. */
10028 inst.instruction |= inst.operands[0].reg << 16;
10029 inst.instruction |= inst.operands[1].reg;
10033 do_fpa_ldmstm (void)
10035 inst.instruction |= inst.operands[0].reg << 12;
10036 switch (inst.operands[1].imm)
10038 case 1: inst.instruction |= CP_T_X; break;
10039 case 2: inst.instruction |= CP_T_Y; break;
10040 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10045 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10047 /* The instruction specified "ea" or "fd", so we can only accept
10048 [Rn]{!}. The instruction does not really support stacking or
10049 unstacking, so we have to emulate these by setting appropriate
10050 bits and offsets. */
10051 constraint (inst.reloc.exp.X_op != O_constant
10052 || inst.reloc.exp.X_add_number != 0,
10053 _("this instruction does not support indexing"));
10055 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
10056 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
10058 if (!(inst.instruction & INDEX_UP))
10059 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
10061 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10063 inst.operands[2].preind = 0;
10064 inst.operands[2].postind = 1;
10068 encode_arm_cp_address (2, TRUE, TRUE, 0);
10071 /* iWMMXt instructions: strictly in alphabetical order. */
10074 do_iwmmxt_tandorc (void)
10076 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10080 do_iwmmxt_textrc (void)
10082 inst.instruction |= inst.operands[0].reg << 12;
10083 inst.instruction |= inst.operands[1].imm;
10087 do_iwmmxt_textrm (void)
10089 inst.instruction |= inst.operands[0].reg << 12;
10090 inst.instruction |= inst.operands[1].reg << 16;
10091 inst.instruction |= inst.operands[2].imm;
10095 do_iwmmxt_tinsr (void)
10097 inst.instruction |= inst.operands[0].reg << 16;
10098 inst.instruction |= inst.operands[1].reg << 12;
10099 inst.instruction |= inst.operands[2].imm;
10103 do_iwmmxt_tmia (void)
10105 inst.instruction |= inst.operands[0].reg << 5;
10106 inst.instruction |= inst.operands[1].reg;
10107 inst.instruction |= inst.operands[2].reg << 12;
10111 do_iwmmxt_waligni (void)
10113 inst.instruction |= inst.operands[0].reg << 12;
10114 inst.instruction |= inst.operands[1].reg << 16;
10115 inst.instruction |= inst.operands[2].reg;
10116 inst.instruction |= inst.operands[3].imm << 20;
10120 do_iwmmxt_wmerge (void)
10122 inst.instruction |= inst.operands[0].reg << 12;
10123 inst.instruction |= inst.operands[1].reg << 16;
10124 inst.instruction |= inst.operands[2].reg;
10125 inst.instruction |= inst.operands[3].imm << 21;
10129 do_iwmmxt_wmov (void)
10131 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10132 inst.instruction |= inst.operands[0].reg << 12;
10133 inst.instruction |= inst.operands[1].reg << 16;
10134 inst.instruction |= inst.operands[1].reg;
10138 do_iwmmxt_wldstbh (void)
10141 inst.instruction |= inst.operands[0].reg << 12;
10143 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10145 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10146 encode_arm_cp_address (1, TRUE, FALSE, reloc);
10150 do_iwmmxt_wldstw (void)
10152 /* RIWR_RIWC clears .isreg for a control register. */
10153 if (!inst.operands[0].isreg)
10155 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10156 inst.instruction |= 0xf0000000;
10159 inst.instruction |= inst.operands[0].reg << 12;
10160 encode_arm_cp_address (1, TRUE, TRUE, 0);
10164 do_iwmmxt_wldstd (void)
10166 inst.instruction |= inst.operands[0].reg << 12;
10167 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10168 && inst.operands[1].immisreg)
10170 inst.instruction &= ~0x1a000ff;
10171 inst.instruction |= (0xfU << 28);
10172 if (inst.operands[1].preind)
10173 inst.instruction |= PRE_INDEX;
10174 if (!inst.operands[1].negative)
10175 inst.instruction |= INDEX_UP;
10176 if (inst.operands[1].writeback)
10177 inst.instruction |= WRITE_BACK;
10178 inst.instruction |= inst.operands[1].reg << 16;
10179 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10180 inst.instruction |= inst.operands[1].imm;
10183 encode_arm_cp_address (1, TRUE, FALSE, 0);
10187 do_iwmmxt_wshufh (void)
10189 inst.instruction |= inst.operands[0].reg << 12;
10190 inst.instruction |= inst.operands[1].reg << 16;
10191 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
10192 inst.instruction |= (inst.operands[2].imm & 0x0f);
10196 do_iwmmxt_wzero (void)
10198 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10199 inst.instruction |= inst.operands[0].reg;
10200 inst.instruction |= inst.operands[0].reg << 12;
10201 inst.instruction |= inst.operands[0].reg << 16;
10205 do_iwmmxt_wrwrwr_or_imm5 (void)
10207 if (inst.operands[2].isreg)
10210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
10211 _("immediate operand requires iWMMXt2"));
10213 if (inst.operands[2].imm == 0)
10215 switch ((inst.instruction >> 20) & 0xf)
10221 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10222 inst.operands[2].imm = 16;
10223 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
10229 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10230 inst.operands[2].imm = 32;
10231 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
10238 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10240 wrn = (inst.instruction >> 16) & 0xf;
10241 inst.instruction &= 0xff0fff0f;
10242 inst.instruction |= wrn;
10243 /* Bail out here; the instruction is now assembled. */
10248 /* Map 32 -> 0, etc. */
10249 inst.operands[2].imm &= 0x1f;
10250 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
10254 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10255 operations first, then control, shift, and load/store. */
10257 /* Insns like "foo X,Y,Z". */
10260 do_mav_triple (void)
10262 inst.instruction |= inst.operands[0].reg << 16;
10263 inst.instruction |= inst.operands[1].reg;
10264 inst.instruction |= inst.operands[2].reg << 12;
10267 /* Insns like "foo W,X,Y,Z".
10268 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10273 inst.instruction |= inst.operands[0].reg << 5;
10274 inst.instruction |= inst.operands[1].reg << 12;
10275 inst.instruction |= inst.operands[2].reg << 16;
10276 inst.instruction |= inst.operands[3].reg;
10279 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10281 do_mav_dspsc (void)
10283 inst.instruction |= inst.operands[1].reg << 12;
10286 /* Maverick shift immediate instructions.
10287 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10288 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10291 do_mav_shift (void)
10293 int imm = inst.operands[2].imm;
10295 inst.instruction |= inst.operands[0].reg << 12;
10296 inst.instruction |= inst.operands[1].reg << 16;
10298 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10299 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10300 Bit 4 should be 0. */
10301 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10303 inst.instruction |= imm;
10306 /* XScale instructions. Also sorted arithmetic before move. */
10308 /* Xscale multiply-accumulate (argument parse)
10311 MIAxycc acc0,Rm,Rs. */
10316 inst.instruction |= inst.operands[1].reg;
10317 inst.instruction |= inst.operands[2].reg << 12;
10320 /* Xscale move-accumulator-register (argument parse)
10322 MARcc acc0,RdLo,RdHi. */
10327 inst.instruction |= inst.operands[1].reg << 12;
10328 inst.instruction |= inst.operands[2].reg << 16;
10331 /* Xscale move-register-accumulator (argument parse)
10333 MRAcc RdLo,RdHi,acc0. */
10338 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10339 inst.instruction |= inst.operands[0].reg << 12;
10340 inst.instruction |= inst.operands[1].reg << 16;
10343 /* Encoding functions relevant only to Thumb. */
10345 /* inst.operands[i] is a shifted-register operand; encode
10346 it into inst.instruction in the format used by Thumb32. */
10349 encode_thumb32_shifted_operand (int i)
10351 unsigned int value = inst.reloc.exp.X_add_number;
10352 unsigned int shift = inst.operands[i].shift_kind;
10354 constraint (inst.operands[i].immisreg,
10355 _("shift by register not allowed in thumb mode"));
10356 inst.instruction |= inst.operands[i].reg;
10357 if (shift == SHIFT_RRX)
10358 inst.instruction |= SHIFT_ROR << 4;
10361 constraint (inst.reloc.exp.X_op != O_constant,
10362 _("expression too complex"));
10364 constraint (value > 32
10365 || (value == 32 && (shift == SHIFT_LSL
10366 || shift == SHIFT_ROR)),
10367 _("shift expression is too large"));
10371 else if (value == 32)
10374 inst.instruction |= shift << 4;
10375 inst.instruction |= (value & 0x1c) << 10;
10376 inst.instruction |= (value & 0x03) << 6;
10381 /* inst.operands[i] was set up by parse_address. Encode it into a
10382 Thumb32 format load or store instruction. Reject forms that cannot
10383 be used with such instructions. If is_t is true, reject forms that
10384 cannot be used with a T instruction; if is_d is true, reject forms
10385 that cannot be used with a D instruction. If it is a store insn,
10386 reject PC in Rn. */
10389 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
10391 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
10393 constraint (!inst.operands[i].isreg,
10394 _("Instruction does not support =N addresses"));
10396 inst.instruction |= inst.operands[i].reg << 16;
10397 if (inst.operands[i].immisreg)
10399 constraint (is_pc, BAD_PC_ADDRESSING);
10400 constraint (is_t || is_d, _("cannot use register index with this instruction"));
10401 constraint (inst.operands[i].negative,
10402 _("Thumb does not support negative register indexing"));
10403 constraint (inst.operands[i].postind,
10404 _("Thumb does not support register post-indexing"));
10405 constraint (inst.operands[i].writeback,
10406 _("Thumb does not support register indexing with writeback"));
10407 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
10408 _("Thumb supports only LSL in shifted register indexing"));
10410 inst.instruction |= inst.operands[i].imm;
10411 if (inst.operands[i].shifted)
10413 constraint (inst.reloc.exp.X_op != O_constant,
10414 _("expression too complex"));
10415 constraint (inst.reloc.exp.X_add_number < 0
10416 || inst.reloc.exp.X_add_number > 3,
10417 _("shift out of range"));
10418 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10420 inst.reloc.type = BFD_RELOC_UNUSED;
10422 else if (inst.operands[i].preind)
10424 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
10425 constraint (is_t && inst.operands[i].writeback,
10426 _("cannot use writeback with this instruction"));
10427 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10428 BAD_PC_ADDRESSING);
10432 inst.instruction |= 0x01000000;
10433 if (inst.operands[i].writeback)
10434 inst.instruction |= 0x00200000;
10438 inst.instruction |= 0x00000c00;
10439 if (inst.operands[i].writeback)
10440 inst.instruction |= 0x00000100;
10442 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10444 else if (inst.operands[i].postind)
10446 gas_assert (inst.operands[i].writeback);
10447 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10448 constraint (is_t, _("cannot use post-indexing with this instruction"));
10451 inst.instruction |= 0x00200000;
10453 inst.instruction |= 0x00000900;
10454 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10456 else /* unindexed - only for coprocessor */
10457 inst.error = _("instruction does not accept unindexed addressing");
10460 /* Table of Thumb instructions which exist in both 16- and 32-bit
10461 encodings (the latter only in post-V6T2 cores). The index is the
10462 value used in the insns table below. When there is more than one
10463 possible 16-bit encoding for the instruction, this table always
10465 Also contains several pseudo-instructions used during relaxation. */
10466 #define T16_32_TAB \
10467 X(_adc, 4140, eb400000), \
10468 X(_adcs, 4140, eb500000), \
10469 X(_add, 1c00, eb000000), \
10470 X(_adds, 1c00, eb100000), \
10471 X(_addi, 0000, f1000000), \
10472 X(_addis, 0000, f1100000), \
10473 X(_add_pc,000f, f20f0000), \
10474 X(_add_sp,000d, f10d0000), \
10475 X(_adr, 000f, f20f0000), \
10476 X(_and, 4000, ea000000), \
10477 X(_ands, 4000, ea100000), \
10478 X(_asr, 1000, fa40f000), \
10479 X(_asrs, 1000, fa50f000), \
10480 X(_b, e000, f000b000), \
10481 X(_bcond, d000, f0008000), \
10482 X(_bic, 4380, ea200000), \
10483 X(_bics, 4380, ea300000), \
10484 X(_cmn, 42c0, eb100f00), \
10485 X(_cmp, 2800, ebb00f00), \
10486 X(_cpsie, b660, f3af8400), \
10487 X(_cpsid, b670, f3af8600), \
10488 X(_cpy, 4600, ea4f0000), \
10489 X(_dec_sp,80dd, f1ad0d00), \
10490 X(_eor, 4040, ea800000), \
10491 X(_eors, 4040, ea900000), \
10492 X(_inc_sp,00dd, f10d0d00), \
10493 X(_ldmia, c800, e8900000), \
10494 X(_ldr, 6800, f8500000), \
10495 X(_ldrb, 7800, f8100000), \
10496 X(_ldrh, 8800, f8300000), \
10497 X(_ldrsb, 5600, f9100000), \
10498 X(_ldrsh, 5e00, f9300000), \
10499 X(_ldr_pc,4800, f85f0000), \
10500 X(_ldr_pc2,4800, f85f0000), \
10501 X(_ldr_sp,9800, f85d0000), \
10502 X(_lsl, 0000, fa00f000), \
10503 X(_lsls, 0000, fa10f000), \
10504 X(_lsr, 0800, fa20f000), \
10505 X(_lsrs, 0800, fa30f000), \
10506 X(_mov, 2000, ea4f0000), \
10507 X(_movs, 2000, ea5f0000), \
10508 X(_mul, 4340, fb00f000), \
10509 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10510 X(_mvn, 43c0, ea6f0000), \
10511 X(_mvns, 43c0, ea7f0000), \
10512 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10513 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10514 X(_orr, 4300, ea400000), \
10515 X(_orrs, 4300, ea500000), \
10516 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10517 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10518 X(_rev, ba00, fa90f080), \
10519 X(_rev16, ba40, fa90f090), \
10520 X(_revsh, bac0, fa90f0b0), \
10521 X(_ror, 41c0, fa60f000), \
10522 X(_rors, 41c0, fa70f000), \
10523 X(_sbc, 4180, eb600000), \
10524 X(_sbcs, 4180, eb700000), \
10525 X(_stmia, c000, e8800000), \
10526 X(_str, 6000, f8400000), \
10527 X(_strb, 7000, f8000000), \
10528 X(_strh, 8000, f8200000), \
10529 X(_str_sp,9000, f84d0000), \
10530 X(_sub, 1e00, eba00000), \
10531 X(_subs, 1e00, ebb00000), \
10532 X(_subi, 8000, f1a00000), \
10533 X(_subis, 8000, f1b00000), \
10534 X(_sxtb, b240, fa4ff080), \
10535 X(_sxth, b200, fa0ff080), \
10536 X(_tst, 4200, ea100f00), \
10537 X(_uxtb, b2c0, fa5ff080), \
10538 X(_uxth, b280, fa1ff080), \
10539 X(_nop, bf00, f3af8000), \
10540 X(_yield, bf10, f3af8001), \
10541 X(_wfe, bf20, f3af8002), \
10542 X(_wfi, bf30, f3af8003), \
10543 X(_sev, bf40, f3af8004), \
10544 X(_sevl, bf50, f3af8005), \
10545 X(_udf, de00, f7f0a000)
10547 /* To catch errors in encoding functions, the codes are all offset by
10548 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10549 as 16-bit instructions. */
10550 #define X(a,b,c) T_MNEM##a
10551 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10554 #define X(a,b,c) 0x##b
10555 static const unsigned short thumb_op16[] = { T16_32_TAB };
10556 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10559 #define X(a,b,c) 0x##c
10560 static const unsigned int thumb_op32[] = { T16_32_TAB };
10561 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10562 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10566 /* Thumb instruction encoders, in alphabetical order. */
10568 /* ADDW or SUBW. */
10571 do_t_add_sub_w (void)
10575 Rd = inst.operands[0].reg;
10576 Rn = inst.operands[1].reg;
10578 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10579 is the SP-{plus,minus}-immediate form of the instruction. */
10581 constraint (Rd == REG_PC, BAD_PC);
10583 reject_bad_reg (Rd);
10585 inst.instruction |= (Rn << 16) | (Rd << 8);
10586 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10589 /* Parse an add or subtract instruction. We get here with inst.instruction
10590 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10593 do_t_add_sub (void)
10597 Rd = inst.operands[0].reg;
10598 Rs = (inst.operands[1].present
10599 ? inst.operands[1].reg /* Rd, Rs, foo */
10600 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10603 set_it_insn_type_last ();
10605 if (unified_syntax)
10608 bfd_boolean narrow;
10611 flags = (inst.instruction == T_MNEM_adds
10612 || inst.instruction == T_MNEM_subs);
10614 narrow = !in_it_block ();
10616 narrow = in_it_block ();
10617 if (!inst.operands[2].isreg)
10621 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10622 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10624 add = (inst.instruction == T_MNEM_add
10625 || inst.instruction == T_MNEM_adds);
10627 if (inst.size_req != 4)
10629 /* Attempt to use a narrow opcode, with relaxation if
10631 if (Rd == REG_SP && Rs == REG_SP && !flags)
10632 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10633 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10634 opcode = T_MNEM_add_sp;
10635 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10636 opcode = T_MNEM_add_pc;
10637 else if (Rd <= 7 && Rs <= 7 && narrow)
10640 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10642 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10646 inst.instruction = THUMB_OP16(opcode);
10647 inst.instruction |= (Rd << 4) | Rs;
10648 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10649 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
10651 if (inst.size_req == 2)
10652 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10654 inst.relax = opcode;
10658 constraint (inst.size_req == 2, BAD_HIREG);
10660 if (inst.size_req == 4
10661 || (inst.size_req != 2 && !opcode))
10663 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10664 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
10665 THUMB1_RELOC_ONLY);
10668 constraint (add, BAD_PC);
10669 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10670 _("only SUBS PC, LR, #const allowed"));
10671 constraint (inst.reloc.exp.X_op != O_constant,
10672 _("expression too complex"));
10673 constraint (inst.reloc.exp.X_add_number < 0
10674 || inst.reloc.exp.X_add_number > 0xff,
10675 _("immediate value out of range"));
10676 inst.instruction = T2_SUBS_PC_LR
10677 | inst.reloc.exp.X_add_number;
10678 inst.reloc.type = BFD_RELOC_UNUSED;
10681 else if (Rs == REG_PC)
10683 /* Always use addw/subw. */
10684 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10685 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10689 inst.instruction = THUMB_OP32 (inst.instruction);
10690 inst.instruction = (inst.instruction & 0xe1ffffff)
10693 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10695 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10697 inst.instruction |= Rd << 8;
10698 inst.instruction |= Rs << 16;
10703 unsigned int value = inst.reloc.exp.X_add_number;
10704 unsigned int shift = inst.operands[2].shift_kind;
10706 Rn = inst.operands[2].reg;
10707 /* See if we can do this with a 16-bit instruction. */
10708 if (!inst.operands[2].shifted && inst.size_req != 4)
10710 if (Rd > 7 || Rs > 7 || Rn > 7)
10715 inst.instruction = ((inst.instruction == T_MNEM_adds
10716 || inst.instruction == T_MNEM_add)
10718 : T_OPCODE_SUB_R3);
10719 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10723 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
10725 /* Thumb-1 cores (except v6-M) require at least one high
10726 register in a narrow non flag setting add. */
10727 if (Rd > 7 || Rn > 7
10728 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10729 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
10736 inst.instruction = T_OPCODE_ADD_HI;
10737 inst.instruction |= (Rd & 8) << 4;
10738 inst.instruction |= (Rd & 7);
10739 inst.instruction |= Rn << 3;
10745 constraint (Rd == REG_PC, BAD_PC);
10746 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10747 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10748 constraint (Rs == REG_PC, BAD_PC);
10749 reject_bad_reg (Rn);
10751 /* If we get here, it can't be done in 16 bits. */
10752 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10753 _("shift must be constant"));
10754 inst.instruction = THUMB_OP32 (inst.instruction);
10755 inst.instruction |= Rd << 8;
10756 inst.instruction |= Rs << 16;
10757 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10758 _("shift value over 3 not allowed in thumb mode"));
10759 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10760 _("only LSL shift allowed in thumb mode"));
10761 encode_thumb32_shifted_operand (2);
10766 constraint (inst.instruction == T_MNEM_adds
10767 || inst.instruction == T_MNEM_subs,
10770 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
10772 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10773 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10776 inst.instruction = (inst.instruction == T_MNEM_add
10777 ? 0x0000 : 0x8000);
10778 inst.instruction |= (Rd << 4) | Rs;
10779 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10783 Rn = inst.operands[2].reg;
10784 constraint (inst.operands[2].shifted, _("unshifted register required"));
10786 /* We now have Rd, Rs, and Rn set to registers. */
10787 if (Rd > 7 || Rs > 7 || Rn > 7)
10789 /* Can't do this for SUB. */
10790 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10791 inst.instruction = T_OPCODE_ADD_HI;
10792 inst.instruction |= (Rd & 8) << 4;
10793 inst.instruction |= (Rd & 7);
10795 inst.instruction |= Rn << 3;
10797 inst.instruction |= Rs << 3;
10799 constraint (1, _("dest must overlap one source register"));
10803 inst.instruction = (inst.instruction == T_MNEM_add
10804 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10805 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10815 Rd = inst.operands[0].reg;
10816 reject_bad_reg (Rd);
10818 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
10820 /* Defer to section relaxation. */
10821 inst.relax = inst.instruction;
10822 inst.instruction = THUMB_OP16 (inst.instruction);
10823 inst.instruction |= Rd << 4;
10825 else if (unified_syntax && inst.size_req != 2)
10827 /* Generate a 32-bit opcode. */
10828 inst.instruction = THUMB_OP32 (inst.instruction);
10829 inst.instruction |= Rd << 8;
10830 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10831 inst.reloc.pc_rel = 1;
10835 /* Generate a 16-bit opcode. */
10836 inst.instruction = THUMB_OP16 (inst.instruction);
10837 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10838 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10839 inst.reloc.pc_rel = 1;
10840 inst.instruction |= Rd << 4;
10843 if (inst.reloc.exp.X_op == O_symbol
10844 && inst.reloc.exp.X_add_symbol != NULL
10845 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10846 && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10847 inst.reloc.exp.X_add_number += 1;
10850 /* Arithmetic instructions for which there is just one 16-bit
10851 instruction encoding, and it allows only two low registers.
10852 For maximal compatibility with ARM syntax, we allow three register
10853 operands even when Thumb-32 instructions are not available, as long
10854 as the first two are identical. For instance, both "sbc r0,r1" and
10855 "sbc r0,r0,r1" are allowed. */
10861 Rd = inst.operands[0].reg;
10862 Rs = (inst.operands[1].present
10863 ? inst.operands[1].reg /* Rd, Rs, foo */
10864 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10865 Rn = inst.operands[2].reg;
10867 reject_bad_reg (Rd);
10868 reject_bad_reg (Rs);
10869 if (inst.operands[2].isreg)
10870 reject_bad_reg (Rn);
10872 if (unified_syntax)
10874 if (!inst.operands[2].isreg)
10876 /* For an immediate, we always generate a 32-bit opcode;
10877 section relaxation will shrink it later if possible. */
10878 inst.instruction = THUMB_OP32 (inst.instruction);
10879 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10880 inst.instruction |= Rd << 8;
10881 inst.instruction |= Rs << 16;
10882 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10886 bfd_boolean narrow;
10888 /* See if we can do this with a 16-bit instruction. */
10889 if (THUMB_SETS_FLAGS (inst.instruction))
10890 narrow = !in_it_block ();
10892 narrow = in_it_block ();
10894 if (Rd > 7 || Rn > 7 || Rs > 7)
10896 if (inst.operands[2].shifted)
10898 if (inst.size_req == 4)
10904 inst.instruction = THUMB_OP16 (inst.instruction);
10905 inst.instruction |= Rd;
10906 inst.instruction |= Rn << 3;
10910 /* If we get here, it can't be done in 16 bits. */
10911 constraint (inst.operands[2].shifted
10912 && inst.operands[2].immisreg,
10913 _("shift must be constant"));
10914 inst.instruction = THUMB_OP32 (inst.instruction);
10915 inst.instruction |= Rd << 8;
10916 inst.instruction |= Rs << 16;
10917 encode_thumb32_shifted_operand (2);
10922 /* On its face this is a lie - the instruction does set the
10923 flags. However, the only supported mnemonic in this mode
10924 says it doesn't. */
10925 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10927 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10928 _("unshifted register required"));
10929 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10930 constraint (Rd != Rs,
10931 _("dest and source1 must be the same register"));
10933 inst.instruction = THUMB_OP16 (inst.instruction);
10934 inst.instruction |= Rd;
10935 inst.instruction |= Rn << 3;
10939 /* Similarly, but for instructions where the arithmetic operation is
10940 commutative, so we can allow either of them to be different from
10941 the destination operand in a 16-bit instruction. For instance, all
10942 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10949 Rd = inst.operands[0].reg;
10950 Rs = (inst.operands[1].present
10951 ? inst.operands[1].reg /* Rd, Rs, foo */
10952 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10953 Rn = inst.operands[2].reg;
10955 reject_bad_reg (Rd);
10956 reject_bad_reg (Rs);
10957 if (inst.operands[2].isreg)
10958 reject_bad_reg (Rn);
10960 if (unified_syntax)
10962 if (!inst.operands[2].isreg)
10964 /* For an immediate, we always generate a 32-bit opcode;
10965 section relaxation will shrink it later if possible. */
10966 inst.instruction = THUMB_OP32 (inst.instruction);
10967 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10968 inst.instruction |= Rd << 8;
10969 inst.instruction |= Rs << 16;
10970 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10974 bfd_boolean narrow;
10976 /* See if we can do this with a 16-bit instruction. */
10977 if (THUMB_SETS_FLAGS (inst.instruction))
10978 narrow = !in_it_block ();
10980 narrow = in_it_block ();
10982 if (Rd > 7 || Rn > 7 || Rs > 7)
10984 if (inst.operands[2].shifted)
10986 if (inst.size_req == 4)
10993 inst.instruction = THUMB_OP16 (inst.instruction);
10994 inst.instruction |= Rd;
10995 inst.instruction |= Rn << 3;
11000 inst.instruction = THUMB_OP16 (inst.instruction);
11001 inst.instruction |= Rd;
11002 inst.instruction |= Rs << 3;
11007 /* If we get here, it can't be done in 16 bits. */
11008 constraint (inst.operands[2].shifted
11009 && inst.operands[2].immisreg,
11010 _("shift must be constant"));
11011 inst.instruction = THUMB_OP32 (inst.instruction);
11012 inst.instruction |= Rd << 8;
11013 inst.instruction |= Rs << 16;
11014 encode_thumb32_shifted_operand (2);
11019 /* On its face this is a lie - the instruction does set the
11020 flags. However, the only supported mnemonic in this mode
11021 says it doesn't. */
11022 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11024 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11025 _("unshifted register required"));
11026 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11028 inst.instruction = THUMB_OP16 (inst.instruction);
11029 inst.instruction |= Rd;
11032 inst.instruction |= Rn << 3;
11034 inst.instruction |= Rs << 3;
11036 constraint (1, _("dest must overlap one source register"));
11044 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11045 constraint (msb > 32, _("bit-field extends past end of register"));
11046 /* The instruction encoding stores the LSB and MSB,
11047 not the LSB and width. */
11048 Rd = inst.operands[0].reg;
11049 reject_bad_reg (Rd);
11050 inst.instruction |= Rd << 8;
11051 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11052 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11053 inst.instruction |= msb - 1;
11062 Rd = inst.operands[0].reg;
11063 reject_bad_reg (Rd);
11065 /* #0 in second position is alternative syntax for bfc, which is
11066 the same instruction but with REG_PC in the Rm field. */
11067 if (!inst.operands[1].isreg)
11071 Rn = inst.operands[1].reg;
11072 reject_bad_reg (Rn);
11075 msb = inst.operands[2].imm + inst.operands[3].imm;
11076 constraint (msb > 32, _("bit-field extends past end of register"));
11077 /* The instruction encoding stores the LSB and MSB,
11078 not the LSB and width. */
11079 inst.instruction |= Rd << 8;
11080 inst.instruction |= Rn << 16;
11081 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11082 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11083 inst.instruction |= msb - 1;
11091 Rd = inst.operands[0].reg;
11092 Rn = inst.operands[1].reg;
11094 reject_bad_reg (Rd);
11095 reject_bad_reg (Rn);
11097 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11098 _("bit-field extends past end of register"));
11099 inst.instruction |= Rd << 8;
11100 inst.instruction |= Rn << 16;
11101 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11102 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11103 inst.instruction |= inst.operands[3].imm - 1;
11106 /* ARM V5 Thumb BLX (argument parse)
11107 BLX <target_addr> which is BLX(1)
11108 BLX <Rm> which is BLX(2)
11109 Unfortunately, there are two different opcodes for this mnemonic.
11110 So, the insns[].value is not used, and the code here zaps values
11111 into inst.instruction.
11113 ??? How to take advantage of the additional two bits of displacement
11114 available in Thumb32 mode? Need new relocation? */
11119 set_it_insn_type_last ();
11121 if (inst.operands[0].isreg)
11123 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11124 /* We have a register, so this is BLX(2). */
11125 inst.instruction |= inst.operands[0].reg << 3;
11129 /* No register. This must be BLX(1). */
11130 inst.instruction = 0xf000e800;
11131 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
11140 bfd_reloc_code_real_type reloc;
11143 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
11145 if (in_it_block ())
11147 /* Conditional branches inside IT blocks are encoded as unconditional
11149 cond = COND_ALWAYS;
11154 if (cond != COND_ALWAYS)
11155 opcode = T_MNEM_bcond;
11157 opcode = inst.instruction;
11160 && (inst.size_req == 4
11161 || (inst.size_req != 2
11162 && (inst.operands[0].hasreloc
11163 || inst.reloc.exp.X_op == O_constant))))
11165 inst.instruction = THUMB_OP32(opcode);
11166 if (cond == COND_ALWAYS)
11167 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
11170 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
11171 _("selected architecture does not support "
11172 "wide conditional branch instruction"));
11174 gas_assert (cond != 0xF);
11175 inst.instruction |= cond << 22;
11176 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
11181 inst.instruction = THUMB_OP16(opcode);
11182 if (cond == COND_ALWAYS)
11183 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
11186 inst.instruction |= cond << 8;
11187 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
11189 /* Allow section relaxation. */
11190 if (unified_syntax && inst.size_req != 2)
11191 inst.relax = opcode;
11193 inst.reloc.type = reloc;
11194 inst.reloc.pc_rel = 1;
11197 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11198 between the two is the maximum immediate allowed - which is passed in
11201 do_t_bkpt_hlt1 (int range)
11203 constraint (inst.cond != COND_ALWAYS,
11204 _("instruction is always unconditional"));
11205 if (inst.operands[0].present)
11207 constraint (inst.operands[0].imm > range,
11208 _("immediate value out of range"));
11209 inst.instruction |= inst.operands[0].imm;
11212 set_it_insn_type (NEUTRAL_IT_INSN);
11218 do_t_bkpt_hlt1 (63);
11224 do_t_bkpt_hlt1 (255);
11228 do_t_branch23 (void)
11230 set_it_insn_type_last ();
11231 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
11233 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11234 this file. We used to simply ignore the PLT reloc type here --
11235 the branch encoding is now needed to deal with TLSCALL relocs.
11236 So if we see a PLT reloc now, put it back to how it used to be to
11237 keep the preexisting behaviour. */
11238 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
11239 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
11241 #if defined(OBJ_COFF)
11242 /* If the destination of the branch is a defined symbol which does not have
11243 the THUMB_FUNC attribute, then we must be calling a function which has
11244 the (interfacearm) attribute. We look for the Thumb entry point to that
11245 function and change the branch to refer to that function instead. */
11246 if ( inst.reloc.exp.X_op == O_symbol
11247 && inst.reloc.exp.X_add_symbol != NULL
11248 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
11249 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
11250 inst.reloc.exp.X_add_symbol =
11251 find_real_start (inst.reloc.exp.X_add_symbol);
11258 set_it_insn_type_last ();
11259 inst.instruction |= inst.operands[0].reg << 3;
11260 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11261 should cause the alignment to be checked once it is known. This is
11262 because BX PC only works if the instruction is word aligned. */
11270 set_it_insn_type_last ();
11271 Rm = inst.operands[0].reg;
11272 reject_bad_reg (Rm);
11273 inst.instruction |= Rm << 16;
11282 Rd = inst.operands[0].reg;
11283 Rm = inst.operands[1].reg;
11285 reject_bad_reg (Rd);
11286 reject_bad_reg (Rm);
11288 inst.instruction |= Rd << 8;
11289 inst.instruction |= Rm << 16;
11290 inst.instruction |= Rm;
11296 set_it_insn_type (OUTSIDE_IT_INSN);
11302 set_it_insn_type (OUTSIDE_IT_INSN);
11303 inst.instruction |= inst.operands[0].imm;
11309 set_it_insn_type (OUTSIDE_IT_INSN);
11311 && (inst.operands[1].present || inst.size_req == 4)
11312 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11314 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11315 inst.instruction = 0xf3af8000;
11316 inst.instruction |= imod << 9;
11317 inst.instruction |= inst.operands[0].imm << 5;
11318 if (inst.operands[1].present)
11319 inst.instruction |= 0x100 | inst.operands[1].imm;
11323 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11324 && (inst.operands[0].imm & 4),
11325 _("selected processor does not support 'A' form "
11326 "of this instruction"));
11327 constraint (inst.operands[1].present || inst.size_req == 4,
11328 _("Thumb does not support the 2-argument "
11329 "form of this instruction"));
11330 inst.instruction |= inst.operands[0].imm;
11334 /* THUMB CPY instruction (argument parse). */
11339 if (inst.size_req == 4)
11341 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11342 inst.instruction |= inst.operands[0].reg << 8;
11343 inst.instruction |= inst.operands[1].reg;
11347 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11348 inst.instruction |= (inst.operands[0].reg & 0x7);
11349 inst.instruction |= inst.operands[1].reg << 3;
11356 set_it_insn_type (OUTSIDE_IT_INSN);
11357 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11358 inst.instruction |= inst.operands[0].reg;
11359 inst.reloc.pc_rel = 1;
11360 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11366 inst.instruction |= inst.operands[0].imm;
11372 unsigned Rd, Rn, Rm;
11374 Rd = inst.operands[0].reg;
11375 Rn = (inst.operands[1].present
11376 ? inst.operands[1].reg : Rd);
11377 Rm = inst.operands[2].reg;
11379 reject_bad_reg (Rd);
11380 reject_bad_reg (Rn);
11381 reject_bad_reg (Rm);
11383 inst.instruction |= Rd << 8;
11384 inst.instruction |= Rn << 16;
11385 inst.instruction |= Rm;
11391 if (unified_syntax && inst.size_req == 4)
11392 inst.instruction = THUMB_OP32 (inst.instruction);
11394 inst.instruction = THUMB_OP16 (inst.instruction);
11400 unsigned int cond = inst.operands[0].imm;
11402 set_it_insn_type (IT_INSN);
11403 now_it.mask = (inst.instruction & 0xf) | 0x10;
11405 now_it.warn_deprecated = FALSE;
11407 /* If the condition is a negative condition, invert the mask. */
11408 if ((cond & 0x1) == 0x0)
11410 unsigned int mask = inst.instruction & 0x000f;
11412 if ((mask & 0x7) == 0)
11414 /* No conversion needed. */
11415 now_it.block_length = 1;
11417 else if ((mask & 0x3) == 0)
11420 now_it.block_length = 2;
11422 else if ((mask & 0x1) == 0)
11425 now_it.block_length = 3;
11430 now_it.block_length = 4;
11433 inst.instruction &= 0xfff0;
11434 inst.instruction |= mask;
11437 inst.instruction |= cond << 4;
11440 /* Helper function used for both push/pop and ldm/stm. */
11442 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11446 load = (inst.instruction & (1 << 20)) != 0;
11448 if (mask & (1 << 13))
11449 inst.error = _("SP not allowed in register list");
11451 if ((mask & (1 << base)) != 0
11453 inst.error = _("having the base register in the register list when "
11454 "using write back is UNPREDICTABLE");
11458 if (mask & (1 << 15))
11460 if (mask & (1 << 14))
11461 inst.error = _("LR and PC should not both be in register list");
11463 set_it_insn_type_last ();
11468 if (mask & (1 << 15))
11469 inst.error = _("PC not allowed in register list");
11472 if ((mask & (mask - 1)) == 0)
11474 /* Single register transfers implemented as str/ldr. */
11477 if (inst.instruction & (1 << 23))
11478 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11480 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11484 if (inst.instruction & (1 << 23))
11485 inst.instruction = 0x00800000; /* ia -> [base] */
11487 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11490 inst.instruction |= 0xf8400000;
11492 inst.instruction |= 0x00100000;
11494 mask = ffs (mask) - 1;
11497 else if (writeback)
11498 inst.instruction |= WRITE_BACK;
11500 inst.instruction |= mask;
11501 inst.instruction |= base << 16;
11507 /* This really doesn't seem worth it. */
11508 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11509 _("expression too complex"));
11510 constraint (inst.operands[1].writeback,
11511 _("Thumb load/store multiple does not support {reglist}^"));
11513 if (unified_syntax)
11515 bfd_boolean narrow;
11519 /* See if we can use a 16-bit instruction. */
11520 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11521 && inst.size_req != 4
11522 && !(inst.operands[1].imm & ~0xff))
11524 mask = 1 << inst.operands[0].reg;
11526 if (inst.operands[0].reg <= 7)
11528 if (inst.instruction == T_MNEM_stmia
11529 ? inst.operands[0].writeback
11530 : (inst.operands[0].writeback
11531 == !(inst.operands[1].imm & mask)))
11533 if (inst.instruction == T_MNEM_stmia
11534 && (inst.operands[1].imm & mask)
11535 && (inst.operands[1].imm & (mask - 1)))
11536 as_warn (_("value stored for r%d is UNKNOWN"),
11537 inst.operands[0].reg);
11539 inst.instruction = THUMB_OP16 (inst.instruction);
11540 inst.instruction |= inst.operands[0].reg << 8;
11541 inst.instruction |= inst.operands[1].imm;
11544 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11546 /* This means 1 register in reg list one of 3 situations:
11547 1. Instruction is stmia, but without writeback.
11548 2. lmdia without writeback, but with Rn not in
11550 3. ldmia with writeback, but with Rn in reglist.
11551 Case 3 is UNPREDICTABLE behaviour, so we handle
11552 case 1 and 2 which can be converted into a 16-bit
11553 str or ldr. The SP cases are handled below. */
11554 unsigned long opcode;
11555 /* First, record an error for Case 3. */
11556 if (inst.operands[1].imm & mask
11557 && inst.operands[0].writeback)
11559 _("having the base register in the register list when "
11560 "using write back is UNPREDICTABLE");
11562 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
11564 inst.instruction = THUMB_OP16 (opcode);
11565 inst.instruction |= inst.operands[0].reg << 3;
11566 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11570 else if (inst.operands[0] .reg == REG_SP)
11572 if (inst.operands[0].writeback)
11575 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11576 ? T_MNEM_push : T_MNEM_pop);
11577 inst.instruction |= inst.operands[1].imm;
11580 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11583 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11584 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
11585 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
11593 if (inst.instruction < 0xffff)
11594 inst.instruction = THUMB_OP32 (inst.instruction);
11596 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11597 inst.operands[0].writeback);
11602 constraint (inst.operands[0].reg > 7
11603 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
11604 constraint (inst.instruction != T_MNEM_ldmia
11605 && inst.instruction != T_MNEM_stmia,
11606 _("Thumb-2 instruction only valid in unified syntax"));
11607 if (inst.instruction == T_MNEM_stmia)
11609 if (!inst.operands[0].writeback)
11610 as_warn (_("this instruction will write back the base register"));
11611 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11612 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
11613 as_warn (_("value stored for r%d is UNKNOWN"),
11614 inst.operands[0].reg);
11618 if (!inst.operands[0].writeback
11619 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11620 as_warn (_("this instruction will write back the base register"));
11621 else if (inst.operands[0].writeback
11622 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11623 as_warn (_("this instruction will not write back the base register"));
11626 inst.instruction = THUMB_OP16 (inst.instruction);
11627 inst.instruction |= inst.operands[0].reg << 8;
11628 inst.instruction |= inst.operands[1].imm;
11635 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11636 || inst.operands[1].postind || inst.operands[1].writeback
11637 || inst.operands[1].immisreg || inst.operands[1].shifted
11638 || inst.operands[1].negative,
11641 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11643 inst.instruction |= inst.operands[0].reg << 12;
11644 inst.instruction |= inst.operands[1].reg << 16;
11645 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11651 if (!inst.operands[1].present)
11653 constraint (inst.operands[0].reg == REG_LR,
11654 _("r14 not allowed as first register "
11655 "when second register is omitted"));
11656 inst.operands[1].reg = inst.operands[0].reg + 1;
11658 constraint (inst.operands[0].reg == inst.operands[1].reg,
11661 inst.instruction |= inst.operands[0].reg << 12;
11662 inst.instruction |= inst.operands[1].reg << 8;
11663 inst.instruction |= inst.operands[2].reg << 16;
11669 unsigned long opcode;
11672 if (inst.operands[0].isreg
11673 && !inst.operands[0].preind
11674 && inst.operands[0].reg == REG_PC)
11675 set_it_insn_type_last ();
11677 opcode = inst.instruction;
11678 if (unified_syntax)
11680 if (!inst.operands[1].isreg)
11682 if (opcode <= 0xffff)
11683 inst.instruction = THUMB_OP32 (opcode);
11684 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11687 if (inst.operands[1].isreg
11688 && !inst.operands[1].writeback
11689 && !inst.operands[1].shifted && !inst.operands[1].postind
11690 && !inst.operands[1].negative && inst.operands[0].reg <= 7
11691 && opcode <= 0xffff
11692 && inst.size_req != 4)
11694 /* Insn may have a 16-bit form. */
11695 Rn = inst.operands[1].reg;
11696 if (inst.operands[1].immisreg)
11698 inst.instruction = THUMB_OP16 (opcode);
11700 if (Rn <= 7 && inst.operands[1].imm <= 7)
11702 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11703 reject_bad_reg (inst.operands[1].imm);
11705 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11706 && opcode != T_MNEM_ldrsb)
11707 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11708 || (Rn == REG_SP && opcode == T_MNEM_str))
11715 if (inst.reloc.pc_rel)
11716 opcode = T_MNEM_ldr_pc2;
11718 opcode = T_MNEM_ldr_pc;
11722 if (opcode == T_MNEM_ldr)
11723 opcode = T_MNEM_ldr_sp;
11725 opcode = T_MNEM_str_sp;
11727 inst.instruction = inst.operands[0].reg << 8;
11731 inst.instruction = inst.operands[0].reg;
11732 inst.instruction |= inst.operands[1].reg << 3;
11734 inst.instruction |= THUMB_OP16 (opcode);
11735 if (inst.size_req == 2)
11736 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11738 inst.relax = opcode;
11742 /* Definitely a 32-bit variant. */
11744 /* Warning for Erratum 752419. */
11745 if (opcode == T_MNEM_ldr
11746 && inst.operands[0].reg == REG_SP
11747 && inst.operands[1].writeback == 1
11748 && !inst.operands[1].immisreg)
11750 if (no_cpu_selected ()
11751 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
11752 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11753 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
11754 as_warn (_("This instruction may be unpredictable "
11755 "if executed on M-profile cores "
11756 "with interrupts enabled."));
11759 /* Do some validations regarding addressing modes. */
11760 if (inst.operands[1].immisreg)
11761 reject_bad_reg (inst.operands[1].imm);
11763 constraint (inst.operands[1].writeback == 1
11764 && inst.operands[0].reg == inst.operands[1].reg,
11767 inst.instruction = THUMB_OP32 (opcode);
11768 inst.instruction |= inst.operands[0].reg << 12;
11769 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
11770 check_ldr_r15_aligned ();
11774 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11776 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
11778 /* Only [Rn,Rm] is acceptable. */
11779 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11780 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11781 || inst.operands[1].postind || inst.operands[1].shifted
11782 || inst.operands[1].negative,
11783 _("Thumb does not support this addressing mode"));
11784 inst.instruction = THUMB_OP16 (inst.instruction);
11788 inst.instruction = THUMB_OP16 (inst.instruction);
11789 if (!inst.operands[1].isreg)
11790 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11793 constraint (!inst.operands[1].preind
11794 || inst.operands[1].shifted
11795 || inst.operands[1].writeback,
11796 _("Thumb does not support this addressing mode"));
11797 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
11799 constraint (inst.instruction & 0x0600,
11800 _("byte or halfword not valid for base register"));
11801 constraint (inst.operands[1].reg == REG_PC
11802 && !(inst.instruction & THUMB_LOAD_BIT),
11803 _("r15 based store not allowed"));
11804 constraint (inst.operands[1].immisreg,
11805 _("invalid base register for register offset"));
11807 if (inst.operands[1].reg == REG_PC)
11808 inst.instruction = T_OPCODE_LDR_PC;
11809 else if (inst.instruction & THUMB_LOAD_BIT)
11810 inst.instruction = T_OPCODE_LDR_SP;
11812 inst.instruction = T_OPCODE_STR_SP;
11814 inst.instruction |= inst.operands[0].reg << 8;
11815 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11819 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11820 if (!inst.operands[1].immisreg)
11822 /* Immediate offset. */
11823 inst.instruction |= inst.operands[0].reg;
11824 inst.instruction |= inst.operands[1].reg << 3;
11825 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11829 /* Register offset. */
11830 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11831 constraint (inst.operands[1].negative,
11832 _("Thumb does not support this addressing mode"));
11835 switch (inst.instruction)
11837 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11838 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11839 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11840 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11841 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11842 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11843 case 0x5600 /* ldrsb */:
11844 case 0x5e00 /* ldrsh */: break;
11848 inst.instruction |= inst.operands[0].reg;
11849 inst.instruction |= inst.operands[1].reg << 3;
11850 inst.instruction |= inst.operands[1].imm << 6;
11856 if (!inst.operands[1].present)
11858 inst.operands[1].reg = inst.operands[0].reg + 1;
11859 constraint (inst.operands[0].reg == REG_LR,
11860 _("r14 not allowed here"));
11861 constraint (inst.operands[0].reg == REG_R12,
11862 _("r12 not allowed here"));
11865 if (inst.operands[2].writeback
11866 && (inst.operands[0].reg == inst.operands[2].reg
11867 || inst.operands[1].reg == inst.operands[2].reg))
11868 as_warn (_("base register written back, and overlaps "
11869 "one of transfer registers"));
11871 inst.instruction |= inst.operands[0].reg << 12;
11872 inst.instruction |= inst.operands[1].reg << 8;
11873 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
11879 inst.instruction |= inst.operands[0].reg << 12;
11880 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11886 unsigned Rd, Rn, Rm, Ra;
11888 Rd = inst.operands[0].reg;
11889 Rn = inst.operands[1].reg;
11890 Rm = inst.operands[2].reg;
11891 Ra = inst.operands[3].reg;
11893 reject_bad_reg (Rd);
11894 reject_bad_reg (Rn);
11895 reject_bad_reg (Rm);
11896 reject_bad_reg (Ra);
11898 inst.instruction |= Rd << 8;
11899 inst.instruction |= Rn << 16;
11900 inst.instruction |= Rm;
11901 inst.instruction |= Ra << 12;
11907 unsigned RdLo, RdHi, Rn, Rm;
11909 RdLo = inst.operands[0].reg;
11910 RdHi = inst.operands[1].reg;
11911 Rn = inst.operands[2].reg;
11912 Rm = inst.operands[3].reg;
11914 reject_bad_reg (RdLo);
11915 reject_bad_reg (RdHi);
11916 reject_bad_reg (Rn);
11917 reject_bad_reg (Rm);
11919 inst.instruction |= RdLo << 12;
11920 inst.instruction |= RdHi << 8;
11921 inst.instruction |= Rn << 16;
11922 inst.instruction |= Rm;
11926 do_t_mov_cmp (void)
11930 Rn = inst.operands[0].reg;
11931 Rm = inst.operands[1].reg;
11934 set_it_insn_type_last ();
11936 if (unified_syntax)
11938 int r0off = (inst.instruction == T_MNEM_mov
11939 || inst.instruction == T_MNEM_movs) ? 8 : 16;
11940 unsigned long opcode;
11941 bfd_boolean narrow;
11942 bfd_boolean low_regs;
11944 low_regs = (Rn <= 7 && Rm <= 7);
11945 opcode = inst.instruction;
11946 if (in_it_block ())
11947 narrow = opcode != T_MNEM_movs;
11949 narrow = opcode != T_MNEM_movs || low_regs;
11950 if (inst.size_req == 4
11951 || inst.operands[1].shifted)
11954 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11955 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11956 && !inst.operands[1].shifted
11960 inst.instruction = T2_SUBS_PC_LR;
11964 if (opcode == T_MNEM_cmp)
11966 constraint (Rn == REG_PC, BAD_PC);
11969 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11971 warn_deprecated_sp (Rm);
11972 /* R15 was documented as a valid choice for Rm in ARMv6,
11973 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11974 tools reject R15, so we do too. */
11975 constraint (Rm == REG_PC, BAD_PC);
11978 reject_bad_reg (Rm);
11980 else if (opcode == T_MNEM_mov
11981 || opcode == T_MNEM_movs)
11983 if (inst.operands[1].isreg)
11985 if (opcode == T_MNEM_movs)
11987 reject_bad_reg (Rn);
11988 reject_bad_reg (Rm);
11992 /* This is mov.n. */
11993 if ((Rn == REG_SP || Rn == REG_PC)
11994 && (Rm == REG_SP || Rm == REG_PC))
11996 as_tsktsk (_("Use of r%u as a source register is "
11997 "deprecated when r%u is the destination "
11998 "register."), Rm, Rn);
12003 /* This is mov.w. */
12004 constraint (Rn == REG_PC, BAD_PC);
12005 constraint (Rm == REG_PC, BAD_PC);
12006 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12007 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
12011 reject_bad_reg (Rn);
12014 if (!inst.operands[1].isreg)
12016 /* Immediate operand. */
12017 if (!in_it_block () && opcode == T_MNEM_mov)
12019 if (low_regs && narrow)
12021 inst.instruction = THUMB_OP16 (opcode);
12022 inst.instruction |= Rn << 8;
12023 if (inst.reloc.type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12024 || inst.reloc.type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
12026 if (inst.size_req == 2)
12027 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
12029 inst.relax = opcode;
12034 constraint (inst.reloc.type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12035 && inst.reloc.type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
12036 THUMB1_RELOC_ONLY);
12038 inst.instruction = THUMB_OP32 (inst.instruction);
12039 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12040 inst.instruction |= Rn << r0off;
12041 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12044 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12045 && (inst.instruction == T_MNEM_mov
12046 || inst.instruction == T_MNEM_movs))
12048 /* Register shifts are encoded as separate shift instructions. */
12049 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12051 if (in_it_block ())
12056 if (inst.size_req == 4)
12059 if (!low_regs || inst.operands[1].imm > 7)
12065 switch (inst.operands[1].shift_kind)
12068 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12071 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12074 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12077 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12083 inst.instruction = opcode;
12086 inst.instruction |= Rn;
12087 inst.instruction |= inst.operands[1].imm << 3;
12092 inst.instruction |= CONDS_BIT;
12094 inst.instruction |= Rn << 8;
12095 inst.instruction |= Rm << 16;
12096 inst.instruction |= inst.operands[1].imm;
12101 /* Some mov with immediate shift have narrow variants.
12102 Register shifts are handled above. */
12103 if (low_regs && inst.operands[1].shifted
12104 && (inst.instruction == T_MNEM_mov
12105 || inst.instruction == T_MNEM_movs))
12107 if (in_it_block ())
12108 narrow = (inst.instruction == T_MNEM_mov);
12110 narrow = (inst.instruction == T_MNEM_movs);
12115 switch (inst.operands[1].shift_kind)
12117 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12118 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12119 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12120 default: narrow = FALSE; break;
12126 inst.instruction |= Rn;
12127 inst.instruction |= Rm << 3;
12128 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12132 inst.instruction = THUMB_OP32 (inst.instruction);
12133 inst.instruction |= Rn << r0off;
12134 encode_thumb32_shifted_operand (1);
12138 switch (inst.instruction)
12141 /* In v4t or v5t a move of two lowregs produces unpredictable
12142 results. Don't allow this. */
12145 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
12146 "MOV Rd, Rs with two low registers is not "
12147 "permitted on this architecture");
12148 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
12152 inst.instruction = T_OPCODE_MOV_HR;
12153 inst.instruction |= (Rn & 0x8) << 4;
12154 inst.instruction |= (Rn & 0x7);
12155 inst.instruction |= Rm << 3;
12159 /* We know we have low registers at this point.
12160 Generate LSLS Rd, Rs, #0. */
12161 inst.instruction = T_OPCODE_LSL_I;
12162 inst.instruction |= Rn;
12163 inst.instruction |= Rm << 3;
12169 inst.instruction = T_OPCODE_CMP_LR;
12170 inst.instruction |= Rn;
12171 inst.instruction |= Rm << 3;
12175 inst.instruction = T_OPCODE_CMP_HR;
12176 inst.instruction |= (Rn & 0x8) << 4;
12177 inst.instruction |= (Rn & 0x7);
12178 inst.instruction |= Rm << 3;
12185 inst.instruction = THUMB_OP16 (inst.instruction);
12187 /* PR 10443: Do not silently ignore shifted operands. */
12188 constraint (inst.operands[1].shifted,
12189 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12191 if (inst.operands[1].isreg)
12193 if (Rn < 8 && Rm < 8)
12195 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12196 since a MOV instruction produces unpredictable results. */
12197 if (inst.instruction == T_OPCODE_MOV_I8)
12198 inst.instruction = T_OPCODE_ADD_I3;
12200 inst.instruction = T_OPCODE_CMP_LR;
12202 inst.instruction |= Rn;
12203 inst.instruction |= Rm << 3;
12207 if (inst.instruction == T_OPCODE_MOV_I8)
12208 inst.instruction = T_OPCODE_MOV_HR;
12210 inst.instruction = T_OPCODE_CMP_HR;
12216 constraint (Rn > 7,
12217 _("only lo regs allowed with immediate"));
12218 inst.instruction |= Rn << 8;
12219 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
12230 top = (inst.instruction & 0x00800000) != 0;
12231 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
12233 constraint (top, _(":lower16: not allowed in this instruction"));
12234 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
12236 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
12238 constraint (!top, _(":upper16: not allowed in this instruction"));
12239 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
12242 Rd = inst.operands[0].reg;
12243 reject_bad_reg (Rd);
12245 inst.instruction |= Rd << 8;
12246 if (inst.reloc.type == BFD_RELOC_UNUSED)
12248 imm = inst.reloc.exp.X_add_number;
12249 inst.instruction |= (imm & 0xf000) << 4;
12250 inst.instruction |= (imm & 0x0800) << 15;
12251 inst.instruction |= (imm & 0x0700) << 4;
12252 inst.instruction |= (imm & 0x00ff);
12257 do_t_mvn_tst (void)
12261 Rn = inst.operands[0].reg;
12262 Rm = inst.operands[1].reg;
12264 if (inst.instruction == T_MNEM_cmp
12265 || inst.instruction == T_MNEM_cmn)
12266 constraint (Rn == REG_PC, BAD_PC);
12268 reject_bad_reg (Rn);
12269 reject_bad_reg (Rm);
12271 if (unified_syntax)
12273 int r0off = (inst.instruction == T_MNEM_mvn
12274 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
12275 bfd_boolean narrow;
12277 if (inst.size_req == 4
12278 || inst.instruction > 0xffff
12279 || inst.operands[1].shifted
12280 || Rn > 7 || Rm > 7)
12282 else if (inst.instruction == T_MNEM_cmn
12283 || inst.instruction == T_MNEM_tst)
12285 else if (THUMB_SETS_FLAGS (inst.instruction))
12286 narrow = !in_it_block ();
12288 narrow = in_it_block ();
12290 if (!inst.operands[1].isreg)
12292 /* For an immediate, we always generate a 32-bit opcode;
12293 section relaxation will shrink it later if possible. */
12294 if (inst.instruction < 0xffff)
12295 inst.instruction = THUMB_OP32 (inst.instruction);
12296 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12297 inst.instruction |= Rn << r0off;
12298 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12302 /* See if we can do this with a 16-bit instruction. */
12305 inst.instruction = THUMB_OP16 (inst.instruction);
12306 inst.instruction |= Rn;
12307 inst.instruction |= Rm << 3;
12311 constraint (inst.operands[1].shifted
12312 && inst.operands[1].immisreg,
12313 _("shift must be constant"));
12314 if (inst.instruction < 0xffff)
12315 inst.instruction = THUMB_OP32 (inst.instruction);
12316 inst.instruction |= Rn << r0off;
12317 encode_thumb32_shifted_operand (1);
12323 constraint (inst.instruction > 0xffff
12324 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12325 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12326 _("unshifted register required"));
12327 constraint (Rn > 7 || Rm > 7,
12330 inst.instruction = THUMB_OP16 (inst.instruction);
12331 inst.instruction |= Rn;
12332 inst.instruction |= Rm << 3;
12341 if (do_vfp_nsyn_mrs () == SUCCESS)
12344 Rd = inst.operands[0].reg;
12345 reject_bad_reg (Rd);
12346 inst.instruction |= Rd << 8;
12348 if (inst.operands[1].isreg)
12350 unsigned br = inst.operands[1].reg;
12351 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12352 as_bad (_("bad register for mrs"));
12354 inst.instruction |= br & (0xf << 16);
12355 inst.instruction |= (br & 0x300) >> 4;
12356 inst.instruction |= (br & SPSR_BIT) >> 2;
12360 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12362 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12364 /* PR gas/12698: The constraint is only applied for m_profile.
12365 If the user has specified -march=all, we want to ignore it as
12366 we are building for any CPU type, including non-m variants. */
12367 bfd_boolean m_profile =
12368 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12369 constraint ((flags != 0) && m_profile, _("selected processor does "
12370 "not support requested special purpose register"));
12373 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12375 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
12376 _("'APSR', 'CPSR' or 'SPSR' expected"));
12378 inst.instruction |= (flags & SPSR_BIT) >> 2;
12379 inst.instruction |= inst.operands[1].imm & 0xff;
12380 inst.instruction |= 0xf0000;
12390 if (do_vfp_nsyn_msr () == SUCCESS)
12393 constraint (!inst.operands[1].isreg,
12394 _("Thumb encoding does not support an immediate here"));
12396 if (inst.operands[0].isreg)
12397 flags = (int)(inst.operands[0].reg);
12399 flags = inst.operands[0].imm;
12401 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12403 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12405 /* PR gas/12698: The constraint is only applied for m_profile.
12406 If the user has specified -march=all, we want to ignore it as
12407 we are building for any CPU type, including non-m variants. */
12408 bfd_boolean m_profile =
12409 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12410 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12411 && (bits & ~(PSR_s | PSR_f)) != 0)
12412 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12413 && bits != PSR_f)) && m_profile,
12414 _("selected processor does not support requested special "
12415 "purpose register"));
12418 constraint ((flags & 0xff) != 0, _("selected processor does not support "
12419 "requested special purpose register"));
12421 Rn = inst.operands[1].reg;
12422 reject_bad_reg (Rn);
12424 inst.instruction |= (flags & SPSR_BIT) >> 2;
12425 inst.instruction |= (flags & 0xf0000) >> 8;
12426 inst.instruction |= (flags & 0x300) >> 4;
12427 inst.instruction |= (flags & 0xff);
12428 inst.instruction |= Rn << 16;
12434 bfd_boolean narrow;
12435 unsigned Rd, Rn, Rm;
12437 if (!inst.operands[2].present)
12438 inst.operands[2].reg = inst.operands[0].reg;
12440 Rd = inst.operands[0].reg;
12441 Rn = inst.operands[1].reg;
12442 Rm = inst.operands[2].reg;
12444 if (unified_syntax)
12446 if (inst.size_req == 4
12452 else if (inst.instruction == T_MNEM_muls)
12453 narrow = !in_it_block ();
12455 narrow = in_it_block ();
12459 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
12460 constraint (Rn > 7 || Rm > 7,
12467 /* 16-bit MULS/Conditional MUL. */
12468 inst.instruction = THUMB_OP16 (inst.instruction);
12469 inst.instruction |= Rd;
12472 inst.instruction |= Rm << 3;
12474 inst.instruction |= Rn << 3;
12476 constraint (1, _("dest must overlap one source register"));
12480 constraint (inst.instruction != T_MNEM_mul,
12481 _("Thumb-2 MUL must not set flags"));
12483 inst.instruction = THUMB_OP32 (inst.instruction);
12484 inst.instruction |= Rd << 8;
12485 inst.instruction |= Rn << 16;
12486 inst.instruction |= Rm << 0;
12488 reject_bad_reg (Rd);
12489 reject_bad_reg (Rn);
12490 reject_bad_reg (Rm);
12497 unsigned RdLo, RdHi, Rn, Rm;
12499 RdLo = inst.operands[0].reg;
12500 RdHi = inst.operands[1].reg;
12501 Rn = inst.operands[2].reg;
12502 Rm = inst.operands[3].reg;
12504 reject_bad_reg (RdLo);
12505 reject_bad_reg (RdHi);
12506 reject_bad_reg (Rn);
12507 reject_bad_reg (Rm);
12509 inst.instruction |= RdLo << 12;
12510 inst.instruction |= RdHi << 8;
12511 inst.instruction |= Rn << 16;
12512 inst.instruction |= Rm;
12515 as_tsktsk (_("rdhi and rdlo must be different"));
12521 set_it_insn_type (NEUTRAL_IT_INSN);
12523 if (unified_syntax)
12525 if (inst.size_req == 4 || inst.operands[0].imm > 15)
12527 inst.instruction = THUMB_OP32 (inst.instruction);
12528 inst.instruction |= inst.operands[0].imm;
12532 /* PR9722: Check for Thumb2 availability before
12533 generating a thumb2 nop instruction. */
12534 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
12536 inst.instruction = THUMB_OP16 (inst.instruction);
12537 inst.instruction |= inst.operands[0].imm << 4;
12540 inst.instruction = 0x46c0;
12545 constraint (inst.operands[0].present,
12546 _("Thumb does not support NOP with hints"));
12547 inst.instruction = 0x46c0;
12554 if (unified_syntax)
12556 bfd_boolean narrow;
12558 if (THUMB_SETS_FLAGS (inst.instruction))
12559 narrow = !in_it_block ();
12561 narrow = in_it_block ();
12562 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12564 if (inst.size_req == 4)
12569 inst.instruction = THUMB_OP32 (inst.instruction);
12570 inst.instruction |= inst.operands[0].reg << 8;
12571 inst.instruction |= inst.operands[1].reg << 16;
12575 inst.instruction = THUMB_OP16 (inst.instruction);
12576 inst.instruction |= inst.operands[0].reg;
12577 inst.instruction |= inst.operands[1].reg << 3;
12582 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12584 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12586 inst.instruction = THUMB_OP16 (inst.instruction);
12587 inst.instruction |= inst.operands[0].reg;
12588 inst.instruction |= inst.operands[1].reg << 3;
12597 Rd = inst.operands[0].reg;
12598 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12600 reject_bad_reg (Rd);
12601 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12602 reject_bad_reg (Rn);
12604 inst.instruction |= Rd << 8;
12605 inst.instruction |= Rn << 16;
12607 if (!inst.operands[2].isreg)
12609 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12610 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12616 Rm = inst.operands[2].reg;
12617 reject_bad_reg (Rm);
12619 constraint (inst.operands[2].shifted
12620 && inst.operands[2].immisreg,
12621 _("shift must be constant"));
12622 encode_thumb32_shifted_operand (2);
12629 unsigned Rd, Rn, Rm;
12631 Rd = inst.operands[0].reg;
12632 Rn = inst.operands[1].reg;
12633 Rm = inst.operands[2].reg;
12635 reject_bad_reg (Rd);
12636 reject_bad_reg (Rn);
12637 reject_bad_reg (Rm);
12639 inst.instruction |= Rd << 8;
12640 inst.instruction |= Rn << 16;
12641 inst.instruction |= Rm;
12642 if (inst.operands[3].present)
12644 unsigned int val = inst.reloc.exp.X_add_number;
12645 constraint (inst.reloc.exp.X_op != O_constant,
12646 _("expression too complex"));
12647 inst.instruction |= (val & 0x1c) << 10;
12648 inst.instruction |= (val & 0x03) << 6;
12655 if (!inst.operands[3].present)
12659 inst.instruction &= ~0x00000020;
12661 /* PR 10168. Swap the Rm and Rn registers. */
12662 Rtmp = inst.operands[1].reg;
12663 inst.operands[1].reg = inst.operands[2].reg;
12664 inst.operands[2].reg = Rtmp;
12672 if (inst.operands[0].immisreg)
12673 reject_bad_reg (inst.operands[0].imm);
12675 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12679 do_t_push_pop (void)
12683 constraint (inst.operands[0].writeback,
12684 _("push/pop do not support {reglist}^"));
12685 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12686 _("expression too complex"));
12688 mask = inst.operands[0].imm;
12689 if (inst.size_req != 4 && (mask & ~0xff) == 0)
12690 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
12691 else if (inst.size_req != 4
12692 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
12693 ? REG_LR : REG_PC)))
12695 inst.instruction = THUMB_OP16 (inst.instruction);
12696 inst.instruction |= THUMB_PP_PC_LR;
12697 inst.instruction |= mask & 0xff;
12699 else if (unified_syntax)
12701 inst.instruction = THUMB_OP32 (inst.instruction);
12702 encode_thumb2_ldmstm (13, mask, TRUE);
12706 inst.error = _("invalid register list to push/pop instruction");
12716 Rd = inst.operands[0].reg;
12717 Rm = inst.operands[1].reg;
12719 reject_bad_reg (Rd);
12720 reject_bad_reg (Rm);
12722 inst.instruction |= Rd << 8;
12723 inst.instruction |= Rm << 16;
12724 inst.instruction |= Rm;
12732 Rd = inst.operands[0].reg;
12733 Rm = inst.operands[1].reg;
12735 reject_bad_reg (Rd);
12736 reject_bad_reg (Rm);
12738 if (Rd <= 7 && Rm <= 7
12739 && inst.size_req != 4)
12741 inst.instruction = THUMB_OP16 (inst.instruction);
12742 inst.instruction |= Rd;
12743 inst.instruction |= Rm << 3;
12745 else if (unified_syntax)
12747 inst.instruction = THUMB_OP32 (inst.instruction);
12748 inst.instruction |= Rd << 8;
12749 inst.instruction |= Rm << 16;
12750 inst.instruction |= Rm;
12753 inst.error = BAD_HIREG;
12761 Rd = inst.operands[0].reg;
12762 Rm = inst.operands[1].reg;
12764 reject_bad_reg (Rd);
12765 reject_bad_reg (Rm);
12767 inst.instruction |= Rd << 8;
12768 inst.instruction |= Rm;
12776 Rd = inst.operands[0].reg;
12777 Rs = (inst.operands[1].present
12778 ? inst.operands[1].reg /* Rd, Rs, foo */
12779 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
12781 reject_bad_reg (Rd);
12782 reject_bad_reg (Rs);
12783 if (inst.operands[2].isreg)
12784 reject_bad_reg (inst.operands[2].reg);
12786 inst.instruction |= Rd << 8;
12787 inst.instruction |= Rs << 16;
12788 if (!inst.operands[2].isreg)
12790 bfd_boolean narrow;
12792 if ((inst.instruction & 0x00100000) != 0)
12793 narrow = !in_it_block ();
12795 narrow = in_it_block ();
12797 if (Rd > 7 || Rs > 7)
12800 if (inst.size_req == 4 || !unified_syntax)
12803 if (inst.reloc.exp.X_op != O_constant
12804 || inst.reloc.exp.X_add_number != 0)
12807 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12808 relaxation, but it doesn't seem worth the hassle. */
12811 inst.reloc.type = BFD_RELOC_UNUSED;
12812 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12813 inst.instruction |= Rs << 3;
12814 inst.instruction |= Rd;
12818 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12819 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12823 encode_thumb32_shifted_operand (2);
12829 if (warn_on_deprecated
12830 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12831 as_tsktsk (_("setend use is deprecated for ARMv8"));
12833 set_it_insn_type (OUTSIDE_IT_INSN);
12834 if (inst.operands[0].imm)
12835 inst.instruction |= 0x8;
12841 if (!inst.operands[1].present)
12842 inst.operands[1].reg = inst.operands[0].reg;
12844 if (unified_syntax)
12846 bfd_boolean narrow;
12849 switch (inst.instruction)
12852 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12854 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12856 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12858 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12862 if (THUMB_SETS_FLAGS (inst.instruction))
12863 narrow = !in_it_block ();
12865 narrow = in_it_block ();
12866 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12868 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12870 if (inst.operands[2].isreg
12871 && (inst.operands[1].reg != inst.operands[0].reg
12872 || inst.operands[2].reg > 7))
12874 if (inst.size_req == 4)
12877 reject_bad_reg (inst.operands[0].reg);
12878 reject_bad_reg (inst.operands[1].reg);
12882 if (inst.operands[2].isreg)
12884 reject_bad_reg (inst.operands[2].reg);
12885 inst.instruction = THUMB_OP32 (inst.instruction);
12886 inst.instruction |= inst.operands[0].reg << 8;
12887 inst.instruction |= inst.operands[1].reg << 16;
12888 inst.instruction |= inst.operands[2].reg;
12890 /* PR 12854: Error on extraneous shifts. */
12891 constraint (inst.operands[2].shifted,
12892 _("extraneous shift as part of operand to shift insn"));
12896 inst.operands[1].shifted = 1;
12897 inst.operands[1].shift_kind = shift_kind;
12898 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12899 ? T_MNEM_movs : T_MNEM_mov);
12900 inst.instruction |= inst.operands[0].reg << 8;
12901 encode_thumb32_shifted_operand (1);
12902 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12903 inst.reloc.type = BFD_RELOC_UNUSED;
12908 if (inst.operands[2].isreg)
12910 switch (shift_kind)
12912 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12913 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12914 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12915 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
12919 inst.instruction |= inst.operands[0].reg;
12920 inst.instruction |= inst.operands[2].reg << 3;
12922 /* PR 12854: Error on extraneous shifts. */
12923 constraint (inst.operands[2].shifted,
12924 _("extraneous shift as part of operand to shift insn"));
12928 switch (shift_kind)
12930 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12931 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12932 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12935 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12936 inst.instruction |= inst.operands[0].reg;
12937 inst.instruction |= inst.operands[1].reg << 3;
12943 constraint (inst.operands[0].reg > 7
12944 || inst.operands[1].reg > 7, BAD_HIREG);
12945 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12947 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12949 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12950 constraint (inst.operands[0].reg != inst.operands[1].reg,
12951 _("source1 and dest must be same register"));
12953 switch (inst.instruction)
12955 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12956 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12957 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12958 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12962 inst.instruction |= inst.operands[0].reg;
12963 inst.instruction |= inst.operands[2].reg << 3;
12965 /* PR 12854: Error on extraneous shifts. */
12966 constraint (inst.operands[2].shifted,
12967 _("extraneous shift as part of operand to shift insn"));
12971 switch (inst.instruction)
12973 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12974 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12975 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12976 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12979 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12980 inst.instruction |= inst.operands[0].reg;
12981 inst.instruction |= inst.operands[1].reg << 3;
12989 unsigned Rd, Rn, Rm;
12991 Rd = inst.operands[0].reg;
12992 Rn = inst.operands[1].reg;
12993 Rm = inst.operands[2].reg;
12995 reject_bad_reg (Rd);
12996 reject_bad_reg (Rn);
12997 reject_bad_reg (Rm);
12999 inst.instruction |= Rd << 8;
13000 inst.instruction |= Rn << 16;
13001 inst.instruction |= Rm;
13007 unsigned Rd, Rn, Rm;
13009 Rd = inst.operands[0].reg;
13010 Rm = inst.operands[1].reg;
13011 Rn = inst.operands[2].reg;
13013 reject_bad_reg (Rd);
13014 reject_bad_reg (Rn);
13015 reject_bad_reg (Rm);
13017 inst.instruction |= Rd << 8;
13018 inst.instruction |= Rn << 16;
13019 inst.instruction |= Rm;
13025 unsigned int value = inst.reloc.exp.X_add_number;
13026 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13027 _("SMC is not permitted on this architecture"));
13028 constraint (inst.reloc.exp.X_op != O_constant,
13029 _("expression too complex"));
13030 inst.reloc.type = BFD_RELOC_UNUSED;
13031 inst.instruction |= (value & 0xf000) >> 12;
13032 inst.instruction |= (value & 0x0ff0);
13033 inst.instruction |= (value & 0x000f) << 16;
13034 /* PR gas/15623: SMC instructions must be last in an IT block. */
13035 set_it_insn_type_last ();
13041 unsigned int value = inst.reloc.exp.X_add_number;
13043 inst.reloc.type = BFD_RELOC_UNUSED;
13044 inst.instruction |= (value & 0x0fff);
13045 inst.instruction |= (value & 0xf000) << 4;
13049 do_t_ssat_usat (int bias)
13053 Rd = inst.operands[0].reg;
13054 Rn = inst.operands[2].reg;
13056 reject_bad_reg (Rd);
13057 reject_bad_reg (Rn);
13059 inst.instruction |= Rd << 8;
13060 inst.instruction |= inst.operands[1].imm - bias;
13061 inst.instruction |= Rn << 16;
13063 if (inst.operands[3].present)
13065 offsetT shift_amount = inst.reloc.exp.X_add_number;
13067 inst.reloc.type = BFD_RELOC_UNUSED;
13069 constraint (inst.reloc.exp.X_op != O_constant,
13070 _("expression too complex"));
13072 if (shift_amount != 0)
13074 constraint (shift_amount > 31,
13075 _("shift expression is too large"));
13077 if (inst.operands[3].shift_kind == SHIFT_ASR)
13078 inst.instruction |= 0x00200000; /* sh bit. */
13080 inst.instruction |= (shift_amount & 0x1c) << 10;
13081 inst.instruction |= (shift_amount & 0x03) << 6;
13089 do_t_ssat_usat (1);
13097 Rd = inst.operands[0].reg;
13098 Rn = inst.operands[2].reg;
13100 reject_bad_reg (Rd);
13101 reject_bad_reg (Rn);
13103 inst.instruction |= Rd << 8;
13104 inst.instruction |= inst.operands[1].imm - 1;
13105 inst.instruction |= Rn << 16;
13111 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
13112 || inst.operands[2].postind || inst.operands[2].writeback
13113 || inst.operands[2].immisreg || inst.operands[2].shifted
13114 || inst.operands[2].negative,
13117 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
13119 inst.instruction |= inst.operands[0].reg << 8;
13120 inst.instruction |= inst.operands[1].reg << 12;
13121 inst.instruction |= inst.operands[2].reg << 16;
13122 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
13128 if (!inst.operands[2].present)
13129 inst.operands[2].reg = inst.operands[1].reg + 1;
13131 constraint (inst.operands[0].reg == inst.operands[1].reg
13132 || inst.operands[0].reg == inst.operands[2].reg
13133 || inst.operands[0].reg == inst.operands[3].reg,
13136 inst.instruction |= inst.operands[0].reg;
13137 inst.instruction |= inst.operands[1].reg << 12;
13138 inst.instruction |= inst.operands[2].reg << 8;
13139 inst.instruction |= inst.operands[3].reg << 16;
13145 unsigned Rd, Rn, Rm;
13147 Rd = inst.operands[0].reg;
13148 Rn = inst.operands[1].reg;
13149 Rm = inst.operands[2].reg;
13151 reject_bad_reg (Rd);
13152 reject_bad_reg (Rn);
13153 reject_bad_reg (Rm);
13155 inst.instruction |= Rd << 8;
13156 inst.instruction |= Rn << 16;
13157 inst.instruction |= Rm;
13158 inst.instruction |= inst.operands[3].imm << 4;
13166 Rd = inst.operands[0].reg;
13167 Rm = inst.operands[1].reg;
13169 reject_bad_reg (Rd);
13170 reject_bad_reg (Rm);
13172 if (inst.instruction <= 0xffff
13173 && inst.size_req != 4
13174 && Rd <= 7 && Rm <= 7
13175 && (!inst.operands[2].present || inst.operands[2].imm == 0))
13177 inst.instruction = THUMB_OP16 (inst.instruction);
13178 inst.instruction |= Rd;
13179 inst.instruction |= Rm << 3;
13181 else if (unified_syntax)
13183 if (inst.instruction <= 0xffff)
13184 inst.instruction = THUMB_OP32 (inst.instruction);
13185 inst.instruction |= Rd << 8;
13186 inst.instruction |= Rm;
13187 inst.instruction |= inst.operands[2].imm << 4;
13191 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
13192 _("Thumb encoding does not support rotation"));
13193 constraint (1, BAD_HIREG);
13200 inst.reloc.type = BFD_RELOC_ARM_SWI;
13209 half = (inst.instruction & 0x10) != 0;
13210 set_it_insn_type_last ();
13211 constraint (inst.operands[0].immisreg,
13212 _("instruction requires register index"));
13214 Rn = inst.operands[0].reg;
13215 Rm = inst.operands[0].imm;
13217 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13218 constraint (Rn == REG_SP, BAD_SP);
13219 reject_bad_reg (Rm);
13221 constraint (!half && inst.operands[0].shifted,
13222 _("instruction does not allow shifted index"));
13223 inst.instruction |= (Rn << 16) | Rm;
13229 if (!inst.operands[0].present)
13230 inst.operands[0].imm = 0;
13232 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
13234 constraint (inst.size_req == 2,
13235 _("immediate value out of range"));
13236 inst.instruction = THUMB_OP32 (inst.instruction);
13237 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
13238 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
13242 inst.instruction = THUMB_OP16 (inst.instruction);
13243 inst.instruction |= inst.operands[0].imm;
13246 set_it_insn_type (NEUTRAL_IT_INSN);
13253 do_t_ssat_usat (0);
13261 Rd = inst.operands[0].reg;
13262 Rn = inst.operands[2].reg;
13264 reject_bad_reg (Rd);
13265 reject_bad_reg (Rn);
13267 inst.instruction |= Rd << 8;
13268 inst.instruction |= inst.operands[1].imm;
13269 inst.instruction |= Rn << 16;
13272 /* Neon instruction encoder helpers. */
13274 /* Encodings for the different types for various Neon opcodes. */
13276 /* An "invalid" code for the following tables. */
13279 struct neon_tab_entry
13282 unsigned float_or_poly;
13283 unsigned scalar_or_imm;
13286 /* Map overloaded Neon opcodes to their respective encodings. */
13287 #define NEON_ENC_TAB \
13288 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13289 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13290 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13291 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13292 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13293 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13294 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13295 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13296 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13297 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13298 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13299 /* Register variants of the following two instructions are encoded as
13300 vcge / vcgt with the operands reversed. */ \
13301 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13302 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13303 X(vfma, N_INV, 0x0000c10, N_INV), \
13304 X(vfms, N_INV, 0x0200c10, N_INV), \
13305 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13306 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13307 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13308 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13309 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13310 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13311 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13312 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13313 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13314 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13315 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13316 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13317 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13318 X(vshl, 0x0000400, N_INV, 0x0800510), \
13319 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13320 X(vand, 0x0000110, N_INV, 0x0800030), \
13321 X(vbic, 0x0100110, N_INV, 0x0800030), \
13322 X(veor, 0x1000110, N_INV, N_INV), \
13323 X(vorn, 0x0300110, N_INV, 0x0800010), \
13324 X(vorr, 0x0200110, N_INV, 0x0800010), \
13325 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13326 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13327 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13328 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13329 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13330 X(vst1, 0x0000000, 0x0800000, N_INV), \
13331 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13332 X(vst2, 0x0000100, 0x0800100, N_INV), \
13333 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13334 X(vst3, 0x0000200, 0x0800200, N_INV), \
13335 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13336 X(vst4, 0x0000300, 0x0800300, N_INV), \
13337 X(vmovn, 0x1b20200, N_INV, N_INV), \
13338 X(vtrn, 0x1b20080, N_INV, N_INV), \
13339 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13340 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13341 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13342 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13343 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13344 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13345 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13346 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13347 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13348 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13349 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13350 X(vseleq, 0xe000a00, N_INV, N_INV), \
13351 X(vselvs, 0xe100a00, N_INV, N_INV), \
13352 X(vselge, 0xe200a00, N_INV, N_INV), \
13353 X(vselgt, 0xe300a00, N_INV, N_INV), \
13354 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13355 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13356 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13357 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13358 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13359 X(aes, 0x3b00300, N_INV, N_INV), \
13360 X(sha3op, 0x2000c00, N_INV, N_INV), \
13361 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13362 X(sha2op, 0x3ba0380, N_INV, N_INV)
13366 #define X(OPC,I,F,S) N_MNEM_##OPC
13371 static const struct neon_tab_entry neon_enc_tab[] =
13373 #define X(OPC,I,F,S) { (I), (F), (S) }
13378 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13379 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13380 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13381 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13382 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13383 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13384 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13385 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13386 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13387 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13388 #define NEON_ENC_SINGLE_(X) \
13389 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13390 #define NEON_ENC_DOUBLE_(X) \
13391 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13392 #define NEON_ENC_FPV8_(X) \
13393 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13395 #define NEON_ENCODE(type, inst) \
13398 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13399 inst.is_neon = 1; \
13403 #define check_neon_suffixes \
13406 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13408 as_bad (_("invalid neon suffix for non neon instruction")); \
13414 /* Define shapes for instruction operands. The following mnemonic characters
13415 are used in this table:
13417 F - VFP S<n> register
13418 D - Neon D<n> register
13419 Q - Neon Q<n> register
13423 L - D<n> register list
13425 This table is used to generate various data:
13426 - enumerations of the form NS_DDR to be used as arguments to
13428 - a table classifying shapes into single, double, quad, mixed.
13429 - a table used to drive neon_select_shape. */
13431 #define NEON_SHAPE_DEF \
13432 X(3, (D, D, D), DOUBLE), \
13433 X(3, (Q, Q, Q), QUAD), \
13434 X(3, (D, D, I), DOUBLE), \
13435 X(3, (Q, Q, I), QUAD), \
13436 X(3, (D, D, S), DOUBLE), \
13437 X(3, (Q, Q, S), QUAD), \
13438 X(2, (D, D), DOUBLE), \
13439 X(2, (Q, Q), QUAD), \
13440 X(2, (D, S), DOUBLE), \
13441 X(2, (Q, S), QUAD), \
13442 X(2, (D, R), DOUBLE), \
13443 X(2, (Q, R), QUAD), \
13444 X(2, (D, I), DOUBLE), \
13445 X(2, (Q, I), QUAD), \
13446 X(3, (D, L, D), DOUBLE), \
13447 X(2, (D, Q), MIXED), \
13448 X(2, (Q, D), MIXED), \
13449 X(3, (D, Q, I), MIXED), \
13450 X(3, (Q, D, I), MIXED), \
13451 X(3, (Q, D, D), MIXED), \
13452 X(3, (D, Q, Q), MIXED), \
13453 X(3, (Q, Q, D), MIXED), \
13454 X(3, (Q, D, S), MIXED), \
13455 X(3, (D, Q, S), MIXED), \
13456 X(4, (D, D, D, I), DOUBLE), \
13457 X(4, (Q, Q, Q, I), QUAD), \
13458 X(4, (D, D, S, I), DOUBLE), \
13459 X(4, (Q, Q, S, I), QUAD), \
13460 X(2, (F, F), SINGLE), \
13461 X(3, (F, F, F), SINGLE), \
13462 X(2, (F, I), SINGLE), \
13463 X(2, (F, D), MIXED), \
13464 X(2, (D, F), MIXED), \
13465 X(3, (F, F, I), MIXED), \
13466 X(4, (R, R, F, F), SINGLE), \
13467 X(4, (F, F, R, R), SINGLE), \
13468 X(3, (D, R, R), DOUBLE), \
13469 X(3, (R, R, D), DOUBLE), \
13470 X(2, (S, R), SINGLE), \
13471 X(2, (R, S), SINGLE), \
13472 X(2, (F, R), SINGLE), \
13473 X(2, (R, F), SINGLE), \
13474 /* Half float shape supported so far. */\
13475 X (2, (H, D), MIXED), \
13476 X (2, (D, H), MIXED), \
13477 X (2, (H, F), MIXED), \
13478 X (2, (F, H), MIXED), \
13479 X (2, (H, H), HALF), \
13480 X (2, (H, R), HALF), \
13481 X (2, (R, H), HALF), \
13482 X (2, (H, I), HALF), \
13483 X (3, (H, H, H), HALF), \
13484 X (3, (H, F, I), MIXED), \
13485 X (3, (F, H, I), MIXED), \
13486 X (3, (D, H, H), MIXED), \
13487 X (3, (D, H, S), MIXED)
13489 #define S2(A,B) NS_##A##B
13490 #define S3(A,B,C) NS_##A##B##C
13491 #define S4(A,B,C,D) NS_##A##B##C##D
13493 #define X(N, L, C) S##N L
13506 enum neon_shape_class
13515 #define X(N, L, C) SC_##C
13517 static enum neon_shape_class neon_shape_class[] =
13536 /* Register widths of above. */
13537 static unsigned neon_shape_el_size[] =
13549 struct neon_shape_info
13552 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13555 #define S2(A,B) { SE_##A, SE_##B }
13556 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13557 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13559 #define X(N, L, C) { N, S##N L }
13561 static struct neon_shape_info neon_shape_tab[] =
13571 /* Bit masks used in type checking given instructions.
13572 'N_EQK' means the type must be the same as (or based on in some way) the key
13573 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13574 set, various other bits can be set as well in order to modify the meaning of
13575 the type constraint. */
13577 enum neon_type_mask
13601 N_KEY = 0x1000000, /* Key element (main type specifier). */
13602 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
13603 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
13604 N_UNT = 0x8000000, /* Must be explicitly untyped. */
13605 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13606 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13607 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13608 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13609 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13610 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13611 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13613 N_MAX_NONSPECIAL = N_P64
13616 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13618 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13619 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13620 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13621 #define N_S_32 (N_S8 | N_S16 | N_S32)
13622 #define N_F_16_32 (N_F16 | N_F32)
13623 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13624 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13625 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13626 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13628 /* Pass this as the first type argument to neon_check_type to ignore types
13630 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13632 /* Select a "shape" for the current instruction (describing register types or
13633 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13634 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13635 function of operand parsing, so this function doesn't need to be called.
13636 Shapes should be listed in order of decreasing length. */
13638 static enum neon_shape
13639 neon_select_shape (enum neon_shape shape, ...)
13642 enum neon_shape first_shape = shape;
13644 /* Fix missing optional operands. FIXME: we don't know at this point how
13645 many arguments we should have, so this makes the assumption that we have
13646 > 1. This is true of all current Neon opcodes, I think, but may not be
13647 true in the future. */
13648 if (!inst.operands[1].present)
13649 inst.operands[1] = inst.operands[0];
13651 va_start (ap, shape);
13653 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
13658 for (j = 0; j < neon_shape_tab[shape].els; j++)
13660 if (!inst.operands[j].present)
13666 switch (neon_shape_tab[shape].el[j])
13668 /* If a .f16, .16, .u16, .s16 type specifier is given over
13669 a VFP single precision register operand, it's essentially
13670 means only half of the register is used.
13672 If the type specifier is given after the mnemonics, the
13673 information is stored in inst.vectype. If the type specifier
13674 is given after register operand, the information is stored
13675 in inst.operands[].vectype.
13677 When there is only one type specifier, and all the register
13678 operands are the same type of hardware register, the type
13679 specifier applies to all register operands.
13681 If no type specifier is given, the shape is inferred from
13682 operand information.
13685 vadd.f16 s0, s1, s2: NS_HHH
13686 vabs.f16 s0, s1: NS_HH
13687 vmov.f16 s0, r1: NS_HR
13688 vmov.f16 r0, s1: NS_RH
13689 vcvt.f16 r0, s1: NS_RH
13690 vcvt.f16.s32 s2, s2, #29: NS_HFI
13691 vcvt.f16.s32 s2, s2: NS_HF
13694 if (!(inst.operands[j].isreg
13695 && inst.operands[j].isvec
13696 && inst.operands[j].issingle
13697 && !inst.operands[j].isquad
13698 && ((inst.vectype.elems == 1
13699 && inst.vectype.el[0].size == 16)
13700 || (inst.vectype.elems > 1
13701 && inst.vectype.el[j].size == 16)
13702 || (inst.vectype.elems == 0
13703 && inst.operands[j].vectype.type != NT_invtype
13704 && inst.operands[j].vectype.size == 16))))
13709 if (!(inst.operands[j].isreg
13710 && inst.operands[j].isvec
13711 && inst.operands[j].issingle
13712 && !inst.operands[j].isquad
13713 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
13714 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
13715 || (inst.vectype.elems == 0
13716 && (inst.operands[j].vectype.size == 32
13717 || inst.operands[j].vectype.type == NT_invtype)))))
13722 if (!(inst.operands[j].isreg
13723 && inst.operands[j].isvec
13724 && !inst.operands[j].isquad
13725 && !inst.operands[j].issingle))
13730 if (!(inst.operands[j].isreg
13731 && !inst.operands[j].isvec))
13736 if (!(inst.operands[j].isreg
13737 && inst.operands[j].isvec
13738 && inst.operands[j].isquad
13739 && !inst.operands[j].issingle))
13744 if (!(!inst.operands[j].isreg
13745 && !inst.operands[j].isscalar))
13750 if (!(!inst.operands[j].isreg
13751 && inst.operands[j].isscalar))
13761 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13762 /* We've matched all the entries in the shape table, and we don't
13763 have any left over operands which have not been matched. */
13769 if (shape == NS_NULL && first_shape != NS_NULL)
13770 first_error (_("invalid instruction shape"));
13775 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13776 means the Q bit should be set). */
13779 neon_quad (enum neon_shape shape)
13781 return neon_shape_class[shape] == SC_QUAD;
13785 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
13788 /* Allow modification to be made to types which are constrained to be
13789 based on the key element, based on bits set alongside N_EQK. */
13790 if ((typebits & N_EQK) != 0)
13792 if ((typebits & N_HLF) != 0)
13794 else if ((typebits & N_DBL) != 0)
13796 if ((typebits & N_SGN) != 0)
13797 *g_type = NT_signed;
13798 else if ((typebits & N_UNS) != 0)
13799 *g_type = NT_unsigned;
13800 else if ((typebits & N_INT) != 0)
13801 *g_type = NT_integer;
13802 else if ((typebits & N_FLT) != 0)
13803 *g_type = NT_float;
13804 else if ((typebits & N_SIZ) != 0)
13805 *g_type = NT_untyped;
13809 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13810 operand type, i.e. the single type specified in a Neon instruction when it
13811 is the only one given. */
13813 static struct neon_type_el
13814 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13816 struct neon_type_el dest = *key;
13818 gas_assert ((thisarg & N_EQK) != 0);
13820 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13825 /* Convert Neon type and size into compact bitmask representation. */
13827 static enum neon_type_mask
13828 type_chk_of_el_type (enum neon_el_type type, unsigned size)
13835 case 8: return N_8;
13836 case 16: return N_16;
13837 case 32: return N_32;
13838 case 64: return N_64;
13846 case 8: return N_I8;
13847 case 16: return N_I16;
13848 case 32: return N_I32;
13849 case 64: return N_I64;
13857 case 16: return N_F16;
13858 case 32: return N_F32;
13859 case 64: return N_F64;
13867 case 8: return N_P8;
13868 case 16: return N_P16;
13869 case 64: return N_P64;
13877 case 8: return N_S8;
13878 case 16: return N_S16;
13879 case 32: return N_S32;
13880 case 64: return N_S64;
13888 case 8: return N_U8;
13889 case 16: return N_U16;
13890 case 32: return N_U32;
13891 case 64: return N_U64;
13902 /* Convert compact Neon bitmask type representation to a type and size. Only
13903 handles the case where a single bit is set in the mask. */
13906 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
13907 enum neon_type_mask mask)
13909 if ((mask & N_EQK) != 0)
13912 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13914 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
13916 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
13918 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
13923 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13925 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
13926 *type = NT_unsigned;
13927 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
13928 *type = NT_integer;
13929 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
13930 *type = NT_untyped;
13931 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
13933 else if ((mask & (N_F_ALL)) != 0)
13941 /* Modify a bitmask of allowed types. This is only needed for type
13945 modify_types_allowed (unsigned allowed, unsigned mods)
13948 enum neon_el_type type;
13954 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13956 if (el_type_of_type_chk (&type, &size,
13957 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13959 neon_modify_type_size (mods, &type, &size);
13960 destmask |= type_chk_of_el_type (type, size);
13967 /* Check type and return type classification.
13968 The manual states (paraphrase): If one datatype is given, it indicates the
13970 - the second operand, if there is one
13971 - the operand, if there is no second operand
13972 - the result, if there are no operands.
13973 This isn't quite good enough though, so we use a concept of a "key" datatype
13974 which is set on a per-instruction basis, which is the one which matters when
13975 only one data type is written.
13976 Note: this function has side-effects (e.g. filling in missing operands). All
13977 Neon instructions should call it before performing bit encoding. */
13979 static struct neon_type_el
13980 neon_check_type (unsigned els, enum neon_shape ns, ...)
13983 unsigned i, pass, key_el = 0;
13984 unsigned types[NEON_MAX_TYPE_ELS];
13985 enum neon_el_type k_type = NT_invtype;
13986 unsigned k_size = -1u;
13987 struct neon_type_el badtype = {NT_invtype, -1};
13988 unsigned key_allowed = 0;
13990 /* Optional registers in Neon instructions are always (not) in operand 1.
13991 Fill in the missing operand here, if it was omitted. */
13992 if (els > 1 && !inst.operands[1].present)
13993 inst.operands[1] = inst.operands[0];
13995 /* Suck up all the varargs. */
13997 for (i = 0; i < els; i++)
13999 unsigned thisarg = va_arg (ap, unsigned);
14000 if (thisarg == N_IGNORE_TYPE)
14005 types[i] = thisarg;
14006 if ((thisarg & N_KEY) != 0)
14011 if (inst.vectype.elems > 0)
14012 for (i = 0; i < els; i++)
14013 if (inst.operands[i].vectype.type != NT_invtype)
14015 first_error (_("types specified in both the mnemonic and operands"));
14019 /* Duplicate inst.vectype elements here as necessary.
14020 FIXME: No idea if this is exactly the same as the ARM assembler,
14021 particularly when an insn takes one register and one non-register
14023 if (inst.vectype.elems == 1 && els > 1)
14026 inst.vectype.elems = els;
14027 inst.vectype.el[key_el] = inst.vectype.el[0];
14028 for (j = 0; j < els; j++)
14030 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14033 else if (inst.vectype.elems == 0 && els > 0)
14036 /* No types were given after the mnemonic, so look for types specified
14037 after each operand. We allow some flexibility here; as long as the
14038 "key" operand has a type, we can infer the others. */
14039 for (j = 0; j < els; j++)
14040 if (inst.operands[j].vectype.type != NT_invtype)
14041 inst.vectype.el[j] = inst.operands[j].vectype;
14043 if (inst.operands[key_el].vectype.type != NT_invtype)
14045 for (j = 0; j < els; j++)
14046 if (inst.operands[j].vectype.type == NT_invtype)
14047 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
14052 first_error (_("operand types can't be inferred"));
14056 else if (inst.vectype.elems != els)
14058 first_error (_("type specifier has the wrong number of parts"));
14062 for (pass = 0; pass < 2; pass++)
14064 for (i = 0; i < els; i++)
14066 unsigned thisarg = types[i];
14067 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
14068 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
14069 enum neon_el_type g_type = inst.vectype.el[i].type;
14070 unsigned g_size = inst.vectype.el[i].size;
14072 /* Decay more-specific signed & unsigned types to sign-insensitive
14073 integer types if sign-specific variants are unavailable. */
14074 if ((g_type == NT_signed || g_type == NT_unsigned)
14075 && (types_allowed & N_SU_ALL) == 0)
14076 g_type = NT_integer;
14078 /* If only untyped args are allowed, decay any more specific types to
14079 them. Some instructions only care about signs for some element
14080 sizes, so handle that properly. */
14081 if (((types_allowed & N_UNT) == 0)
14082 && ((g_size == 8 && (types_allowed & N_8) != 0)
14083 || (g_size == 16 && (types_allowed & N_16) != 0)
14084 || (g_size == 32 && (types_allowed & N_32) != 0)
14085 || (g_size == 64 && (types_allowed & N_64) != 0)))
14086 g_type = NT_untyped;
14090 if ((thisarg & N_KEY) != 0)
14094 key_allowed = thisarg & ~N_KEY;
14096 /* Check architecture constraint on FP16 extension. */
14098 && k_type == NT_float
14099 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
14101 inst.error = _(BAD_FP16);
14108 if ((thisarg & N_VFP) != 0)
14110 enum neon_shape_el regshape;
14111 unsigned regwidth, match;
14113 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14116 first_error (_("invalid instruction shape"));
14119 regshape = neon_shape_tab[ns].el[i];
14120 regwidth = neon_shape_el_size[regshape];
14122 /* In VFP mode, operands must match register widths. If we
14123 have a key operand, use its width, else use the width of
14124 the current operand. */
14130 /* FP16 will use a single precision register. */
14131 if (regwidth == 32 && match == 16)
14133 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
14137 inst.error = _(BAD_FP16);
14142 if (regwidth != match)
14144 first_error (_("operand size must match register width"));
14149 if ((thisarg & N_EQK) == 0)
14151 unsigned given_type = type_chk_of_el_type (g_type, g_size);
14153 if ((given_type & types_allowed) == 0)
14155 first_error (_("bad type in Neon instruction"));
14161 enum neon_el_type mod_k_type = k_type;
14162 unsigned mod_k_size = k_size;
14163 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
14164 if (g_type != mod_k_type || g_size != mod_k_size)
14166 first_error (_("inconsistent types in Neon instruction"));
14174 return inst.vectype.el[key_el];
14177 /* Neon-style VFP instruction forwarding. */
14179 /* Thumb VFP instructions have 0xE in the condition field. */
14182 do_vfp_cond_or_thumb (void)
14187 inst.instruction |= 0xe0000000;
14189 inst.instruction |= inst.cond << 28;
14192 /* Look up and encode a simple mnemonic, for use as a helper function for the
14193 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14194 etc. It is assumed that operand parsing has already been done, and that the
14195 operands are in the form expected by the given opcode (this isn't necessarily
14196 the same as the form in which they were parsed, hence some massaging must
14197 take place before this function is called).
14198 Checks current arch version against that in the looked-up opcode. */
14201 do_vfp_nsyn_opcode (const char *opname)
14203 const struct asm_opcode *opcode;
14205 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
14210 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
14211 thumb_mode ? *opcode->tvariant : *opcode->avariant),
14218 inst.instruction = opcode->tvalue;
14219 opcode->tencode ();
14223 inst.instruction = (inst.cond << 28) | opcode->avalue;
14224 opcode->aencode ();
14229 do_vfp_nsyn_add_sub (enum neon_shape rs)
14231 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
14233 if (rs == NS_FFF || rs == NS_HHH)
14236 do_vfp_nsyn_opcode ("fadds");
14238 do_vfp_nsyn_opcode ("fsubs");
14240 /* ARMv8.2 fp16 instruction. */
14242 do_scalar_fp16_v82_encode ();
14247 do_vfp_nsyn_opcode ("faddd");
14249 do_vfp_nsyn_opcode ("fsubd");
14253 /* Check operand types to see if this is a VFP instruction, and if so call
14257 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
14259 enum neon_shape rs;
14260 struct neon_type_el et;
14265 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14266 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14270 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14271 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14272 N_F_ALL | N_KEY | N_VFP);
14279 if (et.type != NT_invtype)
14290 do_vfp_nsyn_mla_mls (enum neon_shape rs)
14292 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
14294 if (rs == NS_FFF || rs == NS_HHH)
14297 do_vfp_nsyn_opcode ("fmacs");
14299 do_vfp_nsyn_opcode ("fnmacs");
14301 /* ARMv8.2 fp16 instruction. */
14303 do_scalar_fp16_v82_encode ();
14308 do_vfp_nsyn_opcode ("fmacd");
14310 do_vfp_nsyn_opcode ("fnmacd");
14315 do_vfp_nsyn_fma_fms (enum neon_shape rs)
14317 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
14319 if (rs == NS_FFF || rs == NS_HHH)
14322 do_vfp_nsyn_opcode ("ffmas");
14324 do_vfp_nsyn_opcode ("ffnmas");
14326 /* ARMv8.2 fp16 instruction. */
14328 do_scalar_fp16_v82_encode ();
14333 do_vfp_nsyn_opcode ("ffmad");
14335 do_vfp_nsyn_opcode ("ffnmad");
14340 do_vfp_nsyn_mul (enum neon_shape rs)
14342 if (rs == NS_FFF || rs == NS_HHH)
14344 do_vfp_nsyn_opcode ("fmuls");
14346 /* ARMv8.2 fp16 instruction. */
14348 do_scalar_fp16_v82_encode ();
14351 do_vfp_nsyn_opcode ("fmuld");
14355 do_vfp_nsyn_abs_neg (enum neon_shape rs)
14357 int is_neg = (inst.instruction & 0x80) != 0;
14358 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
14360 if (rs == NS_FF || rs == NS_HH)
14363 do_vfp_nsyn_opcode ("fnegs");
14365 do_vfp_nsyn_opcode ("fabss");
14367 /* ARMv8.2 fp16 instruction. */
14369 do_scalar_fp16_v82_encode ();
14374 do_vfp_nsyn_opcode ("fnegd");
14376 do_vfp_nsyn_opcode ("fabsd");
14380 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14381 insns belong to Neon, and are handled elsewhere. */
14384 do_vfp_nsyn_ldm_stm (int is_dbmode)
14386 int is_ldm = (inst.instruction & (1 << 20)) != 0;
14390 do_vfp_nsyn_opcode ("fldmdbs");
14392 do_vfp_nsyn_opcode ("fldmias");
14397 do_vfp_nsyn_opcode ("fstmdbs");
14399 do_vfp_nsyn_opcode ("fstmias");
14404 do_vfp_nsyn_sqrt (void)
14406 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14407 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14409 if (rs == NS_FF || rs == NS_HH)
14411 do_vfp_nsyn_opcode ("fsqrts");
14413 /* ARMv8.2 fp16 instruction. */
14415 do_scalar_fp16_v82_encode ();
14418 do_vfp_nsyn_opcode ("fsqrtd");
14422 do_vfp_nsyn_div (void)
14424 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14425 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14426 N_F_ALL | N_KEY | N_VFP);
14428 if (rs == NS_FFF || rs == NS_HHH)
14430 do_vfp_nsyn_opcode ("fdivs");
14432 /* ARMv8.2 fp16 instruction. */
14434 do_scalar_fp16_v82_encode ();
14437 do_vfp_nsyn_opcode ("fdivd");
14441 do_vfp_nsyn_nmul (void)
14443 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
14444 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14445 N_F_ALL | N_KEY | N_VFP);
14447 if (rs == NS_FFF || rs == NS_HHH)
14449 NEON_ENCODE (SINGLE, inst);
14450 do_vfp_sp_dyadic ();
14452 /* ARMv8.2 fp16 instruction. */
14454 do_scalar_fp16_v82_encode ();
14458 NEON_ENCODE (DOUBLE, inst);
14459 do_vfp_dp_rd_rn_rm ();
14461 do_vfp_cond_or_thumb ();
14466 do_vfp_nsyn_cmp (void)
14468 enum neon_shape rs;
14469 if (inst.operands[1].isreg)
14471 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
14472 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
14474 if (rs == NS_FF || rs == NS_HH)
14476 NEON_ENCODE (SINGLE, inst);
14477 do_vfp_sp_monadic ();
14481 NEON_ENCODE (DOUBLE, inst);
14482 do_vfp_dp_rd_rm ();
14487 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
14488 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
14490 switch (inst.instruction & 0x0fffffff)
14493 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
14496 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
14502 if (rs == NS_FI || rs == NS_HI)
14504 NEON_ENCODE (SINGLE, inst);
14505 do_vfp_sp_compare_z ();
14509 NEON_ENCODE (DOUBLE, inst);
14513 do_vfp_cond_or_thumb ();
14515 /* ARMv8.2 fp16 instruction. */
14516 if (rs == NS_HI || rs == NS_HH)
14517 do_scalar_fp16_v82_encode ();
14521 nsyn_insert_sp (void)
14523 inst.operands[1] = inst.operands[0];
14524 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
14525 inst.operands[0].reg = REG_SP;
14526 inst.operands[0].isreg = 1;
14527 inst.operands[0].writeback = 1;
14528 inst.operands[0].present = 1;
14532 do_vfp_nsyn_push (void)
14536 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
14537 _("register list must contain at least 1 and at most 16 "
14540 if (inst.operands[1].issingle)
14541 do_vfp_nsyn_opcode ("fstmdbs");
14543 do_vfp_nsyn_opcode ("fstmdbd");
14547 do_vfp_nsyn_pop (void)
14551 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
14552 _("register list must contain at least 1 and at most 16 "
14555 if (inst.operands[1].issingle)
14556 do_vfp_nsyn_opcode ("fldmias");
14558 do_vfp_nsyn_opcode ("fldmiad");
14561 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14562 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14565 neon_dp_fixup (struct arm_it* insn)
14567 unsigned int i = insn->instruction;
14572 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14583 insn->instruction = i;
14586 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14590 neon_logbits (unsigned x)
14592 return ffs (x) - 4;
14595 #define LOW4(R) ((R) & 0xf)
14596 #define HI1(R) (((R) >> 4) & 1)
14598 /* Encode insns with bit pattern:
14600 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14601 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14603 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14604 different meaning for some instruction. */
14607 neon_three_same (int isquad, int ubit, int size)
14609 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14610 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14611 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14612 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14613 inst.instruction |= LOW4 (inst.operands[2].reg);
14614 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14615 inst.instruction |= (isquad != 0) << 6;
14616 inst.instruction |= (ubit != 0) << 24;
14618 inst.instruction |= neon_logbits (size) << 20;
14620 neon_dp_fixup (&inst);
14623 /* Encode instructions of the form:
14625 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14626 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14628 Don't write size if SIZE == -1. */
14631 neon_two_same (int qbit, int ubit, int size)
14633 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14634 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14635 inst.instruction |= LOW4 (inst.operands[1].reg);
14636 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14637 inst.instruction |= (qbit != 0) << 6;
14638 inst.instruction |= (ubit != 0) << 24;
14641 inst.instruction |= neon_logbits (size) << 18;
14643 neon_dp_fixup (&inst);
14646 /* Neon instruction encoders, in approximate order of appearance. */
14649 do_neon_dyadic_i_su (void)
14651 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14652 struct neon_type_el et = neon_check_type (3, rs,
14653 N_EQK, N_EQK, N_SU_32 | N_KEY);
14654 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14658 do_neon_dyadic_i64_su (void)
14660 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14661 struct neon_type_el et = neon_check_type (3, rs,
14662 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14663 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14667 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
14670 unsigned size = et.size >> 3;
14671 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14672 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14673 inst.instruction |= LOW4 (inst.operands[1].reg);
14674 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14675 inst.instruction |= (isquad != 0) << 6;
14676 inst.instruction |= immbits << 16;
14677 inst.instruction |= (size >> 3) << 7;
14678 inst.instruction |= (size & 0x7) << 19;
14680 inst.instruction |= (uval != 0) << 24;
14682 neon_dp_fixup (&inst);
14686 do_neon_shl_imm (void)
14688 if (!inst.operands[2].isreg)
14690 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14691 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
14692 int imm = inst.operands[2].imm;
14694 constraint (imm < 0 || (unsigned)imm >= et.size,
14695 _("immediate out of range for shift"));
14696 NEON_ENCODE (IMMED, inst);
14697 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14701 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14702 struct neon_type_el et = neon_check_type (3, rs,
14703 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14706 /* VSHL/VQSHL 3-register variants have syntax such as:
14708 whereas other 3-register operations encoded by neon_three_same have
14711 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14713 tmp = inst.operands[2].reg;
14714 inst.operands[2].reg = inst.operands[1].reg;
14715 inst.operands[1].reg = tmp;
14716 NEON_ENCODE (INTEGER, inst);
14717 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14722 do_neon_qshl_imm (void)
14724 if (!inst.operands[2].isreg)
14726 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14727 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14728 int imm = inst.operands[2].imm;
14730 constraint (imm < 0 || (unsigned)imm >= et.size,
14731 _("immediate out of range for shift"));
14732 NEON_ENCODE (IMMED, inst);
14733 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
14737 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14738 struct neon_type_el et = neon_check_type (3, rs,
14739 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14742 /* See note in do_neon_shl_imm. */
14743 tmp = inst.operands[2].reg;
14744 inst.operands[2].reg = inst.operands[1].reg;
14745 inst.operands[1].reg = tmp;
14746 NEON_ENCODE (INTEGER, inst);
14747 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14752 do_neon_rshl (void)
14754 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14755 struct neon_type_el et = neon_check_type (3, rs,
14756 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14759 tmp = inst.operands[2].reg;
14760 inst.operands[2].reg = inst.operands[1].reg;
14761 inst.operands[1].reg = tmp;
14762 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14766 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14768 /* Handle .I8 pseudo-instructions. */
14771 /* Unfortunately, this will make everything apart from zero out-of-range.
14772 FIXME is this the intended semantics? There doesn't seem much point in
14773 accepting .I8 if so. */
14774 immediate |= immediate << 8;
14780 if (immediate == (immediate & 0x000000ff))
14782 *immbits = immediate;
14785 else if (immediate == (immediate & 0x0000ff00))
14787 *immbits = immediate >> 8;
14790 else if (immediate == (immediate & 0x00ff0000))
14792 *immbits = immediate >> 16;
14795 else if (immediate == (immediate & 0xff000000))
14797 *immbits = immediate >> 24;
14800 if ((immediate & 0xffff) != (immediate >> 16))
14801 goto bad_immediate;
14802 immediate &= 0xffff;
14805 if (immediate == (immediate & 0x000000ff))
14807 *immbits = immediate;
14810 else if (immediate == (immediate & 0x0000ff00))
14812 *immbits = immediate >> 8;
14817 first_error (_("immediate value out of range"));
14822 do_neon_logic (void)
14824 if (inst.operands[2].present && inst.operands[2].isreg)
14826 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14827 neon_check_type (3, rs, N_IGNORE_TYPE);
14828 /* U bit and size field were set as part of the bitmask. */
14829 NEON_ENCODE (INTEGER, inst);
14830 neon_three_same (neon_quad (rs), 0, -1);
14834 const int three_ops_form = (inst.operands[2].present
14835 && !inst.operands[2].isreg);
14836 const int immoperand = (three_ops_form ? 2 : 1);
14837 enum neon_shape rs = (three_ops_form
14838 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14839 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
14840 struct neon_type_el et = neon_check_type (2, rs,
14841 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14842 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
14846 if (et.type == NT_invtype)
14849 if (three_ops_form)
14850 constraint (inst.operands[0].reg != inst.operands[1].reg,
14851 _("first and second operands shall be the same register"));
14853 NEON_ENCODE (IMMED, inst);
14855 immbits = inst.operands[immoperand].imm;
14858 /* .i64 is a pseudo-op, so the immediate must be a repeating
14860 if (immbits != (inst.operands[immoperand].regisimm ?
14861 inst.operands[immoperand].reg : 0))
14863 /* Set immbits to an invalid constant. */
14864 immbits = 0xdeadbeef;
14871 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14875 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14879 /* Pseudo-instruction for VBIC. */
14880 neon_invert_size (&immbits, 0, et.size);
14881 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14885 /* Pseudo-instruction for VORR. */
14886 neon_invert_size (&immbits, 0, et.size);
14887 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14897 inst.instruction |= neon_quad (rs) << 6;
14898 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14899 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14900 inst.instruction |= cmode << 8;
14901 neon_write_immbits (immbits);
14903 neon_dp_fixup (&inst);
14908 do_neon_bitfield (void)
14910 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14911 neon_check_type (3, rs, N_IGNORE_TYPE);
14912 neon_three_same (neon_quad (rs), 0, -1);
14916 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
14919 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14920 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
14922 if (et.type == NT_float)
14924 NEON_ENCODE (FLOAT, inst);
14925 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
14929 NEON_ENCODE (INTEGER, inst);
14930 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
14935 do_neon_dyadic_if_su (void)
14937 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14941 do_neon_dyadic_if_su_d (void)
14943 /* This version only allow D registers, but that constraint is enforced during
14944 operand parsing so we don't need to do anything extra here. */
14945 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14949 do_neon_dyadic_if_i_d (void)
14951 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14952 affected if we specify unsigned args. */
14953 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14956 enum vfp_or_neon_is_neon_bits
14959 NEON_CHECK_ARCH = 2,
14960 NEON_CHECK_ARCH8 = 4
14963 /* Call this function if an instruction which may have belonged to the VFP or
14964 Neon instruction sets, but turned out to be a Neon instruction (due to the
14965 operand types involved, etc.). We have to check and/or fix-up a couple of
14968 - Make sure the user hasn't attempted to make a Neon instruction
14970 - Alter the value in the condition code field if necessary.
14971 - Make sure that the arch supports Neon instructions.
14973 Which of these operations take place depends on bits from enum
14974 vfp_or_neon_is_neon_bits.
14976 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14977 current instruction's condition is COND_ALWAYS, the condition field is
14978 changed to inst.uncond_value. This is necessary because instructions shared
14979 between VFP and Neon may be conditional for the VFP variants only, and the
14980 unconditional Neon version must have, e.g., 0xF in the condition field. */
14983 vfp_or_neon_is_neon (unsigned check)
14985 /* Conditions are always legal in Thumb mode (IT blocks). */
14986 if (!thumb_mode && (check & NEON_CHECK_CC))
14988 if (inst.cond != COND_ALWAYS)
14990 first_error (_(BAD_COND));
14993 if (inst.uncond_value != -1)
14994 inst.instruction |= inst.uncond_value << 28;
14997 if ((check & NEON_CHECK_ARCH)
14998 && !mark_feature_used (&fpu_neon_ext_v1))
15000 first_error (_(BAD_FPU));
15004 if ((check & NEON_CHECK_ARCH8)
15005 && !mark_feature_used (&fpu_neon_ext_armv8))
15007 first_error (_(BAD_FPU));
15015 do_neon_addsub_if_i (void)
15017 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
15020 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15023 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15024 affected if we specify unsigned args. */
15025 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
15028 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15030 V<op> A,B (A is operand 0, B is operand 2)
15035 so handle that case specially. */
15038 neon_exchange_operands (void)
15040 if (inst.operands[1].present)
15042 void *scratch = xmalloc (sizeof (inst.operands[0]));
15044 /* Swap operands[1] and operands[2]. */
15045 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
15046 inst.operands[1] = inst.operands[2];
15047 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
15052 inst.operands[1] = inst.operands[2];
15053 inst.operands[2] = inst.operands[0];
15058 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
15060 if (inst.operands[2].isreg)
15063 neon_exchange_operands ();
15064 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
15068 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15069 struct neon_type_el et = neon_check_type (2, rs,
15070 N_EQK | N_SIZ, immtypes | N_KEY);
15072 NEON_ENCODE (IMMED, inst);
15073 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15074 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15075 inst.instruction |= LOW4 (inst.operands[1].reg);
15076 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15077 inst.instruction |= neon_quad (rs) << 6;
15078 inst.instruction |= (et.type == NT_float) << 10;
15079 inst.instruction |= neon_logbits (et.size) << 18;
15081 neon_dp_fixup (&inst);
15088 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
15092 do_neon_cmp_inv (void)
15094 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
15100 neon_compare (N_IF_32, N_IF_32, FALSE);
15103 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15104 scalars, which are encoded in 5 bits, M : Rm.
15105 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15106 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15109 Dot Product instructions are similar to multiply instructions except elsize
15110 should always be 32.
15112 This function translates SCALAR, which is GAS's internal encoding of indexed
15113 scalar register, to raw encoding. There is also register and index range
15114 check based on ELSIZE. */
15117 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
15119 unsigned regno = NEON_SCALAR_REG (scalar);
15120 unsigned elno = NEON_SCALAR_INDEX (scalar);
15125 if (regno > 7 || elno > 3)
15127 return regno | (elno << 3);
15130 if (regno > 15 || elno > 1)
15132 return regno | (elno << 4);
15136 first_error (_("scalar out of range for multiply instruction"));
15142 /* Encode multiply / multiply-accumulate scalar instructions. */
15145 neon_mul_mac (struct neon_type_el et, int ubit)
15149 /* Give a more helpful error message if we have an invalid type. */
15150 if (et.type == NT_invtype)
15153 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
15154 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15155 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15156 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15157 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15158 inst.instruction |= LOW4 (scalar);
15159 inst.instruction |= HI1 (scalar) << 5;
15160 inst.instruction |= (et.type == NT_float) << 8;
15161 inst.instruction |= neon_logbits (et.size) << 20;
15162 inst.instruction |= (ubit != 0) << 24;
15164 neon_dp_fixup (&inst);
15168 do_neon_mac_maybe_scalar (void)
15170 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
15173 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15176 if (inst.operands[2].isscalar)
15178 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15179 struct neon_type_el et = neon_check_type (3, rs,
15180 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
15181 NEON_ENCODE (SCALAR, inst);
15182 neon_mul_mac (et, neon_quad (rs));
15186 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15187 affected if we specify unsigned args. */
15188 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15193 do_neon_fmac (void)
15195 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
15198 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15201 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
15207 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15208 struct neon_type_el et = neon_check_type (3, rs,
15209 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
15210 neon_three_same (neon_quad (rs), 0, et.size);
15213 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15214 same types as the MAC equivalents. The polynomial type for this instruction
15215 is encoded the same as the integer type. */
15220 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
15223 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15226 if (inst.operands[2].isscalar)
15227 do_neon_mac_maybe_scalar ();
15229 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
15233 do_neon_qdmulh (void)
15235 if (inst.operands[2].isscalar)
15237 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15238 struct neon_type_el et = neon_check_type (3, rs,
15239 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15240 NEON_ENCODE (SCALAR, inst);
15241 neon_mul_mac (et, neon_quad (rs));
15245 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15246 struct neon_type_el et = neon_check_type (3, rs,
15247 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15248 NEON_ENCODE (INTEGER, inst);
15249 /* The U bit (rounding) comes from bit mask. */
15250 neon_three_same (neon_quad (rs), 0, et.size);
15255 do_neon_qrdmlah (void)
15257 /* Check we're on the correct architecture. */
15258 if (!mark_feature_used (&fpu_neon_ext_armv8))
15260 _("instruction form not available on this architecture.");
15261 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
15263 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15264 record_feature_use (&fpu_neon_ext_v8_1);
15267 if (inst.operands[2].isscalar)
15269 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
15270 struct neon_type_el et = neon_check_type (3, rs,
15271 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15272 NEON_ENCODE (SCALAR, inst);
15273 neon_mul_mac (et, neon_quad (rs));
15277 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15278 struct neon_type_el et = neon_check_type (3, rs,
15279 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
15280 NEON_ENCODE (INTEGER, inst);
15281 /* The U bit (rounding) comes from bit mask. */
15282 neon_three_same (neon_quad (rs), 0, et.size);
15287 do_neon_fcmp_absolute (void)
15289 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15290 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15291 N_F_16_32 | N_KEY);
15292 /* Size field comes from bit mask. */
15293 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
15297 do_neon_fcmp_absolute_inv (void)
15299 neon_exchange_operands ();
15300 do_neon_fcmp_absolute ();
15304 do_neon_step (void)
15306 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
15307 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
15308 N_F_16_32 | N_KEY);
15309 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
15313 do_neon_abs_neg (void)
15315 enum neon_shape rs;
15316 struct neon_type_el et;
15318 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
15321 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15324 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15325 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
15327 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15328 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15329 inst.instruction |= LOW4 (inst.operands[1].reg);
15330 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15331 inst.instruction |= neon_quad (rs) << 6;
15332 inst.instruction |= (et.type == NT_float) << 10;
15333 inst.instruction |= neon_logbits (et.size) << 18;
15335 neon_dp_fixup (&inst);
15341 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15342 struct neon_type_el et = neon_check_type (2, rs,
15343 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15344 int imm = inst.operands[2].imm;
15345 constraint (imm < 0 || (unsigned)imm >= et.size,
15346 _("immediate out of range for insert"));
15347 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15353 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15354 struct neon_type_el et = neon_check_type (2, rs,
15355 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15356 int imm = inst.operands[2].imm;
15357 constraint (imm < 1 || (unsigned)imm > et.size,
15358 _("immediate out of range for insert"));
15359 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
15363 do_neon_qshlu_imm (void)
15365 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15366 struct neon_type_el et = neon_check_type (2, rs,
15367 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
15368 int imm = inst.operands[2].imm;
15369 constraint (imm < 0 || (unsigned)imm >= et.size,
15370 _("immediate out of range for shift"));
15371 /* Only encodes the 'U present' variant of the instruction.
15372 In this case, signed types have OP (bit 8) set to 0.
15373 Unsigned types have OP set to 1. */
15374 inst.instruction |= (et.type == NT_unsigned) << 8;
15375 /* The rest of the bits are the same as other immediate shifts. */
15376 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
15380 do_neon_qmovn (void)
15382 struct neon_type_el et = neon_check_type (2, NS_DQ,
15383 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15384 /* Saturating move where operands can be signed or unsigned, and the
15385 destination has the same signedness. */
15386 NEON_ENCODE (INTEGER, inst);
15387 if (et.type == NT_unsigned)
15388 inst.instruction |= 0xc0;
15390 inst.instruction |= 0x80;
15391 neon_two_same (0, 1, et.size / 2);
15395 do_neon_qmovun (void)
15397 struct neon_type_el et = neon_check_type (2, NS_DQ,
15398 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15399 /* Saturating move with unsigned results. Operands must be signed. */
15400 NEON_ENCODE (INTEGER, inst);
15401 neon_two_same (0, 1, et.size / 2);
15405 do_neon_rshift_sat_narrow (void)
15407 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15408 or unsigned. If operands are unsigned, results must also be unsigned. */
15409 struct neon_type_el et = neon_check_type (2, NS_DQI,
15410 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
15411 int imm = inst.operands[2].imm;
15412 /* This gets the bounds check, size encoding and immediate bits calculation
15416 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15417 VQMOVN.I<size> <Dd>, <Qm>. */
15420 inst.operands[2].present = 0;
15421 inst.instruction = N_MNEM_vqmovn;
15426 constraint (imm < 1 || (unsigned)imm > et.size,
15427 _("immediate out of range"));
15428 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
15432 do_neon_rshift_sat_narrow_u (void)
15434 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15435 or unsigned. If operands are unsigned, results must also be unsigned. */
15436 struct neon_type_el et = neon_check_type (2, NS_DQI,
15437 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
15438 int imm = inst.operands[2].imm;
15439 /* This gets the bounds check, size encoding and immediate bits calculation
15443 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15444 VQMOVUN.I<size> <Dd>, <Qm>. */
15447 inst.operands[2].present = 0;
15448 inst.instruction = N_MNEM_vqmovun;
15453 constraint (imm < 1 || (unsigned)imm > et.size,
15454 _("immediate out of range"));
15455 /* FIXME: The manual is kind of unclear about what value U should have in
15456 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15458 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
15462 do_neon_movn (void)
15464 struct neon_type_el et = neon_check_type (2, NS_DQ,
15465 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15466 NEON_ENCODE (INTEGER, inst);
15467 neon_two_same (0, 1, et.size / 2);
15471 do_neon_rshift_narrow (void)
15473 struct neon_type_el et = neon_check_type (2, NS_DQI,
15474 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
15475 int imm = inst.operands[2].imm;
15476 /* This gets the bounds check, size encoding and immediate bits calculation
15480 /* If immediate is zero then we are a pseudo-instruction for
15481 VMOVN.I<size> <Dd>, <Qm> */
15484 inst.operands[2].present = 0;
15485 inst.instruction = N_MNEM_vmovn;
15490 constraint (imm < 1 || (unsigned)imm > et.size,
15491 _("immediate out of range for narrowing operation"));
15492 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
15496 do_neon_shll (void)
15498 /* FIXME: Type checking when lengthening. */
15499 struct neon_type_el et = neon_check_type (2, NS_QDI,
15500 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
15501 unsigned imm = inst.operands[2].imm;
15503 if (imm == et.size)
15505 /* Maximum shift variant. */
15506 NEON_ENCODE (INTEGER, inst);
15507 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15508 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15509 inst.instruction |= LOW4 (inst.operands[1].reg);
15510 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15511 inst.instruction |= neon_logbits (et.size) << 18;
15513 neon_dp_fixup (&inst);
15517 /* A more-specific type check for non-max versions. */
15518 et = neon_check_type (2, NS_QDI,
15519 N_EQK | N_DBL, N_SU_32 | N_KEY);
15520 NEON_ENCODE (IMMED, inst);
15521 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
15525 /* Check the various types for the VCVT instruction, and return which version
15526 the current instruction is. */
15528 #define CVT_FLAVOUR_VAR \
15529 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15530 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15531 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15532 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15533 /* Half-precision conversions. */ \
15534 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15535 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15536 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15537 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15538 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15539 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15540 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15541 Compared with single/double precision variants, only the co-processor \
15542 field is different, so the encoding flow is reused here. */ \
15543 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15544 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15545 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15546 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15547 /* VFP instructions. */ \
15548 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15549 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15550 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15551 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15552 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15553 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15554 /* VFP instructions with bitshift. */ \
15555 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15556 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15557 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15558 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15559 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15560 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15561 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15562 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15564 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15565 neon_cvt_flavour_##C,
15567 /* The different types of conversions we can do. */
15568 enum neon_cvt_flavour
15571 neon_cvt_flavour_invalid,
15572 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
15577 static enum neon_cvt_flavour
15578 get_neon_cvt_flavour (enum neon_shape rs)
15580 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15581 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15582 if (et.type != NT_invtype) \
15584 inst.error = NULL; \
15585 return (neon_cvt_flavour_##C); \
15588 struct neon_type_el et;
15589 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
15590 || rs == NS_FF) ? N_VFP : 0;
15591 /* The instruction versions which take an immediate take one register
15592 argument, which is extended to the width of the full register. Thus the
15593 "source" and "destination" registers must have the same width. Hack that
15594 here by making the size equal to the key (wider, in this case) operand. */
15595 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
15599 return neon_cvt_flavour_invalid;
15614 /* Neon-syntax VFP conversions. */
15617 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
15619 const char *opname = 0;
15621 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
15622 || rs == NS_FHI || rs == NS_HFI)
15624 /* Conversions with immediate bitshift. */
15625 const char *enc[] =
15627 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15633 if (flavour < (int) ARRAY_SIZE (enc))
15635 opname = enc[flavour];
15636 constraint (inst.operands[0].reg != inst.operands[1].reg,
15637 _("operands 0 and 1 must be the same register"));
15638 inst.operands[1] = inst.operands[2];
15639 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
15644 /* Conversions without bitshift. */
15645 const char *enc[] =
15647 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15653 if (flavour < (int) ARRAY_SIZE (enc))
15654 opname = enc[flavour];
15658 do_vfp_nsyn_opcode (opname);
15660 /* ARMv8.2 fp16 VCVT instruction. */
15661 if (flavour == neon_cvt_flavour_s32_f16
15662 || flavour == neon_cvt_flavour_u32_f16
15663 || flavour == neon_cvt_flavour_f16_u32
15664 || flavour == neon_cvt_flavour_f16_s32)
15665 do_scalar_fp16_v82_encode ();
15669 do_vfp_nsyn_cvtz (void)
15671 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
15672 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15673 const char *enc[] =
15675 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15681 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
15682 do_vfp_nsyn_opcode (enc[flavour]);
15686 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
15687 enum neon_cvt_mode mode)
15692 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15693 D register operands. */
15694 if (flavour == neon_cvt_flavour_s32_f64
15695 || flavour == neon_cvt_flavour_u32_f64)
15696 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15699 if (flavour == neon_cvt_flavour_s32_f16
15700 || flavour == neon_cvt_flavour_u32_f16)
15701 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
15704 set_it_insn_type (OUTSIDE_IT_INSN);
15708 case neon_cvt_flavour_s32_f64:
15712 case neon_cvt_flavour_s32_f32:
15716 case neon_cvt_flavour_s32_f16:
15720 case neon_cvt_flavour_u32_f64:
15724 case neon_cvt_flavour_u32_f32:
15728 case neon_cvt_flavour_u32_f16:
15733 first_error (_("invalid instruction shape"));
15739 case neon_cvt_mode_a: rm = 0; break;
15740 case neon_cvt_mode_n: rm = 1; break;
15741 case neon_cvt_mode_p: rm = 2; break;
15742 case neon_cvt_mode_m: rm = 3; break;
15743 default: first_error (_("invalid rounding mode")); return;
15746 NEON_ENCODE (FPV8, inst);
15747 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15748 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15749 inst.instruction |= sz << 8;
15751 /* ARMv8.2 fp16 VCVT instruction. */
15752 if (flavour == neon_cvt_flavour_s32_f16
15753 ||flavour == neon_cvt_flavour_u32_f16)
15754 do_scalar_fp16_v82_encode ();
15755 inst.instruction |= op << 7;
15756 inst.instruction |= rm << 16;
15757 inst.instruction |= 0xf0000000;
15758 inst.is_neon = TRUE;
15762 do_neon_cvt_1 (enum neon_cvt_mode mode)
15764 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
15765 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
15766 NS_FH, NS_HF, NS_FHI, NS_HFI,
15768 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15770 if (flavour == neon_cvt_flavour_invalid)
15773 /* PR11109: Handle round-to-zero for VCVT conversions. */
15774 if (mode == neon_cvt_mode_z
15775 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
15776 && (flavour == neon_cvt_flavour_s16_f16
15777 || flavour == neon_cvt_flavour_u16_f16
15778 || flavour == neon_cvt_flavour_s32_f32
15779 || flavour == neon_cvt_flavour_u32_f32
15780 || flavour == neon_cvt_flavour_s32_f64
15781 || flavour == neon_cvt_flavour_u32_f64)
15782 && (rs == NS_FD || rs == NS_FF))
15784 do_vfp_nsyn_cvtz ();
15788 /* ARMv8.2 fp16 VCVT conversions. */
15789 if (mode == neon_cvt_mode_z
15790 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
15791 && (flavour == neon_cvt_flavour_s32_f16
15792 || flavour == neon_cvt_flavour_u32_f16)
15795 do_vfp_nsyn_cvtz ();
15796 do_scalar_fp16_v82_encode ();
15800 /* VFP rather than Neon conversions. */
15801 if (flavour >= neon_cvt_flavour_first_fp)
15803 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15804 do_vfp_nsyn_cvt (rs, flavour);
15806 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15817 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15818 0x0000100, 0x1000100, 0x0, 0x1000000};
15820 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15823 /* Fixed-point conversion with #0 immediate is encoded as an
15824 integer conversion. */
15825 if (inst.operands[2].present && inst.operands[2].imm == 0)
15827 NEON_ENCODE (IMMED, inst);
15828 if (flavour != neon_cvt_flavour_invalid)
15829 inst.instruction |= enctab[flavour];
15830 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15831 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15832 inst.instruction |= LOW4 (inst.operands[1].reg);
15833 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15834 inst.instruction |= neon_quad (rs) << 6;
15835 inst.instruction |= 1 << 21;
15836 if (flavour < neon_cvt_flavour_s16_f16)
15838 inst.instruction |= 1 << 21;
15839 immbits = 32 - inst.operands[2].imm;
15840 inst.instruction |= immbits << 16;
15844 inst.instruction |= 3 << 20;
15845 immbits = 16 - inst.operands[2].imm;
15846 inst.instruction |= immbits << 16;
15847 inst.instruction &= ~(1 << 9);
15850 neon_dp_fixup (&inst);
15856 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15858 NEON_ENCODE (FLOAT, inst);
15859 set_it_insn_type (OUTSIDE_IT_INSN);
15861 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15864 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15865 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15866 inst.instruction |= LOW4 (inst.operands[1].reg);
15867 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15868 inst.instruction |= neon_quad (rs) << 6;
15869 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
15870 || flavour == neon_cvt_flavour_u32_f32) << 7;
15871 inst.instruction |= mode << 8;
15872 if (flavour == neon_cvt_flavour_u16_f16
15873 || flavour == neon_cvt_flavour_s16_f16)
15874 /* Mask off the original size bits and reencode them. */
15875 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
15878 inst.instruction |= 0xfc000000;
15880 inst.instruction |= 0xf0000000;
15886 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
15887 0x100, 0x180, 0x0, 0x080};
15889 NEON_ENCODE (INTEGER, inst);
15891 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15894 if (flavour != neon_cvt_flavour_invalid)
15895 inst.instruction |= enctab[flavour];
15897 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15898 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15899 inst.instruction |= LOW4 (inst.operands[1].reg);
15900 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15901 inst.instruction |= neon_quad (rs) << 6;
15902 if (flavour >= neon_cvt_flavour_s16_f16
15903 && flavour <= neon_cvt_flavour_f16_u16)
15904 /* Half precision. */
15905 inst.instruction |= 1 << 18;
15907 inst.instruction |= 2 << 18;
15909 neon_dp_fixup (&inst);
15914 /* Half-precision conversions for Advanced SIMD -- neon. */
15917 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15921 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15923 as_bad (_("operand size must match register width"));
15928 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15930 as_bad (_("operand size must match register width"));
15935 inst.instruction = 0x3b60600;
15937 inst.instruction = 0x3b60700;
15939 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15940 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15941 inst.instruction |= LOW4 (inst.operands[1].reg);
15942 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15943 neon_dp_fixup (&inst);
15947 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15948 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15949 do_vfp_nsyn_cvt (rs, flavour);
15951 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15956 do_neon_cvtr (void)
15958 do_neon_cvt_1 (neon_cvt_mode_x);
15964 do_neon_cvt_1 (neon_cvt_mode_z);
15968 do_neon_cvta (void)
15970 do_neon_cvt_1 (neon_cvt_mode_a);
15974 do_neon_cvtn (void)
15976 do_neon_cvt_1 (neon_cvt_mode_n);
15980 do_neon_cvtp (void)
15982 do_neon_cvt_1 (neon_cvt_mode_p);
15986 do_neon_cvtm (void)
15988 do_neon_cvt_1 (neon_cvt_mode_m);
15992 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
15995 mark_feature_used (&fpu_vfp_ext_armv8);
15997 encode_arm_vfp_reg (inst.operands[0].reg,
15998 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15999 encode_arm_vfp_reg (inst.operands[1].reg,
16000 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
16001 inst.instruction |= to ? 0x10000 : 0;
16002 inst.instruction |= t ? 0x80 : 0;
16003 inst.instruction |= is_double ? 0x100 : 0;
16004 do_vfp_cond_or_thumb ();
16008 do_neon_cvttb_1 (bfd_boolean t)
16010 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
16011 NS_DF, NS_DH, NS_NULL);
16015 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
16018 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
16020 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
16023 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
16025 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
16027 /* The VCVTB and VCVTT instructions with D-register operands
16028 don't work for SP only targets. */
16029 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16033 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
16035 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
16037 /* The VCVTB and VCVTT instructions with D-register operands
16038 don't work for SP only targets. */
16039 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16043 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
16050 do_neon_cvtb (void)
16052 do_neon_cvttb_1 (FALSE);
16057 do_neon_cvtt (void)
16059 do_neon_cvttb_1 (TRUE);
16063 neon_move_immediate (void)
16065 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
16066 struct neon_type_el et = neon_check_type (2, rs,
16067 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
16068 unsigned immlo, immhi = 0, immbits;
16069 int op, cmode, float_p;
16071 constraint (et.type == NT_invtype,
16072 _("operand size must be specified for immediate VMOV"));
16074 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16075 op = (inst.instruction & (1 << 5)) != 0;
16077 immlo = inst.operands[1].imm;
16078 if (inst.operands[1].regisimm)
16079 immhi = inst.operands[1].reg;
16081 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
16082 _("immediate has bits set outside the operand size"));
16084 float_p = inst.operands[1].immisfloat;
16086 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
16087 et.size, et.type)) == FAIL)
16089 /* Invert relevant bits only. */
16090 neon_invert_size (&immlo, &immhi, et.size);
16091 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16092 with one or the other; those cases are caught by
16093 neon_cmode_for_move_imm. */
16095 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
16096 &op, et.size, et.type)) == FAIL)
16098 first_error (_("immediate out of range"));
16103 inst.instruction &= ~(1 << 5);
16104 inst.instruction |= op << 5;
16106 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16107 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16108 inst.instruction |= neon_quad (rs) << 6;
16109 inst.instruction |= cmode << 8;
16111 neon_write_immbits (immbits);
16117 if (inst.operands[1].isreg)
16119 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16121 NEON_ENCODE (INTEGER, inst);
16122 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16123 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16124 inst.instruction |= LOW4 (inst.operands[1].reg);
16125 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16126 inst.instruction |= neon_quad (rs) << 6;
16130 NEON_ENCODE (IMMED, inst);
16131 neon_move_immediate ();
16134 neon_dp_fixup (&inst);
16137 /* Encode instructions of form:
16139 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16140 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16143 neon_mixed_length (struct neon_type_el et, unsigned size)
16145 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16146 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16147 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16148 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16149 inst.instruction |= LOW4 (inst.operands[2].reg);
16150 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16151 inst.instruction |= (et.type == NT_unsigned) << 24;
16152 inst.instruction |= neon_logbits (size) << 20;
16154 neon_dp_fixup (&inst);
16158 do_neon_dyadic_long (void)
16160 /* FIXME: Type checking for lengthening op. */
16161 struct neon_type_el et = neon_check_type (3, NS_QDD,
16162 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
16163 neon_mixed_length (et, et.size);
16167 do_neon_abal (void)
16169 struct neon_type_el et = neon_check_type (3, NS_QDD,
16170 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
16171 neon_mixed_length (et, et.size);
16175 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
16177 if (inst.operands[2].isscalar)
16179 struct neon_type_el et = neon_check_type (3, NS_QDS,
16180 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
16181 NEON_ENCODE (SCALAR, inst);
16182 neon_mul_mac (et, et.type == NT_unsigned);
16186 struct neon_type_el et = neon_check_type (3, NS_QDD,
16187 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
16188 NEON_ENCODE (INTEGER, inst);
16189 neon_mixed_length (et, et.size);
16194 do_neon_mac_maybe_scalar_long (void)
16196 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
16199 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16200 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16203 neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
16205 unsigned regno = NEON_SCALAR_REG (scalar);
16206 unsigned elno = NEON_SCALAR_INDEX (scalar);
16210 if (regno > 7 || elno > 3)
16213 return ((regno & 0x7)
16214 | ((elno & 0x1) << 3)
16215 | (((elno >> 1) & 0x1) << 5));
16219 if (regno > 15 || elno > 1)
16222 return (((regno & 0x1) << 5)
16223 | ((regno >> 1) & 0x7)
16224 | ((elno & 0x1) << 3));
16228 first_error (_("scalar out of range for multiply instruction"));
16233 do_neon_fmac_maybe_scalar_long (int subtype)
16235 enum neon_shape rs;
16237 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16238 field (bits[21:20]) has different meaning. For scalar index variant, it's
16239 used to differentiate add and subtract, otherwise it's with fixed value
16243 if (inst.cond != COND_ALWAYS)
16244 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16245 "behaviour is UNPREDICTABLE"));
16247 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
16250 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
16253 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16254 be a scalar index register. */
16255 if (inst.operands[2].isscalar)
16257 high8 = 0xfe000000;
16260 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
16264 high8 = 0xfc000000;
16267 inst.instruction |= (0x1 << 23);
16268 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
16271 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
16273 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16274 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16275 so we simply pass -1 as size. */
16276 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
16277 neon_three_same (quad_p, 0, size);
16279 /* Undo neon_dp_fixup. Redo the high eight bits. */
16280 inst.instruction &= 0x00ffffff;
16281 inst.instruction |= high8;
16283 #define LOW1(R) ((R) & 0x1)
16284 #define HI4(R) (((R) >> 1) & 0xf)
16285 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16286 whether the instruction is in Q form and whether Vm is a scalar indexed
16288 if (inst.operands[2].isscalar)
16291 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
16292 inst.instruction &= 0xffffffd0;
16293 inst.instruction |= rm;
16297 /* Redo Rn as well. */
16298 inst.instruction &= 0xfff0ff7f;
16299 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
16300 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
16305 /* Redo Rn and Rm. */
16306 inst.instruction &= 0xfff0ff50;
16307 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
16308 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
16309 inst.instruction |= HI4 (inst.operands[2].reg);
16310 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
16315 do_neon_vfmal (void)
16317 return do_neon_fmac_maybe_scalar_long (0);
16321 do_neon_vfmsl (void)
16323 return do_neon_fmac_maybe_scalar_long (1);
16327 do_neon_dyadic_wide (void)
16329 struct neon_type_el et = neon_check_type (3, NS_QQD,
16330 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
16331 neon_mixed_length (et, et.size);
16335 do_neon_dyadic_narrow (void)
16337 struct neon_type_el et = neon_check_type (3, NS_QDD,
16338 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
16339 /* Operand sign is unimportant, and the U bit is part of the opcode,
16340 so force the operand type to integer. */
16341 et.type = NT_integer;
16342 neon_mixed_length (et, et.size / 2);
16346 do_neon_mul_sat_scalar_long (void)
16348 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
16352 do_neon_vmull (void)
16354 if (inst.operands[2].isscalar)
16355 do_neon_mac_maybe_scalar_long ();
16358 struct neon_type_el et = neon_check_type (3, NS_QDD,
16359 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
16361 if (et.type == NT_poly)
16362 NEON_ENCODE (POLY, inst);
16364 NEON_ENCODE (INTEGER, inst);
16366 /* For polynomial encoding the U bit must be zero, and the size must
16367 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16368 obviously, as 0b10). */
16371 /* Check we're on the correct architecture. */
16372 if (!mark_feature_used (&fpu_crypto_ext_armv8))
16374 _("Instruction form not available on this architecture.");
16379 neon_mixed_length (et, et.size);
16386 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
16387 struct neon_type_el et = neon_check_type (3, rs,
16388 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16389 unsigned imm = (inst.operands[3].imm * et.size) / 8;
16391 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
16392 _("shift out of range"));
16393 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16394 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16395 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16396 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16397 inst.instruction |= LOW4 (inst.operands[2].reg);
16398 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16399 inst.instruction |= neon_quad (rs) << 6;
16400 inst.instruction |= imm << 8;
16402 neon_dp_fixup (&inst);
16408 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16409 struct neon_type_el et = neon_check_type (2, rs,
16410 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16411 unsigned op = (inst.instruction >> 7) & 3;
16412 /* N (width of reversed regions) is encoded as part of the bitmask. We
16413 extract it here to check the elements to be reversed are smaller.
16414 Otherwise we'd get a reserved instruction. */
16415 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
16416 gas_assert (elsize != 0);
16417 constraint (et.size >= elsize,
16418 _("elements must be smaller than reversal region"));
16419 neon_two_same (neon_quad (rs), 1, et.size);
16425 if (inst.operands[1].isscalar)
16427 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
16428 struct neon_type_el et = neon_check_type (2, rs,
16429 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16430 unsigned sizebits = et.size >> 3;
16431 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
16432 int logsize = neon_logbits (et.size);
16433 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
16435 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
16438 NEON_ENCODE (SCALAR, inst);
16439 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16440 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16441 inst.instruction |= LOW4 (dm);
16442 inst.instruction |= HI1 (dm) << 5;
16443 inst.instruction |= neon_quad (rs) << 6;
16444 inst.instruction |= x << 17;
16445 inst.instruction |= sizebits << 16;
16447 neon_dp_fixup (&inst);
16451 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
16452 struct neon_type_el et = neon_check_type (2, rs,
16453 N_8 | N_16 | N_32 | N_KEY, N_EQK);
16454 /* Duplicate ARM register to lanes of vector. */
16455 NEON_ENCODE (ARMREG, inst);
16458 case 8: inst.instruction |= 0x400000; break;
16459 case 16: inst.instruction |= 0x000020; break;
16460 case 32: inst.instruction |= 0x000000; break;
16463 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16464 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
16465 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
16466 inst.instruction |= neon_quad (rs) << 21;
16467 /* The encoding for this instruction is identical for the ARM and Thumb
16468 variants, except for the condition field. */
16469 do_vfp_cond_or_thumb ();
16473 /* VMOV has particularly many variations. It can be one of:
16474 0. VMOV<c><q> <Qd>, <Qm>
16475 1. VMOV<c><q> <Dd>, <Dm>
16476 (Register operations, which are VORR with Rm = Rn.)
16477 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16478 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16480 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16481 (ARM register to scalar.)
16482 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16483 (Two ARM registers to vector.)
16484 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16485 (Scalar to ARM register.)
16486 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16487 (Vector to two ARM registers.)
16488 8. VMOV.F32 <Sd>, <Sm>
16489 9. VMOV.F64 <Dd>, <Dm>
16490 (VFP register moves.)
16491 10. VMOV.F32 <Sd>, #imm
16492 11. VMOV.F64 <Dd>, #imm
16493 (VFP float immediate load.)
16494 12. VMOV <Rd>, <Sm>
16495 (VFP single to ARM reg.)
16496 13. VMOV <Sd>, <Rm>
16497 (ARM reg to VFP single.)
16498 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16499 (Two ARM regs to two VFP singles.)
16500 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16501 (Two VFP singles to two ARM regs.)
16503 These cases can be disambiguated using neon_select_shape, except cases 1/9
16504 and 3/11 which depend on the operand type too.
16506 All the encoded bits are hardcoded by this function.
16508 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16509 Cases 5, 7 may be used with VFPv2 and above.
16511 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16512 can specify a type where it doesn't make sense to, and is ignored). */
16517 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
16518 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR,
16519 NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
16520 NS_HR, NS_RH, NS_HI, NS_NULL);
16521 struct neon_type_el et;
16522 const char *ldconst = 0;
16526 case NS_DD: /* case 1/9. */
16527 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16528 /* It is not an error here if no type is given. */
16530 if (et.type == NT_float && et.size == 64)
16532 do_vfp_nsyn_opcode ("fcpyd");
16535 /* fall through. */
16537 case NS_QQ: /* case 0/1. */
16539 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16541 /* The architecture manual I have doesn't explicitly state which
16542 value the U bit should have for register->register moves, but
16543 the equivalent VORR instruction has U = 0, so do that. */
16544 inst.instruction = 0x0200110;
16545 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16546 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16547 inst.instruction |= LOW4 (inst.operands[1].reg);
16548 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16549 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16550 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16551 inst.instruction |= neon_quad (rs) << 6;
16553 neon_dp_fixup (&inst);
16557 case NS_DI: /* case 3/11. */
16558 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
16560 if (et.type == NT_float && et.size == 64)
16562 /* case 11 (fconstd). */
16563 ldconst = "fconstd";
16564 goto encode_fconstd;
16566 /* fall through. */
16568 case NS_QI: /* case 2/3. */
16569 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
16571 inst.instruction = 0x0800010;
16572 neon_move_immediate ();
16573 neon_dp_fixup (&inst);
16576 case NS_SR: /* case 4. */
16578 unsigned bcdebits = 0;
16580 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
16581 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
16583 /* .<size> is optional here, defaulting to .32. */
16584 if (inst.vectype.elems == 0
16585 && inst.operands[0].vectype.type == NT_invtype
16586 && inst.operands[1].vectype.type == NT_invtype)
16588 inst.vectype.el[0].type = NT_untyped;
16589 inst.vectype.el[0].size = 32;
16590 inst.vectype.elems = 1;
16593 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
16594 logsize = neon_logbits (et.size);
16596 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16598 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16599 && et.size != 32, _(BAD_FPU));
16600 constraint (et.type == NT_invtype, _("bad type for scalar"));
16601 constraint (x >= 64 / et.size, _("scalar index out of range"));
16605 case 8: bcdebits = 0x8; break;
16606 case 16: bcdebits = 0x1; break;
16607 case 32: bcdebits = 0x0; break;
16611 bcdebits |= x << logsize;
16613 inst.instruction = 0xe000b10;
16614 do_vfp_cond_or_thumb ();
16615 inst.instruction |= LOW4 (dn) << 16;
16616 inst.instruction |= HI1 (dn) << 7;
16617 inst.instruction |= inst.operands[1].reg << 12;
16618 inst.instruction |= (bcdebits & 3) << 5;
16619 inst.instruction |= (bcdebits >> 2) << 21;
16623 case NS_DRR: /* case 5 (fmdrr). */
16624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16627 inst.instruction = 0xc400b10;
16628 do_vfp_cond_or_thumb ();
16629 inst.instruction |= LOW4 (inst.operands[0].reg);
16630 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
16631 inst.instruction |= inst.operands[1].reg << 12;
16632 inst.instruction |= inst.operands[2].reg << 16;
16635 case NS_RS: /* case 6. */
16638 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
16639 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
16640 unsigned abcdebits = 0;
16642 /* .<dt> is optional here, defaulting to .32. */
16643 if (inst.vectype.elems == 0
16644 && inst.operands[0].vectype.type == NT_invtype
16645 && inst.operands[1].vectype.type == NT_invtype)
16647 inst.vectype.el[0].type = NT_untyped;
16648 inst.vectype.el[0].size = 32;
16649 inst.vectype.elems = 1;
16652 et = neon_check_type (2, NS_NULL,
16653 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
16654 logsize = neon_logbits (et.size);
16656 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
16658 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
16659 && et.size != 32, _(BAD_FPU));
16660 constraint (et.type == NT_invtype, _("bad type for scalar"));
16661 constraint (x >= 64 / et.size, _("scalar index out of range"));
16665 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
16666 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
16667 case 32: abcdebits = 0x00; break;
16671 abcdebits |= x << logsize;
16672 inst.instruction = 0xe100b10;
16673 do_vfp_cond_or_thumb ();
16674 inst.instruction |= LOW4 (dn) << 16;
16675 inst.instruction |= HI1 (dn) << 7;
16676 inst.instruction |= inst.operands[0].reg << 12;
16677 inst.instruction |= (abcdebits & 3) << 5;
16678 inst.instruction |= (abcdebits >> 2) << 21;
16682 case NS_RRD: /* case 7 (fmrrd). */
16683 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
16686 inst.instruction = 0xc500b10;
16687 do_vfp_cond_or_thumb ();
16688 inst.instruction |= inst.operands[0].reg << 12;
16689 inst.instruction |= inst.operands[1].reg << 16;
16690 inst.instruction |= LOW4 (inst.operands[2].reg);
16691 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16694 case NS_FF: /* case 8 (fcpys). */
16695 do_vfp_nsyn_opcode ("fcpys");
16699 case NS_FI: /* case 10 (fconsts). */
16700 ldconst = "fconsts";
16702 if (!inst.operands[1].immisfloat)
16705 /* Immediate has to fit in 8 bits so float is enough. */
16706 float imm = (float) inst.operands[1].imm;
16707 memcpy (&new_imm, &imm, sizeof (float));
16708 /* But the assembly may have been written to provide an integer
16709 bit pattern that equates to a float, so check that the
16710 conversion has worked. */
16711 if (is_quarter_float (new_imm))
16713 if (is_quarter_float (inst.operands[1].imm))
16714 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
16716 inst.operands[1].imm = new_imm;
16717 inst.operands[1].immisfloat = 1;
16721 if (is_quarter_float (inst.operands[1].imm))
16723 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
16724 do_vfp_nsyn_opcode (ldconst);
16726 /* ARMv8.2 fp16 vmov.f16 instruction. */
16728 do_scalar_fp16_v82_encode ();
16731 first_error (_("immediate out of range"));
16735 case NS_RF: /* case 12 (fmrs). */
16736 do_vfp_nsyn_opcode ("fmrs");
16737 /* ARMv8.2 fp16 vmov.f16 instruction. */
16739 do_scalar_fp16_v82_encode ();
16743 case NS_FR: /* case 13 (fmsr). */
16744 do_vfp_nsyn_opcode ("fmsr");
16745 /* ARMv8.2 fp16 vmov.f16 instruction. */
16747 do_scalar_fp16_v82_encode ();
16750 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16751 (one of which is a list), but we have parsed four. Do some fiddling to
16752 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16754 case NS_RRFF: /* case 14 (fmrrs). */
16755 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
16756 _("VFP registers must be adjacent"));
16757 inst.operands[2].imm = 2;
16758 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16759 do_vfp_nsyn_opcode ("fmrrs");
16762 case NS_FFRR: /* case 15 (fmsrr). */
16763 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
16764 _("VFP registers must be adjacent"));
16765 inst.operands[1] = inst.operands[2];
16766 inst.operands[2] = inst.operands[3];
16767 inst.operands[0].imm = 2;
16768 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16769 do_vfp_nsyn_opcode ("fmsrr");
16773 /* neon_select_shape has determined that the instruction
16774 shape is wrong and has already set the error message. */
16783 do_neon_rshift_round_imm (void)
16785 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16786 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16787 int imm = inst.operands[2].imm;
16789 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16792 inst.operands[2].present = 0;
16797 constraint (imm < 1 || (unsigned)imm > et.size,
16798 _("immediate out of range for shift"));
16799 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
16804 do_neon_movhf (void)
16806 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
16807 constraint (rs != NS_HH, _("invalid suffix"));
16809 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16812 if (inst.cond != COND_ALWAYS)
16816 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16817 " the behaviour is UNPREDICTABLE"));
16821 inst.error = BAD_COND;
16826 do_vfp_sp_monadic ();
16829 inst.instruction |= 0xf0000000;
16833 do_neon_movl (void)
16835 struct neon_type_el et = neon_check_type (2, NS_QD,
16836 N_EQK | N_DBL, N_SU_32 | N_KEY);
16837 unsigned sizebits = et.size >> 3;
16838 inst.instruction |= sizebits << 19;
16839 neon_two_same (0, et.type == NT_unsigned, -1);
16845 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16846 struct neon_type_el et = neon_check_type (2, rs,
16847 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16848 NEON_ENCODE (INTEGER, inst);
16849 neon_two_same (neon_quad (rs), 1, et.size);
16853 do_neon_zip_uzp (void)
16855 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16856 struct neon_type_el et = neon_check_type (2, rs,
16857 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16858 if (rs == NS_DD && et.size == 32)
16860 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16861 inst.instruction = N_MNEM_vtrn;
16865 neon_two_same (neon_quad (rs), 1, et.size);
16869 do_neon_sat_abs_neg (void)
16871 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16872 struct neon_type_el et = neon_check_type (2, rs,
16873 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16874 neon_two_same (neon_quad (rs), 1, et.size);
16878 do_neon_pair_long (void)
16880 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16881 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
16882 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16883 inst.instruction |= (et.type == NT_unsigned) << 7;
16884 neon_two_same (neon_quad (rs), 1, et.size);
16888 do_neon_recip_est (void)
16890 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16891 struct neon_type_el et = neon_check_type (2, rs,
16892 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
16893 inst.instruction |= (et.type == NT_float) << 8;
16894 neon_two_same (neon_quad (rs), 1, et.size);
16900 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16901 struct neon_type_el et = neon_check_type (2, rs,
16902 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16903 neon_two_same (neon_quad (rs), 1, et.size);
16909 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16910 struct neon_type_el et = neon_check_type (2, rs,
16911 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
16912 neon_two_same (neon_quad (rs), 1, et.size);
16918 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16919 struct neon_type_el et = neon_check_type (2, rs,
16920 N_EQK | N_INT, N_8 | N_KEY);
16921 neon_two_same (neon_quad (rs), 1, et.size);
16927 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16928 neon_two_same (neon_quad (rs), 1, -1);
16932 do_neon_tbl_tbx (void)
16934 unsigned listlenbits;
16935 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
16937 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16939 first_error (_("bad list length for table lookup"));
16943 listlenbits = inst.operands[1].imm - 1;
16944 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16945 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16946 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16947 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16948 inst.instruction |= LOW4 (inst.operands[2].reg);
16949 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16950 inst.instruction |= listlenbits << 8;
16952 neon_dp_fixup (&inst);
16956 do_neon_ldm_stm (void)
16958 /* P, U and L bits are part of bitmask. */
16959 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16960 unsigned offsetbits = inst.operands[1].imm * 2;
16962 if (inst.operands[1].issingle)
16964 do_vfp_nsyn_ldm_stm (is_dbmode);
16968 constraint (is_dbmode && !inst.operands[0].writeback,
16969 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16971 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16972 _("register list must contain at least 1 and at most 16 "
16975 inst.instruction |= inst.operands[0].reg << 16;
16976 inst.instruction |= inst.operands[0].writeback << 21;
16977 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16978 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16980 inst.instruction |= offsetbits;
16982 do_vfp_cond_or_thumb ();
16986 do_neon_ldr_str (void)
16988 int is_ldr = (inst.instruction & (1 << 20)) != 0;
16990 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16991 And is UNPREDICTABLE in thumb mode. */
16993 && inst.operands[1].reg == REG_PC
16994 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
16997 inst.error = _("Use of PC here is UNPREDICTABLE");
16998 else if (warn_on_deprecated)
16999 as_tsktsk (_("Use of PC here is deprecated"));
17002 if (inst.operands[0].issingle)
17005 do_vfp_nsyn_opcode ("flds");
17007 do_vfp_nsyn_opcode ("fsts");
17009 /* ARMv8.2 vldr.16/vstr.16 instruction. */
17010 if (inst.vectype.el[0].size == 16)
17011 do_scalar_fp16_v82_encode ();
17016 do_vfp_nsyn_opcode ("fldd");
17018 do_vfp_nsyn_opcode ("fstd");
17022 /* "interleave" version also handles non-interleaving register VLD1/VST1
17026 do_neon_ld_st_interleave (void)
17028 struct neon_type_el et = neon_check_type (1, NS_NULL,
17029 N_8 | N_16 | N_32 | N_64);
17030 unsigned alignbits = 0;
17032 /* The bits in this table go:
17033 0: register stride of one (0) or two (1)
17034 1,2: register list length, minus one (1, 2, 3, 4).
17035 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17036 We use -1 for invalid entries. */
17037 const int typetable[] =
17039 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17040 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17041 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17042 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17046 if (et.type == NT_invtype)
17049 if (inst.operands[1].immisalign)
17050 switch (inst.operands[1].imm >> 8)
17052 case 64: alignbits = 1; break;
17054 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
17055 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
17056 goto bad_alignment;
17060 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
17061 goto bad_alignment;
17066 first_error (_("bad alignment"));
17070 inst.instruction |= alignbits << 4;
17071 inst.instruction |= neon_logbits (et.size) << 6;
17073 /* Bits [4:6] of the immediate in a list specifier encode register stride
17074 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17075 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17076 up the right value for "type" in a table based on this value and the given
17077 list style, then stick it back. */
17078 idx = ((inst.operands[0].imm >> 4) & 7)
17079 | (((inst.instruction >> 8) & 3) << 3);
17081 typebits = typetable[idx];
17083 constraint (typebits == -1, _("bad list type for instruction"));
17084 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
17085 _("bad element type for instruction"));
17087 inst.instruction &= ~0xf00;
17088 inst.instruction |= typebits << 8;
17091 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17092 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17093 otherwise. The variable arguments are a list of pairs of legal (size, align)
17094 values, terminated with -1. */
17097 neon_alignment_bit (int size, int align, int *do_alignment, ...)
17100 int result = FAIL, thissize, thisalign;
17102 if (!inst.operands[1].immisalign)
17108 va_start (ap, do_alignment);
17112 thissize = va_arg (ap, int);
17113 if (thissize == -1)
17115 thisalign = va_arg (ap, int);
17117 if (size == thissize && align == thisalign)
17120 while (result != SUCCESS);
17124 if (result == SUCCESS)
17127 first_error (_("unsupported alignment for instruction"));
17133 do_neon_ld_st_lane (void)
17135 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
17136 int align_good, do_alignment = 0;
17137 int logsize = neon_logbits (et.size);
17138 int align = inst.operands[1].imm >> 8;
17139 int n = (inst.instruction >> 8) & 3;
17140 int max_el = 64 / et.size;
17142 if (et.type == NT_invtype)
17145 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
17146 _("bad list length"));
17147 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
17148 _("scalar index out of range"));
17149 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
17151 _("stride of 2 unavailable when element size is 8"));
17155 case 0: /* VLD1 / VST1. */
17156 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
17158 if (align_good == FAIL)
17162 unsigned alignbits = 0;
17165 case 16: alignbits = 0x1; break;
17166 case 32: alignbits = 0x3; break;
17169 inst.instruction |= alignbits << 4;
17173 case 1: /* VLD2 / VST2. */
17174 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
17175 16, 32, 32, 64, -1);
17176 if (align_good == FAIL)
17179 inst.instruction |= 1 << 4;
17182 case 2: /* VLD3 / VST3. */
17183 constraint (inst.operands[1].immisalign,
17184 _("can't use alignment with this instruction"));
17187 case 3: /* VLD4 / VST4. */
17188 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
17189 16, 64, 32, 64, 32, 128, -1);
17190 if (align_good == FAIL)
17194 unsigned alignbits = 0;
17197 case 8: alignbits = 0x1; break;
17198 case 16: alignbits = 0x1; break;
17199 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
17202 inst.instruction |= alignbits << 4;
17209 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17210 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
17211 inst.instruction |= 1 << (4 + logsize);
17213 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
17214 inst.instruction |= logsize << 10;
17217 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17220 do_neon_ld_dup (void)
17222 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
17223 int align_good, do_alignment = 0;
17225 if (et.type == NT_invtype)
17228 switch ((inst.instruction >> 8) & 3)
17230 case 0: /* VLD1. */
17231 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
17232 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
17233 &do_alignment, 16, 16, 32, 32, -1);
17234 if (align_good == FAIL)
17236 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
17239 case 2: inst.instruction |= 1 << 5; break;
17240 default: first_error (_("bad list length")); return;
17242 inst.instruction |= neon_logbits (et.size) << 6;
17245 case 1: /* VLD2. */
17246 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
17247 &do_alignment, 8, 16, 16, 32, 32, 64,
17249 if (align_good == FAIL)
17251 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
17252 _("bad list length"));
17253 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
17254 inst.instruction |= 1 << 5;
17255 inst.instruction |= neon_logbits (et.size) << 6;
17258 case 2: /* VLD3. */
17259 constraint (inst.operands[1].immisalign,
17260 _("can't use alignment with this instruction"));
17261 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
17262 _("bad list length"));
17263 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
17264 inst.instruction |= 1 << 5;
17265 inst.instruction |= neon_logbits (et.size) << 6;
17268 case 3: /* VLD4. */
17270 int align = inst.operands[1].imm >> 8;
17271 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
17272 16, 64, 32, 64, 32, 128, -1);
17273 if (align_good == FAIL)
17275 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
17276 _("bad list length"));
17277 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
17278 inst.instruction |= 1 << 5;
17279 if (et.size == 32 && align == 128)
17280 inst.instruction |= 0x3 << 6;
17282 inst.instruction |= neon_logbits (et.size) << 6;
17289 inst.instruction |= do_alignment << 4;
17292 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17293 apart from bits [11:4]. */
17296 do_neon_ldx_stx (void)
17298 if (inst.operands[1].isreg)
17299 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
17301 switch (NEON_LANE (inst.operands[0].imm))
17303 case NEON_INTERLEAVE_LANES:
17304 NEON_ENCODE (INTERLV, inst);
17305 do_neon_ld_st_interleave ();
17308 case NEON_ALL_LANES:
17309 NEON_ENCODE (DUP, inst);
17310 if (inst.instruction == N_INV)
17312 first_error ("only loads support such operands");
17319 NEON_ENCODE (LANE, inst);
17320 do_neon_ld_st_lane ();
17323 /* L bit comes from bit mask. */
17324 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17325 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17326 inst.instruction |= inst.operands[1].reg << 16;
17328 if (inst.operands[1].postind)
17330 int postreg = inst.operands[1].imm & 0xf;
17331 constraint (!inst.operands[1].immisreg,
17332 _("post-index must be a register"));
17333 constraint (postreg == 0xd || postreg == 0xf,
17334 _("bad register for post-index"));
17335 inst.instruction |= postreg;
17339 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17340 constraint (inst.reloc.exp.X_op != O_constant
17341 || inst.reloc.exp.X_add_number != 0,
17344 if (inst.operands[1].writeback)
17346 inst.instruction |= 0xd;
17349 inst.instruction |= 0xf;
17353 inst.instruction |= 0xf9000000;
17355 inst.instruction |= 0xf4000000;
17360 do_vfp_nsyn_fpv8 (enum neon_shape rs)
17362 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17363 D register operands. */
17364 if (neon_shape_class[rs] == SC_DOUBLE)
17365 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17368 NEON_ENCODE (FPV8, inst);
17370 if (rs == NS_FFF || rs == NS_HHH)
17372 do_vfp_sp_dyadic ();
17374 /* ARMv8.2 fp16 instruction. */
17376 do_scalar_fp16_v82_encode ();
17379 do_vfp_dp_rd_rn_rm ();
17382 inst.instruction |= 0x100;
17384 inst.instruction |= 0xf0000000;
17390 set_it_insn_type (OUTSIDE_IT_INSN);
17392 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
17393 first_error (_("invalid instruction shape"));
17399 set_it_insn_type (OUTSIDE_IT_INSN);
17401 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
17404 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17407 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
17411 do_vrint_1 (enum neon_cvt_mode mode)
17413 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
17414 struct neon_type_el et;
17419 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17420 D register operands. */
17421 if (neon_shape_class[rs] == SC_DOUBLE)
17422 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17425 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
17427 if (et.type != NT_invtype)
17429 /* VFP encodings. */
17430 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
17431 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
17432 set_it_insn_type (OUTSIDE_IT_INSN);
17434 NEON_ENCODE (FPV8, inst);
17435 if (rs == NS_FF || rs == NS_HH)
17436 do_vfp_sp_monadic ();
17438 do_vfp_dp_rd_rm ();
17442 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
17443 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
17444 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
17445 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
17446 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
17447 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
17448 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
17452 inst.instruction |= (rs == NS_DD) << 8;
17453 do_vfp_cond_or_thumb ();
17455 /* ARMv8.2 fp16 vrint instruction. */
17457 do_scalar_fp16_v82_encode ();
17461 /* Neon encodings (or something broken...). */
17463 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
17465 if (et.type == NT_invtype)
17468 set_it_insn_type (OUTSIDE_IT_INSN);
17469 NEON_ENCODE (FLOAT, inst);
17471 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
17474 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17475 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17476 inst.instruction |= LOW4 (inst.operands[1].reg);
17477 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17478 inst.instruction |= neon_quad (rs) << 6;
17479 /* Mask off the original size bits and reencode them. */
17480 inst.instruction = ((inst.instruction & 0xfff3ffff)
17481 | neon_logbits (et.size) << 18);
17485 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
17486 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
17487 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
17488 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
17489 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
17490 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
17491 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
17496 inst.instruction |= 0xfc000000;
17498 inst.instruction |= 0xf0000000;
17505 do_vrint_1 (neon_cvt_mode_x);
17511 do_vrint_1 (neon_cvt_mode_z);
17517 do_vrint_1 (neon_cvt_mode_r);
17523 do_vrint_1 (neon_cvt_mode_a);
17529 do_vrint_1 (neon_cvt_mode_n);
17535 do_vrint_1 (neon_cvt_mode_p);
17541 do_vrint_1 (neon_cvt_mode_m);
17545 neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
17547 unsigned regno = NEON_SCALAR_REG (opnd);
17548 unsigned elno = NEON_SCALAR_INDEX (opnd);
17550 if (elsize == 16 && elno < 2 && regno < 16)
17551 return regno | (elno << 4);
17552 else if (elsize == 32 && elno == 0)
17555 first_error (_("scalar out of range"));
17562 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
17564 constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
17565 unsigned rot = inst.reloc.exp.X_add_number;
17566 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
17567 _("immediate out of range"));
17569 if (inst.operands[2].isscalar)
17571 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
17572 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
17573 N_KEY | N_F16 | N_F32).size;
17574 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
17576 inst.instruction = 0xfe000800;
17577 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17578 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17579 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17580 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17581 inst.instruction |= LOW4 (m);
17582 inst.instruction |= HI1 (m) << 5;
17583 inst.instruction |= neon_quad (rs) << 6;
17584 inst.instruction |= rot << 20;
17585 inst.instruction |= (size == 32) << 23;
17589 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
17590 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
17591 N_KEY | N_F16 | N_F32).size;
17592 neon_three_same (neon_quad (rs), 0, -1);
17593 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
17594 inst.instruction |= 0xfc200800;
17595 inst.instruction |= rot << 23;
17596 inst.instruction |= (size == 32) << 20;
17603 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
17605 constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
17606 unsigned rot = inst.reloc.exp.X_add_number;
17607 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17608 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
17609 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
17610 N_KEY | N_F16 | N_F32).size;
17611 neon_three_same (neon_quad (rs), 0, -1);
17612 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
17613 inst.instruction |= 0xfc800800;
17614 inst.instruction |= (rot == 270) << 24;
17615 inst.instruction |= (size == 32) << 20;
17618 /* Dot Product instructions encoding support. */
17621 do_neon_dotproduct (int unsigned_p)
17623 enum neon_shape rs;
17624 unsigned scalar_oprd2 = 0;
17627 if (inst.cond != COND_ALWAYS)
17628 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17629 "is UNPREDICTABLE"));
17631 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
17634 /* Dot Product instructions are in three-same D/Q register format or the third
17635 operand can be a scalar index register. */
17636 if (inst.operands[2].isscalar)
17638 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
17639 high8 = 0xfe000000;
17640 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17644 high8 = 0xfc000000;
17645 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17649 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
17651 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
17653 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17654 Product instruction, so we pass 0 as the "ubit" parameter. And the
17655 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17656 neon_three_same (neon_quad (rs), 0, 32);
17658 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17659 different NEON three-same encoding. */
17660 inst.instruction &= 0x00ffffff;
17661 inst.instruction |= high8;
17662 /* Encode 'U' bit which indicates signedness. */
17663 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
17664 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17665 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17666 the instruction encoding. */
17667 if (inst.operands[2].isscalar)
17669 inst.instruction &= 0xffffffd0;
17670 inst.instruction |= LOW4 (scalar_oprd2);
17671 inst.instruction |= HI1 (scalar_oprd2) << 5;
17675 /* Dot Product instructions for signed integer. */
17678 do_neon_dotproduct_s (void)
17680 return do_neon_dotproduct (0);
17683 /* Dot Product instructions for unsigned integer. */
17686 do_neon_dotproduct_u (void)
17688 return do_neon_dotproduct (1);
17691 /* Crypto v1 instructions. */
17693 do_crypto_2op_1 (unsigned elttype, int op)
17695 set_it_insn_type (OUTSIDE_IT_INSN);
17697 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
17703 NEON_ENCODE (INTEGER, inst);
17704 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17705 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17706 inst.instruction |= LOW4 (inst.operands[1].reg);
17707 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17709 inst.instruction |= op << 6;
17712 inst.instruction |= 0xfc000000;
17714 inst.instruction |= 0xf0000000;
17718 do_crypto_3op_1 (int u, int op)
17720 set_it_insn_type (OUTSIDE_IT_INSN);
17722 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
17723 N_32 | N_UNT | N_KEY).type == NT_invtype)
17728 NEON_ENCODE (INTEGER, inst);
17729 neon_three_same (1, u, 8 << op);
17735 do_crypto_2op_1 (N_8, 0);
17741 do_crypto_2op_1 (N_8, 1);
17747 do_crypto_2op_1 (N_8, 2);
17753 do_crypto_2op_1 (N_8, 3);
17759 do_crypto_3op_1 (0, 0);
17765 do_crypto_3op_1 (0, 1);
17771 do_crypto_3op_1 (0, 2);
17777 do_crypto_3op_1 (0, 3);
17783 do_crypto_3op_1 (1, 0);
17789 do_crypto_3op_1 (1, 1);
17793 do_sha256su1 (void)
17795 do_crypto_3op_1 (1, 2);
17801 do_crypto_2op_1 (N_32, -1);
17807 do_crypto_2op_1 (N_32, 0);
17811 do_sha256su0 (void)
17813 do_crypto_2op_1 (N_32, 1);
17817 do_crc32_1 (unsigned int poly, unsigned int sz)
17819 unsigned int Rd = inst.operands[0].reg;
17820 unsigned int Rn = inst.operands[1].reg;
17821 unsigned int Rm = inst.operands[2].reg;
17823 set_it_insn_type (OUTSIDE_IT_INSN);
17824 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
17825 inst.instruction |= LOW4 (Rn) << 16;
17826 inst.instruction |= LOW4 (Rm);
17827 inst.instruction |= sz << (thumb_mode ? 4 : 21);
17828 inst.instruction |= poly << (thumb_mode ? 20 : 9);
17830 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
17831 as_warn (UNPRED_REG ("r15"));
17873 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
17875 neon_check_type (2, NS_FD, N_S32, N_F64);
17876 do_vfp_sp_dp_cvt ();
17877 do_vfp_cond_or_thumb ();
17881 /* Overall per-instruction processing. */
17883 /* We need to be able to fix up arbitrary expressions in some statements.
17884 This is so that we can handle symbols that are an arbitrary distance from
17885 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17886 which returns part of an address in a form which will be valid for
17887 a data instruction. We do this by pushing the expression into a symbol
17888 in the expr_section, and creating a fix for that. */
17891 fix_new_arm (fragS * frag,
17905 /* Create an absolute valued symbol, so we have something to
17906 refer to in the object file. Unfortunately for us, gas's
17907 generic expression parsing will already have folded out
17908 any use of .set foo/.type foo %function that may have
17909 been used to set type information of the target location,
17910 that's being specified symbolically. We have to presume
17911 the user knows what they are doing. */
17915 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
17917 symbol = symbol_find_or_make (name);
17918 S_SET_SEGMENT (symbol, absolute_section);
17919 symbol_set_frag (symbol, &zero_address_frag);
17920 S_SET_VALUE (symbol, exp->X_add_number);
17921 exp->X_op = O_symbol;
17922 exp->X_add_symbol = symbol;
17923 exp->X_add_number = 0;
17929 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
17930 (enum bfd_reloc_code_real) reloc);
17934 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
17935 pc_rel, (enum bfd_reloc_code_real) reloc);
17939 /* Mark whether the fix is to a THUMB instruction, or an ARM
17941 new_fix->tc_fix_data = thumb_mode;
17944 /* Create a frg for an instruction requiring relaxation. */
17946 output_relax_insn (void)
17952 /* The size of the instruction is unknown, so tie the debug info to the
17953 start of the instruction. */
17954 dwarf2_emit_insn (0);
17956 switch (inst.reloc.exp.X_op)
17959 sym = inst.reloc.exp.X_add_symbol;
17960 offset = inst.reloc.exp.X_add_number;
17964 offset = inst.reloc.exp.X_add_number;
17967 sym = make_expr_symbol (&inst.reloc.exp);
17971 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
17972 inst.relax, sym, offset, NULL/*offset, opcode*/);
17973 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
17976 /* Write a 32-bit thumb instruction to buf. */
17978 put_thumb32_insn (char * buf, unsigned long insn)
17980 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
17981 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
17985 output_inst (const char * str)
17991 as_bad ("%s -- `%s'", inst.error, str);
17996 output_relax_insn ();
17999 if (inst.size == 0)
18002 to = frag_more (inst.size);
18003 /* PR 9814: Record the thumb mode into the current frag so that we know
18004 what type of NOP padding to use, if necessary. We override any previous
18005 setting so that if the mode has changed then the NOPS that we use will
18006 match the encoding of the last instruction in the frag. */
18007 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
18009 if (thumb_mode && (inst.size > THUMB_SIZE))
18011 gas_assert (inst.size == (2 * THUMB_SIZE));
18012 put_thumb32_insn (to, inst.instruction);
18014 else if (inst.size > INSN_SIZE)
18016 gas_assert (inst.size == (2 * INSN_SIZE));
18017 md_number_to_chars (to, inst.instruction, INSN_SIZE);
18018 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
18021 md_number_to_chars (to, inst.instruction, inst.size);
18023 if (inst.reloc.type != BFD_RELOC_UNUSED)
18024 fix_new_arm (frag_now, to - frag_now->fr_literal,
18025 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
18028 dwarf2_emit_insn (inst.size);
18032 output_it_inst (int cond, int mask, char * to)
18034 unsigned long instruction = 0xbf00;
18037 instruction |= mask;
18038 instruction |= cond << 4;
18042 to = frag_more (2);
18044 dwarf2_emit_insn (2);
18048 md_number_to_chars (to, instruction, 2);
18053 /* Tag values used in struct asm_opcode's tag field. */
18056 OT_unconditional, /* Instruction cannot be conditionalized.
18057 The ARM condition field is still 0xE. */
18058 OT_unconditionalF, /* Instruction cannot be conditionalized
18059 and carries 0xF in its ARM condition field. */
18060 OT_csuffix, /* Instruction takes a conditional suffix. */
18061 OT_csuffixF, /* Some forms of the instruction take a conditional
18062 suffix, others place 0xF where the condition field
18064 OT_cinfix3, /* Instruction takes a conditional infix,
18065 beginning at character index 3. (In
18066 unified mode, it becomes a suffix.) */
18067 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
18068 tsts, cmps, cmns, and teqs. */
18069 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
18070 character index 3, even in unified mode. Used for
18071 legacy instructions where suffix and infix forms
18072 may be ambiguous. */
18073 OT_csuf_or_in3, /* Instruction takes either a conditional
18074 suffix or an infix at character index 3. */
18075 OT_odd_infix_unc, /* This is the unconditional variant of an
18076 instruction that takes a conditional infix
18077 at an unusual position. In unified mode,
18078 this variant will accept a suffix. */
18079 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
18080 are the conditional variants of instructions that
18081 take conditional infixes in unusual positions.
18082 The infix appears at character index
18083 (tag - OT_odd_infix_0). These are not accepted
18084 in unified mode. */
18087 /* Subroutine of md_assemble, responsible for looking up the primary
18088 opcode from the mnemonic the user wrote. STR points to the
18089 beginning of the mnemonic.
18091 This is not simply a hash table lookup, because of conditional
18092 variants. Most instructions have conditional variants, which are
18093 expressed with a _conditional affix_ to the mnemonic. If we were
18094 to encode each conditional variant as a literal string in the opcode
18095 table, it would have approximately 20,000 entries.
18097 Most mnemonics take this affix as a suffix, and in unified syntax,
18098 'most' is upgraded to 'all'. However, in the divided syntax, some
18099 instructions take the affix as an infix, notably the s-variants of
18100 the arithmetic instructions. Of those instructions, all but six
18101 have the infix appear after the third character of the mnemonic.
18103 Accordingly, the algorithm for looking up primary opcodes given
18106 1. Look up the identifier in the opcode table.
18107 If we find a match, go to step U.
18109 2. Look up the last two characters of the identifier in the
18110 conditions table. If we find a match, look up the first N-2
18111 characters of the identifier in the opcode table. If we
18112 find a match, go to step CE.
18114 3. Look up the fourth and fifth characters of the identifier in
18115 the conditions table. If we find a match, extract those
18116 characters from the identifier, and look up the remaining
18117 characters in the opcode table. If we find a match, go
18122 U. Examine the tag field of the opcode structure, in case this is
18123 one of the six instructions with its conditional infix in an
18124 unusual place. If it is, the tag tells us where to find the
18125 infix; look it up in the conditions table and set inst.cond
18126 accordingly. Otherwise, this is an unconditional instruction.
18127 Again set inst.cond accordingly. Return the opcode structure.
18129 CE. Examine the tag field to make sure this is an instruction that
18130 should receive a conditional suffix. If it is not, fail.
18131 Otherwise, set inst.cond from the suffix we already looked up,
18132 and return the opcode structure.
18134 CM. Examine the tag field to make sure this is an instruction that
18135 should receive a conditional infix after the third character.
18136 If it is not, fail. Otherwise, undo the edits to the current
18137 line of input and proceed as for case CE. */
18139 static const struct asm_opcode *
18140 opcode_lookup (char **str)
18144 const struct asm_opcode *opcode;
18145 const struct asm_cond *cond;
18148 /* Scan up to the end of the mnemonic, which must end in white space,
18149 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18150 for (base = end = *str; *end != '\0'; end++)
18151 if (*end == ' ' || *end == '.')
18157 /* Handle a possible width suffix and/or Neon type suffix. */
18162 /* The .w and .n suffixes are only valid if the unified syntax is in
18164 if (unified_syntax && end[1] == 'w')
18166 else if (unified_syntax && end[1] == 'n')
18171 inst.vectype.elems = 0;
18173 *str = end + offset;
18175 if (end[offset] == '.')
18177 /* See if we have a Neon type suffix (possible in either unified or
18178 non-unified ARM syntax mode). */
18179 if (parse_neon_type (&inst.vectype, str) == FAIL)
18182 else if (end[offset] != '\0' && end[offset] != ' ')
18188 /* Look for unaffixed or special-case affixed mnemonic. */
18189 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
18194 if (opcode->tag < OT_odd_infix_0)
18196 inst.cond = COND_ALWAYS;
18200 if (warn_on_deprecated && unified_syntax)
18201 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18202 affix = base + (opcode->tag - OT_odd_infix_0);
18203 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
18206 inst.cond = cond->value;
18210 /* Cannot have a conditional suffix on a mnemonic of less than two
18212 if (end - base < 3)
18215 /* Look for suffixed mnemonic. */
18217 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
18218 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
18220 if (opcode && cond)
18223 switch (opcode->tag)
18225 case OT_cinfix3_legacy:
18226 /* Ignore conditional suffixes matched on infix only mnemonics. */
18230 case OT_cinfix3_deprecated:
18231 case OT_odd_infix_unc:
18232 if (!unified_syntax)
18234 /* Fall through. */
18238 case OT_csuf_or_in3:
18239 inst.cond = cond->value;
18242 case OT_unconditional:
18243 case OT_unconditionalF:
18245 inst.cond = cond->value;
18248 /* Delayed diagnostic. */
18249 inst.error = BAD_COND;
18250 inst.cond = COND_ALWAYS;
18259 /* Cannot have a usual-position infix on a mnemonic of less than
18260 six characters (five would be a suffix). */
18261 if (end - base < 6)
18264 /* Look for infixed mnemonic in the usual position. */
18266 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
18270 memcpy (save, affix, 2);
18271 memmove (affix, affix + 2, (end - affix) - 2);
18272 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
18274 memmove (affix + 2, affix, (end - affix) - 2);
18275 memcpy (affix, save, 2);
18278 && (opcode->tag == OT_cinfix3
18279 || opcode->tag == OT_cinfix3_deprecated
18280 || opcode->tag == OT_csuf_or_in3
18281 || opcode->tag == OT_cinfix3_legacy))
18284 if (warn_on_deprecated && unified_syntax
18285 && (opcode->tag == OT_cinfix3
18286 || opcode->tag == OT_cinfix3_deprecated))
18287 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18289 inst.cond = cond->value;
18296 /* This function generates an initial IT instruction, leaving its block
18297 virtually open for the new instructions. Eventually,
18298 the mask will be updated by now_it_add_mask () each time
18299 a new instruction needs to be included in the IT block.
18300 Finally, the block is closed with close_automatic_it_block ().
18301 The block closure can be requested either from md_assemble (),
18302 a tencode (), or due to a label hook. */
18305 new_automatic_it_block (int cond)
18307 now_it.state = AUTOMATIC_IT_BLOCK;
18308 now_it.mask = 0x18;
18310 now_it.block_length = 1;
18311 mapping_state (MAP_THUMB);
18312 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
18313 now_it.warn_deprecated = FALSE;
18314 now_it.insn_cond = TRUE;
18317 /* Close an automatic IT block.
18318 See comments in new_automatic_it_block (). */
18321 close_automatic_it_block (void)
18323 now_it.mask = 0x10;
18324 now_it.block_length = 0;
18327 /* Update the mask of the current automatically-generated IT
18328 instruction. See comments in new_automatic_it_block (). */
18331 now_it_add_mask (int cond)
18333 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18334 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18335 | ((bitvalue) << (nbit)))
18336 const int resulting_bit = (cond & 1);
18338 now_it.mask &= 0xf;
18339 now_it.mask = SET_BIT_VALUE (now_it.mask,
18341 (5 - now_it.block_length));
18342 now_it.mask = SET_BIT_VALUE (now_it.mask,
18344 ((5 - now_it.block_length) - 1) );
18345 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
18348 #undef SET_BIT_VALUE
18351 /* The IT blocks handling machinery is accessed through the these functions:
18352 it_fsm_pre_encode () from md_assemble ()
18353 set_it_insn_type () optional, from the tencode functions
18354 set_it_insn_type_last () ditto
18355 in_it_block () ditto
18356 it_fsm_post_encode () from md_assemble ()
18357 force_automatic_it_block_close () from label handling functions
18360 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18361 initializing the IT insn type with a generic initial value depending
18362 on the inst.condition.
18363 2) During the tencode function, two things may happen:
18364 a) The tencode function overrides the IT insn type by
18365 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18366 b) The tencode function queries the IT block state by
18367 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18369 Both set_it_insn_type and in_it_block run the internal FSM state
18370 handling function (handle_it_state), because: a) setting the IT insn
18371 type may incur in an invalid state (exiting the function),
18372 and b) querying the state requires the FSM to be updated.
18373 Specifically we want to avoid creating an IT block for conditional
18374 branches, so it_fsm_pre_encode is actually a guess and we can't
18375 determine whether an IT block is required until the tencode () routine
18376 has decided what type of instruction this actually it.
18377 Because of this, if set_it_insn_type and in_it_block have to be used,
18378 set_it_insn_type has to be called first.
18380 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18381 determines the insn IT type depending on the inst.cond code.
18382 When a tencode () routine encodes an instruction that can be
18383 either outside an IT block, or, in the case of being inside, has to be
18384 the last one, set_it_insn_type_last () will determine the proper
18385 IT instruction type based on the inst.cond code. Otherwise,
18386 set_it_insn_type can be called for overriding that logic or
18387 for covering other cases.
18389 Calling handle_it_state () may not transition the IT block state to
18390 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18391 still queried. Instead, if the FSM determines that the state should
18392 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18393 after the tencode () function: that's what it_fsm_post_encode () does.
18395 Since in_it_block () calls the state handling function to get an
18396 updated state, an error may occur (due to invalid insns combination).
18397 In that case, inst.error is set.
18398 Therefore, inst.error has to be checked after the execution of
18399 the tencode () routine.
18401 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18402 any pending state change (if any) that didn't take place in
18403 handle_it_state () as explained above. */
18406 it_fsm_pre_encode (void)
18408 if (inst.cond != COND_ALWAYS)
18409 inst.it_insn_type = INSIDE_IT_INSN;
18411 inst.it_insn_type = OUTSIDE_IT_INSN;
18413 now_it.state_handled = 0;
18416 /* IT state FSM handling function. */
18419 handle_it_state (void)
18421 now_it.state_handled = 1;
18422 now_it.insn_cond = FALSE;
18424 switch (now_it.state)
18426 case OUTSIDE_IT_BLOCK:
18427 switch (inst.it_insn_type)
18429 case OUTSIDE_IT_INSN:
18432 case INSIDE_IT_INSN:
18433 case INSIDE_IT_LAST_INSN:
18434 if (thumb_mode == 0)
18437 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
18438 as_tsktsk (_("Warning: conditional outside an IT block"\
18443 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
18444 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
18446 /* Automatically generate the IT instruction. */
18447 new_automatic_it_block (inst.cond);
18448 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
18449 close_automatic_it_block ();
18453 inst.error = BAD_OUT_IT;
18459 case IF_INSIDE_IT_LAST_INSN:
18460 case NEUTRAL_IT_INSN:
18464 now_it.state = MANUAL_IT_BLOCK;
18465 now_it.block_length = 0;
18470 case AUTOMATIC_IT_BLOCK:
18471 /* Three things may happen now:
18472 a) We should increment current it block size;
18473 b) We should close current it block (closing insn or 4 insns);
18474 c) We should close current it block and start a new one (due
18475 to incompatible conditions or
18476 4 insns-length block reached). */
18478 switch (inst.it_insn_type)
18480 case OUTSIDE_IT_INSN:
18481 /* The closure of the block shall happen immediately,
18482 so any in_it_block () call reports the block as closed. */
18483 force_automatic_it_block_close ();
18486 case INSIDE_IT_INSN:
18487 case INSIDE_IT_LAST_INSN:
18488 case IF_INSIDE_IT_LAST_INSN:
18489 now_it.block_length++;
18491 if (now_it.block_length > 4
18492 || !now_it_compatible (inst.cond))
18494 force_automatic_it_block_close ();
18495 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
18496 new_automatic_it_block (inst.cond);
18500 now_it.insn_cond = TRUE;
18501 now_it_add_mask (inst.cond);
18504 if (now_it.state == AUTOMATIC_IT_BLOCK
18505 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
18506 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
18507 close_automatic_it_block ();
18510 case NEUTRAL_IT_INSN:
18511 now_it.block_length++;
18512 now_it.insn_cond = TRUE;
18514 if (now_it.block_length > 4)
18515 force_automatic_it_block_close ();
18517 now_it_add_mask (now_it.cc & 1);
18521 close_automatic_it_block ();
18522 now_it.state = MANUAL_IT_BLOCK;
18527 case MANUAL_IT_BLOCK:
18529 /* Check conditional suffixes. */
18530 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
18533 now_it.mask &= 0x1f;
18534 is_last = (now_it.mask == 0x10);
18535 now_it.insn_cond = TRUE;
18537 switch (inst.it_insn_type)
18539 case OUTSIDE_IT_INSN:
18540 inst.error = BAD_NOT_IT;
18543 case INSIDE_IT_INSN:
18544 if (cond != inst.cond)
18546 inst.error = BAD_IT_COND;
18551 case INSIDE_IT_LAST_INSN:
18552 case IF_INSIDE_IT_LAST_INSN:
18553 if (cond != inst.cond)
18555 inst.error = BAD_IT_COND;
18560 inst.error = BAD_BRANCH;
18565 case NEUTRAL_IT_INSN:
18566 /* The BKPT instruction is unconditional even in an IT block. */
18570 inst.error = BAD_IT_IT;
18580 struct depr_insn_mask
18582 unsigned long pattern;
18583 unsigned long mask;
18584 const char* description;
18587 /* List of 16-bit instruction patterns deprecated in an IT block in
18589 static const struct depr_insn_mask depr_it_insns[] = {
18590 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18591 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18592 { 0xa000, 0xb800, N_("ADR") },
18593 { 0x4800, 0xf800, N_("Literal loads") },
18594 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18595 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18596 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18597 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18598 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18603 it_fsm_post_encode (void)
18607 if (!now_it.state_handled)
18608 handle_it_state ();
18610 if (now_it.insn_cond
18611 && !now_it.warn_deprecated
18612 && warn_on_deprecated
18613 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
18614 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
18616 if (inst.instruction >= 0x10000)
18618 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18619 "performance deprecated in ARMv8-A and ARMv8-R"));
18620 now_it.warn_deprecated = TRUE;
18624 const struct depr_insn_mask *p = depr_it_insns;
18626 while (p->mask != 0)
18628 if ((inst.instruction & p->mask) == p->pattern)
18630 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18631 "instructions of the following class are "
18632 "performance deprecated in ARMv8-A and "
18633 "ARMv8-R: %s"), p->description);
18634 now_it.warn_deprecated = TRUE;
18642 if (now_it.block_length > 1)
18644 as_tsktsk (_("IT blocks containing more than one conditional "
18645 "instruction are performance deprecated in ARMv8-A and "
18647 now_it.warn_deprecated = TRUE;
18651 is_last = (now_it.mask == 0x10);
18654 now_it.state = OUTSIDE_IT_BLOCK;
18660 force_automatic_it_block_close (void)
18662 if (now_it.state == AUTOMATIC_IT_BLOCK)
18664 close_automatic_it_block ();
18665 now_it.state = OUTSIDE_IT_BLOCK;
18673 if (!now_it.state_handled)
18674 handle_it_state ();
18676 return now_it.state != OUTSIDE_IT_BLOCK;
18679 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18680 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18681 here, hence the "known" in the function name. */
18684 known_t32_only_insn (const struct asm_opcode *opcode)
18686 /* Original Thumb-1 wide instruction. */
18687 if (opcode->tencode == do_t_blx
18688 || opcode->tencode == do_t_branch23
18689 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
18690 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
18693 /* Wide-only instruction added to ARMv8-M Baseline. */
18694 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
18695 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
18696 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
18697 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
18703 /* Whether wide instruction variant can be used if available for a valid OPCODE
18707 t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
18709 if (known_t32_only_insn (opcode))
18712 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18713 of variant T3 of B.W is checked in do_t_branch. */
18714 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
18715 && opcode->tencode == do_t_branch)
18718 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18719 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
18720 && opcode->tencode == do_t_mov_cmp
18721 /* Make sure CMP instruction is not affected. */
18722 && opcode->aencode == do_mov)
18725 /* Wide instruction variants of all instructions with narrow *and* wide
18726 variants become available with ARMv6t2. Other opcodes are either
18727 narrow-only or wide-only and are thus available if OPCODE is valid. */
18728 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
18731 /* OPCODE with narrow only instruction variant or wide variant not
18737 md_assemble (char *str)
18740 const struct asm_opcode * opcode;
18742 /* Align the previous label if needed. */
18743 if (last_label_seen != NULL)
18745 symbol_set_frag (last_label_seen, frag_now);
18746 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
18747 S_SET_SEGMENT (last_label_seen, now_seg);
18750 memset (&inst, '\0', sizeof (inst));
18751 inst.reloc.type = BFD_RELOC_UNUSED;
18753 opcode = opcode_lookup (&p);
18756 /* It wasn't an instruction, but it might be a register alias of
18757 the form alias .req reg, or a Neon .dn/.qn directive. */
18758 if (! create_register_alias (str, p)
18759 && ! create_neon_reg_alias (str, p))
18760 as_bad (_("bad instruction `%s'"), str);
18765 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
18766 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18768 /* The value which unconditional instructions should have in place of the
18769 condition field. */
18770 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
18774 arm_feature_set variant;
18776 variant = cpu_variant;
18777 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18778 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
18779 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
18780 /* Check that this instruction is supported for this CPU. */
18781 if (!opcode->tvariant
18782 || (thumb_mode == 1
18783 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
18785 if (opcode->tencode == do_t_swi)
18786 as_bad (_("SVC is not permitted on this architecture"));
18788 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
18791 if (inst.cond != COND_ALWAYS && !unified_syntax
18792 && opcode->tencode != do_t_branch)
18794 as_bad (_("Thumb does not support conditional execution"));
18798 /* Two things are addressed here:
18799 1) Implicit require narrow instructions on Thumb-1.
18800 This avoids relaxation accidentally introducing Thumb-2
18802 2) Reject wide instructions in non Thumb-2 cores.
18804 Only instructions with narrow and wide variants need to be handled
18805 but selecting all non wide-only instructions is easier. */
18806 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
18807 && !t32_insn_ok (variant, opcode))
18809 if (inst.size_req == 0)
18811 else if (inst.size_req == 4)
18813 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
18814 as_bad (_("selected processor does not support 32bit wide "
18815 "variant of instruction `%s'"), str);
18817 as_bad (_("selected processor does not support `%s' in "
18818 "Thumb-2 mode"), str);
18823 inst.instruction = opcode->tvalue;
18825 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
18827 /* Prepare the it_insn_type for those encodings that don't set
18829 it_fsm_pre_encode ();
18831 opcode->tencode ();
18833 it_fsm_post_encode ();
18836 if (!(inst.error || inst.relax))
18838 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
18839 inst.size = (inst.instruction > 0xffff ? 4 : 2);
18840 if (inst.size_req && inst.size_req != inst.size)
18842 as_bad (_("cannot honor width suffix -- `%s'"), str);
18847 /* Something has gone badly wrong if we try to relax a fixed size
18849 gas_assert (inst.size_req == 0 || !inst.relax);
18851 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18852 *opcode->tvariant);
18853 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18854 set those bits when Thumb-2 32-bit instructions are seen. The impact
18855 of relaxable instructions will be considered later after we finish all
18857 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
18858 variant = arm_arch_none;
18860 variant = cpu_variant;
18861 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
18862 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
18865 check_neon_suffixes;
18869 mapping_state (MAP_THUMB);
18872 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
18876 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18877 is_bx = (opcode->aencode == do_bx);
18879 /* Check that this instruction is supported for this CPU. */
18880 if (!(is_bx && fix_v4bx)
18881 && !(opcode->avariant &&
18882 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
18884 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
18889 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
18893 inst.instruction = opcode->avalue;
18894 if (opcode->tag == OT_unconditionalF)
18895 inst.instruction |= 0xFU << 28;
18897 inst.instruction |= inst.cond << 28;
18898 inst.size = INSN_SIZE;
18899 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
18901 it_fsm_pre_encode ();
18902 opcode->aencode ();
18903 it_fsm_post_encode ();
18905 /* Arm mode bx is marked as both v4T and v5 because it's still required
18906 on a hypothetical non-thumb v5 core. */
18908 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
18910 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
18911 *opcode->avariant);
18913 check_neon_suffixes;
18917 mapping_state (MAP_ARM);
18922 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18930 check_it_blocks_finished (void)
18935 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
18936 if (seg_info (sect)->tc_segment_info_data.current_it.state
18937 == MANUAL_IT_BLOCK)
18939 as_warn (_("section '%s' finished with an open IT block."),
18943 if (now_it.state == MANUAL_IT_BLOCK)
18944 as_warn (_("file finished with an open IT block."));
18948 /* Various frobbings of labels and their addresses. */
18951 arm_start_line_hook (void)
18953 last_label_seen = NULL;
18957 arm_frob_label (symbolS * sym)
18959 last_label_seen = sym;
18961 ARM_SET_THUMB (sym, thumb_mode);
18963 #if defined OBJ_COFF || defined OBJ_ELF
18964 ARM_SET_INTERWORK (sym, support_interwork);
18967 force_automatic_it_block_close ();
18969 /* Note - do not allow local symbols (.Lxxx) to be labelled
18970 as Thumb functions. This is because these labels, whilst
18971 they exist inside Thumb code, are not the entry points for
18972 possible ARM->Thumb calls. Also, these labels can be used
18973 as part of a computed goto or switch statement. eg gcc
18974 can generate code that looks like this:
18976 ldr r2, [pc, .Laaa]
18986 The first instruction loads the address of the jump table.
18987 The second instruction converts a table index into a byte offset.
18988 The third instruction gets the jump address out of the table.
18989 The fourth instruction performs the jump.
18991 If the address stored at .Laaa is that of a symbol which has the
18992 Thumb_Func bit set, then the linker will arrange for this address
18993 to have the bottom bit set, which in turn would mean that the
18994 address computation performed by the third instruction would end
18995 up with the bottom bit set. Since the ARM is capable of unaligned
18996 word loads, the instruction would then load the incorrect address
18997 out of the jump table, and chaos would ensue. */
18998 if (label_is_thumb_function_name
18999 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
19000 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
19002 /* When the address of a Thumb function is taken the bottom
19003 bit of that address should be set. This will allow
19004 interworking between Arm and Thumb functions to work
19007 THUMB_SET_FUNC (sym, 1);
19009 label_is_thumb_function_name = FALSE;
19012 dwarf2_emit_label (sym);
19016 arm_data_in_code (void)
19018 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
19020 *input_line_pointer = '/';
19021 input_line_pointer += 5;
19022 *input_line_pointer = 0;
19030 arm_canonicalize_symbol_name (char * name)
19034 if (thumb_mode && (len = strlen (name)) > 5
19035 && streq (name + len - 5, "/data"))
19036 *(name + len - 5) = 0;
19041 /* Table of all register names defined by default. The user can
19042 define additional names with .req. Note that all register names
19043 should appear in both upper and lowercase variants. Some registers
19044 also have mixed-case names. */
19046 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19047 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19048 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19049 #define REGSET(p,t) \
19050 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19051 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19052 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19053 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19054 #define REGSETH(p,t) \
19055 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19056 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19057 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19058 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19059 #define REGSET2(p,t) \
19060 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19061 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19062 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19063 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19064 #define SPLRBANK(base,bank,t) \
19065 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19066 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19067 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19068 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19069 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19070 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19072 static const struct reg_entry reg_names[] =
19074 /* ARM integer registers. */
19075 REGSET(r, RN), REGSET(R, RN),
19077 /* ATPCS synonyms. */
19078 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
19079 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
19080 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
19082 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
19083 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
19084 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
19086 /* Well-known aliases. */
19087 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
19088 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
19090 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
19091 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
19093 /* Coprocessor numbers. */
19094 REGSET(p, CP), REGSET(P, CP),
19096 /* Coprocessor register numbers. The "cr" variants are for backward
19098 REGSET(c, CN), REGSET(C, CN),
19099 REGSET(cr, CN), REGSET(CR, CN),
19101 /* ARM banked registers. */
19102 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
19103 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
19104 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
19105 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
19106 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
19107 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
19108 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
19110 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
19111 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
19112 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
19113 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
19114 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
19115 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
19116 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
19117 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
19119 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
19120 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
19121 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
19122 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
19123 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
19124 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
19125 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
19126 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
19127 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
19129 /* FPA registers. */
19130 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
19131 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
19133 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
19134 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
19136 /* VFP SP registers. */
19137 REGSET(s,VFS), REGSET(S,VFS),
19138 REGSETH(s,VFS), REGSETH(S,VFS),
19140 /* VFP DP Registers. */
19141 REGSET(d,VFD), REGSET(D,VFD),
19142 /* Extra Neon DP registers. */
19143 REGSETH(d,VFD), REGSETH(D,VFD),
19145 /* Neon QP registers. */
19146 REGSET2(q,NQ), REGSET2(Q,NQ),
19148 /* VFP control registers. */
19149 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
19150 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
19151 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
19152 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
19153 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
19154 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
19155 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
19157 /* Maverick DSP coprocessor registers. */
19158 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
19159 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
19161 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
19162 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
19163 REGDEF(dspsc,0,DSPSC),
19165 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
19166 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
19167 REGDEF(DSPSC,0,DSPSC),
19169 /* iWMMXt data registers - p0, c0-15. */
19170 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
19172 /* iWMMXt control registers - p1, c0-3. */
19173 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
19174 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
19175 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
19176 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
19178 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19179 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
19180 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
19181 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
19182 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
19184 /* XScale accumulator registers. */
19185 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
19191 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19192 within psr_required_here. */
19193 static const struct asm_psr psrs[] =
19195 /* Backward compatibility notation. Note that "all" is no longer
19196 truly all possible PSR bits. */
19197 {"all", PSR_c | PSR_f},
19201 /* Individual flags. */
19207 /* Combinations of flags. */
19208 {"fs", PSR_f | PSR_s},
19209 {"fx", PSR_f | PSR_x},
19210 {"fc", PSR_f | PSR_c},
19211 {"sf", PSR_s | PSR_f},
19212 {"sx", PSR_s | PSR_x},
19213 {"sc", PSR_s | PSR_c},
19214 {"xf", PSR_x | PSR_f},
19215 {"xs", PSR_x | PSR_s},
19216 {"xc", PSR_x | PSR_c},
19217 {"cf", PSR_c | PSR_f},
19218 {"cs", PSR_c | PSR_s},
19219 {"cx", PSR_c | PSR_x},
19220 {"fsx", PSR_f | PSR_s | PSR_x},
19221 {"fsc", PSR_f | PSR_s | PSR_c},
19222 {"fxs", PSR_f | PSR_x | PSR_s},
19223 {"fxc", PSR_f | PSR_x | PSR_c},
19224 {"fcs", PSR_f | PSR_c | PSR_s},
19225 {"fcx", PSR_f | PSR_c | PSR_x},
19226 {"sfx", PSR_s | PSR_f | PSR_x},
19227 {"sfc", PSR_s | PSR_f | PSR_c},
19228 {"sxf", PSR_s | PSR_x | PSR_f},
19229 {"sxc", PSR_s | PSR_x | PSR_c},
19230 {"scf", PSR_s | PSR_c | PSR_f},
19231 {"scx", PSR_s | PSR_c | PSR_x},
19232 {"xfs", PSR_x | PSR_f | PSR_s},
19233 {"xfc", PSR_x | PSR_f | PSR_c},
19234 {"xsf", PSR_x | PSR_s | PSR_f},
19235 {"xsc", PSR_x | PSR_s | PSR_c},
19236 {"xcf", PSR_x | PSR_c | PSR_f},
19237 {"xcs", PSR_x | PSR_c | PSR_s},
19238 {"cfs", PSR_c | PSR_f | PSR_s},
19239 {"cfx", PSR_c | PSR_f | PSR_x},
19240 {"csf", PSR_c | PSR_s | PSR_f},
19241 {"csx", PSR_c | PSR_s | PSR_x},
19242 {"cxf", PSR_c | PSR_x | PSR_f},
19243 {"cxs", PSR_c | PSR_x | PSR_s},
19244 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
19245 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
19246 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
19247 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
19248 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
19249 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
19250 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
19251 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
19252 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
19253 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
19254 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
19255 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
19256 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
19257 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
19258 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
19259 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
19260 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
19261 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
19262 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
19263 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
19264 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
19265 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
19266 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
19267 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
19270 /* Table of V7M psr names. */
19271 static const struct asm_psr v7m_psrs[] =
19273 {"apsr", 0x0 }, {"APSR", 0x0 },
19274 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19275 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19276 {"psr", 0x3 }, {"PSR", 0x3 },
19277 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19278 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19279 {"epsr", 0x6 }, {"EPSR", 0x6 },
19280 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19281 {"msp", 0x8 }, {"MSP", 0x8 },
19282 {"psp", 0x9 }, {"PSP", 0x9 },
19283 {"msplim", 0xa }, {"MSPLIM", 0xa },
19284 {"psplim", 0xb }, {"PSPLIM", 0xb },
19285 {"primask", 0x10}, {"PRIMASK", 0x10},
19286 {"basepri", 0x11}, {"BASEPRI", 0x11},
19287 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19288 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19289 {"control", 0x14}, {"CONTROL", 0x14},
19290 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19291 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19292 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19293 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19294 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19295 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19296 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19297 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19298 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19301 /* Table of all shift-in-operand names. */
19302 static const struct asm_shift_name shift_names [] =
19304 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
19305 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
19306 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
19307 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
19308 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
19309 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
19312 /* Table of all explicit relocation names. */
19314 static struct reloc_entry reloc_names[] =
19316 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
19317 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
19318 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
19319 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
19320 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
19321 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
19322 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
19323 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
19324 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
19325 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
19326 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
19327 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
19328 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
19329 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
19330 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
19331 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
19332 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
19333 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
19334 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
19335 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
19336 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
19337 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
19338 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
19339 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
19340 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
19341 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
19342 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
19346 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19347 static const struct asm_cond conds[] =
19351 {"cs", 0x2}, {"hs", 0x2},
19352 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19366 #define UL_BARRIER(L,U,CODE,FEAT) \
19367 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19368 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19370 static struct asm_barrier_opt barrier_opt_names[] =
19372 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
19373 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
19374 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
19375 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
19376 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
19377 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
19378 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
19379 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
19380 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
19381 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
19382 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
19383 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
19384 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
19385 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
19386 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
19387 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
19392 /* Table of ARM-format instructions. */
19394 /* Macros for gluing together operand strings. N.B. In all cases
19395 other than OPS0, the trailing OP_stop comes from default
19396 zero-initialization of the unspecified elements of the array. */
19397 #define OPS0() { OP_stop, }
19398 #define OPS1(a) { OP_##a, }
19399 #define OPS2(a,b) { OP_##a,OP_##b, }
19400 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19401 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19402 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19403 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19405 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19406 This is useful when mixing operands for ARM and THUMB, i.e. using the
19407 MIX_ARM_THUMB_OPERANDS macro.
19408 In order to use these macros, prefix the number of operands with _
19410 #define OPS_1(a) { a, }
19411 #define OPS_2(a,b) { a,b, }
19412 #define OPS_3(a,b,c) { a,b,c, }
19413 #define OPS_4(a,b,c,d) { a,b,c,d, }
19414 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19415 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19417 /* These macros abstract out the exact format of the mnemonic table and
19418 save some repeated characters. */
19420 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19421 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19422 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19423 THUMB_VARIANT, do_##ae, do_##te }
19425 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19426 a T_MNEM_xyz enumerator. */
19427 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19428 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19429 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19430 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19432 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19433 infix after the third character. */
19434 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19435 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19436 THUMB_VARIANT, do_##ae, do_##te }
19437 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19438 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19439 THUMB_VARIANT, do_##ae, do_##te }
19440 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19441 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19442 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19443 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19444 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19445 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19446 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19447 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19449 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19450 field is still 0xE. Many of the Thumb variants can be executed
19451 conditionally, so this is checked separately. */
19452 #define TUE(mnem, op, top, nops, ops, ae, te) \
19453 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19454 THUMB_VARIANT, do_##ae, do_##te }
19456 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19457 Used by mnemonics that have very minimal differences in the encoding for
19458 ARM and Thumb variants and can be handled in a common function. */
19459 #define TUEc(mnem, op, top, nops, ops, en) \
19460 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19461 THUMB_VARIANT, do_##en, do_##en }
19463 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19464 condition code field. */
19465 #define TUF(mnem, op, top, nops, ops, ae, te) \
19466 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19467 THUMB_VARIANT, do_##ae, do_##te }
19469 /* ARM-only variants of all the above. */
19470 #define CE(mnem, op, nops, ops, ae) \
19471 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19473 #define C3(mnem, op, nops, ops, ae) \
19474 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19476 /* Thumb-only variants of TCE and TUE. */
19477 #define ToC(mnem, top, nops, ops, te) \
19478 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19481 #define ToU(mnem, top, nops, ops, te) \
19482 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19485 /* Legacy mnemonics that always have conditional infix after the third
19487 #define CL(mnem, op, nops, ops, ae) \
19488 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19489 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19491 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19492 #define cCE(mnem, op, nops, ops, ae) \
19493 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19495 /* Legacy coprocessor instructions where conditional infix and conditional
19496 suffix are ambiguous. For consistency this includes all FPA instructions,
19497 not just the potentially ambiguous ones. */
19498 #define cCL(mnem, op, nops, ops, ae) \
19499 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19500 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19502 /* Coprocessor, takes either a suffix or a position-3 infix
19503 (for an FPA corner case). */
19504 #define C3E(mnem, op, nops, ops, ae) \
19505 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19506 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19508 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19509 { m1 #m2 m3, OPS##nops ops, \
19510 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19511 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19513 #define CM(m1, m2, op, nops, ops, ae) \
19514 xCM_ (m1, , m2, op, nops, ops, ae), \
19515 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19516 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19517 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19518 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19519 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19520 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19521 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19522 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19523 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19524 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19525 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19526 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19527 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19528 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19529 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19530 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19531 xCM_ (m1, le, m2, op, nops, ops, ae), \
19532 xCM_ (m1, al, m2, op, nops, ops, ae)
19534 #define UE(mnem, op, nops, ops, ae) \
19535 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19537 #define UF(mnem, op, nops, ops, ae) \
19538 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19540 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19541 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19542 use the same encoding function for each. */
19543 #define NUF(mnem, op, nops, ops, enc) \
19544 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19545 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19547 /* Neon data processing, version which indirects through neon_enc_tab for
19548 the various overloaded versions of opcodes. */
19549 #define nUF(mnem, op, nops, ops, enc) \
19550 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19551 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19553 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19555 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19556 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19557 THUMB_VARIANT, do_##enc, do_##enc }
19559 #define NCE(mnem, op, nops, ops, enc) \
19560 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19562 #define NCEF(mnem, op, nops, ops, enc) \
19563 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19565 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19566 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19567 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19568 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19570 #define nCE(mnem, op, nops, ops, enc) \
19571 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19573 #define nCEF(mnem, op, nops, ops, enc) \
19574 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19578 static const struct asm_opcode insns[] =
19580 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19581 #define THUMB_VARIANT & arm_ext_v4t
19582 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
19583 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
19584 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
19585 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
19586 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
19587 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
19588 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
19589 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
19590 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
19591 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
19592 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
19593 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
19594 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
19595 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
19596 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
19597 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
19599 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19600 for setting PSR flag bits. They are obsolete in V6 and do not
19601 have Thumb equivalents. */
19602 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19603 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
19604 CL("tstp", 110f000, 2, (RR, SH), cmp),
19605 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19606 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
19607 CL("cmpp", 150f000, 2, (RR, SH), cmp),
19608 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19609 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
19610 CL("cmnp", 170f000, 2, (RR, SH), cmp),
19612 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
19613 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
19614 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
19615 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
19617 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
19618 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19619 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
19621 OP_ADDRGLDR),ldst, t_ldst),
19622 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
19624 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19625 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19626 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19627 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19628 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19629 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19631 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
19632 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
19635 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
19636 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
19637 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
19638 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
19640 /* Thumb-compatibility pseudo ops. */
19641 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
19642 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
19643 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
19644 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
19645 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
19646 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
19647 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
19648 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
19649 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
19650 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
19651 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
19652 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
19654 /* These may simplify to neg. */
19655 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
19656 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
19658 #undef THUMB_VARIANT
19659 #define THUMB_VARIANT & arm_ext_os
19661 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
19662 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
19664 #undef THUMB_VARIANT
19665 #define THUMB_VARIANT & arm_ext_v6
19667 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
19669 /* V1 instructions with no Thumb analogue prior to V6T2. */
19670 #undef THUMB_VARIANT
19671 #define THUMB_VARIANT & arm_ext_v6t2
19673 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19674 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
19675 CL("teqp", 130f000, 2, (RR, SH), cmp),
19677 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19678 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19679 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
19680 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
19682 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19683 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19685 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19686 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
19688 /* V1 instructions with no Thumb analogue at all. */
19689 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
19690 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
19692 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
19693 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
19694 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
19695 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
19696 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
19697 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
19698 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
19699 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
19702 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19703 #undef THUMB_VARIANT
19704 #define THUMB_VARIANT & arm_ext_v4t
19706 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19707 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
19709 #undef THUMB_VARIANT
19710 #define THUMB_VARIANT & arm_ext_v6t2
19712 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19713 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
19715 /* Generic coprocessor instructions. */
19716 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19717 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19718 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19719 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19720 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19721 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19722 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
19725 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19727 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19728 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
19731 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19732 #undef THUMB_VARIANT
19733 #define THUMB_VARIANT & arm_ext_msr
19735 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
19736 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
19739 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19740 #undef THUMB_VARIANT
19741 #define THUMB_VARIANT & arm_ext_v6t2
19743 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19744 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19745 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19746 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19747 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19748 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19749 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
19750 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
19753 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19754 #undef THUMB_VARIANT
19755 #define THUMB_VARIANT & arm_ext_v4t
19757 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19758 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19759 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19760 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19761 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19762 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
19765 #define ARM_VARIANT & arm_ext_v4t_5
19767 /* ARM Architecture 4T. */
19768 /* Note: bx (and blx) are required on V5, even if the processor does
19769 not support Thumb. */
19770 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
19773 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19774 #undef THUMB_VARIANT
19775 #define THUMB_VARIANT & arm_ext_v5t
19777 /* Note: blx has 2 variants; the .value coded here is for
19778 BLX(2). Only this variant has conditional execution. */
19779 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
19780 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
19782 #undef THUMB_VARIANT
19783 #define THUMB_VARIANT & arm_ext_v6t2
19785 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
19786 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19787 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19788 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19789 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
19790 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
19791 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19792 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
19795 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19796 #undef THUMB_VARIANT
19797 #define THUMB_VARIANT & arm_ext_v5exp
19799 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19800 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19801 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19802 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19804 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19805 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
19807 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19808 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19809 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19810 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
19812 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19813 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19814 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19815 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19817 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19818 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19820 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19821 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19822 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19823 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
19826 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19827 #undef THUMB_VARIANT
19828 #define THUMB_VARIANT & arm_ext_v6t2
19830 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
19831 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
19833 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
19834 ADDRGLDRS), ldrd, t_ldstd),
19836 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19837 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19840 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19842 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
19845 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19846 #undef THUMB_VARIANT
19847 #define THUMB_VARIANT & arm_ext_v6
19849 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
19850 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
19851 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19852 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19853 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
19854 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19855 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19856 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19857 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19858 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
19860 #undef THUMB_VARIANT
19861 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19863 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
19864 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
19866 #undef THUMB_VARIANT
19867 #define THUMB_VARIANT & arm_ext_v6t2
19869 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19870 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
19872 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
19873 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
19875 /* ARM V6 not included in V7M. */
19876 #undef THUMB_VARIANT
19877 #define THUMB_VARIANT & arm_ext_v6_notm
19878 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19879 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19880 UF(rfeib, 9900a00, 1, (RRw), rfe),
19881 UF(rfeda, 8100a00, 1, (RRw), rfe),
19882 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19883 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
19884 UF(rfefa, 8100a00, 1, (RRw), rfe),
19885 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
19886 UF(rfeed, 9900a00, 1, (RRw), rfe),
19887 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19888 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19889 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
19890 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
19891 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
19892 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
19893 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
19894 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19895 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
19896 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
19898 /* ARM V6 not included in V7M (eg. integer SIMD). */
19899 #undef THUMB_VARIANT
19900 #define THUMB_VARIANT & arm_ext_v6_dsp
19901 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
19902 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
19903 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19904 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19905 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19906 /* Old name for QASX. */
19907 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19908 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19909 /* Old name for QSAX. */
19910 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19911 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19912 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19913 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19914 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19915 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19916 /* Old name for SASX. */
19917 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19918 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19919 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19920 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19921 /* Old name for SHASX. */
19922 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19923 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19924 /* Old name for SHSAX. */
19925 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19926 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19927 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19928 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19929 /* Old name for SSAX. */
19930 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19931 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19932 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19933 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19934 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19935 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19936 /* Old name for UASX. */
19937 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19938 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19939 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19940 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19941 /* Old name for UHASX. */
19942 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19943 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19944 /* Old name for UHSAX. */
19945 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19946 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19947 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19948 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19949 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19950 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19951 /* Old name for UQASX. */
19952 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19953 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19954 /* Old name for UQSAX. */
19955 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19956 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19957 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19958 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19959 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19960 /* Old name for USAX. */
19961 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19962 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19963 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19964 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19965 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19966 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19967 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19968 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19969 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
19970 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
19971 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
19972 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19973 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19974 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19975 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19976 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19977 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19978 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19979 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
19980 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19981 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19982 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19983 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19984 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19985 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19986 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19987 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19988 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19989 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19990 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
19991 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
19992 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
19993 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
19994 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
19997 #define ARM_VARIANT & arm_ext_v6k
19998 #undef THUMB_VARIANT
19999 #define THUMB_VARIANT & arm_ext_v6k
20001 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
20002 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
20003 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
20004 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
20006 #undef THUMB_VARIANT
20007 #define THUMB_VARIANT & arm_ext_v6_notm
20008 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
20010 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
20011 RRnpcb), strexd, t_strexd),
20013 #undef THUMB_VARIANT
20014 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20015 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
20017 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
20019 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
20021 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
20023 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
20026 #define ARM_VARIANT & arm_ext_sec
20027 #undef THUMB_VARIANT
20028 #define THUMB_VARIANT & arm_ext_sec
20030 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
20033 #define ARM_VARIANT & arm_ext_virt
20034 #undef THUMB_VARIANT
20035 #define THUMB_VARIANT & arm_ext_virt
20037 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
20038 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
20041 #define ARM_VARIANT & arm_ext_pan
20042 #undef THUMB_VARIANT
20043 #define THUMB_VARIANT & arm_ext_pan
20045 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
20048 #define ARM_VARIANT & arm_ext_v6t2
20049 #undef THUMB_VARIANT
20050 #define THUMB_VARIANT & arm_ext_v6t2
20052 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
20053 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
20054 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
20055 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
20057 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
20058 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
20060 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
20061 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
20062 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
20063 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
20066 #define ARM_VARIANT & arm_ext_v3
20067 #undef THUMB_VARIANT
20068 #define THUMB_VARIANT & arm_ext_v6t2
20070 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
20071 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
20072 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
20075 #define ARM_VARIANT & arm_ext_v6t2
20076 #undef THUMB_VARIANT
20077 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20078 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
20079 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
20081 /* Thumb-only instructions. */
20083 #define ARM_VARIANT NULL
20084 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
20085 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
20087 /* ARM does not really have an IT instruction, so always allow it.
20088 The opcode is copied from Thumb in order to allow warnings in
20089 -mimplicit-it=[never | arm] modes. */
20091 #define ARM_VARIANT & arm_ext_v1
20092 #undef THUMB_VARIANT
20093 #define THUMB_VARIANT & arm_ext_v6t2
20095 TUE("it", bf08, bf08, 1, (COND), it, t_it),
20096 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
20097 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
20098 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
20099 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
20100 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
20101 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
20102 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
20103 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
20104 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
20105 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
20106 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
20107 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
20108 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
20109 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
20110 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20111 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
20112 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
20114 /* Thumb2 only instructions. */
20116 #define ARM_VARIANT NULL
20118 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
20119 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
20120 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
20121 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
20122 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
20123 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
20125 /* Hardware division instructions. */
20127 #define ARM_VARIANT & arm_ext_adiv
20128 #undef THUMB_VARIANT
20129 #define THUMB_VARIANT & arm_ext_div
20131 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
20132 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
20134 /* ARM V6M/V7 instructions. */
20136 #define ARM_VARIANT & arm_ext_barrier
20137 #undef THUMB_VARIANT
20138 #define THUMB_VARIANT & arm_ext_barrier
20140 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
20141 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
20142 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
20144 /* ARM V7 instructions. */
20146 #define ARM_VARIANT & arm_ext_v7
20147 #undef THUMB_VARIANT
20148 #define THUMB_VARIANT & arm_ext_v7
20150 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
20151 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
20154 #define ARM_VARIANT & arm_ext_mp
20155 #undef THUMB_VARIANT
20156 #define THUMB_VARIANT & arm_ext_mp
20158 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
20160 /* AArchv8 instructions. */
20162 #define ARM_VARIANT & arm_ext_v8
20164 /* Instructions shared between armv8-a and armv8-m. */
20165 #undef THUMB_VARIANT
20166 #define THUMB_VARIANT & arm_ext_atomics
20168 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
20169 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
20170 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
20171 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
20172 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
20173 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
20174 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
20175 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
20176 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
20177 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
20179 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
20181 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
20183 #undef THUMB_VARIANT
20184 #define THUMB_VARIANT & arm_ext_v8
20186 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
20187 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
20188 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
20190 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
20192 /* ARMv8 T32 only. */
20194 #define ARM_VARIANT NULL
20195 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
20196 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
20197 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
20199 /* FP for ARMv8. */
20201 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20202 #undef THUMB_VARIANT
20203 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20205 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
20206 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
20207 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
20208 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
20209 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
20210 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
20211 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
20212 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
20213 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
20214 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
20215 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
20216 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
20217 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
20218 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
20219 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
20220 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
20221 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
20223 /* Crypto v1 extensions. */
20225 #define ARM_VARIANT & fpu_crypto_ext_armv8
20226 #undef THUMB_VARIANT
20227 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20229 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
20230 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
20231 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
20232 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
20233 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
20234 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
20235 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
20236 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
20237 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
20238 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
20239 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
20240 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
20241 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
20242 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
20245 #define ARM_VARIANT & crc_ext_armv8
20246 #undef THUMB_VARIANT
20247 #define THUMB_VARIANT & crc_ext_armv8
20248 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
20249 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
20250 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
20251 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
20252 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
20253 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
20255 /* ARMv8.2 RAS extension. */
20257 #define ARM_VARIANT & arm_ext_ras
20258 #undef THUMB_VARIANT
20259 #define THUMB_VARIANT & arm_ext_ras
20260 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
20263 #define ARM_VARIANT & arm_ext_v8_3
20264 #undef THUMB_VARIANT
20265 #define THUMB_VARIANT & arm_ext_v8_3
20266 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
20267 NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla),
20268 NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd),
20271 #define ARM_VARIANT & fpu_neon_ext_dotprod
20272 #undef THUMB_VARIANT
20273 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20274 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
20275 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
20278 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20279 #undef THUMB_VARIANT
20280 #define THUMB_VARIANT NULL
20282 cCE("wfs", e200110, 1, (RR), rd),
20283 cCE("rfs", e300110, 1, (RR), rd),
20284 cCE("wfc", e400110, 1, (RR), rd),
20285 cCE("rfc", e500110, 1, (RR), rd),
20287 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
20288 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
20289 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
20290 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
20292 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
20293 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
20294 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
20295 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
20297 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
20298 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
20299 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
20300 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
20301 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
20302 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
20303 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
20304 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
20305 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
20306 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
20307 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
20308 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
20310 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
20311 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
20312 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
20313 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
20314 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
20315 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
20316 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
20317 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
20318 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
20319 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
20320 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
20321 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
20323 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
20324 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
20325 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
20326 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
20327 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
20328 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
20329 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
20330 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
20331 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
20332 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
20333 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
20334 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
20336 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
20337 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
20338 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
20339 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
20340 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
20341 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
20342 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
20343 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
20344 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
20345 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
20346 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
20347 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
20349 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
20350 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
20351 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
20352 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
20353 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
20354 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
20355 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
20356 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
20357 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
20358 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
20359 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
20360 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
20362 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
20363 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
20364 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
20365 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
20366 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
20367 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
20368 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
20369 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
20370 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
20371 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
20372 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
20373 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
20375 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
20376 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
20377 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
20378 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
20379 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
20380 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
20381 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
20382 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
20383 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
20384 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
20385 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
20386 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
20388 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
20389 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
20390 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
20391 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
20392 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
20393 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
20394 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
20395 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
20396 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
20397 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
20398 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
20399 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
20401 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
20402 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
20403 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
20404 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
20405 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
20406 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
20407 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
20408 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
20409 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
20410 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
20411 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
20412 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
20414 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
20415 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
20416 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
20417 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
20418 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
20419 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
20420 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
20421 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
20422 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
20423 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
20424 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
20425 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
20427 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
20428 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
20429 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
20430 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
20431 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
20432 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
20433 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
20434 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
20435 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
20436 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
20437 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
20438 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
20440 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
20441 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
20442 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
20443 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
20444 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
20445 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
20446 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
20447 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
20448 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
20449 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
20450 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
20451 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
20453 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
20454 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
20455 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
20456 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
20457 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
20458 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
20459 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
20460 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
20461 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
20462 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
20463 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
20464 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
20466 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
20467 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
20468 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
20469 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
20470 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
20471 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
20472 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
20473 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
20474 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
20475 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
20476 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
20477 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
20479 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
20480 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
20481 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
20482 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
20483 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
20484 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
20485 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
20486 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
20487 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
20488 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
20489 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
20490 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
20492 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
20493 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
20494 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
20495 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
20496 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
20497 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
20498 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
20499 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
20500 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
20501 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
20502 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
20503 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
20505 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
20506 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
20507 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
20508 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
20509 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
20510 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20511 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20512 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20513 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
20514 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
20515 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
20516 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
20518 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
20519 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
20520 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
20521 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
20522 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
20523 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20524 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20525 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20526 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
20527 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
20528 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
20529 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
20531 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
20532 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
20533 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
20534 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
20535 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
20536 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20537 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20538 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20539 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
20540 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
20541 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
20542 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
20544 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
20545 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
20546 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
20547 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
20548 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
20549 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20550 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20551 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20552 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
20553 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
20554 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
20555 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
20557 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
20558 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
20559 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
20560 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
20561 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
20562 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20563 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20564 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20565 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
20566 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
20567 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
20568 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
20570 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
20571 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
20572 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
20573 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
20574 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
20575 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20576 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20577 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20578 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
20579 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
20580 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
20581 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
20583 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
20584 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
20585 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
20586 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
20587 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
20588 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20589 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20590 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20591 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
20592 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
20593 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
20594 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
20596 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
20597 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
20598 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
20599 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
20600 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
20601 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20602 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20603 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20604 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
20605 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
20606 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
20607 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
20609 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
20610 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
20611 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
20612 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
20613 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
20614 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20615 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20616 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20617 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
20618 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
20619 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
20620 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
20622 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
20623 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
20624 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
20625 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
20626 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
20627 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20628 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20629 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20630 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
20631 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
20632 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
20633 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
20635 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20636 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20637 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20638 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20639 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20640 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20641 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20642 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20643 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20644 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20645 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20646 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20648 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20649 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20650 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20651 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20652 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20653 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20654 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20655 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20656 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20657 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20658 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20659 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20661 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
20662 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
20663 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
20664 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
20665 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
20666 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
20667 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
20668 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
20669 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
20670 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
20671 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
20672 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
20674 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
20675 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
20676 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
20677 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
20679 cCL("flts", e000110, 2, (RF, RR), rn_rd),
20680 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
20681 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
20682 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
20683 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
20684 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
20685 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
20686 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
20687 cCL("flte", e080110, 2, (RF, RR), rn_rd),
20688 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
20689 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
20690 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
20692 /* The implementation of the FIX instruction is broken on some
20693 assemblers, in that it accepts a precision specifier as well as a
20694 rounding specifier, despite the fact that this is meaningless.
20695 To be more compatible, we accept it as well, though of course it
20696 does not set any bits. */
20697 cCE("fix", e100110, 2, (RR, RF), rd_rm),
20698 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
20699 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
20700 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
20701 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
20702 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
20703 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
20704 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
20705 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
20706 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
20707 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
20708 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
20709 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
20711 /* Instructions that were new with the real FPA, call them V2. */
20713 #define ARM_VARIANT & fpu_fpa_ext_v2
20715 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20716 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20717 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20718 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20719 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20720 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
20723 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20725 /* Moves and type conversions. */
20726 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
20727 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
20728 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
20729 cCE("fmstat", ef1fa10, 0, (), noargs),
20730 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
20731 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
20732 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
20733 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
20734 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
20735 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20736 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
20737 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
20738 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
20739 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
20741 /* Memory operations. */
20742 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20743 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
20744 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20745 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20746 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20747 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20748 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20749 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20750 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20751 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20752 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20753 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
20754 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20755 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
20756 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20757 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
20758 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20759 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
20761 /* Monadic operations. */
20762 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
20763 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
20764 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
20766 /* Dyadic operations. */
20767 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20768 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20769 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20770 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20771 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20772 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20773 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20774 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20775 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20778 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
20779 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
20780 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
20781 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
20783 /* Double precision load/store are still present on single precision
20784 implementations. */
20785 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20786 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
20787 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20788 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20789 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20790 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20791 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20792 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
20793 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20794 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
20797 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20799 /* Moves and type conversions. */
20800 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20801 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20802 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20803 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
20804 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
20805 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
20806 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
20807 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
20808 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
20809 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20810 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20811 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
20812 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
20814 /* Monadic operations. */
20815 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20816 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20817 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20819 /* Dyadic operations. */
20820 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20821 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20822 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20823 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20824 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20825 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20826 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20827 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20828 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20831 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
20832 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
20833 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
20834 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
20837 #define ARM_VARIANT & fpu_vfp_ext_v2
20839 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
20840 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
20841 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
20842 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
20844 /* Instructions which may belong to either the Neon or VFP instruction sets.
20845 Individual encoder functions perform additional architecture checks. */
20847 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20848 #undef THUMB_VARIANT
20849 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20851 /* These mnemonics are unique to VFP. */
20852 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
20853 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
20854 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20855 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20856 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20857 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20858 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
20859 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
20860 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
20861 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
20863 /* Mnemonics shared by Neon and VFP. */
20864 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
20865 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20866 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
20868 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20869 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
20871 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20872 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
20874 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20875 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20876 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20877 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20878 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20879 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
20880 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20881 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
20883 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
20884 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
20885 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
20886 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
20889 /* NOTE: All VMOV encoding is special-cased! */
20890 NCE(vmov, 0, 1, (VMOV), neon_mov),
20891 NCE(vmovq, 0, 1, (VMOV), neon_mov),
20894 #define ARM_VARIANT & arm_ext_fp16
20895 #undef THUMB_VARIANT
20896 #define THUMB_VARIANT & arm_ext_fp16
20897 /* New instructions added from v8.2, allowing the extraction and insertion of
20898 the upper 16 bits of a 32-bit vector register. */
20899 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
20900 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
20902 /* New backported fma/fms instructions optional in v8.2. */
20903 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
20904 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
20906 #undef THUMB_VARIANT
20907 #define THUMB_VARIANT & fpu_neon_ext_v1
20909 #define ARM_VARIANT & fpu_neon_ext_v1
20911 /* Data processing with three registers of the same length. */
20912 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20913 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
20914 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
20915 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20916 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20917 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20918 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20919 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
20920 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
20921 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20922 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20923 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20924 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
20925 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
20926 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20927 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20928 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
20929 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
20930 /* If not immediate, fall back to neon_dyadic_i64_su.
20931 shl_imm should accept I8 I16 I32 I64,
20932 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20933 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
20934 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
20935 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
20936 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
20937 /* Logic ops, types optional & ignored. */
20938 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20939 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20940 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20941 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20942 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20943 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20944 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
20945 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
20946 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
20947 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
20948 /* Bitfield ops, untyped. */
20949 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20950 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20951 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20952 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20953 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
20954 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
20955 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20956 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20957 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20958 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20959 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20960 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
20961 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
20962 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20963 back to neon_dyadic_if_su. */
20964 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20965 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20966 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
20967 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
20968 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20969 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20970 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
20971 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
20972 /* Comparison. Type I8 I16 I32 F32. */
20973 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
20974 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
20975 /* As above, D registers only. */
20976 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20977 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
20978 /* Int and float variants, signedness unimportant. */
20979 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20980 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
20981 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
20982 /* Add/sub take types I8 I16 I32 I64 F32. */
20983 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20984 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
20985 /* vtst takes sizes 8, 16, 32. */
20986 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
20987 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
20988 /* VMUL takes I8 I16 I32 F32 P8. */
20989 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
20990 /* VQD{R}MULH takes S16 S32. */
20991 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20992 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20993 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
20994 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
20995 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20996 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20997 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
20998 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
20999 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
21000 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
21001 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
21002 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
21003 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
21004 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
21005 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
21006 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
21007 /* ARM v8.1 extension. */
21008 nUF (vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
21009 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
21010 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
21011 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
21013 /* Two address, int/float. Types S8 S16 S32 F32. */
21014 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
21015 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
21017 /* Data processing with two registers and a shift amount. */
21018 /* Right shifts, and variants with rounding.
21019 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
21020 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
21021 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
21022 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
21023 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
21024 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
21025 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
21026 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
21027 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
21028 /* Shift and insert. Sizes accepted 8 16 32 64. */
21029 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
21030 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
21031 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
21032 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
21033 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21034 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
21035 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
21036 /* Right shift immediate, saturating & narrowing, with rounding variants.
21037 Types accepted S16 S32 S64 U16 U32 U64. */
21038 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
21039 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
21040 /* As above, unsigned. Types accepted S16 S32 S64. */
21041 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
21042 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
21043 /* Right shift narrowing. Types accepted I16 I32 I64. */
21044 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
21045 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
21046 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21047 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
21048 /* CVT with optional immediate for fixed-point variant. */
21049 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
21051 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
21052 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
21054 /* Data processing, three registers of different lengths. */
21055 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21056 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
21057 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
21058 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
21059 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
21060 /* If not scalar, fall back to neon_dyadic_long.
21061 Vector types as above, scalar types S16 S32 U16 U32. */
21062 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
21063 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
21064 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21065 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
21066 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
21067 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21068 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
21069 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
21070 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
21071 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
21072 /* Saturating doubling multiplies. Types S16 S32. */
21073 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
21074 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
21075 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
21076 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21077 S16 S32 U16 U32. */
21078 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
21080 /* Extract. Size 8. */
21081 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
21082 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
21084 /* Two registers, miscellaneous. */
21085 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21086 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
21087 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
21088 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
21089 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
21090 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
21091 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
21092 /* Vector replicate. Sizes 8 16 32. */
21093 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
21094 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
21095 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21096 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
21097 /* VMOVN. Types I16 I32 I64. */
21098 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
21099 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21100 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
21101 /* VQMOVUN. Types S16 S32 S64. */
21102 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
21103 /* VZIP / VUZP. Sizes 8 16 32. */
21104 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
21105 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
21106 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
21107 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
21108 /* VQABS / VQNEG. Types S8 S16 S32. */
21109 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
21110 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
21111 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
21112 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
21113 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21114 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
21115 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
21116 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
21117 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
21118 /* Reciprocal estimates. Types U32 F16 F32. */
21119 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
21120 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
21121 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
21122 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
21123 /* VCLS. Types S8 S16 S32. */
21124 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
21125 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
21126 /* VCLZ. Types I8 I16 I32. */
21127 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
21128 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
21129 /* VCNT. Size 8. */
21130 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
21131 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
21132 /* Two address, untyped. */
21133 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
21134 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
21135 /* VTRN. Sizes 8 16 32. */
21136 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
21137 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
21139 /* Table lookup. Size 8. */
21140 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
21141 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
21143 #undef THUMB_VARIANT
21144 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21146 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21148 /* Neon element/structure load/store. */
21149 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
21150 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
21151 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
21152 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
21153 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
21154 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
21155 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
21156 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
21158 #undef THUMB_VARIANT
21159 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21161 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21162 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
21163 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
21164 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
21165 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
21166 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
21167 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
21168 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
21169 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
21170 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
21172 #undef THUMB_VARIANT
21173 #define THUMB_VARIANT & fpu_vfp_ext_v3
21175 #define ARM_VARIANT & fpu_vfp_ext_v3
21177 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21178 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21179 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21180 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21181 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21182 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21183 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21184 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21185 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21188 #define ARM_VARIANT & fpu_vfp_ext_fma
21189 #undef THUMB_VARIANT
21190 #define THUMB_VARIANT & fpu_vfp_ext_fma
21191 /* Mnemonics shared by Neon and VFP. These are included in the
21192 VFP FMA variant; NEON and VFP FMA always includes the NEON
21193 FMA instructions. */
21194 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
21195 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
21196 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21197 the v form should always be used. */
21198 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
21199 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
21200 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
21201 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
21202 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
21203 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
21205 #undef THUMB_VARIANT
21207 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21209 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21210 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21211 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21212 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21213 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21214 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
21215 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
21216 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
21219 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21221 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
21222 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
21223 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
21224 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
21225 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
21226 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
21227 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
21228 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
21229 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
21230 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
21231 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
21232 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
21233 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21234 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21235 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21236 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
21237 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
21238 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
21239 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
21240 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
21241 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21242 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21243 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21244 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21245 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21246 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
21247 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
21248 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
21249 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21250 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
21251 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
21252 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
21253 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
21254 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
21255 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
21256 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
21257 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
21258 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21259 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21260 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21261 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21262 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21263 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21264 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21265 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21266 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21267 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
21268 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21269 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21270 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21271 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21272 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21273 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21274 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21275 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21276 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21277 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21278 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21279 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21280 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21281 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21282 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21283 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21284 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21285 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21286 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21287 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
21288 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
21289 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
21290 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
21291 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21292 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21293 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21294 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21295 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21296 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21297 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21298 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21299 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21300 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21301 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21302 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21303 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21304 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21305 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21306 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21307 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21308 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21309 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
21310 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21311 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21312 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21313 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21314 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21315 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21316 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21317 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21318 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21319 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21320 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21321 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21322 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21323 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21324 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21325 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21326 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21327 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21328 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21329 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21330 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21331 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
21332 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21333 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21334 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21335 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21336 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21337 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21338 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21339 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21340 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21341 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21342 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21343 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21344 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21345 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21346 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21347 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21348 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
21349 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
21350 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
21351 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
21352 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
21353 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
21354 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21355 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21356 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21357 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21358 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21359 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21360 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21361 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21362 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21363 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
21364 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
21365 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
21366 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
21367 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
21368 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
21369 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21370 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21371 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21372 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
21373 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
21374 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
21375 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
21376 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
21377 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
21378 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21379 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21380 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21381 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21382 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
21385 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21387 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
21388 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
21389 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
21390 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
21391 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
21392 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
21393 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21394 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21395 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21396 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21397 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21398 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21399 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21400 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21401 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21402 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21403 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21404 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21405 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21406 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21407 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
21408 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21409 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21410 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21411 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21412 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21413 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21414 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21415 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21416 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21417 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21418 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21419 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21420 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21421 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21422 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21423 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21424 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21425 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21426 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21427 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21428 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21429 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21430 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21431 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21432 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21433 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21434 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21435 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21436 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21437 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21438 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21439 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21440 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21441 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21442 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21443 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21446 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21448 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
21449 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
21450 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
21451 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
21452 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
21453 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
21454 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
21455 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
21456 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
21457 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
21458 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
21459 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
21460 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
21461 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
21462 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
21463 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
21464 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
21465 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
21466 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
21467 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
21468 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
21469 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
21470 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
21471 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21472 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
21473 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
21474 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
21475 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
21476 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
21477 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21478 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
21479 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
21480 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
21481 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
21482 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
21483 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
21484 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
21485 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
21486 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
21487 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21488 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
21489 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
21490 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
21491 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21492 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
21493 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
21494 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
21495 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
21496 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
21497 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
21498 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
21499 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
21500 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
21501 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
21502 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
21503 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
21504 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
21505 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
21506 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
21507 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
21508 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
21509 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
21510 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
21511 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
21512 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
21513 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
21514 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
21515 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
21516 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
21517 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
21518 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
21519 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
21520 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21521 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21522 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
21523 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
21525 /* ARMv8.5-A instructions. */
21527 #define ARM_VARIANT & arm_ext_sb
21528 #undef THUMB_VARIANT
21529 #define THUMB_VARIANT & arm_ext_sb
21530 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
21533 #define ARM_VARIANT & arm_ext_predres
21534 #undef THUMB_VARIANT
21535 #define THUMB_VARIANT & arm_ext_predres
21536 CE("cfprctx", e070f93, 1, (RRnpc), rd),
21537 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
21538 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
21540 /* ARMv8-M instructions. */
21542 #define ARM_VARIANT NULL
21543 #undef THUMB_VARIANT
21544 #define THUMB_VARIANT & arm_ext_v8m
21545 ToU("sg", e97fe97f, 0, (), noargs),
21546 ToC("blxns", 4784, 1, (RRnpc), t_blx),
21547 ToC("bxns", 4704, 1, (RRnpc), t_bx),
21548 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
21549 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
21550 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
21551 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
21553 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21554 instructions behave as nop if no VFP is present. */
21555 #undef THUMB_VARIANT
21556 #define THUMB_VARIANT & arm_ext_v8m_main
21557 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
21558 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
21561 #undef THUMB_VARIANT
21587 /* MD interface: bits in the object file. */
21589 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21590 for use in the a.out file, and stores them in the array pointed to by buf.
21591 This knows about the endian-ness of the target machine and does
21592 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21593 2 (short) and 4 (long) Floating numbers are put out as a series of
21594 LITTLENUMS (shorts, here at least). */
21597 md_number_to_chars (char * buf, valueT val, int n)
21599 if (target_big_endian)
21600 number_to_chars_bigendian (buf, val, n);
21602 number_to_chars_littleendian (buf, val, n);
21606 md_chars_to_number (char * buf, int n)
21609 unsigned char * where = (unsigned char *) buf;
21611 if (target_big_endian)
21616 result |= (*where++ & 255);
21624 result |= (where[n] & 255);
21631 /* MD interface: Sections. */
21633 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21634 that an rs_machine_dependent frag may reach. */
21637 arm_frag_max_var (fragS *fragp)
21639 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21640 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21642 Note that we generate relaxable instructions even for cases that don't
21643 really need it, like an immediate that's a trivial constant. So we're
21644 overestimating the instruction size for some of those cases. Rather
21645 than putting more intelligence here, it would probably be better to
21646 avoid generating a relaxation frag in the first place when it can be
21647 determined up front that a short instruction will suffice. */
21649 gas_assert (fragp->fr_type == rs_machine_dependent);
21653 /* Estimate the size of a frag before relaxing. Assume everything fits in
21657 md_estimate_size_before_relax (fragS * fragp,
21658 segT segtype ATTRIBUTE_UNUSED)
21664 /* Convert a machine dependent frag. */
21667 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
21669 unsigned long insn;
21670 unsigned long old_op;
21678 buf = fragp->fr_literal + fragp->fr_fix;
21680 old_op = bfd_get_16(abfd, buf);
21681 if (fragp->fr_symbol)
21683 exp.X_op = O_symbol;
21684 exp.X_add_symbol = fragp->fr_symbol;
21688 exp.X_op = O_constant;
21690 exp.X_add_number = fragp->fr_offset;
21691 opcode = fragp->fr_subtype;
21694 case T_MNEM_ldr_pc:
21695 case T_MNEM_ldr_pc2:
21696 case T_MNEM_ldr_sp:
21697 case T_MNEM_str_sp:
21704 if (fragp->fr_var == 4)
21706 insn = THUMB_OP32 (opcode);
21707 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
21709 insn |= (old_op & 0x700) << 4;
21713 insn |= (old_op & 7) << 12;
21714 insn |= (old_op & 0x38) << 13;
21716 insn |= 0x00000c00;
21717 put_thumb32_insn (buf, insn);
21718 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
21722 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
21724 pc_rel = (opcode == T_MNEM_ldr_pc2);
21727 if (fragp->fr_var == 4)
21729 insn = THUMB_OP32 (opcode);
21730 insn |= (old_op & 0xf0) << 4;
21731 put_thumb32_insn (buf, insn);
21732 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
21736 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21737 exp.X_add_number -= 4;
21745 if (fragp->fr_var == 4)
21747 int r0off = (opcode == T_MNEM_mov
21748 || opcode == T_MNEM_movs) ? 0 : 8;
21749 insn = THUMB_OP32 (opcode);
21750 insn = (insn & 0xe1ffffff) | 0x10000000;
21751 insn |= (old_op & 0x700) << r0off;
21752 put_thumb32_insn (buf, insn);
21753 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21757 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
21762 if (fragp->fr_var == 4)
21764 insn = THUMB_OP32(opcode);
21765 put_thumb32_insn (buf, insn);
21766 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
21769 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
21773 if (fragp->fr_var == 4)
21775 insn = THUMB_OP32(opcode);
21776 insn |= (old_op & 0xf00) << 14;
21777 put_thumb32_insn (buf, insn);
21778 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
21781 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
21784 case T_MNEM_add_sp:
21785 case T_MNEM_add_pc:
21786 case T_MNEM_inc_sp:
21787 case T_MNEM_dec_sp:
21788 if (fragp->fr_var == 4)
21790 /* ??? Choose between add and addw. */
21791 insn = THUMB_OP32 (opcode);
21792 insn |= (old_op & 0xf0) << 4;
21793 put_thumb32_insn (buf, insn);
21794 if (opcode == T_MNEM_add_pc)
21795 reloc_type = BFD_RELOC_ARM_T32_IMM12;
21797 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21800 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21808 if (fragp->fr_var == 4)
21810 insn = THUMB_OP32 (opcode);
21811 insn |= (old_op & 0xf0) << 4;
21812 insn |= (old_op & 0xf) << 16;
21813 put_thumb32_insn (buf, insn);
21814 if (insn & (1 << 20))
21815 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
21817 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
21820 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
21826 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21827 (enum bfd_reloc_code_real) reloc_type);
21828 fixp->fx_file = fragp->fr_file;
21829 fixp->fx_line = fragp->fr_line;
21830 fragp->fr_fix += fragp->fr_var;
21832 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21833 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
21834 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
21835 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
21838 /* Return the size of a relaxable immediate operand instruction.
21839 SHIFT and SIZE specify the form of the allowable immediate. */
21841 relax_immediate (fragS *fragp, int size, int shift)
21847 /* ??? Should be able to do better than this. */
21848 if (fragp->fr_symbol)
21851 low = (1 << shift) - 1;
21852 mask = (1 << (shift + size)) - (1 << shift);
21853 offset = fragp->fr_offset;
21854 /* Force misaligned offsets to 32-bit variant. */
21857 if (offset & ~mask)
21862 /* Get the address of a symbol during relaxation. */
21864 relaxed_symbol_addr (fragS *fragp, long stretch)
21870 sym = fragp->fr_symbol;
21871 sym_frag = symbol_get_frag (sym);
21872 know (S_GET_SEGMENT (sym) != absolute_section
21873 || sym_frag == &zero_address_frag);
21874 addr = S_GET_VALUE (sym) + fragp->fr_offset;
21876 /* If frag has yet to be reached on this pass, assume it will
21877 move by STRETCH just as we did. If this is not so, it will
21878 be because some frag between grows, and that will force
21882 && sym_frag->relax_marker != fragp->relax_marker)
21886 /* Adjust stretch for any alignment frag. Note that if have
21887 been expanding the earlier code, the symbol may be
21888 defined in what appears to be an earlier frag. FIXME:
21889 This doesn't handle the fr_subtype field, which specifies
21890 a maximum number of bytes to skip when doing an
21892 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
21894 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
21897 stretch = - ((- stretch)
21898 & ~ ((1 << (int) f->fr_offset) - 1));
21900 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
21912 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21915 relax_adr (fragS *fragp, asection *sec, long stretch)
21920 /* Assume worst case for symbols not known to be in the same section. */
21921 if (fragp->fr_symbol == NULL
21922 || !S_IS_DEFINED (fragp->fr_symbol)
21923 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21924 || S_IS_WEAK (fragp->fr_symbol))
21927 val = relaxed_symbol_addr (fragp, stretch);
21928 addr = fragp->fr_address + fragp->fr_fix;
21929 addr = (addr + 4) & ~3;
21930 /* Force misaligned targets to 32-bit variant. */
21934 if (val < 0 || val > 1020)
21939 /* Return the size of a relaxable add/sub immediate instruction. */
21941 relax_addsub (fragS *fragp, asection *sec)
21946 buf = fragp->fr_literal + fragp->fr_fix;
21947 op = bfd_get_16(sec->owner, buf);
21948 if ((op & 0xf) == ((op >> 4) & 0xf))
21949 return relax_immediate (fragp, 8, 0);
21951 return relax_immediate (fragp, 3, 0);
21954 /* Return TRUE iff the definition of symbol S could be pre-empted
21955 (overridden) at link or load time. */
21957 symbol_preemptible (symbolS *s)
21959 /* Weak symbols can always be pre-empted. */
21963 /* Non-global symbols cannot be pre-empted. */
21964 if (! S_IS_EXTERNAL (s))
21968 /* In ELF, a global symbol can be marked protected, or private. In that
21969 case it can't be pre-empted (other definitions in the same link unit
21970 would violate the ODR). */
21971 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
21975 /* Other global symbols might be pre-empted. */
21979 /* Return the size of a relaxable branch instruction. BITS is the
21980 size of the offset field in the narrow instruction. */
21983 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
21989 /* Assume worst case for symbols not known to be in the same section. */
21990 if (!S_IS_DEFINED (fragp->fr_symbol)
21991 || sec != S_GET_SEGMENT (fragp->fr_symbol)
21992 || S_IS_WEAK (fragp->fr_symbol))
21996 /* A branch to a function in ARM state will require interworking. */
21997 if (S_IS_DEFINED (fragp->fr_symbol)
21998 && ARM_IS_FUNC (fragp->fr_symbol))
22002 if (symbol_preemptible (fragp->fr_symbol))
22005 val = relaxed_symbol_addr (fragp, stretch);
22006 addr = fragp->fr_address + fragp->fr_fix + 4;
22009 /* Offset is a signed value *2 */
22011 if (val >= limit || val < -limit)
22017 /* Relax a machine dependent frag. This returns the amount by which
22018 the current size of the frag should change. */
22021 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
22026 oldsize = fragp->fr_var;
22027 switch (fragp->fr_subtype)
22029 case T_MNEM_ldr_pc2:
22030 newsize = relax_adr (fragp, sec, stretch);
22032 case T_MNEM_ldr_pc:
22033 case T_MNEM_ldr_sp:
22034 case T_MNEM_str_sp:
22035 newsize = relax_immediate (fragp, 8, 2);
22039 newsize = relax_immediate (fragp, 5, 2);
22043 newsize = relax_immediate (fragp, 5, 1);
22047 newsize = relax_immediate (fragp, 5, 0);
22050 newsize = relax_adr (fragp, sec, stretch);
22056 newsize = relax_immediate (fragp, 8, 0);
22059 newsize = relax_branch (fragp, sec, 11, stretch);
22062 newsize = relax_branch (fragp, sec, 8, stretch);
22064 case T_MNEM_add_sp:
22065 case T_MNEM_add_pc:
22066 newsize = relax_immediate (fragp, 8, 2);
22068 case T_MNEM_inc_sp:
22069 case T_MNEM_dec_sp:
22070 newsize = relax_immediate (fragp, 7, 2);
22076 newsize = relax_addsub (fragp, sec);
22082 fragp->fr_var = newsize;
22083 /* Freeze wide instructions that are at or before the same location as
22084 in the previous pass. This avoids infinite loops.
22085 Don't freeze them unconditionally because targets may be artificially
22086 misaligned by the expansion of preceding frags. */
22087 if (stretch <= 0 && newsize > 2)
22089 md_convert_frag (sec->owner, sec, fragp);
22093 return newsize - oldsize;
22096 /* Round up a section size to the appropriate boundary. */
22099 md_section_align (segT segment ATTRIBUTE_UNUSED,
22105 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22106 of an rs_align_code fragment. */
22109 arm_handle_align (fragS * fragP)
22111 static unsigned char const arm_noop[2][2][4] =
22114 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22115 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22118 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22119 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22122 static unsigned char const thumb_noop[2][2][2] =
22125 {0xc0, 0x46}, /* LE */
22126 {0x46, 0xc0}, /* BE */
22129 {0x00, 0xbf}, /* LE */
22130 {0xbf, 0x00} /* BE */
22133 static unsigned char const wide_thumb_noop[2][4] =
22134 { /* Wide Thumb-2 */
22135 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22136 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22139 unsigned bytes, fix, noop_size;
22141 const unsigned char * noop;
22142 const unsigned char *narrow_noop = NULL;
22147 if (fragP->fr_type != rs_align_code)
22150 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
22151 p = fragP->fr_literal + fragP->fr_fix;
22154 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
22155 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
22157 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
22159 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
22161 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
22162 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
22164 narrow_noop = thumb_noop[1][target_big_endian];
22165 noop = wide_thumb_noop[target_big_endian];
22168 noop = thumb_noop[0][target_big_endian];
22176 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
22177 ? selected_cpu : arm_arch_none,
22179 [target_big_endian];
22186 fragP->fr_var = noop_size;
22188 if (bytes & (noop_size - 1))
22190 fix = bytes & (noop_size - 1);
22192 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
22194 memset (p, 0, fix);
22201 if (bytes & noop_size)
22203 /* Insert a narrow noop. */
22204 memcpy (p, narrow_noop, noop_size);
22206 bytes -= noop_size;
22210 /* Use wide noops for the remainder */
22214 while (bytes >= noop_size)
22216 memcpy (p, noop, noop_size);
22218 bytes -= noop_size;
22222 fragP->fr_fix += fix;
22225 /* Called from md_do_align. Used to create an alignment
22226 frag in a code section. */
22229 arm_frag_align_code (int n, int max)
22233 /* We assume that there will never be a requirement
22234 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22235 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
22240 _("alignments greater than %d bytes not supported in .text sections."),
22241 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
22242 as_fatal ("%s", err_msg);
22245 p = frag_var (rs_align_code,
22246 MAX_MEM_FOR_RS_ALIGN_CODE,
22248 (relax_substateT) max,
22255 /* Perform target specific initialisation of a frag.
22256 Note - despite the name this initialisation is not done when the frag
22257 is created, but only when its type is assigned. A frag can be created
22258 and used a long time before its type is set, so beware of assuming that
22259 this initialisation is performed first. */
22263 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
22265 /* Record whether this frag is in an ARM or a THUMB area. */
22266 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
22269 #else /* OBJ_ELF is defined. */
22271 arm_init_frag (fragS * fragP, int max_chars)
22273 bfd_boolean frag_thumb_mode;
22275 /* If the current ARM vs THUMB mode has not already
22276 been recorded into this frag then do so now. */
22277 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
22278 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
22280 /* PR 21809: Do not set a mapping state for debug sections
22281 - it just confuses other tools. */
22282 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
22285 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
22287 /* Record a mapping symbol for alignment frags. We will delete this
22288 later if the alignment ends up empty. */
22289 switch (fragP->fr_type)
22292 case rs_align_test:
22294 mapping_state_2 (MAP_DATA, max_chars);
22296 case rs_align_code:
22297 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
22304 /* When we change sections we need to issue a new mapping symbol. */
22307 arm_elf_change_section (void)
22309 /* Link an unlinked unwind index table section to the .text section. */
22310 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
22311 && elf_linked_to_section (now_seg) == NULL)
22312 elf_linked_to_section (now_seg) = text_section;
22316 arm_elf_section_type (const char * str, size_t len)
22318 if (len == 5 && strncmp (str, "exidx", 5) == 0)
22319 return SHT_ARM_EXIDX;
22324 /* Code to deal with unwinding tables. */
22326 static void add_unwind_adjustsp (offsetT);
22328 /* Generate any deferred unwind frame offset. */
22331 flush_pending_unwind (void)
22335 offset = unwind.pending_offset;
22336 unwind.pending_offset = 0;
22338 add_unwind_adjustsp (offset);
22341 /* Add an opcode to this list for this function. Two-byte opcodes should
22342 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22346 add_unwind_opcode (valueT op, int length)
22348 /* Add any deferred stack adjustment. */
22349 if (unwind.pending_offset)
22350 flush_pending_unwind ();
22352 unwind.sp_restored = 0;
22354 if (unwind.opcode_count + length > unwind.opcode_alloc)
22356 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
22357 if (unwind.opcodes)
22358 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
22359 unwind.opcode_alloc);
22361 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
22366 unwind.opcodes[unwind.opcode_count] = op & 0xff;
22368 unwind.opcode_count++;
22372 /* Add unwind opcodes to adjust the stack pointer. */
22375 add_unwind_adjustsp (offsetT offset)
22379 if (offset > 0x200)
22381 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22386 /* Long form: 0xb2, uleb128. */
22387 /* This might not fit in a word so add the individual bytes,
22388 remembering the list is built in reverse order. */
22389 o = (valueT) ((offset - 0x204) >> 2);
22391 add_unwind_opcode (0, 1);
22393 /* Calculate the uleb128 encoding of the offset. */
22397 bytes[n] = o & 0x7f;
22403 /* Add the insn. */
22405 add_unwind_opcode (bytes[n - 1], 1);
22406 add_unwind_opcode (0xb2, 1);
22408 else if (offset > 0x100)
22410 /* Two short opcodes. */
22411 add_unwind_opcode (0x3f, 1);
22412 op = (offset - 0x104) >> 2;
22413 add_unwind_opcode (op, 1);
22415 else if (offset > 0)
22417 /* Short opcode. */
22418 op = (offset - 4) >> 2;
22419 add_unwind_opcode (op, 1);
22421 else if (offset < 0)
22424 while (offset > 0x100)
22426 add_unwind_opcode (0x7f, 1);
22429 op = ((offset - 4) >> 2) | 0x40;
22430 add_unwind_opcode (op, 1);
22434 /* Finish the list of unwind opcodes for this function. */
22437 finish_unwind_opcodes (void)
22441 if (unwind.fp_used)
22443 /* Adjust sp as necessary. */
22444 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
22445 flush_pending_unwind ();
22447 /* After restoring sp from the frame pointer. */
22448 op = 0x90 | unwind.fp_reg;
22449 add_unwind_opcode (op, 1);
22452 flush_pending_unwind ();
22456 /* Start an exception table entry. If idx is nonzero this is an index table
22460 start_unwind_section (const segT text_seg, int idx)
22462 const char * text_name;
22463 const char * prefix;
22464 const char * prefix_once;
22465 const char * group_name;
22473 prefix = ELF_STRING_ARM_unwind;
22474 prefix_once = ELF_STRING_ARM_unwind_once;
22475 type = SHT_ARM_EXIDX;
22479 prefix = ELF_STRING_ARM_unwind_info;
22480 prefix_once = ELF_STRING_ARM_unwind_info_once;
22481 type = SHT_PROGBITS;
22484 text_name = segment_name (text_seg);
22485 if (streq (text_name, ".text"))
22488 if (strncmp (text_name, ".gnu.linkonce.t.",
22489 strlen (".gnu.linkonce.t.")) == 0)
22491 prefix = prefix_once;
22492 text_name += strlen (".gnu.linkonce.t.");
22495 sec_name = concat (prefix, text_name, (char *) NULL);
22501 /* Handle COMDAT group. */
22502 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
22504 group_name = elf_group_name (text_seg);
22505 if (group_name == NULL)
22507 as_bad (_("Group section `%s' has no group signature"),
22508 segment_name (text_seg));
22509 ignore_rest_of_line ();
22512 flags |= SHF_GROUP;
22516 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
22519 /* Set the section link for index tables. */
22521 elf_linked_to_section (now_seg) = text_seg;
22525 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22526 personality routine data. Returns zero, or the index table value for
22527 an inline entry. */
22530 create_unwind_entry (int have_data)
22535 /* The current word of data. */
22537 /* The number of bytes left in this word. */
22540 finish_unwind_opcodes ();
22542 /* Remember the current text section. */
22543 unwind.saved_seg = now_seg;
22544 unwind.saved_subseg = now_subseg;
22546 start_unwind_section (now_seg, 0);
22548 if (unwind.personality_routine == NULL)
22550 if (unwind.personality_index == -2)
22553 as_bad (_("handlerdata in cantunwind frame"));
22554 return 1; /* EXIDX_CANTUNWIND. */
22557 /* Use a default personality routine if none is specified. */
22558 if (unwind.personality_index == -1)
22560 if (unwind.opcode_count > 3)
22561 unwind.personality_index = 1;
22563 unwind.personality_index = 0;
22566 /* Space for the personality routine entry. */
22567 if (unwind.personality_index == 0)
22569 if (unwind.opcode_count > 3)
22570 as_bad (_("too many unwind opcodes for personality routine 0"));
22574 /* All the data is inline in the index table. */
22577 while (unwind.opcode_count > 0)
22579 unwind.opcode_count--;
22580 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
22584 /* Pad with "finish" opcodes. */
22586 data = (data << 8) | 0xb0;
22593 /* We get two opcodes "free" in the first word. */
22594 size = unwind.opcode_count - 2;
22598 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22599 if (unwind.personality_index != -1)
22601 as_bad (_("attempt to recreate an unwind entry"));
22605 /* An extra byte is required for the opcode count. */
22606 size = unwind.opcode_count + 1;
22609 size = (size + 3) >> 2;
22611 as_bad (_("too many unwind opcodes"));
22613 frag_align (2, 0, 0);
22614 record_alignment (now_seg, 2);
22615 unwind.table_entry = expr_build_dot ();
22617 /* Allocate the table entry. */
22618 ptr = frag_more ((size << 2) + 4);
22619 /* PR 13449: Zero the table entries in case some of them are not used. */
22620 memset (ptr, 0, (size << 2) + 4);
22621 where = frag_now_fix () - ((size << 2) + 4);
22623 switch (unwind.personality_index)
22626 /* ??? Should this be a PLT generating relocation? */
22627 /* Custom personality routine. */
22628 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
22629 BFD_RELOC_ARM_PREL31);
22634 /* Set the first byte to the number of additional words. */
22635 data = size > 0 ? size - 1 : 0;
22639 /* ABI defined personality routines. */
22641 /* Three opcodes bytes are packed into the first word. */
22648 /* The size and first two opcode bytes go in the first word. */
22649 data = ((0x80 + unwind.personality_index) << 8) | size;
22654 /* Should never happen. */
22658 /* Pack the opcodes into words (MSB first), reversing the list at the same
22660 while (unwind.opcode_count > 0)
22664 md_number_to_chars (ptr, data, 4);
22669 unwind.opcode_count--;
22671 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
22674 /* Finish off the last word. */
22677 /* Pad with "finish" opcodes. */
22679 data = (data << 8) | 0xb0;
22681 md_number_to_chars (ptr, data, 4);
22686 /* Add an empty descriptor if there is no user-specified data. */
22687 ptr = frag_more (4);
22688 md_number_to_chars (ptr, 0, 4);
22695 /* Initialize the DWARF-2 unwind information for this procedure. */
22698 tc_arm_frame_initial_instructions (void)
22700 cfi_add_CFA_def_cfa (REG_SP, 0);
22702 #endif /* OBJ_ELF */
22704 /* Convert REGNAME to a DWARF-2 register number. */
22707 tc_arm_regname_to_dw2regnum (char *regname)
22709 int reg = arm_reg_parse (®name, REG_TYPE_RN);
22713 /* PR 16694: Allow VFP registers as well. */
22714 reg = arm_reg_parse (®name, REG_TYPE_VFS);
22718 reg = arm_reg_parse (®name, REG_TYPE_VFD);
22727 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
22731 exp.X_op = O_secrel;
22732 exp.X_add_symbol = symbol;
22733 exp.X_add_number = 0;
22734 emit_expr (&exp, size);
22738 /* MD interface: Symbol and relocation handling. */
22740 /* Return the address within the segment that a PC-relative fixup is
22741 relative to. For ARM, PC-relative fixups applied to instructions
22742 are generally relative to the location of the fixup plus 8 bytes.
22743 Thumb branches are offset by 4, and Thumb loads relative to PC
22744 require special handling. */
22747 md_pcrel_from_section (fixS * fixP, segT seg)
22749 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
22751 /* If this is pc-relative and we are going to emit a relocation
22752 then we just want to put out any pipeline compensation that the linker
22753 will need. Otherwise we want to use the calculated base.
22754 For WinCE we skip the bias for externals as well, since this
22755 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22757 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
22758 || (arm_force_relocation (fixP)
22760 && !S_IS_EXTERNAL (fixP->fx_addsy)
22766 switch (fixP->fx_r_type)
22768 /* PC relative addressing on the Thumb is slightly odd as the
22769 bottom two bits of the PC are forced to zero for the
22770 calculation. This happens *after* application of the
22771 pipeline offset. However, Thumb adrl already adjusts for
22772 this, so we need not do it again. */
22773 case BFD_RELOC_ARM_THUMB_ADD:
22776 case BFD_RELOC_ARM_THUMB_OFFSET:
22777 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22778 case BFD_RELOC_ARM_T32_ADD_PC12:
22779 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22780 return (base + 4) & ~3;
22782 /* Thumb branches are simply offset by +4. */
22783 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22784 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22785 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22786 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22787 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22790 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22792 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22793 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22794 && ARM_IS_FUNC (fixP->fx_addsy)
22795 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22796 base = fixP->fx_where + fixP->fx_frag->fr_address;
22799 /* BLX is like branches above, but forces the low two bits of PC to
22801 case BFD_RELOC_THUMB_PCREL_BLX:
22803 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22804 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22805 && THUMB_IS_FUNC (fixP->fx_addsy)
22806 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22807 base = fixP->fx_where + fixP->fx_frag->fr_address;
22808 return (base + 4) & ~3;
22810 /* ARM mode branches are offset by +8. However, the Windows CE
22811 loader expects the relocation not to take this into account. */
22812 case BFD_RELOC_ARM_PCREL_BLX:
22814 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22815 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22816 && ARM_IS_FUNC (fixP->fx_addsy)
22817 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22818 base = fixP->fx_where + fixP->fx_frag->fr_address;
22821 case BFD_RELOC_ARM_PCREL_CALL:
22823 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22824 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22825 && THUMB_IS_FUNC (fixP->fx_addsy)
22826 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22827 base = fixP->fx_where + fixP->fx_frag->fr_address;
22830 case BFD_RELOC_ARM_PCREL_BRANCH:
22831 case BFD_RELOC_ARM_PCREL_JUMP:
22832 case BFD_RELOC_ARM_PLT32:
22834 /* When handling fixups immediately, because we have already
22835 discovered the value of a symbol, or the address of the frag involved
22836 we must account for the offset by +8, as the OS loader will never see the reloc.
22837 see fixup_segment() in write.c
22838 The S_IS_EXTERNAL test handles the case of global symbols.
22839 Those need the calculated base, not just the pipe compensation the linker will need. */
22841 && fixP->fx_addsy != NULL
22842 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22843 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
22851 /* ARM mode loads relative to PC are also offset by +8. Unlike
22852 branches, the Windows CE loader *does* expect the relocation
22853 to take this into account. */
22854 case BFD_RELOC_ARM_OFFSET_IMM:
22855 case BFD_RELOC_ARM_OFFSET_IMM8:
22856 case BFD_RELOC_ARM_HWLITERAL:
22857 case BFD_RELOC_ARM_LITERAL:
22858 case BFD_RELOC_ARM_CP_OFF_IMM:
22862 /* Other PC-relative relocations are un-offset. */
22868 static bfd_boolean flag_warn_syms = TRUE;
22871 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
22873 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22874 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22875 does mean that the resulting code might be very confusing to the reader.
22876 Also this warning can be triggered if the user omits an operand before
22877 an immediate address, eg:
22881 GAS treats this as an assignment of the value of the symbol foo to a
22882 symbol LDR, and so (without this code) it will not issue any kind of
22883 warning or error message.
22885 Note - ARM instructions are case-insensitive but the strings in the hash
22886 table are all stored in lower case, so we must first ensure that name is
22888 if (flag_warn_syms && arm_ops_hsh)
22890 char * nbuf = strdup (name);
22893 for (p = nbuf; *p; p++)
22895 if (hash_find (arm_ops_hsh, nbuf) != NULL)
22897 static struct hash_control * already_warned = NULL;
22899 if (already_warned == NULL)
22900 already_warned = hash_new ();
22901 /* Only warn about the symbol once. To keep the code
22902 simple we let hash_insert do the lookup for us. */
22903 if (hash_insert (already_warned, name, NULL) == NULL)
22904 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
22913 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22914 Otherwise we have no need to default values of symbols. */
22917 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
22920 if (name[0] == '_' && name[1] == 'G'
22921 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
22925 if (symbol_find (name))
22926 as_bad (_("GOT already in the symbol table"));
22928 GOT_symbol = symbol_new (name, undefined_section,
22929 (valueT) 0, & zero_address_frag);
22939 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22940 computed as two separate immediate values, added together. We
22941 already know that this value cannot be computed by just one ARM
22944 static unsigned int
22945 validate_immediate_twopart (unsigned int val,
22946 unsigned int * highpart)
22951 for (i = 0; i < 32; i += 2)
22952 if (((a = rotate_left (val, i)) & 0xff) != 0)
22958 * highpart = (a >> 8) | ((i + 24) << 7);
22960 else if (a & 0xff0000)
22962 if (a & 0xff000000)
22964 * highpart = (a >> 16) | ((i + 16) << 7);
22968 gas_assert (a & 0xff000000);
22969 * highpart = (a >> 24) | ((i + 8) << 7);
22972 return (a & 0xff) | (i << 7);
22979 validate_offset_imm (unsigned int val, int hwse)
22981 if ((hwse && val > 255) || val > 4095)
22986 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22987 negative immediate constant by altering the instruction. A bit of
22992 by inverting the second operand, and
22995 by negating the second operand. */
22998 negate_data_op (unsigned long * instruction,
22999 unsigned long value)
23002 unsigned long negated, inverted;
23004 negated = encode_arm_immediate (-value);
23005 inverted = encode_arm_immediate (~value);
23007 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
23010 /* First negates. */
23011 case OPCODE_SUB: /* ADD <-> SUB */
23012 new_inst = OPCODE_ADD;
23017 new_inst = OPCODE_SUB;
23021 case OPCODE_CMP: /* CMP <-> CMN */
23022 new_inst = OPCODE_CMN;
23027 new_inst = OPCODE_CMP;
23031 /* Now Inverted ops. */
23032 case OPCODE_MOV: /* MOV <-> MVN */
23033 new_inst = OPCODE_MVN;
23038 new_inst = OPCODE_MOV;
23042 case OPCODE_AND: /* AND <-> BIC */
23043 new_inst = OPCODE_BIC;
23048 new_inst = OPCODE_AND;
23052 case OPCODE_ADC: /* ADC <-> SBC */
23053 new_inst = OPCODE_SBC;
23058 new_inst = OPCODE_ADC;
23062 /* We cannot do anything. */
23067 if (value == (unsigned) FAIL)
23070 *instruction &= OPCODE_MASK;
23071 *instruction |= new_inst << DATA_OP_SHIFT;
23075 /* Like negate_data_op, but for Thumb-2. */
23077 static unsigned int
23078 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
23082 unsigned int negated, inverted;
23084 negated = encode_thumb32_immediate (-value);
23085 inverted = encode_thumb32_immediate (~value);
23087 rd = (*instruction >> 8) & 0xf;
23088 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
23091 /* ADD <-> SUB. Includes CMP <-> CMN. */
23092 case T2_OPCODE_SUB:
23093 new_inst = T2_OPCODE_ADD;
23097 case T2_OPCODE_ADD:
23098 new_inst = T2_OPCODE_SUB;
23102 /* ORR <-> ORN. Includes MOV <-> MVN. */
23103 case T2_OPCODE_ORR:
23104 new_inst = T2_OPCODE_ORN;
23108 case T2_OPCODE_ORN:
23109 new_inst = T2_OPCODE_ORR;
23113 /* AND <-> BIC. TST has no inverted equivalent. */
23114 case T2_OPCODE_AND:
23115 new_inst = T2_OPCODE_BIC;
23122 case T2_OPCODE_BIC:
23123 new_inst = T2_OPCODE_AND;
23128 case T2_OPCODE_ADC:
23129 new_inst = T2_OPCODE_SBC;
23133 case T2_OPCODE_SBC:
23134 new_inst = T2_OPCODE_ADC;
23138 /* We cannot do anything. */
23143 if (value == (unsigned int)FAIL)
23146 *instruction &= T2_OPCODE_MASK;
23147 *instruction |= new_inst << T2_DATA_OP_SHIFT;
23151 /* Read a 32-bit thumb instruction from buf. */
23153 static unsigned long
23154 get_thumb32_insn (char * buf)
23156 unsigned long insn;
23157 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
23158 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23163 /* We usually want to set the low bit on the address of thumb function
23164 symbols. In particular .word foo - . should have the low bit set.
23165 Generic code tries to fold the difference of two symbols to
23166 a constant. Prevent this and force a relocation when the first symbols
23167 is a thumb function. */
23170 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
23172 if (op == O_subtract
23173 && l->X_op == O_symbol
23174 && r->X_op == O_symbol
23175 && THUMB_IS_FUNC (l->X_add_symbol))
23177 l->X_op = O_subtract;
23178 l->X_op_symbol = r->X_add_symbol;
23179 l->X_add_number -= r->X_add_number;
23183 /* Process as normal. */
23187 /* Encode Thumb2 unconditional branches and calls. The encoding
23188 for the 2 are identical for the immediate values. */
23191 encode_thumb2_b_bl_offset (char * buf, offsetT value)
23193 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23196 addressT S, I1, I2, lo, hi;
23198 S = (value >> 24) & 0x01;
23199 I1 = (value >> 23) & 0x01;
23200 I2 = (value >> 22) & 0x01;
23201 hi = (value >> 12) & 0x3ff;
23202 lo = (value >> 1) & 0x7ff;
23203 newval = md_chars_to_number (buf, THUMB_SIZE);
23204 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23205 newval |= (S << 10) | hi;
23206 newval2 &= ~T2I1I2MASK;
23207 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
23208 md_number_to_chars (buf, newval, THUMB_SIZE);
23209 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
23213 md_apply_fix (fixS * fixP,
23217 offsetT value = * valP;
23219 unsigned int newimm;
23220 unsigned long temp;
23222 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
23224 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
23226 /* Note whether this will delete the relocation. */
23228 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
23231 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23232 consistency with the behaviour on 32-bit hosts. Remember value
23234 value &= 0xffffffff;
23235 value ^= 0x80000000;
23236 value -= 0x80000000;
23239 fixP->fx_addnumber = value;
23241 /* Same treatment for fixP->fx_offset. */
23242 fixP->fx_offset &= 0xffffffff;
23243 fixP->fx_offset ^= 0x80000000;
23244 fixP->fx_offset -= 0x80000000;
23246 switch (fixP->fx_r_type)
23248 case BFD_RELOC_NONE:
23249 /* This will need to go in the object file. */
23253 case BFD_RELOC_ARM_IMMEDIATE:
23254 /* We claim that this fixup has been processed here,
23255 even if in fact we generate an error because we do
23256 not have a reloc for it, so tc_gen_reloc will reject it. */
23259 if (fixP->fx_addsy)
23261 const char *msg = 0;
23263 if (! S_IS_DEFINED (fixP->fx_addsy))
23264 msg = _("undefined symbol %s used as an immediate value");
23265 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
23266 msg = _("symbol %s is in a different section");
23267 else if (S_IS_WEAK (fixP->fx_addsy))
23268 msg = _("symbol %s is weak and may be overridden later");
23272 as_bad_where (fixP->fx_file, fixP->fx_line,
23273 msg, S_GET_NAME (fixP->fx_addsy));
23278 temp = md_chars_to_number (buf, INSN_SIZE);
23280 /* If the offset is negative, we should use encoding A2 for ADR. */
23281 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
23282 newimm = negate_data_op (&temp, value);
23285 newimm = encode_arm_immediate (value);
23287 /* If the instruction will fail, see if we can fix things up by
23288 changing the opcode. */
23289 if (newimm == (unsigned int) FAIL)
23290 newimm = negate_data_op (&temp, value);
23291 /* MOV accepts both ARM modified immediate (A1 encoding) and
23292 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23293 When disassembling, MOV is preferred when there is no encoding
23295 if (newimm == (unsigned int) FAIL
23296 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
23297 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
23298 && !((temp >> SBIT_SHIFT) & 0x1)
23299 && value >= 0 && value <= 0xffff)
23301 /* Clear bits[23:20] to change encoding from A1 to A2. */
23302 temp &= 0xff0fffff;
23303 /* Encoding high 4bits imm. Code below will encode the remaining
23305 temp |= (value & 0x0000f000) << 4;
23306 newimm = value & 0x00000fff;
23310 if (newimm == (unsigned int) FAIL)
23312 as_bad_where (fixP->fx_file, fixP->fx_line,
23313 _("invalid constant (%lx) after fixup"),
23314 (unsigned long) value);
23318 newimm |= (temp & 0xfffff000);
23319 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
23322 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
23324 unsigned int highpart = 0;
23325 unsigned int newinsn = 0xe1a00000; /* nop. */
23327 if (fixP->fx_addsy)
23329 const char *msg = 0;
23331 if (! S_IS_DEFINED (fixP->fx_addsy))
23332 msg = _("undefined symbol %s used as an immediate value");
23333 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
23334 msg = _("symbol %s is in a different section");
23335 else if (S_IS_WEAK (fixP->fx_addsy))
23336 msg = _("symbol %s is weak and may be overridden later");
23340 as_bad_where (fixP->fx_file, fixP->fx_line,
23341 msg, S_GET_NAME (fixP->fx_addsy));
23346 newimm = encode_arm_immediate (value);
23347 temp = md_chars_to_number (buf, INSN_SIZE);
23349 /* If the instruction will fail, see if we can fix things up by
23350 changing the opcode. */
23351 if (newimm == (unsigned int) FAIL
23352 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
23354 /* No ? OK - try using two ADD instructions to generate
23356 newimm = validate_immediate_twopart (value, & highpart);
23358 /* Yes - then make sure that the second instruction is
23360 if (newimm != (unsigned int) FAIL)
23362 /* Still No ? Try using a negated value. */
23363 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
23364 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
23365 /* Otherwise - give up. */
23368 as_bad_where (fixP->fx_file, fixP->fx_line,
23369 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23374 /* Replace the first operand in the 2nd instruction (which
23375 is the PC) with the destination register. We have
23376 already added in the PC in the first instruction and we
23377 do not want to do it again. */
23378 newinsn &= ~ 0xf0000;
23379 newinsn |= ((newinsn & 0x0f000) << 4);
23382 newimm |= (temp & 0xfffff000);
23383 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
23385 highpart |= (newinsn & 0xfffff000);
23386 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
23390 case BFD_RELOC_ARM_OFFSET_IMM:
23391 if (!fixP->fx_done && seg->use_rela_p)
23393 /* Fall through. */
23395 case BFD_RELOC_ARM_LITERAL:
23401 if (validate_offset_imm (value, 0) == FAIL)
23403 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
23404 as_bad_where (fixP->fx_file, fixP->fx_line,
23405 _("invalid literal constant: pool needs to be closer"));
23407 as_bad_where (fixP->fx_file, fixP->fx_line,
23408 _("bad immediate value for offset (%ld)"),
23413 newval = md_chars_to_number (buf, INSN_SIZE);
23415 newval &= 0xfffff000;
23418 newval &= 0xff7ff000;
23419 newval |= value | (sign ? INDEX_UP : 0);
23421 md_number_to_chars (buf, newval, INSN_SIZE);
23424 case BFD_RELOC_ARM_OFFSET_IMM8:
23425 case BFD_RELOC_ARM_HWLITERAL:
23431 if (validate_offset_imm (value, 1) == FAIL)
23433 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
23434 as_bad_where (fixP->fx_file, fixP->fx_line,
23435 _("invalid literal constant: pool needs to be closer"));
23437 as_bad_where (fixP->fx_file, fixP->fx_line,
23438 _("bad immediate value for 8-bit offset (%ld)"),
23443 newval = md_chars_to_number (buf, INSN_SIZE);
23445 newval &= 0xfffff0f0;
23448 newval &= 0xff7ff0f0;
23449 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
23451 md_number_to_chars (buf, newval, INSN_SIZE);
23454 case BFD_RELOC_ARM_T32_OFFSET_U8:
23455 if (value < 0 || value > 1020 || value % 4 != 0)
23456 as_bad_where (fixP->fx_file, fixP->fx_line,
23457 _("bad immediate value for offset (%ld)"), (long) value);
23460 newval = md_chars_to_number (buf+2, THUMB_SIZE);
23462 md_number_to_chars (buf+2, newval, THUMB_SIZE);
23465 case BFD_RELOC_ARM_T32_OFFSET_IMM:
23466 /* This is a complicated relocation used for all varieties of Thumb32
23467 load/store instruction with immediate offset:
23469 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23470 *4, optional writeback(W)
23471 (doubleword load/store)
23473 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23474 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23475 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23476 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23477 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23479 Uppercase letters indicate bits that are already encoded at
23480 this point. Lowercase letters are our problem. For the
23481 second block of instructions, the secondary opcode nybble
23482 (bits 8..11) is present, and bit 23 is zero, even if this is
23483 a PC-relative operation. */
23484 newval = md_chars_to_number (buf, THUMB_SIZE);
23486 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
23488 if ((newval & 0xf0000000) == 0xe0000000)
23490 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23492 newval |= (1 << 23);
23495 if (value % 4 != 0)
23497 as_bad_where (fixP->fx_file, fixP->fx_line,
23498 _("offset not a multiple of 4"));
23504 as_bad_where (fixP->fx_file, fixP->fx_line,
23505 _("offset out of range"));
23510 else if ((newval & 0x000f0000) == 0x000f0000)
23512 /* PC-relative, 12-bit offset. */
23514 newval |= (1 << 23);
23519 as_bad_where (fixP->fx_file, fixP->fx_line,
23520 _("offset out of range"));
23525 else if ((newval & 0x00000100) == 0x00000100)
23527 /* Writeback: 8-bit, +/- offset. */
23529 newval |= (1 << 9);
23534 as_bad_where (fixP->fx_file, fixP->fx_line,
23535 _("offset out of range"));
23540 else if ((newval & 0x00000f00) == 0x00000e00)
23542 /* T-instruction: positive 8-bit offset. */
23543 if (value < 0 || value > 0xff)
23545 as_bad_where (fixP->fx_file, fixP->fx_line,
23546 _("offset out of range"));
23554 /* Positive 12-bit or negative 8-bit offset. */
23558 newval |= (1 << 23);
23568 as_bad_where (fixP->fx_file, fixP->fx_line,
23569 _("offset out of range"));
23576 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
23577 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
23580 case BFD_RELOC_ARM_SHIFT_IMM:
23581 newval = md_chars_to_number (buf, INSN_SIZE);
23582 if (((unsigned long) value) > 32
23584 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
23586 as_bad_where (fixP->fx_file, fixP->fx_line,
23587 _("shift expression is too large"));
23592 /* Shifts of zero must be done as lsl. */
23594 else if (value == 32)
23596 newval &= 0xfffff07f;
23597 newval |= (value & 0x1f) << 7;
23598 md_number_to_chars (buf, newval, INSN_SIZE);
23601 case BFD_RELOC_ARM_T32_IMMEDIATE:
23602 case BFD_RELOC_ARM_T32_ADD_IMM:
23603 case BFD_RELOC_ARM_T32_IMM12:
23604 case BFD_RELOC_ARM_T32_ADD_PC12:
23605 /* We claim that this fixup has been processed here,
23606 even if in fact we generate an error because we do
23607 not have a reloc for it, so tc_gen_reloc will reject it. */
23611 && ! S_IS_DEFINED (fixP->fx_addsy))
23613 as_bad_where (fixP->fx_file, fixP->fx_line,
23614 _("undefined symbol %s used as an immediate value"),
23615 S_GET_NAME (fixP->fx_addsy));
23619 newval = md_chars_to_number (buf, THUMB_SIZE);
23621 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
23624 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23625 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23626 Thumb2 modified immediate encoding (T2). */
23627 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
23628 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23630 newimm = encode_thumb32_immediate (value);
23631 if (newimm == (unsigned int) FAIL)
23632 newimm = thumb32_negate_data_op (&newval, value);
23634 if (newimm == (unsigned int) FAIL)
23636 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
23638 /* Turn add/sum into addw/subw. */
23639 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
23640 newval = (newval & 0xfeffffff) | 0x02000000;
23641 /* No flat 12-bit imm encoding for addsw/subsw. */
23642 if ((newval & 0x00100000) == 0)
23644 /* 12 bit immediate for addw/subw. */
23648 newval ^= 0x00a00000;
23651 newimm = (unsigned int) FAIL;
23658 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23659 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23660 disassembling, MOV is preferred when there is no encoding
23662 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
23663 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23664 but with the Rn field [19:16] set to 1111. */
23665 && (((newval >> 16) & 0xf) == 0xf)
23666 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
23667 && !((newval >> T2_SBIT_SHIFT) & 0x1)
23668 && value >= 0 && value <= 0xffff)
23670 /* Toggle bit[25] to change encoding from T2 to T3. */
23672 /* Clear bits[19:16]. */
23673 newval &= 0xfff0ffff;
23674 /* Encoding high 4bits imm. Code below will encode the
23675 remaining low 12bits. */
23676 newval |= (value & 0x0000f000) << 4;
23677 newimm = value & 0x00000fff;
23682 if (newimm == (unsigned int)FAIL)
23684 as_bad_where (fixP->fx_file, fixP->fx_line,
23685 _("invalid constant (%lx) after fixup"),
23686 (unsigned long) value);
23690 newval |= (newimm & 0x800) << 15;
23691 newval |= (newimm & 0x700) << 4;
23692 newval |= (newimm & 0x0ff);
23694 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
23695 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
23698 case BFD_RELOC_ARM_SMC:
23699 if (((unsigned long) value) > 0xffff)
23700 as_bad_where (fixP->fx_file, fixP->fx_line,
23701 _("invalid smc expression"));
23702 newval = md_chars_to_number (buf, INSN_SIZE);
23703 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23704 md_number_to_chars (buf, newval, INSN_SIZE);
23707 case BFD_RELOC_ARM_HVC:
23708 if (((unsigned long) value) > 0xffff)
23709 as_bad_where (fixP->fx_file, fixP->fx_line,
23710 _("invalid hvc expression"));
23711 newval = md_chars_to_number (buf, INSN_SIZE);
23712 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
23713 md_number_to_chars (buf, newval, INSN_SIZE);
23716 case BFD_RELOC_ARM_SWI:
23717 if (fixP->tc_fix_data != 0)
23719 if (((unsigned long) value) > 0xff)
23720 as_bad_where (fixP->fx_file, fixP->fx_line,
23721 _("invalid swi expression"));
23722 newval = md_chars_to_number (buf, THUMB_SIZE);
23724 md_number_to_chars (buf, newval, THUMB_SIZE);
23728 if (((unsigned long) value) > 0x00ffffff)
23729 as_bad_where (fixP->fx_file, fixP->fx_line,
23730 _("invalid swi expression"));
23731 newval = md_chars_to_number (buf, INSN_SIZE);
23733 md_number_to_chars (buf, newval, INSN_SIZE);
23737 case BFD_RELOC_ARM_MULTI:
23738 if (((unsigned long) value) > 0xffff)
23739 as_bad_where (fixP->fx_file, fixP->fx_line,
23740 _("invalid expression in load/store multiple"));
23741 newval = value | md_chars_to_number (buf, INSN_SIZE);
23742 md_number_to_chars (buf, newval, INSN_SIZE);
23746 case BFD_RELOC_ARM_PCREL_CALL:
23748 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23750 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23751 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23752 && THUMB_IS_FUNC (fixP->fx_addsy))
23753 /* Flip the bl to blx. This is a simple flip
23754 bit here because we generate PCREL_CALL for
23755 unconditional bls. */
23757 newval = md_chars_to_number (buf, INSN_SIZE);
23758 newval = newval | 0x10000000;
23759 md_number_to_chars (buf, newval, INSN_SIZE);
23765 goto arm_branch_common;
23767 case BFD_RELOC_ARM_PCREL_JUMP:
23768 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23770 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23771 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23772 && THUMB_IS_FUNC (fixP->fx_addsy))
23774 /* This would map to a bl<cond>, b<cond>,
23775 b<always> to a Thumb function. We
23776 need to force a relocation for this particular
23778 newval = md_chars_to_number (buf, INSN_SIZE);
23781 /* Fall through. */
23783 case BFD_RELOC_ARM_PLT32:
23785 case BFD_RELOC_ARM_PCREL_BRANCH:
23787 goto arm_branch_common;
23789 case BFD_RELOC_ARM_PCREL_BLX:
23792 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
23794 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23795 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23796 && ARM_IS_FUNC (fixP->fx_addsy))
23798 /* Flip the blx to a bl and warn. */
23799 const char *name = S_GET_NAME (fixP->fx_addsy);
23800 newval = 0xeb000000;
23801 as_warn_where (fixP->fx_file, fixP->fx_line,
23802 _("blx to '%s' an ARM ISA state function changed to bl"),
23804 md_number_to_chars (buf, newval, INSN_SIZE);
23810 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23811 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
23815 /* We are going to store value (shifted right by two) in the
23816 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23817 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23820 as_bad_where (fixP->fx_file, fixP->fx_line,
23821 _("misaligned branch destination"));
23822 if ((value & (offsetT)0xfe000000) != (offsetT)0
23823 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
23824 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23826 if (fixP->fx_done || !seg->use_rela_p)
23828 newval = md_chars_to_number (buf, INSN_SIZE);
23829 newval |= (value >> 2) & 0x00ffffff;
23830 /* Set the H bit on BLX instructions. */
23834 newval |= 0x01000000;
23836 newval &= ~0x01000000;
23838 md_number_to_chars (buf, newval, INSN_SIZE);
23842 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
23843 /* CBZ can only branch forward. */
23845 /* Attempts to use CBZ to branch to the next instruction
23846 (which, strictly speaking, are prohibited) will be turned into
23849 FIXME: It may be better to remove the instruction completely and
23850 perform relaxation. */
23853 newval = md_chars_to_number (buf, THUMB_SIZE);
23854 newval = 0xbf00; /* NOP encoding T1 */
23855 md_number_to_chars (buf, newval, THUMB_SIZE);
23860 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23862 if (fixP->fx_done || !seg->use_rela_p)
23864 newval = md_chars_to_number (buf, THUMB_SIZE);
23865 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
23866 md_number_to_chars (buf, newval, THUMB_SIZE);
23871 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
23872 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
23873 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23875 if (fixP->fx_done || !seg->use_rela_p)
23877 newval = md_chars_to_number (buf, THUMB_SIZE);
23878 newval |= (value & 0x1ff) >> 1;
23879 md_number_to_chars (buf, newval, THUMB_SIZE);
23883 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
23884 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
23885 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23887 if (fixP->fx_done || !seg->use_rela_p)
23889 newval = md_chars_to_number (buf, THUMB_SIZE);
23890 newval |= (value & 0xfff) >> 1;
23891 md_number_to_chars (buf, newval, THUMB_SIZE);
23895 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23897 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23898 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23899 && ARM_IS_FUNC (fixP->fx_addsy)
23900 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23902 /* Force a relocation for a branch 20 bits wide. */
23905 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
23906 as_bad_where (fixP->fx_file, fixP->fx_line,
23907 _("conditional branch out of range"));
23909 if (fixP->fx_done || !seg->use_rela_p)
23912 addressT S, J1, J2, lo, hi;
23914 S = (value & 0x00100000) >> 20;
23915 J2 = (value & 0x00080000) >> 19;
23916 J1 = (value & 0x00040000) >> 18;
23917 hi = (value & 0x0003f000) >> 12;
23918 lo = (value & 0x00000ffe) >> 1;
23920 newval = md_chars_to_number (buf, THUMB_SIZE);
23921 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23922 newval |= (S << 10) | hi;
23923 newval2 |= (J1 << 13) | (J2 << 11) | lo;
23924 md_number_to_chars (buf, newval, THUMB_SIZE);
23925 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
23929 case BFD_RELOC_THUMB_PCREL_BLX:
23930 /* If there is a blx from a thumb state function to
23931 another thumb function flip this to a bl and warn
23935 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23936 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23937 && THUMB_IS_FUNC (fixP->fx_addsy))
23939 const char *name = S_GET_NAME (fixP->fx_addsy);
23940 as_warn_where (fixP->fx_file, fixP->fx_line,
23941 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23943 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23944 newval = newval | 0x1000;
23945 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23946 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23951 goto thumb_bl_common;
23953 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23954 /* A bl from Thumb state ISA to an internal ARM state function
23955 is converted to a blx. */
23957 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
23958 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
23959 && ARM_IS_FUNC (fixP->fx_addsy)
23960 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
23962 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
23963 newval = newval & ~0x1000;
23964 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
23965 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
23971 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23972 /* For a BLX instruction, make sure that the relocation is rounded up
23973 to a word boundary. This follows the semantics of the instruction
23974 which specifies that bit 1 of the target address will come from bit
23975 1 of the base address. */
23976 value = (value + 3) & ~ 3;
23979 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
23980 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
23981 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
23984 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
23986 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
23987 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
23988 else if ((value & ~0x1ffffff)
23989 && ((value & ~0x1ffffff) != ~0x1ffffff))
23990 as_bad_where (fixP->fx_file, fixP->fx_line,
23991 _("Thumb2 branch out of range"));
23994 if (fixP->fx_done || !seg->use_rela_p)
23995 encode_thumb2_b_bl_offset (buf, value);
23999 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24000 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
24001 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
24003 if (fixP->fx_done || !seg->use_rela_p)
24004 encode_thumb2_b_bl_offset (buf, value);
24009 if (fixP->fx_done || !seg->use_rela_p)
24014 if (fixP->fx_done || !seg->use_rela_p)
24015 md_number_to_chars (buf, value, 2);
24019 case BFD_RELOC_ARM_TLS_CALL:
24020 case BFD_RELOC_ARM_THM_TLS_CALL:
24021 case BFD_RELOC_ARM_TLS_DESCSEQ:
24022 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
24023 case BFD_RELOC_ARM_TLS_GOTDESC:
24024 case BFD_RELOC_ARM_TLS_GD32:
24025 case BFD_RELOC_ARM_TLS_LE32:
24026 case BFD_RELOC_ARM_TLS_IE32:
24027 case BFD_RELOC_ARM_TLS_LDM32:
24028 case BFD_RELOC_ARM_TLS_LDO32:
24029 S_SET_THREAD_LOCAL (fixP->fx_addsy);
24032 /* Same handling as above, but with the arm_fdpic guard. */
24033 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
24034 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
24035 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
24038 S_SET_THREAD_LOCAL (fixP->fx_addsy);
24042 as_bad_where (fixP->fx_file, fixP->fx_line,
24043 _("Relocation supported only in FDPIC mode"));
24047 case BFD_RELOC_ARM_GOT32:
24048 case BFD_RELOC_ARM_GOTOFF:
24051 case BFD_RELOC_ARM_GOT_PREL:
24052 if (fixP->fx_done || !seg->use_rela_p)
24053 md_number_to_chars (buf, value, 4);
24056 case BFD_RELOC_ARM_TARGET2:
24057 /* TARGET2 is not partial-inplace, so we need to write the
24058 addend here for REL targets, because it won't be written out
24059 during reloc processing later. */
24060 if (fixP->fx_done || !seg->use_rela_p)
24061 md_number_to_chars (buf, fixP->fx_offset, 4);
24064 /* Relocations for FDPIC. */
24065 case BFD_RELOC_ARM_GOTFUNCDESC:
24066 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
24067 case BFD_RELOC_ARM_FUNCDESC:
24070 if (fixP->fx_done || !seg->use_rela_p)
24071 md_number_to_chars (buf, 0, 4);
24075 as_bad_where (fixP->fx_file, fixP->fx_line,
24076 _("Relocation supported only in FDPIC mode"));
24081 case BFD_RELOC_RVA:
24083 case BFD_RELOC_ARM_TARGET1:
24084 case BFD_RELOC_ARM_ROSEGREL32:
24085 case BFD_RELOC_ARM_SBREL32:
24086 case BFD_RELOC_32_PCREL:
24088 case BFD_RELOC_32_SECREL:
24090 if (fixP->fx_done || !seg->use_rela_p)
24092 /* For WinCE we only do this for pcrel fixups. */
24093 if (fixP->fx_done || fixP->fx_pcrel)
24095 md_number_to_chars (buf, value, 4);
24099 case BFD_RELOC_ARM_PREL31:
24100 if (fixP->fx_done || !seg->use_rela_p)
24102 newval = md_chars_to_number (buf, 4) & 0x80000000;
24103 if ((value ^ (value >> 1)) & 0x40000000)
24105 as_bad_where (fixP->fx_file, fixP->fx_line,
24106 _("rel31 relocation overflow"));
24108 newval |= value & 0x7fffffff;
24109 md_number_to_chars (buf, newval, 4);
24114 case BFD_RELOC_ARM_CP_OFF_IMM:
24115 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
24116 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
24117 newval = md_chars_to_number (buf, INSN_SIZE);
24119 newval = get_thumb32_insn (buf);
24120 if ((newval & 0x0f200f00) == 0x0d000900)
24122 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24123 has permitted values that are multiples of 2, in the range 0
24125 if (value < -510 || value > 510 || (value & 1))
24126 as_bad_where (fixP->fx_file, fixP->fx_line,
24127 _("co-processor offset out of range"));
24129 else if (value < -1023 || value > 1023 || (value & 3))
24130 as_bad_where (fixP->fx_file, fixP->fx_line,
24131 _("co-processor offset out of range"));
24136 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
24137 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
24138 newval = md_chars_to_number (buf, INSN_SIZE);
24140 newval = get_thumb32_insn (buf);
24142 newval &= 0xffffff00;
24145 newval &= 0xff7fff00;
24146 if ((newval & 0x0f200f00) == 0x0d000900)
24148 /* This is a fp16 vstr/vldr.
24150 It requires the immediate offset in the instruction is shifted
24151 left by 1 to be a half-word offset.
24153 Here, left shift by 1 first, and later right shift by 2
24154 should get the right offset. */
24157 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
24159 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
24160 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
24161 md_number_to_chars (buf, newval, INSN_SIZE);
24163 put_thumb32_insn (buf, newval);
24166 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
24167 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
24168 if (value < -255 || value > 255)
24169 as_bad_where (fixP->fx_file, fixP->fx_line,
24170 _("co-processor offset out of range"));
24172 goto cp_off_common;
24174 case BFD_RELOC_ARM_THUMB_OFFSET:
24175 newval = md_chars_to_number (buf, THUMB_SIZE);
24176 /* Exactly what ranges, and where the offset is inserted depends
24177 on the type of instruction, we can establish this from the
24179 switch (newval >> 12)
24181 case 4: /* PC load. */
24182 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24183 forced to zero for these loads; md_pcrel_from has already
24184 compensated for this. */
24186 as_bad_where (fixP->fx_file, fixP->fx_line,
24187 _("invalid offset, target not word aligned (0x%08lX)"),
24188 (((unsigned long) fixP->fx_frag->fr_address
24189 + (unsigned long) fixP->fx_where) & ~3)
24190 + (unsigned long) value);
24192 if (value & ~0x3fc)
24193 as_bad_where (fixP->fx_file, fixP->fx_line,
24194 _("invalid offset, value too big (0x%08lX)"),
24197 newval |= value >> 2;
24200 case 9: /* SP load/store. */
24201 if (value & ~0x3fc)
24202 as_bad_where (fixP->fx_file, fixP->fx_line,
24203 _("invalid offset, value too big (0x%08lX)"),
24205 newval |= value >> 2;
24208 case 6: /* Word load/store. */
24210 as_bad_where (fixP->fx_file, fixP->fx_line,
24211 _("invalid offset, value too big (0x%08lX)"),
24213 newval |= value << 4; /* 6 - 2. */
24216 case 7: /* Byte load/store. */
24218 as_bad_where (fixP->fx_file, fixP->fx_line,
24219 _("invalid offset, value too big (0x%08lX)"),
24221 newval |= value << 6;
24224 case 8: /* Halfword load/store. */
24226 as_bad_where (fixP->fx_file, fixP->fx_line,
24227 _("invalid offset, value too big (0x%08lX)"),
24229 newval |= value << 5; /* 6 - 1. */
24233 as_bad_where (fixP->fx_file, fixP->fx_line,
24234 "Unable to process relocation for thumb opcode: %lx",
24235 (unsigned long) newval);
24238 md_number_to_chars (buf, newval, THUMB_SIZE);
24241 case BFD_RELOC_ARM_THUMB_ADD:
24242 /* This is a complicated relocation, since we use it for all of
24243 the following immediate relocations:
24247 9bit ADD/SUB SP word-aligned
24248 10bit ADD PC/SP word-aligned
24250 The type of instruction being processed is encoded in the
24257 newval = md_chars_to_number (buf, THUMB_SIZE);
24259 int rd = (newval >> 4) & 0xf;
24260 int rs = newval & 0xf;
24261 int subtract = !!(newval & 0x8000);
24263 /* Check for HI regs, only very restricted cases allowed:
24264 Adjusting SP, and using PC or SP to get an address. */
24265 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
24266 || (rs > 7 && rs != REG_SP && rs != REG_PC))
24267 as_bad_where (fixP->fx_file, fixP->fx_line,
24268 _("invalid Hi register with immediate"));
24270 /* If value is negative, choose the opposite instruction. */
24274 subtract = !subtract;
24276 as_bad_where (fixP->fx_file, fixP->fx_line,
24277 _("immediate value out of range"));
24282 if (value & ~0x1fc)
24283 as_bad_where (fixP->fx_file, fixP->fx_line,
24284 _("invalid immediate for stack address calculation"));
24285 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
24286 newval |= value >> 2;
24288 else if (rs == REG_PC || rs == REG_SP)
24290 /* PR gas/18541. If the addition is for a defined symbol
24291 within range of an ADR instruction then accept it. */
24294 && fixP->fx_addsy != NULL)
24298 if (! S_IS_DEFINED (fixP->fx_addsy)
24299 || S_GET_SEGMENT (fixP->fx_addsy) != seg
24300 || S_IS_WEAK (fixP->fx_addsy))
24302 as_bad_where (fixP->fx_file, fixP->fx_line,
24303 _("address calculation needs a strongly defined nearby symbol"));
24307 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
24309 /* Round up to the next 4-byte boundary. */
24314 v = S_GET_VALUE (fixP->fx_addsy) - v;
24318 as_bad_where (fixP->fx_file, fixP->fx_line,
24319 _("symbol too far away"));
24329 if (subtract || value & ~0x3fc)
24330 as_bad_where (fixP->fx_file, fixP->fx_line,
24331 _("invalid immediate for address calculation (value = 0x%08lX)"),
24332 (unsigned long) (subtract ? - value : value));
24333 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
24335 newval |= value >> 2;
24340 as_bad_where (fixP->fx_file, fixP->fx_line,
24341 _("immediate value out of range"));
24342 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
24343 newval |= (rd << 8) | value;
24348 as_bad_where (fixP->fx_file, fixP->fx_line,
24349 _("immediate value out of range"));
24350 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
24351 newval |= rd | (rs << 3) | (value << 6);
24354 md_number_to_chars (buf, newval, THUMB_SIZE);
24357 case BFD_RELOC_ARM_THUMB_IMM:
24358 newval = md_chars_to_number (buf, THUMB_SIZE);
24359 if (value < 0 || value > 255)
24360 as_bad_where (fixP->fx_file, fixP->fx_line,
24361 _("invalid immediate: %ld is out of range"),
24364 md_number_to_chars (buf, newval, THUMB_SIZE);
24367 case BFD_RELOC_ARM_THUMB_SHIFT:
24368 /* 5bit shift value (0..32). LSL cannot take 32. */
24369 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
24370 temp = newval & 0xf800;
24371 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
24372 as_bad_where (fixP->fx_file, fixP->fx_line,
24373 _("invalid shift value: %ld"), (long) value);
24374 /* Shifts of zero must be encoded as LSL. */
24376 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
24377 /* Shifts of 32 are encoded as zero. */
24378 else if (value == 32)
24380 newval |= value << 6;
24381 md_number_to_chars (buf, newval, THUMB_SIZE);
24384 case BFD_RELOC_VTABLE_INHERIT:
24385 case BFD_RELOC_VTABLE_ENTRY:
24389 case BFD_RELOC_ARM_MOVW:
24390 case BFD_RELOC_ARM_MOVT:
24391 case BFD_RELOC_ARM_THUMB_MOVW:
24392 case BFD_RELOC_ARM_THUMB_MOVT:
24393 if (fixP->fx_done || !seg->use_rela_p)
24395 /* REL format relocations are limited to a 16-bit addend. */
24396 if (!fixP->fx_done)
24398 if (value < -0x8000 || value > 0x7fff)
24399 as_bad_where (fixP->fx_file, fixP->fx_line,
24400 _("offset out of range"));
24402 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
24403 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
24408 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
24409 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
24411 newval = get_thumb32_insn (buf);
24412 newval &= 0xfbf08f00;
24413 newval |= (value & 0xf000) << 4;
24414 newval |= (value & 0x0800) << 15;
24415 newval |= (value & 0x0700) << 4;
24416 newval |= (value & 0x00ff);
24417 put_thumb32_insn (buf, newval);
24421 newval = md_chars_to_number (buf, 4);
24422 newval &= 0xfff0f000;
24423 newval |= value & 0x0fff;
24424 newval |= (value & 0xf000) << 4;
24425 md_number_to_chars (buf, newval, 4);
24430 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
24431 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
24432 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
24433 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
24434 gas_assert (!fixP->fx_done);
24437 bfd_boolean is_mov;
24438 bfd_vma encoded_addend = value;
24440 /* Check that addend can be encoded in instruction. */
24441 if (!seg->use_rela_p && (value < 0 || value > 255))
24442 as_bad_where (fixP->fx_file, fixP->fx_line,
24443 _("the offset 0x%08lX is not representable"),
24444 (unsigned long) encoded_addend);
24446 /* Extract the instruction. */
24447 insn = md_chars_to_number (buf, THUMB_SIZE);
24448 is_mov = (insn & 0xf800) == 0x2000;
24453 if (!seg->use_rela_p)
24454 insn |= encoded_addend;
24460 /* Extract the instruction. */
24461 /* Encoding is the following
24466 /* The following conditions must be true :
24471 rd = (insn >> 4) & 0xf;
24473 if ((insn & 0x8000) || (rd != rs) || rd > 7)
24474 as_bad_where (fixP->fx_file, fixP->fx_line,
24475 _("Unable to process relocation for thumb opcode: %lx"),
24476 (unsigned long) insn);
24478 /* Encode as ADD immediate8 thumb 1 code. */
24479 insn = 0x3000 | (rd << 8);
24481 /* Place the encoded addend into the first 8 bits of the
24483 if (!seg->use_rela_p)
24484 insn |= encoded_addend;
24487 /* Update the instruction. */
24488 md_number_to_chars (buf, insn, THUMB_SIZE);
24492 case BFD_RELOC_ARM_ALU_PC_G0_NC:
24493 case BFD_RELOC_ARM_ALU_PC_G0:
24494 case BFD_RELOC_ARM_ALU_PC_G1_NC:
24495 case BFD_RELOC_ARM_ALU_PC_G1:
24496 case BFD_RELOC_ARM_ALU_PC_G2:
24497 case BFD_RELOC_ARM_ALU_SB_G0_NC:
24498 case BFD_RELOC_ARM_ALU_SB_G0:
24499 case BFD_RELOC_ARM_ALU_SB_G1_NC:
24500 case BFD_RELOC_ARM_ALU_SB_G1:
24501 case BFD_RELOC_ARM_ALU_SB_G2:
24502 gas_assert (!fixP->fx_done);
24503 if (!seg->use_rela_p)
24506 bfd_vma encoded_addend;
24507 bfd_vma addend_abs = abs (value);
24509 /* Check that the absolute value of the addend can be
24510 expressed as an 8-bit constant plus a rotation. */
24511 encoded_addend = encode_arm_immediate (addend_abs);
24512 if (encoded_addend == (unsigned int) FAIL)
24513 as_bad_where (fixP->fx_file, fixP->fx_line,
24514 _("the offset 0x%08lX is not representable"),
24515 (unsigned long) addend_abs);
24517 /* Extract the instruction. */
24518 insn = md_chars_to_number (buf, INSN_SIZE);
24520 /* If the addend is positive, use an ADD instruction.
24521 Otherwise use a SUB. Take care not to destroy the S bit. */
24522 insn &= 0xff1fffff;
24528 /* Place the encoded addend into the first 12 bits of the
24530 insn &= 0xfffff000;
24531 insn |= encoded_addend;
24533 /* Update the instruction. */
24534 md_number_to_chars (buf, insn, INSN_SIZE);
24538 case BFD_RELOC_ARM_LDR_PC_G0:
24539 case BFD_RELOC_ARM_LDR_PC_G1:
24540 case BFD_RELOC_ARM_LDR_PC_G2:
24541 case BFD_RELOC_ARM_LDR_SB_G0:
24542 case BFD_RELOC_ARM_LDR_SB_G1:
24543 case BFD_RELOC_ARM_LDR_SB_G2:
24544 gas_assert (!fixP->fx_done);
24545 if (!seg->use_rela_p)
24548 bfd_vma addend_abs = abs (value);
24550 /* Check that the absolute value of the addend can be
24551 encoded in 12 bits. */
24552 if (addend_abs >= 0x1000)
24553 as_bad_where (fixP->fx_file, fixP->fx_line,
24554 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24555 (unsigned long) addend_abs);
24557 /* Extract the instruction. */
24558 insn = md_chars_to_number (buf, INSN_SIZE);
24560 /* If the addend is negative, clear bit 23 of the instruction.
24561 Otherwise set it. */
24563 insn &= ~(1 << 23);
24567 /* Place the absolute value of the addend into the first 12 bits
24568 of the instruction. */
24569 insn &= 0xfffff000;
24570 insn |= addend_abs;
24572 /* Update the instruction. */
24573 md_number_to_chars (buf, insn, INSN_SIZE);
24577 case BFD_RELOC_ARM_LDRS_PC_G0:
24578 case BFD_RELOC_ARM_LDRS_PC_G1:
24579 case BFD_RELOC_ARM_LDRS_PC_G2:
24580 case BFD_RELOC_ARM_LDRS_SB_G0:
24581 case BFD_RELOC_ARM_LDRS_SB_G1:
24582 case BFD_RELOC_ARM_LDRS_SB_G2:
24583 gas_assert (!fixP->fx_done);
24584 if (!seg->use_rela_p)
24587 bfd_vma addend_abs = abs (value);
24589 /* Check that the absolute value of the addend can be
24590 encoded in 8 bits. */
24591 if (addend_abs >= 0x100)
24592 as_bad_where (fixP->fx_file, fixP->fx_line,
24593 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24594 (unsigned long) addend_abs);
24596 /* Extract the instruction. */
24597 insn = md_chars_to_number (buf, INSN_SIZE);
24599 /* If the addend is negative, clear bit 23 of the instruction.
24600 Otherwise set it. */
24602 insn &= ~(1 << 23);
24606 /* Place the first four bits of the absolute value of the addend
24607 into the first 4 bits of the instruction, and the remaining
24608 four into bits 8 .. 11. */
24609 insn &= 0xfffff0f0;
24610 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
24612 /* Update the instruction. */
24613 md_number_to_chars (buf, insn, INSN_SIZE);
24617 case BFD_RELOC_ARM_LDC_PC_G0:
24618 case BFD_RELOC_ARM_LDC_PC_G1:
24619 case BFD_RELOC_ARM_LDC_PC_G2:
24620 case BFD_RELOC_ARM_LDC_SB_G0:
24621 case BFD_RELOC_ARM_LDC_SB_G1:
24622 case BFD_RELOC_ARM_LDC_SB_G2:
24623 gas_assert (!fixP->fx_done);
24624 if (!seg->use_rela_p)
24627 bfd_vma addend_abs = abs (value);
24629 /* Check that the absolute value of the addend is a multiple of
24630 four and, when divided by four, fits in 8 bits. */
24631 if (addend_abs & 0x3)
24632 as_bad_where (fixP->fx_file, fixP->fx_line,
24633 _("bad offset 0x%08lX (must be word-aligned)"),
24634 (unsigned long) addend_abs);
24636 if ((addend_abs >> 2) > 0xff)
24637 as_bad_where (fixP->fx_file, fixP->fx_line,
24638 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24639 (unsigned long) addend_abs);
24641 /* Extract the instruction. */
24642 insn = md_chars_to_number (buf, INSN_SIZE);
24644 /* If the addend is negative, clear bit 23 of the instruction.
24645 Otherwise set it. */
24647 insn &= ~(1 << 23);
24651 /* Place the addend (divided by four) into the first eight
24652 bits of the instruction. */
24653 insn &= 0xfffffff0;
24654 insn |= addend_abs >> 2;
24656 /* Update the instruction. */
24657 md_number_to_chars (buf, insn, INSN_SIZE);
24661 case BFD_RELOC_ARM_V4BX:
24662 /* This will need to go in the object file. */
24666 case BFD_RELOC_UNUSED:
24668 as_bad_where (fixP->fx_file, fixP->fx_line,
24669 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
24673 /* Translate internal representation of relocation info to BFD target
24677 tc_gen_reloc (asection *section, fixS *fixp)
24680 bfd_reloc_code_real_type code;
24682 reloc = XNEW (arelent);
24684 reloc->sym_ptr_ptr = XNEW (asymbol *);
24685 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
24686 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
24688 if (fixp->fx_pcrel)
24690 if (section->use_rela_p)
24691 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
24693 fixp->fx_offset = reloc->address;
24695 reloc->addend = fixp->fx_offset;
24697 switch (fixp->fx_r_type)
24700 if (fixp->fx_pcrel)
24702 code = BFD_RELOC_8_PCREL;
24705 /* Fall through. */
24708 if (fixp->fx_pcrel)
24710 code = BFD_RELOC_16_PCREL;
24713 /* Fall through. */
24716 if (fixp->fx_pcrel)
24718 code = BFD_RELOC_32_PCREL;
24721 /* Fall through. */
24723 case BFD_RELOC_ARM_MOVW:
24724 if (fixp->fx_pcrel)
24726 code = BFD_RELOC_ARM_MOVW_PCREL;
24729 /* Fall through. */
24731 case BFD_RELOC_ARM_MOVT:
24732 if (fixp->fx_pcrel)
24734 code = BFD_RELOC_ARM_MOVT_PCREL;
24737 /* Fall through. */
24739 case BFD_RELOC_ARM_THUMB_MOVW:
24740 if (fixp->fx_pcrel)
24742 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
24745 /* Fall through. */
24747 case BFD_RELOC_ARM_THUMB_MOVT:
24748 if (fixp->fx_pcrel)
24750 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
24753 /* Fall through. */
24755 case BFD_RELOC_NONE:
24756 case BFD_RELOC_ARM_PCREL_BRANCH:
24757 case BFD_RELOC_ARM_PCREL_BLX:
24758 case BFD_RELOC_RVA:
24759 case BFD_RELOC_THUMB_PCREL_BRANCH7:
24760 case BFD_RELOC_THUMB_PCREL_BRANCH9:
24761 case BFD_RELOC_THUMB_PCREL_BRANCH12:
24762 case BFD_RELOC_THUMB_PCREL_BRANCH20:
24763 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24764 case BFD_RELOC_THUMB_PCREL_BRANCH25:
24765 case BFD_RELOC_VTABLE_ENTRY:
24766 case BFD_RELOC_VTABLE_INHERIT:
24768 case BFD_RELOC_32_SECREL:
24770 code = fixp->fx_r_type;
24773 case BFD_RELOC_THUMB_PCREL_BLX:
24775 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
24776 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
24779 code = BFD_RELOC_THUMB_PCREL_BLX;
24782 case BFD_RELOC_ARM_LITERAL:
24783 case BFD_RELOC_ARM_HWLITERAL:
24784 /* If this is called then the a literal has
24785 been referenced across a section boundary. */
24786 as_bad_where (fixp->fx_file, fixp->fx_line,
24787 _("literal referenced across section boundary"));
24791 case BFD_RELOC_ARM_TLS_CALL:
24792 case BFD_RELOC_ARM_THM_TLS_CALL:
24793 case BFD_RELOC_ARM_TLS_DESCSEQ:
24794 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
24795 case BFD_RELOC_ARM_GOT32:
24796 case BFD_RELOC_ARM_GOTOFF:
24797 case BFD_RELOC_ARM_GOT_PREL:
24798 case BFD_RELOC_ARM_PLT32:
24799 case BFD_RELOC_ARM_TARGET1:
24800 case BFD_RELOC_ARM_ROSEGREL32:
24801 case BFD_RELOC_ARM_SBREL32:
24802 case BFD_RELOC_ARM_PREL31:
24803 case BFD_RELOC_ARM_TARGET2:
24804 case BFD_RELOC_ARM_TLS_LDO32:
24805 case BFD_RELOC_ARM_PCREL_CALL:
24806 case BFD_RELOC_ARM_PCREL_JUMP:
24807 case BFD_RELOC_ARM_ALU_PC_G0_NC:
24808 case BFD_RELOC_ARM_ALU_PC_G0:
24809 case BFD_RELOC_ARM_ALU_PC_G1_NC:
24810 case BFD_RELOC_ARM_ALU_PC_G1:
24811 case BFD_RELOC_ARM_ALU_PC_G2:
24812 case BFD_RELOC_ARM_LDR_PC_G0:
24813 case BFD_RELOC_ARM_LDR_PC_G1:
24814 case BFD_RELOC_ARM_LDR_PC_G2:
24815 case BFD_RELOC_ARM_LDRS_PC_G0:
24816 case BFD_RELOC_ARM_LDRS_PC_G1:
24817 case BFD_RELOC_ARM_LDRS_PC_G2:
24818 case BFD_RELOC_ARM_LDC_PC_G0:
24819 case BFD_RELOC_ARM_LDC_PC_G1:
24820 case BFD_RELOC_ARM_LDC_PC_G2:
24821 case BFD_RELOC_ARM_ALU_SB_G0_NC:
24822 case BFD_RELOC_ARM_ALU_SB_G0:
24823 case BFD_RELOC_ARM_ALU_SB_G1_NC:
24824 case BFD_RELOC_ARM_ALU_SB_G1:
24825 case BFD_RELOC_ARM_ALU_SB_G2:
24826 case BFD_RELOC_ARM_LDR_SB_G0:
24827 case BFD_RELOC_ARM_LDR_SB_G1:
24828 case BFD_RELOC_ARM_LDR_SB_G2:
24829 case BFD_RELOC_ARM_LDRS_SB_G0:
24830 case BFD_RELOC_ARM_LDRS_SB_G1:
24831 case BFD_RELOC_ARM_LDRS_SB_G2:
24832 case BFD_RELOC_ARM_LDC_SB_G0:
24833 case BFD_RELOC_ARM_LDC_SB_G1:
24834 case BFD_RELOC_ARM_LDC_SB_G2:
24835 case BFD_RELOC_ARM_V4BX:
24836 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
24837 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
24838 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
24839 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
24840 case BFD_RELOC_ARM_GOTFUNCDESC:
24841 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
24842 case BFD_RELOC_ARM_FUNCDESC:
24843 code = fixp->fx_r_type;
24846 case BFD_RELOC_ARM_TLS_GOTDESC:
24847 case BFD_RELOC_ARM_TLS_GD32:
24848 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
24849 case BFD_RELOC_ARM_TLS_LE32:
24850 case BFD_RELOC_ARM_TLS_IE32:
24851 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
24852 case BFD_RELOC_ARM_TLS_LDM32:
24853 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
24854 /* BFD will include the symbol's address in the addend.
24855 But we don't want that, so subtract it out again here. */
24856 if (!S_IS_COMMON (fixp->fx_addsy))
24857 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
24858 code = fixp->fx_r_type;
24862 case BFD_RELOC_ARM_IMMEDIATE:
24863 as_bad_where (fixp->fx_file, fixp->fx_line,
24864 _("internal relocation (type: IMMEDIATE) not fixed up"));
24867 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
24868 as_bad_where (fixp->fx_file, fixp->fx_line,
24869 _("ADRL used for a symbol not defined in the same file"));
24872 case BFD_RELOC_ARM_OFFSET_IMM:
24873 if (section->use_rela_p)
24875 code = fixp->fx_r_type;
24879 if (fixp->fx_addsy != NULL
24880 && !S_IS_DEFINED (fixp->fx_addsy)
24881 && S_IS_LOCAL (fixp->fx_addsy))
24883 as_bad_where (fixp->fx_file, fixp->fx_line,
24884 _("undefined local label `%s'"),
24885 S_GET_NAME (fixp->fx_addsy));
24889 as_bad_where (fixp->fx_file, fixp->fx_line,
24890 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24897 switch (fixp->fx_r_type)
24899 case BFD_RELOC_NONE: type = "NONE"; break;
24900 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
24901 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
24902 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
24903 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
24904 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
24905 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
24906 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
24907 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
24908 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
24909 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
24910 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
24911 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
24912 default: type = _("<unknown>"); break;
24914 as_bad_where (fixp->fx_file, fixp->fx_line,
24915 _("cannot represent %s relocation in this object file format"),
24922 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
24924 && fixp->fx_addsy == GOT_symbol)
24926 code = BFD_RELOC_ARM_GOTPC;
24927 reloc->addend = fixp->fx_offset = reloc->address;
24931 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
24933 if (reloc->howto == NULL)
24935 as_bad_where (fixp->fx_file, fixp->fx_line,
24936 _("cannot represent %s relocation in this object file format"),
24937 bfd_get_reloc_code_name (code));
24941 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24942 vtable entry to be used in the relocation's section offset. */
24943 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
24944 reloc->address = fixp->fx_offset;
24949 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24952 cons_fix_new_arm (fragS * frag,
24956 bfd_reloc_code_real_type reloc)
24961 FIXME: @@ Should look at CPU word size. */
24965 reloc = BFD_RELOC_8;
24968 reloc = BFD_RELOC_16;
24972 reloc = BFD_RELOC_32;
24975 reloc = BFD_RELOC_64;
24980 if (exp->X_op == O_secrel)
24982 exp->X_op = O_symbol;
24983 reloc = BFD_RELOC_32_SECREL;
24987 fix_new_exp (frag, where, size, exp, pcrel, reloc);
24990 #if defined (OBJ_COFF)
24992 arm_validate_fix (fixS * fixP)
24994 /* If the destination of the branch is a defined symbol which does not have
24995 the THUMB_FUNC attribute, then we must be calling a function which has
24996 the (interfacearm) attribute. We look for the Thumb entry point to that
24997 function and change the branch to refer to that function instead. */
24998 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
24999 && fixP->fx_addsy != NULL
25000 && S_IS_DEFINED (fixP->fx_addsy)
25001 && ! THUMB_IS_FUNC (fixP->fx_addsy))
25003 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
25010 arm_force_relocation (struct fix * fixp)
25012 #if defined (OBJ_COFF) && defined (TE_PE)
25013 if (fixp->fx_r_type == BFD_RELOC_RVA)
25017 /* In case we have a call or a branch to a function in ARM ISA mode from
25018 a thumb function or vice-versa force the relocation. These relocations
25019 are cleared off for some cores that might have blx and simple transformations
25023 switch (fixp->fx_r_type)
25025 case BFD_RELOC_ARM_PCREL_JUMP:
25026 case BFD_RELOC_ARM_PCREL_CALL:
25027 case BFD_RELOC_THUMB_PCREL_BLX:
25028 if (THUMB_IS_FUNC (fixp->fx_addsy))
25032 case BFD_RELOC_ARM_PCREL_BLX:
25033 case BFD_RELOC_THUMB_PCREL_BRANCH25:
25034 case BFD_RELOC_THUMB_PCREL_BRANCH20:
25035 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25036 if (ARM_IS_FUNC (fixp->fx_addsy))
25045 /* Resolve these relocations even if the symbol is extern or weak.
25046 Technically this is probably wrong due to symbol preemption.
25047 In practice these relocations do not have enough range to be useful
25048 at dynamic link time, and some code (e.g. in the Linux kernel)
25049 expects these references to be resolved. */
25050 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
25051 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
25052 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
25053 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
25054 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
25055 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
25056 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
25057 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
25058 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
25059 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
25060 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
25061 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
25062 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
25063 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
25066 /* Always leave these relocations for the linker. */
25067 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
25068 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
25069 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
25072 /* Always generate relocations against function symbols. */
25073 if (fixp->fx_r_type == BFD_RELOC_32
25075 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
25078 return generic_force_reloc (fixp);
25081 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25082 /* Relocations against function names must be left unadjusted,
25083 so that the linker can use this information to generate interworking
25084 stubs. The MIPS version of this function
25085 also prevents relocations that are mips-16 specific, but I do not
25086 know why it does this.
25089 There is one other problem that ought to be addressed here, but
25090 which currently is not: Taking the address of a label (rather
25091 than a function) and then later jumping to that address. Such
25092 addresses also ought to have their bottom bit set (assuming that
25093 they reside in Thumb code), but at the moment they will not. */
25096 arm_fix_adjustable (fixS * fixP)
25098 if (fixP->fx_addsy == NULL)
25101 /* Preserve relocations against symbols with function type. */
25102 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
25105 if (THUMB_IS_FUNC (fixP->fx_addsy)
25106 && fixP->fx_subsy == NULL)
25109 /* We need the symbol name for the VTABLE entries. */
25110 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
25111 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
25114 /* Don't allow symbols to be discarded on GOT related relocs. */
25115 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
25116 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
25117 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
25118 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
25119 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
25120 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
25121 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
25122 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
25123 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
25124 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
25125 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
25126 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
25127 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
25128 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
25129 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
25130 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
25131 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
25134 /* Similarly for group relocations. */
25135 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
25136 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
25137 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
25140 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25141 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
25142 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
25143 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
25144 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
25145 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
25146 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
25147 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
25148 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
25151 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25152 offsets, so keep these symbols. */
25153 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25154 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
25159 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25163 elf32_arm_target_format (void)
25166 return (target_big_endian
25167 ? "elf32-bigarm-symbian"
25168 : "elf32-littlearm-symbian");
25169 #elif defined (TE_VXWORKS)
25170 return (target_big_endian
25171 ? "elf32-bigarm-vxworks"
25172 : "elf32-littlearm-vxworks");
25173 #elif defined (TE_NACL)
25174 return (target_big_endian
25175 ? "elf32-bigarm-nacl"
25176 : "elf32-littlearm-nacl");
25180 if (target_big_endian)
25181 return "elf32-bigarm-fdpic";
25183 return "elf32-littlearm-fdpic";
25187 if (target_big_endian)
25188 return "elf32-bigarm";
25190 return "elf32-littlearm";
25196 armelf_frob_symbol (symbolS * symp,
25199 elf_frob_symbol (symp, puntp);
25203 /* MD interface: Finalization. */
25208 literal_pool * pool;
25210 /* Ensure that all the IT blocks are properly closed. */
25211 check_it_blocks_finished ();
25213 for (pool = list_of_pools; pool; pool = pool->next)
25215 /* Put it at the end of the relevant section. */
25216 subseg_set (pool->section, pool->sub_section);
25218 arm_elf_change_section ();
25225 /* Remove any excess mapping symbols generated for alignment frags in
25226 SEC. We may have created a mapping symbol before a zero byte
25227 alignment; remove it if there's a mapping symbol after the
25230 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
25231 void *dummy ATTRIBUTE_UNUSED)
25233 segment_info_type *seginfo = seg_info (sec);
25236 if (seginfo == NULL || seginfo->frchainP == NULL)
25239 for (fragp = seginfo->frchainP->frch_root;
25241 fragp = fragp->fr_next)
25243 symbolS *sym = fragp->tc_frag_data.last_map;
25244 fragS *next = fragp->fr_next;
25246 /* Variable-sized frags have been converted to fixed size by
25247 this point. But if this was variable-sized to start with,
25248 there will be a fixed-size frag after it. So don't handle
25250 if (sym == NULL || next == NULL)
25253 if (S_GET_VALUE (sym) < next->fr_address)
25254 /* Not at the end of this frag. */
25256 know (S_GET_VALUE (sym) == next->fr_address);
25260 if (next->tc_frag_data.first_map != NULL)
25262 /* Next frag starts with a mapping symbol. Discard this
25264 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
25268 if (next->fr_next == NULL)
25270 /* This mapping symbol is at the end of the section. Discard
25272 know (next->fr_fix == 0 && next->fr_var == 0);
25273 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
25277 /* As long as we have empty frags without any mapping symbols,
25279 /* If the next frag is non-empty and does not start with a
25280 mapping symbol, then this mapping symbol is required. */
25281 if (next->fr_address != next->fr_next->fr_address)
25284 next = next->fr_next;
25286 while (next != NULL);
25291 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25295 arm_adjust_symtab (void)
25300 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
25302 if (ARM_IS_THUMB (sym))
25304 if (THUMB_IS_FUNC (sym))
25306 /* Mark the symbol as a Thumb function. */
25307 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
25308 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
25309 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
25311 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
25312 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
25314 as_bad (_("%s: unexpected function type: %d"),
25315 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
25317 else switch (S_GET_STORAGE_CLASS (sym))
25320 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
25323 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
25326 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
25334 if (ARM_IS_INTERWORK (sym))
25335 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
25342 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
25344 if (ARM_IS_THUMB (sym))
25346 elf_symbol_type * elf_sym;
25348 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
25349 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
25351 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
25352 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
25354 /* If it's a .thumb_func, declare it as so,
25355 otherwise tag label as .code 16. */
25356 if (THUMB_IS_FUNC (sym))
25357 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
25358 ST_BRANCH_TO_THUMB);
25359 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
25360 elf_sym->internal_elf_sym.st_info =
25361 ELF_ST_INFO (bind, STT_ARM_16BIT);
25366 /* Remove any overlapping mapping symbols generated by alignment frags. */
25367 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
25368 /* Now do generic ELF adjustments. */
25369 elf_adjust_symtab ();
25373 /* MD interface: Initialization. */
25376 set_constant_flonums (void)
25380 for (i = 0; i < NUM_FLOAT_VALS; i++)
25381 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
25385 /* Auto-select Thumb mode if it's the only available instruction set for the
25386 given architecture. */
25389 autoselect_thumb_from_cpu_variant (void)
25391 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
25392 opcode_select (16);
25401 if ( (arm_ops_hsh = hash_new ()) == NULL
25402 || (arm_cond_hsh = hash_new ()) == NULL
25403 || (arm_shift_hsh = hash_new ()) == NULL
25404 || (arm_psr_hsh = hash_new ()) == NULL
25405 || (arm_v7m_psr_hsh = hash_new ()) == NULL
25406 || (arm_reg_hsh = hash_new ()) == NULL
25407 || (arm_reloc_hsh = hash_new ()) == NULL
25408 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
25409 as_fatal (_("virtual memory exhausted"));
25411 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
25412 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
25413 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
25414 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
25415 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
25416 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
25417 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
25418 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
25419 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
25420 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
25421 (void *) (v7m_psrs + i));
25422 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
25423 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
25425 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
25427 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
25428 (void *) (barrier_opt_names + i));
25430 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
25432 struct reloc_entry * entry = reloc_names + i;
25434 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
25435 /* This makes encode_branch() use the EABI versions of this relocation. */
25436 entry->reloc = BFD_RELOC_UNUSED;
25438 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
25442 set_constant_flonums ();
25444 /* Set the cpu variant based on the command-line options. We prefer
25445 -mcpu= over -march= if both are set (as for GCC); and we prefer
25446 -mfpu= over any other way of setting the floating point unit.
25447 Use of legacy options with new options are faulted. */
25450 if (mcpu_cpu_opt || march_cpu_opt)
25451 as_bad (_("use of old and new-style options to set CPU type"));
25453 selected_arch = *legacy_cpu;
25455 else if (mcpu_cpu_opt)
25457 selected_arch = *mcpu_cpu_opt;
25458 selected_ext = *mcpu_ext_opt;
25460 else if (march_cpu_opt)
25462 selected_arch = *march_cpu_opt;
25463 selected_ext = *march_ext_opt;
25465 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
25470 as_bad (_("use of old and new-style options to set FPU type"));
25472 selected_fpu = *legacy_fpu;
25475 selected_fpu = *mfpu_opt;
25478 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25479 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25480 /* Some environments specify a default FPU. If they don't, infer it
25481 from the processor. */
25483 selected_fpu = *mcpu_fpu_opt;
25484 else if (march_fpu_opt)
25485 selected_fpu = *march_fpu_opt;
25487 selected_fpu = fpu_default;
25491 if (ARM_FEATURE_ZERO (selected_fpu))
25493 if (!no_cpu_selected ())
25494 selected_fpu = fpu_default;
25496 selected_fpu = fpu_arch_fpa;
25500 if (ARM_FEATURE_ZERO (selected_arch))
25502 selected_arch = cpu_default;
25503 selected_cpu = selected_arch;
25505 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
25507 /* Autodection of feature mode: allow all features in cpu_variant but leave
25508 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25509 after all instruction have been processed and we can decide what CPU
25510 should be selected. */
25511 if (ARM_FEATURE_ZERO (selected_arch))
25512 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
25514 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
25517 autoselect_thumb_from_cpu_variant ();
25519 arm_arch_used = thumb_arch_used = arm_arch_none;
25521 #if defined OBJ_COFF || defined OBJ_ELF
25523 unsigned int flags = 0;
25525 #if defined OBJ_ELF
25526 flags = meabi_flags;
25528 switch (meabi_flags)
25530 case EF_ARM_EABI_UNKNOWN:
25532 /* Set the flags in the private structure. */
25533 if (uses_apcs_26) flags |= F_APCS26;
25534 if (support_interwork) flags |= F_INTERWORK;
25535 if (uses_apcs_float) flags |= F_APCS_FLOAT;
25536 if (pic_code) flags |= F_PIC;
25537 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
25538 flags |= F_SOFT_FLOAT;
25540 switch (mfloat_abi_opt)
25542 case ARM_FLOAT_ABI_SOFT:
25543 case ARM_FLOAT_ABI_SOFTFP:
25544 flags |= F_SOFT_FLOAT;
25547 case ARM_FLOAT_ABI_HARD:
25548 if (flags & F_SOFT_FLOAT)
25549 as_bad (_("hard-float conflicts with specified fpu"));
25553 /* Using pure-endian doubles (even if soft-float). */
25554 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
25555 flags |= F_VFP_FLOAT;
25557 #if defined OBJ_ELF
25558 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
25559 flags |= EF_ARM_MAVERICK_FLOAT;
25562 case EF_ARM_EABI_VER4:
25563 case EF_ARM_EABI_VER5:
25564 /* No additional flags to set. */
25571 bfd_set_private_flags (stdoutput, flags);
25573 /* We have run out flags in the COFF header to encode the
25574 status of ATPCS support, so instead we create a dummy,
25575 empty, debug section called .arm.atpcs. */
25580 sec = bfd_make_section (stdoutput, ".arm.atpcs");
25584 bfd_set_section_flags
25585 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
25586 bfd_set_section_size (stdoutput, sec, 0);
25587 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
25593 /* Record the CPU type as well. */
25594 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
25595 mach = bfd_mach_arm_iWMMXt2;
25596 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
25597 mach = bfd_mach_arm_iWMMXt;
25598 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
25599 mach = bfd_mach_arm_XScale;
25600 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
25601 mach = bfd_mach_arm_ep9312;
25602 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
25603 mach = bfd_mach_arm_5TE;
25604 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
25606 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
25607 mach = bfd_mach_arm_5T;
25609 mach = bfd_mach_arm_5;
25611 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
25613 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
25614 mach = bfd_mach_arm_4T;
25616 mach = bfd_mach_arm_4;
25618 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
25619 mach = bfd_mach_arm_3M;
25620 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
25621 mach = bfd_mach_arm_3;
25622 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
25623 mach = bfd_mach_arm_2a;
25624 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
25625 mach = bfd_mach_arm_2;
25627 mach = bfd_mach_arm_unknown;
25629 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
25632 /* Command line processing. */
25635 Invocation line includes a switch not recognized by the base assembler.
25636 See if it's a processor-specific option.
25638 This routine is somewhat complicated by the need for backwards
25639 compatibility (since older releases of gcc can't be changed).
25640 The new options try to make the interface as compatible as
25643 New options (supported) are:
25645 -mcpu=<cpu name> Assemble for selected processor
25646 -march=<architecture name> Assemble for selected architecture
25647 -mfpu=<fpu architecture> Assemble for selected FPU.
25648 -EB/-mbig-endian Big-endian
25649 -EL/-mlittle-endian Little-endian
25650 -k Generate PIC code
25651 -mthumb Start in Thumb mode
25652 -mthumb-interwork Code supports ARM/Thumb interworking
25654 -m[no-]warn-deprecated Warn about deprecated features
25655 -m[no-]warn-syms Warn when symbols match instructions
25657 For now we will also provide support for:
25659 -mapcs-32 32-bit Program counter
25660 -mapcs-26 26-bit Program counter
25661 -macps-float Floats passed in FP registers
25662 -mapcs-reentrant Reentrant code
25664 (sometime these will probably be replaced with -mapcs=<list of options>
25665 and -matpcs=<list of options>)
25667 The remaining options are only supported for back-wards compatibility.
25668 Cpu variants, the arm part is optional:
25669 -m[arm]1 Currently not supported.
25670 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25671 -m[arm]3 Arm 3 processor
25672 -m[arm]6[xx], Arm 6 processors
25673 -m[arm]7[xx][t][[d]m] Arm 7 processors
25674 -m[arm]8[10] Arm 8 processors
25675 -m[arm]9[20][tdmi] Arm 9 processors
25676 -mstrongarm[110[0]] StrongARM processors
25677 -mxscale XScale processors
25678 -m[arm]v[2345[t[e]]] Arm architectures
25679 -mall All (except the ARM1)
25681 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25682 -mfpe-old (No float load/store multiples)
25683 -mvfpxd VFP Single precision
25685 -mno-fpu Disable all floating point instructions
25687 The following CPU names are recognized:
25688 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25689 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25690 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25691 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25692 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25693 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25694 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25698 const char * md_shortopts = "m:k";
25700 #ifdef ARM_BI_ENDIAN
25701 #define OPTION_EB (OPTION_MD_BASE + 0)
25702 #define OPTION_EL (OPTION_MD_BASE + 1)
25704 #if TARGET_BYTES_BIG_ENDIAN
25705 #define OPTION_EB (OPTION_MD_BASE + 0)
25707 #define OPTION_EL (OPTION_MD_BASE + 1)
25710 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25711 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
25713 struct option md_longopts[] =
25716 {"EB", no_argument, NULL, OPTION_EB},
25719 {"EL", no_argument, NULL, OPTION_EL},
25721 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
25723 {"fdpic", no_argument, NULL, OPTION_FDPIC},
25725 {NULL, no_argument, NULL, 0}
25728 size_t md_longopts_size = sizeof (md_longopts);
25730 struct arm_option_table
25732 const char * option; /* Option name to match. */
25733 const char * help; /* Help information. */
25734 int * var; /* Variable to change. */
25735 int value; /* What to change it to. */
25736 const char * deprecated; /* If non-null, print this message. */
25739 struct arm_option_table arm_opts[] =
25741 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
25742 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
25743 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25744 &support_interwork, 1, NULL},
25745 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
25746 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
25747 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
25749 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
25750 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
25751 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
25752 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
25755 /* These are recognized by the assembler, but have no affect on code. */
25756 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
25757 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
25759 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
25760 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25761 &warn_on_deprecated, 0, NULL},
25762 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
25763 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
25764 {NULL, NULL, NULL, 0, NULL}
25767 struct arm_legacy_option_table
25769 const char * option; /* Option name to match. */
25770 const arm_feature_set ** var; /* Variable to change. */
25771 const arm_feature_set value; /* What to change it to. */
25772 const char * deprecated; /* If non-null, print this message. */
25775 const struct arm_legacy_option_table arm_legacy_opts[] =
25777 /* DON'T add any new processors to this list -- we want the whole list
25778 to go away... Add them to the processors table instead. */
25779 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25780 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
25781 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25782 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
25783 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25784 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
25785 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25786 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
25787 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25788 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
25789 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25790 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
25791 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25792 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
25793 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25794 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
25795 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25796 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
25797 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25798 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
25799 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25800 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
25801 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25802 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
25803 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25804 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
25805 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25806 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
25807 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25808 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
25809 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25810 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
25811 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25812 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
25813 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25814 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
25815 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25816 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
25817 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25818 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
25819 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25820 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
25821 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25822 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
25823 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25824 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
25825 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25826 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25827 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25828 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
25829 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25830 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
25831 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25832 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
25833 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25834 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
25835 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25836 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
25837 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25838 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
25839 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25840 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
25841 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25842 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
25843 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25844 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
25845 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25846 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
25847 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
25848 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
25849 N_("use -mcpu=strongarm110")},
25850 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
25851 N_("use -mcpu=strongarm1100")},
25852 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
25853 N_("use -mcpu=strongarm1110")},
25854 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
25855 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
25856 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
25858 /* Architecture variants -- don't add any more to this list either. */
25859 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25860 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
25861 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25862 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
25863 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25864 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
25865 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25866 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
25867 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25868 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
25869 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25870 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
25871 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25872 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
25873 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25874 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
25875 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25876 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
25878 /* Floating point variants -- don't add any more to this list either. */
25879 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
25880 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
25881 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
25882 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
25883 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25885 {NULL, NULL, ARM_ARCH_NONE, NULL}
25888 struct arm_cpu_option_table
25892 const arm_feature_set value;
25893 const arm_feature_set ext;
25894 /* For some CPUs we assume an FPU unless the user explicitly sets
25896 const arm_feature_set default_fpu;
25897 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25899 const char * canonical_name;
25902 /* This list should, at a minimum, contain all the cpu names
25903 recognized by GCC. */
25904 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25906 static const struct arm_cpu_option_table arm_cpus[] =
25908 ARM_CPU_OPT ("all", NULL, ARM_ANY,
25911 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
25914 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
25917 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
25920 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
25923 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
25926 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
25929 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
25932 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
25935 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
25938 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
25941 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
25944 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
25947 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
25950 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
25953 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
25956 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
25959 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
25962 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
25965 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
25968 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
25971 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
25974 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
25977 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
25980 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
25983 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
25986 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
25989 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
25992 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
25995 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
25998 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
26001 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
26004 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
26007 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
26010 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
26013 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
26016 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
26019 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
26022 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
26025 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
26028 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
26031 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
26034 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
26037 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
26040 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
26043 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
26047 /* For V5 or later processors we default to using VFP; but the user
26048 should really set the FPU type explicitly. */
26049 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
26052 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
26055 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
26058 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
26061 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
26064 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
26067 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
26070 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
26073 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
26076 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
26079 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
26082 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
26085 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
26088 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
26091 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
26094 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
26097 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
26100 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
26103 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
26106 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
26109 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
26112 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
26115 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
26118 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
26121 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
26124 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
26127 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
26130 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
26133 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
26136 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
26139 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
26142 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
26145 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
26148 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
26151 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
26154 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
26157 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
26158 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
26160 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
26162 FPU_ARCH_NEON_VFP_V4),
26163 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
26164 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
26165 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
26166 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
26167 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
26168 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
26169 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
26171 FPU_ARCH_NEON_VFP_V4),
26172 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
26174 FPU_ARCH_NEON_VFP_V4),
26175 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
26177 FPU_ARCH_NEON_VFP_V4),
26178 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
26179 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26180 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26181 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
26182 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26183 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26184 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
26185 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26186 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26187 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
26188 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26189 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
26190 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
26191 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26192 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26193 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
26194 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26195 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26196 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
26197 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26198 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26199 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
26200 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26201 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
26202 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
26203 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26204 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
26205 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
26206 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26207 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
26208 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
26211 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
26213 FPU_ARCH_VFP_V3D16),
26214 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
26215 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
26217 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
26218 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
26219 FPU_ARCH_VFP_V3D16),
26220 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
26221 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
26222 FPU_ARCH_VFP_V3D16),
26223 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
26224 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26225 FPU_ARCH_NEON_VFP_ARMV8),
26226 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
26227 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
26229 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
26232 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
26235 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
26238 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
26241 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
26244 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
26247 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
26250 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
26251 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26252 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26254 /* ??? XSCALE is really an architecture. */
26255 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
26259 /* ??? iwmmxt is not a processor. */
26260 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
26263 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
26266 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
26271 ARM_CPU_OPT ("ep9312", "ARM920T",
26272 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
26273 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
26275 /* Marvell processors. */
26276 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
26277 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
26278 FPU_ARCH_VFP_V3D16),
26279 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
26280 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
26281 FPU_ARCH_NEON_VFP_V4),
26283 /* APM X-Gene family. */
26284 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
26286 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26287 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
26288 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26289 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
26291 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
26295 struct arm_arch_option_table
26299 const arm_feature_set value;
26300 const arm_feature_set default_fpu;
26303 /* This list should, at a minimum, contain all the architecture names
26304 recognized by GCC. */
26305 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26307 static const struct arm_arch_option_table arm_archs[] =
26309 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
26310 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
26311 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
26312 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
26313 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
26314 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
26315 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
26316 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
26317 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
26318 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
26319 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
26320 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
26321 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
26322 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
26323 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
26324 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
26325 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
26326 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
26327 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
26328 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
26329 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
26330 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26331 kept to preserve existing behaviour. */
26332 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
26333 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP),
26334 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
26335 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
26336 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
26337 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26338 kept to preserve existing behaviour. */
26339 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
26340 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP),
26341 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
26342 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
26343 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
26344 /* The official spelling of the ARMv7 profile variants is the dashed form.
26345 Accept the non-dashed form for compatibility with old toolchains. */
26346 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
26347 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
26348 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
26349 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
26350 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
26351 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
26352 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
26353 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
26354 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
26355 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP),
26356 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
26357 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP),
26358 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP),
26359 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP),
26360 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP),
26361 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP),
26362 ARM_ARCH_OPT ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP),
26363 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
26364 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
26365 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
26366 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
26368 #undef ARM_ARCH_OPT
26370 /* ISA extensions in the co-processor and main instruction set space. */
26372 struct arm_option_extension_value_table
26376 const arm_feature_set merge_value;
26377 const arm_feature_set clear_value;
26378 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26379 indicates that an extension is available for all architectures while
26380 ARM_ANY marks an empty entry. */
26381 const arm_feature_set allowed_archs[2];
26384 /* The following table must be in alphabetical order with a NULL last entry. */
26386 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26387 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26389 static const struct arm_option_extension_value_table arm_extensions[] =
26391 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
26392 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
26393 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
26394 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
26395 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
26396 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
26397 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
26399 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
26400 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
26401 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
26402 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
26403 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
26404 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26405 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
26407 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26408 | ARM_EXT2_FP16_FML),
26409 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26410 | ARM_EXT2_FP16_FML),
26412 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
26413 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
26414 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
26415 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
26416 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26417 Thumb divide instruction. Due to this having the same name as the
26418 previous entry, this will be ignored when doing command-line parsing and
26419 only considered by build attribute selection code. */
26420 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
26421 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
26422 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
26423 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
26424 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
26425 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
26426 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
26427 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
26428 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
26429 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
26430 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
26431 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
26432 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
26433 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
26434 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
26435 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
26436 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
26437 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
26438 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
26439 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
26440 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
26442 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
26443 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
26444 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
26445 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
26446 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
26447 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
26448 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
26449 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
26451 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
26452 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
26453 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
26454 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
26455 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
26456 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
26457 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
26458 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
26460 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
26461 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
26462 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
26463 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
26464 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
26468 /* ISA floating-point and Advanced SIMD extensions. */
26469 struct arm_option_fpu_value_table
26472 const arm_feature_set value;
26475 /* This list should, at a minimum, contain all the fpu names
26476 recognized by GCC. */
26477 static const struct arm_option_fpu_value_table arm_fpus[] =
26479 {"softfpa", FPU_NONE},
26480 {"fpe", FPU_ARCH_FPE},
26481 {"fpe2", FPU_ARCH_FPE},
26482 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
26483 {"fpa", FPU_ARCH_FPA},
26484 {"fpa10", FPU_ARCH_FPA},
26485 {"fpa11", FPU_ARCH_FPA},
26486 {"arm7500fe", FPU_ARCH_FPA},
26487 {"softvfp", FPU_ARCH_VFP},
26488 {"softvfp+vfp", FPU_ARCH_VFP_V2},
26489 {"vfp", FPU_ARCH_VFP_V2},
26490 {"vfp9", FPU_ARCH_VFP_V2},
26491 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
26492 {"vfp10", FPU_ARCH_VFP_V2},
26493 {"vfp10-r0", FPU_ARCH_VFP_V1},
26494 {"vfpxd", FPU_ARCH_VFP_V1xD},
26495 {"vfpv2", FPU_ARCH_VFP_V2},
26496 {"vfpv3", FPU_ARCH_VFP_V3},
26497 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
26498 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
26499 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
26500 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
26501 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
26502 {"arm1020t", FPU_ARCH_VFP_V1},
26503 {"arm1020e", FPU_ARCH_VFP_V2},
26504 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
26505 {"arm1136jf-s", FPU_ARCH_VFP_V2},
26506 {"maverick", FPU_ARCH_MAVERICK},
26507 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
26508 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
26509 {"neon-fp16", FPU_ARCH_NEON_FP16},
26510 {"vfpv4", FPU_ARCH_VFP_V4},
26511 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
26512 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
26513 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
26514 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
26515 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
26516 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
26517 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
26518 {"crypto-neon-fp-armv8",
26519 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
26520 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
26521 {"crypto-neon-fp-armv8.1",
26522 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
26523 {NULL, ARM_ARCH_NONE}
26526 struct arm_option_value_table
26532 static const struct arm_option_value_table arm_float_abis[] =
26534 {"hard", ARM_FLOAT_ABI_HARD},
26535 {"softfp", ARM_FLOAT_ABI_SOFTFP},
26536 {"soft", ARM_FLOAT_ABI_SOFT},
26541 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26542 static const struct arm_option_value_table arm_eabis[] =
26544 {"gnu", EF_ARM_EABI_UNKNOWN},
26545 {"4", EF_ARM_EABI_VER4},
26546 {"5", EF_ARM_EABI_VER5},
26551 struct arm_long_option_table
26553 const char * option; /* Substring to match. */
26554 const char * help; /* Help information. */
26555 int (* func) (const char * subopt); /* Function to decode sub-option. */
26556 const char * deprecated; /* If non-null, print this message. */
26560 arm_parse_extension (const char *str, const arm_feature_set *opt_set,
26561 arm_feature_set *ext_set)
26563 /* We insist on extensions being specified in alphabetical order, and with
26564 extensions being added before being removed. We achieve this by having
26565 the global ARM_EXTENSIONS table in alphabetical order, and using the
26566 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26567 or removing it (0) and only allowing it to change in the order
26569 const struct arm_option_extension_value_table * opt = NULL;
26570 const arm_feature_set arm_any = ARM_ANY;
26571 int adding_value = -1;
26573 while (str != NULL && *str != 0)
26580 as_bad (_("invalid architectural extension"));
26585 ext = strchr (str, '+');
26590 len = strlen (str);
26592 if (len >= 2 && strncmp (str, "no", 2) == 0)
26594 if (adding_value != 0)
26597 opt = arm_extensions;
26605 if (adding_value == -1)
26608 opt = arm_extensions;
26610 else if (adding_value != 1)
26612 as_bad (_("must specify extensions to add before specifying "
26613 "those to remove"));
26620 as_bad (_("missing architectural extension"));
26624 gas_assert (adding_value != -1);
26625 gas_assert (opt != NULL);
26627 /* Scan over the options table trying to find an exact match. */
26628 for (; opt->name != NULL; opt++)
26629 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
26631 int i, nb_allowed_archs =
26632 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
26633 /* Check we can apply the extension to this architecture. */
26634 for (i = 0; i < nb_allowed_archs; i++)
26637 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
26639 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
26642 if (i == nb_allowed_archs)
26644 as_bad (_("extension does not apply to the base architecture"));
26648 /* Add or remove the extension. */
26650 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
26652 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
26654 /* Allowing Thumb division instructions for ARMv7 in autodetection
26655 rely on this break so that duplicate extensions (extensions
26656 with the same name as a previous extension in the list) are not
26657 considered for command-line parsing. */
26661 if (opt->name == NULL)
26663 /* Did we fail to find an extension because it wasn't specified in
26664 alphabetical order, or because it does not exist? */
26666 for (opt = arm_extensions; opt->name != NULL; opt++)
26667 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
26670 if (opt->name == NULL)
26671 as_bad (_("unknown architectural extension `%s'"), str);
26673 as_bad (_("architectural extensions must be specified in "
26674 "alphabetical order"));
26680 /* We should skip the extension we've just matched the next time
26692 arm_parse_cpu (const char *str)
26694 const struct arm_cpu_option_table *opt;
26695 const char *ext = strchr (str, '+');
26701 len = strlen (str);
26705 as_bad (_("missing cpu name `%s'"), str);
26709 for (opt = arm_cpus; opt->name != NULL; opt++)
26710 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
26712 mcpu_cpu_opt = &opt->value;
26713 if (mcpu_ext_opt == NULL)
26714 mcpu_ext_opt = XNEW (arm_feature_set);
26715 *mcpu_ext_opt = opt->ext;
26716 mcpu_fpu_opt = &opt->default_fpu;
26717 if (opt->canonical_name)
26719 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
26720 strcpy (selected_cpu_name, opt->canonical_name);
26726 if (len >= sizeof selected_cpu_name)
26727 len = (sizeof selected_cpu_name) - 1;
26729 for (i = 0; i < len; i++)
26730 selected_cpu_name[i] = TOUPPER (opt->name[i]);
26731 selected_cpu_name[i] = 0;
26735 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt);
26740 as_bad (_("unknown cpu `%s'"), str);
26745 arm_parse_arch (const char *str)
26747 const struct arm_arch_option_table *opt;
26748 const char *ext = strchr (str, '+');
26754 len = strlen (str);
26758 as_bad (_("missing architecture name `%s'"), str);
26762 for (opt = arm_archs; opt->name != NULL; opt++)
26763 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
26765 march_cpu_opt = &opt->value;
26766 if (march_ext_opt == NULL)
26767 march_ext_opt = XNEW (arm_feature_set);
26768 *march_ext_opt = arm_arch_none;
26769 march_fpu_opt = &opt->default_fpu;
26770 strcpy (selected_cpu_name, opt->name);
26773 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt);
26778 as_bad (_("unknown architecture `%s'\n"), str);
26783 arm_parse_fpu (const char * str)
26785 const struct arm_option_fpu_value_table * opt;
26787 for (opt = arm_fpus; opt->name != NULL; opt++)
26788 if (streq (opt->name, str))
26790 mfpu_opt = &opt->value;
26794 as_bad (_("unknown floating point format `%s'\n"), str);
26799 arm_parse_float_abi (const char * str)
26801 const struct arm_option_value_table * opt;
26803 for (opt = arm_float_abis; opt->name != NULL; opt++)
26804 if (streq (opt->name, str))
26806 mfloat_abi_opt = opt->value;
26810 as_bad (_("unknown floating point abi `%s'\n"), str);
26816 arm_parse_eabi (const char * str)
26818 const struct arm_option_value_table *opt;
26820 for (opt = arm_eabis; opt->name != NULL; opt++)
26821 if (streq (opt->name, str))
26823 meabi_flags = opt->value;
26826 as_bad (_("unknown EABI `%s'\n"), str);
26832 arm_parse_it_mode (const char * str)
26834 bfd_boolean ret = TRUE;
26836 if (streq ("arm", str))
26837 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
26838 else if (streq ("thumb", str))
26839 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
26840 else if (streq ("always", str))
26841 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
26842 else if (streq ("never", str))
26843 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
26846 as_bad (_("unknown implicit IT mode `%s', should be "\
26847 "arm, thumb, always, or never."), str);
26855 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
26857 codecomposer_syntax = TRUE;
26858 arm_comment_chars[0] = ';';
26859 arm_line_separator_chars[0] = 0;
26863 struct arm_long_option_table arm_long_opts[] =
26865 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26866 arm_parse_cpu, NULL},
26867 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26868 arm_parse_arch, NULL},
26869 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26870 arm_parse_fpu, NULL},
26871 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26872 arm_parse_float_abi, NULL},
26874 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26875 arm_parse_eabi, NULL},
26877 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26878 arm_parse_it_mode, NULL},
26879 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26880 arm_ccs_mode, NULL},
26881 {NULL, NULL, 0, NULL}
26885 md_parse_option (int c, const char * arg)
26887 struct arm_option_table *opt;
26888 const struct arm_legacy_option_table *fopt;
26889 struct arm_long_option_table *lopt;
26895 target_big_endian = 1;
26901 target_big_endian = 0;
26905 case OPTION_FIX_V4BX:
26913 #endif /* OBJ_ELF */
26916 /* Listing option. Just ignore these, we don't support additional
26921 for (opt = arm_opts; opt->option != NULL; opt++)
26923 if (c == opt->option[0]
26924 && ((arg == NULL && opt->option[1] == 0)
26925 || streq (arg, opt->option + 1)))
26927 /* If the option is deprecated, tell the user. */
26928 if (warn_on_deprecated && opt->deprecated != NULL)
26929 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
26930 arg ? arg : "", _(opt->deprecated));
26932 if (opt->var != NULL)
26933 *opt->var = opt->value;
26939 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
26941 if (c == fopt->option[0]
26942 && ((arg == NULL && fopt->option[1] == 0)
26943 || streq (arg, fopt->option + 1)))
26945 /* If the option is deprecated, tell the user. */
26946 if (warn_on_deprecated && fopt->deprecated != NULL)
26947 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
26948 arg ? arg : "", _(fopt->deprecated));
26950 if (fopt->var != NULL)
26951 *fopt->var = &fopt->value;
26957 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
26959 /* These options are expected to have an argument. */
26960 if (c == lopt->option[0]
26962 && strncmp (arg, lopt->option + 1,
26963 strlen (lopt->option + 1)) == 0)
26965 /* If the option is deprecated, tell the user. */
26966 if (warn_on_deprecated && lopt->deprecated != NULL)
26967 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
26968 _(lopt->deprecated));
26970 /* Call the sup-option parser. */
26971 return lopt->func (arg + strlen (lopt->option) - 1);
26982 md_show_usage (FILE * fp)
26984 struct arm_option_table *opt;
26985 struct arm_long_option_table *lopt;
26987 fprintf (fp, _(" ARM-specific assembler options:\n"));
26989 for (opt = arm_opts; opt->option != NULL; opt++)
26990 if (opt->help != NULL)
26991 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
26993 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
26994 if (lopt->help != NULL)
26995 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
26999 -EB assemble code for a big-endian cpu\n"));
27004 -EL assemble code for a little-endian cpu\n"));
27008 --fix-v4bx Allow BX in ARMv4 code\n"));
27012 --fdpic generate an FDPIC object file\n"));
27013 #endif /* OBJ_ELF */
27021 arm_feature_set flags;
27022 } cpu_arch_ver_table;
27024 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
27025 chronologically for architectures, with an exception for ARMv6-M and
27026 ARMv6S-M due to legacy reasons. No new architecture should have a
27027 special case. This allows for build attribute selection results to be
27028 stable when new architectures are added. */
27029 static const cpu_arch_ver_table cpu_arch_ver[] =
27031 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
27032 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
27033 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
27034 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
27035 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
27036 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
27037 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
27038 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
27039 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
27040 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
27041 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
27042 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
27043 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
27044 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
27045 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
27046 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
27047 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
27048 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
27049 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
27050 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
27051 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
27052 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
27053 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
27054 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
27056 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
27057 always selected build attributes to match those of ARMv6-M
27058 (resp. ARMv6S-M). However, due to these architectures being a strict
27059 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
27060 would be selected when fully respecting chronology of architectures.
27061 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
27062 move them before ARMv7 architectures. */
27063 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
27064 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
27066 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
27067 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
27068 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
27069 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
27070 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
27071 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
27072 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
27073 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
27074 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
27075 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
27076 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
27077 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
27078 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
27079 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
27080 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
27081 {-1, ARM_ARCH_NONE}
27084 /* Set an attribute if it has not already been set by the user. */
27087 aeabi_set_attribute_int (int tag, int value)
27090 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
27091 || !attributes_set_explicitly[tag])
27092 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
27096 aeabi_set_attribute_string (int tag, const char *value)
27099 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
27100 || !attributes_set_explicitly[tag])
27101 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
27104 /* Return whether features in the *NEEDED feature set are available via
27105 extensions for the architecture whose feature set is *ARCH_FSET. */
27108 have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
27109 const arm_feature_set *needed)
27111 int i, nb_allowed_archs;
27112 arm_feature_set ext_fset;
27113 const struct arm_option_extension_value_table *opt;
27115 ext_fset = arm_arch_none;
27116 for (opt = arm_extensions; opt->name != NULL; opt++)
27118 /* Extension does not provide any feature we need. */
27119 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
27123 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
27124 for (i = 0; i < nb_allowed_archs; i++)
27127 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
27130 /* Extension is available, add it. */
27131 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
27132 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
27136 /* Can we enable all features in *needed? */
27137 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
27140 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27141 a given architecture feature set *ARCH_EXT_FSET including extension feature
27142 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27143 - if true, check for an exact match of the architecture modulo extensions;
27144 - otherwise, select build attribute value of the first superset
27145 architecture released so that results remains stable when new architectures
27147 For -march/-mcpu=all the build attribute value of the most featureful
27148 architecture is returned. Tag_CPU_arch_profile result is returned in
27152 get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
27153 const arm_feature_set *ext_fset,
27154 char *profile, int exact_match)
27156 arm_feature_set arch_fset;
27157 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
27159 /* Select most featureful architecture with all its extensions if building
27160 for -march=all as the feature sets used to set build attributes. */
27161 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
27163 /* Force revisiting of decision for each new architecture. */
27164 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN);
27166 return TAG_CPU_ARCH_V8;
27169 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
27171 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
27173 arm_feature_set known_arch_fset;
27175 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
27178 /* Base architecture match user-specified architecture and
27179 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27180 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
27185 /* Base architecture match user-specified architecture only
27186 (eg. ARMv6-M in the same case as above). Record it in case we
27187 find a match with above condition. */
27188 else if (p_ver_ret == NULL
27189 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
27195 /* Architecture has all features wanted. */
27196 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
27198 arm_feature_set added_fset;
27200 /* Compute features added by this architecture over the one
27201 recorded in p_ver_ret. */
27202 if (p_ver_ret != NULL)
27203 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
27205 /* First architecture that match incl. with extensions, or the
27206 only difference in features over the recorded match is
27207 features that were optional and are now mandatory. */
27208 if (p_ver_ret == NULL
27209 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
27215 else if (p_ver_ret == NULL)
27217 arm_feature_set needed_ext_fset;
27219 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
27221 /* Architecture has all features needed when using some
27222 extensions. Record it and continue searching in case there
27223 exist an architecture providing all needed features without
27224 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27226 if (have_ext_for_needed_feat_p (&known_arch_fset,
27233 if (p_ver_ret == NULL)
27237 /* Tag_CPU_arch_profile. */
27238 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
27239 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
27240 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
27241 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
27243 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
27245 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
27249 return p_ver_ret->val;
27252 /* Set the public EABI object attributes. */
27255 aeabi_set_public_attributes (void)
27257 char profile = '\0';
27260 int fp16_optional = 0;
27261 int skip_exact_match = 0;
27262 arm_feature_set flags, flags_arch, flags_ext;
27264 /* Autodetection mode, choose the architecture based the instructions
27266 if (no_cpu_selected ())
27268 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
27270 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
27271 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
27273 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
27274 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
27276 /* Code run during relaxation relies on selected_cpu being set. */
27277 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
27278 flags_ext = arm_arch_none;
27279 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
27280 selected_ext = flags_ext;
27281 selected_cpu = flags;
27283 /* Otherwise, choose the architecture based on the capabilities of the
27287 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
27288 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
27289 flags_ext = selected_ext;
27290 flags = selected_cpu;
27292 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
27294 /* Allow the user to override the reported architecture. */
27295 if (!ARM_FEATURE_ZERO (selected_object_arch))
27297 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
27298 flags_ext = arm_arch_none;
27301 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
27303 /* When this function is run again after relaxation has happened there is no
27304 way to determine whether an architecture or CPU was specified by the user:
27305 - selected_cpu is set above for relaxation to work;
27306 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27307 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27308 Therefore, if not in -march=all case we first try an exact match and fall
27309 back to autodetection. */
27310 if (!skip_exact_match)
27311 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
27313 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
27315 as_bad (_("no architecture contains all the instructions used\n"));
27317 /* Tag_CPU_name. */
27318 if (selected_cpu_name[0])
27322 q = selected_cpu_name;
27323 if (strncmp (q, "armv", 4) == 0)
27328 for (i = 0; q[i]; i++)
27329 q[i] = TOUPPER (q[i]);
27331 aeabi_set_attribute_string (Tag_CPU_name, q);
27334 /* Tag_CPU_arch. */
27335 aeabi_set_attribute_int (Tag_CPU_arch, arch);
27337 /* Tag_CPU_arch_profile. */
27338 if (profile != '\0')
27339 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
27341 /* Tag_DSP_extension. */
27342 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
27343 aeabi_set_attribute_int (Tag_DSP_extension, 1);
27345 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
27346 /* Tag_ARM_ISA_use. */
27347 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
27348 || ARM_FEATURE_ZERO (flags_arch))
27349 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
27351 /* Tag_THUMB_ISA_use. */
27352 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
27353 || ARM_FEATURE_ZERO (flags_arch))
27357 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
27358 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
27360 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
27364 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
27367 /* Tag_VFP_arch. */
27368 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
27369 aeabi_set_attribute_int (Tag_VFP_arch,
27370 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
27372 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
27373 aeabi_set_attribute_int (Tag_VFP_arch,
27374 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
27376 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
27379 aeabi_set_attribute_int (Tag_VFP_arch, 3);
27381 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
27383 aeabi_set_attribute_int (Tag_VFP_arch, 4);
27386 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
27387 aeabi_set_attribute_int (Tag_VFP_arch, 2);
27388 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
27389 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
27390 aeabi_set_attribute_int (Tag_VFP_arch, 1);
27392 /* Tag_ABI_HardFP_use. */
27393 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
27394 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
27395 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
27397 /* Tag_WMMX_arch. */
27398 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
27399 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
27400 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
27401 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
27403 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27404 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
27405 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
27406 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
27407 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
27408 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
27410 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
27412 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
27416 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
27421 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27422 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
27423 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
27427 We set Tag_DIV_use to two when integer divide instructions have been used
27428 in ARM state, or when Thumb integer divide instructions have been used,
27429 but we have no architecture profile set, nor have we any ARM instructions.
27431 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27432 by the base architecture.
27434 For new architectures we will have to check these tests. */
27435 gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
27436 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
27437 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
27438 aeabi_set_attribute_int (Tag_DIV_use, 0);
27439 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
27440 || (profile == '\0'
27441 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
27442 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
27443 aeabi_set_attribute_int (Tag_DIV_use, 2);
27445 /* Tag_MP_extension_use. */
27446 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
27447 aeabi_set_attribute_int (Tag_MPextension_use, 1);
27449 /* Tag Virtualization_use. */
27450 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
27452 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
27455 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
27458 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27459 finished and free extension feature bits which will not be used anymore. */
27462 arm_md_post_relax (void)
27464 aeabi_set_public_attributes ();
27465 XDELETE (mcpu_ext_opt);
27466 mcpu_ext_opt = NULL;
27467 XDELETE (march_ext_opt);
27468 march_ext_opt = NULL;
27471 /* Add the default contents for the .ARM.attributes section. */
27476 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
27479 aeabi_set_public_attributes ();
27481 #endif /* OBJ_ELF */
27483 /* Parse a .cpu directive. */
27486 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
27488 const struct arm_cpu_option_table *opt;
27492 name = input_line_pointer;
27493 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
27494 input_line_pointer++;
27495 saved_char = *input_line_pointer;
27496 *input_line_pointer = 0;
27498 /* Skip the first "all" entry. */
27499 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
27500 if (streq (opt->name, name))
27502 selected_arch = opt->value;
27503 selected_ext = opt->ext;
27504 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
27505 if (opt->canonical_name)
27506 strcpy (selected_cpu_name, opt->canonical_name);
27510 for (i = 0; opt->name[i]; i++)
27511 selected_cpu_name[i] = TOUPPER (opt->name[i]);
27513 selected_cpu_name[i] = 0;
27515 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
27517 *input_line_pointer = saved_char;
27518 demand_empty_rest_of_line ();
27521 as_bad (_("unknown cpu `%s'"), name);
27522 *input_line_pointer = saved_char;
27523 ignore_rest_of_line ();
27526 /* Parse a .arch directive. */
27529 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
27531 const struct arm_arch_option_table *opt;
27535 name = input_line_pointer;
27536 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
27537 input_line_pointer++;
27538 saved_char = *input_line_pointer;
27539 *input_line_pointer = 0;
27541 /* Skip the first "all" entry. */
27542 for (opt = arm_archs + 1; opt->name != NULL; opt++)
27543 if (streq (opt->name, name))
27545 selected_arch = opt->value;
27546 selected_ext = arm_arch_none;
27547 selected_cpu = selected_arch;
27548 strcpy (selected_cpu_name, opt->name);
27549 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
27550 *input_line_pointer = saved_char;
27551 demand_empty_rest_of_line ();
27555 as_bad (_("unknown architecture `%s'\n"), name);
27556 *input_line_pointer = saved_char;
27557 ignore_rest_of_line ();
27560 /* Parse a .object_arch directive. */
27563 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
27565 const struct arm_arch_option_table *opt;
27569 name = input_line_pointer;
27570 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
27571 input_line_pointer++;
27572 saved_char = *input_line_pointer;
27573 *input_line_pointer = 0;
27575 /* Skip the first "all" entry. */
27576 for (opt = arm_archs + 1; opt->name != NULL; opt++)
27577 if (streq (opt->name, name))
27579 selected_object_arch = opt->value;
27580 *input_line_pointer = saved_char;
27581 demand_empty_rest_of_line ();
27585 as_bad (_("unknown architecture `%s'\n"), name);
27586 *input_line_pointer = saved_char;
27587 ignore_rest_of_line ();
27590 /* Parse a .arch_extension directive. */
27593 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
27595 const struct arm_option_extension_value_table *opt;
27598 int adding_value = 1;
27600 name = input_line_pointer;
27601 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
27602 input_line_pointer++;
27603 saved_char = *input_line_pointer;
27604 *input_line_pointer = 0;
27606 if (strlen (name) >= 2
27607 && strncmp (name, "no", 2) == 0)
27613 for (opt = arm_extensions; opt->name != NULL; opt++)
27614 if (streq (opt->name, name))
27616 int i, nb_allowed_archs =
27617 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
27618 for (i = 0; i < nb_allowed_archs; i++)
27621 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
27623 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
27627 if (i == nb_allowed_archs)
27629 as_bad (_("architectural extension `%s' is not allowed for the "
27630 "current base architecture"), name);
27635 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
27638 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
27640 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
27641 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
27642 *input_line_pointer = saved_char;
27643 demand_empty_rest_of_line ();
27644 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27645 on this return so that duplicate extensions (extensions with the
27646 same name as a previous extension in the list) are not considered
27647 for command-line parsing. */
27651 if (opt->name == NULL)
27652 as_bad (_("unknown architecture extension `%s'\n"), name);
27654 *input_line_pointer = saved_char;
27655 ignore_rest_of_line ();
27658 /* Parse a .fpu directive. */
27661 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
27663 const struct arm_option_fpu_value_table *opt;
27667 name = input_line_pointer;
27668 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
27669 input_line_pointer++;
27670 saved_char = *input_line_pointer;
27671 *input_line_pointer = 0;
27673 for (opt = arm_fpus; opt->name != NULL; opt++)
27674 if (streq (opt->name, name))
27676 selected_fpu = opt->value;
27677 #ifndef CPU_DEFAULT
27678 if (no_cpu_selected ())
27679 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
27682 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
27683 *input_line_pointer = saved_char;
27684 demand_empty_rest_of_line ();
27688 as_bad (_("unknown floating point format `%s'\n"), name);
27689 *input_line_pointer = saved_char;
27690 ignore_rest_of_line ();
27693 /* Copy symbol information. */
27696 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
27698 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
27702 /* Given a symbolic attribute NAME, return the proper integer value.
27703 Returns -1 if the attribute is not known. */
27706 arm_convert_symbolic_attribute (const char *name)
27708 static const struct
27713 attribute_table[] =
27715 /* When you modify this table you should
27716 also modify the list in doc/c-arm.texi. */
27717 #define T(tag) {#tag, tag}
27718 T (Tag_CPU_raw_name),
27721 T (Tag_CPU_arch_profile),
27722 T (Tag_ARM_ISA_use),
27723 T (Tag_THUMB_ISA_use),
27727 T (Tag_Advanced_SIMD_arch),
27728 T (Tag_PCS_config),
27729 T (Tag_ABI_PCS_R9_use),
27730 T (Tag_ABI_PCS_RW_data),
27731 T (Tag_ABI_PCS_RO_data),
27732 T (Tag_ABI_PCS_GOT_use),
27733 T (Tag_ABI_PCS_wchar_t),
27734 T (Tag_ABI_FP_rounding),
27735 T (Tag_ABI_FP_denormal),
27736 T (Tag_ABI_FP_exceptions),
27737 T (Tag_ABI_FP_user_exceptions),
27738 T (Tag_ABI_FP_number_model),
27739 T (Tag_ABI_align_needed),
27740 T (Tag_ABI_align8_needed),
27741 T (Tag_ABI_align_preserved),
27742 T (Tag_ABI_align8_preserved),
27743 T (Tag_ABI_enum_size),
27744 T (Tag_ABI_HardFP_use),
27745 T (Tag_ABI_VFP_args),
27746 T (Tag_ABI_WMMX_args),
27747 T (Tag_ABI_optimization_goals),
27748 T (Tag_ABI_FP_optimization_goals),
27749 T (Tag_compatibility),
27750 T (Tag_CPU_unaligned_access),
27751 T (Tag_FP_HP_extension),
27752 T (Tag_VFP_HP_extension),
27753 T (Tag_ABI_FP_16bit_format),
27754 T (Tag_MPextension_use),
27756 T (Tag_nodefaults),
27757 T (Tag_also_compatible_with),
27758 T (Tag_conformance),
27760 T (Tag_Virtualization_use),
27761 T (Tag_DSP_extension),
27762 /* We deliberately do not include Tag_MPextension_use_legacy. */
27770 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
27771 if (streq (name, attribute_table[i].name))
27772 return attribute_table[i].tag;
27777 /* Apply sym value for relocations only in the case that they are for
27778 local symbols in the same segment as the fixup and you have the
27779 respective architectural feature for blx and simple switches. */
27782 arm_apply_sym_value (struct fix * fixP, segT this_seg)
27785 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27786 /* PR 17444: If the local symbol is in a different section then a reloc
27787 will always be generated for it, so applying the symbol value now
27788 will result in a double offset being stored in the relocation. */
27789 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
27790 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
27792 switch (fixP->fx_r_type)
27794 case BFD_RELOC_ARM_PCREL_BLX:
27795 case BFD_RELOC_THUMB_PCREL_BRANCH23:
27796 if (ARM_IS_FUNC (fixP->fx_addsy))
27800 case BFD_RELOC_ARM_PCREL_CALL:
27801 case BFD_RELOC_THUMB_PCREL_BLX:
27802 if (THUMB_IS_FUNC (fixP->fx_addsy))
27813 #endif /* OBJ_ELF */