1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
102 #if defined __XSCALE__
103 #define CPU_DEFAULT ARM_ARCH_XSCALE
105 #if defined __thumb__
106 #define CPU_DEFAULT ARM_ARCH_V5T
113 # define FPU_DEFAULT FPU_ARCH_FPA
114 # elif defined (TE_NetBSD)
116 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
118 /* Legacy a.out format. */
119 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
121 # elif defined (TE_VXWORKS)
122 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
124 /* For backwards compatibility, default to FPA. */
125 # define FPU_DEFAULT FPU_ARCH_FPA
127 #endif /* ifndef FPU_DEFAULT */
129 #define streq(a, b) (strcmp (a, b) == 0)
131 static arm_feature_set cpu_variant;
132 static arm_feature_set arm_arch_used;
133 static arm_feature_set thumb_arch_used;
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26 = FALSE;
137 static int atpcs = FALSE;
138 static int support_interwork = FALSE;
139 static int uses_apcs_float = FALSE;
140 static int pic_code = FALSE;
142 /* Variables that we set while parsing command-line options. Once all
143 options have been read we re-process these values to set the real
145 static const arm_feature_set *legacy_cpu = NULL;
146 static const arm_feature_set *legacy_fpu = NULL;
148 static const arm_feature_set *mcpu_cpu_opt = NULL;
149 static const arm_feature_set *mcpu_fpu_opt = NULL;
150 static const arm_feature_set *march_cpu_opt = NULL;
151 static const arm_feature_set *march_fpu_opt = NULL;
152 static const arm_feature_set *mfpu_opt = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
159 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
160 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
161 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
164 static const arm_feature_set cpu_default = CPU_DEFAULT;
167 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
168 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
169 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
170 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
171 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
172 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
173 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
174 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
175 static const arm_feature_set arm_ext_v4t_5 =
176 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
178 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
179 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
180 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
181 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
182 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
183 static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
184 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_arch_any = ARM_ANY;
187 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
188 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
189 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
191 static const arm_feature_set arm_cext_iwmmxt =
192 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
193 static const arm_feature_set arm_cext_xscale =
194 ARM_FEATURE (0, ARM_CEXT_XSCALE);
195 static const arm_feature_set arm_cext_maverick =
196 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
197 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
198 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
199 static const arm_feature_set fpu_vfp_ext_v1xd =
200 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
201 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
202 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
204 static int mfloat_abi_opt = -1;
205 /* Record user cpu selection for object attributes. */
206 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
207 /* Must be long enough to hold any of the names in arm_cpus. */
208 static char selected_cpu_name[16];
211 static int meabi_flags = EABI_DEFAULT;
213 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
218 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
219 symbolS * GOT_symbol;
222 /* 0: assemble for ARM,
223 1: assemble for Thumb,
224 2: assemble for Thumb even though target CPU does not support thumb
226 static int thumb_mode = 0;
228 /* If unified_syntax is true, we are processing the new unified
229 ARM/Thumb syntax. Important differences from the old ARM mode:
231 - Immediate operands do not require a # prefix.
232 - Conditional affixes always appear at the end of the
233 instruction. (For backward compatibility, those instructions
234 that formerly had them in the middle, continue to accept them
236 - The IT instruction may appear, and if it does is validated
237 against subsequent conditional affixes. It does not generate
240 Important differences from the old Thumb mode:
242 - Immediate operands do not require a # prefix.
243 - Most of the V6T2 instructions are only available in unified mode.
244 - The .N and .W suffixes are recognized and honored (it is an error
245 if they cannot be honored).
246 - All instructions set the flags if and only if they have an 's' affix.
247 - Conditional affixes may be used. They are validated against
248 preceding IT instructions. Unlike ARM mode, you cannot use a
249 conditional affix except in the scope of an IT instruction. */
251 static bfd_boolean unified_syntax = FALSE;
256 unsigned long instruction;
260 /* Set to the opcode if the instruction needs relaxation.
261 Zero if the instruction is not relaxed. */
265 bfd_reloc_code_real_type type;
274 unsigned present : 1; /* Operand present. */
275 unsigned isreg : 1; /* Operand was a register. */
276 unsigned immisreg : 1; /* .imm field is a second register. */
277 unsigned hasreloc : 1; /* Operand has relocation suffix. */
278 unsigned writeback : 1; /* Operand has trailing ! */
279 unsigned preind : 1; /* Preindexed address. */
280 unsigned postind : 1; /* Postindexed address. */
281 unsigned negative : 1; /* Index register was negated. */
282 unsigned shifted : 1; /* Shift applied to operation. */
283 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
287 static struct arm_it inst;
289 #define NUM_FLOAT_VALS 8
291 const char * fp_const[] =
293 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
296 /* Number of littlenums required to hold an extended precision number. */
297 #define MAX_LITTLENUMS 6
299 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
309 #define CP_T_X 0x00008000
310 #define CP_T_Y 0x00400000
312 #define CONDS_BIT 0x00100000
313 #define LOAD_BIT 0x00100000
315 #define DOUBLE_LOAD_FLAG 0x00000001
319 const char * template;
323 #define COND_ALWAYS 0xE
327 const char *template;
331 /* The bit that distinguishes CPSR and SPSR. */
332 #define SPSR_BIT (1 << 22)
334 /* The individual PSR flag bits. */
335 #define PSR_c (1 << 16)
336 #define PSR_x (1 << 17)
337 #define PSR_s (1 << 18)
338 #define PSR_f (1 << 19)
343 bfd_reloc_code_real_type reloc;
348 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
353 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
356 /* ARM register categories. This includes coprocessor numbers and various
357 architecture extensions' registers. */
379 /* Structure for a hash table entry for a register. */
383 unsigned char number;
385 unsigned char builtin;
388 /* Diagnostics used when we don't get a register of the expected type. */
389 const char *const reg_expected_msgs[] =
391 N_("ARM register expected"),
392 N_("bad or missing co-processor number"),
393 N_("co-processor register expected"),
394 N_("FPA register expected"),
395 N_("VFP single precision register expected"),
396 N_("VFP double precision register expected"),
397 N_("VFP system register expected"),
398 N_("Maverick MVF register expected"),
399 N_("Maverick MVD register expected"),
400 N_("Maverick MVFX register expected"),
401 N_("Maverick MVDX register expected"),
402 N_("Maverick MVAX register expected"),
403 N_("Maverick DSPSC register expected"),
404 N_("iWMMXt data register expected"),
405 N_("iWMMXt control register expected"),
406 N_("iWMMXt scalar register expected"),
407 N_("XScale accumulator register expected"),
410 /* Some well known registers that we refer to directly elsewhere. */
415 /* ARM instructions take 4bytes in the object file, Thumb instructions
421 /* Basic string to match. */
422 const char *template;
424 /* Parameters to instruction. */
425 unsigned char operands[8];
427 /* Conditional tag - see opcode_lookup. */
428 unsigned int tag : 4;
430 /* Basic instruction code. */
431 unsigned int avalue : 28;
433 /* Thumb-format instruction code. */
436 /* Which architecture variant provides this instruction. */
437 const arm_feature_set *avariant;
438 const arm_feature_set *tvariant;
440 /* Function to call to encode instruction in ARM format. */
441 void (* aencode) (void);
443 /* Function to call to encode instruction in Thumb format. */
444 void (* tencode) (void);
447 /* Defines for various bits that we will want to toggle. */
448 #define INST_IMMEDIATE 0x02000000
449 #define OFFSET_REG 0x02000000
450 #define HWOFFSET_IMM 0x00400000
451 #define SHIFT_BY_REG 0x00000010
452 #define PRE_INDEX 0x01000000
453 #define INDEX_UP 0x00800000
454 #define WRITE_BACK 0x00200000
455 #define LDM_TYPE_2_OR_3 0x00400000
457 #define LITERAL_MASK 0xf000f000
458 #define OPCODE_MASK 0xfe1fffff
459 #define V4_STR_BIT 0x00000020
461 #define DATA_OP_SHIFT 21
463 #define T2_OPCODE_MASK 0xfe1fffff
464 #define T2_DATA_OP_SHIFT 21
466 /* Codes to distinguish the arithmetic instructions. */
477 #define OPCODE_CMP 10
478 #define OPCODE_CMN 11
479 #define OPCODE_ORR 12
480 #define OPCODE_MOV 13
481 #define OPCODE_BIC 14
482 #define OPCODE_MVN 15
484 #define T2_OPCODE_AND 0
485 #define T2_OPCODE_BIC 1
486 #define T2_OPCODE_ORR 2
487 #define T2_OPCODE_ORN 3
488 #define T2_OPCODE_EOR 4
489 #define T2_OPCODE_ADD 8
490 #define T2_OPCODE_ADC 10
491 #define T2_OPCODE_SBC 11
492 #define T2_OPCODE_SUB 13
493 #define T2_OPCODE_RSB 14
495 #define T_OPCODE_MUL 0x4340
496 #define T_OPCODE_TST 0x4200
497 #define T_OPCODE_CMN 0x42c0
498 #define T_OPCODE_NEG 0x4240
499 #define T_OPCODE_MVN 0x43c0
501 #define T_OPCODE_ADD_R3 0x1800
502 #define T_OPCODE_SUB_R3 0x1a00
503 #define T_OPCODE_ADD_HI 0x4400
504 #define T_OPCODE_ADD_ST 0xb000
505 #define T_OPCODE_SUB_ST 0xb080
506 #define T_OPCODE_ADD_SP 0xa800
507 #define T_OPCODE_ADD_PC 0xa000
508 #define T_OPCODE_ADD_I8 0x3000
509 #define T_OPCODE_SUB_I8 0x3800
510 #define T_OPCODE_ADD_I3 0x1c00
511 #define T_OPCODE_SUB_I3 0x1e00
513 #define T_OPCODE_ASR_R 0x4100
514 #define T_OPCODE_LSL_R 0x4080
515 #define T_OPCODE_LSR_R 0x40c0
516 #define T_OPCODE_ROR_R 0x41c0
517 #define T_OPCODE_ASR_I 0x1000
518 #define T_OPCODE_LSL_I 0x0000
519 #define T_OPCODE_LSR_I 0x0800
521 #define T_OPCODE_MOV_I8 0x2000
522 #define T_OPCODE_CMP_I8 0x2800
523 #define T_OPCODE_CMP_LR 0x4280
524 #define T_OPCODE_MOV_HR 0x4600
525 #define T_OPCODE_CMP_HR 0x4500
527 #define T_OPCODE_LDR_PC 0x4800
528 #define T_OPCODE_LDR_SP 0x9800
529 #define T_OPCODE_STR_SP 0x9000
530 #define T_OPCODE_LDR_IW 0x6800
531 #define T_OPCODE_STR_IW 0x6000
532 #define T_OPCODE_LDR_IH 0x8800
533 #define T_OPCODE_STR_IH 0x8000
534 #define T_OPCODE_LDR_IB 0x7800
535 #define T_OPCODE_STR_IB 0x7000
536 #define T_OPCODE_LDR_RW 0x5800
537 #define T_OPCODE_STR_RW 0x5000
538 #define T_OPCODE_LDR_RH 0x5a00
539 #define T_OPCODE_STR_RH 0x5200
540 #define T_OPCODE_LDR_RB 0x5c00
541 #define T_OPCODE_STR_RB 0x5400
543 #define T_OPCODE_PUSH 0xb400
544 #define T_OPCODE_POP 0xbc00
546 #define T_OPCODE_BRANCH 0xe000
548 #define THUMB_SIZE 2 /* Size of thumb instruction. */
549 #define THUMB_PP_PC_LR 0x0100
550 #define THUMB_LOAD_BIT 0x0800
552 #define BAD_ARGS _("bad arguments to instruction")
553 #define BAD_PC _("r15 not allowed here")
554 #define BAD_COND _("instruction cannot be conditional")
555 #define BAD_OVERLAP _("registers may not be the same")
556 #define BAD_HIREG _("lo register required")
557 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
558 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
560 static struct hash_control *arm_ops_hsh;
561 static struct hash_control *arm_cond_hsh;
562 static struct hash_control *arm_shift_hsh;
563 static struct hash_control *arm_psr_hsh;
564 static struct hash_control *arm_reg_hsh;
565 static struct hash_control *arm_reloc_hsh;
567 /* Stuff needed to resolve the label ambiguity
577 symbolS * last_label_seen;
578 static int label_is_thumb_function_name = FALSE;
580 /* Literal pool structure. Held on a per-section
581 and per-sub-section basis. */
583 #define MAX_LITERAL_POOL_SIZE 1024
584 typedef struct literal_pool
586 expressionS literals [MAX_LITERAL_POOL_SIZE];
587 unsigned int next_free_entry;
592 struct literal_pool * next;
595 /* Pointer to a linked list of literal pools. */
596 literal_pool * list_of_pools = NULL;
598 /* State variables for IT block handling. */
599 static bfd_boolean current_it_mask = 0;
600 static int current_cc;
605 /* This array holds the chars that always start a comment. If the
606 pre-processor is disabled, these aren't very useful. */
607 const char comment_chars[] = "@";
609 /* This array holds the chars that only start a comment at the beginning of
610 a line. If the line seems to have the form '# 123 filename'
611 .line and .file directives will appear in the pre-processed output. */
612 /* Note that input_file.c hand checks for '#' at the beginning of the
613 first line of the input file. This is because the compiler outputs
614 #NO_APP at the beginning of its output. */
615 /* Also note that comments like this one will always work. */
616 const char line_comment_chars[] = "#";
618 const char line_separator_chars[] = ";";
620 /* Chars that can be used to separate mant
621 from exp in floating point numbers. */
622 const char EXP_CHARS[] = "eE";
624 /* Chars that mean this number is a floating point constant. */
628 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
630 /* Prefix characters that indicate the start of an immediate
632 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
634 /* Separator character handling. */
636 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
639 skip_past_char (char ** str, char c)
649 #define skip_past_comma(str) skip_past_char (str, ',')
651 /* Arithmetic expressions (possibly involving symbols). */
653 /* Return TRUE if anything in the expression is a bignum. */
656 walk_no_bignums (symbolS * sp)
658 if (symbol_get_value_expression (sp)->X_op == O_big)
661 if (symbol_get_value_expression (sp)->X_add_symbol)
663 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
664 || (symbol_get_value_expression (sp)->X_op_symbol
665 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
671 static int in_my_get_expression = 0;
673 /* Third argument to my_get_expression. */
674 #define GE_NO_PREFIX 0
675 #define GE_IMM_PREFIX 1
676 #define GE_OPT_PREFIX 2
679 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
684 /* In unified syntax, all prefixes are optional. */
686 prefix_mode = GE_OPT_PREFIX;
690 case GE_NO_PREFIX: break;
692 if (!is_immediate_prefix (**str))
694 inst.error = _("immediate expression requires a # prefix");
700 if (is_immediate_prefix (**str))
706 memset (ep, 0, sizeof (expressionS));
708 save_in = input_line_pointer;
709 input_line_pointer = *str;
710 in_my_get_expression = 1;
711 seg = expression (ep);
712 in_my_get_expression = 0;
714 if (ep->X_op == O_illegal)
716 /* We found a bad expression in md_operand(). */
717 *str = input_line_pointer;
718 input_line_pointer = save_in;
719 if (inst.error == NULL)
720 inst.error = _("bad expression");
725 if (seg != absolute_section
726 && seg != text_section
727 && seg != data_section
728 && seg != bss_section
729 && seg != undefined_section)
731 inst.error = _("bad segment");
732 *str = input_line_pointer;
733 input_line_pointer = save_in;
738 /* Get rid of any bignums now, so that we don't generate an error for which
739 we can't establish a line number later on. Big numbers are never valid
740 in instructions, which is where this routine is always called. */
741 if (ep->X_op == O_big
743 && (walk_no_bignums (ep->X_add_symbol)
745 && walk_no_bignums (ep->X_op_symbol)))))
747 inst.error = _("invalid constant");
748 *str = input_line_pointer;
749 input_line_pointer = save_in;
753 *str = input_line_pointer;
754 input_line_pointer = save_in;
758 /* Turn a string in input_line_pointer into a floating point constant
759 of type TYPE, and store the appropriate bytes in *LITP. The number
760 of LITTLENUMS emitted is stored in *SIZEP. An error message is
761 returned, or NULL on OK.
763 Note that fp constants aren't represent in the normal way on the ARM.
764 In big endian mode, things are as expected. However, in little endian
765 mode fp constants are big-endian word-wise, and little-endian byte-wise
766 within the words. For example, (double) 1.1 in big endian mode is
767 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
768 the byte sequence 99 99 f1 3f 9a 99 99 99.
770 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
773 md_atof (int type, char * litP, int * sizeP)
776 LITTLENUM_TYPE words[MAX_LITTLENUMS];
808 return _("bad call to MD_ATOF()");
811 t = atof_ieee (input_line_pointer, type, words);
813 input_line_pointer = t;
816 if (target_big_endian)
818 for (i = 0; i < prec; i++)
820 md_number_to_chars (litP, (valueT) words[i], 2);
826 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
827 for (i = prec - 1; i >= 0; i--)
829 md_number_to_chars (litP, (valueT) words[i], 2);
833 /* For a 4 byte float the order of elements in `words' is 1 0.
834 For an 8 byte float the order is 1 0 3 2. */
835 for (i = 0; i < prec; i += 2)
837 md_number_to_chars (litP, (valueT) words[i + 1], 2);
838 md_number_to_chars (litP + 2, (valueT) words[i], 2);
846 /* We handle all bad expressions here, so that we can report the faulty
847 instruction in the error message. */
849 md_operand (expressionS * expr)
851 if (in_my_get_expression)
852 expr->X_op = O_illegal;
855 /* Immediate values. */
857 /* Generic immediate-value read function for use in directives.
858 Accepts anything that 'expression' can fold to a constant.
859 *val receives the number. */
862 immediate_for_directive (int *val)
865 exp.X_op = O_illegal;
867 if (is_immediate_prefix (*input_line_pointer))
869 input_line_pointer++;
873 if (exp.X_op != O_constant)
875 as_bad (_("expected #constant"));
876 ignore_rest_of_line ();
879 *val = exp.X_add_number;
884 /* Register parsing. */
886 /* Generic register parser. CCP points to what should be the
887 beginning of a register name. If it is indeed a valid register
888 name, advance CCP over it and return the reg_entry structure;
889 otherwise return NULL. Does not issue diagnostics. */
891 static struct reg_entry *
892 arm_reg_parse_multi (char **ccp)
896 struct reg_entry *reg;
898 #ifdef REGISTER_PREFIX
899 if (*start != REGISTER_PREFIX)
903 #ifdef OPTIONAL_REGISTER_PREFIX
904 if (*start == OPTIONAL_REGISTER_PREFIX)
909 if (!ISALPHA (*p) || !is_name_beginner (*p))
914 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
916 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
925 /* As above, but the register must be of type TYPE, and the return
926 value is the register number or FAIL. */
929 arm_reg_parse (char **ccp, enum arm_reg_type type)
932 struct reg_entry *reg = arm_reg_parse_multi (ccp);
934 if (reg && reg->type == type)
937 /* Alternative syntaxes are accepted for a few register classes. */
944 /* Generic coprocessor register names are allowed for these. */
945 if (reg && reg->type == REG_TYPE_CN)
950 /* For backward compatibility, a bare number is valid here. */
952 unsigned long processor = strtoul (start, ccp, 10);
953 if (*ccp != start && processor <= 15)
958 /* WC includes WCG. ??? I'm not sure this is true for all
959 instructions that take WC registers. */
960 if (reg && reg->type == REG_TYPE_MMXWCG)
972 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
974 parse_reg_list (char ** strp)
980 /* We come back here if we get ranges concatenated by '+' or '|'. */
995 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
997 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
1007 inst.error = _("bad range in register list");
1011 for (i = cur_reg + 1; i < reg; i++)
1013 if (range & (1 << i))
1015 (_("Warning: duplicated register (r%d) in register list"),
1023 if (range & (1 << reg))
1024 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1026 else if (reg <= cur_reg)
1027 as_tsktsk (_("Warning: register range not in ascending order"));
1032 while (skip_past_comma (&str) != FAIL
1033 || (in_range = 1, *str++ == '-'));
1038 inst.error = _("missing `}'");
1046 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
1049 if (expr.X_op == O_constant)
1051 if (expr.X_add_number
1052 != (expr.X_add_number & 0x0000ffff))
1054 inst.error = _("invalid register mask");
1058 if ((range & expr.X_add_number) != 0)
1060 int regno = range & expr.X_add_number;
1063 regno = (1 << regno) - 1;
1065 (_("Warning: duplicated register (r%d) in register list"),
1069 range |= expr.X_add_number;
1073 if (inst.reloc.type != 0)
1075 inst.error = _("expression too complex");
1079 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1080 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1081 inst.reloc.pc_rel = 0;
1085 if (*str == '|' || *str == '+')
1091 while (another_range);
1097 /* Parse a VFP register list. If the string is invalid return FAIL.
1098 Otherwise return the number of registers, and set PBASE to the first
1099 register. Double precision registers are matched if DP is nonzero. */
1102 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1110 unsigned long mask = 0;
1120 regtype = REG_TYPE_VFD;
1125 regtype = REG_TYPE_VFS;
1129 base_reg = max_regs;
1133 new_base = arm_reg_parse (str, regtype);
1134 if (new_base == FAIL)
1136 inst.error = gettext (reg_expected_msgs[regtype]);
1140 if (new_base < base_reg)
1141 base_reg = new_base;
1143 if (mask & (1 << new_base))
1145 inst.error = _("invalid register list");
1149 if ((mask >> new_base) != 0 && ! warned)
1151 as_tsktsk (_("register list not in ascending order"));
1155 mask |= 1 << new_base;
1158 if (**str == '-') /* We have the start of a range expression */
1164 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1166 inst.error = gettext (reg_expected_msgs[regtype]);
1170 if (high_range <= new_base)
1172 inst.error = _("register range not in ascending order");
1176 for (new_base++; new_base <= high_range; new_base++)
1178 if (mask & (1 << new_base))
1180 inst.error = _("invalid register list");
1184 mask |= 1 << new_base;
1189 while (skip_past_comma (str) != FAIL);
1193 /* Sanity check -- should have raised a parse error above. */
1194 if (count == 0 || count > max_regs)
1199 /* Final test -- the registers must be consecutive. */
1201 for (i = 0; i < count; i++)
1203 if ((mask & (1u << i)) == 0)
1205 inst.error = _("non-contiguous register range");
1213 /* Parse an explicit relocation suffix on an expression. This is
1214 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1215 arm_reloc_hsh contains no entries, so this function can only
1216 succeed if there is no () after the word. Returns -1 on error,
1217 BFD_RELOC_UNUSED if there wasn't any suffix. */
1219 parse_reloc (char **str)
1221 struct reloc_entry *r;
1225 return BFD_RELOC_UNUSED;
1230 while (*q && *q != ')' && *q != ',')
1235 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1242 /* Directives: register aliases. */
1245 insert_reg_alias (char *str, int number, int type)
1247 struct reg_entry *new;
1250 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1253 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1255 /* Only warn about a redefinition if it's not defined as the
1257 else if (new->number != number || new->type != type)
1258 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1263 name = xstrdup (str);
1264 new = xmalloc (sizeof (struct reg_entry));
1267 new->number = number;
1269 new->builtin = FALSE;
1271 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1275 /* Look for the .req directive. This is of the form:
1277 new_register_name .req existing_register_name
1279 If we find one, or if it looks sufficiently like one that we want to
1280 handle any error here, return non-zero. Otherwise return zero. */
1283 create_register_alias (char * newname, char *p)
1285 struct reg_entry *old;
1286 char *oldname, *nbuf;
1289 /* The input scrubber ensures that whitespace after the mnemonic is
1290 collapsed to single spaces. */
1292 if (strncmp (oldname, " .req ", 6) != 0)
1296 if (*oldname == '\0')
1299 old = hash_find (arm_reg_hsh, oldname);
1302 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1307 the desired alias name, and p points to its end. If not, then
1308 the desired alias name is in the global original_case_string. */
1309 #ifdef TC_CASE_SENSITIVE
1312 newname = original_case_string;
1313 nlen = strlen (newname);
1316 nbuf = alloca (nlen + 1);
1317 memcpy (nbuf, newname, nlen);
1320 /* Create aliases under the new name as stated; an all-lowercase
1321 version of the new name; and an all-uppercase version of the new
1323 insert_reg_alias (nbuf, old->number, old->type);
1325 for (p = nbuf; *p; p++)
1328 if (strncmp (nbuf, newname, nlen))
1329 insert_reg_alias (nbuf, old->number, old->type);
1331 for (p = nbuf; *p; p++)
1334 if (strncmp (nbuf, newname, nlen))
1335 insert_reg_alias (nbuf, old->number, old->type);
1340 /* Should never be called, as .req goes between the alias and the
1341 register name, not at the beginning of the line. */
1343 s_req (int a ATTRIBUTE_UNUSED)
1345 as_bad (_("invalid syntax for .req directive"));
1348 /* The .unreq directive deletes an alias which was previously defined
1349 by .req. For example:
1355 s_unreq (int a ATTRIBUTE_UNUSED)
1360 name = input_line_pointer;
1362 while (*input_line_pointer != 0
1363 && *input_line_pointer != ' '
1364 && *input_line_pointer != '\n')
1365 ++input_line_pointer;
1367 saved_char = *input_line_pointer;
1368 *input_line_pointer = 0;
1371 as_bad (_("invalid syntax for .unreq directive"));
1374 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1377 as_bad (_("unknown register alias '%s'"), name);
1378 else if (reg->builtin)
1379 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1383 hash_delete (arm_reg_hsh, name);
1384 free ((char *) reg->name);
1389 *input_line_pointer = saved_char;
1390 demand_empty_rest_of_line ();
1393 /* Directives: Instruction set selection. */
1396 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1397 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1398 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1399 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1401 static enum mstate mapstate = MAP_UNDEFINED;
1404 mapping_state (enum mstate state)
1407 const char * symname;
1410 if (mapstate == state)
1411 /* The mapping symbol has already been emitted.
1412 There is nothing else to do. */
1421 type = BSF_NO_FLAGS;
1425 type = BSF_NO_FLAGS;
1429 type = BSF_NO_FLAGS;
1437 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1439 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1440 symbol_table_insert (symbolP);
1441 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1446 THUMB_SET_FUNC (symbolP, 0);
1447 ARM_SET_THUMB (symbolP, 0);
1448 ARM_SET_INTERWORK (symbolP, support_interwork);
1452 THUMB_SET_FUNC (symbolP, 1);
1453 ARM_SET_THUMB (symbolP, 1);
1454 ARM_SET_INTERWORK (symbolP, support_interwork);
1463 #define mapping_state(x) /* nothing */
1466 /* Find the real, Thumb encoded start of a Thumb function. */
1469 find_real_start (symbolS * symbolP)
1472 const char * name = S_GET_NAME (symbolP);
1473 symbolS * new_target;
1475 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1476 #define STUB_NAME ".real_start_of"
1481 /* The compiler may generate BL instructions to local labels because
1482 it needs to perform a branch to a far away location. These labels
1483 do not have a corresponding ".real_start_of" label. We check
1484 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1485 the ".real_start_of" convention for nonlocal branches. */
1486 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1489 real_start = ACONCAT ((STUB_NAME, name, NULL));
1490 new_target = symbol_find (real_start);
1492 if (new_target == NULL)
1494 as_warn ("Failed to find real start of function: %s\n", name);
1495 new_target = symbolP;
1502 opcode_select (int width)
1509 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
1510 as_bad (_("selected processor does not support THUMB opcodes"));
1513 /* No need to force the alignment, since we will have been
1514 coming from ARM mode, which is word-aligned. */
1515 record_alignment (now_seg, 1);
1517 mapping_state (MAP_THUMB);
1523 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
1524 as_bad (_("selected processor does not support ARM opcodes"));
1529 frag_align (2, 0, 0);
1531 record_alignment (now_seg, 1);
1533 mapping_state (MAP_ARM);
1537 as_bad (_("invalid instruction size selected (%d)"), width);
1542 s_arm (int ignore ATTRIBUTE_UNUSED)
1545 demand_empty_rest_of_line ();
1549 s_thumb (int ignore ATTRIBUTE_UNUSED)
1552 demand_empty_rest_of_line ();
1556 s_code (int unused ATTRIBUTE_UNUSED)
1560 temp = get_absolute_expression ();
1565 opcode_select (temp);
1569 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1574 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1576 /* If we are not already in thumb mode go into it, EVEN if
1577 the target processor does not support thumb instructions.
1578 This is used by gcc/config/arm/lib1funcs.asm for example
1579 to compile interworking support functions even if the
1580 target processor should not support interworking. */
1584 record_alignment (now_seg, 1);
1587 demand_empty_rest_of_line ();
1591 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1595 /* The following label is the name/address of the start of a Thumb function.
1596 We need to know this for the interworking support. */
1597 label_is_thumb_function_name = TRUE;
1600 /* Perform a .set directive, but also mark the alias as
1601 being a thumb function. */
1604 s_thumb_set (int equiv)
1606 /* XXX the following is a duplicate of the code for s_set() in read.c
1607 We cannot just call that code as we need to get at the symbol that
1614 /* Especial apologies for the random logic:
1615 This just grew, and could be parsed much more simply!
1617 name = input_line_pointer;
1618 delim = get_symbol_end ();
1619 end_name = input_line_pointer;
1622 if (*input_line_pointer != ',')
1625 as_bad (_("expected comma after name \"%s\""), name);
1627 ignore_rest_of_line ();
1631 input_line_pointer++;
1634 if (name[0] == '.' && name[1] == '\0')
1636 /* XXX - this should not happen to .thumb_set. */
1640 if ((symbolP = symbol_find (name)) == NULL
1641 && (symbolP = md_undefined_symbol (name)) == NULL)
1644 /* When doing symbol listings, play games with dummy fragments living
1645 outside the normal fragment chain to record the file and line info
1647 if (listing & LISTING_SYMBOLS)
1649 extern struct list_info_struct * listing_tail;
1650 fragS * dummy_frag = xmalloc (sizeof (fragS));
1652 memset (dummy_frag, 0, sizeof (fragS));
1653 dummy_frag->fr_type = rs_fill;
1654 dummy_frag->line = listing_tail;
1655 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1656 dummy_frag->fr_symbol = symbolP;
1660 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1663 /* "set" symbols are local unless otherwise specified. */
1664 SF_SET_LOCAL (symbolP);
1665 #endif /* OBJ_COFF */
1666 } /* Make a new symbol. */
1668 symbol_table_insert (symbolP);
1673 && S_IS_DEFINED (symbolP)
1674 && S_GET_SEGMENT (symbolP) != reg_section)
1675 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1677 pseudo_set (symbolP);
1679 demand_empty_rest_of_line ();
1681 /* XXX Now we come to the Thumb specific bit of code. */
1683 THUMB_SET_FUNC (symbolP, 1);
1684 ARM_SET_THUMB (symbolP, 1);
1685 #if defined OBJ_ELF || defined OBJ_COFF
1686 ARM_SET_INTERWORK (symbolP, support_interwork);
1690 /* Directives: Mode selection. */
1692 /* .syntax [unified|divided] - choose the new unified syntax
1693 (same for Arm and Thumb encoding, modulo slight differences in what
1694 can be represented) or the old divergent syntax for each mode. */
1696 s_syntax (int unused ATTRIBUTE_UNUSED)
1700 name = input_line_pointer;
1701 delim = get_symbol_end ();
1703 if (!strcasecmp (name, "unified"))
1704 unified_syntax = TRUE;
1705 else if (!strcasecmp (name, "divided"))
1706 unified_syntax = FALSE;
1709 as_bad (_("unrecognized syntax mode \"%s\""), name);
1712 *input_line_pointer = delim;
1713 demand_empty_rest_of_line ();
1716 /* Directives: sectioning and alignment. */
1718 /* Same as s_align_ptwo but align 0 => align 2. */
1721 s_align (int unused ATTRIBUTE_UNUSED)
1725 long max_alignment = 15;
1727 temp = get_absolute_expression ();
1728 if (temp > max_alignment)
1729 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1732 as_bad (_("alignment negative. 0 assumed."));
1736 if (*input_line_pointer == ',')
1738 input_line_pointer++;
1739 temp_fill = get_absolute_expression ();
1747 /* Only make a frag if we HAVE to. */
1748 if (temp && !need_pass_2)
1749 frag_align (temp, (int) temp_fill, 0);
1750 demand_empty_rest_of_line ();
1752 record_alignment (now_seg, temp);
1756 s_bss (int ignore ATTRIBUTE_UNUSED)
1758 /* We don't support putting frags in the BSS segment, we fake it by
1759 marking in_bss, then looking at s_skip for clues. */
1760 subseg_set (bss_section, 0);
1761 demand_empty_rest_of_line ();
1762 mapping_state (MAP_DATA);
1766 s_even (int ignore ATTRIBUTE_UNUSED)
1768 /* Never make frag if expect extra pass. */
1770 frag_align (1, 0, 0);
1772 record_alignment (now_seg, 1);
1774 demand_empty_rest_of_line ();
1777 /* Directives: Literal pools. */
1779 static literal_pool *
1780 find_literal_pool (void)
1782 literal_pool * pool;
1784 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1786 if (pool->section == now_seg
1787 && pool->sub_section == now_subseg)
1794 static literal_pool *
1795 find_or_make_literal_pool (void)
1797 /* Next literal pool ID number. */
1798 static unsigned int latest_pool_num = 1;
1799 literal_pool * pool;
1801 pool = find_literal_pool ();
1805 /* Create a new pool. */
1806 pool = xmalloc (sizeof (* pool));
1810 pool->next_free_entry = 0;
1811 pool->section = now_seg;
1812 pool->sub_section = now_subseg;
1813 pool->next = list_of_pools;
1814 pool->symbol = NULL;
1816 /* Add it to the list. */
1817 list_of_pools = pool;
1820 /* New pools, and emptied pools, will have a NULL symbol. */
1821 if (pool->symbol == NULL)
1823 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1824 (valueT) 0, &zero_address_frag);
1825 pool->id = latest_pool_num ++;
1832 /* Add the literal in the global 'inst'
1833 structure to the relevent literal pool. */
1836 add_to_lit_pool (void)
1838 literal_pool * pool;
1841 pool = find_or_make_literal_pool ();
1843 /* Check if this literal value is already in the pool. */
1844 for (entry = 0; entry < pool->next_free_entry; entry ++)
1846 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1847 && (inst.reloc.exp.X_op == O_constant)
1848 && (pool->literals[entry].X_add_number
1849 == inst.reloc.exp.X_add_number)
1850 && (pool->literals[entry].X_unsigned
1851 == inst.reloc.exp.X_unsigned))
1854 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1855 && (inst.reloc.exp.X_op == O_symbol)
1856 && (pool->literals[entry].X_add_number
1857 == inst.reloc.exp.X_add_number)
1858 && (pool->literals[entry].X_add_symbol
1859 == inst.reloc.exp.X_add_symbol)
1860 && (pool->literals[entry].X_op_symbol
1861 == inst.reloc.exp.X_op_symbol))
1865 /* Do we need to create a new entry? */
1866 if (entry == pool->next_free_entry)
1868 if (entry >= MAX_LITERAL_POOL_SIZE)
1870 inst.error = _("literal pool overflow");
1874 pool->literals[entry] = inst.reloc.exp;
1875 pool->next_free_entry += 1;
1878 inst.reloc.exp.X_op = O_symbol;
1879 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1880 inst.reloc.exp.X_add_symbol = pool->symbol;
1885 /* Can't use symbol_new here, so have to create a symbol and then at
1886 a later date assign it a value. Thats what these functions do. */
1889 symbol_locate (symbolS * symbolP,
1890 const char * name, /* It is copied, the caller can modify. */
1891 segT segment, /* Segment identifier (SEG_<something>). */
1892 valueT valu, /* Symbol value. */
1893 fragS * frag) /* Associated fragment. */
1895 unsigned int name_length;
1896 char * preserved_copy_of_name;
1898 name_length = strlen (name) + 1; /* +1 for \0. */
1899 obstack_grow (¬es, name, name_length);
1900 preserved_copy_of_name = obstack_finish (¬es);
1902 #ifdef tc_canonicalize_symbol_name
1903 preserved_copy_of_name =
1904 tc_canonicalize_symbol_name (preserved_copy_of_name);
1907 S_SET_NAME (symbolP, preserved_copy_of_name);
1909 S_SET_SEGMENT (symbolP, segment);
1910 S_SET_VALUE (symbolP, valu);
1911 symbol_clear_list_pointers (symbolP);
1913 symbol_set_frag (symbolP, frag);
1915 /* Link to end of symbol chain. */
1917 extern int symbol_table_frozen;
1919 if (symbol_table_frozen)
1923 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1925 obj_symbol_new_hook (symbolP);
1927 #ifdef tc_symbol_new_hook
1928 tc_symbol_new_hook (symbolP);
1932 verify_symbol_chain (symbol_rootP, symbol_lastP);
1933 #endif /* DEBUG_SYMS */
1938 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1941 literal_pool * pool;
1944 pool = find_literal_pool ();
1946 || pool->symbol == NULL
1947 || pool->next_free_entry == 0)
1950 mapping_state (MAP_DATA);
1952 /* Align pool as you have word accesses.
1953 Only make a frag if we have to. */
1955 frag_align (2, 0, 0);
1957 record_alignment (now_seg, 2);
1959 sprintf (sym_name, "$$lit_\002%x", pool->id);
1961 symbol_locate (pool->symbol, sym_name, now_seg,
1962 (valueT) frag_now_fix (), frag_now);
1963 symbol_table_insert (pool->symbol);
1965 ARM_SET_THUMB (pool->symbol, thumb_mode);
1967 #if defined OBJ_COFF || defined OBJ_ELF
1968 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1971 for (entry = 0; entry < pool->next_free_entry; entry ++)
1972 /* First output the expression in the instruction to the pool. */
1973 emit_expr (&(pool->literals[entry]), 4); /* .word */
1975 /* Mark the pool as empty. */
1976 pool->next_free_entry = 0;
1977 pool->symbol = NULL;
1981 /* Forward declarations for functions below, in the MD interface
1983 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1984 static valueT create_unwind_entry (int);
1985 static void start_unwind_section (const segT, int);
1986 static void add_unwind_opcode (valueT, int);
1987 static void flush_pending_unwind (void);
1989 /* Directives: Data. */
1992 s_arm_elf_cons (int nbytes)
1996 #ifdef md_flush_pending_output
1997 md_flush_pending_output ();
2000 if (is_it_end_of_statement ())
2002 demand_empty_rest_of_line ();
2006 #ifdef md_cons_align
2007 md_cons_align (nbytes);
2010 mapping_state (MAP_DATA);
2014 char *base = input_line_pointer;
2018 if (exp.X_op != O_symbol)
2019 emit_expr (&exp, (unsigned int) nbytes);
2022 char *before_reloc = input_line_pointer;
2023 reloc = parse_reloc (&input_line_pointer);
2026 as_bad (_("unrecognized relocation suffix"));
2027 ignore_rest_of_line ();
2030 else if (reloc == BFD_RELOC_UNUSED)
2031 emit_expr (&exp, (unsigned int) nbytes);
2034 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
2035 int size = bfd_get_reloc_size (howto);
2037 if (reloc == BFD_RELOC_ARM_PLT32)
2039 as_bad (_("(plt) is only valid on branch targets"));
2040 reloc = BFD_RELOC_UNUSED;
2045 as_bad (_("%s relocations do not fit in %d bytes"),
2046 howto->name, nbytes);
2049 /* We've parsed an expression stopping at O_symbol.
2050 But there may be more expression left now that we
2051 have parsed the relocation marker. Parse it again.
2052 XXX Surely there is a cleaner way to do this. */
2053 char *p = input_line_pointer;
2055 char *save_buf = alloca (input_line_pointer - base);
2056 memcpy (save_buf, base, input_line_pointer - base);
2057 memmove (base + (input_line_pointer - before_reloc),
2058 base, before_reloc - base);
2060 input_line_pointer = base + (input_line_pointer-before_reloc);
2062 memcpy (base, save_buf, p - base);
2064 offset = nbytes - size;
2065 p = frag_more ((int) nbytes);
2066 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2067 size, &exp, 0, reloc);
2072 while (*input_line_pointer++ == ',');
2074 /* Put terminator back into stream. */
2075 input_line_pointer --;
2076 demand_empty_rest_of_line ();
2080 /* Parse a .rel31 directive. */
2083 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2090 if (*input_line_pointer == '1')
2091 highbit = 0x80000000;
2092 else if (*input_line_pointer != '0')
2093 as_bad (_("expected 0 or 1"));
2095 input_line_pointer++;
2096 if (*input_line_pointer != ',')
2097 as_bad (_("missing comma"));
2098 input_line_pointer++;
2100 #ifdef md_flush_pending_output
2101 md_flush_pending_output ();
2104 #ifdef md_cons_align
2108 mapping_state (MAP_DATA);
2113 md_number_to_chars (p, highbit, 4);
2114 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2115 BFD_RELOC_ARM_PREL31);
2117 demand_empty_rest_of_line ();
2120 /* Directives: AEABI stack-unwind tables. */
2122 /* Parse an unwind_fnstart directive. Simply records the current location. */
2125 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2127 demand_empty_rest_of_line ();
2128 /* Mark the start of the function. */
2129 unwind.proc_start = expr_build_dot ();
2131 /* Reset the rest of the unwind info. */
2132 unwind.opcode_count = 0;
2133 unwind.table_entry = NULL;
2134 unwind.personality_routine = NULL;
2135 unwind.personality_index = -1;
2136 unwind.frame_size = 0;
2137 unwind.fp_offset = 0;
2140 unwind.sp_restored = 0;
2144 /* Parse a handlerdata directive. Creates the exception handling table entry
2145 for the function. */
2148 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2150 demand_empty_rest_of_line ();
2151 if (unwind.table_entry)
2152 as_bad (_("dupicate .handlerdata directive"));
2154 create_unwind_entry (1);
2157 /* Parse an unwind_fnend directive. Generates the index table entry. */
2160 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2166 demand_empty_rest_of_line ();
2168 /* Add eh table entry. */
2169 if (unwind.table_entry == NULL)
2170 val = create_unwind_entry (0);
2174 /* Add index table entry. This is two words. */
2175 start_unwind_section (unwind.saved_seg, 1);
2176 frag_align (2, 0, 0);
2177 record_alignment (now_seg, 2);
2179 ptr = frag_more (8);
2180 where = frag_now_fix () - 8;
2182 /* Self relative offset of the function start. */
2183 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2184 BFD_RELOC_ARM_PREL31);
2186 /* Indicate dependency on EHABI-defined personality routines to the
2187 linker, if it hasn't been done already. */
2188 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2189 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2191 static const char *const name[] = {
2192 "__aeabi_unwind_cpp_pr0",
2193 "__aeabi_unwind_cpp_pr1",
2194 "__aeabi_unwind_cpp_pr2"
2196 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2197 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2198 marked_pr_dependency |= 1 << unwind.personality_index;
2199 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2200 = marked_pr_dependency;
2204 /* Inline exception table entry. */
2205 md_number_to_chars (ptr + 4, val, 4);
2207 /* Self relative offset of the table entry. */
2208 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2209 BFD_RELOC_ARM_PREL31);
2211 /* Restore the original section. */
2212 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2216 /* Parse an unwind_cantunwind directive. */
2219 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2221 demand_empty_rest_of_line ();
2222 if (unwind.personality_routine || unwind.personality_index != -1)
2223 as_bad (_("personality routine specified for cantunwind frame"));
2225 unwind.personality_index = -2;
2229 /* Parse a personalityindex directive. */
2232 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2236 if (unwind.personality_routine || unwind.personality_index != -1)
2237 as_bad (_("duplicate .personalityindex directive"));
2241 if (exp.X_op != O_constant
2242 || exp.X_add_number < 0 || exp.X_add_number > 15)
2244 as_bad (_("bad personality routine number"));
2245 ignore_rest_of_line ();
2249 unwind.personality_index = exp.X_add_number;
2251 demand_empty_rest_of_line ();
2255 /* Parse a personality directive. */
2258 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2262 if (unwind.personality_routine || unwind.personality_index != -1)
2263 as_bad (_("duplicate .personality directive"));
2265 name = input_line_pointer;
2266 c = get_symbol_end ();
2267 p = input_line_pointer;
2268 unwind.personality_routine = symbol_find_or_make (name);
2270 demand_empty_rest_of_line ();
2274 /* Parse a directive saving core registers. */
2277 s_arm_unwind_save_core (void)
2283 range = parse_reg_list (&input_line_pointer);
2286 as_bad (_("expected register list"));
2287 ignore_rest_of_line ();
2291 demand_empty_rest_of_line ();
2293 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2294 into .unwind_save {..., sp...}. We aren't bothered about the value of
2295 ip because it is clobbered by calls. */
2296 if (unwind.sp_restored && unwind.fp_reg == 12
2297 && (range & 0x3000) == 0x1000)
2299 unwind.opcode_count--;
2300 unwind.sp_restored = 0;
2301 range = (range | 0x2000) & ~0x1000;
2302 unwind.pending_offset = 0;
2308 /* See if we can use the short opcodes. These pop a block of up to 8
2309 registers starting with r4, plus maybe r14. */
2310 for (n = 0; n < 8; n++)
2312 /* Break at the first non-saved register. */
2313 if ((range & (1 << (n + 4))) == 0)
2316 /* See if there are any other bits set. */
2317 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2319 /* Use the long form. */
2320 op = 0x8000 | ((range >> 4) & 0xfff);
2321 add_unwind_opcode (op, 2);
2325 /* Use the short form. */
2327 op = 0xa8; /* Pop r14. */
2329 op = 0xa0; /* Do not pop r14. */
2331 add_unwind_opcode (op, 1);
2338 op = 0xb100 | (range & 0xf);
2339 add_unwind_opcode (op, 2);
2342 /* Record the number of bytes pushed. */
2343 for (n = 0; n < 16; n++)
2345 if (range & (1 << n))
2346 unwind.frame_size += 4;
2351 /* Parse a directive saving FPA registers. */
2354 s_arm_unwind_save_fpa (int reg)
2360 /* Get Number of registers to transfer. */
2361 if (skip_past_comma (&input_line_pointer) != FAIL)
2364 exp.X_op = O_illegal;
2366 if (exp.X_op != O_constant)
2368 as_bad (_("expected , <constant>"));
2369 ignore_rest_of_line ();
2373 num_regs = exp.X_add_number;
2375 if (num_regs < 1 || num_regs > 4)
2377 as_bad (_("number of registers must be in the range [1:4]"));
2378 ignore_rest_of_line ();
2382 demand_empty_rest_of_line ();
2387 op = 0xb4 | (num_regs - 1);
2388 add_unwind_opcode (op, 1);
2393 op = 0xc800 | (reg << 4) | (num_regs - 1);
2394 add_unwind_opcode (op, 2);
2396 unwind.frame_size += num_regs * 12;
2400 /* Parse a directive saving VFP registers. */
2403 s_arm_unwind_save_vfp (void)
2409 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2412 as_bad (_("expected register list"));
2413 ignore_rest_of_line ();
2417 demand_empty_rest_of_line ();
2422 op = 0xb8 | (count - 1);
2423 add_unwind_opcode (op, 1);
2428 op = 0xb300 | (reg << 4) | (count - 1);
2429 add_unwind_opcode (op, 2);
2431 unwind.frame_size += count * 8 + 4;
2435 /* Parse a directive saving iWMMXt data registers. */
2438 s_arm_unwind_save_mmxwr (void)
2446 if (*input_line_pointer == '{')
2447 input_line_pointer++;
2451 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2455 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2460 as_tsktsk (_("register list not in ascending order"));
2463 if (*input_line_pointer == '-')
2465 input_line_pointer++;
2466 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2469 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2472 else if (reg >= hi_reg)
2474 as_bad (_("bad register range"));
2477 for (; reg < hi_reg; reg++)
2481 while (skip_past_comma (&input_line_pointer) != FAIL);
2483 if (*input_line_pointer == '}')
2484 input_line_pointer++;
2486 demand_empty_rest_of_line ();
2488 /* Generate any deferred opcodes becuuse we're going to be looking at
2490 flush_pending_unwind ();
2492 for (i = 0; i < 16; i++)
2494 if (mask & (1 << i))
2495 unwind.frame_size += 8;
2498 /* Attempt to combine with a previous opcode. We do this because gcc
2499 likes to output separate unwind directives for a single block of
2501 if (unwind.opcode_count > 0)
2503 i = unwind.opcodes[unwind.opcode_count - 1];
2504 if ((i & 0xf8) == 0xc0)
2507 /* Only merge if the blocks are contiguous. */
2510 if ((mask & 0xfe00) == (1 << 9))
2512 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2513 unwind.opcode_count--;
2516 else if (i == 6 && unwind.opcode_count >= 2)
2518 i = unwind.opcodes[unwind.opcode_count - 2];
2522 op = 0xffff << (reg - 1);
2524 || ((mask & op) == (1u << (reg - 1))))
2526 op = (1 << (reg + i + 1)) - 1;
2527 op &= ~((1 << reg) - 1);
2529 unwind.opcode_count -= 2;
2536 /* We want to generate opcodes in the order the registers have been
2537 saved, ie. descending order. */
2538 for (reg = 15; reg >= -1; reg--)
2540 /* Save registers in blocks. */
2542 || !(mask & (1 << reg)))
2544 /* We found an unsaved reg. Generate opcodes to save the
2545 preceeding block. */
2551 op = 0xc0 | (hi_reg - 10);
2552 add_unwind_opcode (op, 1);
2557 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2558 add_unwind_opcode (op, 2);
2567 ignore_rest_of_line ();
2571 s_arm_unwind_save_mmxwcg (void)
2578 if (*input_line_pointer == '{')
2579 input_line_pointer++;
2583 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2587 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2593 as_tsktsk (_("register list not in ascending order"));
2596 if (*input_line_pointer == '-')
2598 input_line_pointer++;
2599 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2602 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2605 else if (reg >= hi_reg)
2607 as_bad (_("bad register range"));
2610 for (; reg < hi_reg; reg++)
2614 while (skip_past_comma (&input_line_pointer) != FAIL);
2616 if (*input_line_pointer == '}')
2617 input_line_pointer++;
2619 demand_empty_rest_of_line ();
2621 /* Generate any deferred opcodes becuuse we're going to be looking at
2623 flush_pending_unwind ();
2625 for (reg = 0; reg < 16; reg++)
2627 if (mask & (1 << reg))
2628 unwind.frame_size += 4;
2631 add_unwind_opcode (op, 2);
2634 ignore_rest_of_line ();
2638 /* Parse an unwind_save directive. */
2641 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2644 struct reg_entry *reg;
2645 bfd_boolean had_brace = FALSE;
2647 /* Figure out what sort of save we have. */
2648 peek = input_line_pointer;
2656 reg = arm_reg_parse_multi (&peek);
2660 as_bad (_("register expected"));
2661 ignore_rest_of_line ();
2670 as_bad (_("FPA .unwind_save does not take a register list"));
2671 ignore_rest_of_line ();
2674 s_arm_unwind_save_fpa (reg->number);
2677 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2678 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2679 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2680 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2683 as_bad (_(".unwind_save does not support this kind of register"));
2684 ignore_rest_of_line ();
2689 /* Parse an unwind_movsp directive. */
2692 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2697 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2700 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2701 ignore_rest_of_line ();
2704 demand_empty_rest_of_line ();
2706 if (reg == REG_SP || reg == REG_PC)
2708 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2712 if (unwind.fp_reg != REG_SP)
2713 as_bad (_("unexpected .unwind_movsp directive"));
2715 /* Generate opcode to restore the value. */
2717 add_unwind_opcode (op, 1);
2719 /* Record the information for later. */
2720 unwind.fp_reg = reg;
2721 unwind.fp_offset = unwind.frame_size;
2722 unwind.sp_restored = 1;
2725 /* Parse an unwind_pad directive. */
2728 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2732 if (immediate_for_directive (&offset) == FAIL)
2737 as_bad (_("stack increment must be multiple of 4"));
2738 ignore_rest_of_line ();
2742 /* Don't generate any opcodes, just record the details for later. */
2743 unwind.frame_size += offset;
2744 unwind.pending_offset += offset;
2746 demand_empty_rest_of_line ();
2749 /* Parse an unwind_setfp directive. */
2752 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2758 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2759 if (skip_past_comma (&input_line_pointer) == FAIL)
2762 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2764 if (fp_reg == FAIL || sp_reg == FAIL)
2766 as_bad (_("expected <reg>, <reg>"));
2767 ignore_rest_of_line ();
2771 /* Optional constant. */
2772 if (skip_past_comma (&input_line_pointer) != FAIL)
2774 if (immediate_for_directive (&offset) == FAIL)
2780 demand_empty_rest_of_line ();
2782 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2784 as_bad (_("register must be either sp or set by a previous"
2785 "unwind_movsp directive"));
2789 /* Don't generate any opcodes, just record the information for later. */
2790 unwind.fp_reg = fp_reg;
2793 unwind.fp_offset = unwind.frame_size - offset;
2795 unwind.fp_offset -= offset;
2798 /* Parse an unwind_raw directive. */
2801 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2804 /* This is an arbitary limit. */
2805 unsigned char op[16];
2809 if (exp.X_op == O_constant
2810 && skip_past_comma (&input_line_pointer) != FAIL)
2812 unwind.frame_size += exp.X_add_number;
2816 exp.X_op = O_illegal;
2818 if (exp.X_op != O_constant)
2820 as_bad (_("expected <offset>, <opcode>"));
2821 ignore_rest_of_line ();
2827 /* Parse the opcode. */
2832 as_bad (_("unwind opcode too long"));
2833 ignore_rest_of_line ();
2835 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2837 as_bad (_("invalid unwind opcode"));
2838 ignore_rest_of_line ();
2841 op[count++] = exp.X_add_number;
2843 /* Parse the next byte. */
2844 if (skip_past_comma (&input_line_pointer) == FAIL)
2850 /* Add the opcode bytes in reverse order. */
2852 add_unwind_opcode (op[count], 1);
2854 demand_empty_rest_of_line ();
2858 /* Parse a .eabi_attribute directive. */
2861 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
2864 bfd_boolean is_string;
2871 if (exp.X_op != O_constant)
2874 tag = exp.X_add_number;
2875 if (tag == 4 || tag == 5 || tag == 32 || (tag > 32 && (tag & 1) != 0))
2880 if (skip_past_comma (&input_line_pointer) == FAIL)
2882 if (tag == 32 || !is_string)
2885 if (exp.X_op != O_constant)
2887 as_bad (_("expected numeric constant"));
2888 ignore_rest_of_line ();
2891 i = exp.X_add_number;
2893 if (tag == Tag_compatibility
2894 && skip_past_comma (&input_line_pointer) == FAIL)
2896 as_bad (_("expected comma"));
2897 ignore_rest_of_line ();
2902 skip_whitespace(input_line_pointer);
2903 if (*input_line_pointer != '"')
2905 input_line_pointer++;
2906 s = input_line_pointer;
2907 while (*input_line_pointer && *input_line_pointer != '"')
2908 input_line_pointer++;
2909 if (*input_line_pointer != '"')
2911 saved_char = *input_line_pointer;
2912 *input_line_pointer = 0;
2920 if (tag == Tag_compatibility)
2921 elf32_arm_add_eabi_attr_compat (stdoutput, i, s);
2923 elf32_arm_add_eabi_attr_string (stdoutput, tag, s);
2925 elf32_arm_add_eabi_attr_int (stdoutput, tag, i);
2929 *input_line_pointer = saved_char;
2930 input_line_pointer++;
2932 demand_empty_rest_of_line ();
2935 as_bad (_("bad string constant"));
2936 ignore_rest_of_line ();
2939 as_bad (_("expected <tag> , <value>"));
2940 ignore_rest_of_line ();
2943 static void s_arm_arch (int);
2944 static void s_arm_cpu (int);
2945 static void s_arm_fpu (int);
2946 #endif /* OBJ_ELF */
2948 /* This table describes all the machine specific pseudo-ops the assembler
2949 has to support. The fields are:
2950 pseudo-op name without dot
2951 function to call to execute this pseudo-op
2952 Integer arg to pass to the function. */
2954 const pseudo_typeS md_pseudo_table[] =
2956 /* Never called because '.req' does not start a line. */
2957 { "req", s_req, 0 },
2958 { "unreq", s_unreq, 0 },
2959 { "bss", s_bss, 0 },
2960 { "align", s_align, 0 },
2961 { "arm", s_arm, 0 },
2962 { "thumb", s_thumb, 0 },
2963 { "code", s_code, 0 },
2964 { "force_thumb", s_force_thumb, 0 },
2965 { "thumb_func", s_thumb_func, 0 },
2966 { "thumb_set", s_thumb_set, 0 },
2967 { "even", s_even, 0 },
2968 { "ltorg", s_ltorg, 0 },
2969 { "pool", s_ltorg, 0 },
2970 { "syntax", s_syntax, 0 },
2972 { "word", s_arm_elf_cons, 4 },
2973 { "long", s_arm_elf_cons, 4 },
2974 { "rel31", s_arm_rel31, 0 },
2975 { "fnstart", s_arm_unwind_fnstart, 0 },
2976 { "fnend", s_arm_unwind_fnend, 0 },
2977 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2978 { "personality", s_arm_unwind_personality, 0 },
2979 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2980 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2981 { "save", s_arm_unwind_save, 0 },
2982 { "movsp", s_arm_unwind_movsp, 0 },
2983 { "pad", s_arm_unwind_pad, 0 },
2984 { "setfp", s_arm_unwind_setfp, 0 },
2985 { "unwind_raw", s_arm_unwind_raw, 0 },
2986 { "cpu", s_arm_cpu, 0 },
2987 { "arch", s_arm_arch, 0 },
2988 { "fpu", s_arm_fpu, 0 },
2989 { "eabi_attribute", s_arm_eabi_attribute, 0 },
2993 { "extend", float_cons, 'x' },
2994 { "ldouble", float_cons, 'x' },
2995 { "packed", float_cons, 'p' },
2999 /* Parser functions used exclusively in instruction operands. */
3001 /* Generic immediate-value read function for use in insn parsing.
3002 STR points to the beginning of the immediate (the leading #);
3003 VAL receives the value; if the value is outside [MIN, MAX]
3004 issue an error. PREFIX_OPT is true if the immediate prefix is
3008 parse_immediate (char **str, int *val, int min, int max,
3009 bfd_boolean prefix_opt)
3012 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
3013 if (exp.X_op != O_constant)
3015 inst.error = _("constant expression required");
3019 if (exp.X_add_number < min || exp.X_add_number > max)
3021 inst.error = _("immediate value out of range");
3025 *val = exp.X_add_number;
3029 /* Returns the pseudo-register number of an FPA immediate constant,
3030 or FAIL if there isn't a valid constant here. */
3033 parse_fpa_immediate (char ** str)
3035 LITTLENUM_TYPE words[MAX_LITTLENUMS];
3041 /* First try and match exact strings, this is to guarantee
3042 that some formats will work even for cross assembly. */
3044 for (i = 0; fp_const[i]; i++)
3046 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
3050 *str += strlen (fp_const[i]);
3051 if (is_end_of_line[(unsigned char) **str])
3057 /* Just because we didn't get a match doesn't mean that the constant
3058 isn't valid, just that it is in a format that we don't
3059 automatically recognize. Try parsing it with the standard
3060 expression routines. */
3062 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
3064 /* Look for a raw floating point number. */
3065 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
3066 && is_end_of_line[(unsigned char) *save_in])
3068 for (i = 0; i < NUM_FLOAT_VALS; i++)
3070 for (j = 0; j < MAX_LITTLENUMS; j++)
3072 if (words[j] != fp_values[i][j])
3076 if (j == MAX_LITTLENUMS)
3084 /* Try and parse a more complex expression, this will probably fail
3085 unless the code uses a floating point prefix (eg "0f"). */
3086 save_in = input_line_pointer;
3087 input_line_pointer = *str;
3088 if (expression (&exp) == absolute_section
3089 && exp.X_op == O_big
3090 && exp.X_add_number < 0)
3092 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
3094 if (gen_to_words (words, 5, (long) 15) == 0)
3096 for (i = 0; i < NUM_FLOAT_VALS; i++)
3098 for (j = 0; j < MAX_LITTLENUMS; j++)
3100 if (words[j] != fp_values[i][j])
3104 if (j == MAX_LITTLENUMS)
3106 *str = input_line_pointer;
3107 input_line_pointer = save_in;
3114 *str = input_line_pointer;
3115 input_line_pointer = save_in;
3116 inst.error = _("invalid FPA immediate expression");
3120 /* Shift operands. */
3123 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
3126 struct asm_shift_name
3129 enum shift_kind kind;
3132 /* Third argument to parse_shift. */
3133 enum parse_shift_mode
3135 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
3136 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
3137 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
3138 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
3139 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
3142 /* Parse a <shift> specifier on an ARM data processing instruction.
3143 This has three forms:
3145 (LSL|LSR|ASL|ASR|ROR) Rs
3146 (LSL|LSR|ASL|ASR|ROR) #imm
3149 Note that ASL is assimilated to LSL in the instruction encoding, and
3150 RRX to ROR #0 (which cannot be written as such). */
3153 parse_shift (char **str, int i, enum parse_shift_mode mode)
3155 const struct asm_shift_name *shift_name;
3156 enum shift_kind shift;
3161 for (p = *str; ISALPHA (*p); p++)
3166 inst.error = _("shift expression expected");
3170 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3172 if (shift_name == NULL)
3174 inst.error = _("shift expression expected");
3178 shift = shift_name->kind;
3182 case NO_SHIFT_RESTRICT:
3183 case SHIFT_IMMEDIATE: break;
3185 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3186 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3188 inst.error = _("'LSL' or 'ASR' required");
3193 case SHIFT_LSL_IMMEDIATE:
3194 if (shift != SHIFT_LSL)
3196 inst.error = _("'LSL' required");
3201 case SHIFT_ASR_IMMEDIATE:
3202 if (shift != SHIFT_ASR)
3204 inst.error = _("'ASR' required");
3212 if (shift != SHIFT_RRX)
3214 /* Whitespace can appear here if the next thing is a bare digit. */
3215 skip_whitespace (p);
3217 if (mode == NO_SHIFT_RESTRICT
3218 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3220 inst.operands[i].imm = reg;
3221 inst.operands[i].immisreg = 1;
3223 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3226 inst.operands[i].shift_kind = shift;
3227 inst.operands[i].shifted = 1;
3232 /* Parse a <shifter_operand> for an ARM data processing instruction:
3235 #<immediate>, <rotate>
3239 where <shift> is defined by parse_shift above, and <rotate> is a
3240 multiple of 2 between 0 and 30. Validation of immediate operands
3241 is deferred to md_apply_fix. */
3244 parse_shifter_operand (char **str, int i)
3249 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3251 inst.operands[i].reg = value;
3252 inst.operands[i].isreg = 1;
3254 /* parse_shift will override this if appropriate */
3255 inst.reloc.exp.X_op = O_constant;
3256 inst.reloc.exp.X_add_number = 0;
3258 if (skip_past_comma (str) == FAIL)
3261 /* Shift operation on register. */
3262 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3265 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3268 if (skip_past_comma (str) == SUCCESS)
3270 /* #x, y -- ie explicit rotation by Y. */
3271 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3274 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3276 inst.error = _("constant expression expected");
3280 value = expr.X_add_number;
3281 if (value < 0 || value > 30 || value % 2 != 0)
3283 inst.error = _("invalid rotation");
3286 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3288 inst.error = _("invalid constant");
3292 /* Convert to decoded value. md_apply_fix will put it back. */
3293 inst.reloc.exp.X_add_number
3294 = (((inst.reloc.exp.X_add_number << (32 - value))
3295 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3298 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3299 inst.reloc.pc_rel = 0;
3303 /* Parse all forms of an ARM address expression. Information is written
3304 to inst.operands[i] and/or inst.reloc.
3306 Preindexed addressing (.preind=1):
3308 [Rn, #offset] .reg=Rn .reloc.exp=offset
3309 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3310 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3311 .shift_kind=shift .reloc.exp=shift_imm
3313 These three may have a trailing ! which causes .writeback to be set also.
3315 Postindexed addressing (.postind=1, .writeback=1):
3317 [Rn], #offset .reg=Rn .reloc.exp=offset
3318 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3319 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3320 .shift_kind=shift .reloc.exp=shift_imm
3322 Unindexed addressing (.preind=0, .postind=0):
3324 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3328 [Rn]{!} shorthand for [Rn,#0]{!}
3329 =immediate .isreg=0 .reloc.exp=immediate
3330 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3332 It is the caller's responsibility to check for addressing modes not
3333 supported by the instruction, and to set inst.reloc.type. */
3336 parse_address (char **str, int i)
3341 if (skip_past_char (&p, '[') == FAIL)
3343 if (skip_past_char (&p, '=') == FAIL)
3345 /* bare address - translate to PC-relative offset */
3346 inst.reloc.pc_rel = 1;
3347 inst.operands[i].reg = REG_PC;
3348 inst.operands[i].isreg = 1;
3349 inst.operands[i].preind = 1;
3351 /* else a load-constant pseudo op, no special treatment needed here */
3353 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3360 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3362 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3365 inst.operands[i].reg = reg;
3366 inst.operands[i].isreg = 1;
3368 if (skip_past_comma (&p) == SUCCESS)
3370 inst.operands[i].preind = 1;
3373 else if (*p == '-') p++, inst.operands[i].negative = 1;
3375 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3377 inst.operands[i].imm = reg;
3378 inst.operands[i].immisreg = 1;
3380 if (skip_past_comma (&p) == SUCCESS)
3381 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3386 if (inst.operands[i].negative)
3388 inst.operands[i].negative = 0;
3391 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3396 if (skip_past_char (&p, ']') == FAIL)
3398 inst.error = _("']' expected");
3402 if (skip_past_char (&p, '!') == SUCCESS)
3403 inst.operands[i].writeback = 1;
3405 else if (skip_past_comma (&p) == SUCCESS)
3407 if (skip_past_char (&p, '{') == SUCCESS)
3409 /* [Rn], {expr} - unindexed, with option */
3410 if (parse_immediate (&p, &inst.operands[i].imm,
3411 0, 255, TRUE) == FAIL)
3414 if (skip_past_char (&p, '}') == FAIL)
3416 inst.error = _("'}' expected at end of 'option' field");
3419 if (inst.operands[i].preind)
3421 inst.error = _("cannot combine index with option");
3429 inst.operands[i].postind = 1;
3430 inst.operands[i].writeback = 1;
3432 if (inst.operands[i].preind)
3434 inst.error = _("cannot combine pre- and post-indexing");
3439 else if (*p == '-') p++, inst.operands[i].negative = 1;
3441 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3443 inst.operands[i].imm = reg;
3444 inst.operands[i].immisreg = 1;
3446 if (skip_past_comma (&p) == SUCCESS)
3447 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3452 if (inst.operands[i].negative)
3454 inst.operands[i].negative = 0;
3457 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3463 /* If at this point neither .preind nor .postind is set, we have a
3464 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3465 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3467 inst.operands[i].preind = 1;
3468 inst.reloc.exp.X_op = O_constant;
3469 inst.reloc.exp.X_add_number = 0;
3475 /* Miscellaneous. */
3477 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3478 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3480 parse_psr (char **str)
3483 unsigned long psr_field;
3485 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3486 feature for ease of use and backwards compatibility. */
3488 if (*p == 's' || *p == 'S')
3489 psr_field = SPSR_BIT;
3490 else if (*p == 'c' || *p == 'C')
3496 if (strncasecmp (p, "PSR", 3) != 0)
3502 /* A suffix follows. */
3503 const struct asm_psr *psr;
3511 while (ISALNUM (*p) || *p == '_');
3513 psr = hash_find_n (arm_psr_hsh, start, p - start);
3517 psr_field |= psr->field;
3522 goto error; /* Garbage after "[CS]PSR". */
3524 psr_field |= (PSR_c | PSR_f);
3530 inst.error = _("flag for {c}psr instruction expected");
3534 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3535 value suitable for splatting into the AIF field of the instruction. */
3538 parse_cps_flags (char **str)
3547 case '\0': case ',':
3550 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3551 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3552 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3555 inst.error = _("unrecognized CPS flag");
3560 if (saw_a_flag == 0)
3562 inst.error = _("missing CPS flags");
3570 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3571 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3574 parse_endian_specifier (char **str)
3579 if (strncasecmp (s, "BE", 2))
3581 else if (strncasecmp (s, "LE", 2))
3585 inst.error = _("valid endian specifiers are be or le");
3589 if (ISALNUM (s[2]) || s[2] == '_')
3591 inst.error = _("valid endian specifiers are be or le");
3596 return little_endian;
3599 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3600 value suitable for poking into the rotate field of an sxt or sxta
3601 instruction, or FAIL on error. */
3604 parse_ror (char **str)
3609 if (strncasecmp (s, "ROR", 3) == 0)
3613 inst.error = _("missing rotation field after comma");
3617 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3622 case 0: *str = s; return 0x0;
3623 case 8: *str = s; return 0x1;
3624 case 16: *str = s; return 0x2;
3625 case 24: *str = s; return 0x3;
3628 inst.error = _("rotation can only be 0, 8, 16, or 24");
3633 /* Parse a conditional code (from conds[] below). The value returned is in the
3634 range 0 .. 14, or FAIL. */
3636 parse_cond (char **str)
3639 const struct asm_cond *c;
3642 while (ISALPHA (*q))
3645 c = hash_find_n (arm_cond_hsh, p, q - p);
3648 inst.error = _("condition required");
3656 /* Parse the operands of a table branch instruction. Similar to a memory
3659 parse_tb (char **str)
3664 if (skip_past_char (&p, '[') == FAIL)
3667 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3669 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3672 inst.operands[0].reg = reg;
3674 if (skip_past_comma (&p) == FAIL)
3677 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3679 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3682 inst.operands[0].imm = reg;
3684 if (skip_past_comma (&p) == SUCCESS)
3686 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3688 if (inst.reloc.exp.X_add_number != 1)
3690 inst.error = _("invalid shift");
3693 inst.operands[0].shifted = 1;
3696 if (skip_past_char (&p, ']') == FAIL)
3698 inst.error = _("']' expected");
3705 /* Matcher codes for parse_operands. */
3706 enum operand_parse_code
3708 OP_stop, /* end of line */
3710 OP_RR, /* ARM register */
3711 OP_RRnpc, /* ARM register, not r15 */
3712 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3713 OP_RRw, /* ARM register, not r15, optional trailing ! */
3714 OP_RCP, /* Coprocessor number */
3715 OP_RCN, /* Coprocessor register */
3716 OP_RF, /* FPA register */
3717 OP_RVS, /* VFP single precision register */
3718 OP_RVD, /* VFP double precision register */
3719 OP_RVC, /* VFP control register */
3720 OP_RMF, /* Maverick F register */
3721 OP_RMD, /* Maverick D register */
3722 OP_RMFX, /* Maverick FX register */
3723 OP_RMDX, /* Maverick DX register */
3724 OP_RMAX, /* Maverick AX register */
3725 OP_RMDS, /* Maverick DSPSC register */
3726 OP_RIWR, /* iWMMXt wR register */
3727 OP_RIWC, /* iWMMXt wC register */
3728 OP_RIWG, /* iWMMXt wCG register */
3729 OP_RXA, /* XScale accumulator register */
3731 OP_REGLST, /* ARM register list */
3732 OP_VRSLST, /* VFP single-precision register list */
3733 OP_VRDLST, /* VFP double-precision register list */
3735 OP_I7, /* immediate value 0 .. 7 */
3736 OP_I15, /* 0 .. 15 */
3737 OP_I16, /* 1 .. 16 */
3738 OP_I31, /* 0 .. 31 */
3739 OP_I31w, /* 0 .. 31, optional trailing ! */
3740 OP_I32, /* 1 .. 32 */
3741 OP_I63s, /* -64 .. 63 */
3742 OP_I255, /* 0 .. 255 */
3743 OP_Iffff, /* 0 .. 65535 */
3745 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3746 OP_I7b, /* 0 .. 7 */
3747 OP_I15b, /* 0 .. 15 */
3748 OP_I31b, /* 0 .. 31 */
3750 OP_SH, /* shifter operand */
3751 OP_ADDR, /* Memory address expression (any mode) */
3752 OP_EXP, /* arbitrary expression */
3753 OP_EXPi, /* same, with optional immediate prefix */
3754 OP_EXPr, /* same, with optional relocation suffix */
3756 OP_CPSF, /* CPS flags */
3757 OP_ENDI, /* Endianness specifier */
3758 OP_PSR, /* CPSR/SPSR mask for msr */
3759 OP_COND, /* conditional code */
3760 OP_TB, /* Table branch. */
3762 OP_RRnpc_I0, /* ARM register or literal 0 */
3763 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3764 OP_RR_EXi, /* ARM register or expression with imm prefix */
3765 OP_RF_IF, /* FPA register or immediate */
3766 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3768 /* Optional operands. */
3769 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3770 OP_oI31b, /* 0 .. 31 */
3771 OP_oIffffb, /* 0 .. 65535 */
3772 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3774 OP_oRR, /* ARM register */
3775 OP_oRRnpc, /* ARM register, not the PC */
3776 OP_oSHll, /* LSL immediate */
3777 OP_oSHar, /* ASR immediate */
3778 OP_oSHllar, /* LSL or ASR immediate */
3779 OP_oROR, /* ROR 0/8/16/24 */
3781 OP_FIRST_OPTIONAL = OP_oI7b
3784 /* Generic instruction operand parser. This does no encoding and no
3785 semantic validation; it merely squirrels values away in the inst
3786 structure. Returns SUCCESS or FAIL depending on whether the
3787 specified grammar matched. */
3789 parse_operands (char *str, const unsigned char *pattern)
3791 unsigned const char *upat = pattern;
3792 char *backtrack_pos = 0;
3793 const char *backtrack_error = 0;
3794 int i, val, backtrack_index = 0;
3796 #define po_char_or_fail(chr) do { \
3797 if (skip_past_char (&str, chr) == FAIL) \
3801 #define po_reg_or_fail(regtype) do { \
3802 val = arm_reg_parse (&str, regtype); \
3805 inst.error = _(reg_expected_msgs[regtype]); \
3808 inst.operands[i].reg = val; \
3809 inst.operands[i].isreg = 1; \
3812 #define po_reg_or_goto(regtype, label) do { \
3813 val = arm_reg_parse (&str, regtype); \
3817 inst.operands[i].reg = val; \
3818 inst.operands[i].isreg = 1; \
3821 #define po_imm_or_fail(min, max, popt) do { \
3822 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3824 inst.operands[i].imm = val; \
3827 #define po_misc_or_fail(expr) do { \
3832 skip_whitespace (str);
3834 for (i = 0; upat[i] != OP_stop; i++)
3836 if (upat[i] >= OP_FIRST_OPTIONAL)
3838 /* Remember where we are in case we need to backtrack. */
3839 assert (!backtrack_pos);
3840 backtrack_pos = str;
3841 backtrack_error = inst.error;
3842 backtrack_index = i;
3846 po_char_or_fail (',');
3854 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3855 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3856 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3857 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3858 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3859 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3860 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3861 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3862 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3863 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3864 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3865 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3866 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3867 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3868 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3869 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3870 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3873 po_char_or_fail ('[');
3874 po_reg_or_fail (REG_TYPE_RN);
3875 po_char_or_fail (']');
3879 po_reg_or_fail (REG_TYPE_RN);
3880 if (skip_past_char (&str, '!') == SUCCESS)
3881 inst.operands[i].writeback = 1;
3885 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3886 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3887 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3888 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3889 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3890 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3891 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3892 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3894 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3896 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3897 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3899 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3900 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3902 /* Immediate variants */
3904 po_char_or_fail ('{');
3905 po_imm_or_fail (0, 255, TRUE);
3906 po_char_or_fail ('}');
3910 /* The expression parser chokes on a trailing !, so we have
3911 to find it first and zap it. */
3914 while (*s && *s != ',')
3919 inst.operands[i].writeback = 1;
3921 po_imm_or_fail (0, 31, TRUE);
3929 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3934 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3939 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3941 if (inst.reloc.exp.X_op == O_symbol)
3943 val = parse_reloc (&str);
3946 inst.error = _("unrecognized relocation suffix");
3949 else if (val != BFD_RELOC_UNUSED)
3951 inst.operands[i].imm = val;
3952 inst.operands[i].hasreloc = 1;
3957 /* Register or expression */
3958 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3959 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3961 /* Register or immediate */
3962 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3963 I0: po_imm_or_fail (0, 0, FALSE); break;
3965 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3967 if (!is_immediate_prefix (*str))
3970 val = parse_fpa_immediate (&str);
3973 /* FPA immediates are encoded as registers 8-15.
3974 parse_fpa_immediate has already applied the offset. */
3975 inst.operands[i].reg = val;
3976 inst.operands[i].isreg = 1;
3979 /* Two kinds of register */
3982 struct reg_entry *rege = arm_reg_parse_multi (&str);
3983 if (rege->type != REG_TYPE_MMXWR
3984 && rege->type != REG_TYPE_MMXWC
3985 && rege->type != REG_TYPE_MMXWCG)
3987 inst.error = _("iWMMXt data or control register expected");
3990 inst.operands[i].reg = rege->number;
3991 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3996 case OP_CPSF: val = parse_cps_flags (&str); break;
3997 case OP_ENDI: val = parse_endian_specifier (&str); break;
3998 case OP_oROR: val = parse_ror (&str); break;
3999 case OP_PSR: val = parse_psr (&str); break;
4000 case OP_COND: val = parse_cond (&str); break;
4003 po_misc_or_fail (parse_tb (&str));
4006 /* Register lists */
4008 val = parse_reg_list (&str);
4011 inst.operands[1].writeback = 1;
4017 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
4021 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
4024 /* Addressing modes */
4026 po_misc_or_fail (parse_address (&str, i));
4030 po_misc_or_fail (parse_shifter_operand (&str, i));
4034 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
4038 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
4042 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
4046 as_fatal ("unhandled operand code %d", upat[i]);
4049 /* Various value-based sanity checks and shared operations. We
4050 do not signal immediate failures for the register constraints;
4051 this allows a syntax error to take precedence. */
4059 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
4060 inst.error = BAD_PC;
4073 inst.operands[i].imm = val;
4080 /* If we get here, this operand was successfully parsed. */
4081 inst.operands[i].present = 1;
4085 inst.error = BAD_ARGS;
4091 /* Do not backtrack over a trailing optional argument that
4092 absorbed some text. We will only fail again, with the
4093 'garbage following instruction' error message, which is
4094 probably less helpful than the current one. */
4095 if (backtrack_index == i && backtrack_pos != str
4096 && upat[i+1] == OP_stop)
4099 /* Try again, skipping the optional argument at backtrack_pos. */
4100 str = backtrack_pos;
4101 inst.error = backtrack_error;
4102 inst.operands[backtrack_index].present = 0;
4103 i = backtrack_index;
4107 /* Check that we have parsed all the arguments. */
4108 if (*str != '\0' && !inst.error)
4109 inst.error = _("garbage following instruction");
4111 return inst.error ? FAIL : SUCCESS;
4114 #undef po_char_or_fail
4115 #undef po_reg_or_fail
4116 #undef po_reg_or_goto
4117 #undef po_imm_or_fail
4119 /* Shorthand macro for instruction encoding functions issuing errors. */
4120 #define constraint(expr, err) do { \
4128 /* Functions for operand encoding. ARM, then Thumb. */
4130 #define rotate_left(v, n) (v << n | v >> (32 - n))
4132 /* If VAL can be encoded in the immediate field of an ARM instruction,
4133 return the encoded form. Otherwise, return FAIL. */
4136 encode_arm_immediate (unsigned int val)
4140 for (i = 0; i < 32; i += 2)
4141 if ((a = rotate_left (val, i)) <= 0xff)
4142 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
4147 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
4148 return the encoded form. Otherwise, return FAIL. */
4150 encode_thumb32_immediate (unsigned int val)
4157 for (i = 1; i <= 24; i++)
4160 if ((val & ~(0xff << i)) == 0)
4161 return ((val >> i) & 0x7f) | ((32 - i) << 7);
4165 if (val == ((a << 16) | a))
4167 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4171 if (val == ((a << 16) | a))
4172 return 0x200 | (a >> 8);
4176 /* Encode a VFP SP register number into inst.instruction. */
4179 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4184 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4188 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4192 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4200 /* Encode a <shift> in an ARM-format instruction. The immediate,
4201 if any, is handled by md_apply_fix. */
4203 encode_arm_shift (int i)
4205 if (inst.operands[i].shift_kind == SHIFT_RRX)
4206 inst.instruction |= SHIFT_ROR << 5;
4209 inst.instruction |= inst.operands[i].shift_kind << 5;
4210 if (inst.operands[i].immisreg)
4212 inst.instruction |= SHIFT_BY_REG;
4213 inst.instruction |= inst.operands[i].imm << 8;
4216 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4221 encode_arm_shifter_operand (int i)
4223 if (inst.operands[i].isreg)
4225 inst.instruction |= inst.operands[i].reg;
4226 encode_arm_shift (i);
4229 inst.instruction |= INST_IMMEDIATE;
4232 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4234 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4236 assert (inst.operands[i].isreg);
4237 inst.instruction |= inst.operands[i].reg << 16;
4239 if (inst.operands[i].preind)
4243 inst.error = _("instruction does not accept preindexed addressing");
4246 inst.instruction |= PRE_INDEX;
4247 if (inst.operands[i].writeback)
4248 inst.instruction |= WRITE_BACK;
4251 else if (inst.operands[i].postind)
4253 assert (inst.operands[i].writeback);
4255 inst.instruction |= WRITE_BACK;
4257 else /* unindexed - only for coprocessor */
4259 inst.error = _("instruction does not accept unindexed addressing");
4263 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4264 && (((inst.instruction & 0x000f0000) >> 16)
4265 == ((inst.instruction & 0x0000f000) >> 12)))
4266 as_warn ((inst.instruction & LOAD_BIT)
4267 ? _("destination register same as write-back base")
4268 : _("source register same as write-back base"));
4271 /* inst.operands[i] was set up by parse_address. Encode it into an
4272 ARM-format mode 2 load or store instruction. If is_t is true,
4273 reject forms that cannot be used with a T instruction (i.e. not
4276 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4278 encode_arm_addr_mode_common (i, is_t);
4280 if (inst.operands[i].immisreg)
4282 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4283 inst.instruction |= inst.operands[i].imm;
4284 if (!inst.operands[i].negative)
4285 inst.instruction |= INDEX_UP;
4286 if (inst.operands[i].shifted)
4288 if (inst.operands[i].shift_kind == SHIFT_RRX)
4289 inst.instruction |= SHIFT_ROR << 5;
4292 inst.instruction |= inst.operands[i].shift_kind << 5;
4293 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4297 else /* immediate offset in inst.reloc */
4299 if (inst.reloc.type == BFD_RELOC_UNUSED)
4300 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4304 /* inst.operands[i] was set up by parse_address. Encode it into an
4305 ARM-format mode 3 load or store instruction. Reject forms that
4306 cannot be used with such instructions. If is_t is true, reject
4307 forms that cannot be used with a T instruction (i.e. not
4310 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4312 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4314 inst.error = _("instruction does not accept scaled register index");
4318 encode_arm_addr_mode_common (i, is_t);
4320 if (inst.operands[i].immisreg)
4322 inst.instruction |= inst.operands[i].imm;
4323 if (!inst.operands[i].negative)
4324 inst.instruction |= INDEX_UP;
4326 else /* immediate offset in inst.reloc */
4328 inst.instruction |= HWOFFSET_IMM;
4329 if (inst.reloc.type == BFD_RELOC_UNUSED)
4330 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4334 /* inst.operands[i] was set up by parse_address. Encode it into an
4335 ARM-format instruction. Reject all forms which cannot be encoded
4336 into a coprocessor load/store instruction. If wb_ok is false,
4337 reject use of writeback; if unind_ok is false, reject use of
4338 unindexed addressing. If reloc_override is not 0, use it instead
4339 of BFD_ARM_CP_OFF_IMM. */
4342 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4344 inst.instruction |= inst.operands[i].reg << 16;
4346 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4348 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4350 assert (!inst.operands[i].writeback);
4353 inst.error = _("instruction does not support unindexed addressing");
4356 inst.instruction |= inst.operands[i].imm;
4357 inst.instruction |= INDEX_UP;
4361 if (inst.operands[i].preind)
4362 inst.instruction |= PRE_INDEX;
4364 if (inst.operands[i].writeback)
4366 if (inst.operands[i].reg == REG_PC)
4368 inst.error = _("pc may not be used with write-back");
4373 inst.error = _("instruction does not support writeback");
4376 inst.instruction |= WRITE_BACK;
4380 inst.reloc.type = reloc_override;
4381 else if (thumb_mode)
4382 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4384 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4388 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4389 Determine whether it can be performed with a move instruction; if
4390 it can, convert inst.instruction to that move instruction and
4391 return 1; if it can't, convert inst.instruction to a literal-pool
4392 load and return 0. If this is not a valid thing to do in the
4393 current context, set inst.error and return 1.
4395 inst.operands[i] describes the destination register. */
4398 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4400 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4402 inst.error = _("invalid pseudo operation");
4405 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4407 inst.error = _("constant expression expected");
4410 if (inst.reloc.exp.X_op == O_constant)
4414 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4416 /* This can be done with a mov(1) instruction. */
4417 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4418 inst.instruction |= inst.reloc.exp.X_add_number;
4424 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4427 /* This can be done with a mov instruction. */
4428 inst.instruction &= LITERAL_MASK;
4429 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4430 inst.instruction |= value & 0xfff;
4434 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4437 /* This can be done with a mvn instruction. */
4438 inst.instruction &= LITERAL_MASK;
4439 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4440 inst.instruction |= value & 0xfff;
4446 if (add_to_lit_pool () == FAIL)
4448 inst.error = _("literal pool insertion failed");
4451 inst.operands[1].reg = REG_PC;
4452 inst.operands[1].isreg = 1;
4453 inst.operands[1].preind = 1;
4454 inst.reloc.pc_rel = 1;
4455 inst.reloc.type = (thumb_p
4456 ? BFD_RELOC_ARM_THUMB_OFFSET
4458 ? BFD_RELOC_ARM_HWLITERAL
4459 : BFD_RELOC_ARM_LITERAL));
4463 /* Functions for instruction encoding, sorted by subarchitecture.
4464 First some generics; their names are taken from the conventional
4465 bit positions for register arguments in ARM format instructions. */
4475 inst.instruction |= inst.operands[0].reg << 12;
4481 inst.instruction |= inst.operands[0].reg << 12;
4482 inst.instruction |= inst.operands[1].reg;
4488 inst.instruction |= inst.operands[0].reg << 12;
4489 inst.instruction |= inst.operands[1].reg << 16;
4495 inst.instruction |= inst.operands[0].reg << 16;
4496 inst.instruction |= inst.operands[1].reg << 12;
4502 unsigned Rn = inst.operands[2].reg;
4503 /* Enforce resutrictions on SWP instruction. */
4504 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
4505 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
4506 _("Rn must not overlap other operands"));
4507 inst.instruction |= inst.operands[0].reg << 12;
4508 inst.instruction |= inst.operands[1].reg;
4509 inst.instruction |= Rn << 16;
4515 inst.instruction |= inst.operands[0].reg << 12;
4516 inst.instruction |= inst.operands[1].reg << 16;
4517 inst.instruction |= inst.operands[2].reg;
4523 inst.instruction |= inst.operands[0].reg;
4524 inst.instruction |= inst.operands[1].reg << 12;
4525 inst.instruction |= inst.operands[2].reg << 16;
4531 inst.instruction |= inst.operands[0].imm;
4537 inst.instruction |= inst.operands[0].reg << 12;
4538 encode_arm_cp_address (1, TRUE, TRUE, 0);
4541 /* ARM instructions, in alphabetical order by function name (except
4542 that wrapper functions appear immediately after the function they
4545 /* This is a pseudo-op of the form "adr rd, label" to be converted
4546 into a relative address of the form "add rd, pc, #label-.-8". */
4551 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4553 /* Frag hacking will turn this into a sub instruction if the offset turns
4554 out to be negative. */
4555 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4556 inst.reloc.pc_rel = 1;
4557 inst.reloc.exp.X_add_number -= 8;
4560 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4561 into a relative address of the form:
4562 add rd, pc, #low(label-.-8)"
4563 add rd, rd, #high(label-.-8)" */
4568 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4570 /* Frag hacking will turn this into a sub instruction if the offset turns
4571 out to be negative. */
4572 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4573 inst.reloc.pc_rel = 1;
4574 inst.size = INSN_SIZE * 2;
4575 inst.reloc.exp.X_add_number -= 8;
4581 if (!inst.operands[1].present)
4582 inst.operands[1].reg = inst.operands[0].reg;
4583 inst.instruction |= inst.operands[0].reg << 12;
4584 inst.instruction |= inst.operands[1].reg << 16;
4585 encode_arm_shifter_operand (2);
4591 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4592 constraint (msb > 32, _("bit-field extends past end of register"));
4593 /* The instruction encoding stores the LSB and MSB,
4594 not the LSB and width. */
4595 inst.instruction |= inst.operands[0].reg << 12;
4596 inst.instruction |= inst.operands[1].imm << 7;
4597 inst.instruction |= (msb - 1) << 16;
4605 /* #0 in second position is alternative syntax for bfc, which is
4606 the same instruction but with REG_PC in the Rm field. */
4607 if (!inst.operands[1].isreg)
4608 inst.operands[1].reg = REG_PC;
4610 msb = inst.operands[2].imm + inst.operands[3].imm;
4611 constraint (msb > 32, _("bit-field extends past end of register"));
4612 /* The instruction encoding stores the LSB and MSB,
4613 not the LSB and width. */
4614 inst.instruction |= inst.operands[0].reg << 12;
4615 inst.instruction |= inst.operands[1].reg;
4616 inst.instruction |= inst.operands[2].imm << 7;
4617 inst.instruction |= (msb - 1) << 16;
4623 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4624 _("bit-field extends past end of register"));
4625 inst.instruction |= inst.operands[0].reg << 12;
4626 inst.instruction |= inst.operands[1].reg;
4627 inst.instruction |= inst.operands[2].imm << 7;
4628 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4631 /* ARM V5 breakpoint instruction (argument parse)
4632 BKPT <16 bit unsigned immediate>
4633 Instruction is not conditional.
4634 The bit pattern given in insns[] has the COND_ALWAYS condition,
4635 and it is an error if the caller tried to override that. */
4640 /* Top 12 of 16 bits to bits 19:8. */
4641 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4643 /* Bottom 4 of 16 bits to bits 3:0. */
4644 inst.instruction |= inst.operands[0].imm & 0xf;
4648 encode_branch (int default_reloc)
4650 if (inst.operands[0].hasreloc)
4652 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4653 _("the only suffix valid here is '(plt)'"));
4654 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4658 inst.reloc.type = default_reloc;
4660 inst.reloc.pc_rel = 1;
4667 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4668 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4671 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4678 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4680 if (inst.cond == COND_ALWAYS)
4681 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4683 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
4687 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4690 /* ARM V5 branch-link-exchange instruction (argument parse)
4691 BLX <target_addr> ie BLX(1)
4692 BLX{<condition>} <Rm> ie BLX(2)
4693 Unfortunately, there are two different opcodes for this mnemonic.
4694 So, the insns[].value is not used, and the code here zaps values
4695 into inst.instruction.
4696 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4701 if (inst.operands[0].isreg)
4703 /* Arg is a register; the opcode provided by insns[] is correct.
4704 It is not illegal to do "blx pc", just useless. */
4705 if (inst.operands[0].reg == REG_PC)
4706 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4708 inst.instruction |= inst.operands[0].reg;
4712 /* Arg is an address; this instruction cannot be executed
4713 conditionally, and the opcode must be adjusted. */
4714 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4715 inst.instruction = 0xfa000000;
4717 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
4718 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
4721 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4728 if (inst.operands[0].reg == REG_PC)
4729 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4731 inst.instruction |= inst.operands[0].reg;
4735 /* ARM v5TEJ. Jump to Jazelle code. */
4740 if (inst.operands[0].reg == REG_PC)
4741 as_tsktsk (_("use of r15 in bxj is not really useful"));
4743 inst.instruction |= inst.operands[0].reg;
4746 /* Co-processor data operation:
4747 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4748 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4752 inst.instruction |= inst.operands[0].reg << 8;
4753 inst.instruction |= inst.operands[1].imm << 20;
4754 inst.instruction |= inst.operands[2].reg << 12;
4755 inst.instruction |= inst.operands[3].reg << 16;
4756 inst.instruction |= inst.operands[4].reg;
4757 inst.instruction |= inst.operands[5].imm << 5;
4763 inst.instruction |= inst.operands[0].reg << 16;
4764 encode_arm_shifter_operand (1);
4767 /* Transfer between coprocessor and ARM registers.
4768 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4773 No special properties. */
4778 inst.instruction |= inst.operands[0].reg << 8;
4779 inst.instruction |= inst.operands[1].imm << 21;
4780 inst.instruction |= inst.operands[2].reg << 12;
4781 inst.instruction |= inst.operands[3].reg << 16;
4782 inst.instruction |= inst.operands[4].reg;
4783 inst.instruction |= inst.operands[5].imm << 5;
4786 /* Transfer between coprocessor register and pair of ARM registers.
4787 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4792 Two XScale instructions are special cases of these:
4794 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4795 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4797 Result unpredicatable if Rd or Rn is R15. */
4802 inst.instruction |= inst.operands[0].reg << 8;
4803 inst.instruction |= inst.operands[1].imm << 4;
4804 inst.instruction |= inst.operands[2].reg << 12;
4805 inst.instruction |= inst.operands[3].reg << 16;
4806 inst.instruction |= inst.operands[4].reg;
4812 inst.instruction |= inst.operands[0].imm << 6;
4813 inst.instruction |= inst.operands[1].imm;
4819 /* There is no IT instruction in ARM mode. We
4820 process it but do not generate code for it. */
4827 int base_reg = inst.operands[0].reg;
4828 int range = inst.operands[1].imm;
4830 inst.instruction |= base_reg << 16;
4831 inst.instruction |= range;
4833 if (inst.operands[1].writeback)
4834 inst.instruction |= LDM_TYPE_2_OR_3;
4836 if (inst.operands[0].writeback)
4838 inst.instruction |= WRITE_BACK;
4839 /* Check for unpredictable uses of writeback. */
4840 if (inst.instruction & LOAD_BIT)
4842 /* Not allowed in LDM type 2. */
4843 if ((inst.instruction & LDM_TYPE_2_OR_3)
4844 && ((range & (1 << REG_PC)) == 0))
4845 as_warn (_("writeback of base register is UNPREDICTABLE"));
4846 /* Only allowed if base reg not in list for other types. */
4847 else if (range & (1 << base_reg))
4848 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4852 /* Not allowed for type 2. */
4853 if (inst.instruction & LDM_TYPE_2_OR_3)
4854 as_warn (_("writeback of base register is UNPREDICTABLE"));
4855 /* Only allowed if base reg not in list, or first in list. */
4856 else if ((range & (1 << base_reg))
4857 && (range & ((1 << base_reg) - 1)))
4858 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4863 /* ARMv5TE load-consecutive (argument parse)
4872 constraint (inst.operands[0].reg % 2 != 0,
4873 _("first destination register must be even"));
4874 constraint (inst.operands[1].present
4875 && inst.operands[1].reg != inst.operands[0].reg + 1,
4876 _("can only load two consecutive registers"));
4877 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4878 constraint (!inst.operands[2].isreg, _("'[' expected"));
4880 if (!inst.operands[1].present)
4881 inst.operands[1].reg = inst.operands[0].reg + 1;
4883 if (inst.instruction & LOAD_BIT)
4885 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4886 register and the first register written; we have to diagnose
4887 overlap between the base and the second register written here. */
4889 if (inst.operands[2].reg == inst.operands[1].reg
4890 && (inst.operands[2].writeback || inst.operands[2].postind))
4891 as_warn (_("base register written back, and overlaps "
4892 "second destination register"));
4894 /* For an index-register load, the index register must not overlap the
4895 destination (even if not write-back). */
4896 else if (inst.operands[2].immisreg
4897 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4898 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4899 as_warn (_("index register overlaps destination register"));
4902 inst.instruction |= inst.operands[0].reg << 12;
4903 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4909 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4910 || inst.operands[1].postind || inst.operands[1].writeback
4911 || inst.operands[1].immisreg || inst.operands[1].shifted
4912 || inst.operands[1].negative
4913 /* This can arise if the programmer has written
4915 or if they have mistakenly used a register name as the last
4918 It is very difficult to distinguish between these two cases
4919 because "rX" might actually be a label. ie the register
4920 name has been occluded by a symbol of the same name. So we
4921 just generate a general 'bad addressing mode' type error
4922 message and leave it up to the programmer to discover the
4923 true cause and fix their mistake. */
4924 || (inst.operands[1].reg == REG_PC),
4927 constraint (inst.reloc.exp.X_op != O_constant
4928 || inst.reloc.exp.X_add_number != 0,
4929 _("offset must be zero in ARM encoding"));
4931 inst.instruction |= inst.operands[0].reg << 12;
4932 inst.instruction |= inst.operands[1].reg << 16;
4933 inst.reloc.type = BFD_RELOC_UNUSED;
4939 constraint (inst.operands[0].reg % 2 != 0,
4940 _("even register required"));
4941 constraint (inst.operands[1].present
4942 && inst.operands[1].reg != inst.operands[0].reg + 1,
4943 _("can only load two consecutive registers"));
4944 /* If op 1 were present and equal to PC, this function wouldn't
4945 have been called in the first place. */
4946 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4948 inst.instruction |= inst.operands[0].reg << 12;
4949 inst.instruction |= inst.operands[2].reg << 16;
4955 inst.instruction |= inst.operands[0].reg << 12;
4956 if (!inst.operands[1].isreg)
4957 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4959 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4965 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4967 if (inst.operands[1].preind)
4969 constraint (inst.reloc.exp.X_op != O_constant ||
4970 inst.reloc.exp.X_add_number != 0,
4971 _("this instruction requires a post-indexed address"));
4973 inst.operands[1].preind = 0;
4974 inst.operands[1].postind = 1;
4975 inst.operands[1].writeback = 1;
4977 inst.instruction |= inst.operands[0].reg << 12;
4978 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4981 /* Halfword and signed-byte load/store operations. */
4986 inst.instruction |= inst.operands[0].reg << 12;
4987 if (!inst.operands[1].isreg)
4988 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4990 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4996 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4998 if (inst.operands[1].preind)
5000 constraint (inst.reloc.exp.X_op != O_constant ||
5001 inst.reloc.exp.X_add_number != 0,
5002 _("this instruction requires a post-indexed address"));
5004 inst.operands[1].preind = 0;
5005 inst.operands[1].postind = 1;
5006 inst.operands[1].writeback = 1;
5008 inst.instruction |= inst.operands[0].reg << 12;
5009 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
5012 /* Co-processor register load/store.
5013 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
5017 inst.instruction |= inst.operands[0].reg << 8;
5018 inst.instruction |= inst.operands[1].reg << 12;
5019 encode_arm_cp_address (2, TRUE, TRUE, 0);
5025 /* This restriction does not apply to mls (nor to mla in v6, but
5026 that's hard to detect at present). */
5027 if (inst.operands[0].reg == inst.operands[1].reg
5028 && !(inst.instruction & 0x00400000))
5029 as_tsktsk (_("rd and rm should be different in mla"));
5031 inst.instruction |= inst.operands[0].reg << 16;
5032 inst.instruction |= inst.operands[1].reg;
5033 inst.instruction |= inst.operands[2].reg << 8;
5034 inst.instruction |= inst.operands[3].reg << 12;
5041 inst.instruction |= inst.operands[0].reg << 12;
5042 encode_arm_shifter_operand (1);
5045 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
5049 inst.instruction |= inst.operands[0].reg << 12;
5050 /* The value is in two pieces: 0:11, 16:19. */
5051 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
5052 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
5058 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
5059 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
5061 _("'CPSR' or 'SPSR' expected"));
5062 inst.instruction |= inst.operands[0].reg << 12;
5063 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
5066 /* Two possible forms:
5067 "{C|S}PSR_<field>, Rm",
5068 "{C|S}PSR_f, #expression". */
5073 inst.instruction |= inst.operands[0].imm;
5074 if (inst.operands[1].isreg)
5075 inst.instruction |= inst.operands[1].reg;
5078 inst.instruction |= INST_IMMEDIATE;
5079 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5080 inst.reloc.pc_rel = 0;
5087 if (!inst.operands[2].present)
5088 inst.operands[2].reg = inst.operands[0].reg;
5089 inst.instruction |= inst.operands[0].reg << 16;
5090 inst.instruction |= inst.operands[1].reg;
5091 inst.instruction |= inst.operands[2].reg << 8;
5093 if (inst.operands[0].reg == inst.operands[1].reg)
5094 as_tsktsk (_("rd and rm should be different in mul"));
5097 /* Long Multiply Parser
5098 UMULL RdLo, RdHi, Rm, Rs
5099 SMULL RdLo, RdHi, Rm, Rs
5100 UMLAL RdLo, RdHi, Rm, Rs
5101 SMLAL RdLo, RdHi, Rm, Rs. */
5106 inst.instruction |= inst.operands[0].reg << 12;
5107 inst.instruction |= inst.operands[1].reg << 16;
5108 inst.instruction |= inst.operands[2].reg;
5109 inst.instruction |= inst.operands[3].reg << 8;
5111 /* rdhi, rdlo and rm must all be different. */
5112 if (inst.operands[0].reg == inst.operands[1].reg
5113 || inst.operands[0].reg == inst.operands[2].reg
5114 || inst.operands[1].reg == inst.operands[2].reg)
5115 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
5121 if (inst.operands[0].present)
5123 /* Architectural NOP hints are CPSR sets with no bits selected. */
5124 inst.instruction &= 0xf0000000;
5125 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
5129 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
5130 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
5131 Condition defaults to COND_ALWAYS.
5132 Error if Rd, Rn or Rm are R15. */
5137 inst.instruction |= inst.operands[0].reg << 12;
5138 inst.instruction |= inst.operands[1].reg << 16;
5139 inst.instruction |= inst.operands[2].reg;
5140 if (inst.operands[3].present)
5141 encode_arm_shift (3);
5144 /* ARM V6 PKHTB (Argument Parse). */
5149 if (!inst.operands[3].present)
5151 /* If the shift specifier is omitted, turn the instruction
5152 into pkhbt rd, rm, rn. */
5153 inst.instruction &= 0xfff00010;
5154 inst.instruction |= inst.operands[0].reg << 12;
5155 inst.instruction |= inst.operands[1].reg;
5156 inst.instruction |= inst.operands[2].reg << 16;
5160 inst.instruction |= inst.operands[0].reg << 12;
5161 inst.instruction |= inst.operands[1].reg << 16;
5162 inst.instruction |= inst.operands[2].reg;
5163 encode_arm_shift (3);
5167 /* ARMv5TE: Preload-Cache
5171 Syntactically, like LDR with B=1, W=0, L=1. */
5176 constraint (!inst.operands[0].isreg,
5177 _("'[' expected after PLD mnemonic"));
5178 constraint (inst.operands[0].postind,
5179 _("post-indexed expression used in preload instruction"));
5180 constraint (inst.operands[0].writeback,
5181 _("writeback used in preload instruction"));
5182 constraint (!inst.operands[0].preind,
5183 _("unindexed addressing used in preload instruction"));
5184 inst.instruction |= inst.operands[0].reg;
5185 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
5191 inst.operands[1] = inst.operands[0];
5192 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
5193 inst.operands[0].isreg = 1;
5194 inst.operands[0].writeback = 1;
5195 inst.operands[0].reg = REG_SP;
5199 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
5200 word at the specified address and the following word
5202 Unconditionally executed.
5203 Error if Rn is R15. */
5208 inst.instruction |= inst.operands[0].reg << 16;
5209 if (inst.operands[0].writeback)
5210 inst.instruction |= WRITE_BACK;
5213 /* ARM V6 ssat (argument parse). */
5218 inst.instruction |= inst.operands[0].reg << 12;
5219 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5220 inst.instruction |= inst.operands[2].reg;
5222 if (inst.operands[3].present)
5223 encode_arm_shift (3);
5226 /* ARM V6 usat (argument parse). */
5231 inst.instruction |= inst.operands[0].reg << 12;
5232 inst.instruction |= inst.operands[1].imm << 16;
5233 inst.instruction |= inst.operands[2].reg;
5235 if (inst.operands[3].present)
5236 encode_arm_shift (3);
5239 /* ARM V6 ssat16 (argument parse). */
5244 inst.instruction |= inst.operands[0].reg << 12;
5245 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5246 inst.instruction |= inst.operands[2].reg;
5252 inst.instruction |= inst.operands[0].reg << 12;
5253 inst.instruction |= inst.operands[1].imm << 16;
5254 inst.instruction |= inst.operands[2].reg;
5257 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5258 preserving the other bits.
5260 setend <endian_specifier>, where <endian_specifier> is either
5266 if (inst.operands[0].imm)
5267 inst.instruction |= 0x200;
5273 unsigned int Rm = (inst.operands[1].present
5274 ? inst.operands[1].reg
5275 : inst.operands[0].reg);
5277 inst.instruction |= inst.operands[0].reg << 12;
5278 inst.instruction |= Rm;
5279 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5281 constraint (inst.operands[0].reg != Rm,
5282 _("source1 and dest must be same register"));
5283 inst.instruction |= inst.operands[2].reg << 8;
5284 inst.instruction |= SHIFT_BY_REG;
5287 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5293 inst.reloc.type = BFD_RELOC_ARM_SMC;
5294 inst.reloc.pc_rel = 0;
5300 inst.reloc.type = BFD_RELOC_ARM_SWI;
5301 inst.reloc.pc_rel = 0;
5304 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5305 SMLAxy{cond} Rd,Rm,Rs,Rn
5306 SMLAWy{cond} Rd,Rm,Rs,Rn
5307 Error if any register is R15. */
5312 inst.instruction |= inst.operands[0].reg << 16;
5313 inst.instruction |= inst.operands[1].reg;
5314 inst.instruction |= inst.operands[2].reg << 8;
5315 inst.instruction |= inst.operands[3].reg << 12;
5318 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5319 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5320 Error if any register is R15.
5321 Warning if Rdlo == Rdhi. */
5326 inst.instruction |= inst.operands[0].reg << 12;
5327 inst.instruction |= inst.operands[1].reg << 16;
5328 inst.instruction |= inst.operands[2].reg;
5329 inst.instruction |= inst.operands[3].reg << 8;
5331 if (inst.operands[0].reg == inst.operands[1].reg)
5332 as_tsktsk (_("rdhi and rdlo must be different"));
5335 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5336 SMULxy{cond} Rd,Rm,Rs
5337 Error if any register is R15. */
5342 inst.instruction |= inst.operands[0].reg << 16;
5343 inst.instruction |= inst.operands[1].reg;
5344 inst.instruction |= inst.operands[2].reg << 8;
5347 /* ARM V6 srs (argument parse). */
5352 inst.instruction |= inst.operands[0].imm;
5353 if (inst.operands[0].writeback)
5354 inst.instruction |= WRITE_BACK;
5357 /* ARM V6 strex (argument parse). */
5362 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5363 || inst.operands[2].postind || inst.operands[2].writeback
5364 || inst.operands[2].immisreg || inst.operands[2].shifted
5365 || inst.operands[2].negative
5366 /* See comment in do_ldrex(). */
5367 || (inst.operands[2].reg == REG_PC),
5370 constraint (inst.operands[0].reg == inst.operands[1].reg
5371 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5373 constraint (inst.reloc.exp.X_op != O_constant
5374 || inst.reloc.exp.X_add_number != 0,
5375 _("offset must be zero in ARM encoding"));
5377 inst.instruction |= inst.operands[0].reg << 12;
5378 inst.instruction |= inst.operands[1].reg;
5379 inst.instruction |= inst.operands[2].reg << 16;
5380 inst.reloc.type = BFD_RELOC_UNUSED;
5386 constraint (inst.operands[1].reg % 2 != 0,
5387 _("even register required"));
5388 constraint (inst.operands[2].present
5389 && inst.operands[2].reg != inst.operands[1].reg + 1,
5390 _("can only store two consecutive registers"));
5391 /* If op 2 were present and equal to PC, this function wouldn't
5392 have been called in the first place. */
5393 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5395 constraint (inst.operands[0].reg == inst.operands[1].reg
5396 || inst.operands[0].reg == inst.operands[1].reg + 1
5397 || inst.operands[0].reg == inst.operands[3].reg,
5400 inst.instruction |= inst.operands[0].reg << 12;
5401 inst.instruction |= inst.operands[1].reg;
5402 inst.instruction |= inst.operands[3].reg << 16;
5405 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5406 extends it to 32-bits, and adds the result to a value in another
5407 register. You can specify a rotation by 0, 8, 16, or 24 bits
5408 before extracting the 16-bit value.
5409 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5410 Condition defaults to COND_ALWAYS.
5411 Error if any register uses R15. */
5416 inst.instruction |= inst.operands[0].reg << 12;
5417 inst.instruction |= inst.operands[1].reg << 16;
5418 inst.instruction |= inst.operands[2].reg;
5419 inst.instruction |= inst.operands[3].imm << 10;
5424 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5425 Condition defaults to COND_ALWAYS.
5426 Error if any register uses R15. */
5431 inst.instruction |= inst.operands[0].reg << 12;
5432 inst.instruction |= inst.operands[1].reg;
5433 inst.instruction |= inst.operands[2].imm << 10;
5436 /* VFP instructions. In a logical order: SP variant first, monad
5437 before dyad, arithmetic then move then load/store. */
5440 do_vfp_sp_monadic (void)
5442 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5443 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5447 do_vfp_sp_dyadic (void)
5449 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5450 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5451 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5455 do_vfp_sp_compare_z (void)
5457 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5461 do_vfp_dp_sp_cvt (void)
5463 inst.instruction |= inst.operands[0].reg << 12;
5464 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5468 do_vfp_sp_dp_cvt (void)
5470 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5471 inst.instruction |= inst.operands[1].reg;
5475 do_vfp_reg_from_sp (void)
5477 inst.instruction |= inst.operands[0].reg << 12;
5478 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5482 do_vfp_reg2_from_sp2 (void)
5484 constraint (inst.operands[2].imm != 2,
5485 _("only two consecutive VFP SP registers allowed here"));
5486 inst.instruction |= inst.operands[0].reg << 12;
5487 inst.instruction |= inst.operands[1].reg << 16;
5488 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5492 do_vfp_sp_from_reg (void)
5494 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5495 inst.instruction |= inst.operands[1].reg << 12;
5499 do_vfp_sp2_from_reg2 (void)
5501 constraint (inst.operands[0].imm != 2,
5502 _("only two consecutive VFP SP registers allowed here"));
5503 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5504 inst.instruction |= inst.operands[1].reg << 12;
5505 inst.instruction |= inst.operands[2].reg << 16;
5509 do_vfp_sp_ldst (void)
5511 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5512 encode_arm_cp_address (1, FALSE, TRUE, 0);
5516 do_vfp_dp_ldst (void)
5518 inst.instruction |= inst.operands[0].reg << 12;
5519 encode_arm_cp_address (1, FALSE, TRUE, 0);
5524 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5526 if (inst.operands[0].writeback)
5527 inst.instruction |= WRITE_BACK;
5529 constraint (ldstm_type != VFP_LDSTMIA,
5530 _("this addressing mode requires base-register writeback"));
5531 inst.instruction |= inst.operands[0].reg << 16;
5532 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5533 inst.instruction |= inst.operands[1].imm;
5537 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5541 if (inst.operands[0].writeback)
5542 inst.instruction |= WRITE_BACK;
5544 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5545 _("this addressing mode requires base-register writeback"));
5547 inst.instruction |= inst.operands[0].reg << 16;
5548 inst.instruction |= inst.operands[1].reg << 12;
5550 count = inst.operands[1].imm << 1;
5551 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5554 inst.instruction |= count;
5558 do_vfp_sp_ldstmia (void)
5560 vfp_sp_ldstm (VFP_LDSTMIA);
5564 do_vfp_sp_ldstmdb (void)
5566 vfp_sp_ldstm (VFP_LDSTMDB);
5570 do_vfp_dp_ldstmia (void)
5572 vfp_dp_ldstm (VFP_LDSTMIA);
5576 do_vfp_dp_ldstmdb (void)
5578 vfp_dp_ldstm (VFP_LDSTMDB);
5582 do_vfp_xp_ldstmia (void)
5584 vfp_dp_ldstm (VFP_LDSTMIAX);
5588 do_vfp_xp_ldstmdb (void)
5590 vfp_dp_ldstm (VFP_LDSTMDBX);
5593 /* FPA instructions. Also in a logical order. */
5598 inst.instruction |= inst.operands[0].reg << 16;
5599 inst.instruction |= inst.operands[1].reg;
5603 do_fpa_ldmstm (void)
5605 inst.instruction |= inst.operands[0].reg << 12;
5606 switch (inst.operands[1].imm)
5608 case 1: inst.instruction |= CP_T_X; break;
5609 case 2: inst.instruction |= CP_T_Y; break;
5610 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5615 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5617 /* The instruction specified "ea" or "fd", so we can only accept
5618 [Rn]{!}. The instruction does not really support stacking or
5619 unstacking, so we have to emulate these by setting appropriate
5620 bits and offsets. */
5621 constraint (inst.reloc.exp.X_op != O_constant
5622 || inst.reloc.exp.X_add_number != 0,
5623 _("this instruction does not support indexing"));
5625 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5626 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5628 if (!(inst.instruction & INDEX_UP))
5629 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5631 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5633 inst.operands[2].preind = 0;
5634 inst.operands[2].postind = 1;
5638 encode_arm_cp_address (2, TRUE, TRUE, 0);
5641 /* iWMMXt instructions: strictly in alphabetical order. */
5644 do_iwmmxt_tandorc (void)
5646 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5650 do_iwmmxt_textrc (void)
5652 inst.instruction |= inst.operands[0].reg << 12;
5653 inst.instruction |= inst.operands[1].imm;
5657 do_iwmmxt_textrm (void)
5659 inst.instruction |= inst.operands[0].reg << 12;
5660 inst.instruction |= inst.operands[1].reg << 16;
5661 inst.instruction |= inst.operands[2].imm;
5665 do_iwmmxt_tinsr (void)
5667 inst.instruction |= inst.operands[0].reg << 16;
5668 inst.instruction |= inst.operands[1].reg << 12;
5669 inst.instruction |= inst.operands[2].imm;
5673 do_iwmmxt_tmia (void)
5675 inst.instruction |= inst.operands[0].reg << 5;
5676 inst.instruction |= inst.operands[1].reg;
5677 inst.instruction |= inst.operands[2].reg << 12;
5681 do_iwmmxt_waligni (void)
5683 inst.instruction |= inst.operands[0].reg << 12;
5684 inst.instruction |= inst.operands[1].reg << 16;
5685 inst.instruction |= inst.operands[2].reg;
5686 inst.instruction |= inst.operands[3].imm << 20;
5690 do_iwmmxt_wmov (void)
5692 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5693 inst.instruction |= inst.operands[0].reg << 12;
5694 inst.instruction |= inst.operands[1].reg << 16;
5695 inst.instruction |= inst.operands[1].reg;
5699 do_iwmmxt_wldstbh (void)
5702 inst.instruction |= inst.operands[0].reg << 12;
5703 inst.reloc.exp.X_add_number *= 4;
5705 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
5707 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
5708 encode_arm_cp_address (1, TRUE, FALSE, reloc);
5712 do_iwmmxt_wldstw (void)
5714 /* RIWR_RIWC clears .isreg for a control register. */
5715 if (!inst.operands[0].isreg)
5717 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5718 inst.instruction |= 0xf0000000;
5721 inst.instruction |= inst.operands[0].reg << 12;
5722 encode_arm_cp_address (1, TRUE, TRUE, 0);
5726 do_iwmmxt_wldstd (void)
5728 inst.instruction |= inst.operands[0].reg << 12;
5729 encode_arm_cp_address (1, TRUE, FALSE, 0);
5733 do_iwmmxt_wshufh (void)
5735 inst.instruction |= inst.operands[0].reg << 12;
5736 inst.instruction |= inst.operands[1].reg << 16;
5737 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5738 inst.instruction |= (inst.operands[2].imm & 0x0f);
5742 do_iwmmxt_wzero (void)
5744 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5745 inst.instruction |= inst.operands[0].reg;
5746 inst.instruction |= inst.operands[0].reg << 12;
5747 inst.instruction |= inst.operands[0].reg << 16;
5750 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5751 operations first, then control, shift, and load/store. */
5753 /* Insns like "foo X,Y,Z". */
5756 do_mav_triple (void)
5758 inst.instruction |= inst.operands[0].reg << 16;
5759 inst.instruction |= inst.operands[1].reg;
5760 inst.instruction |= inst.operands[2].reg << 12;
5763 /* Insns like "foo W,X,Y,Z".
5764 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5769 inst.instruction |= inst.operands[0].reg << 5;
5770 inst.instruction |= inst.operands[1].reg << 12;
5771 inst.instruction |= inst.operands[2].reg << 16;
5772 inst.instruction |= inst.operands[3].reg;
5775 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5779 inst.instruction |= inst.operands[1].reg << 12;
5782 /* Maverick shift immediate instructions.
5783 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5784 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5789 int imm = inst.operands[2].imm;
5791 inst.instruction |= inst.operands[0].reg << 12;
5792 inst.instruction |= inst.operands[1].reg << 16;
5794 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5795 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5796 Bit 4 should be 0. */
5797 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5799 inst.instruction |= imm;
5802 /* XScale instructions. Also sorted arithmetic before move. */
5804 /* Xscale multiply-accumulate (argument parse)
5807 MIAxycc acc0,Rm,Rs. */
5812 inst.instruction |= inst.operands[1].reg;
5813 inst.instruction |= inst.operands[2].reg << 12;
5816 /* Xscale move-accumulator-register (argument parse)
5818 MARcc acc0,RdLo,RdHi. */
5823 inst.instruction |= inst.operands[1].reg << 12;
5824 inst.instruction |= inst.operands[2].reg << 16;
5827 /* Xscale move-register-accumulator (argument parse)
5829 MRAcc RdLo,RdHi,acc0. */
5834 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5835 inst.instruction |= inst.operands[0].reg << 12;
5836 inst.instruction |= inst.operands[1].reg << 16;
5839 /* Encoding functions relevant only to Thumb. */
5841 /* inst.operands[i] is a shifted-register operand; encode
5842 it into inst.instruction in the format used by Thumb32. */
5845 encode_thumb32_shifted_operand (int i)
5847 unsigned int value = inst.reloc.exp.X_add_number;
5848 unsigned int shift = inst.operands[i].shift_kind;
5850 constraint (inst.operands[i].immisreg,
5851 _("shift by register not allowed in thumb mode"));
5852 inst.instruction |= inst.operands[i].reg;
5853 if (shift == SHIFT_RRX)
5854 inst.instruction |= SHIFT_ROR << 4;
5857 constraint (inst.reloc.exp.X_op != O_constant,
5858 _("expression too complex"));
5860 constraint (value > 32
5861 || (value == 32 && (shift == SHIFT_LSL
5862 || shift == SHIFT_ROR)),
5863 _("shift expression is too large"));
5867 else if (value == 32)
5870 inst.instruction |= shift << 4;
5871 inst.instruction |= (value & 0x1c) << 10;
5872 inst.instruction |= (value & 0x03) << 6;
5877 /* inst.operands[i] was set up by parse_address. Encode it into a
5878 Thumb32 format load or store instruction. Reject forms that cannot
5879 be used with such instructions. If is_t is true, reject forms that
5880 cannot be used with a T instruction; if is_d is true, reject forms
5881 that cannot be used with a D instruction. */
5884 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5886 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5888 constraint (!inst.operands[i].isreg,
5889 _("Thumb does not support the ldr =N pseudo-operation"));
5891 inst.instruction |= inst.operands[i].reg << 16;
5892 if (inst.operands[i].immisreg)
5894 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5895 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5896 constraint (inst.operands[i].negative,
5897 _("Thumb does not support negative register indexing"));
5898 constraint (inst.operands[i].postind,
5899 _("Thumb does not support register post-indexing"));
5900 constraint (inst.operands[i].writeback,
5901 _("Thumb does not support register indexing with writeback"));
5902 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5903 _("Thumb supports only LSL in shifted register indexing"));
5905 inst.instruction |= inst.operands[1].imm;
5906 if (inst.operands[i].shifted)
5908 constraint (inst.reloc.exp.X_op != O_constant,
5909 _("expression too complex"));
5910 constraint (inst.reloc.exp.X_add_number < 0
5911 || inst.reloc.exp.X_add_number > 3,
5912 _("shift out of range"));
5913 inst.instruction |= inst.reloc.exp.X_add_number << 4;
5915 inst.reloc.type = BFD_RELOC_UNUSED;
5917 else if (inst.operands[i].preind)
5919 constraint (is_pc && inst.operands[i].writeback,
5920 _("cannot use writeback with PC-relative addressing"));
5921 constraint (is_t && inst.operands[1].writeback,
5922 _("cannot use writeback with this instruction"));
5926 inst.instruction |= 0x01000000;
5927 if (inst.operands[i].writeback)
5928 inst.instruction |= 0x00200000;
5932 inst.instruction |= 0x00000c00;
5933 if (inst.operands[i].writeback)
5934 inst.instruction |= 0x00000100;
5936 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5938 else if (inst.operands[i].postind)
5940 assert (inst.operands[i].writeback);
5941 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5942 constraint (is_t, _("cannot use post-indexing with this instruction"));
5945 inst.instruction |= 0x00200000;
5947 inst.instruction |= 0x00000900;
5948 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5950 else /* unindexed - only for coprocessor */
5951 inst.error = _("instruction does not accept unindexed addressing");
5954 /* Table of Thumb instructions which exist in both 16- and 32-bit
5955 encodings (the latter only in post-V6T2 cores). The index is the
5956 value used in the insns table below. When there is more than one
5957 possible 16-bit encoding for the instruction, this table always
5959 Also contains several pseudo-instructions used during relaxation. */
5960 #define T16_32_TAB \
5961 X(adc, 4140, eb400000), \
5962 X(adcs, 4140, eb500000), \
5963 X(add, 1c00, eb000000), \
5964 X(adds, 1c00, eb100000), \
5965 X(addi, 0000, f1000000), \
5966 X(addis, 0000, f1100000), \
5967 X(add_pc,000f, f20f0000), \
5968 X(add_sp,000d, f10d0000), \
5969 X(adr, 000f, f20f0000), \
5970 X(and, 4000, ea000000), \
5971 X(ands, 4000, ea100000), \
5972 X(asr, 1000, fa40f000), \
5973 X(asrs, 1000, fa50f000), \
5974 X(b, e000, f000b000), \
5975 X(bcond, d000, f0008000), \
5976 X(bic, 4380, ea200000), \
5977 X(bics, 4380, ea300000), \
5978 X(cmn, 42c0, eb100f00), \
5979 X(cmp, 2800, ebb00f00), \
5980 X(cpsie, b660, f3af8400), \
5981 X(cpsid, b670, f3af8600), \
5982 X(cpy, 4600, ea4f0000), \
5983 X(dec_sp,80dd, f1bd0d00), \
5984 X(eor, 4040, ea800000), \
5985 X(eors, 4040, ea900000), \
5986 X(inc_sp,00dd, f10d0d00), \
5987 X(ldmia, c800, e8900000), \
5988 X(ldr, 6800, f8500000), \
5989 X(ldrb, 7800, f8100000), \
5990 X(ldrh, 8800, f8300000), \
5991 X(ldrsb, 5600, f9100000), \
5992 X(ldrsh, 5e00, f9300000), \
5993 X(ldr_pc,4800, f85f0000), \
5994 X(ldr_pc2,4800, f85f0000), \
5995 X(ldr_sp,9800, f85d0000), \
5996 X(lsl, 0000, fa00f000), \
5997 X(lsls, 0000, fa10f000), \
5998 X(lsr, 0800, fa20f000), \
5999 X(lsrs, 0800, fa30f000), \
6000 X(mov, 2000, ea4f0000), \
6001 X(movs, 2000, ea5f0000), \
6002 X(mul, 4340, fb00f000), \
6003 X(muls, 4340, ffffffff), /* no 32b muls */ \
6004 X(mvn, 43c0, ea6f0000), \
6005 X(mvns, 43c0, ea7f0000), \
6006 X(neg, 4240, f1c00000), /* rsb #0 */ \
6007 X(negs, 4240, f1d00000), /* rsbs #0 */ \
6008 X(orr, 4300, ea400000), \
6009 X(orrs, 4300, ea500000), \
6010 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
6011 X(push, b400, e92d0000), /* stmdb sp!,... */ \
6012 X(rev, ba00, fa90f080), \
6013 X(rev16, ba40, fa90f090), \
6014 X(revsh, bac0, fa90f0b0), \
6015 X(ror, 41c0, fa60f000), \
6016 X(rors, 41c0, fa70f000), \
6017 X(sbc, 4180, eb600000), \
6018 X(sbcs, 4180, eb700000), \
6019 X(stmia, c000, e8800000), \
6020 X(str, 6000, f8400000), \
6021 X(strb, 7000, f8000000), \
6022 X(strh, 8000, f8200000), \
6023 X(str_sp,9000, f84d0000), \
6024 X(sub, 1e00, eba00000), \
6025 X(subs, 1e00, ebb00000), \
6026 X(subi, 8000, f1a00000), \
6027 X(subis, 8000, f1b00000), \
6028 X(sxtb, b240, fa4ff080), \
6029 X(sxth, b200, fa0ff080), \
6030 X(tst, 4200, ea100f00), \
6031 X(uxtb, b2c0, fa5ff080), \
6032 X(uxth, b280, fa1ff080), \
6033 X(nop, bf00, f3af8000), \
6034 X(yield, bf10, f3af8001), \
6035 X(wfe, bf20, f3af8002), \
6036 X(wfi, bf30, f3af8003), \
6037 X(sev, bf40, f3af9004), /* typo, 8004? */
6039 /* To catch errors in encoding functions, the codes are all offset by
6040 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
6041 as 16-bit instructions. */
6042 #define X(a,b,c) T_MNEM_##a
6043 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
6046 #define X(a,b,c) 0x##b
6047 static const unsigned short thumb_op16[] = { T16_32_TAB };
6048 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
6051 #define X(a,b,c) 0x##c
6052 static const unsigned int thumb_op32[] = { T16_32_TAB };
6053 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
6054 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
6058 /* Thumb instruction encoders, in alphabetical order. */
6062 do_t_add_sub_w (void)
6066 Rd = inst.operands[0].reg;
6067 Rn = inst.operands[1].reg;
6069 constraint (Rd == 15, _("PC not allowed as destination"));
6070 inst.instruction |= (Rn << 16) | (Rd << 8);
6071 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
6074 /* Parse an add or subtract instruction. We get here with inst.instruction
6075 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
6082 Rd = inst.operands[0].reg;
6083 Rs = (inst.operands[1].present
6084 ? inst.operands[1].reg /* Rd, Rs, foo */
6085 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6093 flags = (inst.instruction == T_MNEM_adds
6094 || inst.instruction == T_MNEM_subs);
6096 narrow = (current_it_mask == 0);
6098 narrow = (current_it_mask != 0);
6099 if (!inst.operands[2].isreg)
6102 if (inst.size_req != 4)
6106 add = (inst.instruction == T_MNEM_add
6107 || inst.instruction == T_MNEM_adds);
6108 /* Attempt to use a narrow opcode, with relaxation if
6110 if (Rd == REG_SP && Rs == REG_SP && !flags)
6111 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
6112 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
6113 opcode = T_MNEM_add_sp;
6114 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
6115 opcode = T_MNEM_add_pc;
6116 else if (Rd <= 7 && Rs <= 7 && narrow)
6119 opcode = add ? T_MNEM_addis : T_MNEM_subis;
6121 opcode = add ? T_MNEM_addi : T_MNEM_subi;
6125 inst.instruction = THUMB_OP16(opcode);
6126 inst.instruction |= (Rd << 4) | Rs;
6127 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6128 if (inst.size_req != 2)
6129 inst.relax = opcode;
6132 constraint (inst.size_req == 2, BAD_HIREG);
6134 if (inst.size_req == 4
6135 || (inst.size_req != 2 && !opcode))
6137 /* ??? Convert large immediates to addw/subw. */
6138 inst.instruction = THUMB_OP32 (inst.instruction);
6139 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6140 inst.instruction |= inst.operands[0].reg << 8;
6141 inst.instruction |= inst.operands[1].reg << 16;
6142 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6147 Rn = inst.operands[2].reg;
6148 /* See if we can do this with a 16-bit instruction. */
6149 if (!inst.operands[2].shifted && inst.size_req != 4)
6151 if (Rd > 7 || Rs > 7 || Rn > 7)
6156 inst.instruction = ((inst.instruction == T_MNEM_adds
6157 || inst.instruction == T_MNEM_add)
6160 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6164 if (inst.instruction == T_MNEM_add)
6168 inst.instruction = T_OPCODE_ADD_HI;
6169 inst.instruction |= (Rd & 8) << 4;
6170 inst.instruction |= (Rd & 7);
6171 inst.instruction |= Rn << 3;
6174 /* ... because addition is commutative! */
6177 inst.instruction = T_OPCODE_ADD_HI;
6178 inst.instruction |= (Rd & 8) << 4;
6179 inst.instruction |= (Rd & 7);
6180 inst.instruction |= Rs << 3;
6185 /* If we get here, it can't be done in 16 bits. */
6186 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
6187 _("shift must be constant"));
6188 inst.instruction = THUMB_OP32 (inst.instruction);
6189 inst.instruction |= Rd << 8;
6190 inst.instruction |= Rs << 16;
6191 encode_thumb32_shifted_operand (2);
6196 constraint (inst.instruction == T_MNEM_adds
6197 || inst.instruction == T_MNEM_subs,
6200 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
6202 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
6203 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
6206 inst.instruction = (inst.instruction == T_MNEM_add
6208 inst.instruction |= (Rd << 4) | Rs;
6209 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6213 Rn = inst.operands[2].reg;
6214 constraint (inst.operands[2].shifted, _("unshifted register required"));
6216 /* We now have Rd, Rs, and Rn set to registers. */
6217 if (Rd > 7 || Rs > 7 || Rn > 7)
6219 /* Can't do this for SUB. */
6220 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
6221 inst.instruction = T_OPCODE_ADD_HI;
6222 inst.instruction |= (Rd & 8) << 4;
6223 inst.instruction |= (Rd & 7);
6225 inst.instruction |= Rn << 3;
6227 inst.instruction |= Rs << 3;
6229 constraint (1, _("dest must overlap one source register"));
6233 inst.instruction = (inst.instruction == T_MNEM_add
6234 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
6235 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
6243 if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
6245 /* Defer to section relaxation. */
6246 inst.relax = inst.instruction;
6247 inst.instruction = THUMB_OP16 (inst.instruction);
6248 inst.instruction |= inst.operands[0].reg << 4;
6250 else if (unified_syntax && inst.size_req != 2)
6252 /* Generate a 32-bit opcode. */
6253 inst.instruction = THUMB_OP32 (inst.instruction);
6254 inst.instruction |= inst.operands[0].reg << 8;
6255 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
6256 inst.reloc.pc_rel = 1;
6260 /* Generate a 16-bit opcode. */
6261 inst.instruction = THUMB_OP16 (inst.instruction);
6262 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
6263 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
6264 inst.reloc.pc_rel = 1;
6266 inst.instruction |= inst.operands[0].reg << 4;
6270 /* Arithmetic instructions for which there is just one 16-bit
6271 instruction encoding, and it allows only two low registers.
6272 For maximal compatibility with ARM syntax, we allow three register
6273 operands even when Thumb-32 instructions are not available, as long
6274 as the first two are identical. For instance, both "sbc r0,r1" and
6275 "sbc r0,r0,r1" are allowed. */
6281 Rd = inst.operands[0].reg;
6282 Rs = (inst.operands[1].present
6283 ? inst.operands[1].reg /* Rd, Rs, foo */
6284 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6285 Rn = inst.operands[2].reg;
6289 if (!inst.operands[2].isreg)
6291 /* For an immediate, we always generate a 32-bit opcode;
6292 section relaxation will shrink it later if possible. */
6293 inst.instruction = THUMB_OP32 (inst.instruction);
6294 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6295 inst.instruction |= Rd << 8;
6296 inst.instruction |= Rs << 16;
6297 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6303 /* See if we can do this with a 16-bit instruction. */
6304 if (THUMB_SETS_FLAGS (inst.instruction))
6305 narrow = current_it_mask == 0;
6307 narrow = current_it_mask != 0;
6309 if (Rd > 7 || Rn > 7 || Rs > 7)
6311 if (inst.operands[2].shifted)
6313 if (inst.size_req == 4)
6319 inst.instruction = THUMB_OP16 (inst.instruction);
6320 inst.instruction |= Rd;
6321 inst.instruction |= Rn << 3;
6325 /* If we get here, it can't be done in 16 bits. */
6326 constraint (inst.operands[2].shifted
6327 && inst.operands[2].immisreg,
6328 _("shift must be constant"));
6329 inst.instruction = THUMB_OP32 (inst.instruction);
6330 inst.instruction |= Rd << 8;
6331 inst.instruction |= Rs << 16;
6332 encode_thumb32_shifted_operand (2);
6337 /* On its face this is a lie - the instruction does set the
6338 flags. However, the only supported mnemonic in this mode
6340 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6342 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6343 _("unshifted register required"));
6344 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6345 constraint (Rd != Rs,
6346 _("dest and source1 must be the same register"));
6348 inst.instruction = THUMB_OP16 (inst.instruction);
6349 inst.instruction |= Rd;
6350 inst.instruction |= Rn << 3;
6354 /* Similarly, but for instructions where the arithmetic operation is
6355 commutative, so we can allow either of them to be different from
6356 the destination operand in a 16-bit instruction. For instance, all
6357 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6364 Rd = inst.operands[0].reg;
6365 Rs = (inst.operands[1].present
6366 ? inst.operands[1].reg /* Rd, Rs, foo */
6367 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6368 Rn = inst.operands[2].reg;
6372 if (!inst.operands[2].isreg)
6374 /* For an immediate, we always generate a 32-bit opcode;
6375 section relaxation will shrink it later if possible. */
6376 inst.instruction = THUMB_OP32 (inst.instruction);
6377 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6378 inst.instruction |= Rd << 8;
6379 inst.instruction |= Rs << 16;
6380 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6386 /* See if we can do this with a 16-bit instruction. */
6387 if (THUMB_SETS_FLAGS (inst.instruction))
6388 narrow = current_it_mask == 0;
6390 narrow = current_it_mask != 0;
6392 if (Rd > 7 || Rn > 7 || Rs > 7)
6394 if (inst.operands[2].shifted)
6396 if (inst.size_req == 4)
6403 inst.instruction = THUMB_OP16 (inst.instruction);
6404 inst.instruction |= Rd;
6405 inst.instruction |= Rn << 3;
6410 inst.instruction = THUMB_OP16 (inst.instruction);
6411 inst.instruction |= Rd;
6412 inst.instruction |= Rs << 3;
6417 /* If we get here, it can't be done in 16 bits. */
6418 constraint (inst.operands[2].shifted
6419 && inst.operands[2].immisreg,
6420 _("shift must be constant"));
6421 inst.instruction = THUMB_OP32 (inst.instruction);
6422 inst.instruction |= Rd << 8;
6423 inst.instruction |= Rs << 16;
6424 encode_thumb32_shifted_operand (2);
6429 /* On its face this is a lie - the instruction does set the
6430 flags. However, the only supported mnemonic in this mode
6432 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6434 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6435 _("unshifted register required"));
6436 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6438 inst.instruction = THUMB_OP16 (inst.instruction);
6439 inst.instruction |= Rd;
6442 inst.instruction |= Rn << 3;
6444 inst.instruction |= Rs << 3;
6446 constraint (1, _("dest must overlap one source register"));
6453 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6454 constraint (msb > 32, _("bit-field extends past end of register"));
6455 /* The instruction encoding stores the LSB and MSB,
6456 not the LSB and width. */
6457 inst.instruction |= inst.operands[0].reg << 8;
6458 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6459 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6460 inst.instruction |= msb - 1;
6468 /* #0 in second position is alternative syntax for bfc, which is
6469 the same instruction but with REG_PC in the Rm field. */
6470 if (!inst.operands[1].isreg)
6471 inst.operands[1].reg = REG_PC;
6473 msb = inst.operands[2].imm + inst.operands[3].imm;
6474 constraint (msb > 32, _("bit-field extends past end of register"));
6475 /* The instruction encoding stores the LSB and MSB,
6476 not the LSB and width. */
6477 inst.instruction |= inst.operands[0].reg << 8;
6478 inst.instruction |= inst.operands[1].reg << 16;
6479 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6480 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6481 inst.instruction |= msb - 1;
6487 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6488 _("bit-field extends past end of register"));
6489 inst.instruction |= inst.operands[0].reg << 8;
6490 inst.instruction |= inst.operands[1].reg << 16;
6491 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6492 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6493 inst.instruction |= inst.operands[3].imm - 1;
6496 /* ARM V5 Thumb BLX (argument parse)
6497 BLX <target_addr> which is BLX(1)
6498 BLX <Rm> which is BLX(2)
6499 Unfortunately, there are two different opcodes for this mnemonic.
6500 So, the insns[].value is not used, and the code here zaps values
6501 into inst.instruction.
6503 ??? How to take advantage of the additional two bits of displacement
6504 available in Thumb32 mode? Need new relocation? */
6509 if (inst.operands[0].isreg)
6510 /* We have a register, so this is BLX(2). */
6511 inst.instruction |= inst.operands[0].reg << 3;
6514 /* No register. This must be BLX(1). */
6515 inst.instruction = 0xf000e800;
6517 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
6518 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6521 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6522 inst.reloc.pc_rel = 1;
6530 if (inst.cond != COND_ALWAYS)
6531 opcode = T_MNEM_bcond;
6533 opcode = inst.instruction;
6535 if (unified_syntax && inst.size_req == 4)
6537 inst.instruction = THUMB_OP32(opcode);
6538 if (inst.cond == COND_ALWAYS)
6539 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6542 assert (inst.cond != 0xF);
6543 inst.instruction |= inst.cond << 22;
6544 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6549 inst.instruction = THUMB_OP16(opcode);
6550 if (inst.cond == COND_ALWAYS)
6551 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6554 inst.instruction |= inst.cond << 8;
6555 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6557 /* Allow section relaxation. */
6558 if (unified_syntax && inst.size_req != 2)
6559 inst.relax = opcode;
6562 inst.reloc.pc_rel = 1;
6568 if (inst.operands[0].present)
6570 constraint (inst.operands[0].imm > 255,
6571 _("immediate value out of range"));
6572 inst.instruction |= inst.operands[0].imm;
6577 do_t_branch23 (void)
6579 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6580 inst.reloc.pc_rel = 1;
6582 /* If the destination of the branch is a defined symbol which does not have
6583 the THUMB_FUNC attribute, then we must be calling a function which has
6584 the (interfacearm) attribute. We look for the Thumb entry point to that
6585 function and change the branch to refer to that function instead. */
6586 if ( inst.reloc.exp.X_op == O_symbol
6587 && inst.reloc.exp.X_add_symbol != NULL
6588 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6589 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6590 inst.reloc.exp.X_add_symbol =
6591 find_real_start (inst.reloc.exp.X_add_symbol);
6597 inst.instruction |= inst.operands[0].reg << 3;
6598 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6599 should cause the alignment to be checked once it is known. This is
6600 because BX PC only works if the instruction is word aligned. */
6606 if (inst.operands[0].reg == REG_PC)
6607 as_tsktsk (_("use of r15 in bxj is not really useful"));
6609 inst.instruction |= inst.operands[0].reg << 16;
6615 inst.instruction |= inst.operands[0].reg << 8;
6616 inst.instruction |= inst.operands[1].reg << 16;
6617 inst.instruction |= inst.operands[1].reg;
6624 && (inst.operands[1].present || inst.size_req == 4))
6626 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6627 inst.instruction = 0xf3af8000;
6628 inst.instruction |= imod << 9;
6629 inst.instruction |= inst.operands[0].imm << 5;
6630 if (inst.operands[1].present)
6631 inst.instruction |= 0x100 | inst.operands[1].imm;
6635 constraint (inst.operands[1].present,
6636 _("Thumb does not support the 2-argument "
6637 "form of this instruction"));
6638 inst.instruction |= inst.operands[0].imm;
6642 /* THUMB CPY instruction (argument parse). */
6647 if (inst.size_req == 4)
6649 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6650 inst.instruction |= inst.operands[0].reg << 8;
6651 inst.instruction |= inst.operands[1].reg;
6655 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6656 inst.instruction |= (inst.operands[0].reg & 0x7);
6657 inst.instruction |= inst.operands[1].reg << 3;
6664 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6665 inst.instruction |= inst.operands[0].reg;
6666 inst.reloc.pc_rel = 1;
6667 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6673 if (unified_syntax && inst.size_req == 4)
6674 inst.instruction = THUMB_OP32 (inst.instruction);
6676 inst.instruction = THUMB_OP16 (inst.instruction);
6682 unsigned int cond = inst.operands[0].imm;
6684 current_it_mask = (inst.instruction & 0xf) | 0x10;
6687 /* If the condition is a negative condition, invert the mask. */
6688 if ((cond & 0x1) == 0x0)
6690 unsigned int mask = inst.instruction & 0x000f;
6692 if ((mask & 0x7) == 0)
6693 /* no conversion needed */;
6694 else if ((mask & 0x3) == 0)
6696 else if ((mask & 0x1) == 0)
6701 inst.instruction &= 0xfff0;
6702 inst.instruction |= mask;
6705 inst.instruction |= cond << 4;
6711 /* This really doesn't seem worth it. */
6712 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6713 _("expression too complex"));
6714 constraint (inst.operands[1].writeback,
6715 _("Thumb load/store multiple does not support {reglist}^"));
6719 /* See if we can use a 16-bit instruction. */
6720 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6721 && inst.size_req != 4
6722 && inst.operands[0].reg <= 7
6723 && !(inst.operands[1].imm & ~0xff)
6724 && (inst.instruction == T_MNEM_stmia
6725 ? inst.operands[0].writeback
6726 : (inst.operands[0].writeback
6727 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6729 if (inst.instruction == T_MNEM_stmia
6730 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6731 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6732 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6733 inst.operands[0].reg);
6735 inst.instruction = THUMB_OP16 (inst.instruction);
6736 inst.instruction |= inst.operands[0].reg << 8;
6737 inst.instruction |= inst.operands[1].imm;
6741 if (inst.operands[1].imm & (1 << 13))
6742 as_warn (_("SP should not be in register list"));
6743 if (inst.instruction == T_MNEM_stmia)
6745 if (inst.operands[1].imm & (1 << 15))
6746 as_warn (_("PC should not be in register list"));
6747 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6748 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6749 inst.operands[0].reg);
6753 if (inst.operands[1].imm & (1 << 14)
6754 && inst.operands[1].imm & (1 << 15))
6755 as_warn (_("LR and PC should not both be in register list"));
6756 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6757 && inst.operands[0].writeback)
6758 as_warn (_("base register should not be in register list "
6759 "when written back"));
6761 if (inst.instruction < 0xffff)
6762 inst.instruction = THUMB_OP32 (inst.instruction);
6763 inst.instruction |= inst.operands[0].reg << 16;
6764 inst.instruction |= inst.operands[1].imm;
6765 if (inst.operands[0].writeback)
6766 inst.instruction |= WRITE_BACK;
6771 constraint (inst.operands[0].reg > 7
6772 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6773 if (inst.instruction == T_MNEM_stmia)
6775 if (!inst.operands[0].writeback)
6776 as_warn (_("this instruction will write back the base register"));
6777 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6778 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6779 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6780 inst.operands[0].reg);
6784 if (!inst.operands[0].writeback
6785 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6786 as_warn (_("this instruction will write back the base register"));
6787 else if (inst.operands[0].writeback
6788 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6789 as_warn (_("this instruction will not write back the base register"));
6792 inst.instruction = THUMB_OP16 (inst.instruction);
6793 inst.instruction |= inst.operands[0].reg << 8;
6794 inst.instruction |= inst.operands[1].imm;
6801 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6802 || inst.operands[1].postind || inst.operands[1].writeback
6803 || inst.operands[1].immisreg || inst.operands[1].shifted
6804 || inst.operands[1].negative,
6807 inst.instruction |= inst.operands[0].reg << 12;
6808 inst.instruction |= inst.operands[1].reg << 16;
6809 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6815 if (!inst.operands[1].present)
6817 constraint (inst.operands[0].reg == REG_LR,
6818 _("r14 not allowed as first register "
6819 "when second register is omitted"));
6820 inst.operands[1].reg = inst.operands[0].reg + 1;
6822 constraint (inst.operands[0].reg == inst.operands[1].reg,
6825 inst.instruction |= inst.operands[0].reg << 12;
6826 inst.instruction |= inst.operands[1].reg << 8;
6827 inst.instruction |= inst.operands[2].reg << 16;
6833 unsigned long opcode;
6836 opcode = inst.instruction;
6839 if (inst.operands[1].isreg
6840 && !inst.operands[1].writeback
6841 && !inst.operands[1].shifted && !inst.operands[1].postind
6842 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6844 && inst.size_req != 4)
6846 /* Insn may have a 16-bit form. */
6847 Rn = inst.operands[1].reg;
6848 if (inst.operands[1].immisreg)
6850 inst.instruction = THUMB_OP16 (opcode);
6852 if (Rn <= 7 && inst.operands[1].imm <= 7)
6855 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
6856 && opcode != T_MNEM_ldrsb)
6857 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
6858 || (Rn == REG_SP && opcode == T_MNEM_str))
6865 if (inst.reloc.pc_rel)
6866 opcode = T_MNEM_ldr_pc2;
6868 opcode = T_MNEM_ldr_pc;
6872 if (opcode == T_MNEM_ldr)
6873 opcode = T_MNEM_ldr_sp;
6875 opcode = T_MNEM_str_sp;
6877 inst.instruction = inst.operands[0].reg << 8;
6881 inst.instruction = inst.operands[0].reg;
6882 inst.instruction |= inst.operands[1].reg << 3;
6884 inst.instruction |= THUMB_OP16 (opcode);
6885 if (inst.size_req == 2)
6886 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6888 inst.relax = opcode;
6892 /* Definitely a 32-bit variant. */
6893 inst.instruction = THUMB_OP32 (opcode);
6894 inst.instruction |= inst.operands[0].reg << 12;
6895 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6899 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6901 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6903 /* Only [Rn,Rm] is acceptable. */
6904 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6905 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6906 || inst.operands[1].postind || inst.operands[1].shifted
6907 || inst.operands[1].negative,
6908 _("Thumb does not support this addressing mode"));
6909 inst.instruction = THUMB_OP16 (inst.instruction);
6913 inst.instruction = THUMB_OP16 (inst.instruction);
6914 if (!inst.operands[1].isreg)
6915 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6918 constraint (!inst.operands[1].preind
6919 || inst.operands[1].shifted
6920 || inst.operands[1].writeback,
6921 _("Thumb does not support this addressing mode"));
6922 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6924 constraint (inst.instruction & 0x0600,
6925 _("byte or halfword not valid for base register"));
6926 constraint (inst.operands[1].reg == REG_PC
6927 && !(inst.instruction & THUMB_LOAD_BIT),
6928 _("r15 based store not allowed"));
6929 constraint (inst.operands[1].immisreg,
6930 _("invalid base register for register offset"));
6932 if (inst.operands[1].reg == REG_PC)
6933 inst.instruction = T_OPCODE_LDR_PC;
6934 else if (inst.instruction & THUMB_LOAD_BIT)
6935 inst.instruction = T_OPCODE_LDR_SP;
6937 inst.instruction = T_OPCODE_STR_SP;
6939 inst.instruction |= inst.operands[0].reg << 8;
6940 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6944 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6945 if (!inst.operands[1].immisreg)
6947 /* Immediate offset. */
6948 inst.instruction |= inst.operands[0].reg;
6949 inst.instruction |= inst.operands[1].reg << 3;
6950 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6954 /* Register offset. */
6955 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6956 constraint (inst.operands[1].negative,
6957 _("Thumb does not support this addressing mode"));
6960 switch (inst.instruction)
6962 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6963 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6964 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6965 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6966 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6967 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6968 case 0x5600 /* ldrsb */:
6969 case 0x5e00 /* ldrsh */: break;
6973 inst.instruction |= inst.operands[0].reg;
6974 inst.instruction |= inst.operands[1].reg << 3;
6975 inst.instruction |= inst.operands[1].imm << 6;
6981 if (!inst.operands[1].present)
6983 inst.operands[1].reg = inst.operands[0].reg + 1;
6984 constraint (inst.operands[0].reg == REG_LR,
6985 _("r14 not allowed here"));
6987 inst.instruction |= inst.operands[0].reg << 12;
6988 inst.instruction |= inst.operands[1].reg << 8;
6989 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6996 inst.instruction |= inst.operands[0].reg << 12;
6997 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
7003 inst.instruction |= inst.operands[0].reg << 8;
7004 inst.instruction |= inst.operands[1].reg << 16;
7005 inst.instruction |= inst.operands[2].reg;
7006 inst.instruction |= inst.operands[3].reg << 12;
7012 inst.instruction |= inst.operands[0].reg << 12;
7013 inst.instruction |= inst.operands[1].reg << 8;
7014 inst.instruction |= inst.operands[2].reg << 16;
7015 inst.instruction |= inst.operands[3].reg;
7023 int r0off = (inst.instruction == T_MNEM_mov
7024 || inst.instruction == T_MNEM_movs) ? 8 : 16;
7025 unsigned long opcode;
7027 bfd_boolean low_regs;
7029 low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
7030 opcode = inst.instruction;
7031 if (current_it_mask)
7032 narrow = opcode != T_MNEM_movs;
7034 narrow = opcode != T_MNEM_movs || low_regs;
7035 if (inst.size_req == 4
7036 || inst.operands[1].shifted)
7039 if (!inst.operands[1].isreg)
7041 /* Immediate operand. */
7042 if (current_it_mask == 0 && opcode == T_MNEM_mov)
7044 if (low_regs && narrow)
7046 inst.instruction = THUMB_OP16 (opcode);
7047 inst.instruction |= inst.operands[0].reg << 8;
7048 if (inst.size_req == 2)
7049 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7051 inst.relax = opcode;
7055 inst.instruction = THUMB_OP32 (inst.instruction);
7056 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7057 inst.instruction |= inst.operands[0].reg << r0off;
7058 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7063 inst.instruction = THUMB_OP32 (inst.instruction);
7064 inst.instruction |= inst.operands[0].reg << r0off;
7065 encode_thumb32_shifted_operand (1);
7068 switch (inst.instruction)
7071 inst.instruction = T_OPCODE_MOV_HR;
7072 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7073 inst.instruction |= (inst.operands[0].reg & 0x7);
7074 inst.instruction |= inst.operands[1].reg << 3;
7078 /* We know we have low registers at this point.
7079 Generate ADD Rd, Rs, #0. */
7080 inst.instruction = T_OPCODE_ADD_I3;
7081 inst.instruction |= inst.operands[0].reg;
7082 inst.instruction |= inst.operands[1].reg << 3;
7088 inst.instruction = T_OPCODE_CMP_LR;
7089 inst.instruction |= inst.operands[0].reg;
7090 inst.instruction |= inst.operands[1].reg << 3;
7094 inst.instruction = T_OPCODE_CMP_HR;
7095 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
7096 inst.instruction |= (inst.operands[0].reg & 0x7);
7097 inst.instruction |= inst.operands[1].reg << 3;
7104 inst.instruction = THUMB_OP16 (inst.instruction);
7105 if (inst.operands[1].isreg)
7107 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
7109 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
7110 since a MOV instruction produces unpredictable results. */
7111 if (inst.instruction == T_OPCODE_MOV_I8)
7112 inst.instruction = T_OPCODE_ADD_I3;
7114 inst.instruction = T_OPCODE_CMP_LR;
7116 inst.instruction |= inst.operands[0].reg;
7117 inst.instruction |= inst.operands[1].reg << 3;
7121 if (inst.instruction == T_OPCODE_MOV_I8)
7122 inst.instruction = T_OPCODE_MOV_HR;
7124 inst.instruction = T_OPCODE_CMP_HR;
7130 constraint (inst.operands[0].reg > 7,
7131 _("only lo regs allowed with immediate"));
7132 inst.instruction |= inst.operands[0].reg << 8;
7133 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
7140 inst.instruction |= inst.operands[0].reg << 8;
7141 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
7142 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
7143 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
7144 inst.instruction |= (inst.operands[1].imm & 0x00ff);
7152 int r0off = (inst.instruction == T_MNEM_mvn
7153 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
7156 if (inst.size_req == 4
7157 || inst.instruction > 0xffff
7158 || inst.operands[1].shifted
7159 || inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7161 else if (inst.instruction == T_MNEM_cmn)
7163 else if (THUMB_SETS_FLAGS (inst.instruction))
7164 narrow = (current_it_mask == 0);
7166 narrow = (current_it_mask != 0);
7168 if (!inst.operands[1].isreg)
7170 /* For an immediate, we always generate a 32-bit opcode;
7171 section relaxation will shrink it later if possible. */
7172 if (inst.instruction < 0xffff)
7173 inst.instruction = THUMB_OP32 (inst.instruction);
7174 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7175 inst.instruction |= inst.operands[0].reg << r0off;
7176 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7180 /* See if we can do this with a 16-bit instruction. */
7183 inst.instruction = THUMB_OP16 (inst.instruction);
7184 inst.instruction |= inst.operands[0].reg;
7185 inst.instruction |= inst.operands[1].reg << 3;
7189 constraint (inst.operands[1].shifted
7190 && inst.operands[1].immisreg,
7191 _("shift must be constant"));
7192 if (inst.instruction < 0xffff)
7193 inst.instruction = THUMB_OP32 (inst.instruction);
7194 inst.instruction |= inst.operands[0].reg << r0off;
7195 encode_thumb32_shifted_operand (1);
7201 constraint (inst.instruction > 0xffff
7202 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
7203 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
7204 _("unshifted register required"));
7205 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7208 inst.instruction = THUMB_OP16 (inst.instruction);
7209 inst.instruction |= inst.operands[0].reg;
7210 inst.instruction |= inst.operands[1].reg << 3;
7217 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7218 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
7220 _("'CPSR' or 'SPSR' expected"));
7221 inst.instruction |= inst.operands[0].reg << 8;
7222 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
7228 constraint (!inst.operands[1].isreg,
7229 _("Thumb encoding does not support an immediate here"));
7230 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
7231 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
7232 inst.instruction |= inst.operands[1].reg << 16;
7238 if (!inst.operands[2].present)
7239 inst.operands[2].reg = inst.operands[0].reg;
7241 /* There is no 32-bit MULS and no 16-bit MUL. */
7242 if (unified_syntax && inst.instruction == T_MNEM_mul)
7244 inst.instruction = THUMB_OP32 (inst.instruction);
7245 inst.instruction |= inst.operands[0].reg << 8;
7246 inst.instruction |= inst.operands[1].reg << 16;
7247 inst.instruction |= inst.operands[2].reg << 0;
7251 constraint (!unified_syntax
7252 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
7253 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7256 inst.instruction = THUMB_OP16 (inst.instruction);
7257 inst.instruction |= inst.operands[0].reg;
7259 if (inst.operands[0].reg == inst.operands[1].reg)
7260 inst.instruction |= inst.operands[2].reg << 3;
7261 else if (inst.operands[0].reg == inst.operands[2].reg)
7262 inst.instruction |= inst.operands[1].reg << 3;
7264 constraint (1, _("dest must overlap one source register"));
7271 inst.instruction |= inst.operands[0].reg << 12;
7272 inst.instruction |= inst.operands[1].reg << 8;
7273 inst.instruction |= inst.operands[2].reg << 16;
7274 inst.instruction |= inst.operands[3].reg;
7276 if (inst.operands[0].reg == inst.operands[1].reg)
7277 as_tsktsk (_("rdhi and rdlo must be different"));
7285 if (inst.size_req == 4 || inst.operands[0].imm > 15)
7287 inst.instruction = THUMB_OP32 (inst.instruction);
7288 inst.instruction |= inst.operands[0].imm;
7292 inst.instruction = THUMB_OP16 (inst.instruction);
7293 inst.instruction |= inst.operands[0].imm << 4;
7298 constraint (inst.operands[0].present,
7299 _("Thumb does not support NOP with hints"));
7300 inst.instruction = 0x46c0;
7311 if (THUMB_SETS_FLAGS (inst.instruction))
7312 narrow = (current_it_mask == 0);
7314 narrow = (current_it_mask != 0);
7315 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7317 if (inst.size_req == 4)
7322 inst.instruction = THUMB_OP32 (inst.instruction);
7323 inst.instruction |= inst.operands[0].reg << 8;
7324 inst.instruction |= inst.operands[1].reg << 16;
7328 inst.instruction = THUMB_OP16 (inst.instruction);
7329 inst.instruction |= inst.operands[0].reg;
7330 inst.instruction |= inst.operands[1].reg << 3;
7335 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
7337 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7339 inst.instruction = THUMB_OP16 (inst.instruction);
7340 inst.instruction |= inst.operands[0].reg;
7341 inst.instruction |= inst.operands[1].reg << 3;
7348 inst.instruction |= inst.operands[0].reg << 8;
7349 inst.instruction |= inst.operands[1].reg << 16;
7350 inst.instruction |= inst.operands[2].reg;
7351 if (inst.operands[3].present)
7353 unsigned int val = inst.reloc.exp.X_add_number;
7354 constraint (inst.reloc.exp.X_op != O_constant,
7355 _("expression too complex"));
7356 inst.instruction |= (val & 0x1c) << 10;
7357 inst.instruction |= (val & 0x03) << 6;
7364 if (!inst.operands[3].present)
7365 inst.instruction &= ~0x00000020;
7372 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
7376 do_t_push_pop (void)
7380 constraint (inst.operands[0].writeback,
7381 _("push/pop do not support {reglist}^"));
7382 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
7383 _("expression too complex"));
7385 mask = inst.operands[0].imm;
7386 if ((mask & ~0xff) == 0)
7387 inst.instruction = THUMB_OP16 (inst.instruction);
7388 else if ((inst.instruction == T_MNEM_push
7389 && (mask & ~0xff) == 1 << REG_LR)
7390 || (inst.instruction == T_MNEM_pop
7391 && (mask & ~0xff) == 1 << REG_PC))
7393 inst.instruction = THUMB_OP16 (inst.instruction);
7394 inst.instruction |= THUMB_PP_PC_LR;
7397 else if (unified_syntax)
7399 if (mask & (1 << 13))
7400 inst.error = _("SP not allowed in register list");
7401 if (inst.instruction == T_MNEM_push)
7403 if (mask & (1 << 15))
7404 inst.error = _("PC not allowed in register list");
7408 if (mask & (1 << 14)
7409 && mask & (1 << 15))
7410 inst.error = _("LR and PC should not both be in register list");
7412 if ((mask & (mask - 1)) == 0)
7414 /* Single register push/pop implemented as str/ldr. */
7415 if (inst.instruction == T_MNEM_push)
7416 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7418 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7419 mask = ffs(mask) - 1;
7423 inst.instruction = THUMB_OP32 (inst.instruction);
7427 inst.error = _("invalid register list to push/pop instruction");
7431 inst.instruction |= mask;
7437 inst.instruction |= inst.operands[0].reg << 8;
7438 inst.instruction |= inst.operands[1].reg << 16;
7444 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7445 && inst.size_req != 4)
7447 inst.instruction = THUMB_OP16 (inst.instruction);
7448 inst.instruction |= inst.operands[0].reg;
7449 inst.instruction |= inst.operands[1].reg << 3;
7451 else if (unified_syntax)
7453 inst.instruction = THUMB_OP32 (inst.instruction);
7454 inst.instruction |= inst.operands[0].reg << 8;
7455 inst.instruction |= inst.operands[1].reg << 16;
7456 inst.instruction |= inst.operands[1].reg;
7459 inst.error = BAD_HIREG;
7467 Rd = inst.operands[0].reg;
7468 Rs = (inst.operands[1].present
7469 ? inst.operands[1].reg /* Rd, Rs, foo */
7470 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7472 inst.instruction |= Rd << 8;
7473 inst.instruction |= Rs << 16;
7474 if (!inst.operands[2].isreg)
7476 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7477 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7480 encode_thumb32_shifted_operand (2);
7486 if (inst.operands[0].imm)
7487 inst.instruction |= 0x8;
7493 if (!inst.operands[1].present)
7494 inst.operands[1].reg = inst.operands[0].reg;
7501 switch (inst.instruction)
7504 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
7506 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
7508 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
7510 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
7514 if (THUMB_SETS_FLAGS (inst.instruction))
7515 narrow = (current_it_mask == 0);
7517 narrow = (current_it_mask != 0);
7518 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
7520 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
7522 if (inst.operands[2].isreg
7523 && (inst.operands[1].reg != inst.operands[0].reg
7524 || inst.operands[2].reg > 7))
7526 if (inst.size_req == 4)
7531 if (inst.operands[2].isreg)
7533 inst.instruction = THUMB_OP32 (inst.instruction);
7534 inst.instruction |= inst.operands[0].reg << 8;
7535 inst.instruction |= inst.operands[1].reg << 16;
7536 inst.instruction |= inst.operands[2].reg;
7540 inst.operands[1].shifted = 1;
7541 inst.operands[1].shift_kind = shift_kind;
7542 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7543 ? T_MNEM_movs : T_MNEM_mov);
7544 inst.instruction |= inst.operands[0].reg << 8;
7545 encode_thumb32_shifted_operand (1);
7546 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7547 inst.reloc.type = BFD_RELOC_UNUSED;
7552 if (inst.operands[2].isreg)
7556 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
7557 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
7558 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
7559 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
7563 inst.instruction |= inst.operands[0].reg;
7564 inst.instruction |= inst.operands[2].reg << 3;
7570 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
7571 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
7572 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
7575 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7576 inst.instruction |= inst.operands[0].reg;
7577 inst.instruction |= inst.operands[1].reg << 3;
7583 constraint (inst.operands[0].reg > 7
7584 || inst.operands[1].reg > 7, BAD_HIREG);
7585 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7587 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7589 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7590 constraint (inst.operands[0].reg != inst.operands[1].reg,
7591 _("source1 and dest must be same register"));
7593 switch (inst.instruction)
7595 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7596 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7597 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7598 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7602 inst.instruction |= inst.operands[0].reg;
7603 inst.instruction |= inst.operands[2].reg << 3;
7607 switch (inst.instruction)
7609 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7610 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7611 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7612 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7615 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7616 inst.instruction |= inst.operands[0].reg;
7617 inst.instruction |= inst.operands[1].reg << 3;
7625 inst.instruction |= inst.operands[0].reg << 8;
7626 inst.instruction |= inst.operands[1].reg << 16;
7627 inst.instruction |= inst.operands[2].reg;
7633 unsigned int value = inst.reloc.exp.X_add_number;
7634 constraint (inst.reloc.exp.X_op != O_constant,
7635 _("expression too complex"));
7636 inst.reloc.type = BFD_RELOC_UNUSED;
7637 inst.instruction |= (value & 0xf000) >> 12;
7638 inst.instruction |= (value & 0x0ff0);
7639 inst.instruction |= (value & 0x000f) << 16;
7645 inst.instruction |= inst.operands[0].reg << 8;
7646 inst.instruction |= inst.operands[1].imm - 1;
7647 inst.instruction |= inst.operands[2].reg << 16;
7649 if (inst.operands[3].present)
7651 constraint (inst.reloc.exp.X_op != O_constant,
7652 _("expression too complex"));
7654 if (inst.reloc.exp.X_add_number != 0)
7656 if (inst.operands[3].shift_kind == SHIFT_ASR)
7657 inst.instruction |= 0x00200000; /* sh bit */
7658 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7659 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7661 inst.reloc.type = BFD_RELOC_UNUSED;
7668 inst.instruction |= inst.operands[0].reg << 8;
7669 inst.instruction |= inst.operands[1].imm - 1;
7670 inst.instruction |= inst.operands[2].reg << 16;
7676 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7677 || inst.operands[2].postind || inst.operands[2].writeback
7678 || inst.operands[2].immisreg || inst.operands[2].shifted
7679 || inst.operands[2].negative,
7682 inst.instruction |= inst.operands[0].reg << 8;
7683 inst.instruction |= inst.operands[1].reg << 12;
7684 inst.instruction |= inst.operands[2].reg << 16;
7685 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7691 if (!inst.operands[2].present)
7692 inst.operands[2].reg = inst.operands[1].reg + 1;
7694 constraint (inst.operands[0].reg == inst.operands[1].reg
7695 || inst.operands[0].reg == inst.operands[2].reg
7696 || inst.operands[0].reg == inst.operands[3].reg
7697 || inst.operands[1].reg == inst.operands[2].reg,
7700 inst.instruction |= inst.operands[0].reg;
7701 inst.instruction |= inst.operands[1].reg << 12;
7702 inst.instruction |= inst.operands[2].reg << 8;
7703 inst.instruction |= inst.operands[3].reg << 16;
7709 inst.instruction |= inst.operands[0].reg << 8;
7710 inst.instruction |= inst.operands[1].reg << 16;
7711 inst.instruction |= inst.operands[2].reg;
7712 inst.instruction |= inst.operands[3].imm << 4;
7718 if (inst.instruction <= 0xffff && inst.size_req != 4
7719 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7720 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7722 inst.instruction = THUMB_OP16 (inst.instruction);
7723 inst.instruction |= inst.operands[0].reg;
7724 inst.instruction |= inst.operands[1].reg << 3;
7726 else if (unified_syntax)
7728 if (inst.instruction <= 0xffff)
7729 inst.instruction = THUMB_OP32 (inst.instruction);
7730 inst.instruction |= inst.operands[0].reg << 8;
7731 inst.instruction |= inst.operands[1].reg;
7732 inst.instruction |= inst.operands[2].imm << 4;
7736 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7737 _("Thumb encoding does not support rotation"));
7738 constraint (1, BAD_HIREG);
7745 inst.reloc.type = BFD_RELOC_ARM_SWI;
7753 half = (inst.instruction & 0x10) != 0;
7754 constraint (inst.operands[0].imm == 15,
7755 _("PC is not a valid index register"));
7756 constraint (!half && inst.operands[0].shifted,
7757 _("instruction does not allow shifted index"));
7758 constraint (half && !inst.operands[0].shifted,
7759 _("instruction requires shifted index"));
7760 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7766 inst.instruction |= inst.operands[0].reg << 8;
7767 inst.instruction |= inst.operands[1].imm;
7768 inst.instruction |= inst.operands[2].reg << 16;
7770 if (inst.operands[3].present)
7772 constraint (inst.reloc.exp.X_op != O_constant,
7773 _("expression too complex"));
7774 if (inst.reloc.exp.X_add_number != 0)
7776 if (inst.operands[3].shift_kind == SHIFT_ASR)
7777 inst.instruction |= 0x00200000; /* sh bit */
7779 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7780 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7782 inst.reloc.type = BFD_RELOC_UNUSED;
7789 inst.instruction |= inst.operands[0].reg << 8;
7790 inst.instruction |= inst.operands[1].imm;
7791 inst.instruction |= inst.operands[2].reg << 16;
7794 /* Overall per-instruction processing. */
7796 /* We need to be able to fix up arbitrary expressions in some statements.
7797 This is so that we can handle symbols that are an arbitrary distance from
7798 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7799 which returns part of an address in a form which will be valid for
7800 a data instruction. We do this by pushing the expression into a symbol
7801 in the expr_section, and creating a fix for that. */
7804 fix_new_arm (fragS * frag,
7819 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7823 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7828 /* Mark whether the fix is to a THUMB instruction, or an ARM
7830 new_fix->tc_fix_data = thumb_mode;
7833 /* Create a frg for an instruction requiring relaxation. */
7835 output_relax_insn (void)
7841 switch (inst.reloc.exp.X_op)
7844 sym = inst.reloc.exp.X_add_symbol;
7845 offset = inst.reloc.exp.X_add_number;
7849 offset = inst.reloc.exp.X_add_number;
7852 sym = make_expr_symbol (&inst.reloc.exp);
7856 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
7857 inst.relax, sym, offset, NULL/*offset, opcode*/);
7858 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
7861 dwarf2_emit_insn (INSN_SIZE);
7865 /* Write a 32-bit thumb instruction to buf. */
7867 put_thumb32_insn (char * buf, unsigned long insn)
7869 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
7870 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
7874 output_inst (const char * str)
7880 as_bad ("%s -- `%s'", inst.error, str);
7884 output_relax_insn();
7890 to = frag_more (inst.size);
7892 if (thumb_mode && (inst.size > THUMB_SIZE))
7894 assert (inst.size == (2 * THUMB_SIZE));
7895 put_thumb32_insn (to, inst.instruction);
7897 else if (inst.size > INSN_SIZE)
7899 assert (inst.size == (2 * INSN_SIZE));
7900 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7901 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7904 md_number_to_chars (to, inst.instruction, inst.size);
7906 if (inst.reloc.type != BFD_RELOC_UNUSED)
7907 fix_new_arm (frag_now, to - frag_now->fr_literal,
7908 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7912 dwarf2_emit_insn (inst.size);
7916 /* Tag values used in struct asm_opcode's tag field. */
7919 OT_unconditional, /* Instruction cannot be conditionalized.
7920 The ARM condition field is still 0xE. */
7921 OT_unconditionalF, /* Instruction cannot be conditionalized
7922 and carries 0xF in its ARM condition field. */
7923 OT_csuffix, /* Instruction takes a conditional suffix. */
7924 OT_cinfix3, /* Instruction takes a conditional infix,
7925 beginning at character index 3. (In
7926 unified mode, it becomes a suffix.) */
7927 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
7928 character index 3, even in unified mode. Used for
7929 legacy instructions where suffix and infix forms
7930 may be ambiguous. */
7931 OT_csuf_or_in3, /* Instruction takes either a conditional
7932 suffix or an infix at character index 3. */
7933 OT_odd_infix_unc, /* This is the unconditional variant of an
7934 instruction that takes a conditional infix
7935 at an unusual position. In unified mode,
7936 this variant will accept a suffix. */
7937 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7938 are the conditional variants of instructions that
7939 take conditional infixes in unusual positions.
7940 The infix appears at character index
7941 (tag - OT_odd_infix_0). These are not accepted
7945 /* Subroutine of md_assemble, responsible for looking up the primary
7946 opcode from the mnemonic the user wrote. STR points to the
7947 beginning of the mnemonic.
7949 This is not simply a hash table lookup, because of conditional
7950 variants. Most instructions have conditional variants, which are
7951 expressed with a _conditional affix_ to the mnemonic. If we were
7952 to encode each conditional variant as a literal string in the opcode
7953 table, it would have approximately 20,000 entries.
7955 Most mnemonics take this affix as a suffix, and in unified syntax,
7956 'most' is upgraded to 'all'. However, in the divided syntax, some
7957 instructions take the affix as an infix, notably the s-variants of
7958 the arithmetic instructions. Of those instructions, all but six
7959 have the infix appear after the third character of the mnemonic.
7961 Accordingly, the algorithm for looking up primary opcodes given
7964 1. Look up the identifier in the opcode table.
7965 If we find a match, go to step U.
7967 2. Look up the last two characters of the identifier in the
7968 conditions table. If we find a match, look up the first N-2
7969 characters of the identifier in the opcode table. If we
7970 find a match, go to step CE.
7972 3. Look up the fourth and fifth characters of the identifier in
7973 the conditions table. If we find a match, extract those
7974 characters from the identifier, and look up the remaining
7975 characters in the opcode table. If we find a match, go
7980 U. Examine the tag field of the opcode structure, in case this is
7981 one of the six instructions with its conditional infix in an
7982 unusual place. If it is, the tag tells us where to find the
7983 infix; look it up in the conditions table and set inst.cond
7984 accordingly. Otherwise, this is an unconditional instruction.
7985 Again set inst.cond accordingly. Return the opcode structure.
7987 CE. Examine the tag field to make sure this is an instruction that
7988 should receive a conditional suffix. If it is not, fail.
7989 Otherwise, set inst.cond from the suffix we already looked up,
7990 and return the opcode structure.
7992 CM. Examine the tag field to make sure this is an instruction that
7993 should receive a conditional infix after the third character.
7994 If it is not, fail. Otherwise, undo the edits to the current
7995 line of input and proceed as for case CE. */
7997 static const struct asm_opcode *
7998 opcode_lookup (char **str)
8002 const struct asm_opcode *opcode;
8003 const struct asm_cond *cond;
8006 /* Scan up to the end of the mnemonic, which must end in white space,
8007 '.' (in unified mode only), or end of string. */
8008 for (base = end = *str; *end != '\0'; end++)
8009 if (*end == ' ' || (unified_syntax && *end == '.'))
8015 /* Handle a possible width suffix. */
8018 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
8020 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
8030 /* Look for unaffixed or special-case affixed mnemonic. */
8031 opcode = hash_find_n (arm_ops_hsh, base, end - base);
8035 if (opcode->tag < OT_odd_infix_0)
8037 inst.cond = COND_ALWAYS;
8042 as_warn (_("conditional infixes are deprecated in unified syntax"));
8043 affix = base + (opcode->tag - OT_odd_infix_0);
8044 cond = hash_find_n (arm_cond_hsh, affix, 2);
8047 inst.cond = cond->value;
8051 /* Cannot have a conditional suffix on a mnemonic of less than two
8056 /* Look for suffixed mnemonic. */
8058 cond = hash_find_n (arm_cond_hsh, affix, 2);
8059 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
8063 switch (opcode->tag)
8065 case OT_cinfix3_legacy:
8066 /* Ignore conditional suffixes matched on infix only mnemonics. */
8070 case OT_odd_infix_unc:
8071 if (!unified_syntax)
8073 /* else fall through */
8076 case OT_csuf_or_in3:
8077 inst.cond = cond->value;
8080 case OT_unconditional:
8081 case OT_unconditionalF:
8082 /* delayed diagnostic */
8083 inst.error = BAD_COND;
8084 inst.cond = COND_ALWAYS;
8092 /* Cannot have a usual-position infix on a mnemonic of less than
8093 six characters (five would be a suffix). */
8097 /* Look for infixed mnemonic in the usual position. */
8099 cond = hash_find_n (arm_cond_hsh, affix, 2);
8103 memcpy (save, affix, 2);
8104 memmove (affix, affix + 2, (end - affix) - 2);
8105 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
8106 memmove (affix + 2, affix, (end - affix) - 2);
8107 memcpy (affix, save, 2);
8109 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3
8110 || opcode->tag == OT_cinfix3_legacy))
8113 if (unified_syntax && opcode->tag == OT_cinfix3)
8114 as_warn (_("conditional infixes are deprecated in unified syntax"));
8116 inst.cond = cond->value;
8124 md_assemble (char *str)
8127 const struct asm_opcode * opcode;
8129 /* Align the previous label if needed. */
8130 if (last_label_seen != NULL)
8132 symbol_set_frag (last_label_seen, frag_now);
8133 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
8134 S_SET_SEGMENT (last_label_seen, now_seg);
8137 memset (&inst, '\0', sizeof (inst));
8138 inst.reloc.type = BFD_RELOC_UNUSED;
8140 opcode = opcode_lookup (&p);
8143 /* It wasn't an instruction, but it might be a register alias of
8144 the form alias .req reg. */
8145 if (!create_register_alias (str, p))
8146 as_bad (_("bad instruction `%s'"), str);
8153 arm_feature_set variant;
8155 variant = cpu_variant;
8156 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
8157 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
8158 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
8159 /* Check that this instruction is supported for this CPU. */
8161 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant))
8163 as_bad (_("selected processor does not support `%s'"), str);
8166 if (inst.cond != COND_ALWAYS && !unified_syntax
8167 && opcode->tencode != do_t_branch)
8169 as_bad (_("Thumb does not support conditional execution"));
8173 /* Check conditional suffixes. */
8174 if (current_it_mask)
8177 cond = current_cc ^ ((current_it_mask >> 4) & 1) ^ 1;
8178 if (cond != inst.cond)
8180 as_bad (_("incorrect condition in IT block"));
8183 current_it_mask <<= 1;
8184 current_it_mask &= 0x1f;
8186 else if (inst.cond != COND_ALWAYS && opcode->tencode != do_t_branch)
8188 as_bad (_("thumb conditional instrunction not in IT block"));
8192 mapping_state (MAP_THUMB);
8193 inst.instruction = opcode->tvalue;
8195 if (!parse_operands (p, opcode->operands))
8198 /* Clear current_it_mask at the end of an IT block. */
8199 if (current_it_mask == 0x10)
8200 current_it_mask = 0;
8202 if (!(inst.error || inst.relax))
8204 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
8205 inst.size = (inst.instruction > 0xffff ? 4 : 2);
8206 if (inst.size_req && inst.size_req != inst.size)
8208 as_bad (_("cannot honor width suffix -- `%s'"), str);
8212 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8214 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
8215 set those bits when Thumb-2 32-bit instuctions are seen. ie.
8216 anything other than bl/blx.
8217 This is overly pessimistic for relaxable instructions. */
8218 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
8220 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8225 /* Check that this instruction is supported for this CPU. */
8226 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
8228 as_bad (_("selected processor does not support `%s'"), str);
8233 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
8237 mapping_state (MAP_ARM);
8238 inst.instruction = opcode->avalue;
8239 if (opcode->tag == OT_unconditionalF)
8240 inst.instruction |= 0xF << 28;
8242 inst.instruction |= inst.cond << 28;
8243 inst.size = INSN_SIZE;
8244 if (!parse_operands (p, opcode->operands))
8246 /* Arm mode bx is marked as both v4T and v5 because it's still required
8247 on a hypothetical non-thumb v5 core. */
8248 if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
8249 || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
8250 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
8252 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8258 /* Various frobbings of labels and their addresses. */
8261 arm_start_line_hook (void)
8263 last_label_seen = NULL;
8267 arm_frob_label (symbolS * sym)
8269 last_label_seen = sym;
8271 ARM_SET_THUMB (sym, thumb_mode);
8273 #if defined OBJ_COFF || defined OBJ_ELF
8274 ARM_SET_INTERWORK (sym, support_interwork);
8277 /* Note - do not allow local symbols (.Lxxx) to be labeled
8278 as Thumb functions. This is because these labels, whilst
8279 they exist inside Thumb code, are not the entry points for
8280 possible ARM->Thumb calls. Also, these labels can be used
8281 as part of a computed goto or switch statement. eg gcc
8282 can generate code that looks like this:
8294 The first instruction loads the address of the jump table.
8295 The second instruction converts a table index into a byte offset.
8296 The third instruction gets the jump address out of the table.
8297 The fourth instruction performs the jump.
8299 If the address stored at .Laaa is that of a symbol which has the
8300 Thumb_Func bit set, then the linker will arrange for this address
8301 to have the bottom bit set, which in turn would mean that the
8302 address computation performed by the third instruction would end
8303 up with the bottom bit set. Since the ARM is capable of unaligned
8304 word loads, the instruction would then load the incorrect address
8305 out of the jump table, and chaos would ensue. */
8306 if (label_is_thumb_function_name
8307 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
8308 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
8310 /* When the address of a Thumb function is taken the bottom
8311 bit of that address should be set. This will allow
8312 interworking between Arm and Thumb functions to work
8315 THUMB_SET_FUNC (sym, 1);
8317 label_is_thumb_function_name = FALSE;
8321 dwarf2_emit_label (sym);
8326 arm_data_in_code (void)
8328 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
8330 *input_line_pointer = '/';
8331 input_line_pointer += 5;
8332 *input_line_pointer = 0;
8340 arm_canonicalize_symbol_name (char * name)
8344 if (thumb_mode && (len = strlen (name)) > 5
8345 && streq (name + len - 5, "/data"))
8346 *(name + len - 5) = 0;
8351 /* Table of all register names defined by default. The user can
8352 define additional names with .req. Note that all register names
8353 should appear in both upper and lowercase variants. Some registers
8354 also have mixed-case names. */
8356 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
8357 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
8358 #define REGSET(p,t) \
8359 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
8360 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
8361 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
8362 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
8364 static const struct reg_entry reg_names[] =
8366 /* ARM integer registers. */
8367 REGSET(r, RN), REGSET(R, RN),
8369 /* ATPCS synonyms. */
8370 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
8371 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
8372 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
8374 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
8375 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
8376 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
8378 /* Well-known aliases. */
8379 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
8380 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
8382 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
8383 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
8385 /* Coprocessor numbers. */
8386 REGSET(p, CP), REGSET(P, CP),
8388 /* Coprocessor register numbers. The "cr" variants are for backward
8390 REGSET(c, CN), REGSET(C, CN),
8391 REGSET(cr, CN), REGSET(CR, CN),
8393 /* FPA registers. */
8394 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
8395 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
8397 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
8398 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
8400 /* VFP SP registers. */
8402 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
8403 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
8404 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
8405 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
8408 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
8409 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
8410 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
8411 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
8413 /* VFP DP Registers. */
8414 REGSET(d,VFD), REGSET(D,VFS),
8416 /* VFP control registers. */
8417 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
8418 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
8420 /* Maverick DSP coprocessor registers. */
8421 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
8422 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
8424 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
8425 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
8426 REGDEF(dspsc,0,DSPSC),
8428 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
8429 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
8430 REGDEF(DSPSC,0,DSPSC),
8432 /* iWMMXt data registers - p0, c0-15. */
8433 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
8435 /* iWMMXt control registers - p1, c0-3. */
8436 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
8437 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
8438 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
8439 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
8441 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
8442 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
8443 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
8444 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
8445 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
8447 /* XScale accumulator registers. */
8448 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
8454 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
8455 within psr_required_here. */
8456 static const struct asm_psr psrs[] =
8458 /* Backward compatibility notation. Note that "all" is no longer
8459 truly all possible PSR bits. */
8460 {"all", PSR_c | PSR_f},
8464 /* Individual flags. */
8469 /* Combinations of flags. */
8470 {"fs", PSR_f | PSR_s},
8471 {"fx", PSR_f | PSR_x},
8472 {"fc", PSR_f | PSR_c},
8473 {"sf", PSR_s | PSR_f},
8474 {"sx", PSR_s | PSR_x},
8475 {"sc", PSR_s | PSR_c},
8476 {"xf", PSR_x | PSR_f},
8477 {"xs", PSR_x | PSR_s},
8478 {"xc", PSR_x | PSR_c},
8479 {"cf", PSR_c | PSR_f},
8480 {"cs", PSR_c | PSR_s},
8481 {"cx", PSR_c | PSR_x},
8482 {"fsx", PSR_f | PSR_s | PSR_x},
8483 {"fsc", PSR_f | PSR_s | PSR_c},
8484 {"fxs", PSR_f | PSR_x | PSR_s},
8485 {"fxc", PSR_f | PSR_x | PSR_c},
8486 {"fcs", PSR_f | PSR_c | PSR_s},
8487 {"fcx", PSR_f | PSR_c | PSR_x},
8488 {"sfx", PSR_s | PSR_f | PSR_x},
8489 {"sfc", PSR_s | PSR_f | PSR_c},
8490 {"sxf", PSR_s | PSR_x | PSR_f},
8491 {"sxc", PSR_s | PSR_x | PSR_c},
8492 {"scf", PSR_s | PSR_c | PSR_f},
8493 {"scx", PSR_s | PSR_c | PSR_x},
8494 {"xfs", PSR_x | PSR_f | PSR_s},
8495 {"xfc", PSR_x | PSR_f | PSR_c},
8496 {"xsf", PSR_x | PSR_s | PSR_f},
8497 {"xsc", PSR_x | PSR_s | PSR_c},
8498 {"xcf", PSR_x | PSR_c | PSR_f},
8499 {"xcs", PSR_x | PSR_c | PSR_s},
8500 {"cfs", PSR_c | PSR_f | PSR_s},
8501 {"cfx", PSR_c | PSR_f | PSR_x},
8502 {"csf", PSR_c | PSR_s | PSR_f},
8503 {"csx", PSR_c | PSR_s | PSR_x},
8504 {"cxf", PSR_c | PSR_x | PSR_f},
8505 {"cxs", PSR_c | PSR_x | PSR_s},
8506 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
8507 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
8508 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
8509 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
8510 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
8511 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
8512 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
8513 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
8514 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
8515 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
8516 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
8517 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
8518 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
8519 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
8520 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
8521 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
8522 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
8523 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
8524 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
8525 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
8526 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
8527 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
8528 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
8529 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8532 /* Table of all shift-in-operand names. */
8533 static const struct asm_shift_name shift_names [] =
8535 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8536 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8537 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8538 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8539 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8540 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8543 /* Table of all explicit relocation names. */
8545 static struct reloc_entry reloc_names[] =
8547 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8548 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8549 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8550 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8551 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8552 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8553 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8554 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8555 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8556 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8557 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8561 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8562 static const struct asm_cond conds[] =
8566 {"cs", 0x2}, {"hs", 0x2},
8567 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8581 /* Table of ARM-format instructions. */
8583 /* Macros for gluing together operand strings. N.B. In all cases
8584 other than OPS0, the trailing OP_stop comes from default
8585 zero-initialization of the unspecified elements of the array. */
8586 #define OPS0() { OP_stop, }
8587 #define OPS1(a) { OP_##a, }
8588 #define OPS2(a,b) { OP_##a,OP_##b, }
8589 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8590 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8591 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8592 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8594 /* These macros abstract out the exact format of the mnemonic table and
8595 save some repeated characters. */
8597 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8598 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8599 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8600 THUMB_VARIANT, do_##ae, do_##te }
8602 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8603 a T_MNEM_xyz enumerator. */
8604 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8605 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8606 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8607 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8609 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8610 infix after the third character. */
8611 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8612 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8613 THUMB_VARIANT, do_##ae, do_##te }
8614 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8615 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8616 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8617 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8619 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8620 appear in the condition table. */
8621 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8622 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8623 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8625 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8626 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8627 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8628 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8629 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8630 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8631 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8632 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8633 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8634 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8635 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8636 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8637 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8638 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8639 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8640 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8641 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8642 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8643 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8644 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8646 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8647 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8648 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8649 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8651 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8652 field is still 0xE. */
8653 #define TUE(mnem, op, top, nops, ops, ae, te) \
8654 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8655 THUMB_VARIANT, do_##ae, do_##te }
8657 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8658 condition code field. */
8659 #define TUF(mnem, op, top, nops, ops, ae, te) \
8660 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8661 THUMB_VARIANT, do_##ae, do_##te }
8663 /* ARM-only variants of all the above. */
8664 #define CE(mnem, op, nops, ops, ae) \
8665 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8667 #define C3(mnem, op, nops, ops, ae) \
8668 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8670 /* Legacy mnemonics that always have conditional infix after the third
8672 #define CL(mnem, op, nops, ops, ae) \
8673 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8674 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8676 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
8677 #define cCE(mnem, op, nops, ops, ae) \
8678 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8680 /* Legacy coprocessor instructions where conditional infix and conditional
8681 suffix are ambiguous. For consistency this includes all FPA instructions,
8682 not just the potentially ambiguous ones. */
8683 #define cCL(mnem, op, nops, ops, ae) \
8684 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
8685 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8687 /* Coprocessor, takes either a suffix or a position-3 infix
8688 (for an FPA corner case). */
8689 #define C3E(mnem, op, nops, ops, ae) \
8690 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
8691 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8693 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8694 { #m1 #m2 #m3, OPS##nops ops, \
8695 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8696 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8698 #define CM(m1, m2, op, nops, ops, ae) \
8699 xCM_(m1, , m2, op, nops, ops, ae), \
8700 xCM_(m1, eq, m2, op, nops, ops, ae), \
8701 xCM_(m1, ne, m2, op, nops, ops, ae), \
8702 xCM_(m1, cs, m2, op, nops, ops, ae), \
8703 xCM_(m1, hs, m2, op, nops, ops, ae), \
8704 xCM_(m1, cc, m2, op, nops, ops, ae), \
8705 xCM_(m1, ul, m2, op, nops, ops, ae), \
8706 xCM_(m1, lo, m2, op, nops, ops, ae), \
8707 xCM_(m1, mi, m2, op, nops, ops, ae), \
8708 xCM_(m1, pl, m2, op, nops, ops, ae), \
8709 xCM_(m1, vs, m2, op, nops, ops, ae), \
8710 xCM_(m1, vc, m2, op, nops, ops, ae), \
8711 xCM_(m1, hi, m2, op, nops, ops, ae), \
8712 xCM_(m1, ls, m2, op, nops, ops, ae), \
8713 xCM_(m1, ge, m2, op, nops, ops, ae), \
8714 xCM_(m1, lt, m2, op, nops, ops, ae), \
8715 xCM_(m1, gt, m2, op, nops, ops, ae), \
8716 xCM_(m1, le, m2, op, nops, ops, ae), \
8717 xCM_(m1, al, m2, op, nops, ops, ae)
8719 #define UE(mnem, op, nops, ops, ae) \
8720 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8722 #define UF(mnem, op, nops, ops, ae) \
8723 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8727 /* Thumb-only, unconditional. */
8728 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8730 static const struct asm_opcode insns[] =
8732 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
8733 #define THUMB_VARIANT &arm_ext_v4t
8734 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8735 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8736 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8737 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8738 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8739 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8740 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8741 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8742 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8743 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8744 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8745 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8746 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8747 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8748 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8749 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8751 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8752 for setting PSR flag bits. They are obsolete in V6 and do not
8753 have Thumb equivalents. */
8754 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8755 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8756 CL(tstp, 110f000, 2, (RR, SH), cmp),
8757 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8758 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8759 CL(cmpp, 150f000, 2, (RR, SH), cmp),
8760 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8761 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8762 CL(cmnp, 170f000, 2, (RR, SH), cmp),
8764 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8765 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8766 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8767 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8769 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8770 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8771 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8772 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8774 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8775 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8776 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8777 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8779 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8780 tCE(b, a000000, b, 1, (EXPr), branch, t_branch),
8781 TCE(bl, b000000, f000f800, 1, (EXPr), bl, t_branch23),
8784 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8785 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8786 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8788 /* Thumb-compatibility pseudo ops. */
8789 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8790 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8791 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8792 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8793 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8794 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8795 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8796 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8797 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8798 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8799 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8800 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8802 #undef THUMB_VARIANT
8803 #define THUMB_VARIANT &arm_ext_v6
8804 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8806 /* V1 instructions with no Thumb analogue prior to V6T2. */
8807 #undef THUMB_VARIANT
8808 #define THUMB_VARIANT &arm_ext_v6t2
8809 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8810 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8811 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8812 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8813 CL(teqp, 130f000, 2, (RR, SH), cmp),
8815 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8816 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8817 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8818 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8820 TC3(stmdb, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8821 TC3(stmfd, 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8823 TC3(ldmdb, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8824 TC3(ldmea, 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8826 /* V1 instructions with no Thumb analogue at all. */
8827 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8828 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8830 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8831 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8832 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8833 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8834 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8835 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8836 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8837 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8840 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
8841 #undef THUMB_VARIANT
8842 #define THUMB_VARIANT &arm_ext_v4t
8843 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8844 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8846 #undef THUMB_VARIANT
8847 #define THUMB_VARIANT &arm_ext_v6t2
8848 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8849 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8851 /* Generic coprocessor instructions. */
8852 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8853 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8854 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8855 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8856 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8857 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8858 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8861 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
8862 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8863 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8866 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
8867 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8868 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8871 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
8872 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8873 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8874 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8875 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8876 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8877 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8878 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8879 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8882 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
8883 #undef THUMB_VARIANT
8884 #define THUMB_VARIANT &arm_ext_v4t
8885 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8886 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8887 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8888 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8889 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8890 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8893 #define ARM_VARIANT &arm_ext_v4t_5
8894 /* ARM Architecture 4T. */
8895 /* Note: bx (and blx) are required on V5, even if the processor does
8896 not support Thumb. */
8897 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8900 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
8901 #undef THUMB_VARIANT
8902 #define THUMB_VARIANT &arm_ext_v5t
8903 /* Note: blx has 2 variants; the .value coded here is for
8904 BLX(2). Only this variant has conditional execution. */
8905 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8906 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8908 #undef THUMB_VARIANT
8909 #define THUMB_VARIANT &arm_ext_v6t2
8910 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8911 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8912 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8913 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8914 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8915 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8916 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8917 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8920 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
8921 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8922 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8923 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8924 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8926 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8927 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8929 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8930 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8931 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8932 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8934 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8935 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8936 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8937 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8939 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8940 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8942 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8943 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8944 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8945 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8948 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
8949 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8950 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8951 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8953 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8954 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8957 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
8958 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8961 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
8962 #undef THUMB_VARIANT
8963 #define THUMB_VARIANT &arm_ext_v6
8964 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8965 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8966 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8967 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8968 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8969 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8970 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8971 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8972 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8973 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8975 #undef THUMB_VARIANT
8976 #define THUMB_VARIANT &arm_ext_v6t2
8977 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8978 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8979 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8980 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8981 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8982 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8983 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8984 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8985 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8986 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8987 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8988 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8989 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8990 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8991 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8992 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8993 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8994 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8995 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8996 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8997 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8998 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8999 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9000 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9001 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9002 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9003 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9004 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9005 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9006 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9007 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9008 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9009 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9010 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9011 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9012 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9013 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9014 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9015 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9016 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9017 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9018 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9019 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9020 UF(rfeib, 9900a00, 1, (RRw), rfe),
9021 UF(rfeda, 8100a00, 1, (RRw), rfe),
9022 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9023 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
9024 UF(rfefa, 9900a00, 1, (RRw), rfe),
9025 UF(rfeea, 8100a00, 1, (RRw), rfe),
9026 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
9027 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9028 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9029 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9030 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9031 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9032 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9033 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
9034 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
9035 TCE(sel, 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
9036 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9037 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9038 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9039 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9040 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9041 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9042 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9043 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
9044 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9045 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9046 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9047 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9048 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9049 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9050 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9051 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9052 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9053 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9054 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
9055 UF(srsib, 9cd0500, 1, (I31w), srs),
9056 UF(srsda, 84d0500, 1, (I31w), srs),
9057 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
9058 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
9059 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
9060 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
9061 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
9062 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
9063 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
9064 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
9065 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
9068 #define ARM_VARIANT &arm_ext_v6k
9069 #undef THUMB_VARIANT
9070 #define THUMB_VARIANT &arm_ext_v6k
9071 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
9072 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
9073 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
9074 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
9076 #undef THUMB_VARIANT
9077 #define THUMB_VARIANT &arm_ext_v6t2
9078 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9079 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
9080 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
9081 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9082 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
9083 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
9084 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
9087 #define ARM_VARIANT &arm_ext_v6z
9088 TCE(smc, 1600070, f7f08000, 1, (EXPi), smc, t_smc),
9091 #define ARM_VARIANT &arm_ext_v6t2
9092 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
9093 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
9094 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9095 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
9097 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
9098 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
9099 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
9100 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
9102 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9103 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9104 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9105 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
9107 UT(cbnz, b900, 2, (RR, EXP), t_czb),
9108 UT(cbz, b100, 2, (RR, EXP), t_czb),
9109 /* ARM does not really have an IT instruction. */
9110 TUE(it, 0, bf08, 1, (COND), it, t_it),
9111 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
9112 TUE(ite, 0, bf04, 1, (COND), it, t_it),
9113 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
9114 TUE(itet, 0, bf06, 1, (COND), it, t_it),
9115 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
9116 TUE(itee, 0, bf02, 1, (COND), it, t_it),
9117 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
9118 TUE(itett, 0, bf07, 1, (COND), it, t_it),
9119 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
9120 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
9121 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
9122 TUE(itete, 0, bf05, 1, (COND), it, t_it),
9123 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
9124 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
9126 /* Thumb2 only instructions. */
9128 #define ARM_VARIANT NULL
9130 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9131 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
9132 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
9133 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
9136 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
9137 cCE(wfs, e200110, 1, (RR), rd),
9138 cCE(rfs, e300110, 1, (RR), rd),
9139 cCE(wfc, e400110, 1, (RR), rd),
9140 cCE(rfc, e500110, 1, (RR), rd),
9142 cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
9143 cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
9144 cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
9145 cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
9147 cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
9148 cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
9149 cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
9150 cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
9152 cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
9153 cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
9154 cCL(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
9155 cCL(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
9156 cCL(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
9157 cCL(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
9158 cCL(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
9159 cCL(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
9160 cCL(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
9161 cCL(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
9162 cCL(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
9163 cCL(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
9165 cCL(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
9166 cCL(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
9167 cCL(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
9168 cCL(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
9169 cCL(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
9170 cCL(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
9171 cCL(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
9172 cCL(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
9173 cCL(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
9174 cCL(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
9175 cCL(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
9176 cCL(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
9178 cCL(abss, e208100, 2, (RF, RF_IF), rd_rm),
9179 cCL(abssp, e208120, 2, (RF, RF_IF), rd_rm),
9180 cCL(abssm, e208140, 2, (RF, RF_IF), rd_rm),
9181 cCL(abssz, e208160, 2, (RF, RF_IF), rd_rm),
9182 cCL(absd, e208180, 2, (RF, RF_IF), rd_rm),
9183 cCL(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
9184 cCL(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
9185 cCL(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
9186 cCL(abse, e288100, 2, (RF, RF_IF), rd_rm),
9187 cCL(absep, e288120, 2, (RF, RF_IF), rd_rm),
9188 cCL(absem, e288140, 2, (RF, RF_IF), rd_rm),
9189 cCL(absez, e288160, 2, (RF, RF_IF), rd_rm),
9191 cCL(rnds, e308100, 2, (RF, RF_IF), rd_rm),
9192 cCL(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
9193 cCL(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
9194 cCL(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
9195 cCL(rndd, e308180, 2, (RF, RF_IF), rd_rm),
9196 cCL(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
9197 cCL(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
9198 cCL(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
9199 cCL(rnde, e388100, 2, (RF, RF_IF), rd_rm),
9200 cCL(rndep, e388120, 2, (RF, RF_IF), rd_rm),
9201 cCL(rndem, e388140, 2, (RF, RF_IF), rd_rm),
9202 cCL(rndez, e388160, 2, (RF, RF_IF), rd_rm),
9204 cCL(sqts, e408100, 2, (RF, RF_IF), rd_rm),
9205 cCL(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
9206 cCL(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
9207 cCL(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
9208 cCL(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
9209 cCL(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
9210 cCL(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
9211 cCL(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
9212 cCL(sqte, e488100, 2, (RF, RF_IF), rd_rm),
9213 cCL(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
9214 cCL(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
9215 cCL(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
9217 cCL(logs, e508100, 2, (RF, RF_IF), rd_rm),
9218 cCL(logsp, e508120, 2, (RF, RF_IF), rd_rm),
9219 cCL(logsm, e508140, 2, (RF, RF_IF), rd_rm),
9220 cCL(logsz, e508160, 2, (RF, RF_IF), rd_rm),
9221 cCL(logd, e508180, 2, (RF, RF_IF), rd_rm),
9222 cCL(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
9223 cCL(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
9224 cCL(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
9225 cCL(loge, e588100, 2, (RF, RF_IF), rd_rm),
9226 cCL(logep, e588120, 2, (RF, RF_IF), rd_rm),
9227 cCL(logem, e588140, 2, (RF, RF_IF), rd_rm),
9228 cCL(logez, e588160, 2, (RF, RF_IF), rd_rm),
9230 cCL(lgns, e608100, 2, (RF, RF_IF), rd_rm),
9231 cCL(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
9232 cCL(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
9233 cCL(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
9234 cCL(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
9235 cCL(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
9236 cCL(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
9237 cCL(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
9238 cCL(lgne, e688100, 2, (RF, RF_IF), rd_rm),
9239 cCL(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
9240 cCL(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
9241 cCL(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
9243 cCL(exps, e708100, 2, (RF, RF_IF), rd_rm),
9244 cCL(expsp, e708120, 2, (RF, RF_IF), rd_rm),
9245 cCL(expsm, e708140, 2, (RF, RF_IF), rd_rm),
9246 cCL(expsz, e708160, 2, (RF, RF_IF), rd_rm),
9247 cCL(expd, e708180, 2, (RF, RF_IF), rd_rm),
9248 cCL(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
9249 cCL(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
9250 cCL(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
9251 cCL(expe, e788100, 2, (RF, RF_IF), rd_rm),
9252 cCL(expep, e788120, 2, (RF, RF_IF), rd_rm),
9253 cCL(expem, e788140, 2, (RF, RF_IF), rd_rm),
9254 cCL(expdz, e788160, 2, (RF, RF_IF), rd_rm),
9256 cCL(sins, e808100, 2, (RF, RF_IF), rd_rm),
9257 cCL(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
9258 cCL(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
9259 cCL(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
9260 cCL(sind, e808180, 2, (RF, RF_IF), rd_rm),
9261 cCL(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
9262 cCL(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
9263 cCL(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
9264 cCL(sine, e888100, 2, (RF, RF_IF), rd_rm),
9265 cCL(sinep, e888120, 2, (RF, RF_IF), rd_rm),
9266 cCL(sinem, e888140, 2, (RF, RF_IF), rd_rm),
9267 cCL(sinez, e888160, 2, (RF, RF_IF), rd_rm),
9269 cCL(coss, e908100, 2, (RF, RF_IF), rd_rm),
9270 cCL(cossp, e908120, 2, (RF, RF_IF), rd_rm),
9271 cCL(cossm, e908140, 2, (RF, RF_IF), rd_rm),
9272 cCL(cossz, e908160, 2, (RF, RF_IF), rd_rm),
9273 cCL(cosd, e908180, 2, (RF, RF_IF), rd_rm),
9274 cCL(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
9275 cCL(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
9276 cCL(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
9277 cCL(cose, e988100, 2, (RF, RF_IF), rd_rm),
9278 cCL(cosep, e988120, 2, (RF, RF_IF), rd_rm),
9279 cCL(cosem, e988140, 2, (RF, RF_IF), rd_rm),
9280 cCL(cosez, e988160, 2, (RF, RF_IF), rd_rm),
9282 cCL(tans, ea08100, 2, (RF, RF_IF), rd_rm),
9283 cCL(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
9284 cCL(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
9285 cCL(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
9286 cCL(tand, ea08180, 2, (RF, RF_IF), rd_rm),
9287 cCL(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
9288 cCL(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
9289 cCL(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
9290 cCL(tane, ea88100, 2, (RF, RF_IF), rd_rm),
9291 cCL(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
9292 cCL(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
9293 cCL(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
9295 cCL(asns, eb08100, 2, (RF, RF_IF), rd_rm),
9296 cCL(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
9297 cCL(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
9298 cCL(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
9299 cCL(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
9300 cCL(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
9301 cCL(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
9302 cCL(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
9303 cCL(asne, eb88100, 2, (RF, RF_IF), rd_rm),
9304 cCL(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
9305 cCL(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
9306 cCL(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
9308 cCL(acss, ec08100, 2, (RF, RF_IF), rd_rm),
9309 cCL(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
9310 cCL(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
9311 cCL(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
9312 cCL(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
9313 cCL(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
9314 cCL(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
9315 cCL(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
9316 cCL(acse, ec88100, 2, (RF, RF_IF), rd_rm),
9317 cCL(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
9318 cCL(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
9319 cCL(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
9321 cCL(atns, ed08100, 2, (RF, RF_IF), rd_rm),
9322 cCL(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
9323 cCL(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
9324 cCL(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
9325 cCL(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
9326 cCL(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
9327 cCL(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
9328 cCL(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
9329 cCL(atne, ed88100, 2, (RF, RF_IF), rd_rm),
9330 cCL(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
9331 cCL(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
9332 cCL(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
9334 cCL(urds, ee08100, 2, (RF, RF_IF), rd_rm),
9335 cCL(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
9336 cCL(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
9337 cCL(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
9338 cCL(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
9339 cCL(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
9340 cCL(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
9341 cCL(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
9342 cCL(urde, ee88100, 2, (RF, RF_IF), rd_rm),
9343 cCL(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
9344 cCL(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
9345 cCL(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
9347 cCL(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
9348 cCL(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
9349 cCL(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
9350 cCL(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
9351 cCL(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
9352 cCL(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
9353 cCL(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
9354 cCL(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
9355 cCL(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
9356 cCL(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
9357 cCL(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
9358 cCL(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
9360 cCL(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
9361 cCL(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
9362 cCL(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
9363 cCL(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
9364 cCL(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
9365 cCL(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9366 cCL(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9367 cCL(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9368 cCL(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
9369 cCL(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
9370 cCL(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
9371 cCL(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
9373 cCL(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
9374 cCL(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
9375 cCL(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
9376 cCL(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
9377 cCL(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
9378 cCL(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9379 cCL(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9380 cCL(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9381 cCL(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
9382 cCL(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
9383 cCL(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
9384 cCL(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
9386 cCL(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
9387 cCL(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
9388 cCL(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
9389 cCL(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
9390 cCL(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
9391 cCL(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9392 cCL(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9393 cCL(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9394 cCL(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
9395 cCL(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
9396 cCL(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
9397 cCL(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
9399 cCL(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
9400 cCL(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
9401 cCL(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
9402 cCL(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
9403 cCL(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
9404 cCL(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9405 cCL(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9406 cCL(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9407 cCL(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
9408 cCL(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
9409 cCL(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
9410 cCL(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
9412 cCL(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
9413 cCL(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
9414 cCL(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
9415 cCL(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
9416 cCL(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
9417 cCL(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9418 cCL(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9419 cCL(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9420 cCL(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
9421 cCL(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
9422 cCL(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
9423 cCL(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
9425 cCL(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
9426 cCL(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
9427 cCL(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
9428 cCL(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
9429 cCL(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
9430 cCL(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9431 cCL(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9432 cCL(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9433 cCL(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
9434 cCL(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
9435 cCL(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
9436 cCL(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
9438 cCL(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
9439 cCL(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
9440 cCL(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
9441 cCL(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
9442 cCL(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
9443 cCL(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9444 cCL(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9445 cCL(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9446 cCL(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
9447 cCL(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
9448 cCL(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
9449 cCL(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
9451 cCL(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
9452 cCL(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
9453 cCL(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
9454 cCL(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
9455 cCL(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
9456 cCL(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9457 cCL(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9458 cCL(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9459 cCL(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
9460 cCL(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
9461 cCL(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
9462 cCL(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
9464 cCL(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
9465 cCL(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
9466 cCL(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
9467 cCL(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
9468 cCL(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
9469 cCL(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9470 cCL(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9471 cCL(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9472 cCL(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
9473 cCL(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
9474 cCL(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
9475 cCL(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
9477 cCL(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
9478 cCL(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
9479 cCL(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
9480 cCL(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
9481 cCL(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
9482 cCL(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9483 cCL(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9484 cCL(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9485 cCL(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
9486 cCL(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
9487 cCL(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
9488 cCL(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
9490 cCL(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9491 cCL(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9492 cCL(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9493 cCL(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9494 cCL(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9495 cCL(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9496 cCL(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9497 cCL(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9498 cCL(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9499 cCL(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9500 cCL(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9501 cCL(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9503 cCL(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9504 cCL(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9505 cCL(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9506 cCL(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9507 cCL(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9508 cCL(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9509 cCL(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9510 cCL(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9511 cCL(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9512 cCL(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9513 cCL(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9514 cCL(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9516 cCL(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
9517 cCL(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
9518 cCL(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
9519 cCL(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
9520 cCL(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
9521 cCL(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
9522 cCL(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
9523 cCL(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
9524 cCL(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
9525 cCL(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
9526 cCL(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
9527 cCL(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
9529 cCE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
9530 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
9531 cCE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
9532 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
9534 cCL(flts, e000110, 2, (RF, RR), rn_rd),
9535 cCL(fltsp, e000130, 2, (RF, RR), rn_rd),
9536 cCL(fltsm, e000150, 2, (RF, RR), rn_rd),
9537 cCL(fltsz, e000170, 2, (RF, RR), rn_rd),
9538 cCL(fltd, e000190, 2, (RF, RR), rn_rd),
9539 cCL(fltdp, e0001b0, 2, (RF, RR), rn_rd),
9540 cCL(fltdm, e0001d0, 2, (RF, RR), rn_rd),
9541 cCL(fltdz, e0001f0, 2, (RF, RR), rn_rd),
9542 cCL(flte, e080110, 2, (RF, RR), rn_rd),
9543 cCL(fltep, e080130, 2, (RF, RR), rn_rd),
9544 cCL(fltem, e080150, 2, (RF, RR), rn_rd),
9545 cCL(fltez, e080170, 2, (RF, RR), rn_rd),
9547 /* The implementation of the FIX instruction is broken on some
9548 assemblers, in that it accepts a precision specifier as well as a
9549 rounding specifier, despite the fact that this is meaningless.
9550 To be more compatible, we accept it as well, though of course it
9551 does not set any bits. */
9552 cCE(fix, e100110, 2, (RR, RF), rd_rm),
9553 cCL(fixp, e100130, 2, (RR, RF), rd_rm),
9554 cCL(fixm, e100150, 2, (RR, RF), rd_rm),
9555 cCL(fixz, e100170, 2, (RR, RF), rd_rm),
9556 cCL(fixsp, e100130, 2, (RR, RF), rd_rm),
9557 cCL(fixsm, e100150, 2, (RR, RF), rd_rm),
9558 cCL(fixsz, e100170, 2, (RR, RF), rd_rm),
9559 cCL(fixdp, e100130, 2, (RR, RF), rd_rm),
9560 cCL(fixdm, e100150, 2, (RR, RF), rd_rm),
9561 cCL(fixdz, e100170, 2, (RR, RF), rd_rm),
9562 cCL(fixep, e100130, 2, (RR, RF), rd_rm),
9563 cCL(fixem, e100150, 2, (RR, RF), rd_rm),
9564 cCL(fixez, e100170, 2, (RR, RF), rd_rm),
9566 /* Instructions that were new with the real FPA, call them V2. */
9568 #define ARM_VARIANT &fpu_fpa_ext_v2
9569 cCE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9570 cCL(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9571 cCL(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9572 cCE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9573 cCL(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9574 cCL(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9577 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
9578 /* Moves and type conversions. */
9579 cCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9580 cCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9581 cCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9582 cCE(fmstat, ef1fa10, 0, (), noargs),
9583 cCE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9584 cCE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9585 cCE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9586 cCE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9587 cCE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9588 cCE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9589 cCE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9590 cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9592 /* Memory operations. */
9593 cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9594 cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9595 cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9596 cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9597 cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9598 cCE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9599 cCE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9600 cCE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9601 cCE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9602 cCE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9603 cCE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9604 cCE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9605 cCE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9606 cCE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9607 cCE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9608 cCE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9609 cCE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9610 cCE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9612 /* Monadic operations. */
9613 cCE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9614 cCE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9615 cCE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9617 /* Dyadic operations. */
9618 cCE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9619 cCE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9620 cCE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9621 cCE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9622 cCE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9623 cCE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9624 cCE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9625 cCE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9626 cCE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9629 cCE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9630 cCE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9631 cCE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9632 cCE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9635 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
9636 /* Moves and type conversions. */
9637 cCE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9638 cCE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9639 cCE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9640 cCE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9641 cCE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9642 cCE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9643 cCE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9644 cCE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9645 cCE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9646 cCE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9647 cCE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9648 cCE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9649 cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9651 /* Memory operations. */
9652 cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9653 cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9654 cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9655 cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9656 cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9657 cCE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9658 cCE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9659 cCE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9660 cCE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9661 cCE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9663 /* Monadic operations. */
9664 cCE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9665 cCE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9666 cCE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9668 /* Dyadic operations. */
9669 cCE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9670 cCE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9671 cCE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9672 cCE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9673 cCE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9674 cCE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9675 cCE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9676 cCE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9677 cCE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9680 cCE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9681 cCE(fcmpzd, eb50b40, 1, (RVD), rd),
9682 cCE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9683 cCE(fcmpezd, eb50bc0, 1, (RVD), rd),
9686 #define ARM_VARIANT &fpu_vfp_ext_v2
9687 cCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9688 cCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9689 cCE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9690 cCE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9693 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
9694 cCE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9695 cCE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9696 cCE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9697 cCE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9698 cCE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9699 cCE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9700 cCE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9701 cCE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9704 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
9705 cCE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9706 cCE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9707 cCE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9708 cCE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9709 cCE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9710 cCE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9711 cCE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9712 cCE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9713 cCE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9714 cCE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9715 cCE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9716 cCE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9717 cCE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9718 cCE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9719 cCE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9720 cCE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9721 cCE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9722 cCE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9723 cCE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9724 cCE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9725 cCE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9726 cCE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9727 cCE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9728 cCE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9729 cCE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9730 cCE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9731 cCE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9732 cCE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9733 cCE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9734 cCE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9735 cCE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9736 cCE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9737 cCE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9738 cCE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9739 cCE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9740 cCE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9741 cCE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9742 cCE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9743 cCE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9744 cCE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9745 cCE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9746 cCE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9747 cCE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9748 cCE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9749 cCE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9750 cCE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9751 cCE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9752 cCE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9753 cCE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9754 cCE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9755 cCE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9756 cCE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9757 cCE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9758 cCE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9759 cCE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9760 cCE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9761 cCE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9762 cCE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9763 cCE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9764 cCE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9765 cCE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9766 cCE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9767 cCE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9768 cCE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9769 cCE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9770 cCE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9771 cCE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9772 cCE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9773 cCE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9774 cCE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9775 cCE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9776 cCE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9777 cCE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9778 cCE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9779 cCE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9780 cCE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9781 cCE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9782 cCE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9783 cCE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9784 cCE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9785 cCE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9786 cCE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9787 cCE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9788 cCE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9789 cCE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9790 cCE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9791 cCE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9792 cCE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9793 cCE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9794 cCE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9795 cCE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9796 cCE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9797 cCE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9798 cCE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9799 cCE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9800 cCE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9801 cCE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9802 cCE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9803 cCE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9804 cCE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9805 cCE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9806 cCE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9807 cCE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9808 cCE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9809 cCE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9810 cCE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9811 cCE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9812 cCE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9813 cCE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9814 cCE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9815 cCE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9816 cCE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9817 cCE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9818 cCE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9819 cCE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9820 cCE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9821 cCE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9822 cCE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9823 cCE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9824 cCE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9825 cCE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9826 cCE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9827 cCE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9828 cCE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9829 cCE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9830 cCE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9831 cCE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9832 cCE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9833 cCE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9834 cCE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9835 cCE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9836 cCE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9837 cCE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9838 cCE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9839 cCE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9840 cCE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9841 cCE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9842 cCE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9843 cCE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9844 cCE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9845 cCE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9846 cCE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9847 cCE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9848 cCE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9849 cCE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9850 cCE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9851 cCE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9852 cCE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9853 cCE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9854 cCE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9855 cCE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9856 cCE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9857 cCE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9858 cCE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9859 cCE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9860 cCE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9861 cCE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9862 cCE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9863 cCE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9864 cCE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9865 cCE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9866 cCE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9869 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
9870 cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9871 cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9872 cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9873 cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9874 cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9875 cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9876 cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9877 cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9878 cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9879 cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9880 cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9881 cCE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9882 cCE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9883 cCE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9884 cCE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9885 cCE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9886 cCE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9887 cCE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9888 cCE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9889 cCE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9890 cCE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9891 cCE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9892 cCE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9893 cCE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9894 cCE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9895 cCE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9896 cCE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9897 cCE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9898 cCE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9899 cCE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9900 cCE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9901 cCE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9902 cCE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9903 cCE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9904 cCE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9905 cCE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9906 cCE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9907 cCE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9908 cCE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9909 cCE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9910 cCE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9911 cCE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9912 cCE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9913 cCE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9914 cCE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9915 cCE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9916 cCE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9917 cCE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9918 cCE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9919 cCE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9920 cCE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9921 cCE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9922 cCE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9923 cCE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9924 cCE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9925 cCE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9926 cCE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9927 cCE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9928 cCE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9929 cCE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9930 cCE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9931 cCE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9932 cCE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9933 cCE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9934 cCE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9935 cCE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9936 cCE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9937 cCE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9938 cCE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9939 cCE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9940 cCE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9941 cCE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9942 cCE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9943 cCE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9944 cCE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9945 cCE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9948 #undef THUMB_VARIANT
9971 /* MD interface: bits in the object file. */
9973 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9974 for use in the a.out file, and stores them in the array pointed to by buf.
9975 This knows about the endian-ness of the target machine and does
9976 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9977 2 (short) and 4 (long) Floating numbers are put out as a series of
9978 LITTLENUMS (shorts, here at least). */
9981 md_number_to_chars (char * buf, valueT val, int n)
9983 if (target_big_endian)
9984 number_to_chars_bigendian (buf, val, n);
9986 number_to_chars_littleendian (buf, val, n);
9990 md_chars_to_number (char * buf, int n)
9993 unsigned char * where = (unsigned char *) buf;
9995 if (target_big_endian)
10000 result |= (*where++ & 255);
10008 result |= (where[n] & 255);
10015 /* MD interface: Sections. */
10017 /* Estimate the size of a frag before relaxing. Assume everything fits in
10021 md_estimate_size_before_relax (fragS * fragp,
10022 segT segtype ATTRIBUTE_UNUSED)
10028 /* Convert a machine dependent frag. */
10031 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
10033 unsigned long insn;
10034 unsigned long old_op;
10042 buf = fragp->fr_literal + fragp->fr_fix;
10044 old_op = bfd_get_16(abfd, buf);
10045 if (fragp->fr_symbol) {
10046 exp.X_op = O_symbol;
10047 exp.X_add_symbol = fragp->fr_symbol;
10049 exp.X_op = O_constant;
10051 exp.X_add_number = fragp->fr_offset;
10052 opcode = fragp->fr_subtype;
10055 case T_MNEM_ldr_pc:
10056 case T_MNEM_ldr_pc2:
10057 case T_MNEM_ldr_sp:
10058 case T_MNEM_str_sp:
10065 if (fragp->fr_var == 4)
10067 insn = THUMB_OP32(opcode);
10068 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
10070 insn |= (old_op & 0x700) << 4;
10074 insn |= (old_op & 7) << 12;
10075 insn |= (old_op & 0x38) << 13;
10077 insn |= 0x00000c00;
10078 put_thumb32_insn (buf, insn);
10079 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10083 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
10085 pc_rel = (opcode == T_MNEM_ldr_pc2);
10088 if (fragp->fr_var == 4)
10090 insn = THUMB_OP32 (opcode);
10091 insn |= (old_op & 0xf0) << 4;
10092 put_thumb32_insn (buf, insn);
10093 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
10097 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10098 exp.X_add_number -= 4;
10106 if (fragp->fr_var == 4)
10108 int r0off = (opcode == T_MNEM_mov
10109 || opcode == T_MNEM_movs) ? 0 : 8;
10110 insn = THUMB_OP32 (opcode);
10111 insn = (insn & 0xe1ffffff) | 0x10000000;
10112 insn |= (old_op & 0x700) << r0off;
10113 put_thumb32_insn (buf, insn);
10114 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10118 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
10123 if (fragp->fr_var == 4)
10125 insn = THUMB_OP32(opcode);
10126 put_thumb32_insn (buf, insn);
10127 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
10130 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
10134 if (fragp->fr_var == 4)
10136 insn = THUMB_OP32(opcode);
10137 insn |= (old_op & 0xf00) << 14;
10138 put_thumb32_insn (buf, insn);
10139 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
10142 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
10145 case T_MNEM_add_sp:
10146 case T_MNEM_add_pc:
10147 case T_MNEM_inc_sp:
10148 case T_MNEM_dec_sp:
10149 if (fragp->fr_var == 4)
10151 /* ??? Choose between add and addw. */
10152 insn = THUMB_OP32 (opcode);
10153 insn |= (old_op & 0xf0) << 4;
10154 put_thumb32_insn (buf, insn);
10155 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10158 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10166 if (fragp->fr_var == 4)
10168 insn = THUMB_OP32 (opcode);
10169 insn |= (old_op & 0xf0) << 4;
10170 insn |= (old_op & 0xf) << 16;
10171 put_thumb32_insn (buf, insn);
10172 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
10175 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
10181 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
10183 fixp->fx_file = fragp->fr_file;
10184 fixp->fx_line = fragp->fr_line;
10185 fragp->fr_fix += fragp->fr_var;
10188 /* Return the size of a relaxable immediate operand instruction.
10189 SHIFT and SIZE specify the form of the allowable immediate. */
10191 relax_immediate (fragS *fragp, int size, int shift)
10197 /* ??? Should be able to do better than this. */
10198 if (fragp->fr_symbol)
10201 low = (1 << shift) - 1;
10202 mask = (1 << (shift + size)) - (1 << shift);
10203 offset = fragp->fr_offset;
10204 /* Force misaligned offsets to 32-bit variant. */
10207 if (offset & ~mask)
10212 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
10215 relax_adr (fragS *fragp, asection *sec)
10220 /* Assume worst case for symbols not known to be in the same section. */
10221 if (!S_IS_DEFINED(fragp->fr_symbol)
10222 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10225 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10226 addr = fragp->fr_address + fragp->fr_fix;
10227 addr = (addr + 4) & ~3;
10228 /* Fix the insn as the 4-byte version if the target address is not
10229 sufficiently aligned. This is prevents an infinite loop when two
10230 instructions have contradictory range/alignment requirements. */
10234 if (val < 0 || val > 1020)
10239 /* Return the size of a relaxable add/sub immediate instruction. */
10241 relax_addsub (fragS *fragp, asection *sec)
10246 buf = fragp->fr_literal + fragp->fr_fix;
10247 op = bfd_get_16(sec->owner, buf);
10248 if ((op & 0xf) == ((op >> 4) & 0xf))
10249 return relax_immediate (fragp, 8, 0);
10251 return relax_immediate (fragp, 3, 0);
10255 /* Return the size of a relaxable branch instruction. BITS is the
10256 size of the offset field in the narrow instruction. */
10259 relax_branch (fragS *fragp, asection *sec, int bits)
10265 /* Assume worst case for symbols not known to be in the same section. */
10266 if (!S_IS_DEFINED(fragp->fr_symbol)
10267 || sec != S_GET_SEGMENT (fragp->fr_symbol))
10270 val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
10271 addr = fragp->fr_address + fragp->fr_fix + 4;
10274 /* Offset is a signed value *2 */
10276 if (val >= limit || val < -limit)
10282 /* Relax a machine dependent frag. This returns the amount by which
10283 the current size of the frag should change. */
10286 arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
10291 oldsize = fragp->fr_var;
10292 switch (fragp->fr_subtype)
10294 case T_MNEM_ldr_pc2:
10295 newsize = relax_adr(fragp, sec);
10297 case T_MNEM_ldr_pc:
10298 case T_MNEM_ldr_sp:
10299 case T_MNEM_str_sp:
10300 newsize = relax_immediate(fragp, 8, 2);
10304 newsize = relax_immediate(fragp, 5, 2);
10308 newsize = relax_immediate(fragp, 5, 1);
10312 newsize = relax_immediate(fragp, 5, 0);
10315 newsize = relax_adr(fragp, sec);
10321 newsize = relax_immediate(fragp, 8, 0);
10324 newsize = relax_branch(fragp, sec, 11);
10327 newsize = relax_branch(fragp, sec, 8);
10329 case T_MNEM_add_sp:
10330 case T_MNEM_add_pc:
10331 newsize = relax_immediate (fragp, 8, 2);
10333 case T_MNEM_inc_sp:
10334 case T_MNEM_dec_sp:
10335 newsize = relax_immediate (fragp, 7, 2);
10341 newsize = relax_addsub (fragp, sec);
10348 fragp->fr_var = -newsize;
10349 md_convert_frag (sec->owner, sec, fragp);
10351 return -(newsize + oldsize);
10353 fragp->fr_var = newsize;
10354 return newsize - oldsize;
10357 /* Round up a section size to the appropriate boundary. */
10360 md_section_align (segT segment ATTRIBUTE_UNUSED,
10366 /* Round all sects to multiple of 4. */
10367 return (size + 3) & ~3;
10371 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
10372 of an rs_align_code fragment. */
10375 arm_handle_align (fragS * fragP)
10377 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
10378 static char const thumb_noop[2] = { 0xc0, 0x46 };
10379 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
10380 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
10382 int bytes, fix, noop_size;
10386 if (fragP->fr_type != rs_align_code)
10389 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
10390 p = fragP->fr_literal + fragP->fr_fix;
10393 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
10394 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
10396 if (fragP->tc_frag_data)
10398 if (target_big_endian)
10399 noop = thumb_bigend_noop;
10402 noop_size = sizeof (thumb_noop);
10406 if (target_big_endian)
10407 noop = arm_bigend_noop;
10410 noop_size = sizeof (arm_noop);
10413 if (bytes & (noop_size - 1))
10415 fix = bytes & (noop_size - 1);
10416 memset (p, 0, fix);
10421 while (bytes >= noop_size)
10423 memcpy (p, noop, noop_size);
10425 bytes -= noop_size;
10429 fragP->fr_fix += fix;
10430 fragP->fr_var = noop_size;
10433 /* Called from md_do_align. Used to create an alignment
10434 frag in a code section. */
10437 arm_frag_align_code (int n, int max)
10441 /* We assume that there will never be a requirement
10442 to support alignments greater than 32 bytes. */
10443 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
10444 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
10446 p = frag_var (rs_align_code,
10447 MAX_MEM_FOR_RS_ALIGN_CODE,
10449 (relax_substateT) max,
10456 /* Perform target specific initialisation of a frag. */
10459 arm_init_frag (fragS * fragP)
10461 /* Record whether this frag is in an ARM or a THUMB area. */
10462 fragP->tc_frag_data = thumb_mode;
10466 /* When we change sections we need to issue a new mapping symbol. */
10469 arm_elf_change_section (void)
10472 segment_info_type *seginfo;
10474 /* Link an unlinked unwind index table section to the .text section. */
10475 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
10476 && elf_linked_to_section (now_seg) == NULL)
10477 elf_linked_to_section (now_seg) = text_section;
10479 if (!SEG_NORMAL (now_seg))
10482 flags = bfd_get_section_flags (stdoutput, now_seg);
10484 /* We can ignore sections that only contain debug info. */
10485 if ((flags & SEC_ALLOC) == 0)
10488 seginfo = seg_info (now_seg);
10489 mapstate = seginfo->tc_segment_info_data.mapstate;
10490 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
10494 arm_elf_section_type (const char * str, size_t len)
10496 if (len == 5 && strncmp (str, "exidx", 5) == 0)
10497 return SHT_ARM_EXIDX;
10502 /* Code to deal with unwinding tables. */
10504 static void add_unwind_adjustsp (offsetT);
10506 /* Cenerate and deferred unwind frame offset. */
10509 flush_pending_unwind (void)
10513 offset = unwind.pending_offset;
10514 unwind.pending_offset = 0;
10516 add_unwind_adjustsp (offset);
10519 /* Add an opcode to this list for this function. Two-byte opcodes should
10520 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
10524 add_unwind_opcode (valueT op, int length)
10526 /* Add any deferred stack adjustment. */
10527 if (unwind.pending_offset)
10528 flush_pending_unwind ();
10530 unwind.sp_restored = 0;
10532 if (unwind.opcode_count + length > unwind.opcode_alloc)
10534 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
10535 if (unwind.opcodes)
10536 unwind.opcodes = xrealloc (unwind.opcodes,
10537 unwind.opcode_alloc);
10539 unwind.opcodes = xmalloc (unwind.opcode_alloc);
10544 unwind.opcodes[unwind.opcode_count] = op & 0xff;
10546 unwind.opcode_count++;
10550 /* Add unwind opcodes to adjust the stack pointer. */
10553 add_unwind_adjustsp (offsetT offset)
10557 if (offset > 0x200)
10559 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
10564 /* Long form: 0xb2, uleb128. */
10565 /* This might not fit in a word so add the individual bytes,
10566 remembering the list is built in reverse order. */
10567 o = (valueT) ((offset - 0x204) >> 2);
10569 add_unwind_opcode (0, 1);
10571 /* Calculate the uleb128 encoding of the offset. */
10575 bytes[n] = o & 0x7f;
10581 /* Add the insn. */
10583 add_unwind_opcode (bytes[n - 1], 1);
10584 add_unwind_opcode (0xb2, 1);
10586 else if (offset > 0x100)
10588 /* Two short opcodes. */
10589 add_unwind_opcode (0x3f, 1);
10590 op = (offset - 0x104) >> 2;
10591 add_unwind_opcode (op, 1);
10593 else if (offset > 0)
10595 /* Short opcode. */
10596 op = (offset - 4) >> 2;
10597 add_unwind_opcode (op, 1);
10599 else if (offset < 0)
10602 while (offset > 0x100)
10604 add_unwind_opcode (0x7f, 1);
10607 op = ((offset - 4) >> 2) | 0x40;
10608 add_unwind_opcode (op, 1);
10612 /* Finish the list of unwind opcodes for this function. */
10614 finish_unwind_opcodes (void)
10618 if (unwind.fp_used)
10620 /* Adjust sp as neccessary. */
10621 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
10622 flush_pending_unwind ();
10624 /* After restoring sp from the frame pointer. */
10625 op = 0x90 | unwind.fp_reg;
10626 add_unwind_opcode (op, 1);
10629 flush_pending_unwind ();
10633 /* Start an exception table entry. If idx is nonzero this is an index table
10637 start_unwind_section (const segT text_seg, int idx)
10639 const char * text_name;
10640 const char * prefix;
10641 const char * prefix_once;
10642 const char * group_name;
10646 size_t sec_name_len;
10653 prefix = ELF_STRING_ARM_unwind;
10654 prefix_once = ELF_STRING_ARM_unwind_once;
10655 type = SHT_ARM_EXIDX;
10659 prefix = ELF_STRING_ARM_unwind_info;
10660 prefix_once = ELF_STRING_ARM_unwind_info_once;
10661 type = SHT_PROGBITS;
10664 text_name = segment_name (text_seg);
10665 if (streq (text_name, ".text"))
10668 if (strncmp (text_name, ".gnu.linkonce.t.",
10669 strlen (".gnu.linkonce.t.")) == 0)
10671 prefix = prefix_once;
10672 text_name += strlen (".gnu.linkonce.t.");
10675 prefix_len = strlen (prefix);
10676 text_len = strlen (text_name);
10677 sec_name_len = prefix_len + text_len;
10678 sec_name = xmalloc (sec_name_len + 1);
10679 memcpy (sec_name, prefix, prefix_len);
10680 memcpy (sec_name + prefix_len, text_name, text_len);
10681 sec_name[prefix_len + text_len] = '\0';
10687 /* Handle COMDAT group. */
10688 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
10690 group_name = elf_group_name (text_seg);
10691 if (group_name == NULL)
10693 as_bad ("Group section `%s' has no group signature",
10694 segment_name (text_seg));
10695 ignore_rest_of_line ();
10698 flags |= SHF_GROUP;
10702 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
10704 /* Set the setion link for index tables. */
10706 elf_linked_to_section (now_seg) = text_seg;
10710 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
10711 personality routine data. Returns zero, or the index table value for
10712 and inline entry. */
10715 create_unwind_entry (int have_data)
10720 /* The current word of data. */
10722 /* The number of bytes left in this word. */
10725 finish_unwind_opcodes ();
10727 /* Remember the current text section. */
10728 unwind.saved_seg = now_seg;
10729 unwind.saved_subseg = now_subseg;
10731 start_unwind_section (now_seg, 0);
10733 if (unwind.personality_routine == NULL)
10735 if (unwind.personality_index == -2)
10738 as_bad (_("handerdata in cantunwind frame"));
10739 return 1; /* EXIDX_CANTUNWIND. */
10742 /* Use a default personality routine if none is specified. */
10743 if (unwind.personality_index == -1)
10745 if (unwind.opcode_count > 3)
10746 unwind.personality_index = 1;
10748 unwind.personality_index = 0;
10751 /* Space for the personality routine entry. */
10752 if (unwind.personality_index == 0)
10754 if (unwind.opcode_count > 3)
10755 as_bad (_("too many unwind opcodes for personality routine 0"));
10759 /* All the data is inline in the index table. */
10762 while (unwind.opcode_count > 0)
10764 unwind.opcode_count--;
10765 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10769 /* Pad with "finish" opcodes. */
10771 data = (data << 8) | 0xb0;
10778 /* We get two opcodes "free" in the first word. */
10779 size = unwind.opcode_count - 2;
10782 /* An extra byte is required for the opcode count. */
10783 size = unwind.opcode_count + 1;
10785 size = (size + 3) >> 2;
10787 as_bad (_("too many unwind opcodes"));
10789 frag_align (2, 0, 0);
10790 record_alignment (now_seg, 2);
10791 unwind.table_entry = expr_build_dot ();
10793 /* Allocate the table entry. */
10794 ptr = frag_more ((size << 2) + 4);
10795 where = frag_now_fix () - ((size << 2) + 4);
10797 switch (unwind.personality_index)
10800 /* ??? Should this be a PLT generating relocation? */
10801 /* Custom personality routine. */
10802 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
10803 BFD_RELOC_ARM_PREL31);
10808 /* Set the first byte to the number of additional words. */
10813 /* ABI defined personality routines. */
10815 /* Three opcodes bytes are packed into the first word. */
10822 /* The size and first two opcode bytes go in the first word. */
10823 data = ((0x80 + unwind.personality_index) << 8) | size;
10828 /* Should never happen. */
10832 /* Pack the opcodes into words (MSB first), reversing the list at the same
10834 while (unwind.opcode_count > 0)
10838 md_number_to_chars (ptr, data, 4);
10843 unwind.opcode_count--;
10845 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
10848 /* Finish off the last word. */
10851 /* Pad with "finish" opcodes. */
10853 data = (data << 8) | 0xb0;
10855 md_number_to_chars (ptr, data, 4);
10860 /* Add an empty descriptor if there is no user-specified data. */
10861 ptr = frag_more (4);
10862 md_number_to_chars (ptr, 0, 4);
10868 /* Convert REGNAME to a DWARF-2 register number. */
10871 tc_arm_regname_to_dw2regnum (const char *regname)
10873 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
10881 /* Initialize the DWARF-2 unwind information for this procedure. */
10884 tc_arm_frame_initial_instructions (void)
10886 cfi_add_CFA_def_cfa (REG_SP, 0);
10888 #endif /* OBJ_ELF */
10891 /* MD interface: Symbol and relocation handling. */
10893 /* Return the address within the segment that a PC-relative fixup is
10894 relative to. For ARM, PC-relative fixups applied to instructions
10895 are generally relative to the location of the fixup plus 8 bytes.
10896 Thumb branches are offset by 4, and Thumb loads relative to PC
10897 require special handling. */
10900 md_pcrel_from_section (fixS * fixP, segT seg)
10902 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10904 /* If this is pc-relative and we are going to emit a relocation
10905 then we just want to put out any pipeline compensation that the linker
10906 will need. Otherwise we want to use the calculated base. */
10908 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10909 || arm_force_relocation (fixP)))
10912 switch (fixP->fx_r_type)
10914 /* PC relative addressing on the Thumb is slightly odd as the
10915 bottom two bits of the PC are forced to zero for the
10916 calculation. This happens *after* application of the
10917 pipeline offset. However, Thumb adrl already adjusts for
10918 this, so we need not do it again. */
10919 case BFD_RELOC_ARM_THUMB_ADD:
10922 case BFD_RELOC_ARM_THUMB_OFFSET:
10923 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10924 case BFD_RELOC_ARM_T32_ADD_PC12:
10925 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
10926 return (base + 4) & ~3;
10928 /* Thumb branches are simply offset by +4. */
10929 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10930 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10931 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10932 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10933 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10934 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10935 case BFD_RELOC_THUMB_PCREL_BLX:
10938 /* ARM mode branches are offset by +8. However, the Windows CE
10939 loader expects the relocation not to take this into account. */
10940 case BFD_RELOC_ARM_PCREL_BRANCH:
10941 case BFD_RELOC_ARM_PCREL_CALL:
10942 case BFD_RELOC_ARM_PCREL_JUMP:
10943 case BFD_RELOC_ARM_PCREL_BLX:
10944 case BFD_RELOC_ARM_PLT32:
10951 /* ARM mode loads relative to PC are also offset by +8. Unlike
10952 branches, the Windows CE loader *does* expect the relocation
10953 to take this into account. */
10954 case BFD_RELOC_ARM_OFFSET_IMM:
10955 case BFD_RELOC_ARM_OFFSET_IMM8:
10956 case BFD_RELOC_ARM_HWLITERAL:
10957 case BFD_RELOC_ARM_LITERAL:
10958 case BFD_RELOC_ARM_CP_OFF_IMM:
10962 /* Other PC-relative relocations are un-offset. */
10968 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10969 Otherwise we have no need to default values of symbols. */
10972 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
10975 if (name[0] == '_' && name[1] == 'G'
10976 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10980 if (symbol_find (name))
10981 as_bad ("GOT already in the symbol table");
10983 GOT_symbol = symbol_new (name, undefined_section,
10984 (valueT) 0, & zero_address_frag);
10994 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10995 computed as two separate immediate values, added together. We
10996 already know that this value cannot be computed by just one ARM
10999 static unsigned int
11000 validate_immediate_twopart (unsigned int val,
11001 unsigned int * highpart)
11006 for (i = 0; i < 32; i += 2)
11007 if (((a = rotate_left (val, i)) & 0xff) != 0)
11013 * highpart = (a >> 8) | ((i + 24) << 7);
11015 else if (a & 0xff0000)
11017 if (a & 0xff000000)
11019 * highpart = (a >> 16) | ((i + 16) << 7);
11023 assert (a & 0xff000000);
11024 * highpart = (a >> 24) | ((i + 8) << 7);
11027 return (a & 0xff) | (i << 7);
11034 validate_offset_imm (unsigned int val, int hwse)
11036 if ((hwse && val > 255) || val > 4095)
11041 /* Subroutine of md_apply_fix. Do those data_ops which can take a
11042 negative immediate constant by altering the instruction. A bit of
11047 by inverting the second operand, and
11050 by negating the second operand. */
11053 negate_data_op (unsigned long * instruction,
11054 unsigned long value)
11057 unsigned long negated, inverted;
11059 negated = encode_arm_immediate (-value);
11060 inverted = encode_arm_immediate (~value);
11062 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
11065 /* First negates. */
11066 case OPCODE_SUB: /* ADD <-> SUB */
11067 new_inst = OPCODE_ADD;
11072 new_inst = OPCODE_SUB;
11076 case OPCODE_CMP: /* CMP <-> CMN */
11077 new_inst = OPCODE_CMN;
11082 new_inst = OPCODE_CMP;
11086 /* Now Inverted ops. */
11087 case OPCODE_MOV: /* MOV <-> MVN */
11088 new_inst = OPCODE_MVN;
11093 new_inst = OPCODE_MOV;
11097 case OPCODE_AND: /* AND <-> BIC */
11098 new_inst = OPCODE_BIC;
11103 new_inst = OPCODE_AND;
11107 case OPCODE_ADC: /* ADC <-> SBC */
11108 new_inst = OPCODE_SBC;
11113 new_inst = OPCODE_ADC;
11117 /* We cannot do anything. */
11122 if (value == (unsigned) FAIL)
11125 *instruction &= OPCODE_MASK;
11126 *instruction |= new_inst << DATA_OP_SHIFT;
11130 /* Like negate_data_op, but for Thumb-2. */
11132 static unsigned int
11133 thumb32_negate_data_op (offsetT *instruction, offsetT value)
11137 offsetT negated, inverted;
11139 negated = encode_thumb32_immediate (-value);
11140 inverted = encode_thumb32_immediate (~value);
11142 rd = (*instruction >> 8) & 0xf;
11143 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
11146 /* ADD <-> SUB. Includes CMP <-> CMN. */
11147 case T2_OPCODE_SUB:
11148 new_inst = T2_OPCODE_ADD;
11152 case T2_OPCODE_ADD:
11153 new_inst = T2_OPCODE_SUB;
11157 /* ORR <-> ORN. Includes MOV <-> MVN. */
11158 case T2_OPCODE_ORR:
11159 new_inst = T2_OPCODE_ORN;
11163 case T2_OPCODE_ORN:
11164 new_inst = T2_OPCODE_ORR;
11168 /* AND <-> BIC. TST has no inverted equivalent. */
11169 case T2_OPCODE_AND:
11170 new_inst = T2_OPCODE_BIC;
11177 case T2_OPCODE_BIC:
11178 new_inst = T2_OPCODE_AND;
11183 case T2_OPCODE_ADC:
11184 new_inst = T2_OPCODE_SBC;
11188 case T2_OPCODE_SBC:
11189 new_inst = T2_OPCODE_ADC;
11193 /* We cannot do anything. */
11201 *instruction &= T2_OPCODE_MASK;
11202 *instruction |= new_inst << T2_DATA_OP_SHIFT;
11206 /* Read a 32-bit thumb instruction from buf. */
11207 static unsigned long
11208 get_thumb32_insn (char * buf)
11210 unsigned long insn;
11211 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
11212 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11218 md_apply_fix (fixS * fixP,
11222 offsetT value = * valP;
11224 unsigned int newimm;
11225 unsigned long temp;
11227 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
11229 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
11231 /* Note whether this will delete the relocation. */
11232 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
11235 /* On a 64-bit host, silently truncate 'value' to 32 bits for
11236 consistency with the behavior on 32-bit hosts. Remember value
11238 value &= 0xffffffff;
11239 value ^= 0x80000000;
11240 value -= 0x80000000;
11243 fixP->fx_addnumber = value;
11245 /* Same treatment for fixP->fx_offset. */
11246 fixP->fx_offset &= 0xffffffff;
11247 fixP->fx_offset ^= 0x80000000;
11248 fixP->fx_offset -= 0x80000000;
11250 switch (fixP->fx_r_type)
11252 case BFD_RELOC_NONE:
11253 /* This will need to go in the object file. */
11257 case BFD_RELOC_ARM_IMMEDIATE:
11258 /* We claim that this fixup has been processed here,
11259 even if in fact we generate an error because we do
11260 not have a reloc for it, so tc_gen_reloc will reject it. */
11264 && ! S_IS_DEFINED (fixP->fx_addsy))
11266 as_bad_where (fixP->fx_file, fixP->fx_line,
11267 _("undefined symbol %s used as an immediate value"),
11268 S_GET_NAME (fixP->fx_addsy));
11272 newimm = encode_arm_immediate (value);
11273 temp = md_chars_to_number (buf, INSN_SIZE);
11275 /* If the instruction will fail, see if we can fix things up by
11276 changing the opcode. */
11277 if (newimm == (unsigned int) FAIL
11278 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
11280 as_bad_where (fixP->fx_file, fixP->fx_line,
11281 _("invalid constant (%lx) after fixup"),
11282 (unsigned long) value);
11286 newimm |= (temp & 0xfffff000);
11287 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11290 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11292 unsigned int highpart = 0;
11293 unsigned int newinsn = 0xe1a00000; /* nop. */
11295 newimm = encode_arm_immediate (value);
11296 temp = md_chars_to_number (buf, INSN_SIZE);
11298 /* If the instruction will fail, see if we can fix things up by
11299 changing the opcode. */
11300 if (newimm == (unsigned int) FAIL
11301 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
11303 /* No ? OK - try using two ADD instructions to generate
11305 newimm = validate_immediate_twopart (value, & highpart);
11307 /* Yes - then make sure that the second instruction is
11309 if (newimm != (unsigned int) FAIL)
11311 /* Still No ? Try using a negated value. */
11312 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
11313 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
11314 /* Otherwise - give up. */
11317 as_bad_where (fixP->fx_file, fixP->fx_line,
11318 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
11323 /* Replace the first operand in the 2nd instruction (which
11324 is the PC) with the destination register. We have
11325 already added in the PC in the first instruction and we
11326 do not want to do it again. */
11327 newinsn &= ~ 0xf0000;
11328 newinsn |= ((newinsn & 0x0f000) << 4);
11331 newimm |= (temp & 0xfffff000);
11332 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
11334 highpart |= (newinsn & 0xfffff000);
11335 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
11339 case BFD_RELOC_ARM_OFFSET_IMM:
11340 case BFD_RELOC_ARM_LITERAL:
11346 if (validate_offset_imm (value, 0) == FAIL)
11348 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
11349 as_bad_where (fixP->fx_file, fixP->fx_line,
11350 _("invalid literal constant: pool needs to be closer"));
11352 as_bad_where (fixP->fx_file, fixP->fx_line,
11353 _("bad immediate value for offset (%ld)"),
11358 newval = md_chars_to_number (buf, INSN_SIZE);
11359 newval &= 0xff7ff000;
11360 newval |= value | (sign ? INDEX_UP : 0);
11361 md_number_to_chars (buf, newval, INSN_SIZE);
11364 case BFD_RELOC_ARM_OFFSET_IMM8:
11365 case BFD_RELOC_ARM_HWLITERAL:
11371 if (validate_offset_imm (value, 1) == FAIL)
11373 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
11374 as_bad_where (fixP->fx_file, fixP->fx_line,
11375 _("invalid literal constant: pool needs to be closer"));
11377 as_bad (_("bad immediate value for half-word offset (%ld)"),
11382 newval = md_chars_to_number (buf, INSN_SIZE);
11383 newval &= 0xff7ff0f0;
11384 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
11385 md_number_to_chars (buf, newval, INSN_SIZE);
11388 case BFD_RELOC_ARM_T32_OFFSET_U8:
11389 if (value < 0 || value > 1020 || value % 4 != 0)
11390 as_bad_where (fixP->fx_file, fixP->fx_line,
11391 _("bad immediate value for offset (%ld)"), (long) value);
11394 newval = md_chars_to_number (buf+2, THUMB_SIZE);
11396 md_number_to_chars (buf+2, newval, THUMB_SIZE);
11399 case BFD_RELOC_ARM_T32_OFFSET_IMM:
11400 /* This is a complicated relocation used for all varieties of Thumb32
11401 load/store instruction with immediate offset:
11403 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
11404 *4, optional writeback(W)
11405 (doubleword load/store)
11407 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
11408 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
11409 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
11410 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
11411 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
11413 Uppercase letters indicate bits that are already encoded at
11414 this point. Lowercase letters are our problem. For the
11415 second block of instructions, the secondary opcode nybble
11416 (bits 8..11) is present, and bit 23 is zero, even if this is
11417 a PC-relative operation. */
11418 newval = md_chars_to_number (buf, THUMB_SIZE);
11420 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
11422 if ((newval & 0xf0000000) == 0xe0000000)
11424 /* Doubleword load/store: 8-bit offset, scaled by 4. */
11426 newval |= (1 << 23);
11429 if (value % 4 != 0)
11431 as_bad_where (fixP->fx_file, fixP->fx_line,
11432 _("offset not a multiple of 4"));
11438 as_bad_where (fixP->fx_file, fixP->fx_line,
11439 _("offset out of range"));
11444 else if ((newval & 0x000f0000) == 0x000f0000)
11446 /* PC-relative, 12-bit offset. */
11448 newval |= (1 << 23);
11451 if (value >= 0xfff)
11453 as_bad_where (fixP->fx_file, fixP->fx_line,
11454 _("offset out of range"));
11459 else if ((newval & 0x00000100) == 0x00000100)
11461 /* Writeback: 8-bit, +/- offset. */
11463 newval |= (1 << 9);
11468 as_bad_where (fixP->fx_file, fixP->fx_line,
11469 _("offset out of range"));
11474 else if ((newval & 0x00000f00) == 0x00000e00)
11476 /* T-instruction: positive 8-bit offset. */
11477 if (value < 0 || value >= 0xff)
11479 as_bad_where (fixP->fx_file, fixP->fx_line,
11480 _("offset out of range"));
11488 /* Positive 12-bit or negative 8-bit offset. */
11492 newval |= (1 << 23);
11502 as_bad_where (fixP->fx_file, fixP->fx_line,
11503 _("offset out of range"));
11510 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
11511 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
11514 case BFD_RELOC_ARM_SHIFT_IMM:
11515 newval = md_chars_to_number (buf, INSN_SIZE);
11516 if (((unsigned long) value) > 32
11518 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
11520 as_bad_where (fixP->fx_file, fixP->fx_line,
11521 _("shift expression is too large"));
11526 /* Shifts of zero must be done as lsl. */
11528 else if (value == 32)
11530 newval &= 0xfffff07f;
11531 newval |= (value & 0x1f) << 7;
11532 md_number_to_chars (buf, newval, INSN_SIZE);
11535 case BFD_RELOC_ARM_T32_IMMEDIATE:
11536 case BFD_RELOC_ARM_T32_IMM12:
11537 case BFD_RELOC_ARM_T32_ADD_PC12:
11538 /* We claim that this fixup has been processed here,
11539 even if in fact we generate an error because we do
11540 not have a reloc for it, so tc_gen_reloc will reject it. */
11544 && ! S_IS_DEFINED (fixP->fx_addsy))
11546 as_bad_where (fixP->fx_file, fixP->fx_line,
11547 _("undefined symbol %s used as an immediate value"),
11548 S_GET_NAME (fixP->fx_addsy));
11552 newval = md_chars_to_number (buf, THUMB_SIZE);
11554 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
11556 /* FUTURE: Implement analogue of negate_data_op for T32. */
11557 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
11559 newimm = encode_thumb32_immediate (value);
11560 if (newimm == (unsigned int) FAIL)
11561 newimm = thumb32_negate_data_op (&newval, value);
11565 /* 12 bit immediate for addw/subw. */
11569 newval ^= 0x00a00000;
11572 newimm = (unsigned int) FAIL;
11577 if (newimm == (unsigned int)FAIL)
11579 as_bad_where (fixP->fx_file, fixP->fx_line,
11580 _("invalid constant (%lx) after fixup"),
11581 (unsigned long) value);
11585 newval |= (newimm & 0x800) << 15;
11586 newval |= (newimm & 0x700) << 4;
11587 newval |= (newimm & 0x0ff);
11589 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
11590 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
11593 case BFD_RELOC_ARM_SMC:
11594 if (((unsigned long) value) > 0xffff)
11595 as_bad_where (fixP->fx_file, fixP->fx_line,
11596 _("invalid smc expression"));
11597 newval = md_chars_to_number (buf, INSN_SIZE);
11598 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
11599 md_number_to_chars (buf, newval, INSN_SIZE);
11602 case BFD_RELOC_ARM_SWI:
11603 if (fixP->tc_fix_data != 0)
11605 if (((unsigned long) value) > 0xff)
11606 as_bad_where (fixP->fx_file, fixP->fx_line,
11607 _("invalid swi expression"));
11608 newval = md_chars_to_number (buf, THUMB_SIZE);
11610 md_number_to_chars (buf, newval, THUMB_SIZE);
11614 if (((unsigned long) value) > 0x00ffffff)
11615 as_bad_where (fixP->fx_file, fixP->fx_line,
11616 _("invalid swi expression"));
11617 newval = md_chars_to_number (buf, INSN_SIZE);
11619 md_number_to_chars (buf, newval, INSN_SIZE);
11623 case BFD_RELOC_ARM_MULTI:
11624 if (((unsigned long) value) > 0xffff)
11625 as_bad_where (fixP->fx_file, fixP->fx_line,
11626 _("invalid expression in load/store multiple"));
11627 newval = value | md_chars_to_number (buf, INSN_SIZE);
11628 md_number_to_chars (buf, newval, INSN_SIZE);
11632 case BFD_RELOC_ARM_PCREL_CALL:
11633 newval = md_chars_to_number (buf, INSN_SIZE);
11634 if ((newval & 0xf0000000) == 0xf0000000)
11638 goto arm_branch_common;
11640 case BFD_RELOC_ARM_PCREL_JUMP:
11641 case BFD_RELOC_ARM_PLT32:
11643 case BFD_RELOC_ARM_PCREL_BRANCH:
11645 goto arm_branch_common;
11647 case BFD_RELOC_ARM_PCREL_BLX:
11650 /* We are going to store value (shifted right by two) in the
11651 instruction, in a 24 bit, signed field. Bits 26 through 32 either
11652 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
11653 also be be clear. */
11655 as_bad_where (fixP->fx_file, fixP->fx_line,
11656 _("misaligned branch destination"));
11657 if ((value & (offsetT)0xfe000000) != (offsetT)0
11658 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
11659 as_bad_where (fixP->fx_file, fixP->fx_line,
11660 _("branch out of range"));
11662 if (fixP->fx_done || !seg->use_rela_p)
11664 newval = md_chars_to_number (buf, INSN_SIZE);
11665 newval |= (value >> 2) & 0x00ffffff;
11666 md_number_to_chars (buf, newval, INSN_SIZE);
11670 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
11671 /* CZB can only branch forward. */
11673 as_bad_where (fixP->fx_file, fixP->fx_line,
11674 _("branch out of range"));
11676 if (fixP->fx_done || !seg->use_rela_p)
11678 newval = md_chars_to_number (buf, THUMB_SIZE);
11679 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
11680 md_number_to_chars (buf, newval, THUMB_SIZE);
11684 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
11685 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
11686 as_bad_where (fixP->fx_file, fixP->fx_line,
11687 _("branch out of range"));
11689 if (fixP->fx_done || !seg->use_rela_p)
11691 newval = md_chars_to_number (buf, THUMB_SIZE);
11692 newval |= (value & 0x1ff) >> 1;
11693 md_number_to_chars (buf, newval, THUMB_SIZE);
11697 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
11698 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
11699 as_bad_where (fixP->fx_file, fixP->fx_line,
11700 _("branch out of range"));
11702 if (fixP->fx_done || !seg->use_rela_p)
11704 newval = md_chars_to_number (buf, THUMB_SIZE);
11705 newval |= (value & 0xfff) >> 1;
11706 md_number_to_chars (buf, newval, THUMB_SIZE);
11710 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11711 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
11712 as_bad_where (fixP->fx_file, fixP->fx_line,
11713 _("conditional branch out of range"));
11715 if (fixP->fx_done || !seg->use_rela_p)
11718 addressT S, J1, J2, lo, hi;
11720 S = (value & 0x00100000) >> 20;
11721 J2 = (value & 0x00080000) >> 19;
11722 J1 = (value & 0x00040000) >> 18;
11723 hi = (value & 0x0003f000) >> 12;
11724 lo = (value & 0x00000ffe) >> 1;
11726 newval = md_chars_to_number (buf, THUMB_SIZE);
11727 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11728 newval |= (S << 10) | hi;
11729 newval2 |= (J1 << 13) | (J2 << 11) | lo;
11730 md_number_to_chars (buf, newval, THUMB_SIZE);
11731 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11735 case BFD_RELOC_THUMB_PCREL_BLX:
11736 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11737 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
11738 as_bad_where (fixP->fx_file, fixP->fx_line,
11739 _("branch out of range"));
11741 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
11742 /* For a BLX instruction, make sure that the relocation is rounded up
11743 to a word boundary. This follows the semantics of the instruction
11744 which specifies that bit 1 of the target address will come from bit
11745 1 of the base address. */
11746 value = (value + 1) & ~ 1;
11748 if (fixP->fx_done || !seg->use_rela_p)
11752 newval = md_chars_to_number (buf, THUMB_SIZE);
11753 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11754 newval |= (value & 0x7fffff) >> 12;
11755 newval2 |= (value & 0xfff) >> 1;
11756 md_number_to_chars (buf, newval, THUMB_SIZE);
11757 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11761 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11762 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
11763 as_bad_where (fixP->fx_file, fixP->fx_line,
11764 _("branch out of range"));
11766 if (fixP->fx_done || !seg->use_rela_p)
11769 addressT S, I1, I2, lo, hi;
11771 S = (value & 0x01000000) >> 24;
11772 I1 = (value & 0x00800000) >> 23;
11773 I2 = (value & 0x00400000) >> 22;
11774 hi = (value & 0x003ff000) >> 12;
11775 lo = (value & 0x00000ffe) >> 1;
11780 newval = md_chars_to_number (buf, THUMB_SIZE);
11781 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
11782 newval |= (S << 10) | hi;
11783 newval2 |= (I1 << 13) | (I2 << 11) | lo;
11784 md_number_to_chars (buf, newval, THUMB_SIZE);
11785 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
11790 if (fixP->fx_done || !seg->use_rela_p)
11791 md_number_to_chars (buf, value, 1);
11795 if (fixP->fx_done || !seg->use_rela_p)
11796 md_number_to_chars (buf, value, 2);
11800 case BFD_RELOC_ARM_TLS_GD32:
11801 case BFD_RELOC_ARM_TLS_LE32:
11802 case BFD_RELOC_ARM_TLS_IE32:
11803 case BFD_RELOC_ARM_TLS_LDM32:
11804 case BFD_RELOC_ARM_TLS_LDO32:
11805 S_SET_THREAD_LOCAL (fixP->fx_addsy);
11808 case BFD_RELOC_ARM_GOT32:
11809 case BFD_RELOC_ARM_GOTOFF:
11810 case BFD_RELOC_ARM_TARGET2:
11811 if (fixP->fx_done || !seg->use_rela_p)
11812 md_number_to_chars (buf, 0, 4);
11816 case BFD_RELOC_RVA:
11818 case BFD_RELOC_ARM_TARGET1:
11819 case BFD_RELOC_ARM_ROSEGREL32:
11820 case BFD_RELOC_ARM_SBREL32:
11821 case BFD_RELOC_32_PCREL:
11822 if (fixP->fx_done || !seg->use_rela_p)
11823 md_number_to_chars (buf, value, 4);
11827 case BFD_RELOC_ARM_PREL31:
11828 if (fixP->fx_done || !seg->use_rela_p)
11830 newval = md_chars_to_number (buf, 4) & 0x80000000;
11831 if ((value ^ (value >> 1)) & 0x40000000)
11833 as_bad_where (fixP->fx_file, fixP->fx_line,
11834 _("rel31 relocation overflow"));
11836 newval |= value & 0x7fffffff;
11837 md_number_to_chars (buf, newval, 4);
11842 case BFD_RELOC_ARM_CP_OFF_IMM:
11843 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
11844 if (value < -1023 || value > 1023 || (value & 3))
11845 as_bad_where (fixP->fx_file, fixP->fx_line,
11846 _("co-processor offset out of range"));
11851 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11852 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11853 newval = md_chars_to_number (buf, INSN_SIZE);
11855 newval = get_thumb32_insn (buf);
11856 newval &= 0xff7fff00;
11857 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
11859 newval &= ~WRITE_BACK;
11860 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
11861 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
11862 md_number_to_chars (buf, newval, INSN_SIZE);
11864 put_thumb32_insn (buf, newval);
11867 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
11868 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
11869 if (value < -255 || value > 255)
11870 as_bad_where (fixP->fx_file, fixP->fx_line,
11871 _("co-processor offset out of range"));
11872 goto cp_off_common;
11874 case BFD_RELOC_ARM_THUMB_OFFSET:
11875 newval = md_chars_to_number (buf, THUMB_SIZE);
11876 /* Exactly what ranges, and where the offset is inserted depends
11877 on the type of instruction, we can establish this from the
11879 switch (newval >> 12)
11881 case 4: /* PC load. */
11882 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
11883 forced to zero for these loads; md_pcrel_from has already
11884 compensated for this. */
11886 as_bad_where (fixP->fx_file, fixP->fx_line,
11887 _("invalid offset, target not word aligned (0x%08lX)"),
11888 (((unsigned long) fixP->fx_frag->fr_address
11889 + (unsigned long) fixP->fx_where) & ~3)
11890 + (unsigned long) value);
11892 if (value & ~0x3fc)
11893 as_bad_where (fixP->fx_file, fixP->fx_line,
11894 _("invalid offset, value too big (0x%08lX)"),
11897 newval |= value >> 2;
11900 case 9: /* SP load/store. */
11901 if (value & ~0x3fc)
11902 as_bad_where (fixP->fx_file, fixP->fx_line,
11903 _("invalid offset, value too big (0x%08lX)"),
11905 newval |= value >> 2;
11908 case 6: /* Word load/store. */
11910 as_bad_where (fixP->fx_file, fixP->fx_line,
11911 _("invalid offset, value too big (0x%08lX)"),
11913 newval |= value << 4; /* 6 - 2. */
11916 case 7: /* Byte load/store. */
11918 as_bad_where (fixP->fx_file, fixP->fx_line,
11919 _("invalid offset, value too big (0x%08lX)"),
11921 newval |= value << 6;
11924 case 8: /* Halfword load/store. */
11926 as_bad_where (fixP->fx_file, fixP->fx_line,
11927 _("invalid offset, value too big (0x%08lX)"),
11929 newval |= value << 5; /* 6 - 1. */
11933 as_bad_where (fixP->fx_file, fixP->fx_line,
11934 "Unable to process relocation for thumb opcode: %lx",
11935 (unsigned long) newval);
11938 md_number_to_chars (buf, newval, THUMB_SIZE);
11941 case BFD_RELOC_ARM_THUMB_ADD:
11942 /* This is a complicated relocation, since we use it for all of
11943 the following immediate relocations:
11947 9bit ADD/SUB SP word-aligned
11948 10bit ADD PC/SP word-aligned
11950 The type of instruction being processed is encoded in the
11957 newval = md_chars_to_number (buf, THUMB_SIZE);
11959 int rd = (newval >> 4) & 0xf;
11960 int rs = newval & 0xf;
11961 int subtract = !!(newval & 0x8000);
11963 /* Check for HI regs, only very restricted cases allowed:
11964 Adjusting SP, and using PC or SP to get an address. */
11965 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
11966 || (rs > 7 && rs != REG_SP && rs != REG_PC))
11967 as_bad_where (fixP->fx_file, fixP->fx_line,
11968 _("invalid Hi register with immediate"));
11970 /* If value is negative, choose the opposite instruction. */
11974 subtract = !subtract;
11976 as_bad_where (fixP->fx_file, fixP->fx_line,
11977 _("immediate value out of range"));
11982 if (value & ~0x1fc)
11983 as_bad_where (fixP->fx_file, fixP->fx_line,
11984 _("invalid immediate for stack address calculation"));
11985 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11986 newval |= value >> 2;
11988 else if (rs == REG_PC || rs == REG_SP)
11990 if (subtract || value & ~0x3fc)
11991 as_bad_where (fixP->fx_file, fixP->fx_line,
11992 _("invalid immediate for address calculation (value = 0x%08lX)"),
11993 (unsigned long) value);
11994 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11996 newval |= value >> 2;
12001 as_bad_where (fixP->fx_file, fixP->fx_line,
12002 _("immediate value out of range"));
12003 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
12004 newval |= (rd << 8) | value;
12009 as_bad_where (fixP->fx_file, fixP->fx_line,
12010 _("immediate value out of range"));
12011 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
12012 newval |= rd | (rs << 3) | (value << 6);
12015 md_number_to_chars (buf, newval, THUMB_SIZE);
12018 case BFD_RELOC_ARM_THUMB_IMM:
12019 newval = md_chars_to_number (buf, THUMB_SIZE);
12020 if (value < 0 || value > 255)
12021 as_bad_where (fixP->fx_file, fixP->fx_line,
12022 _("invalid immediate: %ld is too large"),
12025 md_number_to_chars (buf, newval, THUMB_SIZE);
12028 case BFD_RELOC_ARM_THUMB_SHIFT:
12029 /* 5bit shift value (0..32). LSL cannot take 32. */
12030 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
12031 temp = newval & 0xf800;
12032 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
12033 as_bad_where (fixP->fx_file, fixP->fx_line,
12034 _("invalid shift value: %ld"), (long) value);
12035 /* Shifts of zero must be encoded as LSL. */
12037 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
12038 /* Shifts of 32 are encoded as zero. */
12039 else if (value == 32)
12041 newval |= value << 6;
12042 md_number_to_chars (buf, newval, THUMB_SIZE);
12045 case BFD_RELOC_VTABLE_INHERIT:
12046 case BFD_RELOC_VTABLE_ENTRY:
12050 case BFD_RELOC_UNUSED:
12052 as_bad_where (fixP->fx_file, fixP->fx_line,
12053 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
12057 /* Translate internal representation of relocation info to BFD target
12061 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
12065 bfd_reloc_code_real_type code;
12067 reloc = xmalloc (sizeof (arelent));
12069 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
12070 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
12071 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
12073 if (fixp->fx_pcrel)
12074 fixp->fx_offset = reloc->address;
12075 reloc->addend = fixp->fx_offset;
12077 switch (fixp->fx_r_type)
12080 if (fixp->fx_pcrel)
12082 code = BFD_RELOC_8_PCREL;
12087 if (fixp->fx_pcrel)
12089 code = BFD_RELOC_16_PCREL;
12094 if (fixp->fx_pcrel)
12096 code = BFD_RELOC_32_PCREL;
12100 case BFD_RELOC_NONE:
12101 case BFD_RELOC_ARM_PCREL_BRANCH:
12102 case BFD_RELOC_ARM_PCREL_BLX:
12103 case BFD_RELOC_RVA:
12104 case BFD_RELOC_THUMB_PCREL_BRANCH7:
12105 case BFD_RELOC_THUMB_PCREL_BRANCH9:
12106 case BFD_RELOC_THUMB_PCREL_BRANCH12:
12107 case BFD_RELOC_THUMB_PCREL_BRANCH20:
12108 case BFD_RELOC_THUMB_PCREL_BRANCH23:
12109 case BFD_RELOC_THUMB_PCREL_BRANCH25:
12110 case BFD_RELOC_THUMB_PCREL_BLX:
12111 case BFD_RELOC_VTABLE_ENTRY:
12112 case BFD_RELOC_VTABLE_INHERIT:
12113 code = fixp->fx_r_type;
12116 case BFD_RELOC_ARM_LITERAL:
12117 case BFD_RELOC_ARM_HWLITERAL:
12118 /* If this is called then the a literal has
12119 been referenced across a section boundary. */
12120 as_bad_where (fixp->fx_file, fixp->fx_line,
12121 _("literal referenced across section boundary"));
12125 case BFD_RELOC_ARM_GOT32:
12126 case BFD_RELOC_ARM_GOTOFF:
12127 case BFD_RELOC_ARM_PLT32:
12128 case BFD_RELOC_ARM_TARGET1:
12129 case BFD_RELOC_ARM_ROSEGREL32:
12130 case BFD_RELOC_ARM_SBREL32:
12131 case BFD_RELOC_ARM_PREL31:
12132 case BFD_RELOC_ARM_TARGET2:
12133 case BFD_RELOC_ARM_TLS_LE32:
12134 case BFD_RELOC_ARM_TLS_LDO32:
12135 case BFD_RELOC_ARM_PCREL_CALL:
12136 case BFD_RELOC_ARM_PCREL_JUMP:
12137 code = fixp->fx_r_type;
12140 case BFD_RELOC_ARM_TLS_GD32:
12141 case BFD_RELOC_ARM_TLS_IE32:
12142 case BFD_RELOC_ARM_TLS_LDM32:
12143 /* BFD will include the symbol's address in the addend.
12144 But we don't want that, so subtract it out again here. */
12145 if (!S_IS_COMMON (fixp->fx_addsy))
12146 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
12147 code = fixp->fx_r_type;
12151 case BFD_RELOC_ARM_IMMEDIATE:
12152 as_bad_where (fixp->fx_file, fixp->fx_line,
12153 _("internal relocation (type: IMMEDIATE) not fixed up"));
12156 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
12157 as_bad_where (fixp->fx_file, fixp->fx_line,
12158 _("ADRL used for a symbol not defined in the same file"));
12161 case BFD_RELOC_ARM_OFFSET_IMM:
12162 if (fixp->fx_addsy != NULL
12163 && !S_IS_DEFINED (fixp->fx_addsy)
12164 && S_IS_LOCAL (fixp->fx_addsy))
12166 as_bad_where (fixp->fx_file, fixp->fx_line,
12167 _("undefined local label `%s'"),
12168 S_GET_NAME (fixp->fx_addsy));
12172 as_bad_where (fixp->fx_file, fixp->fx_line,
12173 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
12180 switch (fixp->fx_r_type)
12182 case BFD_RELOC_NONE: type = "NONE"; break;
12183 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
12184 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
12185 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
12186 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
12187 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
12188 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
12189 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
12190 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
12191 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
12192 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
12193 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
12194 default: type = _("<unknown>"); break;
12196 as_bad_where (fixp->fx_file, fixp->fx_line,
12197 _("cannot represent %s relocation in this object file format"),
12204 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
12206 && fixp->fx_addsy == GOT_symbol)
12208 code = BFD_RELOC_ARM_GOTPC;
12209 reloc->addend = fixp->fx_offset = reloc->address;
12213 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
12215 if (reloc->howto == NULL)
12217 as_bad_where (fixp->fx_file, fixp->fx_line,
12218 _("cannot represent %s relocation in this object file format"),
12219 bfd_get_reloc_code_name (code));
12223 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
12224 vtable entry to be used in the relocation's section offset. */
12225 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12226 reloc->address = fixp->fx_offset;
12231 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
12234 cons_fix_new_arm (fragS * frag,
12239 bfd_reloc_code_real_type type;
12243 FIXME: @@ Should look at CPU word size. */
12247 type = BFD_RELOC_8;
12250 type = BFD_RELOC_16;
12254 type = BFD_RELOC_32;
12257 type = BFD_RELOC_64;
12261 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
12264 #if defined OBJ_COFF || defined OBJ_ELF
12266 arm_validate_fix (fixS * fixP)
12268 /* If the destination of the branch is a defined symbol which does not have
12269 the THUMB_FUNC attribute, then we must be calling a function which has
12270 the (interfacearm) attribute. We look for the Thumb entry point to that
12271 function and change the branch to refer to that function instead. */
12272 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
12273 && fixP->fx_addsy != NULL
12274 && S_IS_DEFINED (fixP->fx_addsy)
12275 && ! THUMB_IS_FUNC (fixP->fx_addsy))
12277 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
12283 arm_force_relocation (struct fix * fixp)
12285 #if defined (OBJ_COFF) && defined (TE_PE)
12286 if (fixp->fx_r_type == BFD_RELOC_RVA)
12290 /* Resolve these relocations even if the symbol is extern or weak. */
12291 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
12292 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
12293 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
12294 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
12295 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
12296 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
12299 return generic_force_reloc (fixp);
12303 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
12304 local labels from being added to the output symbol table when they
12305 are used with the ADRL pseudo op. The ADRL relocation should always
12306 be resolved before the binbary is emitted, so it is safe to say that
12307 it is adjustable. */
12310 arm_fix_adjustable (fixS * fixP)
12312 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
12319 /* Relocations against Thumb function names must be left unadjusted,
12320 so that the linker can use this information to correctly set the
12321 bottom bit of their addresses. The MIPS version of this function
12322 also prevents relocations that are mips-16 specific, but I do not
12323 know why it does this.
12326 There is one other problem that ought to be addressed here, but
12327 which currently is not: Taking the address of a label (rather
12328 than a function) and then later jumping to that address. Such
12329 addresses also ought to have their bottom bit set (assuming that
12330 they reside in Thumb code), but at the moment they will not. */
12333 arm_fix_adjustable (fixS * fixP)
12335 if (fixP->fx_addsy == NULL)
12338 if (THUMB_IS_FUNC (fixP->fx_addsy)
12339 && fixP->fx_subsy == NULL)
12342 /* We need the symbol name for the VTABLE entries. */
12343 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12344 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
12347 /* Don't allow symbols to be discarded on GOT related relocs. */
12348 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
12349 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
12350 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
12351 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
12352 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
12353 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
12354 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
12355 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
12356 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
12363 elf32_arm_target_format (void)
12366 return (target_big_endian
12367 ? "elf32-bigarm-symbian"
12368 : "elf32-littlearm-symbian");
12369 #elif defined (TE_VXWORKS)
12370 return (target_big_endian
12371 ? "elf32-bigarm-vxworks"
12372 : "elf32-littlearm-vxworks");
12374 if (target_big_endian)
12375 return "elf32-bigarm";
12377 return "elf32-littlearm";
12382 armelf_frob_symbol (symbolS * symp,
12385 elf_frob_symbol (symp, puntp);
12389 /* MD interface: Finalization. */
12391 /* A good place to do this, although this was probably not intended
12392 for this kind of use. We need to dump the literal pool before
12393 references are made to a null symbol pointer. */
12398 literal_pool * pool;
12400 for (pool = list_of_pools; pool; pool = pool->next)
12402 /* Put it at the end of the relevent section. */
12403 subseg_set (pool->section, pool->sub_section);
12405 arm_elf_change_section ();
12411 /* Adjust the symbol table. This marks Thumb symbols as distinct from
12415 arm_adjust_symtab (void)
12420 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12422 if (ARM_IS_THUMB (sym))
12424 if (THUMB_IS_FUNC (sym))
12426 /* Mark the symbol as a Thumb function. */
12427 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
12428 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
12429 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
12431 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
12432 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
12434 as_bad (_("%s: unexpected function type: %d"),
12435 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
12437 else switch (S_GET_STORAGE_CLASS (sym))
12440 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
12443 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
12446 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
12454 if (ARM_IS_INTERWORK (sym))
12455 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
12462 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
12464 if (ARM_IS_THUMB (sym))
12466 elf_symbol_type * elf_sym;
12468 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
12469 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
12471 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
12473 /* If it's a .thumb_func, declare it as so,
12474 otherwise tag label as .code 16. */
12475 if (THUMB_IS_FUNC (sym))
12476 elf_sym->internal_elf_sym.st_info =
12477 ELF_ST_INFO (bind, STT_ARM_TFUNC);
12479 elf_sym->internal_elf_sym.st_info =
12480 ELF_ST_INFO (bind, STT_ARM_16BIT);
12487 /* MD interface: Initialization. */
12490 set_constant_flonums (void)
12494 for (i = 0; i < NUM_FLOAT_VALS; i++)
12495 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
12505 if ( (arm_ops_hsh = hash_new ()) == NULL
12506 || (arm_cond_hsh = hash_new ()) == NULL
12507 || (arm_shift_hsh = hash_new ()) == NULL
12508 || (arm_psr_hsh = hash_new ()) == NULL
12509 || (arm_reg_hsh = hash_new ()) == NULL
12510 || (arm_reloc_hsh = hash_new ()) == NULL)
12511 as_fatal (_("virtual memory exhausted"));
12513 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
12514 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
12515 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
12516 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
12517 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
12518 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
12519 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
12520 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
12521 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
12522 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
12524 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
12525 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
12528 set_constant_flonums ();
12530 /* Set the cpu variant based on the command-line options. We prefer
12531 -mcpu= over -march= if both are set (as for GCC); and we prefer
12532 -mfpu= over any other way of setting the floating point unit.
12533 Use of legacy options with new options are faulted. */
12536 if (mcpu_cpu_opt || march_cpu_opt)
12537 as_bad (_("use of old and new-style options to set CPU type"));
12539 mcpu_cpu_opt = legacy_cpu;
12541 else if (!mcpu_cpu_opt)
12542 mcpu_cpu_opt = march_cpu_opt;
12547 as_bad (_("use of old and new-style options to set FPU type"));
12549 mfpu_opt = legacy_fpu;
12551 else if (!mfpu_opt)
12553 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
12554 /* Some environments specify a default FPU. If they don't, infer it
12555 from the processor. */
12557 mfpu_opt = mcpu_fpu_opt;
12559 mfpu_opt = march_fpu_opt;
12561 mfpu_opt = &fpu_default;
12568 mfpu_opt = &fpu_default;
12569 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
12570 mfpu_opt = &fpu_arch_vfp_v2;
12572 mfpu_opt = &fpu_arch_fpa;
12578 mcpu_cpu_opt = &cpu_default;
12579 selected_cpu = cpu_default;
12583 selected_cpu = *mcpu_cpu_opt;
12585 mcpu_cpu_opt = &arm_arch_any;
12588 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
12590 arm_arch_used = thumb_arch_used = arm_arch_none;
12592 #if defined OBJ_COFF || defined OBJ_ELF
12594 unsigned int flags = 0;
12596 #if defined OBJ_ELF
12597 flags = meabi_flags;
12599 switch (meabi_flags)
12601 case EF_ARM_EABI_UNKNOWN:
12603 /* Set the flags in the private structure. */
12604 if (uses_apcs_26) flags |= F_APCS26;
12605 if (support_interwork) flags |= F_INTERWORK;
12606 if (uses_apcs_float) flags |= F_APCS_FLOAT;
12607 if (pic_code) flags |= F_PIC;
12608 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
12609 flags |= F_SOFT_FLOAT;
12611 switch (mfloat_abi_opt)
12613 case ARM_FLOAT_ABI_SOFT:
12614 case ARM_FLOAT_ABI_SOFTFP:
12615 flags |= F_SOFT_FLOAT;
12618 case ARM_FLOAT_ABI_HARD:
12619 if (flags & F_SOFT_FLOAT)
12620 as_bad (_("hard-float conflicts with specified fpu"));
12624 /* Using pure-endian doubles (even if soft-float). */
12625 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
12626 flags |= F_VFP_FLOAT;
12628 #if defined OBJ_ELF
12629 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
12630 flags |= EF_ARM_MAVERICK_FLOAT;
12633 case EF_ARM_EABI_VER4:
12634 /* No additional flags to set. */
12641 bfd_set_private_flags (stdoutput, flags);
12643 /* We have run out flags in the COFF header to encode the
12644 status of ATPCS support, so instead we create a dummy,
12645 empty, debug section called .arm.atpcs. */
12650 sec = bfd_make_section (stdoutput, ".arm.atpcs");
12654 bfd_set_section_flags
12655 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
12656 bfd_set_section_size (stdoutput, sec, 0);
12657 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
12663 /* Record the CPU type as well. */
12664 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
12665 mach = bfd_mach_arm_iWMMXt;
12666 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
12667 mach = bfd_mach_arm_XScale;
12668 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
12669 mach = bfd_mach_arm_ep9312;
12670 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
12671 mach = bfd_mach_arm_5TE;
12672 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
12674 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12675 mach = bfd_mach_arm_5T;
12677 mach = bfd_mach_arm_5;
12679 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
12681 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
12682 mach = bfd_mach_arm_4T;
12684 mach = bfd_mach_arm_4;
12686 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
12687 mach = bfd_mach_arm_3M;
12688 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
12689 mach = bfd_mach_arm_3;
12690 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
12691 mach = bfd_mach_arm_2a;
12692 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
12693 mach = bfd_mach_arm_2;
12695 mach = bfd_mach_arm_unknown;
12697 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
12700 /* Command line processing. */
12703 Invocation line includes a switch not recognized by the base assembler.
12704 See if it's a processor-specific option.
12706 This routine is somewhat complicated by the need for backwards
12707 compatibility (since older releases of gcc can't be changed).
12708 The new options try to make the interface as compatible as
12711 New options (supported) are:
12713 -mcpu=<cpu name> Assemble for selected processor
12714 -march=<architecture name> Assemble for selected architecture
12715 -mfpu=<fpu architecture> Assemble for selected FPU.
12716 -EB/-mbig-endian Big-endian
12717 -EL/-mlittle-endian Little-endian
12718 -k Generate PIC code
12719 -mthumb Start in Thumb mode
12720 -mthumb-interwork Code supports ARM/Thumb interworking
12722 For now we will also provide support for:
12724 -mapcs-32 32-bit Program counter
12725 -mapcs-26 26-bit Program counter
12726 -macps-float Floats passed in FP registers
12727 -mapcs-reentrant Reentrant code
12729 (sometime these will probably be replaced with -mapcs=<list of options>
12730 and -matpcs=<list of options>)
12732 The remaining options are only supported for back-wards compatibility.
12733 Cpu variants, the arm part is optional:
12734 -m[arm]1 Currently not supported.
12735 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
12736 -m[arm]3 Arm 3 processor
12737 -m[arm]6[xx], Arm 6 processors
12738 -m[arm]7[xx][t][[d]m] Arm 7 processors
12739 -m[arm]8[10] Arm 8 processors
12740 -m[arm]9[20][tdmi] Arm 9 processors
12741 -mstrongarm[110[0]] StrongARM processors
12742 -mxscale XScale processors
12743 -m[arm]v[2345[t[e]]] Arm architectures
12744 -mall All (except the ARM1)
12746 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
12747 -mfpe-old (No float load/store multiples)
12748 -mvfpxd VFP Single precision
12750 -mno-fpu Disable all floating point instructions
12752 The following CPU names are recognized:
12753 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
12754 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
12755 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
12756 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
12757 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
12758 arm10t arm10e, arm1020t, arm1020e, arm10200e,
12759 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
12763 const char * md_shortopts = "m:k";
12765 #ifdef ARM_BI_ENDIAN
12766 #define OPTION_EB (OPTION_MD_BASE + 0)
12767 #define OPTION_EL (OPTION_MD_BASE + 1)
12769 #if TARGET_BYTES_BIG_ENDIAN
12770 #define OPTION_EB (OPTION_MD_BASE + 0)
12772 #define OPTION_EL (OPTION_MD_BASE + 1)
12776 struct option md_longopts[] =
12779 {"EB", no_argument, NULL, OPTION_EB},
12782 {"EL", no_argument, NULL, OPTION_EL},
12784 {NULL, no_argument, NULL, 0}
12787 size_t md_longopts_size = sizeof (md_longopts);
12789 struct arm_option_table
12791 char *option; /* Option name to match. */
12792 char *help; /* Help information. */
12793 int *var; /* Variable to change. */
12794 int value; /* What to change it to. */
12795 char *deprecated; /* If non-null, print this message. */
12798 struct arm_option_table arm_opts[] =
12800 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
12801 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
12802 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
12803 &support_interwork, 1, NULL},
12804 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
12805 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
12806 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
12808 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
12809 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
12810 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
12811 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
12814 /* These are recognized by the assembler, but have no affect on code. */
12815 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
12816 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
12817 {NULL, NULL, NULL, 0, NULL}
12820 struct arm_legacy_option_table
12822 char *option; /* Option name to match. */
12823 const arm_feature_set **var; /* Variable to change. */
12824 const arm_feature_set value; /* What to change it to. */
12825 char *deprecated; /* If non-null, print this message. */
12828 const struct arm_legacy_option_table arm_legacy_opts[] =
12830 /* DON'T add any new processors to this list -- we want the whole list
12831 to go away... Add them to the processors table instead. */
12832 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12833 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
12834 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12835 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
12836 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12837 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
12838 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12839 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
12840 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12841 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
12842 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12843 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
12844 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12845 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
12846 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12847 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
12848 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12849 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
12850 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12851 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
12852 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12853 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
12854 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12855 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
12856 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12857 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
12858 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12859 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
12860 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12861 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
12862 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12863 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
12864 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12865 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
12866 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12867 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
12868 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12869 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
12870 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12871 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
12872 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12873 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
12874 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12875 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
12876 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12877 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
12878 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12879 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12880 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12881 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
12882 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12883 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
12884 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12885 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
12886 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12887 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
12888 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12889 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
12890 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12891 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
12892 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12893 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
12894 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12895 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
12896 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12897 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
12898 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12899 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
12900 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
12901 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
12902 N_("use -mcpu=strongarm110")},
12903 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
12904 N_("use -mcpu=strongarm1100")},
12905 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
12906 N_("use -mcpu=strongarm1110")},
12907 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
12908 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
12909 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
12911 /* Architecture variants -- don't add any more to this list either. */
12912 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12913 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
12914 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12915 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
12916 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12917 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
12918 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12919 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
12920 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12921 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
12922 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12923 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
12924 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12925 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
12926 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12927 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
12928 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12929 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
12931 /* Floating point variants -- don't add any more to this list either. */
12932 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
12933 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
12934 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
12935 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
12936 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
12938 {NULL, NULL, ARM_ARCH_NONE, NULL}
12941 struct arm_cpu_option_table
12944 const arm_feature_set value;
12945 /* For some CPUs we assume an FPU unless the user explicitly sets
12947 const arm_feature_set default_fpu;
12948 /* The canonical name of the CPU, or NULL to use NAME converted to upper
12950 const char *canonical_name;
12953 /* This list should, at a minimum, contain all the cpu names
12954 recognized by GCC. */
12955 static const struct arm_cpu_option_table arm_cpus[] =
12957 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
12958 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
12959 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
12960 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12961 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
12962 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12963 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12964 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12965 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12966 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12967 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12968 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12969 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12970 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12971 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12972 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
12973 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12974 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12975 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12976 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12977 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12978 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12979 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12980 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12981 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12982 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12983 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12984 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
12985 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12986 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12987 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12988 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12989 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12990 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12991 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12992 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12993 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12994 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
12995 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12996 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
12997 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12998 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
12999 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13000 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
13001 /* For V5 or later processors we default to using VFP; but the user
13002 should really set the FPU type explicitly. */
13003 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13004 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13005 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13006 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
13007 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13008 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13009 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
13010 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13011 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
13012 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
13013 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13014 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13015 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13016 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13017 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13018 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
13019 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
13020 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13021 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
13022 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
13023 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
13024 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
13025 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
13026 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
13027 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
13028 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, NULL},
13029 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, NULL},
13030 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
13031 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
13032 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
13033 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
13034 /* ??? XSCALE is really an architecture. */
13035 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13036 /* ??? iwmmxt is not a processor. */
13037 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
13038 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
13040 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
13041 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
13044 struct arm_arch_option_table
13047 const arm_feature_set value;
13048 const arm_feature_set default_fpu;
13051 /* This list should, at a minimum, contain all the architecture names
13052 recognized by GCC. */
13053 static const struct arm_arch_option_table arm_archs[] =
13055 {"all", ARM_ANY, FPU_ARCH_FPA},
13056 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
13057 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
13058 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
13059 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
13060 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
13061 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
13062 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
13063 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
13064 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
13065 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
13066 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
13067 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
13068 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
13069 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
13070 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
13071 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
13072 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
13073 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
13074 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
13075 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
13076 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
13077 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
13078 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
13079 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
13080 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
13081 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
13082 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
13083 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
13086 /* ISA extensions in the co-processor space. */
13087 struct arm_option_cpu_value_table
13090 const arm_feature_set value;
13093 static const struct arm_option_cpu_value_table arm_extensions[] =
13095 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK)},
13096 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE)},
13097 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT)},
13098 {NULL, ARM_ARCH_NONE}
13101 /* This list should, at a minimum, contain all the fpu names
13102 recognized by GCC. */
13103 static const struct arm_option_cpu_value_table arm_fpus[] =
13105 {"softfpa", FPU_NONE},
13106 {"fpe", FPU_ARCH_FPE},
13107 {"fpe2", FPU_ARCH_FPE},
13108 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
13109 {"fpa", FPU_ARCH_FPA},
13110 {"fpa10", FPU_ARCH_FPA},
13111 {"fpa11", FPU_ARCH_FPA},
13112 {"arm7500fe", FPU_ARCH_FPA},
13113 {"softvfp", FPU_ARCH_VFP},
13114 {"softvfp+vfp", FPU_ARCH_VFP_V2},
13115 {"vfp", FPU_ARCH_VFP_V2},
13116 {"vfp9", FPU_ARCH_VFP_V2},
13117 {"vfp10", FPU_ARCH_VFP_V2},
13118 {"vfp10-r0", FPU_ARCH_VFP_V1},
13119 {"vfpxd", FPU_ARCH_VFP_V1xD},
13120 {"arm1020t", FPU_ARCH_VFP_V1},
13121 {"arm1020e", FPU_ARCH_VFP_V2},
13122 {"arm1136jfs", FPU_ARCH_VFP_V2},
13123 {"arm1136jf-s", FPU_ARCH_VFP_V2},
13124 {"maverick", FPU_ARCH_MAVERICK},
13125 {NULL, ARM_ARCH_NONE}
13128 struct arm_option_value_table
13134 static const struct arm_option_value_table arm_float_abis[] =
13136 {"hard", ARM_FLOAT_ABI_HARD},
13137 {"softfp", ARM_FLOAT_ABI_SOFTFP},
13138 {"soft", ARM_FLOAT_ABI_SOFT},
13143 /* We only know how to output GNU and ver 4 (AAELF) formats. */
13144 static const struct arm_option_value_table arm_eabis[] =
13146 {"gnu", EF_ARM_EABI_UNKNOWN},
13147 {"4", EF_ARM_EABI_VER4},
13152 struct arm_long_option_table
13154 char * option; /* Substring to match. */
13155 char * help; /* Help information. */
13156 int (* func) (char * subopt); /* Function to decode sub-option. */
13157 char * deprecated; /* If non-null, print this message. */
13161 arm_parse_extension (char * str, const arm_feature_set **opt_p)
13163 arm_feature_set *ext_set = xmalloc (sizeof (arm_feature_set));
13165 /* Copy the feature set, so that we can modify it. */
13166 *ext_set = **opt_p;
13169 while (str != NULL && *str != 0)
13171 const struct arm_option_cpu_value_table * opt;
13177 as_bad (_("invalid architectural extension"));
13182 ext = strchr (str, '+');
13185 optlen = ext - str;
13187 optlen = strlen (str);
13191 as_bad (_("missing architectural extension"));
13195 for (opt = arm_extensions; opt->name != NULL; opt++)
13196 if (strncmp (opt->name, str, optlen) == 0)
13198 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
13202 if (opt->name == NULL)
13204 as_bad (_("unknown architectural extnsion `%s'"), str);
13215 arm_parse_cpu (char * str)
13217 const struct arm_cpu_option_table * opt;
13218 char * ext = strchr (str, '+');
13222 optlen = ext - str;
13224 optlen = strlen (str);
13228 as_bad (_("missing cpu name `%s'"), str);
13232 for (opt = arm_cpus; opt->name != NULL; opt++)
13233 if (strncmp (opt->name, str, optlen) == 0)
13235 mcpu_cpu_opt = &opt->value;
13236 mcpu_fpu_opt = &opt->default_fpu;
13237 if (opt->canonical_name)
13238 strcpy(selected_cpu_name, opt->canonical_name);
13242 for (i = 0; i < optlen; i++)
13243 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13244 selected_cpu_name[i] = 0;
13248 return arm_parse_extension (ext, &mcpu_cpu_opt);
13253 as_bad (_("unknown cpu `%s'"), str);
13258 arm_parse_arch (char * str)
13260 const struct arm_arch_option_table *opt;
13261 char *ext = strchr (str, '+');
13265 optlen = ext - str;
13267 optlen = strlen (str);
13271 as_bad (_("missing architecture name `%s'"), str);
13275 for (opt = arm_archs; opt->name != NULL; opt++)
13276 if (streq (opt->name, str))
13278 march_cpu_opt = &opt->value;
13279 march_fpu_opt = &opt->default_fpu;
13280 strcpy(selected_cpu_name, opt->name);
13283 return arm_parse_extension (ext, &march_cpu_opt);
13288 as_bad (_("unknown architecture `%s'\n"), str);
13293 arm_parse_fpu (char * str)
13295 const struct arm_option_cpu_value_table * opt;
13297 for (opt = arm_fpus; opt->name != NULL; opt++)
13298 if (streq (opt->name, str))
13300 mfpu_opt = &opt->value;
13304 as_bad (_("unknown floating point format `%s'\n"), str);
13309 arm_parse_float_abi (char * str)
13311 const struct arm_option_value_table * opt;
13313 for (opt = arm_float_abis; opt->name != NULL; opt++)
13314 if (streq (opt->name, str))
13316 mfloat_abi_opt = opt->value;
13320 as_bad (_("unknown floating point abi `%s'\n"), str);
13326 arm_parse_eabi (char * str)
13328 const struct arm_option_value_table *opt;
13330 for (opt = arm_eabis; opt->name != NULL; opt++)
13331 if (streq (opt->name, str))
13333 meabi_flags = opt->value;
13336 as_bad (_("unknown EABI `%s'\n"), str);
13341 struct arm_long_option_table arm_long_opts[] =
13343 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
13344 arm_parse_cpu, NULL},
13345 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
13346 arm_parse_arch, NULL},
13347 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
13348 arm_parse_fpu, NULL},
13349 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
13350 arm_parse_float_abi, NULL},
13352 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
13353 arm_parse_eabi, NULL},
13355 {NULL, NULL, 0, NULL}
13359 md_parse_option (int c, char * arg)
13361 struct arm_option_table *opt;
13362 const struct arm_legacy_option_table *fopt;
13363 struct arm_long_option_table *lopt;
13369 target_big_endian = 1;
13375 target_big_endian = 0;
13380 /* Listing option. Just ignore these, we don't support additional
13385 for (opt = arm_opts; opt->option != NULL; opt++)
13387 if (c == opt->option[0]
13388 && ((arg == NULL && opt->option[1] == 0)
13389 || streq (arg, opt->option + 1)))
13391 #if WARN_DEPRECATED
13392 /* If the option is deprecated, tell the user. */
13393 if (opt->deprecated != NULL)
13394 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13395 arg ? arg : "", _(opt->deprecated));
13398 if (opt->var != NULL)
13399 *opt->var = opt->value;
13405 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
13407 if (c == fopt->option[0]
13408 && ((arg == NULL && fopt->option[1] == 0)
13409 || streq (arg, fopt->option + 1)))
13411 #if WARN_DEPRECATED
13412 /* If the option is deprecated, tell the user. */
13413 if (fopt->deprecated != NULL)
13414 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
13415 arg ? arg : "", _(fopt->deprecated));
13418 if (fopt->var != NULL)
13419 *fopt->var = &fopt->value;
13425 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13427 /* These options are expected to have an argument. */
13428 if (c == lopt->option[0]
13430 && strncmp (arg, lopt->option + 1,
13431 strlen (lopt->option + 1)) == 0)
13433 #if WARN_DEPRECATED
13434 /* If the option is deprecated, tell the user. */
13435 if (lopt->deprecated != NULL)
13436 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
13437 _(lopt->deprecated));
13440 /* Call the sup-option parser. */
13441 return lopt->func (arg + strlen (lopt->option) - 1);
13452 md_show_usage (FILE * fp)
13454 struct arm_option_table *opt;
13455 struct arm_long_option_table *lopt;
13457 fprintf (fp, _(" ARM-specific assembler options:\n"));
13459 for (opt = arm_opts; opt->option != NULL; opt++)
13460 if (opt->help != NULL)
13461 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
13463 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
13464 if (lopt->help != NULL)
13465 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
13469 -EB assemble code for a big-endian cpu\n"));
13474 -EL assemble code for a little-endian cpu\n"));
13480 /* Set the public EABI object attributes. */
13482 aeabi_set_public_attributes (void)
13485 arm_feature_set flags;
13487 /* Choose the architecture based on the capabilities of the requested cpu
13488 (if any) and/or the instructions actually used. */
13489 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
13490 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
13491 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
13492 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6t2))
13494 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6z))
13496 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6k))
13498 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v6))
13500 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5e))
13502 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v5)
13503 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v5t))
13505 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t))
13507 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4))
13512 /* Tag_CPU_name. */
13513 if (selected_cpu_name[0])
13517 p = selected_cpu_name;
13518 if (strncmp(p, "armv", 4) == 0)
13523 for (i = 0; p[i]; i++)
13524 p[i] = TOUPPER (p[i]);
13526 elf32_arm_add_eabi_attr_string (stdoutput, 5, p);
13528 /* Tag_CPU_arch. */
13529 elf32_arm_add_eabi_attr_int (stdoutput, 6, arch);
13530 /* Tag_ARM_ISA_use. */
13531 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
13532 elf32_arm_add_eabi_attr_int (stdoutput, 8, 1);
13533 /* Tag_THUMB_ISA_use. */
13534 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_full))
13535 elf32_arm_add_eabi_attr_int (stdoutput, 9,
13536 ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2) ? 2 : 1);
13537 /* Tag_VFP_arch. */
13538 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v2)
13539 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v2))
13540 elf32_arm_add_eabi_attr_int (stdoutput, 10, 2);
13541 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used, fpu_arch_vfp_v1)
13542 || ARM_CPU_HAS_FEATURE (arm_arch_used, fpu_arch_vfp_v1))
13543 elf32_arm_add_eabi_attr_int (stdoutput, 10, 1);
13544 /* Tag_WMMX_arch. */
13545 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_cext_iwmmxt)
13546 || ARM_CPU_HAS_FEATURE (arm_arch_used, arm_cext_iwmmxt))
13547 elf32_arm_add_eabi_attr_int (stdoutput, 11, 1);
13550 /* Add the .ARM.attributes section. */
13559 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
13562 aeabi_set_public_attributes ();
13563 size = elf32_arm_eabi_attr_size (stdoutput);
13564 s = subseg_new (".ARM.attributes", 0);
13565 bfd_set_section_flags (stdoutput, s, SEC_READONLY | SEC_DATA);
13566 addr = frag_now_fix ();
13567 p = frag_more (size);
13568 elf32_arm_set_eabi_attr_contents (stdoutput, (bfd_byte *)p, size);
13572 /* Parse a .cpu directive. */
13575 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
13577 const struct arm_cpu_option_table *opt;
13581 name = input_line_pointer;
13582 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13583 input_line_pointer++;
13584 saved_char = *input_line_pointer;
13585 *input_line_pointer = 0;
13587 /* Skip the first "all" entry. */
13588 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
13589 if (streq (opt->name, name))
13591 mcpu_cpu_opt = &opt->value;
13592 selected_cpu = opt->value;
13593 if (opt->canonical_name)
13594 strcpy(selected_cpu_name, opt->canonical_name);
13598 for (i = 0; opt->name[i]; i++)
13599 selected_cpu_name[i] = TOUPPER (opt->name[i]);
13600 selected_cpu_name[i] = 0;
13602 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13603 *input_line_pointer = saved_char;
13604 demand_empty_rest_of_line ();
13607 as_bad (_("unknown cpu `%s'"), name);
13608 *input_line_pointer = saved_char;
13609 ignore_rest_of_line ();
13613 /* Parse a .arch directive. */
13616 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
13618 const struct arm_arch_option_table *opt;
13622 name = input_line_pointer;
13623 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13624 input_line_pointer++;
13625 saved_char = *input_line_pointer;
13626 *input_line_pointer = 0;
13628 /* Skip the first "all" entry. */
13629 for (opt = arm_archs + 1; opt->name != NULL; opt++)
13630 if (streq (opt->name, name))
13632 mcpu_cpu_opt = &opt->value;
13633 selected_cpu = opt->value;
13634 strcpy(selected_cpu_name, opt->name);
13635 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13636 *input_line_pointer = saved_char;
13637 demand_empty_rest_of_line ();
13641 as_bad (_("unknown architecture `%s'\n"), name);
13642 *input_line_pointer = saved_char;
13643 ignore_rest_of_line ();
13647 /* Parse a .fpu directive. */
13650 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
13652 const struct arm_option_cpu_value_table *opt;
13656 name = input_line_pointer;
13657 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
13658 input_line_pointer++;
13659 saved_char = *input_line_pointer;
13660 *input_line_pointer = 0;
13662 for (opt = arm_fpus; opt->name != NULL; opt++)
13663 if (streq (opt->name, name))
13665 mfpu_opt = &opt->value;
13666 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
13667 *input_line_pointer = saved_char;
13668 demand_empty_rest_of_line ();
13672 as_bad (_("unknown floating point format `%s'\n"), name);
13673 *input_line_pointer = saved_char;
13674 ignore_rest_of_line ();
13676 #endif /* OBJ_ELF */