1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
31 #include "safe-ctype.h"
33 /* Need TARGET_CPU. */
40 #include "opcode/arm.h"
44 #include "dwarf2dbg.h"
45 #include "dw2gencfi.h"
48 /* XXX Set this to 1 after the next binutils release. */
49 #define WARN_DEPRECATED 0
52 /* Must be at least the size of the largest unwind opcode (currently two). */
53 #define ARM_OPCODE_CHUNK_SIZE 8
55 /* This structure holds the unwinding state. */
60 symbolS * table_entry;
61 symbolS * personality_routine;
62 int personality_index;
63 /* The segment containing the function. */
66 /* Opcodes generated from this function. */
67 unsigned char * opcodes;
70 /* The number of bytes pushed to the stack. */
72 /* We don't add stack adjustment opcodes immediately so that we can merge
73 multiple adjustments. We can also omit the final adjustment
74 when using a frame pointer. */
75 offsetT pending_offset;
76 /* These two fields are set by both unwind_movsp and unwind_setfp. They
77 hold the reg+offset to use when restoring sp from a frame pointer. */
80 /* Nonzero if an unwind_setfp directive has been seen. */
82 /* Nonzero if the last opcode restores sp from fp_reg. */
83 unsigned sp_restored:1;
86 /* Bit N indicates that an R_ARM_NONE relocation has been output for
87 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
88 emitted only once per section, to save unnecessary bloat. */
89 static unsigned int marked_pr_dependency = 0;
100 /* Types of processor to assemble for. */
101 #define ARM_1 ARM_ARCH_V1
102 #define ARM_2 ARM_ARCH_V2
103 #define ARM_3 ARM_ARCH_V2S
104 #define ARM_250 ARM_ARCH_V2S
105 #define ARM_6 ARM_ARCH_V3
106 #define ARM_7 ARM_ARCH_V3
107 #define ARM_8 ARM_ARCH_V4
108 #define ARM_9 ARM_ARCH_V4T
109 #define ARM_STRONG ARM_ARCH_V4
110 #define ARM_CPU_MASK 0x0000000f /* XXX? */
113 #if defined __XSCALE__
114 #define CPU_DEFAULT (ARM_ARCH_XSCALE)
116 #if defined __thumb__
117 #define CPU_DEFAULT (ARM_ARCH_V5T)
119 #define CPU_DEFAULT ARM_ANY
126 # define FPU_DEFAULT FPU_ARCH_FPA
127 # elif defined (TE_NetBSD)
129 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
131 /* Legacy a.out format. */
132 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
134 # elif defined (TE_VXWORKS)
135 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
137 /* For backwards compatibility, default to FPA. */
138 # define FPU_DEFAULT FPU_ARCH_FPA
140 #endif /* ifndef FPU_DEFAULT */
142 #define streq(a, b) (strcmp (a, b) == 0)
144 static unsigned long cpu_variant;
146 /* Flags stored in private area of BFD structure. */
147 static int uses_apcs_26 = FALSE;
148 static int atpcs = FALSE;
149 static int support_interwork = FALSE;
150 static int uses_apcs_float = FALSE;
151 static int pic_code = FALSE;
153 /* Variables that we set while parsing command-line options. Once all
154 options have been read we re-process these values to set the real
156 static int legacy_cpu = -1;
157 static int legacy_fpu = -1;
159 static int mcpu_cpu_opt = -1;
160 static int mcpu_fpu_opt = -1;
161 static int march_cpu_opt = -1;
162 static int march_fpu_opt = -1;
163 static int mfpu_opt = -1;
164 static int mfloat_abi_opt = -1;
167 static int meabi_flags = EABI_DEFAULT;
169 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
174 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
175 symbolS * GOT_symbol;
178 /* Size of relocation record. */
179 const int md_reloc_size = 8;
181 /* 0: assemble for ARM,
182 1: assemble for Thumb,
183 2: assemble for Thumb even though target CPU does not support thumb
185 static int thumb_mode = 0;
187 /* If unified_syntax is true, we are processing the new unified
188 ARM/Thumb syntax. Important differences from the old ARM mode:
190 - Immediate operands do not require a # prefix.
191 - Conditional affixes always appear at the end of the
192 instruction. (For backward compatibility, those instructions
193 that formerly had them in the middle, continue to accept them
195 - The IT instruction may appear, and if it does is validated
196 against subsequent conditional affixes. It does not generate
199 Important differences from the old Thumb mode:
201 - Immediate operands do not require a # prefix.
202 - Most of the V6T2 instructions are only available in unified mode.
203 - The .N and .W suffixes are recognized and honored (it is an error
204 if they cannot be honored).
205 - All instructions set the flags if and only if they have an 's' affix.
206 - Conditional affixes may be used. They are validated against
207 preceding IT instructions. Unlike ARM mode, you cannot use a
208 conditional affix except in the scope of an IT instruction. */
210 static bfd_boolean unified_syntax = FALSE;
215 unsigned long instruction;
221 bfd_reloc_code_real_type type;
230 unsigned present : 1; /* Operand present. */
231 unsigned isreg : 1; /* Operand was a register. */
232 unsigned immisreg : 1; /* .imm field is a second register. */
233 unsigned hasreloc : 1; /* Operand has relocation suffix. */
234 unsigned writeback : 1; /* Operand has trailing ! */
235 unsigned preind : 1; /* Preindexed address. */
236 unsigned postind : 1; /* Postindexed address. */
237 unsigned negative : 1; /* Index register was negated. */
238 unsigned shifted : 1; /* Shift applied to operation. */
239 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
243 static struct arm_it inst;
245 #define NUM_FLOAT_VALS 8
247 const char * fp_const[] =
249 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
252 /* Number of littlenums required to hold an extended precision number. */
253 #define MAX_LITTLENUMS 6
255 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
265 #define CP_T_X 0x00008000
266 #define CP_T_Y 0x00400000
268 #define CONDS_BIT 0x00100000
269 #define LOAD_BIT 0x00100000
271 #define DOUBLE_LOAD_FLAG 0x00000001
275 const char * template;
279 #define COND_ALWAYS 0xE
283 const char *template;
287 /* The bit that distinguishes CPSR and SPSR. */
288 #define SPSR_BIT (1 << 22)
290 /* The individual PSR flag bits. */
291 #define PSR_c (1 << 16)
292 #define PSR_x (1 << 17)
293 #define PSR_s (1 << 18)
294 #define PSR_f (1 << 19)
299 bfd_reloc_code_real_type reloc;
304 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn
309 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
312 /* ARM register categories. This includes coprocessor numbers and various
313 architecture extensions' registers. */
335 /* Structure for a hash table entry for a register. */
339 unsigned char number;
341 unsigned char builtin;
344 /* Diagnostics used when we don't get a register of the expected type. */
345 const char *const reg_expected_msgs[] =
347 N_("ARM register expected"),
348 N_("bad or missing co-processor number"),
349 N_("co-processor register expected"),
350 N_("FPA register expected"),
351 N_("VFP single precision register expected"),
352 N_("VFP double precision register expected"),
353 N_("VFP system register expected"),
354 N_("Maverick MVF register expected"),
355 N_("Maverick MVD register expected"),
356 N_("Maverick MVFX register expected"),
357 N_("Maverick MVDX register expected"),
358 N_("Maverick MVAX register expected"),
359 N_("Maverick DSPSC register expected"),
360 N_("iWMMXt data register expected"),
361 N_("iWMMXt control register expected"),
362 N_("iWMMXt scalar register expected"),
363 N_("XScale accumulator register expected"),
366 /* Some well known registers that we refer to directly elsewhere. */
371 /* ARM instructions take 4bytes in the object file, Thumb instructions
377 /* Basic string to match. */
378 const char *template;
380 /* Parameters to instruction. */
381 unsigned char operands[8];
383 /* Conditional tag - see opcode_lookup. */
384 unsigned int tag : 4;
386 /* Basic instruction code. */
387 unsigned int avalue : 28;
389 /* Thumb-format instruction code. */
392 /* Which architecture variant provides this instruction. */
393 unsigned long avariant;
394 unsigned long tvariant;
396 /* Function to call to encode instruction in ARM format. */
397 void (* aencode) (void);
399 /* Function to call to encode instruction in Thumb format. */
400 void (* tencode) (void);
403 /* Defines for various bits that we will want to toggle. */
404 #define INST_IMMEDIATE 0x02000000
405 #define OFFSET_REG 0x02000000
406 #define HWOFFSET_IMM 0x00400000
407 #define SHIFT_BY_REG 0x00000010
408 #define PRE_INDEX 0x01000000
409 #define INDEX_UP 0x00800000
410 #define WRITE_BACK 0x00200000
411 #define LDM_TYPE_2_OR_3 0x00400000
413 #define LITERAL_MASK 0xf000f000
414 #define OPCODE_MASK 0xfe1fffff
415 #define V4_STR_BIT 0x00000020
417 #define DATA_OP_SHIFT 21
419 /* Codes to distinguish the arithmetic instructions. */
430 #define OPCODE_CMP 10
431 #define OPCODE_CMN 11
432 #define OPCODE_ORR 12
433 #define OPCODE_MOV 13
434 #define OPCODE_BIC 14
435 #define OPCODE_MVN 15
437 #define T_OPCODE_MUL 0x4340
438 #define T_OPCODE_TST 0x4200
439 #define T_OPCODE_CMN 0x42c0
440 #define T_OPCODE_NEG 0x4240
441 #define T_OPCODE_MVN 0x43c0
443 #define T_OPCODE_ADD_R3 0x1800
444 #define T_OPCODE_SUB_R3 0x1a00
445 #define T_OPCODE_ADD_HI 0x4400
446 #define T_OPCODE_ADD_ST 0xb000
447 #define T_OPCODE_SUB_ST 0xb080
448 #define T_OPCODE_ADD_SP 0xa800
449 #define T_OPCODE_ADD_PC 0xa000
450 #define T_OPCODE_ADD_I8 0x3000
451 #define T_OPCODE_SUB_I8 0x3800
452 #define T_OPCODE_ADD_I3 0x1c00
453 #define T_OPCODE_SUB_I3 0x1e00
455 #define T_OPCODE_ASR_R 0x4100
456 #define T_OPCODE_LSL_R 0x4080
457 #define T_OPCODE_LSR_R 0x40c0
458 #define T_OPCODE_ROR_R 0x41c0
459 #define T_OPCODE_ASR_I 0x1000
460 #define T_OPCODE_LSL_I 0x0000
461 #define T_OPCODE_LSR_I 0x0800
463 #define T_OPCODE_MOV_I8 0x2000
464 #define T_OPCODE_CMP_I8 0x2800
465 #define T_OPCODE_CMP_LR 0x4280
466 #define T_OPCODE_MOV_HR 0x4600
467 #define T_OPCODE_CMP_HR 0x4500
469 #define T_OPCODE_LDR_PC 0x4800
470 #define T_OPCODE_LDR_SP 0x9800
471 #define T_OPCODE_STR_SP 0x9000
472 #define T_OPCODE_LDR_IW 0x6800
473 #define T_OPCODE_STR_IW 0x6000
474 #define T_OPCODE_LDR_IH 0x8800
475 #define T_OPCODE_STR_IH 0x8000
476 #define T_OPCODE_LDR_IB 0x7800
477 #define T_OPCODE_STR_IB 0x7000
478 #define T_OPCODE_LDR_RW 0x5800
479 #define T_OPCODE_STR_RW 0x5000
480 #define T_OPCODE_LDR_RH 0x5a00
481 #define T_OPCODE_STR_RH 0x5200
482 #define T_OPCODE_LDR_RB 0x5c00
483 #define T_OPCODE_STR_RB 0x5400
485 #define T_OPCODE_PUSH 0xb400
486 #define T_OPCODE_POP 0xbc00
488 #define T_OPCODE_BRANCH 0xe000
490 #define THUMB_SIZE 2 /* Size of thumb instruction. */
491 #define THUMB_PP_PC_LR 0x0100
492 #define THUMB_LOAD_BIT 0x0800
494 #define BAD_ARGS _("bad arguments to instruction")
495 #define BAD_PC _("r15 not allowed here")
496 #define BAD_COND _("instruction cannot be conditional")
497 #define BAD_OVERLAP _("registers may not be the same")
498 #define BAD_HIREG _("lo register required")
499 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
501 static struct hash_control *arm_ops_hsh;
502 static struct hash_control *arm_cond_hsh;
503 static struct hash_control *arm_shift_hsh;
504 static struct hash_control *arm_psr_hsh;
505 static struct hash_control *arm_reg_hsh;
506 static struct hash_control *arm_reloc_hsh;
508 /* Stuff needed to resolve the label ambiguity
518 symbolS * last_label_seen;
519 static int label_is_thumb_function_name = FALSE;
521 /* Literal pool structure. Held on a per-section
522 and per-sub-section basis. */
524 #define MAX_LITERAL_POOL_SIZE 1024
525 typedef struct literal_pool
527 expressionS literals [MAX_LITERAL_POOL_SIZE];
528 unsigned int next_free_entry;
533 struct literal_pool * next;
536 /* Pointer to a linked list of literal pools. */
537 literal_pool * list_of_pools = NULL;
541 /* This array holds the chars that always start a comment. If the
542 pre-processor is disabled, these aren't very useful. */
543 const char comment_chars[] = "@";
545 /* This array holds the chars that only start a comment at the beginning of
546 a line. If the line seems to have the form '# 123 filename'
547 .line and .file directives will appear in the pre-processed output. */
548 /* Note that input_file.c hand checks for '#' at the beginning of the
549 first line of the input file. This is because the compiler outputs
550 #NO_APP at the beginning of its output. */
551 /* Also note that comments like this one will always work. */
552 const char line_comment_chars[] = "#";
554 const char line_separator_chars[] = ";";
556 /* Chars that can be used to separate mant
557 from exp in floating point numbers. */
558 const char EXP_CHARS[] = "eE";
560 /* Chars that mean this number is a floating point constant. */
564 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
566 /* Prefix characters that indicate the start of an immediate
568 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
570 /* Separator character handling. */
572 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
575 skip_past_char (char ** str, char c)
585 #define skip_past_comma(str) skip_past_char (str, ',')
587 /* Arithmetic expressions (possibly involving symbols). */
589 /* Return TRUE if anything in the expression is a bignum. */
592 walk_no_bignums (symbolS * sp)
594 if (symbol_get_value_expression (sp)->X_op == O_big)
597 if (symbol_get_value_expression (sp)->X_add_symbol)
599 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
600 || (symbol_get_value_expression (sp)->X_op_symbol
601 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
607 static int in_my_get_expression = 0;
609 /* Third argument to my_get_expression. */
610 #define GE_NO_PREFIX 0
611 #define GE_IMM_PREFIX 1
612 #define GE_OPT_PREFIX 2
615 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
620 /* In unified syntax, all prefixes are optional. */
622 prefix_mode = GE_OPT_PREFIX;
626 case GE_NO_PREFIX: break;
628 if (!is_immediate_prefix (**str))
630 inst.error = _("immediate expression requires a # prefix");
636 if (is_immediate_prefix (**str))
642 memset (ep, 0, sizeof (expressionS));
644 save_in = input_line_pointer;
645 input_line_pointer = *str;
646 in_my_get_expression = 1;
647 seg = expression (ep);
648 in_my_get_expression = 0;
650 if (ep->X_op == O_illegal)
652 /* We found a bad expression in md_operand(). */
653 *str = input_line_pointer;
654 input_line_pointer = save_in;
655 if (inst.error == NULL)
656 inst.error = _("bad expression");
661 if (seg != absolute_section
662 && seg != text_section
663 && seg != data_section
664 && seg != bss_section
665 && seg != undefined_section)
667 inst.error = _("bad segment");
668 *str = input_line_pointer;
669 input_line_pointer = save_in;
674 /* Get rid of any bignums now, so that we don't generate an error for which
675 we can't establish a line number later on. Big numbers are never valid
676 in instructions, which is where this routine is always called. */
677 if (ep->X_op == O_big
679 && (walk_no_bignums (ep->X_add_symbol)
681 && walk_no_bignums (ep->X_op_symbol)))))
683 inst.error = _("invalid constant");
684 *str = input_line_pointer;
685 input_line_pointer = save_in;
689 *str = input_line_pointer;
690 input_line_pointer = save_in;
694 /* Turn a string in input_line_pointer into a floating point constant
695 of type TYPE, and store the appropriate bytes in *LITP. The number
696 of LITTLENUMS emitted is stored in *SIZEP. An error message is
697 returned, or NULL on OK.
699 Note that fp constants aren't represent in the normal way on the ARM.
700 In big endian mode, things are as expected. However, in little endian
701 mode fp constants are big-endian word-wise, and little-endian byte-wise
702 within the words. For example, (double) 1.1 in big endian mode is
703 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
704 the byte sequence 99 99 f1 3f 9a 99 99 99.
706 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
709 md_atof (int type, char * litP, int * sizeP)
712 LITTLENUM_TYPE words[MAX_LITTLENUMS];
744 return _("bad call to MD_ATOF()");
747 t = atof_ieee (input_line_pointer, type, words);
749 input_line_pointer = t;
752 if (target_big_endian)
754 for (i = 0; i < prec; i++)
756 md_number_to_chars (litP, (valueT) words[i], 2);
762 if (cpu_variant & FPU_ARCH_VFP)
763 for (i = prec - 1; i >= 0; i--)
765 md_number_to_chars (litP, (valueT) words[i], 2);
769 /* For a 4 byte float the order of elements in `words' is 1 0.
770 For an 8 byte float the order is 1 0 3 2. */
771 for (i = 0; i < prec; i += 2)
773 md_number_to_chars (litP, (valueT) words[i + 1], 2);
774 md_number_to_chars (litP + 2, (valueT) words[i], 2);
782 /* We handle all bad expressions here, so that we can report the faulty
783 instruction in the error message. */
785 md_operand (expressionS * expr)
787 if (in_my_get_expression)
788 expr->X_op = O_illegal;
791 /* Immediate values. */
793 /* Generic immediate-value read function for use in directives.
794 Accepts anything that 'expression' can fold to a constant.
795 *val receives the number. */
798 immediate_for_directive (int *val)
801 exp.X_op = O_illegal;
803 if (is_immediate_prefix (*input_line_pointer))
805 input_line_pointer++;
809 if (exp.X_op != O_constant)
811 as_bad (_("expected #constant"));
812 ignore_rest_of_line ();
815 *val = exp.X_add_number;
820 /* Register parsing. */
822 /* Generic register parser. CCP points to what should be the
823 beginning of a register name. If it is indeed a valid register
824 name, advance CCP over it and return the reg_entry structure;
825 otherwise return NULL. Does not issue diagnostics. */
827 static struct reg_entry *
828 arm_reg_parse_multi (char **ccp)
832 struct reg_entry *reg;
834 #ifdef REGISTER_PREFIX
835 if (*start != REGISTER_PREFIX)
839 #ifdef OPTIONAL_REGISTER_PREFIX
840 if (*start == OPTIONAL_REGISTER_PREFIX)
845 if (!ISALPHA (*p) || !is_name_beginner (*p))
850 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
852 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
861 /* As above, but the register must be of type TYPE, and the return
862 value is the register number or NULL. */
865 arm_reg_parse (char **ccp, enum arm_reg_type type)
868 struct reg_entry *reg = arm_reg_parse_multi (ccp);
870 if (reg && reg->type == type)
873 /* Alternative syntaxes are accepted for a few register classes. */
880 /* Generic coprocessor register names are allowed for these. */
881 if (reg->type == REG_TYPE_CN)
886 /* For backward compatibility, a bare number is valid here. */
888 unsigned long processor = strtoul (start, ccp, 10);
889 if (*ccp != start && processor <= 15)
894 /* WC includes WCG. ??? I'm not sure this is true for all
895 instructions that take WC registers. */
896 if (reg->type == REG_TYPE_MMXWCG)
908 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
910 parse_reg_list (char ** strp)
916 /* We come back here if we get ranges concatenated by '+' or '|'. */
931 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
933 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
943 inst.error = _("bad range in register list");
947 for (i = cur_reg + 1; i < reg; i++)
949 if (range & (1 << i))
951 (_("Warning: duplicated register (r%d) in register list"),
959 if (range & (1 << reg))
960 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
962 else if (reg <= cur_reg)
963 as_tsktsk (_("Warning: register range not in ascending order"));
968 while (skip_past_comma (&str) != FAIL
969 || (in_range = 1, *str++ == '-'));
974 inst.error = _("missing `}'");
982 if (my_get_expression (&expr, &str, GE_NO_PREFIX))
985 if (expr.X_op == O_constant)
987 if (expr.X_add_number
988 != (expr.X_add_number & 0x0000ffff))
990 inst.error = _("invalid register mask");
994 if ((range & expr.X_add_number) != 0)
996 int regno = range & expr.X_add_number;
999 regno = (1 << regno) - 1;
1001 (_("Warning: duplicated register (r%d) in register list"),
1005 range |= expr.X_add_number;
1009 if (inst.reloc.type != 0)
1011 inst.error = _("expression too complex");
1015 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
1016 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1017 inst.reloc.pc_rel = 0;
1021 if (*str == '|' || *str == '+')
1027 while (another_range);
1033 /* Parse a VFP register list. If the string is invalid return FAIL.
1034 Otherwise return the number of registers, and set PBASE to the first
1035 register. Double precision registers are matched if DP is nonzero. */
1038 parse_vfp_reg_list (char **str, unsigned int *pbase, int dp)
1046 unsigned long mask = 0;
1056 regtype = REG_TYPE_VFD;
1061 regtype = REG_TYPE_VFS;
1065 base_reg = max_regs;
1069 new_base = arm_reg_parse (str, regtype);
1070 if (new_base == FAIL)
1072 inst.error = gettext (reg_expected_msgs[regtype]);
1076 if (new_base < base_reg)
1077 base_reg = new_base;
1079 if (mask & (1 << new_base))
1081 inst.error = _("invalid register list");
1085 if ((mask >> new_base) != 0 && ! warned)
1087 as_tsktsk (_("register list not in ascending order"));
1091 mask |= 1 << new_base;
1094 if (**str == '-') /* We have the start of a range expression */
1100 if ((high_range = arm_reg_parse (str, regtype)) == FAIL)
1102 inst.error = gettext (reg_expected_msgs[regtype]);
1106 if (high_range <= new_base)
1108 inst.error = _("register range not in ascending order");
1112 for (new_base++; new_base <= high_range; new_base++)
1114 if (mask & (1 << new_base))
1116 inst.error = _("invalid register list");
1120 mask |= 1 << new_base;
1125 while (skip_past_comma (str) != FAIL);
1129 /* Sanity check -- should have raised a parse error above. */
1130 if (count == 0 || count > max_regs)
1135 /* Final test -- the registers must be consecutive. */
1137 for (i = 0; i < count; i++)
1139 if ((mask & (1u << i)) == 0)
1141 inst.error = _("non-contiguous register range");
1149 /* Parse an explicit relocation suffix on an expression. This is
1150 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1151 arm_reloc_hsh contains no entries, so this function can only
1152 succeed if there is no () after the word. Returns -1 on error,
1153 BFD_RELOC_UNUSED if there wasn't any suffix. */
1155 parse_reloc (char **str)
1157 struct reloc_entry *r;
1161 return BFD_RELOC_UNUSED;
1166 while (*q && *q != ')' && *q != ',')
1171 if ((r = hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
1178 /* Directives: register aliases. */
1181 insert_reg_alias (char *str, int number, int type)
1183 struct reg_entry *new;
1186 if ((new = hash_find (arm_reg_hsh, str)) != 0)
1189 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
1191 /* Only warn about a redefinition if it's not defined as the
1193 else if (new->number != number || new->type != type)
1194 as_warn (_("ignoring redefinition of register alias '%s'"), str);
1199 name = xstrdup (str);
1200 new = xmalloc (sizeof (struct reg_entry));
1203 new->number = number;
1205 new->builtin = FALSE;
1207 if (hash_insert (arm_reg_hsh, name, (PTR) new))
1211 /* Look for the .req directive. This is of the form:
1213 new_register_name .req existing_register_name
1215 If we find one, or if it looks sufficiently like one that we want to
1216 handle any error here, return non-zero. Otherwise return zero. */
1219 create_register_alias (char * newname, char *p)
1221 struct reg_entry *old;
1222 char *oldname, *nbuf;
1225 /* The input scrubber ensures that whitespace after the mnemonic is
1226 collapsed to single spaces. */
1228 if (strncmp (oldname, " .req ", 6) != 0)
1232 if (*oldname == '\0')
1235 old = hash_find (arm_reg_hsh, oldname);
1238 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
1242 /* If TC_CASE_SENSITIVE is defined, then newname already points to
1243 the desired alias name, and p points to its end. If not, then
1244 the desired alias name is in the global original_case_string. */
1245 #ifdef TC_CASE_SENSITIVE
1248 newname = original_case_string;
1249 nlen = strlen (newname);
1252 nbuf = alloca (nlen + 1);
1253 memcpy (nbuf, newname, nlen);
1256 /* Create aliases under the new name as stated; an all-lowercase
1257 version of the new name; and an all-uppercase version of the new
1259 insert_reg_alias (nbuf, old->number, old->type);
1261 for (p = nbuf; *p; p++)
1264 if (strncmp (nbuf, newname, nlen))
1265 insert_reg_alias (nbuf, old->number, old->type);
1267 for (p = nbuf; *p; p++)
1270 if (strncmp (nbuf, newname, nlen))
1271 insert_reg_alias (nbuf, old->number, old->type);
1276 /* Should never be called, as .req goes between the alias and the
1277 register name, not at the beginning of the line. */
1279 s_req (int a ATTRIBUTE_UNUSED)
1281 as_bad (_("invalid syntax for .req directive"));
1284 /* The .unreq directive deletes an alias which was previously defined
1285 by .req. For example:
1291 s_unreq (int a ATTRIBUTE_UNUSED)
1296 name = input_line_pointer;
1298 while (*input_line_pointer != 0
1299 && *input_line_pointer != ' '
1300 && *input_line_pointer != '\n')
1301 ++input_line_pointer;
1303 saved_char = *input_line_pointer;
1304 *input_line_pointer = 0;
1307 as_bad (_("invalid syntax for .unreq directive"));
1310 struct reg_entry *reg = hash_find (arm_reg_hsh, name);
1313 as_bad (_("unknown register alias '%s'"), name);
1314 else if (reg->builtin)
1315 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
1319 hash_delete (arm_reg_hsh, name);
1320 free ((char *) reg->name);
1325 *input_line_pointer = saved_char;
1326 demand_empty_rest_of_line ();
1329 /* Directives: Instruction set selection. */
1332 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
1333 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
1334 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
1335 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
1337 static enum mstate mapstate = MAP_UNDEFINED;
1340 mapping_state (enum mstate state)
1343 const char * symname;
1346 if (mapstate == state)
1347 /* The mapping symbol has already been emitted.
1348 There is nothing else to do. */
1357 type = BSF_NO_FLAGS;
1361 type = BSF_NO_FLAGS;
1365 type = BSF_NO_FLAGS;
1373 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
1375 symbolP = symbol_new (symname, now_seg, (valueT) frag_now_fix (), frag_now);
1376 symbol_table_insert (symbolP);
1377 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
1382 THUMB_SET_FUNC (symbolP, 0);
1383 ARM_SET_THUMB (symbolP, 0);
1384 ARM_SET_INTERWORK (symbolP, support_interwork);
1388 THUMB_SET_FUNC (symbolP, 1);
1389 ARM_SET_THUMB (symbolP, 1);
1390 ARM_SET_INTERWORK (symbolP, support_interwork);
1399 #define mapping_state(x) /* nothing */
1402 /* Find the real, Thumb encoded start of a Thumb function. */
1405 find_real_start (symbolS * symbolP)
1408 const char * name = S_GET_NAME (symbolP);
1409 symbolS * new_target;
1411 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
1412 #define STUB_NAME ".real_start_of"
1417 /* The compiler may generate BL instructions to local labels because
1418 it needs to perform a branch to a far away location. These labels
1419 do not have a corresponding ".real_start_of" label. We check
1420 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
1421 the ".real_start_of" convention for nonlocal branches. */
1422 if (S_IS_LOCAL (symbolP) || name[0] == '.')
1425 real_start = ACONCAT ((STUB_NAME, name, NULL));
1426 new_target = symbol_find (real_start);
1428 if (new_target == NULL)
1430 as_warn ("Failed to find real start of function: %s\n", name);
1431 new_target = symbolP;
1438 opcode_select (int width)
1445 if (! (cpu_variant & ARM_EXT_V4T))
1446 as_bad (_("selected processor does not support THUMB opcodes"));
1449 /* No need to force the alignment, since we will have been
1450 coming from ARM mode, which is word-aligned. */
1451 record_alignment (now_seg, 1);
1453 mapping_state (MAP_THUMB);
1459 if ((cpu_variant & ARM_ALL) == ARM_EXT_V4T)
1460 as_bad (_("selected processor does not support ARM opcodes"));
1465 frag_align (2, 0, 0);
1467 record_alignment (now_seg, 1);
1469 mapping_state (MAP_ARM);
1473 as_bad (_("invalid instruction size selected (%d)"), width);
1478 s_arm (int ignore ATTRIBUTE_UNUSED)
1481 demand_empty_rest_of_line ();
1485 s_thumb (int ignore ATTRIBUTE_UNUSED)
1488 demand_empty_rest_of_line ();
1492 s_code (int unused ATTRIBUTE_UNUSED)
1496 temp = get_absolute_expression ();
1501 opcode_select (temp);
1505 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1510 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
1512 /* If we are not already in thumb mode go into it, EVEN if
1513 the target processor does not support thumb instructions.
1514 This is used by gcc/config/arm/lib1funcs.asm for example
1515 to compile interworking support functions even if the
1516 target processor should not support interworking. */
1520 record_alignment (now_seg, 1);
1523 demand_empty_rest_of_line ();
1527 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
1531 /* The following label is the name/address of the start of a Thumb function.
1532 We need to know this for the interworking support. */
1533 label_is_thumb_function_name = TRUE;
1536 /* Perform a .set directive, but also mark the alias as
1537 being a thumb function. */
1540 s_thumb_set (int equiv)
1542 /* XXX the following is a duplicate of the code for s_set() in read.c
1543 We cannot just call that code as we need to get at the symbol that
1550 /* Especial apologies for the random logic:
1551 This just grew, and could be parsed much more simply!
1553 name = input_line_pointer;
1554 delim = get_symbol_end ();
1555 end_name = input_line_pointer;
1558 if (*input_line_pointer != ',')
1561 as_bad (_("expected comma after name \"%s\""), name);
1563 ignore_rest_of_line ();
1567 input_line_pointer++;
1570 if (name[0] == '.' && name[1] == '\0')
1572 /* XXX - this should not happen to .thumb_set. */
1576 if ((symbolP = symbol_find (name)) == NULL
1577 && (symbolP = md_undefined_symbol (name)) == NULL)
1580 /* When doing symbol listings, play games with dummy fragments living
1581 outside the normal fragment chain to record the file and line info
1583 if (listing & LISTING_SYMBOLS)
1585 extern struct list_info_struct * listing_tail;
1586 fragS * dummy_frag = xmalloc (sizeof (fragS));
1588 memset (dummy_frag, 0, sizeof (fragS));
1589 dummy_frag->fr_type = rs_fill;
1590 dummy_frag->line = listing_tail;
1591 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1592 dummy_frag->fr_symbol = symbolP;
1596 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1599 /* "set" symbols are local unless otherwise specified. */
1600 SF_SET_LOCAL (symbolP);
1601 #endif /* OBJ_COFF */
1602 } /* Make a new symbol. */
1604 symbol_table_insert (symbolP);
1609 && S_IS_DEFINED (symbolP)
1610 && S_GET_SEGMENT (symbolP) != reg_section)
1611 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1613 pseudo_set (symbolP);
1615 demand_empty_rest_of_line ();
1617 /* XXX Now we come to the Thumb specific bit of code. */
1619 THUMB_SET_FUNC (symbolP, 1);
1620 ARM_SET_THUMB (symbolP, 1);
1621 #if defined OBJ_ELF || defined OBJ_COFF
1622 ARM_SET_INTERWORK (symbolP, support_interwork);
1626 /* Directives: Mode selection. */
1628 /* .syntax [unified|divided] - choose the new unified syntax
1629 (same for Arm and Thumb encoding, modulo slight differences in what
1630 can be represented) or the old divergent syntax for each mode. */
1632 s_syntax (int unused ATTRIBUTE_UNUSED)
1636 name = input_line_pointer;
1637 delim = get_symbol_end ();
1639 if (!strcasecmp (name, "unified"))
1640 unified_syntax = TRUE;
1641 else if (!strcasecmp (name, "divided"))
1642 unified_syntax = FALSE;
1645 as_bad (_("unrecognized syntax mode \"%s\""), name);
1648 *input_line_pointer = delim;
1649 demand_empty_rest_of_line ();
1652 /* Directives: sectioning and alignment. */
1654 /* Same as s_align_ptwo but align 0 => align 2. */
1657 s_align (int unused ATTRIBUTE_UNUSED)
1661 long max_alignment = 15;
1663 temp = get_absolute_expression ();
1664 if (temp > max_alignment)
1665 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
1668 as_bad (_("alignment negative. 0 assumed."));
1672 if (*input_line_pointer == ',')
1674 input_line_pointer++;
1675 temp_fill = get_absolute_expression ();
1683 /* Only make a frag if we HAVE to. */
1684 if (temp && !need_pass_2)
1685 frag_align (temp, (int) temp_fill, 0);
1686 demand_empty_rest_of_line ();
1688 record_alignment (now_seg, temp);
1692 s_bss (int ignore ATTRIBUTE_UNUSED)
1694 /* We don't support putting frags in the BSS segment, we fake it by
1695 marking in_bss, then looking at s_skip for clues. */
1696 subseg_set (bss_section, 0);
1697 demand_empty_rest_of_line ();
1698 mapping_state (MAP_DATA);
1702 s_even (int ignore ATTRIBUTE_UNUSED)
1704 /* Never make frag if expect extra pass. */
1706 frag_align (1, 0, 0);
1708 record_alignment (now_seg, 1);
1710 demand_empty_rest_of_line ();
1713 /* Directives: Literal pools. */
1715 static literal_pool *
1716 find_literal_pool (void)
1718 literal_pool * pool;
1720 for (pool = list_of_pools; pool != NULL; pool = pool->next)
1722 if (pool->section == now_seg
1723 && pool->sub_section == now_subseg)
1730 static literal_pool *
1731 find_or_make_literal_pool (void)
1733 /* Next literal pool ID number. */
1734 static unsigned int latest_pool_num = 1;
1735 literal_pool * pool;
1737 pool = find_literal_pool ();
1741 /* Create a new pool. */
1742 pool = xmalloc (sizeof (* pool));
1746 pool->next_free_entry = 0;
1747 pool->section = now_seg;
1748 pool->sub_section = now_subseg;
1749 pool->next = list_of_pools;
1750 pool->symbol = NULL;
1752 /* Add it to the list. */
1753 list_of_pools = pool;
1756 /* New pools, and emptied pools, will have a NULL symbol. */
1757 if (pool->symbol == NULL)
1759 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
1760 (valueT) 0, &zero_address_frag);
1761 pool->id = latest_pool_num ++;
1768 /* Add the literal in the global 'inst'
1769 structure to the relevent literal pool. */
1772 add_to_lit_pool (void)
1774 literal_pool * pool;
1777 pool = find_or_make_literal_pool ();
1779 /* Check if this literal value is already in the pool. */
1780 for (entry = 0; entry < pool->next_free_entry; entry ++)
1782 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1783 && (inst.reloc.exp.X_op == O_constant)
1784 && (pool->literals[entry].X_add_number
1785 == inst.reloc.exp.X_add_number)
1786 && (pool->literals[entry].X_unsigned
1787 == inst.reloc.exp.X_unsigned))
1790 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
1791 && (inst.reloc.exp.X_op == O_symbol)
1792 && (pool->literals[entry].X_add_number
1793 == inst.reloc.exp.X_add_number)
1794 && (pool->literals[entry].X_add_symbol
1795 == inst.reloc.exp.X_add_symbol)
1796 && (pool->literals[entry].X_op_symbol
1797 == inst.reloc.exp.X_op_symbol))
1801 /* Do we need to create a new entry? */
1802 if (entry == pool->next_free_entry)
1804 if (entry >= MAX_LITERAL_POOL_SIZE)
1806 inst.error = _("literal pool overflow");
1810 pool->literals[entry] = inst.reloc.exp;
1811 pool->next_free_entry += 1;
1814 inst.reloc.exp.X_op = O_symbol;
1815 inst.reloc.exp.X_add_number = ((int) entry) * 4;
1816 inst.reloc.exp.X_add_symbol = pool->symbol;
1821 /* Can't use symbol_new here, so have to create a symbol and then at
1822 a later date assign it a value. Thats what these functions do. */
1825 symbol_locate (symbolS * symbolP,
1826 const char * name, /* It is copied, the caller can modify. */
1827 segT segment, /* Segment identifier (SEG_<something>). */
1828 valueT valu, /* Symbol value. */
1829 fragS * frag) /* Associated fragment. */
1831 unsigned int name_length;
1832 char * preserved_copy_of_name;
1834 name_length = strlen (name) + 1; /* +1 for \0. */
1835 obstack_grow (¬es, name, name_length);
1836 preserved_copy_of_name = obstack_finish (¬es);
1838 #ifdef tc_canonicalize_symbol_name
1839 preserved_copy_of_name =
1840 tc_canonicalize_symbol_name (preserved_copy_of_name);
1843 S_SET_NAME (symbolP, preserved_copy_of_name);
1845 S_SET_SEGMENT (symbolP, segment);
1846 S_SET_VALUE (symbolP, valu);
1847 symbol_clear_list_pointers (symbolP);
1849 symbol_set_frag (symbolP, frag);
1851 /* Link to end of symbol chain. */
1853 extern int symbol_table_frozen;
1855 if (symbol_table_frozen)
1859 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1861 obj_symbol_new_hook (symbolP);
1863 #ifdef tc_symbol_new_hook
1864 tc_symbol_new_hook (symbolP);
1868 verify_symbol_chain (symbol_rootP, symbol_lastP);
1869 #endif /* DEBUG_SYMS */
1874 s_ltorg (int ignored ATTRIBUTE_UNUSED)
1877 literal_pool * pool;
1880 pool = find_literal_pool ();
1882 || pool->symbol == NULL
1883 || pool->next_free_entry == 0)
1886 mapping_state (MAP_DATA);
1888 /* Align pool as you have word accesses.
1889 Only make a frag if we have to. */
1891 frag_align (2, 0, 0);
1893 record_alignment (now_seg, 2);
1895 sprintf (sym_name, "$$lit_\002%x", pool->id);
1897 symbol_locate (pool->symbol, sym_name, now_seg,
1898 (valueT) frag_now_fix (), frag_now);
1899 symbol_table_insert (pool->symbol);
1901 ARM_SET_THUMB (pool->symbol, thumb_mode);
1903 #if defined OBJ_COFF || defined OBJ_ELF
1904 ARM_SET_INTERWORK (pool->symbol, support_interwork);
1907 for (entry = 0; entry < pool->next_free_entry; entry ++)
1908 /* First output the expression in the instruction to the pool. */
1909 emit_expr (&(pool->literals[entry]), 4); /* .word */
1911 /* Mark the pool as empty. */
1912 pool->next_free_entry = 0;
1913 pool->symbol = NULL;
1917 /* Forward declarations for functions below, in the MD interface
1919 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
1920 static valueT create_unwind_entry (int);
1921 static void start_unwind_section (const segT, int);
1922 static void add_unwind_opcode (valueT, int);
1923 static void flush_pending_unwind (void);
1925 /* Directives: Data. */
1928 s_arm_elf_cons (int nbytes)
1932 #ifdef md_flush_pending_output
1933 md_flush_pending_output ();
1936 if (is_it_end_of_statement ())
1938 demand_empty_rest_of_line ();
1942 #ifdef md_cons_align
1943 md_cons_align (nbytes);
1946 mapping_state (MAP_DATA);
1950 char *base = input_line_pointer;
1954 if (exp.X_op != O_symbol)
1955 emit_expr (&exp, (unsigned int) nbytes);
1958 char *before_reloc = input_line_pointer;
1959 reloc = parse_reloc (&input_line_pointer);
1962 as_bad (_("unrecognized relocation suffix"));
1963 ignore_rest_of_line ();
1966 else if (reloc == BFD_RELOC_UNUSED)
1967 emit_expr (&exp, (unsigned int) nbytes);
1970 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
1971 int size = bfd_get_reloc_size (howto);
1973 if (reloc == BFD_RELOC_ARM_PLT32)
1975 as_bad (_("(plt) is only valid on branch targets"));
1976 reloc = BFD_RELOC_UNUSED;
1981 as_bad (_("%s relocations do not fit in %d bytes"),
1982 howto->name, nbytes);
1985 /* We've parsed an expression stopping at O_symbol.
1986 But there may be more expression left now that we
1987 have parsed the relocation marker. Parse it again.
1988 XXX Surely there is a cleaner way to do this. */
1989 char *p = input_line_pointer;
1991 char *save_buf = alloca (input_line_pointer - base);
1992 memcpy (save_buf, base, input_line_pointer - base);
1993 memmove (base + (input_line_pointer - before_reloc),
1994 base, before_reloc - base);
1996 input_line_pointer = base + (input_line_pointer-before_reloc);
1998 memcpy (base, save_buf, p - base);
2000 offset = nbytes - size;
2001 p = frag_more ((int) nbytes);
2002 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
2003 size, &exp, 0, reloc);
2008 while (*input_line_pointer++ == ',');
2010 /* Put terminator back into stream. */
2011 input_line_pointer --;
2012 demand_empty_rest_of_line ();
2016 /* Parse a .rel31 directive. */
2019 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
2026 if (*input_line_pointer == '1')
2027 highbit = 0x80000000;
2028 else if (*input_line_pointer != '0')
2029 as_bad (_("expected 0 or 1"));
2031 input_line_pointer++;
2032 if (*input_line_pointer != ',')
2033 as_bad (_("missing comma"));
2034 input_line_pointer++;
2036 #ifdef md_flush_pending_output
2037 md_flush_pending_output ();
2040 #ifdef md_cons_align
2044 mapping_state (MAP_DATA);
2049 md_number_to_chars (p, highbit, 4);
2050 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
2051 BFD_RELOC_ARM_PREL31);
2053 demand_empty_rest_of_line ();
2056 /* Directives: AEABI stack-unwind tables. */
2058 /* Parse an unwind_fnstart directive. Simply records the current location. */
2061 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
2063 demand_empty_rest_of_line ();
2064 /* Mark the start of the function. */
2065 unwind.proc_start = expr_build_dot ();
2067 /* Reset the rest of the unwind info. */
2068 unwind.opcode_count = 0;
2069 unwind.table_entry = NULL;
2070 unwind.personality_routine = NULL;
2071 unwind.personality_index = -1;
2072 unwind.frame_size = 0;
2073 unwind.fp_offset = 0;
2076 unwind.sp_restored = 0;
2080 /* Parse a handlerdata directive. Creates the exception handling table entry
2081 for the function. */
2084 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
2086 demand_empty_rest_of_line ();
2087 if (unwind.table_entry)
2088 as_bad (_("dupicate .handlerdata directive"));
2090 create_unwind_entry (1);
2093 /* Parse an unwind_fnend directive. Generates the index table entry. */
2096 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
2102 demand_empty_rest_of_line ();
2104 /* Add eh table entry. */
2105 if (unwind.table_entry == NULL)
2106 val = create_unwind_entry (0);
2110 /* Add index table entry. This is two words. */
2111 start_unwind_section (unwind.saved_seg, 1);
2112 frag_align (2, 0, 0);
2113 record_alignment (now_seg, 2);
2115 ptr = frag_more (8);
2116 where = frag_now_fix () - 8;
2118 /* Self relative offset of the function start. */
2119 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
2120 BFD_RELOC_ARM_PREL31);
2122 /* Indicate dependency on EHABI-defined personality routines to the
2123 linker, if it hasn't been done already. */
2124 if (unwind.personality_index >= 0 && unwind.personality_index < 3
2125 && !(marked_pr_dependency & (1 << unwind.personality_index)))
2127 static const char *const name[] = {
2128 "__aeabi_unwind_cpp_pr0",
2129 "__aeabi_unwind_cpp_pr1",
2130 "__aeabi_unwind_cpp_pr2"
2132 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
2133 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
2134 marked_pr_dependency |= 1 << unwind.personality_index;
2135 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
2136 = marked_pr_dependency;
2140 /* Inline exception table entry. */
2141 md_number_to_chars (ptr + 4, val, 4);
2143 /* Self relative offset of the table entry. */
2144 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
2145 BFD_RELOC_ARM_PREL31);
2147 /* Restore the original section. */
2148 subseg_set (unwind.saved_seg, unwind.saved_subseg);
2152 /* Parse an unwind_cantunwind directive. */
2155 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
2157 demand_empty_rest_of_line ();
2158 if (unwind.personality_routine || unwind.personality_index != -1)
2159 as_bad (_("personality routine specified for cantunwind frame"));
2161 unwind.personality_index = -2;
2165 /* Parse a personalityindex directive. */
2168 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
2172 if (unwind.personality_routine || unwind.personality_index != -1)
2173 as_bad (_("duplicate .personalityindex directive"));
2177 if (exp.X_op != O_constant
2178 || exp.X_add_number < 0 || exp.X_add_number > 15)
2180 as_bad (_("bad personality routine number"));
2181 ignore_rest_of_line ();
2185 unwind.personality_index = exp.X_add_number;
2187 demand_empty_rest_of_line ();
2191 /* Parse a personality directive. */
2194 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
2198 if (unwind.personality_routine || unwind.personality_index != -1)
2199 as_bad (_("duplicate .personality directive"));
2201 name = input_line_pointer;
2202 c = get_symbol_end ();
2203 p = input_line_pointer;
2204 unwind.personality_routine = symbol_find_or_make (name);
2206 demand_empty_rest_of_line ();
2210 /* Parse a directive saving core registers. */
2213 s_arm_unwind_save_core (void)
2219 range = parse_reg_list (&input_line_pointer);
2222 as_bad (_("expected register list"));
2223 ignore_rest_of_line ();
2227 demand_empty_rest_of_line ();
2229 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
2230 into .unwind_save {..., sp...}. We aren't bothered about the value of
2231 ip because it is clobbered by calls. */
2232 if (unwind.sp_restored && unwind.fp_reg == 12
2233 && (range & 0x3000) == 0x1000)
2235 unwind.opcode_count--;
2236 unwind.sp_restored = 0;
2237 range = (range | 0x2000) & ~0x1000;
2238 unwind.pending_offset = 0;
2241 /* See if we can use the short opcodes. These pop a block of upto 8
2242 registers starting with r4, plus maybe r14. */
2243 for (n = 0; n < 8; n++)
2245 /* Break at the first non-saved register. */
2246 if ((range & (1 << (n + 4))) == 0)
2249 /* See if there are any other bits set. */
2250 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
2252 /* Use the long form. */
2253 op = 0x8000 | ((range >> 4) & 0xfff);
2254 add_unwind_opcode (op, 2);
2258 /* Use the short form. */
2260 op = 0xa8; /* Pop r14. */
2262 op = 0xa0; /* Do not pop r14. */
2264 add_unwind_opcode (op, 1);
2270 op = 0xb100 | (range & 0xf);
2271 add_unwind_opcode (op, 2);
2274 /* Record the number of bytes pushed. */
2275 for (n = 0; n < 16; n++)
2277 if (range & (1 << n))
2278 unwind.frame_size += 4;
2283 /* Parse a directive saving FPA registers. */
2286 s_arm_unwind_save_fpa (int reg)
2292 /* Get Number of registers to transfer. */
2293 if (skip_past_comma (&input_line_pointer) != FAIL)
2296 exp.X_op = O_illegal;
2298 if (exp.X_op != O_constant)
2300 as_bad (_("expected , <constant>"));
2301 ignore_rest_of_line ();
2305 num_regs = exp.X_add_number;
2307 if (num_regs < 1 || num_regs > 4)
2309 as_bad (_("number of registers must be in the range [1:4]"));
2310 ignore_rest_of_line ();
2314 demand_empty_rest_of_line ();
2319 op = 0xb4 | (num_regs - 1);
2320 add_unwind_opcode (op, 1);
2325 op = 0xc800 | (reg << 4) | (num_regs - 1);
2326 add_unwind_opcode (op, 2);
2328 unwind.frame_size += num_regs * 12;
2332 /* Parse a directive saving VFP registers. */
2335 s_arm_unwind_save_vfp (void)
2341 count = parse_vfp_reg_list (&input_line_pointer, ®, 1);
2344 as_bad (_("expected register list"));
2345 ignore_rest_of_line ();
2349 demand_empty_rest_of_line ();
2354 op = 0xb8 | (count - 1);
2355 add_unwind_opcode (op, 1);
2360 op = 0xb300 | (reg << 4) | (count - 1);
2361 add_unwind_opcode (op, 2);
2363 unwind.frame_size += count * 8 + 4;
2367 /* Parse a directive saving iWMMXt data registers. */
2370 s_arm_unwind_save_mmxwr (void)
2378 if (*input_line_pointer == '{')
2379 input_line_pointer++;
2383 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2387 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2392 as_tsktsk (_("register list not in ascending order"));
2395 if (*input_line_pointer == '-')
2397 input_line_pointer++;
2398 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
2401 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWR]));
2404 else if (reg >= hi_reg)
2406 as_bad (_("bad register range"));
2409 for (; reg < hi_reg; reg++)
2413 while (skip_past_comma (&input_line_pointer) != FAIL);
2415 if (*input_line_pointer == '}')
2416 input_line_pointer++;
2418 demand_empty_rest_of_line ();
2420 /* Generate any deferred opcodes becuuse we're going to be looking at
2422 flush_pending_unwind ();
2424 for (i = 0; i < 16; i++)
2426 if (mask & (1 << i))
2427 unwind.frame_size += 8;
2430 /* Attempt to combine with a previous opcode. We do this because gcc
2431 likes to output separate unwind directives for a single block of
2433 if (unwind.opcode_count > 0)
2435 i = unwind.opcodes[unwind.opcode_count - 1];
2436 if ((i & 0xf8) == 0xc0)
2439 /* Only merge if the blocks are contiguous. */
2442 if ((mask & 0xfe00) == (1 << 9))
2444 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
2445 unwind.opcode_count--;
2448 else if (i == 6 && unwind.opcode_count >= 2)
2450 i = unwind.opcodes[unwind.opcode_count - 2];
2454 op = 0xffff << (reg - 1);
2456 || ((mask & op) == (1u << (reg - 1))))
2458 op = (1 << (reg + i + 1)) - 1;
2459 op &= ~((1 << reg) - 1);
2461 unwind.opcode_count -= 2;
2468 /* We want to generate opcodes in the order the registers have been
2469 saved, ie. descending order. */
2470 for (reg = 15; reg >= -1; reg--)
2472 /* Save registers in blocks. */
2474 || !(mask & (1 << reg)))
2476 /* We found an unsaved reg. Generate opcodes to save the
2477 preceeding block. */
2483 op = 0xc0 | (hi_reg - 10);
2484 add_unwind_opcode (op, 1);
2489 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
2490 add_unwind_opcode (op, 2);
2499 ignore_rest_of_line ();
2503 s_arm_unwind_save_mmxwcg (void)
2510 if (*input_line_pointer == '{')
2511 input_line_pointer++;
2515 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2519 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2525 as_tsktsk (_("register list not in ascending order"));
2528 if (*input_line_pointer == '-')
2530 input_line_pointer++;
2531 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
2534 as_bad (_(reg_expected_msgs[REG_TYPE_MMXWCG]));
2537 else if (reg >= hi_reg)
2539 as_bad (_("bad register range"));
2542 for (; reg < hi_reg; reg++)
2546 while (skip_past_comma (&input_line_pointer) != FAIL);
2548 if (*input_line_pointer == '}')
2549 input_line_pointer++;
2551 demand_empty_rest_of_line ();
2553 /* Generate any deferred opcodes becuuse we're going to be looking at
2555 flush_pending_unwind ();
2557 for (reg = 0; reg < 16; reg++)
2559 if (mask & (1 << reg))
2560 unwind.frame_size += 4;
2563 add_unwind_opcode (op, 2);
2566 ignore_rest_of_line ();
2570 /* Parse an unwind_save directive. */
2573 s_arm_unwind_save (int ignored ATTRIBUTE_UNUSED)
2576 struct reg_entry *reg;
2577 bfd_boolean had_brace = FALSE;
2579 /* Figure out what sort of save we have. */
2580 peek = input_line_pointer;
2588 reg = arm_reg_parse_multi (&peek);
2592 as_bad (_("register expected"));
2593 ignore_rest_of_line ();
2602 as_bad (_("FPA .unwind_save does not take a register list"));
2603 ignore_rest_of_line ();
2606 s_arm_unwind_save_fpa (reg->number);
2609 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
2610 case REG_TYPE_VFD: s_arm_unwind_save_vfp (); return;
2611 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
2612 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
2615 as_bad (_(".unwind_save does not support this kind of register"));
2616 ignore_rest_of_line ();
2621 /* Parse an unwind_movsp directive. */
2624 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
2629 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2632 as_bad (_(reg_expected_msgs[REG_TYPE_RN]));
2633 ignore_rest_of_line ();
2636 demand_empty_rest_of_line ();
2638 if (reg == REG_SP || reg == REG_PC)
2640 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
2644 if (unwind.fp_reg != REG_SP)
2645 as_bad (_("unexpected .unwind_movsp directive"));
2647 /* Generate opcode to restore the value. */
2649 add_unwind_opcode (op, 1);
2651 /* Record the information for later. */
2652 unwind.fp_reg = reg;
2653 unwind.fp_offset = unwind.frame_size;
2654 unwind.sp_restored = 1;
2657 /* Parse an unwind_pad directive. */
2660 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
2664 if (immediate_for_directive (&offset) == FAIL)
2669 as_bad (_("stack increment must be multiple of 4"));
2670 ignore_rest_of_line ();
2674 /* Don't generate any opcodes, just record the details for later. */
2675 unwind.frame_size += offset;
2676 unwind.pending_offset += offset;
2678 demand_empty_rest_of_line ();
2681 /* Parse an unwind_setfp directive. */
2684 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
2690 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2691 if (skip_past_comma (&input_line_pointer) == FAIL)
2694 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
2696 if (fp_reg == FAIL || sp_reg == FAIL)
2698 as_bad (_("expected <reg>, <reg>"));
2699 ignore_rest_of_line ();
2703 /* Optional constant. */
2704 if (skip_past_comma (&input_line_pointer) != FAIL)
2706 if (immediate_for_directive (&offset) == FAIL)
2712 demand_empty_rest_of_line ();
2714 if (sp_reg != 13 && sp_reg != unwind.fp_reg)
2716 as_bad (_("register must be either sp or set by a previous"
2717 "unwind_movsp directive"));
2721 /* Don't generate any opcodes, just record the information for later. */
2722 unwind.fp_reg = fp_reg;
2725 unwind.fp_offset = unwind.frame_size - offset;
2727 unwind.fp_offset -= offset;
2730 /* Parse an unwind_raw directive. */
2733 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
2736 /* This is an arbitary limit. */
2737 unsigned char op[16];
2741 if (exp.X_op == O_constant
2742 && skip_past_comma (&input_line_pointer) != FAIL)
2744 unwind.frame_size += exp.X_add_number;
2748 exp.X_op = O_illegal;
2750 if (exp.X_op != O_constant)
2752 as_bad (_("expected <offset>, <opcode>"));
2753 ignore_rest_of_line ();
2759 /* Parse the opcode. */
2764 as_bad (_("unwind opcode too long"));
2765 ignore_rest_of_line ();
2767 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
2769 as_bad (_("invalid unwind opcode"));
2770 ignore_rest_of_line ();
2773 op[count++] = exp.X_add_number;
2775 /* Parse the next byte. */
2776 if (skip_past_comma (&input_line_pointer) == FAIL)
2782 /* Add the opcode bytes in reverse order. */
2784 add_unwind_opcode (op[count], 1);
2786 demand_empty_rest_of_line ();
2788 #endif /* OBJ_ELF */
2790 /* This table describes all the machine specific pseudo-ops the assembler
2791 has to support. The fields are:
2792 pseudo-op name without dot
2793 function to call to execute this pseudo-op
2794 Integer arg to pass to the function. */
2796 const pseudo_typeS md_pseudo_table[] =
2798 /* Never called because '.req' does not start a line. */
2799 { "req", s_req, 0 },
2800 { "unreq", s_unreq, 0 },
2801 { "bss", s_bss, 0 },
2802 { "align", s_align, 0 },
2803 { "arm", s_arm, 0 },
2804 { "thumb", s_thumb, 0 },
2805 { "code", s_code, 0 },
2806 { "force_thumb", s_force_thumb, 0 },
2807 { "thumb_func", s_thumb_func, 0 },
2808 { "thumb_set", s_thumb_set, 0 },
2809 { "even", s_even, 0 },
2810 { "ltorg", s_ltorg, 0 },
2811 { "pool", s_ltorg, 0 },
2812 { "syntax", s_syntax, 0 },
2814 { "word", s_arm_elf_cons, 4 },
2815 { "long", s_arm_elf_cons, 4 },
2816 { "rel31", s_arm_rel31, 0 },
2817 { "fnstart", s_arm_unwind_fnstart, 0 },
2818 { "fnend", s_arm_unwind_fnend, 0 },
2819 { "cantunwind", s_arm_unwind_cantunwind, 0 },
2820 { "personality", s_arm_unwind_personality, 0 },
2821 { "personalityindex", s_arm_unwind_personalityindex, 0 },
2822 { "handlerdata", s_arm_unwind_handlerdata, 0 },
2823 { "save", s_arm_unwind_save, 0 },
2824 { "movsp", s_arm_unwind_movsp, 0 },
2825 { "pad", s_arm_unwind_pad, 0 },
2826 { "setfp", s_arm_unwind_setfp, 0 },
2827 { "unwind_raw", s_arm_unwind_raw, 0 },
2831 { "extend", float_cons, 'x' },
2832 { "ldouble", float_cons, 'x' },
2833 { "packed", float_cons, 'p' },
2837 /* Parser functions used exclusively in instruction operands. */
2839 /* Generic immediate-value read function for use in insn parsing.
2840 STR points to the beginning of the immediate (the leading #);
2841 VAL receives the value; if the value is outside [MIN, MAX]
2842 issue an error. PREFIX_OPT is true if the immediate prefix is
2846 parse_immediate (char **str, int *val, int min, int max,
2847 bfd_boolean prefix_opt)
2850 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
2851 if (exp.X_op != O_constant)
2853 inst.error = _("constant expression required");
2857 if (exp.X_add_number < min || exp.X_add_number > max)
2859 inst.error = _("immediate value out of range");
2863 *val = exp.X_add_number;
2867 /* Returns the pseudo-register number of an FPA immediate constant,
2868 or FAIL if there isn't a valid constant here. */
2871 parse_fpa_immediate (char ** str)
2873 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2879 /* First try and match exact strings, this is to guarantee
2880 that some formats will work even for cross assembly. */
2882 for (i = 0; fp_const[i]; i++)
2884 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2888 *str += strlen (fp_const[i]);
2889 if (is_end_of_line[(unsigned char) **str])
2895 /* Just because we didn't get a match doesn't mean that the constant
2896 isn't valid, just that it is in a format that we don't
2897 automatically recognize. Try parsing it with the standard
2898 expression routines. */
2900 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2902 /* Look for a raw floating point number. */
2903 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2904 && is_end_of_line[(unsigned char) *save_in])
2906 for (i = 0; i < NUM_FLOAT_VALS; i++)
2908 for (j = 0; j < MAX_LITTLENUMS; j++)
2910 if (words[j] != fp_values[i][j])
2914 if (j == MAX_LITTLENUMS)
2922 /* Try and parse a more complex expression, this will probably fail
2923 unless the code uses a floating point prefix (eg "0f"). */
2924 save_in = input_line_pointer;
2925 input_line_pointer = *str;
2926 if (expression (&exp) == absolute_section
2927 && exp.X_op == O_big
2928 && exp.X_add_number < 0)
2930 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2932 if (gen_to_words (words, 5, (long) 15) == 0)
2934 for (i = 0; i < NUM_FLOAT_VALS; i++)
2936 for (j = 0; j < MAX_LITTLENUMS; j++)
2938 if (words[j] != fp_values[i][j])
2942 if (j == MAX_LITTLENUMS)
2944 *str = input_line_pointer;
2945 input_line_pointer = save_in;
2952 *str = input_line_pointer;
2953 input_line_pointer = save_in;
2954 inst.error = _("invalid FPA immediate expression");
2958 /* Shift operands. */
2961 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
2964 struct asm_shift_name
2967 enum shift_kind kind;
2970 /* Third argument to parse_shift. */
2971 enum parse_shift_mode
2973 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
2974 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
2975 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
2976 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
2977 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
2980 /* Parse a <shift> specifier on an ARM data processing instruction.
2981 This has three forms:
2983 (LSL|LSR|ASL|ASR|ROR) Rs
2984 (LSL|LSR|ASL|ASR|ROR) #imm
2987 Note that ASL is assimilated to LSL in the instruction encoding, and
2988 RRX to ROR #0 (which cannot be written as such). */
2991 parse_shift (char **str, int i, enum parse_shift_mode mode)
2993 const struct asm_shift_name *shift_name;
2994 enum shift_kind shift;
2999 for (p = *str; ISALPHA (*p); p++)
3004 inst.error = _("shift expression expected");
3008 shift_name = hash_find_n (arm_shift_hsh, *str, p - *str);
3010 if (shift_name == NULL)
3012 inst.error = _("shift expression expected");
3016 shift = shift_name->kind;
3020 case NO_SHIFT_RESTRICT:
3021 case SHIFT_IMMEDIATE: break;
3023 case SHIFT_LSL_OR_ASR_IMMEDIATE:
3024 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
3026 inst.error = _("'LSL' or 'ASR' required");
3031 case SHIFT_LSL_IMMEDIATE:
3032 if (shift != SHIFT_LSL)
3034 inst.error = _("'LSL' required");
3039 case SHIFT_ASR_IMMEDIATE:
3040 if (shift != SHIFT_ASR)
3042 inst.error = _("'ASR' required");
3050 if (shift != SHIFT_RRX)
3052 /* Whitespace can appear here if the next thing is a bare digit. */
3053 skip_whitespace (p);
3055 if (mode == NO_SHIFT_RESTRICT
3056 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3058 inst.operands[i].imm = reg;
3059 inst.operands[i].immisreg = 1;
3061 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3064 inst.operands[i].shift_kind = shift;
3065 inst.operands[i].shifted = 1;
3070 /* Parse a <shifter_operand> for an ARM data processing instruction:
3073 #<immediate>, <rotate>
3077 where <shift> is defined by parse_shift above, and <rotate> is a
3078 multiple of 2 between 0 and 30. Validation of immediate operands
3079 is deferred to md_apply_fix. */
3082 parse_shifter_operand (char **str, int i)
3087 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
3089 inst.operands[i].reg = value;
3090 inst.operands[i].isreg = 1;
3092 /* parse_shift will override this if appropriate */
3093 inst.reloc.exp.X_op = O_constant;
3094 inst.reloc.exp.X_add_number = 0;
3096 if (skip_past_comma (str) == FAIL)
3099 /* Shift operation on register. */
3100 return parse_shift (str, i, NO_SHIFT_RESTRICT);
3103 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
3106 if (skip_past_comma (str) == SUCCESS)
3108 /* #x, y -- ie explicit rotation by Y. */
3109 if (my_get_expression (&expr, str, GE_NO_PREFIX))
3112 if (expr.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
3114 inst.error = _("constant expression expected");
3118 value = expr.X_add_number;
3119 if (value < 0 || value > 30 || value % 2 != 0)
3121 inst.error = _("invalid rotation");
3124 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
3126 inst.error = _("invalid constant");
3130 /* Convert to decoded value. md_apply_fix will put it back. */
3131 inst.reloc.exp.X_add_number
3132 = (((inst.reloc.exp.X_add_number << (32 - value))
3133 | (inst.reloc.exp.X_add_number >> value)) & 0xffffffff);
3136 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
3137 inst.reloc.pc_rel = 0;
3141 /* Parse all forms of an ARM address expression. Information is written
3142 to inst.operands[i] and/or inst.reloc.
3144 Preindexed addressing (.preind=1):
3146 [Rn, #offset] .reg=Rn .reloc.exp=offset
3147 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3148 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3149 .shift_kind=shift .reloc.exp=shift_imm
3151 These three may have a trailing ! which causes .writeback to be set also.
3153 Postindexed addressing (.postind=1, .writeback=1):
3155 [Rn], #offset .reg=Rn .reloc.exp=offset
3156 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3157 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
3158 .shift_kind=shift .reloc.exp=shift_imm
3160 Unindexed addressing (.preind=0, .postind=0):
3162 [Rn], {option} .reg=Rn .imm=option .immisreg=0
3166 [Rn]{!} shorthand for [Rn,#0]{!}
3167 =immediate .isreg=0 .reloc.exp=immediate
3168 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
3170 It is the caller's responsibility to check for addressing modes not
3171 supported by the instruction, and to set inst.reloc.type. */
3174 parse_address (char **str, int i)
3179 if (skip_past_char (&p, '[') == FAIL)
3181 if (skip_past_char (&p, '=') == FAIL)
3183 /* bare address - translate to PC-relative offset */
3184 inst.reloc.pc_rel = 1;
3185 inst.operands[i].reg = REG_PC;
3186 inst.operands[i].isreg = 1;
3187 inst.operands[i].preind = 1;
3189 /* else a load-constant pseudo op, no special treatment needed here */
3191 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
3198 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3200 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3203 inst.operands[i].reg = reg;
3204 inst.operands[i].isreg = 1;
3206 if (skip_past_comma (&p) == SUCCESS)
3208 inst.operands[i].preind = 1;
3211 else if (*p == '-') p++, inst.operands[i].negative = 1;
3213 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3215 inst.operands[i].imm = reg;
3216 inst.operands[i].immisreg = 1;
3218 if (skip_past_comma (&p) == SUCCESS)
3219 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3224 if (inst.operands[i].negative)
3226 inst.operands[i].negative = 0;
3229 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3234 if (skip_past_char (&p, ']') == FAIL)
3236 inst.error = _("']' expected");
3240 if (skip_past_char (&p, '!') == SUCCESS)
3241 inst.operands[i].writeback = 1;
3243 else if (skip_past_comma (&p) == SUCCESS)
3245 if (skip_past_char (&p, '{') == SUCCESS)
3247 /* [Rn], {expr} - unindexed, with option */
3248 if (parse_immediate (&p, &inst.operands[i].imm,
3249 0, 255, TRUE) == FAIL)
3252 if (skip_past_char (&p, '}') == FAIL)
3254 inst.error = _("'}' expected at end of 'option' field");
3257 if (inst.operands[i].preind)
3259 inst.error = _("cannot combine index with option");
3267 inst.operands[i].postind = 1;
3268 inst.operands[i].writeback = 1;
3270 if (inst.operands[i].preind)
3272 inst.error = _("cannot combine pre- and post-indexing");
3277 else if (*p == '-') p++, inst.operands[i].negative = 1;
3279 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
3281 inst.operands[i].imm = reg;
3282 inst.operands[i].immisreg = 1;
3284 if (skip_past_comma (&p) == SUCCESS)
3285 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
3290 if (inst.operands[i].negative)
3292 inst.operands[i].negative = 0;
3295 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
3301 /* If at this point neither .preind nor .postind is set, we have a
3302 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
3303 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
3305 inst.operands[i].preind = 1;
3306 inst.reloc.exp.X_op = O_constant;
3307 inst.reloc.exp.X_add_number = 0;
3313 /* Miscellaneous. */
3315 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
3316 or a bitmask suitable to be or-ed into the ARM msr instruction. */
3318 parse_psr (char **str)
3321 unsigned long psr_field;
3323 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
3324 feature for ease of use and backwards compatibility. */
3326 if (*p == 's' || *p == 'S')
3327 psr_field = SPSR_BIT;
3328 else if (*p == 'c' || *p == 'C')
3334 if (strncasecmp (p, "PSR", 3) != 0)
3340 /* A suffix follows. */
3341 const struct asm_psr *psr;
3349 while (ISALNUM (*p) || *p == '_');
3351 psr = hash_find_n (arm_psr_hsh, start, p - start);
3355 psr_field |= psr->field;
3360 goto error; /* Garbage after "[CS]PSR". */
3362 psr_field |= (PSR_c | PSR_f);
3368 inst.error = _("flag for {c}psr instruction expected");
3372 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
3373 value suitable for splatting into the AIF field of the instruction. */
3376 parse_cps_flags (char **str)
3385 case '\0': case ',':
3388 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
3389 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
3390 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
3393 inst.error = _("unrecognized CPS flag");
3398 if (saw_a_flag == 0)
3400 inst.error = _("missing CPS flags");
3408 /* Parse an endian specifier ("BE" or "LE", case insensitive);
3409 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
3412 parse_endian_specifier (char **str)
3417 if (strncasecmp (s, "BE", 2))
3419 else if (strncasecmp (s, "LE", 2))
3423 inst.error = _("valid endian specifiers are be or le");
3427 if (ISALNUM (s[2]) || s[2] == '_')
3429 inst.error = _("valid endian specifiers are be or le");
3434 return little_endian;
3437 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
3438 value suitable for poking into the rotate field of an sxt or sxta
3439 instruction, or FAIL on error. */
3442 parse_ror (char **str)
3447 if (strncasecmp (s, "ROR", 3) == 0)
3451 inst.error = _("missing rotation field after comma");
3455 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
3460 case 0: *str = s; return 0x0;
3461 case 8: *str = s; return 0x1;
3462 case 16: *str = s; return 0x2;
3463 case 24: *str = s; return 0x3;
3466 inst.error = _("rotation can only be 0, 8, 16, or 24");
3471 /* Parse a conditional code (from conds[] below). The value returned is in the
3472 range 0 .. 14, or FAIL. */
3474 parse_cond (char **str)
3477 const struct asm_cond *c;
3480 while (ISALPHA (*q))
3483 c = hash_find_n (arm_cond_hsh, p, q - p);
3486 inst.error = _("condition required");
3494 /* Parse the operands of a table branch instruction. Similar to a memory
3497 parse_tb (char **str)
3502 if (skip_past_char (&p, '[') == FAIL)
3505 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3507 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3510 inst.operands[0].reg = reg;
3512 if (skip_past_comma (&p) == FAIL)
3515 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
3517 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
3520 inst.operands[0].imm = reg;
3522 if (skip_past_comma (&p) == SUCCESS)
3524 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
3526 if (inst.reloc.exp.X_add_number != 1)
3528 inst.error = _("invalid shift");
3531 inst.operands[0].shifted = 1;
3534 if (skip_past_char (&p, ']') == FAIL)
3536 inst.error = _("']' expected");
3543 /* Matcher codes for parse_operands. */
3544 enum operand_parse_code
3546 OP_stop, /* end of line */
3548 OP_RR, /* ARM register */
3549 OP_RRnpc, /* ARM register, not r15 */
3550 OP_RRnpcb, /* ARM register, not r15, in square brackets */
3551 OP_RRw, /* ARM register, not r15, optional trailing ! */
3552 OP_RCP, /* Coprocessor number */
3553 OP_RCN, /* Coprocessor register */
3554 OP_RF, /* FPA register */
3555 OP_RVS, /* VFP single precision register */
3556 OP_RVD, /* VFP double precision register */
3557 OP_RVC, /* VFP control register */
3558 OP_RMF, /* Maverick F register */
3559 OP_RMD, /* Maverick D register */
3560 OP_RMFX, /* Maverick FX register */
3561 OP_RMDX, /* Maverick DX register */
3562 OP_RMAX, /* Maverick AX register */
3563 OP_RMDS, /* Maverick DSPSC register */
3564 OP_RIWR, /* iWMMXt wR register */
3565 OP_RIWC, /* iWMMXt wC register */
3566 OP_RIWG, /* iWMMXt wCG register */
3567 OP_RXA, /* XScale accumulator register */
3569 OP_REGLST, /* ARM register list */
3570 OP_VRSLST, /* VFP single-precision register list */
3571 OP_VRDLST, /* VFP double-precision register list */
3573 OP_I7, /* immediate value 0 .. 7 */
3574 OP_I15, /* 0 .. 15 */
3575 OP_I16, /* 1 .. 16 */
3576 OP_I31, /* 0 .. 31 */
3577 OP_I31w, /* 0 .. 31, optional trailing ! */
3578 OP_I32, /* 1 .. 32 */
3579 OP_I63s, /* -64 .. 63 */
3580 OP_I255, /* 0 .. 255 */
3581 OP_Iffff, /* 0 .. 65535 */
3583 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
3584 OP_I7b, /* 0 .. 7 */
3585 OP_I15b, /* 0 .. 15 */
3586 OP_I31b, /* 0 .. 31 */
3588 OP_SH, /* shifter operand */
3589 OP_ADDR, /* Memory address expression (any mode) */
3590 OP_EXP, /* arbitrary expression */
3591 OP_EXPi, /* same, with optional immediate prefix */
3592 OP_EXPr, /* same, with optional relocation suffix */
3594 OP_CPSF, /* CPS flags */
3595 OP_ENDI, /* Endianness specifier */
3596 OP_PSR, /* CPSR/SPSR mask for msr */
3597 OP_COND, /* conditional code */
3598 OP_TB, /* Table branch. */
3600 OP_RRnpc_I0, /* ARM register or literal 0 */
3601 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
3602 OP_RR_EXi, /* ARM register or expression with imm prefix */
3603 OP_RF_IF, /* FPA register or immediate */
3604 OP_RIWR_RIWC, /* iWMMXt R or C reg */
3606 /* Optional operands. */
3607 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
3608 OP_oI31b, /* 0 .. 31 */
3609 OP_oIffffb, /* 0 .. 65535 */
3610 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
3612 OP_oRR, /* ARM register */
3613 OP_oRRnpc, /* ARM register, not the PC */
3614 OP_oSHll, /* LSL immediate */
3615 OP_oSHar, /* ASR immediate */
3616 OP_oSHllar, /* LSL or ASR immediate */
3617 OP_oROR, /* ROR 0/8/16/24 */
3619 OP_FIRST_OPTIONAL = OP_oI7b
3622 /* Generic instruction operand parser. This does no encoding and no
3623 semantic validation; it merely squirrels values away in the inst
3624 structure. Returns SUCCESS or FAIL depending on whether the
3625 specified grammar matched. */
3627 parse_operands (char *str, const unsigned char *pattern)
3629 unsigned const char *upat = pattern;
3630 char *backtrack_pos = 0;
3631 const char *backtrack_error = 0;
3632 int i, val, backtrack_index = 0;
3634 #define po_char_or_fail(chr) do { \
3635 if (skip_past_char (&str, chr) == FAIL) \
3639 #define po_reg_or_fail(regtype) do { \
3640 val = arm_reg_parse (&str, regtype); \
3643 inst.error = _(reg_expected_msgs[regtype]); \
3646 inst.operands[i].reg = val; \
3647 inst.operands[i].isreg = 1; \
3650 #define po_reg_or_goto(regtype, label) do { \
3651 val = arm_reg_parse (&str, regtype); \
3655 inst.operands[i].reg = val; \
3656 inst.operands[i].isreg = 1; \
3659 #define po_imm_or_fail(min, max, popt) do { \
3660 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
3662 inst.operands[i].imm = val; \
3665 #define po_misc_or_fail(expr) do { \
3670 skip_whitespace (str);
3672 for (i = 0; upat[i] != OP_stop; i++)
3674 if (upat[i] >= OP_FIRST_OPTIONAL)
3676 /* Remember where we are in case we need to backtrack. */
3677 assert (!backtrack_pos);
3678 backtrack_pos = str;
3679 backtrack_error = inst.error;
3680 backtrack_index = i;
3684 po_char_or_fail (',');
3692 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
3693 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
3694 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
3695 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
3696 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
3697 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
3698 case OP_RVC: po_reg_or_fail (REG_TYPE_VFC); break;
3699 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
3700 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
3701 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
3702 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
3703 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
3704 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
3705 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
3706 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
3707 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
3708 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
3711 po_char_or_fail ('[');
3712 po_reg_or_fail (REG_TYPE_RN);
3713 po_char_or_fail (']');
3717 po_reg_or_fail (REG_TYPE_RN);
3718 if (skip_past_char (&str, '!') == SUCCESS)
3719 inst.operands[i].writeback = 1;
3723 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
3724 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
3725 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
3726 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
3727 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
3728 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
3729 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
3730 case OP_Iffff: po_imm_or_fail ( 0, 0xffff, FALSE); break;
3732 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
3734 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
3735 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
3737 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
3738 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
3740 /* Immediate variants */
3742 po_char_or_fail ('{');
3743 po_imm_or_fail (0, 255, TRUE);
3744 po_char_or_fail ('}');
3748 /* The expression parser chokes on a trailing !, so we have
3749 to find it first and zap it. */
3752 while (*s && *s != ',')
3757 inst.operands[i].writeback = 1;
3759 po_imm_or_fail (0, 31, TRUE);
3767 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3772 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3777 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
3779 if (inst.reloc.exp.X_op == O_symbol)
3781 val = parse_reloc (&str);
3784 inst.error = _("unrecognized relocation suffix");
3787 else if (val != BFD_RELOC_UNUSED)
3789 inst.operands[i].imm = val;
3790 inst.operands[i].hasreloc = 1;
3795 /* Register or expression */
3796 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
3797 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
3799 /* Register or immediate */
3800 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
3801 I0: po_imm_or_fail (0, 0, FALSE); break;
3803 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
3805 if (!is_immediate_prefix (*str))
3808 val = parse_fpa_immediate (&str);
3811 /* FPA immediates are encoded as registers 8-15.
3812 parse_fpa_immediate has already applied the offset. */
3813 inst.operands[i].reg = val;
3814 inst.operands[i].isreg = 1;
3817 /* Two kinds of register */
3820 struct reg_entry *rege = arm_reg_parse_multi (&str);
3821 if (rege->type != REG_TYPE_MMXWR
3822 && rege->type != REG_TYPE_MMXWC
3823 && rege->type != REG_TYPE_MMXWCG)
3825 inst.error = _("iWMMXt data or control register expected");
3828 inst.operands[i].reg = rege->number;
3829 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
3834 case OP_CPSF: val = parse_cps_flags (&str); break;
3835 case OP_ENDI: val = parse_endian_specifier (&str); break;
3836 case OP_oROR: val = parse_ror (&str); break;
3837 case OP_PSR: val = parse_psr (&str); break;
3838 case OP_COND: val = parse_cond (&str); break;
3841 po_misc_or_fail (parse_tb (&str));
3844 /* Register lists */
3846 val = parse_reg_list (&str);
3849 inst.operands[1].writeback = 1;
3855 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 0);
3859 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, 1);
3862 /* Addressing modes */
3864 po_misc_or_fail (parse_address (&str, i));
3868 po_misc_or_fail (parse_shifter_operand (&str, i));
3872 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
3876 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
3880 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
3884 as_fatal ("unhandled operand code %d", upat[i]);
3887 /* Various value-based sanity checks and shared operations. We
3888 do not signal immediate failures for the register constraints;
3889 this allows a syntax error to take precedence. */
3897 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
3898 inst.error = BAD_PC;
3911 inst.operands[i].imm = val;
3918 /* If we get here, this operand was successfully parsed. */
3919 inst.operands[i].present = 1;
3923 inst.error = BAD_ARGS;
3929 /* Do not backtrack over a trailing optional argument that
3930 absorbed some text. We will only fail again, with the
3931 'garbage following instruction' error message, which is
3932 probably less helpful than the current one. */
3933 if (backtrack_index == i && backtrack_pos != str
3934 && upat[i+1] == OP_stop)
3937 /* Try again, skipping the optional argument at backtrack_pos. */
3938 str = backtrack_pos;
3939 inst.error = backtrack_error;
3940 inst.operands[backtrack_index].present = 0;
3941 i = backtrack_index;
3945 /* Check that we have parsed all the arguments. */
3946 if (*str != '\0' && !inst.error)
3947 inst.error = _("garbage following instruction");
3949 return inst.error ? FAIL : SUCCESS;
3952 #undef po_char_or_fail
3953 #undef po_reg_or_fail
3954 #undef po_reg_or_goto
3955 #undef po_imm_or_fail
3957 /* Shorthand macro for instruction encoding functions issuing errors. */
3958 #define constraint(expr, err) do { \
3966 /* Functions for operand encoding. ARM, then Thumb. */
3968 #define rotate_left(v, n) (v << n | v >> (32 - n))
3970 /* If VAL can be encoded in the immediate field of an ARM instruction,
3971 return the encoded form. Otherwise, return FAIL. */
3974 encode_arm_immediate (unsigned int val)
3978 for (i = 0; i < 32; i += 2)
3979 if ((a = rotate_left (val, i)) <= 0xff)
3980 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
3985 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
3986 return the encoded form. Otherwise, return FAIL. */
3988 encode_thumb32_immediate (unsigned int val)
3995 for (i = 0; i < 32; i++)
3997 a = rotate_left (val, i);
3998 if (a >= 128 && a <= 255)
3999 return (a & 0x7f) | (i << 7);
4003 if (val == ((a << 16) | a))
4005 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
4009 if (val == ((a << 16) | a))
4010 return 0x200 | (a >> 8);
4014 /* Encode a VFP SP register number into inst.instruction. */
4017 encode_arm_vfp_sp_reg (int reg, enum vfp_sp_reg_pos pos)
4022 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
4026 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
4030 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
4038 /* Encode a <shift> in an ARM-format instruction. The immediate,
4039 if any, is handled by md_apply_fix. */
4041 encode_arm_shift (int i)
4043 if (inst.operands[i].shift_kind == SHIFT_RRX)
4044 inst.instruction |= SHIFT_ROR << 5;
4047 inst.instruction |= inst.operands[i].shift_kind << 5;
4048 if (inst.operands[i].immisreg)
4050 inst.instruction |= SHIFT_BY_REG;
4051 inst.instruction |= inst.operands[i].imm << 8;
4054 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4059 encode_arm_shifter_operand (int i)
4061 if (inst.operands[i].isreg)
4063 inst.instruction |= inst.operands[i].reg;
4064 encode_arm_shift (i);
4067 inst.instruction |= INST_IMMEDIATE;
4070 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
4072 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
4074 assert (inst.operands[i].isreg);
4075 inst.instruction |= inst.operands[i].reg << 16;
4077 if (inst.operands[i].preind)
4081 inst.error = _("instruction does not accept preindexed addressing");
4084 inst.instruction |= PRE_INDEX;
4085 if (inst.operands[i].writeback)
4086 inst.instruction |= WRITE_BACK;
4089 else if (inst.operands[i].postind)
4091 assert (inst.operands[i].writeback);
4093 inst.instruction |= WRITE_BACK;
4095 else /* unindexed - only for coprocessor */
4097 inst.error = _("instruction does not accept unindexed addressing");
4101 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
4102 && (((inst.instruction & 0x000f0000) >> 16)
4103 == ((inst.instruction & 0x0000f000) >> 12)))
4104 as_warn ((inst.instruction & LOAD_BIT)
4105 ? _("destination register same as write-back base")
4106 : _("source register same as write-back base"));
4109 /* inst.operands[i] was set up by parse_address. Encode it into an
4110 ARM-format mode 2 load or store instruction. If is_t is true,
4111 reject forms that cannot be used with a T instruction (i.e. not
4114 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
4116 encode_arm_addr_mode_common (i, is_t);
4118 if (inst.operands[i].immisreg)
4120 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
4121 inst.instruction |= inst.operands[i].imm;
4122 if (!inst.operands[i].negative)
4123 inst.instruction |= INDEX_UP;
4124 if (inst.operands[i].shifted)
4126 if (inst.operands[i].shift_kind == SHIFT_RRX)
4127 inst.instruction |= SHIFT_ROR << 5;
4130 inst.instruction |= inst.operands[i].shift_kind << 5;
4131 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
4135 else /* immediate offset in inst.reloc */
4137 if (inst.reloc.type == BFD_RELOC_UNUSED)
4138 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
4142 /* inst.operands[i] was set up by parse_address. Encode it into an
4143 ARM-format mode 3 load or store instruction. Reject forms that
4144 cannot be used with such instructions. If is_t is true, reject
4145 forms that cannot be used with a T instruction (i.e. not
4148 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
4150 if (inst.operands[i].immisreg && inst.operands[i].shifted)
4152 inst.error = _("instruction does not accept scaled register index");
4156 encode_arm_addr_mode_common (i, is_t);
4158 if (inst.operands[i].immisreg)
4160 inst.instruction |= inst.operands[i].imm;
4161 if (!inst.operands[i].negative)
4162 inst.instruction |= INDEX_UP;
4164 else /* immediate offset in inst.reloc */
4166 inst.instruction |= HWOFFSET_IMM;
4167 if (inst.reloc.type == BFD_RELOC_UNUSED)
4168 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
4172 /* inst.operands[i] was set up by parse_address. Encode it into an
4173 ARM-format instruction. Reject all forms which cannot be encoded
4174 into a coprocessor load/store instruction. If wb_ok is false,
4175 reject use of writeback; if unind_ok is false, reject use of
4176 unindexed addressing. If reloc_override is not 0, use it instead
4177 of BFD_ARM_CP_OFF_IMM. */
4180 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
4182 inst.instruction |= inst.operands[i].reg << 16;
4184 assert (!(inst.operands[i].preind && inst.operands[i].postind));
4186 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
4188 assert (!inst.operands[i].writeback);
4191 inst.error = _("instruction does not support unindexed addressing");
4194 inst.instruction |= inst.operands[i].imm;
4195 inst.instruction |= INDEX_UP;
4199 if (inst.operands[i].preind)
4200 inst.instruction |= PRE_INDEX;
4202 if (inst.operands[i].writeback)
4204 if (inst.operands[i].reg == REG_PC)
4206 inst.error = _("pc may not be used with write-back");
4211 inst.error = _("instruction does not support writeback");
4214 inst.instruction |= WRITE_BACK;
4218 inst.reloc.type = reloc_override;
4220 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4224 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
4225 Determine whether it can be performed with a move instruction; if
4226 it can, convert inst.instruction to that move instruction and
4227 return 1; if it can't, convert inst.instruction to a literal-pool
4228 load and return 0. If this is not a valid thing to do in the
4229 current context, set inst.error and return 1.
4231 inst.operands[i] describes the destination register. */
4234 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
4236 if ((inst.instruction & (thumb_p ? THUMB_LOAD_BIT : LOAD_BIT)) == 0)
4238 inst.error = _("invalid pseudo operation");
4241 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
4243 inst.error = _("constant expression expected");
4246 if (inst.reloc.exp.X_op == O_constant)
4250 if ((inst.reloc.exp.X_add_number & ~0xFF) == 0)
4252 /* This can be done with a mov(1) instruction. */
4253 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
4254 inst.instruction |= inst.reloc.exp.X_add_number;
4260 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
4263 /* This can be done with a mov instruction. */
4264 inst.instruction &= LITERAL_MASK;
4265 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
4266 inst.instruction |= value & 0xfff;
4270 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
4273 /* This can be done with a mvn instruction. */
4274 inst.instruction &= LITERAL_MASK;
4275 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
4276 inst.instruction |= value & 0xfff;
4282 if (add_to_lit_pool () == FAIL)
4284 inst.error = _("literal pool insertion failed");
4287 inst.operands[1].reg = REG_PC;
4288 inst.operands[1].isreg = 1;
4289 inst.operands[1].preind = 1;
4290 inst.reloc.pc_rel = 1;
4291 inst.reloc.type = (thumb_p
4292 ? BFD_RELOC_ARM_THUMB_OFFSET
4294 ? BFD_RELOC_ARM_HWLITERAL
4295 : BFD_RELOC_ARM_LITERAL));
4299 /* Functions for instruction encoding, sorted by subarchitecture.
4300 First some generics; their names are taken from the conventional
4301 bit positions for register arguments in ARM format instructions. */
4311 inst.instruction |= inst.operands[0].reg << 12;
4317 inst.instruction |= inst.operands[0].reg << 12;
4318 inst.instruction |= inst.operands[1].reg;
4324 inst.instruction |= inst.operands[0].reg << 12;
4325 inst.instruction |= inst.operands[1].reg << 16;
4331 inst.instruction |= inst.operands[0].reg << 16;
4332 inst.instruction |= inst.operands[1].reg << 12;
4338 inst.instruction |= inst.operands[0].reg << 12;
4339 inst.instruction |= inst.operands[1].reg;
4340 inst.instruction |= inst.operands[2].reg << 16;
4346 inst.instruction |= inst.operands[0].reg << 12;
4347 inst.instruction |= inst.operands[1].reg << 16;
4348 inst.instruction |= inst.operands[2].reg;
4354 inst.instruction |= inst.operands[0].reg;
4355 inst.instruction |= inst.operands[1].reg << 12;
4356 inst.instruction |= inst.operands[2].reg << 16;
4362 inst.instruction |= inst.operands[0].imm;
4368 inst.instruction |= inst.operands[0].reg << 12;
4369 encode_arm_cp_address (1, TRUE, TRUE, 0);
4372 /* ARM instructions, in alphabetical order by function name (except
4373 that wrapper functions appear immediately after the function they
4376 /* This is a pseudo-op of the form "adr rd, label" to be converted
4377 into a relative address of the form "add rd, pc, #label-.-8". */
4382 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4384 /* Frag hacking will turn this into a sub instruction if the offset turns
4385 out to be negative. */
4386 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4387 inst.reloc.pc_rel = 1;
4388 inst.reloc.exp.X_add_number -= 8;
4391 /* This is a pseudo-op of the form "adrl rd, label" to be converted
4392 into a relative address of the form:
4393 add rd, pc, #low(label-.-8)"
4394 add rd, rd, #high(label-.-8)" */
4399 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
4401 /* Frag hacking will turn this into a sub instruction if the offset turns
4402 out to be negative. */
4403 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
4404 inst.reloc.pc_rel = 1;
4405 inst.size = INSN_SIZE * 2;
4406 inst.reloc.exp.X_add_number -= 8;
4412 if (!inst.operands[1].present)
4413 inst.operands[1].reg = inst.operands[0].reg;
4414 inst.instruction |= inst.operands[0].reg << 12;
4415 inst.instruction |= inst.operands[1].reg << 16;
4416 encode_arm_shifter_operand (2);
4422 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
4423 constraint (msb > 32, _("bit-field extends past end of register"));
4424 /* The instruction encoding stores the LSB and MSB,
4425 not the LSB and width. */
4426 inst.instruction |= inst.operands[0].reg << 12;
4427 inst.instruction |= inst.operands[1].imm << 7;
4428 inst.instruction |= (msb - 1) << 16;
4436 /* #0 in second position is alternative syntax for bfc, which is
4437 the same instruction but with REG_PC in the Rm field. */
4438 if (!inst.operands[1].isreg)
4439 inst.operands[1].reg = REG_PC;
4441 msb = inst.operands[2].imm + inst.operands[3].imm;
4442 constraint (msb > 32, _("bit-field extends past end of register"));
4443 /* The instruction encoding stores the LSB and MSB,
4444 not the LSB and width. */
4445 inst.instruction |= inst.operands[0].reg << 12;
4446 inst.instruction |= inst.operands[1].reg;
4447 inst.instruction |= inst.operands[2].imm << 7;
4448 inst.instruction |= (msb - 1) << 16;
4454 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
4455 _("bit-field extends past end of register"));
4456 inst.instruction |= inst.operands[0].reg << 12;
4457 inst.instruction |= inst.operands[1].reg;
4458 inst.instruction |= inst.operands[2].imm << 7;
4459 inst.instruction |= (inst.operands[3].imm - 1) << 16;
4462 /* ARM V5 breakpoint instruction (argument parse)
4463 BKPT <16 bit unsigned immediate>
4464 Instruction is not conditional.
4465 The bit pattern given in insns[] has the COND_ALWAYS condition,
4466 and it is an error if the caller tried to override that. */
4471 /* Top 12 of 16 bits to bits 19:8. */
4472 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
4474 /* Bottom 4 of 16 bits to bits 3:0. */
4475 inst.instruction |= inst.operands[0].imm & 0xf;
4479 encode_branch (int default_reloc)
4481 if (inst.operands[0].hasreloc)
4483 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32,
4484 _("the only suffix valid here is '(plt)'"));
4485 inst.reloc.type = BFD_RELOC_ARM_PLT32;
4489 inst.reloc.type = default_reloc;
4491 inst.reloc.pc_rel = 1;
4497 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
4500 /* ARM V5 branch-link-exchange instruction (argument parse)
4501 BLX <target_addr> ie BLX(1)
4502 BLX{<condition>} <Rm> ie BLX(2)
4503 Unfortunately, there are two different opcodes for this mnemonic.
4504 So, the insns[].value is not used, and the code here zaps values
4505 into inst.instruction.
4506 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
4511 if (inst.operands[0].isreg)
4513 /* Arg is a register; the opcode provided by insns[] is correct.
4514 It is not illegal to do "blx pc", just useless. */
4515 if (inst.operands[0].reg == REG_PC)
4516 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
4518 inst.instruction |= inst.operands[0].reg;
4522 /* Arg is an address; this instruction cannot be executed
4523 conditionally, and the opcode must be adjusted. */
4524 constraint (inst.cond != COND_ALWAYS, BAD_COND);
4525 inst.instruction = 0xfa000000;
4526 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
4533 if (inst.operands[0].reg == REG_PC)
4534 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
4536 inst.instruction |= inst.operands[0].reg;
4540 /* ARM v5TEJ. Jump to Jazelle code. */
4545 if (inst.operands[0].reg == REG_PC)
4546 as_tsktsk (_("use of r15 in bxj is not really useful"));
4548 inst.instruction |= inst.operands[0].reg;
4551 /* Co-processor data operation:
4552 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
4553 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
4557 inst.instruction |= inst.operands[0].reg << 8;
4558 inst.instruction |= inst.operands[1].imm << 20;
4559 inst.instruction |= inst.operands[2].reg << 12;
4560 inst.instruction |= inst.operands[3].reg << 16;
4561 inst.instruction |= inst.operands[4].reg;
4562 inst.instruction |= inst.operands[5].imm << 5;
4568 inst.instruction |= inst.operands[0].reg << 16;
4569 encode_arm_shifter_operand (1);
4572 /* Transfer between coprocessor and ARM registers.
4573 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
4578 No special properties. */
4583 inst.instruction |= inst.operands[0].reg << 8;
4584 inst.instruction |= inst.operands[1].imm << 21;
4585 inst.instruction |= inst.operands[2].reg << 12;
4586 inst.instruction |= inst.operands[3].reg << 16;
4587 inst.instruction |= inst.operands[4].reg;
4588 inst.instruction |= inst.operands[5].imm << 5;
4591 /* Transfer between coprocessor register and pair of ARM registers.
4592 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
4597 Two XScale instructions are special cases of these:
4599 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
4600 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
4602 Result unpredicatable if Rd or Rn is R15. */
4607 inst.instruction |= inst.operands[0].reg << 8;
4608 inst.instruction |= inst.operands[1].imm << 4;
4609 inst.instruction |= inst.operands[2].reg << 12;
4610 inst.instruction |= inst.operands[3].reg << 16;
4611 inst.instruction |= inst.operands[4].reg;
4617 inst.instruction |= inst.operands[0].imm << 6;
4618 inst.instruction |= inst.operands[1].imm;
4624 /* There is no IT instruction in ARM mode. We
4625 process it but do not generate code for it. */
4632 int base_reg = inst.operands[0].reg;
4633 int range = inst.operands[1].imm;
4635 inst.instruction |= base_reg << 16;
4636 inst.instruction |= range;
4638 if (inst.operands[1].writeback)
4639 inst.instruction |= LDM_TYPE_2_OR_3;
4641 if (inst.operands[0].writeback)
4643 inst.instruction |= WRITE_BACK;
4644 /* Check for unpredictable uses of writeback. */
4645 if (inst.instruction & LOAD_BIT)
4647 /* Not allowed in LDM type 2. */
4648 if ((inst.instruction & LDM_TYPE_2_OR_3)
4649 && ((range & (1 << REG_PC)) == 0))
4650 as_warn (_("writeback of base register is UNPREDICTABLE"));
4651 /* Only allowed if base reg not in list for other types. */
4652 else if (range & (1 << base_reg))
4653 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
4657 /* Not allowed for type 2. */
4658 if (inst.instruction & LDM_TYPE_2_OR_3)
4659 as_warn (_("writeback of base register is UNPREDICTABLE"));
4660 /* Only allowed if base reg not in list, or first in list. */
4661 else if ((range & (1 << base_reg))
4662 && (range & ((1 << base_reg) - 1)))
4663 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
4668 /* ARMv5TE load-consecutive (argument parse)
4677 constraint (inst.operands[0].reg % 2 != 0,
4678 _("first destination register must be even"));
4679 constraint (inst.operands[1].present
4680 && inst.operands[1].reg != inst.operands[0].reg + 1,
4681 _("can only load two consecutive registers"));
4682 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4683 constraint (!inst.operands[2].isreg, _("'[' expected"));
4685 if (!inst.operands[1].present)
4686 inst.operands[1].reg = inst.operands[0].reg + 1;
4688 if (inst.instruction & LOAD_BIT)
4690 /* encode_arm_addr_mode_3 will diagnose overlap between the base
4691 register and the first register written; we have to diagnose
4692 overlap between the base and the second register written here. */
4694 if (inst.operands[2].reg == inst.operands[1].reg
4695 && (inst.operands[2].writeback || inst.operands[2].postind))
4696 as_warn (_("base register written back, and overlaps "
4697 "second destination register"));
4699 /* For an index-register load, the index register must not overlap the
4700 destination (even if not write-back). */
4701 else if (inst.operands[2].immisreg
4702 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
4703 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
4704 as_warn (_("index register overlaps destination register"));
4707 inst.instruction |= inst.operands[0].reg << 12;
4708 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
4714 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
4715 || inst.operands[1].postind || inst.operands[1].writeback
4716 || inst.operands[1].immisreg || inst.operands[1].shifted
4717 || inst.operands[1].negative,
4718 _("instruction does not accept this addressing mode"));
4720 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
4722 constraint (inst.reloc.exp.X_op != O_constant
4723 || inst.reloc.exp.X_add_number != 0,
4724 _("offset must be zero in ARM encoding"));
4726 inst.instruction |= inst.operands[0].reg << 12;
4727 inst.instruction |= inst.operands[1].reg << 16;
4728 inst.reloc.type = BFD_RELOC_UNUSED;
4734 constraint (inst.operands[0].reg % 2 != 0,
4735 _("even register required"));
4736 constraint (inst.operands[1].present
4737 && inst.operands[1].reg != inst.operands[0].reg + 1,
4738 _("can only load two consecutive registers"));
4739 /* If op 1 were present and equal to PC, this function wouldn't
4740 have been called in the first place. */
4741 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
4743 inst.instruction |= inst.operands[0].reg << 12;
4744 inst.instruction |= inst.operands[2].reg << 16;
4750 inst.instruction |= inst.operands[0].reg << 12;
4751 if (!inst.operands[1].isreg)
4752 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
4754 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
4760 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4762 if (inst.operands[1].preind)
4764 constraint (inst.reloc.exp.X_op != O_constant ||
4765 inst.reloc.exp.X_add_number != 0,
4766 _("this instruction requires a post-indexed address"));
4768 inst.operands[1].preind = 0;
4769 inst.operands[1].postind = 1;
4770 inst.operands[1].writeback = 1;
4772 inst.instruction |= inst.operands[0].reg << 12;
4773 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
4776 /* Halfword and signed-byte load/store operations. */
4781 inst.instruction |= inst.operands[0].reg << 12;
4782 if (!inst.operands[1].isreg)
4783 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
4785 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
4791 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
4793 if (inst.operands[1].preind)
4795 constraint (inst.reloc.exp.X_op != O_constant ||
4796 inst.reloc.exp.X_add_number != 0,
4797 _("this instruction requires a post-indexed address"));
4799 inst.operands[1].preind = 0;
4800 inst.operands[1].postind = 1;
4801 inst.operands[1].writeback = 1;
4803 inst.instruction |= inst.operands[0].reg << 12;
4804 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
4807 /* Co-processor register load/store.
4808 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
4812 inst.instruction |= inst.operands[0].reg << 8;
4813 inst.instruction |= inst.operands[1].reg << 12;
4814 encode_arm_cp_address (2, TRUE, TRUE, 0);
4820 /* This restriction does not apply to mls (nor to mla in v6, but
4821 that's hard to detect at present). */
4822 if (inst.operands[0].reg == inst.operands[1].reg
4823 && !(inst.instruction & 0x00400000))
4824 as_tsktsk (_("rd and rm should be different in mla"));
4826 inst.instruction |= inst.operands[0].reg << 16;
4827 inst.instruction |= inst.operands[1].reg;
4828 inst.instruction |= inst.operands[2].reg << 8;
4829 inst.instruction |= inst.operands[3].reg << 12;
4836 inst.instruction |= inst.operands[0].reg << 12;
4837 encode_arm_shifter_operand (1);
4840 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
4844 inst.instruction |= inst.operands[0].reg << 12;
4845 /* The value is in two pieces: 0:11, 16:19. */
4846 inst.instruction |= (inst.operands[1].imm & 0x00000fff);
4847 inst.instruction |= (inst.operands[1].imm & 0x0000f000) << 4;
4853 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
4854 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
4856 _("'CPSR' or 'SPSR' expected"));
4857 inst.instruction |= inst.operands[0].reg << 12;
4858 inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
4861 /* Two possible forms:
4862 "{C|S}PSR_<field>, Rm",
4863 "{C|S}PSR_f, #expression". */
4868 inst.instruction |= inst.operands[0].imm;
4869 if (inst.operands[1].isreg)
4870 inst.instruction |= inst.operands[1].reg;
4873 inst.instruction |= INST_IMMEDIATE;
4874 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4875 inst.reloc.pc_rel = 0;
4882 if (!inst.operands[2].present)
4883 inst.operands[2].reg = inst.operands[0].reg;
4884 inst.instruction |= inst.operands[0].reg << 16;
4885 inst.instruction |= inst.operands[1].reg;
4886 inst.instruction |= inst.operands[2].reg << 8;
4888 if (inst.operands[0].reg == inst.operands[1].reg)
4889 as_tsktsk (_("rd and rm should be different in mul"));
4892 /* Long Multiply Parser
4893 UMULL RdLo, RdHi, Rm, Rs
4894 SMULL RdLo, RdHi, Rm, Rs
4895 UMLAL RdLo, RdHi, Rm, Rs
4896 SMLAL RdLo, RdHi, Rm, Rs. */
4901 inst.instruction |= inst.operands[0].reg << 12;
4902 inst.instruction |= inst.operands[1].reg << 16;
4903 inst.instruction |= inst.operands[2].reg;
4904 inst.instruction |= inst.operands[3].reg << 8;
4906 /* rdhi, rdlo and rm must all be different. */
4907 if (inst.operands[0].reg == inst.operands[1].reg
4908 || inst.operands[0].reg == inst.operands[2].reg
4909 || inst.operands[1].reg == inst.operands[2].reg)
4910 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
4916 if (inst.operands[0].present)
4918 /* Architectural NOP hints are CPSR sets with no bits selected. */
4919 inst.instruction &= 0xf0000000;
4920 inst.instruction |= 0x0320f000 + inst.operands[0].imm;
4924 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
4925 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
4926 Condition defaults to COND_ALWAYS.
4927 Error if Rd, Rn or Rm are R15. */
4932 inst.instruction |= inst.operands[0].reg << 12;
4933 inst.instruction |= inst.operands[1].reg << 16;
4934 inst.instruction |= inst.operands[2].reg;
4935 if (inst.operands[3].present)
4936 encode_arm_shift (3);
4939 /* ARM V6 PKHTB (Argument Parse). */
4944 if (!inst.operands[3].present)
4946 /* If the shift specifier is omitted, turn the instruction
4947 into pkhbt rd, rm, rn. */
4948 inst.instruction &= 0xfff00010;
4949 inst.instruction |= inst.operands[0].reg << 12;
4950 inst.instruction |= inst.operands[1].reg;
4951 inst.instruction |= inst.operands[2].reg << 16;
4955 inst.instruction |= inst.operands[0].reg << 12;
4956 inst.instruction |= inst.operands[1].reg << 16;
4957 inst.instruction |= inst.operands[2].reg;
4958 encode_arm_shift (3);
4962 /* ARMv5TE: Preload-Cache
4966 Syntactically, like LDR with B=1, W=0, L=1. */
4971 constraint (!inst.operands[0].isreg,
4972 _("'[' expected after PLD mnemonic"));
4973 constraint (inst.operands[0].postind,
4974 _("post-indexed expression used in preload instruction"));
4975 constraint (inst.operands[0].writeback,
4976 _("writeback used in preload instruction"));
4977 constraint (!inst.operands[0].preind,
4978 _("unindexed addressing used in preload instruction"));
4979 inst.instruction |= inst.operands[0].reg;
4980 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
4986 inst.operands[1] = inst.operands[0];
4987 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
4988 inst.operands[0].isreg = 1;
4989 inst.operands[0].writeback = 1;
4990 inst.operands[0].reg = REG_SP;
4994 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
4995 word at the specified address and the following word
4997 Unconditionally executed.
4998 Error if Rn is R15. */
5003 inst.instruction |= inst.operands[0].reg << 16;
5004 if (inst.operands[0].writeback)
5005 inst.instruction |= WRITE_BACK;
5008 /* ARM V6 ssat (argument parse). */
5013 inst.instruction |= inst.operands[0].reg << 12;
5014 inst.instruction |= (inst.operands[1].imm - 1) << 16;
5015 inst.instruction |= inst.operands[2].reg;
5017 if (inst.operands[3].present)
5018 encode_arm_shift (3);
5021 /* ARM V6 usat (argument parse). */
5026 inst.instruction |= inst.operands[0].reg << 12;
5027 inst.instruction |= inst.operands[1].imm << 16;
5028 inst.instruction |= inst.operands[2].reg;
5030 if (inst.operands[3].present)
5031 encode_arm_shift (3);
5034 /* ARM V6 ssat16 (argument parse). */
5039 inst.instruction |= inst.operands[0].reg << 12;
5040 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
5041 inst.instruction |= inst.operands[2].reg;
5047 inst.instruction |= inst.operands[0].reg << 12;
5048 inst.instruction |= inst.operands[1].imm << 16;
5049 inst.instruction |= inst.operands[2].reg;
5052 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
5053 preserving the other bits.
5055 setend <endian_specifier>, where <endian_specifier> is either
5061 if (inst.operands[0].imm)
5062 inst.instruction |= 0x200;
5068 unsigned int Rm = (inst.operands[1].present
5069 ? inst.operands[1].reg
5070 : inst.operands[0].reg);
5072 inst.instruction |= inst.operands[0].reg << 12;
5073 inst.instruction |= Rm;
5074 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
5076 constraint (inst.operands[0].reg != Rm,
5077 _("source1 and dest must be same register"));
5078 inst.instruction |= inst.operands[2].reg << 8;
5079 inst.instruction |= SHIFT_BY_REG;
5082 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
5088 inst.reloc.type = BFD_RELOC_ARM_SMI;
5089 inst.reloc.pc_rel = 0;
5095 inst.reloc.type = BFD_RELOC_ARM_SWI;
5096 inst.reloc.pc_rel = 0;
5099 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
5100 SMLAxy{cond} Rd,Rm,Rs,Rn
5101 SMLAWy{cond} Rd,Rm,Rs,Rn
5102 Error if any register is R15. */
5107 inst.instruction |= inst.operands[0].reg << 16;
5108 inst.instruction |= inst.operands[1].reg;
5109 inst.instruction |= inst.operands[2].reg << 8;
5110 inst.instruction |= inst.operands[3].reg << 12;
5113 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
5114 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
5115 Error if any register is R15.
5116 Warning if Rdlo == Rdhi. */
5121 inst.instruction |= inst.operands[0].reg << 12;
5122 inst.instruction |= inst.operands[1].reg << 16;
5123 inst.instruction |= inst.operands[2].reg;
5124 inst.instruction |= inst.operands[3].reg << 8;
5126 if (inst.operands[0].reg == inst.operands[1].reg)
5127 as_tsktsk (_("rdhi and rdlo must be different"));
5130 /* ARM V5E (El Segundo) signed-multiply (argument parse)
5131 SMULxy{cond} Rd,Rm,Rs
5132 Error if any register is R15. */
5137 inst.instruction |= inst.operands[0].reg << 16;
5138 inst.instruction |= inst.operands[1].reg;
5139 inst.instruction |= inst.operands[2].reg << 8;
5142 /* ARM V6 srs (argument parse). */
5147 inst.instruction |= inst.operands[0].imm;
5148 if (inst.operands[0].writeback)
5149 inst.instruction |= WRITE_BACK;
5152 /* ARM V6 strex (argument parse). */
5157 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
5158 || inst.operands[2].postind || inst.operands[2].writeback
5159 || inst.operands[2].immisreg || inst.operands[2].shifted
5160 || inst.operands[2].negative,
5161 _("instruction does not accept this addressing mode"));
5163 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
5165 constraint (inst.operands[0].reg == inst.operands[1].reg
5166 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
5168 constraint (inst.reloc.exp.X_op != O_constant
5169 || inst.reloc.exp.X_add_number != 0,
5170 _("offset must be zero in ARM encoding"));
5172 inst.instruction |= inst.operands[0].reg << 12;
5173 inst.instruction |= inst.operands[1].reg;
5174 inst.instruction |= inst.operands[2].reg << 16;
5175 inst.reloc.type = BFD_RELOC_UNUSED;
5181 constraint (inst.operands[1].reg % 2 != 0,
5182 _("even register required"));
5183 constraint (inst.operands[2].present
5184 && inst.operands[2].reg != inst.operands[1].reg + 1,
5185 _("can only store two consecutive registers"));
5186 /* If op 2 were present and equal to PC, this function wouldn't
5187 have been called in the first place. */
5188 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
5190 constraint (inst.operands[0].reg == inst.operands[1].reg
5191 || inst.operands[0].reg == inst.operands[1].reg + 1
5192 || inst.operands[0].reg == inst.operands[3].reg,
5195 inst.instruction |= inst.operands[0].reg << 12;
5196 inst.instruction |= inst.operands[1].reg;
5197 inst.instruction |= inst.operands[3].reg << 16;
5200 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
5201 extends it to 32-bits, and adds the result to a value in another
5202 register. You can specify a rotation by 0, 8, 16, or 24 bits
5203 before extracting the 16-bit value.
5204 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
5205 Condition defaults to COND_ALWAYS.
5206 Error if any register uses R15. */
5211 inst.instruction |= inst.operands[0].reg << 12;
5212 inst.instruction |= inst.operands[1].reg << 16;
5213 inst.instruction |= inst.operands[2].reg;
5214 inst.instruction |= inst.operands[3].imm << 10;
5219 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
5220 Condition defaults to COND_ALWAYS.
5221 Error if any register uses R15. */
5226 inst.instruction |= inst.operands[0].reg << 12;
5227 inst.instruction |= inst.operands[1].reg;
5228 inst.instruction |= inst.operands[2].imm << 10;
5231 /* VFP instructions. In a logical order: SP variant first, monad
5232 before dyad, arithmetic then move then load/store. */
5235 do_vfp_sp_monadic (void)
5237 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5238 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5242 do_vfp_sp_dyadic (void)
5244 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5245 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5246 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5250 do_vfp_sp_compare_z (void)
5252 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5256 do_vfp_dp_sp_cvt (void)
5258 inst.instruction |= inst.operands[0].reg << 12;
5259 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sm);
5263 do_vfp_sp_dp_cvt (void)
5265 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5266 inst.instruction |= inst.operands[1].reg;
5270 do_vfp_reg_from_sp (void)
5272 inst.instruction |= inst.operands[0].reg << 12;
5273 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sn);
5277 do_vfp_reg2_from_sp2 (void)
5279 constraint (inst.operands[2].imm != 2,
5280 _("only two consecutive VFP SP registers allowed here"));
5281 inst.instruction |= inst.operands[0].reg << 12;
5282 inst.instruction |= inst.operands[1].reg << 16;
5283 encode_arm_vfp_sp_reg (inst.operands[2].reg, VFP_REG_Sm);
5287 do_vfp_sp_from_reg (void)
5289 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sn);
5290 inst.instruction |= inst.operands[1].reg << 12;
5294 do_vfp_sp2_from_reg2 (void)
5296 constraint (inst.operands[0].imm != 2,
5297 _("only two consecutive VFP SP registers allowed here"));
5298 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sm);
5299 inst.instruction |= inst.operands[1].reg << 12;
5300 inst.instruction |= inst.operands[2].reg << 16;
5304 do_vfp_sp_ldst (void)
5306 encode_arm_vfp_sp_reg (inst.operands[0].reg, VFP_REG_Sd);
5307 encode_arm_cp_address (1, FALSE, TRUE, 0);
5311 do_vfp_dp_ldst (void)
5313 inst.instruction |= inst.operands[0].reg << 12;
5314 encode_arm_cp_address (1, FALSE, TRUE, 0);
5319 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
5321 if (inst.operands[0].writeback)
5322 inst.instruction |= WRITE_BACK;
5324 constraint (ldstm_type != VFP_LDSTMIA,
5325 _("this addressing mode requires base-register writeback"));
5326 inst.instruction |= inst.operands[0].reg << 16;
5327 encode_arm_vfp_sp_reg (inst.operands[1].reg, VFP_REG_Sd);
5328 inst.instruction |= inst.operands[1].imm;
5332 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
5336 if (inst.operands[0].writeback)
5337 inst.instruction |= WRITE_BACK;
5339 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
5340 _("this addressing mode requires base-register writeback"));
5342 inst.instruction |= inst.operands[0].reg << 16;
5343 inst.instruction |= inst.operands[1].reg << 12;
5345 count = inst.operands[1].imm << 1;
5346 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
5349 inst.instruction |= count;
5353 do_vfp_sp_ldstmia (void)
5355 vfp_sp_ldstm (VFP_LDSTMIA);
5359 do_vfp_sp_ldstmdb (void)
5361 vfp_sp_ldstm (VFP_LDSTMDB);
5365 do_vfp_dp_ldstmia (void)
5367 vfp_dp_ldstm (VFP_LDSTMIA);
5371 do_vfp_dp_ldstmdb (void)
5373 vfp_dp_ldstm (VFP_LDSTMDB);
5377 do_vfp_xp_ldstmia (void)
5379 vfp_dp_ldstm (VFP_LDSTMIAX);
5383 do_vfp_xp_ldstmdb (void)
5385 vfp_dp_ldstm (VFP_LDSTMDBX);
5388 /* FPA instructions. Also in a logical order. */
5393 inst.instruction |= inst.operands[0].reg << 16;
5394 inst.instruction |= inst.operands[1].reg;
5398 do_fpa_ldmstm (void)
5400 inst.instruction |= inst.operands[0].reg << 12;
5401 switch (inst.operands[1].imm)
5403 case 1: inst.instruction |= CP_T_X; break;
5404 case 2: inst.instruction |= CP_T_Y; break;
5405 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
5410 if (inst.instruction & (PRE_INDEX | INDEX_UP))
5412 /* The instruction specified "ea" or "fd", so we can only accept
5413 [Rn]{!}. The instruction does not really support stacking or
5414 unstacking, so we have to emulate these by setting appropriate
5415 bits and offsets. */
5416 constraint (inst.reloc.exp.X_op != O_constant
5417 || inst.reloc.exp.X_add_number != 0,
5418 _("this instruction does not support indexing"));
5420 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
5421 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
5423 if (!(inst.instruction & INDEX_UP))
5424 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
5426 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
5428 inst.operands[2].preind = 0;
5429 inst.operands[2].postind = 1;
5433 encode_arm_cp_address (2, TRUE, TRUE, 0);
5436 /* iWMMXt instructions: strictly in alphabetical order. */
5439 do_iwmmxt_tandorc (void)
5441 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
5445 do_iwmmxt_textrc (void)
5447 inst.instruction |= inst.operands[0].reg << 12;
5448 inst.instruction |= inst.operands[1].imm;
5452 do_iwmmxt_textrm (void)
5454 inst.instruction |= inst.operands[0].reg << 12;
5455 inst.instruction |= inst.operands[1].reg << 16;
5456 inst.instruction |= inst.operands[2].imm;
5460 do_iwmmxt_tinsr (void)
5462 inst.instruction |= inst.operands[0].reg << 16;
5463 inst.instruction |= inst.operands[1].reg << 12;
5464 inst.instruction |= inst.operands[2].imm;
5468 do_iwmmxt_tmia (void)
5470 inst.instruction |= inst.operands[0].reg << 5;
5471 inst.instruction |= inst.operands[1].reg;
5472 inst.instruction |= inst.operands[2].reg << 12;
5476 do_iwmmxt_waligni (void)
5478 inst.instruction |= inst.operands[0].reg << 12;
5479 inst.instruction |= inst.operands[1].reg << 16;
5480 inst.instruction |= inst.operands[2].reg;
5481 inst.instruction |= inst.operands[3].imm << 20;
5485 do_iwmmxt_wmov (void)
5487 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
5488 inst.instruction |= inst.operands[0].reg << 12;
5489 inst.instruction |= inst.operands[1].reg << 16;
5490 inst.instruction |= inst.operands[1].reg;
5494 do_iwmmxt_wldstbh (void)
5496 inst.instruction |= inst.operands[0].reg << 12;
5497 inst.reloc.exp.X_add_number *= 4;
5498 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5502 do_iwmmxt_wldstw (void)
5504 /* RIWR_RIWC clears .isreg for a control register. */
5505 if (!inst.operands[0].isreg)
5507 constraint (inst.cond != COND_ALWAYS, BAD_COND);
5508 inst.instruction |= 0xf0000000;
5511 inst.instruction |= inst.operands[0].reg << 12;
5512 encode_arm_cp_address (1, TRUE, TRUE, 0);
5516 do_iwmmxt_wldstd (void)
5518 inst.instruction |= inst.operands[0].reg << 12;
5519 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_CP_OFF_IMM_S2);
5523 do_iwmmxt_wshufh (void)
5525 inst.instruction |= inst.operands[0].reg << 12;
5526 inst.instruction |= inst.operands[1].reg << 16;
5527 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
5528 inst.instruction |= (inst.operands[2].imm & 0x0f);
5532 do_iwmmxt_wzero (void)
5534 /* WZERO reg is an alias for WANDN reg, reg, reg. */
5535 inst.instruction |= inst.operands[0].reg;
5536 inst.instruction |= inst.operands[0].reg << 12;
5537 inst.instruction |= inst.operands[0].reg << 16;
5540 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
5541 operations first, then control, shift, and load/store. */
5543 /* Insns like "foo X,Y,Z". */
5546 do_mav_triple (void)
5548 inst.instruction |= inst.operands[0].reg << 16;
5549 inst.instruction |= inst.operands[1].reg;
5550 inst.instruction |= inst.operands[2].reg << 12;
5553 /* Insns like "foo W,X,Y,Z".
5554 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
5559 inst.instruction |= inst.operands[0].reg << 5;
5560 inst.instruction |= inst.operands[1].reg << 12;
5561 inst.instruction |= inst.operands[2].reg << 16;
5562 inst.instruction |= inst.operands[3].reg;
5565 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
5569 inst.instruction |= inst.operands[1].reg << 12;
5572 /* Maverick shift immediate instructions.
5573 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
5574 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
5579 int imm = inst.operands[2].imm;
5581 inst.instruction |= inst.operands[0].reg << 12;
5582 inst.instruction |= inst.operands[1].reg << 16;
5584 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
5585 Bits 5-7 of the insn should have bits 4-6 of the immediate.
5586 Bit 4 should be 0. */
5587 imm = (imm & 0xf) | ((imm & 0x70) << 1);
5589 inst.instruction |= imm;
5592 /* XScale instructions. Also sorted arithmetic before move. */
5594 /* Xscale multiply-accumulate (argument parse)
5597 MIAxycc acc0,Rm,Rs. */
5602 inst.instruction |= inst.operands[1].reg;
5603 inst.instruction |= inst.operands[2].reg << 12;
5606 /* Xscale move-accumulator-register (argument parse)
5608 MARcc acc0,RdLo,RdHi. */
5613 inst.instruction |= inst.operands[1].reg << 12;
5614 inst.instruction |= inst.operands[2].reg << 16;
5617 /* Xscale move-register-accumulator (argument parse)
5619 MRAcc RdLo,RdHi,acc0. */
5624 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
5625 inst.instruction |= inst.operands[0].reg << 12;
5626 inst.instruction |= inst.operands[1].reg << 16;
5629 /* Encoding functions relevant only to Thumb. */
5631 /* inst.operands[i] is a shifted-register operand; encode
5632 it into inst.instruction in the format used by Thumb32. */
5635 encode_thumb32_shifted_operand (int i)
5637 unsigned int value = inst.reloc.exp.X_add_number;
5638 unsigned int shift = inst.operands[i].shift_kind;
5640 inst.instruction |= inst.operands[i].reg;
5641 if (shift == SHIFT_RRX)
5642 inst.instruction |= SHIFT_ROR << 4;
5645 constraint (inst.reloc.exp.X_op != O_constant,
5646 _("expression too complex"));
5648 constraint (value > 32
5649 || (value == 32 && (shift == SHIFT_LSL
5650 || shift == SHIFT_ROR)),
5651 _("shift expression is too large"));
5655 else if (value == 32)
5658 inst.instruction |= shift << 4;
5659 inst.instruction |= (value & 0x1c) << 10;
5660 inst.instruction |= (value & 0x03) << 6;
5665 /* inst.operands[i] was set up by parse_address. Encode it into a
5666 Thumb32 format load or store instruction. Reject forms that cannot
5667 be used with such instructions. If is_t is true, reject forms that
5668 cannot be used with a T instruction; if is_d is true, reject forms
5669 that cannot be used with a D instruction. */
5672 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
5674 bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
5676 constraint (!inst.operands[i].isreg,
5677 _("Thumb does not support the ldr =N pseudo-operation"));
5679 inst.instruction |= inst.operands[i].reg << 16;
5680 if (inst.operands[i].immisreg)
5682 constraint (is_pc, _("cannot use register index with PC-relative addressing"));
5683 constraint (is_t || is_d, _("cannot use register index with this instruction"));
5684 constraint (inst.operands[i].negative,
5685 _("Thumb does not support negative register indexing"));
5686 constraint (inst.operands[i].postind,
5687 _("Thumb does not support register post-indexing"));
5688 constraint (inst.operands[i].writeback,
5689 _("Thumb does not support register indexing with writeback"));
5690 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
5691 _("Thumb supports only LSL in shifted register indexing"));
5693 inst.instruction |= inst.operands[1].imm;
5694 if (inst.operands[i].shifted)
5696 constraint (inst.reloc.exp.X_op != O_constant,
5697 _("expression too complex"));
5698 constraint (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 3,
5699 _("shift out of range"));
5700 inst.instruction |= inst.reloc.exp.X_op << 4;
5702 inst.reloc.type = BFD_RELOC_UNUSED;
5704 else if (inst.operands[i].preind)
5706 constraint (is_pc && inst.operands[i].writeback,
5707 _("cannot use writeback with PC-relative addressing"));
5708 constraint (is_t && inst.operands[1].writeback,
5709 _("cannot use writeback with this instruction"));
5713 inst.instruction |= 0x01000000;
5714 if (inst.operands[i].writeback)
5715 inst.instruction |= 0x00200000;
5719 inst.instruction |= 0x00000c00;
5720 if (inst.operands[i].writeback)
5721 inst.instruction |= 0x00000100;
5723 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5725 else if (inst.operands[i].postind)
5727 assert (inst.operands[i].writeback);
5728 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
5729 constraint (is_t, _("cannot use post-indexing with this instruction"));
5732 inst.instruction |= 0x00200000;
5734 inst.instruction |= 0x00000900;
5735 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
5737 else /* unindexed - only for coprocessor */
5738 inst.error = _("instruction does not accept unindexed addressing");
5741 /* Table of Thumb instructions which exist in both 16- and 32-bit
5742 encodings (the latter only in post-V6T2 cores). The index is the
5743 value used in the insns table below. When there is more than one
5744 possible 16-bit encoding for the instruction, this table always
5745 holds variant (1). */
5746 #define T16_32_TAB \
5747 X(adc, 4140, eb400000), \
5748 X(adcs, 4140, eb500000), \
5749 X(add, 1c00, eb000000), \
5750 X(adds, 1c00, eb100000), \
5751 X(adr, 000f, f20f0000), \
5752 X(and, 4000, ea000000), \
5753 X(ands, 4000, ea100000), \
5754 X(asr, 1000, fa40f000), \
5755 X(asrs, 1000, fa50f000), \
5756 X(bic, 4380, ea200000), \
5757 X(bics, 4380, ea300000), \
5758 X(cmn, 42c0, eb100f00), \
5759 X(cmp, 2800, ebb00f00), \
5760 X(cpsie, b660, f3af8400), \
5761 X(cpsid, b670, f3af8600), \
5762 X(cpy, 4600, ea4f0000), \
5763 X(eor, 4040, ea800000), \
5764 X(eors, 4040, ea900000), \
5765 X(ldmia, c800, e8900000), \
5766 X(ldr, 6800, f8500000), \
5767 X(ldrb, 7800, f8100000), \
5768 X(ldrh, 8800, f8300000), \
5769 X(ldrsb, 5600, f9100000), \
5770 X(ldrsh, 5e00, f9300000), \
5771 X(lsl, 0000, fa00f000), \
5772 X(lsls, 0000, fa10f000), \
5773 X(lsr, 0800, fa20f000), \
5774 X(lsrs, 0800, fa30f000), \
5775 X(mov, 2000, ea4f0000), \
5776 X(movs, 2000, ea5f0000), \
5777 X(mul, 4340, fb00f000), \
5778 X(muls, 4340, ffffffff), /* no 32b muls */ \
5779 X(mvn, 43c0, ea6f0000), \
5780 X(mvns, 43c0, ea7f0000), \
5781 X(neg, 4240, f1c00000), /* rsb #0 */ \
5782 X(negs, 4240, f1d00000), /* rsbs #0 */ \
5783 X(orr, 4300, ea400000), \
5784 X(orrs, 4300, ea500000), \
5785 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
5786 X(push, b400, e92d0000), /* stmdb sp!,... */ \
5787 X(rev, ba00, fa90f080), \
5788 X(rev16, ba40, fa90f090), \
5789 X(revsh, bac0, fa90f0b0), \
5790 X(ror, 41c0, fa60f000), \
5791 X(rors, 41c0, fa70f000), \
5792 X(sbc, 4180, eb600000), \
5793 X(sbcs, 4180, eb700000), \
5794 X(stmia, c000, e8800000), \
5795 X(str, 6000, f8400000), \
5796 X(strb, 7000, f8000000), \
5797 X(strh, 8000, f8200000), \
5798 X(sub, 1e00, eba00000), \
5799 X(subs, 1e00, ebb00000), \
5800 X(sxtb, b240, fa4ff080), \
5801 X(sxth, b200, fa0ff080), \
5802 X(tst, 4200, ea100f00), \
5803 X(uxtb, b2c0, fa5ff080), \
5804 X(uxth, b280, fa1ff080), \
5805 X(nop, bf00, f3af8000), \
5806 X(yield, bf10, f3af8001), \
5807 X(wfe, bf20, f3af8002), \
5808 X(wfi, bf30, f3af8003), \
5809 X(sev, bf40, f3af9004), /* typo, 8004? */
5811 /* To catch errors in encoding functions, the codes are all offset by
5812 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
5813 as 16-bit instructions. */
5814 #define X(a,b,c) T_MNEM_##a
5815 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
5818 #define X(a,b,c) 0x##b
5819 static const unsigned short thumb_op16[] = { T16_32_TAB };
5820 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
5823 #define X(a,b,c) 0x##c
5824 static const unsigned int thumb_op32[] = { T16_32_TAB };
5825 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
5826 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
5830 /* Thumb instruction encoders, in alphabetical order. */
5834 do_t_add_sub_w (void)
5838 Rd = inst.operands[0].reg;
5839 Rn = inst.operands[1].reg;
5841 constraint (Rd == 15, _("PC not allowed as destination"));
5842 inst.instruction |= (Rn << 16) | (Rd << 8);
5843 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
5846 /* Parse an add or subtract instruction. We get here with inst.instruction
5847 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
5854 Rd = inst.operands[0].reg;
5855 Rs = (inst.operands[1].present
5856 ? inst.operands[1].reg /* Rd, Rs, foo */
5857 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
5861 if (!inst.operands[2].isreg)
5863 /* For an immediate, we always generate a 32-bit opcode;
5864 section relaxation will shrink it later if possible. */
5865 inst.instruction = THUMB_OP32 (inst.instruction);
5866 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
5867 inst.instruction |= inst.operands[0].reg << 8;
5868 inst.instruction |= inst.operands[1].reg << 16;
5869 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
5873 Rn = inst.operands[2].reg;
5874 /* See if we can do this with a 16-bit instruction. */
5875 if (!inst.operands[2].shifted && inst.size_req != 4)
5877 if (Rd <= 7 && Rn <= 7 && Rn <= 7
5878 && (inst.instruction == T_MNEM_adds
5879 || inst.instruction == T_MNEM_subs))
5881 inst.instruction = (inst.instruction == T_MNEM_adds
5884 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5888 if (inst.instruction == T_MNEM_add)
5892 inst.instruction = T_OPCODE_ADD_HI;
5893 inst.instruction |= (Rd & 8) << 4;
5894 inst.instruction |= (Rd & 7);
5895 inst.instruction |= Rn << 3;
5898 /* ... because addition is commutative! */
5901 inst.instruction = T_OPCODE_ADD_HI;
5902 inst.instruction |= (Rd & 8) << 4;
5903 inst.instruction |= (Rd & 7);
5904 inst.instruction |= Rs << 3;
5909 /* If we get here, it can't be done in 16 bits. */
5910 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
5911 _("shift must be constant"));
5912 inst.instruction = THUMB_OP32 (inst.instruction);
5913 inst.instruction |= Rd << 8;
5914 inst.instruction |= Rs << 16;
5915 encode_thumb32_shifted_operand (2);
5920 constraint (inst.instruction == T_MNEM_adds
5921 || inst.instruction == T_MNEM_subs,
5924 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
5926 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
5927 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
5930 inst.instruction = (inst.instruction == T_MNEM_add
5932 inst.instruction |= (Rd << 4) | Rs;
5933 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5937 Rn = inst.operands[2].reg;
5938 constraint (inst.operands[2].shifted, _("unshifted register required"));
5940 /* We now have Rd, Rs, and Rn set to registers. */
5941 if (Rd > 7 || Rs > 7 || Rn > 7)
5943 /* Can't do this for SUB. */
5944 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
5945 inst.instruction = T_OPCODE_ADD_HI;
5946 inst.instruction |= (Rd & 8) << 4;
5947 inst.instruction |= (Rd & 7);
5949 inst.instruction |= Rn << 3;
5951 inst.instruction |= Rs << 3;
5953 constraint (1, _("dest must overlap one source register"));
5957 inst.instruction = (inst.instruction == T_MNEM_add
5958 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
5959 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
5967 if (unified_syntax && inst.size_req != 2)
5969 /* Always generate a 32-bit opcode;
5970 section relaxation will shrink it later if possible. */
5971 inst.instruction = THUMB_OP32 (inst.instruction);
5972 inst.instruction |= inst.operands[0].reg << 8;
5973 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
5974 inst.reloc.pc_rel = 1;
5978 inst.instruction = THUMB_OP16 (inst.instruction);
5979 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5980 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5981 inst.reloc.pc_rel = 1;
5983 inst.instruction |= inst.operands[0].reg << 4;
5987 /* Arithmetic instructions for which there is just one 16-bit
5988 instruction encoding, and it allows only two low registers.
5989 For maximal compatibility with ARM syntax, we allow three register
5990 operands even when Thumb-32 instructions are not available, as long
5991 as the first two are identical. For instance, both "sbc r0,r1" and
5992 "sbc r0,r0,r1" are allowed. */
5998 Rd = inst.operands[0].reg;
5999 Rs = (inst.operands[1].present
6000 ? inst.operands[1].reg /* Rd, Rs, foo */
6001 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6002 Rn = inst.operands[2].reg;
6006 if (!inst.operands[2].isreg)
6008 /* For an immediate, we always generate a 32-bit opcode;
6009 section relaxation will shrink it later if possible. */
6010 inst.instruction = THUMB_OP32 (inst.instruction);
6011 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6012 inst.instruction |= Rd << 8;
6013 inst.instruction |= Rs << 16;
6014 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6018 /* See if we can do this with a 16-bit instruction. */
6019 if (THUMB_SETS_FLAGS (inst.instruction)
6020 && !inst.operands[2].shifted
6021 && inst.size_req != 4
6024 inst.instruction = THUMB_OP16 (inst.instruction);
6025 inst.instruction |= Rd;
6026 inst.instruction |= Rn << 3;
6030 /* If we get here, it can't be done in 16 bits. */
6031 constraint (inst.operands[2].shifted
6032 && inst.operands[2].immisreg,
6033 _("shift must be constant"));
6034 inst.instruction = THUMB_OP32 (inst.instruction);
6035 inst.instruction |= Rd << 8;
6036 inst.instruction |= Rs << 16;
6037 encode_thumb32_shifted_operand (2);
6042 /* On its face this is a lie - the instruction does set the
6043 flags. However, the only supported mnemonic in this mode
6045 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6047 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6048 _("unshifted register required"));
6049 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6050 constraint (Rd != Rs,
6051 _("dest and source1 must be the same register"));
6053 inst.instruction = THUMB_OP16 (inst.instruction);
6054 inst.instruction |= Rd;
6055 inst.instruction |= Rn << 3;
6059 /* Similarly, but for instructions where the arithmetic operation is
6060 commutative, so we can allow either of them to be different from
6061 the destination operand in a 16-bit instruction. For instance, all
6062 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
6069 Rd = inst.operands[0].reg;
6070 Rs = (inst.operands[1].present
6071 ? inst.operands[1].reg /* Rd, Rs, foo */
6072 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
6073 Rn = inst.operands[2].reg;
6077 if (!inst.operands[2].isreg)
6079 /* For an immediate, we always generate a 32-bit opcode;
6080 section relaxation will shrink it later if possible. */
6081 inst.instruction = THUMB_OP32 (inst.instruction);
6082 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6083 inst.instruction |= Rd << 8;
6084 inst.instruction |= Rs << 16;
6085 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6089 /* See if we can do this with a 16-bit instruction. */
6090 if (THUMB_SETS_FLAGS (inst.instruction)
6091 && !inst.operands[2].shifted
6092 && inst.size_req != 4)
6096 inst.instruction = THUMB_OP16 (inst.instruction);
6097 inst.instruction |= Rd;
6098 inst.instruction |= Rn << 3;
6103 inst.instruction = THUMB_OP16 (inst.instruction);
6104 inst.instruction |= Rd;
6105 inst.instruction |= Rs << 3;
6110 /* If we get here, it can't be done in 16 bits. */
6111 constraint (inst.operands[2].shifted
6112 && inst.operands[2].immisreg,
6113 _("shift must be constant"));
6114 inst.instruction = THUMB_OP32 (inst.instruction);
6115 inst.instruction |= Rd << 8;
6116 inst.instruction |= Rs << 16;
6117 encode_thumb32_shifted_operand (2);
6122 /* On its face this is a lie - the instruction does set the
6123 flags. However, the only supported mnemonic in this mode
6125 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6127 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
6128 _("unshifted register required"));
6129 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
6131 inst.instruction = THUMB_OP16 (inst.instruction);
6132 inst.instruction |= Rd;
6135 inst.instruction |= Rn << 3;
6137 inst.instruction |= Rs << 3;
6139 constraint (1, _("dest must overlap one source register"));
6146 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
6147 constraint (msb > 32, _("bit-field extends past end of register"));
6148 /* The instruction encoding stores the LSB and MSB,
6149 not the LSB and width. */
6150 inst.instruction |= inst.operands[0].reg << 8;
6151 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
6152 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
6153 inst.instruction |= msb - 1;
6161 /* #0 in second position is alternative syntax for bfc, which is
6162 the same instruction but with REG_PC in the Rm field. */
6163 if (!inst.operands[1].isreg)
6164 inst.operands[1].reg = REG_PC;
6166 msb = inst.operands[2].imm + inst.operands[3].imm;
6167 constraint (msb > 32, _("bit-field extends past end of register"));
6168 /* The instruction encoding stores the LSB and MSB,
6169 not the LSB and width. */
6170 inst.instruction |= inst.operands[0].reg << 8;
6171 inst.instruction |= inst.operands[1].reg << 16;
6172 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6173 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6174 inst.instruction |= msb - 1;
6180 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
6181 _("bit-field extends past end of register"));
6182 inst.instruction |= inst.operands[0].reg << 8;
6183 inst.instruction |= inst.operands[1].reg << 16;
6184 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
6185 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
6186 inst.instruction |= inst.operands[3].imm - 1;
6189 /* ARM V5 Thumb BLX (argument parse)
6190 BLX <target_addr> which is BLX(1)
6191 BLX <Rm> which is BLX(2)
6192 Unfortunately, there are two different opcodes for this mnemonic.
6193 So, the insns[].value is not used, and the code here zaps values
6194 into inst.instruction.
6196 ??? How to take advantage of the additional two bits of displacement
6197 available in Thumb32 mode? Need new relocation? */
6202 if (inst.operands[0].isreg)
6203 /* We have a register, so this is BLX(2). */
6204 inst.instruction |= inst.operands[0].reg << 3;
6207 /* No register. This must be BLX(1). */
6208 inst.instruction = 0xf000e800;
6209 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BLX;
6210 inst.reloc.pc_rel = 1;
6217 if (unified_syntax && inst.size_req != 2)
6219 if (inst.cond == COND_ALWAYS)
6221 inst.instruction = 0xf000b000;
6222 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
6226 assert (inst.cond != 0xF);
6227 inst.instruction = (inst.cond << 22) | 0xf0008000;
6228 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
6233 if (inst.cond == COND_ALWAYS)
6234 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
6237 inst.instruction = 0xd000 | (inst.cond << 8);
6238 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
6242 inst.reloc.pc_rel = 1;
6248 if (inst.operands[0].present)
6250 constraint (inst.operands[0].imm > 255,
6251 _("immediate value out of range"));
6252 inst.instruction |= inst.operands[0].imm;
6257 do_t_branch23 (void)
6259 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
6260 inst.reloc.pc_rel = 1;
6262 /* If the destination of the branch is a defined symbol which does not have
6263 the THUMB_FUNC attribute, then we must be calling a function which has
6264 the (interfacearm) attribute. We look for the Thumb entry point to that
6265 function and change the branch to refer to that function instead. */
6266 if ( inst.reloc.exp.X_op == O_symbol
6267 && inst.reloc.exp.X_add_symbol != NULL
6268 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
6269 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
6270 inst.reloc.exp.X_add_symbol =
6271 find_real_start (inst.reloc.exp.X_add_symbol);
6277 inst.instruction |= inst.operands[0].reg << 3;
6278 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
6279 should cause the alignment to be checked once it is known. This is
6280 because BX PC only works if the instruction is word aligned. */
6286 if (inst.operands[0].reg == REG_PC)
6287 as_tsktsk (_("use of r15 in bxj is not really useful"));
6289 inst.instruction |= inst.operands[0].reg << 16;
6295 inst.instruction |= inst.operands[0].reg << 8;
6296 inst.instruction |= inst.operands[1].reg << 16;
6297 inst.instruction |= inst.operands[1].reg;
6304 && (inst.operands[1].present || inst.size_req == 4))
6306 unsigned int imod = (inst.instruction & 0x0030) >> 4;
6307 inst.instruction = 0xf3af8000;
6308 inst.instruction |= imod << 9;
6309 inst.instruction |= inst.operands[0].imm << 5;
6310 if (inst.operands[1].present)
6311 inst.instruction |= 0x100 | inst.operands[1].imm;
6315 constraint (inst.operands[1].present,
6316 _("Thumb does not support the 2-argument "
6317 "form of this instruction"));
6318 inst.instruction |= inst.operands[0].imm;
6322 /* THUMB CPY instruction (argument parse). */
6327 if (inst.size_req == 4)
6329 inst.instruction = THUMB_OP32 (T_MNEM_mov);
6330 inst.instruction |= inst.operands[0].reg << 8;
6331 inst.instruction |= inst.operands[1].reg;
6335 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6336 inst.instruction |= (inst.operands[0].reg & 0x7);
6337 inst.instruction |= inst.operands[1].reg << 3;
6344 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6345 inst.instruction |= inst.operands[0].reg;
6346 inst.reloc.pc_rel = 1;
6347 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
6353 if (unified_syntax && inst.size_req == 4)
6354 inst.instruction = THUMB_OP32 (inst.instruction);
6356 inst.instruction = THUMB_OP16 (inst.instruction);
6362 unsigned int cond = inst.operands[0].imm;
6363 if ((cond & 0x1) == 0x0)
6365 unsigned int mask = inst.instruction & 0x000f;
6366 inst.instruction &= 0xfff0;
6368 if ((mask & 0x7) == 0)
6369 /* no conversion needed */;
6370 else if ((mask & 0x3) == 0)
6371 mask = (~(mask & 0x8) & 0x8) | 0x4;
6372 else if ((mask & 1) == 0)
6373 mask = (~(mask & 0xC) & 0xC) | 0x2;
6375 mask = (~(mask & 0xE) & 0xE) | 0x1;
6377 inst.instruction |= (mask & 0xF);
6380 inst.instruction |= cond << 4;
6386 /* This really doesn't seem worth it. */
6387 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6388 _("expression too complex"));
6389 constraint (inst.operands[1].writeback,
6390 _("Thumb load/store multiple does not support {reglist}^"));
6394 /* See if we can use a 16-bit instruction. */
6395 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
6396 && inst.size_req != 4
6397 && inst.operands[0].reg <= 7
6398 && !(inst.operands[1].imm & ~0xff)
6399 && (inst.instruction == T_MNEM_stmia
6400 ? inst.operands[0].writeback
6401 : (inst.operands[0].writeback
6402 == !(inst.operands[1].imm & (1 << inst.operands[0].reg)))))
6404 if (inst.instruction == T_MNEM_stmia
6405 && (inst.operands[1].imm & (1 << inst.operands[0].reg))
6406 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6407 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6408 inst.operands[0].reg);
6410 inst.instruction = THUMB_OP16 (inst.instruction);
6411 inst.instruction |= inst.operands[0].reg << 8;
6412 inst.instruction |= inst.operands[1].imm;
6416 if (inst.operands[1].imm & (1 << 13))
6417 as_warn (_("SP should not be in register list"));
6418 if (inst.instruction == T_MNEM_stmia)
6420 if (inst.operands[1].imm & (1 << 15))
6421 as_warn (_("PC should not be in register list"));
6422 if (inst.operands[1].imm & (1 << inst.operands[0].reg))
6423 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6424 inst.operands[0].reg);
6428 if (inst.operands[1].imm & (1 << 14)
6429 && inst.operands[1].imm & (1 << 15))
6430 as_warn (_("LR and PC should not both be in register list"));
6431 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6432 && inst.operands[0].writeback)
6433 as_warn (_("base register should not be in register list "
6434 "when written back"));
6436 if (inst.instruction < 0xffff)
6437 inst.instruction = THUMB_OP32 (inst.instruction);
6438 inst.instruction |= inst.operands[0].reg << 16;
6439 inst.instruction |= inst.operands[1].imm;
6440 if (inst.operands[0].writeback)
6441 inst.instruction |= WRITE_BACK;
6446 constraint (inst.operands[0].reg > 7
6447 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
6448 if (inst.instruction == T_MNEM_stmia)
6450 if (!inst.operands[0].writeback)
6451 as_warn (_("this instruction will write back the base register"));
6452 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
6453 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
6454 as_warn (_("value stored for r%d is UNPREDICTABLE"),
6455 inst.operands[0].reg);
6459 if (!inst.operands[0].writeback
6460 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
6461 as_warn (_("this instruction will write back the base register"));
6462 else if (inst.operands[0].writeback
6463 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
6464 as_warn (_("this instruction will not write back the base register"));
6467 inst.instruction = THUMB_OP16 (inst.instruction);
6468 inst.instruction |= inst.operands[0].reg << 8;
6469 inst.instruction |= inst.operands[1].imm;
6476 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
6477 || inst.operands[1].postind || inst.operands[1].writeback
6478 || inst.operands[1].immisreg || inst.operands[1].shifted
6479 || inst.operands[1].negative,
6480 _("instruction does not accept this addressing mode"));
6482 inst.instruction |= inst.operands[0].reg << 12;
6483 inst.instruction |= inst.operands[1].reg << 16;
6484 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
6490 if (!inst.operands[1].present)
6492 constraint (inst.operands[0].reg == REG_LR,
6493 _("r14 not allowed as first register "
6494 "when second register is omitted"));
6495 inst.operands[1].reg = inst.operands[0].reg + 1;
6497 constraint (inst.operands[0].reg == inst.operands[1].reg,
6500 inst.instruction |= inst.operands[0].reg << 12;
6501 inst.instruction |= inst.operands[1].reg << 8;
6502 inst.instruction |= inst.operands[2].reg << 16;
6510 /* Generation of 16-bit instructions for anything other than
6511 Rd, [Rn, Ri] is deferred to section relaxation time. */
6512 if (inst.operands[1].isreg && inst.operands[1].immisreg
6513 && !inst.operands[1].shifted && !inst.operands[1].postind
6514 && !inst.operands[1].negative && inst.operands[0].reg <= 7
6515 && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7
6516 && inst.instruction <= 0xffff)
6518 inst.instruction = THUMB_OP16 (inst.instruction);
6522 inst.instruction = THUMB_OP32 (inst.instruction);
6523 inst.instruction |= inst.operands[0].reg << 12;
6524 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
6528 constraint (inst.operands[0].reg > 7, BAD_HIREG);
6530 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
6532 /* Only [Rn,Rm] is acceptable. */
6533 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
6534 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
6535 || inst.operands[1].postind || inst.operands[1].shifted
6536 || inst.operands[1].negative,
6537 _("Thumb does not support this addressing mode"));
6538 inst.instruction = THUMB_OP16 (inst.instruction);
6542 inst.instruction = THUMB_OP16 (inst.instruction);
6543 if (!inst.operands[1].isreg)
6544 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
6547 constraint (!inst.operands[1].preind
6548 || inst.operands[1].shifted
6549 || inst.operands[1].writeback,
6550 _("Thumb does not support this addressing mode"));
6551 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
6553 constraint (inst.instruction & 0x0600,
6554 _("byte or halfword not valid for base register"));
6555 constraint (inst.operands[1].reg == REG_PC
6556 && !(inst.instruction & THUMB_LOAD_BIT),
6557 _("r15 based store not allowed"));
6558 constraint (inst.operands[1].immisreg,
6559 _("invalid base register for register offset"));
6561 if (inst.operands[1].reg == REG_PC)
6562 inst.instruction = T_OPCODE_LDR_PC;
6563 else if (inst.instruction & THUMB_LOAD_BIT)
6564 inst.instruction = T_OPCODE_LDR_SP;
6566 inst.instruction = T_OPCODE_STR_SP;
6568 inst.instruction |= inst.operands[0].reg << 8;
6569 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6573 constraint (inst.operands[1].reg > 7, BAD_HIREG);
6574 if (!inst.operands[1].immisreg)
6576 /* Immediate offset. */
6577 inst.instruction |= inst.operands[0].reg;
6578 inst.instruction |= inst.operands[1].reg << 3;
6579 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
6583 /* Register offset. */
6584 constraint (inst.operands[1].imm > 7, BAD_HIREG);
6585 constraint (inst.operands[1].negative,
6586 _("Thumb does not support this addressing mode"));
6589 switch (inst.instruction)
6591 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
6592 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
6593 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
6594 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
6595 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
6596 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
6597 case 0x5600 /* ldrsb */:
6598 case 0x5e00 /* ldrsh */: break;
6602 inst.instruction |= inst.operands[0].reg;
6603 inst.instruction |= inst.operands[1].reg << 3;
6604 inst.instruction |= inst.operands[1].imm << 6;
6610 if (!inst.operands[1].present)
6612 inst.operands[1].reg = inst.operands[0].reg + 1;
6613 constraint (inst.operands[0].reg == REG_LR,
6614 _("r14 not allowed here"));
6616 inst.instruction |= inst.operands[0].reg << 12;
6617 inst.instruction |= inst.operands[1].reg << 8;
6618 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
6625 inst.instruction |= inst.operands[0].reg << 12;
6626 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
6632 inst.instruction |= inst.operands[0].reg << 8;
6633 inst.instruction |= inst.operands[1].reg << 16;
6634 inst.instruction |= inst.operands[2].reg;
6635 inst.instruction |= inst.operands[3].reg << 12;
6641 inst.instruction |= inst.operands[0].reg << 12;
6642 inst.instruction |= inst.operands[1].reg << 8;
6643 inst.instruction |= inst.operands[2].reg << 16;
6644 inst.instruction |= inst.operands[3].reg;
6652 int r0off = (inst.instruction == T_MNEM_mov
6653 || inst.instruction == T_MNEM_movs) ? 8 : 16;
6654 if (!inst.operands[1].isreg)
6656 /* For an immediate, we always generate a 32-bit opcode;
6657 section relaxation will shrink it later if possible. */
6658 inst.instruction = THUMB_OP32 (inst.instruction);
6659 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6660 inst.instruction |= inst.operands[0].reg << r0off;
6661 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6663 else if (inst.size_req == 4
6664 || inst.operands[1].shifted
6665 || (inst.instruction == T_MNEM_movs
6666 && (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)))
6668 inst.instruction = THUMB_OP32 (inst.instruction);
6669 inst.instruction |= inst.operands[0].reg << r0off;
6670 encode_thumb32_shifted_operand (1);
6673 switch (inst.instruction)
6676 inst.instruction = T_OPCODE_MOV_HR;
6677 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6678 inst.instruction |= (inst.operands[0].reg & 0x7);
6679 inst.instruction |= inst.operands[1].reg << 3;
6683 /* We know we have low registers at this point.
6684 Generate ADD Rd, Rs, #0. */
6685 inst.instruction = T_OPCODE_ADD_I3;
6686 inst.instruction |= inst.operands[0].reg;
6687 inst.instruction |= inst.operands[1].reg << 3;
6691 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7)
6693 inst.instruction = T_OPCODE_CMP_LR;
6694 inst.instruction |= inst.operands[0].reg;
6695 inst.instruction |= inst.operands[1].reg << 3;
6699 inst.instruction = T_OPCODE_CMP_HR;
6700 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
6701 inst.instruction |= (inst.operands[0].reg & 0x7);
6702 inst.instruction |= inst.operands[1].reg << 3;
6709 inst.instruction = THUMB_OP16 (inst.instruction);
6710 if (inst.operands[1].isreg)
6712 if (inst.operands[0].reg < 8 && inst.operands[1].reg < 8)
6714 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
6715 since a MOV instruction produces unpredictable results. */
6716 if (inst.instruction == T_OPCODE_MOV_I8)
6717 inst.instruction = T_OPCODE_ADD_I3;
6719 inst.instruction = T_OPCODE_CMP_LR;
6721 inst.instruction |= inst.operands[0].reg;
6722 inst.instruction |= inst.operands[1].reg << 3;
6726 if (inst.instruction == T_OPCODE_MOV_I8)
6727 inst.instruction = T_OPCODE_MOV_HR;
6729 inst.instruction = T_OPCODE_CMP_HR;
6735 constraint (inst.operands[0].reg > 7,
6736 _("only lo regs allowed with immediate"));
6737 inst.instruction |= inst.operands[0].reg << 8;
6738 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
6745 inst.instruction |= inst.operands[0].reg << 8;
6746 inst.instruction |= (inst.operands[1].imm & 0xf000) << 4;
6747 inst.instruction |= (inst.operands[1].imm & 0x0800) << 15;
6748 inst.instruction |= (inst.operands[1].imm & 0x0700) << 4;
6749 inst.instruction |= (inst.operands[1].imm & 0x00ff);
6757 int r0off = (inst.instruction == T_MNEM_mvn
6758 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
6759 if (!inst.operands[1].isreg)
6761 /* For an immediate, we always generate a 32-bit opcode;
6762 section relaxation will shrink it later if possible. */
6763 if (inst.instruction < 0xffff)
6764 inst.instruction = THUMB_OP32 (inst.instruction);
6765 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
6766 inst.instruction |= inst.operands[0].reg << r0off;
6767 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
6771 /* See if we can do this with a 16-bit instruction. */
6772 if (inst.instruction < 0xffff
6773 && THUMB_SETS_FLAGS (inst.instruction)
6774 && !inst.operands[1].shifted
6775 && inst.operands[0].reg <= 7
6776 && inst.operands[1].reg <= 7
6777 && inst.size_req != 4)
6779 inst.instruction = THUMB_OP16 (inst.instruction);
6780 inst.instruction |= inst.operands[0].reg;
6781 inst.instruction |= inst.operands[1].reg << 3;
6785 constraint (inst.operands[1].shifted
6786 && inst.operands[1].immisreg,
6787 _("shift must be constant"));
6788 if (inst.instruction < 0xffff)
6789 inst.instruction = THUMB_OP32 (inst.instruction);
6790 inst.instruction |= inst.operands[0].reg << r0off;
6791 encode_thumb32_shifted_operand (1);
6797 constraint (inst.instruction > 0xffff
6798 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
6799 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
6800 _("unshifted register required"));
6801 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6804 inst.instruction = THUMB_OP16 (inst.instruction);
6805 inst.instruction |= inst.operands[0].reg;
6806 inst.instruction |= inst.operands[1].reg << 3;
6813 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
6814 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
6816 _("'CPSR' or 'SPSR' expected"));
6817 inst.instruction |= inst.operands[0].reg << 8;
6818 inst.instruction |= (inst.operands[1].imm & SPSR_BIT) >> 2;
6824 constraint (!inst.operands[1].isreg,
6825 _("Thumb encoding does not support an immediate here"));
6826 inst.instruction |= (inst.operands[0].imm & SPSR_BIT) >> 2;
6827 inst.instruction |= (inst.operands[0].imm & ~SPSR_BIT) >> 8;
6828 inst.instruction |= inst.operands[1].reg << 16;
6834 if (!inst.operands[2].present)
6835 inst.operands[2].reg = inst.operands[0].reg;
6837 /* There is no 32-bit MULS and no 16-bit MUL. */
6838 if (unified_syntax && inst.instruction == T_MNEM_mul)
6840 inst.instruction = THUMB_OP32 (inst.instruction);
6841 inst.instruction |= inst.operands[0].reg << 8;
6842 inst.instruction |= inst.operands[1].reg << 16;
6843 inst.instruction |= inst.operands[2].reg << 0;
6847 constraint (!unified_syntax
6848 && inst.instruction == T_MNEM_muls, BAD_THUMB32);
6849 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6852 inst.instruction = THUMB_OP16 (inst.instruction);
6853 inst.instruction |= inst.operands[0].reg;
6855 if (inst.operands[0].reg == inst.operands[1].reg)
6856 inst.instruction |= inst.operands[2].reg << 3;
6857 else if (inst.operands[0].reg == inst.operands[2].reg)
6858 inst.instruction |= inst.operands[1].reg << 3;
6860 constraint (1, _("dest must overlap one source register"));
6867 inst.instruction |= inst.operands[0].reg << 12;
6868 inst.instruction |= inst.operands[1].reg << 8;
6869 inst.instruction |= inst.operands[2].reg << 16;
6870 inst.instruction |= inst.operands[3].reg;
6872 if (inst.operands[0].reg == inst.operands[1].reg)
6873 as_tsktsk (_("rdhi and rdlo must be different"));
6881 if (inst.size_req == 4 || inst.operands[0].imm > 15)
6883 inst.instruction = THUMB_OP32 (inst.instruction);
6884 inst.instruction |= inst.operands[0].imm;
6888 inst.instruction = THUMB_OP16 (inst.instruction);
6889 inst.instruction |= inst.operands[0].imm << 4;
6894 constraint (inst.operands[0].present,
6895 _("Thumb does not support NOP with hints"));
6896 inst.instruction = 0x46c0;
6905 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7
6906 || !THUMB_SETS_FLAGS (inst.instruction)
6907 || inst.size_req == 4)
6909 inst.instruction = THUMB_OP32 (inst.instruction);
6910 inst.instruction |= inst.operands[0].reg << 8;
6911 inst.instruction |= inst.operands[1].reg << 16;
6915 inst.instruction = THUMB_OP16 (inst.instruction);
6916 inst.instruction |= inst.operands[0].reg;
6917 inst.instruction |= inst.operands[1].reg << 3;
6922 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
6924 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
6926 inst.instruction = THUMB_OP16 (inst.instruction);
6927 inst.instruction |= inst.operands[0].reg;
6928 inst.instruction |= inst.operands[1].reg << 3;
6935 inst.instruction |= inst.operands[0].reg << 8;
6936 inst.instruction |= inst.operands[1].reg << 16;
6937 inst.instruction |= inst.operands[2].reg;
6938 if (inst.operands[3].present)
6940 unsigned int val = inst.reloc.exp.X_add_number;
6941 constraint (inst.reloc.exp.X_op != O_constant,
6942 _("expression too complex"));
6943 inst.instruction |= (val & 0x1c) << 10;
6944 inst.instruction |= (val & 0x03) << 6;
6951 if (!inst.operands[3].present)
6952 inst.instruction &= ~0x00000020;
6959 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
6963 do_t_push_pop (void)
6967 constraint (inst.operands[0].writeback,
6968 _("push/pop do not support {reglist}^"));
6969 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
6970 _("expression too complex"));
6972 mask = inst.operands[0].imm;
6973 if ((mask & ~0xff) == 0)
6974 inst.instruction = THUMB_OP16 (inst.instruction);
6975 else if ((inst.instruction == T_MNEM_push
6976 && (mask & ~0xff) == 1 << REG_LR)
6977 || (inst.instruction == T_MNEM_pop
6978 && (mask & ~0xff) == 1 << REG_PC))
6980 inst.instruction = THUMB_OP16 (inst.instruction);
6981 inst.instruction |= THUMB_PP_PC_LR;
6984 else if (unified_syntax)
6986 if (mask & (1 << 13))
6987 inst.error = _("SP not allowed in register list");
6988 if (inst.instruction == T_MNEM_push)
6990 if (mask & (1 << 15))
6991 inst.error = _("PC not allowed in register list");
6995 if (mask & (1 << 14)
6996 && mask & (1 << 15))
6997 inst.error = _("LR and PC should not both be in register list");
6999 if ((mask & (mask - 1)) == 0)
7001 /* Single register push/pop implemented as str/ldr. */
7002 if (inst.instruction == T_MNEM_push)
7003 inst.instruction = 0xf84d0d04; /* str reg, [sp, #-4]! */
7005 inst.instruction = 0xf85d0b04; /* ldr reg, [sp], #4 */
7006 mask = ffs(mask) - 1;
7010 inst.instruction = THUMB_OP32 (inst.instruction);
7014 inst.error = _("invalid register list to push/pop instruction");
7018 inst.instruction |= mask;
7024 inst.instruction |= inst.operands[0].reg << 8;
7025 inst.instruction |= inst.operands[1].reg << 16;
7031 if (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7032 && inst.size_req != 4)
7034 inst.instruction = THUMB_OP16 (inst.instruction);
7035 inst.instruction |= inst.operands[0].reg;
7036 inst.instruction |= inst.operands[1].reg << 3;
7038 else if (unified_syntax)
7040 inst.instruction = THUMB_OP32 (inst.instruction);
7041 inst.instruction |= inst.operands[0].reg << 8;
7042 inst.instruction |= inst.operands[1].reg << 16;
7043 inst.instruction |= inst.operands[1].reg;
7046 inst.error = BAD_HIREG;
7054 Rd = inst.operands[0].reg;
7055 Rs = (inst.operands[1].present
7056 ? inst.operands[1].reg /* Rd, Rs, foo */
7057 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
7059 inst.instruction |= Rd << 8;
7060 inst.instruction |= Rs << 16;
7061 if (!inst.operands[2].isreg)
7063 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
7064 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
7067 encode_thumb32_shifted_operand (2);
7073 if (inst.operands[0].imm)
7074 inst.instruction |= 0x8;
7080 if (!inst.operands[1].present)
7081 inst.operands[1].reg = inst.operands[0].reg;
7085 if (inst.operands[0].reg > 7
7086 || inst.operands[1].reg > 7
7087 || !THUMB_SETS_FLAGS (inst.instruction)
7088 || (!inst.operands[2].isreg && inst.instruction == T_MNEM_rors)
7089 || (inst.operands[2].isreg && inst.operands[1].reg != inst.operands[0].reg)
7090 || inst.size_req == 4)
7092 if (inst.operands[2].isreg)
7094 inst.instruction = THUMB_OP32 (inst.instruction);
7095 inst.instruction |= inst.operands[0].reg << 8;
7096 inst.instruction |= inst.operands[1].reg << 16;
7097 inst.instruction |= inst.operands[2].reg;
7101 inst.operands[1].shifted = 1;
7102 switch (inst.instruction)
7105 case T_MNEM_asrs: inst.operands[1].shift_kind = SHIFT_ASR; break;
7107 case T_MNEM_lsls: inst.operands[1].shift_kind = SHIFT_LSL; break;
7109 case T_MNEM_lsrs: inst.operands[1].shift_kind = SHIFT_LSR; break;
7111 case T_MNEM_rors: inst.operands[1].shift_kind = SHIFT_ROR; break;
7115 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
7116 ? T_MNEM_movs : T_MNEM_mov);
7117 inst.instruction |= inst.operands[0].reg << 8;
7118 encode_thumb32_shifted_operand (1);
7119 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
7120 inst.reloc.type = BFD_RELOC_UNUSED;
7125 if (inst.operands[2].isreg)
7127 switch (inst.instruction)
7129 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_R; break;
7130 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_R; break;
7131 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_R; break;
7132 case T_MNEM_rors: inst.instruction = T_OPCODE_ROR_R; break;
7136 inst.instruction |= inst.operands[0].reg;
7137 inst.instruction |= inst.operands[2].reg << 3;
7141 switch (inst.instruction)
7143 case T_MNEM_asrs: inst.instruction = T_OPCODE_ASR_I; break;
7144 case T_MNEM_lsls: inst.instruction = T_OPCODE_LSL_I; break;
7145 case T_MNEM_lsrs: inst.instruction = T_OPCODE_LSR_I; break;
7148 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7149 inst.instruction |= inst.operands[0].reg;
7150 inst.instruction |= inst.operands[1].reg << 3;
7156 constraint (inst.operands[0].reg > 7
7157 || inst.operands[1].reg > 7, BAD_HIREG);
7158 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
7160 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
7162 constraint (inst.operands[2].reg > 7, BAD_HIREG);
7163 constraint (inst.operands[0].reg != inst.operands[1].reg,
7164 _("source1 and dest must be same register"));
7166 switch (inst.instruction)
7168 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
7169 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
7170 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
7171 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
7175 inst.instruction |= inst.operands[0].reg;
7176 inst.instruction |= inst.operands[2].reg << 3;
7180 switch (inst.instruction)
7182 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
7183 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
7184 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
7185 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
7188 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
7189 inst.instruction |= inst.operands[0].reg;
7190 inst.instruction |= inst.operands[1].reg << 3;
7198 inst.instruction |= inst.operands[0].reg << 8;
7199 inst.instruction |= inst.operands[1].reg << 16;
7200 inst.instruction |= inst.operands[2].reg;
7206 unsigned int value = inst.reloc.exp.X_add_number;
7207 constraint (inst.reloc.exp.X_op != O_constant,
7208 _("expression too complex"));
7209 inst.reloc.type = BFD_RELOC_UNUSED;
7210 inst.instruction |= (value & 0xf000) >> 12;
7211 inst.instruction |= (value & 0x0ff0);
7212 inst.instruction |= (value & 0x000f) << 16;
7218 inst.instruction |= inst.operands[0].reg << 8;
7219 inst.instruction |= inst.operands[1].imm - 1;
7220 inst.instruction |= inst.operands[2].reg << 16;
7222 if (inst.operands[3].present)
7224 constraint (inst.reloc.exp.X_op != O_constant,
7225 _("expression too complex"));
7227 if (inst.reloc.exp.X_add_number != 0)
7229 if (inst.operands[3].shift_kind == SHIFT_ASR)
7230 inst.instruction |= 0x00200000; /* sh bit */
7231 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7232 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7234 inst.reloc.type = BFD_RELOC_UNUSED;
7241 inst.instruction |= inst.operands[0].reg << 8;
7242 inst.instruction |= inst.operands[1].imm - 1;
7243 inst.instruction |= inst.operands[2].reg << 16;
7249 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
7250 || inst.operands[2].postind || inst.operands[2].writeback
7251 || inst.operands[2].immisreg || inst.operands[2].shifted
7252 || inst.operands[2].negative,
7253 _("instruction does not accept this addressing mode"));
7255 inst.instruction |= inst.operands[0].reg << 8;
7256 inst.instruction |= inst.operands[1].reg << 12;
7257 inst.instruction |= inst.operands[2].reg << 16;
7258 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
7264 if (!inst.operands[2].present)
7265 inst.operands[2].reg = inst.operands[1].reg + 1;
7267 constraint (inst.operands[0].reg == inst.operands[1].reg
7268 || inst.operands[0].reg == inst.operands[2].reg
7269 || inst.operands[0].reg == inst.operands[3].reg
7270 || inst.operands[1].reg == inst.operands[2].reg,
7273 inst.instruction |= inst.operands[0].reg;
7274 inst.instruction |= inst.operands[1].reg << 12;
7275 inst.instruction |= inst.operands[2].reg << 8;
7276 inst.instruction |= inst.operands[3].reg << 16;
7282 inst.instruction |= inst.operands[0].reg << 8;
7283 inst.instruction |= inst.operands[1].reg << 16;
7284 inst.instruction |= inst.operands[2].reg;
7285 inst.instruction |= inst.operands[3].imm << 4;
7291 if (inst.instruction <= 0xffff && inst.size_req != 4
7292 && inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7
7293 && (!inst.operands[2].present || inst.operands[2].imm == 0))
7295 inst.instruction = THUMB_OP16 (inst.instruction);
7296 inst.instruction |= inst.operands[0].reg;
7297 inst.instruction |= inst.operands[1].reg << 3;
7299 else if (unified_syntax)
7301 if (inst.instruction <= 0xffff)
7302 inst.instruction = THUMB_OP32 (inst.instruction);
7303 inst.instruction |= inst.operands[0].reg << 8;
7304 inst.instruction |= inst.operands[1].reg;
7305 inst.instruction |= inst.operands[2].imm << 4;
7309 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
7310 _("Thumb encoding does not support rotation"));
7311 constraint (1, BAD_HIREG);
7318 inst.reloc.type = BFD_RELOC_ARM_SWI;
7326 half = (inst.instruction & 0x10) != 0;
7327 constraint (inst.operands[0].imm == 15,
7328 _("PC is not a valid index register"));
7329 constraint (!half && inst.operands[0].shifted,
7330 _("instruction does not allow shifted index"));
7331 constraint (half && !inst.operands[0].shifted,
7332 _("instruction requires shifted index"));
7333 inst.instruction |= (inst.operands[0].reg << 16) | inst.operands[0].imm;
7339 inst.instruction |= inst.operands[0].reg << 8;
7340 inst.instruction |= inst.operands[1].imm;
7341 inst.instruction |= inst.operands[2].reg << 16;
7343 if (inst.operands[3].present)
7345 constraint (inst.reloc.exp.X_op != O_constant,
7346 _("expression too complex"));
7347 if (inst.reloc.exp.X_add_number != 0)
7349 if (inst.operands[3].shift_kind == SHIFT_ASR)
7350 inst.instruction |= 0x00200000; /* sh bit */
7352 inst.instruction |= (inst.reloc.exp.X_add_number & 0x1c) << 10;
7353 inst.instruction |= (inst.reloc.exp.X_add_number & 0x03) << 6;
7355 inst.reloc.type = BFD_RELOC_UNUSED;
7362 inst.instruction |= inst.operands[0].reg << 8;
7363 inst.instruction |= inst.operands[1].imm;
7364 inst.instruction |= inst.operands[2].reg << 16;
7367 /* Overall per-instruction processing. */
7369 /* We need to be able to fix up arbitrary expressions in some statements.
7370 This is so that we can handle symbols that are an arbitrary distance from
7371 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7372 which returns part of an address in a form which will be valid for
7373 a data instruction. We do this by pushing the expression into a symbol
7374 in the expr_section, and creating a fix for that. */
7377 fix_new_arm (fragS * frag,
7392 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7396 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7401 /* Mark whether the fix is to a THUMB instruction, or an ARM
7403 new_fix->tc_fix_data = thumb_mode;
7407 output_inst (const char * str)
7413 as_bad ("%s -- `%s'", inst.error, str);
7419 to = frag_more (inst.size);
7421 if (thumb_mode && (inst.size > THUMB_SIZE))
7423 assert (inst.size == (2 * THUMB_SIZE));
7424 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
7425 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
7427 else if (inst.size > INSN_SIZE)
7429 assert (inst.size == (2 * INSN_SIZE));
7430 md_number_to_chars (to, inst.instruction, INSN_SIZE);
7431 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
7434 md_number_to_chars (to, inst.instruction, inst.size);
7436 if (inst.reloc.type != BFD_RELOC_UNUSED)
7437 fix_new_arm (frag_now, to - frag_now->fr_literal,
7438 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
7442 dwarf2_emit_insn (inst.size);
7446 /* Tag values used in struct asm_opcode's tag field. */
7449 OT_unconditional, /* Instruction cannot be conditionalized.
7450 The ARM condition field is still 0xE. */
7451 OT_unconditionalF, /* Instruction cannot be conditionalized
7452 and carries 0xF in its ARM condition field. */
7453 OT_csuffix, /* Instruction takes a conditional suffix. */
7454 OT_cinfix3, /* Instruction takes a conditional infix,
7455 beginning at character index 3. (In
7456 unified mode, it becomes a suffix.) */
7457 OT_csuf_or_in3, /* Instruction takes either a conditional
7458 suffix or an infix at character index 3.
7459 (In unified mode, a suffix only. */
7460 OT_odd_infix_unc, /* This is the unconditional variant of an
7461 instruction that takes a conditional infix
7462 at an unusual position. In unified mode,
7463 this variant will accept a suffix. */
7464 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
7465 are the conditional variants of instructions that
7466 take conditional infixes in unusual positions.
7467 The infix appears at character index
7468 (tag - OT_odd_infix_0). These are not accepted
7472 /* Subroutine of md_assemble, responsible for looking up the primary
7473 opcode from the mnemonic the user wrote. STR points to the
7474 beginning of the mnemonic.
7476 This is not simply a hash table lookup, because of conditional
7477 variants. Most instructions have conditional variants, which are
7478 expressed with a _conditional affix_ to the mnemonic. If we were
7479 to encode each conditional variant as a literal string in the opcode
7480 table, it would have approximately 20,000 entries.
7482 Most mnemonics take this affix as a suffix, and in unified syntax,
7483 'most' is upgraded to 'all'. However, in the divided syntax, some
7484 instructions take the affix as an infix, notably the s-variants of
7485 the arithmetic instructions. Of those instructions, all but six
7486 have the infix appear after the third character of the mnemonic.
7488 Accordingly, the algorithm for looking up primary opcodes given
7491 1. Look up the identifier in the opcode table.
7492 If we find a match, go to step U.
7494 2. Look up the last two characters of the identifier in the
7495 conditions table. If we find a match, look up the first N-2
7496 characters of the identifier in the opcode table. If we
7497 find a match, go to step CE.
7499 3. Look up the fourth and fifth characters of the identifier in
7500 the conditions table. If we find a match, extract those
7501 characters from the identifier, and look up the remaining
7502 characters in the opcode table. If we find a match, go
7507 U. Examine the tag field of the opcode structure, in case this is
7508 one of the six instructions with its conditional infix in an
7509 unusual place. If it is, the tag tells us where to find the
7510 infix; look it up in the conditions table and set inst.cond
7511 accordingly. Otherwise, this is an unconditional instruction.
7512 Again set inst.cond accordingly. Return the opcode structure.
7514 CE. Examine the tag field to make sure this is an instruction that
7515 should receive a conditional suffix. If it is not, fail.
7516 Otherwise, set inst.cond from the suffix we already looked up,
7517 and return the opcode structure.
7519 CM. Examine the tag field to make sure this is an instruction that
7520 should receive a conditional infix after the third character.
7521 If it is not, fail. Otherwise, undo the edits to the current
7522 line of input and proceed as for case CE. */
7524 static const struct asm_opcode *
7525 opcode_lookup (char **str)
7529 const struct asm_opcode *opcode;
7530 const struct asm_cond *cond;
7532 /* Scan up to the end of the mnemonic, which must end in white space,
7533 '.' (in unified mode only), or end of string. */
7534 for (base = end = *str; *end != '\0'; end++)
7535 if (*end == ' ' || (unified_syntax && *end == '.'))
7541 /* Handle a possible width suffix. */
7544 if (end[1] == 'w' && (end[2] == ' ' || end[2] == '\0'))
7546 else if (end[1] == 'n' && (end[2] == ' ' || end[2] == '\0'))
7556 /* Look for unaffixed or special-case affixed mnemonic. */
7557 opcode = hash_find_n (arm_ops_hsh, base, end - base);
7561 if (opcode->tag < OT_odd_infix_0)
7563 inst.cond = COND_ALWAYS;
7568 as_warn (_("conditional infixes are deprecated in unified syntax"));
7569 affix = base + (opcode->tag - OT_odd_infix_0);
7570 cond = hash_find_n (arm_cond_hsh, affix, 2);
7573 inst.cond = cond->value;
7577 /* Cannot have a conditional suffix on a mnemonic of less than two
7582 /* Look for suffixed mnemonic. */
7584 cond = hash_find_n (arm_cond_hsh, affix, 2);
7585 opcode = hash_find_n (arm_ops_hsh, base, affix - base);
7589 switch (opcode->tag)
7592 case OT_odd_infix_unc:
7593 if (!unified_syntax)
7595 /* else fall through */
7598 case OT_csuf_or_in3:
7599 inst.cond = cond->value;
7602 case OT_unconditional:
7603 case OT_unconditionalF:
7604 /* delayed diagnostic */
7605 inst.error = BAD_COND;
7606 inst.cond = COND_ALWAYS;
7614 /* Cannot have a usual-position infix on a mnemonic of less than
7615 six characters (five would be a suffix). */
7619 /* Look for infixed mnemonic in the usual position. */
7621 cond = hash_find_n (arm_cond_hsh, affix, 2);
7625 memcpy (save, affix, 2);
7626 memmove (affix, affix + 2, (end - affix) - 2);
7627 opcode = hash_find_n (arm_ops_hsh, base, (end - base) - 2);
7628 memmove (affix + 2, affix, (end - affix) - 2);
7629 memcpy (affix, save, 2);
7631 if (opcode && (opcode->tag == OT_cinfix3 || opcode->tag == OT_csuf_or_in3))
7635 as_warn (_("conditional infixes are deprecated in unified syntax"));
7637 inst.cond = cond->value;
7645 md_assemble (char *str)
7648 const struct asm_opcode * opcode;
7650 /* Align the previous label if needed. */
7651 if (last_label_seen != NULL)
7653 symbol_set_frag (last_label_seen, frag_now);
7654 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
7655 S_SET_SEGMENT (last_label_seen, now_seg);
7658 memset (&inst, '\0', sizeof (inst));
7659 inst.reloc.type = BFD_RELOC_UNUSED;
7661 opcode = opcode_lookup (&p);
7664 /* It wasn't an instruction, but it might be a register alias of
7665 the form alias .req reg. */
7666 if (!create_register_alias (str, p))
7667 as_bad (_("bad instruction `%s'"), str);
7674 /* Check that this instruction is supported for this CPU. */
7675 if (thumb_mode == 1 && (opcode->tvariant & cpu_variant) == 0)
7677 as_bad (_("selected processor does not support `%s'"), str);
7680 if (inst.cond != COND_ALWAYS && !unified_syntax
7681 && opcode->tencode != do_t_branch)
7683 as_bad (_("Thumb does not support conditional execution"));
7687 mapping_state (MAP_THUMB);
7688 inst.instruction = opcode->tvalue;
7690 if (!parse_operands (p, opcode->operands))
7695 assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
7696 inst.size = (inst.instruction > 0xffff ? 4 : 2);
7697 if (inst.size_req && inst.size_req != inst.size)
7699 as_bad (_("cannot honor width suffix -- `%s'"), str);
7706 /* Check that this instruction is supported for this CPU. */
7707 if ((opcode->avariant & cpu_variant) == 0)
7709 as_bad (_("selected processor does not support `%s'"), str);
7714 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
7718 mapping_state (MAP_ARM);
7719 inst.instruction = opcode->avalue;
7720 if (opcode->tag == OT_unconditionalF)
7721 inst.instruction |= 0xF << 28;
7723 inst.instruction |= inst.cond << 28;
7724 inst.size = INSN_SIZE;
7725 if (!parse_operands (p, opcode->operands))
7731 /* Various frobbings of labels and their addresses. */
7734 arm_start_line_hook (void)
7736 last_label_seen = NULL;
7740 arm_frob_label (symbolS * sym)
7742 last_label_seen = sym;
7744 ARM_SET_THUMB (sym, thumb_mode);
7746 #if defined OBJ_COFF || defined OBJ_ELF
7747 ARM_SET_INTERWORK (sym, support_interwork);
7750 /* Note - do not allow local symbols (.Lxxx) to be labeled
7751 as Thumb functions. This is because these labels, whilst
7752 they exist inside Thumb code, are not the entry points for
7753 possible ARM->Thumb calls. Also, these labels can be used
7754 as part of a computed goto or switch statement. eg gcc
7755 can generate code that looks like this:
7767 The first instruction loads the address of the jump table.
7768 The second instruction converts a table index into a byte offset.
7769 The third instruction gets the jump address out of the table.
7770 The fourth instruction performs the jump.
7772 If the address stored at .Laaa is that of a symbol which has the
7773 Thumb_Func bit set, then the linker will arrange for this address
7774 to have the bottom bit set, which in turn would mean that the
7775 address computation performed by the third instruction would end
7776 up with the bottom bit set. Since the ARM is capable of unaligned
7777 word loads, the instruction would then load the incorrect address
7778 out of the jump table, and chaos would ensue. */
7779 if (label_is_thumb_function_name
7780 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
7781 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
7783 /* When the address of a Thumb function is taken the bottom
7784 bit of that address should be set. This will allow
7785 interworking between Arm and Thumb functions to work
7788 THUMB_SET_FUNC (sym, 1);
7790 label_is_thumb_function_name = FALSE;
7795 arm_data_in_code (void)
7797 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7799 *input_line_pointer = '/';
7800 input_line_pointer += 5;
7801 *input_line_pointer = 0;
7809 arm_canonicalize_symbol_name (char * name)
7813 if (thumb_mode && (len = strlen (name)) > 5
7814 && streq (name + len - 5, "/data"))
7815 *(name + len - 5) = 0;
7820 /* Table of all register names defined by default. The user can
7821 define additional names with .req. Note that all register names
7822 should appear in both upper and lowercase variants. Some registers
7823 also have mixed-case names. */
7825 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE }
7826 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
7827 #define REGSET(p,t) \
7828 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
7829 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
7830 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
7831 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
7833 static const struct reg_entry reg_names[] =
7835 /* ARM integer registers. */
7836 REGSET(r, RN), REGSET(R, RN),
7838 /* ATPCS synonyms. */
7839 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
7840 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
7841 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7843 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
7844 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
7845 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7847 /* Well-known aliases. */
7848 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
7849 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
7851 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
7852 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
7854 /* Coprocessor numbers. */
7855 REGSET(p, CP), REGSET(P, CP),
7857 /* Coprocessor register numbers. The "cr" variants are for backward
7859 REGSET(c, CN), REGSET(C, CN),
7860 REGSET(cr, CN), REGSET(CR, CN),
7862 /* FPA registers. */
7863 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
7864 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
7866 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
7867 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
7869 /* VFP SP registers. */
7871 REGNUM(s,16,VFS), REGNUM(s,17,VFS), REGNUM(s,18,VFS), REGNUM(s,19,VFS),
7872 REGNUM(s,20,VFS), REGNUM(s,21,VFS), REGNUM(s,22,VFS), REGNUM(s,23,VFS),
7873 REGNUM(s,24,VFS), REGNUM(s,25,VFS), REGNUM(s,26,VFS), REGNUM(s,27,VFS),
7874 REGNUM(s,28,VFS), REGNUM(s,29,VFS), REGNUM(s,30,VFS), REGNUM(s,31,VFS),
7877 REGNUM(S,16,VFS), REGNUM(S,17,VFS), REGNUM(S,18,VFS), REGNUM(S,19,VFS),
7878 REGNUM(S,20,VFS), REGNUM(S,21,VFS), REGNUM(S,22,VFS), REGNUM(S,23,VFS),
7879 REGNUM(S,24,VFS), REGNUM(S,25,VFS), REGNUM(S,26,VFS), REGNUM(S,27,VFS),
7880 REGNUM(S,28,VFS), REGNUM(S,29,VFS), REGNUM(S,30,VFS), REGNUM(S,31,VFS),
7882 /* VFP DP Registers. */
7883 REGSET(d,VFD), REGSET(D,VFS),
7885 /* VFP control registers. */
7886 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
7887 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
7889 /* Maverick DSP coprocessor registers. */
7890 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
7891 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
7893 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
7894 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
7895 REGDEF(dspsc,0,DSPSC),
7897 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
7898 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
7899 REGDEF(DSPSC,0,DSPSC),
7901 /* iWMMXt data registers - p0, c0-15. */
7902 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
7904 /* iWMMXt control registers - p1, c0-3. */
7905 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
7906 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
7907 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
7908 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
7910 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
7911 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
7912 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
7913 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
7914 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
7916 /* XScale accumulator registers. */
7917 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
7923 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
7924 within psr_required_here. */
7925 static const struct asm_psr psrs[] =
7927 /* Backward compatibility notation. Note that "all" is no longer
7928 truly all possible PSR bits. */
7929 {"all", PSR_c | PSR_f},
7933 /* Individual flags. */
7938 /* Combinations of flags. */
7939 {"fs", PSR_f | PSR_s},
7940 {"fx", PSR_f | PSR_x},
7941 {"fc", PSR_f | PSR_c},
7942 {"sf", PSR_s | PSR_f},
7943 {"sx", PSR_s | PSR_x},
7944 {"sc", PSR_s | PSR_c},
7945 {"xf", PSR_x | PSR_f},
7946 {"xs", PSR_x | PSR_s},
7947 {"xc", PSR_x | PSR_c},
7948 {"cf", PSR_c | PSR_f},
7949 {"cs", PSR_c | PSR_s},
7950 {"cx", PSR_c | PSR_x},
7951 {"fsx", PSR_f | PSR_s | PSR_x},
7952 {"fsc", PSR_f | PSR_s | PSR_c},
7953 {"fxs", PSR_f | PSR_x | PSR_s},
7954 {"fxc", PSR_f | PSR_x | PSR_c},
7955 {"fcs", PSR_f | PSR_c | PSR_s},
7956 {"fcx", PSR_f | PSR_c | PSR_x},
7957 {"sfx", PSR_s | PSR_f | PSR_x},
7958 {"sfc", PSR_s | PSR_f | PSR_c},
7959 {"sxf", PSR_s | PSR_x | PSR_f},
7960 {"sxc", PSR_s | PSR_x | PSR_c},
7961 {"scf", PSR_s | PSR_c | PSR_f},
7962 {"scx", PSR_s | PSR_c | PSR_x},
7963 {"xfs", PSR_x | PSR_f | PSR_s},
7964 {"xfc", PSR_x | PSR_f | PSR_c},
7965 {"xsf", PSR_x | PSR_s | PSR_f},
7966 {"xsc", PSR_x | PSR_s | PSR_c},
7967 {"xcf", PSR_x | PSR_c | PSR_f},
7968 {"xcs", PSR_x | PSR_c | PSR_s},
7969 {"cfs", PSR_c | PSR_f | PSR_s},
7970 {"cfx", PSR_c | PSR_f | PSR_x},
7971 {"csf", PSR_c | PSR_s | PSR_f},
7972 {"csx", PSR_c | PSR_s | PSR_x},
7973 {"cxf", PSR_c | PSR_x | PSR_f},
7974 {"cxs", PSR_c | PSR_x | PSR_s},
7975 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
7976 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
7977 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
7978 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
7979 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
7980 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
7981 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
7982 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
7983 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
7984 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
7985 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
7986 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
7987 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
7988 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
7989 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
7990 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
7991 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
7992 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
7993 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
7994 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
7995 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
7996 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
7997 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
7998 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
8001 /* Table of all shift-in-operand names. */
8002 static const struct asm_shift_name shift_names [] =
8004 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
8005 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
8006 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
8007 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
8008 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
8009 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
8012 /* Table of all explicit relocation names. */
8014 static struct reloc_entry reloc_names[] =
8016 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
8017 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
8018 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
8019 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
8020 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
8021 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
8022 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
8023 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
8024 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
8025 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
8026 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32}
8030 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
8031 static const struct asm_cond conds[] =
8035 {"cs", 0x2}, {"hs", 0x2},
8036 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
8050 /* Table of ARM-format instructions. */
8052 /* Macros for gluing together operand strings. N.B. In all cases
8053 other than OPS0, the trailing OP_stop comes from default
8054 zero-initialization of the unspecified elements of the array. */
8055 #define OPS0() { OP_stop, }
8056 #define OPS1(a) { OP_##a, }
8057 #define OPS2(a,b) { OP_##a,OP_##b, }
8058 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
8059 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
8060 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
8061 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
8063 /* These macros abstract out the exact format of the mnemonic table and
8064 save some repeated characters. */
8066 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
8067 #define TxCE(mnem, op, top, nops, ops, ae, te) \
8068 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
8069 THUMB_VARIANT, do_##ae, do_##te }
8071 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
8072 a T_MNEM_xyz enumerator. */
8073 #define TCE(mnem, aop, top, nops, ops, ae, te) \
8074 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
8075 #define tCE(mnem, aop, top, nops, ops, ae, te) \
8076 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8078 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
8079 infix after the third character. */
8080 #define TxC3(mnem, op, top, nops, ops, ae, te) \
8081 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
8082 THUMB_VARIANT, do_##ae, do_##te }
8083 #define TC3(mnem, aop, top, nops, ops, ae, te) \
8084 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
8085 #define tC3(mnem, aop, top, nops, ops, ae, te) \
8086 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
8088 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
8089 appear in the condition table. */
8090 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
8091 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8092 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
8094 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
8095 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
8096 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
8097 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
8098 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
8099 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
8100 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
8101 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
8102 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
8103 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
8104 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
8105 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
8106 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
8107 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
8108 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
8109 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
8110 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
8111 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
8112 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
8113 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
8115 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
8116 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
8117 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
8118 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
8120 /* Mnemonic that cannot be conditionalized. The ARM condition-code
8121 field is still 0xE. */
8122 #define TUE(mnem, op, top, nops, ops, ae, te) \
8123 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
8124 THUMB_VARIANT, do_##ae, do_##te }
8126 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
8127 condition code field. */
8128 #define TUF(mnem, op, top, nops, ops, ae, te) \
8129 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
8130 THUMB_VARIANT, do_##ae, do_##te }
8132 /* ARM-only variants of all the above. */
8133 #define CE(mnem, op, nops, ops, ae) \
8134 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8136 #define C3(mnem, op, nops, ops, ae) \
8137 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8139 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
8140 { #m1 #m2 #m3, OPS##nops ops, \
8141 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
8142 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
8144 #define CM(m1, m2, op, nops, ops, ae) \
8145 xCM_(m1, , m2, op, nops, ops, ae), \
8146 xCM_(m1, eq, m2, op, nops, ops, ae), \
8147 xCM_(m1, ne, m2, op, nops, ops, ae), \
8148 xCM_(m1, cs, m2, op, nops, ops, ae), \
8149 xCM_(m1, hs, m2, op, nops, ops, ae), \
8150 xCM_(m1, cc, m2, op, nops, ops, ae), \
8151 xCM_(m1, ul, m2, op, nops, ops, ae), \
8152 xCM_(m1, lo, m2, op, nops, ops, ae), \
8153 xCM_(m1, mi, m2, op, nops, ops, ae), \
8154 xCM_(m1, pl, m2, op, nops, ops, ae), \
8155 xCM_(m1, vs, m2, op, nops, ops, ae), \
8156 xCM_(m1, vc, m2, op, nops, ops, ae), \
8157 xCM_(m1, hi, m2, op, nops, ops, ae), \
8158 xCM_(m1, ls, m2, op, nops, ops, ae), \
8159 xCM_(m1, ge, m2, op, nops, ops, ae), \
8160 xCM_(m1, lt, m2, op, nops, ops, ae), \
8161 xCM_(m1, gt, m2, op, nops, ops, ae), \
8162 xCM_(m1, le, m2, op, nops, ops, ae), \
8163 xCM_(m1, al, m2, op, nops, ops, ae)
8165 #define UE(mnem, op, nops, ops, ae) \
8166 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8168 #define UF(mnem, op, nops, ops, ae) \
8169 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
8173 /* Thumb-only, unconditional. */
8174 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
8176 /* ARM-only, takes either a suffix or a position-3 infix
8177 (for an FPA corner case). */
8178 #define C3E(mnem, op, nops, ops, ae) \
8179 { #mnem, OPS##nops ops, OT_csuf_or_in3, 0x##op, 0, ARM_VARIANT, 0, do_##ae, 0 }
8181 static const struct asm_opcode insns[] =
8183 #define ARM_VARIANT ARM_EXT_V1 /* Core ARM Instructions. */
8184 #define THUMB_VARIANT ARM_EXT_V4T
8185 tCE(and, 0000000, and, 3, (RR, oRR, SH), arit, t_arit3c),
8186 tC3(ands, 0100000, ands, 3, (RR, oRR, SH), arit, t_arit3c),
8187 tCE(eor, 0200000, eor, 3, (RR, oRR, SH), arit, t_arit3c),
8188 tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
8189 tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
8190 tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
8191 tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
8192 tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
8193 tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
8194 tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
8195 tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
8196 tC3(sbcs, 0d00000, sbcs, 3, (RR, oRR, SH), arit, t_arit3),
8197 tCE(orr, 1800000, orr, 3, (RR, oRR, SH), arit, t_arit3c),
8198 tC3(orrs, 1900000, orrs, 3, (RR, oRR, SH), arit, t_arit3c),
8199 tCE(bic, 1c00000, bic, 3, (RR, oRR, SH), arit, t_arit3),
8200 tC3(bics, 1d00000, bics, 3, (RR, oRR, SH), arit, t_arit3),
8202 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
8203 for setting PSR flag bits. They are obsolete in V6 and do not
8204 have Thumb equivalents. */
8205 tCE(tst, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8206 tC3(tsts, 1100000, tst, 2, (RR, SH), cmp, t_mvn_tst),
8207 C3(tstp, 110f000, 2, (RR, SH), cmp),
8208 tCE(cmp, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8209 tC3(cmps, 1500000, cmp, 2, (RR, SH), cmp, t_mov_cmp),
8210 C3(cmpp, 150f000, 2, (RR, SH), cmp),
8211 tCE(cmn, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8212 tC3(cmns, 1700000, cmn, 2, (RR, SH), cmp, t_mvn_tst),
8213 C3(cmnp, 170f000, 2, (RR, SH), cmp),
8215 tCE(mov, 1a00000, mov, 2, (RR, SH), mov, t_mov_cmp),
8216 tC3(movs, 1b00000, movs, 2, (RR, SH), mov, t_mov_cmp),
8217 tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
8218 tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
8220 tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
8221 tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
8222 tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
8223 tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
8225 tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8226 tC3(stmea, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8227 tC3(ldmia, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8228 tC3(ldmfd, 8900000, ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8230 TCE(swi, f000000, df00, 1, (EXPi), swi, t_swi),
8231 TCE(b, a000000, e000, 1, (EXPr), branch, t_branch),
8232 TCE(bl, b000000, f000f800, 1, (EXPr), branch, t_branch23),
8235 tCE(adr, 28f0000, adr, 2, (RR, EXP), adr, t_adr),
8236 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
8237 tCE(nop, 1a00000, nop, 1, (oI255c), nop, t_nop),
8239 /* Thumb-compatibility pseudo ops. */
8240 tCE(lsl, 1a00000, lsl, 3, (RR, oRR, SH), shift, t_shift),
8241 tC3(lsls, 1b00000, lsls, 3, (RR, oRR, SH), shift, t_shift),
8242 tCE(lsr, 1a00020, lsr, 3, (RR, oRR, SH), shift, t_shift),
8243 tC3(lsrs, 1b00020, lsrs, 3, (RR, oRR, SH), shift, t_shift),
8244 tCE(asr, 1a00040, asr, 3, (RR, oRR, SH), shift, t_shift),
8245 tC3(asrs, 1b00040, asrs, 3, (RR, oRR, SH), shift, t_shift),
8246 tCE(ror, 1a00060, ror, 3, (RR, oRR, SH), shift, t_shift),
8247 tC3(rors, 1b00060, rors, 3, (RR, oRR, SH), shift, t_shift),
8248 tCE(neg, 2600000, neg, 2, (RR, RR), rd_rn, t_neg),
8249 tC3(negs, 2700000, negs, 2, (RR, RR), rd_rn, t_neg),
8250 tCE(push, 92d0000, push, 1, (REGLST), push_pop, t_push_pop),
8251 tCE(pop, 8bd0000, pop, 1, (REGLST), push_pop, t_push_pop),
8253 #undef THUMB_VARIANT
8254 #define THUMB_VARIANT ARM_EXT_V6
8255 TCE(cpy, 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
8257 /* V1 instructions with no Thumb analogue prior to V6T2. */
8258 #undef THUMB_VARIANT
8259 #define THUMB_VARIANT ARM_EXT_V6T2
8260 TCE(rsb, 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
8261 TC3(rsbs, 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
8262 TCE(teq, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8263 TC3(teqs, 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
8264 C3(teqp, 130f000, 2, (RR, SH), cmp),
8266 TC3(ldrt, 4300000, f8500e00, 2, (RR, ADDR), ldstt, t_ldstt),
8267 TC3(ldrbt, 4700000, f8300e00, 2, (RR, ADDR), ldstt, t_ldstt),
8268 TC3(strt, 4200000, f8400e00, 2, (RR, ADDR), ldstt, t_ldstt),
8269 TC3(strbt, 4600000, f8200e00, 2, (RR, ADDR), ldstt, t_ldstt),
8271 TC3(stmdb, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8272 TC3(stmfd, 9000000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8274 TC3(ldmdb, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8275 TC3(ldmea, 9100000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
8277 /* V1 instructions with no Thumb analogue at all. */
8278 CE(rsc, 0e00000, 3, (RR, oRR, SH), arit),
8279 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
8281 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
8282 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
8283 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
8284 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
8285 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
8286 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
8287 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
8288 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
8291 #define ARM_VARIANT ARM_EXT_V2 /* ARM 2 - multiplies. */
8292 #undef THUMB_VARIANT
8293 #define THUMB_VARIANT ARM_EXT_V4T
8294 tCE(mul, 0000090, mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8295 tC3(muls, 0100090, muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
8297 #undef THUMB_VARIANT
8298 #define THUMB_VARIANT ARM_EXT_V6T2
8299 TCE(mla, 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8300 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
8302 /* Generic coprocessor instructions. */
8303 TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8304 TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8305 TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8306 TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8307 TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8308 TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8309 TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8312 #define ARM_VARIANT ARM_EXT_V2S /* ARM 3 - swp instructions. */
8313 CE(swp, 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8314 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
8317 #define ARM_VARIANT ARM_EXT_V3 /* ARM 6 Status register instructions. */
8318 TCE(mrs, 10f0000, f3ef8000, 2, (RR, PSR), mrs, t_mrs),
8319 TCE(msr, 120f000, f3808000, 2, (PSR, RR_EXi), msr, t_msr),
8322 #define ARM_VARIANT ARM_EXT_V3M /* ARM 7M long multiplies. */
8323 TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8324 CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8325 TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8326 CM(umull,s, 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8327 TCE(smlal, 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8328 CM(smlal,s, 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8329 TCE(umlal, 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
8330 CM(umlal,s, 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
8333 #define ARM_VARIANT ARM_EXT_V4 /* ARM Architecture 4. */
8334 #undef THUMB_VARIANT
8335 #define THUMB_VARIANT ARM_EXT_V4T
8336 tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
8337 tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
8338 tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8339 tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8340 tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
8341 tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
8344 #define ARM_VARIANT ARM_EXT_V4T|ARM_EXT_V5
8345 /* ARM Architecture 4T. */
8346 /* Note: bx (and blx) are required on V5, even if the processor does
8347 not support Thumb. */
8348 TCE(bx, 12fff10, 4700, 1, (RR), bx, t_bx),
8351 #define ARM_VARIANT ARM_EXT_V5 /* ARM Architecture 5T. */
8352 #undef THUMB_VARIANT
8353 #define THUMB_VARIANT ARM_EXT_V5T
8354 /* Note: blx has 2 variants; the .value coded here is for
8355 BLX(2). Only this variant has conditional execution. */
8356 TCE(blx, 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
8357 TUE(bkpt, 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
8359 #undef THUMB_VARIANT
8360 #define THUMB_VARIANT ARM_EXT_V6T2
8361 TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
8362 TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
8363 TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
8364 TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
8365 TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
8366 TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
8367 TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8368 TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
8371 #define ARM_VARIANT ARM_EXT_V5ExP /* ARM Architecture 5TExP. */
8372 TCE(smlabb, 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8373 TCE(smlatb, 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8374 TCE(smlabt, 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8375 TCE(smlatt, 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8377 TCE(smlawb, 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8378 TCE(smlawt, 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
8380 TCE(smlalbb, 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8381 TCE(smlaltb, 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8382 TCE(smlalbt, 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8383 TCE(smlaltt, 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
8385 TCE(smulbb, 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8386 TCE(smultb, 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8387 TCE(smulbt, 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8388 TCE(smultt, 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8390 TCE(smulwb, 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8391 TCE(smulwt, 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8393 TCE(qadd, 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8394 TCE(qdadd, 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8395 TCE(qsub, 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8396 TCE(qdsub, 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, rd_rm_rn),
8399 #define ARM_VARIANT ARM_EXT_V5E /* ARM Architecture 5TE. */
8400 TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
8401 TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8402 TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
8404 TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8405 TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8408 #define ARM_VARIANT ARM_EXT_V5J /* ARM Architecture 5TEJ. */
8409 TCE(bxj, 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
8412 #define ARM_VARIANT ARM_EXT_V6 /* ARM V6. */
8413 #undef THUMB_VARIANT
8414 #define THUMB_VARIANT ARM_EXT_V6
8415 TUF(cpsie, 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
8416 TUF(cpsid, 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
8417 tCE(rev, 6bf0f30, rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8418 tCE(rev16, 6bf0fb0, rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8419 tCE(revsh, 6ff0fb0, revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
8420 tCE(sxth, 6bf0070, sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8421 tCE(uxth, 6ff0070, uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8422 tCE(sxtb, 6af0070, sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8423 tCE(uxtb, 6ef0070, uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8424 TUF(setend, 1010000, b650, 1, (ENDI), setend, t_setend),
8426 #undef THUMB_VARIANT
8427 #define THUMB_VARIANT ARM_EXT_V6T2
8428 TUF(cps, 1020000, f3af8100, 1, (I31b), imm0, imm0),
8429 TCE(ldrex, 1900f9f, e8500f00, 2, (RRnpc, ADDR), ldrex, t_ldrex),
8430 TUF(mcrr2, c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8431 TUF(mrrc2, c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
8432 TCE(pkhbt, 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
8433 TCE(pkhtb, 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
8434 TCE(qadd16, 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8435 TCE(qadd8, 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8436 TCE(qaddsubx, 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8437 TCE(qsub16, 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8438 TCE(qsub8, 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8439 TCE(qsubaddx, 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8440 TCE(sadd16, 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8441 TCE(sadd8, 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8442 TCE(saddsubx, 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8443 TCE(shadd16, 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8444 TCE(shadd8, 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8445 TCE(shaddsubx, 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8446 TCE(shsub16, 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8447 TCE(shsub8, 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8448 TCE(shsubaddx, 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8449 TCE(ssub16, 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8450 TCE(ssub8, 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8451 TCE(ssubaddx, 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8452 TCE(uadd16, 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8453 TCE(uadd8, 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8454 TCE(uaddsubx, 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8455 TCE(uhadd16, 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8456 TCE(uhadd8, 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8457 TCE(uhaddsubx, 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8458 TCE(uhsub16, 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8459 TCE(uhsub8, 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8460 TCE(uhsubaddx, 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8461 TCE(uqadd16, 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8462 TCE(uqadd8, 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8463 TCE(uqaddsubx, 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8464 TCE(uqsub16, 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8465 TCE(uqsub8, 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8466 TCE(uqsubaddx, 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8467 TCE(usub16, 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8468 TCE(usub8, 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8469 TCE(usubaddx, 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8470 TUF(rfeia, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8471 UF(rfeib, 9900a00, 1, (RRw), rfe),
8472 UF(rfeda, 8100a00, 1, (RRw), rfe),
8473 TUF(rfedb, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8474 TUF(rfefd, 8900a00, e990c000, 1, (RRw), rfe, rfe),
8475 UF(rfefa, 9900a00, 1, (RRw), rfe),
8476 UF(rfeea, 8100a00, 1, (RRw), rfe),
8477 TUF(rfeed, 9100a00, e810c000, 1, (RRw), rfe, rfe),
8478 TCE(sxtah, 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8479 TCE(sxtab16, 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8480 TCE(sxtab, 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8481 TCE(sxtb16, 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8482 TCE(uxtah, 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8483 TCE(uxtab16, 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8484 TCE(uxtab, 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
8485 TCE(uxtb16, 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
8486 TCE(sel, 68000b0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
8487 TCE(smlad, 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8488 TCE(smladx, 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8489 TCE(smlald, 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8490 TCE(smlaldx, 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8491 TCE(smlsd, 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8492 TCE(smlsdx, 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8493 TCE(smlsld, 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8494 TCE(smlsldx, 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
8495 TCE(smmla, 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8496 TCE(smmlar, 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8497 TCE(smmls, 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8498 TCE(smmlsr, 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8499 TCE(smmul, 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8500 TCE(smmulr, 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8501 TCE(smuad, 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8502 TCE(smuadx, 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8503 TCE(smusd, 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8504 TCE(smusdx, 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8505 TUF(srsia, 8cd0500, e980c000, 1, (I31w), srs, srs),
8506 UF(srsib, 9cd0500, 1, (I31w), srs),
8507 UF(srsda, 84d0500, 1, (I31w), srs),
8508 TUF(srsdb, 94d0500, e800c000, 1, (I31w), srs, srs),
8509 TCE(ssat, 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
8510 TCE(ssat16, 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
8511 TCE(strex, 1800f90, e8400000, 3, (RRnpc, RRnpc, ADDR), strex, t_strex),
8512 TCE(umaal, 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
8513 TCE(usad8, 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
8514 TCE(usada8, 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
8515 TCE(usat, 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
8516 TCE(usat16, 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
8519 #define ARM_VARIANT ARM_EXT_V6K
8520 #undef THUMB_VARIANT
8521 #define THUMB_VARIANT ARM_EXT_V6K
8522 tCE(yield, 320f001, yield, 0, (), noargs, t_hint),
8523 tCE(wfe, 320f002, wfe, 0, (), noargs, t_hint),
8524 tCE(wfi, 320f003, wfi, 0, (), noargs, t_hint),
8525 tCE(sev, 320f004, sev, 0, (), noargs, t_hint),
8527 #undef THUMB_VARIANT
8528 #define THUMB_VARIANT ARM_EXT_V6T2
8529 TCE(ldrexb, 1d00f9f, e8d00f4f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8530 TCE(ldrexh, 1f00f9f, e8d00f5f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
8531 TCE(ldrexd, 1b00f9f, e8d0007f, 3, (RRnpc, oRRnpc, RRnpcb), ldrexd, t_ldrexd),
8532 TCE(strexb, 1c00f90, e8c00f40, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8533 TCE(strexh, 1e00f90, e8c00f50, 3, (RRnpc, RRnpc, ADDR), strex, rm_rd_rn),
8534 TCE(strexd, 1a00f90, e8c00070, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), strexd, t_strexd),
8535 TUF(clrex, 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
8538 #define ARM_VARIANT ARM_EXT_V6Z
8539 TCE(smi, 1600070, f7f08000, 1, (EXPi), smi, t_smi),
8542 #define ARM_VARIANT ARM_EXT_V6T2
8543 TCE(bfc, 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
8544 TCE(bfi, 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
8545 TCE(sbfx, 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8546 TCE(ubfx, 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
8548 TCE(mls, 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
8549 TCE(movw, 3000000, f2400000, 2, (RRnpc, Iffff), mov16, t_mov16),
8550 TCE(movt, 3400000, f2c00000, 2, (RRnpc, Iffff), mov16, t_mov16),
8551 TCE(rbit, 3ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
8553 TC3(ldrht, 03000b0, f8300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8554 TC3(ldrsht, 03000f0, f9300e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8555 TC3(ldrsbt, 03000d0, f9100e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8556 TC3(strht, 02000b0, f8200e00, 2, (RR, ADDR), ldsttv4, t_ldstt),
8558 UT(cbnz, b900, 2, (RR, EXP), t_czb),
8559 UT(cbz, b100, 2, (RR, EXP), t_czb),
8560 /* ARM does not really have an IT instruction. */
8561 TUE(it, 0, bf08, 1, (COND), it, t_it),
8562 TUE(itt, 0, bf0c, 1, (COND), it, t_it),
8563 TUE(ite, 0, bf04, 1, (COND), it, t_it),
8564 TUE(ittt, 0, bf0e, 1, (COND), it, t_it),
8565 TUE(itet, 0, bf06, 1, (COND), it, t_it),
8566 TUE(itte, 0, bf0a, 1, (COND), it, t_it),
8567 TUE(itee, 0, bf02, 1, (COND), it, t_it),
8568 TUE(itttt, 0, bf0f, 1, (COND), it, t_it),
8569 TUE(itett, 0, bf07, 1, (COND), it, t_it),
8570 TUE(ittet, 0, bf0b, 1, (COND), it, t_it),
8571 TUE(iteet, 0, bf03, 1, (COND), it, t_it),
8572 TUE(ittte, 0, bf0d, 1, (COND), it, t_it),
8573 TUE(itete, 0, bf05, 1, (COND), it, t_it),
8574 TUE(ittee, 0, bf09, 1, (COND), it, t_it),
8575 TUE(iteee, 0, bf01, 1, (COND), it, t_it),
8577 /* Thumb2 only instructions. */
8579 #define ARM_VARIANT 0
8581 TCE(addw, 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8582 TCE(subw, 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
8583 TCE(tbb, 0, e8d0f000, 1, (TB), 0, t_tb),
8584 TCE(tbh, 0, e8d0f010, 1, (TB), 0, t_tb),
8587 #define ARM_VARIANT FPU_FPA_EXT_V1 /* Core FPA instruction set (V1). */
8588 CE(wfs, e200110, 1, (RR), rd),
8589 CE(rfs, e300110, 1, (RR), rd),
8590 CE(wfc, e400110, 1, (RR), rd),
8591 CE(rfc, e500110, 1, (RR), rd),
8593 C3(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
8594 C3(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
8595 C3(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
8596 C3(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
8598 C3(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
8599 C3(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
8600 C3(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
8601 C3(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
8603 C3(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
8604 C3(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
8605 C3(mvfsm, e008140, 2, (RF, RF_IF), rd_rm),
8606 C3(mvfsz, e008160, 2, (RF, RF_IF), rd_rm),
8607 C3(mvfd, e008180, 2, (RF, RF_IF), rd_rm),
8608 C3(mvfdp, e0081a0, 2, (RF, RF_IF), rd_rm),
8609 C3(mvfdm, e0081c0, 2, (RF, RF_IF), rd_rm),
8610 C3(mvfdz, e0081e0, 2, (RF, RF_IF), rd_rm),
8611 C3(mvfe, e088100, 2, (RF, RF_IF), rd_rm),
8612 C3(mvfep, e088120, 2, (RF, RF_IF), rd_rm),
8613 C3(mvfem, e088140, 2, (RF, RF_IF), rd_rm),
8614 C3(mvfez, e088160, 2, (RF, RF_IF), rd_rm),
8616 C3(mnfs, e108100, 2, (RF, RF_IF), rd_rm),
8617 C3(mnfsp, e108120, 2, (RF, RF_IF), rd_rm),
8618 C3(mnfsm, e108140, 2, (RF, RF_IF), rd_rm),
8619 C3(mnfsz, e108160, 2, (RF, RF_IF), rd_rm),
8620 C3(mnfd, e108180, 2, (RF, RF_IF), rd_rm),
8621 C3(mnfdp, e1081a0, 2, (RF, RF_IF), rd_rm),
8622 C3(mnfdm, e1081c0, 2, (RF, RF_IF), rd_rm),
8623 C3(mnfdz, e1081e0, 2, (RF, RF_IF), rd_rm),
8624 C3(mnfe, e188100, 2, (RF, RF_IF), rd_rm),
8625 C3(mnfep, e188120, 2, (RF, RF_IF), rd_rm),
8626 C3(mnfem, e188140, 2, (RF, RF_IF), rd_rm),
8627 C3(mnfez, e188160, 2, (RF, RF_IF), rd_rm),
8629 C3(abss, e208100, 2, (RF, RF_IF), rd_rm),
8630 C3(abssp, e208120, 2, (RF, RF_IF), rd_rm),
8631 C3(abssm, e208140, 2, (RF, RF_IF), rd_rm),
8632 C3(abssz, e208160, 2, (RF, RF_IF), rd_rm),
8633 C3(absd, e208180, 2, (RF, RF_IF), rd_rm),
8634 C3(absdp, e2081a0, 2, (RF, RF_IF), rd_rm),
8635 C3(absdm, e2081c0, 2, (RF, RF_IF), rd_rm),
8636 C3(absdz, e2081e0, 2, (RF, RF_IF), rd_rm),
8637 C3(abse, e288100, 2, (RF, RF_IF), rd_rm),
8638 C3(absep, e288120, 2, (RF, RF_IF), rd_rm),
8639 C3(absem, e288140, 2, (RF, RF_IF), rd_rm),
8640 C3(absez, e288160, 2, (RF, RF_IF), rd_rm),
8642 C3(rnds, e308100, 2, (RF, RF_IF), rd_rm),
8643 C3(rndsp, e308120, 2, (RF, RF_IF), rd_rm),
8644 C3(rndsm, e308140, 2, (RF, RF_IF), rd_rm),
8645 C3(rndsz, e308160, 2, (RF, RF_IF), rd_rm),
8646 C3(rndd, e308180, 2, (RF, RF_IF), rd_rm),
8647 C3(rnddp, e3081a0, 2, (RF, RF_IF), rd_rm),
8648 C3(rnddm, e3081c0, 2, (RF, RF_IF), rd_rm),
8649 C3(rnddz, e3081e0, 2, (RF, RF_IF), rd_rm),
8650 C3(rnde, e388100, 2, (RF, RF_IF), rd_rm),
8651 C3(rndep, e388120, 2, (RF, RF_IF), rd_rm),
8652 C3(rndem, e388140, 2, (RF, RF_IF), rd_rm),
8653 C3(rndez, e388160, 2, (RF, RF_IF), rd_rm),
8655 C3(sqts, e408100, 2, (RF, RF_IF), rd_rm),
8656 C3(sqtsp, e408120, 2, (RF, RF_IF), rd_rm),
8657 C3(sqtsm, e408140, 2, (RF, RF_IF), rd_rm),
8658 C3(sqtsz, e408160, 2, (RF, RF_IF), rd_rm),
8659 C3(sqtd, e408180, 2, (RF, RF_IF), rd_rm),
8660 C3(sqtdp, e4081a0, 2, (RF, RF_IF), rd_rm),
8661 C3(sqtdm, e4081c0, 2, (RF, RF_IF), rd_rm),
8662 C3(sqtdz, e4081e0, 2, (RF, RF_IF), rd_rm),
8663 C3(sqte, e488100, 2, (RF, RF_IF), rd_rm),
8664 C3(sqtep, e488120, 2, (RF, RF_IF), rd_rm),
8665 C3(sqtem, e488140, 2, (RF, RF_IF), rd_rm),
8666 C3(sqtez, e488160, 2, (RF, RF_IF), rd_rm),
8668 C3(logs, e508100, 2, (RF, RF_IF), rd_rm),
8669 C3(logsp, e508120, 2, (RF, RF_IF), rd_rm),
8670 C3(logsm, e508140, 2, (RF, RF_IF), rd_rm),
8671 C3(logsz, e508160, 2, (RF, RF_IF), rd_rm),
8672 C3(logd, e508180, 2, (RF, RF_IF), rd_rm),
8673 C3(logdp, e5081a0, 2, (RF, RF_IF), rd_rm),
8674 C3(logdm, e5081c0, 2, (RF, RF_IF), rd_rm),
8675 C3(logdz, e5081e0, 2, (RF, RF_IF), rd_rm),
8676 C3(loge, e588100, 2, (RF, RF_IF), rd_rm),
8677 C3(logep, e588120, 2, (RF, RF_IF), rd_rm),
8678 C3(logem, e588140, 2, (RF, RF_IF), rd_rm),
8679 C3(logez, e588160, 2, (RF, RF_IF), rd_rm),
8681 C3(lgns, e608100, 2, (RF, RF_IF), rd_rm),
8682 C3(lgnsp, e608120, 2, (RF, RF_IF), rd_rm),
8683 C3(lgnsm, e608140, 2, (RF, RF_IF), rd_rm),
8684 C3(lgnsz, e608160, 2, (RF, RF_IF), rd_rm),
8685 C3(lgnd, e608180, 2, (RF, RF_IF), rd_rm),
8686 C3(lgndp, e6081a0, 2, (RF, RF_IF), rd_rm),
8687 C3(lgndm, e6081c0, 2, (RF, RF_IF), rd_rm),
8688 C3(lgndz, e6081e0, 2, (RF, RF_IF), rd_rm),
8689 C3(lgne, e688100, 2, (RF, RF_IF), rd_rm),
8690 C3(lgnep, e688120, 2, (RF, RF_IF), rd_rm),
8691 C3(lgnem, e688140, 2, (RF, RF_IF), rd_rm),
8692 C3(lgnez, e688160, 2, (RF, RF_IF), rd_rm),
8694 C3(exps, e708100, 2, (RF, RF_IF), rd_rm),
8695 C3(expsp, e708120, 2, (RF, RF_IF), rd_rm),
8696 C3(expsm, e708140, 2, (RF, RF_IF), rd_rm),
8697 C3(expsz, e708160, 2, (RF, RF_IF), rd_rm),
8698 C3(expd, e708180, 2, (RF, RF_IF), rd_rm),
8699 C3(expdp, e7081a0, 2, (RF, RF_IF), rd_rm),
8700 C3(expdm, e7081c0, 2, (RF, RF_IF), rd_rm),
8701 C3(expdz, e7081e0, 2, (RF, RF_IF), rd_rm),
8702 C3(expe, e788100, 2, (RF, RF_IF), rd_rm),
8703 C3(expep, e788120, 2, (RF, RF_IF), rd_rm),
8704 C3(expem, e788140, 2, (RF, RF_IF), rd_rm),
8705 C3(expdz, e788160, 2, (RF, RF_IF), rd_rm),
8707 C3(sins, e808100, 2, (RF, RF_IF), rd_rm),
8708 C3(sinsp, e808120, 2, (RF, RF_IF), rd_rm),
8709 C3(sinsm, e808140, 2, (RF, RF_IF), rd_rm),
8710 C3(sinsz, e808160, 2, (RF, RF_IF), rd_rm),
8711 C3(sind, e808180, 2, (RF, RF_IF), rd_rm),
8712 C3(sindp, e8081a0, 2, (RF, RF_IF), rd_rm),
8713 C3(sindm, e8081c0, 2, (RF, RF_IF), rd_rm),
8714 C3(sindz, e8081e0, 2, (RF, RF_IF), rd_rm),
8715 C3(sine, e888100, 2, (RF, RF_IF), rd_rm),
8716 C3(sinep, e888120, 2, (RF, RF_IF), rd_rm),
8717 C3(sinem, e888140, 2, (RF, RF_IF), rd_rm),
8718 C3(sinez, e888160, 2, (RF, RF_IF), rd_rm),
8720 C3(coss, e908100, 2, (RF, RF_IF), rd_rm),
8721 C3(cossp, e908120, 2, (RF, RF_IF), rd_rm),
8722 C3(cossm, e908140, 2, (RF, RF_IF), rd_rm),
8723 C3(cossz, e908160, 2, (RF, RF_IF), rd_rm),
8724 C3(cosd, e908180, 2, (RF, RF_IF), rd_rm),
8725 C3(cosdp, e9081a0, 2, (RF, RF_IF), rd_rm),
8726 C3(cosdm, e9081c0, 2, (RF, RF_IF), rd_rm),
8727 C3(cosdz, e9081e0, 2, (RF, RF_IF), rd_rm),
8728 C3(cose, e988100, 2, (RF, RF_IF), rd_rm),
8729 C3(cosep, e988120, 2, (RF, RF_IF), rd_rm),
8730 C3(cosem, e988140, 2, (RF, RF_IF), rd_rm),
8731 C3(cosez, e988160, 2, (RF, RF_IF), rd_rm),
8733 C3(tans, ea08100, 2, (RF, RF_IF), rd_rm),
8734 C3(tansp, ea08120, 2, (RF, RF_IF), rd_rm),
8735 C3(tansm, ea08140, 2, (RF, RF_IF), rd_rm),
8736 C3(tansz, ea08160, 2, (RF, RF_IF), rd_rm),
8737 C3(tand, ea08180, 2, (RF, RF_IF), rd_rm),
8738 C3(tandp, ea081a0, 2, (RF, RF_IF), rd_rm),
8739 C3(tandm, ea081c0, 2, (RF, RF_IF), rd_rm),
8740 C3(tandz, ea081e0, 2, (RF, RF_IF), rd_rm),
8741 C3(tane, ea88100, 2, (RF, RF_IF), rd_rm),
8742 C3(tanep, ea88120, 2, (RF, RF_IF), rd_rm),
8743 C3(tanem, ea88140, 2, (RF, RF_IF), rd_rm),
8744 C3(tanez, ea88160, 2, (RF, RF_IF), rd_rm),
8746 C3(asns, eb08100, 2, (RF, RF_IF), rd_rm),
8747 C3(asnsp, eb08120, 2, (RF, RF_IF), rd_rm),
8748 C3(asnsm, eb08140, 2, (RF, RF_IF), rd_rm),
8749 C3(asnsz, eb08160, 2, (RF, RF_IF), rd_rm),
8750 C3(asnd, eb08180, 2, (RF, RF_IF), rd_rm),
8751 C3(asndp, eb081a0, 2, (RF, RF_IF), rd_rm),
8752 C3(asndm, eb081c0, 2, (RF, RF_IF), rd_rm),
8753 C3(asndz, eb081e0, 2, (RF, RF_IF), rd_rm),
8754 C3(asne, eb88100, 2, (RF, RF_IF), rd_rm),
8755 C3(asnep, eb88120, 2, (RF, RF_IF), rd_rm),
8756 C3(asnem, eb88140, 2, (RF, RF_IF), rd_rm),
8757 C3(asnez, eb88160, 2, (RF, RF_IF), rd_rm),
8759 C3(acss, ec08100, 2, (RF, RF_IF), rd_rm),
8760 C3(acssp, ec08120, 2, (RF, RF_IF), rd_rm),
8761 C3(acssm, ec08140, 2, (RF, RF_IF), rd_rm),
8762 C3(acssz, ec08160, 2, (RF, RF_IF), rd_rm),
8763 C3(acsd, ec08180, 2, (RF, RF_IF), rd_rm),
8764 C3(acsdp, ec081a0, 2, (RF, RF_IF), rd_rm),
8765 C3(acsdm, ec081c0, 2, (RF, RF_IF), rd_rm),
8766 C3(acsdz, ec081e0, 2, (RF, RF_IF), rd_rm),
8767 C3(acse, ec88100, 2, (RF, RF_IF), rd_rm),
8768 C3(acsep, ec88120, 2, (RF, RF_IF), rd_rm),
8769 C3(acsem, ec88140, 2, (RF, RF_IF), rd_rm),
8770 C3(acsez, ec88160, 2, (RF, RF_IF), rd_rm),
8772 C3(atns, ed08100, 2, (RF, RF_IF), rd_rm),
8773 C3(atnsp, ed08120, 2, (RF, RF_IF), rd_rm),
8774 C3(atnsm, ed08140, 2, (RF, RF_IF), rd_rm),
8775 C3(atnsz, ed08160, 2, (RF, RF_IF), rd_rm),
8776 C3(atnd, ed08180, 2, (RF, RF_IF), rd_rm),
8777 C3(atndp, ed081a0, 2, (RF, RF_IF), rd_rm),
8778 C3(atndm, ed081c0, 2, (RF, RF_IF), rd_rm),
8779 C3(atndz, ed081e0, 2, (RF, RF_IF), rd_rm),
8780 C3(atne, ed88100, 2, (RF, RF_IF), rd_rm),
8781 C3(atnep, ed88120, 2, (RF, RF_IF), rd_rm),
8782 C3(atnem, ed88140, 2, (RF, RF_IF), rd_rm),
8783 C3(atnez, ed88160, 2, (RF, RF_IF), rd_rm),
8785 C3(urds, ee08100, 2, (RF, RF_IF), rd_rm),
8786 C3(urdsp, ee08120, 2, (RF, RF_IF), rd_rm),
8787 C3(urdsm, ee08140, 2, (RF, RF_IF), rd_rm),
8788 C3(urdsz, ee08160, 2, (RF, RF_IF), rd_rm),
8789 C3(urdd, ee08180, 2, (RF, RF_IF), rd_rm),
8790 C3(urddp, ee081a0, 2, (RF, RF_IF), rd_rm),
8791 C3(urddm, ee081c0, 2, (RF, RF_IF), rd_rm),
8792 C3(urddz, ee081e0, 2, (RF, RF_IF), rd_rm),
8793 C3(urde, ee88100, 2, (RF, RF_IF), rd_rm),
8794 C3(urdep, ee88120, 2, (RF, RF_IF), rd_rm),
8795 C3(urdem, ee88140, 2, (RF, RF_IF), rd_rm),
8796 C3(urdez, ee88160, 2, (RF, RF_IF), rd_rm),
8798 C3(nrms, ef08100, 2, (RF, RF_IF), rd_rm),
8799 C3(nrmsp, ef08120, 2, (RF, RF_IF), rd_rm),
8800 C3(nrmsm, ef08140, 2, (RF, RF_IF), rd_rm),
8801 C3(nrmsz, ef08160, 2, (RF, RF_IF), rd_rm),
8802 C3(nrmd, ef08180, 2, (RF, RF_IF), rd_rm),
8803 C3(nrmdp, ef081a0, 2, (RF, RF_IF), rd_rm),
8804 C3(nrmdm, ef081c0, 2, (RF, RF_IF), rd_rm),
8805 C3(nrmdz, ef081e0, 2, (RF, RF_IF), rd_rm),
8806 C3(nrme, ef88100, 2, (RF, RF_IF), rd_rm),
8807 C3(nrmep, ef88120, 2, (RF, RF_IF), rd_rm),
8808 C3(nrmem, ef88140, 2, (RF, RF_IF), rd_rm),
8809 C3(nrmez, ef88160, 2, (RF, RF_IF), rd_rm),
8811 C3(adfs, e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
8812 C3(adfsp, e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
8813 C3(adfsm, e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
8814 C3(adfsz, e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
8815 C3(adfd, e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
8816 C3(adfdp, e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8817 C3(adfdm, e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8818 C3(adfdz, e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8819 C3(adfe, e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
8820 C3(adfep, e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
8821 C3(adfem, e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
8822 C3(adfez, e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
8824 C3(sufs, e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
8825 C3(sufsp, e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
8826 C3(sufsm, e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
8827 C3(sufsz, e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
8828 C3(sufd, e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
8829 C3(sufdp, e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8830 C3(sufdm, e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8831 C3(sufdz, e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8832 C3(sufe, e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
8833 C3(sufep, e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
8834 C3(sufem, e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
8835 C3(sufez, e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
8837 C3(rsfs, e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
8838 C3(rsfsp, e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
8839 C3(rsfsm, e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
8840 C3(rsfsz, e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
8841 C3(rsfd, e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
8842 C3(rsfdp, e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8843 C3(rsfdm, e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8844 C3(rsfdz, e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8845 C3(rsfe, e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
8846 C3(rsfep, e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
8847 C3(rsfem, e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
8848 C3(rsfez, e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
8850 C3(mufs, e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
8851 C3(mufsp, e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
8852 C3(mufsm, e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
8853 C3(mufsz, e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
8854 C3(mufd, e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
8855 C3(mufdp, e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8856 C3(mufdm, e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8857 C3(mufdz, e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8858 C3(mufe, e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
8859 C3(mufep, e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
8860 C3(mufem, e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
8861 C3(mufez, e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
8863 C3(dvfs, e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
8864 C3(dvfsp, e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
8865 C3(dvfsm, e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
8866 C3(dvfsz, e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
8867 C3(dvfd, e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
8868 C3(dvfdp, e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8869 C3(dvfdm, e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8870 C3(dvfdz, e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8871 C3(dvfe, e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
8872 C3(dvfep, e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
8873 C3(dvfem, e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
8874 C3(dvfez, e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
8876 C3(rdfs, e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
8877 C3(rdfsp, e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
8878 C3(rdfsm, e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
8879 C3(rdfsz, e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
8880 C3(rdfd, e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
8881 C3(rdfdp, e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8882 C3(rdfdm, e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8883 C3(rdfdz, e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8884 C3(rdfe, e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
8885 C3(rdfep, e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
8886 C3(rdfem, e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
8887 C3(rdfez, e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
8889 C3(pows, e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
8890 C3(powsp, e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
8891 C3(powsm, e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
8892 C3(powsz, e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
8893 C3(powd, e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
8894 C3(powdp, e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8895 C3(powdm, e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8896 C3(powdz, e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8897 C3(powe, e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
8898 C3(powep, e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
8899 C3(powem, e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
8900 C3(powez, e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
8902 C3(rpws, e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
8903 C3(rpwsp, e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
8904 C3(rpwsm, e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
8905 C3(rpwsz, e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
8906 C3(rpwd, e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
8907 C3(rpwdp, e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8908 C3(rpwdm, e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8909 C3(rpwdz, e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8910 C3(rpwe, e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
8911 C3(rpwep, e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
8912 C3(rpwem, e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
8913 C3(rpwez, e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
8915 C3(rmfs, e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
8916 C3(rmfsp, e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
8917 C3(rmfsm, e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
8918 C3(rmfsz, e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
8919 C3(rmfd, e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
8920 C3(rmfdp, e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8921 C3(rmfdm, e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8922 C3(rmfdz, e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8923 C3(rmfe, e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
8924 C3(rmfep, e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
8925 C3(rmfem, e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
8926 C3(rmfez, e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
8928 C3(fmls, e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
8929 C3(fmlsp, e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
8930 C3(fmlsm, e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
8931 C3(fmlsz, e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
8932 C3(fmld, e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
8933 C3(fmldp, e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8934 C3(fmldm, e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8935 C3(fmldz, e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8936 C3(fmle, e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
8937 C3(fmlep, e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
8938 C3(fmlem, e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
8939 C3(fmlez, e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
8941 C3(fdvs, ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8942 C3(fdvsp, ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8943 C3(fdvsm, ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8944 C3(fdvsz, ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8945 C3(fdvd, ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8946 C3(fdvdp, ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8947 C3(fdvdm, ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8948 C3(fdvdz, ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8949 C3(fdve, ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8950 C3(fdvep, ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8951 C3(fdvem, ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8952 C3(fdvez, ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8954 C3(frds, eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8955 C3(frdsp, eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8956 C3(frdsm, eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8957 C3(frdsz, eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8958 C3(frdd, eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8959 C3(frddp, eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8960 C3(frddm, eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8961 C3(frddz, eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8962 C3(frde, eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8963 C3(frdep, eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8964 C3(frdem, eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8965 C3(frdez, eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8967 C3(pols, ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
8968 C3(polsp, ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
8969 C3(polsm, ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
8970 C3(polsz, ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
8971 C3(pold, ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
8972 C3(poldp, ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
8973 C3(poldm, ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
8974 C3(poldz, ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
8975 C3(pole, ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
8976 C3(polep, ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
8977 C3(polem, ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
8978 C3(polez, ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
8980 CE(cmf, e90f110, 2, (RF, RF_IF), fpa_cmp),
8981 C3E(cmfe, ed0f110, 2, (RF, RF_IF), fpa_cmp),
8982 CE(cnf, eb0f110, 2, (RF, RF_IF), fpa_cmp),
8983 C3E(cnfe, ef0f110, 2, (RF, RF_IF), fpa_cmp),
8985 C3(flts, e000110, 2, (RF, RR), rn_rd),
8986 C3(fltsp, e000130, 2, (RF, RR), rn_rd),
8987 C3(fltsm, e000150, 2, (RF, RR), rn_rd),
8988 C3(fltsz, e000170, 2, (RF, RR), rn_rd),
8989 C3(fltd, e000190, 2, (RF, RR), rn_rd),
8990 C3(fltdp, e0001b0, 2, (RF, RR), rn_rd),
8991 C3(fltdm, e0001d0, 2, (RF, RR), rn_rd),
8992 C3(fltdz, e0001f0, 2, (RF, RR), rn_rd),
8993 C3(flte, e080110, 2, (RF, RR), rn_rd),
8994 C3(fltep, e080130, 2, (RF, RR), rn_rd),
8995 C3(fltem, e080150, 2, (RF, RR), rn_rd),
8996 C3(fltez, e080170, 2, (RF, RR), rn_rd),
8998 /* The implementation of the FIX instruction is broken on some
8999 assemblers, in that it accepts a precision specifier as well as a
9000 rounding specifier, despite the fact that this is meaningless.
9001 To be more compatible, we accept it as well, though of course it
9002 does not set any bits. */
9003 CE(fix, e100110, 2, (RR, RF), rd_rm),
9004 C3(fixp, e100130, 2, (RR, RF), rd_rm),
9005 C3(fixm, e100150, 2, (RR, RF), rd_rm),
9006 C3(fixz, e100170, 2, (RR, RF), rd_rm),
9007 C3(fixsp, e100130, 2, (RR, RF), rd_rm),
9008 C3(fixsm, e100150, 2, (RR, RF), rd_rm),
9009 C3(fixsz, e100170, 2, (RR, RF), rd_rm),
9010 C3(fixdp, e100130, 2, (RR, RF), rd_rm),
9011 C3(fixdm, e100150, 2, (RR, RF), rd_rm),
9012 C3(fixdz, e100170, 2, (RR, RF), rd_rm),
9013 C3(fixep, e100130, 2, (RR, RF), rd_rm),
9014 C3(fixem, e100150, 2, (RR, RF), rd_rm),
9015 C3(fixez, e100170, 2, (RR, RF), rd_rm),
9017 /* Instructions that were new with the real FPA, call them V2. */
9019 #define ARM_VARIANT FPU_FPA_EXT_V2
9020 CE(lfm, c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9021 C3(lfmfd, c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9022 C3(lfmea, d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9023 CE(sfm, c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9024 C3(sfmfd, d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9025 C3(sfmea, c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
9028 #define ARM_VARIANT FPU_VFP_EXT_V1xD /* VFP V1xD (single precision). */
9029 /* Moves and type conversions. */
9030 CE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
9031 CE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
9032 CE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
9033 CE(fmstat, ef1fa10, 0, (), noargs),
9034 CE(fsitos, eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
9035 CE(fuitos, eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
9036 CE(ftosis, ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
9037 CE(ftosizs, ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9038 CE(ftouis, ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
9039 CE(ftouizs, ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
9040 CE(fmrx, ef00a10, 2, (RR, RVC), rd_rn),
9041 CE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
9043 /* Memory operations. */
9044 CE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
9045 CE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
9046 CE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9047 CE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9048 CE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9049 CE(fldmeas, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9050 CE(fldmiax, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9051 CE(fldmfdx, c900b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9052 CE(fldmdbx, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9053 CE(fldmeax, d300b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9054 CE(fstmias, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9055 CE(fstmeas, c800a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
9056 CE(fstmdbs, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9057 CE(fstmfds, d200a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
9058 CE(fstmiax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9059 CE(fstmeax, c800b00, 2, (RRw, VRDLST), vfp_xp_ldstmia),
9060 CE(fstmdbx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9061 CE(fstmfdx, d200b00, 2, (RRw, VRDLST), vfp_xp_ldstmdb),
9063 /* Monadic operations. */
9064 CE(fabss, eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
9065 CE(fnegs, eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
9066 CE(fsqrts, eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
9068 /* Dyadic operations. */
9069 CE(fadds, e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9070 CE(fsubs, e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9071 CE(fmuls, e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9072 CE(fdivs, e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9073 CE(fmacs, e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9074 CE(fmscs, e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9075 CE(fnmuls, e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9076 CE(fnmacs, e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9077 CE(fnmscs, e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
9080 CE(fcmps, eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
9081 CE(fcmpzs, eb50a40, 1, (RVS), vfp_sp_compare_z),
9082 CE(fcmpes, eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
9083 CE(fcmpezs, eb50ac0, 1, (RVS), vfp_sp_compare_z),
9086 #define ARM_VARIANT FPU_VFP_EXT_V1 /* VFP V1 (Double precision). */
9087 /* Moves and type conversions. */
9088 CE(fcpyd, eb00b40, 2, (RVD, RVD), rd_rm),
9089 CE(fcvtds, eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9090 CE(fcvtsd, eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9091 CE(fmdhr, e200b10, 2, (RVD, RR), rn_rd),
9092 CE(fmdlr, e000b10, 2, (RVD, RR), rn_rd),
9093 CE(fmrdh, e300b10, 2, (RR, RVD), rd_rn),
9094 CE(fmrdl, e100b10, 2, (RR, RVD), rd_rn),
9095 CE(fsitod, eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
9096 CE(fuitod, eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
9097 CE(ftosid, ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9098 CE(ftosizd, ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9099 CE(ftouid, ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
9100 CE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
9102 /* Memory operations. */
9103 CE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
9104 CE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
9105 CE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9106 CE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9107 CE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9108 CE(fldmead, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9109 CE(fstmiad, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9110 CE(fstmead, c800b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
9111 CE(fstmdbd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9112 CE(fstmfdd, d200b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
9114 /* Monadic operations. */
9115 CE(fabsd, eb00bc0, 2, (RVD, RVD), rd_rm),
9116 CE(fnegd, eb10b40, 2, (RVD, RVD), rd_rm),
9117 CE(fsqrtd, eb10bc0, 2, (RVD, RVD), rd_rm),
9119 /* Dyadic operations. */
9120 CE(faddd, e300b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9121 CE(fsubd, e300b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9122 CE(fmuld, e200b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9123 CE(fdivd, e800b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9124 CE(fmacd, e000b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9125 CE(fmscd, e100b00, 3, (RVD, RVD, RVD), rd_rn_rm),
9126 CE(fnmuld, e200b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9127 CE(fnmacd, e000b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9128 CE(fnmscd, e100b40, 3, (RVD, RVD, RVD), rd_rn_rm),
9131 CE(fcmpd, eb40b40, 2, (RVD, RVD), rd_rm),
9132 CE(fcmpzd, eb50b40, 1, (RVD), rd),
9133 CE(fcmped, eb40bc0, 2, (RVD, RVD), rd_rm),
9134 CE(fcmpezd, eb50bc0, 1, (RVD), rd),
9137 #define ARM_VARIANT FPU_VFP_EXT_V2
9138 CE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
9139 CE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
9140 CE(fmdrr, c400b10, 3, (RVD, RR, RR), rm_rd_rn),
9141 CE(fmrrd, c500b10, 3, (RR, RR, RVD), rd_rn_rm),
9144 #define ARM_VARIANT ARM_CEXT_XSCALE /* Intel XScale extensions. */
9145 CE(mia, e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9146 CE(miaph, e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9147 CE(miabb, e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9148 CE(miabt, e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9149 CE(miatb, e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9150 CE(miatt, e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
9151 CE(mar, c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
9152 CE(mra, c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
9155 #define ARM_VARIANT ARM_CEXT_IWMMXT /* Intel Wireless MMX technology. */
9156 CE(tandcb, e13f130, 1, (RR), iwmmxt_tandorc),
9157 CE(tandch, e53f130, 1, (RR), iwmmxt_tandorc),
9158 CE(tandcw, e93f130, 1, (RR), iwmmxt_tandorc),
9159 CE(tbcstb, e400010, 2, (RIWR, RR), rn_rd),
9160 CE(tbcsth, e400050, 2, (RIWR, RR), rn_rd),
9161 CE(tbcstw, e400090, 2, (RIWR, RR), rn_rd),
9162 CE(textrcb, e130170, 2, (RR, I7), iwmmxt_textrc),
9163 CE(textrch, e530170, 2, (RR, I7), iwmmxt_textrc),
9164 CE(textrcw, e930170, 2, (RR, I7), iwmmxt_textrc),
9165 CE(textrmub, e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9166 CE(textrmuh, e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9167 CE(textrmuw, e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
9168 CE(textrmsb, e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9169 CE(textrmsh, e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9170 CE(textrmsw, e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
9171 CE(tinsrb, e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9172 CE(tinsrh, e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9173 CE(tinsrw, e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
9174 CE(tmcr, e000110, 2, (RIWC, RR), rn_rd),
9175 CE(tmcrr, c400000, 3, (RIWR, RR, RR), rm_rd_rn),
9176 CE(tmia, e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9177 CE(tmiaph, e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9178 CE(tmiabb, e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9179 CE(tmiabt, e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9180 CE(tmiatb, e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9181 CE(tmiatt, e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
9182 CE(tmovmskb, e100030, 2, (RR, RIWR), rd_rn),
9183 CE(tmovmskh, e500030, 2, (RR, RIWR), rd_rn),
9184 CE(tmovmskw, e900030, 2, (RR, RIWR), rd_rn),
9185 CE(tmrc, e100110, 2, (RR, RIWC), rd_rn),
9186 CE(tmrrc, c500000, 3, (RR, RR, RIWR), rd_rn_rm),
9187 CE(torcb, e13f150, 1, (RR), iwmmxt_tandorc),
9188 CE(torch, e53f150, 1, (RR), iwmmxt_tandorc),
9189 CE(torcw, e93f150, 1, (RR), iwmmxt_tandorc),
9190 CE(waccb, e0001c0, 2, (RIWR, RIWR), rd_rn),
9191 CE(wacch, e4001c0, 2, (RIWR, RIWR), rd_rn),
9192 CE(waccw, e8001c0, 2, (RIWR, RIWR), rd_rn),
9193 CE(waddbss, e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9194 CE(waddb, e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9195 CE(waddbus, e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9196 CE(waddhss, e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9197 CE(waddh, e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9198 CE(waddhus, e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9199 CE(waddwss, eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9200 CE(waddw, e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9201 CE(waddwus, e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9202 CE(waligni, e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
9203 CE(walignr0, e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9204 CE(walignr1, e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9205 CE(walignr2, ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9206 CE(walignr3, eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9207 CE(wand, e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9208 CE(wandn, e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9209 CE(wavg2b, e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9210 CE(wavg2br, e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9211 CE(wavg2h, ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9212 CE(wavg2hr, ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9213 CE(wcmpeqb, e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9214 CE(wcmpeqh, e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9215 CE(wcmpeqw, e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9216 CE(wcmpgtub, e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9217 CE(wcmpgtuh, e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9218 CE(wcmpgtuw, e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9219 CE(wcmpgtsb, e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9220 CE(wcmpgtsh, e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9221 CE(wcmpgtsw, eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9222 CE(wldrb, c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9223 CE(wldrh, c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9224 CE(wldrw, c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9225 CE(wldrd, c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9226 CE(wmacs, e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9227 CE(wmacsz, e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9228 CE(wmacu, e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9229 CE(wmacuz, e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9230 CE(wmadds, ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9231 CE(wmaddu, e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9232 CE(wmaxsb, e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9233 CE(wmaxsh, e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9234 CE(wmaxsw, ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9235 CE(wmaxub, e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9236 CE(wmaxuh, e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9237 CE(wmaxuw, e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9238 CE(wminsb, e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9239 CE(wminsh, e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9240 CE(wminsw, eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9241 CE(wminub, e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9242 CE(wminuh, e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9243 CE(wminuw, e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9244 CE(wmov, e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
9245 CE(wmulsm, e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9246 CE(wmulsl, e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9247 CE(wmulum, e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9248 CE(wmulul, e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9249 CE(wor, e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9250 CE(wpackhss, e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9251 CE(wpackhus, e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9252 CE(wpackwss, eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9253 CE(wpackwus, e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9254 CE(wpackdss, ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9255 CE(wpackdus, ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9256 CE(wrorh, e700040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9257 CE(wrorhg, e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9258 CE(wrorw, eb00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9259 CE(wrorwg, eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9260 CE(wrord, ef00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9261 CE(wrordg, ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9262 CE(wsadb, e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9263 CE(wsadbz, e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9264 CE(wsadh, e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9265 CE(wsadhz, e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9266 CE(wshufh, e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
9267 CE(wsllh, e500040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9268 CE(wsllhg, e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9269 CE(wsllw, e900040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9270 CE(wsllwg, e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9271 CE(wslld, ed00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9272 CE(wslldg, ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9273 CE(wsrah, e400040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9274 CE(wsrahg, e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9275 CE(wsraw, e800040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9276 CE(wsrawg, e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9277 CE(wsrad, ec00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9278 CE(wsradg, ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9279 CE(wsrlh, e600040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9280 CE(wsrlhg, e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9281 CE(wsrlw, ea00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9282 CE(wsrlwg, ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9283 CE(wsrld, ee00040, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9284 CE(wsrldg, ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
9285 CE(wstrb, c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9286 CE(wstrh, c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
9287 CE(wstrw, c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
9288 CE(wstrd, c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
9289 CE(wsubbss, e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9290 CE(wsubb, e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9291 CE(wsubbus, e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9292 CE(wsubhss, e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9293 CE(wsubh, e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9294 CE(wsubhus, e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9295 CE(wsubwss, eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9296 CE(wsubw, e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9297 CE(wsubwus, e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9298 CE(wunpckehub,e0000c0, 2, (RIWR, RIWR), rd_rn),
9299 CE(wunpckehuh,e4000c0, 2, (RIWR, RIWR), rd_rn),
9300 CE(wunpckehuw,e8000c0, 2, (RIWR, RIWR), rd_rn),
9301 CE(wunpckehsb,e2000c0, 2, (RIWR, RIWR), rd_rn),
9302 CE(wunpckehsh,e6000c0, 2, (RIWR, RIWR), rd_rn),
9303 CE(wunpckehsw,ea000c0, 2, (RIWR, RIWR), rd_rn),
9304 CE(wunpckihb, e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9305 CE(wunpckihh, e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9306 CE(wunpckihw, e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9307 CE(wunpckelub,e0000e0, 2, (RIWR, RIWR), rd_rn),
9308 CE(wunpckeluh,e4000e0, 2, (RIWR, RIWR), rd_rn),
9309 CE(wunpckeluw,e8000e0, 2, (RIWR, RIWR), rd_rn),
9310 CE(wunpckelsb,e2000e0, 2, (RIWR, RIWR), rd_rn),
9311 CE(wunpckelsh,e6000e0, 2, (RIWR, RIWR), rd_rn),
9312 CE(wunpckelsw,ea000e0, 2, (RIWR, RIWR), rd_rn),
9313 CE(wunpckilb, e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9314 CE(wunpckilh, e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9315 CE(wunpckilw, e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9316 CE(wxor, e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
9317 CE(wzero, e300000, 1, (RIWR), iwmmxt_wzero),
9320 #define ARM_VARIANT ARM_CEXT_MAVERICK /* Cirrus Maverick instructions. */
9321 CE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
9322 CE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
9323 CE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
9324 CE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
9325 CE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
9326 CE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
9327 CE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
9328 CE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
9329 CE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
9330 CE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
9331 CE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
9332 CE(cfmvrdl, e100410, 2, (RR, RMD), rd_rn),
9333 CE(cfmvdhr, e000430, 2, (RMD, RR), rn_rd),
9334 CE(cfmvrdh, e100430, 2, (RR, RMD), rd_rn),
9335 CE(cfmv64lr, e000510, 2, (RMDX, RR), rn_rd),
9336 CE(cfmvr64l, e100510, 2, (RR, RMDX), rd_rn),
9337 CE(cfmv64hr, e000530, 2, (RMDX, RR), rn_rd),
9338 CE(cfmvr64h, e100530, 2, (RR, RMDX), rd_rn),
9339 CE(cfmval32, e200440, 2, (RMAX, RMFX), rd_rn),
9340 CE(cfmv32al, e100440, 2, (RMFX, RMAX), rd_rn),
9341 CE(cfmvam32, e200460, 2, (RMAX, RMFX), rd_rn),
9342 CE(cfmv32am, e100460, 2, (RMFX, RMAX), rd_rn),
9343 CE(cfmvah32, e200480, 2, (RMAX, RMFX), rd_rn),
9344 CE(cfmv32ah, e100480, 2, (RMFX, RMAX), rd_rn),
9345 CE(cfmva32, e2004a0, 2, (RMAX, RMFX), rd_rn),
9346 CE(cfmv32a, e1004a0, 2, (RMFX, RMAX), rd_rn),
9347 CE(cfmva64, e2004c0, 2, (RMAX, RMDX), rd_rn),
9348 CE(cfmv64a, e1004c0, 2, (RMDX, RMAX), rd_rn),
9349 CE(cfmvsc32, e2004e0, 2, (RMDS, RMDX), mav_dspsc),
9350 CE(cfmv32sc, e1004e0, 2, (RMDX, RMDS), rd),
9351 CE(cfcpys, e000400, 2, (RMF, RMF), rd_rn),
9352 CE(cfcpyd, e000420, 2, (RMD, RMD), rd_rn),
9353 CE(cfcvtsd, e000460, 2, (RMD, RMF), rd_rn),
9354 CE(cfcvtds, e000440, 2, (RMF, RMD), rd_rn),
9355 CE(cfcvt32s, e000480, 2, (RMF, RMFX), rd_rn),
9356 CE(cfcvt32d, e0004a0, 2, (RMD, RMFX), rd_rn),
9357 CE(cfcvt64s, e0004c0, 2, (RMF, RMDX), rd_rn),
9358 CE(cfcvt64d, e0004e0, 2, (RMD, RMDX), rd_rn),
9359 CE(cfcvts32, e100580, 2, (RMFX, RMF), rd_rn),
9360 CE(cfcvtd32, e1005a0, 2, (RMFX, RMD), rd_rn),
9361 CE(cftruncs32,e1005c0, 2, (RMFX, RMF), rd_rn),
9362 CE(cftruncd32,e1005e0, 2, (RMFX, RMD), rd_rn),
9363 CE(cfrshl32, e000550, 3, (RMFX, RMFX, RR), mav_triple),
9364 CE(cfrshl64, e000570, 3, (RMDX, RMDX, RR), mav_triple),
9365 CE(cfsh32, e000500, 3, (RMFX, RMFX, I63s), mav_shift),
9366 CE(cfsh64, e200500, 3, (RMDX, RMDX, I63s), mav_shift),
9367 CE(cfcmps, e100490, 3, (RR, RMF, RMF), rd_rn_rm),
9368 CE(cfcmpd, e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
9369 CE(cfcmp32, e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
9370 CE(cfcmp64, e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
9371 CE(cfabss, e300400, 2, (RMF, RMF), rd_rn),
9372 CE(cfabsd, e300420, 2, (RMD, RMD), rd_rn),
9373 CE(cfnegs, e300440, 2, (RMF, RMF), rd_rn),
9374 CE(cfnegd, e300460, 2, (RMD, RMD), rd_rn),
9375 CE(cfadds, e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
9376 CE(cfaddd, e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
9377 CE(cfsubs, e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
9378 CE(cfsubd, e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
9379 CE(cfmuls, e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
9380 CE(cfmuld, e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
9381 CE(cfabs32, e300500, 2, (RMFX, RMFX), rd_rn),
9382 CE(cfabs64, e300520, 2, (RMDX, RMDX), rd_rn),
9383 CE(cfneg32, e300540, 2, (RMFX, RMFX), rd_rn),
9384 CE(cfneg64, e300560, 2, (RMDX, RMDX), rd_rn),
9385 CE(cfadd32, e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9386 CE(cfadd64, e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9387 CE(cfsub32, e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9388 CE(cfsub64, e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9389 CE(cfmul32, e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9390 CE(cfmul64, e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
9391 CE(cfmac32, e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9392 CE(cfmsc32, e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
9393 CE(cfmadd32, e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9394 CE(cfmsub32, e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
9395 CE(cfmadda32, e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9396 CE(cfmsuba32, e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
9399 #undef THUMB_VARIANT
9419 /* MD interface: bits in the object file. */
9421 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
9422 for use in the a.out file, and stores them in the array pointed to by buf.
9423 This knows about the endian-ness of the target machine and does
9424 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
9425 2 (short) and 4 (long) Floating numbers are put out as a series of
9426 LITTLENUMS (shorts, here at least). */
9429 md_number_to_chars (char * buf, valueT val, int n)
9431 if (target_big_endian)
9432 number_to_chars_bigendian (buf, val, n);
9434 number_to_chars_littleendian (buf, val, n);
9438 md_chars_to_number (char * buf, int n)
9441 unsigned char * where = (unsigned char *) buf;
9443 if (target_big_endian)
9448 result |= (*where++ & 255);
9456 result |= (where[n] & 255);
9463 /* MD interface: Sections. */
9466 md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
9467 segT segtype ATTRIBUTE_UNUSED)
9469 as_fatal (_("md_estimate_size_before_relax\n"));
9473 /* Round up a section size to the appropriate boundary. */
9476 md_section_align (segT segment ATTRIBUTE_UNUSED,
9482 /* Round all sects to multiple of 4. */
9483 return (size + 3) & ~3;
9487 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
9488 of an rs_align_code fragment. */
9491 arm_handle_align (fragS * fragP)
9493 static char const arm_noop[4] = { 0x00, 0x00, 0xa0, 0xe1 };
9494 static char const thumb_noop[2] = { 0xc0, 0x46 };
9495 static char const arm_bigend_noop[4] = { 0xe1, 0xa0, 0x00, 0x00 };
9496 static char const thumb_bigend_noop[2] = { 0x46, 0xc0 };
9498 int bytes, fix, noop_size;
9502 if (fragP->fr_type != rs_align_code)
9505 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
9506 p = fragP->fr_literal + fragP->fr_fix;
9509 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
9510 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
9512 if (fragP->tc_frag_data)
9514 if (target_big_endian)
9515 noop = thumb_bigend_noop;
9518 noop_size = sizeof (thumb_noop);
9522 if (target_big_endian)
9523 noop = arm_bigend_noop;
9526 noop_size = sizeof (arm_noop);
9529 if (bytes & (noop_size - 1))
9531 fix = bytes & (noop_size - 1);
9537 while (bytes >= noop_size)
9539 memcpy (p, noop, noop_size);
9545 fragP->fr_fix += fix;
9546 fragP->fr_var = noop_size;
9549 /* Called from md_do_align. Used to create an alignment
9550 frag in a code section. */
9553 arm_frag_align_code (int n, int max)
9557 /* We assume that there will never be a requirement
9558 to support alignments greater than 32 bytes. */
9559 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
9560 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
9562 p = frag_var (rs_align_code,
9563 MAX_MEM_FOR_RS_ALIGN_CODE,
9565 (relax_substateT) max,
9572 /* Perform target specific initialisation of a frag. */
9575 arm_init_frag (fragS * fragP)
9577 /* Record whether this frag is in an ARM or a THUMB area. */
9578 fragP->tc_frag_data = thumb_mode;
9582 /* When we change sections we need to issue a new mapping symbol. */
9585 arm_elf_change_section (void)
9588 segment_info_type *seginfo;
9590 /* Link an unlinked unwind index table section to the .text section. */
9591 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
9592 && elf_linked_to_section (now_seg) == NULL)
9593 elf_linked_to_section (now_seg) = text_section;
9595 if (!SEG_NORMAL (now_seg))
9598 flags = bfd_get_section_flags (stdoutput, now_seg);
9600 /* We can ignore sections that only contain debug info. */
9601 if ((flags & SEC_ALLOC) == 0)
9604 seginfo = seg_info (now_seg);
9605 mapstate = seginfo->tc_segment_info_data.mapstate;
9606 marked_pr_dependency = seginfo->tc_segment_info_data.marked_pr_dependency;
9610 arm_elf_section_type (const char * str, size_t len)
9612 if (len == 5 && strncmp (str, "exidx", 5) == 0)
9613 return SHT_ARM_EXIDX;
9618 /* Code to deal with unwinding tables. */
9620 static void add_unwind_adjustsp (offsetT);
9622 /* Cenerate and deferred unwind frame offset. */
9625 flush_pending_unwind (void)
9629 offset = unwind.pending_offset;
9630 unwind.pending_offset = 0;
9632 add_unwind_adjustsp (offset);
9635 /* Add an opcode to this list for this function. Two-byte opcodes should
9636 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
9640 add_unwind_opcode (valueT op, int length)
9642 /* Add any deferred stack adjustment. */
9643 if (unwind.pending_offset)
9644 flush_pending_unwind ();
9646 unwind.sp_restored = 0;
9648 if (unwind.opcode_count + length > unwind.opcode_alloc)
9650 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
9652 unwind.opcodes = xrealloc (unwind.opcodes,
9653 unwind.opcode_alloc);
9655 unwind.opcodes = xmalloc (unwind.opcode_alloc);
9660 unwind.opcodes[unwind.opcode_count] = op & 0xff;
9662 unwind.opcode_count++;
9666 /* Add unwind opcodes to adjust the stack pointer. */
9669 add_unwind_adjustsp (offsetT offset)
9675 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
9680 /* Long form: 0xb2, uleb128. */
9681 /* This might not fit in a word so add the individual bytes,
9682 remembering the list is built in reverse order. */
9683 o = (valueT) ((offset - 0x204) >> 2);
9685 add_unwind_opcode (0, 1);
9687 /* Calculate the uleb128 encoding of the offset. */
9691 bytes[n] = o & 0x7f;
9699 add_unwind_opcode (bytes[n - 1], 1);
9700 add_unwind_opcode (0xb2, 1);
9702 else if (offset > 0x100)
9704 /* Two short opcodes. */
9705 add_unwind_opcode (0x3f, 1);
9706 op = (offset - 0x104) >> 2;
9707 add_unwind_opcode (op, 1);
9709 else if (offset > 0)
9712 op = (offset - 4) >> 2;
9713 add_unwind_opcode (op, 1);
9715 else if (offset < 0)
9718 while (offset > 0x100)
9720 add_unwind_opcode (0x7f, 1);
9723 op = ((offset - 4) >> 2) | 0x40;
9724 add_unwind_opcode (op, 1);
9728 /* Finish the list of unwind opcodes for this function. */
9730 finish_unwind_opcodes (void)
9736 /* Adjust sp as neccessary. */
9737 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
9738 flush_pending_unwind ();
9740 /* After restoring sp from the frame pointer. */
9741 op = 0x90 | unwind.fp_reg;
9742 add_unwind_opcode (op, 1);
9745 flush_pending_unwind ();
9749 /* Start an exception table entry. If idx is nonzero this is an index table
9753 start_unwind_section (const segT text_seg, int idx)
9755 const char * text_name;
9756 const char * prefix;
9757 const char * prefix_once;
9758 const char * group_name;
9762 size_t sec_name_len;
9769 prefix = ELF_STRING_ARM_unwind;
9770 prefix_once = ELF_STRING_ARM_unwind_once;
9771 type = SHT_ARM_EXIDX;
9775 prefix = ELF_STRING_ARM_unwind_info;
9776 prefix_once = ELF_STRING_ARM_unwind_info_once;
9777 type = SHT_PROGBITS;
9780 text_name = segment_name (text_seg);
9781 if (streq (text_name, ".text"))
9784 if (strncmp (text_name, ".gnu.linkonce.t.",
9785 strlen (".gnu.linkonce.t.")) == 0)
9787 prefix = prefix_once;
9788 text_name += strlen (".gnu.linkonce.t.");
9791 prefix_len = strlen (prefix);
9792 text_len = strlen (text_name);
9793 sec_name_len = prefix_len + text_len;
9794 sec_name = xmalloc (sec_name_len + 1);
9795 memcpy (sec_name, prefix, prefix_len);
9796 memcpy (sec_name + prefix_len, text_name, text_len);
9797 sec_name[prefix_len + text_len] = '\0';
9803 /* Handle COMDAT group. */
9804 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
9806 group_name = elf_group_name (text_seg);
9807 if (group_name == NULL)
9809 as_bad ("Group section `%s' has no group signature",
9810 segment_name (text_seg));
9811 ignore_rest_of_line ();
9818 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
9820 /* Set the setion link for index tables. */
9822 elf_linked_to_section (now_seg) = text_seg;
9826 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
9827 personality routine data. Returns zero, or the index table value for
9828 and inline entry. */
9831 create_unwind_entry (int have_data)
9836 /* The current word of data. */
9838 /* The number of bytes left in this word. */
9841 finish_unwind_opcodes ();
9843 /* Remember the current text section. */
9844 unwind.saved_seg = now_seg;
9845 unwind.saved_subseg = now_subseg;
9847 start_unwind_section (now_seg, 0);
9849 if (unwind.personality_routine == NULL)
9851 if (unwind.personality_index == -2)
9854 as_bad (_("handerdata in cantunwind frame"));
9855 return 1; /* EXIDX_CANTUNWIND. */
9858 /* Use a default personality routine if none is specified. */
9859 if (unwind.personality_index == -1)
9861 if (unwind.opcode_count > 3)
9862 unwind.personality_index = 1;
9864 unwind.personality_index = 0;
9867 /* Space for the personality routine entry. */
9868 if (unwind.personality_index == 0)
9870 if (unwind.opcode_count > 3)
9871 as_bad (_("too many unwind opcodes for personality routine 0"));
9875 /* All the data is inline in the index table. */
9878 while (unwind.opcode_count > 0)
9880 unwind.opcode_count--;
9881 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9885 /* Pad with "finish" opcodes. */
9887 data = (data << 8) | 0xb0;
9894 /* We get two opcodes "free" in the first word. */
9895 size = unwind.opcode_count - 2;
9898 /* An extra byte is required for the opcode count. */
9899 size = unwind.opcode_count + 1;
9901 size = (size + 3) >> 2;
9903 as_bad (_("too many unwind opcodes"));
9905 frag_align (2, 0, 0);
9906 record_alignment (now_seg, 2);
9907 unwind.table_entry = expr_build_dot ();
9909 /* Allocate the table entry. */
9910 ptr = frag_more ((size << 2) + 4);
9911 where = frag_now_fix () - ((size << 2) + 4);
9913 switch (unwind.personality_index)
9916 /* ??? Should this be a PLT generating relocation? */
9917 /* Custom personality routine. */
9918 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
9919 BFD_RELOC_ARM_PREL31);
9924 /* Set the first byte to the number of additional words. */
9929 /* ABI defined personality routines. */
9931 /* Three opcodes bytes are packed into the first word. */
9938 /* The size and first two opcode bytes go in the first word. */
9939 data = ((0x80 + unwind.personality_index) << 8) | size;
9944 /* Should never happen. */
9948 /* Pack the opcodes into words (MSB first), reversing the list at the same
9950 while (unwind.opcode_count > 0)
9954 md_number_to_chars (ptr, data, 4);
9959 unwind.opcode_count--;
9961 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
9964 /* Finish off the last word. */
9967 /* Pad with "finish" opcodes. */
9969 data = (data << 8) | 0xb0;
9971 md_number_to_chars (ptr, data, 4);
9976 /* Add an empty descriptor if there is no user-specified data. */
9977 ptr = frag_more (4);
9978 md_number_to_chars (ptr, 0, 4);
9984 /* Convert REGNAME to a DWARF-2 register number. */
9987 tc_arm_regname_to_dw2regnum (const char *regname)
9989 int reg = arm_reg_parse ((char **) ®name, REG_TYPE_RN);
9997 /* Initialize the DWARF-2 unwind information for this procedure. */
10000 tc_arm_frame_initial_instructions (void)
10002 cfi_add_CFA_def_cfa (REG_SP, 0);
10004 #endif /* OBJ_ELF */
10007 /* MD interface: Symbol and relocation handling. */
10009 /* Return the address within the segment that a PC-relative fixup is
10010 relative to. For ARM, PC-relative fixups applied to instructions
10011 are generally relative to the location of the fixup plus 8 bytes.
10012 Thumb branches are offset by 4, and Thumb loads relative to PC
10013 require special handling. */
10016 md_pcrel_from_section (fixS * fixP, segT seg)
10018 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
10020 /* If this is pc-relative and we are going to emit a relocation
10021 then we just want to put out any pipeline compensation that the linker
10022 will need. Otherwise we want to use the calculated base. */
10024 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
10025 || arm_force_relocation (fixP)))
10028 switch (fixP->fx_r_type)
10030 /* PC relative addressing on the Thumb is slightly odd as the
10031 bottom two bits of the PC are forced to zero for the
10032 calculation. This happens *after* application of the
10033 pipeline offset. However, Thumb adrl already adjusts for
10034 this, so we need not do it again. */
10035 case BFD_RELOC_ARM_THUMB_ADD:
10038 case BFD_RELOC_ARM_THUMB_OFFSET:
10039 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10040 case BFD_RELOC_ARM_T32_ADD_PC12:
10041 return (base + 4) & ~3;
10043 /* Thumb branches are simply offset by +4. */
10044 case BFD_RELOC_THUMB_PCREL_BRANCH7:
10045 case BFD_RELOC_THUMB_PCREL_BRANCH9:
10046 case BFD_RELOC_THUMB_PCREL_BRANCH12:
10047 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10048 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10049 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10050 case BFD_RELOC_THUMB_PCREL_BLX:
10053 /* ARM mode branches are offset by +8. However, the Windows CE
10054 loader expects the relocation not to take this into account. */
10055 case BFD_RELOC_ARM_PCREL_BRANCH:
10056 case BFD_RELOC_ARM_PCREL_BLX:
10057 case BFD_RELOC_ARM_PLT32:
10064 /* ARM mode loads relative to PC are also offset by +8. Unlike
10065 branches, the Windows CE loader *does* expect the relocation
10066 to take this into account. */
10067 case BFD_RELOC_ARM_OFFSET_IMM:
10068 case BFD_RELOC_ARM_OFFSET_IMM8:
10069 case BFD_RELOC_ARM_HWLITERAL:
10070 case BFD_RELOC_ARM_LITERAL:
10071 case BFD_RELOC_ARM_CP_OFF_IMM:
10075 /* Other PC-relative relocations are un-offset. */
10081 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
10082 Otherwise we have no need to default values of symbols. */
10085 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
10088 if (name[0] == '_' && name[1] == 'G'
10089 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
10093 if (symbol_find (name))
10094 as_bad ("GOT already in the symbol table");
10096 GOT_symbol = symbol_new (name, undefined_section,
10097 (valueT) 0, & zero_address_frag);
10107 /* Subroutine of md_apply_fix. Check to see if an immediate can be
10108 computed as two separate immediate values, added together. We
10109 already know that this value cannot be computed by just one ARM
10112 static unsigned int
10113 validate_immediate_twopart (unsigned int val,
10114 unsigned int * highpart)
10119 for (i = 0; i < 32; i += 2)
10120 if (((a = rotate_left (val, i)) & 0xff) != 0)
10126 * highpart = (a >> 8) | ((i + 24) << 7);
10128 else if (a & 0xff0000)
10130 if (a & 0xff000000)
10132 * highpart = (a >> 16) | ((i + 16) << 7);
10136 assert (a & 0xff000000);
10137 * highpart = (a >> 24) | ((i + 8) << 7);
10140 return (a & 0xff) | (i << 7);
10147 validate_offset_imm (unsigned int val, int hwse)
10149 if ((hwse && val > 255) || val > 4095)
10154 /* Subroutine of md_apply_fix. Do those data_ops which can take a
10155 negative immediate constant by altering the instruction. A bit of
10160 by inverting the second operand, and
10163 by negating the second operand. */
10166 negate_data_op (unsigned long * instruction,
10167 unsigned long value)
10170 unsigned long negated, inverted;
10172 negated = encode_arm_immediate (-value);
10173 inverted = encode_arm_immediate (~value);
10175 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
10178 /* First negates. */
10179 case OPCODE_SUB: /* ADD <-> SUB */
10180 new_inst = OPCODE_ADD;
10185 new_inst = OPCODE_SUB;
10189 case OPCODE_CMP: /* CMP <-> CMN */
10190 new_inst = OPCODE_CMN;
10195 new_inst = OPCODE_CMP;
10199 /* Now Inverted ops. */
10200 case OPCODE_MOV: /* MOV <-> MVN */
10201 new_inst = OPCODE_MVN;
10206 new_inst = OPCODE_MOV;
10210 case OPCODE_AND: /* AND <-> BIC */
10211 new_inst = OPCODE_BIC;
10216 new_inst = OPCODE_AND;
10220 case OPCODE_ADC: /* ADC <-> SBC */
10221 new_inst = OPCODE_SBC;
10226 new_inst = OPCODE_ADC;
10230 /* We cannot do anything. */
10235 if (value == (unsigned) FAIL)
10238 *instruction &= OPCODE_MASK;
10239 *instruction |= new_inst << DATA_OP_SHIFT;
10244 md_apply_fix (fixS * fixP,
10248 offsetT value = * valP;
10250 unsigned int newimm;
10251 unsigned long temp;
10253 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
10255 assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
10257 /* Note whether this will delete the relocation. */
10258 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
10261 /* On a 64-bit host, silently truncate 'value' to 32 bits for
10262 consistency with the behavior on 32-bit hosts. Remember value
10264 value &= 0xffffffff;
10265 value ^= 0x80000000;
10266 value -= 0x80000000;
10269 fixP->fx_addnumber = value;
10271 /* Same treatment for fixP->fx_offset. */
10272 fixP->fx_offset &= 0xffffffff;
10273 fixP->fx_offset ^= 0x80000000;
10274 fixP->fx_offset -= 0x80000000;
10276 switch (fixP->fx_r_type)
10278 case BFD_RELOC_NONE:
10279 /* This will need to go in the object file. */
10283 case BFD_RELOC_ARM_IMMEDIATE:
10284 /* We claim that this fixup has been processed here,
10285 even if in fact we generate an error because we do
10286 not have a reloc for it, so tc_gen_reloc will reject it. */
10290 && ! S_IS_DEFINED (fixP->fx_addsy))
10292 as_bad_where (fixP->fx_file, fixP->fx_line,
10293 _("undefined symbol %s used as an immediate value"),
10294 S_GET_NAME (fixP->fx_addsy));
10298 newimm = encode_arm_immediate (value);
10299 temp = md_chars_to_number (buf, INSN_SIZE);
10301 /* If the instruction will fail, see if we can fix things up by
10302 changing the opcode. */
10303 if (newimm == (unsigned int) FAIL
10304 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
10306 as_bad_where (fixP->fx_file, fixP->fx_line,
10307 _("invalid constant (%lx) after fixup"),
10308 (unsigned long) value);
10312 newimm |= (temp & 0xfffff000);
10313 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10316 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
10318 unsigned int highpart = 0;
10319 unsigned int newinsn = 0xe1a00000; /* nop. */
10321 newimm = encode_arm_immediate (value);
10322 temp = md_chars_to_number (buf, INSN_SIZE);
10324 /* If the instruction will fail, see if we can fix things up by
10325 changing the opcode. */
10326 if (newimm == (unsigned int) FAIL
10327 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
10329 /* No ? OK - try using two ADD instructions to generate
10331 newimm = validate_immediate_twopart (value, & highpart);
10333 /* Yes - then make sure that the second instruction is
10335 if (newimm != (unsigned int) FAIL)
10337 /* Still No ? Try using a negated value. */
10338 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
10339 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
10340 /* Otherwise - give up. */
10343 as_bad_where (fixP->fx_file, fixP->fx_line,
10344 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
10349 /* Replace the first operand in the 2nd instruction (which
10350 is the PC) with the destination register. We have
10351 already added in the PC in the first instruction and we
10352 do not want to do it again. */
10353 newinsn &= ~ 0xf0000;
10354 newinsn |= ((newinsn & 0x0f000) << 4);
10357 newimm |= (temp & 0xfffff000);
10358 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
10360 highpart |= (newinsn & 0xfffff000);
10361 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
10365 case BFD_RELOC_ARM_OFFSET_IMM:
10366 case BFD_RELOC_ARM_LITERAL:
10372 if (validate_offset_imm (value, 0) == FAIL)
10374 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
10375 as_bad_where (fixP->fx_file, fixP->fx_line,
10376 _("invalid literal constant: pool needs to be closer"));
10378 as_bad_where (fixP->fx_file, fixP->fx_line,
10379 _("bad immediate value for offset (%ld)"),
10384 newval = md_chars_to_number (buf, INSN_SIZE);
10385 newval &= 0xff7ff000;
10386 newval |= value | (sign ? INDEX_UP : 0);
10387 md_number_to_chars (buf, newval, INSN_SIZE);
10390 case BFD_RELOC_ARM_OFFSET_IMM8:
10391 case BFD_RELOC_ARM_HWLITERAL:
10397 if (validate_offset_imm (value, 1) == FAIL)
10399 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
10400 as_bad_where (fixP->fx_file, fixP->fx_line,
10401 _("invalid literal constant: pool needs to be closer"));
10403 as_bad (_("bad immediate value for half-word offset (%ld)"),
10408 newval = md_chars_to_number (buf, INSN_SIZE);
10409 newval &= 0xff7ff0f0;
10410 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
10411 md_number_to_chars (buf, newval, INSN_SIZE);
10414 case BFD_RELOC_ARM_T32_OFFSET_U8:
10415 if (value < 0 || value > 1020 || value % 4 != 0)
10416 as_bad_where (fixP->fx_file, fixP->fx_line,
10417 _("bad immediate value for offset (%ld)"), (long) value);
10420 newval = md_chars_to_number (buf+2, THUMB_SIZE);
10422 md_number_to_chars (buf+2, newval, THUMB_SIZE);
10425 case BFD_RELOC_ARM_T32_OFFSET_IMM:
10426 /* This is a complicated relocation used for all varieties of Thumb32
10427 load/store instruction with immediate offset:
10429 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
10430 *4, optional writeback(W)
10431 (doubleword load/store)
10433 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
10434 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
10435 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
10436 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
10437 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
10439 Uppercase letters indicate bits that are already encoded at
10440 this point. Lowercase letters are our problem. For the
10441 second block of instructions, the secondary opcode nybble
10442 (bits 8..11) is present, and bit 23 is zero, even if this is
10443 a PC-relative operation. */
10444 newval = md_chars_to_number (buf, THUMB_SIZE);
10446 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
10448 if ((newval & 0xf0000000) == 0xe0000000)
10450 /* Doubleword load/store: 8-bit offset, scaled by 4. */
10452 newval |= (1 << 23);
10455 if (value % 4 != 0)
10457 as_bad_where (fixP->fx_file, fixP->fx_line,
10458 _("offset not a multiple of 4"));
10464 as_bad_where (fixP->fx_file, fixP->fx_line,
10465 _("offset out of range"));
10470 else if ((newval & 0x000f0000) == 0x000f0000)
10472 /* PC-relative, 12-bit offset. */
10474 newval |= (1 << 23);
10477 if (value >= 0xfff)
10479 as_bad_where (fixP->fx_file, fixP->fx_line,
10480 _("offset out of range"));
10485 else if ((newval & 0x00000100) == 0x00000100)
10487 /* Writeback: 8-bit, +/- offset. */
10489 newval |= (1 << 9);
10494 as_bad_where (fixP->fx_file, fixP->fx_line,
10495 _("offset out of range"));
10500 else if ((newval & 0x00000f00) == 0x00000e00)
10502 /* T-instruction: positive 8-bit offset. */
10503 if (value < 0 || value >= 0xff)
10505 as_bad_where (fixP->fx_file, fixP->fx_line,
10506 _("offset out of range"));
10514 /* Positive 12-bit or negative 8-bit offset. */
10518 newval |= (1 << 23);
10528 as_bad_where (fixP->fx_file, fixP->fx_line,
10529 _("offset out of range"));
10536 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
10537 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
10540 case BFD_RELOC_ARM_SHIFT_IMM:
10541 newval = md_chars_to_number (buf, INSN_SIZE);
10542 if (((unsigned long) value) > 32
10544 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
10546 as_bad_where (fixP->fx_file, fixP->fx_line,
10547 _("shift expression is too large"));
10552 /* Shifts of zero must be done as lsl. */
10554 else if (value == 32)
10556 newval &= 0xfffff07f;
10557 newval |= (value & 0x1f) << 7;
10558 md_number_to_chars (buf, newval, INSN_SIZE);
10561 case BFD_RELOC_ARM_T32_IMMEDIATE:
10562 case BFD_RELOC_ARM_T32_IMM12:
10563 case BFD_RELOC_ARM_T32_ADD_PC12:
10564 /* We claim that this fixup has been processed here,
10565 even if in fact we generate an error because we do
10566 not have a reloc for it, so tc_gen_reloc will reject it. */
10570 && ! S_IS_DEFINED (fixP->fx_addsy))
10572 as_bad_where (fixP->fx_file, fixP->fx_line,
10573 _("undefined symbol %s used as an immediate value"),
10574 S_GET_NAME (fixP->fx_addsy));
10578 newval = md_chars_to_number (buf, THUMB_SIZE);
10580 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
10582 /* FUTURE: Implement analogue of negate_data_op for T32. */
10583 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE)
10584 newimm = encode_thumb32_immediate (value);
10587 /* 12 bit immediate for addw/subw. */
10591 newval ^= 0x00a00000;
10594 newimm = (unsigned int) FAIL;
10599 if (newimm == (unsigned int)FAIL)
10601 as_bad_where (fixP->fx_file, fixP->fx_line,
10602 _("invalid constant (%lx) after fixup"),
10603 (unsigned long) value);
10607 newval |= (newimm & 0x800) << 15;
10608 newval |= (newimm & 0x700) << 4;
10609 newval |= (newimm & 0x0ff);
10611 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
10612 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
10615 case BFD_RELOC_ARM_SMI:
10616 if (((unsigned long) value) > 0xffff)
10617 as_bad_where (fixP->fx_file, fixP->fx_line,
10618 _("invalid smi expression"));
10619 newval = md_chars_to_number (buf, INSN_SIZE);
10620 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
10621 md_number_to_chars (buf, newval, INSN_SIZE);
10624 case BFD_RELOC_ARM_SWI:
10625 if (fixP->tc_fix_data != 0)
10627 if (((unsigned long) value) > 0xff)
10628 as_bad_where (fixP->fx_file, fixP->fx_line,
10629 _("invalid swi expression"));
10630 newval = md_chars_to_number (buf, THUMB_SIZE);
10632 md_number_to_chars (buf, newval, THUMB_SIZE);
10636 if (((unsigned long) value) > 0x00ffffff)
10637 as_bad_where (fixP->fx_file, fixP->fx_line,
10638 _("invalid swi expression"));
10639 newval = md_chars_to_number (buf, INSN_SIZE);
10641 md_number_to_chars (buf, newval, INSN_SIZE);
10645 case BFD_RELOC_ARM_MULTI:
10646 if (((unsigned long) value) > 0xffff)
10647 as_bad_where (fixP->fx_file, fixP->fx_line,
10648 _("invalid expression in load/store multiple"));
10649 newval = value | md_chars_to_number (buf, INSN_SIZE);
10650 md_number_to_chars (buf, newval, INSN_SIZE);
10653 case BFD_RELOC_ARM_PCREL_BRANCH:
10655 case BFD_RELOC_ARM_PLT32:
10658 /* We are going to store value (shifted right by two) in the
10659 instruction, in a 24 bit, signed field. Bits 0 and 1 must be
10660 clear, and bits 26 through 32 either all clear or all set. */
10661 if (value & 0x00000003)
10662 as_bad_where (fixP->fx_file, fixP->fx_line,
10663 _("misaligned branch destination"));
10664 if ((value & (offsetT)0xfe000000) != (offsetT)0
10665 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
10666 as_bad_where (fixP->fx_file, fixP->fx_line,
10667 _("branch out of range"));
10669 if (fixP->fx_done || !seg->use_rela_p)
10671 newval = md_chars_to_number (buf, INSN_SIZE);
10672 newval |= (value >> 2) & 0x00ffffff;
10673 md_number_to_chars (buf, newval, INSN_SIZE);
10677 case BFD_RELOC_ARM_PCREL_BLX:
10678 /* BLX allows bit 1 to be set in the branch destination, since
10679 it targets a Thumb instruction which is only required to be
10680 aligned modulo 2. Other constraints are as for B/BL. */
10681 if (value & 0x00000001)
10682 as_bad_where (fixP->fx_file, fixP->fx_line,
10683 _("misaligned BLX destination"));
10684 if ((value & (offsetT)0xfe000000) != (offsetT)0
10685 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
10686 as_bad_where (fixP->fx_file, fixP->fx_line,
10687 _("branch out of range"));
10689 if (fixP->fx_done || !seg->use_rela_p)
10692 hbit = (value >> 1) & 1;
10693 value = (value >> 2) & 0x00ffffff;
10695 newval = md_chars_to_number (buf, INSN_SIZE);
10696 newval |= value | hbit << 24;
10697 md_number_to_chars (buf, newval, INSN_SIZE);
10701 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CZB */
10702 /* CZB can only branch forward. */
10704 as_bad_where (fixP->fx_file, fixP->fx_line,
10705 _("branch out of range"));
10707 if (fixP->fx_done || !seg->use_rela_p)
10709 newval = md_chars_to_number (buf, THUMB_SIZE);
10710 newval |= ((value & 0x2e) << 2) | ((value & 0x40) << 3);
10711 md_number_to_chars (buf, newval, THUMB_SIZE);
10715 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
10716 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
10717 as_bad_where (fixP->fx_file, fixP->fx_line,
10718 _("branch out of range"));
10720 if (fixP->fx_done || !seg->use_rela_p)
10722 newval = md_chars_to_number (buf, THUMB_SIZE);
10723 newval |= (value & 0x1ff) >> 1;
10724 md_number_to_chars (buf, newval, THUMB_SIZE);
10728 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
10729 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
10730 as_bad_where (fixP->fx_file, fixP->fx_line,
10731 _("branch out of range"));
10733 if (fixP->fx_done || !seg->use_rela_p)
10735 newval = md_chars_to_number (buf, THUMB_SIZE);
10736 newval |= (value & 0xfff) >> 1;
10737 md_number_to_chars (buf, newval, THUMB_SIZE);
10741 case BFD_RELOC_THUMB_PCREL_BRANCH20:
10742 if ((value & ~0x1fffff) && ((value & ~0x1fffff) != ~0x1fffff))
10743 as_bad_where (fixP->fx_file, fixP->fx_line,
10744 _("conditional branch out of range"));
10746 if (fixP->fx_done || !seg->use_rela_p)
10749 addressT S, J1, J2, lo, hi;
10751 S = (value & 0x00100000) >> 20;
10752 J2 = (value & 0x00080000) >> 19;
10753 J1 = (value & 0x00040000) >> 18;
10754 hi = (value & 0x0003f000) >> 12;
10755 lo = (value & 0x00000ffe) >> 1;
10757 newval = md_chars_to_number (buf, THUMB_SIZE);
10758 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10759 newval |= (S << 10) | hi;
10760 newval2 |= (J1 << 13) | (J2 << 11) | lo;
10761 md_number_to_chars (buf, newval, THUMB_SIZE);
10762 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10766 case BFD_RELOC_THUMB_PCREL_BLX:
10767 case BFD_RELOC_THUMB_PCREL_BRANCH23:
10768 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
10769 as_bad_where (fixP->fx_file, fixP->fx_line,
10770 _("branch out of range"));
10772 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
10773 /* For a BLX instruction, make sure that the relocation is rounded up
10774 to a word boundary. This follows the semantics of the instruction
10775 which specifies that bit 1 of the target address will come from bit
10776 1 of the base address. */
10777 value = (value + 1) & ~ 1;
10779 if (fixP->fx_done || !seg->use_rela_p)
10783 newval = md_chars_to_number (buf, THUMB_SIZE);
10784 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10785 newval |= (value & 0x7fffff) >> 12;
10786 newval2 |= (value & 0xfff) >> 1;
10787 md_number_to_chars (buf, newval, THUMB_SIZE);
10788 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10792 case BFD_RELOC_THUMB_PCREL_BRANCH25:
10793 if ((value & ~0x1ffffff) && ((value & ~0x1ffffff) != ~0x1ffffff))
10794 as_bad_where (fixP->fx_file, fixP->fx_line,
10795 _("branch out of range"));
10797 if (fixP->fx_done || !seg->use_rela_p)
10800 addressT S, I1, I2, lo, hi;
10802 S = (value & 0x01000000) >> 24;
10803 I1 = (value & 0x00800000) >> 23;
10804 I2 = (value & 0x00400000) >> 22;
10805 hi = (value & 0x003ff000) >> 12;
10806 lo = (value & 0x00000ffe) >> 1;
10811 newval = md_chars_to_number (buf, THUMB_SIZE);
10812 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
10813 newval |= (S << 10) | hi;
10814 newval2 |= (I1 << 13) | (I2 << 11) | lo;
10815 md_number_to_chars (buf, newval, THUMB_SIZE);
10816 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
10821 if (fixP->fx_done || !seg->use_rela_p)
10822 md_number_to_chars (buf, value, 1);
10826 if (fixP->fx_done || !seg->use_rela_p)
10827 md_number_to_chars (buf, value, 2);
10831 case BFD_RELOC_ARM_TLS_GD32:
10832 case BFD_RELOC_ARM_TLS_LE32:
10833 case BFD_RELOC_ARM_TLS_IE32:
10834 case BFD_RELOC_ARM_TLS_LDM32:
10835 case BFD_RELOC_ARM_TLS_LDO32:
10836 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10839 case BFD_RELOC_ARM_GOT32:
10840 case BFD_RELOC_ARM_GOTOFF:
10841 case BFD_RELOC_ARM_TARGET2:
10842 if (fixP->fx_done || !seg->use_rela_p)
10843 md_number_to_chars (buf, 0, 4);
10847 case BFD_RELOC_RVA:
10849 case BFD_RELOC_ARM_TARGET1:
10850 case BFD_RELOC_ARM_ROSEGREL32:
10851 case BFD_RELOC_ARM_SBREL32:
10852 case BFD_RELOC_32_PCREL:
10853 if (fixP->fx_done || !seg->use_rela_p)
10854 md_number_to_chars (buf, value, 4);
10858 case BFD_RELOC_ARM_PREL31:
10859 if (fixP->fx_done || !seg->use_rela_p)
10861 newval = md_chars_to_number (buf, 4) & 0x80000000;
10862 if ((value ^ (value >> 1)) & 0x40000000)
10864 as_bad_where (fixP->fx_file, fixP->fx_line,
10865 _("rel31 relocation overflow"));
10867 newval |= value & 0x7fffffff;
10868 md_number_to_chars (buf, newval, 4);
10873 case BFD_RELOC_ARM_CP_OFF_IMM:
10874 if (value < -1023 || value > 1023 || (value & 3))
10875 as_bad_where (fixP->fx_file, fixP->fx_line,
10876 _("co-processor offset out of range"));
10881 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
10882 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
10884 newval &= ~WRITE_BACK;
10885 md_number_to_chars (buf, newval, INSN_SIZE);
10888 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
10889 if (value < -255 || value > 255)
10890 as_bad_where (fixP->fx_file, fixP->fx_line,
10891 _("co-processor offset out of range"));
10892 goto cp_off_common;
10894 case BFD_RELOC_ARM_THUMB_OFFSET:
10895 newval = md_chars_to_number (buf, THUMB_SIZE);
10896 /* Exactly what ranges, and where the offset is inserted depends
10897 on the type of instruction, we can establish this from the
10899 switch (newval >> 12)
10901 case 4: /* PC load. */
10902 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
10903 forced to zero for these loads; md_pcrel_from has already
10904 compensated for this. */
10906 as_bad_where (fixP->fx_file, fixP->fx_line,
10907 _("invalid offset, target not word aligned (0x%08lX)"),
10908 (((unsigned int) fixP->fx_frag->fr_address
10909 + (unsigned int) fixP->fx_where) & ~3) + value);
10911 if (value & ~0x3fc)
10912 as_bad_where (fixP->fx_file, fixP->fx_line,
10913 _("invalid offset, value too big (0x%08lX)"),
10916 newval |= value >> 2;
10919 case 9: /* SP load/store. */
10920 if (value & ~0x3fc)
10921 as_bad_where (fixP->fx_file, fixP->fx_line,
10922 _("invalid offset, value too big (0x%08lX)"),
10924 newval |= value >> 2;
10927 case 6: /* Word load/store. */
10929 as_bad_where (fixP->fx_file, fixP->fx_line,
10930 _("invalid offset, value too big (0x%08lX)"),
10932 newval |= value << 4; /* 6 - 2. */
10935 case 7: /* Byte load/store. */
10937 as_bad_where (fixP->fx_file, fixP->fx_line,
10938 _("invalid offset, value too big (0x%08lX)"),
10940 newval |= value << 6;
10943 case 8: /* Halfword load/store. */
10945 as_bad_where (fixP->fx_file, fixP->fx_line,
10946 _("invalid offset, value too big (0x%08lX)"),
10948 newval |= value << 5; /* 6 - 1. */
10952 as_bad_where (fixP->fx_file, fixP->fx_line,
10953 "Unable to process relocation for thumb opcode: %lx",
10954 (unsigned long) newval);
10957 md_number_to_chars (buf, newval, THUMB_SIZE);
10960 case BFD_RELOC_ARM_THUMB_ADD:
10961 /* This is a complicated relocation, since we use it for all of
10962 the following immediate relocations:
10966 9bit ADD/SUB SP word-aligned
10967 10bit ADD PC/SP word-aligned
10969 The type of instruction being processed is encoded in the
10976 newval = md_chars_to_number (buf, THUMB_SIZE);
10978 int rd = (newval >> 4) & 0xf;
10979 int rs = newval & 0xf;
10980 int subtract = !!(newval & 0x8000);
10982 /* Check for HI regs, only very restricted cases allowed:
10983 Adjusting SP, and using PC or SP to get an address. */
10984 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
10985 || (rs > 7 && rs != REG_SP && rs != REG_PC))
10986 as_bad_where (fixP->fx_file, fixP->fx_line,
10987 _("invalid Hi register with immediate"));
10989 /* If value is negative, choose the opposite instruction. */
10993 subtract = !subtract;
10995 as_bad_where (fixP->fx_file, fixP->fx_line,
10996 _("immediate value out of range"));
11001 if (value & ~0x1fc)
11002 as_bad_where (fixP->fx_file, fixP->fx_line,
11003 _("invalid immediate for stack address calculation"));
11004 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
11005 newval |= value >> 2;
11007 else if (rs == REG_PC || rs == REG_SP)
11009 if (subtract || value & ~0x3fc)
11010 as_bad_where (fixP->fx_file, fixP->fx_line,
11011 _("invalid immediate for address calculation (value = 0x%08lX)"),
11012 (unsigned long) value);
11013 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
11015 newval |= value >> 2;
11020 as_bad_where (fixP->fx_file, fixP->fx_line,
11021 _("immediate value out of range"));
11022 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
11023 newval |= (rd << 8) | value;
11028 as_bad_where (fixP->fx_file, fixP->fx_line,
11029 _("immediate value out of range"));
11030 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
11031 newval |= rd | (rs << 3) | (value << 6);
11034 md_number_to_chars (buf, newval, THUMB_SIZE);
11037 case BFD_RELOC_ARM_THUMB_IMM:
11038 newval = md_chars_to_number (buf, THUMB_SIZE);
11039 if (value < 0 || value > 255)
11040 as_bad_where (fixP->fx_file, fixP->fx_line,
11041 _("invalid immediate: %ld is too large"),
11044 md_number_to_chars (buf, newval, THUMB_SIZE);
11047 case BFD_RELOC_ARM_THUMB_SHIFT:
11048 /* 5bit shift value (0..32). LSL cannot take 32. */
11049 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
11050 temp = newval & 0xf800;
11051 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
11052 as_bad_where (fixP->fx_file, fixP->fx_line,
11053 _("invalid shift value: %ld"), (long) value);
11054 /* Shifts of zero must be encoded as LSL. */
11056 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
11057 /* Shifts of 32 are encoded as zero. */
11058 else if (value == 32)
11060 newval |= value << 6;
11061 md_number_to_chars (buf, newval, THUMB_SIZE);
11064 case BFD_RELOC_VTABLE_INHERIT:
11065 case BFD_RELOC_VTABLE_ENTRY:
11069 case BFD_RELOC_UNUSED:
11071 as_bad_where (fixP->fx_file, fixP->fx_line,
11072 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
11076 /* Translate internal representation of relocation info to BFD target
11080 tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
11084 bfd_reloc_code_real_type code;
11086 reloc = xmalloc (sizeof (arelent));
11088 reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
11089 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
11090 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
11092 if (fixp->fx_pcrel)
11093 fixp->fx_offset = reloc->address;
11094 reloc->addend = fixp->fx_offset;
11096 switch (fixp->fx_r_type)
11099 if (fixp->fx_pcrel)
11101 code = BFD_RELOC_8_PCREL;
11106 if (fixp->fx_pcrel)
11108 code = BFD_RELOC_16_PCREL;
11113 if (fixp->fx_pcrel)
11115 code = BFD_RELOC_32_PCREL;
11119 case BFD_RELOC_NONE:
11120 case BFD_RELOC_ARM_PCREL_BRANCH:
11121 case BFD_RELOC_ARM_PCREL_BLX:
11122 case BFD_RELOC_RVA:
11123 case BFD_RELOC_THUMB_PCREL_BRANCH7:
11124 case BFD_RELOC_THUMB_PCREL_BRANCH9:
11125 case BFD_RELOC_THUMB_PCREL_BRANCH12:
11126 case BFD_RELOC_THUMB_PCREL_BRANCH20:
11127 case BFD_RELOC_THUMB_PCREL_BRANCH23:
11128 case BFD_RELOC_THUMB_PCREL_BRANCH25:
11129 case BFD_RELOC_THUMB_PCREL_BLX:
11130 case BFD_RELOC_VTABLE_ENTRY:
11131 case BFD_RELOC_VTABLE_INHERIT:
11132 code = fixp->fx_r_type;
11135 case BFD_RELOC_ARM_LITERAL:
11136 case BFD_RELOC_ARM_HWLITERAL:
11137 /* If this is called then the a literal has
11138 been referenced across a section boundary. */
11139 as_bad_where (fixp->fx_file, fixp->fx_line,
11140 _("literal referenced across section boundary"));
11144 case BFD_RELOC_ARM_GOT32:
11145 case BFD_RELOC_ARM_GOTOFF:
11146 case BFD_RELOC_ARM_PLT32:
11147 case BFD_RELOC_ARM_TARGET1:
11148 case BFD_RELOC_ARM_ROSEGREL32:
11149 case BFD_RELOC_ARM_SBREL32:
11150 case BFD_RELOC_ARM_PREL31:
11151 case BFD_RELOC_ARM_TARGET2:
11152 case BFD_RELOC_ARM_TLS_LE32:
11153 case BFD_RELOC_ARM_TLS_LDO32:
11154 code = fixp->fx_r_type;
11157 case BFD_RELOC_ARM_TLS_GD32:
11158 case BFD_RELOC_ARM_TLS_IE32:
11159 case BFD_RELOC_ARM_TLS_LDM32:
11160 /* BFD will include the symbol's address in the addend.
11161 But we don't want that, so subtract it out again here. */
11162 if (!S_IS_COMMON (fixp->fx_addsy))
11163 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
11164 code = fixp->fx_r_type;
11168 case BFD_RELOC_ARM_IMMEDIATE:
11169 as_bad_where (fixp->fx_file, fixp->fx_line,
11170 _("internal relocation (type: IMMEDIATE) not fixed up"));
11173 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
11174 as_bad_where (fixp->fx_file, fixp->fx_line,
11175 _("ADRL used for a symbol not defined in the same file"));
11178 case BFD_RELOC_ARM_OFFSET_IMM:
11179 if (fixp->fx_addsy != NULL
11180 && !S_IS_DEFINED (fixp->fx_addsy)
11181 && S_IS_LOCAL (fixp->fx_addsy))
11183 as_bad_where (fixp->fx_file, fixp->fx_line,
11184 _("undefined local label `%s'"),
11185 S_GET_NAME (fixp->fx_addsy));
11189 as_bad_where (fixp->fx_file, fixp->fx_line,
11190 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
11197 switch (fixp->fx_r_type)
11199 case BFD_RELOC_NONE: type = "NONE"; break;
11200 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
11201 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
11202 case BFD_RELOC_ARM_SMI: type = "SMI"; break;
11203 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
11204 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
11205 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
11206 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
11207 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
11208 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
11209 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
11210 default: type = _("<unknown>"); break;
11212 as_bad_where (fixp->fx_file, fixp->fx_line,
11213 _("cannot represent %s relocation in this object file format"),
11220 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
11222 && fixp->fx_addsy == GOT_symbol)
11224 code = BFD_RELOC_ARM_GOTPC;
11225 reloc->addend = fixp->fx_offset = reloc->address;
11229 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
11231 if (reloc->howto == NULL)
11233 as_bad_where (fixp->fx_file, fixp->fx_line,
11234 _("cannot represent %s relocation in this object file format"),
11235 bfd_get_reloc_code_name (code));
11239 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
11240 vtable entry to be used in the relocation's section offset. */
11241 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11242 reloc->address = fixp->fx_offset;
11247 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
11250 cons_fix_new_arm (fragS * frag,
11255 bfd_reloc_code_real_type type;
11259 FIXME: @@ Should look at CPU word size. */
11263 type = BFD_RELOC_8;
11266 type = BFD_RELOC_16;
11270 type = BFD_RELOC_32;
11273 type = BFD_RELOC_64;
11277 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
11280 #if defined OBJ_COFF || defined OBJ_ELF
11282 arm_validate_fix (fixS * fixP)
11284 /* If the destination of the branch is a defined symbol which does not have
11285 the THUMB_FUNC attribute, then we must be calling a function which has
11286 the (interfacearm) attribute. We look for the Thumb entry point to that
11287 function and change the branch to refer to that function instead. */
11288 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
11289 && fixP->fx_addsy != NULL
11290 && S_IS_DEFINED (fixP->fx_addsy)
11291 && ! THUMB_IS_FUNC (fixP->fx_addsy))
11293 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
11299 arm_force_relocation (struct fix * fixp)
11301 #if defined (OBJ_COFF) && defined (TE_PE)
11302 if (fixp->fx_r_type == BFD_RELOC_RVA)
11306 /* Resolve these relocations even if the symbol is extern or weak. */
11307 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
11308 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
11309 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11312 return generic_force_reloc (fixp);
11316 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
11317 local labels from being added to the output symbol table when they
11318 are used with the ADRL pseudo op. The ADRL relocation should always
11319 be resolved before the binbary is emitted, so it is safe to say that
11320 it is adjustable. */
11323 arm_fix_adjustable (fixS * fixP)
11325 if (fixP->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
11332 /* Relocations against Thumb function names must be left unadjusted,
11333 so that the linker can use this information to correctly set the
11334 bottom bit of their addresses. The MIPS version of this function
11335 also prevents relocations that are mips-16 specific, but I do not
11336 know why it does this.
11339 There is one other problem that ought to be addressed here, but
11340 which currently is not: Taking the address of a label (rather
11341 than a function) and then later jumping to that address. Such
11342 addresses also ought to have their bottom bit set (assuming that
11343 they reside in Thumb code), but at the moment they will not. */
11346 arm_fix_adjustable (fixS * fixP)
11348 if (fixP->fx_addsy == NULL)
11351 if (THUMB_IS_FUNC (fixP->fx_addsy)
11352 && fixP->fx_subsy == NULL)
11355 /* We need the symbol name for the VTABLE entries. */
11356 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11357 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11360 /* Don't allow symbols to be discarded on GOT related relocs. */
11361 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
11362 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
11363 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
11364 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
11365 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
11366 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
11367 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
11368 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
11369 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
11376 elf32_arm_target_format (void)
11379 return (target_big_endian
11380 ? "elf32-bigarm-symbian"
11381 : "elf32-littlearm-symbian");
11382 #elif defined (TE_VXWORKS)
11383 return (target_big_endian
11384 ? "elf32-bigarm-vxworks"
11385 : "elf32-littlearm-vxworks");
11387 if (target_big_endian)
11388 return "elf32-bigarm";
11390 return "elf32-littlearm";
11395 armelf_frob_symbol (symbolS * symp,
11398 elf_frob_symbol (symp, puntp);
11402 /* MD interface: Finalization. */
11404 /* A good place to do this, although this was probably not intended
11405 for this kind of use. We need to dump the literal pool before
11406 references are made to a null symbol pointer. */
11411 literal_pool * pool;
11413 for (pool = list_of_pools; pool; pool = pool->next)
11415 /* Put it at the end of the relevent section. */
11416 subseg_set (pool->section, pool->sub_section);
11418 arm_elf_change_section ();
11424 /* Adjust the symbol table. This marks Thumb symbols as distinct from
11428 arm_adjust_symtab (void)
11433 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11435 if (ARM_IS_THUMB (sym))
11437 if (THUMB_IS_FUNC (sym))
11439 /* Mark the symbol as a Thumb function. */
11440 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
11441 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
11442 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
11444 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
11445 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
11447 as_bad (_("%s: unexpected function type: %d"),
11448 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
11450 else switch (S_GET_STORAGE_CLASS (sym))
11453 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
11456 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
11459 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
11467 if (ARM_IS_INTERWORK (sym))
11468 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
11475 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
11477 if (ARM_IS_THUMB (sym))
11479 elf_symbol_type * elf_sym;
11481 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
11482 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
11484 if (! bfd_is_arm_mapping_symbol_name (elf_sym->symbol.name))
11486 /* If it's a .thumb_func, declare it as so,
11487 otherwise tag label as .code 16. */
11488 if (THUMB_IS_FUNC (sym))
11489 elf_sym->internal_elf_sym.st_info =
11490 ELF_ST_INFO (bind, STT_ARM_TFUNC);
11492 elf_sym->internal_elf_sym.st_info =
11493 ELF_ST_INFO (bind, STT_ARM_16BIT);
11500 /* MD interface: Initialization. */
11503 set_constant_flonums (void)
11507 for (i = 0; i < NUM_FLOAT_VALS; i++)
11508 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
11518 if ( (arm_ops_hsh = hash_new ()) == NULL
11519 || (arm_cond_hsh = hash_new ()) == NULL
11520 || (arm_shift_hsh = hash_new ()) == NULL
11521 || (arm_psr_hsh = hash_new ()) == NULL
11522 || (arm_reg_hsh = hash_new ()) == NULL
11523 || (arm_reloc_hsh = hash_new ()) == NULL)
11524 as_fatal (_("virtual memory exhausted"));
11526 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
11527 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
11528 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
11529 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
11530 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
11531 hash_insert (arm_shift_hsh, shift_names[i].name, (PTR) (shift_names + i));
11532 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
11533 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
11534 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
11535 hash_insert (arm_reg_hsh, reg_names[i].name, (PTR) (reg_names + i));
11537 for (i = 0; i < sizeof (reloc_names) / sizeof (struct reloc_entry); i++)
11538 hash_insert (arm_reloc_hsh, reloc_names[i].name, (PTR) (reloc_names + i));
11541 set_constant_flonums ();
11543 /* Set the cpu variant based on the command-line options. We prefer
11544 -mcpu= over -march= if both are set (as for GCC); and we prefer
11545 -mfpu= over any other way of setting the floating point unit.
11546 Use of legacy options with new options are faulted. */
11547 if (legacy_cpu != -1)
11549 if (mcpu_cpu_opt != -1 || march_cpu_opt != -1)
11550 as_bad (_("use of old and new-style options to set CPU type"));
11552 mcpu_cpu_opt = legacy_cpu;
11554 else if (mcpu_cpu_opt == -1)
11555 mcpu_cpu_opt = march_cpu_opt;
11557 if (legacy_fpu != -1)
11559 if (mfpu_opt != -1)
11560 as_bad (_("use of old and new-style options to set FPU type"));
11562 mfpu_opt = legacy_fpu;
11564 else if (mfpu_opt == -1)
11566 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
11567 /* Some environments specify a default FPU. If they don't, infer it
11568 from the processor. */
11569 if (mcpu_fpu_opt != -1)
11570 mfpu_opt = mcpu_fpu_opt;
11572 mfpu_opt = march_fpu_opt;
11574 mfpu_opt = FPU_DEFAULT;
11578 if (mfpu_opt == -1)
11580 if (mcpu_cpu_opt == -1)
11581 mfpu_opt = FPU_DEFAULT;
11582 else if (mcpu_cpu_opt & ARM_EXT_V5)
11583 mfpu_opt = FPU_ARCH_VFP_V2;
11585 mfpu_opt = FPU_ARCH_FPA;
11588 if (mcpu_cpu_opt == -1)
11589 mcpu_cpu_opt = CPU_DEFAULT;
11591 cpu_variant = mcpu_cpu_opt | mfpu_opt;
11593 #if defined OBJ_COFF || defined OBJ_ELF
11595 unsigned int flags = 0;
11597 #if defined OBJ_ELF
11598 flags = meabi_flags;
11600 switch (meabi_flags)
11602 case EF_ARM_EABI_UNKNOWN:
11604 /* Set the flags in the private structure. */
11605 if (uses_apcs_26) flags |= F_APCS26;
11606 if (support_interwork) flags |= F_INTERWORK;
11607 if (uses_apcs_float) flags |= F_APCS_FLOAT;
11608 if (pic_code) flags |= F_PIC;
11609 if ((cpu_variant & FPU_ANY) == FPU_NONE
11610 || (cpu_variant & FPU_ANY) == FPU_ARCH_VFP) /* VFP layout only. */
11611 flags |= F_SOFT_FLOAT;
11613 switch (mfloat_abi_opt)
11615 case ARM_FLOAT_ABI_SOFT:
11616 case ARM_FLOAT_ABI_SOFTFP:
11617 flags |= F_SOFT_FLOAT;
11620 case ARM_FLOAT_ABI_HARD:
11621 if (flags & F_SOFT_FLOAT)
11622 as_bad (_("hard-float conflicts with specified fpu"));
11626 /* Using VFP conventions (even if soft-float). */
11627 if (cpu_variant & FPU_VFP_EXT_NONE)
11628 flags |= F_VFP_FLOAT;
11630 #if defined OBJ_ELF
11631 if (cpu_variant & FPU_ARCH_MAVERICK)
11632 flags |= EF_ARM_MAVERICK_FLOAT;
11635 case EF_ARM_EABI_VER4:
11636 /* No additional flags to set. */
11643 bfd_set_private_flags (stdoutput, flags);
11645 /* We have run out flags in the COFF header to encode the
11646 status of ATPCS support, so instead we create a dummy,
11647 empty, debug section called .arm.atpcs. */
11652 sec = bfd_make_section (stdoutput, ".arm.atpcs");
11656 bfd_set_section_flags
11657 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
11658 bfd_set_section_size (stdoutput, sec, 0);
11659 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
11665 /* Record the CPU type as well. */
11666 switch (cpu_variant & ARM_CPU_MASK)
11669 mach = bfd_mach_arm_2;
11672 case ARM_3: /* Also ARM_250. */
11673 mach = bfd_mach_arm_2a;
11676 case ARM_6: /* Also ARM_7. */
11677 mach = bfd_mach_arm_3;
11681 mach = bfd_mach_arm_unknown;
11685 /* Catch special cases. */
11686 if (cpu_variant & ARM_CEXT_IWMMXT)
11687 mach = bfd_mach_arm_iWMMXt;
11688 else if (cpu_variant & ARM_CEXT_XSCALE)
11689 mach = bfd_mach_arm_XScale;
11690 else if (cpu_variant & ARM_CEXT_MAVERICK)
11691 mach = bfd_mach_arm_ep9312;
11692 else if (cpu_variant & ARM_EXT_V5E)
11693 mach = bfd_mach_arm_5TE;
11694 else if (cpu_variant & ARM_EXT_V5)
11696 if (cpu_variant & ARM_EXT_V4T)
11697 mach = bfd_mach_arm_5T;
11699 mach = bfd_mach_arm_5;
11701 else if (cpu_variant & ARM_EXT_V4)
11703 if (cpu_variant & ARM_EXT_V4T)
11704 mach = bfd_mach_arm_4T;
11706 mach = bfd_mach_arm_4;
11708 else if (cpu_variant & ARM_EXT_V3M)
11709 mach = bfd_mach_arm_3M;
11711 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
11714 /* Command line processing. */
11717 Invocation line includes a switch not recognized by the base assembler.
11718 See if it's a processor-specific option.
11720 This routine is somewhat complicated by the need for backwards
11721 compatibility (since older releases of gcc can't be changed).
11722 The new options try to make the interface as compatible as
11725 New options (supported) are:
11727 -mcpu=<cpu name> Assemble for selected processor
11728 -march=<architecture name> Assemble for selected architecture
11729 -mfpu=<fpu architecture> Assemble for selected FPU.
11730 -EB/-mbig-endian Big-endian
11731 -EL/-mlittle-endian Little-endian
11732 -k Generate PIC code
11733 -mthumb Start in Thumb mode
11734 -mthumb-interwork Code supports ARM/Thumb interworking
11736 For now we will also provide support for:
11738 -mapcs-32 32-bit Program counter
11739 -mapcs-26 26-bit Program counter
11740 -macps-float Floats passed in FP registers
11741 -mapcs-reentrant Reentrant code
11743 (sometime these will probably be replaced with -mapcs=<list of options>
11744 and -matpcs=<list of options>)
11746 The remaining options are only supported for back-wards compatibility.
11747 Cpu variants, the arm part is optional:
11748 -m[arm]1 Currently not supported.
11749 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
11750 -m[arm]3 Arm 3 processor
11751 -m[arm]6[xx], Arm 6 processors
11752 -m[arm]7[xx][t][[d]m] Arm 7 processors
11753 -m[arm]8[10] Arm 8 processors
11754 -m[arm]9[20][tdmi] Arm 9 processors
11755 -mstrongarm[110[0]] StrongARM processors
11756 -mxscale XScale processors
11757 -m[arm]v[2345[t[e]]] Arm architectures
11758 -mall All (except the ARM1)
11760 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
11761 -mfpe-old (No float load/store multiples)
11762 -mvfpxd VFP Single precision
11764 -mno-fpu Disable all floating point instructions
11766 The following CPU names are recognized:
11767 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
11768 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
11769 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
11770 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
11771 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
11772 arm10t arm10e, arm1020t, arm1020e, arm10200e,
11773 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
11777 const char * md_shortopts = "m:k";
11779 #ifdef ARM_BI_ENDIAN
11780 #define OPTION_EB (OPTION_MD_BASE + 0)
11781 #define OPTION_EL (OPTION_MD_BASE + 1)
11783 #if TARGET_BYTES_BIG_ENDIAN
11784 #define OPTION_EB (OPTION_MD_BASE + 0)
11786 #define OPTION_EL (OPTION_MD_BASE + 1)
11790 struct option md_longopts[] =
11793 {"EB", no_argument, NULL, OPTION_EB},
11796 {"EL", no_argument, NULL, OPTION_EL},
11798 {NULL, no_argument, NULL, 0}
11801 size_t md_longopts_size = sizeof (md_longopts);
11803 struct arm_option_table
11805 char *option; /* Option name to match. */
11806 char *help; /* Help information. */
11807 int *var; /* Variable to change. */
11808 int value; /* What to change it to. */
11809 char *deprecated; /* If non-null, print this message. */
11812 struct arm_option_table arm_opts[] =
11814 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
11815 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
11816 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
11817 &support_interwork, 1, NULL},
11818 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
11819 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
11820 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
11822 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
11823 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
11824 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
11825 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
11828 /* These are recognized by the assembler, but have no affect on code. */
11829 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
11830 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
11832 /* DON'T add any new processors to this list -- we want the whole list
11833 to go away... Add them to the processors table instead. */
11834 {"marm1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11835 {"m1", NULL, &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
11836 {"marm2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11837 {"m2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
11838 {"marm250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11839 {"m250", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
11840 {"marm3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11841 {"m3", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
11842 {"marm6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11843 {"m6", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
11844 {"marm600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11845 {"m600", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
11846 {"marm610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11847 {"m610", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
11848 {"marm620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11849 {"m620", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
11850 {"marm7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11851 {"m7", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
11852 {"marm70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11853 {"m70", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
11854 {"marm700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11855 {"m700", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
11856 {"marm700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11857 {"m700i", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
11858 {"marm710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11859 {"m710", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
11860 {"marm710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11861 {"m710c", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
11862 {"marm720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11863 {"m720", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
11864 {"marm7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11865 {"m7d", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
11866 {"marm7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11867 {"m7di", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
11868 {"marm7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11869 {"m7m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
11870 {"marm7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11871 {"m7dm", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
11872 {"marm7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11873 {"m7dmi", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
11874 {"marm7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11875 {"m7100", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
11876 {"marm7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11877 {"m7500", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
11878 {"marm7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11879 {"m7500fe", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
11880 {"marm7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11881 {"m7t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11882 {"marm7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11883 {"m7tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
11884 {"marm710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11885 {"m710t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
11886 {"marm720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11887 {"m720t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
11888 {"marm740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11889 {"m740t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
11890 {"marm8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11891 {"m8", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
11892 {"marm810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11893 {"m810", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
11894 {"marm9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11895 {"m9", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
11896 {"marm9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11897 {"m9tdmi", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
11898 {"marm920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11899 {"m920", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
11900 {"marm940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11901 {"m940", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
11902 {"mstrongarm", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
11903 {"mstrongarm110", NULL, &legacy_cpu, ARM_ARCH_V4,
11904 N_("use -mcpu=strongarm110")},
11905 {"mstrongarm1100", NULL, &legacy_cpu, ARM_ARCH_V4,
11906 N_("use -mcpu=strongarm1100")},
11907 {"mstrongarm1110", NULL, &legacy_cpu, ARM_ARCH_V4,
11908 N_("use -mcpu=strongarm1110")},
11909 {"mxscale", NULL, &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
11910 {"miwmmxt", NULL, &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
11911 {"mall", NULL, &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
11913 /* Architecture variants -- don't add any more to this list either. */
11914 {"mv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11915 {"marmv2", NULL, &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
11916 {"mv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11917 {"marmv2a", NULL, &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
11918 {"mv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11919 {"marmv3", NULL, &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
11920 {"mv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11921 {"marmv3m", NULL, &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
11922 {"mv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11923 {"marmv4", NULL, &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
11924 {"mv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11925 {"marmv4t", NULL, &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
11926 {"mv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11927 {"marmv5", NULL, &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
11928 {"mv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11929 {"marmv5t", NULL, &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
11930 {"mv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11931 {"marmv5e", NULL, &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
11933 /* Floating point variants -- don't add any more to this list either. */
11934 {"mfpe-old", NULL, &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
11935 {"mfpa10", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
11936 {"mfpa11", NULL, &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
11937 {"mno-fpu", NULL, &legacy_fpu, 0,
11938 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
11940 {NULL, NULL, NULL, 0, NULL}
11943 struct arm_cpu_option_table
11947 /* For some CPUs we assume an FPU unless the user explicitly sets
11952 /* This list should, at a minimum, contain all the cpu names
11953 recognized by GCC. */
11954 static struct arm_cpu_option_table arm_cpus[] =
11956 {"all", ARM_ANY, FPU_ARCH_FPA},
11957 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA},
11958 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA},
11959 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA},
11960 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA},
11961 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA},
11962 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA},
11963 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA},
11964 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA},
11965 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA},
11966 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA},
11967 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA},
11968 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA},
11969 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA},
11970 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA},
11971 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA},
11972 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA},
11973 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA},
11974 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA},
11975 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA},
11976 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11977 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA},
11978 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11979 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11980 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA},
11981 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA},
11982 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA},
11983 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA},
11984 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11985 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
11986 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA},
11987 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA},
11988 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA},
11989 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA},
11990 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA},
11991 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA},
11992 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA},
11993 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA},
11994 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA},
11995 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA},
11996 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11997 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11998 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA},
11999 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA},
12000 /* For V5 or later processors we default to using VFP; but the user
12001 should really set the FPU type explicitly. */
12002 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12003 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12004 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12005 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12006 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12007 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12008 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12009 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2},
12010 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12011 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12012 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12013 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12014 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1},
12015 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2},
12016 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12017 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2},
12018 {"arm1136js", ARM_ARCH_V6, FPU_NONE},
12019 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE},
12020 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12021 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2},
12022 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2},
12023 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE},
12024 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE},
12025 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2},
12026 /* ??? XSCALE is really an architecture. */
12027 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12028 /* ??? iwmmxt is not a processor. */
12029 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2},
12030 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2},
12032 {"ep9312", ARM_ARCH_V4T | ARM_CEXT_MAVERICK, FPU_ARCH_MAVERICK},
12036 struct arm_arch_option_table
12043 /* This list should, at a minimum, contain all the architecture names
12044 recognized by GCC. */
12045 static struct arm_arch_option_table arm_archs[] =
12047 {"all", ARM_ANY, FPU_ARCH_FPA},
12048 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
12049 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
12050 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
12051 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
12052 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
12053 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
12054 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
12055 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
12056 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
12057 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
12058 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
12059 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
12060 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
12061 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
12062 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
12063 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
12064 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
12065 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
12066 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
12067 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
12068 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
12069 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
12070 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
12071 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
12072 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
12073 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
12074 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
12078 /* ISA extensions in the co-processor space. */
12079 struct arm_option_value_table
12085 static struct arm_option_value_table arm_extensions[] =
12087 {"maverick", ARM_CEXT_MAVERICK},
12088 {"xscale", ARM_CEXT_XSCALE},
12089 {"iwmmxt", ARM_CEXT_IWMMXT},
12093 /* This list should, at a minimum, contain all the fpu names
12094 recognized by GCC. */
12095 static struct arm_option_value_table arm_fpus[] =
12097 {"softfpa", FPU_NONE},
12098 {"fpe", FPU_ARCH_FPE},
12099 {"fpe2", FPU_ARCH_FPE},
12100 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
12101 {"fpa", FPU_ARCH_FPA},
12102 {"fpa10", FPU_ARCH_FPA},
12103 {"fpa11", FPU_ARCH_FPA},
12104 {"arm7500fe", FPU_ARCH_FPA},
12105 {"softvfp", FPU_ARCH_VFP},
12106 {"softvfp+vfp", FPU_ARCH_VFP_V2},
12107 {"vfp", FPU_ARCH_VFP_V2},
12108 {"vfp9", FPU_ARCH_VFP_V2},
12109 {"vfp10", FPU_ARCH_VFP_V2},
12110 {"vfp10-r0", FPU_ARCH_VFP_V1},
12111 {"vfpxd", FPU_ARCH_VFP_V1xD},
12112 {"arm1020t", FPU_ARCH_VFP_V1},
12113 {"arm1020e", FPU_ARCH_VFP_V2},
12114 {"arm1136jfs", FPU_ARCH_VFP_V2},
12115 {"arm1136jf-s", FPU_ARCH_VFP_V2},
12116 {"maverick", FPU_ARCH_MAVERICK},
12120 static struct arm_option_value_table arm_float_abis[] =
12122 {"hard", ARM_FLOAT_ABI_HARD},
12123 {"softfp", ARM_FLOAT_ABI_SOFTFP},
12124 {"soft", ARM_FLOAT_ABI_SOFT},
12129 /* We only know how to output GNU and ver 4 (AAELF) formats. */
12130 static struct arm_option_value_table arm_eabis[] =
12132 {"gnu", EF_ARM_EABI_UNKNOWN},
12133 {"4", EF_ARM_EABI_VER4},
12138 struct arm_long_option_table
12140 char * option; /* Substring to match. */
12141 char * help; /* Help information. */
12142 int (* func) (char * subopt); /* Function to decode sub-option. */
12143 char * deprecated; /* If non-null, print this message. */
12147 arm_parse_extension (char * str, int * opt_p)
12149 while (str != NULL && *str != 0)
12151 struct arm_option_value_table * opt;
12157 as_bad (_("invalid architectural extension"));
12162 ext = strchr (str, '+');
12165 optlen = ext - str;
12167 optlen = strlen (str);
12171 as_bad (_("missing architectural extension"));
12175 for (opt = arm_extensions; opt->name != NULL; opt++)
12176 if (strncmp (opt->name, str, optlen) == 0)
12178 *opt_p |= opt->value;
12182 if (opt->name == NULL)
12184 as_bad (_("unknown architectural extnsion `%s'"), str);
12195 arm_parse_cpu (char * str)
12197 struct arm_cpu_option_table * opt;
12198 char * ext = strchr (str, '+');
12202 optlen = ext - str;
12204 optlen = strlen (str);
12208 as_bad (_("missing cpu name `%s'"), str);
12212 for (opt = arm_cpus; opt->name != NULL; opt++)
12213 if (strncmp (opt->name, str, optlen) == 0)
12215 mcpu_cpu_opt = opt->value;
12216 mcpu_fpu_opt = opt->default_fpu;
12219 return arm_parse_extension (ext, &mcpu_cpu_opt);
12224 as_bad (_("unknown cpu `%s'"), str);
12229 arm_parse_arch (char * str)
12231 struct arm_arch_option_table *opt;
12232 char *ext = strchr (str, '+');
12236 optlen = ext - str;
12238 optlen = strlen (str);
12242 as_bad (_("missing architecture name `%s'"), str);
12247 for (opt = arm_archs; opt->name != NULL; opt++)
12248 if (streq (opt->name, str))
12250 march_cpu_opt = opt->value;
12251 march_fpu_opt = opt->default_fpu;
12254 return arm_parse_extension (ext, &march_cpu_opt);
12259 as_bad (_("unknown architecture `%s'\n"), str);
12264 arm_parse_fpu (char * str)
12266 struct arm_option_value_table * opt;
12268 for (opt = arm_fpus; opt->name != NULL; opt++)
12269 if (streq (opt->name, str))
12271 mfpu_opt = opt->value;
12275 as_bad (_("unknown floating point format `%s'\n"), str);
12280 arm_parse_float_abi (char * str)
12282 struct arm_option_value_table * opt;
12284 for (opt = arm_float_abis; opt->name != NULL; opt++)
12285 if (streq (opt->name, str))
12287 mfloat_abi_opt = opt->value;
12291 as_bad (_("unknown floating point abi `%s'\n"), str);
12297 arm_parse_eabi (char * str)
12299 struct arm_option_value_table *opt;
12301 for (opt = arm_eabis; opt->name != NULL; opt++)
12302 if (streq (opt->name, str))
12304 meabi_flags = opt->value;
12307 as_bad (_("unknown EABI `%s'\n"), str);
12312 struct arm_long_option_table arm_long_opts[] =
12314 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
12315 arm_parse_cpu, NULL},
12316 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
12317 arm_parse_arch, NULL},
12318 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
12319 arm_parse_fpu, NULL},
12320 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
12321 arm_parse_float_abi, NULL},
12323 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
12324 arm_parse_eabi, NULL},
12326 {NULL, NULL, 0, NULL}
12330 md_parse_option (int c, char * arg)
12332 struct arm_option_table *opt;
12333 struct arm_long_option_table *lopt;
12339 target_big_endian = 1;
12345 target_big_endian = 0;
12350 /* Listing option. Just ignore these, we don't support additional
12355 for (opt = arm_opts; opt->option != NULL; opt++)
12357 if (c == opt->option[0]
12358 && ((arg == NULL && opt->option[1] == 0)
12359 || streq (arg, opt->option + 1)))
12361 #if WARN_DEPRECATED
12362 /* If the option is deprecated, tell the user. */
12363 if (opt->deprecated != NULL)
12364 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
12365 arg ? arg : "", _(opt->deprecated));
12368 if (opt->var != NULL)
12369 *opt->var = opt->value;
12375 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12377 /* These options are expected to have an argument. */
12378 if (c == lopt->option[0]
12380 && strncmp (arg, lopt->option + 1,
12381 strlen (lopt->option + 1)) == 0)
12383 #if WARN_DEPRECATED
12384 /* If the option is deprecated, tell the user. */
12385 if (lopt->deprecated != NULL)
12386 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
12387 _(lopt->deprecated));
12390 /* Call the sup-option parser. */
12391 return lopt->func (arg + strlen (lopt->option) - 1);
12402 md_show_usage (FILE * fp)
12404 struct arm_option_table *opt;
12405 struct arm_long_option_table *lopt;
12407 fprintf (fp, _(" ARM-specific assembler options:\n"));
12409 for (opt = arm_opts; opt->option != NULL; opt++)
12410 if (opt->help != NULL)
12411 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
12413 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
12414 if (lopt->help != NULL)
12415 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
12419 -EB assemble code for a big-endian cpu\n"));
12424 -EL assemble code for a little-endian cpu\n"));