1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
199 static const arm_feature_set arm_ext_m =
200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
201 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
202 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
203 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
204 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
205 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
207 static const arm_feature_set arm_arch_any = ARM_ANY;
208 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
211 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
213 static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
215 static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217 static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219 static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223 static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
227 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
228 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
229 static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
231 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
234 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
239 static const arm_feature_set fpu_neon_ext_armv8 =
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
241 static const arm_feature_set fpu_crypto_ext_armv8 =
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
337 enum neon_el_type type;
341 #define NEON_MAX_TYPE_ELS 4
345 struct neon_type_el el[NEON_MAX_TYPE_ELS];
349 enum it_instruction_type
354 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
355 if inside, should be the last one. */
356 NEUTRAL_IT_INSN, /* This could be either inside or outside,
357 i.e. BKPT and NOP. */
358 IT_INSN /* The IT insn has been parsed. */
361 /* The maximum number of operands we need. */
362 #define ARM_IT_MAX_OPERANDS 6
367 unsigned long instruction;
371 /* "uncond_value" is set to the value in place of the conditional field in
372 unconditional versions of the instruction, or -1 if nothing is
375 struct neon_type vectype;
376 /* This does not indicate an actual NEON instruction, only that
377 the mnemonic accepts neon-style type suffixes. */
379 /* Set to the opcode if the instruction needs relaxation.
380 Zero if the instruction is not relaxed. */
384 bfd_reloc_code_real_type type;
389 enum it_instruction_type it_insn_type;
395 struct neon_type_el vectype;
396 unsigned present : 1; /* Operand present. */
397 unsigned isreg : 1; /* Operand was a register. */
398 unsigned immisreg : 1; /* .imm field is a second register. */
399 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
400 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
401 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
402 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
403 instructions. This allows us to disambiguate ARM <-> vector insns. */
404 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
405 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
406 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
407 unsigned issingle : 1; /* Operand is VFP single-precision register. */
408 unsigned hasreloc : 1; /* Operand has relocation suffix. */
409 unsigned writeback : 1; /* Operand has trailing ! */
410 unsigned preind : 1; /* Preindexed address. */
411 unsigned postind : 1; /* Postindexed address. */
412 unsigned negative : 1; /* Index register was negated. */
413 unsigned shifted : 1; /* Shift applied to operation. */
414 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
415 } operands[ARM_IT_MAX_OPERANDS];
418 static struct arm_it inst;
420 #define NUM_FLOAT_VALS 8
422 const char * fp_const[] =
424 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
427 /* Number of littlenums required to hold an extended precision number. */
428 #define MAX_LITTLENUMS 6
430 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
440 #define CP_T_X 0x00008000
441 #define CP_T_Y 0x00400000
443 #define CONDS_BIT 0x00100000
444 #define LOAD_BIT 0x00100000
446 #define DOUBLE_LOAD_FLAG 0x00000001
450 const char * template_name;
454 #define COND_ALWAYS 0xE
458 const char * template_name;
462 struct asm_barrier_opt
464 const char * template_name;
468 /* The bit that distinguishes CPSR and SPSR. */
469 #define SPSR_BIT (1 << 22)
471 /* The individual PSR flag bits. */
472 #define PSR_c (1 << 16)
473 #define PSR_x (1 << 17)
474 #define PSR_s (1 << 18)
475 #define PSR_f (1 << 19)
480 bfd_reloc_code_real_type reloc;
485 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
486 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
491 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
494 /* Bits for DEFINED field in neon_typed_alias. */
495 #define NTA_HASTYPE 1
496 #define NTA_HASINDEX 2
498 struct neon_typed_alias
500 unsigned char defined;
502 struct neon_type_el eltype;
505 /* ARM register categories. This includes coprocessor numbers and various
506 architecture extensions' registers. */
533 /* Structure for a hash table entry for a register.
534 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
535 information which states whether a vector type or index is specified (for a
536 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
542 unsigned char builtin;
543 struct neon_typed_alias * neon;
546 /* Diagnostics used when we don't get a register of the expected type. */
547 const char * const reg_expected_msgs[] =
549 N_("ARM register expected"),
550 N_("bad or missing co-processor number"),
551 N_("co-processor register expected"),
552 N_("FPA register expected"),
553 N_("VFP single precision register expected"),
554 N_("VFP/Neon double precision register expected"),
555 N_("Neon quad precision register expected"),
556 N_("VFP single or double precision register expected"),
557 N_("Neon double or quad precision register expected"),
558 N_("VFP single, double or Neon quad precision register expected"),
559 N_("VFP system register expected"),
560 N_("Maverick MVF register expected"),
561 N_("Maverick MVD register expected"),
562 N_("Maverick MVFX register expected"),
563 N_("Maverick MVDX register expected"),
564 N_("Maverick MVAX register expected"),
565 N_("Maverick DSPSC register expected"),
566 N_("iWMMXt data register expected"),
567 N_("iWMMXt control register expected"),
568 N_("iWMMXt scalar register expected"),
569 N_("XScale accumulator register expected"),
572 /* Some well known registers that we refer to directly elsewhere. */
578 /* ARM instructions take 4bytes in the object file, Thumb instructions
584 /* Basic string to match. */
585 const char * template_name;
587 /* Parameters to instruction. */
588 unsigned int operands[8];
590 /* Conditional tag - see opcode_lookup. */
591 unsigned int tag : 4;
593 /* Basic instruction code. */
594 unsigned int avalue : 28;
596 /* Thumb-format instruction code. */
599 /* Which architecture variant provides this instruction. */
600 const arm_feature_set * avariant;
601 const arm_feature_set * tvariant;
603 /* Function to call to encode instruction in ARM format. */
604 void (* aencode) (void);
606 /* Function to call to encode instruction in Thumb format. */
607 void (* tencode) (void);
610 /* Defines for various bits that we will want to toggle. */
611 #define INST_IMMEDIATE 0x02000000
612 #define OFFSET_REG 0x02000000
613 #define HWOFFSET_IMM 0x00400000
614 #define SHIFT_BY_REG 0x00000010
615 #define PRE_INDEX 0x01000000
616 #define INDEX_UP 0x00800000
617 #define WRITE_BACK 0x00200000
618 #define LDM_TYPE_2_OR_3 0x00400000
619 #define CPSI_MMOD 0x00020000
621 #define LITERAL_MASK 0xf000f000
622 #define OPCODE_MASK 0xfe1fffff
623 #define V4_STR_BIT 0x00000020
625 #define T2_SUBS_PC_LR 0xf3de8f00
627 #define DATA_OP_SHIFT 21
629 #define T2_OPCODE_MASK 0xfe1fffff
630 #define T2_DATA_OP_SHIFT 21
632 #define A_COND_MASK 0xf0000000
633 #define A_PUSH_POP_OP_MASK 0x0fff0000
635 /* Opcodes for pushing/poping registers to/from the stack. */
636 #define A1_OPCODE_PUSH 0x092d0000
637 #define A2_OPCODE_PUSH 0x052d0004
638 #define A2_OPCODE_POP 0x049d0004
640 /* Codes to distinguish the arithmetic instructions. */
651 #define OPCODE_CMP 10
652 #define OPCODE_CMN 11
653 #define OPCODE_ORR 12
654 #define OPCODE_MOV 13
655 #define OPCODE_BIC 14
656 #define OPCODE_MVN 15
658 #define T2_OPCODE_AND 0
659 #define T2_OPCODE_BIC 1
660 #define T2_OPCODE_ORR 2
661 #define T2_OPCODE_ORN 3
662 #define T2_OPCODE_EOR 4
663 #define T2_OPCODE_ADD 8
664 #define T2_OPCODE_ADC 10
665 #define T2_OPCODE_SBC 11
666 #define T2_OPCODE_SUB 13
667 #define T2_OPCODE_RSB 14
669 #define T_OPCODE_MUL 0x4340
670 #define T_OPCODE_TST 0x4200
671 #define T_OPCODE_CMN 0x42c0
672 #define T_OPCODE_NEG 0x4240
673 #define T_OPCODE_MVN 0x43c0
675 #define T_OPCODE_ADD_R3 0x1800
676 #define T_OPCODE_SUB_R3 0x1a00
677 #define T_OPCODE_ADD_HI 0x4400
678 #define T_OPCODE_ADD_ST 0xb000
679 #define T_OPCODE_SUB_ST 0xb080
680 #define T_OPCODE_ADD_SP 0xa800
681 #define T_OPCODE_ADD_PC 0xa000
682 #define T_OPCODE_ADD_I8 0x3000
683 #define T_OPCODE_SUB_I8 0x3800
684 #define T_OPCODE_ADD_I3 0x1c00
685 #define T_OPCODE_SUB_I3 0x1e00
687 #define T_OPCODE_ASR_R 0x4100
688 #define T_OPCODE_LSL_R 0x4080
689 #define T_OPCODE_LSR_R 0x40c0
690 #define T_OPCODE_ROR_R 0x41c0
691 #define T_OPCODE_ASR_I 0x1000
692 #define T_OPCODE_LSL_I 0x0000
693 #define T_OPCODE_LSR_I 0x0800
695 #define T_OPCODE_MOV_I8 0x2000
696 #define T_OPCODE_CMP_I8 0x2800
697 #define T_OPCODE_CMP_LR 0x4280
698 #define T_OPCODE_MOV_HR 0x4600
699 #define T_OPCODE_CMP_HR 0x4500
701 #define T_OPCODE_LDR_PC 0x4800
702 #define T_OPCODE_LDR_SP 0x9800
703 #define T_OPCODE_STR_SP 0x9000
704 #define T_OPCODE_LDR_IW 0x6800
705 #define T_OPCODE_STR_IW 0x6000
706 #define T_OPCODE_LDR_IH 0x8800
707 #define T_OPCODE_STR_IH 0x8000
708 #define T_OPCODE_LDR_IB 0x7800
709 #define T_OPCODE_STR_IB 0x7000
710 #define T_OPCODE_LDR_RW 0x5800
711 #define T_OPCODE_STR_RW 0x5000
712 #define T_OPCODE_LDR_RH 0x5a00
713 #define T_OPCODE_STR_RH 0x5200
714 #define T_OPCODE_LDR_RB 0x5c00
715 #define T_OPCODE_STR_RB 0x5400
717 #define T_OPCODE_PUSH 0xb400
718 #define T_OPCODE_POP 0xbc00
720 #define T_OPCODE_BRANCH 0xe000
722 #define THUMB_SIZE 2 /* Size of thumb instruction. */
723 #define THUMB_PP_PC_LR 0x0100
724 #define THUMB_LOAD_BIT 0x0800
725 #define THUMB2_LOAD_BIT 0x00100000
727 #define BAD_ARGS _("bad arguments to instruction")
728 #define BAD_SP _("r13 not allowed here")
729 #define BAD_PC _("r15 not allowed here")
730 #define BAD_COND _("instruction cannot be conditional")
731 #define BAD_OVERLAP _("registers may not be the same")
732 #define BAD_HIREG _("lo register required")
733 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
734 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
735 #define BAD_BRANCH _("branch must be last instruction in IT block")
736 #define BAD_NOT_IT _("instruction not allowed in IT block")
737 #define BAD_FPU _("selected FPU does not support instruction")
738 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
739 #define BAD_IT_COND _("incorrect condition in IT block")
740 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
741 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
742 #define BAD_PC_ADDRESSING \
743 _("cannot use register index with PC-relative addressing")
744 #define BAD_PC_WRITEBACK \
745 _("cannot use writeback with PC-relative addressing")
746 #define BAD_RANGE _("branch out of range")
748 static struct hash_control * arm_ops_hsh;
749 static struct hash_control * arm_cond_hsh;
750 static struct hash_control * arm_shift_hsh;
751 static struct hash_control * arm_psr_hsh;
752 static struct hash_control * arm_v7m_psr_hsh;
753 static struct hash_control * arm_reg_hsh;
754 static struct hash_control * arm_reloc_hsh;
755 static struct hash_control * arm_barrier_opt_hsh;
757 /* Stuff needed to resolve the label ambiguity
766 symbolS * last_label_seen;
767 static int label_is_thumb_function_name = FALSE;
769 /* Literal pool structure. Held on a per-section
770 and per-sub-section basis. */
772 #define MAX_LITERAL_POOL_SIZE 1024
773 typedef struct literal_pool
775 expressionS literals [MAX_LITERAL_POOL_SIZE];
776 unsigned int next_free_entry;
782 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
784 struct literal_pool * next;
787 /* Pointer to a linked list of literal pools. */
788 literal_pool * list_of_pools = NULL;
791 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
793 static struct current_it now_it;
797 now_it_compatible (int cond)
799 return (cond & ~1) == (now_it.cc & ~1);
803 conditional_insn (void)
805 return inst.cond != COND_ALWAYS;
808 static int in_it_block (void);
810 static int handle_it_state (void);
812 static void force_automatic_it_block_close (void);
814 static void it_fsm_post_encode (void);
816 #define set_it_insn_type(type) \
819 inst.it_insn_type = type; \
820 if (handle_it_state () == FAIL) \
825 #define set_it_insn_type_nonvoid(type, failret) \
828 inst.it_insn_type = type; \
829 if (handle_it_state () == FAIL) \
834 #define set_it_insn_type_last() \
837 if (inst.cond == COND_ALWAYS) \
838 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
840 set_it_insn_type (INSIDE_IT_LAST_INSN); \
846 /* This array holds the chars that always start a comment. If the
847 pre-processor is disabled, these aren't very useful. */
848 const char comment_chars[] = "@";
850 /* This array holds the chars that only start a comment at the beginning of
851 a line. If the line seems to have the form '# 123 filename'
852 .line and .file directives will appear in the pre-processed output. */
853 /* Note that input_file.c hand checks for '#' at the beginning of the
854 first line of the input file. This is because the compiler outputs
855 #NO_APP at the beginning of its output. */
856 /* Also note that comments like this one will always work. */
857 const char line_comment_chars[] = "#";
859 const char line_separator_chars[] = ";";
861 /* Chars that can be used to separate mant
862 from exp in floating point numbers. */
863 const char EXP_CHARS[] = "eE";
865 /* Chars that mean this number is a floating point constant. */
869 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
871 /* Prefix characters that indicate the start of an immediate
873 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
875 /* Separator character handling. */
877 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
880 skip_past_char (char ** str, char c)
891 #define skip_past_comma(str) skip_past_char (str, ',')
893 /* Arithmetic expressions (possibly involving symbols). */
895 /* Return TRUE if anything in the expression is a bignum. */
898 walk_no_bignums (symbolS * sp)
900 if (symbol_get_value_expression (sp)->X_op == O_big)
903 if (symbol_get_value_expression (sp)->X_add_symbol)
905 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
906 || (symbol_get_value_expression (sp)->X_op_symbol
907 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
913 static int in_my_get_expression = 0;
915 /* Third argument to my_get_expression. */
916 #define GE_NO_PREFIX 0
917 #define GE_IMM_PREFIX 1
918 #define GE_OPT_PREFIX 2
919 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
920 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
921 #define GE_OPT_PREFIX_BIG 3
924 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
929 /* In unified syntax, all prefixes are optional. */
931 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
936 case GE_NO_PREFIX: break;
938 if (!is_immediate_prefix (**str))
940 inst.error = _("immediate expression requires a # prefix");
946 case GE_OPT_PREFIX_BIG:
947 if (is_immediate_prefix (**str))
953 memset (ep, 0, sizeof (expressionS));
955 save_in = input_line_pointer;
956 input_line_pointer = *str;
957 in_my_get_expression = 1;
958 seg = expression (ep);
959 in_my_get_expression = 0;
961 if (ep->X_op == O_illegal || ep->X_op == O_absent)
963 /* We found a bad or missing expression in md_operand(). */
964 *str = input_line_pointer;
965 input_line_pointer = save_in;
966 if (inst.error == NULL)
967 inst.error = (ep->X_op == O_absent
968 ? _("missing expression") :_("bad expression"));
973 if (seg != absolute_section
974 && seg != text_section
975 && seg != data_section
976 && seg != bss_section
977 && seg != undefined_section)
979 inst.error = _("bad segment");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
988 /* Get rid of any bignums now, so that we don't generate an error for which
989 we can't establish a line number later on. Big numbers are never valid
990 in instructions, which is where this routine is always called. */
991 if (prefix_mode != GE_OPT_PREFIX_BIG
992 && (ep->X_op == O_big
994 && (walk_no_bignums (ep->X_add_symbol)
996 && walk_no_bignums (ep->X_op_symbol))))))
998 inst.error = _("invalid constant");
999 *str = input_line_pointer;
1000 input_line_pointer = save_in;
1004 *str = input_line_pointer;
1005 input_line_pointer = save_in;
1009 /* Turn a string in input_line_pointer into a floating point constant
1010 of type TYPE, and store the appropriate bytes in *LITP. The number
1011 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1012 returned, or NULL on OK.
1014 Note that fp constants aren't represent in the normal way on the ARM.
1015 In big endian mode, things are as expected. However, in little endian
1016 mode fp constants are big-endian word-wise, and little-endian byte-wise
1017 within the words. For example, (double) 1.1 in big endian mode is
1018 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1019 the byte sequence 99 99 f1 3f 9a 99 99 99.
1021 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1024 md_atof (int type, char * litP, int * sizeP)
1027 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1059 return _("Unrecognized or unsupported floating point constant");
1062 t = atof_ieee (input_line_pointer, type, words);
1064 input_line_pointer = t;
1065 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1067 if (target_big_endian)
1069 for (i = 0; i < prec; i++)
1071 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1072 litP += sizeof (LITTLENUM_TYPE);
1077 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1078 for (i = prec - 1; i >= 0; i--)
1080 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1081 litP += sizeof (LITTLENUM_TYPE);
1084 /* For a 4 byte float the order of elements in `words' is 1 0.
1085 For an 8 byte float the order is 1 0 3 2. */
1086 for (i = 0; i < prec; i += 2)
1088 md_number_to_chars (litP, (valueT) words[i + 1],
1089 sizeof (LITTLENUM_TYPE));
1090 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1091 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += 2 * sizeof (LITTLENUM_TYPE);
1099 /* We handle all bad expressions here, so that we can report the faulty
1100 instruction in the error message. */
1102 md_operand (expressionS * exp)
1104 if (in_my_get_expression)
1105 exp->X_op = O_illegal;
1108 /* Immediate values. */
1110 /* Generic immediate-value read function for use in directives.
1111 Accepts anything that 'expression' can fold to a constant.
1112 *val receives the number. */
1115 immediate_for_directive (int *val)
1118 exp.X_op = O_illegal;
1120 if (is_immediate_prefix (*input_line_pointer))
1122 input_line_pointer++;
1126 if (exp.X_op != O_constant)
1128 as_bad (_("expected #constant"));
1129 ignore_rest_of_line ();
1132 *val = exp.X_add_number;
1137 /* Register parsing. */
1139 /* Generic register parser. CCP points to what should be the
1140 beginning of a register name. If it is indeed a valid register
1141 name, advance CCP over it and return the reg_entry structure;
1142 otherwise return NULL. Does not issue diagnostics. */
1144 static struct reg_entry *
1145 arm_reg_parse_multi (char **ccp)
1149 struct reg_entry *reg;
1151 #ifdef REGISTER_PREFIX
1152 if (*start != REGISTER_PREFIX)
1156 #ifdef OPTIONAL_REGISTER_PREFIX
1157 if (*start == OPTIONAL_REGISTER_PREFIX)
1162 if (!ISALPHA (*p) || !is_name_beginner (*p))
1167 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1169 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1179 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1180 enum arm_reg_type type)
1182 /* Alternative syntaxes are accepted for a few register classes. */
1189 /* Generic coprocessor register names are allowed for these. */
1190 if (reg && reg->type == REG_TYPE_CN)
1195 /* For backward compatibility, a bare number is valid here. */
1197 unsigned long processor = strtoul (start, ccp, 10);
1198 if (*ccp != start && processor <= 15)
1202 case REG_TYPE_MMXWC:
1203 /* WC includes WCG. ??? I'm not sure this is true for all
1204 instructions that take WC registers. */
1205 if (reg && reg->type == REG_TYPE_MMXWCG)
1216 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1217 return value is the register number or FAIL. */
1220 arm_reg_parse (char **ccp, enum arm_reg_type type)
1223 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1226 /* Do not allow a scalar (reg+index) to parse as a register. */
1227 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1230 if (reg && reg->type == type)
1233 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1240 /* Parse a Neon type specifier. *STR should point at the leading '.'
1241 character. Does no verification at this stage that the type fits the opcode
1248 Can all be legally parsed by this function.
1250 Fills in neon_type struct pointer with parsed information, and updates STR
1251 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1252 type, FAIL if not. */
1255 parse_neon_type (struct neon_type *type, char **str)
1262 while (type->elems < NEON_MAX_TYPE_ELS)
1264 enum neon_el_type thistype = NT_untyped;
1265 unsigned thissize = -1u;
1272 /* Just a size without an explicit type. */
1276 switch (TOLOWER (*ptr))
1278 case 'i': thistype = NT_integer; break;
1279 case 'f': thistype = NT_float; break;
1280 case 'p': thistype = NT_poly; break;
1281 case 's': thistype = NT_signed; break;
1282 case 'u': thistype = NT_unsigned; break;
1284 thistype = NT_float;
1289 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1295 /* .f is an abbreviation for .f32. */
1296 if (thistype == NT_float && !ISDIGIT (*ptr))
1301 thissize = strtoul (ptr, &ptr, 10);
1303 if (thissize != 8 && thissize != 16 && thissize != 32
1306 as_bad (_("bad size %d in type specifier"), thissize);
1314 type->el[type->elems].type = thistype;
1315 type->el[type->elems].size = thissize;
1320 /* Empty/missing type is not a successful parse. */
1321 if (type->elems == 0)
1329 /* Errors may be set multiple times during parsing or bit encoding
1330 (particularly in the Neon bits), but usually the earliest error which is set
1331 will be the most meaningful. Avoid overwriting it with later (cascading)
1332 errors by calling this function. */
1335 first_error (const char *err)
1341 /* Parse a single type, e.g. ".s32", leading period included. */
1343 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1346 struct neon_type optype;
1350 if (parse_neon_type (&optype, &str) == SUCCESS)
1352 if (optype.elems == 1)
1353 *vectype = optype.el[0];
1356 first_error (_("only one type should be specified for operand"));
1362 first_error (_("vector type expected"));
1374 /* Special meanings for indices (which have a range of 0-7), which will fit into
1377 #define NEON_ALL_LANES 15
1378 #define NEON_INTERLEAVE_LANES 14
1380 /* Parse either a register or a scalar, with an optional type. Return the
1381 register number, and optionally fill in the actual type of the register
1382 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1383 type/index information in *TYPEINFO. */
1386 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1387 enum arm_reg_type *rtype,
1388 struct neon_typed_alias *typeinfo)
1391 struct reg_entry *reg = arm_reg_parse_multi (&str);
1392 struct neon_typed_alias atype;
1393 struct neon_type_el parsetype;
1397 atype.eltype.type = NT_invtype;
1398 atype.eltype.size = -1;
1400 /* Try alternate syntax for some types of register. Note these are mutually
1401 exclusive with the Neon syntax extensions. */
1404 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1412 /* Undo polymorphism when a set of register types may be accepted. */
1413 if ((type == REG_TYPE_NDQ
1414 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1415 || (type == REG_TYPE_VFSD
1416 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1417 || (type == REG_TYPE_NSDQ
1418 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1419 || reg->type == REG_TYPE_NQ))
1420 || (type == REG_TYPE_MMXWC
1421 && (reg->type == REG_TYPE_MMXWCG)))
1422 type = (enum arm_reg_type) reg->type;
1424 if (type != reg->type)
1430 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1432 if ((atype.defined & NTA_HASTYPE) != 0)
1434 first_error (_("can't redefine type for operand"));
1437 atype.defined |= NTA_HASTYPE;
1438 atype.eltype = parsetype;
1441 if (skip_past_char (&str, '[') == SUCCESS)
1443 if (type != REG_TYPE_VFD)
1445 first_error (_("only D registers may be indexed"));
1449 if ((atype.defined & NTA_HASINDEX) != 0)
1451 first_error (_("can't change index for operand"));
1455 atype.defined |= NTA_HASINDEX;
1457 if (skip_past_char (&str, ']') == SUCCESS)
1458 atype.index = NEON_ALL_LANES;
1463 my_get_expression (&exp, &str, GE_NO_PREFIX);
1465 if (exp.X_op != O_constant)
1467 first_error (_("constant expression required"));
1471 if (skip_past_char (&str, ']') == FAIL)
1474 atype.index = exp.X_add_number;
1489 /* Like arm_reg_parse, but allow allow the following extra features:
1490 - If RTYPE is non-zero, return the (possibly restricted) type of the
1491 register (e.g. Neon double or quad reg when either has been requested).
1492 - If this is a Neon vector type with additional type information, fill
1493 in the struct pointed to by VECTYPE (if non-NULL).
1494 This function will fault on encountering a scalar. */
1497 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1498 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1500 struct neon_typed_alias atype;
1502 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1507 /* Do not allow regname(... to parse as a register. */
1511 /* Do not allow a scalar (reg+index) to parse as a register. */
1512 if ((atype.defined & NTA_HASINDEX) != 0)
1514 first_error (_("register operand expected, but got scalar"));
1519 *vectype = atype.eltype;
1526 #define NEON_SCALAR_REG(X) ((X) >> 4)
1527 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1529 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1530 have enough information to be able to do a good job bounds-checking. So, we
1531 just do easy checks here, and do further checks later. */
1534 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1538 struct neon_typed_alias atype;
1540 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1542 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1545 if (atype.index == NEON_ALL_LANES)
1547 first_error (_("scalar must have an index"));
1550 else if (atype.index >= 64 / elsize)
1552 first_error (_("scalar index out of range"));
1557 *type = atype.eltype;
1561 return reg * 16 + atype.index;
1564 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1567 parse_reg_list (char ** strp)
1569 char * str = * strp;
1573 /* We come back here if we get ranges concatenated by '+' or '|'. */
1588 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1590 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1600 first_error (_("bad range in register list"));
1604 for (i = cur_reg + 1; i < reg; i++)
1606 if (range & (1 << i))
1608 (_("Warning: duplicated register (r%d) in register list"),
1616 if (range & (1 << reg))
1617 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1619 else if (reg <= cur_reg)
1620 as_tsktsk (_("Warning: register range not in ascending order"));
1625 while (skip_past_comma (&str) != FAIL
1626 || (in_range = 1, *str++ == '-'));
1631 first_error (_("missing `}'"));
1639 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1642 if (exp.X_op == O_constant)
1644 if (exp.X_add_number
1645 != (exp.X_add_number & 0x0000ffff))
1647 inst.error = _("invalid register mask");
1651 if ((range & exp.X_add_number) != 0)
1653 int regno = range & exp.X_add_number;
1656 regno = (1 << regno) - 1;
1658 (_("Warning: duplicated register (r%d) in register list"),
1662 range |= exp.X_add_number;
1666 if (inst.reloc.type != 0)
1668 inst.error = _("expression too complex");
1672 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1673 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1674 inst.reloc.pc_rel = 0;
1678 if (*str == '|' || *str == '+')
1684 while (another_range);
1690 /* Types of registers in a list. */
1699 /* Parse a VFP register list. If the string is invalid return FAIL.
1700 Otherwise return the number of registers, and set PBASE to the first
1701 register. Parses registers of type ETYPE.
1702 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1703 - Q registers can be used to specify pairs of D registers
1704 - { } can be omitted from around a singleton register list
1705 FIXME: This is not implemented, as it would require backtracking in
1708 This could be done (the meaning isn't really ambiguous), but doesn't
1709 fit in well with the current parsing framework.
1710 - 32 D registers may be used (also true for VFPv3).
1711 FIXME: Types are ignored in these register lists, which is probably a
1715 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1720 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1724 unsigned long mask = 0;
1729 inst.error = _("expecting {");
1738 regtype = REG_TYPE_VFS;
1743 regtype = REG_TYPE_VFD;
1746 case REGLIST_NEON_D:
1747 regtype = REG_TYPE_NDQ;
1751 if (etype != REGLIST_VFP_S)
1753 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1754 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1758 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1761 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1768 base_reg = max_regs;
1772 int setmask = 1, addregs = 1;
1774 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1776 if (new_base == FAIL)
1778 first_error (_(reg_expected_msgs[regtype]));
1782 if (new_base >= max_regs)
1784 first_error (_("register out of range in list"));
1788 /* Note: a value of 2 * n is returned for the register Q<n>. */
1789 if (regtype == REG_TYPE_NQ)
1795 if (new_base < base_reg)
1796 base_reg = new_base;
1798 if (mask & (setmask << new_base))
1800 first_error (_("invalid register list"));
1804 if ((mask >> new_base) != 0 && ! warned)
1806 as_tsktsk (_("register list not in ascending order"));
1810 mask |= setmask << new_base;
1813 if (*str == '-') /* We have the start of a range expression */
1819 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1822 inst.error = gettext (reg_expected_msgs[regtype]);
1826 if (high_range >= max_regs)
1828 first_error (_("register out of range in list"));
1832 if (regtype == REG_TYPE_NQ)
1833 high_range = high_range + 1;
1835 if (high_range <= new_base)
1837 inst.error = _("register range not in ascending order");
1841 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1843 if (mask & (setmask << new_base))
1845 inst.error = _("invalid register list");
1849 mask |= setmask << new_base;
1854 while (skip_past_comma (&str) != FAIL);
1858 /* Sanity check -- should have raised a parse error above. */
1859 if (count == 0 || count > max_regs)
1864 /* Final test -- the registers must be consecutive. */
1866 for (i = 0; i < count; i++)
1868 if ((mask & (1u << i)) == 0)
1870 inst.error = _("non-contiguous register range");
1880 /* True if two alias types are the same. */
1883 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1891 if (a->defined != b->defined)
1894 if ((a->defined & NTA_HASTYPE) != 0
1895 && (a->eltype.type != b->eltype.type
1896 || a->eltype.size != b->eltype.size))
1899 if ((a->defined & NTA_HASINDEX) != 0
1900 && (a->index != b->index))
1906 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1907 The base register is put in *PBASE.
1908 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1910 The register stride (minus one) is put in bit 4 of the return value.
1911 Bits [6:5] encode the list length (minus one).
1912 The type of the list elements is put in *ELTYPE, if non-NULL. */
1914 #define NEON_LANE(X) ((X) & 0xf)
1915 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1916 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1919 parse_neon_el_struct_list (char **str, unsigned *pbase,
1920 struct neon_type_el *eltype)
1927 int leading_brace = 0;
1928 enum arm_reg_type rtype = REG_TYPE_NDQ;
1929 const char *const incr_error = _("register stride must be 1 or 2");
1930 const char *const type_error = _("mismatched element/structure types in list");
1931 struct neon_typed_alias firsttype;
1933 if (skip_past_char (&ptr, '{') == SUCCESS)
1938 struct neon_typed_alias atype;
1939 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1943 first_error (_(reg_expected_msgs[rtype]));
1950 if (rtype == REG_TYPE_NQ)
1956 else if (reg_incr == -1)
1958 reg_incr = getreg - base_reg;
1959 if (reg_incr < 1 || reg_incr > 2)
1961 first_error (_(incr_error));
1965 else if (getreg != base_reg + reg_incr * count)
1967 first_error (_(incr_error));
1971 if (! neon_alias_types_same (&atype, &firsttype))
1973 first_error (_(type_error));
1977 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1981 struct neon_typed_alias htype;
1982 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1984 lane = NEON_INTERLEAVE_LANES;
1985 else if (lane != NEON_INTERLEAVE_LANES)
1987 first_error (_(type_error));
1992 else if (reg_incr != 1)
1994 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1998 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2001 first_error (_(reg_expected_msgs[rtype]));
2004 if (! neon_alias_types_same (&htype, &firsttype))
2006 first_error (_(type_error));
2009 count += hireg + dregs - getreg;
2013 /* If we're using Q registers, we can't use [] or [n] syntax. */
2014 if (rtype == REG_TYPE_NQ)
2020 if ((atype.defined & NTA_HASINDEX) != 0)
2024 else if (lane != atype.index)
2026 first_error (_(type_error));
2030 else if (lane == -1)
2031 lane = NEON_INTERLEAVE_LANES;
2032 else if (lane != NEON_INTERLEAVE_LANES)
2034 first_error (_(type_error));
2039 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2041 /* No lane set by [x]. We must be interleaving structures. */
2043 lane = NEON_INTERLEAVE_LANES;
2046 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2047 || (count > 1 && reg_incr == -1))
2049 first_error (_("error parsing element/structure list"));
2053 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2055 first_error (_("expected }"));
2063 *eltype = firsttype.eltype;
2068 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2071 /* Parse an explicit relocation suffix on an expression. This is
2072 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2073 arm_reloc_hsh contains no entries, so this function can only
2074 succeed if there is no () after the word. Returns -1 on error,
2075 BFD_RELOC_UNUSED if there wasn't any suffix. */
2078 parse_reloc (char **str)
2080 struct reloc_entry *r;
2084 return BFD_RELOC_UNUSED;
2089 while (*q && *q != ')' && *q != ',')
2094 if ((r = (struct reloc_entry *)
2095 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2102 /* Directives: register aliases. */
2104 static struct reg_entry *
2105 insert_reg_alias (char *str, unsigned number, int type)
2107 struct reg_entry *new_reg;
2110 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2112 if (new_reg->builtin)
2113 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2115 /* Only warn about a redefinition if it's not defined as the
2117 else if (new_reg->number != number || new_reg->type != type)
2118 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2123 name = xstrdup (str);
2124 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2126 new_reg->name = name;
2127 new_reg->number = number;
2128 new_reg->type = type;
2129 new_reg->builtin = FALSE;
2130 new_reg->neon = NULL;
2132 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2139 insert_neon_reg_alias (char *str, int number, int type,
2140 struct neon_typed_alias *atype)
2142 struct reg_entry *reg = insert_reg_alias (str, number, type);
2146 first_error (_("attempt to redefine typed alias"));
2152 reg->neon = (struct neon_typed_alias *)
2153 xmalloc (sizeof (struct neon_typed_alias));
2154 *reg->neon = *atype;
2158 /* Look for the .req directive. This is of the form:
2160 new_register_name .req existing_register_name
2162 If we find one, or if it looks sufficiently like one that we want to
2163 handle any error here, return TRUE. Otherwise return FALSE. */
2166 create_register_alias (char * newname, char *p)
2168 struct reg_entry *old;
2169 char *oldname, *nbuf;
2172 /* The input scrubber ensures that whitespace after the mnemonic is
2173 collapsed to single spaces. */
2175 if (strncmp (oldname, " .req ", 6) != 0)
2179 if (*oldname == '\0')
2182 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2185 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2189 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2190 the desired alias name, and p points to its end. If not, then
2191 the desired alias name is in the global original_case_string. */
2192 #ifdef TC_CASE_SENSITIVE
2195 newname = original_case_string;
2196 nlen = strlen (newname);
2199 nbuf = (char *) alloca (nlen + 1);
2200 memcpy (nbuf, newname, nlen);
2203 /* Create aliases under the new name as stated; an all-lowercase
2204 version of the new name; and an all-uppercase version of the new
2206 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2208 for (p = nbuf; *p; p++)
2211 if (strncmp (nbuf, newname, nlen))
2213 /* If this attempt to create an additional alias fails, do not bother
2214 trying to create the all-lower case alias. We will fail and issue
2215 a second, duplicate error message. This situation arises when the
2216 programmer does something like:
2219 The second .req creates the "Foo" alias but then fails to create
2220 the artificial FOO alias because it has already been created by the
2222 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2226 for (p = nbuf; *p; p++)
2229 if (strncmp (nbuf, newname, nlen))
2230 insert_reg_alias (nbuf, old->number, old->type);
2236 /* Create a Neon typed/indexed register alias using directives, e.g.:
2241 These typed registers can be used instead of the types specified after the
2242 Neon mnemonic, so long as all operands given have types. Types can also be
2243 specified directly, e.g.:
2244 vadd d0.s32, d1.s32, d2.s32 */
2247 create_neon_reg_alias (char *newname, char *p)
2249 enum arm_reg_type basetype;
2250 struct reg_entry *basereg;
2251 struct reg_entry mybasereg;
2252 struct neon_type ntype;
2253 struct neon_typed_alias typeinfo;
2254 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2257 typeinfo.defined = 0;
2258 typeinfo.eltype.type = NT_invtype;
2259 typeinfo.eltype.size = -1;
2260 typeinfo.index = -1;
2264 if (strncmp (p, " .dn ", 5) == 0)
2265 basetype = REG_TYPE_VFD;
2266 else if (strncmp (p, " .qn ", 5) == 0)
2267 basetype = REG_TYPE_NQ;
2276 basereg = arm_reg_parse_multi (&p);
2278 if (basereg && basereg->type != basetype)
2280 as_bad (_("bad type for register"));
2284 if (basereg == NULL)
2287 /* Try parsing as an integer. */
2288 my_get_expression (&exp, &p, GE_NO_PREFIX);
2289 if (exp.X_op != O_constant)
2291 as_bad (_("expression must be constant"));
2294 basereg = &mybasereg;
2295 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2301 typeinfo = *basereg->neon;
2303 if (parse_neon_type (&ntype, &p) == SUCCESS)
2305 /* We got a type. */
2306 if (typeinfo.defined & NTA_HASTYPE)
2308 as_bad (_("can't redefine the type of a register alias"));
2312 typeinfo.defined |= NTA_HASTYPE;
2313 if (ntype.elems != 1)
2315 as_bad (_("you must specify a single type only"));
2318 typeinfo.eltype = ntype.el[0];
2321 if (skip_past_char (&p, '[') == SUCCESS)
2324 /* We got a scalar index. */
2326 if (typeinfo.defined & NTA_HASINDEX)
2328 as_bad (_("can't redefine the index of a scalar alias"));
2332 my_get_expression (&exp, &p, GE_NO_PREFIX);
2334 if (exp.X_op != O_constant)
2336 as_bad (_("scalar index must be constant"));
2340 typeinfo.defined |= NTA_HASINDEX;
2341 typeinfo.index = exp.X_add_number;
2343 if (skip_past_char (&p, ']') == FAIL)
2345 as_bad (_("expecting ]"));
2350 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2351 the desired alias name, and p points to its end. If not, then
2352 the desired alias name is in the global original_case_string. */
2353 #ifdef TC_CASE_SENSITIVE
2354 namelen = nameend - newname;
2356 newname = original_case_string;
2357 namelen = strlen (newname);
2360 namebuf = (char *) alloca (namelen + 1);
2361 strncpy (namebuf, newname, namelen);
2362 namebuf[namelen] = '\0';
2364 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2365 typeinfo.defined != 0 ? &typeinfo : NULL);
2367 /* Insert name in all uppercase. */
2368 for (p = namebuf; *p; p++)
2371 if (strncmp (namebuf, newname, namelen))
2372 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2373 typeinfo.defined != 0 ? &typeinfo : NULL);
2375 /* Insert name in all lowercase. */
2376 for (p = namebuf; *p; p++)
2379 if (strncmp (namebuf, newname, namelen))
2380 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2381 typeinfo.defined != 0 ? &typeinfo : NULL);
2386 /* Should never be called, as .req goes between the alias and the
2387 register name, not at the beginning of the line. */
2390 s_req (int a ATTRIBUTE_UNUSED)
2392 as_bad (_("invalid syntax for .req directive"));
2396 s_dn (int a ATTRIBUTE_UNUSED)
2398 as_bad (_("invalid syntax for .dn directive"));
2402 s_qn (int a ATTRIBUTE_UNUSED)
2404 as_bad (_("invalid syntax for .qn directive"));
2407 /* The .unreq directive deletes an alias which was previously defined
2408 by .req. For example:
2414 s_unreq (int a ATTRIBUTE_UNUSED)
2419 name = input_line_pointer;
2421 while (*input_line_pointer != 0
2422 && *input_line_pointer != ' '
2423 && *input_line_pointer != '\n')
2424 ++input_line_pointer;
2426 saved_char = *input_line_pointer;
2427 *input_line_pointer = 0;
2430 as_bad (_("invalid syntax for .unreq directive"));
2433 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2437 as_bad (_("unknown register alias '%s'"), name);
2438 else if (reg->builtin)
2439 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2446 hash_delete (arm_reg_hsh, name, FALSE);
2447 free ((char *) reg->name);
2452 /* Also locate the all upper case and all lower case versions.
2453 Do not complain if we cannot find one or the other as it
2454 was probably deleted above. */
2456 nbuf = strdup (name);
2457 for (p = nbuf; *p; p++)
2459 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2462 hash_delete (arm_reg_hsh, nbuf, FALSE);
2463 free ((char *) reg->name);
2469 for (p = nbuf; *p; p++)
2471 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2474 hash_delete (arm_reg_hsh, nbuf, FALSE);
2475 free ((char *) reg->name);
2485 *input_line_pointer = saved_char;
2486 demand_empty_rest_of_line ();
2489 /* Directives: Instruction set selection. */
2492 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2493 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2494 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2495 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2497 /* Create a new mapping symbol for the transition to STATE. */
2500 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2503 const char * symname;
2510 type = BSF_NO_FLAGS;
2514 type = BSF_NO_FLAGS;
2518 type = BSF_NO_FLAGS;
2524 symbolP = symbol_new (symname, now_seg, value, frag);
2525 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2530 THUMB_SET_FUNC (symbolP, 0);
2531 ARM_SET_THUMB (symbolP, 0);
2532 ARM_SET_INTERWORK (symbolP, support_interwork);
2536 THUMB_SET_FUNC (symbolP, 1);
2537 ARM_SET_THUMB (symbolP, 1);
2538 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 /* Save the mapping symbols for future reference. Also check that
2547 we do not place two mapping symbols at the same offset within a
2548 frag. We'll handle overlap between frags in
2549 check_mapping_symbols.
2551 If .fill or other data filling directive generates zero sized data,
2552 the mapping symbol for the following code will have the same value
2553 as the one generated for the data filling directive. In this case,
2554 we replace the old symbol with the new one at the same address. */
2557 if (frag->tc_frag_data.first_map != NULL)
2559 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2560 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2562 frag->tc_frag_data.first_map = symbolP;
2564 if (frag->tc_frag_data.last_map != NULL)
2566 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2567 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2568 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2570 frag->tc_frag_data.last_map = symbolP;
2573 /* We must sometimes convert a region marked as code to data during
2574 code alignment, if an odd number of bytes have to be padded. The
2575 code mapping symbol is pushed to an aligned address. */
2578 insert_data_mapping_symbol (enum mstate state,
2579 valueT value, fragS *frag, offsetT bytes)
2581 /* If there was already a mapping symbol, remove it. */
2582 if (frag->tc_frag_data.last_map != NULL
2583 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2585 symbolS *symp = frag->tc_frag_data.last_map;
2589 know (frag->tc_frag_data.first_map == symp);
2590 frag->tc_frag_data.first_map = NULL;
2592 frag->tc_frag_data.last_map = NULL;
2593 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2596 make_mapping_symbol (MAP_DATA, value, frag);
2597 make_mapping_symbol (state, value + bytes, frag);
2600 static void mapping_state_2 (enum mstate state, int max_chars);
2602 /* Set the mapping state to STATE. Only call this when about to
2603 emit some STATE bytes to the file. */
2606 mapping_state (enum mstate state)
2608 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2610 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2612 if (mapstate == state)
2613 /* The mapping symbol has already been emitted.
2614 There is nothing else to do. */
2617 if (state == MAP_ARM || state == MAP_THUMB)
2619 All ARM instructions require 4-byte alignment.
2620 (Almost) all Thumb instructions require 2-byte alignment.
2622 When emitting instructions into any section, mark the section
2625 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2626 but themselves require 2-byte alignment; this applies to some
2627 PC- relative forms. However, these cases will invovle implicit
2628 literal pool generation or an explicit .align >=2, both of
2629 which will cause the section to me marked with sufficient
2630 alignment. Thus, we don't handle those cases here. */
2631 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2633 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2634 /* This case will be evaluated later in the next else. */
2636 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2637 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2639 /* Only add the symbol if the offset is > 0:
2640 if we're at the first frag, check it's size > 0;
2641 if we're not at the first frag, then for sure
2642 the offset is > 0. */
2643 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2644 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2647 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2650 mapping_state_2 (state, 0);
2654 /* Same as mapping_state, but MAX_CHARS bytes have already been
2655 allocated. Put the mapping symbol that far back. */
2658 mapping_state_2 (enum mstate state, int max_chars)
2660 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2662 if (!SEG_NORMAL (now_seg))
2665 if (mapstate == state)
2666 /* The mapping symbol has already been emitted.
2667 There is nothing else to do. */
2670 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2671 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2674 #define mapping_state(x) ((void)0)
2675 #define mapping_state_2(x, y) ((void)0)
2678 /* Find the real, Thumb encoded start of a Thumb function. */
2682 find_real_start (symbolS * symbolP)
2685 const char * name = S_GET_NAME (symbolP);
2686 symbolS * new_target;
2688 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2689 #define STUB_NAME ".real_start_of"
2694 /* The compiler may generate BL instructions to local labels because
2695 it needs to perform a branch to a far away location. These labels
2696 do not have a corresponding ".real_start_of" label. We check
2697 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2698 the ".real_start_of" convention for nonlocal branches. */
2699 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2702 real_start = ACONCAT ((STUB_NAME, name, NULL));
2703 new_target = symbol_find (real_start);
2705 if (new_target == NULL)
2707 as_warn (_("Failed to find real start of function: %s\n"), name);
2708 new_target = symbolP;
2716 opcode_select (int width)
2723 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2724 as_bad (_("selected processor does not support THUMB opcodes"));
2727 /* No need to force the alignment, since we will have been
2728 coming from ARM mode, which is word-aligned. */
2729 record_alignment (now_seg, 1);
2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2737 as_bad (_("selected processor does not support ARM opcodes"));
2742 frag_align (2, 0, 0);
2744 record_alignment (now_seg, 1);
2749 as_bad (_("invalid instruction size selected (%d)"), width);
2754 s_arm (int ignore ATTRIBUTE_UNUSED)
2757 demand_empty_rest_of_line ();
2761 s_thumb (int ignore ATTRIBUTE_UNUSED)
2764 demand_empty_rest_of_line ();
2768 s_code (int unused ATTRIBUTE_UNUSED)
2772 temp = get_absolute_expression ();
2777 opcode_select (temp);
2781 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2786 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2788 /* If we are not already in thumb mode go into it, EVEN if
2789 the target processor does not support thumb instructions.
2790 This is used by gcc/config/arm/lib1funcs.asm for example
2791 to compile interworking support functions even if the
2792 target processor should not support interworking. */
2796 record_alignment (now_seg, 1);
2799 demand_empty_rest_of_line ();
2803 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2807 /* The following label is the name/address of the start of a Thumb function.
2808 We need to know this for the interworking support. */
2809 label_is_thumb_function_name = TRUE;
2812 /* Perform a .set directive, but also mark the alias as
2813 being a thumb function. */
2816 s_thumb_set (int equiv)
2818 /* XXX the following is a duplicate of the code for s_set() in read.c
2819 We cannot just call that code as we need to get at the symbol that
2826 /* Especial apologies for the random logic:
2827 This just grew, and could be parsed much more simply!
2829 name = input_line_pointer;
2830 delim = get_symbol_end ();
2831 end_name = input_line_pointer;
2834 if (*input_line_pointer != ',')
2837 as_bad (_("expected comma after name \"%s\""), name);
2839 ignore_rest_of_line ();
2843 input_line_pointer++;
2846 if (name[0] == '.' && name[1] == '\0')
2848 /* XXX - this should not happen to .thumb_set. */
2852 if ((symbolP = symbol_find (name)) == NULL
2853 && (symbolP = md_undefined_symbol (name)) == NULL)
2856 /* When doing symbol listings, play games with dummy fragments living
2857 outside the normal fragment chain to record the file and line info
2859 if (listing & LISTING_SYMBOLS)
2861 extern struct list_info_struct * listing_tail;
2862 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2864 memset (dummy_frag, 0, sizeof (fragS));
2865 dummy_frag->fr_type = rs_fill;
2866 dummy_frag->line = listing_tail;
2867 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2868 dummy_frag->fr_symbol = symbolP;
2872 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2875 /* "set" symbols are local unless otherwise specified. */
2876 SF_SET_LOCAL (symbolP);
2877 #endif /* OBJ_COFF */
2878 } /* Make a new symbol. */
2880 symbol_table_insert (symbolP);
2885 && S_IS_DEFINED (symbolP)
2886 && S_GET_SEGMENT (symbolP) != reg_section)
2887 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2889 pseudo_set (symbolP);
2891 demand_empty_rest_of_line ();
2893 /* XXX Now we come to the Thumb specific bit of code. */
2895 THUMB_SET_FUNC (symbolP, 1);
2896 ARM_SET_THUMB (symbolP, 1);
2897 #if defined OBJ_ELF || defined OBJ_COFF
2898 ARM_SET_INTERWORK (symbolP, support_interwork);
2902 /* Directives: Mode selection. */
2904 /* .syntax [unified|divided] - choose the new unified syntax
2905 (same for Arm and Thumb encoding, modulo slight differences in what
2906 can be represented) or the old divergent syntax for each mode. */
2908 s_syntax (int unused ATTRIBUTE_UNUSED)
2912 name = input_line_pointer;
2913 delim = get_symbol_end ();
2915 if (!strcasecmp (name, "unified"))
2916 unified_syntax = TRUE;
2917 else if (!strcasecmp (name, "divided"))
2918 unified_syntax = FALSE;
2921 as_bad (_("unrecognized syntax mode \"%s\""), name);
2924 *input_line_pointer = delim;
2925 demand_empty_rest_of_line ();
2928 /* Directives: sectioning and alignment. */
2930 /* Same as s_align_ptwo but align 0 => align 2. */
2933 s_align (int unused ATTRIBUTE_UNUSED)
2938 long max_alignment = 15;
2940 temp = get_absolute_expression ();
2941 if (temp > max_alignment)
2942 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2945 as_bad (_("alignment negative. 0 assumed."));
2949 if (*input_line_pointer == ',')
2951 input_line_pointer++;
2952 temp_fill = get_absolute_expression ();
2964 /* Only make a frag if we HAVE to. */
2965 if (temp && !need_pass_2)
2967 if (!fill_p && subseg_text_p (now_seg))
2968 frag_align_code (temp, 0);
2970 frag_align (temp, (int) temp_fill, 0);
2972 demand_empty_rest_of_line ();
2974 record_alignment (now_seg, temp);
2978 s_bss (int ignore ATTRIBUTE_UNUSED)
2980 /* We don't support putting frags in the BSS segment, we fake it by
2981 marking in_bss, then looking at s_skip for clues. */
2982 subseg_set (bss_section, 0);
2983 demand_empty_rest_of_line ();
2985 #ifdef md_elf_section_change_hook
2986 md_elf_section_change_hook ();
2991 s_even (int ignore ATTRIBUTE_UNUSED)
2993 /* Never make frag if expect extra pass. */
2995 frag_align (1, 0, 0);
2997 record_alignment (now_seg, 1);
2999 demand_empty_rest_of_line ();
3002 /* Directives: Literal pools. */
3004 static literal_pool *
3005 find_literal_pool (void)
3007 literal_pool * pool;
3009 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3011 if (pool->section == now_seg
3012 && pool->sub_section == now_subseg)
3019 static literal_pool *
3020 find_or_make_literal_pool (void)
3022 /* Next literal pool ID number. */
3023 static unsigned int latest_pool_num = 1;
3024 literal_pool * pool;
3026 pool = find_literal_pool ();
3030 /* Create a new pool. */
3031 pool = (literal_pool *) xmalloc (sizeof (* pool));
3035 pool->next_free_entry = 0;
3036 pool->section = now_seg;
3037 pool->sub_section = now_subseg;
3038 pool->next = list_of_pools;
3039 pool->symbol = NULL;
3041 /* Add it to the list. */
3042 list_of_pools = pool;
3045 /* New pools, and emptied pools, will have a NULL symbol. */
3046 if (pool->symbol == NULL)
3048 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3049 (valueT) 0, &zero_address_frag);
3050 pool->id = latest_pool_num ++;
3057 /* Add the literal in the global 'inst'
3058 structure to the relevant literal pool. */
3061 add_to_lit_pool (void)
3063 literal_pool * pool;
3066 pool = find_or_make_literal_pool ();
3068 /* Check if this literal value is already in the pool. */
3069 for (entry = 0; entry < pool->next_free_entry; entry ++)
3071 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3072 && (inst.reloc.exp.X_op == O_constant)
3073 && (pool->literals[entry].X_add_number
3074 == inst.reloc.exp.X_add_number)
3075 && (pool->literals[entry].X_unsigned
3076 == inst.reloc.exp.X_unsigned))
3079 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3080 && (inst.reloc.exp.X_op == O_symbol)
3081 && (pool->literals[entry].X_add_number
3082 == inst.reloc.exp.X_add_number)
3083 && (pool->literals[entry].X_add_symbol
3084 == inst.reloc.exp.X_add_symbol)
3085 && (pool->literals[entry].X_op_symbol
3086 == inst.reloc.exp.X_op_symbol))
3090 /* Do we need to create a new entry? */
3091 if (entry == pool->next_free_entry)
3093 if (entry >= MAX_LITERAL_POOL_SIZE)
3095 inst.error = _("literal pool overflow");
3099 pool->literals[entry] = inst.reloc.exp;
3101 /* PR ld/12974: Record the location of the first source line to reference
3102 this entry in the literal pool. If it turns out during linking that the
3103 symbol does not exist we will be able to give an accurate line number for
3104 the (first use of the) missing reference. */
3105 if (debug_type == DEBUG_DWARF2)
3106 dwarf2_where (pool->locs + entry);
3108 pool->next_free_entry += 1;
3111 inst.reloc.exp.X_op = O_symbol;
3112 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3113 inst.reloc.exp.X_add_symbol = pool->symbol;
3118 /* Can't use symbol_new here, so have to create a symbol and then at
3119 a later date assign it a value. Thats what these functions do. */
3122 symbol_locate (symbolS * symbolP,
3123 const char * name, /* It is copied, the caller can modify. */
3124 segT segment, /* Segment identifier (SEG_<something>). */
3125 valueT valu, /* Symbol value. */
3126 fragS * frag) /* Associated fragment. */
3128 unsigned int name_length;
3129 char * preserved_copy_of_name;
3131 name_length = strlen (name) + 1; /* +1 for \0. */
3132 obstack_grow (¬es, name, name_length);
3133 preserved_copy_of_name = (char *) obstack_finish (¬es);
3135 #ifdef tc_canonicalize_symbol_name
3136 preserved_copy_of_name =
3137 tc_canonicalize_symbol_name (preserved_copy_of_name);
3140 S_SET_NAME (symbolP, preserved_copy_of_name);
3142 S_SET_SEGMENT (symbolP, segment);
3143 S_SET_VALUE (symbolP, valu);
3144 symbol_clear_list_pointers (symbolP);
3146 symbol_set_frag (symbolP, frag);
3148 /* Link to end of symbol chain. */
3150 extern int symbol_table_frozen;
3152 if (symbol_table_frozen)
3156 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3158 obj_symbol_new_hook (symbolP);
3160 #ifdef tc_symbol_new_hook
3161 tc_symbol_new_hook (symbolP);
3165 verify_symbol_chain (symbol_rootP, symbol_lastP);
3166 #endif /* DEBUG_SYMS */
3171 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3174 literal_pool * pool;
3177 pool = find_literal_pool ();
3179 || pool->symbol == NULL
3180 || pool->next_free_entry == 0)
3183 mapping_state (MAP_DATA);
3185 /* Align pool as you have word accesses.
3186 Only make a frag if we have to. */
3188 frag_align (2, 0, 0);
3190 record_alignment (now_seg, 2);
3192 sprintf (sym_name, "$$lit_\002%x", pool->id);
3194 symbol_locate (pool->symbol, sym_name, now_seg,
3195 (valueT) frag_now_fix (), frag_now);
3196 symbol_table_insert (pool->symbol);
3198 ARM_SET_THUMB (pool->symbol, thumb_mode);
3200 #if defined OBJ_COFF || defined OBJ_ELF
3201 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3204 for (entry = 0; entry < pool->next_free_entry; entry ++)
3207 if (debug_type == DEBUG_DWARF2)
3208 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3210 /* First output the expression in the instruction to the pool. */
3211 emit_expr (&(pool->literals[entry]), 4); /* .word */
3214 /* Mark the pool as empty. */
3215 pool->next_free_entry = 0;
3216 pool->symbol = NULL;
3220 /* Forward declarations for functions below, in the MD interface
3222 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3223 static valueT create_unwind_entry (int);
3224 static void start_unwind_section (const segT, int);
3225 static void add_unwind_opcode (valueT, int);
3226 static void flush_pending_unwind (void);
3228 /* Directives: Data. */
3231 s_arm_elf_cons (int nbytes)
3235 #ifdef md_flush_pending_output
3236 md_flush_pending_output ();
3239 if (is_it_end_of_statement ())
3241 demand_empty_rest_of_line ();
3245 #ifdef md_cons_align
3246 md_cons_align (nbytes);
3249 mapping_state (MAP_DATA);
3253 char *base = input_line_pointer;
3257 if (exp.X_op != O_symbol)
3258 emit_expr (&exp, (unsigned int) nbytes);
3261 char *before_reloc = input_line_pointer;
3262 reloc = parse_reloc (&input_line_pointer);
3265 as_bad (_("unrecognized relocation suffix"));
3266 ignore_rest_of_line ();
3269 else if (reloc == BFD_RELOC_UNUSED)
3270 emit_expr (&exp, (unsigned int) nbytes);
3273 reloc_howto_type *howto = (reloc_howto_type *)
3274 bfd_reloc_type_lookup (stdoutput,
3275 (bfd_reloc_code_real_type) reloc);
3276 int size = bfd_get_reloc_size (howto);
3278 if (reloc == BFD_RELOC_ARM_PLT32)
3280 as_bad (_("(plt) is only valid on branch targets"));
3281 reloc = BFD_RELOC_UNUSED;
3286 as_bad (_("%s relocations do not fit in %d bytes"),
3287 howto->name, nbytes);
3290 /* We've parsed an expression stopping at O_symbol.
3291 But there may be more expression left now that we
3292 have parsed the relocation marker. Parse it again.
3293 XXX Surely there is a cleaner way to do this. */
3294 char *p = input_line_pointer;
3296 char *save_buf = (char *) alloca (input_line_pointer - base);
3297 memcpy (save_buf, base, input_line_pointer - base);
3298 memmove (base + (input_line_pointer - before_reloc),
3299 base, before_reloc - base);
3301 input_line_pointer = base + (input_line_pointer-before_reloc);
3303 memcpy (base, save_buf, p - base);
3305 offset = nbytes - size;
3306 p = frag_more ((int) nbytes);
3307 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3308 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3313 while (*input_line_pointer++ == ',');
3315 /* Put terminator back into stream. */
3316 input_line_pointer --;
3317 demand_empty_rest_of_line ();
3320 /* Emit an expression containing a 32-bit thumb instruction.
3321 Implementation based on put_thumb32_insn. */
3324 emit_thumb32_expr (expressionS * exp)
3326 expressionS exp_high = *exp;
3328 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3329 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3330 exp->X_add_number &= 0xffff;
3331 emit_expr (exp, (unsigned int) THUMB_SIZE);
3334 /* Guess the instruction size based on the opcode. */
3337 thumb_insn_size (int opcode)
3339 if ((unsigned int) opcode < 0xe800u)
3341 else if ((unsigned int) opcode >= 0xe8000000u)
3348 emit_insn (expressionS *exp, int nbytes)
3352 if (exp->X_op == O_constant)
3357 size = thumb_insn_size (exp->X_add_number);
3361 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3363 as_bad (_(".inst.n operand too big. "\
3364 "Use .inst.w instead"));
3369 if (now_it.state == AUTOMATIC_IT_BLOCK)
3370 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3372 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3374 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3375 emit_thumb32_expr (exp);
3377 emit_expr (exp, (unsigned int) size);
3379 it_fsm_post_encode ();
3383 as_bad (_("cannot determine Thumb instruction size. " \
3384 "Use .inst.n/.inst.w instead"));
3387 as_bad (_("constant expression required"));
3392 /* Like s_arm_elf_cons but do not use md_cons_align and
3393 set the mapping state to MAP_ARM/MAP_THUMB. */
3396 s_arm_elf_inst (int nbytes)
3398 if (is_it_end_of_statement ())
3400 demand_empty_rest_of_line ();
3404 /* Calling mapping_state () here will not change ARM/THUMB,
3405 but will ensure not to be in DATA state. */
3408 mapping_state (MAP_THUMB);
3413 as_bad (_("width suffixes are invalid in ARM mode"));
3414 ignore_rest_of_line ();
3420 mapping_state (MAP_ARM);
3429 if (! emit_insn (& exp, nbytes))
3431 ignore_rest_of_line ();
3435 while (*input_line_pointer++ == ',');
3437 /* Put terminator back into stream. */
3438 input_line_pointer --;
3439 demand_empty_rest_of_line ();
3442 /* Parse a .rel31 directive. */
3445 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3452 if (*input_line_pointer == '1')
3453 highbit = 0x80000000;
3454 else if (*input_line_pointer != '0')
3455 as_bad (_("expected 0 or 1"));
3457 input_line_pointer++;
3458 if (*input_line_pointer != ',')
3459 as_bad (_("missing comma"));
3460 input_line_pointer++;
3462 #ifdef md_flush_pending_output
3463 md_flush_pending_output ();
3466 #ifdef md_cons_align
3470 mapping_state (MAP_DATA);
3475 md_number_to_chars (p, highbit, 4);
3476 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3477 BFD_RELOC_ARM_PREL31);
3479 demand_empty_rest_of_line ();
3482 /* Directives: AEABI stack-unwind tables. */
3484 /* Parse an unwind_fnstart directive. Simply records the current location. */
3487 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3489 demand_empty_rest_of_line ();
3490 if (unwind.proc_start)
3492 as_bad (_("duplicate .fnstart directive"));
3496 /* Mark the start of the function. */
3497 unwind.proc_start = expr_build_dot ();
3499 /* Reset the rest of the unwind info. */
3500 unwind.opcode_count = 0;
3501 unwind.table_entry = NULL;
3502 unwind.personality_routine = NULL;
3503 unwind.personality_index = -1;
3504 unwind.frame_size = 0;
3505 unwind.fp_offset = 0;
3506 unwind.fp_reg = REG_SP;
3508 unwind.sp_restored = 0;
3512 /* Parse a handlerdata directive. Creates the exception handling table entry
3513 for the function. */
3516 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3518 demand_empty_rest_of_line ();
3519 if (!unwind.proc_start)
3520 as_bad (MISSING_FNSTART);
3522 if (unwind.table_entry)
3523 as_bad (_("duplicate .handlerdata directive"));
3525 create_unwind_entry (1);
3528 /* Parse an unwind_fnend directive. Generates the index table entry. */
3531 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3536 unsigned int marked_pr_dependency;
3538 demand_empty_rest_of_line ();
3540 if (!unwind.proc_start)
3542 as_bad (_(".fnend directive without .fnstart"));
3546 /* Add eh table entry. */
3547 if (unwind.table_entry == NULL)
3548 val = create_unwind_entry (0);
3552 /* Add index table entry. This is two words. */
3553 start_unwind_section (unwind.saved_seg, 1);
3554 frag_align (2, 0, 0);
3555 record_alignment (now_seg, 2);
3557 ptr = frag_more (8);
3559 where = frag_now_fix () - 8;
3561 /* Self relative offset of the function start. */
3562 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3563 BFD_RELOC_ARM_PREL31);
3565 /* Indicate dependency on EHABI-defined personality routines to the
3566 linker, if it hasn't been done already. */
3567 marked_pr_dependency
3568 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3569 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3570 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3572 static const char *const name[] =
3574 "__aeabi_unwind_cpp_pr0",
3575 "__aeabi_unwind_cpp_pr1",
3576 "__aeabi_unwind_cpp_pr2"
3578 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3579 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3580 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3581 |= 1 << unwind.personality_index;
3585 /* Inline exception table entry. */
3586 md_number_to_chars (ptr + 4, val, 4);
3588 /* Self relative offset of the table entry. */
3589 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3590 BFD_RELOC_ARM_PREL31);
3592 /* Restore the original section. */
3593 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3595 unwind.proc_start = NULL;
3599 /* Parse an unwind_cantunwind directive. */
3602 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3604 demand_empty_rest_of_line ();
3605 if (!unwind.proc_start)
3606 as_bad (MISSING_FNSTART);
3608 if (unwind.personality_routine || unwind.personality_index != -1)
3609 as_bad (_("personality routine specified for cantunwind frame"));
3611 unwind.personality_index = -2;
3615 /* Parse a personalityindex directive. */
3618 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3622 if (!unwind.proc_start)
3623 as_bad (MISSING_FNSTART);
3625 if (unwind.personality_routine || unwind.personality_index != -1)
3626 as_bad (_("duplicate .personalityindex directive"));
3630 if (exp.X_op != O_constant
3631 || exp.X_add_number < 0 || exp.X_add_number > 15)
3633 as_bad (_("bad personality routine number"));
3634 ignore_rest_of_line ();
3638 unwind.personality_index = exp.X_add_number;
3640 demand_empty_rest_of_line ();
3644 /* Parse a personality directive. */
3647 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3651 if (!unwind.proc_start)
3652 as_bad (MISSING_FNSTART);
3654 if (unwind.personality_routine || unwind.personality_index != -1)
3655 as_bad (_("duplicate .personality directive"));
3657 name = input_line_pointer;
3658 c = get_symbol_end ();
3659 p = input_line_pointer;
3660 unwind.personality_routine = symbol_find_or_make (name);
3662 demand_empty_rest_of_line ();
3666 /* Parse a directive saving core registers. */
3669 s_arm_unwind_save_core (void)
3675 range = parse_reg_list (&input_line_pointer);
3678 as_bad (_("expected register list"));
3679 ignore_rest_of_line ();
3683 demand_empty_rest_of_line ();
3685 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3686 into .unwind_save {..., sp...}. We aren't bothered about the value of
3687 ip because it is clobbered by calls. */
3688 if (unwind.sp_restored && unwind.fp_reg == 12
3689 && (range & 0x3000) == 0x1000)
3691 unwind.opcode_count--;
3692 unwind.sp_restored = 0;
3693 range = (range | 0x2000) & ~0x1000;
3694 unwind.pending_offset = 0;
3700 /* See if we can use the short opcodes. These pop a block of up to 8
3701 registers starting with r4, plus maybe r14. */
3702 for (n = 0; n < 8; n++)
3704 /* Break at the first non-saved register. */
3705 if ((range & (1 << (n + 4))) == 0)
3708 /* See if there are any other bits set. */
3709 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3711 /* Use the long form. */
3712 op = 0x8000 | ((range >> 4) & 0xfff);
3713 add_unwind_opcode (op, 2);
3717 /* Use the short form. */
3719 op = 0xa8; /* Pop r14. */
3721 op = 0xa0; /* Do not pop r14. */
3723 add_unwind_opcode (op, 1);
3730 op = 0xb100 | (range & 0xf);
3731 add_unwind_opcode (op, 2);
3734 /* Record the number of bytes pushed. */
3735 for (n = 0; n < 16; n++)
3737 if (range & (1 << n))
3738 unwind.frame_size += 4;
3743 /* Parse a directive saving FPA registers. */
3746 s_arm_unwind_save_fpa (int reg)
3752 /* Get Number of registers to transfer. */
3753 if (skip_past_comma (&input_line_pointer) != FAIL)
3756 exp.X_op = O_illegal;
3758 if (exp.X_op != O_constant)
3760 as_bad (_("expected , <constant>"));
3761 ignore_rest_of_line ();
3765 num_regs = exp.X_add_number;
3767 if (num_regs < 1 || num_regs > 4)
3769 as_bad (_("number of registers must be in the range [1:4]"));
3770 ignore_rest_of_line ();
3774 demand_empty_rest_of_line ();
3779 op = 0xb4 | (num_regs - 1);
3780 add_unwind_opcode (op, 1);
3785 op = 0xc800 | (reg << 4) | (num_regs - 1);
3786 add_unwind_opcode (op, 2);
3788 unwind.frame_size += num_regs * 12;
3792 /* Parse a directive saving VFP registers for ARMv6 and above. */
3795 s_arm_unwind_save_vfp_armv6 (void)
3800 int num_vfpv3_regs = 0;
3801 int num_regs_below_16;
3803 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3806 as_bad (_("expected register list"));
3807 ignore_rest_of_line ();
3811 demand_empty_rest_of_line ();
3813 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3814 than FSTMX/FLDMX-style ones). */
3816 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3818 num_vfpv3_regs = count;
3819 else if (start + count > 16)
3820 num_vfpv3_regs = start + count - 16;
3822 if (num_vfpv3_regs > 0)
3824 int start_offset = start > 16 ? start - 16 : 0;
3825 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3826 add_unwind_opcode (op, 2);
3829 /* Generate opcode for registers numbered in the range 0 .. 15. */
3830 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3831 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3832 if (num_regs_below_16 > 0)
3834 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3835 add_unwind_opcode (op, 2);
3838 unwind.frame_size += count * 8;
3842 /* Parse a directive saving VFP registers for pre-ARMv6. */
3845 s_arm_unwind_save_vfp (void)
3851 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3854 as_bad (_("expected register list"));
3855 ignore_rest_of_line ();
3859 demand_empty_rest_of_line ();
3864 op = 0xb8 | (count - 1);
3865 add_unwind_opcode (op, 1);
3870 op = 0xb300 | (reg << 4) | (count - 1);
3871 add_unwind_opcode (op, 2);
3873 unwind.frame_size += count * 8 + 4;
3877 /* Parse a directive saving iWMMXt data registers. */
3880 s_arm_unwind_save_mmxwr (void)
3888 if (*input_line_pointer == '{')
3889 input_line_pointer++;
3893 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3897 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3902 as_tsktsk (_("register list not in ascending order"));
3905 if (*input_line_pointer == '-')
3907 input_line_pointer++;
3908 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3911 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3914 else if (reg >= hi_reg)
3916 as_bad (_("bad register range"));
3919 for (; reg < hi_reg; reg++)
3923 while (skip_past_comma (&input_line_pointer) != FAIL);
3925 if (*input_line_pointer == '}')
3926 input_line_pointer++;
3928 demand_empty_rest_of_line ();
3930 /* Generate any deferred opcodes because we're going to be looking at
3932 flush_pending_unwind ();
3934 for (i = 0; i < 16; i++)
3936 if (mask & (1 << i))
3937 unwind.frame_size += 8;
3940 /* Attempt to combine with a previous opcode. We do this because gcc
3941 likes to output separate unwind directives for a single block of
3943 if (unwind.opcode_count > 0)
3945 i = unwind.opcodes[unwind.opcode_count - 1];
3946 if ((i & 0xf8) == 0xc0)
3949 /* Only merge if the blocks are contiguous. */
3952 if ((mask & 0xfe00) == (1 << 9))
3954 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3955 unwind.opcode_count--;
3958 else if (i == 6 && unwind.opcode_count >= 2)
3960 i = unwind.opcodes[unwind.opcode_count - 2];
3964 op = 0xffff << (reg - 1);
3966 && ((mask & op) == (1u << (reg - 1))))
3968 op = (1 << (reg + i + 1)) - 1;
3969 op &= ~((1 << reg) - 1);
3971 unwind.opcode_count -= 2;
3978 /* We want to generate opcodes in the order the registers have been
3979 saved, ie. descending order. */
3980 for (reg = 15; reg >= -1; reg--)
3982 /* Save registers in blocks. */
3984 || !(mask & (1 << reg)))
3986 /* We found an unsaved reg. Generate opcodes to save the
3993 op = 0xc0 | (hi_reg - 10);
3994 add_unwind_opcode (op, 1);
3999 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4000 add_unwind_opcode (op, 2);
4009 ignore_rest_of_line ();
4013 s_arm_unwind_save_mmxwcg (void)
4020 if (*input_line_pointer == '{')
4021 input_line_pointer++;
4025 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4029 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4035 as_tsktsk (_("register list not in ascending order"));
4038 if (*input_line_pointer == '-')
4040 input_line_pointer++;
4041 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4044 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4047 else if (reg >= hi_reg)
4049 as_bad (_("bad register range"));
4052 for (; reg < hi_reg; reg++)
4056 while (skip_past_comma (&input_line_pointer) != FAIL);
4058 if (*input_line_pointer == '}')
4059 input_line_pointer++;
4061 demand_empty_rest_of_line ();
4063 /* Generate any deferred opcodes because we're going to be looking at
4065 flush_pending_unwind ();
4067 for (reg = 0; reg < 16; reg++)
4069 if (mask & (1 << reg))
4070 unwind.frame_size += 4;
4073 add_unwind_opcode (op, 2);
4076 ignore_rest_of_line ();
4080 /* Parse an unwind_save directive.
4081 If the argument is non-zero, this is a .vsave directive. */
4084 s_arm_unwind_save (int arch_v6)
4087 struct reg_entry *reg;
4088 bfd_boolean had_brace = FALSE;
4090 if (!unwind.proc_start)
4091 as_bad (MISSING_FNSTART);
4093 /* Figure out what sort of save we have. */
4094 peek = input_line_pointer;
4102 reg = arm_reg_parse_multi (&peek);
4106 as_bad (_("register expected"));
4107 ignore_rest_of_line ();
4116 as_bad (_("FPA .unwind_save does not take a register list"));
4117 ignore_rest_of_line ();
4120 input_line_pointer = peek;
4121 s_arm_unwind_save_fpa (reg->number);
4124 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4127 s_arm_unwind_save_vfp_armv6 ();
4129 s_arm_unwind_save_vfp ();
4131 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4132 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4135 as_bad (_(".unwind_save does not support this kind of register"));
4136 ignore_rest_of_line ();
4141 /* Parse an unwind_movsp directive. */
4144 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4150 if (!unwind.proc_start)
4151 as_bad (MISSING_FNSTART);
4153 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4156 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4157 ignore_rest_of_line ();
4161 /* Optional constant. */
4162 if (skip_past_comma (&input_line_pointer) != FAIL)
4164 if (immediate_for_directive (&offset) == FAIL)
4170 demand_empty_rest_of_line ();
4172 if (reg == REG_SP || reg == REG_PC)
4174 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4178 if (unwind.fp_reg != REG_SP)
4179 as_bad (_("unexpected .unwind_movsp directive"));
4181 /* Generate opcode to restore the value. */
4183 add_unwind_opcode (op, 1);
4185 /* Record the information for later. */
4186 unwind.fp_reg = reg;
4187 unwind.fp_offset = unwind.frame_size - offset;
4188 unwind.sp_restored = 1;
4191 /* Parse an unwind_pad directive. */
4194 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4198 if (!unwind.proc_start)
4199 as_bad (MISSING_FNSTART);
4201 if (immediate_for_directive (&offset) == FAIL)
4206 as_bad (_("stack increment must be multiple of 4"));
4207 ignore_rest_of_line ();
4211 /* Don't generate any opcodes, just record the details for later. */
4212 unwind.frame_size += offset;
4213 unwind.pending_offset += offset;
4215 demand_empty_rest_of_line ();
4218 /* Parse an unwind_setfp directive. */
4221 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4227 if (!unwind.proc_start)
4228 as_bad (MISSING_FNSTART);
4230 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4231 if (skip_past_comma (&input_line_pointer) == FAIL)
4234 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4236 if (fp_reg == FAIL || sp_reg == FAIL)
4238 as_bad (_("expected <reg>, <reg>"));
4239 ignore_rest_of_line ();
4243 /* Optional constant. */
4244 if (skip_past_comma (&input_line_pointer) != FAIL)
4246 if (immediate_for_directive (&offset) == FAIL)
4252 demand_empty_rest_of_line ();
4254 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4256 as_bad (_("register must be either sp or set by a previous"
4257 "unwind_movsp directive"));
4261 /* Don't generate any opcodes, just record the information for later. */
4262 unwind.fp_reg = fp_reg;
4264 if (sp_reg == REG_SP)
4265 unwind.fp_offset = unwind.frame_size - offset;
4267 unwind.fp_offset -= offset;
4270 /* Parse an unwind_raw directive. */
4273 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4276 /* This is an arbitrary limit. */
4277 unsigned char op[16];
4280 if (!unwind.proc_start)
4281 as_bad (MISSING_FNSTART);
4284 if (exp.X_op == O_constant
4285 && skip_past_comma (&input_line_pointer) != FAIL)
4287 unwind.frame_size += exp.X_add_number;
4291 exp.X_op = O_illegal;
4293 if (exp.X_op != O_constant)
4295 as_bad (_("expected <offset>, <opcode>"));
4296 ignore_rest_of_line ();
4302 /* Parse the opcode. */
4307 as_bad (_("unwind opcode too long"));
4308 ignore_rest_of_line ();
4310 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4312 as_bad (_("invalid unwind opcode"));
4313 ignore_rest_of_line ();
4316 op[count++] = exp.X_add_number;
4318 /* Parse the next byte. */
4319 if (skip_past_comma (&input_line_pointer) == FAIL)
4325 /* Add the opcode bytes in reverse order. */
4327 add_unwind_opcode (op[count], 1);
4329 demand_empty_rest_of_line ();
4333 /* Parse a .eabi_attribute directive. */
4336 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4338 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4340 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4341 attributes_set_explicitly[tag] = 1;
4344 /* Emit a tls fix for the symbol. */
4347 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4351 #ifdef md_flush_pending_output
4352 md_flush_pending_output ();
4355 #ifdef md_cons_align
4359 /* Since we're just labelling the code, there's no need to define a
4362 p = obstack_next_free (&frchain_now->frch_obstack);
4363 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4364 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4365 : BFD_RELOC_ARM_TLS_DESCSEQ);
4367 #endif /* OBJ_ELF */
4369 static void s_arm_arch (int);
4370 static void s_arm_object_arch (int);
4371 static void s_arm_cpu (int);
4372 static void s_arm_fpu (int);
4373 static void s_arm_arch_extension (int);
4378 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4385 if (exp.X_op == O_symbol)
4386 exp.X_op = O_secrel;
4388 emit_expr (&exp, 4);
4390 while (*input_line_pointer++ == ',');
4392 input_line_pointer--;
4393 demand_empty_rest_of_line ();
4397 /* This table describes all the machine specific pseudo-ops the assembler
4398 has to support. The fields are:
4399 pseudo-op name without dot
4400 function to call to execute this pseudo-op
4401 Integer arg to pass to the function. */
4403 const pseudo_typeS md_pseudo_table[] =
4405 /* Never called because '.req' does not start a line. */
4406 { "req", s_req, 0 },
4407 /* Following two are likewise never called. */
4410 { "unreq", s_unreq, 0 },
4411 { "bss", s_bss, 0 },
4412 { "align", s_align, 0 },
4413 { "arm", s_arm, 0 },
4414 { "thumb", s_thumb, 0 },
4415 { "code", s_code, 0 },
4416 { "force_thumb", s_force_thumb, 0 },
4417 { "thumb_func", s_thumb_func, 0 },
4418 { "thumb_set", s_thumb_set, 0 },
4419 { "even", s_even, 0 },
4420 { "ltorg", s_ltorg, 0 },
4421 { "pool", s_ltorg, 0 },
4422 { "syntax", s_syntax, 0 },
4423 { "cpu", s_arm_cpu, 0 },
4424 { "arch", s_arm_arch, 0 },
4425 { "object_arch", s_arm_object_arch, 0 },
4426 { "fpu", s_arm_fpu, 0 },
4427 { "arch_extension", s_arm_arch_extension, 0 },
4429 { "word", s_arm_elf_cons, 4 },
4430 { "long", s_arm_elf_cons, 4 },
4431 { "inst.n", s_arm_elf_inst, 2 },
4432 { "inst.w", s_arm_elf_inst, 4 },
4433 { "inst", s_arm_elf_inst, 0 },
4434 { "rel31", s_arm_rel31, 0 },
4435 { "fnstart", s_arm_unwind_fnstart, 0 },
4436 { "fnend", s_arm_unwind_fnend, 0 },
4437 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4438 { "personality", s_arm_unwind_personality, 0 },
4439 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4440 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4441 { "save", s_arm_unwind_save, 0 },
4442 { "vsave", s_arm_unwind_save, 1 },
4443 { "movsp", s_arm_unwind_movsp, 0 },
4444 { "pad", s_arm_unwind_pad, 0 },
4445 { "setfp", s_arm_unwind_setfp, 0 },
4446 { "unwind_raw", s_arm_unwind_raw, 0 },
4447 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4448 { "tlsdescseq", s_arm_tls_descseq, 0 },
4452 /* These are used for dwarf. */
4456 /* These are used for dwarf2. */
4457 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4458 { "loc", dwarf2_directive_loc, 0 },
4459 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4461 { "extend", float_cons, 'x' },
4462 { "ldouble", float_cons, 'x' },
4463 { "packed", float_cons, 'p' },
4465 {"secrel32", pe_directive_secrel, 0},
4470 /* Parser functions used exclusively in instruction operands. */
4472 /* Generic immediate-value read function for use in insn parsing.
4473 STR points to the beginning of the immediate (the leading #);
4474 VAL receives the value; if the value is outside [MIN, MAX]
4475 issue an error. PREFIX_OPT is true if the immediate prefix is
4479 parse_immediate (char **str, int *val, int min, int max,
4480 bfd_boolean prefix_opt)
4483 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4484 if (exp.X_op != O_constant)
4486 inst.error = _("constant expression required");
4490 if (exp.X_add_number < min || exp.X_add_number > max)
4492 inst.error = _("immediate value out of range");
4496 *val = exp.X_add_number;
4500 /* Less-generic immediate-value read function with the possibility of loading a
4501 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4502 instructions. Puts the result directly in inst.operands[i]. */
4505 parse_big_immediate (char **str, int i)
4510 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4512 if (exp.X_op == O_constant)
4514 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4515 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4516 O_constant. We have to be careful not to break compilation for
4517 32-bit X_add_number, though. */
4518 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4520 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4521 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4522 inst.operands[i].regisimm = 1;
4525 else if (exp.X_op == O_big
4526 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4528 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4530 /* Bignums have their least significant bits in
4531 generic_bignum[0]. Make sure we put 32 bits in imm and
4532 32 bits in reg, in a (hopefully) portable way. */
4533 gas_assert (parts != 0);
4535 /* Make sure that the number is not too big.
4536 PR 11972: Bignums can now be sign-extended to the
4537 size of a .octa so check that the out of range bits
4538 are all zero or all one. */
4539 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4541 LITTLENUM_TYPE m = -1;
4543 if (generic_bignum[parts * 2] != 0
4544 && generic_bignum[parts * 2] != m)
4547 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4548 if (generic_bignum[j] != generic_bignum[j-1])
4552 inst.operands[i].imm = 0;
4553 for (j = 0; j < parts; j++, idx++)
4554 inst.operands[i].imm |= generic_bignum[idx]
4555 << (LITTLENUM_NUMBER_OF_BITS * j);
4556 inst.operands[i].reg = 0;
4557 for (j = 0; j < parts; j++, idx++)
4558 inst.operands[i].reg |= generic_bignum[idx]
4559 << (LITTLENUM_NUMBER_OF_BITS * j);
4560 inst.operands[i].regisimm = 1;
4570 /* Returns the pseudo-register number of an FPA immediate constant,
4571 or FAIL if there isn't a valid constant here. */
4574 parse_fpa_immediate (char ** str)
4576 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4582 /* First try and match exact strings, this is to guarantee
4583 that some formats will work even for cross assembly. */
4585 for (i = 0; fp_const[i]; i++)
4587 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4591 *str += strlen (fp_const[i]);
4592 if (is_end_of_line[(unsigned char) **str])
4598 /* Just because we didn't get a match doesn't mean that the constant
4599 isn't valid, just that it is in a format that we don't
4600 automatically recognize. Try parsing it with the standard
4601 expression routines. */
4603 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4605 /* Look for a raw floating point number. */
4606 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4607 && is_end_of_line[(unsigned char) *save_in])
4609 for (i = 0; i < NUM_FLOAT_VALS; i++)
4611 for (j = 0; j < MAX_LITTLENUMS; j++)
4613 if (words[j] != fp_values[i][j])
4617 if (j == MAX_LITTLENUMS)
4625 /* Try and parse a more complex expression, this will probably fail
4626 unless the code uses a floating point prefix (eg "0f"). */
4627 save_in = input_line_pointer;
4628 input_line_pointer = *str;
4629 if (expression (&exp) == absolute_section
4630 && exp.X_op == O_big
4631 && exp.X_add_number < 0)
4633 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4635 if (gen_to_words (words, 5, (long) 15) == 0)
4637 for (i = 0; i < NUM_FLOAT_VALS; i++)
4639 for (j = 0; j < MAX_LITTLENUMS; j++)
4641 if (words[j] != fp_values[i][j])
4645 if (j == MAX_LITTLENUMS)
4647 *str = input_line_pointer;
4648 input_line_pointer = save_in;
4655 *str = input_line_pointer;
4656 input_line_pointer = save_in;
4657 inst.error = _("invalid FPA immediate expression");
4661 /* Returns 1 if a number has "quarter-precision" float format
4662 0baBbbbbbc defgh000 00000000 00000000. */
4665 is_quarter_float (unsigned imm)
4667 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4668 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4671 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4672 0baBbbbbbc defgh000 00000000 00000000.
4673 The zero and minus-zero cases need special handling, since they can't be
4674 encoded in the "quarter-precision" float format, but can nonetheless be
4675 loaded as integer constants. */
4678 parse_qfloat_immediate (char **ccp, int *immed)
4682 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4683 int found_fpchar = 0;
4685 skip_past_char (&str, '#');
4687 /* We must not accidentally parse an integer as a floating-point number. Make
4688 sure that the value we parse is not an integer by checking for special
4689 characters '.' or 'e'.
4690 FIXME: This is a horrible hack, but doing better is tricky because type
4691 information isn't in a very usable state at parse time. */
4693 skip_whitespace (fpnum);
4695 if (strncmp (fpnum, "0x", 2) == 0)
4699 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4700 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4710 if ((str = atof_ieee (str, 's', words)) != NULL)
4712 unsigned fpword = 0;
4715 /* Our FP word must be 32 bits (single-precision FP). */
4716 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4718 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4722 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4735 /* Shift operands. */
4738 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4741 struct asm_shift_name
4744 enum shift_kind kind;
4747 /* Third argument to parse_shift. */
4748 enum parse_shift_mode
4750 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4751 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4752 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4753 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4754 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4757 /* Parse a <shift> specifier on an ARM data processing instruction.
4758 This has three forms:
4760 (LSL|LSR|ASL|ASR|ROR) Rs
4761 (LSL|LSR|ASL|ASR|ROR) #imm
4764 Note that ASL is assimilated to LSL in the instruction encoding, and
4765 RRX to ROR #0 (which cannot be written as such). */
4768 parse_shift (char **str, int i, enum parse_shift_mode mode)
4770 const struct asm_shift_name *shift_name;
4771 enum shift_kind shift;
4776 for (p = *str; ISALPHA (*p); p++)
4781 inst.error = _("shift expression expected");
4785 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4788 if (shift_name == NULL)
4790 inst.error = _("shift expression expected");
4794 shift = shift_name->kind;
4798 case NO_SHIFT_RESTRICT:
4799 case SHIFT_IMMEDIATE: break;
4801 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4802 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4804 inst.error = _("'LSL' or 'ASR' required");
4809 case SHIFT_LSL_IMMEDIATE:
4810 if (shift != SHIFT_LSL)
4812 inst.error = _("'LSL' required");
4817 case SHIFT_ASR_IMMEDIATE:
4818 if (shift != SHIFT_ASR)
4820 inst.error = _("'ASR' required");
4828 if (shift != SHIFT_RRX)
4830 /* Whitespace can appear here if the next thing is a bare digit. */
4831 skip_whitespace (p);
4833 if (mode == NO_SHIFT_RESTRICT
4834 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4836 inst.operands[i].imm = reg;
4837 inst.operands[i].immisreg = 1;
4839 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4842 inst.operands[i].shift_kind = shift;
4843 inst.operands[i].shifted = 1;
4848 /* Parse a <shifter_operand> for an ARM data processing instruction:
4851 #<immediate>, <rotate>
4855 where <shift> is defined by parse_shift above, and <rotate> is a
4856 multiple of 2 between 0 and 30. Validation of immediate operands
4857 is deferred to md_apply_fix. */
4860 parse_shifter_operand (char **str, int i)
4865 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4867 inst.operands[i].reg = value;
4868 inst.operands[i].isreg = 1;
4870 /* parse_shift will override this if appropriate */
4871 inst.reloc.exp.X_op = O_constant;
4872 inst.reloc.exp.X_add_number = 0;
4874 if (skip_past_comma (str) == FAIL)
4877 /* Shift operation on register. */
4878 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4881 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4884 if (skip_past_comma (str) == SUCCESS)
4886 /* #x, y -- ie explicit rotation by Y. */
4887 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4890 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4892 inst.error = _("constant expression expected");
4896 value = exp.X_add_number;
4897 if (value < 0 || value > 30 || value % 2 != 0)
4899 inst.error = _("invalid rotation");
4902 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4904 inst.error = _("invalid constant");
4908 /* Encode as specified. */
4909 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4913 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4914 inst.reloc.pc_rel = 0;
4918 /* Group relocation information. Each entry in the table contains the
4919 textual name of the relocation as may appear in assembler source
4920 and must end with a colon.
4921 Along with this textual name are the relocation codes to be used if
4922 the corresponding instruction is an ALU instruction (ADD or SUB only),
4923 an LDR, an LDRS, or an LDC. */
4925 struct group_reloc_table_entry
4936 /* Varieties of non-ALU group relocation. */
4943 static struct group_reloc_table_entry group_reloc_table[] =
4944 { /* Program counter relative: */
4946 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4951 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4952 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4953 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4954 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4956 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4962 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4963 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4964 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4967 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4968 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4969 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4970 /* Section base relative */
4972 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4977 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4978 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4979 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4980 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4982 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4987 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4988 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4989 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4990 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4992 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4993 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4994 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4995 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4997 /* Given the address of a pointer pointing to the textual name of a group
4998 relocation as may appear in assembler source, attempt to find its details
4999 in group_reloc_table. The pointer will be updated to the character after
5000 the trailing colon. On failure, FAIL will be returned; SUCCESS
5001 otherwise. On success, *entry will be updated to point at the relevant
5002 group_reloc_table entry. */
5005 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5008 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5010 int length = strlen (group_reloc_table[i].name);
5012 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5013 && (*str)[length] == ':')
5015 *out = &group_reloc_table[i];
5016 *str += (length + 1);
5024 /* Parse a <shifter_operand> for an ARM data processing instruction
5025 (as for parse_shifter_operand) where group relocations are allowed:
5028 #<immediate>, <rotate>
5029 #:<group_reloc>:<expression>
5033 where <group_reloc> is one of the strings defined in group_reloc_table.
5034 The hashes are optional.
5036 Everything else is as for parse_shifter_operand. */
5038 static parse_operand_result
5039 parse_shifter_operand_group_reloc (char **str, int i)
5041 /* Determine if we have the sequence of characters #: or just :
5042 coming next. If we do, then we check for a group relocation.
5043 If we don't, punt the whole lot to parse_shifter_operand. */
5045 if (((*str)[0] == '#' && (*str)[1] == ':')
5046 || (*str)[0] == ':')
5048 struct group_reloc_table_entry *entry;
5050 if ((*str)[0] == '#')
5055 /* Try to parse a group relocation. Anything else is an error. */
5056 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5058 inst.error = _("unknown group relocation");
5059 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5062 /* We now have the group relocation table entry corresponding to
5063 the name in the assembler source. Next, we parse the expression. */
5064 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5065 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5067 /* Record the relocation type (always the ALU variant here). */
5068 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5069 gas_assert (inst.reloc.type != 0);
5071 return PARSE_OPERAND_SUCCESS;
5074 return parse_shifter_operand (str, i) == SUCCESS
5075 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5077 /* Never reached. */
5080 /* Parse a Neon alignment expression. Information is written to
5081 inst.operands[i]. We assume the initial ':' has been skipped.
5083 align .imm = align << 8, .immisalign=1, .preind=0 */
5084 static parse_operand_result
5085 parse_neon_alignment (char **str, int i)
5090 my_get_expression (&exp, &p, GE_NO_PREFIX);
5092 if (exp.X_op != O_constant)
5094 inst.error = _("alignment must be constant");
5095 return PARSE_OPERAND_FAIL;
5098 inst.operands[i].imm = exp.X_add_number << 8;
5099 inst.operands[i].immisalign = 1;
5100 /* Alignments are not pre-indexes. */
5101 inst.operands[i].preind = 0;
5104 return PARSE_OPERAND_SUCCESS;
5107 /* Parse all forms of an ARM address expression. Information is written
5108 to inst.operands[i] and/or inst.reloc.
5110 Preindexed addressing (.preind=1):
5112 [Rn, #offset] .reg=Rn .reloc.exp=offset
5113 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5114 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5115 .shift_kind=shift .reloc.exp=shift_imm
5117 These three may have a trailing ! which causes .writeback to be set also.
5119 Postindexed addressing (.postind=1, .writeback=1):
5121 [Rn], #offset .reg=Rn .reloc.exp=offset
5122 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5123 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 .shift_kind=shift .reloc.exp=shift_imm
5126 Unindexed addressing (.preind=0, .postind=0):
5128 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5132 [Rn]{!} shorthand for [Rn,#0]{!}
5133 =immediate .isreg=0 .reloc.exp=immediate
5134 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5136 It is the caller's responsibility to check for addressing modes not
5137 supported by the instruction, and to set inst.reloc.type. */
5139 static parse_operand_result
5140 parse_address_main (char **str, int i, int group_relocations,
5141 group_reloc_type group_type)
5146 if (skip_past_char (&p, '[') == FAIL)
5148 if (skip_past_char (&p, '=') == FAIL)
5150 /* Bare address - translate to PC-relative offset. */
5151 inst.reloc.pc_rel = 1;
5152 inst.operands[i].reg = REG_PC;
5153 inst.operands[i].isreg = 1;
5154 inst.operands[i].preind = 1;
5156 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5158 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5159 return PARSE_OPERAND_FAIL;
5162 return PARSE_OPERAND_SUCCESS;
5165 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5167 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5168 return PARSE_OPERAND_FAIL;
5170 inst.operands[i].reg = reg;
5171 inst.operands[i].isreg = 1;
5173 if (skip_past_comma (&p) == SUCCESS)
5175 inst.operands[i].preind = 1;
5178 else if (*p == '-') p++, inst.operands[i].negative = 1;
5180 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5182 inst.operands[i].imm = reg;
5183 inst.operands[i].immisreg = 1;
5185 if (skip_past_comma (&p) == SUCCESS)
5186 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5187 return PARSE_OPERAND_FAIL;
5189 else if (skip_past_char (&p, ':') == SUCCESS)
5191 /* FIXME: '@' should be used here, but it's filtered out by generic
5192 code before we get to see it here. This may be subject to
5194 parse_operand_result result = parse_neon_alignment (&p, i);
5196 if (result != PARSE_OPERAND_SUCCESS)
5201 if (inst.operands[i].negative)
5203 inst.operands[i].negative = 0;
5207 if (group_relocations
5208 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5210 struct group_reloc_table_entry *entry;
5212 /* Skip over the #: or : sequence. */
5218 /* Try to parse a group relocation. Anything else is an
5220 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5222 inst.error = _("unknown group relocation");
5223 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5226 /* We now have the group relocation table entry corresponding to
5227 the name in the assembler source. Next, we parse the
5229 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5230 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5232 /* Record the relocation type. */
5236 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5240 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5244 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5251 if (inst.reloc.type == 0)
5253 inst.error = _("this group relocation is not allowed on this instruction");
5254 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5260 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5261 return PARSE_OPERAND_FAIL;
5262 /* If the offset is 0, find out if it's a +0 or -0. */
5263 if (inst.reloc.exp.X_op == O_constant
5264 && inst.reloc.exp.X_add_number == 0)
5266 skip_whitespace (q);
5270 skip_whitespace (q);
5273 inst.operands[i].negative = 1;
5278 else if (skip_past_char (&p, ':') == SUCCESS)
5280 /* FIXME: '@' should be used here, but it's filtered out by generic code
5281 before we get to see it here. This may be subject to change. */
5282 parse_operand_result result = parse_neon_alignment (&p, i);
5284 if (result != PARSE_OPERAND_SUCCESS)
5288 if (skip_past_char (&p, ']') == FAIL)
5290 inst.error = _("']' expected");
5291 return PARSE_OPERAND_FAIL;
5294 if (skip_past_char (&p, '!') == SUCCESS)
5295 inst.operands[i].writeback = 1;
5297 else if (skip_past_comma (&p) == SUCCESS)
5299 if (skip_past_char (&p, '{') == SUCCESS)
5301 /* [Rn], {expr} - unindexed, with option */
5302 if (parse_immediate (&p, &inst.operands[i].imm,
5303 0, 255, TRUE) == FAIL)
5304 return PARSE_OPERAND_FAIL;
5306 if (skip_past_char (&p, '}') == FAIL)
5308 inst.error = _("'}' expected at end of 'option' field");
5309 return PARSE_OPERAND_FAIL;
5311 if (inst.operands[i].preind)
5313 inst.error = _("cannot combine index with option");
5314 return PARSE_OPERAND_FAIL;
5317 return PARSE_OPERAND_SUCCESS;
5321 inst.operands[i].postind = 1;
5322 inst.operands[i].writeback = 1;
5324 if (inst.operands[i].preind)
5326 inst.error = _("cannot combine pre- and post-indexing");
5327 return PARSE_OPERAND_FAIL;
5331 else if (*p == '-') p++, inst.operands[i].negative = 1;
5333 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5335 /* We might be using the immediate for alignment already. If we
5336 are, OR the register number into the low-order bits. */
5337 if (inst.operands[i].immisalign)
5338 inst.operands[i].imm |= reg;
5340 inst.operands[i].imm = reg;
5341 inst.operands[i].immisreg = 1;
5343 if (skip_past_comma (&p) == SUCCESS)
5344 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5345 return PARSE_OPERAND_FAIL;
5350 if (inst.operands[i].negative)
5352 inst.operands[i].negative = 0;
5355 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5356 return PARSE_OPERAND_FAIL;
5357 /* If the offset is 0, find out if it's a +0 or -0. */
5358 if (inst.reloc.exp.X_op == O_constant
5359 && inst.reloc.exp.X_add_number == 0)
5361 skip_whitespace (q);
5365 skip_whitespace (q);
5368 inst.operands[i].negative = 1;
5374 /* If at this point neither .preind nor .postind is set, we have a
5375 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5376 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5378 inst.operands[i].preind = 1;
5379 inst.reloc.exp.X_op = O_constant;
5380 inst.reloc.exp.X_add_number = 0;
5383 return PARSE_OPERAND_SUCCESS;
5387 parse_address (char **str, int i)
5389 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5393 static parse_operand_result
5394 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5396 return parse_address_main (str, i, 1, type);
5399 /* Parse an operand for a MOVW or MOVT instruction. */
5401 parse_half (char **str)
5406 skip_past_char (&p, '#');
5407 if (strncasecmp (p, ":lower16:", 9) == 0)
5408 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5409 else if (strncasecmp (p, ":upper16:", 9) == 0)
5410 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5412 if (inst.reloc.type != BFD_RELOC_UNUSED)
5415 skip_whitespace (p);
5418 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5421 if (inst.reloc.type == BFD_RELOC_UNUSED)
5423 if (inst.reloc.exp.X_op != O_constant)
5425 inst.error = _("constant expression expected");
5428 if (inst.reloc.exp.X_add_number < 0
5429 || inst.reloc.exp.X_add_number > 0xffff)
5431 inst.error = _("immediate value out of range");
5439 /* Miscellaneous. */
5441 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5442 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5444 parse_psr (char **str, bfd_boolean lhs)
5447 unsigned long psr_field;
5448 const struct asm_psr *psr;
5450 bfd_boolean is_apsr = FALSE;
5451 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5453 /* PR gas/12698: If the user has specified -march=all then m_profile will
5454 be TRUE, but we want to ignore it in this case as we are building for any
5455 CPU type, including non-m variants. */
5456 if (selected_cpu.core == arm_arch_any.core)
5459 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5460 feature for ease of use and backwards compatibility. */
5462 if (strncasecmp (p, "SPSR", 4) == 0)
5465 goto unsupported_psr;
5467 psr_field = SPSR_BIT;
5469 else if (strncasecmp (p, "CPSR", 4) == 0)
5472 goto unsupported_psr;
5476 else if (strncasecmp (p, "APSR", 4) == 0)
5478 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5479 and ARMv7-R architecture CPUs. */
5488 while (ISALNUM (*p) || *p == '_');
5490 if (strncasecmp (start, "iapsr", 5) == 0
5491 || strncasecmp (start, "eapsr", 5) == 0
5492 || strncasecmp (start, "xpsr", 4) == 0
5493 || strncasecmp (start, "psr", 3) == 0)
5494 p = start + strcspn (start, "rR") + 1;
5496 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5502 /* If APSR is being written, a bitfield may be specified. Note that
5503 APSR itself is handled above. */
5504 if (psr->field <= 3)
5506 psr_field = psr->field;
5512 /* M-profile MSR instructions have the mask field set to "10", except
5513 *PSR variants which modify APSR, which may use a different mask (and
5514 have been handled already). Do that by setting the PSR_f field
5516 return psr->field | (lhs ? PSR_f : 0);
5519 goto unsupported_psr;
5525 /* A suffix follows. */
5531 while (ISALNUM (*p) || *p == '_');
5535 /* APSR uses a notation for bits, rather than fields. */
5536 unsigned int nzcvq_bits = 0;
5537 unsigned int g_bit = 0;
5540 for (bit = start; bit != p; bit++)
5542 switch (TOLOWER (*bit))
5545 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5549 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5553 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5557 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5561 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5565 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5569 inst.error = _("unexpected bit specified after APSR");
5574 if (nzcvq_bits == 0x1f)
5579 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5581 inst.error = _("selected processor does not "
5582 "support DSP extension");
5589 if ((nzcvq_bits & 0x20) != 0
5590 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5591 || (g_bit & 0x2) != 0)
5593 inst.error = _("bad bitmask specified after APSR");
5599 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5604 psr_field |= psr->field;
5610 goto error; /* Garbage after "[CS]PSR". */
5612 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5613 is deprecated, but allow it anyway. */
5617 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5620 else if (!m_profile)
5621 /* These bits are never right for M-profile devices: don't set them
5622 (only code paths which read/write APSR reach here). */
5623 psr_field |= (PSR_c | PSR_f);
5629 inst.error = _("selected processor does not support requested special "
5630 "purpose register");
5634 inst.error = _("flag for {c}psr instruction expected");
5638 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5639 value suitable for splatting into the AIF field of the instruction. */
5642 parse_cps_flags (char **str)
5651 case '\0': case ',':
5654 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5655 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5656 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5659 inst.error = _("unrecognized CPS flag");
5664 if (saw_a_flag == 0)
5666 inst.error = _("missing CPS flags");
5674 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5675 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5678 parse_endian_specifier (char **str)
5683 if (strncasecmp (s, "BE", 2))
5685 else if (strncasecmp (s, "LE", 2))
5689 inst.error = _("valid endian specifiers are be or le");
5693 if (ISALNUM (s[2]) || s[2] == '_')
5695 inst.error = _("valid endian specifiers are be or le");
5700 return little_endian;
5703 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5704 value suitable for poking into the rotate field of an sxt or sxta
5705 instruction, or FAIL on error. */
5708 parse_ror (char **str)
5713 if (strncasecmp (s, "ROR", 3) == 0)
5717 inst.error = _("missing rotation field after comma");
5721 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5726 case 0: *str = s; return 0x0;
5727 case 8: *str = s; return 0x1;
5728 case 16: *str = s; return 0x2;
5729 case 24: *str = s; return 0x3;
5732 inst.error = _("rotation can only be 0, 8, 16, or 24");
5737 /* Parse a conditional code (from conds[] below). The value returned is in the
5738 range 0 .. 14, or FAIL. */
5740 parse_cond (char **str)
5743 const struct asm_cond *c;
5745 /* Condition codes are always 2 characters, so matching up to
5746 3 characters is sufficient. */
5751 while (ISALPHA (*q) && n < 3)
5753 cond[n] = TOLOWER (*q);
5758 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5761 inst.error = _("condition required");
5769 /* Parse an option for a barrier instruction. Returns the encoding for the
5772 parse_barrier (char **str)
5775 const struct asm_barrier_opt *o;
5778 while (ISALPHA (*q))
5781 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5790 /* Parse the operands of a table branch instruction. Similar to a memory
5793 parse_tb (char **str)
5798 if (skip_past_char (&p, '[') == FAIL)
5800 inst.error = _("'[' expected");
5804 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5806 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5809 inst.operands[0].reg = reg;
5811 if (skip_past_comma (&p) == FAIL)
5813 inst.error = _("',' expected");
5817 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5819 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5822 inst.operands[0].imm = reg;
5824 if (skip_past_comma (&p) == SUCCESS)
5826 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5828 if (inst.reloc.exp.X_add_number != 1)
5830 inst.error = _("invalid shift");
5833 inst.operands[0].shifted = 1;
5836 if (skip_past_char (&p, ']') == FAIL)
5838 inst.error = _("']' expected");
5845 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5846 information on the types the operands can take and how they are encoded.
5847 Up to four operands may be read; this function handles setting the
5848 ".present" field for each read operand itself.
5849 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5850 else returns FAIL. */
5853 parse_neon_mov (char **str, int *which_operand)
5855 int i = *which_operand, val;
5856 enum arm_reg_type rtype;
5858 struct neon_type_el optype;
5860 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5862 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5863 inst.operands[i].reg = val;
5864 inst.operands[i].isscalar = 1;
5865 inst.operands[i].vectype = optype;
5866 inst.operands[i++].present = 1;
5868 if (skip_past_comma (&ptr) == FAIL)
5871 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5874 inst.operands[i].reg = val;
5875 inst.operands[i].isreg = 1;
5876 inst.operands[i].present = 1;
5878 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5881 /* Cases 0, 1, 2, 3, 5 (D only). */
5882 if (skip_past_comma (&ptr) == FAIL)
5885 inst.operands[i].reg = val;
5886 inst.operands[i].isreg = 1;
5887 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5888 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5889 inst.operands[i].isvec = 1;
5890 inst.operands[i].vectype = optype;
5891 inst.operands[i++].present = 1;
5893 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5895 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5896 Case 13: VMOV <Sd>, <Rm> */
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5901 if (rtype == REG_TYPE_NQ)
5903 first_error (_("can't use Neon quad register here"));
5906 else if (rtype != REG_TYPE_VFS)
5909 if (skip_past_comma (&ptr) == FAIL)
5911 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5913 inst.operands[i].reg = val;
5914 inst.operands[i].isreg = 1;
5915 inst.operands[i].present = 1;
5918 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5921 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5922 Case 1: VMOV<c><q> <Dd>, <Dm>
5923 Case 8: VMOV.F32 <Sd>, <Sm>
5924 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5926 inst.operands[i].reg = val;
5927 inst.operands[i].isreg = 1;
5928 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5929 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5930 inst.operands[i].isvec = 1;
5931 inst.operands[i].vectype = optype;
5932 inst.operands[i].present = 1;
5934 if (skip_past_comma (&ptr) == SUCCESS)
5939 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5942 inst.operands[i].reg = val;
5943 inst.operands[i].isreg = 1;
5944 inst.operands[i++].present = 1;
5946 if (skip_past_comma (&ptr) == FAIL)
5949 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5952 inst.operands[i].reg = val;
5953 inst.operands[i].isreg = 1;
5954 inst.operands[i].present = 1;
5957 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5958 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5959 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5960 Case 10: VMOV.F32 <Sd>, #<imm>
5961 Case 11: VMOV.F64 <Dd>, #<imm> */
5962 inst.operands[i].immisfloat = 1;
5963 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5964 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5965 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5969 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5973 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5976 inst.operands[i].reg = val;
5977 inst.operands[i].isreg = 1;
5978 inst.operands[i++].present = 1;
5980 if (skip_past_comma (&ptr) == FAIL)
5983 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5985 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5986 inst.operands[i].reg = val;
5987 inst.operands[i].isscalar = 1;
5988 inst.operands[i].present = 1;
5989 inst.operands[i].vectype = optype;
5991 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5993 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5994 inst.operands[i].reg = val;
5995 inst.operands[i].isreg = 1;
5996 inst.operands[i++].present = 1;
5998 if (skip_past_comma (&ptr) == FAIL)
6001 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6004 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6008 inst.operands[i].reg = val;
6009 inst.operands[i].isreg = 1;
6010 inst.operands[i].isvec = 1;
6011 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6012 inst.operands[i].vectype = optype;
6013 inst.operands[i].present = 1;
6015 if (rtype == REG_TYPE_VFS)
6019 if (skip_past_comma (&ptr) == FAIL)
6021 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6024 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6027 inst.operands[i].reg = val;
6028 inst.operands[i].isreg = 1;
6029 inst.operands[i].isvec = 1;
6030 inst.operands[i].issingle = 1;
6031 inst.operands[i].vectype = optype;
6032 inst.operands[i].present = 1;
6035 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6039 inst.operands[i].reg = val;
6040 inst.operands[i].isreg = 1;
6041 inst.operands[i].isvec = 1;
6042 inst.operands[i].issingle = 1;
6043 inst.operands[i].vectype = optype;
6044 inst.operands[i].present = 1;
6049 first_error (_("parse error"));
6053 /* Successfully parsed the operands. Update args. */
6059 first_error (_("expected comma"));
6063 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6067 /* Use this macro when the operand constraints are different
6068 for ARM and THUMB (e.g. ldrd). */
6069 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6070 ((arm_operand) | ((thumb_operand) << 16))
6072 /* Matcher codes for parse_operands. */
6073 enum operand_parse_code
6075 OP_stop, /* end of line */
6077 OP_RR, /* ARM register */
6078 OP_RRnpc, /* ARM register, not r15 */
6079 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6080 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6081 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6082 optional trailing ! */
6083 OP_RRw, /* ARM register, not r15, optional trailing ! */
6084 OP_RCP, /* Coprocessor number */
6085 OP_RCN, /* Coprocessor register */
6086 OP_RF, /* FPA register */
6087 OP_RVS, /* VFP single precision register */
6088 OP_RVD, /* VFP double precision register (0..15) */
6089 OP_RND, /* Neon double precision register (0..31) */
6090 OP_RNQ, /* Neon quad precision register */
6091 OP_RVSD, /* VFP single or double precision register */
6092 OP_RNDQ, /* Neon double or quad precision register */
6093 OP_RNSDQ, /* Neon single, double or quad precision register */
6094 OP_RNSC, /* Neon scalar D[X] */
6095 OP_RVC, /* VFP control register */
6096 OP_RMF, /* Maverick F register */
6097 OP_RMD, /* Maverick D register */
6098 OP_RMFX, /* Maverick FX register */
6099 OP_RMDX, /* Maverick DX register */
6100 OP_RMAX, /* Maverick AX register */
6101 OP_RMDS, /* Maverick DSPSC register */
6102 OP_RIWR, /* iWMMXt wR register */
6103 OP_RIWC, /* iWMMXt wC register */
6104 OP_RIWG, /* iWMMXt wCG register */
6105 OP_RXA, /* XScale accumulator register */
6107 OP_REGLST, /* ARM register list */
6108 OP_VRSLST, /* VFP single-precision register list */
6109 OP_VRDLST, /* VFP double-precision register list */
6110 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6111 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6112 OP_NSTRLST, /* Neon element/structure list */
6114 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6115 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6116 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6117 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6118 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6119 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6120 OP_VMOV, /* Neon VMOV operands. */
6121 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6122 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6123 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6125 OP_I0, /* immediate zero */
6126 OP_I7, /* immediate value 0 .. 7 */
6127 OP_I15, /* 0 .. 15 */
6128 OP_I16, /* 1 .. 16 */
6129 OP_I16z, /* 0 .. 16 */
6130 OP_I31, /* 0 .. 31 */
6131 OP_I31w, /* 0 .. 31, optional trailing ! */
6132 OP_I32, /* 1 .. 32 */
6133 OP_I32z, /* 0 .. 32 */
6134 OP_I63, /* 0 .. 63 */
6135 OP_I63s, /* -64 .. 63 */
6136 OP_I64, /* 1 .. 64 */
6137 OP_I64z, /* 0 .. 64 */
6138 OP_I255, /* 0 .. 255 */
6140 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6141 OP_I7b, /* 0 .. 7 */
6142 OP_I15b, /* 0 .. 15 */
6143 OP_I31b, /* 0 .. 31 */
6145 OP_SH, /* shifter operand */
6146 OP_SHG, /* shifter operand with possible group relocation */
6147 OP_ADDR, /* Memory address expression (any mode) */
6148 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6149 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6150 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6151 OP_EXP, /* arbitrary expression */
6152 OP_EXPi, /* same, with optional immediate prefix */
6153 OP_EXPr, /* same, with optional relocation suffix */
6154 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6156 OP_CPSF, /* CPS flags */
6157 OP_ENDI, /* Endianness specifier */
6158 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6159 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6160 OP_COND, /* conditional code */
6161 OP_TB, /* Table branch. */
6163 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6165 OP_RRnpc_I0, /* ARM register or literal 0 */
6166 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6167 OP_RR_EXi, /* ARM register or expression with imm prefix */
6168 OP_RF_IF, /* FPA register or immediate */
6169 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6170 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6172 /* Optional operands. */
6173 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6174 OP_oI31b, /* 0 .. 31 */
6175 OP_oI32b, /* 1 .. 32 */
6176 OP_oI32z, /* 0 .. 32 */
6177 OP_oIffffb, /* 0 .. 65535 */
6178 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6180 OP_oRR, /* ARM register */
6181 OP_oRRnpc, /* ARM register, not the PC */
6182 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6183 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6184 OP_oRND, /* Optional Neon double precision register */
6185 OP_oRNQ, /* Optional Neon quad precision register */
6186 OP_oRNDQ, /* Optional Neon double or quad precision register */
6187 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6188 OP_oSHll, /* LSL immediate */
6189 OP_oSHar, /* ASR immediate */
6190 OP_oSHllar, /* LSL or ASR immediate */
6191 OP_oROR, /* ROR 0/8/16/24 */
6192 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6194 /* Some pre-defined mixed (ARM/THUMB) operands. */
6195 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6196 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6197 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6199 OP_FIRST_OPTIONAL = OP_oI7b
6202 /* Generic instruction operand parser. This does no encoding and no
6203 semantic validation; it merely squirrels values away in the inst
6204 structure. Returns SUCCESS or FAIL depending on whether the
6205 specified grammar matched. */
6207 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6209 unsigned const int *upat = pattern;
6210 char *backtrack_pos = 0;
6211 const char *backtrack_error = 0;
6212 int i, val = 0, backtrack_index = 0;
6213 enum arm_reg_type rtype;
6214 parse_operand_result result;
6215 unsigned int op_parse_code;
6217 #define po_char_or_fail(chr) \
6220 if (skip_past_char (&str, chr) == FAIL) \
6225 #define po_reg_or_fail(regtype) \
6228 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6229 & inst.operands[i].vectype); \
6232 first_error (_(reg_expected_msgs[regtype])); \
6235 inst.operands[i].reg = val; \
6236 inst.operands[i].isreg = 1; \
6237 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6238 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6239 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6240 || rtype == REG_TYPE_VFD \
6241 || rtype == REG_TYPE_NQ); \
6245 #define po_reg_or_goto(regtype, label) \
6248 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6249 & inst.operands[i].vectype); \
6253 inst.operands[i].reg = val; \
6254 inst.operands[i].isreg = 1; \
6255 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6256 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6257 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6258 || rtype == REG_TYPE_VFD \
6259 || rtype == REG_TYPE_NQ); \
6263 #define po_imm_or_fail(min, max, popt) \
6266 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6268 inst.operands[i].imm = val; \
6272 #define po_scalar_or_goto(elsz, label) \
6275 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6278 inst.operands[i].reg = val; \
6279 inst.operands[i].isscalar = 1; \
6283 #define po_misc_or_fail(expr) \
6291 #define po_misc_or_fail_no_backtrack(expr) \
6295 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6296 backtrack_pos = 0; \
6297 if (result != PARSE_OPERAND_SUCCESS) \
6302 #define po_barrier_or_imm(str) \
6305 val = parse_barrier (&str); \
6308 if (ISALPHA (*str)) \
6315 if ((inst.instruction & 0xf0) == 0x60 \
6318 /* ISB can only take SY as an option. */ \
6319 inst.error = _("invalid barrier type"); \
6326 skip_whitespace (str);
6328 for (i = 0; upat[i] != OP_stop; i++)
6330 op_parse_code = upat[i];
6331 if (op_parse_code >= 1<<16)
6332 op_parse_code = thumb ? (op_parse_code >> 16)
6333 : (op_parse_code & ((1<<16)-1));
6335 if (op_parse_code >= OP_FIRST_OPTIONAL)
6337 /* Remember where we are in case we need to backtrack. */
6338 gas_assert (!backtrack_pos);
6339 backtrack_pos = str;
6340 backtrack_error = inst.error;
6341 backtrack_index = i;
6344 if (i > 0 && (i > 1 || inst.operands[0].present))
6345 po_char_or_fail (',');
6347 switch (op_parse_code)
6355 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6356 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6357 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6358 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6359 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6360 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6362 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6364 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6366 /* Also accept generic coprocessor regs for unknown registers. */
6368 po_reg_or_fail (REG_TYPE_CN);
6370 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6371 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6372 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6373 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6374 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6375 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6376 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6377 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6378 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6379 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6381 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6383 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6384 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6386 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6388 /* Neon scalar. Using an element size of 8 means that some invalid
6389 scalars are accepted here, so deal with those in later code. */
6390 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6394 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6397 po_imm_or_fail (0, 0, TRUE);
6402 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6407 po_scalar_or_goto (8, try_rr);
6410 po_reg_or_fail (REG_TYPE_RN);
6416 po_scalar_or_goto (8, try_nsdq);
6419 po_reg_or_fail (REG_TYPE_NSDQ);
6425 po_scalar_or_goto (8, try_ndq);
6428 po_reg_or_fail (REG_TYPE_NDQ);
6434 po_scalar_or_goto (8, try_vfd);
6437 po_reg_or_fail (REG_TYPE_VFD);
6442 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6443 not careful then bad things might happen. */
6444 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6449 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6452 /* There's a possibility of getting a 64-bit immediate here, so
6453 we need special handling. */
6454 if (parse_big_immediate (&str, i) == FAIL)
6456 inst.error = _("immediate value is out of range");
6464 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6467 po_imm_or_fail (0, 63, TRUE);
6472 po_char_or_fail ('[');
6473 po_reg_or_fail (REG_TYPE_RN);
6474 po_char_or_fail (']');
6480 po_reg_or_fail (REG_TYPE_RN);
6481 if (skip_past_char (&str, '!') == SUCCESS)
6482 inst.operands[i].writeback = 1;
6486 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6487 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6488 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6489 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6490 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6491 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6492 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6493 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6494 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6495 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6496 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6497 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6499 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6501 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6502 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6504 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6505 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6506 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6507 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6509 /* Immediate variants */
6511 po_char_or_fail ('{');
6512 po_imm_or_fail (0, 255, TRUE);
6513 po_char_or_fail ('}');
6517 /* The expression parser chokes on a trailing !, so we have
6518 to find it first and zap it. */
6521 while (*s && *s != ',')
6526 inst.operands[i].writeback = 1;
6528 po_imm_or_fail (0, 31, TRUE);
6536 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6541 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6546 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6548 if (inst.reloc.exp.X_op == O_symbol)
6550 val = parse_reloc (&str);
6553 inst.error = _("unrecognized relocation suffix");
6556 else if (val != BFD_RELOC_UNUSED)
6558 inst.operands[i].imm = val;
6559 inst.operands[i].hasreloc = 1;
6564 /* Operand for MOVW or MOVT. */
6566 po_misc_or_fail (parse_half (&str));
6569 /* Register or expression. */
6570 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6571 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6573 /* Register or immediate. */
6574 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6575 I0: po_imm_or_fail (0, 0, FALSE); break;
6577 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6579 if (!is_immediate_prefix (*str))
6582 val = parse_fpa_immediate (&str);
6585 /* FPA immediates are encoded as registers 8-15.
6586 parse_fpa_immediate has already applied the offset. */
6587 inst.operands[i].reg = val;
6588 inst.operands[i].isreg = 1;
6591 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6592 I32z: po_imm_or_fail (0, 32, FALSE); break;
6594 /* Two kinds of register. */
6597 struct reg_entry *rege = arm_reg_parse_multi (&str);
6599 || (rege->type != REG_TYPE_MMXWR
6600 && rege->type != REG_TYPE_MMXWC
6601 && rege->type != REG_TYPE_MMXWCG))
6603 inst.error = _("iWMMXt data or control register expected");
6606 inst.operands[i].reg = rege->number;
6607 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6613 struct reg_entry *rege = arm_reg_parse_multi (&str);
6615 || (rege->type != REG_TYPE_MMXWC
6616 && rege->type != REG_TYPE_MMXWCG))
6618 inst.error = _("iWMMXt control register expected");
6621 inst.operands[i].reg = rege->number;
6622 inst.operands[i].isreg = 1;
6627 case OP_CPSF: val = parse_cps_flags (&str); break;
6628 case OP_ENDI: val = parse_endian_specifier (&str); break;
6629 case OP_oROR: val = parse_ror (&str); break;
6630 case OP_COND: val = parse_cond (&str); break;
6631 case OP_oBARRIER_I15:
6632 po_barrier_or_imm (str); break;
6634 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6640 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6641 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6643 inst.error = _("Banked registers are not available with this "
6649 val = parse_psr (&str, op_parse_code == OP_wPSR);
6653 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6656 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6658 if (strncasecmp (str, "APSR_", 5) == 0)
6665 case 'c': found = (found & 1) ? 16 : found | 1; break;
6666 case 'n': found = (found & 2) ? 16 : found | 2; break;
6667 case 'z': found = (found & 4) ? 16 : found | 4; break;
6668 case 'v': found = (found & 8) ? 16 : found | 8; break;
6669 default: found = 16;
6673 inst.operands[i].isvec = 1;
6674 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6675 inst.operands[i].reg = REG_PC;
6682 po_misc_or_fail (parse_tb (&str));
6685 /* Register lists. */
6687 val = parse_reg_list (&str);
6690 inst.operands[1].writeback = 1;
6696 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6700 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6704 /* Allow Q registers too. */
6705 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6710 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6712 inst.operands[i].issingle = 1;
6717 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6722 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6723 &inst.operands[i].vectype);
6726 /* Addressing modes */
6728 po_misc_or_fail (parse_address (&str, i));
6732 po_misc_or_fail_no_backtrack (
6733 parse_address_group_reloc (&str, i, GROUP_LDR));
6737 po_misc_or_fail_no_backtrack (
6738 parse_address_group_reloc (&str, i, GROUP_LDRS));
6742 po_misc_or_fail_no_backtrack (
6743 parse_address_group_reloc (&str, i, GROUP_LDC));
6747 po_misc_or_fail (parse_shifter_operand (&str, i));
6751 po_misc_or_fail_no_backtrack (
6752 parse_shifter_operand_group_reloc (&str, i));
6756 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6760 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6764 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6768 as_fatal (_("unhandled operand code %d"), op_parse_code);
6771 /* Various value-based sanity checks and shared operations. We
6772 do not signal immediate failures for the register constraints;
6773 this allows a syntax error to take precedence. */
6774 switch (op_parse_code)
6782 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6783 inst.error = BAD_PC;
6788 if (inst.operands[i].isreg)
6790 if (inst.operands[i].reg == REG_PC)
6791 inst.error = BAD_PC;
6792 else if (inst.operands[i].reg == REG_SP)
6793 inst.error = BAD_SP;
6798 if (inst.operands[i].isreg
6799 && inst.operands[i].reg == REG_PC
6800 && (inst.operands[i].writeback || thumb))
6801 inst.error = BAD_PC;
6810 case OP_oBARRIER_I15:
6819 inst.operands[i].imm = val;
6826 /* If we get here, this operand was successfully parsed. */
6827 inst.operands[i].present = 1;
6831 inst.error = BAD_ARGS;
6836 /* The parse routine should already have set inst.error, but set a
6837 default here just in case. */
6839 inst.error = _("syntax error");
6843 /* Do not backtrack over a trailing optional argument that
6844 absorbed some text. We will only fail again, with the
6845 'garbage following instruction' error message, which is
6846 probably less helpful than the current one. */
6847 if (backtrack_index == i && backtrack_pos != str
6848 && upat[i+1] == OP_stop)
6851 inst.error = _("syntax error");
6855 /* Try again, skipping the optional argument at backtrack_pos. */
6856 str = backtrack_pos;
6857 inst.error = backtrack_error;
6858 inst.operands[backtrack_index].present = 0;
6859 i = backtrack_index;
6863 /* Check that we have parsed all the arguments. */
6864 if (*str != '\0' && !inst.error)
6865 inst.error = _("garbage following instruction");
6867 return inst.error ? FAIL : SUCCESS;
6870 #undef po_char_or_fail
6871 #undef po_reg_or_fail
6872 #undef po_reg_or_goto
6873 #undef po_imm_or_fail
6874 #undef po_scalar_or_fail
6875 #undef po_barrier_or_imm
6877 /* Shorthand macro for instruction encoding functions issuing errors. */
6878 #define constraint(expr, err) \
6889 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6890 instructions are unpredictable if these registers are used. This
6891 is the BadReg predicate in ARM's Thumb-2 documentation. */
6892 #define reject_bad_reg(reg) \
6894 if (reg == REG_SP || reg == REG_PC) \
6896 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6901 /* If REG is R13 (the stack pointer), warn that its use is
6903 #define warn_deprecated_sp(reg) \
6905 if (warn_on_deprecated && reg == REG_SP) \
6906 as_warn (_("use of r13 is deprecated")); \
6909 /* Functions for operand encoding. ARM, then Thumb. */
6911 #define rotate_left(v, n) (v << n | v >> (32 - n))
6913 /* If VAL can be encoded in the immediate field of an ARM instruction,
6914 return the encoded form. Otherwise, return FAIL. */
6917 encode_arm_immediate (unsigned int val)
6921 for (i = 0; i < 32; i += 2)
6922 if ((a = rotate_left (val, i)) <= 0xff)
6923 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6928 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6929 return the encoded form. Otherwise, return FAIL. */
6931 encode_thumb32_immediate (unsigned int val)
6938 for (i = 1; i <= 24; i++)
6941 if ((val & ~(0xff << i)) == 0)
6942 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6946 if (val == ((a << 16) | a))
6948 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6952 if (val == ((a << 16) | a))
6953 return 0x200 | (a >> 8);
6957 /* Encode a VFP SP or DP register number into inst.instruction. */
6960 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6962 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6965 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6968 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6971 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6976 first_error (_("D register out of range for selected VFP version"));
6984 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6988 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6992 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6996 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7000 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7004 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7012 /* Encode a <shift> in an ARM-format instruction. The immediate,
7013 if any, is handled by md_apply_fix. */
7015 encode_arm_shift (int i)
7017 if (inst.operands[i].shift_kind == SHIFT_RRX)
7018 inst.instruction |= SHIFT_ROR << 5;
7021 inst.instruction |= inst.operands[i].shift_kind << 5;
7022 if (inst.operands[i].immisreg)
7024 inst.instruction |= SHIFT_BY_REG;
7025 inst.instruction |= inst.operands[i].imm << 8;
7028 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7033 encode_arm_shifter_operand (int i)
7035 if (inst.operands[i].isreg)
7037 inst.instruction |= inst.operands[i].reg;
7038 encode_arm_shift (i);
7042 inst.instruction |= INST_IMMEDIATE;
7043 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7044 inst.instruction |= inst.operands[i].imm;
7048 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7050 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7053 Generate an error if the operand is not a register. */
7054 constraint (!inst.operands[i].isreg,
7055 _("Instruction does not support =N addresses"));
7057 inst.instruction |= inst.operands[i].reg << 16;
7059 if (inst.operands[i].preind)
7063 inst.error = _("instruction does not accept preindexed addressing");
7066 inst.instruction |= PRE_INDEX;
7067 if (inst.operands[i].writeback)
7068 inst.instruction |= WRITE_BACK;
7071 else if (inst.operands[i].postind)
7073 gas_assert (inst.operands[i].writeback);
7075 inst.instruction |= WRITE_BACK;
7077 else /* unindexed - only for coprocessor */
7079 inst.error = _("instruction does not accept unindexed addressing");
7083 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7084 && (((inst.instruction & 0x000f0000) >> 16)
7085 == ((inst.instruction & 0x0000f000) >> 12)))
7086 as_warn ((inst.instruction & LOAD_BIT)
7087 ? _("destination register same as write-back base")
7088 : _("source register same as write-back base"));
7091 /* inst.operands[i] was set up by parse_address. Encode it into an
7092 ARM-format mode 2 load or store instruction. If is_t is true,
7093 reject forms that cannot be used with a T instruction (i.e. not
7096 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7098 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7100 encode_arm_addr_mode_common (i, is_t);
7102 if (inst.operands[i].immisreg)
7104 constraint ((inst.operands[i].imm == REG_PC
7105 || (is_pc && inst.operands[i].writeback)),
7107 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7108 inst.instruction |= inst.operands[i].imm;
7109 if (!inst.operands[i].negative)
7110 inst.instruction |= INDEX_UP;
7111 if (inst.operands[i].shifted)
7113 if (inst.operands[i].shift_kind == SHIFT_RRX)
7114 inst.instruction |= SHIFT_ROR << 5;
7117 inst.instruction |= inst.operands[i].shift_kind << 5;
7118 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7122 else /* immediate offset in inst.reloc */
7124 if (is_pc && !inst.reloc.pc_rel)
7126 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7128 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7129 cannot use PC in addressing.
7130 PC cannot be used in writeback addressing, either. */
7131 constraint ((is_t || inst.operands[i].writeback),
7134 /* Use of PC in str is deprecated for ARMv7. */
7135 if (warn_on_deprecated
7137 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7138 as_warn (_("use of PC in this instruction is deprecated"));
7141 if (inst.reloc.type == BFD_RELOC_UNUSED)
7143 /* Prefer + for zero encoded value. */
7144 if (!inst.operands[i].negative)
7145 inst.instruction |= INDEX_UP;
7146 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7151 /* inst.operands[i] was set up by parse_address. Encode it into an
7152 ARM-format mode 3 load or store instruction. Reject forms that
7153 cannot be used with such instructions. If is_t is true, reject
7154 forms that cannot be used with a T instruction (i.e. not
7157 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7159 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7161 inst.error = _("instruction does not accept scaled register index");
7165 encode_arm_addr_mode_common (i, is_t);
7167 if (inst.operands[i].immisreg)
7169 constraint ((inst.operands[i].imm == REG_PC
7170 || inst.operands[i].reg == REG_PC),
7172 inst.instruction |= inst.operands[i].imm;
7173 if (!inst.operands[i].negative)
7174 inst.instruction |= INDEX_UP;
7176 else /* immediate offset in inst.reloc */
7178 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7179 && inst.operands[i].writeback),
7181 inst.instruction |= HWOFFSET_IMM;
7182 if (inst.reloc.type == BFD_RELOC_UNUSED)
7184 /* Prefer + for zero encoded value. */
7185 if (!inst.operands[i].negative)
7186 inst.instruction |= INDEX_UP;
7188 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7193 /* inst.operands[i] was set up by parse_address. Encode it into an
7194 ARM-format instruction. Reject all forms which cannot be encoded
7195 into a coprocessor load/store instruction. If wb_ok is false,
7196 reject use of writeback; if unind_ok is false, reject use of
7197 unindexed addressing. If reloc_override is not 0, use it instead
7198 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7199 (in which case it is preserved). */
7202 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7204 inst.instruction |= inst.operands[i].reg << 16;
7206 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7208 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7210 gas_assert (!inst.operands[i].writeback);
7213 inst.error = _("instruction does not support unindexed addressing");
7216 inst.instruction |= inst.operands[i].imm;
7217 inst.instruction |= INDEX_UP;
7221 if (inst.operands[i].preind)
7222 inst.instruction |= PRE_INDEX;
7224 if (inst.operands[i].writeback)
7226 if (inst.operands[i].reg == REG_PC)
7228 inst.error = _("pc may not be used with write-back");
7233 inst.error = _("instruction does not support writeback");
7236 inst.instruction |= WRITE_BACK;
7240 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7241 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7242 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7243 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7246 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7248 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7251 /* Prefer + for zero encoded value. */
7252 if (!inst.operands[i].negative)
7253 inst.instruction |= INDEX_UP;
7258 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7259 Determine whether it can be performed with a move instruction; if
7260 it can, convert inst.instruction to that move instruction and
7261 return TRUE; if it can't, convert inst.instruction to a literal-pool
7262 load and return FALSE. If this is not a valid thing to do in the
7263 current context, set inst.error and return TRUE.
7265 inst.operands[i] describes the destination register. */
7268 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7273 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7277 if ((inst.instruction & tbit) == 0)
7279 inst.error = _("invalid pseudo operation");
7282 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7284 inst.error = _("constant expression expected");
7287 if (inst.reloc.exp.X_op == O_constant)
7291 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7293 /* This can be done with a mov(1) instruction. */
7294 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7295 inst.instruction |= inst.reloc.exp.X_add_number;
7301 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7304 /* This can be done with a mov instruction. */
7305 inst.instruction &= LITERAL_MASK;
7306 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7307 inst.instruction |= value & 0xfff;
7311 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7314 /* This can be done with a mvn instruction. */
7315 inst.instruction &= LITERAL_MASK;
7316 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7317 inst.instruction |= value & 0xfff;
7323 if (add_to_lit_pool () == FAIL)
7325 inst.error = _("literal pool insertion failed");
7328 inst.operands[1].reg = REG_PC;
7329 inst.operands[1].isreg = 1;
7330 inst.operands[1].preind = 1;
7331 inst.reloc.pc_rel = 1;
7332 inst.reloc.type = (thumb_p
7333 ? BFD_RELOC_ARM_THUMB_OFFSET
7335 ? BFD_RELOC_ARM_HWLITERAL
7336 : BFD_RELOC_ARM_LITERAL));
7340 /* Functions for instruction encoding, sorted by sub-architecture.
7341 First some generics; their names are taken from the conventional
7342 bit positions for register arguments in ARM format instructions. */
7352 inst.instruction |= inst.operands[0].reg << 12;
7358 inst.instruction |= inst.operands[0].reg << 12;
7359 inst.instruction |= inst.operands[1].reg;
7365 inst.instruction |= inst.operands[0].reg << 12;
7366 inst.instruction |= inst.operands[1].reg << 16;
7372 inst.instruction |= inst.operands[0].reg << 16;
7373 inst.instruction |= inst.operands[1].reg << 12;
7377 check_obsolete (const arm_feature_set *feature, const char *msg)
7379 if (ARM_CPU_IS_ANY (cpu_variant))
7381 as_warn ("%s", msg);
7384 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7396 unsigned Rn = inst.operands[2].reg;
7397 /* Enforce restrictions on SWP instruction. */
7398 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7400 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7401 _("Rn must not overlap other operands"));
7403 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7405 if (!check_obsolete (&arm_ext_v8,
7406 _("swp{b} use is obsoleted for ARMv8 and later"))
7407 && warn_on_deprecated
7408 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7409 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7412 inst.instruction |= inst.operands[0].reg << 12;
7413 inst.instruction |= inst.operands[1].reg;
7414 inst.instruction |= Rn << 16;
7420 inst.instruction |= inst.operands[0].reg << 12;
7421 inst.instruction |= inst.operands[1].reg << 16;
7422 inst.instruction |= inst.operands[2].reg;
7428 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7429 constraint (((inst.reloc.exp.X_op != O_constant
7430 && inst.reloc.exp.X_op != O_illegal)
7431 || inst.reloc.exp.X_add_number != 0),
7433 inst.instruction |= inst.operands[0].reg;
7434 inst.instruction |= inst.operands[1].reg << 12;
7435 inst.instruction |= inst.operands[2].reg << 16;
7441 inst.instruction |= inst.operands[0].imm;
7447 inst.instruction |= inst.operands[0].reg << 12;
7448 encode_arm_cp_address (1, TRUE, TRUE, 0);
7451 /* ARM instructions, in alphabetical order by function name (except
7452 that wrapper functions appear immediately after the function they
7455 /* This is a pseudo-op of the form "adr rd, label" to be converted
7456 into a relative address of the form "add rd, pc, #label-.-8". */
7461 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7463 /* Frag hacking will turn this into a sub instruction if the offset turns
7464 out to be negative. */
7465 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7466 inst.reloc.pc_rel = 1;
7467 inst.reloc.exp.X_add_number -= 8;
7470 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7471 into a relative address of the form:
7472 add rd, pc, #low(label-.-8)"
7473 add rd, rd, #high(label-.-8)" */
7478 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7480 /* Frag hacking will turn this into a sub instruction if the offset turns
7481 out to be negative. */
7482 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7483 inst.reloc.pc_rel = 1;
7484 inst.size = INSN_SIZE * 2;
7485 inst.reloc.exp.X_add_number -= 8;
7491 if (!inst.operands[1].present)
7492 inst.operands[1].reg = inst.operands[0].reg;
7493 inst.instruction |= inst.operands[0].reg << 12;
7494 inst.instruction |= inst.operands[1].reg << 16;
7495 encode_arm_shifter_operand (2);
7501 if (inst.operands[0].present)
7503 constraint ((inst.instruction & 0xf0) != 0x40
7504 && inst.operands[0].imm > 0xf
7505 && inst.operands[0].imm < 0x0,
7506 _("bad barrier type"));
7507 inst.instruction |= inst.operands[0].imm;
7510 inst.instruction |= 0xf;
7516 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7517 constraint (msb > 32, _("bit-field extends past end of register"));
7518 /* The instruction encoding stores the LSB and MSB,
7519 not the LSB and width. */
7520 inst.instruction |= inst.operands[0].reg << 12;
7521 inst.instruction |= inst.operands[1].imm << 7;
7522 inst.instruction |= (msb - 1) << 16;
7530 /* #0 in second position is alternative syntax for bfc, which is
7531 the same instruction but with REG_PC in the Rm field. */
7532 if (!inst.operands[1].isreg)
7533 inst.operands[1].reg = REG_PC;
7535 msb = inst.operands[2].imm + inst.operands[3].imm;
7536 constraint (msb > 32, _("bit-field extends past end of register"));
7537 /* The instruction encoding stores the LSB and MSB,
7538 not the LSB and width. */
7539 inst.instruction |= inst.operands[0].reg << 12;
7540 inst.instruction |= inst.operands[1].reg;
7541 inst.instruction |= inst.operands[2].imm << 7;
7542 inst.instruction |= (msb - 1) << 16;
7548 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7549 _("bit-field extends past end of register"));
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].reg;
7552 inst.instruction |= inst.operands[2].imm << 7;
7553 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7556 /* ARM V5 breakpoint instruction (argument parse)
7557 BKPT <16 bit unsigned immediate>
7558 Instruction is not conditional.
7559 The bit pattern given in insns[] has the COND_ALWAYS condition,
7560 and it is an error if the caller tried to override that. */
7565 /* Top 12 of 16 bits to bits 19:8. */
7566 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7568 /* Bottom 4 of 16 bits to bits 3:0. */
7569 inst.instruction |= inst.operands[0].imm & 0xf;
7573 encode_branch (int default_reloc)
7575 if (inst.operands[0].hasreloc)
7577 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7578 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7579 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7580 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7581 ? BFD_RELOC_ARM_PLT32
7582 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7585 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7586 inst.reloc.pc_rel = 1;
7593 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7594 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7597 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7604 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7606 if (inst.cond == COND_ALWAYS)
7607 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7609 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7613 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7616 /* ARM V5 branch-link-exchange instruction (argument parse)
7617 BLX <target_addr> ie BLX(1)
7618 BLX{<condition>} <Rm> ie BLX(2)
7619 Unfortunately, there are two different opcodes for this mnemonic.
7620 So, the insns[].value is not used, and the code here zaps values
7621 into inst.instruction.
7622 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7627 if (inst.operands[0].isreg)
7629 /* Arg is a register; the opcode provided by insns[] is correct.
7630 It is not illegal to do "blx pc", just useless. */
7631 if (inst.operands[0].reg == REG_PC)
7632 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7634 inst.instruction |= inst.operands[0].reg;
7638 /* Arg is an address; this instruction cannot be executed
7639 conditionally, and the opcode must be adjusted.
7640 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7641 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7642 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7643 inst.instruction = 0xfa000000;
7644 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7651 bfd_boolean want_reloc;
7653 if (inst.operands[0].reg == REG_PC)
7654 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7656 inst.instruction |= inst.operands[0].reg;
7657 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7658 it is for ARMv4t or earlier. */
7659 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7660 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7664 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7669 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7673 /* ARM v5TEJ. Jump to Jazelle code. */
7678 if (inst.operands[0].reg == REG_PC)
7679 as_tsktsk (_("use of r15 in bxj is not really useful"));
7681 inst.instruction |= inst.operands[0].reg;
7684 /* Co-processor data operation:
7685 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7686 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7690 inst.instruction |= inst.operands[0].reg << 8;
7691 inst.instruction |= inst.operands[1].imm << 20;
7692 inst.instruction |= inst.operands[2].reg << 12;
7693 inst.instruction |= inst.operands[3].reg << 16;
7694 inst.instruction |= inst.operands[4].reg;
7695 inst.instruction |= inst.operands[5].imm << 5;
7701 inst.instruction |= inst.operands[0].reg << 16;
7702 encode_arm_shifter_operand (1);
7705 /* Transfer between coprocessor and ARM registers.
7706 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7711 No special properties. */
7713 struct deprecated_coproc_regs_s
7720 arm_feature_set deprecated;
7721 arm_feature_set obsoleted;
7722 const char *dep_msg;
7723 const char *obs_msg;
7726 #define DEPR_ACCESS_V8 \
7727 N_("This coprocessor register access is deprecated in ARMv8")
7729 /* Table of all deprecated coprocessor registers. */
7730 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7732 {15, 0, 7, 10, 5, /* CP15DMB. */
7733 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7734 DEPR_ACCESS_V8, NULL},
7735 {15, 0, 7, 10, 4, /* CP15DSB. */
7736 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7737 DEPR_ACCESS_V8, NULL},
7738 {15, 0, 7, 5, 4, /* CP15ISB. */
7739 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7740 DEPR_ACCESS_V8, NULL},
7741 {14, 6, 1, 0, 0, /* TEEHBR. */
7742 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7743 DEPR_ACCESS_V8, NULL},
7744 {14, 6, 0, 0, 0, /* TEECR. */
7745 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7746 DEPR_ACCESS_V8, NULL},
7749 #undef DEPR_ACCESS_V8
7751 static const size_t deprecated_coproc_reg_count =
7752 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7760 Rd = inst.operands[2].reg;
7763 if (inst.instruction == 0xee000010
7764 || inst.instruction == 0xfe000010)
7766 reject_bad_reg (Rd);
7769 constraint (Rd == REG_SP, BAD_SP);
7774 if (inst.instruction == 0xe000010)
7775 constraint (Rd == REG_PC, BAD_PC);
7778 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7780 const struct deprecated_coproc_regs_s *r =
7781 deprecated_coproc_regs + i;
7783 if (inst.operands[0].reg == r->cp
7784 && inst.operands[1].imm == r->opc1
7785 && inst.operands[3].reg == r->crn
7786 && inst.operands[4].reg == r->crm
7787 && inst.operands[5].imm == r->opc2)
7789 if (!check_obsolete (&r->obsoleted, r->obs_msg)
7790 && warn_on_deprecated
7791 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7792 as_warn ("%s", r->dep_msg);
7796 inst.instruction |= inst.operands[0].reg << 8;
7797 inst.instruction |= inst.operands[1].imm << 21;
7798 inst.instruction |= Rd << 12;
7799 inst.instruction |= inst.operands[3].reg << 16;
7800 inst.instruction |= inst.operands[4].reg;
7801 inst.instruction |= inst.operands[5].imm << 5;
7804 /* Transfer between coprocessor register and pair of ARM registers.
7805 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7810 Two XScale instructions are special cases of these:
7812 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7813 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7815 Result unpredictable if Rd or Rn is R15. */
7822 Rd = inst.operands[2].reg;
7823 Rn = inst.operands[3].reg;
7827 reject_bad_reg (Rd);
7828 reject_bad_reg (Rn);
7832 constraint (Rd == REG_PC, BAD_PC);
7833 constraint (Rn == REG_PC, BAD_PC);
7836 inst.instruction |= inst.operands[0].reg << 8;
7837 inst.instruction |= inst.operands[1].imm << 4;
7838 inst.instruction |= Rd << 12;
7839 inst.instruction |= Rn << 16;
7840 inst.instruction |= inst.operands[4].reg;
7846 inst.instruction |= inst.operands[0].imm << 6;
7847 if (inst.operands[1].present)
7849 inst.instruction |= CPSI_MMOD;
7850 inst.instruction |= inst.operands[1].imm;
7857 inst.instruction |= inst.operands[0].imm;
7863 unsigned Rd, Rn, Rm;
7865 Rd = inst.operands[0].reg;
7866 Rn = (inst.operands[1].present
7867 ? inst.operands[1].reg : Rd);
7868 Rm = inst.operands[2].reg;
7870 constraint ((Rd == REG_PC), BAD_PC);
7871 constraint ((Rn == REG_PC), BAD_PC);
7872 constraint ((Rm == REG_PC), BAD_PC);
7874 inst.instruction |= Rd << 16;
7875 inst.instruction |= Rn << 0;
7876 inst.instruction |= Rm << 8;
7882 /* There is no IT instruction in ARM mode. We
7883 process it to do the validation as if in
7884 thumb mode, just in case the code gets
7885 assembled for thumb using the unified syntax. */
7890 set_it_insn_type (IT_INSN);
7891 now_it.mask = (inst.instruction & 0xf) | 0x10;
7892 now_it.cc = inst.operands[0].imm;
7896 /* If there is only one register in the register list,
7897 then return its register number. Otherwise return -1. */
7899 only_one_reg_in_list (int range)
7901 int i = ffs (range) - 1;
7902 return (i > 15 || range != (1 << i)) ? -1 : i;
7906 encode_ldmstm(int from_push_pop_mnem)
7908 int base_reg = inst.operands[0].reg;
7909 int range = inst.operands[1].imm;
7912 inst.instruction |= base_reg << 16;
7913 inst.instruction |= range;
7915 if (inst.operands[1].writeback)
7916 inst.instruction |= LDM_TYPE_2_OR_3;
7918 if (inst.operands[0].writeback)
7920 inst.instruction |= WRITE_BACK;
7921 /* Check for unpredictable uses of writeback. */
7922 if (inst.instruction & LOAD_BIT)
7924 /* Not allowed in LDM type 2. */
7925 if ((inst.instruction & LDM_TYPE_2_OR_3)
7926 && ((range & (1 << REG_PC)) == 0))
7927 as_warn (_("writeback of base register is UNPREDICTABLE"));
7928 /* Only allowed if base reg not in list for other types. */
7929 else if (range & (1 << base_reg))
7930 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7934 /* Not allowed for type 2. */
7935 if (inst.instruction & LDM_TYPE_2_OR_3)
7936 as_warn (_("writeback of base register is UNPREDICTABLE"));
7937 /* Only allowed if base reg not in list, or first in list. */
7938 else if ((range & (1 << base_reg))
7939 && (range & ((1 << base_reg) - 1)))
7940 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7944 /* If PUSH/POP has only one register, then use the A2 encoding. */
7945 one_reg = only_one_reg_in_list (range);
7946 if (from_push_pop_mnem && one_reg >= 0)
7948 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7950 inst.instruction &= A_COND_MASK;
7951 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7952 inst.instruction |= one_reg << 12;
7959 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7962 /* ARMv5TE load-consecutive (argument parse)
7971 constraint (inst.operands[0].reg % 2 != 0,
7972 _("first transfer register must be even"));
7973 constraint (inst.operands[1].present
7974 && inst.operands[1].reg != inst.operands[0].reg + 1,
7975 _("can only transfer two consecutive registers"));
7976 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7977 constraint (!inst.operands[2].isreg, _("'[' expected"));
7979 if (!inst.operands[1].present)
7980 inst.operands[1].reg = inst.operands[0].reg + 1;
7982 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7983 register and the first register written; we have to diagnose
7984 overlap between the base and the second register written here. */
7986 if (inst.operands[2].reg == inst.operands[1].reg
7987 && (inst.operands[2].writeback || inst.operands[2].postind))
7988 as_warn (_("base register written back, and overlaps "
7989 "second transfer register"));
7991 if (!(inst.instruction & V4_STR_BIT))
7993 /* For an index-register load, the index register must not overlap the
7994 destination (even if not write-back). */
7995 if (inst.operands[2].immisreg
7996 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7997 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7998 as_warn (_("index register overlaps transfer register"));
8000 inst.instruction |= inst.operands[0].reg << 12;
8001 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8007 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8008 || inst.operands[1].postind || inst.operands[1].writeback
8009 || inst.operands[1].immisreg || inst.operands[1].shifted
8010 || inst.operands[1].negative
8011 /* This can arise if the programmer has written
8013 or if they have mistakenly used a register name as the last
8016 It is very difficult to distinguish between these two cases
8017 because "rX" might actually be a label. ie the register
8018 name has been occluded by a symbol of the same name. So we
8019 just generate a general 'bad addressing mode' type error
8020 message and leave it up to the programmer to discover the
8021 true cause and fix their mistake. */
8022 || (inst.operands[1].reg == REG_PC),
8025 constraint (inst.reloc.exp.X_op != O_constant
8026 || inst.reloc.exp.X_add_number != 0,
8027 _("offset must be zero in ARM encoding"));
8029 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8031 inst.instruction |= inst.operands[0].reg << 12;
8032 inst.instruction |= inst.operands[1].reg << 16;
8033 inst.reloc.type = BFD_RELOC_UNUSED;
8039 constraint (inst.operands[0].reg % 2 != 0,
8040 _("even register required"));
8041 constraint (inst.operands[1].present
8042 && inst.operands[1].reg != inst.operands[0].reg + 1,
8043 _("can only load two consecutive registers"));
8044 /* If op 1 were present and equal to PC, this function wouldn't
8045 have been called in the first place. */
8046 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8048 inst.instruction |= inst.operands[0].reg << 12;
8049 inst.instruction |= inst.operands[2].reg << 16;
8052 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8053 which is not a multiple of four is UNPREDICTABLE. */
8055 check_ldr_r15_aligned (void)
8057 constraint (!(inst.operands[1].immisreg)
8058 && (inst.operands[0].reg == REG_PC
8059 && inst.operands[1].reg == REG_PC
8060 && (inst.reloc.exp.X_add_number & 0x3)),
8061 _("ldr to register 15 must be 4-byte alligned"));
8067 inst.instruction |= inst.operands[0].reg << 12;
8068 if (!inst.operands[1].isreg)
8069 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8071 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8072 check_ldr_r15_aligned ();
8078 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8080 if (inst.operands[1].preind)
8082 constraint (inst.reloc.exp.X_op != O_constant
8083 || inst.reloc.exp.X_add_number != 0,
8084 _("this instruction requires a post-indexed address"));
8086 inst.operands[1].preind = 0;
8087 inst.operands[1].postind = 1;
8088 inst.operands[1].writeback = 1;
8090 inst.instruction |= inst.operands[0].reg << 12;
8091 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8094 /* Halfword and signed-byte load/store operations. */
8099 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8100 inst.instruction |= inst.operands[0].reg << 12;
8101 if (!inst.operands[1].isreg)
8102 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8104 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8110 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8112 if (inst.operands[1].preind)
8114 constraint (inst.reloc.exp.X_op != O_constant
8115 || inst.reloc.exp.X_add_number != 0,
8116 _("this instruction requires a post-indexed address"));
8118 inst.operands[1].preind = 0;
8119 inst.operands[1].postind = 1;
8120 inst.operands[1].writeback = 1;
8122 inst.instruction |= inst.operands[0].reg << 12;
8123 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8126 /* Co-processor register load/store.
8127 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8131 inst.instruction |= inst.operands[0].reg << 8;
8132 inst.instruction |= inst.operands[1].reg << 12;
8133 encode_arm_cp_address (2, TRUE, TRUE, 0);
8139 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8140 if (inst.operands[0].reg == inst.operands[1].reg
8141 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8142 && !(inst.instruction & 0x00400000))
8143 as_tsktsk (_("Rd and Rm should be different in mla"));
8145 inst.instruction |= inst.operands[0].reg << 16;
8146 inst.instruction |= inst.operands[1].reg;
8147 inst.instruction |= inst.operands[2].reg << 8;
8148 inst.instruction |= inst.operands[3].reg << 12;
8154 inst.instruction |= inst.operands[0].reg << 12;
8155 encode_arm_shifter_operand (1);
8158 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8165 top = (inst.instruction & 0x00400000) != 0;
8166 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8167 _(":lower16: not allowed this instruction"));
8168 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8169 _(":upper16: not allowed instruction"));
8170 inst.instruction |= inst.operands[0].reg << 12;
8171 if (inst.reloc.type == BFD_RELOC_UNUSED)
8173 imm = inst.reloc.exp.X_add_number;
8174 /* The value is in two pieces: 0:11, 16:19. */
8175 inst.instruction |= (imm & 0x00000fff);
8176 inst.instruction |= (imm & 0x0000f000) << 4;
8180 static void do_vfp_nsyn_opcode (const char *);
8183 do_vfp_nsyn_mrs (void)
8185 if (inst.operands[0].isvec)
8187 if (inst.operands[1].reg != 1)
8188 first_error (_("operand 1 must be FPSCR"));
8189 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8190 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8191 do_vfp_nsyn_opcode ("fmstat");
8193 else if (inst.operands[1].isvec)
8194 do_vfp_nsyn_opcode ("fmrx");
8202 do_vfp_nsyn_msr (void)
8204 if (inst.operands[0].isvec)
8205 do_vfp_nsyn_opcode ("fmxr");
8215 unsigned Rt = inst.operands[0].reg;
8217 if (thumb_mode && inst.operands[0].reg == REG_SP)
8219 inst.error = BAD_SP;
8223 /* APSR_ sets isvec. All other refs to PC are illegal. */
8224 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8226 inst.error = BAD_PC;
8230 switch (inst.operands[1].reg)
8237 inst.instruction |= (inst.operands[1].reg << 16);
8240 first_error (_("operand 1 must be a VFP extension System Register"));
8243 inst.instruction |= (Rt << 12);
8249 unsigned Rt = inst.operands[1].reg;
8252 reject_bad_reg (Rt);
8253 else if (Rt == REG_PC)
8255 inst.error = BAD_PC;
8259 switch (inst.operands[0].reg)
8264 inst.instruction |= (inst.operands[0].reg << 16);
8267 first_error (_("operand 0 must be FPSID or FPSCR pr FPEXC"));
8270 inst.instruction |= (Rt << 12);
8278 if (do_vfp_nsyn_mrs () == SUCCESS)
8281 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8282 inst.instruction |= inst.operands[0].reg << 12;
8284 if (inst.operands[1].isreg)
8286 br = inst.operands[1].reg;
8287 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8288 as_bad (_("bad register for mrs"));
8292 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8293 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8295 _("'APSR', 'CPSR' or 'SPSR' expected"));
8296 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8299 inst.instruction |= br;
8302 /* Two possible forms:
8303 "{C|S}PSR_<field>, Rm",
8304 "{C|S}PSR_f, #expression". */
8309 if (do_vfp_nsyn_msr () == SUCCESS)
8312 inst.instruction |= inst.operands[0].imm;
8313 if (inst.operands[1].isreg)
8314 inst.instruction |= inst.operands[1].reg;
8317 inst.instruction |= INST_IMMEDIATE;
8318 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8319 inst.reloc.pc_rel = 0;
8326 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8328 if (!inst.operands[2].present)
8329 inst.operands[2].reg = inst.operands[0].reg;
8330 inst.instruction |= inst.operands[0].reg << 16;
8331 inst.instruction |= inst.operands[1].reg;
8332 inst.instruction |= inst.operands[2].reg << 8;
8334 if (inst.operands[0].reg == inst.operands[1].reg
8335 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8336 as_tsktsk (_("Rd and Rm should be different in mul"));
8339 /* Long Multiply Parser
8340 UMULL RdLo, RdHi, Rm, Rs
8341 SMULL RdLo, RdHi, Rm, Rs
8342 UMLAL RdLo, RdHi, Rm, Rs
8343 SMLAL RdLo, RdHi, Rm, Rs. */
8348 inst.instruction |= inst.operands[0].reg << 12;
8349 inst.instruction |= inst.operands[1].reg << 16;
8350 inst.instruction |= inst.operands[2].reg;
8351 inst.instruction |= inst.operands[3].reg << 8;
8353 /* rdhi and rdlo must be different. */
8354 if (inst.operands[0].reg == inst.operands[1].reg)
8355 as_tsktsk (_("rdhi and rdlo must be different"));
8357 /* rdhi, rdlo and rm must all be different before armv6. */
8358 if ((inst.operands[0].reg == inst.operands[2].reg
8359 || inst.operands[1].reg == inst.operands[2].reg)
8360 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8361 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8367 if (inst.operands[0].present
8368 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8370 /* Architectural NOP hints are CPSR sets with no bits selected. */
8371 inst.instruction &= 0xf0000000;
8372 inst.instruction |= 0x0320f000;
8373 if (inst.operands[0].present)
8374 inst.instruction |= inst.operands[0].imm;
8378 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8379 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8380 Condition defaults to COND_ALWAYS.
8381 Error if Rd, Rn or Rm are R15. */
8386 inst.instruction |= inst.operands[0].reg << 12;
8387 inst.instruction |= inst.operands[1].reg << 16;
8388 inst.instruction |= inst.operands[2].reg;
8389 if (inst.operands[3].present)
8390 encode_arm_shift (3);
8393 /* ARM V6 PKHTB (Argument Parse). */
8398 if (!inst.operands[3].present)
8400 /* If the shift specifier is omitted, turn the instruction
8401 into pkhbt rd, rm, rn. */
8402 inst.instruction &= 0xfff00010;
8403 inst.instruction |= inst.operands[0].reg << 12;
8404 inst.instruction |= inst.operands[1].reg;
8405 inst.instruction |= inst.operands[2].reg << 16;
8409 inst.instruction |= inst.operands[0].reg << 12;
8410 inst.instruction |= inst.operands[1].reg << 16;
8411 inst.instruction |= inst.operands[2].reg;
8412 encode_arm_shift (3);
8416 /* ARMv5TE: Preload-Cache
8417 MP Extensions: Preload for write
8421 Syntactically, like LDR with B=1, W=0, L=1. */
8426 constraint (!inst.operands[0].isreg,
8427 _("'[' expected after PLD mnemonic"));
8428 constraint (inst.operands[0].postind,
8429 _("post-indexed expression used in preload instruction"));
8430 constraint (inst.operands[0].writeback,
8431 _("writeback used in preload instruction"));
8432 constraint (!inst.operands[0].preind,
8433 _("unindexed addressing used in preload instruction"));
8434 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8437 /* ARMv7: PLI <addr_mode> */
8441 constraint (!inst.operands[0].isreg,
8442 _("'[' expected after PLI mnemonic"));
8443 constraint (inst.operands[0].postind,
8444 _("post-indexed expression used in preload instruction"));
8445 constraint (inst.operands[0].writeback,
8446 _("writeback used in preload instruction"));
8447 constraint (!inst.operands[0].preind,
8448 _("unindexed addressing used in preload instruction"));
8449 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8450 inst.instruction &= ~PRE_INDEX;
8456 inst.operands[1] = inst.operands[0];
8457 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8458 inst.operands[0].isreg = 1;
8459 inst.operands[0].writeback = 1;
8460 inst.operands[0].reg = REG_SP;
8461 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8464 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8465 word at the specified address and the following word
8467 Unconditionally executed.
8468 Error if Rn is R15. */
8473 inst.instruction |= inst.operands[0].reg << 16;
8474 if (inst.operands[0].writeback)
8475 inst.instruction |= WRITE_BACK;
8478 /* ARM V6 ssat (argument parse). */
8483 inst.instruction |= inst.operands[0].reg << 12;
8484 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8485 inst.instruction |= inst.operands[2].reg;
8487 if (inst.operands[3].present)
8488 encode_arm_shift (3);
8491 /* ARM V6 usat (argument parse). */
8496 inst.instruction |= inst.operands[0].reg << 12;
8497 inst.instruction |= inst.operands[1].imm << 16;
8498 inst.instruction |= inst.operands[2].reg;
8500 if (inst.operands[3].present)
8501 encode_arm_shift (3);
8504 /* ARM V6 ssat16 (argument parse). */
8509 inst.instruction |= inst.operands[0].reg << 12;
8510 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8511 inst.instruction |= inst.operands[2].reg;
8517 inst.instruction |= inst.operands[0].reg << 12;
8518 inst.instruction |= inst.operands[1].imm << 16;
8519 inst.instruction |= inst.operands[2].reg;
8522 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8523 preserving the other bits.
8525 setend <endian_specifier>, where <endian_specifier> is either
8531 if (inst.operands[0].imm)
8532 inst.instruction |= 0x200;
8538 unsigned int Rm = (inst.operands[1].present
8539 ? inst.operands[1].reg
8540 : inst.operands[0].reg);
8542 inst.instruction |= inst.operands[0].reg << 12;
8543 inst.instruction |= Rm;
8544 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8546 inst.instruction |= inst.operands[2].reg << 8;
8547 inst.instruction |= SHIFT_BY_REG;
8548 /* PR 12854: Error on extraneous shifts. */
8549 constraint (inst.operands[2].shifted,
8550 _("extraneous shift as part of operand to shift insn"));
8553 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8559 inst.reloc.type = BFD_RELOC_ARM_SMC;
8560 inst.reloc.pc_rel = 0;
8566 inst.reloc.type = BFD_RELOC_ARM_HVC;
8567 inst.reloc.pc_rel = 0;
8573 inst.reloc.type = BFD_RELOC_ARM_SWI;
8574 inst.reloc.pc_rel = 0;
8577 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8578 SMLAxy{cond} Rd,Rm,Rs,Rn
8579 SMLAWy{cond} Rd,Rm,Rs,Rn
8580 Error if any register is R15. */
8585 inst.instruction |= inst.operands[0].reg << 16;
8586 inst.instruction |= inst.operands[1].reg;
8587 inst.instruction |= inst.operands[2].reg << 8;
8588 inst.instruction |= inst.operands[3].reg << 12;
8591 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8592 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8593 Error if any register is R15.
8594 Warning if Rdlo == Rdhi. */
8599 inst.instruction |= inst.operands[0].reg << 12;
8600 inst.instruction |= inst.operands[1].reg << 16;
8601 inst.instruction |= inst.operands[2].reg;
8602 inst.instruction |= inst.operands[3].reg << 8;
8604 if (inst.operands[0].reg == inst.operands[1].reg)
8605 as_tsktsk (_("rdhi and rdlo must be different"));
8608 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8609 SMULxy{cond} Rd,Rm,Rs
8610 Error if any register is R15. */
8615 inst.instruction |= inst.operands[0].reg << 16;
8616 inst.instruction |= inst.operands[1].reg;
8617 inst.instruction |= inst.operands[2].reg << 8;
8620 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8621 the same for both ARM and Thumb-2. */
8628 if (inst.operands[0].present)
8630 reg = inst.operands[0].reg;
8631 constraint (reg != REG_SP, _("SRS base register must be r13"));
8636 inst.instruction |= reg << 16;
8637 inst.instruction |= inst.operands[1].imm;
8638 if (inst.operands[0].writeback || inst.operands[1].writeback)
8639 inst.instruction |= WRITE_BACK;
8642 /* ARM V6 strex (argument parse). */
8647 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8648 || inst.operands[2].postind || inst.operands[2].writeback
8649 || inst.operands[2].immisreg || inst.operands[2].shifted
8650 || inst.operands[2].negative
8651 /* See comment in do_ldrex(). */
8652 || (inst.operands[2].reg == REG_PC),
8655 constraint (inst.operands[0].reg == inst.operands[1].reg
8656 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8658 constraint (inst.reloc.exp.X_op != O_constant
8659 || inst.reloc.exp.X_add_number != 0,
8660 _("offset must be zero in ARM encoding"));
8662 inst.instruction |= inst.operands[0].reg << 12;
8663 inst.instruction |= inst.operands[1].reg;
8664 inst.instruction |= inst.operands[2].reg << 16;
8665 inst.reloc.type = BFD_RELOC_UNUSED;
8671 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8672 || inst.operands[2].postind || inst.operands[2].writeback
8673 || inst.operands[2].immisreg || inst.operands[2].shifted
8674 || inst.operands[2].negative,
8677 constraint (inst.operands[0].reg == inst.operands[1].reg
8678 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8686 constraint (inst.operands[1].reg % 2 != 0,
8687 _("even register required"));
8688 constraint (inst.operands[2].present
8689 && inst.operands[2].reg != inst.operands[1].reg + 1,
8690 _("can only store two consecutive registers"));
8691 /* If op 2 were present and equal to PC, this function wouldn't
8692 have been called in the first place. */
8693 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8695 constraint (inst.operands[0].reg == inst.operands[1].reg
8696 || inst.operands[0].reg == inst.operands[1].reg + 1
8697 || inst.operands[0].reg == inst.operands[3].reg,
8700 inst.instruction |= inst.operands[0].reg << 12;
8701 inst.instruction |= inst.operands[1].reg;
8702 inst.instruction |= inst.operands[3].reg << 16;
8705 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8706 extends it to 32-bits, and adds the result to a value in another
8707 register. You can specify a rotation by 0, 8, 16, or 24 bits
8708 before extracting the 16-bit value.
8709 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8710 Condition defaults to COND_ALWAYS.
8711 Error if any register uses R15. */
8716 inst.instruction |= inst.operands[0].reg << 12;
8717 inst.instruction |= inst.operands[1].reg << 16;
8718 inst.instruction |= inst.operands[2].reg;
8719 inst.instruction |= inst.operands[3].imm << 10;
8724 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8725 Condition defaults to COND_ALWAYS.
8726 Error if any register uses R15. */
8731 inst.instruction |= inst.operands[0].reg << 12;
8732 inst.instruction |= inst.operands[1].reg;
8733 inst.instruction |= inst.operands[2].imm << 10;
8736 /* VFP instructions. In a logical order: SP variant first, monad
8737 before dyad, arithmetic then move then load/store. */
8740 do_vfp_sp_monadic (void)
8742 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8743 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8747 do_vfp_sp_dyadic (void)
8749 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8750 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8751 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8755 do_vfp_sp_compare_z (void)
8757 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8761 do_vfp_dp_sp_cvt (void)
8763 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8764 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8768 do_vfp_sp_dp_cvt (void)
8770 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8771 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8775 do_vfp_reg_from_sp (void)
8777 inst.instruction |= inst.operands[0].reg << 12;
8778 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8782 do_vfp_reg2_from_sp2 (void)
8784 constraint (inst.operands[2].imm != 2,
8785 _("only two consecutive VFP SP registers allowed here"));
8786 inst.instruction |= inst.operands[0].reg << 12;
8787 inst.instruction |= inst.operands[1].reg << 16;
8788 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8792 do_vfp_sp_from_reg (void)
8794 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8795 inst.instruction |= inst.operands[1].reg << 12;
8799 do_vfp_sp2_from_reg2 (void)
8801 constraint (inst.operands[0].imm != 2,
8802 _("only two consecutive VFP SP registers allowed here"));
8803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8804 inst.instruction |= inst.operands[1].reg << 12;
8805 inst.instruction |= inst.operands[2].reg << 16;
8809 do_vfp_sp_ldst (void)
8811 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8812 encode_arm_cp_address (1, FALSE, TRUE, 0);
8816 do_vfp_dp_ldst (void)
8818 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8819 encode_arm_cp_address (1, FALSE, TRUE, 0);
8824 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8826 if (inst.operands[0].writeback)
8827 inst.instruction |= WRITE_BACK;
8829 constraint (ldstm_type != VFP_LDSTMIA,
8830 _("this addressing mode requires base-register writeback"));
8831 inst.instruction |= inst.operands[0].reg << 16;
8832 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8833 inst.instruction |= inst.operands[1].imm;
8837 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8841 if (inst.operands[0].writeback)
8842 inst.instruction |= WRITE_BACK;
8844 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8845 _("this addressing mode requires base-register writeback"));
8847 inst.instruction |= inst.operands[0].reg << 16;
8848 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8850 count = inst.operands[1].imm << 1;
8851 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8854 inst.instruction |= count;
8858 do_vfp_sp_ldstmia (void)
8860 vfp_sp_ldstm (VFP_LDSTMIA);
8864 do_vfp_sp_ldstmdb (void)
8866 vfp_sp_ldstm (VFP_LDSTMDB);
8870 do_vfp_dp_ldstmia (void)
8872 vfp_dp_ldstm (VFP_LDSTMIA);
8876 do_vfp_dp_ldstmdb (void)
8878 vfp_dp_ldstm (VFP_LDSTMDB);
8882 do_vfp_xp_ldstmia (void)
8884 vfp_dp_ldstm (VFP_LDSTMIAX);
8888 do_vfp_xp_ldstmdb (void)
8890 vfp_dp_ldstm (VFP_LDSTMDBX);
8894 do_vfp_dp_rd_rm (void)
8896 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8897 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8901 do_vfp_dp_rn_rd (void)
8903 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8904 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8908 do_vfp_dp_rd_rn (void)
8910 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8911 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8915 do_vfp_dp_rd_rn_rm (void)
8917 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8918 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8919 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8925 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8929 do_vfp_dp_rm_rd_rn (void)
8931 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8932 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8933 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8936 /* VFPv3 instructions. */
8938 do_vfp_sp_const (void)
8940 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8941 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8942 inst.instruction |= (inst.operands[1].imm & 0x0f);
8946 do_vfp_dp_const (void)
8948 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8949 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8950 inst.instruction |= (inst.operands[1].imm & 0x0f);
8954 vfp_conv (int srcsize)
8956 int immbits = srcsize - inst.operands[1].imm;
8958 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8960 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8961 i.e. immbits must be in range 0 - 16. */
8962 inst.error = _("immediate value out of range, expected range [0, 16]");
8965 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8967 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8968 i.e. immbits must be in range 0 - 31. */
8969 inst.error = _("immediate value out of range, expected range [1, 32]");
8973 inst.instruction |= (immbits & 1) << 5;
8974 inst.instruction |= (immbits >> 1);
8978 do_vfp_sp_conv_16 (void)
8980 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8985 do_vfp_dp_conv_16 (void)
8987 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8992 do_vfp_sp_conv_32 (void)
8994 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8999 do_vfp_dp_conv_32 (void)
9001 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9005 /* FPA instructions. Also in a logical order. */
9010 inst.instruction |= inst.operands[0].reg << 16;
9011 inst.instruction |= inst.operands[1].reg;
9015 do_fpa_ldmstm (void)
9017 inst.instruction |= inst.operands[0].reg << 12;
9018 switch (inst.operands[1].imm)
9020 case 1: inst.instruction |= CP_T_X; break;
9021 case 2: inst.instruction |= CP_T_Y; break;
9022 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9027 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9029 /* The instruction specified "ea" or "fd", so we can only accept
9030 [Rn]{!}. The instruction does not really support stacking or
9031 unstacking, so we have to emulate these by setting appropriate
9032 bits and offsets. */
9033 constraint (inst.reloc.exp.X_op != O_constant
9034 || inst.reloc.exp.X_add_number != 0,
9035 _("this instruction does not support indexing"));
9037 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9038 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9040 if (!(inst.instruction & INDEX_UP))
9041 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9043 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9045 inst.operands[2].preind = 0;
9046 inst.operands[2].postind = 1;
9050 encode_arm_cp_address (2, TRUE, TRUE, 0);
9053 /* iWMMXt instructions: strictly in alphabetical order. */
9056 do_iwmmxt_tandorc (void)
9058 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9062 do_iwmmxt_textrc (void)
9064 inst.instruction |= inst.operands[0].reg << 12;
9065 inst.instruction |= inst.operands[1].imm;
9069 do_iwmmxt_textrm (void)
9071 inst.instruction |= inst.operands[0].reg << 12;
9072 inst.instruction |= inst.operands[1].reg << 16;
9073 inst.instruction |= inst.operands[2].imm;
9077 do_iwmmxt_tinsr (void)
9079 inst.instruction |= inst.operands[0].reg << 16;
9080 inst.instruction |= inst.operands[1].reg << 12;
9081 inst.instruction |= inst.operands[2].imm;
9085 do_iwmmxt_tmia (void)
9087 inst.instruction |= inst.operands[0].reg << 5;
9088 inst.instruction |= inst.operands[1].reg;
9089 inst.instruction |= inst.operands[2].reg << 12;
9093 do_iwmmxt_waligni (void)
9095 inst.instruction |= inst.operands[0].reg << 12;
9096 inst.instruction |= inst.operands[1].reg << 16;
9097 inst.instruction |= inst.operands[2].reg;
9098 inst.instruction |= inst.operands[3].imm << 20;
9102 do_iwmmxt_wmerge (void)
9104 inst.instruction |= inst.operands[0].reg << 12;
9105 inst.instruction |= inst.operands[1].reg << 16;
9106 inst.instruction |= inst.operands[2].reg;
9107 inst.instruction |= inst.operands[3].imm << 21;
9111 do_iwmmxt_wmov (void)
9113 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9114 inst.instruction |= inst.operands[0].reg << 12;
9115 inst.instruction |= inst.operands[1].reg << 16;
9116 inst.instruction |= inst.operands[1].reg;
9120 do_iwmmxt_wldstbh (void)
9123 inst.instruction |= inst.operands[0].reg << 12;
9125 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9127 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9128 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9132 do_iwmmxt_wldstw (void)
9134 /* RIWR_RIWC clears .isreg for a control register. */
9135 if (!inst.operands[0].isreg)
9137 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9138 inst.instruction |= 0xf0000000;
9141 inst.instruction |= inst.operands[0].reg << 12;
9142 encode_arm_cp_address (1, TRUE, TRUE, 0);
9146 do_iwmmxt_wldstd (void)
9148 inst.instruction |= inst.operands[0].reg << 12;
9149 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9150 && inst.operands[1].immisreg)
9152 inst.instruction &= ~0x1a000ff;
9153 inst.instruction |= (0xf << 28);
9154 if (inst.operands[1].preind)
9155 inst.instruction |= PRE_INDEX;
9156 if (!inst.operands[1].negative)
9157 inst.instruction |= INDEX_UP;
9158 if (inst.operands[1].writeback)
9159 inst.instruction |= WRITE_BACK;
9160 inst.instruction |= inst.operands[1].reg << 16;
9161 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9162 inst.instruction |= inst.operands[1].imm;
9165 encode_arm_cp_address (1, TRUE, FALSE, 0);
9169 do_iwmmxt_wshufh (void)
9171 inst.instruction |= inst.operands[0].reg << 12;
9172 inst.instruction |= inst.operands[1].reg << 16;
9173 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9174 inst.instruction |= (inst.operands[2].imm & 0x0f);
9178 do_iwmmxt_wzero (void)
9180 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9181 inst.instruction |= inst.operands[0].reg;
9182 inst.instruction |= inst.operands[0].reg << 12;
9183 inst.instruction |= inst.operands[0].reg << 16;
9187 do_iwmmxt_wrwrwr_or_imm5 (void)
9189 if (inst.operands[2].isreg)
9192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9193 _("immediate operand requires iWMMXt2"));
9195 if (inst.operands[2].imm == 0)
9197 switch ((inst.instruction >> 20) & 0xf)
9203 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9204 inst.operands[2].imm = 16;
9205 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9211 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9212 inst.operands[2].imm = 32;
9213 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9220 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9222 wrn = (inst.instruction >> 16) & 0xf;
9223 inst.instruction &= 0xff0fff0f;
9224 inst.instruction |= wrn;
9225 /* Bail out here; the instruction is now assembled. */
9230 /* Map 32 -> 0, etc. */
9231 inst.operands[2].imm &= 0x1f;
9232 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9236 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9237 operations first, then control, shift, and load/store. */
9239 /* Insns like "foo X,Y,Z". */
9242 do_mav_triple (void)
9244 inst.instruction |= inst.operands[0].reg << 16;
9245 inst.instruction |= inst.operands[1].reg;
9246 inst.instruction |= inst.operands[2].reg << 12;
9249 /* Insns like "foo W,X,Y,Z".
9250 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9255 inst.instruction |= inst.operands[0].reg << 5;
9256 inst.instruction |= inst.operands[1].reg << 12;
9257 inst.instruction |= inst.operands[2].reg << 16;
9258 inst.instruction |= inst.operands[3].reg;
9261 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9265 inst.instruction |= inst.operands[1].reg << 12;
9268 /* Maverick shift immediate instructions.
9269 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9270 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9275 int imm = inst.operands[2].imm;
9277 inst.instruction |= inst.operands[0].reg << 12;
9278 inst.instruction |= inst.operands[1].reg << 16;
9280 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9281 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9282 Bit 4 should be 0. */
9283 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9285 inst.instruction |= imm;
9288 /* XScale instructions. Also sorted arithmetic before move. */
9290 /* Xscale multiply-accumulate (argument parse)
9293 MIAxycc acc0,Rm,Rs. */
9298 inst.instruction |= inst.operands[1].reg;
9299 inst.instruction |= inst.operands[2].reg << 12;
9302 /* Xscale move-accumulator-register (argument parse)
9304 MARcc acc0,RdLo,RdHi. */
9309 inst.instruction |= inst.operands[1].reg << 12;
9310 inst.instruction |= inst.operands[2].reg << 16;
9313 /* Xscale move-register-accumulator (argument parse)
9315 MRAcc RdLo,RdHi,acc0. */
9320 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9321 inst.instruction |= inst.operands[0].reg << 12;
9322 inst.instruction |= inst.operands[1].reg << 16;
9325 /* Encoding functions relevant only to Thumb. */
9327 /* inst.operands[i] is a shifted-register operand; encode
9328 it into inst.instruction in the format used by Thumb32. */
9331 encode_thumb32_shifted_operand (int i)
9333 unsigned int value = inst.reloc.exp.X_add_number;
9334 unsigned int shift = inst.operands[i].shift_kind;
9336 constraint (inst.operands[i].immisreg,
9337 _("shift by register not allowed in thumb mode"));
9338 inst.instruction |= inst.operands[i].reg;
9339 if (shift == SHIFT_RRX)
9340 inst.instruction |= SHIFT_ROR << 4;
9343 constraint (inst.reloc.exp.X_op != O_constant,
9344 _("expression too complex"));
9346 constraint (value > 32
9347 || (value == 32 && (shift == SHIFT_LSL
9348 || shift == SHIFT_ROR)),
9349 _("shift expression is too large"));
9353 else if (value == 32)
9356 inst.instruction |= shift << 4;
9357 inst.instruction |= (value & 0x1c) << 10;
9358 inst.instruction |= (value & 0x03) << 6;
9363 /* inst.operands[i] was set up by parse_address. Encode it into a
9364 Thumb32 format load or store instruction. Reject forms that cannot
9365 be used with such instructions. If is_t is true, reject forms that
9366 cannot be used with a T instruction; if is_d is true, reject forms
9367 that cannot be used with a D instruction. If it is a store insn,
9371 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9373 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9375 constraint (!inst.operands[i].isreg,
9376 _("Instruction does not support =N addresses"));
9378 inst.instruction |= inst.operands[i].reg << 16;
9379 if (inst.operands[i].immisreg)
9381 constraint (is_pc, BAD_PC_ADDRESSING);
9382 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9383 constraint (inst.operands[i].negative,
9384 _("Thumb does not support negative register indexing"));
9385 constraint (inst.operands[i].postind,
9386 _("Thumb does not support register post-indexing"));
9387 constraint (inst.operands[i].writeback,
9388 _("Thumb does not support register indexing with writeback"));
9389 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9390 _("Thumb supports only LSL in shifted register indexing"));
9392 inst.instruction |= inst.operands[i].imm;
9393 if (inst.operands[i].shifted)
9395 constraint (inst.reloc.exp.X_op != O_constant,
9396 _("expression too complex"));
9397 constraint (inst.reloc.exp.X_add_number < 0
9398 || inst.reloc.exp.X_add_number > 3,
9399 _("shift out of range"));
9400 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9402 inst.reloc.type = BFD_RELOC_UNUSED;
9404 else if (inst.operands[i].preind)
9406 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9407 constraint (is_t && inst.operands[i].writeback,
9408 _("cannot use writeback with this instruction"));
9409 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9410 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9414 inst.instruction |= 0x01000000;
9415 if (inst.operands[i].writeback)
9416 inst.instruction |= 0x00200000;
9420 inst.instruction |= 0x00000c00;
9421 if (inst.operands[i].writeback)
9422 inst.instruction |= 0x00000100;
9424 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9426 else if (inst.operands[i].postind)
9428 gas_assert (inst.operands[i].writeback);
9429 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9430 constraint (is_t, _("cannot use post-indexing with this instruction"));
9433 inst.instruction |= 0x00200000;
9435 inst.instruction |= 0x00000900;
9436 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9438 else /* unindexed - only for coprocessor */
9439 inst.error = _("instruction does not accept unindexed addressing");
9442 /* Table of Thumb instructions which exist in both 16- and 32-bit
9443 encodings (the latter only in post-V6T2 cores). The index is the
9444 value used in the insns table below. When there is more than one
9445 possible 16-bit encoding for the instruction, this table always
9447 Also contains several pseudo-instructions used during relaxation. */
9448 #define T16_32_TAB \
9449 X(_adc, 4140, eb400000), \
9450 X(_adcs, 4140, eb500000), \
9451 X(_add, 1c00, eb000000), \
9452 X(_adds, 1c00, eb100000), \
9453 X(_addi, 0000, f1000000), \
9454 X(_addis, 0000, f1100000), \
9455 X(_add_pc,000f, f20f0000), \
9456 X(_add_sp,000d, f10d0000), \
9457 X(_adr, 000f, f20f0000), \
9458 X(_and, 4000, ea000000), \
9459 X(_ands, 4000, ea100000), \
9460 X(_asr, 1000, fa40f000), \
9461 X(_asrs, 1000, fa50f000), \
9462 X(_b, e000, f000b000), \
9463 X(_bcond, d000, f0008000), \
9464 X(_bic, 4380, ea200000), \
9465 X(_bics, 4380, ea300000), \
9466 X(_cmn, 42c0, eb100f00), \
9467 X(_cmp, 2800, ebb00f00), \
9468 X(_cpsie, b660, f3af8400), \
9469 X(_cpsid, b670, f3af8600), \
9470 X(_cpy, 4600, ea4f0000), \
9471 X(_dec_sp,80dd, f1ad0d00), \
9472 X(_eor, 4040, ea800000), \
9473 X(_eors, 4040, ea900000), \
9474 X(_inc_sp,00dd, f10d0d00), \
9475 X(_ldmia, c800, e8900000), \
9476 X(_ldr, 6800, f8500000), \
9477 X(_ldrb, 7800, f8100000), \
9478 X(_ldrh, 8800, f8300000), \
9479 X(_ldrsb, 5600, f9100000), \
9480 X(_ldrsh, 5e00, f9300000), \
9481 X(_ldr_pc,4800, f85f0000), \
9482 X(_ldr_pc2,4800, f85f0000), \
9483 X(_ldr_sp,9800, f85d0000), \
9484 X(_lsl, 0000, fa00f000), \
9485 X(_lsls, 0000, fa10f000), \
9486 X(_lsr, 0800, fa20f000), \
9487 X(_lsrs, 0800, fa30f000), \
9488 X(_mov, 2000, ea4f0000), \
9489 X(_movs, 2000, ea5f0000), \
9490 X(_mul, 4340, fb00f000), \
9491 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9492 X(_mvn, 43c0, ea6f0000), \
9493 X(_mvns, 43c0, ea7f0000), \
9494 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9495 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9496 X(_orr, 4300, ea400000), \
9497 X(_orrs, 4300, ea500000), \
9498 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9499 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9500 X(_rev, ba00, fa90f080), \
9501 X(_rev16, ba40, fa90f090), \
9502 X(_revsh, bac0, fa90f0b0), \
9503 X(_ror, 41c0, fa60f000), \
9504 X(_rors, 41c0, fa70f000), \
9505 X(_sbc, 4180, eb600000), \
9506 X(_sbcs, 4180, eb700000), \
9507 X(_stmia, c000, e8800000), \
9508 X(_str, 6000, f8400000), \
9509 X(_strb, 7000, f8000000), \
9510 X(_strh, 8000, f8200000), \
9511 X(_str_sp,9000, f84d0000), \
9512 X(_sub, 1e00, eba00000), \
9513 X(_subs, 1e00, ebb00000), \
9514 X(_subi, 8000, f1a00000), \
9515 X(_subis, 8000, f1b00000), \
9516 X(_sxtb, b240, fa4ff080), \
9517 X(_sxth, b200, fa0ff080), \
9518 X(_tst, 4200, ea100f00), \
9519 X(_uxtb, b2c0, fa5ff080), \
9520 X(_uxth, b280, fa1ff080), \
9521 X(_nop, bf00, f3af8000), \
9522 X(_yield, bf10, f3af8001), \
9523 X(_wfe, bf20, f3af8002), \
9524 X(_wfi, bf30, f3af8003), \
9525 X(_sev, bf40, f3af8004),
9527 /* To catch errors in encoding functions, the codes are all offset by
9528 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9529 as 16-bit instructions. */
9530 #define X(a,b,c) T_MNEM##a
9531 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9534 #define X(a,b,c) 0x##b
9535 static const unsigned short thumb_op16[] = { T16_32_TAB };
9536 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9539 #define X(a,b,c) 0x##c
9540 static const unsigned int thumb_op32[] = { T16_32_TAB };
9541 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9542 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9546 /* Thumb instruction encoders, in alphabetical order. */
9551 do_t_add_sub_w (void)
9555 Rd = inst.operands[0].reg;
9556 Rn = inst.operands[1].reg;
9558 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9559 is the SP-{plus,minus}-immediate form of the instruction. */
9561 constraint (Rd == REG_PC, BAD_PC);
9563 reject_bad_reg (Rd);
9565 inst.instruction |= (Rn << 16) | (Rd << 8);
9566 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9569 /* Parse an add or subtract instruction. We get here with inst.instruction
9570 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9577 Rd = inst.operands[0].reg;
9578 Rs = (inst.operands[1].present
9579 ? inst.operands[1].reg /* Rd, Rs, foo */
9580 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9583 set_it_insn_type_last ();
9591 flags = (inst.instruction == T_MNEM_adds
9592 || inst.instruction == T_MNEM_subs);
9594 narrow = !in_it_block ();
9596 narrow = in_it_block ();
9597 if (!inst.operands[2].isreg)
9601 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9603 add = (inst.instruction == T_MNEM_add
9604 || inst.instruction == T_MNEM_adds);
9606 if (inst.size_req != 4)
9608 /* Attempt to use a narrow opcode, with relaxation if
9610 if (Rd == REG_SP && Rs == REG_SP && !flags)
9611 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9612 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9613 opcode = T_MNEM_add_sp;
9614 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9615 opcode = T_MNEM_add_pc;
9616 else if (Rd <= 7 && Rs <= 7 && narrow)
9619 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9621 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9625 inst.instruction = THUMB_OP16(opcode);
9626 inst.instruction |= (Rd << 4) | Rs;
9627 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9628 if (inst.size_req != 2)
9629 inst.relax = opcode;
9632 constraint (inst.size_req == 2, BAD_HIREG);
9634 if (inst.size_req == 4
9635 || (inst.size_req != 2 && !opcode))
9639 constraint (add, BAD_PC);
9640 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9641 _("only SUBS PC, LR, #const allowed"));
9642 constraint (inst.reloc.exp.X_op != O_constant,
9643 _("expression too complex"));
9644 constraint (inst.reloc.exp.X_add_number < 0
9645 || inst.reloc.exp.X_add_number > 0xff,
9646 _("immediate value out of range"));
9647 inst.instruction = T2_SUBS_PC_LR
9648 | inst.reloc.exp.X_add_number;
9649 inst.reloc.type = BFD_RELOC_UNUSED;
9652 else if (Rs == REG_PC)
9654 /* Always use addw/subw. */
9655 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9656 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9660 inst.instruction = THUMB_OP32 (inst.instruction);
9661 inst.instruction = (inst.instruction & 0xe1ffffff)
9664 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9666 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9668 inst.instruction |= Rd << 8;
9669 inst.instruction |= Rs << 16;
9674 unsigned int value = inst.reloc.exp.X_add_number;
9675 unsigned int shift = inst.operands[2].shift_kind;
9677 Rn = inst.operands[2].reg;
9678 /* See if we can do this with a 16-bit instruction. */
9679 if (!inst.operands[2].shifted && inst.size_req != 4)
9681 if (Rd > 7 || Rs > 7 || Rn > 7)
9686 inst.instruction = ((inst.instruction == T_MNEM_adds
9687 || inst.instruction == T_MNEM_add)
9690 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9694 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9696 /* Thumb-1 cores (except v6-M) require at least one high
9697 register in a narrow non flag setting add. */
9698 if (Rd > 7 || Rn > 7
9699 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9700 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9707 inst.instruction = T_OPCODE_ADD_HI;
9708 inst.instruction |= (Rd & 8) << 4;
9709 inst.instruction |= (Rd & 7);
9710 inst.instruction |= Rn << 3;
9716 constraint (Rd == REG_PC, BAD_PC);
9717 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9718 constraint (Rs == REG_PC, BAD_PC);
9719 reject_bad_reg (Rn);
9721 /* If we get here, it can't be done in 16 bits. */
9722 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9723 _("shift must be constant"));
9724 inst.instruction = THUMB_OP32 (inst.instruction);
9725 inst.instruction |= Rd << 8;
9726 inst.instruction |= Rs << 16;
9727 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9728 _("shift value over 3 not allowed in thumb mode"));
9729 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9730 _("only LSL shift allowed in thumb mode"));
9731 encode_thumb32_shifted_operand (2);
9736 constraint (inst.instruction == T_MNEM_adds
9737 || inst.instruction == T_MNEM_subs,
9740 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9742 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9743 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9746 inst.instruction = (inst.instruction == T_MNEM_add
9748 inst.instruction |= (Rd << 4) | Rs;
9749 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9753 Rn = inst.operands[2].reg;
9754 constraint (inst.operands[2].shifted, _("unshifted register required"));
9756 /* We now have Rd, Rs, and Rn set to registers. */
9757 if (Rd > 7 || Rs > 7 || Rn > 7)
9759 /* Can't do this for SUB. */
9760 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9761 inst.instruction = T_OPCODE_ADD_HI;
9762 inst.instruction |= (Rd & 8) << 4;
9763 inst.instruction |= (Rd & 7);
9765 inst.instruction |= Rn << 3;
9767 inst.instruction |= Rs << 3;
9769 constraint (1, _("dest must overlap one source register"));
9773 inst.instruction = (inst.instruction == T_MNEM_add
9774 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9775 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9785 Rd = inst.operands[0].reg;
9786 reject_bad_reg (Rd);
9788 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9790 /* Defer to section relaxation. */
9791 inst.relax = inst.instruction;
9792 inst.instruction = THUMB_OP16 (inst.instruction);
9793 inst.instruction |= Rd << 4;
9795 else if (unified_syntax && inst.size_req != 2)
9797 /* Generate a 32-bit opcode. */
9798 inst.instruction = THUMB_OP32 (inst.instruction);
9799 inst.instruction |= Rd << 8;
9800 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9801 inst.reloc.pc_rel = 1;
9805 /* Generate a 16-bit opcode. */
9806 inst.instruction = THUMB_OP16 (inst.instruction);
9807 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9808 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9809 inst.reloc.pc_rel = 1;
9811 inst.instruction |= Rd << 4;
9815 /* Arithmetic instructions for which there is just one 16-bit
9816 instruction encoding, and it allows only two low registers.
9817 For maximal compatibility with ARM syntax, we allow three register
9818 operands even when Thumb-32 instructions are not available, as long
9819 as the first two are identical. For instance, both "sbc r0,r1" and
9820 "sbc r0,r0,r1" are allowed. */
9826 Rd = inst.operands[0].reg;
9827 Rs = (inst.operands[1].present
9828 ? inst.operands[1].reg /* Rd, Rs, foo */
9829 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9830 Rn = inst.operands[2].reg;
9832 reject_bad_reg (Rd);
9833 reject_bad_reg (Rs);
9834 if (inst.operands[2].isreg)
9835 reject_bad_reg (Rn);
9839 if (!inst.operands[2].isreg)
9841 /* For an immediate, we always generate a 32-bit opcode;
9842 section relaxation will shrink it later if possible. */
9843 inst.instruction = THUMB_OP32 (inst.instruction);
9844 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9845 inst.instruction |= Rd << 8;
9846 inst.instruction |= Rs << 16;
9847 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9853 /* See if we can do this with a 16-bit instruction. */
9854 if (THUMB_SETS_FLAGS (inst.instruction))
9855 narrow = !in_it_block ();
9857 narrow = in_it_block ();
9859 if (Rd > 7 || Rn > 7 || Rs > 7)
9861 if (inst.operands[2].shifted)
9863 if (inst.size_req == 4)
9869 inst.instruction = THUMB_OP16 (inst.instruction);
9870 inst.instruction |= Rd;
9871 inst.instruction |= Rn << 3;
9875 /* If we get here, it can't be done in 16 bits. */
9876 constraint (inst.operands[2].shifted
9877 && inst.operands[2].immisreg,
9878 _("shift must be constant"));
9879 inst.instruction = THUMB_OP32 (inst.instruction);
9880 inst.instruction |= Rd << 8;
9881 inst.instruction |= Rs << 16;
9882 encode_thumb32_shifted_operand (2);
9887 /* On its face this is a lie - the instruction does set the
9888 flags. However, the only supported mnemonic in this mode
9890 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9892 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9893 _("unshifted register required"));
9894 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9895 constraint (Rd != Rs,
9896 _("dest and source1 must be the same register"));
9898 inst.instruction = THUMB_OP16 (inst.instruction);
9899 inst.instruction |= Rd;
9900 inst.instruction |= Rn << 3;
9904 /* Similarly, but for instructions where the arithmetic operation is
9905 commutative, so we can allow either of them to be different from
9906 the destination operand in a 16-bit instruction. For instance, all
9907 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9914 Rd = inst.operands[0].reg;
9915 Rs = (inst.operands[1].present
9916 ? inst.operands[1].reg /* Rd, Rs, foo */
9917 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9918 Rn = inst.operands[2].reg;
9920 reject_bad_reg (Rd);
9921 reject_bad_reg (Rs);
9922 if (inst.operands[2].isreg)
9923 reject_bad_reg (Rn);
9927 if (!inst.operands[2].isreg)
9929 /* For an immediate, we always generate a 32-bit opcode;
9930 section relaxation will shrink it later if possible. */
9931 inst.instruction = THUMB_OP32 (inst.instruction);
9932 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9933 inst.instruction |= Rd << 8;
9934 inst.instruction |= Rs << 16;
9935 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9941 /* See if we can do this with a 16-bit instruction. */
9942 if (THUMB_SETS_FLAGS (inst.instruction))
9943 narrow = !in_it_block ();
9945 narrow = in_it_block ();
9947 if (Rd > 7 || Rn > 7 || Rs > 7)
9949 if (inst.operands[2].shifted)
9951 if (inst.size_req == 4)
9958 inst.instruction = THUMB_OP16 (inst.instruction);
9959 inst.instruction |= Rd;
9960 inst.instruction |= Rn << 3;
9965 inst.instruction = THUMB_OP16 (inst.instruction);
9966 inst.instruction |= Rd;
9967 inst.instruction |= Rs << 3;
9972 /* If we get here, it can't be done in 16 bits. */
9973 constraint (inst.operands[2].shifted
9974 && inst.operands[2].immisreg,
9975 _("shift must be constant"));
9976 inst.instruction = THUMB_OP32 (inst.instruction);
9977 inst.instruction |= Rd << 8;
9978 inst.instruction |= Rs << 16;
9979 encode_thumb32_shifted_operand (2);
9984 /* On its face this is a lie - the instruction does set the
9985 flags. However, the only supported mnemonic in this mode
9987 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9989 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9990 _("unshifted register required"));
9991 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9993 inst.instruction = THUMB_OP16 (inst.instruction);
9994 inst.instruction |= Rd;
9997 inst.instruction |= Rn << 3;
9999 inst.instruction |= Rs << 3;
10001 constraint (1, _("dest must overlap one source register"));
10006 do_t_barrier (void)
10008 if (inst.operands[0].present)
10010 constraint ((inst.instruction & 0xf0) != 0x40
10011 && inst.operands[0].imm > 0xf
10012 && inst.operands[0].imm < 0x0,
10013 _("bad barrier type"));
10014 inst.instruction |= inst.operands[0].imm;
10017 inst.instruction |= 0xf;
10024 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10025 constraint (msb > 32, _("bit-field extends past end of register"));
10026 /* The instruction encoding stores the LSB and MSB,
10027 not the LSB and width. */
10028 Rd = inst.operands[0].reg;
10029 reject_bad_reg (Rd);
10030 inst.instruction |= Rd << 8;
10031 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10032 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10033 inst.instruction |= msb - 1;
10042 Rd = inst.operands[0].reg;
10043 reject_bad_reg (Rd);
10045 /* #0 in second position is alternative syntax for bfc, which is
10046 the same instruction but with REG_PC in the Rm field. */
10047 if (!inst.operands[1].isreg)
10051 Rn = inst.operands[1].reg;
10052 reject_bad_reg (Rn);
10055 msb = inst.operands[2].imm + inst.operands[3].imm;
10056 constraint (msb > 32, _("bit-field extends past end of register"));
10057 /* The instruction encoding stores the LSB and MSB,
10058 not the LSB and width. */
10059 inst.instruction |= Rd << 8;
10060 inst.instruction |= Rn << 16;
10061 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10062 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10063 inst.instruction |= msb - 1;
10071 Rd = inst.operands[0].reg;
10072 Rn = inst.operands[1].reg;
10074 reject_bad_reg (Rd);
10075 reject_bad_reg (Rn);
10077 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10078 _("bit-field extends past end of register"));
10079 inst.instruction |= Rd << 8;
10080 inst.instruction |= Rn << 16;
10081 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10082 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10083 inst.instruction |= inst.operands[3].imm - 1;
10086 /* ARM V5 Thumb BLX (argument parse)
10087 BLX <target_addr> which is BLX(1)
10088 BLX <Rm> which is BLX(2)
10089 Unfortunately, there are two different opcodes for this mnemonic.
10090 So, the insns[].value is not used, and the code here zaps values
10091 into inst.instruction.
10093 ??? How to take advantage of the additional two bits of displacement
10094 available in Thumb32 mode? Need new relocation? */
10099 set_it_insn_type_last ();
10101 if (inst.operands[0].isreg)
10103 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10104 /* We have a register, so this is BLX(2). */
10105 inst.instruction |= inst.operands[0].reg << 3;
10109 /* No register. This must be BLX(1). */
10110 inst.instruction = 0xf000e800;
10111 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10123 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10125 if (in_it_block ())
10127 /* Conditional branches inside IT blocks are encoded as unconditional
10129 cond = COND_ALWAYS;
10134 if (cond != COND_ALWAYS)
10135 opcode = T_MNEM_bcond;
10137 opcode = inst.instruction;
10140 && (inst.size_req == 4
10141 || (inst.size_req != 2
10142 && (inst.operands[0].hasreloc
10143 || inst.reloc.exp.X_op == O_constant))))
10145 inst.instruction = THUMB_OP32(opcode);
10146 if (cond == COND_ALWAYS)
10147 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10150 gas_assert (cond != 0xF);
10151 inst.instruction |= cond << 22;
10152 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10157 inst.instruction = THUMB_OP16(opcode);
10158 if (cond == COND_ALWAYS)
10159 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10162 inst.instruction |= cond << 8;
10163 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10165 /* Allow section relaxation. */
10166 if (unified_syntax && inst.size_req != 2)
10167 inst.relax = opcode;
10169 inst.reloc.type = reloc;
10170 inst.reloc.pc_rel = 1;
10176 constraint (inst.cond != COND_ALWAYS,
10177 _("instruction is always unconditional"));
10178 if (inst.operands[0].present)
10180 constraint (inst.operands[0].imm > 255,
10181 _("immediate value out of range"));
10182 inst.instruction |= inst.operands[0].imm;
10183 set_it_insn_type (NEUTRAL_IT_INSN);
10188 do_t_branch23 (void)
10190 set_it_insn_type_last ();
10191 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10193 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10194 this file. We used to simply ignore the PLT reloc type here --
10195 the branch encoding is now needed to deal with TLSCALL relocs.
10196 So if we see a PLT reloc now, put it back to how it used to be to
10197 keep the preexisting behaviour. */
10198 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10199 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10201 #if defined(OBJ_COFF)
10202 /* If the destination of the branch is a defined symbol which does not have
10203 the THUMB_FUNC attribute, then we must be calling a function which has
10204 the (interfacearm) attribute. We look for the Thumb entry point to that
10205 function and change the branch to refer to that function instead. */
10206 if ( inst.reloc.exp.X_op == O_symbol
10207 && inst.reloc.exp.X_add_symbol != NULL
10208 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10209 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10210 inst.reloc.exp.X_add_symbol =
10211 find_real_start (inst.reloc.exp.X_add_symbol);
10218 set_it_insn_type_last ();
10219 inst.instruction |= inst.operands[0].reg << 3;
10220 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10221 should cause the alignment to be checked once it is known. This is
10222 because BX PC only works if the instruction is word aligned. */
10230 set_it_insn_type_last ();
10231 Rm = inst.operands[0].reg;
10232 reject_bad_reg (Rm);
10233 inst.instruction |= Rm << 16;
10242 Rd = inst.operands[0].reg;
10243 Rm = inst.operands[1].reg;
10245 reject_bad_reg (Rd);
10246 reject_bad_reg (Rm);
10248 inst.instruction |= Rd << 8;
10249 inst.instruction |= Rm << 16;
10250 inst.instruction |= Rm;
10256 set_it_insn_type (OUTSIDE_IT_INSN);
10257 inst.instruction |= inst.operands[0].imm;
10263 set_it_insn_type (OUTSIDE_IT_INSN);
10265 && (inst.operands[1].present || inst.size_req == 4)
10266 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10268 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10269 inst.instruction = 0xf3af8000;
10270 inst.instruction |= imod << 9;
10271 inst.instruction |= inst.operands[0].imm << 5;
10272 if (inst.operands[1].present)
10273 inst.instruction |= 0x100 | inst.operands[1].imm;
10277 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10278 && (inst.operands[0].imm & 4),
10279 _("selected processor does not support 'A' form "
10280 "of this instruction"));
10281 constraint (inst.operands[1].present || inst.size_req == 4,
10282 _("Thumb does not support the 2-argument "
10283 "form of this instruction"));
10284 inst.instruction |= inst.operands[0].imm;
10288 /* THUMB CPY instruction (argument parse). */
10293 if (inst.size_req == 4)
10295 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10296 inst.instruction |= inst.operands[0].reg << 8;
10297 inst.instruction |= inst.operands[1].reg;
10301 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10302 inst.instruction |= (inst.operands[0].reg & 0x7);
10303 inst.instruction |= inst.operands[1].reg << 3;
10310 set_it_insn_type (OUTSIDE_IT_INSN);
10311 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10312 inst.instruction |= inst.operands[0].reg;
10313 inst.reloc.pc_rel = 1;
10314 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10320 inst.instruction |= inst.operands[0].imm;
10326 unsigned Rd, Rn, Rm;
10328 Rd = inst.operands[0].reg;
10329 Rn = (inst.operands[1].present
10330 ? inst.operands[1].reg : Rd);
10331 Rm = inst.operands[2].reg;
10333 reject_bad_reg (Rd);
10334 reject_bad_reg (Rn);
10335 reject_bad_reg (Rm);
10337 inst.instruction |= Rd << 8;
10338 inst.instruction |= Rn << 16;
10339 inst.instruction |= Rm;
10345 if (unified_syntax && inst.size_req == 4)
10346 inst.instruction = THUMB_OP32 (inst.instruction);
10348 inst.instruction = THUMB_OP16 (inst.instruction);
10354 unsigned int cond = inst.operands[0].imm;
10356 set_it_insn_type (IT_INSN);
10357 now_it.mask = (inst.instruction & 0xf) | 0x10;
10360 /* If the condition is a negative condition, invert the mask. */
10361 if ((cond & 0x1) == 0x0)
10363 unsigned int mask = inst.instruction & 0x000f;
10365 if ((mask & 0x7) == 0)
10366 /* no conversion needed */;
10367 else if ((mask & 0x3) == 0)
10369 else if ((mask & 0x1) == 0)
10374 inst.instruction &= 0xfff0;
10375 inst.instruction |= mask;
10378 inst.instruction |= cond << 4;
10381 /* Helper function used for both push/pop and ldm/stm. */
10383 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10387 load = (inst.instruction & (1 << 20)) != 0;
10389 if (mask & (1 << 13))
10390 inst.error = _("SP not allowed in register list");
10392 if ((mask & (1 << base)) != 0
10394 inst.error = _("having the base register in the register list when "
10395 "using write back is UNPREDICTABLE");
10399 if (mask & (1 << 15))
10401 if (mask & (1 << 14))
10402 inst.error = _("LR and PC should not both be in register list");
10404 set_it_insn_type_last ();
10409 if (mask & (1 << 15))
10410 inst.error = _("PC not allowed in register list");
10413 if ((mask & (mask - 1)) == 0)
10415 /* Single register transfers implemented as str/ldr. */
10418 if (inst.instruction & (1 << 23))
10419 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10421 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10425 if (inst.instruction & (1 << 23))
10426 inst.instruction = 0x00800000; /* ia -> [base] */
10428 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10431 inst.instruction |= 0xf8400000;
10433 inst.instruction |= 0x00100000;
10435 mask = ffs (mask) - 1;
10438 else if (writeback)
10439 inst.instruction |= WRITE_BACK;
10441 inst.instruction |= mask;
10442 inst.instruction |= base << 16;
10448 /* This really doesn't seem worth it. */
10449 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10450 _("expression too complex"));
10451 constraint (inst.operands[1].writeback,
10452 _("Thumb load/store multiple does not support {reglist}^"));
10454 if (unified_syntax)
10456 bfd_boolean narrow;
10460 /* See if we can use a 16-bit instruction. */
10461 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10462 && inst.size_req != 4
10463 && !(inst.operands[1].imm & ~0xff))
10465 mask = 1 << inst.operands[0].reg;
10467 if (inst.operands[0].reg <= 7)
10469 if (inst.instruction == T_MNEM_stmia
10470 ? inst.operands[0].writeback
10471 : (inst.operands[0].writeback
10472 == !(inst.operands[1].imm & mask)))
10474 if (inst.instruction == T_MNEM_stmia
10475 && (inst.operands[1].imm & mask)
10476 && (inst.operands[1].imm & (mask - 1)))
10477 as_warn (_("value stored for r%d is UNKNOWN"),
10478 inst.operands[0].reg);
10480 inst.instruction = THUMB_OP16 (inst.instruction);
10481 inst.instruction |= inst.operands[0].reg << 8;
10482 inst.instruction |= inst.operands[1].imm;
10485 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10487 /* This means 1 register in reg list one of 3 situations:
10488 1. Instruction is stmia, but without writeback.
10489 2. lmdia without writeback, but with Rn not in
10491 3. ldmia with writeback, but with Rn in reglist.
10492 Case 3 is UNPREDICTABLE behaviour, so we handle
10493 case 1 and 2 which can be converted into a 16-bit
10494 str or ldr. The SP cases are handled below. */
10495 unsigned long opcode;
10496 /* First, record an error for Case 3. */
10497 if (inst.operands[1].imm & mask
10498 && inst.operands[0].writeback)
10500 _("having the base register in the register list when "
10501 "using write back is UNPREDICTABLE");
10503 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10505 inst.instruction = THUMB_OP16 (opcode);
10506 inst.instruction |= inst.operands[0].reg << 3;
10507 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10511 else if (inst.operands[0] .reg == REG_SP)
10513 if (inst.operands[0].writeback)
10516 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10517 ? T_MNEM_push : T_MNEM_pop);
10518 inst.instruction |= inst.operands[1].imm;
10521 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10524 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10525 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10526 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10534 if (inst.instruction < 0xffff)
10535 inst.instruction = THUMB_OP32 (inst.instruction);
10537 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10538 inst.operands[0].writeback);
10543 constraint (inst.operands[0].reg > 7
10544 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10545 constraint (inst.instruction != T_MNEM_ldmia
10546 && inst.instruction != T_MNEM_stmia,
10547 _("Thumb-2 instruction only valid in unified syntax"));
10548 if (inst.instruction == T_MNEM_stmia)
10550 if (!inst.operands[0].writeback)
10551 as_warn (_("this instruction will write back the base register"));
10552 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10553 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10554 as_warn (_("value stored for r%d is UNKNOWN"),
10555 inst.operands[0].reg);
10559 if (!inst.operands[0].writeback
10560 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10561 as_warn (_("this instruction will write back the base register"));
10562 else if (inst.operands[0].writeback
10563 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10564 as_warn (_("this instruction will not write back the base register"));
10567 inst.instruction = THUMB_OP16 (inst.instruction);
10568 inst.instruction |= inst.operands[0].reg << 8;
10569 inst.instruction |= inst.operands[1].imm;
10576 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10577 || inst.operands[1].postind || inst.operands[1].writeback
10578 || inst.operands[1].immisreg || inst.operands[1].shifted
10579 || inst.operands[1].negative,
10582 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10584 inst.instruction |= inst.operands[0].reg << 12;
10585 inst.instruction |= inst.operands[1].reg << 16;
10586 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10592 if (!inst.operands[1].present)
10594 constraint (inst.operands[0].reg == REG_LR,
10595 _("r14 not allowed as first register "
10596 "when second register is omitted"));
10597 inst.operands[1].reg = inst.operands[0].reg + 1;
10599 constraint (inst.operands[0].reg == inst.operands[1].reg,
10602 inst.instruction |= inst.operands[0].reg << 12;
10603 inst.instruction |= inst.operands[1].reg << 8;
10604 inst.instruction |= inst.operands[2].reg << 16;
10610 unsigned long opcode;
10613 if (inst.operands[0].isreg
10614 && !inst.operands[0].preind
10615 && inst.operands[0].reg == REG_PC)
10616 set_it_insn_type_last ();
10618 opcode = inst.instruction;
10619 if (unified_syntax)
10621 if (!inst.operands[1].isreg)
10623 if (opcode <= 0xffff)
10624 inst.instruction = THUMB_OP32 (opcode);
10625 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10628 if (inst.operands[1].isreg
10629 && !inst.operands[1].writeback
10630 && !inst.operands[1].shifted && !inst.operands[1].postind
10631 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10632 && opcode <= 0xffff
10633 && inst.size_req != 4)
10635 /* Insn may have a 16-bit form. */
10636 Rn = inst.operands[1].reg;
10637 if (inst.operands[1].immisreg)
10639 inst.instruction = THUMB_OP16 (opcode);
10641 if (Rn <= 7 && inst.operands[1].imm <= 7)
10643 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10644 reject_bad_reg (inst.operands[1].imm);
10646 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10647 && opcode != T_MNEM_ldrsb)
10648 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10649 || (Rn == REG_SP && opcode == T_MNEM_str))
10656 if (inst.reloc.pc_rel)
10657 opcode = T_MNEM_ldr_pc2;
10659 opcode = T_MNEM_ldr_pc;
10663 if (opcode == T_MNEM_ldr)
10664 opcode = T_MNEM_ldr_sp;
10666 opcode = T_MNEM_str_sp;
10668 inst.instruction = inst.operands[0].reg << 8;
10672 inst.instruction = inst.operands[0].reg;
10673 inst.instruction |= inst.operands[1].reg << 3;
10675 inst.instruction |= THUMB_OP16 (opcode);
10676 if (inst.size_req == 2)
10677 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10679 inst.relax = opcode;
10683 /* Definitely a 32-bit variant. */
10685 /* Warning for Erratum 752419. */
10686 if (opcode == T_MNEM_ldr
10687 && inst.operands[0].reg == REG_SP
10688 && inst.operands[1].writeback == 1
10689 && !inst.operands[1].immisreg)
10691 if (no_cpu_selected ()
10692 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10693 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10694 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10695 as_warn (_("This instruction may be unpredictable "
10696 "if executed on M-profile cores "
10697 "with interrupts enabled."));
10700 /* Do some validations regarding addressing modes. */
10701 if (inst.operands[1].immisreg)
10702 reject_bad_reg (inst.operands[1].imm);
10704 constraint (inst.operands[1].writeback == 1
10705 && inst.operands[0].reg == inst.operands[1].reg,
10708 inst.instruction = THUMB_OP32 (opcode);
10709 inst.instruction |= inst.operands[0].reg << 12;
10710 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10711 check_ldr_r15_aligned ();
10715 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10717 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10719 /* Only [Rn,Rm] is acceptable. */
10720 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10721 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10722 || inst.operands[1].postind || inst.operands[1].shifted
10723 || inst.operands[1].negative,
10724 _("Thumb does not support this addressing mode"));
10725 inst.instruction = THUMB_OP16 (inst.instruction);
10729 inst.instruction = THUMB_OP16 (inst.instruction);
10730 if (!inst.operands[1].isreg)
10731 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10734 constraint (!inst.operands[1].preind
10735 || inst.operands[1].shifted
10736 || inst.operands[1].writeback,
10737 _("Thumb does not support this addressing mode"));
10738 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10740 constraint (inst.instruction & 0x0600,
10741 _("byte or halfword not valid for base register"));
10742 constraint (inst.operands[1].reg == REG_PC
10743 && !(inst.instruction & THUMB_LOAD_BIT),
10744 _("r15 based store not allowed"));
10745 constraint (inst.operands[1].immisreg,
10746 _("invalid base register for register offset"));
10748 if (inst.operands[1].reg == REG_PC)
10749 inst.instruction = T_OPCODE_LDR_PC;
10750 else if (inst.instruction & THUMB_LOAD_BIT)
10751 inst.instruction = T_OPCODE_LDR_SP;
10753 inst.instruction = T_OPCODE_STR_SP;
10755 inst.instruction |= inst.operands[0].reg << 8;
10756 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10760 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10761 if (!inst.operands[1].immisreg)
10763 /* Immediate offset. */
10764 inst.instruction |= inst.operands[0].reg;
10765 inst.instruction |= inst.operands[1].reg << 3;
10766 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10770 /* Register offset. */
10771 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10772 constraint (inst.operands[1].negative,
10773 _("Thumb does not support this addressing mode"));
10776 switch (inst.instruction)
10778 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10779 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10780 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10781 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10782 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10783 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10784 case 0x5600 /* ldrsb */:
10785 case 0x5e00 /* ldrsh */: break;
10789 inst.instruction |= inst.operands[0].reg;
10790 inst.instruction |= inst.operands[1].reg << 3;
10791 inst.instruction |= inst.operands[1].imm << 6;
10797 if (!inst.operands[1].present)
10799 inst.operands[1].reg = inst.operands[0].reg + 1;
10800 constraint (inst.operands[0].reg == REG_LR,
10801 _("r14 not allowed here"));
10802 constraint (inst.operands[0].reg == REG_R12,
10803 _("r12 not allowed here"));
10806 if (inst.operands[2].writeback
10807 && (inst.operands[0].reg == inst.operands[2].reg
10808 || inst.operands[1].reg == inst.operands[2].reg))
10809 as_warn (_("base register written back, and overlaps "
10810 "one of transfer registers"));
10812 inst.instruction |= inst.operands[0].reg << 12;
10813 inst.instruction |= inst.operands[1].reg << 8;
10814 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10820 inst.instruction |= inst.operands[0].reg << 12;
10821 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10827 unsigned Rd, Rn, Rm, Ra;
10829 Rd = inst.operands[0].reg;
10830 Rn = inst.operands[1].reg;
10831 Rm = inst.operands[2].reg;
10832 Ra = inst.operands[3].reg;
10834 reject_bad_reg (Rd);
10835 reject_bad_reg (Rn);
10836 reject_bad_reg (Rm);
10837 reject_bad_reg (Ra);
10839 inst.instruction |= Rd << 8;
10840 inst.instruction |= Rn << 16;
10841 inst.instruction |= Rm;
10842 inst.instruction |= Ra << 12;
10848 unsigned RdLo, RdHi, Rn, Rm;
10850 RdLo = inst.operands[0].reg;
10851 RdHi = inst.operands[1].reg;
10852 Rn = inst.operands[2].reg;
10853 Rm = inst.operands[3].reg;
10855 reject_bad_reg (RdLo);
10856 reject_bad_reg (RdHi);
10857 reject_bad_reg (Rn);
10858 reject_bad_reg (Rm);
10860 inst.instruction |= RdLo << 12;
10861 inst.instruction |= RdHi << 8;
10862 inst.instruction |= Rn << 16;
10863 inst.instruction |= Rm;
10867 do_t_mov_cmp (void)
10871 Rn = inst.operands[0].reg;
10872 Rm = inst.operands[1].reg;
10875 set_it_insn_type_last ();
10877 if (unified_syntax)
10879 int r0off = (inst.instruction == T_MNEM_mov
10880 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10881 unsigned long opcode;
10882 bfd_boolean narrow;
10883 bfd_boolean low_regs;
10885 low_regs = (Rn <= 7 && Rm <= 7);
10886 opcode = inst.instruction;
10887 if (in_it_block ())
10888 narrow = opcode != T_MNEM_movs;
10890 narrow = opcode != T_MNEM_movs || low_regs;
10891 if (inst.size_req == 4
10892 || inst.operands[1].shifted)
10895 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10896 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10897 && !inst.operands[1].shifted
10901 inst.instruction = T2_SUBS_PC_LR;
10905 if (opcode == T_MNEM_cmp)
10907 constraint (Rn == REG_PC, BAD_PC);
10910 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10912 warn_deprecated_sp (Rm);
10913 /* R15 was documented as a valid choice for Rm in ARMv6,
10914 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10915 tools reject R15, so we do too. */
10916 constraint (Rm == REG_PC, BAD_PC);
10919 reject_bad_reg (Rm);
10921 else if (opcode == T_MNEM_mov
10922 || opcode == T_MNEM_movs)
10924 if (inst.operands[1].isreg)
10926 if (opcode == T_MNEM_movs)
10928 reject_bad_reg (Rn);
10929 reject_bad_reg (Rm);
10933 /* This is mov.n. */
10934 if ((Rn == REG_SP || Rn == REG_PC)
10935 && (Rm == REG_SP || Rm == REG_PC))
10937 as_warn (_("Use of r%u as a source register is "
10938 "deprecated when r%u is the destination "
10939 "register."), Rm, Rn);
10944 /* This is mov.w. */
10945 constraint (Rn == REG_PC, BAD_PC);
10946 constraint (Rm == REG_PC, BAD_PC);
10947 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10951 reject_bad_reg (Rn);
10954 if (!inst.operands[1].isreg)
10956 /* Immediate operand. */
10957 if (!in_it_block () && opcode == T_MNEM_mov)
10959 if (low_regs && narrow)
10961 inst.instruction = THUMB_OP16 (opcode);
10962 inst.instruction |= Rn << 8;
10963 if (inst.size_req == 2)
10964 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10966 inst.relax = opcode;
10970 inst.instruction = THUMB_OP32 (inst.instruction);
10971 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10972 inst.instruction |= Rn << r0off;
10973 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10976 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10977 && (inst.instruction == T_MNEM_mov
10978 || inst.instruction == T_MNEM_movs))
10980 /* Register shifts are encoded as separate shift instructions. */
10981 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10983 if (in_it_block ())
10988 if (inst.size_req == 4)
10991 if (!low_regs || inst.operands[1].imm > 7)
10997 switch (inst.operands[1].shift_kind)
11000 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11003 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11006 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11009 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11015 inst.instruction = opcode;
11018 inst.instruction |= Rn;
11019 inst.instruction |= inst.operands[1].imm << 3;
11024 inst.instruction |= CONDS_BIT;
11026 inst.instruction |= Rn << 8;
11027 inst.instruction |= Rm << 16;
11028 inst.instruction |= inst.operands[1].imm;
11033 /* Some mov with immediate shift have narrow variants.
11034 Register shifts are handled above. */
11035 if (low_regs && inst.operands[1].shifted
11036 && (inst.instruction == T_MNEM_mov
11037 || inst.instruction == T_MNEM_movs))
11039 if (in_it_block ())
11040 narrow = (inst.instruction == T_MNEM_mov);
11042 narrow = (inst.instruction == T_MNEM_movs);
11047 switch (inst.operands[1].shift_kind)
11049 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11050 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11051 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11052 default: narrow = FALSE; break;
11058 inst.instruction |= Rn;
11059 inst.instruction |= Rm << 3;
11060 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11064 inst.instruction = THUMB_OP32 (inst.instruction);
11065 inst.instruction |= Rn << r0off;
11066 encode_thumb32_shifted_operand (1);
11070 switch (inst.instruction)
11073 /* In v4t or v5t a move of two lowregs produces unpredictable
11074 results. Don't allow this. */
11077 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11078 "MOV Rd, Rs with two low registers is not "
11079 "permitted on this architecture");
11080 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11084 inst.instruction = T_OPCODE_MOV_HR;
11085 inst.instruction |= (Rn & 0x8) << 4;
11086 inst.instruction |= (Rn & 0x7);
11087 inst.instruction |= Rm << 3;
11091 /* We know we have low registers at this point.
11092 Generate LSLS Rd, Rs, #0. */
11093 inst.instruction = T_OPCODE_LSL_I;
11094 inst.instruction |= Rn;
11095 inst.instruction |= Rm << 3;
11101 inst.instruction = T_OPCODE_CMP_LR;
11102 inst.instruction |= Rn;
11103 inst.instruction |= Rm << 3;
11107 inst.instruction = T_OPCODE_CMP_HR;
11108 inst.instruction |= (Rn & 0x8) << 4;
11109 inst.instruction |= (Rn & 0x7);
11110 inst.instruction |= Rm << 3;
11117 inst.instruction = THUMB_OP16 (inst.instruction);
11119 /* PR 10443: Do not silently ignore shifted operands. */
11120 constraint (inst.operands[1].shifted,
11121 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11123 if (inst.operands[1].isreg)
11125 if (Rn < 8 && Rm < 8)
11127 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11128 since a MOV instruction produces unpredictable results. */
11129 if (inst.instruction == T_OPCODE_MOV_I8)
11130 inst.instruction = T_OPCODE_ADD_I3;
11132 inst.instruction = T_OPCODE_CMP_LR;
11134 inst.instruction |= Rn;
11135 inst.instruction |= Rm << 3;
11139 if (inst.instruction == T_OPCODE_MOV_I8)
11140 inst.instruction = T_OPCODE_MOV_HR;
11142 inst.instruction = T_OPCODE_CMP_HR;
11148 constraint (Rn > 7,
11149 _("only lo regs allowed with immediate"));
11150 inst.instruction |= Rn << 8;
11151 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11162 top = (inst.instruction & 0x00800000) != 0;
11163 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11165 constraint (top, _(":lower16: not allowed this instruction"));
11166 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11168 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11170 constraint (!top, _(":upper16: not allowed this instruction"));
11171 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11174 Rd = inst.operands[0].reg;
11175 reject_bad_reg (Rd);
11177 inst.instruction |= Rd << 8;
11178 if (inst.reloc.type == BFD_RELOC_UNUSED)
11180 imm = inst.reloc.exp.X_add_number;
11181 inst.instruction |= (imm & 0xf000) << 4;
11182 inst.instruction |= (imm & 0x0800) << 15;
11183 inst.instruction |= (imm & 0x0700) << 4;
11184 inst.instruction |= (imm & 0x00ff);
11189 do_t_mvn_tst (void)
11193 Rn = inst.operands[0].reg;
11194 Rm = inst.operands[1].reg;
11196 if (inst.instruction == T_MNEM_cmp
11197 || inst.instruction == T_MNEM_cmn)
11198 constraint (Rn == REG_PC, BAD_PC);
11200 reject_bad_reg (Rn);
11201 reject_bad_reg (Rm);
11203 if (unified_syntax)
11205 int r0off = (inst.instruction == T_MNEM_mvn
11206 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11207 bfd_boolean narrow;
11209 if (inst.size_req == 4
11210 || inst.instruction > 0xffff
11211 || inst.operands[1].shifted
11212 || Rn > 7 || Rm > 7)
11214 else if (inst.instruction == T_MNEM_cmn)
11216 else if (THUMB_SETS_FLAGS (inst.instruction))
11217 narrow = !in_it_block ();
11219 narrow = in_it_block ();
11221 if (!inst.operands[1].isreg)
11223 /* For an immediate, we always generate a 32-bit opcode;
11224 section relaxation will shrink it later if possible. */
11225 if (inst.instruction < 0xffff)
11226 inst.instruction = THUMB_OP32 (inst.instruction);
11227 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11228 inst.instruction |= Rn << r0off;
11229 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11233 /* See if we can do this with a 16-bit instruction. */
11236 inst.instruction = THUMB_OP16 (inst.instruction);
11237 inst.instruction |= Rn;
11238 inst.instruction |= Rm << 3;
11242 constraint (inst.operands[1].shifted
11243 && inst.operands[1].immisreg,
11244 _("shift must be constant"));
11245 if (inst.instruction < 0xffff)
11246 inst.instruction = THUMB_OP32 (inst.instruction);
11247 inst.instruction |= Rn << r0off;
11248 encode_thumb32_shifted_operand (1);
11254 constraint (inst.instruction > 0xffff
11255 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11256 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11257 _("unshifted register required"));
11258 constraint (Rn > 7 || Rm > 7,
11261 inst.instruction = THUMB_OP16 (inst.instruction);
11262 inst.instruction |= Rn;
11263 inst.instruction |= Rm << 3;
11272 if (do_vfp_nsyn_mrs () == SUCCESS)
11275 Rd = inst.operands[0].reg;
11276 reject_bad_reg (Rd);
11277 inst.instruction |= Rd << 8;
11279 if (inst.operands[1].isreg)
11281 unsigned br = inst.operands[1].reg;
11282 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11283 as_bad (_("bad register for mrs"));
11285 inst.instruction |= br & (0xf << 16);
11286 inst.instruction |= (br & 0x300) >> 4;
11287 inst.instruction |= (br & SPSR_BIT) >> 2;
11291 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11293 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11295 /* PR gas/12698: The constraint is only applied for m_profile.
11296 If the user has specified -march=all, we want to ignore it as
11297 we are building for any CPU type, including non-m variants. */
11298 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11299 constraint ((flags != 0) && m_profile, _("selected processor does "
11300 "not support requested special purpose register"));
11303 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11305 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11306 _("'APSR', 'CPSR' or 'SPSR' expected"));
11308 inst.instruction |= (flags & SPSR_BIT) >> 2;
11309 inst.instruction |= inst.operands[1].imm & 0xff;
11310 inst.instruction |= 0xf0000;
11320 if (do_vfp_nsyn_msr () == SUCCESS)
11323 constraint (!inst.operands[1].isreg,
11324 _("Thumb encoding does not support an immediate here"));
11326 if (inst.operands[0].isreg)
11327 flags = (int)(inst.operands[0].reg);
11329 flags = inst.operands[0].imm;
11331 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11333 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11335 /* PR gas/12698: The constraint is only applied for m_profile.
11336 If the user has specified -march=all, we want to ignore it as
11337 we are building for any CPU type, including non-m variants. */
11338 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11339 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11340 && (bits & ~(PSR_s | PSR_f)) != 0)
11341 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11342 && bits != PSR_f)) && m_profile,
11343 _("selected processor does not support requested special "
11344 "purpose register"));
11347 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11348 "requested special purpose register"));
11350 Rn = inst.operands[1].reg;
11351 reject_bad_reg (Rn);
11353 inst.instruction |= (flags & SPSR_BIT) >> 2;
11354 inst.instruction |= (flags & 0xf0000) >> 8;
11355 inst.instruction |= (flags & 0x300) >> 4;
11356 inst.instruction |= (flags & 0xff);
11357 inst.instruction |= Rn << 16;
11363 bfd_boolean narrow;
11364 unsigned Rd, Rn, Rm;
11366 if (!inst.operands[2].present)
11367 inst.operands[2].reg = inst.operands[0].reg;
11369 Rd = inst.operands[0].reg;
11370 Rn = inst.operands[1].reg;
11371 Rm = inst.operands[2].reg;
11373 if (unified_syntax)
11375 if (inst.size_req == 4
11381 else if (inst.instruction == T_MNEM_muls)
11382 narrow = !in_it_block ();
11384 narrow = in_it_block ();
11388 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11389 constraint (Rn > 7 || Rm > 7,
11396 /* 16-bit MULS/Conditional MUL. */
11397 inst.instruction = THUMB_OP16 (inst.instruction);
11398 inst.instruction |= Rd;
11401 inst.instruction |= Rm << 3;
11403 inst.instruction |= Rn << 3;
11405 constraint (1, _("dest must overlap one source register"));
11409 constraint (inst.instruction != T_MNEM_mul,
11410 _("Thumb-2 MUL must not set flags"));
11412 inst.instruction = THUMB_OP32 (inst.instruction);
11413 inst.instruction |= Rd << 8;
11414 inst.instruction |= Rn << 16;
11415 inst.instruction |= Rm << 0;
11417 reject_bad_reg (Rd);
11418 reject_bad_reg (Rn);
11419 reject_bad_reg (Rm);
11426 unsigned RdLo, RdHi, Rn, Rm;
11428 RdLo = inst.operands[0].reg;
11429 RdHi = inst.operands[1].reg;
11430 Rn = inst.operands[2].reg;
11431 Rm = inst.operands[3].reg;
11433 reject_bad_reg (RdLo);
11434 reject_bad_reg (RdHi);
11435 reject_bad_reg (Rn);
11436 reject_bad_reg (Rm);
11438 inst.instruction |= RdLo << 12;
11439 inst.instruction |= RdHi << 8;
11440 inst.instruction |= Rn << 16;
11441 inst.instruction |= Rm;
11444 as_tsktsk (_("rdhi and rdlo must be different"));
11450 set_it_insn_type (NEUTRAL_IT_INSN);
11452 if (unified_syntax)
11454 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11456 inst.instruction = THUMB_OP32 (inst.instruction);
11457 inst.instruction |= inst.operands[0].imm;
11461 /* PR9722: Check for Thumb2 availability before
11462 generating a thumb2 nop instruction. */
11463 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11465 inst.instruction = THUMB_OP16 (inst.instruction);
11466 inst.instruction |= inst.operands[0].imm << 4;
11469 inst.instruction = 0x46c0;
11474 constraint (inst.operands[0].present,
11475 _("Thumb does not support NOP with hints"));
11476 inst.instruction = 0x46c0;
11483 if (unified_syntax)
11485 bfd_boolean narrow;
11487 if (THUMB_SETS_FLAGS (inst.instruction))
11488 narrow = !in_it_block ();
11490 narrow = in_it_block ();
11491 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11493 if (inst.size_req == 4)
11498 inst.instruction = THUMB_OP32 (inst.instruction);
11499 inst.instruction |= inst.operands[0].reg << 8;
11500 inst.instruction |= inst.operands[1].reg << 16;
11504 inst.instruction = THUMB_OP16 (inst.instruction);
11505 inst.instruction |= inst.operands[0].reg;
11506 inst.instruction |= inst.operands[1].reg << 3;
11511 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11513 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11515 inst.instruction = THUMB_OP16 (inst.instruction);
11516 inst.instruction |= inst.operands[0].reg;
11517 inst.instruction |= inst.operands[1].reg << 3;
11526 Rd = inst.operands[0].reg;
11527 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11529 reject_bad_reg (Rd);
11530 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11531 reject_bad_reg (Rn);
11533 inst.instruction |= Rd << 8;
11534 inst.instruction |= Rn << 16;
11536 if (!inst.operands[2].isreg)
11538 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11539 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11545 Rm = inst.operands[2].reg;
11546 reject_bad_reg (Rm);
11548 constraint (inst.operands[2].shifted
11549 && inst.operands[2].immisreg,
11550 _("shift must be constant"));
11551 encode_thumb32_shifted_operand (2);
11558 unsigned Rd, Rn, Rm;
11560 Rd = inst.operands[0].reg;
11561 Rn = inst.operands[1].reg;
11562 Rm = inst.operands[2].reg;
11564 reject_bad_reg (Rd);
11565 reject_bad_reg (Rn);
11566 reject_bad_reg (Rm);
11568 inst.instruction |= Rd << 8;
11569 inst.instruction |= Rn << 16;
11570 inst.instruction |= Rm;
11571 if (inst.operands[3].present)
11573 unsigned int val = inst.reloc.exp.X_add_number;
11574 constraint (inst.reloc.exp.X_op != O_constant,
11575 _("expression too complex"));
11576 inst.instruction |= (val & 0x1c) << 10;
11577 inst.instruction |= (val & 0x03) << 6;
11584 if (!inst.operands[3].present)
11588 inst.instruction &= ~0x00000020;
11590 /* PR 10168. Swap the Rm and Rn registers. */
11591 Rtmp = inst.operands[1].reg;
11592 inst.operands[1].reg = inst.operands[2].reg;
11593 inst.operands[2].reg = Rtmp;
11601 if (inst.operands[0].immisreg)
11602 reject_bad_reg (inst.operands[0].imm);
11604 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11608 do_t_push_pop (void)
11612 constraint (inst.operands[0].writeback,
11613 _("push/pop do not support {reglist}^"));
11614 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11615 _("expression too complex"));
11617 mask = inst.operands[0].imm;
11618 if ((mask & ~0xff) == 0)
11619 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11620 else if ((inst.instruction == T_MNEM_push
11621 && (mask & ~0xff) == 1 << REG_LR)
11622 || (inst.instruction == T_MNEM_pop
11623 && (mask & ~0xff) == 1 << REG_PC))
11625 inst.instruction = THUMB_OP16 (inst.instruction);
11626 inst.instruction |= THUMB_PP_PC_LR;
11627 inst.instruction |= mask & 0xff;
11629 else if (unified_syntax)
11631 inst.instruction = THUMB_OP32 (inst.instruction);
11632 encode_thumb2_ldmstm (13, mask, TRUE);
11636 inst.error = _("invalid register list to push/pop instruction");
11646 Rd = inst.operands[0].reg;
11647 Rm = inst.operands[1].reg;
11649 reject_bad_reg (Rd);
11650 reject_bad_reg (Rm);
11652 inst.instruction |= Rd << 8;
11653 inst.instruction |= Rm << 16;
11654 inst.instruction |= Rm;
11662 Rd = inst.operands[0].reg;
11663 Rm = inst.operands[1].reg;
11665 reject_bad_reg (Rd);
11666 reject_bad_reg (Rm);
11668 if (Rd <= 7 && Rm <= 7
11669 && inst.size_req != 4)
11671 inst.instruction = THUMB_OP16 (inst.instruction);
11672 inst.instruction |= Rd;
11673 inst.instruction |= Rm << 3;
11675 else if (unified_syntax)
11677 inst.instruction = THUMB_OP32 (inst.instruction);
11678 inst.instruction |= Rd << 8;
11679 inst.instruction |= Rm << 16;
11680 inst.instruction |= Rm;
11683 inst.error = BAD_HIREG;
11691 Rd = inst.operands[0].reg;
11692 Rm = inst.operands[1].reg;
11694 reject_bad_reg (Rd);
11695 reject_bad_reg (Rm);
11697 inst.instruction |= Rd << 8;
11698 inst.instruction |= Rm;
11706 Rd = inst.operands[0].reg;
11707 Rs = (inst.operands[1].present
11708 ? inst.operands[1].reg /* Rd, Rs, foo */
11709 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11711 reject_bad_reg (Rd);
11712 reject_bad_reg (Rs);
11713 if (inst.operands[2].isreg)
11714 reject_bad_reg (inst.operands[2].reg);
11716 inst.instruction |= Rd << 8;
11717 inst.instruction |= Rs << 16;
11718 if (!inst.operands[2].isreg)
11720 bfd_boolean narrow;
11722 if ((inst.instruction & 0x00100000) != 0)
11723 narrow = !in_it_block ();
11725 narrow = in_it_block ();
11727 if (Rd > 7 || Rs > 7)
11730 if (inst.size_req == 4 || !unified_syntax)
11733 if (inst.reloc.exp.X_op != O_constant
11734 || inst.reloc.exp.X_add_number != 0)
11737 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11738 relaxation, but it doesn't seem worth the hassle. */
11741 inst.reloc.type = BFD_RELOC_UNUSED;
11742 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11743 inst.instruction |= Rs << 3;
11744 inst.instruction |= Rd;
11748 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11749 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11753 encode_thumb32_shifted_operand (2);
11759 set_it_insn_type (OUTSIDE_IT_INSN);
11760 if (inst.operands[0].imm)
11761 inst.instruction |= 0x8;
11767 if (!inst.operands[1].present)
11768 inst.operands[1].reg = inst.operands[0].reg;
11770 if (unified_syntax)
11772 bfd_boolean narrow;
11775 switch (inst.instruction)
11778 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11780 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11782 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11784 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11788 if (THUMB_SETS_FLAGS (inst.instruction))
11789 narrow = !in_it_block ();
11791 narrow = in_it_block ();
11792 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11794 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11796 if (inst.operands[2].isreg
11797 && (inst.operands[1].reg != inst.operands[0].reg
11798 || inst.operands[2].reg > 7))
11800 if (inst.size_req == 4)
11803 reject_bad_reg (inst.operands[0].reg);
11804 reject_bad_reg (inst.operands[1].reg);
11808 if (inst.operands[2].isreg)
11810 reject_bad_reg (inst.operands[2].reg);
11811 inst.instruction = THUMB_OP32 (inst.instruction);
11812 inst.instruction |= inst.operands[0].reg << 8;
11813 inst.instruction |= inst.operands[1].reg << 16;
11814 inst.instruction |= inst.operands[2].reg;
11816 /* PR 12854: Error on extraneous shifts. */
11817 constraint (inst.operands[2].shifted,
11818 _("extraneous shift as part of operand to shift insn"));
11822 inst.operands[1].shifted = 1;
11823 inst.operands[1].shift_kind = shift_kind;
11824 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11825 ? T_MNEM_movs : T_MNEM_mov);
11826 inst.instruction |= inst.operands[0].reg << 8;
11827 encode_thumb32_shifted_operand (1);
11828 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11829 inst.reloc.type = BFD_RELOC_UNUSED;
11834 if (inst.operands[2].isreg)
11836 switch (shift_kind)
11838 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11839 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11840 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11841 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11845 inst.instruction |= inst.operands[0].reg;
11846 inst.instruction |= inst.operands[2].reg << 3;
11848 /* PR 12854: Error on extraneous shifts. */
11849 constraint (inst.operands[2].shifted,
11850 _("extraneous shift as part of operand to shift insn"));
11854 switch (shift_kind)
11856 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11857 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11858 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11861 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11862 inst.instruction |= inst.operands[0].reg;
11863 inst.instruction |= inst.operands[1].reg << 3;
11869 constraint (inst.operands[0].reg > 7
11870 || inst.operands[1].reg > 7, BAD_HIREG);
11871 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11873 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11875 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11876 constraint (inst.operands[0].reg != inst.operands[1].reg,
11877 _("source1 and dest must be same register"));
11879 switch (inst.instruction)
11881 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11882 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11883 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11884 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11888 inst.instruction |= inst.operands[0].reg;
11889 inst.instruction |= inst.operands[2].reg << 3;
11891 /* PR 12854: Error on extraneous shifts. */
11892 constraint (inst.operands[2].shifted,
11893 _("extraneous shift as part of operand to shift insn"));
11897 switch (inst.instruction)
11899 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11900 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11901 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11902 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11905 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11906 inst.instruction |= inst.operands[0].reg;
11907 inst.instruction |= inst.operands[1].reg << 3;
11915 unsigned Rd, Rn, Rm;
11917 Rd = inst.operands[0].reg;
11918 Rn = inst.operands[1].reg;
11919 Rm = inst.operands[2].reg;
11921 reject_bad_reg (Rd);
11922 reject_bad_reg (Rn);
11923 reject_bad_reg (Rm);
11925 inst.instruction |= Rd << 8;
11926 inst.instruction |= Rn << 16;
11927 inst.instruction |= Rm;
11933 unsigned Rd, Rn, Rm;
11935 Rd = inst.operands[0].reg;
11936 Rm = inst.operands[1].reg;
11937 Rn = inst.operands[2].reg;
11939 reject_bad_reg (Rd);
11940 reject_bad_reg (Rn);
11941 reject_bad_reg (Rm);
11943 inst.instruction |= Rd << 8;
11944 inst.instruction |= Rn << 16;
11945 inst.instruction |= Rm;
11951 unsigned int value = inst.reloc.exp.X_add_number;
11952 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11953 _("SMC is not permitted on this architecture"));
11954 constraint (inst.reloc.exp.X_op != O_constant,
11955 _("expression too complex"));
11956 inst.reloc.type = BFD_RELOC_UNUSED;
11957 inst.instruction |= (value & 0xf000) >> 12;
11958 inst.instruction |= (value & 0x0ff0);
11959 inst.instruction |= (value & 0x000f) << 16;
11965 unsigned int value = inst.reloc.exp.X_add_number;
11967 inst.reloc.type = BFD_RELOC_UNUSED;
11968 inst.instruction |= (value & 0x0fff);
11969 inst.instruction |= (value & 0xf000) << 4;
11973 do_t_ssat_usat (int bias)
11977 Rd = inst.operands[0].reg;
11978 Rn = inst.operands[2].reg;
11980 reject_bad_reg (Rd);
11981 reject_bad_reg (Rn);
11983 inst.instruction |= Rd << 8;
11984 inst.instruction |= inst.operands[1].imm - bias;
11985 inst.instruction |= Rn << 16;
11987 if (inst.operands[3].present)
11989 offsetT shift_amount = inst.reloc.exp.X_add_number;
11991 inst.reloc.type = BFD_RELOC_UNUSED;
11993 constraint (inst.reloc.exp.X_op != O_constant,
11994 _("expression too complex"));
11996 if (shift_amount != 0)
11998 constraint (shift_amount > 31,
11999 _("shift expression is too large"));
12001 if (inst.operands[3].shift_kind == SHIFT_ASR)
12002 inst.instruction |= 0x00200000; /* sh bit. */
12004 inst.instruction |= (shift_amount & 0x1c) << 10;
12005 inst.instruction |= (shift_amount & 0x03) << 6;
12013 do_t_ssat_usat (1);
12021 Rd = inst.operands[0].reg;
12022 Rn = inst.operands[2].reg;
12024 reject_bad_reg (Rd);
12025 reject_bad_reg (Rn);
12027 inst.instruction |= Rd << 8;
12028 inst.instruction |= inst.operands[1].imm - 1;
12029 inst.instruction |= Rn << 16;
12035 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12036 || inst.operands[2].postind || inst.operands[2].writeback
12037 || inst.operands[2].immisreg || inst.operands[2].shifted
12038 || inst.operands[2].negative,
12041 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12043 inst.instruction |= inst.operands[0].reg << 8;
12044 inst.instruction |= inst.operands[1].reg << 12;
12045 inst.instruction |= inst.operands[2].reg << 16;
12046 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12052 if (!inst.operands[2].present)
12053 inst.operands[2].reg = inst.operands[1].reg + 1;
12055 constraint (inst.operands[0].reg == inst.operands[1].reg
12056 || inst.operands[0].reg == inst.operands[2].reg
12057 || inst.operands[0].reg == inst.operands[3].reg,
12060 inst.instruction |= inst.operands[0].reg;
12061 inst.instruction |= inst.operands[1].reg << 12;
12062 inst.instruction |= inst.operands[2].reg << 8;
12063 inst.instruction |= inst.operands[3].reg << 16;
12069 unsigned Rd, Rn, Rm;
12071 Rd = inst.operands[0].reg;
12072 Rn = inst.operands[1].reg;
12073 Rm = inst.operands[2].reg;
12075 reject_bad_reg (Rd);
12076 reject_bad_reg (Rn);
12077 reject_bad_reg (Rm);
12079 inst.instruction |= Rd << 8;
12080 inst.instruction |= Rn << 16;
12081 inst.instruction |= Rm;
12082 inst.instruction |= inst.operands[3].imm << 4;
12090 Rd = inst.operands[0].reg;
12091 Rm = inst.operands[1].reg;
12093 reject_bad_reg (Rd);
12094 reject_bad_reg (Rm);
12096 if (inst.instruction <= 0xffff
12097 && inst.size_req != 4
12098 && Rd <= 7 && Rm <= 7
12099 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12101 inst.instruction = THUMB_OP16 (inst.instruction);
12102 inst.instruction |= Rd;
12103 inst.instruction |= Rm << 3;
12105 else if (unified_syntax)
12107 if (inst.instruction <= 0xffff)
12108 inst.instruction = THUMB_OP32 (inst.instruction);
12109 inst.instruction |= Rd << 8;
12110 inst.instruction |= Rm;
12111 inst.instruction |= inst.operands[2].imm << 4;
12115 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12116 _("Thumb encoding does not support rotation"));
12117 constraint (1, BAD_HIREG);
12124 /* We have to do the following check manually as ARM_EXT_OS only applies
12126 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12128 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12129 /* This only applies to the v6m howver, not later architectures. */
12130 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12131 as_bad (_("SVC is not permitted on this architecture"));
12132 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12135 inst.reloc.type = BFD_RELOC_ARM_SWI;
12144 half = (inst.instruction & 0x10) != 0;
12145 set_it_insn_type_last ();
12146 constraint (inst.operands[0].immisreg,
12147 _("instruction requires register index"));
12149 Rn = inst.operands[0].reg;
12150 Rm = inst.operands[0].imm;
12152 constraint (Rn == REG_SP, BAD_SP);
12153 reject_bad_reg (Rm);
12155 constraint (!half && inst.operands[0].shifted,
12156 _("instruction does not allow shifted index"));
12157 inst.instruction |= (Rn << 16) | Rm;
12163 do_t_ssat_usat (0);
12171 Rd = inst.operands[0].reg;
12172 Rn = inst.operands[2].reg;
12174 reject_bad_reg (Rd);
12175 reject_bad_reg (Rn);
12177 inst.instruction |= Rd << 8;
12178 inst.instruction |= inst.operands[1].imm;
12179 inst.instruction |= Rn << 16;
12182 /* Neon instruction encoder helpers. */
12184 /* Encodings for the different types for various Neon opcodes. */
12186 /* An "invalid" code for the following tables. */
12189 struct neon_tab_entry
12192 unsigned float_or_poly;
12193 unsigned scalar_or_imm;
12196 /* Map overloaded Neon opcodes to their respective encodings. */
12197 #define NEON_ENC_TAB \
12198 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12199 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12200 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12201 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12202 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12203 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12204 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12205 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12206 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12207 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12208 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12209 /* Register variants of the following two instructions are encoded as
12210 vcge / vcgt with the operands reversed. */ \
12211 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12212 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12213 X(vfma, N_INV, 0x0000c10, N_INV), \
12214 X(vfms, N_INV, 0x0200c10, N_INV), \
12215 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12216 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12217 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12218 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12219 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12220 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12221 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12222 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12223 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12224 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12225 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12226 X(vshl, 0x0000400, N_INV, 0x0800510), \
12227 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12228 X(vand, 0x0000110, N_INV, 0x0800030), \
12229 X(vbic, 0x0100110, N_INV, 0x0800030), \
12230 X(veor, 0x1000110, N_INV, N_INV), \
12231 X(vorn, 0x0300110, N_INV, 0x0800010), \
12232 X(vorr, 0x0200110, N_INV, 0x0800010), \
12233 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12234 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12235 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12236 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12237 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12238 X(vst1, 0x0000000, 0x0800000, N_INV), \
12239 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12240 X(vst2, 0x0000100, 0x0800100, N_INV), \
12241 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12242 X(vst3, 0x0000200, 0x0800200, N_INV), \
12243 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12244 X(vst4, 0x0000300, 0x0800300, N_INV), \
12245 X(vmovn, 0x1b20200, N_INV, N_INV), \
12246 X(vtrn, 0x1b20080, N_INV, N_INV), \
12247 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12248 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12249 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12250 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12251 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12252 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12253 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12254 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12255 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12256 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12257 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12261 #define X(OPC,I,F,S) N_MNEM_##OPC
12266 static const struct neon_tab_entry neon_enc_tab[] =
12268 #define X(OPC,I,F,S) { (I), (F), (S) }
12273 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12274 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12275 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12276 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12277 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12278 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12279 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12280 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12281 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12282 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12283 #define NEON_ENC_SINGLE_(X) \
12284 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12285 #define NEON_ENC_DOUBLE_(X) \
12286 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12288 #define NEON_ENCODE(type, inst) \
12291 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12292 inst.is_neon = 1; \
12296 #define check_neon_suffixes \
12299 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12301 as_bad (_("invalid neon suffix for non neon instruction")); \
12307 /* Define shapes for instruction operands. The following mnemonic characters
12308 are used in this table:
12310 F - VFP S<n> register
12311 D - Neon D<n> register
12312 Q - Neon Q<n> register
12316 L - D<n> register list
12318 This table is used to generate various data:
12319 - enumerations of the form NS_DDR to be used as arguments to
12321 - a table classifying shapes into single, double, quad, mixed.
12322 - a table used to drive neon_select_shape. */
12324 #define NEON_SHAPE_DEF \
12325 X(3, (D, D, D), DOUBLE), \
12326 X(3, (Q, Q, Q), QUAD), \
12327 X(3, (D, D, I), DOUBLE), \
12328 X(3, (Q, Q, I), QUAD), \
12329 X(3, (D, D, S), DOUBLE), \
12330 X(3, (Q, Q, S), QUAD), \
12331 X(2, (D, D), DOUBLE), \
12332 X(2, (Q, Q), QUAD), \
12333 X(2, (D, S), DOUBLE), \
12334 X(2, (Q, S), QUAD), \
12335 X(2, (D, R), DOUBLE), \
12336 X(2, (Q, R), QUAD), \
12337 X(2, (D, I), DOUBLE), \
12338 X(2, (Q, I), QUAD), \
12339 X(3, (D, L, D), DOUBLE), \
12340 X(2, (D, Q), MIXED), \
12341 X(2, (Q, D), MIXED), \
12342 X(3, (D, Q, I), MIXED), \
12343 X(3, (Q, D, I), MIXED), \
12344 X(3, (Q, D, D), MIXED), \
12345 X(3, (D, Q, Q), MIXED), \
12346 X(3, (Q, Q, D), MIXED), \
12347 X(3, (Q, D, S), MIXED), \
12348 X(3, (D, Q, S), MIXED), \
12349 X(4, (D, D, D, I), DOUBLE), \
12350 X(4, (Q, Q, Q, I), QUAD), \
12351 X(2, (F, F), SINGLE), \
12352 X(3, (F, F, F), SINGLE), \
12353 X(2, (F, I), SINGLE), \
12354 X(2, (F, D), MIXED), \
12355 X(2, (D, F), MIXED), \
12356 X(3, (F, F, I), MIXED), \
12357 X(4, (R, R, F, F), SINGLE), \
12358 X(4, (F, F, R, R), SINGLE), \
12359 X(3, (D, R, R), DOUBLE), \
12360 X(3, (R, R, D), DOUBLE), \
12361 X(2, (S, R), SINGLE), \
12362 X(2, (R, S), SINGLE), \
12363 X(2, (F, R), SINGLE), \
12364 X(2, (R, F), SINGLE)
12366 #define S2(A,B) NS_##A##B
12367 #define S3(A,B,C) NS_##A##B##C
12368 #define S4(A,B,C,D) NS_##A##B##C##D
12370 #define X(N, L, C) S##N L
12383 enum neon_shape_class
12391 #define X(N, L, C) SC_##C
12393 static enum neon_shape_class neon_shape_class[] =
12411 /* Register widths of above. */
12412 static unsigned neon_shape_el_size[] =
12423 struct neon_shape_info
12426 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12429 #define S2(A,B) { SE_##A, SE_##B }
12430 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12431 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12433 #define X(N, L, C) { N, S##N L }
12435 static struct neon_shape_info neon_shape_tab[] =
12445 /* Bit masks used in type checking given instructions.
12446 'N_EQK' means the type must be the same as (or based on in some way) the key
12447 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12448 set, various other bits can be set as well in order to modify the meaning of
12449 the type constraint. */
12451 enum neon_type_mask
12474 N_KEY = 0x1000000, /* Key element (main type specifier). */
12475 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12476 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12477 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12478 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12479 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12480 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12481 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12482 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12483 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12485 N_MAX_NONSPECIAL = N_F64
12488 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12490 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12491 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12492 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12493 #define N_SUF_32 (N_SU_32 | N_F32)
12494 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12495 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12497 /* Pass this as the first type argument to neon_check_type to ignore types
12499 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12501 /* Select a "shape" for the current instruction (describing register types or
12502 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12503 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12504 function of operand parsing, so this function doesn't need to be called.
12505 Shapes should be listed in order of decreasing length. */
12507 static enum neon_shape
12508 neon_select_shape (enum neon_shape shape, ...)
12511 enum neon_shape first_shape = shape;
12513 /* Fix missing optional operands. FIXME: we don't know at this point how
12514 many arguments we should have, so this makes the assumption that we have
12515 > 1. This is true of all current Neon opcodes, I think, but may not be
12516 true in the future. */
12517 if (!inst.operands[1].present)
12518 inst.operands[1] = inst.operands[0];
12520 va_start (ap, shape);
12522 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12527 for (j = 0; j < neon_shape_tab[shape].els; j++)
12529 if (!inst.operands[j].present)
12535 switch (neon_shape_tab[shape].el[j])
12538 if (!(inst.operands[j].isreg
12539 && inst.operands[j].isvec
12540 && inst.operands[j].issingle
12541 && !inst.operands[j].isquad))
12546 if (!(inst.operands[j].isreg
12547 && inst.operands[j].isvec
12548 && !inst.operands[j].isquad
12549 && !inst.operands[j].issingle))
12554 if (!(inst.operands[j].isreg
12555 && !inst.operands[j].isvec))
12560 if (!(inst.operands[j].isreg
12561 && inst.operands[j].isvec
12562 && inst.operands[j].isquad
12563 && !inst.operands[j].issingle))
12568 if (!(!inst.operands[j].isreg
12569 && !inst.operands[j].isscalar))
12574 if (!(!inst.operands[j].isreg
12575 && inst.operands[j].isscalar))
12585 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12586 /* We've matched all the entries in the shape table, and we don't
12587 have any left over operands which have not been matched. */
12593 if (shape == NS_NULL && first_shape != NS_NULL)
12594 first_error (_("invalid instruction shape"));
12599 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12600 means the Q bit should be set). */
12603 neon_quad (enum neon_shape shape)
12605 return neon_shape_class[shape] == SC_QUAD;
12609 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12612 /* Allow modification to be made to types which are constrained to be
12613 based on the key element, based on bits set alongside N_EQK. */
12614 if ((typebits & N_EQK) != 0)
12616 if ((typebits & N_HLF) != 0)
12618 else if ((typebits & N_DBL) != 0)
12620 if ((typebits & N_SGN) != 0)
12621 *g_type = NT_signed;
12622 else if ((typebits & N_UNS) != 0)
12623 *g_type = NT_unsigned;
12624 else if ((typebits & N_INT) != 0)
12625 *g_type = NT_integer;
12626 else if ((typebits & N_FLT) != 0)
12627 *g_type = NT_float;
12628 else if ((typebits & N_SIZ) != 0)
12629 *g_type = NT_untyped;
12633 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12634 operand type, i.e. the single type specified in a Neon instruction when it
12635 is the only one given. */
12637 static struct neon_type_el
12638 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12640 struct neon_type_el dest = *key;
12642 gas_assert ((thisarg & N_EQK) != 0);
12644 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12649 /* Convert Neon type and size into compact bitmask representation. */
12651 static enum neon_type_mask
12652 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12659 case 8: return N_8;
12660 case 16: return N_16;
12661 case 32: return N_32;
12662 case 64: return N_64;
12670 case 8: return N_I8;
12671 case 16: return N_I16;
12672 case 32: return N_I32;
12673 case 64: return N_I64;
12681 case 16: return N_F16;
12682 case 32: return N_F32;
12683 case 64: return N_F64;
12691 case 8: return N_P8;
12692 case 16: return N_P16;
12700 case 8: return N_S8;
12701 case 16: return N_S16;
12702 case 32: return N_S32;
12703 case 64: return N_S64;
12711 case 8: return N_U8;
12712 case 16: return N_U16;
12713 case 32: return N_U32;
12714 case 64: return N_U64;
12725 /* Convert compact Neon bitmask type representation to a type and size. Only
12726 handles the case where a single bit is set in the mask. */
12729 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12730 enum neon_type_mask mask)
12732 if ((mask & N_EQK) != 0)
12735 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12737 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12739 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12741 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12746 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12748 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12749 *type = NT_unsigned;
12750 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12751 *type = NT_integer;
12752 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12753 *type = NT_untyped;
12754 else if ((mask & (N_P8 | N_P16)) != 0)
12756 else if ((mask & (N_F32 | N_F64)) != 0)
12764 /* Modify a bitmask of allowed types. This is only needed for type
12768 modify_types_allowed (unsigned allowed, unsigned mods)
12771 enum neon_el_type type;
12777 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12779 if (el_type_of_type_chk (&type, &size,
12780 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12782 neon_modify_type_size (mods, &type, &size);
12783 destmask |= type_chk_of_el_type (type, size);
12790 /* Check type and return type classification.
12791 The manual states (paraphrase): If one datatype is given, it indicates the
12793 - the second operand, if there is one
12794 - the operand, if there is no second operand
12795 - the result, if there are no operands.
12796 This isn't quite good enough though, so we use a concept of a "key" datatype
12797 which is set on a per-instruction basis, which is the one which matters when
12798 only one data type is written.
12799 Note: this function has side-effects (e.g. filling in missing operands). All
12800 Neon instructions should call it before performing bit encoding. */
12802 static struct neon_type_el
12803 neon_check_type (unsigned els, enum neon_shape ns, ...)
12806 unsigned i, pass, key_el = 0;
12807 unsigned types[NEON_MAX_TYPE_ELS];
12808 enum neon_el_type k_type = NT_invtype;
12809 unsigned k_size = -1u;
12810 struct neon_type_el badtype = {NT_invtype, -1};
12811 unsigned key_allowed = 0;
12813 /* Optional registers in Neon instructions are always (not) in operand 1.
12814 Fill in the missing operand here, if it was omitted. */
12815 if (els > 1 && !inst.operands[1].present)
12816 inst.operands[1] = inst.operands[0];
12818 /* Suck up all the varargs. */
12820 for (i = 0; i < els; i++)
12822 unsigned thisarg = va_arg (ap, unsigned);
12823 if (thisarg == N_IGNORE_TYPE)
12828 types[i] = thisarg;
12829 if ((thisarg & N_KEY) != 0)
12834 if (inst.vectype.elems > 0)
12835 for (i = 0; i < els; i++)
12836 if (inst.operands[i].vectype.type != NT_invtype)
12838 first_error (_("types specified in both the mnemonic and operands"));
12842 /* Duplicate inst.vectype elements here as necessary.
12843 FIXME: No idea if this is exactly the same as the ARM assembler,
12844 particularly when an insn takes one register and one non-register
12846 if (inst.vectype.elems == 1 && els > 1)
12849 inst.vectype.elems = els;
12850 inst.vectype.el[key_el] = inst.vectype.el[0];
12851 for (j = 0; j < els; j++)
12853 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12856 else if (inst.vectype.elems == 0 && els > 0)
12859 /* No types were given after the mnemonic, so look for types specified
12860 after each operand. We allow some flexibility here; as long as the
12861 "key" operand has a type, we can infer the others. */
12862 for (j = 0; j < els; j++)
12863 if (inst.operands[j].vectype.type != NT_invtype)
12864 inst.vectype.el[j] = inst.operands[j].vectype;
12866 if (inst.operands[key_el].vectype.type != NT_invtype)
12868 for (j = 0; j < els; j++)
12869 if (inst.operands[j].vectype.type == NT_invtype)
12870 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12875 first_error (_("operand types can't be inferred"));
12879 else if (inst.vectype.elems != els)
12881 first_error (_("type specifier has the wrong number of parts"));
12885 for (pass = 0; pass < 2; pass++)
12887 for (i = 0; i < els; i++)
12889 unsigned thisarg = types[i];
12890 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12891 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12892 enum neon_el_type g_type = inst.vectype.el[i].type;
12893 unsigned g_size = inst.vectype.el[i].size;
12895 /* Decay more-specific signed & unsigned types to sign-insensitive
12896 integer types if sign-specific variants are unavailable. */
12897 if ((g_type == NT_signed || g_type == NT_unsigned)
12898 && (types_allowed & N_SU_ALL) == 0)
12899 g_type = NT_integer;
12901 /* If only untyped args are allowed, decay any more specific types to
12902 them. Some instructions only care about signs for some element
12903 sizes, so handle that properly. */
12904 if ((g_size == 8 && (types_allowed & N_8) != 0)
12905 || (g_size == 16 && (types_allowed & N_16) != 0)
12906 || (g_size == 32 && (types_allowed & N_32) != 0)
12907 || (g_size == 64 && (types_allowed & N_64) != 0))
12908 g_type = NT_untyped;
12912 if ((thisarg & N_KEY) != 0)
12916 key_allowed = thisarg & ~N_KEY;
12921 if ((thisarg & N_VFP) != 0)
12923 enum neon_shape_el regshape;
12924 unsigned regwidth, match;
12926 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12929 first_error (_("invalid instruction shape"));
12932 regshape = neon_shape_tab[ns].el[i];
12933 regwidth = neon_shape_el_size[regshape];
12935 /* In VFP mode, operands must match register widths. If we
12936 have a key operand, use its width, else use the width of
12937 the current operand. */
12943 if (regwidth != match)
12945 first_error (_("operand size must match register width"));
12950 if ((thisarg & N_EQK) == 0)
12952 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12954 if ((given_type & types_allowed) == 0)
12956 first_error (_("bad type in Neon instruction"));
12962 enum neon_el_type mod_k_type = k_type;
12963 unsigned mod_k_size = k_size;
12964 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12965 if (g_type != mod_k_type || g_size != mod_k_size)
12967 first_error (_("inconsistent types in Neon instruction"));
12975 return inst.vectype.el[key_el];
12978 /* Neon-style VFP instruction forwarding. */
12980 /* Thumb VFP instructions have 0xE in the condition field. */
12983 do_vfp_cond_or_thumb (void)
12988 inst.instruction |= 0xe0000000;
12990 inst.instruction |= inst.cond << 28;
12993 /* Look up and encode a simple mnemonic, for use as a helper function for the
12994 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12995 etc. It is assumed that operand parsing has already been done, and that the
12996 operands are in the form expected by the given opcode (this isn't necessarily
12997 the same as the form in which they were parsed, hence some massaging must
12998 take place before this function is called).
12999 Checks current arch version against that in the looked-up opcode. */
13002 do_vfp_nsyn_opcode (const char *opname)
13004 const struct asm_opcode *opcode;
13006 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13012 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13019 inst.instruction = opcode->tvalue;
13020 opcode->tencode ();
13024 inst.instruction = (inst.cond << 28) | opcode->avalue;
13025 opcode->aencode ();
13030 do_vfp_nsyn_add_sub (enum neon_shape rs)
13032 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13037 do_vfp_nsyn_opcode ("fadds");
13039 do_vfp_nsyn_opcode ("fsubs");
13044 do_vfp_nsyn_opcode ("faddd");
13046 do_vfp_nsyn_opcode ("fsubd");
13050 /* Check operand types to see if this is a VFP instruction, and if so call
13054 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13056 enum neon_shape rs;
13057 struct neon_type_el et;
13062 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13063 et = neon_check_type (2, rs,
13064 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13068 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13069 et = neon_check_type (3, rs,
13070 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13077 if (et.type != NT_invtype)
13088 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13090 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13095 do_vfp_nsyn_opcode ("fmacs");
13097 do_vfp_nsyn_opcode ("fnmacs");
13102 do_vfp_nsyn_opcode ("fmacd");
13104 do_vfp_nsyn_opcode ("fnmacd");
13109 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13111 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13116 do_vfp_nsyn_opcode ("ffmas");
13118 do_vfp_nsyn_opcode ("ffnmas");
13123 do_vfp_nsyn_opcode ("ffmad");
13125 do_vfp_nsyn_opcode ("ffnmad");
13130 do_vfp_nsyn_mul (enum neon_shape rs)
13133 do_vfp_nsyn_opcode ("fmuls");
13135 do_vfp_nsyn_opcode ("fmuld");
13139 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13141 int is_neg = (inst.instruction & 0x80) != 0;
13142 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13147 do_vfp_nsyn_opcode ("fnegs");
13149 do_vfp_nsyn_opcode ("fabss");
13154 do_vfp_nsyn_opcode ("fnegd");
13156 do_vfp_nsyn_opcode ("fabsd");
13160 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13161 insns belong to Neon, and are handled elsewhere. */
13164 do_vfp_nsyn_ldm_stm (int is_dbmode)
13166 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13170 do_vfp_nsyn_opcode ("fldmdbs");
13172 do_vfp_nsyn_opcode ("fldmias");
13177 do_vfp_nsyn_opcode ("fstmdbs");
13179 do_vfp_nsyn_opcode ("fstmias");
13184 do_vfp_nsyn_sqrt (void)
13186 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13187 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13190 do_vfp_nsyn_opcode ("fsqrts");
13192 do_vfp_nsyn_opcode ("fsqrtd");
13196 do_vfp_nsyn_div (void)
13198 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13199 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13200 N_F32 | N_F64 | N_KEY | N_VFP);
13203 do_vfp_nsyn_opcode ("fdivs");
13205 do_vfp_nsyn_opcode ("fdivd");
13209 do_vfp_nsyn_nmul (void)
13211 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13212 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13213 N_F32 | N_F64 | N_KEY | N_VFP);
13217 NEON_ENCODE (SINGLE, inst);
13218 do_vfp_sp_dyadic ();
13222 NEON_ENCODE (DOUBLE, inst);
13223 do_vfp_dp_rd_rn_rm ();
13225 do_vfp_cond_or_thumb ();
13229 do_vfp_nsyn_cmp (void)
13231 if (inst.operands[1].isreg)
13233 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13234 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13238 NEON_ENCODE (SINGLE, inst);
13239 do_vfp_sp_monadic ();
13243 NEON_ENCODE (DOUBLE, inst);
13244 do_vfp_dp_rd_rm ();
13249 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13250 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13252 switch (inst.instruction & 0x0fffffff)
13255 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13258 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13266 NEON_ENCODE (SINGLE, inst);
13267 do_vfp_sp_compare_z ();
13271 NEON_ENCODE (DOUBLE, inst);
13275 do_vfp_cond_or_thumb ();
13279 nsyn_insert_sp (void)
13281 inst.operands[1] = inst.operands[0];
13282 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13283 inst.operands[0].reg = REG_SP;
13284 inst.operands[0].isreg = 1;
13285 inst.operands[0].writeback = 1;
13286 inst.operands[0].present = 1;
13290 do_vfp_nsyn_push (void)
13293 if (inst.operands[1].issingle)
13294 do_vfp_nsyn_opcode ("fstmdbs");
13296 do_vfp_nsyn_opcode ("fstmdbd");
13300 do_vfp_nsyn_pop (void)
13303 if (inst.operands[1].issingle)
13304 do_vfp_nsyn_opcode ("fldmias");
13306 do_vfp_nsyn_opcode ("fldmiad");
13309 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13310 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13313 neon_dp_fixup (struct arm_it* insn)
13315 unsigned int i = insn->instruction;
13320 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13331 insn->instruction = i;
13334 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13338 neon_logbits (unsigned x)
13340 return ffs (x) - 4;
13343 #define LOW4(R) ((R) & 0xf)
13344 #define HI1(R) (((R) >> 4) & 1)
13346 /* Encode insns with bit pattern:
13348 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13349 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13351 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13352 different meaning for some instruction. */
13355 neon_three_same (int isquad, int ubit, int size)
13357 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13358 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13359 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13360 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13361 inst.instruction |= LOW4 (inst.operands[2].reg);
13362 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13363 inst.instruction |= (isquad != 0) << 6;
13364 inst.instruction |= (ubit != 0) << 24;
13366 inst.instruction |= neon_logbits (size) << 20;
13368 neon_dp_fixup (&inst);
13371 /* Encode instructions of the form:
13373 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13374 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13376 Don't write size if SIZE == -1. */
13379 neon_two_same (int qbit, int ubit, int size)
13381 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13382 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13383 inst.instruction |= LOW4 (inst.operands[1].reg);
13384 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13385 inst.instruction |= (qbit != 0) << 6;
13386 inst.instruction |= (ubit != 0) << 24;
13389 inst.instruction |= neon_logbits (size) << 18;
13391 neon_dp_fixup (&inst);
13394 /* Neon instruction encoders, in approximate order of appearance. */
13397 do_neon_dyadic_i_su (void)
13399 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13400 struct neon_type_el et = neon_check_type (3, rs,
13401 N_EQK, N_EQK, N_SU_32 | N_KEY);
13402 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13406 do_neon_dyadic_i64_su (void)
13408 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13409 struct neon_type_el et = neon_check_type (3, rs,
13410 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13411 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13415 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13418 unsigned size = et.size >> 3;
13419 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13420 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13421 inst.instruction |= LOW4 (inst.operands[1].reg);
13422 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13423 inst.instruction |= (isquad != 0) << 6;
13424 inst.instruction |= immbits << 16;
13425 inst.instruction |= (size >> 3) << 7;
13426 inst.instruction |= (size & 0x7) << 19;
13428 inst.instruction |= (uval != 0) << 24;
13430 neon_dp_fixup (&inst);
13434 do_neon_shl_imm (void)
13436 if (!inst.operands[2].isreg)
13438 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13439 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13440 NEON_ENCODE (IMMED, inst);
13441 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13445 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13446 struct neon_type_el et = neon_check_type (3, rs,
13447 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13450 /* VSHL/VQSHL 3-register variants have syntax such as:
13452 whereas other 3-register operations encoded by neon_three_same have
13455 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13457 tmp = inst.operands[2].reg;
13458 inst.operands[2].reg = inst.operands[1].reg;
13459 inst.operands[1].reg = tmp;
13460 NEON_ENCODE (INTEGER, inst);
13461 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13466 do_neon_qshl_imm (void)
13468 if (!inst.operands[2].isreg)
13470 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13471 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13473 NEON_ENCODE (IMMED, inst);
13474 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13475 inst.operands[2].imm);
13479 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13480 struct neon_type_el et = neon_check_type (3, rs,
13481 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13484 /* See note in do_neon_shl_imm. */
13485 tmp = inst.operands[2].reg;
13486 inst.operands[2].reg = inst.operands[1].reg;
13487 inst.operands[1].reg = tmp;
13488 NEON_ENCODE (INTEGER, inst);
13489 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13494 do_neon_rshl (void)
13496 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13497 struct neon_type_el et = neon_check_type (3, rs,
13498 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13501 tmp = inst.operands[2].reg;
13502 inst.operands[2].reg = inst.operands[1].reg;
13503 inst.operands[1].reg = tmp;
13504 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13508 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13510 /* Handle .I8 pseudo-instructions. */
13513 /* Unfortunately, this will make everything apart from zero out-of-range.
13514 FIXME is this the intended semantics? There doesn't seem much point in
13515 accepting .I8 if so. */
13516 immediate |= immediate << 8;
13522 if (immediate == (immediate & 0x000000ff))
13524 *immbits = immediate;
13527 else if (immediate == (immediate & 0x0000ff00))
13529 *immbits = immediate >> 8;
13532 else if (immediate == (immediate & 0x00ff0000))
13534 *immbits = immediate >> 16;
13537 else if (immediate == (immediate & 0xff000000))
13539 *immbits = immediate >> 24;
13542 if ((immediate & 0xffff) != (immediate >> 16))
13543 goto bad_immediate;
13544 immediate &= 0xffff;
13547 if (immediate == (immediate & 0x000000ff))
13549 *immbits = immediate;
13552 else if (immediate == (immediate & 0x0000ff00))
13554 *immbits = immediate >> 8;
13559 first_error (_("immediate value out of range"));
13563 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13567 neon_bits_same_in_bytes (unsigned imm)
13569 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13570 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13571 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13572 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13575 /* For immediate of above form, return 0bABCD. */
13578 neon_squash_bits (unsigned imm)
13580 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13581 | ((imm & 0x01000000) >> 21);
13584 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13587 neon_qfloat_bits (unsigned imm)
13589 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13592 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13593 the instruction. *OP is passed as the initial value of the op field, and
13594 may be set to a different value depending on the constant (i.e.
13595 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13596 MVN). If the immediate looks like a repeated pattern then also
13597 try smaller element sizes. */
13600 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13601 unsigned *immbits, int *op, int size,
13602 enum neon_el_type type)
13604 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13606 if (type == NT_float && !float_p)
13609 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13611 if (size != 32 || *op == 1)
13613 *immbits = neon_qfloat_bits (immlo);
13619 if (neon_bits_same_in_bytes (immhi)
13620 && neon_bits_same_in_bytes (immlo))
13624 *immbits = (neon_squash_bits (immhi) << 4)
13625 | neon_squash_bits (immlo);
13630 if (immhi != immlo)
13636 if (immlo == (immlo & 0x000000ff))
13641 else if (immlo == (immlo & 0x0000ff00))
13643 *immbits = immlo >> 8;
13646 else if (immlo == (immlo & 0x00ff0000))
13648 *immbits = immlo >> 16;
13651 else if (immlo == (immlo & 0xff000000))
13653 *immbits = immlo >> 24;
13656 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13658 *immbits = (immlo >> 8) & 0xff;
13661 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13663 *immbits = (immlo >> 16) & 0xff;
13667 if ((immlo & 0xffff) != (immlo >> 16))
13674 if (immlo == (immlo & 0x000000ff))
13679 else if (immlo == (immlo & 0x0000ff00))
13681 *immbits = immlo >> 8;
13685 if ((immlo & 0xff) != (immlo >> 8))
13690 if (immlo == (immlo & 0x000000ff))
13692 /* Don't allow MVN with 8-bit immediate. */
13702 /* Write immediate bits [7:0] to the following locations:
13704 |28/24|23 19|18 16|15 4|3 0|
13705 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13707 This function is used by VMOV/VMVN/VORR/VBIC. */
13710 neon_write_immbits (unsigned immbits)
13712 inst.instruction |= immbits & 0xf;
13713 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13714 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13717 /* Invert low-order SIZE bits of XHI:XLO. */
13720 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13722 unsigned immlo = xlo ? *xlo : 0;
13723 unsigned immhi = xhi ? *xhi : 0;
13728 immlo = (~immlo) & 0xff;
13732 immlo = (~immlo) & 0xffff;
13736 immhi = (~immhi) & 0xffffffff;
13737 /* fall through. */
13740 immlo = (~immlo) & 0xffffffff;
13755 do_neon_logic (void)
13757 if (inst.operands[2].present && inst.operands[2].isreg)
13759 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13760 neon_check_type (3, rs, N_IGNORE_TYPE);
13761 /* U bit and size field were set as part of the bitmask. */
13762 NEON_ENCODE (INTEGER, inst);
13763 neon_three_same (neon_quad (rs), 0, -1);
13767 const int three_ops_form = (inst.operands[2].present
13768 && !inst.operands[2].isreg);
13769 const int immoperand = (three_ops_form ? 2 : 1);
13770 enum neon_shape rs = (three_ops_form
13771 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13772 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13773 struct neon_type_el et = neon_check_type (2, rs,
13774 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13775 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13779 if (et.type == NT_invtype)
13782 if (three_ops_form)
13783 constraint (inst.operands[0].reg != inst.operands[1].reg,
13784 _("first and second operands shall be the same register"));
13786 NEON_ENCODE (IMMED, inst);
13788 immbits = inst.operands[immoperand].imm;
13791 /* .i64 is a pseudo-op, so the immediate must be a repeating
13793 if (immbits != (inst.operands[immoperand].regisimm ?
13794 inst.operands[immoperand].reg : 0))
13796 /* Set immbits to an invalid constant. */
13797 immbits = 0xdeadbeef;
13804 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13808 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13812 /* Pseudo-instruction for VBIC. */
13813 neon_invert_size (&immbits, 0, et.size);
13814 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13818 /* Pseudo-instruction for VORR. */
13819 neon_invert_size (&immbits, 0, et.size);
13820 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13830 inst.instruction |= neon_quad (rs) << 6;
13831 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13832 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13833 inst.instruction |= cmode << 8;
13834 neon_write_immbits (immbits);
13836 neon_dp_fixup (&inst);
13841 do_neon_bitfield (void)
13843 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13844 neon_check_type (3, rs, N_IGNORE_TYPE);
13845 neon_three_same (neon_quad (rs), 0, -1);
13849 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13852 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13853 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13855 if (et.type == NT_float)
13857 NEON_ENCODE (FLOAT, inst);
13858 neon_three_same (neon_quad (rs), 0, -1);
13862 NEON_ENCODE (INTEGER, inst);
13863 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13868 do_neon_dyadic_if_su (void)
13870 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13874 do_neon_dyadic_if_su_d (void)
13876 /* This version only allow D registers, but that constraint is enforced during
13877 operand parsing so we don't need to do anything extra here. */
13878 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13882 do_neon_dyadic_if_i_d (void)
13884 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13885 affected if we specify unsigned args. */
13886 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13889 enum vfp_or_neon_is_neon_bits
13892 NEON_CHECK_ARCH = 2
13895 /* Call this function if an instruction which may have belonged to the VFP or
13896 Neon instruction sets, but turned out to be a Neon instruction (due to the
13897 operand types involved, etc.). We have to check and/or fix-up a couple of
13900 - Make sure the user hasn't attempted to make a Neon instruction
13902 - Alter the value in the condition code field if necessary.
13903 - Make sure that the arch supports Neon instructions.
13905 Which of these operations take place depends on bits from enum
13906 vfp_or_neon_is_neon_bits.
13908 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13909 current instruction's condition is COND_ALWAYS, the condition field is
13910 changed to inst.uncond_value. This is necessary because instructions shared
13911 between VFP and Neon may be conditional for the VFP variants only, and the
13912 unconditional Neon version must have, e.g., 0xF in the condition field. */
13915 vfp_or_neon_is_neon (unsigned check)
13917 /* Conditions are always legal in Thumb mode (IT blocks). */
13918 if (!thumb_mode && (check & NEON_CHECK_CC))
13920 if (inst.cond != COND_ALWAYS)
13922 first_error (_(BAD_COND));
13925 if (inst.uncond_value != -1)
13926 inst.instruction |= inst.uncond_value << 28;
13929 if ((check & NEON_CHECK_ARCH)
13930 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13932 first_error (_(BAD_FPU));
13940 do_neon_addsub_if_i (void)
13942 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13945 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13948 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13949 affected if we specify unsigned args. */
13950 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13953 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13955 V<op> A,B (A is operand 0, B is operand 2)
13960 so handle that case specially. */
13963 neon_exchange_operands (void)
13965 void *scratch = alloca (sizeof (inst.operands[0]));
13966 if (inst.operands[1].present)
13968 /* Swap operands[1] and operands[2]. */
13969 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13970 inst.operands[1] = inst.operands[2];
13971 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13975 inst.operands[1] = inst.operands[2];
13976 inst.operands[2] = inst.operands[0];
13981 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13983 if (inst.operands[2].isreg)
13986 neon_exchange_operands ();
13987 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13991 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13992 struct neon_type_el et = neon_check_type (2, rs,
13993 N_EQK | N_SIZ, immtypes | N_KEY);
13995 NEON_ENCODE (IMMED, inst);
13996 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13997 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13998 inst.instruction |= LOW4 (inst.operands[1].reg);
13999 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14000 inst.instruction |= neon_quad (rs) << 6;
14001 inst.instruction |= (et.type == NT_float) << 10;
14002 inst.instruction |= neon_logbits (et.size) << 18;
14004 neon_dp_fixup (&inst);
14011 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14015 do_neon_cmp_inv (void)
14017 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14023 neon_compare (N_IF_32, N_IF_32, FALSE);
14026 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14027 scalars, which are encoded in 5 bits, M : Rm.
14028 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14029 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14033 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14035 unsigned regno = NEON_SCALAR_REG (scalar);
14036 unsigned elno = NEON_SCALAR_INDEX (scalar);
14041 if (regno > 7 || elno > 3)
14043 return regno | (elno << 3);
14046 if (regno > 15 || elno > 1)
14048 return regno | (elno << 4);
14052 first_error (_("scalar out of range for multiply instruction"));
14058 /* Encode multiply / multiply-accumulate scalar instructions. */
14061 neon_mul_mac (struct neon_type_el et, int ubit)
14065 /* Give a more helpful error message if we have an invalid type. */
14066 if (et.type == NT_invtype)
14069 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14070 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14071 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14072 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14073 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14074 inst.instruction |= LOW4 (scalar);
14075 inst.instruction |= HI1 (scalar) << 5;
14076 inst.instruction |= (et.type == NT_float) << 8;
14077 inst.instruction |= neon_logbits (et.size) << 20;
14078 inst.instruction |= (ubit != 0) << 24;
14080 neon_dp_fixup (&inst);
14084 do_neon_mac_maybe_scalar (void)
14086 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14089 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14092 if (inst.operands[2].isscalar)
14094 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14095 struct neon_type_el et = neon_check_type (3, rs,
14096 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14097 NEON_ENCODE (SCALAR, inst);
14098 neon_mul_mac (et, neon_quad (rs));
14102 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14103 affected if we specify unsigned args. */
14104 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14109 do_neon_fmac (void)
14111 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14114 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14117 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14123 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14124 struct neon_type_el et = neon_check_type (3, rs,
14125 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14126 neon_three_same (neon_quad (rs), 0, et.size);
14129 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14130 same types as the MAC equivalents. The polynomial type for this instruction
14131 is encoded the same as the integer type. */
14136 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14139 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14142 if (inst.operands[2].isscalar)
14143 do_neon_mac_maybe_scalar ();
14145 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14149 do_neon_qdmulh (void)
14151 if (inst.operands[2].isscalar)
14153 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14154 struct neon_type_el et = neon_check_type (3, rs,
14155 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14156 NEON_ENCODE (SCALAR, inst);
14157 neon_mul_mac (et, neon_quad (rs));
14161 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14162 struct neon_type_el et = neon_check_type (3, rs,
14163 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14164 NEON_ENCODE (INTEGER, inst);
14165 /* The U bit (rounding) comes from bit mask. */
14166 neon_three_same (neon_quad (rs), 0, et.size);
14171 do_neon_fcmp_absolute (void)
14173 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14174 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14175 /* Size field comes from bit mask. */
14176 neon_three_same (neon_quad (rs), 1, -1);
14180 do_neon_fcmp_absolute_inv (void)
14182 neon_exchange_operands ();
14183 do_neon_fcmp_absolute ();
14187 do_neon_step (void)
14189 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14190 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14191 neon_three_same (neon_quad (rs), 0, -1);
14195 do_neon_abs_neg (void)
14197 enum neon_shape rs;
14198 struct neon_type_el et;
14200 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14203 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14206 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14207 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14209 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14210 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14211 inst.instruction |= LOW4 (inst.operands[1].reg);
14212 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14213 inst.instruction |= neon_quad (rs) << 6;
14214 inst.instruction |= (et.type == NT_float) << 10;
14215 inst.instruction |= neon_logbits (et.size) << 18;
14217 neon_dp_fixup (&inst);
14223 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14224 struct neon_type_el et = neon_check_type (2, rs,
14225 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14226 int imm = inst.operands[2].imm;
14227 constraint (imm < 0 || (unsigned)imm >= et.size,
14228 _("immediate out of range for insert"));
14229 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14235 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14236 struct neon_type_el et = neon_check_type (2, rs,
14237 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14238 int imm = inst.operands[2].imm;
14239 constraint (imm < 1 || (unsigned)imm > et.size,
14240 _("immediate out of range for insert"));
14241 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14245 do_neon_qshlu_imm (void)
14247 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14248 struct neon_type_el et = neon_check_type (2, rs,
14249 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14250 int imm = inst.operands[2].imm;
14251 constraint (imm < 0 || (unsigned)imm >= et.size,
14252 _("immediate out of range for shift"));
14253 /* Only encodes the 'U present' variant of the instruction.
14254 In this case, signed types have OP (bit 8) set to 0.
14255 Unsigned types have OP set to 1. */
14256 inst.instruction |= (et.type == NT_unsigned) << 8;
14257 /* The rest of the bits are the same as other immediate shifts. */
14258 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14262 do_neon_qmovn (void)
14264 struct neon_type_el et = neon_check_type (2, NS_DQ,
14265 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14266 /* Saturating move where operands can be signed or unsigned, and the
14267 destination has the same signedness. */
14268 NEON_ENCODE (INTEGER, inst);
14269 if (et.type == NT_unsigned)
14270 inst.instruction |= 0xc0;
14272 inst.instruction |= 0x80;
14273 neon_two_same (0, 1, et.size / 2);
14277 do_neon_qmovun (void)
14279 struct neon_type_el et = neon_check_type (2, NS_DQ,
14280 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14281 /* Saturating move with unsigned results. Operands must be signed. */
14282 NEON_ENCODE (INTEGER, inst);
14283 neon_two_same (0, 1, et.size / 2);
14287 do_neon_rshift_sat_narrow (void)
14289 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14290 or unsigned. If operands are unsigned, results must also be unsigned. */
14291 struct neon_type_el et = neon_check_type (2, NS_DQI,
14292 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14293 int imm = inst.operands[2].imm;
14294 /* This gets the bounds check, size encoding and immediate bits calculation
14298 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14299 VQMOVN.I<size> <Dd>, <Qm>. */
14302 inst.operands[2].present = 0;
14303 inst.instruction = N_MNEM_vqmovn;
14308 constraint (imm < 1 || (unsigned)imm > et.size,
14309 _("immediate out of range"));
14310 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14314 do_neon_rshift_sat_narrow_u (void)
14316 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14317 or unsigned. If operands are unsigned, results must also be unsigned. */
14318 struct neon_type_el et = neon_check_type (2, NS_DQI,
14319 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14320 int imm = inst.operands[2].imm;
14321 /* This gets the bounds check, size encoding and immediate bits calculation
14325 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14326 VQMOVUN.I<size> <Dd>, <Qm>. */
14329 inst.operands[2].present = 0;
14330 inst.instruction = N_MNEM_vqmovun;
14335 constraint (imm < 1 || (unsigned)imm > et.size,
14336 _("immediate out of range"));
14337 /* FIXME: The manual is kind of unclear about what value U should have in
14338 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14340 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14344 do_neon_movn (void)
14346 struct neon_type_el et = neon_check_type (2, NS_DQ,
14347 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14348 NEON_ENCODE (INTEGER, inst);
14349 neon_two_same (0, 1, et.size / 2);
14353 do_neon_rshift_narrow (void)
14355 struct neon_type_el et = neon_check_type (2, NS_DQI,
14356 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14357 int imm = inst.operands[2].imm;
14358 /* This gets the bounds check, size encoding and immediate bits calculation
14362 /* If immediate is zero then we are a pseudo-instruction for
14363 VMOVN.I<size> <Dd>, <Qm> */
14366 inst.operands[2].present = 0;
14367 inst.instruction = N_MNEM_vmovn;
14372 constraint (imm < 1 || (unsigned)imm > et.size,
14373 _("immediate out of range for narrowing operation"));
14374 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14378 do_neon_shll (void)
14380 /* FIXME: Type checking when lengthening. */
14381 struct neon_type_el et = neon_check_type (2, NS_QDI,
14382 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14383 unsigned imm = inst.operands[2].imm;
14385 if (imm == et.size)
14387 /* Maximum shift variant. */
14388 NEON_ENCODE (INTEGER, inst);
14389 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14390 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14391 inst.instruction |= LOW4 (inst.operands[1].reg);
14392 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14393 inst.instruction |= neon_logbits (et.size) << 18;
14395 neon_dp_fixup (&inst);
14399 /* A more-specific type check for non-max versions. */
14400 et = neon_check_type (2, NS_QDI,
14401 N_EQK | N_DBL, N_SU_32 | N_KEY);
14402 NEON_ENCODE (IMMED, inst);
14403 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14407 /* Check the various types for the VCVT instruction, and return which version
14408 the current instruction is. */
14411 neon_cvt_flavour (enum neon_shape rs)
14413 #define CVT_VAR(C,X,Y) \
14414 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14415 if (et.type != NT_invtype) \
14417 inst.error = NULL; \
14420 struct neon_type_el et;
14421 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14422 || rs == NS_FF) ? N_VFP : 0;
14423 /* The instruction versions which take an immediate take one register
14424 argument, which is extended to the width of the full register. Thus the
14425 "source" and "destination" registers must have the same width. Hack that
14426 here by making the size equal to the key (wider, in this case) operand. */
14427 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14429 CVT_VAR (0, N_S32, N_F32);
14430 CVT_VAR (1, N_U32, N_F32);
14431 CVT_VAR (2, N_F32, N_S32);
14432 CVT_VAR (3, N_F32, N_U32);
14433 /* Half-precision conversions. */
14434 CVT_VAR (4, N_F32, N_F16);
14435 CVT_VAR (5, N_F16, N_F32);
14439 /* VFP instructions. */
14440 CVT_VAR (6, N_F32, N_F64);
14441 CVT_VAR (7, N_F64, N_F32);
14442 CVT_VAR (8, N_S32, N_F64 | key);
14443 CVT_VAR (9, N_U32, N_F64 | key);
14444 CVT_VAR (10, N_F64 | key, N_S32);
14445 CVT_VAR (11, N_F64 | key, N_U32);
14446 /* VFP instructions with bitshift. */
14447 CVT_VAR (12, N_F32 | key, N_S16);
14448 CVT_VAR (13, N_F32 | key, N_U16);
14449 CVT_VAR (14, N_F64 | key, N_S16);
14450 CVT_VAR (15, N_F64 | key, N_U16);
14451 CVT_VAR (16, N_S16, N_F32 | key);
14452 CVT_VAR (17, N_U16, N_F32 | key);
14453 CVT_VAR (18, N_S16, N_F64 | key);
14454 CVT_VAR (19, N_U16, N_F64 | key);
14460 /* Neon-syntax VFP conversions. */
14463 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14465 const char *opname = 0;
14467 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14469 /* Conversions with immediate bitshift. */
14470 const char *enc[] =
14494 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14496 opname = enc[flavour];
14497 constraint (inst.operands[0].reg != inst.operands[1].reg,
14498 _("operands 0 and 1 must be the same register"));
14499 inst.operands[1] = inst.operands[2];
14500 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14505 /* Conversions without bitshift. */
14506 const char *enc[] =
14522 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14523 opname = enc[flavour];
14527 do_vfp_nsyn_opcode (opname);
14531 do_vfp_nsyn_cvtz (void)
14533 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14534 int flavour = neon_cvt_flavour (rs);
14535 const char *enc[] =
14549 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14550 do_vfp_nsyn_opcode (enc[flavour]);
14554 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14556 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14557 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14558 int flavour = neon_cvt_flavour (rs);
14560 /* PR11109: Handle round-to-zero for VCVT conversions. */
14562 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14563 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14564 && (rs == NS_FD || rs == NS_FF))
14566 do_vfp_nsyn_cvtz ();
14570 /* VFP rather than Neon conversions. */
14573 do_vfp_nsyn_cvt (rs, flavour);
14583 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14585 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14588 /* Fixed-point conversion with #0 immediate is encoded as an
14589 integer conversion. */
14590 if (inst.operands[2].present && inst.operands[2].imm == 0)
14592 immbits = 32 - inst.operands[2].imm;
14593 NEON_ENCODE (IMMED, inst);
14595 inst.instruction |= enctab[flavour];
14596 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14597 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14598 inst.instruction |= LOW4 (inst.operands[1].reg);
14599 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14600 inst.instruction |= neon_quad (rs) << 6;
14601 inst.instruction |= 1 << 21;
14602 inst.instruction |= immbits << 16;
14604 neon_dp_fixup (&inst);
14612 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14614 NEON_ENCODE (INTEGER, inst);
14616 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14620 inst.instruction |= enctab[flavour];
14622 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14623 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14624 inst.instruction |= LOW4 (inst.operands[1].reg);
14625 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14626 inst.instruction |= neon_quad (rs) << 6;
14627 inst.instruction |= 2 << 18;
14629 neon_dp_fixup (&inst);
14633 /* Half-precision conversions for Advanced SIMD -- neon. */
14638 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14640 as_bad (_("operand size must match register width"));
14645 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14647 as_bad (_("operand size must match register width"));
14652 inst.instruction = 0x3b60600;
14654 inst.instruction = 0x3b60700;
14656 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14657 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14658 inst.instruction |= LOW4 (inst.operands[1].reg);
14659 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14660 neon_dp_fixup (&inst);
14664 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14665 do_vfp_nsyn_cvt (rs, flavour);
14670 do_neon_cvtr (void)
14672 do_neon_cvt_1 (FALSE);
14678 do_neon_cvt_1 (TRUE);
14682 do_neon_cvtb (void)
14684 inst.instruction = 0xeb20a40;
14686 /* The sizes are attached to the mnemonic. */
14687 if (inst.vectype.el[0].type != NT_invtype
14688 && inst.vectype.el[0].size == 16)
14689 inst.instruction |= 0x00010000;
14691 /* Programmer's syntax: the sizes are attached to the operands. */
14692 else if (inst.operands[0].vectype.type != NT_invtype
14693 && inst.operands[0].vectype.size == 16)
14694 inst.instruction |= 0x00010000;
14696 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14697 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14698 do_vfp_cond_or_thumb ();
14703 do_neon_cvtt (void)
14706 inst.instruction |= 0x80;
14710 neon_move_immediate (void)
14712 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14713 struct neon_type_el et = neon_check_type (2, rs,
14714 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14715 unsigned immlo, immhi = 0, immbits;
14716 int op, cmode, float_p;
14718 constraint (et.type == NT_invtype,
14719 _("operand size must be specified for immediate VMOV"));
14721 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14722 op = (inst.instruction & (1 << 5)) != 0;
14724 immlo = inst.operands[1].imm;
14725 if (inst.operands[1].regisimm)
14726 immhi = inst.operands[1].reg;
14728 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14729 _("immediate has bits set outside the operand size"));
14731 float_p = inst.operands[1].immisfloat;
14733 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14734 et.size, et.type)) == FAIL)
14736 /* Invert relevant bits only. */
14737 neon_invert_size (&immlo, &immhi, et.size);
14738 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14739 with one or the other; those cases are caught by
14740 neon_cmode_for_move_imm. */
14742 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14743 &op, et.size, et.type)) == FAIL)
14745 first_error (_("immediate out of range"));
14750 inst.instruction &= ~(1 << 5);
14751 inst.instruction |= op << 5;
14753 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14754 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14755 inst.instruction |= neon_quad (rs) << 6;
14756 inst.instruction |= cmode << 8;
14758 neon_write_immbits (immbits);
14764 if (inst.operands[1].isreg)
14766 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14768 NEON_ENCODE (INTEGER, inst);
14769 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14770 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14771 inst.instruction |= LOW4 (inst.operands[1].reg);
14772 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14773 inst.instruction |= neon_quad (rs) << 6;
14777 NEON_ENCODE (IMMED, inst);
14778 neon_move_immediate ();
14781 neon_dp_fixup (&inst);
14784 /* Encode instructions of form:
14786 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14787 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14790 neon_mixed_length (struct neon_type_el et, unsigned size)
14792 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14793 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14794 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14795 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14796 inst.instruction |= LOW4 (inst.operands[2].reg);
14797 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14798 inst.instruction |= (et.type == NT_unsigned) << 24;
14799 inst.instruction |= neon_logbits (size) << 20;
14801 neon_dp_fixup (&inst);
14805 do_neon_dyadic_long (void)
14807 /* FIXME: Type checking for lengthening op. */
14808 struct neon_type_el et = neon_check_type (3, NS_QDD,
14809 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14810 neon_mixed_length (et, et.size);
14814 do_neon_abal (void)
14816 struct neon_type_el et = neon_check_type (3, NS_QDD,
14817 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14818 neon_mixed_length (et, et.size);
14822 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14824 if (inst.operands[2].isscalar)
14826 struct neon_type_el et = neon_check_type (3, NS_QDS,
14827 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14828 NEON_ENCODE (SCALAR, inst);
14829 neon_mul_mac (et, et.type == NT_unsigned);
14833 struct neon_type_el et = neon_check_type (3, NS_QDD,
14834 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14835 NEON_ENCODE (INTEGER, inst);
14836 neon_mixed_length (et, et.size);
14841 do_neon_mac_maybe_scalar_long (void)
14843 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14847 do_neon_dyadic_wide (void)
14849 struct neon_type_el et = neon_check_type (3, NS_QQD,
14850 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14851 neon_mixed_length (et, et.size);
14855 do_neon_dyadic_narrow (void)
14857 struct neon_type_el et = neon_check_type (3, NS_QDD,
14858 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14859 /* Operand sign is unimportant, and the U bit is part of the opcode,
14860 so force the operand type to integer. */
14861 et.type = NT_integer;
14862 neon_mixed_length (et, et.size / 2);
14866 do_neon_mul_sat_scalar_long (void)
14868 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14872 do_neon_vmull (void)
14874 if (inst.operands[2].isscalar)
14875 do_neon_mac_maybe_scalar_long ();
14878 struct neon_type_el et = neon_check_type (3, NS_QDD,
14879 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14880 if (et.type == NT_poly)
14881 NEON_ENCODE (POLY, inst);
14883 NEON_ENCODE (INTEGER, inst);
14884 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14885 zero. Should be OK as-is. */
14886 neon_mixed_length (et, et.size);
14893 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14894 struct neon_type_el et = neon_check_type (3, rs,
14895 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14896 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14898 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14899 _("shift out of range"));
14900 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14901 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14902 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14903 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14904 inst.instruction |= LOW4 (inst.operands[2].reg);
14905 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14906 inst.instruction |= neon_quad (rs) << 6;
14907 inst.instruction |= imm << 8;
14909 neon_dp_fixup (&inst);
14915 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14916 struct neon_type_el et = neon_check_type (2, rs,
14917 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14918 unsigned op = (inst.instruction >> 7) & 3;
14919 /* N (width of reversed regions) is encoded as part of the bitmask. We
14920 extract it here to check the elements to be reversed are smaller.
14921 Otherwise we'd get a reserved instruction. */
14922 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14923 gas_assert (elsize != 0);
14924 constraint (et.size >= elsize,
14925 _("elements must be smaller than reversal region"));
14926 neon_two_same (neon_quad (rs), 1, et.size);
14932 if (inst.operands[1].isscalar)
14934 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14935 struct neon_type_el et = neon_check_type (2, rs,
14936 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14937 unsigned sizebits = et.size >> 3;
14938 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14939 int logsize = neon_logbits (et.size);
14940 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14942 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14945 NEON_ENCODE (SCALAR, inst);
14946 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14947 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14948 inst.instruction |= LOW4 (dm);
14949 inst.instruction |= HI1 (dm) << 5;
14950 inst.instruction |= neon_quad (rs) << 6;
14951 inst.instruction |= x << 17;
14952 inst.instruction |= sizebits << 16;
14954 neon_dp_fixup (&inst);
14958 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14959 struct neon_type_el et = neon_check_type (2, rs,
14960 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14961 /* Duplicate ARM register to lanes of vector. */
14962 NEON_ENCODE (ARMREG, inst);
14965 case 8: inst.instruction |= 0x400000; break;
14966 case 16: inst.instruction |= 0x000020; break;
14967 case 32: inst.instruction |= 0x000000; break;
14970 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14971 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14972 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14973 inst.instruction |= neon_quad (rs) << 21;
14974 /* The encoding for this instruction is identical for the ARM and Thumb
14975 variants, except for the condition field. */
14976 do_vfp_cond_or_thumb ();
14980 /* VMOV has particularly many variations. It can be one of:
14981 0. VMOV<c><q> <Qd>, <Qm>
14982 1. VMOV<c><q> <Dd>, <Dm>
14983 (Register operations, which are VORR with Rm = Rn.)
14984 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14985 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14987 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14988 (ARM register to scalar.)
14989 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14990 (Two ARM registers to vector.)
14991 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14992 (Scalar to ARM register.)
14993 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14994 (Vector to two ARM registers.)
14995 8. VMOV.F32 <Sd>, <Sm>
14996 9. VMOV.F64 <Dd>, <Dm>
14997 (VFP register moves.)
14998 10. VMOV.F32 <Sd>, #imm
14999 11. VMOV.F64 <Dd>, #imm
15000 (VFP float immediate load.)
15001 12. VMOV <Rd>, <Sm>
15002 (VFP single to ARM reg.)
15003 13. VMOV <Sd>, <Rm>
15004 (ARM reg to VFP single.)
15005 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15006 (Two ARM regs to two VFP singles.)
15007 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15008 (Two VFP singles to two ARM regs.)
15010 These cases can be disambiguated using neon_select_shape, except cases 1/9
15011 and 3/11 which depend on the operand type too.
15013 All the encoded bits are hardcoded by this function.
15015 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15016 Cases 5, 7 may be used with VFPv2 and above.
15018 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15019 can specify a type where it doesn't make sense to, and is ignored). */
15024 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15025 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15027 struct neon_type_el et;
15028 const char *ldconst = 0;
15032 case NS_DD: /* case 1/9. */
15033 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15034 /* It is not an error here if no type is given. */
15036 if (et.type == NT_float && et.size == 64)
15038 do_vfp_nsyn_opcode ("fcpyd");
15041 /* fall through. */
15043 case NS_QQ: /* case 0/1. */
15045 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15047 /* The architecture manual I have doesn't explicitly state which
15048 value the U bit should have for register->register moves, but
15049 the equivalent VORR instruction has U = 0, so do that. */
15050 inst.instruction = 0x0200110;
15051 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15052 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15053 inst.instruction |= LOW4 (inst.operands[1].reg);
15054 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15055 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15056 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15057 inst.instruction |= neon_quad (rs) << 6;
15059 neon_dp_fixup (&inst);
15063 case NS_DI: /* case 3/11. */
15064 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15066 if (et.type == NT_float && et.size == 64)
15068 /* case 11 (fconstd). */
15069 ldconst = "fconstd";
15070 goto encode_fconstd;
15072 /* fall through. */
15074 case NS_QI: /* case 2/3. */
15075 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15077 inst.instruction = 0x0800010;
15078 neon_move_immediate ();
15079 neon_dp_fixup (&inst);
15082 case NS_SR: /* case 4. */
15084 unsigned bcdebits = 0;
15086 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15087 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15089 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15090 logsize = neon_logbits (et.size);
15092 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15094 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15095 && et.size != 32, _(BAD_FPU));
15096 constraint (et.type == NT_invtype, _("bad type for scalar"));
15097 constraint (x >= 64 / et.size, _("scalar index out of range"));
15101 case 8: bcdebits = 0x8; break;
15102 case 16: bcdebits = 0x1; break;
15103 case 32: bcdebits = 0x0; break;
15107 bcdebits |= x << logsize;
15109 inst.instruction = 0xe000b10;
15110 do_vfp_cond_or_thumb ();
15111 inst.instruction |= LOW4 (dn) << 16;
15112 inst.instruction |= HI1 (dn) << 7;
15113 inst.instruction |= inst.operands[1].reg << 12;
15114 inst.instruction |= (bcdebits & 3) << 5;
15115 inst.instruction |= (bcdebits >> 2) << 21;
15119 case NS_DRR: /* case 5 (fmdrr). */
15120 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15123 inst.instruction = 0xc400b10;
15124 do_vfp_cond_or_thumb ();
15125 inst.instruction |= LOW4 (inst.operands[0].reg);
15126 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15127 inst.instruction |= inst.operands[1].reg << 12;
15128 inst.instruction |= inst.operands[2].reg << 16;
15131 case NS_RS: /* case 6. */
15134 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15135 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15136 unsigned abcdebits = 0;
15138 et = neon_check_type (2, NS_NULL,
15139 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15140 logsize = neon_logbits (et.size);
15142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15144 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15145 && et.size != 32, _(BAD_FPU));
15146 constraint (et.type == NT_invtype, _("bad type for scalar"));
15147 constraint (x >= 64 / et.size, _("scalar index out of range"));
15151 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15152 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15153 case 32: abcdebits = 0x00; break;
15157 abcdebits |= x << logsize;
15158 inst.instruction = 0xe100b10;
15159 do_vfp_cond_or_thumb ();
15160 inst.instruction |= LOW4 (dn) << 16;
15161 inst.instruction |= HI1 (dn) << 7;
15162 inst.instruction |= inst.operands[0].reg << 12;
15163 inst.instruction |= (abcdebits & 3) << 5;
15164 inst.instruction |= (abcdebits >> 2) << 21;
15168 case NS_RRD: /* case 7 (fmrrd). */
15169 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15172 inst.instruction = 0xc500b10;
15173 do_vfp_cond_or_thumb ();
15174 inst.instruction |= inst.operands[0].reg << 12;
15175 inst.instruction |= inst.operands[1].reg << 16;
15176 inst.instruction |= LOW4 (inst.operands[2].reg);
15177 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15180 case NS_FF: /* case 8 (fcpys). */
15181 do_vfp_nsyn_opcode ("fcpys");
15184 case NS_FI: /* case 10 (fconsts). */
15185 ldconst = "fconsts";
15187 if (is_quarter_float (inst.operands[1].imm))
15189 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15190 do_vfp_nsyn_opcode (ldconst);
15193 first_error (_("immediate out of range"));
15196 case NS_RF: /* case 12 (fmrs). */
15197 do_vfp_nsyn_opcode ("fmrs");
15200 case NS_FR: /* case 13 (fmsr). */
15201 do_vfp_nsyn_opcode ("fmsr");
15204 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15205 (one of which is a list), but we have parsed four. Do some fiddling to
15206 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15208 case NS_RRFF: /* case 14 (fmrrs). */
15209 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15210 _("VFP registers must be adjacent"));
15211 inst.operands[2].imm = 2;
15212 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15213 do_vfp_nsyn_opcode ("fmrrs");
15216 case NS_FFRR: /* case 15 (fmsrr). */
15217 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15218 _("VFP registers must be adjacent"));
15219 inst.operands[1] = inst.operands[2];
15220 inst.operands[2] = inst.operands[3];
15221 inst.operands[0].imm = 2;
15222 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15223 do_vfp_nsyn_opcode ("fmsrr");
15232 do_neon_rshift_round_imm (void)
15234 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15235 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15236 int imm = inst.operands[2].imm;
15238 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15241 inst.operands[2].present = 0;
15246 constraint (imm < 1 || (unsigned)imm > et.size,
15247 _("immediate out of range for shift"));
15248 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15253 do_neon_movl (void)
15255 struct neon_type_el et = neon_check_type (2, NS_QD,
15256 N_EQK | N_DBL, N_SU_32 | N_KEY);
15257 unsigned sizebits = et.size >> 3;
15258 inst.instruction |= sizebits << 19;
15259 neon_two_same (0, et.type == NT_unsigned, -1);
15265 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15266 struct neon_type_el et = neon_check_type (2, rs,
15267 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15268 NEON_ENCODE (INTEGER, inst);
15269 neon_two_same (neon_quad (rs), 1, et.size);
15273 do_neon_zip_uzp (void)
15275 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15276 struct neon_type_el et = neon_check_type (2, rs,
15277 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15278 if (rs == NS_DD && et.size == 32)
15280 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15281 inst.instruction = N_MNEM_vtrn;
15285 neon_two_same (neon_quad (rs), 1, et.size);
15289 do_neon_sat_abs_neg (void)
15291 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15292 struct neon_type_el et = neon_check_type (2, rs,
15293 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15294 neon_two_same (neon_quad (rs), 1, et.size);
15298 do_neon_pair_long (void)
15300 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15301 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15302 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15303 inst.instruction |= (et.type == NT_unsigned) << 7;
15304 neon_two_same (neon_quad (rs), 1, et.size);
15308 do_neon_recip_est (void)
15310 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15311 struct neon_type_el et = neon_check_type (2, rs,
15312 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15313 inst.instruction |= (et.type == NT_float) << 8;
15314 neon_two_same (neon_quad (rs), 1, et.size);
15320 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15321 struct neon_type_el et = neon_check_type (2, rs,
15322 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15323 neon_two_same (neon_quad (rs), 1, et.size);
15329 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15330 struct neon_type_el et = neon_check_type (2, rs,
15331 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15332 neon_two_same (neon_quad (rs), 1, et.size);
15338 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15339 struct neon_type_el et = neon_check_type (2, rs,
15340 N_EQK | N_INT, N_8 | N_KEY);
15341 neon_two_same (neon_quad (rs), 1, et.size);
15347 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15348 neon_two_same (neon_quad (rs), 1, -1);
15352 do_neon_tbl_tbx (void)
15354 unsigned listlenbits;
15355 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15357 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15359 first_error (_("bad list length for table lookup"));
15363 listlenbits = inst.operands[1].imm - 1;
15364 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15365 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15366 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15367 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15368 inst.instruction |= LOW4 (inst.operands[2].reg);
15369 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15370 inst.instruction |= listlenbits << 8;
15372 neon_dp_fixup (&inst);
15376 do_neon_ldm_stm (void)
15378 /* P, U and L bits are part of bitmask. */
15379 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15380 unsigned offsetbits = inst.operands[1].imm * 2;
15382 if (inst.operands[1].issingle)
15384 do_vfp_nsyn_ldm_stm (is_dbmode);
15388 constraint (is_dbmode && !inst.operands[0].writeback,
15389 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15391 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15392 _("register list must contain at least 1 and at most 16 "
15395 inst.instruction |= inst.operands[0].reg << 16;
15396 inst.instruction |= inst.operands[0].writeback << 21;
15397 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15398 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15400 inst.instruction |= offsetbits;
15402 do_vfp_cond_or_thumb ();
15406 do_neon_ldr_str (void)
15408 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15410 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15411 And is UNPREDICTABLE in thumb mode. */
15413 && inst.operands[1].reg == REG_PC
15414 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15416 if (!thumb_mode && warn_on_deprecated)
15417 as_warn (_("Use of PC here is deprecated"));
15419 inst.error = _("Use of PC here is UNPREDICTABLE");
15422 if (inst.operands[0].issingle)
15425 do_vfp_nsyn_opcode ("flds");
15427 do_vfp_nsyn_opcode ("fsts");
15432 do_vfp_nsyn_opcode ("fldd");
15434 do_vfp_nsyn_opcode ("fstd");
15438 /* "interleave" version also handles non-interleaving register VLD1/VST1
15442 do_neon_ld_st_interleave (void)
15444 struct neon_type_el et = neon_check_type (1, NS_NULL,
15445 N_8 | N_16 | N_32 | N_64);
15446 unsigned alignbits = 0;
15448 /* The bits in this table go:
15449 0: register stride of one (0) or two (1)
15450 1,2: register list length, minus one (1, 2, 3, 4).
15451 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15452 We use -1 for invalid entries. */
15453 const int typetable[] =
15455 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15456 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15457 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15458 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15462 if (et.type == NT_invtype)
15465 if (inst.operands[1].immisalign)
15466 switch (inst.operands[1].imm >> 8)
15468 case 64: alignbits = 1; break;
15470 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15471 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15472 goto bad_alignment;
15476 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15477 goto bad_alignment;
15482 first_error (_("bad alignment"));
15486 inst.instruction |= alignbits << 4;
15487 inst.instruction |= neon_logbits (et.size) << 6;
15489 /* Bits [4:6] of the immediate in a list specifier encode register stride
15490 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15491 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15492 up the right value for "type" in a table based on this value and the given
15493 list style, then stick it back. */
15494 idx = ((inst.operands[0].imm >> 4) & 7)
15495 | (((inst.instruction >> 8) & 3) << 3);
15497 typebits = typetable[idx];
15499 constraint (typebits == -1, _("bad list type for instruction"));
15501 inst.instruction &= ~0xf00;
15502 inst.instruction |= typebits << 8;
15505 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15506 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15507 otherwise. The variable arguments are a list of pairs of legal (size, align)
15508 values, terminated with -1. */
15511 neon_alignment_bit (int size, int align, int *do_align, ...)
15514 int result = FAIL, thissize, thisalign;
15516 if (!inst.operands[1].immisalign)
15522 va_start (ap, do_align);
15526 thissize = va_arg (ap, int);
15527 if (thissize == -1)
15529 thisalign = va_arg (ap, int);
15531 if (size == thissize && align == thisalign)
15534 while (result != SUCCESS);
15538 if (result == SUCCESS)
15541 first_error (_("unsupported alignment for instruction"));
15547 do_neon_ld_st_lane (void)
15549 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15550 int align_good, do_align = 0;
15551 int logsize = neon_logbits (et.size);
15552 int align = inst.operands[1].imm >> 8;
15553 int n = (inst.instruction >> 8) & 3;
15554 int max_el = 64 / et.size;
15556 if (et.type == NT_invtype)
15559 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15560 _("bad list length"));
15561 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15562 _("scalar index out of range"));
15563 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15565 _("stride of 2 unavailable when element size is 8"));
15569 case 0: /* VLD1 / VST1. */
15570 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15572 if (align_good == FAIL)
15576 unsigned alignbits = 0;
15579 case 16: alignbits = 0x1; break;
15580 case 32: alignbits = 0x3; break;
15583 inst.instruction |= alignbits << 4;
15587 case 1: /* VLD2 / VST2. */
15588 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15590 if (align_good == FAIL)
15593 inst.instruction |= 1 << 4;
15596 case 2: /* VLD3 / VST3. */
15597 constraint (inst.operands[1].immisalign,
15598 _("can't use alignment with this instruction"));
15601 case 3: /* VLD4 / VST4. */
15602 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15603 16, 64, 32, 64, 32, 128, -1);
15604 if (align_good == FAIL)
15608 unsigned alignbits = 0;
15611 case 8: alignbits = 0x1; break;
15612 case 16: alignbits = 0x1; break;
15613 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15616 inst.instruction |= alignbits << 4;
15623 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15624 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15625 inst.instruction |= 1 << (4 + logsize);
15627 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15628 inst.instruction |= logsize << 10;
15631 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15634 do_neon_ld_dup (void)
15636 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15637 int align_good, do_align = 0;
15639 if (et.type == NT_invtype)
15642 switch ((inst.instruction >> 8) & 3)
15644 case 0: /* VLD1. */
15645 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15646 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15647 &do_align, 16, 16, 32, 32, -1);
15648 if (align_good == FAIL)
15650 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15653 case 2: inst.instruction |= 1 << 5; break;
15654 default: first_error (_("bad list length")); return;
15656 inst.instruction |= neon_logbits (et.size) << 6;
15659 case 1: /* VLD2. */
15660 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15661 &do_align, 8, 16, 16, 32, 32, 64, -1);
15662 if (align_good == FAIL)
15664 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15665 _("bad list length"));
15666 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15667 inst.instruction |= 1 << 5;
15668 inst.instruction |= neon_logbits (et.size) << 6;
15671 case 2: /* VLD3. */
15672 constraint (inst.operands[1].immisalign,
15673 _("can't use alignment with this instruction"));
15674 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15675 _("bad list length"));
15676 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15677 inst.instruction |= 1 << 5;
15678 inst.instruction |= neon_logbits (et.size) << 6;
15681 case 3: /* VLD4. */
15683 int align = inst.operands[1].imm >> 8;
15684 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15685 16, 64, 32, 64, 32, 128, -1);
15686 if (align_good == FAIL)
15688 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15689 _("bad list length"));
15690 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15691 inst.instruction |= 1 << 5;
15692 if (et.size == 32 && align == 128)
15693 inst.instruction |= 0x3 << 6;
15695 inst.instruction |= neon_logbits (et.size) << 6;
15702 inst.instruction |= do_align << 4;
15705 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15706 apart from bits [11:4]. */
15709 do_neon_ldx_stx (void)
15711 if (inst.operands[1].isreg)
15712 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15714 switch (NEON_LANE (inst.operands[0].imm))
15716 case NEON_INTERLEAVE_LANES:
15717 NEON_ENCODE (INTERLV, inst);
15718 do_neon_ld_st_interleave ();
15721 case NEON_ALL_LANES:
15722 NEON_ENCODE (DUP, inst);
15727 NEON_ENCODE (LANE, inst);
15728 do_neon_ld_st_lane ();
15731 /* L bit comes from bit mask. */
15732 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15733 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15734 inst.instruction |= inst.operands[1].reg << 16;
15736 if (inst.operands[1].postind)
15738 int postreg = inst.operands[1].imm & 0xf;
15739 constraint (!inst.operands[1].immisreg,
15740 _("post-index must be a register"));
15741 constraint (postreg == 0xd || postreg == 0xf,
15742 _("bad register for post-index"));
15743 inst.instruction |= postreg;
15745 else if (inst.operands[1].writeback)
15747 inst.instruction |= 0xd;
15750 inst.instruction |= 0xf;
15753 inst.instruction |= 0xf9000000;
15755 inst.instruction |= 0xf4000000;
15758 /* Overall per-instruction processing. */
15760 /* We need to be able to fix up arbitrary expressions in some statements.
15761 This is so that we can handle symbols that are an arbitrary distance from
15762 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15763 which returns part of an address in a form which will be valid for
15764 a data instruction. We do this by pushing the expression into a symbol
15765 in the expr_section, and creating a fix for that. */
15768 fix_new_arm (fragS * frag,
15782 /* Create an absolute valued symbol, so we have something to
15783 refer to in the object file. Unfortunately for us, gas's
15784 generic expression parsing will already have folded out
15785 any use of .set foo/.type foo %function that may have
15786 been used to set type information of the target location,
15787 that's being specified symbolically. We have to presume
15788 the user knows what they are doing. */
15792 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15794 symbol = symbol_find_or_make (name);
15795 S_SET_SEGMENT (symbol, absolute_section);
15796 symbol_set_frag (symbol, &zero_address_frag);
15797 S_SET_VALUE (symbol, exp->X_add_number);
15798 exp->X_op = O_symbol;
15799 exp->X_add_symbol = symbol;
15800 exp->X_add_number = 0;
15806 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15807 (enum bfd_reloc_code_real) reloc);
15811 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15812 pc_rel, (enum bfd_reloc_code_real) reloc);
15816 /* Mark whether the fix is to a THUMB instruction, or an ARM
15818 new_fix->tc_fix_data = thumb_mode;
15821 /* Create a frg for an instruction requiring relaxation. */
15823 output_relax_insn (void)
15829 /* The size of the instruction is unknown, so tie the debug info to the
15830 start of the instruction. */
15831 dwarf2_emit_insn (0);
15833 switch (inst.reloc.exp.X_op)
15836 sym = inst.reloc.exp.X_add_symbol;
15837 offset = inst.reloc.exp.X_add_number;
15841 offset = inst.reloc.exp.X_add_number;
15844 sym = make_expr_symbol (&inst.reloc.exp);
15848 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15849 inst.relax, sym, offset, NULL/*offset, opcode*/);
15850 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15853 /* Write a 32-bit thumb instruction to buf. */
15855 put_thumb32_insn (char * buf, unsigned long insn)
15857 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15858 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15862 output_inst (const char * str)
15868 as_bad ("%s -- `%s'", inst.error, str);
15873 output_relax_insn ();
15876 if (inst.size == 0)
15879 to = frag_more (inst.size);
15880 /* PR 9814: Record the thumb mode into the current frag so that we know
15881 what type of NOP padding to use, if necessary. We override any previous
15882 setting so that if the mode has changed then the NOPS that we use will
15883 match the encoding of the last instruction in the frag. */
15884 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15886 if (thumb_mode && (inst.size > THUMB_SIZE))
15888 gas_assert (inst.size == (2 * THUMB_SIZE));
15889 put_thumb32_insn (to, inst.instruction);
15891 else if (inst.size > INSN_SIZE)
15893 gas_assert (inst.size == (2 * INSN_SIZE));
15894 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15895 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15898 md_number_to_chars (to, inst.instruction, inst.size);
15900 if (inst.reloc.type != BFD_RELOC_UNUSED)
15901 fix_new_arm (frag_now, to - frag_now->fr_literal,
15902 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15905 dwarf2_emit_insn (inst.size);
15909 output_it_inst (int cond, int mask, char * to)
15911 unsigned long instruction = 0xbf00;
15914 instruction |= mask;
15915 instruction |= cond << 4;
15919 to = frag_more (2);
15921 dwarf2_emit_insn (2);
15925 md_number_to_chars (to, instruction, 2);
15930 /* Tag values used in struct asm_opcode's tag field. */
15933 OT_unconditional, /* Instruction cannot be conditionalized.
15934 The ARM condition field is still 0xE. */
15935 OT_unconditionalF, /* Instruction cannot be conditionalized
15936 and carries 0xF in its ARM condition field. */
15937 OT_csuffix, /* Instruction takes a conditional suffix. */
15938 OT_csuffixF, /* Some forms of the instruction take a conditional
15939 suffix, others place 0xF where the condition field
15941 OT_cinfix3, /* Instruction takes a conditional infix,
15942 beginning at character index 3. (In
15943 unified mode, it becomes a suffix.) */
15944 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15945 tsts, cmps, cmns, and teqs. */
15946 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15947 character index 3, even in unified mode. Used for
15948 legacy instructions where suffix and infix forms
15949 may be ambiguous. */
15950 OT_csuf_or_in3, /* Instruction takes either a conditional
15951 suffix or an infix at character index 3. */
15952 OT_odd_infix_unc, /* This is the unconditional variant of an
15953 instruction that takes a conditional infix
15954 at an unusual position. In unified mode,
15955 this variant will accept a suffix. */
15956 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15957 are the conditional variants of instructions that
15958 take conditional infixes in unusual positions.
15959 The infix appears at character index
15960 (tag - OT_odd_infix_0). These are not accepted
15961 in unified mode. */
15964 /* Subroutine of md_assemble, responsible for looking up the primary
15965 opcode from the mnemonic the user wrote. STR points to the
15966 beginning of the mnemonic.
15968 This is not simply a hash table lookup, because of conditional
15969 variants. Most instructions have conditional variants, which are
15970 expressed with a _conditional affix_ to the mnemonic. If we were
15971 to encode each conditional variant as a literal string in the opcode
15972 table, it would have approximately 20,000 entries.
15974 Most mnemonics take this affix as a suffix, and in unified syntax,
15975 'most' is upgraded to 'all'. However, in the divided syntax, some
15976 instructions take the affix as an infix, notably the s-variants of
15977 the arithmetic instructions. Of those instructions, all but six
15978 have the infix appear after the third character of the mnemonic.
15980 Accordingly, the algorithm for looking up primary opcodes given
15983 1. Look up the identifier in the opcode table.
15984 If we find a match, go to step U.
15986 2. Look up the last two characters of the identifier in the
15987 conditions table. If we find a match, look up the first N-2
15988 characters of the identifier in the opcode table. If we
15989 find a match, go to step CE.
15991 3. Look up the fourth and fifth characters of the identifier in
15992 the conditions table. If we find a match, extract those
15993 characters from the identifier, and look up the remaining
15994 characters in the opcode table. If we find a match, go
15999 U. Examine the tag field of the opcode structure, in case this is
16000 one of the six instructions with its conditional infix in an
16001 unusual place. If it is, the tag tells us where to find the
16002 infix; look it up in the conditions table and set inst.cond
16003 accordingly. Otherwise, this is an unconditional instruction.
16004 Again set inst.cond accordingly. Return the opcode structure.
16006 CE. Examine the tag field to make sure this is an instruction that
16007 should receive a conditional suffix. If it is not, fail.
16008 Otherwise, set inst.cond from the suffix we already looked up,
16009 and return the opcode structure.
16011 CM. Examine the tag field to make sure this is an instruction that
16012 should receive a conditional infix after the third character.
16013 If it is not, fail. Otherwise, undo the edits to the current
16014 line of input and proceed as for case CE. */
16016 static const struct asm_opcode *
16017 opcode_lookup (char **str)
16021 const struct asm_opcode *opcode;
16022 const struct asm_cond *cond;
16025 /* Scan up to the end of the mnemonic, which must end in white space,
16026 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16027 for (base = end = *str; *end != '\0'; end++)
16028 if (*end == ' ' || *end == '.')
16034 /* Handle a possible width suffix and/or Neon type suffix. */
16039 /* The .w and .n suffixes are only valid if the unified syntax is in
16041 if (unified_syntax && end[1] == 'w')
16043 else if (unified_syntax && end[1] == 'n')
16048 inst.vectype.elems = 0;
16050 *str = end + offset;
16052 if (end[offset] == '.')
16054 /* See if we have a Neon type suffix (possible in either unified or
16055 non-unified ARM syntax mode). */
16056 if (parse_neon_type (&inst.vectype, str) == FAIL)
16059 else if (end[offset] != '\0' && end[offset] != ' ')
16065 /* Look for unaffixed or special-case affixed mnemonic. */
16066 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16071 if (opcode->tag < OT_odd_infix_0)
16073 inst.cond = COND_ALWAYS;
16077 if (warn_on_deprecated && unified_syntax)
16078 as_warn (_("conditional infixes are deprecated in unified syntax"));
16079 affix = base + (opcode->tag - OT_odd_infix_0);
16080 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16083 inst.cond = cond->value;
16087 /* Cannot have a conditional suffix on a mnemonic of less than two
16089 if (end - base < 3)
16092 /* Look for suffixed mnemonic. */
16094 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16095 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16097 if (opcode && cond)
16100 switch (opcode->tag)
16102 case OT_cinfix3_legacy:
16103 /* Ignore conditional suffixes matched on infix only mnemonics. */
16107 case OT_cinfix3_deprecated:
16108 case OT_odd_infix_unc:
16109 if (!unified_syntax)
16111 /* else fall through */
16115 case OT_csuf_or_in3:
16116 inst.cond = cond->value;
16119 case OT_unconditional:
16120 case OT_unconditionalF:
16122 inst.cond = cond->value;
16125 /* Delayed diagnostic. */
16126 inst.error = BAD_COND;
16127 inst.cond = COND_ALWAYS;
16136 /* Cannot have a usual-position infix on a mnemonic of less than
16137 six characters (five would be a suffix). */
16138 if (end - base < 6)
16141 /* Look for infixed mnemonic in the usual position. */
16143 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16147 memcpy (save, affix, 2);
16148 memmove (affix, affix + 2, (end - affix) - 2);
16149 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16151 memmove (affix + 2, affix, (end - affix) - 2);
16152 memcpy (affix, save, 2);
16155 && (opcode->tag == OT_cinfix3
16156 || opcode->tag == OT_cinfix3_deprecated
16157 || opcode->tag == OT_csuf_or_in3
16158 || opcode->tag == OT_cinfix3_legacy))
16161 if (warn_on_deprecated && unified_syntax
16162 && (opcode->tag == OT_cinfix3
16163 || opcode->tag == OT_cinfix3_deprecated))
16164 as_warn (_("conditional infixes are deprecated in unified syntax"));
16166 inst.cond = cond->value;
16173 /* This function generates an initial IT instruction, leaving its block
16174 virtually open for the new instructions. Eventually,
16175 the mask will be updated by now_it_add_mask () each time
16176 a new instruction needs to be included in the IT block.
16177 Finally, the block is closed with close_automatic_it_block ().
16178 The block closure can be requested either from md_assemble (),
16179 a tencode (), or due to a label hook. */
16182 new_automatic_it_block (int cond)
16184 now_it.state = AUTOMATIC_IT_BLOCK;
16185 now_it.mask = 0x18;
16187 now_it.block_length = 1;
16188 mapping_state (MAP_THUMB);
16189 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16192 /* Close an automatic IT block.
16193 See comments in new_automatic_it_block (). */
16196 close_automatic_it_block (void)
16198 now_it.mask = 0x10;
16199 now_it.block_length = 0;
16202 /* Update the mask of the current automatically-generated IT
16203 instruction. See comments in new_automatic_it_block (). */
16206 now_it_add_mask (int cond)
16208 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16209 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16210 | ((bitvalue) << (nbit)))
16211 const int resulting_bit = (cond & 1);
16213 now_it.mask &= 0xf;
16214 now_it.mask = SET_BIT_VALUE (now_it.mask,
16216 (5 - now_it.block_length));
16217 now_it.mask = SET_BIT_VALUE (now_it.mask,
16219 ((5 - now_it.block_length) - 1) );
16220 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16223 #undef SET_BIT_VALUE
16226 /* The IT blocks handling machinery is accessed through the these functions:
16227 it_fsm_pre_encode () from md_assemble ()
16228 set_it_insn_type () optional, from the tencode functions
16229 set_it_insn_type_last () ditto
16230 in_it_block () ditto
16231 it_fsm_post_encode () from md_assemble ()
16232 force_automatic_it_block_close () from label habdling functions
16235 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16236 initializing the IT insn type with a generic initial value depending
16237 on the inst.condition.
16238 2) During the tencode function, two things may happen:
16239 a) The tencode function overrides the IT insn type by
16240 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16241 b) The tencode function queries the IT block state by
16242 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16244 Both set_it_insn_type and in_it_block run the internal FSM state
16245 handling function (handle_it_state), because: a) setting the IT insn
16246 type may incur in an invalid state (exiting the function),
16247 and b) querying the state requires the FSM to be updated.
16248 Specifically we want to avoid creating an IT block for conditional
16249 branches, so it_fsm_pre_encode is actually a guess and we can't
16250 determine whether an IT block is required until the tencode () routine
16251 has decided what type of instruction this actually it.
16252 Because of this, if set_it_insn_type and in_it_block have to be used,
16253 set_it_insn_type has to be called first.
16255 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16256 determines the insn IT type depending on the inst.cond code.
16257 When a tencode () routine encodes an instruction that can be
16258 either outside an IT block, or, in the case of being inside, has to be
16259 the last one, set_it_insn_type_last () will determine the proper
16260 IT instruction type based on the inst.cond code. Otherwise,
16261 set_it_insn_type can be called for overriding that logic or
16262 for covering other cases.
16264 Calling handle_it_state () may not transition the IT block state to
16265 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16266 still queried. Instead, if the FSM determines that the state should
16267 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16268 after the tencode () function: that's what it_fsm_post_encode () does.
16270 Since in_it_block () calls the state handling function to get an
16271 updated state, an error may occur (due to invalid insns combination).
16272 In that case, inst.error is set.
16273 Therefore, inst.error has to be checked after the execution of
16274 the tencode () routine.
16276 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16277 any pending state change (if any) that didn't take place in
16278 handle_it_state () as explained above. */
16281 it_fsm_pre_encode (void)
16283 if (inst.cond != COND_ALWAYS)
16284 inst.it_insn_type = INSIDE_IT_INSN;
16286 inst.it_insn_type = OUTSIDE_IT_INSN;
16288 now_it.state_handled = 0;
16291 /* IT state FSM handling function. */
16294 handle_it_state (void)
16296 now_it.state_handled = 1;
16298 switch (now_it.state)
16300 case OUTSIDE_IT_BLOCK:
16301 switch (inst.it_insn_type)
16303 case OUTSIDE_IT_INSN:
16306 case INSIDE_IT_INSN:
16307 case INSIDE_IT_LAST_INSN:
16308 if (thumb_mode == 0)
16311 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16312 as_tsktsk (_("Warning: conditional outside an IT block"\
16317 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16318 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16320 /* Automatically generate the IT instruction. */
16321 new_automatic_it_block (inst.cond);
16322 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16323 close_automatic_it_block ();
16327 inst.error = BAD_OUT_IT;
16333 case IF_INSIDE_IT_LAST_INSN:
16334 case NEUTRAL_IT_INSN:
16338 now_it.state = MANUAL_IT_BLOCK;
16339 now_it.block_length = 0;
16344 case AUTOMATIC_IT_BLOCK:
16345 /* Three things may happen now:
16346 a) We should increment current it block size;
16347 b) We should close current it block (closing insn or 4 insns);
16348 c) We should close current it block and start a new one (due
16349 to incompatible conditions or
16350 4 insns-length block reached). */
16352 switch (inst.it_insn_type)
16354 case OUTSIDE_IT_INSN:
16355 /* The closure of the block shall happen immediatelly,
16356 so any in_it_block () call reports the block as closed. */
16357 force_automatic_it_block_close ();
16360 case INSIDE_IT_INSN:
16361 case INSIDE_IT_LAST_INSN:
16362 case IF_INSIDE_IT_LAST_INSN:
16363 now_it.block_length++;
16365 if (now_it.block_length > 4
16366 || !now_it_compatible (inst.cond))
16368 force_automatic_it_block_close ();
16369 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16370 new_automatic_it_block (inst.cond);
16374 now_it_add_mask (inst.cond);
16377 if (now_it.state == AUTOMATIC_IT_BLOCK
16378 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16379 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16380 close_automatic_it_block ();
16383 case NEUTRAL_IT_INSN:
16384 now_it.block_length++;
16386 if (now_it.block_length > 4)
16387 force_automatic_it_block_close ();
16389 now_it_add_mask (now_it.cc & 1);
16393 close_automatic_it_block ();
16394 now_it.state = MANUAL_IT_BLOCK;
16399 case MANUAL_IT_BLOCK:
16401 /* Check conditional suffixes. */
16402 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16405 now_it.mask &= 0x1f;
16406 is_last = (now_it.mask == 0x10);
16408 switch (inst.it_insn_type)
16410 case OUTSIDE_IT_INSN:
16411 inst.error = BAD_NOT_IT;
16414 case INSIDE_IT_INSN:
16415 if (cond != inst.cond)
16417 inst.error = BAD_IT_COND;
16422 case INSIDE_IT_LAST_INSN:
16423 case IF_INSIDE_IT_LAST_INSN:
16424 if (cond != inst.cond)
16426 inst.error = BAD_IT_COND;
16431 inst.error = BAD_BRANCH;
16436 case NEUTRAL_IT_INSN:
16437 /* The BKPT instruction is unconditional even in an IT block. */
16441 inst.error = BAD_IT_IT;
16452 it_fsm_post_encode (void)
16456 if (!now_it.state_handled)
16457 handle_it_state ();
16459 is_last = (now_it.mask == 0x10);
16462 now_it.state = OUTSIDE_IT_BLOCK;
16468 force_automatic_it_block_close (void)
16470 if (now_it.state == AUTOMATIC_IT_BLOCK)
16472 close_automatic_it_block ();
16473 now_it.state = OUTSIDE_IT_BLOCK;
16481 if (!now_it.state_handled)
16482 handle_it_state ();
16484 return now_it.state != OUTSIDE_IT_BLOCK;
16488 md_assemble (char *str)
16491 const struct asm_opcode * opcode;
16493 /* Align the previous label if needed. */
16494 if (last_label_seen != NULL)
16496 symbol_set_frag (last_label_seen, frag_now);
16497 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16498 S_SET_SEGMENT (last_label_seen, now_seg);
16501 memset (&inst, '\0', sizeof (inst));
16502 inst.reloc.type = BFD_RELOC_UNUSED;
16504 opcode = opcode_lookup (&p);
16507 /* It wasn't an instruction, but it might be a register alias of
16508 the form alias .req reg, or a Neon .dn/.qn directive. */
16509 if (! create_register_alias (str, p)
16510 && ! create_neon_reg_alias (str, p))
16511 as_bad (_("bad instruction `%s'"), str);
16516 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16517 as_warn (_("s suffix on comparison instruction is deprecated"));
16519 /* The value which unconditional instructions should have in place of the
16520 condition field. */
16521 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16525 arm_feature_set variant;
16527 variant = cpu_variant;
16528 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16529 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16530 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16531 /* Check that this instruction is supported for this CPU. */
16532 if (!opcode->tvariant
16533 || (thumb_mode == 1
16534 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16536 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16539 if (inst.cond != COND_ALWAYS && !unified_syntax
16540 && opcode->tencode != do_t_branch)
16542 as_bad (_("Thumb does not support conditional execution"));
16546 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16548 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16549 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16550 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16552 /* Two things are addressed here.
16553 1) Implicit require narrow instructions on Thumb-1.
16554 This avoids relaxation accidentally introducing Thumb-2
16556 2) Reject wide instructions in non Thumb-2 cores. */
16557 if (inst.size_req == 0)
16559 else if (inst.size_req == 4)
16561 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16567 inst.instruction = opcode->tvalue;
16569 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16571 /* Prepare the it_insn_type for those encodings that don't set
16573 it_fsm_pre_encode ();
16575 opcode->tencode ();
16577 it_fsm_post_encode ();
16580 if (!(inst.error || inst.relax))
16582 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16583 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16584 if (inst.size_req && inst.size_req != inst.size)
16586 as_bad (_("cannot honor width suffix -- `%s'"), str);
16591 /* Something has gone badly wrong if we try to relax a fixed size
16593 gas_assert (inst.size_req == 0 || !inst.relax);
16595 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16596 *opcode->tvariant);
16597 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16598 set those bits when Thumb-2 32-bit instructions are seen. ie.
16599 anything other than bl/blx and v6-M instructions.
16600 This is overly pessimistic for relaxable instructions. */
16601 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16603 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16604 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16605 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16608 check_neon_suffixes;
16612 mapping_state (MAP_THUMB);
16615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16619 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16620 is_bx = (opcode->aencode == do_bx);
16622 /* Check that this instruction is supported for this CPU. */
16623 if (!(is_bx && fix_v4bx)
16624 && !(opcode->avariant &&
16625 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16627 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16632 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16636 inst.instruction = opcode->avalue;
16637 if (opcode->tag == OT_unconditionalF)
16638 inst.instruction |= 0xF << 28;
16640 inst.instruction |= inst.cond << 28;
16641 inst.size = INSN_SIZE;
16642 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16644 it_fsm_pre_encode ();
16645 opcode->aencode ();
16646 it_fsm_post_encode ();
16648 /* Arm mode bx is marked as both v4T and v5 because it's still required
16649 on a hypothetical non-thumb v5 core. */
16651 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16653 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16654 *opcode->avariant);
16656 check_neon_suffixes;
16660 mapping_state (MAP_ARM);
16665 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16673 check_it_blocks_finished (void)
16678 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16679 if (seg_info (sect)->tc_segment_info_data.current_it.state
16680 == MANUAL_IT_BLOCK)
16682 as_warn (_("section '%s' finished with an open IT block."),
16686 if (now_it.state == MANUAL_IT_BLOCK)
16687 as_warn (_("file finished with an open IT block."));
16691 /* Various frobbings of labels and their addresses. */
16694 arm_start_line_hook (void)
16696 last_label_seen = NULL;
16700 arm_frob_label (symbolS * sym)
16702 last_label_seen = sym;
16704 ARM_SET_THUMB (sym, thumb_mode);
16706 #if defined OBJ_COFF || defined OBJ_ELF
16707 ARM_SET_INTERWORK (sym, support_interwork);
16710 force_automatic_it_block_close ();
16712 /* Note - do not allow local symbols (.Lxxx) to be labelled
16713 as Thumb functions. This is because these labels, whilst
16714 they exist inside Thumb code, are not the entry points for
16715 possible ARM->Thumb calls. Also, these labels can be used
16716 as part of a computed goto or switch statement. eg gcc
16717 can generate code that looks like this:
16719 ldr r2, [pc, .Laaa]
16729 The first instruction loads the address of the jump table.
16730 The second instruction converts a table index into a byte offset.
16731 The third instruction gets the jump address out of the table.
16732 The fourth instruction performs the jump.
16734 If the address stored at .Laaa is that of a symbol which has the
16735 Thumb_Func bit set, then the linker will arrange for this address
16736 to have the bottom bit set, which in turn would mean that the
16737 address computation performed by the third instruction would end
16738 up with the bottom bit set. Since the ARM is capable of unaligned
16739 word loads, the instruction would then load the incorrect address
16740 out of the jump table, and chaos would ensue. */
16741 if (label_is_thumb_function_name
16742 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16743 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16745 /* When the address of a Thumb function is taken the bottom
16746 bit of that address should be set. This will allow
16747 interworking between Arm and Thumb functions to work
16750 THUMB_SET_FUNC (sym, 1);
16752 label_is_thumb_function_name = FALSE;
16755 dwarf2_emit_label (sym);
16759 arm_data_in_code (void)
16761 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16763 *input_line_pointer = '/';
16764 input_line_pointer += 5;
16765 *input_line_pointer = 0;
16773 arm_canonicalize_symbol_name (char * name)
16777 if (thumb_mode && (len = strlen (name)) > 5
16778 && streq (name + len - 5, "/data"))
16779 *(name + len - 5) = 0;
16784 /* Table of all register names defined by default. The user can
16785 define additional names with .req. Note that all register names
16786 should appear in both upper and lowercase variants. Some registers
16787 also have mixed-case names. */
16789 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16790 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16791 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16792 #define REGSET(p,t) \
16793 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16794 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16795 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16796 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16797 #define REGSETH(p,t) \
16798 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16799 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16800 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16801 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16802 #define REGSET2(p,t) \
16803 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16804 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16805 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16806 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16807 #define SPLRBANK(base,bank,t) \
16808 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16809 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16810 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16811 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16812 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16813 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16815 static const struct reg_entry reg_names[] =
16817 /* ARM integer registers. */
16818 REGSET(r, RN), REGSET(R, RN),
16820 /* ATPCS synonyms. */
16821 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16822 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16823 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16825 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16826 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16827 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16829 /* Well-known aliases. */
16830 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16831 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16833 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16834 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16836 /* Coprocessor numbers. */
16837 REGSET(p, CP), REGSET(P, CP),
16839 /* Coprocessor register numbers. The "cr" variants are for backward
16841 REGSET(c, CN), REGSET(C, CN),
16842 REGSET(cr, CN), REGSET(CR, CN),
16844 /* ARM banked registers. */
16845 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16846 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16847 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16848 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16849 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16850 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16851 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16853 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16854 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16855 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16856 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16857 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16858 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16859 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16860 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16862 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16863 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16864 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16865 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16866 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16867 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16868 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16869 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16870 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16872 /* FPA registers. */
16873 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16874 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16876 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16877 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16879 /* VFP SP registers. */
16880 REGSET(s,VFS), REGSET(S,VFS),
16881 REGSETH(s,VFS), REGSETH(S,VFS),
16883 /* VFP DP Registers. */
16884 REGSET(d,VFD), REGSET(D,VFD),
16885 /* Extra Neon DP registers. */
16886 REGSETH(d,VFD), REGSETH(D,VFD),
16888 /* Neon QP registers. */
16889 REGSET2(q,NQ), REGSET2(Q,NQ),
16891 /* VFP control registers. */
16892 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16893 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16894 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16895 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16896 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16897 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16899 /* Maverick DSP coprocessor registers. */
16900 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16901 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16903 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16904 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16905 REGDEF(dspsc,0,DSPSC),
16907 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16908 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16909 REGDEF(DSPSC,0,DSPSC),
16911 /* iWMMXt data registers - p0, c0-15. */
16912 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16914 /* iWMMXt control registers - p1, c0-3. */
16915 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16916 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16917 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16918 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16920 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16921 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16922 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16923 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16924 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16926 /* XScale accumulator registers. */
16927 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16933 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16934 within psr_required_here. */
16935 static const struct asm_psr psrs[] =
16937 /* Backward compatibility notation. Note that "all" is no longer
16938 truly all possible PSR bits. */
16939 {"all", PSR_c | PSR_f},
16943 /* Individual flags. */
16949 /* Combinations of flags. */
16950 {"fs", PSR_f | PSR_s},
16951 {"fx", PSR_f | PSR_x},
16952 {"fc", PSR_f | PSR_c},
16953 {"sf", PSR_s | PSR_f},
16954 {"sx", PSR_s | PSR_x},
16955 {"sc", PSR_s | PSR_c},
16956 {"xf", PSR_x | PSR_f},
16957 {"xs", PSR_x | PSR_s},
16958 {"xc", PSR_x | PSR_c},
16959 {"cf", PSR_c | PSR_f},
16960 {"cs", PSR_c | PSR_s},
16961 {"cx", PSR_c | PSR_x},
16962 {"fsx", PSR_f | PSR_s | PSR_x},
16963 {"fsc", PSR_f | PSR_s | PSR_c},
16964 {"fxs", PSR_f | PSR_x | PSR_s},
16965 {"fxc", PSR_f | PSR_x | PSR_c},
16966 {"fcs", PSR_f | PSR_c | PSR_s},
16967 {"fcx", PSR_f | PSR_c | PSR_x},
16968 {"sfx", PSR_s | PSR_f | PSR_x},
16969 {"sfc", PSR_s | PSR_f | PSR_c},
16970 {"sxf", PSR_s | PSR_x | PSR_f},
16971 {"sxc", PSR_s | PSR_x | PSR_c},
16972 {"scf", PSR_s | PSR_c | PSR_f},
16973 {"scx", PSR_s | PSR_c | PSR_x},
16974 {"xfs", PSR_x | PSR_f | PSR_s},
16975 {"xfc", PSR_x | PSR_f | PSR_c},
16976 {"xsf", PSR_x | PSR_s | PSR_f},
16977 {"xsc", PSR_x | PSR_s | PSR_c},
16978 {"xcf", PSR_x | PSR_c | PSR_f},
16979 {"xcs", PSR_x | PSR_c | PSR_s},
16980 {"cfs", PSR_c | PSR_f | PSR_s},
16981 {"cfx", PSR_c | PSR_f | PSR_x},
16982 {"csf", PSR_c | PSR_s | PSR_f},
16983 {"csx", PSR_c | PSR_s | PSR_x},
16984 {"cxf", PSR_c | PSR_x | PSR_f},
16985 {"cxs", PSR_c | PSR_x | PSR_s},
16986 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16987 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16988 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16989 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16990 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16991 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16992 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16993 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16994 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16995 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16996 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16997 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16998 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16999 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17000 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17001 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17002 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17003 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17004 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17005 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17006 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17007 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17008 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17009 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17012 /* Table of V7M psr names. */
17013 static const struct asm_psr v7m_psrs[] =
17015 {"apsr", 0 }, {"APSR", 0 },
17016 {"iapsr", 1 }, {"IAPSR", 1 },
17017 {"eapsr", 2 }, {"EAPSR", 2 },
17018 {"psr", 3 }, {"PSR", 3 },
17019 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17020 {"ipsr", 5 }, {"IPSR", 5 },
17021 {"epsr", 6 }, {"EPSR", 6 },
17022 {"iepsr", 7 }, {"IEPSR", 7 },
17023 {"msp", 8 }, {"MSP", 8 },
17024 {"psp", 9 }, {"PSP", 9 },
17025 {"primask", 16}, {"PRIMASK", 16},
17026 {"basepri", 17}, {"BASEPRI", 17},
17027 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17028 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17029 {"faultmask", 19}, {"FAULTMASK", 19},
17030 {"control", 20}, {"CONTROL", 20}
17033 /* Table of all shift-in-operand names. */
17034 static const struct asm_shift_name shift_names [] =
17036 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17037 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17038 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17039 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17040 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17041 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17044 /* Table of all explicit relocation names. */
17046 static struct reloc_entry reloc_names[] =
17048 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17049 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17050 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17051 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17052 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17053 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17054 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17055 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17056 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17057 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17058 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17059 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17060 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17061 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17062 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17063 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17064 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17065 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17069 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17070 static const struct asm_cond conds[] =
17074 {"cs", 0x2}, {"hs", 0x2},
17075 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17089 static struct asm_barrier_opt barrier_opt_names[] =
17091 { "sy", 0xf }, { "SY", 0xf },
17092 { "un", 0x7 }, { "UN", 0x7 },
17093 { "st", 0xe }, { "ST", 0xe },
17094 { "unst", 0x6 }, { "UNST", 0x6 },
17095 { "ish", 0xb }, { "ISH", 0xb },
17096 { "sh", 0xb }, { "SH", 0xb },
17097 { "ishst", 0xa }, { "ISHST", 0xa },
17098 { "shst", 0xa }, { "SHST", 0xa },
17099 { "nsh", 0x7 }, { "NSH", 0x7 },
17100 { "nshst", 0x6 }, { "NSHST", 0x6 },
17101 { "osh", 0x3 }, { "OSH", 0x3 },
17102 { "oshst", 0x2 }, { "OSHST", 0x2 }
17105 /* Table of ARM-format instructions. */
17107 /* Macros for gluing together operand strings. N.B. In all cases
17108 other than OPS0, the trailing OP_stop comes from default
17109 zero-initialization of the unspecified elements of the array. */
17110 #define OPS0() { OP_stop, }
17111 #define OPS1(a) { OP_##a, }
17112 #define OPS2(a,b) { OP_##a,OP_##b, }
17113 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17114 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17115 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17116 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17118 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17119 This is useful when mixing operands for ARM and THUMB, i.e. using the
17120 MIX_ARM_THUMB_OPERANDS macro.
17121 In order to use these macros, prefix the number of operands with _
17123 #define OPS_1(a) { a, }
17124 #define OPS_2(a,b) { a,b, }
17125 #define OPS_3(a,b,c) { a,b,c, }
17126 #define OPS_4(a,b,c,d) { a,b,c,d, }
17127 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17128 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17130 /* These macros abstract out the exact format of the mnemonic table and
17131 save some repeated characters. */
17133 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17134 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17135 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17136 THUMB_VARIANT, do_##ae, do_##te }
17138 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17139 a T_MNEM_xyz enumerator. */
17140 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17141 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17142 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17143 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17145 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17146 infix after the third character. */
17147 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17148 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17149 THUMB_VARIANT, do_##ae, do_##te }
17150 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17151 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17152 THUMB_VARIANT, do_##ae, do_##te }
17153 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17154 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17155 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17156 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17157 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17158 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17159 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17160 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17162 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17163 appear in the condition table. */
17164 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17165 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17166 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17168 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17169 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17170 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17171 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17172 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17173 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17174 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17175 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17176 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17177 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17178 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17179 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17180 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17181 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17182 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17183 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17184 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17185 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17186 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17187 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17189 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17190 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17191 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17192 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17194 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17195 field is still 0xE. Many of the Thumb variants can be executed
17196 conditionally, so this is checked separately. */
17197 #define TUE(mnem, op, top, nops, ops, ae, te) \
17198 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17199 THUMB_VARIANT, do_##ae, do_##te }
17201 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17202 condition code field. */
17203 #define TUF(mnem, op, top, nops, ops, ae, te) \
17204 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17205 THUMB_VARIANT, do_##ae, do_##te }
17207 /* ARM-only variants of all the above. */
17208 #define CE(mnem, op, nops, ops, ae) \
17209 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17211 #define C3(mnem, op, nops, ops, ae) \
17212 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17214 /* Legacy mnemonics that always have conditional infix after the third
17216 #define CL(mnem, op, nops, ops, ae) \
17217 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17218 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17220 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17221 #define cCE(mnem, op, nops, ops, ae) \
17222 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17224 /* Legacy coprocessor instructions where conditional infix and conditional
17225 suffix are ambiguous. For consistency this includes all FPA instructions,
17226 not just the potentially ambiguous ones. */
17227 #define cCL(mnem, op, nops, ops, ae) \
17228 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17229 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17231 /* Coprocessor, takes either a suffix or a position-3 infix
17232 (for an FPA corner case). */
17233 #define C3E(mnem, op, nops, ops, ae) \
17234 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17235 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17237 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17238 { m1 #m2 m3, OPS##nops ops, \
17239 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17240 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17242 #define CM(m1, m2, op, nops, ops, ae) \
17243 xCM_ (m1, , m2, op, nops, ops, ae), \
17244 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17245 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17246 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17247 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17248 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17249 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17250 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17251 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17252 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17253 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17254 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17255 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17256 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17257 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17258 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17259 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17260 xCM_ (m1, le, m2, op, nops, ops, ae), \
17261 xCM_ (m1, al, m2, op, nops, ops, ae)
17263 #define UE(mnem, op, nops, ops, ae) \
17264 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17266 #define UF(mnem, op, nops, ops, ae) \
17267 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17269 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17270 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17271 use the same encoding function for each. */
17272 #define NUF(mnem, op, nops, ops, enc) \
17273 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17274 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17276 /* Neon data processing, version which indirects through neon_enc_tab for
17277 the various overloaded versions of opcodes. */
17278 #define nUF(mnem, op, nops, ops, enc) \
17279 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17280 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17282 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17284 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17285 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17286 THUMB_VARIANT, do_##enc, do_##enc }
17288 #define NCE(mnem, op, nops, ops, enc) \
17289 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17291 #define NCEF(mnem, op, nops, ops, enc) \
17292 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17294 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17295 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17296 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17297 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17299 #define nCE(mnem, op, nops, ops, enc) \
17300 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17302 #define nCEF(mnem, op, nops, ops, enc) \
17303 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17307 static const struct asm_opcode insns[] =
17309 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17310 #define THUMB_VARIANT &arm_ext_v4t
17311 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17312 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17313 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17314 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17315 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17316 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17317 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17318 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17319 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17320 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17321 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17322 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17323 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17324 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17325 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17326 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17328 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17329 for setting PSR flag bits. They are obsolete in V6 and do not
17330 have Thumb equivalents. */
17331 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17332 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17333 CL("tstp", 110f000, 2, (RR, SH), cmp),
17334 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17335 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17336 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17337 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17338 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17339 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17341 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17342 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17343 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17344 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17346 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17347 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17348 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17350 OP_ADDRGLDR),ldst, t_ldst),
17351 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17353 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17354 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17355 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17356 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17357 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17358 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17360 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17361 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17362 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17363 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17366 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17367 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17368 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17370 /* Thumb-compatibility pseudo ops. */
17371 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17372 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17373 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17374 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17375 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17376 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17377 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17378 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17379 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17380 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17381 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17382 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17384 /* These may simplify to neg. */
17385 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17386 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17388 #undef THUMB_VARIANT
17389 #define THUMB_VARIANT & arm_ext_v6
17391 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17393 /* V1 instructions with no Thumb analogue prior to V6T2. */
17394 #undef THUMB_VARIANT
17395 #define THUMB_VARIANT & arm_ext_v6t2
17397 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17398 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17399 CL("teqp", 130f000, 2, (RR, SH), cmp),
17401 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17402 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17403 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17404 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17406 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17407 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17409 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17410 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17412 /* V1 instructions with no Thumb analogue at all. */
17413 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17414 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17416 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17417 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17418 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17419 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17420 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17421 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17422 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17423 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17426 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17427 #undef THUMB_VARIANT
17428 #define THUMB_VARIANT & arm_ext_v4t
17430 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17431 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17433 #undef THUMB_VARIANT
17434 #define THUMB_VARIANT & arm_ext_v6t2
17436 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17437 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17439 /* Generic coprocessor instructions. */
17440 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17441 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17442 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17443 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17444 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17445 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17446 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17449 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17451 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17452 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17455 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17456 #undef THUMB_VARIANT
17457 #define THUMB_VARIANT & arm_ext_msr
17459 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17460 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17463 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17464 #undef THUMB_VARIANT
17465 #define THUMB_VARIANT & arm_ext_v6t2
17467 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17468 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17469 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17470 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17471 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17472 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17473 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17474 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17477 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17478 #undef THUMB_VARIANT
17479 #define THUMB_VARIANT & arm_ext_v4t
17481 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17482 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17483 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17484 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17485 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17486 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17489 #define ARM_VARIANT & arm_ext_v4t_5
17491 /* ARM Architecture 4T. */
17492 /* Note: bx (and blx) are required on V5, even if the processor does
17493 not support Thumb. */
17494 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17497 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17498 #undef THUMB_VARIANT
17499 #define THUMB_VARIANT & arm_ext_v5t
17501 /* Note: blx has 2 variants; the .value coded here is for
17502 BLX(2). Only this variant has conditional execution. */
17503 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17504 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17506 #undef THUMB_VARIANT
17507 #define THUMB_VARIANT & arm_ext_v6t2
17509 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17510 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17511 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17512 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17513 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17514 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17515 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17516 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17519 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17520 #undef THUMB_VARIANT
17521 #define THUMB_VARIANT &arm_ext_v5exp
17523 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17524 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17525 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17526 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17528 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17529 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17531 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17532 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17533 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17534 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17536 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17537 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17538 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17539 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17541 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17542 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17544 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17545 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17546 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17547 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17550 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17551 #undef THUMB_VARIANT
17552 #define THUMB_VARIANT &arm_ext_v6t2
17554 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17555 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17557 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17558 ADDRGLDRS), ldrd, t_ldstd),
17560 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17561 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17564 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17566 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17569 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17570 #undef THUMB_VARIANT
17571 #define THUMB_VARIANT & arm_ext_v6
17573 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17574 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17575 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17576 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17577 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17578 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17579 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17580 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17581 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17582 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17584 #undef THUMB_VARIANT
17585 #define THUMB_VARIANT & arm_ext_v6t2
17587 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17588 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17590 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17591 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17593 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17594 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17596 /* ARM V6 not included in V7M. */
17597 #undef THUMB_VARIANT
17598 #define THUMB_VARIANT & arm_ext_v6_notm
17599 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17600 UF(rfeib, 9900a00, 1, (RRw), rfe),
17601 UF(rfeda, 8100a00, 1, (RRw), rfe),
17602 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17603 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17604 UF(rfefa, 9900a00, 1, (RRw), rfe),
17605 UF(rfeea, 8100a00, 1, (RRw), rfe),
17606 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17607 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17608 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17609 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17610 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17612 /* ARM V6 not included in V7M (eg. integer SIMD). */
17613 #undef THUMB_VARIANT
17614 #define THUMB_VARIANT & arm_ext_v6_dsp
17615 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17616 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17617 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17618 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17619 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17620 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17621 /* Old name for QASX. */
17622 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17623 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17624 /* Old name for QSAX. */
17625 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17626 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17627 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17628 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17629 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17630 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17631 /* Old name for SASX. */
17632 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17633 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17634 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17635 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17636 /* Old name for SHASX. */
17637 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17638 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17639 /* Old name for SHSAX. */
17640 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17641 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17642 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17643 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17644 /* Old name for SSAX. */
17645 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17646 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17647 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17648 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17649 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17650 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17651 /* Old name for UASX. */
17652 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17653 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17654 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17655 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17656 /* Old name for UHASX. */
17657 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17658 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17659 /* Old name for UHSAX. */
17660 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17661 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17662 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17663 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17664 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17665 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17666 /* Old name for UQASX. */
17667 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17668 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17669 /* Old name for UQSAX. */
17670 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17671 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17672 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17673 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17674 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17675 /* Old name for USAX. */
17676 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17677 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17678 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17679 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17680 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17681 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17682 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17683 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17684 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17685 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17686 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17687 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17688 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17689 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17690 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17691 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17692 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17693 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17694 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17695 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17696 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17697 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17698 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17699 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17700 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17701 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17702 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17703 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17704 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17705 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17706 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17707 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17708 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17709 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17712 #define ARM_VARIANT & arm_ext_v6k
17713 #undef THUMB_VARIANT
17714 #define THUMB_VARIANT & arm_ext_v6k
17716 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17717 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17718 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17719 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17721 #undef THUMB_VARIANT
17722 #define THUMB_VARIANT & arm_ext_v6_notm
17723 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17725 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17726 RRnpcb), strexd, t_strexd),
17728 #undef THUMB_VARIANT
17729 #define THUMB_VARIANT & arm_ext_v6t2
17730 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17732 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17734 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17736 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17738 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17741 #define ARM_VARIANT & arm_ext_sec
17742 #undef THUMB_VARIANT
17743 #define THUMB_VARIANT & arm_ext_sec
17745 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17748 #define ARM_VARIANT & arm_ext_virt
17749 #undef THUMB_VARIANT
17750 #define THUMB_VARIANT & arm_ext_virt
17752 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17753 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17756 #define ARM_VARIANT & arm_ext_v6t2
17757 #undef THUMB_VARIANT
17758 #define THUMB_VARIANT & arm_ext_v6t2
17760 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17761 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17762 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17763 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17765 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17766 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17767 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17768 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17770 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17771 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17772 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17773 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17775 /* Thumb-only instructions. */
17777 #define ARM_VARIANT NULL
17778 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17779 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17781 /* ARM does not really have an IT instruction, so always allow it.
17782 The opcode is copied from Thumb in order to allow warnings in
17783 -mimplicit-it=[never | arm] modes. */
17785 #define ARM_VARIANT & arm_ext_v1
17787 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17788 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17789 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17790 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17791 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17792 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17793 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17794 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17795 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17796 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17797 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17798 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17799 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17800 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17801 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17802 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17803 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17804 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17806 /* Thumb2 only instructions. */
17808 #define ARM_VARIANT NULL
17810 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17811 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17812 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17813 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17814 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17815 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17817 /* Hardware division instructions. */
17819 #define ARM_VARIANT & arm_ext_adiv
17820 #undef THUMB_VARIANT
17821 #define THUMB_VARIANT & arm_ext_div
17823 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17824 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17826 /* ARM V6M/V7 instructions. */
17828 #define ARM_VARIANT & arm_ext_barrier
17829 #undef THUMB_VARIANT
17830 #define THUMB_VARIANT & arm_ext_barrier
17832 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17833 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17834 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17836 /* ARM V7 instructions. */
17838 #define ARM_VARIANT & arm_ext_v7
17839 #undef THUMB_VARIANT
17840 #define THUMB_VARIANT & arm_ext_v7
17842 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17843 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17846 #define ARM_VARIANT & arm_ext_mp
17847 #undef THUMB_VARIANT
17848 #define THUMB_VARIANT & arm_ext_mp
17850 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17853 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17855 cCE("wfs", e200110, 1, (RR), rd),
17856 cCE("rfs", e300110, 1, (RR), rd),
17857 cCE("wfc", e400110, 1, (RR), rd),
17858 cCE("rfc", e500110, 1, (RR), rd),
17860 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17861 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17862 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17863 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17865 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17866 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17867 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17868 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17870 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17871 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17872 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17873 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17874 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17875 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17876 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17877 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17878 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17879 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17880 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17881 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17883 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17884 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17885 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17886 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17887 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17888 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17889 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17890 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17891 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17892 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17893 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17894 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17896 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17897 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17898 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17899 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17900 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17901 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17902 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17903 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17904 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17905 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17906 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17907 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17909 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17910 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17911 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17912 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17913 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17914 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17915 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17916 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17917 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17918 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17919 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17920 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17922 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17923 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17924 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17925 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17926 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17927 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17928 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17929 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17930 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17931 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17932 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17933 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17935 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17936 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17937 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17938 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17939 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17940 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17941 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17942 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17943 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17944 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17945 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17946 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17948 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17949 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17950 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17951 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17952 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17953 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17954 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17955 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17956 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17957 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17958 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17959 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17961 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17962 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17963 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17964 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17965 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17966 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17967 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17968 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17969 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17970 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17971 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17972 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17974 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17975 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17976 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17977 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17978 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17979 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17980 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17981 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17982 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17983 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17984 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17985 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17987 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17988 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17989 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17990 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17991 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17992 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17993 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17994 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17995 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17996 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17997 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17998 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18000 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18001 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18002 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18003 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18004 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18005 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18006 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18007 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18008 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18009 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18010 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18011 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18013 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18014 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18015 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18016 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18017 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18018 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18019 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18020 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18021 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18022 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18023 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18024 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18026 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18027 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18028 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18029 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18030 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18031 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18032 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18033 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18034 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18035 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18036 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18037 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18039 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18040 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18041 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18042 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18043 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18044 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18045 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18046 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18047 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18048 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18049 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18050 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18052 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18053 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18054 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18055 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18056 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18057 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18058 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18059 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18060 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18061 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18062 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18063 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18065 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18066 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18067 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18068 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18069 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18070 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18071 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18072 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18073 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18074 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18075 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18076 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18078 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18079 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18080 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18082 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18083 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18091 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18092 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18093 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18094 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18095 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18096 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18097 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18098 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18099 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18100 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18101 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18102 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18104 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18105 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18106 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18107 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18108 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18109 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18110 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18111 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18112 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18113 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18114 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18115 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18117 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18118 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18119 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18120 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18121 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18122 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18123 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18124 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18125 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18126 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18127 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18128 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18130 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18131 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18132 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18133 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18134 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18135 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18136 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18137 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18138 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18139 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18140 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18141 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18143 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18144 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18145 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18146 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18147 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18148 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18149 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18150 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18151 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18152 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18153 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18154 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18156 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18157 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18158 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18159 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18160 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18161 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18162 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18163 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18164 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18165 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18166 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18167 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18169 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18170 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18171 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18172 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18173 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18174 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18175 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18176 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18177 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18178 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18179 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18180 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18182 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18183 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18184 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18185 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18186 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18187 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18188 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18189 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18190 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18191 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18192 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18193 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18195 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18196 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18197 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18198 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18199 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18200 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18201 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18202 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18203 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18204 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18205 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18206 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18208 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18209 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18210 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18211 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18212 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18213 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18214 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18215 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18216 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18217 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18218 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18219 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18221 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18222 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18223 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18224 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18225 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18226 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18227 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18228 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18229 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18230 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18231 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18232 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18234 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18235 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18236 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18237 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18238 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18239 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18240 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18241 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18242 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18243 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18244 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18245 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18247 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18248 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18249 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18250 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18252 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18253 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18254 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18255 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18256 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18257 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18258 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18259 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18260 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18261 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18262 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18263 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18265 /* The implementation of the FIX instruction is broken on some
18266 assemblers, in that it accepts a precision specifier as well as a
18267 rounding specifier, despite the fact that this is meaningless.
18268 To be more compatible, we accept it as well, though of course it
18269 does not set any bits. */
18270 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18271 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18272 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18273 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18274 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18275 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18276 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18277 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18278 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18279 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18280 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18281 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18282 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18284 /* Instructions that were new with the real FPA, call them V2. */
18286 #define ARM_VARIANT & fpu_fpa_ext_v2
18288 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18289 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18290 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18291 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18292 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18293 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18296 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18298 /* Moves and type conversions. */
18299 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18300 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18301 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18302 cCE("fmstat", ef1fa10, 0, (), noargs),
18303 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
18304 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
18305 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18306 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18307 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18308 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18309 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18310 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18311 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18312 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18314 /* Memory operations. */
18315 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18316 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18317 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18318 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18319 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18320 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18321 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18322 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18323 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18324 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18325 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18326 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18327 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18328 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18329 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18330 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18331 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18332 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18334 /* Monadic operations. */
18335 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18336 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18337 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18339 /* Dyadic operations. */
18340 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18341 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18342 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18343 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18344 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18345 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18346 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18347 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18348 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18351 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18352 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18353 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18354 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18356 /* Double precision load/store are still present on single precision
18357 implementations. */
18358 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18359 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18360 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18361 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18362 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18363 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18364 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18365 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18366 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18367 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18370 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18372 /* Moves and type conversions. */
18373 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18374 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18375 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18376 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18377 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18378 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18379 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18380 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18381 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18382 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18383 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18384 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18385 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18387 /* Monadic operations. */
18388 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18389 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18390 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18392 /* Dyadic operations. */
18393 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18394 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18395 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18396 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18397 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18398 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18399 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18400 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18401 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18404 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18405 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18406 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18407 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18410 #define ARM_VARIANT & fpu_vfp_ext_v2
18412 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18413 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18414 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18415 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18417 /* Instructions which may belong to either the Neon or VFP instruction sets.
18418 Individual encoder functions perform additional architecture checks. */
18420 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18421 #undef THUMB_VARIANT
18422 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18424 /* These mnemonics are unique to VFP. */
18425 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18426 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18427 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18428 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18429 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18430 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18431 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18432 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18433 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18434 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18436 /* Mnemonics shared by Neon and VFP. */
18437 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18438 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18439 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18441 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18442 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18444 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18445 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18447 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18448 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18449 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18450 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18451 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18452 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18453 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18454 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18456 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18457 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18458 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18459 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18462 /* NOTE: All VMOV encoding is special-cased! */
18463 NCE(vmov, 0, 1, (VMOV), neon_mov),
18464 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18466 #undef THUMB_VARIANT
18467 #define THUMB_VARIANT & fpu_neon_ext_v1
18469 #define ARM_VARIANT & fpu_neon_ext_v1
18471 /* Data processing with three registers of the same length. */
18472 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18473 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18474 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18475 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18476 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18477 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18478 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18479 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18480 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18481 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18482 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18483 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18484 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18485 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18486 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18487 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18488 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18489 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18490 /* If not immediate, fall back to neon_dyadic_i64_su.
18491 shl_imm should accept I8 I16 I32 I64,
18492 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18493 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18494 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18495 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18496 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18497 /* Logic ops, types optional & ignored. */
18498 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18499 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18500 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18501 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18502 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18503 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18504 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18505 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18506 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18507 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18508 /* Bitfield ops, untyped. */
18509 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18510 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18511 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18512 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18513 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18514 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18515 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18516 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18517 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18518 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18519 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18520 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18521 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18522 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18523 back to neon_dyadic_if_su. */
18524 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18525 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18526 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18527 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18528 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18529 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18530 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18531 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18532 /* Comparison. Type I8 I16 I32 F32. */
18533 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18534 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18535 /* As above, D registers only. */
18536 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18537 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18538 /* Int and float variants, signedness unimportant. */
18539 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18540 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18541 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18542 /* Add/sub take types I8 I16 I32 I64 F32. */
18543 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18544 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18545 /* vtst takes sizes 8, 16, 32. */
18546 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18547 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18548 /* VMUL takes I8 I16 I32 F32 P8. */
18549 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18550 /* VQD{R}MULH takes S16 S32. */
18551 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18552 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18553 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18554 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18555 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18556 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18557 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18558 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18559 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18560 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18561 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18562 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18563 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18564 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18565 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18566 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18568 /* Two address, int/float. Types S8 S16 S32 F32. */
18569 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18570 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18572 /* Data processing with two registers and a shift amount. */
18573 /* Right shifts, and variants with rounding.
18574 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18575 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18576 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18577 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18578 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18579 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18580 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18581 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18582 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18583 /* Shift and insert. Sizes accepted 8 16 32 64. */
18584 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18585 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18586 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18587 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18588 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18589 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18590 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18591 /* Right shift immediate, saturating & narrowing, with rounding variants.
18592 Types accepted S16 S32 S64 U16 U32 U64. */
18593 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18594 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18595 /* As above, unsigned. Types accepted S16 S32 S64. */
18596 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18597 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18598 /* Right shift narrowing. Types accepted I16 I32 I64. */
18599 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18600 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18601 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18602 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18603 /* CVT with optional immediate for fixed-point variant. */
18604 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18606 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18607 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18609 /* Data processing, three registers of different lengths. */
18610 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18611 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18612 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18613 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18614 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18615 /* If not scalar, fall back to neon_dyadic_long.
18616 Vector types as above, scalar types S16 S32 U16 U32. */
18617 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18618 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18619 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18620 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18621 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18622 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18623 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18624 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18625 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18626 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18627 /* Saturating doubling multiplies. Types S16 S32. */
18628 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18629 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18630 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18631 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18632 S16 S32 U16 U32. */
18633 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18635 /* Extract. Size 8. */
18636 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18637 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18639 /* Two registers, miscellaneous. */
18640 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18641 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18642 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18643 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18644 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18645 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18646 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18647 /* Vector replicate. Sizes 8 16 32. */
18648 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18649 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18650 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18651 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18652 /* VMOVN. Types I16 I32 I64. */
18653 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18654 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18655 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18656 /* VQMOVUN. Types S16 S32 S64. */
18657 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18658 /* VZIP / VUZP. Sizes 8 16 32. */
18659 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18660 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18661 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18662 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18663 /* VQABS / VQNEG. Types S8 S16 S32. */
18664 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18665 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18666 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18667 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18668 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18669 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18670 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18671 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18672 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18673 /* Reciprocal estimates. Types U32 F32. */
18674 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18675 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18676 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18677 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18678 /* VCLS. Types S8 S16 S32. */
18679 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18680 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18681 /* VCLZ. Types I8 I16 I32. */
18682 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18683 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18684 /* VCNT. Size 8. */
18685 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18686 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18687 /* Two address, untyped. */
18688 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18689 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18690 /* VTRN. Sizes 8 16 32. */
18691 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18692 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18694 /* Table lookup. Size 8. */
18695 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18696 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18698 #undef THUMB_VARIANT
18699 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18701 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18703 /* Neon element/structure load/store. */
18704 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18705 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18706 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18707 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18708 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18709 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18710 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18711 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18713 #undef THUMB_VARIANT
18714 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18716 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18717 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18718 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18719 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18720 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18721 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18722 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18723 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18724 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18725 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18727 #undef THUMB_VARIANT
18728 #define THUMB_VARIANT & fpu_vfp_ext_v3
18730 #define ARM_VARIANT & fpu_vfp_ext_v3
18732 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18733 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18734 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18735 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18736 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18737 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18738 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18739 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18740 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18743 #define ARM_VARIANT &fpu_vfp_ext_fma
18744 #undef THUMB_VARIANT
18745 #define THUMB_VARIANT &fpu_vfp_ext_fma
18746 /* Mnemonics shared by Neon and VFP. These are included in the
18747 VFP FMA variant; NEON and VFP FMA always includes the NEON
18748 FMA instructions. */
18749 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18750 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18751 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18752 the v form should always be used. */
18753 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18754 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18755 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18756 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18757 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18758 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18760 #undef THUMB_VARIANT
18762 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18764 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18765 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18766 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18767 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18768 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18769 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18770 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18771 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18774 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18776 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18777 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18778 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18779 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18780 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18781 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18782 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18783 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18784 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18785 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18786 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18787 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18788 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18789 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18790 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18791 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18792 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18793 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18794 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18795 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18796 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18797 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18798 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18799 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18800 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18801 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18802 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18803 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18804 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18805 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18806 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18807 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18808 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18809 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18810 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18811 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18812 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18813 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18818 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18819 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18821 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18822 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18823 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18829 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18830 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18831 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18832 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18833 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18834 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18835 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18836 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18837 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18838 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18839 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18840 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18841 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18842 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18843 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18844 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18845 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18846 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18847 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18848 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18849 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18850 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18851 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18852 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18853 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18854 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18855 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18856 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18857 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18858 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18859 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18860 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18861 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18862 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18863 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18864 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18865 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18866 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18867 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18868 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18869 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18870 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18871 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18872 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18873 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18874 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18875 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18876 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18877 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18878 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18879 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18880 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18881 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18882 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18883 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18884 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18885 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18886 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18887 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18888 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18889 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18890 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18891 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18892 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18893 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18894 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18895 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18896 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18897 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18898 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18899 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18900 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18901 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18902 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18903 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18904 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18905 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18906 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18907 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18908 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18909 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18910 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18911 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18912 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18913 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18914 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18915 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18916 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18917 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18918 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18919 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18920 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18921 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18922 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18923 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18924 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18925 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18926 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18927 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18928 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18929 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18930 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18931 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18932 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18933 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18934 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18935 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18936 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18937 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18940 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18942 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18943 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18944 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18945 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18946 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18947 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18948 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18949 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18950 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18951 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18952 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18953 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18954 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18955 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18956 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18957 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18958 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18959 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18960 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18961 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18962 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18963 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18964 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18965 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18966 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18967 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18968 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18969 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18970 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18971 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18972 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18973 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18974 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18975 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18976 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18977 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18978 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18979 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18980 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18981 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18982 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18983 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18984 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18985 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18986 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18987 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18988 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18989 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18990 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18991 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18992 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18993 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18994 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18995 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18996 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18997 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18998 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19001 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19003 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19004 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19005 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19006 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19007 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19008 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19009 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19010 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19011 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19012 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19013 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19014 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19015 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19016 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19017 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19018 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19019 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19020 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19021 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19022 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19023 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19024 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19025 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19026 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19027 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19028 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19029 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19030 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19031 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19032 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19033 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19034 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19035 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19036 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19037 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19038 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19039 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19040 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19041 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19042 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19043 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19044 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19045 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19046 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19047 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19048 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19049 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19050 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19051 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19052 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19053 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19054 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19055 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19056 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19057 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19058 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19059 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19060 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19061 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19062 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19063 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19064 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19065 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19066 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19067 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19068 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19069 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19070 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19071 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19072 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19073 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19074 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19075 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19076 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19077 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19078 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19081 #undef THUMB_VARIANT
19108 /* MD interface: bits in the object file. */
19110 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19111 for use in the a.out file, and stores them in the array pointed to by buf.
19112 This knows about the endian-ness of the target machine and does
19113 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19114 2 (short) and 4 (long) Floating numbers are put out as a series of
19115 LITTLENUMS (shorts, here at least). */
19118 md_number_to_chars (char * buf, valueT val, int n)
19120 if (target_big_endian)
19121 number_to_chars_bigendian (buf, val, n);
19123 number_to_chars_littleendian (buf, val, n);
19127 md_chars_to_number (char * buf, int n)
19130 unsigned char * where = (unsigned char *) buf;
19132 if (target_big_endian)
19137 result |= (*where++ & 255);
19145 result |= (where[n] & 255);
19152 /* MD interface: Sections. */
19154 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19155 that an rs_machine_dependent frag may reach. */
19158 arm_frag_max_var (fragS *fragp)
19160 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19161 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19163 Note that we generate relaxable instructions even for cases that don't
19164 really need it, like an immediate that's a trivial constant. So we're
19165 overestimating the instruction size for some of those cases. Rather
19166 than putting more intelligence here, it would probably be better to
19167 avoid generating a relaxation frag in the first place when it can be
19168 determined up front that a short instruction will suffice. */
19170 gas_assert (fragp->fr_type == rs_machine_dependent);
19174 /* Estimate the size of a frag before relaxing. Assume everything fits in
19178 md_estimate_size_before_relax (fragS * fragp,
19179 segT segtype ATTRIBUTE_UNUSED)
19185 /* Convert a machine dependent frag. */
19188 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19190 unsigned long insn;
19191 unsigned long old_op;
19199 buf = fragp->fr_literal + fragp->fr_fix;
19201 old_op = bfd_get_16(abfd, buf);
19202 if (fragp->fr_symbol)
19204 exp.X_op = O_symbol;
19205 exp.X_add_symbol = fragp->fr_symbol;
19209 exp.X_op = O_constant;
19211 exp.X_add_number = fragp->fr_offset;
19212 opcode = fragp->fr_subtype;
19215 case T_MNEM_ldr_pc:
19216 case T_MNEM_ldr_pc2:
19217 case T_MNEM_ldr_sp:
19218 case T_MNEM_str_sp:
19225 if (fragp->fr_var == 4)
19227 insn = THUMB_OP32 (opcode);
19228 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19230 insn |= (old_op & 0x700) << 4;
19234 insn |= (old_op & 7) << 12;
19235 insn |= (old_op & 0x38) << 13;
19237 insn |= 0x00000c00;
19238 put_thumb32_insn (buf, insn);
19239 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19243 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19245 pc_rel = (opcode == T_MNEM_ldr_pc2);
19248 if (fragp->fr_var == 4)
19250 insn = THUMB_OP32 (opcode);
19251 insn |= (old_op & 0xf0) << 4;
19252 put_thumb32_insn (buf, insn);
19253 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19257 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19258 exp.X_add_number -= 4;
19266 if (fragp->fr_var == 4)
19268 int r0off = (opcode == T_MNEM_mov
19269 || opcode == T_MNEM_movs) ? 0 : 8;
19270 insn = THUMB_OP32 (opcode);
19271 insn = (insn & 0xe1ffffff) | 0x10000000;
19272 insn |= (old_op & 0x700) << r0off;
19273 put_thumb32_insn (buf, insn);
19274 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19278 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19283 if (fragp->fr_var == 4)
19285 insn = THUMB_OP32(opcode);
19286 put_thumb32_insn (buf, insn);
19287 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19290 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19294 if (fragp->fr_var == 4)
19296 insn = THUMB_OP32(opcode);
19297 insn |= (old_op & 0xf00) << 14;
19298 put_thumb32_insn (buf, insn);
19299 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19302 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19305 case T_MNEM_add_sp:
19306 case T_MNEM_add_pc:
19307 case T_MNEM_inc_sp:
19308 case T_MNEM_dec_sp:
19309 if (fragp->fr_var == 4)
19311 /* ??? Choose between add and addw. */
19312 insn = THUMB_OP32 (opcode);
19313 insn |= (old_op & 0xf0) << 4;
19314 put_thumb32_insn (buf, insn);
19315 if (opcode == T_MNEM_add_pc)
19316 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19318 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19321 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19329 if (fragp->fr_var == 4)
19331 insn = THUMB_OP32 (opcode);
19332 insn |= (old_op & 0xf0) << 4;
19333 insn |= (old_op & 0xf) << 16;
19334 put_thumb32_insn (buf, insn);
19335 if (insn & (1 << 20))
19336 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19338 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19341 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19347 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19348 (enum bfd_reloc_code_real) reloc_type);
19349 fixp->fx_file = fragp->fr_file;
19350 fixp->fx_line = fragp->fr_line;
19351 fragp->fr_fix += fragp->fr_var;
19354 /* Return the size of a relaxable immediate operand instruction.
19355 SHIFT and SIZE specify the form of the allowable immediate. */
19357 relax_immediate (fragS *fragp, int size, int shift)
19363 /* ??? Should be able to do better than this. */
19364 if (fragp->fr_symbol)
19367 low = (1 << shift) - 1;
19368 mask = (1 << (shift + size)) - (1 << shift);
19369 offset = fragp->fr_offset;
19370 /* Force misaligned offsets to 32-bit variant. */
19373 if (offset & ~mask)
19378 /* Get the address of a symbol during relaxation. */
19380 relaxed_symbol_addr (fragS *fragp, long stretch)
19386 sym = fragp->fr_symbol;
19387 sym_frag = symbol_get_frag (sym);
19388 know (S_GET_SEGMENT (sym) != absolute_section
19389 || sym_frag == &zero_address_frag);
19390 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19392 /* If frag has yet to be reached on this pass, assume it will
19393 move by STRETCH just as we did. If this is not so, it will
19394 be because some frag between grows, and that will force
19398 && sym_frag->relax_marker != fragp->relax_marker)
19402 /* Adjust stretch for any alignment frag. Note that if have
19403 been expanding the earlier code, the symbol may be
19404 defined in what appears to be an earlier frag. FIXME:
19405 This doesn't handle the fr_subtype field, which specifies
19406 a maximum number of bytes to skip when doing an
19408 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19410 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19413 stretch = - ((- stretch)
19414 & ~ ((1 << (int) f->fr_offset) - 1));
19416 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19428 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19431 relax_adr (fragS *fragp, asection *sec, long stretch)
19436 /* Assume worst case for symbols not known to be in the same section. */
19437 if (fragp->fr_symbol == NULL
19438 || !S_IS_DEFINED (fragp->fr_symbol)
19439 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19440 || S_IS_WEAK (fragp->fr_symbol))
19443 val = relaxed_symbol_addr (fragp, stretch);
19444 addr = fragp->fr_address + fragp->fr_fix;
19445 addr = (addr + 4) & ~3;
19446 /* Force misaligned targets to 32-bit variant. */
19450 if (val < 0 || val > 1020)
19455 /* Return the size of a relaxable add/sub immediate instruction. */
19457 relax_addsub (fragS *fragp, asection *sec)
19462 buf = fragp->fr_literal + fragp->fr_fix;
19463 op = bfd_get_16(sec->owner, buf);
19464 if ((op & 0xf) == ((op >> 4) & 0xf))
19465 return relax_immediate (fragp, 8, 0);
19467 return relax_immediate (fragp, 3, 0);
19471 /* Return the size of a relaxable branch instruction. BITS is the
19472 size of the offset field in the narrow instruction. */
19475 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19481 /* Assume worst case for symbols not known to be in the same section. */
19482 if (!S_IS_DEFINED (fragp->fr_symbol)
19483 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19484 || S_IS_WEAK (fragp->fr_symbol))
19488 if (S_IS_DEFINED (fragp->fr_symbol)
19489 && ARM_IS_FUNC (fragp->fr_symbol))
19492 /* PR 12532. Global symbols with default visibility might
19493 be preempted, so do not relax relocations to them. */
19494 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19495 && (! S_IS_LOCAL (fragp->fr_symbol)))
19499 val = relaxed_symbol_addr (fragp, stretch);
19500 addr = fragp->fr_address + fragp->fr_fix + 4;
19503 /* Offset is a signed value *2 */
19505 if (val >= limit || val < -limit)
19511 /* Relax a machine dependent frag. This returns the amount by which
19512 the current size of the frag should change. */
19515 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19520 oldsize = fragp->fr_var;
19521 switch (fragp->fr_subtype)
19523 case T_MNEM_ldr_pc2:
19524 newsize = relax_adr (fragp, sec, stretch);
19526 case T_MNEM_ldr_pc:
19527 case T_MNEM_ldr_sp:
19528 case T_MNEM_str_sp:
19529 newsize = relax_immediate (fragp, 8, 2);
19533 newsize = relax_immediate (fragp, 5, 2);
19537 newsize = relax_immediate (fragp, 5, 1);
19541 newsize = relax_immediate (fragp, 5, 0);
19544 newsize = relax_adr (fragp, sec, stretch);
19550 newsize = relax_immediate (fragp, 8, 0);
19553 newsize = relax_branch (fragp, sec, 11, stretch);
19556 newsize = relax_branch (fragp, sec, 8, stretch);
19558 case T_MNEM_add_sp:
19559 case T_MNEM_add_pc:
19560 newsize = relax_immediate (fragp, 8, 2);
19562 case T_MNEM_inc_sp:
19563 case T_MNEM_dec_sp:
19564 newsize = relax_immediate (fragp, 7, 2);
19570 newsize = relax_addsub (fragp, sec);
19576 fragp->fr_var = newsize;
19577 /* Freeze wide instructions that are at or before the same location as
19578 in the previous pass. This avoids infinite loops.
19579 Don't freeze them unconditionally because targets may be artificially
19580 misaligned by the expansion of preceding frags. */
19581 if (stretch <= 0 && newsize > 2)
19583 md_convert_frag (sec->owner, sec, fragp);
19587 return newsize - oldsize;
19590 /* Round up a section size to the appropriate boundary. */
19593 md_section_align (segT segment ATTRIBUTE_UNUSED,
19596 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19597 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19599 /* For a.out, force the section size to be aligned. If we don't do
19600 this, BFD will align it for us, but it will not write out the
19601 final bytes of the section. This may be a bug in BFD, but it is
19602 easier to fix it here since that is how the other a.out targets
19606 align = bfd_get_section_alignment (stdoutput, segment);
19607 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19614 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19615 of an rs_align_code fragment. */
19618 arm_handle_align (fragS * fragP)
19620 static char const arm_noop[2][2][4] =
19623 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19624 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19627 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19628 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19631 static char const thumb_noop[2][2][2] =
19634 {0xc0, 0x46}, /* LE */
19635 {0x46, 0xc0}, /* BE */
19638 {0x00, 0xbf}, /* LE */
19639 {0xbf, 0x00} /* BE */
19642 static char const wide_thumb_noop[2][4] =
19643 { /* Wide Thumb-2 */
19644 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19645 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19648 unsigned bytes, fix, noop_size;
19651 const char *narrow_noop = NULL;
19656 if (fragP->fr_type != rs_align_code)
19659 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19660 p = fragP->fr_literal + fragP->fr_fix;
19663 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19664 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19666 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19668 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19670 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19672 narrow_noop = thumb_noop[1][target_big_endian];
19673 noop = wide_thumb_noop[target_big_endian];
19676 noop = thumb_noop[0][target_big_endian];
19684 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19685 [target_big_endian];
19692 fragP->fr_var = noop_size;
19694 if (bytes & (noop_size - 1))
19696 fix = bytes & (noop_size - 1);
19698 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19700 memset (p, 0, fix);
19707 if (bytes & noop_size)
19709 /* Insert a narrow noop. */
19710 memcpy (p, narrow_noop, noop_size);
19712 bytes -= noop_size;
19716 /* Use wide noops for the remainder */
19720 while (bytes >= noop_size)
19722 memcpy (p, noop, noop_size);
19724 bytes -= noop_size;
19728 fragP->fr_fix += fix;
19731 /* Called from md_do_align. Used to create an alignment
19732 frag in a code section. */
19735 arm_frag_align_code (int n, int max)
19739 /* We assume that there will never be a requirement
19740 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19741 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19746 _("alignments greater than %d bytes not supported in .text sections."),
19747 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19748 as_fatal ("%s", err_msg);
19751 p = frag_var (rs_align_code,
19752 MAX_MEM_FOR_RS_ALIGN_CODE,
19754 (relax_substateT) max,
19761 /* Perform target specific initialisation of a frag.
19762 Note - despite the name this initialisation is not done when the frag
19763 is created, but only when its type is assigned. A frag can be created
19764 and used a long time before its type is set, so beware of assuming that
19765 this initialisationis performed first. */
19769 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19771 /* Record whether this frag is in an ARM or a THUMB area. */
19772 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19775 #else /* OBJ_ELF is defined. */
19777 arm_init_frag (fragS * fragP, int max_chars)
19779 /* If the current ARM vs THUMB mode has not already
19780 been recorded into this frag then do so now. */
19781 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19783 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19785 /* Record a mapping symbol for alignment frags. We will delete this
19786 later if the alignment ends up empty. */
19787 switch (fragP->fr_type)
19790 case rs_align_test:
19792 mapping_state_2 (MAP_DATA, max_chars);
19794 case rs_align_code:
19795 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19803 /* When we change sections we need to issue a new mapping symbol. */
19806 arm_elf_change_section (void)
19808 /* Link an unlinked unwind index table section to the .text section. */
19809 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19810 && elf_linked_to_section (now_seg) == NULL)
19811 elf_linked_to_section (now_seg) = text_section;
19815 arm_elf_section_type (const char * str, size_t len)
19817 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19818 return SHT_ARM_EXIDX;
19823 /* Code to deal with unwinding tables. */
19825 static void add_unwind_adjustsp (offsetT);
19827 /* Generate any deferred unwind frame offset. */
19830 flush_pending_unwind (void)
19834 offset = unwind.pending_offset;
19835 unwind.pending_offset = 0;
19837 add_unwind_adjustsp (offset);
19840 /* Add an opcode to this list for this function. Two-byte opcodes should
19841 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19845 add_unwind_opcode (valueT op, int length)
19847 /* Add any deferred stack adjustment. */
19848 if (unwind.pending_offset)
19849 flush_pending_unwind ();
19851 unwind.sp_restored = 0;
19853 if (unwind.opcode_count + length > unwind.opcode_alloc)
19855 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19856 if (unwind.opcodes)
19857 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19858 unwind.opcode_alloc);
19860 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19865 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19867 unwind.opcode_count++;
19871 /* Add unwind opcodes to adjust the stack pointer. */
19874 add_unwind_adjustsp (offsetT offset)
19878 if (offset > 0x200)
19880 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19885 /* Long form: 0xb2, uleb128. */
19886 /* This might not fit in a word so add the individual bytes,
19887 remembering the list is built in reverse order. */
19888 o = (valueT) ((offset - 0x204) >> 2);
19890 add_unwind_opcode (0, 1);
19892 /* Calculate the uleb128 encoding of the offset. */
19896 bytes[n] = o & 0x7f;
19902 /* Add the insn. */
19904 add_unwind_opcode (bytes[n - 1], 1);
19905 add_unwind_opcode (0xb2, 1);
19907 else if (offset > 0x100)
19909 /* Two short opcodes. */
19910 add_unwind_opcode (0x3f, 1);
19911 op = (offset - 0x104) >> 2;
19912 add_unwind_opcode (op, 1);
19914 else if (offset > 0)
19916 /* Short opcode. */
19917 op = (offset - 4) >> 2;
19918 add_unwind_opcode (op, 1);
19920 else if (offset < 0)
19923 while (offset > 0x100)
19925 add_unwind_opcode (0x7f, 1);
19928 op = ((offset - 4) >> 2) | 0x40;
19929 add_unwind_opcode (op, 1);
19933 /* Finish the list of unwind opcodes for this function. */
19935 finish_unwind_opcodes (void)
19939 if (unwind.fp_used)
19941 /* Adjust sp as necessary. */
19942 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19943 flush_pending_unwind ();
19945 /* After restoring sp from the frame pointer. */
19946 op = 0x90 | unwind.fp_reg;
19947 add_unwind_opcode (op, 1);
19950 flush_pending_unwind ();
19954 /* Start an exception table entry. If idx is nonzero this is an index table
19958 start_unwind_section (const segT text_seg, int idx)
19960 const char * text_name;
19961 const char * prefix;
19962 const char * prefix_once;
19963 const char * group_name;
19967 size_t sec_name_len;
19974 prefix = ELF_STRING_ARM_unwind;
19975 prefix_once = ELF_STRING_ARM_unwind_once;
19976 type = SHT_ARM_EXIDX;
19980 prefix = ELF_STRING_ARM_unwind_info;
19981 prefix_once = ELF_STRING_ARM_unwind_info_once;
19982 type = SHT_PROGBITS;
19985 text_name = segment_name (text_seg);
19986 if (streq (text_name, ".text"))
19989 if (strncmp (text_name, ".gnu.linkonce.t.",
19990 strlen (".gnu.linkonce.t.")) == 0)
19992 prefix = prefix_once;
19993 text_name += strlen (".gnu.linkonce.t.");
19996 prefix_len = strlen (prefix);
19997 text_len = strlen (text_name);
19998 sec_name_len = prefix_len + text_len;
19999 sec_name = (char *) xmalloc (sec_name_len + 1);
20000 memcpy (sec_name, prefix, prefix_len);
20001 memcpy (sec_name + prefix_len, text_name, text_len);
20002 sec_name[prefix_len + text_len] = '\0';
20008 /* Handle COMDAT group. */
20009 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20011 group_name = elf_group_name (text_seg);
20012 if (group_name == NULL)
20014 as_bad (_("Group section `%s' has no group signature"),
20015 segment_name (text_seg));
20016 ignore_rest_of_line ();
20019 flags |= SHF_GROUP;
20023 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20025 /* Set the section link for index tables. */
20027 elf_linked_to_section (now_seg) = text_seg;
20031 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20032 personality routine data. Returns zero, or the index table value for
20033 and inline entry. */
20036 create_unwind_entry (int have_data)
20041 /* The current word of data. */
20043 /* The number of bytes left in this word. */
20046 finish_unwind_opcodes ();
20048 /* Remember the current text section. */
20049 unwind.saved_seg = now_seg;
20050 unwind.saved_subseg = now_subseg;
20052 start_unwind_section (now_seg, 0);
20054 if (unwind.personality_routine == NULL)
20056 if (unwind.personality_index == -2)
20059 as_bad (_("handlerdata in cantunwind frame"));
20060 return 1; /* EXIDX_CANTUNWIND. */
20063 /* Use a default personality routine if none is specified. */
20064 if (unwind.personality_index == -1)
20066 if (unwind.opcode_count > 3)
20067 unwind.personality_index = 1;
20069 unwind.personality_index = 0;
20072 /* Space for the personality routine entry. */
20073 if (unwind.personality_index == 0)
20075 if (unwind.opcode_count > 3)
20076 as_bad (_("too many unwind opcodes for personality routine 0"));
20080 /* All the data is inline in the index table. */
20083 while (unwind.opcode_count > 0)
20085 unwind.opcode_count--;
20086 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20090 /* Pad with "finish" opcodes. */
20092 data = (data << 8) | 0xb0;
20099 /* We get two opcodes "free" in the first word. */
20100 size = unwind.opcode_count - 2;
20104 gas_assert (unwind.personality_index == -1);
20106 /* An extra byte is required for the opcode count. */
20107 size = unwind.opcode_count + 1;
20110 size = (size + 3) >> 2;
20112 as_bad (_("too many unwind opcodes"));
20114 frag_align (2, 0, 0);
20115 record_alignment (now_seg, 2);
20116 unwind.table_entry = expr_build_dot ();
20118 /* Allocate the table entry. */
20119 ptr = frag_more ((size << 2) + 4);
20120 /* PR 13449: Zero the table entries in case some of them are not used. */
20121 memset (ptr, 0, (size << 2) + 4);
20122 where = frag_now_fix () - ((size << 2) + 4);
20124 switch (unwind.personality_index)
20127 /* ??? Should this be a PLT generating relocation? */
20128 /* Custom personality routine. */
20129 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20130 BFD_RELOC_ARM_PREL31);
20135 /* Set the first byte to the number of additional words. */
20136 data = size > 0 ? size - 1 : 0;
20140 /* ABI defined personality routines. */
20142 /* Three opcodes bytes are packed into the first word. */
20149 /* The size and first two opcode bytes go in the first word. */
20150 data = ((0x80 + unwind.personality_index) << 8) | size;
20155 /* Should never happen. */
20159 /* Pack the opcodes into words (MSB first), reversing the list at the same
20161 while (unwind.opcode_count > 0)
20165 md_number_to_chars (ptr, data, 4);
20170 unwind.opcode_count--;
20172 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20175 /* Finish off the last word. */
20178 /* Pad with "finish" opcodes. */
20180 data = (data << 8) | 0xb0;
20182 md_number_to_chars (ptr, data, 4);
20187 /* Add an empty descriptor if there is no user-specified data. */
20188 ptr = frag_more (4);
20189 md_number_to_chars (ptr, 0, 4);
20196 /* Initialize the DWARF-2 unwind information for this procedure. */
20199 tc_arm_frame_initial_instructions (void)
20201 cfi_add_CFA_def_cfa (REG_SP, 0);
20203 #endif /* OBJ_ELF */
20205 /* Convert REGNAME to a DWARF-2 register number. */
20208 tc_arm_regname_to_dw2regnum (char *regname)
20210 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20220 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20224 exp.X_op = O_secrel;
20225 exp.X_add_symbol = symbol;
20226 exp.X_add_number = 0;
20227 emit_expr (&exp, size);
20231 /* MD interface: Symbol and relocation handling. */
20233 /* Return the address within the segment that a PC-relative fixup is
20234 relative to. For ARM, PC-relative fixups applied to instructions
20235 are generally relative to the location of the fixup plus 8 bytes.
20236 Thumb branches are offset by 4, and Thumb loads relative to PC
20237 require special handling. */
20240 md_pcrel_from_section (fixS * fixP, segT seg)
20242 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20244 /* If this is pc-relative and we are going to emit a relocation
20245 then we just want to put out any pipeline compensation that the linker
20246 will need. Otherwise we want to use the calculated base.
20247 For WinCE we skip the bias for externals as well, since this
20248 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20250 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20251 || (arm_force_relocation (fixP)
20253 && !S_IS_EXTERNAL (fixP->fx_addsy)
20259 switch (fixP->fx_r_type)
20261 /* PC relative addressing on the Thumb is slightly odd as the
20262 bottom two bits of the PC are forced to zero for the
20263 calculation. This happens *after* application of the
20264 pipeline offset. However, Thumb adrl already adjusts for
20265 this, so we need not do it again. */
20266 case BFD_RELOC_ARM_THUMB_ADD:
20269 case BFD_RELOC_ARM_THUMB_OFFSET:
20270 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20271 case BFD_RELOC_ARM_T32_ADD_PC12:
20272 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20273 return (base + 4) & ~3;
20275 /* Thumb branches are simply offset by +4. */
20276 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20277 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20278 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20279 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20280 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20283 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20285 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20286 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20287 && ARM_IS_FUNC (fixP->fx_addsy)
20288 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20289 base = fixP->fx_where + fixP->fx_frag->fr_address;
20292 /* BLX is like branches above, but forces the low two bits of PC to
20294 case BFD_RELOC_THUMB_PCREL_BLX:
20296 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20297 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20298 && THUMB_IS_FUNC (fixP->fx_addsy)
20299 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20300 base = fixP->fx_where + fixP->fx_frag->fr_address;
20301 return (base + 4) & ~3;
20303 /* ARM mode branches are offset by +8. However, the Windows CE
20304 loader expects the relocation not to take this into account. */
20305 case BFD_RELOC_ARM_PCREL_BLX:
20307 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20308 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20309 && ARM_IS_FUNC (fixP->fx_addsy)
20310 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20311 base = fixP->fx_where + fixP->fx_frag->fr_address;
20314 case BFD_RELOC_ARM_PCREL_CALL:
20316 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20317 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20318 && THUMB_IS_FUNC (fixP->fx_addsy)
20319 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20320 base = fixP->fx_where + fixP->fx_frag->fr_address;
20323 case BFD_RELOC_ARM_PCREL_BRANCH:
20324 case BFD_RELOC_ARM_PCREL_JUMP:
20325 case BFD_RELOC_ARM_PLT32:
20327 /* When handling fixups immediately, because we have already
20328 discovered the value of a symbol, or the address of the frag involved
20329 we must account for the offset by +8, as the OS loader will never see the reloc.
20330 see fixup_segment() in write.c
20331 The S_IS_EXTERNAL test handles the case of global symbols.
20332 Those need the calculated base, not just the pipe compensation the linker will need. */
20334 && fixP->fx_addsy != NULL
20335 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20336 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20344 /* ARM mode loads relative to PC are also offset by +8. Unlike
20345 branches, the Windows CE loader *does* expect the relocation
20346 to take this into account. */
20347 case BFD_RELOC_ARM_OFFSET_IMM:
20348 case BFD_RELOC_ARM_OFFSET_IMM8:
20349 case BFD_RELOC_ARM_HWLITERAL:
20350 case BFD_RELOC_ARM_LITERAL:
20351 case BFD_RELOC_ARM_CP_OFF_IMM:
20355 /* Other PC-relative relocations are un-offset. */
20361 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20362 Otherwise we have no need to default values of symbols. */
20365 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20368 if (name[0] == '_' && name[1] == 'G'
20369 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20373 if (symbol_find (name))
20374 as_bad (_("GOT already in the symbol table"));
20376 GOT_symbol = symbol_new (name, undefined_section,
20377 (valueT) 0, & zero_address_frag);
20387 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20388 computed as two separate immediate values, added together. We
20389 already know that this value cannot be computed by just one ARM
20392 static unsigned int
20393 validate_immediate_twopart (unsigned int val,
20394 unsigned int * highpart)
20399 for (i = 0; i < 32; i += 2)
20400 if (((a = rotate_left (val, i)) & 0xff) != 0)
20406 * highpart = (a >> 8) | ((i + 24) << 7);
20408 else if (a & 0xff0000)
20410 if (a & 0xff000000)
20412 * highpart = (a >> 16) | ((i + 16) << 7);
20416 gas_assert (a & 0xff000000);
20417 * highpart = (a >> 24) | ((i + 8) << 7);
20420 return (a & 0xff) | (i << 7);
20427 validate_offset_imm (unsigned int val, int hwse)
20429 if ((hwse && val > 255) || val > 4095)
20434 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20435 negative immediate constant by altering the instruction. A bit of
20440 by inverting the second operand, and
20443 by negating the second operand. */
20446 negate_data_op (unsigned long * instruction,
20447 unsigned long value)
20450 unsigned long negated, inverted;
20452 negated = encode_arm_immediate (-value);
20453 inverted = encode_arm_immediate (~value);
20455 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20458 /* First negates. */
20459 case OPCODE_SUB: /* ADD <-> SUB */
20460 new_inst = OPCODE_ADD;
20465 new_inst = OPCODE_SUB;
20469 case OPCODE_CMP: /* CMP <-> CMN */
20470 new_inst = OPCODE_CMN;
20475 new_inst = OPCODE_CMP;
20479 /* Now Inverted ops. */
20480 case OPCODE_MOV: /* MOV <-> MVN */
20481 new_inst = OPCODE_MVN;
20486 new_inst = OPCODE_MOV;
20490 case OPCODE_AND: /* AND <-> BIC */
20491 new_inst = OPCODE_BIC;
20496 new_inst = OPCODE_AND;
20500 case OPCODE_ADC: /* ADC <-> SBC */
20501 new_inst = OPCODE_SBC;
20506 new_inst = OPCODE_ADC;
20510 /* We cannot do anything. */
20515 if (value == (unsigned) FAIL)
20518 *instruction &= OPCODE_MASK;
20519 *instruction |= new_inst << DATA_OP_SHIFT;
20523 /* Like negate_data_op, but for Thumb-2. */
20525 static unsigned int
20526 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20530 unsigned int negated, inverted;
20532 negated = encode_thumb32_immediate (-value);
20533 inverted = encode_thumb32_immediate (~value);
20535 rd = (*instruction >> 8) & 0xf;
20536 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20539 /* ADD <-> SUB. Includes CMP <-> CMN. */
20540 case T2_OPCODE_SUB:
20541 new_inst = T2_OPCODE_ADD;
20545 case T2_OPCODE_ADD:
20546 new_inst = T2_OPCODE_SUB;
20550 /* ORR <-> ORN. Includes MOV <-> MVN. */
20551 case T2_OPCODE_ORR:
20552 new_inst = T2_OPCODE_ORN;
20556 case T2_OPCODE_ORN:
20557 new_inst = T2_OPCODE_ORR;
20561 /* AND <-> BIC. TST has no inverted equivalent. */
20562 case T2_OPCODE_AND:
20563 new_inst = T2_OPCODE_BIC;
20570 case T2_OPCODE_BIC:
20571 new_inst = T2_OPCODE_AND;
20576 case T2_OPCODE_ADC:
20577 new_inst = T2_OPCODE_SBC;
20581 case T2_OPCODE_SBC:
20582 new_inst = T2_OPCODE_ADC;
20586 /* We cannot do anything. */
20591 if (value == (unsigned int)FAIL)
20594 *instruction &= T2_OPCODE_MASK;
20595 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20599 /* Read a 32-bit thumb instruction from buf. */
20600 static unsigned long
20601 get_thumb32_insn (char * buf)
20603 unsigned long insn;
20604 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20605 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20611 /* We usually want to set the low bit on the address of thumb function
20612 symbols. In particular .word foo - . should have the low bit set.
20613 Generic code tries to fold the difference of two symbols to
20614 a constant. Prevent this and force a relocation when the first symbols
20615 is a thumb function. */
20618 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20620 if (op == O_subtract
20621 && l->X_op == O_symbol
20622 && r->X_op == O_symbol
20623 && THUMB_IS_FUNC (l->X_add_symbol))
20625 l->X_op = O_subtract;
20626 l->X_op_symbol = r->X_add_symbol;
20627 l->X_add_number -= r->X_add_number;
20631 /* Process as normal. */
20635 /* Encode Thumb2 unconditional branches and calls. The encoding
20636 for the 2 are identical for the immediate values. */
20639 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20641 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20644 addressT S, I1, I2, lo, hi;
20646 S = (value >> 24) & 0x01;
20647 I1 = (value >> 23) & 0x01;
20648 I2 = (value >> 22) & 0x01;
20649 hi = (value >> 12) & 0x3ff;
20650 lo = (value >> 1) & 0x7ff;
20651 newval = md_chars_to_number (buf, THUMB_SIZE);
20652 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20653 newval |= (S << 10) | hi;
20654 newval2 &= ~T2I1I2MASK;
20655 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20656 md_number_to_chars (buf, newval, THUMB_SIZE);
20657 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20661 md_apply_fix (fixS * fixP,
20665 offsetT value = * valP;
20667 unsigned int newimm;
20668 unsigned long temp;
20670 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20672 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20674 /* Note whether this will delete the relocation. */
20676 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20679 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20680 consistency with the behaviour on 32-bit hosts. Remember value
20682 value &= 0xffffffff;
20683 value ^= 0x80000000;
20684 value -= 0x80000000;
20687 fixP->fx_addnumber = value;
20689 /* Same treatment for fixP->fx_offset. */
20690 fixP->fx_offset &= 0xffffffff;
20691 fixP->fx_offset ^= 0x80000000;
20692 fixP->fx_offset -= 0x80000000;
20694 switch (fixP->fx_r_type)
20696 case BFD_RELOC_NONE:
20697 /* This will need to go in the object file. */
20701 case BFD_RELOC_ARM_IMMEDIATE:
20702 /* We claim that this fixup has been processed here,
20703 even if in fact we generate an error because we do
20704 not have a reloc for it, so tc_gen_reloc will reject it. */
20707 if (fixP->fx_addsy)
20709 const char *msg = 0;
20711 if (! S_IS_DEFINED (fixP->fx_addsy))
20712 msg = _("undefined symbol %s used as an immediate value");
20713 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20714 msg = _("symbol %s is in a different section");
20715 else if (S_IS_WEAK (fixP->fx_addsy))
20716 msg = _("symbol %s is weak and may be overridden later");
20720 as_bad_where (fixP->fx_file, fixP->fx_line,
20721 msg, S_GET_NAME (fixP->fx_addsy));
20726 temp = md_chars_to_number (buf, INSN_SIZE);
20728 /* If the offset is negative, we should use encoding A2 for ADR. */
20729 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
20730 newimm = negate_data_op (&temp, value);
20733 newimm = encode_arm_immediate (value);
20735 /* If the instruction will fail, see if we can fix things up by
20736 changing the opcode. */
20737 if (newimm == (unsigned int) FAIL)
20738 newimm = negate_data_op (&temp, value);
20741 if (newimm == (unsigned int) FAIL)
20743 as_bad_where (fixP->fx_file, fixP->fx_line,
20744 _("invalid constant (%lx) after fixup"),
20745 (unsigned long) value);
20749 newimm |= (temp & 0xfffff000);
20750 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20753 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20755 unsigned int highpart = 0;
20756 unsigned int newinsn = 0xe1a00000; /* nop. */
20758 if (fixP->fx_addsy)
20760 const char *msg = 0;
20762 if (! S_IS_DEFINED (fixP->fx_addsy))
20763 msg = _("undefined symbol %s used as an immediate value");
20764 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20765 msg = _("symbol %s is in a different section");
20766 else if (S_IS_WEAK (fixP->fx_addsy))
20767 msg = _("symbol %s is weak and may be overridden later");
20771 as_bad_where (fixP->fx_file, fixP->fx_line,
20772 msg, S_GET_NAME (fixP->fx_addsy));
20777 newimm = encode_arm_immediate (value);
20778 temp = md_chars_to_number (buf, INSN_SIZE);
20780 /* If the instruction will fail, see if we can fix things up by
20781 changing the opcode. */
20782 if (newimm == (unsigned int) FAIL
20783 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20785 /* No ? OK - try using two ADD instructions to generate
20787 newimm = validate_immediate_twopart (value, & highpart);
20789 /* Yes - then make sure that the second instruction is
20791 if (newimm != (unsigned int) FAIL)
20793 /* Still No ? Try using a negated value. */
20794 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20795 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20796 /* Otherwise - give up. */
20799 as_bad_where (fixP->fx_file, fixP->fx_line,
20800 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20805 /* Replace the first operand in the 2nd instruction (which
20806 is the PC) with the destination register. We have
20807 already added in the PC in the first instruction and we
20808 do not want to do it again. */
20809 newinsn &= ~ 0xf0000;
20810 newinsn |= ((newinsn & 0x0f000) << 4);
20813 newimm |= (temp & 0xfffff000);
20814 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20816 highpart |= (newinsn & 0xfffff000);
20817 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20821 case BFD_RELOC_ARM_OFFSET_IMM:
20822 if (!fixP->fx_done && seg->use_rela_p)
20825 case BFD_RELOC_ARM_LITERAL:
20831 if (validate_offset_imm (value, 0) == FAIL)
20833 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20834 as_bad_where (fixP->fx_file, fixP->fx_line,
20835 _("invalid literal constant: pool needs to be closer"));
20837 as_bad_where (fixP->fx_file, fixP->fx_line,
20838 _("bad immediate value for offset (%ld)"),
20843 newval = md_chars_to_number (buf, INSN_SIZE);
20845 newval &= 0xfffff000;
20848 newval &= 0xff7ff000;
20849 newval |= value | (sign ? INDEX_UP : 0);
20851 md_number_to_chars (buf, newval, INSN_SIZE);
20854 case BFD_RELOC_ARM_OFFSET_IMM8:
20855 case BFD_RELOC_ARM_HWLITERAL:
20861 if (validate_offset_imm (value, 1) == FAIL)
20863 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20864 as_bad_where (fixP->fx_file, fixP->fx_line,
20865 _("invalid literal constant: pool needs to be closer"));
20867 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20872 newval = md_chars_to_number (buf, INSN_SIZE);
20874 newval &= 0xfffff0f0;
20877 newval &= 0xff7ff0f0;
20878 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20880 md_number_to_chars (buf, newval, INSN_SIZE);
20883 case BFD_RELOC_ARM_T32_OFFSET_U8:
20884 if (value < 0 || value > 1020 || value % 4 != 0)
20885 as_bad_where (fixP->fx_file, fixP->fx_line,
20886 _("bad immediate value for offset (%ld)"), (long) value);
20889 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20891 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20894 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20895 /* This is a complicated relocation used for all varieties of Thumb32
20896 load/store instruction with immediate offset:
20898 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20899 *4, optional writeback(W)
20900 (doubleword load/store)
20902 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20903 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20904 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20905 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20906 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20908 Uppercase letters indicate bits that are already encoded at
20909 this point. Lowercase letters are our problem. For the
20910 second block of instructions, the secondary opcode nybble
20911 (bits 8..11) is present, and bit 23 is zero, even if this is
20912 a PC-relative operation. */
20913 newval = md_chars_to_number (buf, THUMB_SIZE);
20915 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20917 if ((newval & 0xf0000000) == 0xe0000000)
20919 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20921 newval |= (1 << 23);
20924 if (value % 4 != 0)
20926 as_bad_where (fixP->fx_file, fixP->fx_line,
20927 _("offset not a multiple of 4"));
20933 as_bad_where (fixP->fx_file, fixP->fx_line,
20934 _("offset out of range"));
20939 else if ((newval & 0x000f0000) == 0x000f0000)
20941 /* PC-relative, 12-bit offset. */
20943 newval |= (1 << 23);
20948 as_bad_where (fixP->fx_file, fixP->fx_line,
20949 _("offset out of range"));
20954 else if ((newval & 0x00000100) == 0x00000100)
20956 /* Writeback: 8-bit, +/- offset. */
20958 newval |= (1 << 9);
20963 as_bad_where (fixP->fx_file, fixP->fx_line,
20964 _("offset out of range"));
20969 else if ((newval & 0x00000f00) == 0x00000e00)
20971 /* T-instruction: positive 8-bit offset. */
20972 if (value < 0 || value > 0xff)
20974 as_bad_where (fixP->fx_file, fixP->fx_line,
20975 _("offset out of range"));
20983 /* Positive 12-bit or negative 8-bit offset. */
20987 newval |= (1 << 23);
20997 as_bad_where (fixP->fx_file, fixP->fx_line,
20998 _("offset out of range"));
21005 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21006 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21009 case BFD_RELOC_ARM_SHIFT_IMM:
21010 newval = md_chars_to_number (buf, INSN_SIZE);
21011 if (((unsigned long) value) > 32
21013 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21015 as_bad_where (fixP->fx_file, fixP->fx_line,
21016 _("shift expression is too large"));
21021 /* Shifts of zero must be done as lsl. */
21023 else if (value == 32)
21025 newval &= 0xfffff07f;
21026 newval |= (value & 0x1f) << 7;
21027 md_number_to_chars (buf, newval, INSN_SIZE);
21030 case BFD_RELOC_ARM_T32_IMMEDIATE:
21031 case BFD_RELOC_ARM_T32_ADD_IMM:
21032 case BFD_RELOC_ARM_T32_IMM12:
21033 case BFD_RELOC_ARM_T32_ADD_PC12:
21034 /* We claim that this fixup has been processed here,
21035 even if in fact we generate an error because we do
21036 not have a reloc for it, so tc_gen_reloc will reject it. */
21040 && ! S_IS_DEFINED (fixP->fx_addsy))
21042 as_bad_where (fixP->fx_file, fixP->fx_line,
21043 _("undefined symbol %s used as an immediate value"),
21044 S_GET_NAME (fixP->fx_addsy));
21048 newval = md_chars_to_number (buf, THUMB_SIZE);
21050 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21053 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21054 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21056 newimm = encode_thumb32_immediate (value);
21057 if (newimm == (unsigned int) FAIL)
21058 newimm = thumb32_negate_data_op (&newval, value);
21060 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21061 && newimm == (unsigned int) FAIL)
21063 /* Turn add/sum into addw/subw. */
21064 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21065 newval = (newval & 0xfeffffff) | 0x02000000;
21066 /* No flat 12-bit imm encoding for addsw/subsw. */
21067 if ((newval & 0x00100000) == 0)
21069 /* 12 bit immediate for addw/subw. */
21073 newval ^= 0x00a00000;
21076 newimm = (unsigned int) FAIL;
21082 if (newimm == (unsigned int)FAIL)
21084 as_bad_where (fixP->fx_file, fixP->fx_line,
21085 _("invalid constant (%lx) after fixup"),
21086 (unsigned long) value);
21090 newval |= (newimm & 0x800) << 15;
21091 newval |= (newimm & 0x700) << 4;
21092 newval |= (newimm & 0x0ff);
21094 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21095 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21098 case BFD_RELOC_ARM_SMC:
21099 if (((unsigned long) value) > 0xffff)
21100 as_bad_where (fixP->fx_file, fixP->fx_line,
21101 _("invalid smc expression"));
21102 newval = md_chars_to_number (buf, INSN_SIZE);
21103 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21104 md_number_to_chars (buf, newval, INSN_SIZE);
21107 case BFD_RELOC_ARM_HVC:
21108 if (((unsigned long) value) > 0xffff)
21109 as_bad_where (fixP->fx_file, fixP->fx_line,
21110 _("invalid hvc expression"));
21111 newval = md_chars_to_number (buf, INSN_SIZE);
21112 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21113 md_number_to_chars (buf, newval, INSN_SIZE);
21116 case BFD_RELOC_ARM_SWI:
21117 if (fixP->tc_fix_data != 0)
21119 if (((unsigned long) value) > 0xff)
21120 as_bad_where (fixP->fx_file, fixP->fx_line,
21121 _("invalid swi expression"));
21122 newval = md_chars_to_number (buf, THUMB_SIZE);
21124 md_number_to_chars (buf, newval, THUMB_SIZE);
21128 if (((unsigned long) value) > 0x00ffffff)
21129 as_bad_where (fixP->fx_file, fixP->fx_line,
21130 _("invalid swi expression"));
21131 newval = md_chars_to_number (buf, INSN_SIZE);
21133 md_number_to_chars (buf, newval, INSN_SIZE);
21137 case BFD_RELOC_ARM_MULTI:
21138 if (((unsigned long) value) > 0xffff)
21139 as_bad_where (fixP->fx_file, fixP->fx_line,
21140 _("invalid expression in load/store multiple"));
21141 newval = value | md_chars_to_number (buf, INSN_SIZE);
21142 md_number_to_chars (buf, newval, INSN_SIZE);
21146 case BFD_RELOC_ARM_PCREL_CALL:
21148 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21150 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21151 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21152 && THUMB_IS_FUNC (fixP->fx_addsy))
21153 /* Flip the bl to blx. This is a simple flip
21154 bit here because we generate PCREL_CALL for
21155 unconditional bls. */
21157 newval = md_chars_to_number (buf, INSN_SIZE);
21158 newval = newval | 0x10000000;
21159 md_number_to_chars (buf, newval, INSN_SIZE);
21165 goto arm_branch_common;
21167 case BFD_RELOC_ARM_PCREL_JUMP:
21168 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21170 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21171 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21172 && THUMB_IS_FUNC (fixP->fx_addsy))
21174 /* This would map to a bl<cond>, b<cond>,
21175 b<always> to a Thumb function. We
21176 need to force a relocation for this particular
21178 newval = md_chars_to_number (buf, INSN_SIZE);
21182 case BFD_RELOC_ARM_PLT32:
21184 case BFD_RELOC_ARM_PCREL_BRANCH:
21186 goto arm_branch_common;
21188 case BFD_RELOC_ARM_PCREL_BLX:
21191 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21193 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21194 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21195 && ARM_IS_FUNC (fixP->fx_addsy))
21197 /* Flip the blx to a bl and warn. */
21198 const char *name = S_GET_NAME (fixP->fx_addsy);
21199 newval = 0xeb000000;
21200 as_warn_where (fixP->fx_file, fixP->fx_line,
21201 _("blx to '%s' an ARM ISA state function changed to bl"),
21203 md_number_to_chars (buf, newval, INSN_SIZE);
21209 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21210 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21214 /* We are going to store value (shifted right by two) in the
21215 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21216 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21217 also be be clear. */
21219 as_bad_where (fixP->fx_file, fixP->fx_line,
21220 _("misaligned branch destination"));
21221 if ((value & (offsetT)0xfe000000) != (offsetT)0
21222 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21223 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21225 if (fixP->fx_done || !seg->use_rela_p)
21227 newval = md_chars_to_number (buf, INSN_SIZE);
21228 newval |= (value >> 2) & 0x00ffffff;
21229 /* Set the H bit on BLX instructions. */
21233 newval |= 0x01000000;
21235 newval &= ~0x01000000;
21237 md_number_to_chars (buf, newval, INSN_SIZE);
21241 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21242 /* CBZ can only branch forward. */
21244 /* Attempts to use CBZ to branch to the next instruction
21245 (which, strictly speaking, are prohibited) will be turned into
21248 FIXME: It may be better to remove the instruction completely and
21249 perform relaxation. */
21252 newval = md_chars_to_number (buf, THUMB_SIZE);
21253 newval = 0xbf00; /* NOP encoding T1 */
21254 md_number_to_chars (buf, newval, THUMB_SIZE);
21259 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21261 if (fixP->fx_done || !seg->use_rela_p)
21263 newval = md_chars_to_number (buf, THUMB_SIZE);
21264 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21265 md_number_to_chars (buf, newval, THUMB_SIZE);
21270 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21271 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21272 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21274 if (fixP->fx_done || !seg->use_rela_p)
21276 newval = md_chars_to_number (buf, THUMB_SIZE);
21277 newval |= (value & 0x1ff) >> 1;
21278 md_number_to_chars (buf, newval, THUMB_SIZE);
21282 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21283 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21284 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21286 if (fixP->fx_done || !seg->use_rela_p)
21288 newval = md_chars_to_number (buf, THUMB_SIZE);
21289 newval |= (value & 0xfff) >> 1;
21290 md_number_to_chars (buf, newval, THUMB_SIZE);
21294 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21296 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21297 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21298 && ARM_IS_FUNC (fixP->fx_addsy)
21299 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21301 /* Force a relocation for a branch 20 bits wide. */
21304 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21305 as_bad_where (fixP->fx_file, fixP->fx_line,
21306 _("conditional branch out of range"));
21308 if (fixP->fx_done || !seg->use_rela_p)
21311 addressT S, J1, J2, lo, hi;
21313 S = (value & 0x00100000) >> 20;
21314 J2 = (value & 0x00080000) >> 19;
21315 J1 = (value & 0x00040000) >> 18;
21316 hi = (value & 0x0003f000) >> 12;
21317 lo = (value & 0x00000ffe) >> 1;
21319 newval = md_chars_to_number (buf, THUMB_SIZE);
21320 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21321 newval |= (S << 10) | hi;
21322 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21323 md_number_to_chars (buf, newval, THUMB_SIZE);
21324 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21328 case BFD_RELOC_THUMB_PCREL_BLX:
21329 /* If there is a blx from a thumb state function to
21330 another thumb function flip this to a bl and warn
21334 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21335 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21336 && THUMB_IS_FUNC (fixP->fx_addsy))
21338 const char *name = S_GET_NAME (fixP->fx_addsy);
21339 as_warn_where (fixP->fx_file, fixP->fx_line,
21340 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21342 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21343 newval = newval | 0x1000;
21344 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21345 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21350 goto thumb_bl_common;
21352 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21353 /* A bl from Thumb state ISA to an internal ARM state function
21354 is converted to a blx. */
21356 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21357 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21358 && ARM_IS_FUNC (fixP->fx_addsy)
21359 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21361 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21362 newval = newval & ~0x1000;
21363 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21364 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21371 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
21372 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21373 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21376 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21377 /* For a BLX instruction, make sure that the relocation is rounded up
21378 to a word boundary. This follows the semantics of the instruction
21379 which specifies that bit 1 of the target address will come from bit
21380 1 of the base address. */
21381 value = (value + 1) & ~ 1;
21383 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21385 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21386 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21387 else if ((value & ~0x1ffffff)
21388 && ((value & ~0x1ffffff) != ~0x1ffffff))
21389 as_bad_where (fixP->fx_file, fixP->fx_line,
21390 _("Thumb2 branch out of range"));
21393 if (fixP->fx_done || !seg->use_rela_p)
21394 encode_thumb2_b_bl_offset (buf, value);
21398 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21399 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21400 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21402 if (fixP->fx_done || !seg->use_rela_p)
21403 encode_thumb2_b_bl_offset (buf, value);
21408 if (fixP->fx_done || !seg->use_rela_p)
21409 md_number_to_chars (buf, value, 1);
21413 if (fixP->fx_done || !seg->use_rela_p)
21414 md_number_to_chars (buf, value, 2);
21418 case BFD_RELOC_ARM_TLS_CALL:
21419 case BFD_RELOC_ARM_THM_TLS_CALL:
21420 case BFD_RELOC_ARM_TLS_DESCSEQ:
21421 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21422 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21425 case BFD_RELOC_ARM_TLS_GOTDESC:
21426 case BFD_RELOC_ARM_TLS_GD32:
21427 case BFD_RELOC_ARM_TLS_LE32:
21428 case BFD_RELOC_ARM_TLS_IE32:
21429 case BFD_RELOC_ARM_TLS_LDM32:
21430 case BFD_RELOC_ARM_TLS_LDO32:
21431 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21434 case BFD_RELOC_ARM_GOT32:
21435 case BFD_RELOC_ARM_GOTOFF:
21436 if (fixP->fx_done || !seg->use_rela_p)
21437 md_number_to_chars (buf, 0, 4);
21440 case BFD_RELOC_ARM_GOT_PREL:
21441 if (fixP->fx_done || !seg->use_rela_p)
21442 md_number_to_chars (buf, value, 4);
21445 case BFD_RELOC_ARM_TARGET2:
21446 /* TARGET2 is not partial-inplace, so we need to write the
21447 addend here for REL targets, because it won't be written out
21448 during reloc processing later. */
21449 if (fixP->fx_done || !seg->use_rela_p)
21450 md_number_to_chars (buf, fixP->fx_offset, 4);
21454 case BFD_RELOC_RVA:
21456 case BFD_RELOC_ARM_TARGET1:
21457 case BFD_RELOC_ARM_ROSEGREL32:
21458 case BFD_RELOC_ARM_SBREL32:
21459 case BFD_RELOC_32_PCREL:
21461 case BFD_RELOC_32_SECREL:
21463 if (fixP->fx_done || !seg->use_rela_p)
21465 /* For WinCE we only do this for pcrel fixups. */
21466 if (fixP->fx_done || fixP->fx_pcrel)
21468 md_number_to_chars (buf, value, 4);
21472 case BFD_RELOC_ARM_PREL31:
21473 if (fixP->fx_done || !seg->use_rela_p)
21475 newval = md_chars_to_number (buf, 4) & 0x80000000;
21476 if ((value ^ (value >> 1)) & 0x40000000)
21478 as_bad_where (fixP->fx_file, fixP->fx_line,
21479 _("rel31 relocation overflow"));
21481 newval |= value & 0x7fffffff;
21482 md_number_to_chars (buf, newval, 4);
21487 case BFD_RELOC_ARM_CP_OFF_IMM:
21488 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21489 if (value < -1023 || value > 1023 || (value & 3))
21490 as_bad_where (fixP->fx_file, fixP->fx_line,
21491 _("co-processor offset out of range"));
21496 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21497 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21498 newval = md_chars_to_number (buf, INSN_SIZE);
21500 newval = get_thumb32_insn (buf);
21502 newval &= 0xffffff00;
21505 newval &= 0xff7fff00;
21506 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21508 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21509 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21510 md_number_to_chars (buf, newval, INSN_SIZE);
21512 put_thumb32_insn (buf, newval);
21515 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21516 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21517 if (value < -255 || value > 255)
21518 as_bad_where (fixP->fx_file, fixP->fx_line,
21519 _("co-processor offset out of range"));
21521 goto cp_off_common;
21523 case BFD_RELOC_ARM_THUMB_OFFSET:
21524 newval = md_chars_to_number (buf, THUMB_SIZE);
21525 /* Exactly what ranges, and where the offset is inserted depends
21526 on the type of instruction, we can establish this from the
21528 switch (newval >> 12)
21530 case 4: /* PC load. */
21531 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21532 forced to zero for these loads; md_pcrel_from has already
21533 compensated for this. */
21535 as_bad_where (fixP->fx_file, fixP->fx_line,
21536 _("invalid offset, target not word aligned (0x%08lX)"),
21537 (((unsigned long) fixP->fx_frag->fr_address
21538 + (unsigned long) fixP->fx_where) & ~3)
21539 + (unsigned long) value);
21541 if (value & ~0x3fc)
21542 as_bad_where (fixP->fx_file, fixP->fx_line,
21543 _("invalid offset, value too big (0x%08lX)"),
21546 newval |= value >> 2;
21549 case 9: /* SP load/store. */
21550 if (value & ~0x3fc)
21551 as_bad_where (fixP->fx_file, fixP->fx_line,
21552 _("invalid offset, value too big (0x%08lX)"),
21554 newval |= value >> 2;
21557 case 6: /* Word load/store. */
21559 as_bad_where (fixP->fx_file, fixP->fx_line,
21560 _("invalid offset, value too big (0x%08lX)"),
21562 newval |= value << 4; /* 6 - 2. */
21565 case 7: /* Byte load/store. */
21567 as_bad_where (fixP->fx_file, fixP->fx_line,
21568 _("invalid offset, value too big (0x%08lX)"),
21570 newval |= value << 6;
21573 case 8: /* Halfword load/store. */
21575 as_bad_where (fixP->fx_file, fixP->fx_line,
21576 _("invalid offset, value too big (0x%08lX)"),
21578 newval |= value << 5; /* 6 - 1. */
21582 as_bad_where (fixP->fx_file, fixP->fx_line,
21583 "Unable to process relocation for thumb opcode: %lx",
21584 (unsigned long) newval);
21587 md_number_to_chars (buf, newval, THUMB_SIZE);
21590 case BFD_RELOC_ARM_THUMB_ADD:
21591 /* This is a complicated relocation, since we use it for all of
21592 the following immediate relocations:
21596 9bit ADD/SUB SP word-aligned
21597 10bit ADD PC/SP word-aligned
21599 The type of instruction being processed is encoded in the
21606 newval = md_chars_to_number (buf, THUMB_SIZE);
21608 int rd = (newval >> 4) & 0xf;
21609 int rs = newval & 0xf;
21610 int subtract = !!(newval & 0x8000);
21612 /* Check for HI regs, only very restricted cases allowed:
21613 Adjusting SP, and using PC or SP to get an address. */
21614 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21615 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21616 as_bad_where (fixP->fx_file, fixP->fx_line,
21617 _("invalid Hi register with immediate"));
21619 /* If value is negative, choose the opposite instruction. */
21623 subtract = !subtract;
21625 as_bad_where (fixP->fx_file, fixP->fx_line,
21626 _("immediate value out of range"));
21631 if (value & ~0x1fc)
21632 as_bad_where (fixP->fx_file, fixP->fx_line,
21633 _("invalid immediate for stack address calculation"));
21634 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21635 newval |= value >> 2;
21637 else if (rs == REG_PC || rs == REG_SP)
21639 if (subtract || value & ~0x3fc)
21640 as_bad_where (fixP->fx_file, fixP->fx_line,
21641 _("invalid immediate for address calculation (value = 0x%08lX)"),
21642 (unsigned long) value);
21643 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21645 newval |= value >> 2;
21650 as_bad_where (fixP->fx_file, fixP->fx_line,
21651 _("immediate value out of range"));
21652 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21653 newval |= (rd << 8) | value;
21658 as_bad_where (fixP->fx_file, fixP->fx_line,
21659 _("immediate value out of range"));
21660 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21661 newval |= rd | (rs << 3) | (value << 6);
21664 md_number_to_chars (buf, newval, THUMB_SIZE);
21667 case BFD_RELOC_ARM_THUMB_IMM:
21668 newval = md_chars_to_number (buf, THUMB_SIZE);
21669 if (value < 0 || value > 255)
21670 as_bad_where (fixP->fx_file, fixP->fx_line,
21671 _("invalid immediate: %ld is out of range"),
21674 md_number_to_chars (buf, newval, THUMB_SIZE);
21677 case BFD_RELOC_ARM_THUMB_SHIFT:
21678 /* 5bit shift value (0..32). LSL cannot take 32. */
21679 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21680 temp = newval & 0xf800;
21681 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21682 as_bad_where (fixP->fx_file, fixP->fx_line,
21683 _("invalid shift value: %ld"), (long) value);
21684 /* Shifts of zero must be encoded as LSL. */
21686 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21687 /* Shifts of 32 are encoded as zero. */
21688 else if (value == 32)
21690 newval |= value << 6;
21691 md_number_to_chars (buf, newval, THUMB_SIZE);
21694 case BFD_RELOC_VTABLE_INHERIT:
21695 case BFD_RELOC_VTABLE_ENTRY:
21699 case BFD_RELOC_ARM_MOVW:
21700 case BFD_RELOC_ARM_MOVT:
21701 case BFD_RELOC_ARM_THUMB_MOVW:
21702 case BFD_RELOC_ARM_THUMB_MOVT:
21703 if (fixP->fx_done || !seg->use_rela_p)
21705 /* REL format relocations are limited to a 16-bit addend. */
21706 if (!fixP->fx_done)
21708 if (value < -0x8000 || value > 0x7fff)
21709 as_bad_where (fixP->fx_file, fixP->fx_line,
21710 _("offset out of range"));
21712 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21713 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21718 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21719 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21721 newval = get_thumb32_insn (buf);
21722 newval &= 0xfbf08f00;
21723 newval |= (value & 0xf000) << 4;
21724 newval |= (value & 0x0800) << 15;
21725 newval |= (value & 0x0700) << 4;
21726 newval |= (value & 0x00ff);
21727 put_thumb32_insn (buf, newval);
21731 newval = md_chars_to_number (buf, 4);
21732 newval &= 0xfff0f000;
21733 newval |= value & 0x0fff;
21734 newval |= (value & 0xf000) << 4;
21735 md_number_to_chars (buf, newval, 4);
21740 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21741 case BFD_RELOC_ARM_ALU_PC_G0:
21742 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21743 case BFD_RELOC_ARM_ALU_PC_G1:
21744 case BFD_RELOC_ARM_ALU_PC_G2:
21745 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21746 case BFD_RELOC_ARM_ALU_SB_G0:
21747 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21748 case BFD_RELOC_ARM_ALU_SB_G1:
21749 case BFD_RELOC_ARM_ALU_SB_G2:
21750 gas_assert (!fixP->fx_done);
21751 if (!seg->use_rela_p)
21754 bfd_vma encoded_addend;
21755 bfd_vma addend_abs = abs (value);
21757 /* Check that the absolute value of the addend can be
21758 expressed as an 8-bit constant plus a rotation. */
21759 encoded_addend = encode_arm_immediate (addend_abs);
21760 if (encoded_addend == (unsigned int) FAIL)
21761 as_bad_where (fixP->fx_file, fixP->fx_line,
21762 _("the offset 0x%08lX is not representable"),
21763 (unsigned long) addend_abs);
21765 /* Extract the instruction. */
21766 insn = md_chars_to_number (buf, INSN_SIZE);
21768 /* If the addend is positive, use an ADD instruction.
21769 Otherwise use a SUB. Take care not to destroy the S bit. */
21770 insn &= 0xff1fffff;
21776 /* Place the encoded addend into the first 12 bits of the
21778 insn &= 0xfffff000;
21779 insn |= encoded_addend;
21781 /* Update the instruction. */
21782 md_number_to_chars (buf, insn, INSN_SIZE);
21786 case BFD_RELOC_ARM_LDR_PC_G0:
21787 case BFD_RELOC_ARM_LDR_PC_G1:
21788 case BFD_RELOC_ARM_LDR_PC_G2:
21789 case BFD_RELOC_ARM_LDR_SB_G0:
21790 case BFD_RELOC_ARM_LDR_SB_G1:
21791 case BFD_RELOC_ARM_LDR_SB_G2:
21792 gas_assert (!fixP->fx_done);
21793 if (!seg->use_rela_p)
21796 bfd_vma addend_abs = abs (value);
21798 /* Check that the absolute value of the addend can be
21799 encoded in 12 bits. */
21800 if (addend_abs >= 0x1000)
21801 as_bad_where (fixP->fx_file, fixP->fx_line,
21802 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21803 (unsigned long) addend_abs);
21805 /* Extract the instruction. */
21806 insn = md_chars_to_number (buf, INSN_SIZE);
21808 /* If the addend is negative, clear bit 23 of the instruction.
21809 Otherwise set it. */
21811 insn &= ~(1 << 23);
21815 /* Place the absolute value of the addend into the first 12 bits
21816 of the instruction. */
21817 insn &= 0xfffff000;
21818 insn |= addend_abs;
21820 /* Update the instruction. */
21821 md_number_to_chars (buf, insn, INSN_SIZE);
21825 case BFD_RELOC_ARM_LDRS_PC_G0:
21826 case BFD_RELOC_ARM_LDRS_PC_G1:
21827 case BFD_RELOC_ARM_LDRS_PC_G2:
21828 case BFD_RELOC_ARM_LDRS_SB_G0:
21829 case BFD_RELOC_ARM_LDRS_SB_G1:
21830 case BFD_RELOC_ARM_LDRS_SB_G2:
21831 gas_assert (!fixP->fx_done);
21832 if (!seg->use_rela_p)
21835 bfd_vma addend_abs = abs (value);
21837 /* Check that the absolute value of the addend can be
21838 encoded in 8 bits. */
21839 if (addend_abs >= 0x100)
21840 as_bad_where (fixP->fx_file, fixP->fx_line,
21841 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21842 (unsigned long) addend_abs);
21844 /* Extract the instruction. */
21845 insn = md_chars_to_number (buf, INSN_SIZE);
21847 /* If the addend is negative, clear bit 23 of the instruction.
21848 Otherwise set it. */
21850 insn &= ~(1 << 23);
21854 /* Place the first four bits of the absolute value of the addend
21855 into the first 4 bits of the instruction, and the remaining
21856 four into bits 8 .. 11. */
21857 insn &= 0xfffff0f0;
21858 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21860 /* Update the instruction. */
21861 md_number_to_chars (buf, insn, INSN_SIZE);
21865 case BFD_RELOC_ARM_LDC_PC_G0:
21866 case BFD_RELOC_ARM_LDC_PC_G1:
21867 case BFD_RELOC_ARM_LDC_PC_G2:
21868 case BFD_RELOC_ARM_LDC_SB_G0:
21869 case BFD_RELOC_ARM_LDC_SB_G1:
21870 case BFD_RELOC_ARM_LDC_SB_G2:
21871 gas_assert (!fixP->fx_done);
21872 if (!seg->use_rela_p)
21875 bfd_vma addend_abs = abs (value);
21877 /* Check that the absolute value of the addend is a multiple of
21878 four and, when divided by four, fits in 8 bits. */
21879 if (addend_abs & 0x3)
21880 as_bad_where (fixP->fx_file, fixP->fx_line,
21881 _("bad offset 0x%08lX (must be word-aligned)"),
21882 (unsigned long) addend_abs);
21884 if ((addend_abs >> 2) > 0xff)
21885 as_bad_where (fixP->fx_file, fixP->fx_line,
21886 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21887 (unsigned long) addend_abs);
21889 /* Extract the instruction. */
21890 insn = md_chars_to_number (buf, INSN_SIZE);
21892 /* If the addend is negative, clear bit 23 of the instruction.
21893 Otherwise set it. */
21895 insn &= ~(1 << 23);
21899 /* Place the addend (divided by four) into the first eight
21900 bits of the instruction. */
21901 insn &= 0xfffffff0;
21902 insn |= addend_abs >> 2;
21904 /* Update the instruction. */
21905 md_number_to_chars (buf, insn, INSN_SIZE);
21909 case BFD_RELOC_ARM_V4BX:
21910 /* This will need to go in the object file. */
21914 case BFD_RELOC_UNUSED:
21916 as_bad_where (fixP->fx_file, fixP->fx_line,
21917 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21921 /* Translate internal representation of relocation info to BFD target
21925 tc_gen_reloc (asection *section, fixS *fixp)
21928 bfd_reloc_code_real_type code;
21930 reloc = (arelent *) xmalloc (sizeof (arelent));
21932 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21933 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21934 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21936 if (fixp->fx_pcrel)
21938 if (section->use_rela_p)
21939 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21941 fixp->fx_offset = reloc->address;
21943 reloc->addend = fixp->fx_offset;
21945 switch (fixp->fx_r_type)
21948 if (fixp->fx_pcrel)
21950 code = BFD_RELOC_8_PCREL;
21955 if (fixp->fx_pcrel)
21957 code = BFD_RELOC_16_PCREL;
21962 if (fixp->fx_pcrel)
21964 code = BFD_RELOC_32_PCREL;
21968 case BFD_RELOC_ARM_MOVW:
21969 if (fixp->fx_pcrel)
21971 code = BFD_RELOC_ARM_MOVW_PCREL;
21975 case BFD_RELOC_ARM_MOVT:
21976 if (fixp->fx_pcrel)
21978 code = BFD_RELOC_ARM_MOVT_PCREL;
21982 case BFD_RELOC_ARM_THUMB_MOVW:
21983 if (fixp->fx_pcrel)
21985 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21989 case BFD_RELOC_ARM_THUMB_MOVT:
21990 if (fixp->fx_pcrel)
21992 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21996 case BFD_RELOC_NONE:
21997 case BFD_RELOC_ARM_PCREL_BRANCH:
21998 case BFD_RELOC_ARM_PCREL_BLX:
21999 case BFD_RELOC_RVA:
22000 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22001 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22002 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22003 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22004 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22005 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22006 case BFD_RELOC_VTABLE_ENTRY:
22007 case BFD_RELOC_VTABLE_INHERIT:
22009 case BFD_RELOC_32_SECREL:
22011 code = fixp->fx_r_type;
22014 case BFD_RELOC_THUMB_PCREL_BLX:
22016 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22017 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22020 code = BFD_RELOC_THUMB_PCREL_BLX;
22023 case BFD_RELOC_ARM_LITERAL:
22024 case BFD_RELOC_ARM_HWLITERAL:
22025 /* If this is called then the a literal has
22026 been referenced across a section boundary. */
22027 as_bad_where (fixp->fx_file, fixp->fx_line,
22028 _("literal referenced across section boundary"));
22032 case BFD_RELOC_ARM_TLS_CALL:
22033 case BFD_RELOC_ARM_THM_TLS_CALL:
22034 case BFD_RELOC_ARM_TLS_DESCSEQ:
22035 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22036 case BFD_RELOC_ARM_GOT32:
22037 case BFD_RELOC_ARM_GOTOFF:
22038 case BFD_RELOC_ARM_GOT_PREL:
22039 case BFD_RELOC_ARM_PLT32:
22040 case BFD_RELOC_ARM_TARGET1:
22041 case BFD_RELOC_ARM_ROSEGREL32:
22042 case BFD_RELOC_ARM_SBREL32:
22043 case BFD_RELOC_ARM_PREL31:
22044 case BFD_RELOC_ARM_TARGET2:
22045 case BFD_RELOC_ARM_TLS_LE32:
22046 case BFD_RELOC_ARM_TLS_LDO32:
22047 case BFD_RELOC_ARM_PCREL_CALL:
22048 case BFD_RELOC_ARM_PCREL_JUMP:
22049 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22050 case BFD_RELOC_ARM_ALU_PC_G0:
22051 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22052 case BFD_RELOC_ARM_ALU_PC_G1:
22053 case BFD_RELOC_ARM_ALU_PC_G2:
22054 case BFD_RELOC_ARM_LDR_PC_G0:
22055 case BFD_RELOC_ARM_LDR_PC_G1:
22056 case BFD_RELOC_ARM_LDR_PC_G2:
22057 case BFD_RELOC_ARM_LDRS_PC_G0:
22058 case BFD_RELOC_ARM_LDRS_PC_G1:
22059 case BFD_RELOC_ARM_LDRS_PC_G2:
22060 case BFD_RELOC_ARM_LDC_PC_G0:
22061 case BFD_RELOC_ARM_LDC_PC_G1:
22062 case BFD_RELOC_ARM_LDC_PC_G2:
22063 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22064 case BFD_RELOC_ARM_ALU_SB_G0:
22065 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22066 case BFD_RELOC_ARM_ALU_SB_G1:
22067 case BFD_RELOC_ARM_ALU_SB_G2:
22068 case BFD_RELOC_ARM_LDR_SB_G0:
22069 case BFD_RELOC_ARM_LDR_SB_G1:
22070 case BFD_RELOC_ARM_LDR_SB_G2:
22071 case BFD_RELOC_ARM_LDRS_SB_G0:
22072 case BFD_RELOC_ARM_LDRS_SB_G1:
22073 case BFD_RELOC_ARM_LDRS_SB_G2:
22074 case BFD_RELOC_ARM_LDC_SB_G0:
22075 case BFD_RELOC_ARM_LDC_SB_G1:
22076 case BFD_RELOC_ARM_LDC_SB_G2:
22077 case BFD_RELOC_ARM_V4BX:
22078 code = fixp->fx_r_type;
22081 case BFD_RELOC_ARM_TLS_GOTDESC:
22082 case BFD_RELOC_ARM_TLS_GD32:
22083 case BFD_RELOC_ARM_TLS_IE32:
22084 case BFD_RELOC_ARM_TLS_LDM32:
22085 /* BFD will include the symbol's address in the addend.
22086 But we don't want that, so subtract it out again here. */
22087 if (!S_IS_COMMON (fixp->fx_addsy))
22088 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22089 code = fixp->fx_r_type;
22093 case BFD_RELOC_ARM_IMMEDIATE:
22094 as_bad_where (fixp->fx_file, fixp->fx_line,
22095 _("internal relocation (type: IMMEDIATE) not fixed up"));
22098 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22099 as_bad_where (fixp->fx_file, fixp->fx_line,
22100 _("ADRL used for a symbol not defined in the same file"));
22103 case BFD_RELOC_ARM_OFFSET_IMM:
22104 if (section->use_rela_p)
22106 code = fixp->fx_r_type;
22110 if (fixp->fx_addsy != NULL
22111 && !S_IS_DEFINED (fixp->fx_addsy)
22112 && S_IS_LOCAL (fixp->fx_addsy))
22114 as_bad_where (fixp->fx_file, fixp->fx_line,
22115 _("undefined local label `%s'"),
22116 S_GET_NAME (fixp->fx_addsy));
22120 as_bad_where (fixp->fx_file, fixp->fx_line,
22121 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22128 switch (fixp->fx_r_type)
22130 case BFD_RELOC_NONE: type = "NONE"; break;
22131 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22132 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22133 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22134 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22135 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22136 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22137 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22138 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22139 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22140 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22141 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22142 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22143 default: type = _("<unknown>"); break;
22145 as_bad_where (fixp->fx_file, fixp->fx_line,
22146 _("cannot represent %s relocation in this object file format"),
22153 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22155 && fixp->fx_addsy == GOT_symbol)
22157 code = BFD_RELOC_ARM_GOTPC;
22158 reloc->addend = fixp->fx_offset = reloc->address;
22162 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22164 if (reloc->howto == NULL)
22166 as_bad_where (fixp->fx_file, fixp->fx_line,
22167 _("cannot represent %s relocation in this object file format"),
22168 bfd_get_reloc_code_name (code));
22172 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22173 vtable entry to be used in the relocation's section offset. */
22174 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22175 reloc->address = fixp->fx_offset;
22180 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22183 cons_fix_new_arm (fragS * frag,
22188 bfd_reloc_code_real_type type;
22192 FIXME: @@ Should look at CPU word size. */
22196 type = BFD_RELOC_8;
22199 type = BFD_RELOC_16;
22203 type = BFD_RELOC_32;
22206 type = BFD_RELOC_64;
22211 if (exp->X_op == O_secrel)
22213 exp->X_op = O_symbol;
22214 type = BFD_RELOC_32_SECREL;
22218 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22221 #if defined (OBJ_COFF)
22223 arm_validate_fix (fixS * fixP)
22225 /* If the destination of the branch is a defined symbol which does not have
22226 the THUMB_FUNC attribute, then we must be calling a function which has
22227 the (interfacearm) attribute. We look for the Thumb entry point to that
22228 function and change the branch to refer to that function instead. */
22229 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22230 && fixP->fx_addsy != NULL
22231 && S_IS_DEFINED (fixP->fx_addsy)
22232 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22234 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22241 arm_force_relocation (struct fix * fixp)
22243 #if defined (OBJ_COFF) && defined (TE_PE)
22244 if (fixp->fx_r_type == BFD_RELOC_RVA)
22248 /* In case we have a call or a branch to a function in ARM ISA mode from
22249 a thumb function or vice-versa force the relocation. These relocations
22250 are cleared off for some cores that might have blx and simple transformations
22254 switch (fixp->fx_r_type)
22256 case BFD_RELOC_ARM_PCREL_JUMP:
22257 case BFD_RELOC_ARM_PCREL_CALL:
22258 case BFD_RELOC_THUMB_PCREL_BLX:
22259 if (THUMB_IS_FUNC (fixp->fx_addsy))
22263 case BFD_RELOC_ARM_PCREL_BLX:
22264 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22265 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22266 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22267 if (ARM_IS_FUNC (fixp->fx_addsy))
22276 /* Resolve these relocations even if the symbol is extern or weak.
22277 Technically this is probably wrong due to symbol preemption.
22278 In practice these relocations do not have enough range to be useful
22279 at dynamic link time, and some code (e.g. in the Linux kernel)
22280 expects these references to be resolved. */
22281 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22282 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22283 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22284 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22285 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22286 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22287 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22288 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22289 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22290 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22291 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22292 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22293 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22294 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22297 /* Always leave these relocations for the linker. */
22298 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22299 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22300 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22303 /* Always generate relocations against function symbols. */
22304 if (fixp->fx_r_type == BFD_RELOC_32
22306 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22309 return generic_force_reloc (fixp);
22312 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22313 /* Relocations against function names must be left unadjusted,
22314 so that the linker can use this information to generate interworking
22315 stubs. The MIPS version of this function
22316 also prevents relocations that are mips-16 specific, but I do not
22317 know why it does this.
22320 There is one other problem that ought to be addressed here, but
22321 which currently is not: Taking the address of a label (rather
22322 than a function) and then later jumping to that address. Such
22323 addresses also ought to have their bottom bit set (assuming that
22324 they reside in Thumb code), but at the moment they will not. */
22327 arm_fix_adjustable (fixS * fixP)
22329 if (fixP->fx_addsy == NULL)
22332 /* Preserve relocations against symbols with function type. */
22333 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22336 if (THUMB_IS_FUNC (fixP->fx_addsy)
22337 && fixP->fx_subsy == NULL)
22340 /* We need the symbol name for the VTABLE entries. */
22341 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22342 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22345 /* Don't allow symbols to be discarded on GOT related relocs. */
22346 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22347 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22348 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22349 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22350 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22351 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22352 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22353 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22354 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22355 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22356 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22357 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22358 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22359 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22362 /* Similarly for group relocations. */
22363 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22364 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22365 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22368 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22369 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22370 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22371 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22372 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22373 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22374 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22375 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22376 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22381 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22386 elf32_arm_target_format (void)
22389 return (target_big_endian
22390 ? "elf32-bigarm-symbian"
22391 : "elf32-littlearm-symbian");
22392 #elif defined (TE_VXWORKS)
22393 return (target_big_endian
22394 ? "elf32-bigarm-vxworks"
22395 : "elf32-littlearm-vxworks");
22396 #elif defined (TE_NACL)
22397 return (target_big_endian
22398 ? "elf32-bigarm-nacl"
22399 : "elf32-littlearm-nacl");
22401 if (target_big_endian)
22402 return "elf32-bigarm";
22404 return "elf32-littlearm";
22409 armelf_frob_symbol (symbolS * symp,
22412 elf_frob_symbol (symp, puntp);
22416 /* MD interface: Finalization. */
22421 literal_pool * pool;
22423 /* Ensure that all the IT blocks are properly closed. */
22424 check_it_blocks_finished ();
22426 for (pool = list_of_pools; pool; pool = pool->next)
22428 /* Put it at the end of the relevant section. */
22429 subseg_set (pool->section, pool->sub_section);
22431 arm_elf_change_section ();
22438 /* Remove any excess mapping symbols generated for alignment frags in
22439 SEC. We may have created a mapping symbol before a zero byte
22440 alignment; remove it if there's a mapping symbol after the
22443 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22444 void *dummy ATTRIBUTE_UNUSED)
22446 segment_info_type *seginfo = seg_info (sec);
22449 if (seginfo == NULL || seginfo->frchainP == NULL)
22452 for (fragp = seginfo->frchainP->frch_root;
22454 fragp = fragp->fr_next)
22456 symbolS *sym = fragp->tc_frag_data.last_map;
22457 fragS *next = fragp->fr_next;
22459 /* Variable-sized frags have been converted to fixed size by
22460 this point. But if this was variable-sized to start with,
22461 there will be a fixed-size frag after it. So don't handle
22463 if (sym == NULL || next == NULL)
22466 if (S_GET_VALUE (sym) < next->fr_address)
22467 /* Not at the end of this frag. */
22469 know (S_GET_VALUE (sym) == next->fr_address);
22473 if (next->tc_frag_data.first_map != NULL)
22475 /* Next frag starts with a mapping symbol. Discard this
22477 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22481 if (next->fr_next == NULL)
22483 /* This mapping symbol is at the end of the section. Discard
22485 know (next->fr_fix == 0 && next->fr_var == 0);
22486 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22490 /* As long as we have empty frags without any mapping symbols,
22492 /* If the next frag is non-empty and does not start with a
22493 mapping symbol, then this mapping symbol is required. */
22494 if (next->fr_address != next->fr_next->fr_address)
22497 next = next->fr_next;
22499 while (next != NULL);
22504 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22508 arm_adjust_symtab (void)
22513 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22515 if (ARM_IS_THUMB (sym))
22517 if (THUMB_IS_FUNC (sym))
22519 /* Mark the symbol as a Thumb function. */
22520 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22521 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22522 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22524 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22525 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22527 as_bad (_("%s: unexpected function type: %d"),
22528 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22530 else switch (S_GET_STORAGE_CLASS (sym))
22533 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22536 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22539 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22547 if (ARM_IS_INTERWORK (sym))
22548 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22555 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22557 if (ARM_IS_THUMB (sym))
22559 elf_symbol_type * elf_sym;
22561 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22562 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22564 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22565 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22567 /* If it's a .thumb_func, declare it as so,
22568 otherwise tag label as .code 16. */
22569 if (THUMB_IS_FUNC (sym))
22570 elf_sym->internal_elf_sym.st_target_internal
22571 = ST_BRANCH_TO_THUMB;
22572 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22573 elf_sym->internal_elf_sym.st_info =
22574 ELF_ST_INFO (bind, STT_ARM_16BIT);
22579 /* Remove any overlapping mapping symbols generated by alignment frags. */
22580 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22581 /* Now do generic ELF adjustments. */
22582 elf_adjust_symtab ();
22586 /* MD interface: Initialization. */
22589 set_constant_flonums (void)
22593 for (i = 0; i < NUM_FLOAT_VALS; i++)
22594 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22598 /* Auto-select Thumb mode if it's the only available instruction set for the
22599 given architecture. */
22602 autoselect_thumb_from_cpu_variant (void)
22604 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22605 opcode_select (16);
22614 if ( (arm_ops_hsh = hash_new ()) == NULL
22615 || (arm_cond_hsh = hash_new ()) == NULL
22616 || (arm_shift_hsh = hash_new ()) == NULL
22617 || (arm_psr_hsh = hash_new ()) == NULL
22618 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22619 || (arm_reg_hsh = hash_new ()) == NULL
22620 || (arm_reloc_hsh = hash_new ()) == NULL
22621 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22622 as_fatal (_("virtual memory exhausted"));
22624 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22625 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22626 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22627 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22628 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22629 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22630 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22631 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22632 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22633 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22634 (void *) (v7m_psrs + i));
22635 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22636 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22638 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22640 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22641 (void *) (barrier_opt_names + i));
22643 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22645 struct reloc_entry * entry = reloc_names + i;
22647 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22648 /* This makes encode_branch() use the EABI versions of this relocation. */
22649 entry->reloc = BFD_RELOC_UNUSED;
22651 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22655 set_constant_flonums ();
22657 /* Set the cpu variant based on the command-line options. We prefer
22658 -mcpu= over -march= if both are set (as for GCC); and we prefer
22659 -mfpu= over any other way of setting the floating point unit.
22660 Use of legacy options with new options are faulted. */
22663 if (mcpu_cpu_opt || march_cpu_opt)
22664 as_bad (_("use of old and new-style options to set CPU type"));
22666 mcpu_cpu_opt = legacy_cpu;
22668 else if (!mcpu_cpu_opt)
22669 mcpu_cpu_opt = march_cpu_opt;
22674 as_bad (_("use of old and new-style options to set FPU type"));
22676 mfpu_opt = legacy_fpu;
22678 else if (!mfpu_opt)
22680 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22681 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22682 /* Some environments specify a default FPU. If they don't, infer it
22683 from the processor. */
22685 mfpu_opt = mcpu_fpu_opt;
22687 mfpu_opt = march_fpu_opt;
22689 mfpu_opt = &fpu_default;
22695 if (mcpu_cpu_opt != NULL)
22696 mfpu_opt = &fpu_default;
22697 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22698 mfpu_opt = &fpu_arch_vfp_v2;
22700 mfpu_opt = &fpu_arch_fpa;
22706 mcpu_cpu_opt = &cpu_default;
22707 selected_cpu = cpu_default;
22711 selected_cpu = *mcpu_cpu_opt;
22713 mcpu_cpu_opt = &arm_arch_any;
22716 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22718 autoselect_thumb_from_cpu_variant ();
22720 arm_arch_used = thumb_arch_used = arm_arch_none;
22722 #if defined OBJ_COFF || defined OBJ_ELF
22724 unsigned int flags = 0;
22726 #if defined OBJ_ELF
22727 flags = meabi_flags;
22729 switch (meabi_flags)
22731 case EF_ARM_EABI_UNKNOWN:
22733 /* Set the flags in the private structure. */
22734 if (uses_apcs_26) flags |= F_APCS26;
22735 if (support_interwork) flags |= F_INTERWORK;
22736 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22737 if (pic_code) flags |= F_PIC;
22738 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22739 flags |= F_SOFT_FLOAT;
22741 switch (mfloat_abi_opt)
22743 case ARM_FLOAT_ABI_SOFT:
22744 case ARM_FLOAT_ABI_SOFTFP:
22745 flags |= F_SOFT_FLOAT;
22748 case ARM_FLOAT_ABI_HARD:
22749 if (flags & F_SOFT_FLOAT)
22750 as_bad (_("hard-float conflicts with specified fpu"));
22754 /* Using pure-endian doubles (even if soft-float). */
22755 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22756 flags |= F_VFP_FLOAT;
22758 #if defined OBJ_ELF
22759 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22760 flags |= EF_ARM_MAVERICK_FLOAT;
22763 case EF_ARM_EABI_VER4:
22764 case EF_ARM_EABI_VER5:
22765 /* No additional flags to set. */
22772 bfd_set_private_flags (stdoutput, flags);
22774 /* We have run out flags in the COFF header to encode the
22775 status of ATPCS support, so instead we create a dummy,
22776 empty, debug section called .arm.atpcs. */
22781 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22785 bfd_set_section_flags
22786 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22787 bfd_set_section_size (stdoutput, sec, 0);
22788 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22794 /* Record the CPU type as well. */
22795 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22796 mach = bfd_mach_arm_iWMMXt2;
22797 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22798 mach = bfd_mach_arm_iWMMXt;
22799 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22800 mach = bfd_mach_arm_XScale;
22801 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22802 mach = bfd_mach_arm_ep9312;
22803 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22804 mach = bfd_mach_arm_5TE;
22805 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22807 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22808 mach = bfd_mach_arm_5T;
22810 mach = bfd_mach_arm_5;
22812 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22814 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22815 mach = bfd_mach_arm_4T;
22817 mach = bfd_mach_arm_4;
22819 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22820 mach = bfd_mach_arm_3M;
22821 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22822 mach = bfd_mach_arm_3;
22823 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22824 mach = bfd_mach_arm_2a;
22825 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22826 mach = bfd_mach_arm_2;
22828 mach = bfd_mach_arm_unknown;
22830 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22833 /* Command line processing. */
22836 Invocation line includes a switch not recognized by the base assembler.
22837 See if it's a processor-specific option.
22839 This routine is somewhat complicated by the need for backwards
22840 compatibility (since older releases of gcc can't be changed).
22841 The new options try to make the interface as compatible as
22844 New options (supported) are:
22846 -mcpu=<cpu name> Assemble for selected processor
22847 -march=<architecture name> Assemble for selected architecture
22848 -mfpu=<fpu architecture> Assemble for selected FPU.
22849 -EB/-mbig-endian Big-endian
22850 -EL/-mlittle-endian Little-endian
22851 -k Generate PIC code
22852 -mthumb Start in Thumb mode
22853 -mthumb-interwork Code supports ARM/Thumb interworking
22855 -m[no-]warn-deprecated Warn about deprecated features
22857 For now we will also provide support for:
22859 -mapcs-32 32-bit Program counter
22860 -mapcs-26 26-bit Program counter
22861 -macps-float Floats passed in FP registers
22862 -mapcs-reentrant Reentrant code
22864 (sometime these will probably be replaced with -mapcs=<list of options>
22865 and -matpcs=<list of options>)
22867 The remaining options are only supported for back-wards compatibility.
22868 Cpu variants, the arm part is optional:
22869 -m[arm]1 Currently not supported.
22870 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22871 -m[arm]3 Arm 3 processor
22872 -m[arm]6[xx], Arm 6 processors
22873 -m[arm]7[xx][t][[d]m] Arm 7 processors
22874 -m[arm]8[10] Arm 8 processors
22875 -m[arm]9[20][tdmi] Arm 9 processors
22876 -mstrongarm[110[0]] StrongARM processors
22877 -mxscale XScale processors
22878 -m[arm]v[2345[t[e]]] Arm architectures
22879 -mall All (except the ARM1)
22881 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22882 -mfpe-old (No float load/store multiples)
22883 -mvfpxd VFP Single precision
22885 -mno-fpu Disable all floating point instructions
22887 The following CPU names are recognized:
22888 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22889 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22890 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22891 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22892 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22893 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22894 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22898 const char * md_shortopts = "m:k";
22900 #ifdef ARM_BI_ENDIAN
22901 #define OPTION_EB (OPTION_MD_BASE + 0)
22902 #define OPTION_EL (OPTION_MD_BASE + 1)
22904 #if TARGET_BYTES_BIG_ENDIAN
22905 #define OPTION_EB (OPTION_MD_BASE + 0)
22907 #define OPTION_EL (OPTION_MD_BASE + 1)
22910 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22912 struct option md_longopts[] =
22915 {"EB", no_argument, NULL, OPTION_EB},
22918 {"EL", no_argument, NULL, OPTION_EL},
22920 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22921 {NULL, no_argument, NULL, 0}
22924 size_t md_longopts_size = sizeof (md_longopts);
22926 struct arm_option_table
22928 char *option; /* Option name to match. */
22929 char *help; /* Help information. */
22930 int *var; /* Variable to change. */
22931 int value; /* What to change it to. */
22932 char *deprecated; /* If non-null, print this message. */
22935 struct arm_option_table arm_opts[] =
22937 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22938 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22939 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22940 &support_interwork, 1, NULL},
22941 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22942 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22943 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22945 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22946 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22947 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22948 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22951 /* These are recognized by the assembler, but have no affect on code. */
22952 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22953 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22955 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22956 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22957 &warn_on_deprecated, 0, NULL},
22958 {NULL, NULL, NULL, 0, NULL}
22961 struct arm_legacy_option_table
22963 char *option; /* Option name to match. */
22964 const arm_feature_set **var; /* Variable to change. */
22965 const arm_feature_set value; /* What to change it to. */
22966 char *deprecated; /* If non-null, print this message. */
22969 const struct arm_legacy_option_table arm_legacy_opts[] =
22971 /* DON'T add any new processors to this list -- we want the whole list
22972 to go away... Add them to the processors table instead. */
22973 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22974 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22975 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22976 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22977 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22978 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22979 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22980 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22981 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22982 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22983 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22984 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22985 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22986 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22987 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22988 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22989 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22990 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22991 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22992 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22993 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22994 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22995 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22996 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22997 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22998 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22999 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23000 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23001 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23002 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23003 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23004 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23005 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23006 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23007 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23008 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23009 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23010 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23011 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23012 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23013 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23014 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23015 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23016 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23017 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23018 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23019 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23020 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23021 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23022 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23023 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23024 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23025 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23026 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23027 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23028 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23029 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23030 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23031 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23032 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23033 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23034 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23035 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23036 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23037 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23038 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23039 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23040 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23041 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23042 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23043 N_("use -mcpu=strongarm110")},
23044 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23045 N_("use -mcpu=strongarm1100")},
23046 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23047 N_("use -mcpu=strongarm1110")},
23048 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23049 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23050 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23052 /* Architecture variants -- don't add any more to this list either. */
23053 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23054 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23055 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23056 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23057 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23058 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23059 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23060 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23061 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23062 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23063 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23064 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23065 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23066 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23067 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23068 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23069 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23070 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23072 /* Floating point variants -- don't add any more to this list either. */
23073 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23074 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23075 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23076 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23077 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23079 {NULL, NULL, ARM_ARCH_NONE, NULL}
23082 struct arm_cpu_option_table
23086 const arm_feature_set value;
23087 /* For some CPUs we assume an FPU unless the user explicitly sets
23089 const arm_feature_set default_fpu;
23090 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23092 const char *canonical_name;
23095 /* This list should, at a minimum, contain all the cpu names
23096 recognized by GCC. */
23097 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23098 static const struct arm_cpu_option_table arm_cpus[] =
23100 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23101 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23102 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23103 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23104 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23105 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23106 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23107 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23108 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23109 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23110 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23111 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23112 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23113 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23114 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23115 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23116 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23117 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23118 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23119 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23120 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23121 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23122 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23123 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23124 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23125 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23126 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23127 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23128 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23129 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23130 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23131 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23132 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23133 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23134 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23135 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23136 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23137 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23138 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23139 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23140 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23141 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23142 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23143 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23144 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23145 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23146 /* For V5 or later processors we default to using VFP; but the user
23147 should really set the FPU type explicitly. */
23148 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23149 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23150 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23151 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23152 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23153 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23154 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23155 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23156 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23157 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23158 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23159 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23160 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23161 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23162 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23163 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23164 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23165 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23166 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23167 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23169 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23170 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23171 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23172 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23173 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23174 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23175 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23176 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23177 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23179 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23180 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23181 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23182 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23183 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23184 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23185 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23186 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23187 FPU_NONE, "Cortex-A5"),
23188 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23189 FPU_ARCH_NEON_VFP_V4,
23191 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23192 ARM_FEATURE (0, FPU_VFP_V3
23193 | FPU_NEON_EXT_V1),
23195 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23196 ARM_FEATURE (0, FPU_VFP_V3
23197 | FPU_NEON_EXT_V1),
23199 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23200 FPU_ARCH_NEON_VFP_V4,
23202 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23203 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23205 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23206 FPU_NONE, "Cortex-R5"),
23207 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23208 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23209 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23210 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23211 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23212 /* ??? XSCALE is really an architecture. */
23213 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23214 /* ??? iwmmxt is not a processor. */
23215 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23216 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23217 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23219 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23222 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23226 struct arm_arch_option_table
23230 const arm_feature_set value;
23231 const arm_feature_set default_fpu;
23234 /* This list should, at a minimum, contain all the architecture names
23235 recognized by GCC. */
23236 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23237 static const struct arm_arch_option_table arm_archs[] =
23239 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23240 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23241 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23242 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23243 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23244 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23245 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23246 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23247 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23248 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23249 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23250 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23251 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23252 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23253 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23254 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23255 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23256 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23257 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23258 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23259 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23260 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23261 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23262 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23263 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23264 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23265 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23266 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23267 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23268 /* The official spelling of the ARMv7 profile variants is the dashed form.
23269 Accept the non-dashed form for compatibility with old toolchains. */
23270 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23271 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23272 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23273 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23274 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23275 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23276 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23277 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
23278 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23279 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23280 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23281 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23283 #undef ARM_ARCH_OPT
23285 /* ISA extensions in the co-processor and main instruction set space. */
23286 struct arm_option_extension_value_table
23290 const arm_feature_set value;
23291 const arm_feature_set allowed_archs;
23294 /* The following table must be in alphabetical order with a NULL last entry.
23296 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23297 static const struct arm_option_extension_value_table arm_extensions[] =
23299 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23300 ARM_FEATURE (ARM_EXT_V8, 0)),
23301 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
23302 ARM_FEATURE (ARM_EXT_V8, 0)),
23303 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23304 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23305 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23306 ARM_EXT_OPT ("iwmmxt2",
23307 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23308 ARM_EXT_OPT ("maverick",
23309 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23310 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23311 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23312 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
23313 ARM_FEATURE (ARM_EXT_V8, 0)),
23314 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23315 ARM_FEATURE (ARM_EXT_V6M, 0)),
23316 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23317 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23318 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23320 ARM_FEATURE (ARM_EXT_V7A, 0)),
23321 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23322 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23326 /* ISA floating-point and Advanced SIMD extensions. */
23327 struct arm_option_fpu_value_table
23330 const arm_feature_set value;
23333 /* This list should, at a minimum, contain all the fpu names
23334 recognized by GCC. */
23335 static const struct arm_option_fpu_value_table arm_fpus[] =
23337 {"softfpa", FPU_NONE},
23338 {"fpe", FPU_ARCH_FPE},
23339 {"fpe2", FPU_ARCH_FPE},
23340 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23341 {"fpa", FPU_ARCH_FPA},
23342 {"fpa10", FPU_ARCH_FPA},
23343 {"fpa11", FPU_ARCH_FPA},
23344 {"arm7500fe", FPU_ARCH_FPA},
23345 {"softvfp", FPU_ARCH_VFP},
23346 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23347 {"vfp", FPU_ARCH_VFP_V2},
23348 {"vfp9", FPU_ARCH_VFP_V2},
23349 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23350 {"vfp10", FPU_ARCH_VFP_V2},
23351 {"vfp10-r0", FPU_ARCH_VFP_V1},
23352 {"vfpxd", FPU_ARCH_VFP_V1xD},
23353 {"vfpv2", FPU_ARCH_VFP_V2},
23354 {"vfpv3", FPU_ARCH_VFP_V3},
23355 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23356 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23357 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23358 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23359 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23360 {"arm1020t", FPU_ARCH_VFP_V1},
23361 {"arm1020e", FPU_ARCH_VFP_V2},
23362 {"arm1136jfs", FPU_ARCH_VFP_V2},
23363 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23364 {"maverick", FPU_ARCH_MAVERICK},
23365 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23366 {"neon-fp16", FPU_ARCH_NEON_FP16},
23367 {"vfpv4", FPU_ARCH_VFP_V4},
23368 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23369 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23370 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23371 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
23372 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
23373 {"crypto-neon-fp-armv8",
23374 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
23375 {NULL, ARM_ARCH_NONE}
23378 struct arm_option_value_table
23384 static const struct arm_option_value_table arm_float_abis[] =
23386 {"hard", ARM_FLOAT_ABI_HARD},
23387 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23388 {"soft", ARM_FLOAT_ABI_SOFT},
23393 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23394 static const struct arm_option_value_table arm_eabis[] =
23396 {"gnu", EF_ARM_EABI_UNKNOWN},
23397 {"4", EF_ARM_EABI_VER4},
23398 {"5", EF_ARM_EABI_VER5},
23403 struct arm_long_option_table
23405 char * option; /* Substring to match. */
23406 char * help; /* Help information. */
23407 int (* func) (char * subopt); /* Function to decode sub-option. */
23408 char * deprecated; /* If non-null, print this message. */
23412 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23414 arm_feature_set *ext_set = (arm_feature_set *)
23415 xmalloc (sizeof (arm_feature_set));
23417 /* We insist on extensions being specified in alphabetical order, and with
23418 extensions being added before being removed. We achieve this by having
23419 the global ARM_EXTENSIONS table in alphabetical order, and using the
23420 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23421 or removing it (0) and only allowing it to change in the order
23423 const struct arm_option_extension_value_table * opt = NULL;
23424 int adding_value = -1;
23426 /* Copy the feature set, so that we can modify it. */
23427 *ext_set = **opt_p;
23430 while (str != NULL && *str != 0)
23437 as_bad (_("invalid architectural extension"));
23442 ext = strchr (str, '+');
23447 len = strlen (str);
23449 if (len >= 2 && strncmp (str, "no", 2) == 0)
23451 if (adding_value != 0)
23454 opt = arm_extensions;
23462 if (adding_value == -1)
23465 opt = arm_extensions;
23467 else if (adding_value != 1)
23469 as_bad (_("must specify extensions to add before specifying "
23470 "those to remove"));
23477 as_bad (_("missing architectural extension"));
23481 gas_assert (adding_value != -1);
23482 gas_assert (opt != NULL);
23484 /* Scan over the options table trying to find an exact match. */
23485 for (; opt->name != NULL; opt++)
23486 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23488 /* Check we can apply the extension to this architecture. */
23489 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23491 as_bad (_("extension does not apply to the base architecture"));
23495 /* Add or remove the extension. */
23497 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23499 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23504 if (opt->name == NULL)
23506 /* Did we fail to find an extension because it wasn't specified in
23507 alphabetical order, or because it does not exist? */
23509 for (opt = arm_extensions; opt->name != NULL; opt++)
23510 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23513 if (opt->name == NULL)
23514 as_bad (_("unknown architectural extension `%s'"), str);
23516 as_bad (_("architectural extensions must be specified in "
23517 "alphabetical order"));
23523 /* We should skip the extension we've just matched the next time
23535 arm_parse_cpu (char *str)
23537 const struct arm_cpu_option_table *opt;
23538 char *ext = strchr (str, '+');
23544 len = strlen (str);
23548 as_bad (_("missing cpu name `%s'"), str);
23552 for (opt = arm_cpus; opt->name != NULL; opt++)
23553 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23555 mcpu_cpu_opt = &opt->value;
23556 mcpu_fpu_opt = &opt->default_fpu;
23557 if (opt->canonical_name)
23558 strcpy (selected_cpu_name, opt->canonical_name);
23563 for (i = 0; i < len; i++)
23564 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23565 selected_cpu_name[i] = 0;
23569 return arm_parse_extension (ext, &mcpu_cpu_opt);
23574 as_bad (_("unknown cpu `%s'"), str);
23579 arm_parse_arch (char *str)
23581 const struct arm_arch_option_table *opt;
23582 char *ext = strchr (str, '+');
23588 len = strlen (str);
23592 as_bad (_("missing architecture name `%s'"), str);
23596 for (opt = arm_archs; opt->name != NULL; opt++)
23597 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23599 march_cpu_opt = &opt->value;
23600 march_fpu_opt = &opt->default_fpu;
23601 strcpy (selected_cpu_name, opt->name);
23604 return arm_parse_extension (ext, &march_cpu_opt);
23609 as_bad (_("unknown architecture `%s'\n"), str);
23614 arm_parse_fpu (char * str)
23616 const struct arm_option_fpu_value_table * opt;
23618 for (opt = arm_fpus; opt->name != NULL; opt++)
23619 if (streq (opt->name, str))
23621 mfpu_opt = &opt->value;
23625 as_bad (_("unknown floating point format `%s'\n"), str);
23630 arm_parse_float_abi (char * str)
23632 const struct arm_option_value_table * opt;
23634 for (opt = arm_float_abis; opt->name != NULL; opt++)
23635 if (streq (opt->name, str))
23637 mfloat_abi_opt = opt->value;
23641 as_bad (_("unknown floating point abi `%s'\n"), str);
23647 arm_parse_eabi (char * str)
23649 const struct arm_option_value_table *opt;
23651 for (opt = arm_eabis; opt->name != NULL; opt++)
23652 if (streq (opt->name, str))
23654 meabi_flags = opt->value;
23657 as_bad (_("unknown EABI `%s'\n"), str);
23663 arm_parse_it_mode (char * str)
23665 bfd_boolean ret = TRUE;
23667 if (streq ("arm", str))
23668 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23669 else if (streq ("thumb", str))
23670 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23671 else if (streq ("always", str))
23672 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23673 else if (streq ("never", str))
23674 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23677 as_bad (_("unknown implicit IT mode `%s', should be "\
23678 "arm, thumb, always, or never."), str);
23685 struct arm_long_option_table arm_long_opts[] =
23687 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23688 arm_parse_cpu, NULL},
23689 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23690 arm_parse_arch, NULL},
23691 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23692 arm_parse_fpu, NULL},
23693 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23694 arm_parse_float_abi, NULL},
23696 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23697 arm_parse_eabi, NULL},
23699 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23700 arm_parse_it_mode, NULL},
23701 {NULL, NULL, 0, NULL}
23705 md_parse_option (int c, char * arg)
23707 struct arm_option_table *opt;
23708 const struct arm_legacy_option_table *fopt;
23709 struct arm_long_option_table *lopt;
23715 target_big_endian = 1;
23721 target_big_endian = 0;
23725 case OPTION_FIX_V4BX:
23730 /* Listing option. Just ignore these, we don't support additional
23735 for (opt = arm_opts; opt->option != NULL; opt++)
23737 if (c == opt->option[0]
23738 && ((arg == NULL && opt->option[1] == 0)
23739 || streq (arg, opt->option + 1)))
23741 /* If the option is deprecated, tell the user. */
23742 if (warn_on_deprecated && opt->deprecated != NULL)
23743 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23744 arg ? arg : "", _(opt->deprecated));
23746 if (opt->var != NULL)
23747 *opt->var = opt->value;
23753 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23755 if (c == fopt->option[0]
23756 && ((arg == NULL && fopt->option[1] == 0)
23757 || streq (arg, fopt->option + 1)))
23759 /* If the option is deprecated, tell the user. */
23760 if (warn_on_deprecated && fopt->deprecated != NULL)
23761 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23762 arg ? arg : "", _(fopt->deprecated));
23764 if (fopt->var != NULL)
23765 *fopt->var = &fopt->value;
23771 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23773 /* These options are expected to have an argument. */
23774 if (c == lopt->option[0]
23776 && strncmp (arg, lopt->option + 1,
23777 strlen (lopt->option + 1)) == 0)
23779 /* If the option is deprecated, tell the user. */
23780 if (warn_on_deprecated && lopt->deprecated != NULL)
23781 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23782 _(lopt->deprecated));
23784 /* Call the sup-option parser. */
23785 return lopt->func (arg + strlen (lopt->option) - 1);
23796 md_show_usage (FILE * fp)
23798 struct arm_option_table *opt;
23799 struct arm_long_option_table *lopt;
23801 fprintf (fp, _(" ARM-specific assembler options:\n"));
23803 for (opt = arm_opts; opt->option != NULL; opt++)
23804 if (opt->help != NULL)
23805 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23807 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23808 if (lopt->help != NULL)
23809 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23813 -EB assemble code for a big-endian cpu\n"));
23818 -EL assemble code for a little-endian cpu\n"));
23822 --fix-v4bx Allow BX in ARMv4 code\n"));
23830 arm_feature_set flags;
23831 } cpu_arch_ver_table;
23833 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23834 least features first. */
23835 static const cpu_arch_ver_table cpu_arch_ver[] =
23841 {4, ARM_ARCH_V5TE},
23842 {5, ARM_ARCH_V5TEJ},
23846 {11, ARM_ARCH_V6M},
23847 {12, ARM_ARCH_V6SM},
23848 {8, ARM_ARCH_V6T2},
23849 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
23850 {10, ARM_ARCH_V7R},
23851 {10, ARM_ARCH_V7M},
23852 {14, ARM_ARCH_V8A},
23856 /* Set an attribute if it has not already been set by the user. */
23858 aeabi_set_attribute_int (int tag, int value)
23861 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23862 || !attributes_set_explicitly[tag])
23863 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23867 aeabi_set_attribute_string (int tag, const char *value)
23870 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23871 || !attributes_set_explicitly[tag])
23872 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23875 /* Set the public EABI object attributes. */
23877 aeabi_set_public_attributes (void)
23882 int fp16_optional = 0;
23883 arm_feature_set flags;
23884 arm_feature_set tmp;
23885 const cpu_arch_ver_table *p;
23887 /* Choose the architecture based on the capabilities of the requested cpu
23888 (if any) and/or the instructions actually used. */
23889 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23890 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23891 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23893 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23894 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23896 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23897 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23899 /* Allow the user to override the reported architecture. */
23902 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23903 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23906 /* We need to make sure that the attributes do not identify us as v6S-M
23907 when the only v6S-M feature in use is the Operating System Extensions. */
23908 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23909 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23910 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23914 for (p = cpu_arch_ver; p->val; p++)
23916 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23919 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23923 /* The table lookup above finds the last architecture to contribute
23924 a new feature. Unfortunately, Tag13 is a subset of the union of
23925 v6T2 and v7-M, so it is never seen as contributing a new feature.
23926 We can not search for the last entry which is entirely used,
23927 because if no CPU is specified we build up only those flags
23928 actually used. Perhaps we should separate out the specified
23929 and implicit cases. Avoid taking this path for -march=all by
23930 checking for contradictory v7-A / v7-M features. */
23932 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23933 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23934 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23937 /* Tag_CPU_name. */
23938 if (selected_cpu_name[0])
23942 q = selected_cpu_name;
23943 if (strncmp (q, "armv", 4) == 0)
23948 for (i = 0; q[i]; i++)
23949 q[i] = TOUPPER (q[i]);
23951 aeabi_set_attribute_string (Tag_CPU_name, q);
23954 /* Tag_CPU_arch. */
23955 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23957 /* Tag_CPU_arch_profile. */
23958 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23960 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23962 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23967 if (profile != '\0')
23968 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
23970 /* Tag_ARM_ISA_use. */
23971 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23973 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23975 /* Tag_THUMB_ISA_use. */
23976 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23978 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23979 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23981 /* Tag_VFP_arch. */
23982 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
23983 aeabi_set_attribute_int (Tag_VFP_arch, 7);
23984 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23985 aeabi_set_attribute_int (Tag_VFP_arch,
23986 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23988 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23991 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23993 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23995 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23998 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23999 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24000 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24001 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24002 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24004 /* Tag_ABI_HardFP_use. */
24005 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24006 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24007 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24009 /* Tag_WMMX_arch. */
24010 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24011 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24012 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24013 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24015 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24016 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24017 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24018 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24020 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24022 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24026 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24031 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24032 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24033 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24037 We set Tag_DIV_use to two when integer divide instructions have been used
24038 in ARM state, or when Thumb integer divide instructions have been used,
24039 but we have no architecture profile set, nor have we any ARM instructions.
24041 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24044 For new architectures we will have to check these tests. */
24045 gas_assert (arch <= TAG_CPU_ARCH_V8);
24046 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24047 aeabi_set_attribute_int (Tag_DIV_use, 0);
24048 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24049 || (profile == '\0'
24050 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24051 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24052 aeabi_set_attribute_int (Tag_DIV_use, 2);
24054 /* Tag_MP_extension_use. */
24055 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24056 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24058 /* Tag Virtualization_use. */
24059 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24061 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24064 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24067 /* Add the default contents for the .ARM.attributes section. */
24071 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24074 aeabi_set_public_attributes ();
24076 #endif /* OBJ_ELF */
24079 /* Parse a .cpu directive. */
24082 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24084 const struct arm_cpu_option_table *opt;
24088 name = input_line_pointer;
24089 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24090 input_line_pointer++;
24091 saved_char = *input_line_pointer;
24092 *input_line_pointer = 0;
24094 /* Skip the first "all" entry. */
24095 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24096 if (streq (opt->name, name))
24098 mcpu_cpu_opt = &opt->value;
24099 selected_cpu = opt->value;
24100 if (opt->canonical_name)
24101 strcpy (selected_cpu_name, opt->canonical_name);
24105 for (i = 0; opt->name[i]; i++)
24106 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24108 selected_cpu_name[i] = 0;
24110 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24111 *input_line_pointer = saved_char;
24112 demand_empty_rest_of_line ();
24115 as_bad (_("unknown cpu `%s'"), name);
24116 *input_line_pointer = saved_char;
24117 ignore_rest_of_line ();
24121 /* Parse a .arch directive. */
24124 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24126 const struct arm_arch_option_table *opt;
24130 name = input_line_pointer;
24131 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24132 input_line_pointer++;
24133 saved_char = *input_line_pointer;
24134 *input_line_pointer = 0;
24136 /* Skip the first "all" entry. */
24137 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24138 if (streq (opt->name, name))
24140 mcpu_cpu_opt = &opt->value;
24141 selected_cpu = opt->value;
24142 strcpy (selected_cpu_name, opt->name);
24143 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24144 *input_line_pointer = saved_char;
24145 demand_empty_rest_of_line ();
24149 as_bad (_("unknown architecture `%s'\n"), name);
24150 *input_line_pointer = saved_char;
24151 ignore_rest_of_line ();
24155 /* Parse a .object_arch directive. */
24158 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24160 const struct arm_arch_option_table *opt;
24164 name = input_line_pointer;
24165 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24166 input_line_pointer++;
24167 saved_char = *input_line_pointer;
24168 *input_line_pointer = 0;
24170 /* Skip the first "all" entry. */
24171 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24172 if (streq (opt->name, name))
24174 object_arch = &opt->value;
24175 *input_line_pointer = saved_char;
24176 demand_empty_rest_of_line ();
24180 as_bad (_("unknown architecture `%s'\n"), name);
24181 *input_line_pointer = saved_char;
24182 ignore_rest_of_line ();
24185 /* Parse a .arch_extension directive. */
24188 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24190 const struct arm_option_extension_value_table *opt;
24193 int adding_value = 1;
24195 name = input_line_pointer;
24196 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24197 input_line_pointer++;
24198 saved_char = *input_line_pointer;
24199 *input_line_pointer = 0;
24201 if (strlen (name) >= 2
24202 && strncmp (name, "no", 2) == 0)
24208 for (opt = arm_extensions; opt->name != NULL; opt++)
24209 if (streq (opt->name, name))
24211 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24213 as_bad (_("architectural extension `%s' is not allowed for the "
24214 "current base architecture"), name);
24219 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24221 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24223 mcpu_cpu_opt = &selected_cpu;
24224 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24225 *input_line_pointer = saved_char;
24226 demand_empty_rest_of_line ();
24230 if (opt->name == NULL)
24231 as_bad (_("unknown architecture `%s'\n"), name);
24233 *input_line_pointer = saved_char;
24234 ignore_rest_of_line ();
24237 /* Parse a .fpu directive. */
24240 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24242 const struct arm_option_fpu_value_table *opt;
24246 name = input_line_pointer;
24247 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24248 input_line_pointer++;
24249 saved_char = *input_line_pointer;
24250 *input_line_pointer = 0;
24252 for (opt = arm_fpus; opt->name != NULL; opt++)
24253 if (streq (opt->name, name))
24255 mfpu_opt = &opt->value;
24256 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24257 *input_line_pointer = saved_char;
24258 demand_empty_rest_of_line ();
24262 as_bad (_("unknown floating point format `%s'\n"), name);
24263 *input_line_pointer = saved_char;
24264 ignore_rest_of_line ();
24267 /* Copy symbol information. */
24270 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24272 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24276 /* Given a symbolic attribute NAME, return the proper integer value.
24277 Returns -1 if the attribute is not known. */
24280 arm_convert_symbolic_attribute (const char *name)
24282 static const struct
24287 attribute_table[] =
24289 /* When you modify this table you should
24290 also modify the list in doc/c-arm.texi. */
24291 #define T(tag) {#tag, tag}
24292 T (Tag_CPU_raw_name),
24295 T (Tag_CPU_arch_profile),
24296 T (Tag_ARM_ISA_use),
24297 T (Tag_THUMB_ISA_use),
24301 T (Tag_Advanced_SIMD_arch),
24302 T (Tag_PCS_config),
24303 T (Tag_ABI_PCS_R9_use),
24304 T (Tag_ABI_PCS_RW_data),
24305 T (Tag_ABI_PCS_RO_data),
24306 T (Tag_ABI_PCS_GOT_use),
24307 T (Tag_ABI_PCS_wchar_t),
24308 T (Tag_ABI_FP_rounding),
24309 T (Tag_ABI_FP_denormal),
24310 T (Tag_ABI_FP_exceptions),
24311 T (Tag_ABI_FP_user_exceptions),
24312 T (Tag_ABI_FP_number_model),
24313 T (Tag_ABI_align_needed),
24314 T (Tag_ABI_align8_needed),
24315 T (Tag_ABI_align_preserved),
24316 T (Tag_ABI_align8_preserved),
24317 T (Tag_ABI_enum_size),
24318 T (Tag_ABI_HardFP_use),
24319 T (Tag_ABI_VFP_args),
24320 T (Tag_ABI_WMMX_args),
24321 T (Tag_ABI_optimization_goals),
24322 T (Tag_ABI_FP_optimization_goals),
24323 T (Tag_compatibility),
24324 T (Tag_CPU_unaligned_access),
24325 T (Tag_FP_HP_extension),
24326 T (Tag_VFP_HP_extension),
24327 T (Tag_ABI_FP_16bit_format),
24328 T (Tag_MPextension_use),
24330 T (Tag_nodefaults),
24331 T (Tag_also_compatible_with),
24332 T (Tag_conformance),
24334 T (Tag_Virtualization_use),
24335 /* We deliberately do not include Tag_MPextension_use_legacy. */
24343 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24344 if (streq (name, attribute_table[i].name))
24345 return attribute_table[i].tag;
24351 /* Apply sym value for relocations only in the case that
24352 they are for local symbols and you have the respective
24353 architectural feature for blx and simple switches. */
24355 arm_apply_sym_value (struct fix * fixP)
24358 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24359 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24361 switch (fixP->fx_r_type)
24363 case BFD_RELOC_ARM_PCREL_BLX:
24364 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24365 if (ARM_IS_FUNC (fixP->fx_addsy))
24369 case BFD_RELOC_ARM_PCREL_CALL:
24370 case BFD_RELOC_THUMB_PCREL_BLX:
24371 if (THUMB_IS_FUNC (fixP->fx_addsy))
24382 #endif /* OBJ_ELF */