1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 /* Need TARGET_CPU. */
40 /* Types of processor to assemble for. */
41 #define ARM_1 0x00000001
42 #define ARM_2 0x00000002
43 #define ARM_3 0x00000004
45 #define ARM_6 0x00000008
46 #define ARM_7 ARM_6 /* Same core instruction set. */
47 #define ARM_8 ARM_6 /* Same core instruction set. */
48 #define ARM_9 ARM_6 /* Same core instruction set. */
49 #define ARM_CPU_MASK 0x0000000f
51 /* The following bitmasks control CPU extensions (ARM7 onwards): */
52 #define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
53 #define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
54 #define ARM_THUMB 0x00000040 /* Allow BX instruction. */
55 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only. */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations. */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
83 #define CPU_DEFAULT ARM_ALL
88 #define FPU_DEFAULT FPU_ALL
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
94 static unsigned long cpu_variant = CPU_DEFAULT | FPU_DEFAULT;
95 static int target_oabi = 0;
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure. */
99 static boolean uses_apcs_26 = false;
100 static boolean support_interwork = false;
101 static boolean uses_apcs_float = false;
102 static boolean pic_code = false;
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST char comment_chars[] = "@";
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST char line_comment_chars[] = "#";
118 CONST char line_separator_chars[] = ";";
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST char EXP_CHARS[] = "eE";
124 /* Chars that mean this number is a floating point constant. */
128 CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
130 /* Prefix characters that indicate the start of an immediate
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
135 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
136 symbolS * GOT_symbol;
139 /* Size of relocation record. */
140 CONST int md_reloc_size = 8;
142 /* 0: assemble for ARM,
143 1: assemble for Thumb,
144 2: assemble for Thumb even though target CPU does not support thumb
146 static int thumb_mode = 0;
148 typedef struct arm_fix
156 unsigned long instruction;
161 bfd_reloc_code_real_type type;
171 CONST char * template;
175 static CONST struct asm_shift shift[] =
191 #define NO_SHIFT_RESTRICT 1
192 #define SHIFT_RESTRICT 0
194 #define NUM_FLOAT_VALS 8
196 CONST char * fp_const[] =
198 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
201 /* Number of littlenums required to hold an extended precision number. */
202 #define MAX_LITTLENUMS 6
204 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
214 #define CP_T_X 0x00008000
215 #define CP_T_Y 0x00400000
216 #define CP_T_Pre 0x01000000
217 #define CP_T_UD 0x00800000
218 #define CP_T_WB 0x00200000
220 #define CONDS_BIT (0x00100000)
221 #define LOAD_BIT (0x00100000)
222 #define TRANS_BIT (0x00200000)
226 CONST char * template;
230 /* This is to save a hash look-up in the common case. */
231 #define COND_ALWAYS 0xe0000000
233 static CONST struct asm_cond conds[] =
237 {"cs", 0x20000000}, {"hs", 0x20000000},
238 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
253 /* Warning: If the top bit of the set_bits is set, then the standard
254 instruction bitmask is ignored, and the new bitmask is taken from
258 CONST char * template; /* Basic flag string. */
259 unsigned long set_bits; /* Bits to set. */
262 static CONST struct asm_flg s_flag[] =
268 static CONST struct asm_flg ldr_flags[] =
272 {"bt", 0x00400000 | TRANS_BIT},
279 static CONST struct asm_flg str_flags[] =
283 {"bt", 0x00400000 | TRANS_BIT},
288 static CONST struct asm_flg byte_flag[] =
294 static CONST struct asm_flg cmp_flags[] =
301 static CONST struct asm_flg ldm_flags[] =
314 static CONST struct asm_flg stm_flags[] =
327 static CONST struct asm_flg lfm_flags[] =
334 static CONST struct asm_flg sfm_flags[] =
341 static CONST struct asm_flg round_flags[] =
349 /* The implementation of the FIX instruction is broken on some assemblers,
350 in that it accepts a precision specifier as well as a rounding specifier,
351 despite the fact that this is meaningless. To be more compatible, we
352 accept it as well, though of course it does not set any bits. */
353 static CONST struct asm_flg fix_flags[] =
370 static CONST struct asm_flg except_flag[] =
376 static CONST struct asm_flg cplong_flag[] =
384 CONST char * template;
389 /* The bit that distnguishes CPSR and SPSR. */
390 #define SPSR_BIT (1 << 22)
392 /* How many bits to shift the PSR_xxx bits up by. */
395 #define PSR_c (1 << 0)
396 #define PSR_x (1 << 1)
397 #define PSR_s (1 << 2)
398 #define PSR_f (1 << 3)
400 static CONST struct asm_psr psrs[] =
402 {"CPSR", true, PSR_c | PSR_f},
403 {"CPSR_all", true, PSR_c | PSR_f},
404 {"SPSR", false, PSR_c | PSR_f},
405 {"SPSR_all", false, PSR_c | PSR_f},
406 {"CPSR_flg", true, PSR_f},
407 {"CPSR_f", true, PSR_f},
408 {"SPSR_flg", false, PSR_f},
409 {"SPSR_f", false, PSR_f},
410 {"CPSR_c", true, PSR_c},
411 {"CPSR_ctl", true, PSR_c},
412 {"SPSR_c", false, PSR_c},
413 {"SPSR_ctl", false, PSR_c},
414 {"CPSR_x", true, PSR_x},
415 {"CPSR_s", true, PSR_s},
416 {"SPSR_x", false, PSR_x},
417 {"SPSR_s", false, PSR_s},
418 /* Combinations of flags. */
419 {"CPSR_fs", true, PSR_f | PSR_s},
420 {"CPSR_fx", true, PSR_f | PSR_x},
421 {"CPSR_fc", true, PSR_f | PSR_c},
422 {"CPSR_sf", true, PSR_s | PSR_f},
423 {"CPSR_sx", true, PSR_s | PSR_x},
424 {"CPSR_sc", true, PSR_s | PSR_c},
425 {"CPSR_xf", true, PSR_x | PSR_f},
426 {"CPSR_xs", true, PSR_x | PSR_s},
427 {"CPSR_xc", true, PSR_x | PSR_c},
428 {"CPSR_cf", true, PSR_c | PSR_f},
429 {"CPSR_cs", true, PSR_c | PSR_s},
430 {"CPSR_cx", true, PSR_c | PSR_x},
431 {"CPSR_fsx", true, PSR_f | PSR_s | PSR_x},
432 {"CPSR_fsc", true, PSR_f | PSR_s | PSR_c},
433 {"CPSR_fxs", true, PSR_f | PSR_x | PSR_s},
434 {"CPSR_fxc", true, PSR_f | PSR_x | PSR_c},
435 {"CPSR_fcs", true, PSR_f | PSR_c | PSR_s},
436 {"CPSR_fcx", true, PSR_f | PSR_c | PSR_x},
437 {"CPSR_sfx", true, PSR_s | PSR_f | PSR_x},
438 {"CPSR_sfc", true, PSR_s | PSR_f | PSR_c},
439 {"CPSR_sxf", true, PSR_s | PSR_x | PSR_f},
440 {"CPSR_sxc", true, PSR_s | PSR_x | PSR_c},
441 {"CPSR_scf", true, PSR_s | PSR_c | PSR_f},
442 {"CPSR_scx", true, PSR_s | PSR_c | PSR_x},
443 {"CPSR_xfs", true, PSR_x | PSR_f | PSR_s},
444 {"CPSR_xfc", true, PSR_x | PSR_f | PSR_c},
445 {"CPSR_xsf", true, PSR_x | PSR_s | PSR_f},
446 {"CPSR_xsc", true, PSR_x | PSR_s | PSR_c},
447 {"CPSR_xcf", true, PSR_x | PSR_c | PSR_f},
448 {"CPSR_xcs", true, PSR_x | PSR_c | PSR_s},
449 {"CPSR_cfs", true, PSR_c | PSR_f | PSR_s},
450 {"CPSR_cfx", true, PSR_c | PSR_f | PSR_x},
451 {"CPSR_csf", true, PSR_c | PSR_s | PSR_f},
452 {"CPSR_csx", true, PSR_c | PSR_s | PSR_x},
453 {"CPSR_cxf", true, PSR_c | PSR_x | PSR_f},
454 {"CPSR_cxs", true, PSR_c | PSR_x | PSR_s},
455 {"CPSR_fsxc", true, PSR_f | PSR_s | PSR_x | PSR_c},
456 {"CPSR_fscx", true, PSR_f | PSR_s | PSR_c | PSR_x},
457 {"CPSR_fxsc", true, PSR_f | PSR_x | PSR_s | PSR_c},
458 {"CPSR_fxcs", true, PSR_f | PSR_x | PSR_c | PSR_s},
459 {"CPSR_fcsx", true, PSR_f | PSR_c | PSR_s | PSR_x},
460 {"CPSR_fcxs", true, PSR_f | PSR_c | PSR_x | PSR_s},
461 {"CPSR_sfxc", true, PSR_s | PSR_f | PSR_x | PSR_c},
462 {"CPSR_sfcx", true, PSR_s | PSR_f | PSR_c | PSR_x},
463 {"CPSR_sxfc", true, PSR_s | PSR_x | PSR_f | PSR_c},
464 {"CPSR_sxcf", true, PSR_s | PSR_x | PSR_c | PSR_f},
465 {"CPSR_scfx", true, PSR_s | PSR_c | PSR_f | PSR_x},
466 {"CPSR_scxf", true, PSR_s | PSR_c | PSR_x | PSR_f},
467 {"CPSR_xfsc", true, PSR_x | PSR_f | PSR_s | PSR_c},
468 {"CPSR_xfcs", true, PSR_x | PSR_f | PSR_c | PSR_s},
469 {"CPSR_xsfc", true, PSR_x | PSR_s | PSR_f | PSR_c},
470 {"CPSR_xscf", true, PSR_x | PSR_s | PSR_c | PSR_f},
471 {"CPSR_xcfs", true, PSR_x | PSR_c | PSR_f | PSR_s},
472 {"CPSR_xcsf", true, PSR_x | PSR_c | PSR_s | PSR_f},
473 {"CPSR_cfsx", true, PSR_c | PSR_f | PSR_s | PSR_x},
474 {"CPSR_cfxs", true, PSR_c | PSR_f | PSR_x | PSR_s},
475 {"CPSR_csfx", true, PSR_c | PSR_s | PSR_f | PSR_x},
476 {"CPSR_csxf", true, PSR_c | PSR_s | PSR_x | PSR_f},
477 {"CPSR_cxfs", true, PSR_c | PSR_x | PSR_f | PSR_s},
478 {"CPSR_cxsf", true, PSR_c | PSR_x | PSR_s | PSR_f},
479 {"SPSR_fs", false, PSR_f | PSR_s},
480 {"SPSR_fx", false, PSR_f | PSR_x},
481 {"SPSR_fc", false, PSR_f | PSR_c},
482 {"SPSR_sf", false, PSR_s | PSR_f},
483 {"SPSR_sx", false, PSR_s | PSR_x},
484 {"SPSR_sc", false, PSR_s | PSR_c},
485 {"SPSR_xf", false, PSR_x | PSR_f},
486 {"SPSR_xs", false, PSR_x | PSR_s},
487 {"SPSR_xc", false, PSR_x | PSR_c},
488 {"SPSR_cf", false, PSR_c | PSR_f},
489 {"SPSR_cs", false, PSR_c | PSR_s},
490 {"SPSR_cx", false, PSR_c | PSR_x},
491 {"SPSR_fsx", false, PSR_f | PSR_s | PSR_x},
492 {"SPSR_fsc", false, PSR_f | PSR_s | PSR_c},
493 {"SPSR_fxs", false, PSR_f | PSR_x | PSR_s},
494 {"SPSR_fxc", false, PSR_f | PSR_x | PSR_c},
495 {"SPSR_fcs", false, PSR_f | PSR_c | PSR_s},
496 {"SPSR_fcx", false, PSR_f | PSR_c | PSR_x},
497 {"SPSR_sfx", false, PSR_s | PSR_f | PSR_x},
498 {"SPSR_sfc", false, PSR_s | PSR_f | PSR_c},
499 {"SPSR_sxf", false, PSR_s | PSR_x | PSR_f},
500 {"SPSR_sxc", false, PSR_s | PSR_x | PSR_c},
501 {"SPSR_scf", false, PSR_s | PSR_c | PSR_f},
502 {"SPSR_scx", false, PSR_s | PSR_c | PSR_x},
503 {"SPSR_xfs", false, PSR_x | PSR_f | PSR_s},
504 {"SPSR_xfc", false, PSR_x | PSR_f | PSR_c},
505 {"SPSR_xsf", false, PSR_x | PSR_s | PSR_f},
506 {"SPSR_xsc", false, PSR_x | PSR_s | PSR_c},
507 {"SPSR_xcf", false, PSR_x | PSR_c | PSR_f},
508 {"SPSR_xcs", false, PSR_x | PSR_c | PSR_s},
509 {"SPSR_cfs", false, PSR_c | PSR_f | PSR_s},
510 {"SPSR_cfx", false, PSR_c | PSR_f | PSR_x},
511 {"SPSR_csf", false, PSR_c | PSR_s | PSR_f},
512 {"SPSR_csx", false, PSR_c | PSR_s | PSR_x},
513 {"SPSR_cxf", false, PSR_c | PSR_x | PSR_f},
514 {"SPSR_cxs", false, PSR_c | PSR_x | PSR_s},
515 {"SPSR_fsxc", false, PSR_f | PSR_s | PSR_x | PSR_c},
516 {"SPSR_fscx", false, PSR_f | PSR_s | PSR_c | PSR_x},
517 {"SPSR_fxsc", false, PSR_f | PSR_x | PSR_s | PSR_c},
518 {"SPSR_fxcs", false, PSR_f | PSR_x | PSR_c | PSR_s},
519 {"SPSR_fcsx", false, PSR_f | PSR_c | PSR_s | PSR_x},
520 {"SPSR_fcxs", false, PSR_f | PSR_c | PSR_x | PSR_s},
521 {"SPSR_sfxc", false, PSR_s | PSR_f | PSR_x | PSR_c},
522 {"SPSR_sfcx", false, PSR_s | PSR_f | PSR_c | PSR_x},
523 {"SPSR_sxfc", false, PSR_s | PSR_x | PSR_f | PSR_c},
524 {"SPSR_sxcf", false, PSR_s | PSR_x | PSR_c | PSR_f},
525 {"SPSR_scfx", false, PSR_s | PSR_c | PSR_f | PSR_x},
526 {"SPSR_scxf", false, PSR_s | PSR_c | PSR_x | PSR_f},
527 {"SPSR_xfsc", false, PSR_x | PSR_f | PSR_s | PSR_c},
528 {"SPSR_xfcs", false, PSR_x | PSR_f | PSR_c | PSR_s},
529 {"SPSR_xsfc", false, PSR_x | PSR_s | PSR_f | PSR_c},
530 {"SPSR_xscf", false, PSR_x | PSR_s | PSR_c | PSR_f},
531 {"SPSR_xcfs", false, PSR_x | PSR_c | PSR_f | PSR_s},
532 {"SPSR_xcsf", false, PSR_x | PSR_c | PSR_s | PSR_f},
533 {"SPSR_cfsx", false, PSR_c | PSR_f | PSR_s | PSR_x},
534 {"SPSR_cfxs", false, PSR_c | PSR_f | PSR_x | PSR_s},
535 {"SPSR_csfx", false, PSR_c | PSR_s | PSR_f | PSR_x},
536 {"SPSR_csxf", false, PSR_c | PSR_s | PSR_x | PSR_f},
537 {"SPSR_cxfs", false, PSR_c | PSR_x | PSR_f | PSR_s},
538 {"SPSR_cxsf", false, PSR_c | PSR_x | PSR_s | PSR_f},
539 /* For backwards compatability with older toolchain we also
540 support lower case versions of some of these flags. */
541 {"cpsr", true, PSR_c | PSR_f},
542 {"cpsr_all", true, PSR_c | PSR_f},
543 {"spsr", false, PSR_c | PSR_f},
544 {"spsr_all", false, PSR_c | PSR_f},
545 {"cpsr_flg", true, PSR_f},
546 {"cpsr_f", true, PSR_f},
547 {"spsr_flg", false, PSR_f},
548 {"spsr_f", false, PSR_f},
549 {"cpsr_c", true, PSR_c},
550 {"cpsr_ctl", true, PSR_c},
551 {"spsr_c", false, PSR_c},
552 {"spsr_ctl", false, PSR_c}
555 /* Functions called by parser. */
556 /* ARM instructions. */
557 static void do_arit PARAMS ((char *, unsigned long));
558 static void do_cmp PARAMS ((char *, unsigned long));
559 static void do_mov PARAMS ((char *, unsigned long));
560 static void do_ldst PARAMS ((char *, unsigned long));
561 static void do_ldmstm PARAMS ((char *, unsigned long));
562 static void do_branch PARAMS ((char *, unsigned long));
563 static void do_swi PARAMS ((char *, unsigned long));
564 /* Pseudo Op codes. */
565 static void do_adr PARAMS ((char *, unsigned long));
566 static void do_adrl PARAMS ((char *, unsigned long));
567 static void do_nop PARAMS ((char *, unsigned long));
569 static void do_mul PARAMS ((char *, unsigned long));
570 static void do_mla PARAMS ((char *, unsigned long));
572 static void do_swap PARAMS ((char *, unsigned long));
574 static void do_msr PARAMS ((char *, unsigned long));
575 static void do_mrs PARAMS ((char *, unsigned long));
577 static void do_mull PARAMS ((char *, unsigned long));
579 static void do_bx PARAMS ((char *, unsigned long));
581 /* Coprocessor Instructions. */
582 static void do_cdp PARAMS ((char *, unsigned long));
583 static void do_lstc PARAMS ((char *, unsigned long));
584 static void do_co_reg PARAMS ((char *, unsigned long));
585 static void do_fp_ctrl PARAMS ((char *, unsigned long));
586 static void do_fp_ldst PARAMS ((char *, unsigned long));
587 static void do_fp_ldmstm PARAMS ((char *, unsigned long));
588 static void do_fp_dyadic PARAMS ((char *, unsigned long));
589 static void do_fp_monadic PARAMS ((char *, unsigned long));
590 static void do_fp_cmp PARAMS ((char *, unsigned long));
591 static void do_fp_from_reg PARAMS ((char *, unsigned long));
592 static void do_fp_to_reg PARAMS ((char *, unsigned long));
594 static void fix_new_arm PARAMS ((fragS *, int, short, expressionS *, int, int));
595 static int arm_reg_parse PARAMS ((char **));
596 static CONST struct asm_psr * arm_psr_parse PARAMS ((char **));
597 static void symbol_locate PARAMS ((symbolS *, CONST char *, segT, valueT, fragS *));
598 static int add_to_lit_pool PARAMS ((void));
599 static unsigned validate_immediate PARAMS ((unsigned));
600 static unsigned validate_immediate_twopart PARAMS ((unsigned int, unsigned int *));
601 static int validate_offset_imm PARAMS ((unsigned int, int));
602 static void opcode_select PARAMS ((int));
603 static void end_of_line PARAMS ((char *));
604 static int reg_required_here PARAMS ((char **, int));
605 static int psr_required_here PARAMS ((char **));
606 static int co_proc_number PARAMS ((char **));
607 static int cp_opc_expr PARAMS ((char **, int, int));
608 static int cp_reg_required_here PARAMS ((char **, int));
609 static int fp_reg_required_here PARAMS ((char **, int));
610 static int cp_address_offset PARAMS ((char **));
611 static int cp_address_required_here PARAMS ((char **));
612 static int my_get_float_expression PARAMS ((char **));
613 static int skip_past_comma PARAMS ((char **));
614 static int walk_no_bignums PARAMS ((symbolS *));
615 static int negate_data_op PARAMS ((unsigned long *, unsigned long));
616 static int data_op2 PARAMS ((char **));
617 static int fp_op2 PARAMS ((char **));
618 static long reg_list PARAMS ((char **));
619 static void thumb_load_store PARAMS ((char *, int, int));
620 static int decode_shift PARAMS ((char **, int));
621 static int ldst_extend PARAMS ((char **, int));
622 static void thumb_add_sub PARAMS ((char *, int));
623 static void insert_reg PARAMS ((int));
624 static void thumb_shift PARAMS ((char *, int));
625 static void thumb_mov_compare PARAMS ((char *, int));
626 static void set_constant_flonums PARAMS ((void));
627 static valueT md_chars_to_number PARAMS ((char *, int));
628 static void insert_reg_alias PARAMS ((char *, int));
629 static void output_inst PARAMS ((void));
631 static bfd_reloc_code_real_type arm_parse_reloc PARAMS ((void));
634 /* ARM instructions take 4bytes in the object file, Thumb instructions
638 /* LONGEST_INST is the longest basic instruction name without conditions or
639 flags. ARM7M has 4 of length 5. */
641 #define LONGEST_INST 5
645 /* Basic string to match. */
646 CONST char * template;
648 /* Basic instruction code. */
651 /* Compulsory suffix that must follow conds. If "", then the
652 instruction is not conditional and must have no suffix. */
653 CONST char * comp_suffix;
655 /* Bits to toggle if flag 'n' set. */
656 CONST struct asm_flg * flags;
658 /* Which CPU variants this exists for. */
659 unsigned long variants;
661 /* Function to call to parse args. */
662 void (* parms) PARAMS ((char *, unsigned long));
665 static CONST struct asm_opcode insns[] =
667 /* ARM Instructions. */
668 {"and", 0x00000000, NULL, s_flag, ARM_ANY, do_arit},
669 {"eor", 0x00200000, NULL, s_flag, ARM_ANY, do_arit},
670 {"sub", 0x00400000, NULL, s_flag, ARM_ANY, do_arit},
671 {"rsb", 0x00600000, NULL, s_flag, ARM_ANY, do_arit},
672 {"add", 0x00800000, NULL, s_flag, ARM_ANY, do_arit},
673 {"adc", 0x00a00000, NULL, s_flag, ARM_ANY, do_arit},
674 {"sbc", 0x00c00000, NULL, s_flag, ARM_ANY, do_arit},
675 {"rsc", 0x00e00000, NULL, s_flag, ARM_ANY, do_arit},
676 {"orr", 0x01800000, NULL, s_flag, ARM_ANY, do_arit},
677 {"bic", 0x01c00000, NULL, s_flag, ARM_ANY, do_arit},
678 {"tst", 0x01000000, NULL, cmp_flags, ARM_ANY, do_cmp},
679 {"teq", 0x01200000, NULL, cmp_flags, ARM_ANY, do_cmp},
680 {"cmp", 0x01400000, NULL, cmp_flags, ARM_ANY, do_cmp},
681 {"cmn", 0x01600000, NULL, cmp_flags, ARM_ANY, do_cmp},
682 {"mov", 0x01a00000, NULL, s_flag, ARM_ANY, do_mov},
683 {"mvn", 0x01e00000, NULL, s_flag, ARM_ANY, do_mov},
684 {"str", 0x04000000, NULL, str_flags, ARM_ANY, do_ldst},
685 {"ldr", 0x04100000, NULL, ldr_flags, ARM_ANY, do_ldst},
686 {"stm", 0x08000000, NULL, stm_flags, ARM_ANY, do_ldmstm},
687 {"ldm", 0x08100000, NULL, ldm_flags, ARM_ANY, do_ldmstm},
688 {"swi", 0x0f000000, NULL, NULL, ARM_ANY, do_swi},
690 {"bl", 0x0b000000, NULL, NULL, ARM_ANY, do_branch},
691 {"b", 0x0a000000, NULL, NULL, ARM_ANY, do_branch},
693 {"bl", 0x0bfffffe, NULL, NULL, ARM_ANY, do_branch},
694 {"b", 0x0afffffe, NULL, NULL, ARM_ANY, do_branch},
698 {"adr", 0x028f0000, NULL, NULL, ARM_ANY, do_adr},
699 {"adrl", 0x028f0000, NULL, NULL, ARM_ANY, do_adrl},
700 {"nop", 0x01a00000, NULL, NULL, ARM_ANY, do_nop},
702 /* ARM 2 multiplies. */
703 {"mul", 0x00000090, NULL, s_flag, ARM_2UP, do_mul},
704 {"mla", 0x00200090, NULL, s_flag, ARM_2UP, do_mla},
706 /* ARM 3 - swp instructions. */
707 {"swp", 0x01000090, NULL, byte_flag, ARM_3UP, do_swap},
709 /* ARM 6 Coprocessor instructions. */
710 {"mrs", 0x010f0000, NULL, NULL, ARM_6UP, do_mrs},
711 {"msr", 0x0120f000, NULL, NULL, ARM_6UP, do_msr},
712 /* ScottB: our code uses 0x0128f000 for msr.
713 NickC: but this is wrong because the bits 16 through 19 are
714 handled by the PSR_xxx defines above. */
716 /* ARM 7M long multiplies - need signed/unsigned flags! */
717 {"smull", 0x00c00090, NULL, s_flag, ARM_LONGMUL, do_mull},
718 {"umull", 0x00800090, NULL, s_flag, ARM_LONGMUL, do_mull},
719 {"smlal", 0x00e00090, NULL, s_flag, ARM_LONGMUL, do_mull},
720 {"umlal", 0x00a00090, NULL, s_flag, ARM_LONGMUL, do_mull},
722 /* ARM THUMB interworking. */
723 {"bx", 0x012fff10, NULL, NULL, ARM_THUMB, do_bx},
725 /* Floating point instructions. */
726 {"wfs", 0x0e200110, NULL, NULL, FPU_ALL, do_fp_ctrl},
727 {"rfs", 0x0e300110, NULL, NULL, FPU_ALL, do_fp_ctrl},
728 {"wfc", 0x0e400110, NULL, NULL, FPU_ALL, do_fp_ctrl},
729 {"rfc", 0x0e500110, NULL, NULL, FPU_ALL, do_fp_ctrl},
730 {"ldf", 0x0c100100, "sdep", NULL, FPU_ALL, do_fp_ldst},
731 {"stf", 0x0c000100, "sdep", NULL, FPU_ALL, do_fp_ldst},
732 {"lfm", 0x0c100200, NULL, lfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
733 {"sfm", 0x0c000200, NULL, sfm_flags, FPU_MEMMULTI, do_fp_ldmstm},
734 {"mvf", 0x0e008100, "sde", round_flags, FPU_ALL, do_fp_monadic},
735 {"mnf", 0x0e108100, "sde", round_flags, FPU_ALL, do_fp_monadic},
736 {"abs", 0x0e208100, "sde", round_flags, FPU_ALL, do_fp_monadic},
737 {"rnd", 0x0e308100, "sde", round_flags, FPU_ALL, do_fp_monadic},
738 {"sqt", 0x0e408100, "sde", round_flags, FPU_ALL, do_fp_monadic},
739 {"log", 0x0e508100, "sde", round_flags, FPU_ALL, do_fp_monadic},
740 {"lgn", 0x0e608100, "sde", round_flags, FPU_ALL, do_fp_monadic},
741 {"exp", 0x0e708100, "sde", round_flags, FPU_ALL, do_fp_monadic},
742 {"sin", 0x0e808100, "sde", round_flags, FPU_ALL, do_fp_monadic},
743 {"cos", 0x0e908100, "sde", round_flags, FPU_ALL, do_fp_monadic},
744 {"tan", 0x0ea08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
745 {"asn", 0x0eb08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
746 {"acs", 0x0ec08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
747 {"atn", 0x0ed08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
748 {"urd", 0x0ee08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
749 {"nrm", 0x0ef08100, "sde", round_flags, FPU_ALL, do_fp_monadic},
750 {"adf", 0x0e000100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
751 {"suf", 0x0e200100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
752 {"rsf", 0x0e300100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
753 {"muf", 0x0e100100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
754 {"dvf", 0x0e400100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
755 {"rdf", 0x0e500100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
756 {"pow", 0x0e600100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
757 {"rpw", 0x0e700100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
758 {"rmf", 0x0e800100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
759 {"fml", 0x0e900100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
760 {"fdv", 0x0ea00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
761 {"frd", 0x0eb00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
762 {"pol", 0x0ec00100, "sde", round_flags, FPU_ALL, do_fp_dyadic},
763 {"cmf", 0x0e90f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
764 {"cnf", 0x0eb0f110, NULL, except_flag, FPU_ALL, do_fp_cmp},
765 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
766 be an optional suffix, but part of the instruction. To be compatible,
768 {"cmfe", 0x0ed0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
769 {"cnfe", 0x0ef0f110, NULL, NULL, FPU_ALL, do_fp_cmp},
770 {"flt", 0x0e000110, "sde", round_flags, FPU_ALL, do_fp_from_reg},
771 {"fix", 0x0e100110, NULL, fix_flags, FPU_ALL, do_fp_to_reg},
773 /* Generic copressor instructions. */
774 {"cdp", 0x0e000000, NULL, NULL, ARM_2UP, do_cdp},
775 {"ldc", 0x0c100000, NULL, cplong_flag, ARM_2UP, do_lstc},
776 {"stc", 0x0c000000, NULL, cplong_flag, ARM_2UP, do_lstc},
777 {"mcr", 0x0e000010, NULL, NULL, ARM_2UP, do_co_reg},
778 {"mrc", 0x0e100010, NULL, NULL, ARM_2UP, do_co_reg},
781 /* Defines for various bits that we will want to toggle. */
782 #define INST_IMMEDIATE 0x02000000
783 #define OFFSET_REG 0x02000000
784 #define HWOFFSET_IMM 0x00400000
785 #define SHIFT_BY_REG 0x00000010
786 #define PRE_INDEX 0x01000000
787 #define INDEX_UP 0x00800000
788 #define WRITE_BACK 0x00200000
789 #define LDM_TYPE_2_OR_3 0x00400000
791 #define LITERAL_MASK 0xf000f000
792 #define COND_MASK 0xf0000000
793 #define OPCODE_MASK 0xfe1fffff
794 #define DATA_OP_SHIFT 21
796 /* Codes to distinguish the arithmetic instructions. */
807 #define OPCODE_CMP 10
808 #define OPCODE_CMN 11
809 #define OPCODE_ORR 12
810 #define OPCODE_MOV 13
811 #define OPCODE_BIC 14
812 #define OPCODE_MVN 15
814 static void do_t_nop PARAMS ((char *));
815 static void do_t_arit PARAMS ((char *));
816 static void do_t_add PARAMS ((char *));
817 static void do_t_asr PARAMS ((char *));
818 static void do_t_branch9 PARAMS ((char *));
819 static void do_t_branch12 PARAMS ((char *));
820 static void do_t_branch23 PARAMS ((char *));
821 static void do_t_bx PARAMS ((char *));
822 static void do_t_compare PARAMS ((char *));
823 static void do_t_ldmstm PARAMS ((char *));
824 static void do_t_ldr PARAMS ((char *));
825 static void do_t_ldrb PARAMS ((char *));
826 static void do_t_ldrh PARAMS ((char *));
827 static void do_t_lds PARAMS ((char *));
828 static void do_t_lsl PARAMS ((char *));
829 static void do_t_lsr PARAMS ((char *));
830 static void do_t_mov PARAMS ((char *));
831 static void do_t_push_pop PARAMS ((char *));
832 static void do_t_str PARAMS ((char *));
833 static void do_t_strb PARAMS ((char *));
834 static void do_t_strh PARAMS ((char *));
835 static void do_t_sub PARAMS ((char *));
836 static void do_t_swi PARAMS ((char *));
837 static void do_t_adr PARAMS ((char *));
839 #define T_OPCODE_MUL 0x4340
840 #define T_OPCODE_TST 0x4200
841 #define T_OPCODE_CMN 0x42c0
842 #define T_OPCODE_NEG 0x4240
843 #define T_OPCODE_MVN 0x43c0
845 #define T_OPCODE_ADD_R3 0x1800
846 #define T_OPCODE_SUB_R3 0x1a00
847 #define T_OPCODE_ADD_HI 0x4400
848 #define T_OPCODE_ADD_ST 0xb000
849 #define T_OPCODE_SUB_ST 0xb080
850 #define T_OPCODE_ADD_SP 0xa800
851 #define T_OPCODE_ADD_PC 0xa000
852 #define T_OPCODE_ADD_I8 0x3000
853 #define T_OPCODE_SUB_I8 0x3800
854 #define T_OPCODE_ADD_I3 0x1c00
855 #define T_OPCODE_SUB_I3 0x1e00
857 #define T_OPCODE_ASR_R 0x4100
858 #define T_OPCODE_LSL_R 0x4080
859 #define T_OPCODE_LSR_R 0x40c0
860 #define T_OPCODE_ASR_I 0x1000
861 #define T_OPCODE_LSL_I 0x0000
862 #define T_OPCODE_LSR_I 0x0800
864 #define T_OPCODE_MOV_I8 0x2000
865 #define T_OPCODE_CMP_I8 0x2800
866 #define T_OPCODE_CMP_LR 0x4280
867 #define T_OPCODE_MOV_HR 0x4600
868 #define T_OPCODE_CMP_HR 0x4500
870 #define T_OPCODE_LDR_PC 0x4800
871 #define T_OPCODE_LDR_SP 0x9800
872 #define T_OPCODE_STR_SP 0x9000
873 #define T_OPCODE_LDR_IW 0x6800
874 #define T_OPCODE_STR_IW 0x6000
875 #define T_OPCODE_LDR_IH 0x8800
876 #define T_OPCODE_STR_IH 0x8000
877 #define T_OPCODE_LDR_IB 0x7800
878 #define T_OPCODE_STR_IB 0x7000
879 #define T_OPCODE_LDR_RW 0x5800
880 #define T_OPCODE_STR_RW 0x5000
881 #define T_OPCODE_LDR_RH 0x5a00
882 #define T_OPCODE_STR_RH 0x5200
883 #define T_OPCODE_LDR_RB 0x5c00
884 #define T_OPCODE_STR_RB 0x5400
886 #define T_OPCODE_PUSH 0xb400
887 #define T_OPCODE_POP 0xbc00
889 #define T_OPCODE_BRANCH 0xe7fe
891 static int thumb_reg PARAMS ((char ** str, int hi_lo));
893 #define THUMB_SIZE 2 /* Size of thumb instruction. */
894 #define THUMB_REG_LO 0x1
895 #define THUMB_REG_HI 0x2
896 #define THUMB_REG_ANY 0x3
898 #define THUMB_H1 0x0080
899 #define THUMB_H2 0x0040
906 #define THUMB_COMPARE 1
909 #define THUMB_STORE 1
911 #define THUMB_PP_PC_LR 0x0100
913 /* These three are used for immediate shifts, do not alter. */
915 #define THUMB_HALFWORD 1
920 /* Basic string to match. */
921 CONST char * template;
923 /* Basic instruction code. */
928 /* Which CPU variants this exists for. */
929 unsigned long variants;
931 /* Function to call to parse args. */
932 void (* parms) PARAMS ((char *));
935 static CONST struct thumb_opcode tinsns[] =
937 {"adc", 0x4140, 2, ARM_THUMB, do_t_arit},
938 {"add", 0x0000, 2, ARM_THUMB, do_t_add},
939 {"and", 0x4000, 2, ARM_THUMB, do_t_arit},
940 {"asr", 0x0000, 2, ARM_THUMB, do_t_asr},
941 {"b", T_OPCODE_BRANCH, 2, ARM_THUMB, do_t_branch12},
942 {"beq", 0xd0fe, 2, ARM_THUMB, do_t_branch9},
943 {"bne", 0xd1fe, 2, ARM_THUMB, do_t_branch9},
944 {"bcs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
945 {"bhs", 0xd2fe, 2, ARM_THUMB, do_t_branch9},
946 {"bcc", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
947 {"bul", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
948 {"blo", 0xd3fe, 2, ARM_THUMB, do_t_branch9},
949 {"bmi", 0xd4fe, 2, ARM_THUMB, do_t_branch9},
950 {"bpl", 0xd5fe, 2, ARM_THUMB, do_t_branch9},
951 {"bvs", 0xd6fe, 2, ARM_THUMB, do_t_branch9},
952 {"bvc", 0xd7fe, 2, ARM_THUMB, do_t_branch9},
953 {"bhi", 0xd8fe, 2, ARM_THUMB, do_t_branch9},
954 {"bls", 0xd9fe, 2, ARM_THUMB, do_t_branch9},
955 {"bge", 0xdafe, 2, ARM_THUMB, do_t_branch9},
956 {"blt", 0xdbfe, 2, ARM_THUMB, do_t_branch9},
957 {"bgt", 0xdcfe, 2, ARM_THUMB, do_t_branch9},
958 {"ble", 0xddfe, 2, ARM_THUMB, do_t_branch9},
959 {"bal", 0xdefe, 2, ARM_THUMB, do_t_branch9},
960 {"bic", 0x4380, 2, ARM_THUMB, do_t_arit},
961 {"bl", 0xf7fffffe, 4, ARM_THUMB, do_t_branch23},
962 {"bx", 0x4700, 2, ARM_THUMB, do_t_bx},
963 {"cmn", T_OPCODE_CMN, 2, ARM_THUMB, do_t_arit},
964 {"cmp", 0x0000, 2, ARM_THUMB, do_t_compare},
965 {"eor", 0x4040, 2, ARM_THUMB, do_t_arit},
966 {"ldmia", 0xc800, 2, ARM_THUMB, do_t_ldmstm},
967 {"ldr", 0x0000, 2, ARM_THUMB, do_t_ldr},
968 {"ldrb", 0x0000, 2, ARM_THUMB, do_t_ldrb},
969 {"ldrh", 0x0000, 2, ARM_THUMB, do_t_ldrh},
970 {"ldrsb", 0x5600, 2, ARM_THUMB, do_t_lds},
971 {"ldrsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
972 {"ldsb", 0x5600, 2, ARM_THUMB, do_t_lds},
973 {"ldsh", 0x5e00, 2, ARM_THUMB, do_t_lds},
974 {"lsl", 0x0000, 2, ARM_THUMB, do_t_lsl},
975 {"lsr", 0x0000, 2, ARM_THUMB, do_t_lsr},
976 {"mov", 0x0000, 2, ARM_THUMB, do_t_mov},
977 {"mul", T_OPCODE_MUL, 2, ARM_THUMB, do_t_arit},
978 {"mvn", T_OPCODE_MVN, 2, ARM_THUMB, do_t_arit},
979 {"neg", T_OPCODE_NEG, 2, ARM_THUMB, do_t_arit},
980 {"orr", 0x4300, 2, ARM_THUMB, do_t_arit},
981 {"pop", 0xbc00, 2, ARM_THUMB, do_t_push_pop},
982 {"push", 0xb400, 2, ARM_THUMB, do_t_push_pop},
983 {"ror", 0x41c0, 2, ARM_THUMB, do_t_arit},
984 {"sbc", 0x4180, 2, ARM_THUMB, do_t_arit},
985 {"stmia", 0xc000, 2, ARM_THUMB, do_t_ldmstm},
986 {"str", 0x0000, 2, ARM_THUMB, do_t_str},
987 {"strb", 0x0000, 2, ARM_THUMB, do_t_strb},
988 {"strh", 0x0000, 2, ARM_THUMB, do_t_strh},
989 {"swi", 0xdf00, 2, ARM_THUMB, do_t_swi},
990 {"sub", 0x0000, 2, ARM_THUMB, do_t_sub},
991 {"tst", T_OPCODE_TST, 2, ARM_THUMB, do_t_arit},
993 {"adr", 0x0000, 2, ARM_THUMB, do_t_adr},
994 {"nop", 0x46C0, 2, ARM_THUMB, do_t_nop}, /* mov r8,r8 */
1003 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1004 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1005 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1011 /* These are the standard names. Users can add aliases with .req. */
1012 static CONST struct reg_entry reg_table[] =
1014 /* Processor Register Numbers. */
1015 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1016 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1017 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1018 {"r12", 12}, {"r13", REG_SP},{"r14", REG_LR},{"r15", REG_PC},
1019 /* APCS conventions. */
1020 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1021 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1022 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1023 {"fp", 11}, {"ip", 12}, {"sp", REG_SP},{"lr", REG_LR},{"pc", REG_PC},
1024 /* ATPCS additions to APCS conventions. */
1025 {"wr", 7}, {"v8", 11},
1027 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1028 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1029 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1030 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1031 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1032 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1033 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1034 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1035 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1036 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1037 /* ATPCS additions to float register names. */
1038 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1039 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1040 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1041 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1042 /* FIXME: At some point we need to add VFP register names. */
1043 /* Array terminator. */
1047 #define BAD_ARGS _("Bad arguments to instruction")
1048 #define BAD_PC _("r15 not allowed here")
1049 #define BAD_FLAGS _("Instruction should not have flags")
1050 #define BAD_COND _("Instruction is not conditional")
1052 static struct hash_control * arm_ops_hsh = NULL;
1053 static struct hash_control * arm_tops_hsh = NULL;
1054 static struct hash_control * arm_cond_hsh = NULL;
1055 static struct hash_control * arm_shift_hsh = NULL;
1056 static struct hash_control * arm_reg_hsh = NULL;
1057 static struct hash_control * arm_psr_hsh = NULL;
1059 /* This table describes all the machine specific pseudo-ops the assembler
1060 has to support. The fields are:
1061 pseudo-op name without dot
1062 function to call to execute this pseudo-op
1063 Integer arg to pass to the function. */
1065 static void s_req PARAMS ((int));
1066 static void s_align PARAMS ((int));
1067 static void s_bss PARAMS ((int));
1068 static void s_even PARAMS ((int));
1069 static void s_ltorg PARAMS ((int));
1070 static void s_arm PARAMS ((int));
1071 static void s_thumb PARAMS ((int));
1072 static void s_code PARAMS ((int));
1073 static void s_force_thumb PARAMS ((int));
1074 static void s_thumb_func PARAMS ((int));
1075 static void s_thumb_set PARAMS ((int));
1076 static void arm_s_text PARAMS ((int));
1077 static void arm_s_data PARAMS ((int));
1079 static void arm_s_section PARAMS ((int));
1080 static void s_arm_elf_cons PARAMS ((int));
1083 static int my_get_expression PARAMS ((expressionS *, char **));
1085 CONST pseudo_typeS md_pseudo_table[] =
1087 /* Never called becasue '.req' does not start line. */
1088 { "req", s_req, 0 },
1089 { "bss", s_bss, 0 },
1090 { "align", s_align, 0 },
1091 { "arm", s_arm, 0 },
1092 { "thumb", s_thumb, 0 },
1093 { "code", s_code, 0 },
1094 { "force_thumb", s_force_thumb, 0 },
1095 { "thumb_func", s_thumb_func, 0 },
1096 { "thumb_set", s_thumb_set, 0 },
1097 { "even", s_even, 0 },
1098 { "ltorg", s_ltorg, 0 },
1099 { "pool", s_ltorg, 0 },
1100 /* Allow for the effect of section changes. */
1101 { "text", arm_s_text, 0 },
1102 { "data", arm_s_data, 0 },
1104 { "section", arm_s_section, 0 },
1105 { "section.s", arm_s_section, 0 },
1106 { "sect", arm_s_section, 0 },
1107 { "sect.s", arm_s_section, 0 },
1108 { "word", s_arm_elf_cons, 4 },
1109 { "long", s_arm_elf_cons, 4 },
1113 { "extend", float_cons, 'x' },
1114 { "ldouble", float_cons, 'x' },
1115 { "packed", float_cons, 'p' },
1119 /* Stuff needed to resolve the label ambiguity
1129 symbolS * last_label_seen;
1130 static int label_is_thumb_function_name = false;
1132 /* Literal stuff. */
1134 #define MAX_LITERAL_POOL_SIZE 1024
1136 typedef struct literalS
1138 struct expressionS exp;
1139 struct arm_it * inst;
1142 literalT literals[MAX_LITERAL_POOL_SIZE];
1144 /* Next free entry in the pool. */
1145 int next_literal_pool_place = 0;
1147 /* Next literal pool number. */
1148 int lit_pool_num = 1;
1150 symbolS * current_poolP = NULL;
1157 if (current_poolP == NULL)
1158 current_poolP = symbol_create (FAKE_LABEL_NAME, undefined_section,
1159 (valueT) 0, &zero_address_frag);
1161 /* Check if this literal value is already in the pool: */
1162 while (lit_count < next_literal_pool_place)
1164 if (literals[lit_count].exp.X_op == inst.reloc.exp.X_op
1165 && inst.reloc.exp.X_op == O_constant
1166 && (literals[lit_count].exp.X_add_number
1167 == inst.reloc.exp.X_add_number)
1168 && literals[lit_count].exp.X_unsigned == inst.reloc.exp.X_unsigned)
1173 if (lit_count == next_literal_pool_place) /* New entry. */
1175 if (next_literal_pool_place > MAX_LITERAL_POOL_SIZE)
1177 inst.error = _("Literal Pool Overflow");
1181 literals[next_literal_pool_place].exp = inst.reloc.exp;
1182 lit_count = next_literal_pool_place++;
1185 inst.reloc.exp.X_op = O_symbol;
1186 inst.reloc.exp.X_add_number = (lit_count) * 4 - 8;
1187 inst.reloc.exp.X_add_symbol = current_poolP;
1192 /* Can't use symbol_new here, so have to create a symbol and then at
1193 a later date assign it a value. Thats what these functions do. */
1196 symbol_locate (symbolP, name, segment, valu, frag)
1198 CONST char * name; /* It is copied, the caller can modify. */
1199 segT segment; /* Segment identifier (SEG_<something>). */
1200 valueT valu; /* Symbol value. */
1201 fragS * frag; /* Associated fragment. */
1203 unsigned int name_length;
1204 char * preserved_copy_of_name;
1206 name_length = strlen (name) + 1; /* +1 for \0. */
1207 obstack_grow (¬es, name, name_length);
1208 preserved_copy_of_name = obstack_finish (¬es);
1209 #ifdef STRIP_UNDERSCORE
1210 if (preserved_copy_of_name[0] == '_')
1211 preserved_copy_of_name++;
1214 #ifdef tc_canonicalize_symbol_name
1215 preserved_copy_of_name =
1216 tc_canonicalize_symbol_name (preserved_copy_of_name);
1219 S_SET_NAME (symbolP, preserved_copy_of_name);
1221 S_SET_SEGMENT (symbolP, segment);
1222 S_SET_VALUE (symbolP, valu);
1223 symbol_clear_list_pointers(symbolP);
1225 symbol_set_frag (symbolP, frag);
1227 /* Link to end of symbol chain. */
1229 extern int symbol_table_frozen;
1230 if (symbol_table_frozen)
1234 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
1236 obj_symbol_new_hook (symbolP);
1238 #ifdef tc_symbol_new_hook
1239 tc_symbol_new_hook (symbolP);
1243 verify_symbol_chain (symbol_rootP, symbol_lastP);
1244 #endif /* DEBUG_SYMS */
1247 /* Check that an immediate is valid.
1248 If so, convert it to the right format. */
1251 validate_immediate (val)
1257 #define rotate_left(v, n) (v << n | v >> (32 - n))
1259 for (i = 0; i < 32; i += 2)
1260 if ((a = rotate_left (val, i)) <= 0xff)
1261 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
1266 /* Check to see if an immediate can be computed as two seperate immediate
1267 values, added together. We already know that this value cannot be
1268 computed by just one ARM instruction. */
1271 validate_immediate_twopart (val, highpart)
1273 unsigned int * highpart;
1278 for (i = 0; i < 32; i += 2)
1279 if (((a = rotate_left (val, i)) & 0xff) != 0)
1285 * highpart = (a >> 8) | ((i + 24) << 7);
1287 else if (a & 0xff0000)
1291 * highpart = (a >> 16) | ((i + 16) << 7);
1295 assert (a & 0xff000000);
1296 * highpart = (a >> 24) | ((i + 8) << 7);
1299 return (a & 0xff) | (i << 7);
1306 validate_offset_imm (val, hwse)
1310 if ((hwse && val > 255) || val > 4095)
1317 int a ATTRIBUTE_UNUSED;
1319 as_bad (_("Invalid syntax for .req directive."));
1324 int ignore ATTRIBUTE_UNUSED;
1326 /* We don't support putting frags in the BSS segment, we fake it by
1327 marking in_bss, then looking at s_skip for clues. */
1328 subseg_set (bss_section, 0);
1329 demand_empty_rest_of_line ();
1334 int ignore ATTRIBUTE_UNUSED;
1336 /* Never make frag if expect extra pass. */
1338 frag_align (1, 0, 0);
1340 record_alignment (now_seg, 1);
1342 demand_empty_rest_of_line ();
1347 int ignored ATTRIBUTE_UNUSED;
1352 if (current_poolP == NULL)
1355 /* Align pool as you have word accesses.
1356 Only make a frag if we have to. */
1358 frag_align (2, 0, 0);
1360 record_alignment (now_seg, 2);
1362 sprintf (sym_name, "$$lit_\002%x", lit_pool_num++);
1364 symbol_locate (current_poolP, sym_name, now_seg,
1365 (valueT) frag_now_fix (), frag_now);
1366 symbol_table_insert (current_poolP);
1368 ARM_SET_THUMB (current_poolP, thumb_mode);
1370 #if defined OBJ_COFF || defined OBJ_ELF
1371 ARM_SET_INTERWORK (current_poolP, support_interwork);
1374 while (lit_count < next_literal_pool_place)
1375 /* First output the expression in the instruction to the pool. */
1376 emit_expr (&(literals[lit_count++].exp), 4); /* .word */
1378 next_literal_pool_place = 0;
1379 current_poolP = NULL;
1382 /* Same as s_align_ptwo but align 0 => align 2. */
1386 int unused ATTRIBUTE_UNUSED;
1389 register long temp_fill;
1390 long max_alignment = 15;
1392 temp = get_absolute_expression ();
1393 if (temp > max_alignment)
1394 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
1397 as_bad (_("Alignment negative. 0 assumed."));
1401 if (*input_line_pointer == ',')
1403 input_line_pointer++;
1404 temp_fill = get_absolute_expression ();
1412 /* Only make a frag if we HAVE to. */
1413 if (temp && !need_pass_2)
1414 frag_align (temp, (int) temp_fill, 0);
1415 demand_empty_rest_of_line ();
1417 record_alignment (now_seg, temp);
1421 s_force_thumb (ignore)
1422 int ignore ATTRIBUTE_UNUSED;
1424 /* If we are not already in thumb mode go into it, EVEN if
1425 the target processor does not support thumb instructions.
1426 This is used by gcc/config/arm/lib1funcs.asm for example
1427 to compile interworking support functions even if the
1428 target processor should not support interworking. */
1433 record_alignment (now_seg, 1);
1436 demand_empty_rest_of_line ();
1440 s_thumb_func (ignore)
1441 int ignore ATTRIBUTE_UNUSED;
1446 /* The following label is the name/address of the start of a Thumb function.
1447 We need to know this for the interworking support. */
1448 label_is_thumb_function_name = true;
1450 demand_empty_rest_of_line ();
1453 /* Perform a .set directive, but also mark the alias as
1454 being a thumb function. */
1460 /* XXX the following is a duplicate of the code for s_set() in read.c
1461 We cannot just call that code as we need to get at the symbol that
1463 register char * name;
1464 register char delim;
1465 register char * end_name;
1466 register symbolS * symbolP;
1468 /* Especial apologies for the random logic:
1469 This just grew, and could be parsed much more simply!
1471 name = input_line_pointer;
1472 delim = get_symbol_end ();
1473 end_name = input_line_pointer;
1478 if (*input_line_pointer != ',')
1481 as_bad (_("Expected comma after name \"%s\""), name);
1483 ignore_rest_of_line ();
1487 input_line_pointer++;
1490 if (name[0] == '.' && name[1] == '\0')
1492 /* XXX - this should not happen to .thumb_set. */
1496 if ((symbolP = symbol_find (name)) == NULL
1497 && (symbolP = md_undefined_symbol (name)) == NULL)
1500 /* When doing symbol listings, play games with dummy fragments living
1501 outside the normal fragment chain to record the file and line info
1503 if (listing & LISTING_SYMBOLS)
1505 extern struct list_info_struct * listing_tail;
1506 fragS * dummy_frag = (fragS *) xmalloc (sizeof (fragS));
1508 memset (dummy_frag, 0, sizeof (fragS));
1509 dummy_frag->fr_type = rs_fill;
1510 dummy_frag->line = listing_tail;
1511 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
1512 dummy_frag->fr_symbol = symbolP;
1516 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
1519 /* "set" symbols are local unless otherwise specified. */
1520 SF_SET_LOCAL (symbolP);
1521 #endif /* OBJ_COFF */
1522 } /* Make a new symbol. */
1524 symbol_table_insert (symbolP);
1529 && S_IS_DEFINED (symbolP)
1530 && S_GET_SEGMENT (symbolP) != reg_section)
1531 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
1533 pseudo_set (symbolP);
1535 demand_empty_rest_of_line ();
1537 /* XXX Now we come to the Thumb specific bit of code. */
1539 THUMB_SET_FUNC (symbolP, 1);
1540 ARM_SET_THUMB (symbolP, 1);
1541 #if defined OBJ_ELF || defined OBJ_COFF
1542 ARM_SET_INTERWORK (symbolP, support_interwork);
1546 /* If we change section we must dump the literal pool first. */
1552 if (now_seg != text_section)
1556 obj_elf_text (ignore);
1566 if (flag_readonly_data_in_text)
1568 if (now_seg != text_section)
1571 else if (now_seg != data_section)
1575 obj_elf_data (ignore);
1583 arm_s_section (ignore)
1588 obj_elf_section (ignore);
1593 opcode_select (width)
1601 if (! (cpu_variant & ARM_THUMB))
1602 as_bad (_("selected processor does not support THUMB opcodes"));
1605 /* No need to force the alignment, since we will have been
1606 coming from ARM mode, which is word-aligned. */
1607 record_alignment (now_seg, 1);
1614 if ((cpu_variant & ARM_ANY) == ARM_THUMB)
1615 as_bad (_("selected processor does not support ARM opcodes"));
1620 frag_align (2, 0, 0);
1622 record_alignment (now_seg, 1);
1627 as_bad (_("invalid instruction size selected (%d)"), width);
1633 int ignore ATTRIBUTE_UNUSED;
1636 demand_empty_rest_of_line ();
1641 int ignore ATTRIBUTE_UNUSED;
1644 demand_empty_rest_of_line ();
1649 int unused ATTRIBUTE_UNUSED;
1653 temp = get_absolute_expression ();
1658 opcode_select (temp);
1662 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
1670 skip_whitespace (str);
1673 inst.error = _("Garbage following instruction");
1677 skip_past_comma (str)
1680 char * p = * str, c;
1683 while ((c = *p) == ' ' || c == ',')
1686 if (c == ',' && comma++)
1694 return comma ? SUCCESS : FAIL;
1697 /* A standard register must be given at this point.
1698 SHIFT is the place to put it in inst.instruction.
1699 Restores input start point on error.
1700 Returns the reg#, or FAIL. */
1703 reg_required_here (str, shift)
1707 static char buff [128]; /* XXX */
1709 char * start = * str;
1711 if ((reg = arm_reg_parse (str)) != FAIL && int_register (reg))
1714 inst.instruction |= reg << shift;
1718 /* Restore the start point, we may have got a reg of the wrong class. */
1721 /* In the few cases where we might be able to accept something else
1722 this error can be overridden. */
1723 sprintf (buff, _("Register expected, not '%.100s'"), start);
1729 static CONST struct asm_psr *
1731 register char ** ccp;
1733 char * start = * ccp;
1736 CONST struct asm_psr * psr;
1740 /* Skip to the end of the next word in the input stream. */
1745 while (isalpha (c) || c == '_');
1747 /* Terminate the word. */
1750 /* Now locate the word in the psr hash table. */
1751 psr = (CONST struct asm_psr *) hash_find (arm_psr_hsh, start);
1753 /* Restore the input stream. */
1756 /* If we found a valid match, advance the
1757 stream pointer past the end of the word. */
1763 /* Parse the input looking for a PSR flag. */
1766 psr_required_here (str)
1769 char * start = * str;
1770 CONST struct asm_psr * psr;
1772 psr = arm_psr_parse (str);
1776 /* If this is the SPSR that is being modified, set the R bit. */
1778 inst.instruction |= SPSR_BIT;
1780 /* Set the psr flags in the MSR instruction. */
1781 inst.instruction |= psr->field << PSR_SHIFT;
1786 /* In the few cases where we might be able to accept
1787 something else this error can be overridden. */
1788 inst.error = _("flag for {c}psr instruction expected");
1790 /* Restore the start point. */
1796 co_proc_number (str)
1799 int processor, pchar;
1801 skip_whitespace (* str);
1803 /* The data sheet seems to imply that just a number on its own is valid
1804 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1806 if (**str == 'p' || **str == 'P')
1810 if (pchar >= '0' && pchar <= '9')
1812 processor = pchar - '0';
1813 if (**str >= '0' && **str <= '9')
1815 processor = processor * 10 + *(*str)++ - '0';
1818 inst.error = _("Illegal co-processor number");
1825 inst.error = _("Bad or missing co-processor number");
1829 inst.instruction |= processor << 8;
1834 cp_opc_expr (str, where, length)
1841 skip_whitespace (* str);
1843 memset (&expr, '\0', sizeof (expr));
1845 if (my_get_expression (&expr, str))
1847 if (expr.X_op != O_constant)
1849 inst.error = _("bad or missing expression");
1853 if ((expr.X_add_number & ((1 << length) - 1)) != expr.X_add_number)
1855 inst.error = _("immediate co-processor expression too large");
1859 inst.instruction |= expr.X_add_number << where;
1864 cp_reg_required_here (str, where)
1869 char * start = *str;
1871 if ((reg = arm_reg_parse (str)) != FAIL && cp_register (reg))
1874 inst.instruction |= reg << where;
1878 /* In the few cases where we might be able to accept something else
1879 this error can be overridden. */
1880 inst.error = _("Co-processor register expected");
1882 /* Restore the start point. */
1888 fp_reg_required_here (str, where)
1893 char * start = * str;
1895 if ((reg = arm_reg_parse (str)) != FAIL && fp_register (reg))
1898 inst.instruction |= reg << where;
1902 /* In the few cases where we might be able to accept something else
1903 this error can be overridden. */
1904 inst.error = _("Floating point register expected");
1906 /* Restore the start point. */
1912 cp_address_offset (str)
1917 skip_whitespace (* str);
1919 if (! is_immediate_prefix (**str))
1921 inst.error = _("immediate expression expected");
1927 if (my_get_expression (& inst.reloc.exp, str))
1930 if (inst.reloc.exp.X_op == O_constant)
1932 offset = inst.reloc.exp.X_add_number;
1936 inst.error = _("co-processor address must be word aligned");
1940 if (offset > 1023 || offset < -1023)
1942 inst.error = _("offset too large");
1947 inst.instruction |= INDEX_UP;
1951 inst.instruction |= offset >> 2;
1954 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
1960 cp_address_required_here (str)
1972 skip_whitespace (p);
1974 if ((reg = reg_required_here (& p, 16)) == FAIL)
1977 skip_whitespace (p);
1983 if (skip_past_comma (& p) == SUCCESS)
1986 write_back = WRITE_BACK;
1990 inst.error = _("pc may not be used in post-increment");
1994 if (cp_address_offset (& p) == FAIL)
1998 pre_inc = PRE_INDEX | INDEX_UP;
2002 /* '['Rn, #expr']'[!] */
2004 if (skip_past_comma (& p) == FAIL)
2006 inst.error = _("pre-indexed expression expected");
2010 pre_inc = PRE_INDEX;
2012 if (cp_address_offset (& p) == FAIL)
2015 skip_whitespace (p);
2019 inst.error = _("missing ]");
2023 skip_whitespace (p);
2029 inst.error = _("pc may not be used with write-back");
2034 write_back = WRITE_BACK;
2040 if (my_get_expression (&inst.reloc.exp, &p))
2043 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
2044 inst.reloc.exp.X_add_number -= 8; /* PC rel adjust. */
2045 inst.reloc.pc_rel = 1;
2046 inst.instruction |= (REG_PC << 16);
2047 pre_inc = PRE_INDEX;
2050 inst.instruction |= write_back | pre_inc;
2058 unsigned long flags;
2060 /* Do nothing really. */
2061 inst.instruction |= flags; /* This is pointless. */
2069 unsigned long flags;
2073 /* Only one syntax. */
2074 skip_whitespace (str);
2076 if (reg_required_here (&str, 12) == FAIL)
2078 inst.error = BAD_ARGS;
2082 if (skip_past_comma (&str) == FAIL)
2084 inst.error = _("comma expected after register name");
2088 skip_whitespace (str);
2090 if ( strcmp (str, "CPSR") == 0
2091 || strcmp (str, "SPSR") == 0
2092 /* Lower case versions for backwards compatability. */
2093 || strcmp (str, "cpsr") == 0
2094 || strcmp (str, "spsr") == 0)
2097 /* This is for backwards compatability with older toolchains. */
2098 else if ( strcmp (str, "cpsr_all") == 0
2099 || strcmp (str, "spsr_all") == 0)
2103 inst.error = _("{C|S}PSR expected");
2107 if (* str == 's' || * str == 'S')
2108 inst.instruction |= SPSR_BIT;
2111 inst.instruction |= flags;
2115 /* Two possible forms:
2116 "{C|S}PSR_<field>, Rm",
2117 "{C|S}PSR_f, #expression". */
2122 unsigned long flags;
2124 skip_whitespace (str);
2126 if (psr_required_here (& str) == FAIL)
2129 if (skip_past_comma (& str) == FAIL)
2131 inst.error = _("comma missing after psr flags");
2135 skip_whitespace (str);
2137 if (reg_required_here (& str, 0) != FAIL)
2140 inst.instruction |= flags;
2145 if (! is_immediate_prefix (* str))
2148 _("only a register or immediate value can follow a psr flag");
2155 if (my_get_expression (& inst.reloc.exp, & str))
2158 _("only a register or immediate value can follow a psr flag");
2162 if (inst.instruction & ((PSR_c | PSR_x | PSR_s) << PSR_SHIFT))
2164 inst.error = _("can only set flag field with immediate value");
2168 flags |= INST_IMMEDIATE;
2170 if (inst.reloc.exp.X_add_symbol)
2172 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2173 inst.reloc.pc_rel = 0;
2177 unsigned value = validate_immediate (inst.reloc.exp.X_add_number);
2179 if (value == (unsigned) FAIL)
2181 inst.error = _("Invalid constant");
2185 inst.instruction |= value;
2189 inst.instruction |= flags;
2193 /* Long Multiply Parser
2194 UMULL RdLo, RdHi, Rm, Rs
2195 SMULL RdLo, RdHi, Rm, Rs
2196 UMLAL RdLo, RdHi, Rm, Rs
2197 SMLAL RdLo, RdHi, Rm, Rs. */
2200 do_mull (str, flags)
2202 unsigned long flags;
2204 int rdlo, rdhi, rm, rs;
2206 /* Only one format "rdlo, rdhi, rm, rs". */
2207 skip_whitespace (str);
2209 if ((rdlo = reg_required_here (&str, 12)) == FAIL)
2211 inst.error = BAD_ARGS;
2215 if (skip_past_comma (&str) == FAIL
2216 || (rdhi = reg_required_here (&str, 16)) == FAIL)
2218 inst.error = BAD_ARGS;
2222 if (skip_past_comma (&str) == FAIL
2223 || (rm = reg_required_here (&str, 0)) == FAIL)
2225 inst.error = BAD_ARGS;
2229 /* rdhi, rdlo and rm must all be different. */
2230 if (rdlo == rdhi || rdlo == rm || rdhi == rm)
2231 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2233 if (skip_past_comma (&str) == FAIL
2234 || (rs = reg_required_here (&str, 8)) == FAIL)
2236 inst.error = BAD_ARGS;
2240 if (rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC || rdhi == REG_PC)
2242 inst.error = BAD_PC;
2246 inst.instruction |= flags;
2254 unsigned long flags;
2258 /* Only one format "rd, rm, rs". */
2259 skip_whitespace (str);
2261 if ((rd = reg_required_here (&str, 16)) == FAIL)
2263 inst.error = BAD_ARGS;
2269 inst.error = BAD_PC;
2273 if (skip_past_comma (&str) == FAIL
2274 || (rm = reg_required_here (&str, 0)) == FAIL)
2276 inst.error = BAD_ARGS;
2282 inst.error = BAD_PC;
2287 as_tsktsk (_("rd and rm should be different in mul"));
2289 if (skip_past_comma (&str) == FAIL
2290 || (rm = reg_required_here (&str, 8)) == FAIL)
2292 inst.error = BAD_ARGS;
2298 inst.error = BAD_PC;
2302 inst.instruction |= flags;
2310 unsigned long flags;
2314 /* Only one format "rd, rm, rs, rn". */
2315 skip_whitespace (str);
2317 if ((rd = reg_required_here (&str, 16)) == FAIL)
2319 inst.error = BAD_ARGS;
2325 inst.error = BAD_PC;
2329 if (skip_past_comma (&str) == FAIL
2330 || (rm = reg_required_here (&str, 0)) == FAIL)
2332 inst.error = BAD_ARGS;
2338 inst.error = BAD_PC;
2343 as_tsktsk (_("rd and rm should be different in mla"));
2345 if (skip_past_comma (&str) == FAIL
2346 || (rd = reg_required_here (&str, 8)) == FAIL
2347 || skip_past_comma (&str) == FAIL
2348 || (rm = reg_required_here (&str, 12)) == FAIL)
2350 inst.error = BAD_ARGS;
2354 if (rd == REG_PC || rm == REG_PC)
2356 inst.error = BAD_PC;
2360 inst.instruction |= flags;
2365 /* Returns the index into fp_values of a floating point number,
2366 or -1 if not in the table. */
2369 my_get_float_expression (str)
2372 LITTLENUM_TYPE words[MAX_LITTLENUMS];
2378 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
2380 /* Look for a raw floating point number. */
2381 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
2382 && is_end_of_line[(unsigned char) *save_in])
2384 for (i = 0; i < NUM_FLOAT_VALS; i++)
2386 for (j = 0; j < MAX_LITTLENUMS; j++)
2388 if (words[j] != fp_values[i][j])
2392 if (j == MAX_LITTLENUMS)
2400 /* Try and parse a more complex expression, this will probably fail
2401 unless the code uses a floating point prefix (eg "0f"). */
2402 save_in = input_line_pointer;
2403 input_line_pointer = *str;
2404 if (expression (&exp) == absolute_section
2405 && exp.X_op == O_big
2406 && exp.X_add_number < 0)
2408 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2410 if (gen_to_words (words, 5, (long) 15) == 0)
2412 for (i = 0; i < NUM_FLOAT_VALS; i++)
2414 for (j = 0; j < MAX_LITTLENUMS; j++)
2416 if (words[j] != fp_values[i][j])
2420 if (j == MAX_LITTLENUMS)
2422 *str = input_line_pointer;
2423 input_line_pointer = save_in;
2430 *str = input_line_pointer;
2431 input_line_pointer = save_in;
2435 /* Return true if anything in the expression is a bignum. */
2438 walk_no_bignums (sp)
2441 if (symbol_get_value_expression (sp)->X_op == O_big)
2444 if (symbol_get_value_expression (sp)->X_add_symbol)
2446 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
2447 || (symbol_get_value_expression (sp)->X_op_symbol
2448 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
2455 my_get_expression (ep, str)
2462 save_in = input_line_pointer;
2463 input_line_pointer = *str;
2464 seg = expression (ep);
2467 if (seg != absolute_section
2468 && seg != text_section
2469 && seg != data_section
2470 && seg != bss_section
2471 && seg != undefined_section)
2473 inst.error = _("bad_segment");
2474 *str = input_line_pointer;
2475 input_line_pointer = save_in;
2480 /* Get rid of any bignums now, so that we don't generate an error for which
2481 we can't establish a line number later on. Big numbers are never valid
2482 in instructions, which is where this routine is always called. */
2483 if (ep->X_op == O_big
2484 || (ep->X_add_symbol
2485 && (walk_no_bignums (ep->X_add_symbol)
2487 && walk_no_bignums (ep->X_op_symbol)))))
2489 inst.error = _("Invalid constant");
2490 *str = input_line_pointer;
2491 input_line_pointer = save_in;
2495 *str = input_line_pointer;
2496 input_line_pointer = save_in;
2500 /* UNRESTRICT should be one if <shift> <register> is permitted for this
2504 decode_shift (str, unrestrict)
2508 struct asm_shift * shft;
2512 skip_whitespace (* str);
2514 for (p = * str; isalpha (* p); p ++)
2519 inst.error = _("Shift expression expected");
2525 shft = (struct asm_shift *) hash_find (arm_shift_hsh, * str);
2529 if ( ! strncmp (* str, "rrx", 3)
2530 || ! strncmp (* str, "RRX", 3))
2533 inst.instruction |= shft->value;
2537 skip_whitespace (p);
2539 if (unrestrict && reg_required_here (& p, 8) != FAIL)
2541 inst.instruction |= shft->value | SHIFT_BY_REG;
2545 else if (is_immediate_prefix (* p))
2550 if (my_get_expression (& inst.reloc.exp, & p))
2553 /* Validate some simple #expressions. */
2554 if (inst.reloc.exp.X_op == O_constant)
2556 unsigned num = inst.reloc.exp.X_add_number;
2558 /* Reject operations greater than 32, or lsl #32. */
2559 if (num > 32 || (num == 32 && shft->value == 0))
2561 inst.error = _("Invalid immediate shift");
2565 /* Shifts of zero should be converted to lsl
2573 /* Shifts of 32 are encoded as 0, for those shifts that
2578 inst.instruction |= (num << 7) | shft->value;
2583 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
2584 inst.reloc.pc_rel = 0;
2585 inst.instruction |= shft->value;
2592 inst.error = (unrestrict
2593 ? _("shift requires register or #expression")
2594 : _("shift requires #expression"));
2600 inst.error = _("Shift expression expected");
2604 /* Do those data_ops which can take a negative immediate constant
2605 by altering the instuction. A bit of a hack really.
2609 by inverting the second operand, and
2612 by negating the second operand. */
2615 negate_data_op (instruction, value)
2616 unsigned long * instruction;
2617 unsigned long value;
2620 unsigned long negated, inverted;
2622 negated = validate_immediate (-value);
2623 inverted = validate_immediate (~value);
2625 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
2628 /* First negates. */
2629 case OPCODE_SUB: /* ADD <-> SUB */
2630 new_inst = OPCODE_ADD;
2635 new_inst = OPCODE_SUB;
2639 case OPCODE_CMP: /* CMP <-> CMN */
2640 new_inst = OPCODE_CMN;
2645 new_inst = OPCODE_CMP;
2649 /* Now Inverted ops. */
2650 case OPCODE_MOV: /* MOV <-> MVN */
2651 new_inst = OPCODE_MVN;
2656 new_inst = OPCODE_MOV;
2660 case OPCODE_AND: /* AND <-> BIC */
2661 new_inst = OPCODE_BIC;
2666 new_inst = OPCODE_AND;
2670 case OPCODE_ADC: /* ADC <-> SBC */
2671 new_inst = OPCODE_SBC;
2676 new_inst = OPCODE_ADC;
2680 /* We cannot do anything. */
2685 if (value == (unsigned) FAIL)
2688 *instruction &= OPCODE_MASK;
2689 *instruction |= new_inst << DATA_OP_SHIFT;
2700 skip_whitespace (* str);
2702 if (reg_required_here (str, 0) != FAIL)
2704 if (skip_past_comma (str) == SUCCESS)
2705 /* Shift operation on register. */
2706 return decode_shift (str, NO_SHIFT_RESTRICT);
2712 /* Immediate expression. */
2713 if (is_immediate_prefix (**str))
2718 if (my_get_expression (&inst.reloc.exp, str))
2721 if (inst.reloc.exp.X_add_symbol)
2723 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2724 inst.reloc.pc_rel = 0;
2728 if (skip_past_comma (str) == SUCCESS)
2730 /* #x, y -- ie explicit rotation by Y. */
2731 if (my_get_expression (&expr, str))
2734 if (expr.X_op != O_constant)
2736 inst.error = _("Constant expression expected");
2740 /* Rotate must be a multiple of 2. */
2741 if (((unsigned) expr.X_add_number) > 30
2742 || (expr.X_add_number & 1) != 0
2743 || ((unsigned) inst.reloc.exp.X_add_number) > 255)
2745 inst.error = _("Invalid constant");
2748 inst.instruction |= INST_IMMEDIATE;
2749 inst.instruction |= inst.reloc.exp.X_add_number;
2750 inst.instruction |= expr.X_add_number << 7;
2754 /* Implicit rotation, select a suitable one. */
2755 value = validate_immediate (inst.reloc.exp.X_add_number);
2759 /* Can't be done. Perhaps the code reads something like
2760 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be OK. */
2761 if ((value = negate_data_op (&inst.instruction,
2762 inst.reloc.exp.X_add_number))
2765 inst.error = _("Invalid constant");
2770 inst.instruction |= value;
2773 inst.instruction |= INST_IMMEDIATE;
2778 inst.error = _("Register or shift expression expected");
2787 skip_whitespace (* str);
2789 if (fp_reg_required_here (str, 0) != FAIL)
2793 /* Immediate expression. */
2794 if (*((*str)++) == '#')
2800 skip_whitespace (* str);
2802 /* First try and match exact strings, this is to guarantee
2803 that some formats will work even for cross assembly. */
2805 for (i = 0; fp_const[i]; i++)
2807 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
2811 *str += strlen (fp_const[i]);
2812 if (is_end_of_line[(unsigned char) **str])
2814 inst.instruction |= i + 8;
2821 /* Just because we didn't get a match doesn't mean that the
2822 constant isn't valid, just that it is in a format that we
2823 don't automatically recognize. Try parsing it with
2824 the standard expression routines. */
2825 if ((i = my_get_float_expression (str)) >= 0)
2827 inst.instruction |= i + 8;
2831 inst.error = _("Invalid floating point immediate expression");
2835 _("Floating point register or immediate expression expected");
2841 do_arit (str, flags)
2843 unsigned long flags;
2845 skip_whitespace (str);
2847 if (reg_required_here (&str, 12) == FAIL
2848 || skip_past_comma (&str) == FAIL
2849 || reg_required_here (&str, 16) == FAIL
2850 || skip_past_comma (&str) == FAIL
2851 || data_op2 (&str) == FAIL)
2854 inst.error = BAD_ARGS;
2858 inst.instruction |= flags;
2866 unsigned long flags;
2868 /* This is a pseudo-op of the form "adr rd, label" to be converted
2869 into a relative address of the form "add rd, pc, #label-.-8". */
2870 skip_whitespace (str);
2872 if (reg_required_here (&str, 12) == FAIL
2873 || skip_past_comma (&str) == FAIL
2874 || my_get_expression (&inst.reloc.exp, &str))
2877 inst.error = BAD_ARGS;
2881 /* Frag hacking will turn this into a sub instruction if the offset turns
2882 out to be negative. */
2883 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
2884 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust. */
2885 inst.reloc.pc_rel = 1;
2886 inst.instruction |= flags;
2892 do_adrl (str, flags)
2894 unsigned long flags;
2896 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2897 into a relative address of the form:
2898 add rd, pc, #low(label-.-8)"
2899 add rd, rd, #high(label-.-8)" */
2901 skip_whitespace (str);
2903 if (reg_required_here (& str, 12) == FAIL
2904 || skip_past_comma (& str) == FAIL
2905 || my_get_expression (& inst.reloc.exp, & str))
2908 inst.error = BAD_ARGS;
2914 /* Frag hacking will turn this into a sub instruction if the offset turns
2915 out to be negative. */
2916 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
2917 inst.reloc.exp.X_add_number -= 8; /* PC relative adjust */
2918 inst.reloc.pc_rel = 1;
2919 inst.instruction |= flags;
2920 inst.size = INSN_SIZE * 2;
2928 unsigned long flags;
2930 skip_whitespace (str);
2932 if (reg_required_here (&str, 16) == FAIL)
2935 inst.error = BAD_ARGS;
2939 if (skip_past_comma (&str) == FAIL
2940 || data_op2 (&str) == FAIL)
2943 inst.error = BAD_ARGS;
2947 inst.instruction |= flags;
2948 if ((flags & 0x0000f000) == 0)
2949 inst.instruction |= CONDS_BIT;
2958 unsigned long flags;
2960 skip_whitespace (str);
2962 if (reg_required_here (&str, 12) == FAIL)
2965 inst.error = BAD_ARGS;
2969 if (skip_past_comma (&str) == FAIL
2970 || data_op2 (&str) == FAIL)
2973 inst.error = BAD_ARGS;
2977 inst.instruction |= flags;
2983 ldst_extend (str, hwse)
2994 if (my_get_expression (& inst.reloc.exp, str))
2997 if (inst.reloc.exp.X_op == O_constant)
2999 int value = inst.reloc.exp.X_add_number;
3001 if ((hwse && (value < -255 || value > 255))
3002 || (value < -4095 || value > 4095))
3004 inst.error = _("address offset too large");
3014 /* Halfword and signextension instructions have the
3015 immediate value split across bits 11..8 and bits 3..0. */
3017 inst.instruction |= (add | HWOFFSET_IMM
3018 | ((value >> 4) << 8) | (value & 0xF));
3020 inst.instruction |= add | value;
3026 inst.instruction |= HWOFFSET_IMM;
3027 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3030 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3031 inst.reloc.pc_rel = 0;
3044 if (reg_required_here (str, 0) == FAIL)
3048 inst.instruction |= add;
3051 inst.instruction |= add | OFFSET_REG;
3052 if (skip_past_comma (str) == SUCCESS)
3053 return decode_shift (str, SHIFT_RESTRICT);
3061 do_ldst (str, flags)
3063 unsigned long flags;
3070 /* This is not ideal, but it is the simplest way of dealing with the
3071 ARM7T halfword instructions (since they use a different
3072 encoding, but the same mnemonic): */
3073 halfword = (flags & 0x80000000) != 0;
3076 /* This is actually a load/store of a halfword, or a
3077 signed-extension load. */
3078 if ((cpu_variant & ARM_HALFWORD) == 0)
3081 = _("Processor does not support halfwords or signed bytes");
3085 inst.instruction = ((inst.instruction & COND_MASK)
3086 | (flags & ~COND_MASK));
3091 skip_whitespace (str);
3093 if ((conflict_reg = reg_required_here (& str, 12)) == FAIL)
3096 inst.error = BAD_ARGS;
3100 if (skip_past_comma (& str) == FAIL)
3102 inst.error = _("Address expected");
3112 skip_whitespace (str);
3114 if ((reg = reg_required_here (&str, 16)) == FAIL)
3117 /* Conflicts can occur on stores as well as loads. */
3118 conflict_reg = (conflict_reg == reg);
3120 skip_whitespace (str);
3126 if (skip_past_comma (&str) == SUCCESS)
3128 /* [Rn],... (post inc) */
3129 if (ldst_extend (&str, halfword) == FAIL)
3132 as_warn (_("%s register same as write-back base"),
3133 ((inst.instruction & LOAD_BIT)
3134 ? _("destination") : _("source")));
3140 inst.instruction |= HWOFFSET_IMM;
3142 skip_whitespace (str);
3147 as_warn (_("%s register same as write-back base"),
3148 ((inst.instruction & LOAD_BIT)
3149 ? _("destination") : _("source")));
3151 inst.instruction |= WRITE_BACK;
3155 if (! (flags & TRANS_BIT))
3162 if (skip_past_comma (&str) == FAIL)
3164 inst.error = _("pre-indexed expression expected");
3169 if (ldst_extend (&str, halfword) == FAIL)
3172 skip_whitespace (str);
3176 inst.error = _("missing ]");
3180 skip_whitespace (str);
3185 as_warn (_("%s register same as write-back base"),
3186 ((inst.instruction & LOAD_BIT)
3187 ? _("destination") : _("source")));
3189 inst.instruction |= WRITE_BACK;
3193 else if (*str == '=')
3195 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
3198 skip_whitespace (str);
3200 if (my_get_expression (&inst.reloc.exp, &str))
3203 if (inst.reloc.exp.X_op != O_constant
3204 && inst.reloc.exp.X_op != O_symbol)
3206 inst.error = _("Constant expression expected");
3210 if (inst.reloc.exp.X_op == O_constant
3211 && (value = validate_immediate (inst.reloc.exp.X_add_number)) != FAIL)
3213 /* This can be done with a mov instruction. */
3214 inst.instruction &= LITERAL_MASK;
3215 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
3216 inst.instruction |= (flags & COND_MASK) | (value & 0xfff);
3222 /* Insert into literal pool. */
3223 if (add_to_lit_pool () == FAIL)
3226 inst.error = _("literal pool insertion failed");
3230 /* Change the instruction exp to point to the pool. */
3233 inst.instruction |= HWOFFSET_IMM;
3234 inst.reloc.type = BFD_RELOC_ARM_HWLITERAL;
3237 inst.reloc.type = BFD_RELOC_ARM_LITERAL;
3238 inst.reloc.pc_rel = 1;
3239 inst.instruction |= (REG_PC << 16);
3245 if (my_get_expression (&inst.reloc.exp, &str))
3250 inst.instruction |= HWOFFSET_IMM;
3251 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
3254 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
3256 /* PC rel adjust. */
3257 inst.reloc.exp.X_add_number -= 8;
3259 inst.reloc.pc_rel = 1;
3260 inst.instruction |= (REG_PC << 16);
3264 if (pre_inc && (flags & TRANS_BIT))
3265 inst.error = _("Pre-increment instruction with translate");
3267 inst.instruction |= flags | (pre_inc ? PRE_INDEX : 0);
3276 char * str = * strp;
3280 /* We come back here if we get ranges concatenated by '+' or '|'. */
3295 skip_whitespace (str);
3297 if ((reg = reg_required_here (& str, -1)) == FAIL)
3306 inst.error = _("Bad range in register list");
3310 for (i = cur_reg + 1; i < reg; i++)
3312 if (range & (1 << i))
3314 (_("Warning: Duplicated register (r%d) in register list"),
3322 if (range & (1 << reg))
3323 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3325 else if (reg <= cur_reg)
3326 as_tsktsk (_("Warning: Register range not in ascending order"));
3331 while (skip_past_comma (&str) != FAIL
3332 || (in_range = 1, *str++ == '-'));
3334 skip_whitespace (str);
3338 inst.error = _("Missing `}'");
3346 if (my_get_expression (&expr, &str))
3349 if (expr.X_op == O_constant)
3351 if (expr.X_add_number
3352 != (expr.X_add_number & 0x0000ffff))
3354 inst.error = _("invalid register mask");
3358 if ((range & expr.X_add_number) != 0)
3360 int regno = range & expr.X_add_number;
3363 regno = (1 << regno) - 1;
3365 (_("Warning: Duplicated register (r%d) in register list"),
3369 range |= expr.X_add_number;
3373 if (inst.reloc.type != 0)
3375 inst.error = _("expression too complex");
3379 memcpy (&inst.reloc.exp, &expr, sizeof (expressionS));
3380 inst.reloc.type = BFD_RELOC_ARM_MULTI;
3381 inst.reloc.pc_rel = 0;
3385 skip_whitespace (str);
3387 if (*str == '|' || *str == '+')
3393 while (another_range);
3400 do_ldmstm (str, flags)
3402 unsigned long flags;
3407 skip_whitespace (str);
3409 if ((base_reg = reg_required_here (&str, 16)) == FAIL)
3412 if (base_reg == REG_PC)
3414 inst.error = _("r15 not allowed as base register");
3418 skip_whitespace (str);
3422 flags |= WRITE_BACK;
3426 if (skip_past_comma (&str) == FAIL
3427 || (range = reg_list (&str)) == FAIL)
3430 inst.error = BAD_ARGS;
3437 flags |= LDM_TYPE_2_OR_3;
3440 inst.instruction |= flags | range;
3448 unsigned long flags;
3450 skip_whitespace (str);
3452 /* Allow optional leading '#'. */
3453 if (is_immediate_prefix (*str))
3456 if (my_get_expression (& inst.reloc.exp, & str))
3459 inst.reloc.type = BFD_RELOC_ARM_SWI;
3460 inst.reloc.pc_rel = 0;
3461 inst.instruction |= flags;
3469 do_swap (str, flags)
3471 unsigned long flags;
3475 skip_whitespace (str);
3477 if ((reg = reg_required_here (&str, 12)) == FAIL)
3482 inst.error = _("r15 not allowed in swap");
3486 if (skip_past_comma (&str) == FAIL
3487 || (reg = reg_required_here (&str, 0)) == FAIL)
3490 inst.error = BAD_ARGS;
3496 inst.error = _("r15 not allowed in swap");
3500 if (skip_past_comma (&str) == FAIL
3503 inst.error = BAD_ARGS;
3507 skip_whitespace (str);
3509 if ((reg = reg_required_here (&str, 16)) == FAIL)
3514 inst.error = BAD_PC;
3518 skip_whitespace (str);
3522 inst.error = _("missing ]");
3526 inst.instruction |= flags;
3532 do_branch (str, flags)
3534 unsigned long flags ATTRIBUTE_UNUSED;
3536 if (my_get_expression (&inst.reloc.exp, &str))
3543 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
3544 required for the instruction. */
3546 /* arm_parse_reloc () works on input_line_pointer.
3547 We actually want to parse the operands to the branch instruction
3548 passed in 'str'. Save the input pointer and restore it later. */
3549 save_in = input_line_pointer;
3550 input_line_pointer = str;
3551 if (inst.reloc.exp.X_op == O_symbol
3553 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32)
3555 inst.reloc.type = BFD_RELOC_ARM_PLT32;
3556 inst.reloc.pc_rel = 0;
3557 /* Modify str to point to after parsed operands, otherwise
3558 end_of_line() will complain about the (PLT) left in str. */
3559 str = input_line_pointer;
3563 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3564 inst.reloc.pc_rel = 1;
3566 input_line_pointer = save_in;
3569 inst.reloc.type = BFD_RELOC_ARM_PCREL_BRANCH;
3570 inst.reloc.pc_rel = 1;
3571 #endif /* OBJ_ELF */
3580 unsigned long flags ATTRIBUTE_UNUSED;
3584 skip_whitespace (str);
3586 if ((reg = reg_required_here (&str, 0)) == FAIL)
3588 inst.error = BAD_ARGS;
3593 inst.error = BAD_PC;
3601 unsigned long flags ATTRIBUTE_UNUSED;
3603 /* Co-processor data operation.
3604 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3605 skip_whitespace (str);
3607 if (co_proc_number (&str) == FAIL)
3610 inst.error = BAD_ARGS;
3614 if (skip_past_comma (&str) == FAIL
3615 || cp_opc_expr (&str, 20,4) == FAIL)
3618 inst.error = BAD_ARGS;
3622 if (skip_past_comma (&str) == FAIL
3623 || cp_reg_required_here (&str, 12) == FAIL)
3626 inst.error = BAD_ARGS;
3630 if (skip_past_comma (&str) == FAIL
3631 || cp_reg_required_here (&str, 16) == FAIL)
3634 inst.error = BAD_ARGS;
3638 if (skip_past_comma (&str) == FAIL
3639 || cp_reg_required_here (&str, 0) == FAIL)
3642 inst.error = BAD_ARGS;
3646 if (skip_past_comma (&str) == SUCCESS)
3648 if (cp_opc_expr (&str, 5, 3) == FAIL)
3651 inst.error = BAD_ARGS;
3661 do_lstc (str, flags)
3663 unsigned long flags;
3665 /* Co-processor register load/store.
3666 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3668 skip_whitespace (str);
3670 if (co_proc_number (&str) == FAIL)
3673 inst.error = BAD_ARGS;
3677 if (skip_past_comma (&str) == FAIL
3678 || cp_reg_required_here (&str, 12) == FAIL)
3681 inst.error = BAD_ARGS;
3685 if (skip_past_comma (&str) == FAIL
3686 || cp_address_required_here (&str) == FAIL)
3689 inst.error = BAD_ARGS;
3693 inst.instruction |= flags;
3699 do_co_reg (str, flags)
3701 unsigned long flags;
3703 /* Co-processor register transfer.
3704 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3706 skip_whitespace (str);
3708 if (co_proc_number (&str) == FAIL)
3711 inst.error = BAD_ARGS;
3715 if (skip_past_comma (&str) == FAIL
3716 || cp_opc_expr (&str, 21, 3) == FAIL)
3719 inst.error = BAD_ARGS;
3723 if (skip_past_comma (&str) == FAIL
3724 || reg_required_here (&str, 12) == FAIL)
3727 inst.error = BAD_ARGS;
3731 if (skip_past_comma (&str) == FAIL
3732 || cp_reg_required_here (&str, 16) == FAIL)
3735 inst.error = BAD_ARGS;
3739 if (skip_past_comma (&str) == FAIL
3740 || cp_reg_required_here (&str, 0) == FAIL)
3743 inst.error = BAD_ARGS;
3747 if (skip_past_comma (&str) == SUCCESS)
3749 if (cp_opc_expr (&str, 5, 3) == FAIL)
3752 inst.error = BAD_ARGS;
3758 inst.error = BAD_COND;
3766 do_fp_ctrl (str, flags)
3768 unsigned long flags ATTRIBUTE_UNUSED;
3770 /* FP control registers.
3771 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3773 skip_whitespace (str);
3775 if (reg_required_here (&str, 12) == FAIL)
3778 inst.error = BAD_ARGS;
3787 do_fp_ldst (str, flags)
3789 unsigned long flags ATTRIBUTE_UNUSED;
3791 skip_whitespace (str);
3793 switch (inst.suffix)
3798 inst.instruction |= CP_T_X;
3801 inst.instruction |= CP_T_Y;
3804 inst.instruction |= CP_T_X | CP_T_Y;
3810 if (fp_reg_required_here (&str, 12) == FAIL)
3813 inst.error = BAD_ARGS;
3817 if (skip_past_comma (&str) == FAIL
3818 || cp_address_required_here (&str) == FAIL)
3821 inst.error = BAD_ARGS;
3829 do_fp_ldmstm (str, flags)
3831 unsigned long flags;
3835 skip_whitespace (str);
3837 if (fp_reg_required_here (&str, 12) == FAIL)
3840 inst.error = BAD_ARGS;
3844 /* Get Number of registers to transfer. */
3845 if (skip_past_comma (&str) == FAIL
3846 || my_get_expression (&inst.reloc.exp, &str))
3849 inst.error = _("constant expression expected");
3853 if (inst.reloc.exp.X_op != O_constant)
3855 inst.error = _("Constant value required for number of registers");
3859 num_regs = inst.reloc.exp.X_add_number;
3861 if (num_regs < 1 || num_regs > 4)
3863 inst.error = _("number of registers must be in the range [1:4]");
3870 inst.instruction |= CP_T_X;
3873 inst.instruction |= CP_T_Y;
3876 inst.instruction |= CP_T_Y | CP_T_X;
3890 /* The instruction specified "ea" or "fd", so we can only accept
3891 [Rn]{!}. The instruction does not really support stacking or
3892 unstacking, so we have to emulate these by setting appropriate
3893 bits and offsets. */
3894 if (skip_past_comma (&str) == FAIL
3898 inst.error = BAD_ARGS;
3903 skip_whitespace (str);
3905 if ((reg = reg_required_here (&str, 16)) == FAIL)
3908 skip_whitespace (str);
3912 inst.error = BAD_ARGS;
3924 _("R15 not allowed as base register with write-back");
3931 if (flags & CP_T_Pre)
3933 /* Pre-decrement. */
3934 offset = 3 * num_regs;
3940 /* Post-increment. */
3944 offset = 3 * num_regs;
3948 /* No write-back, so convert this into a standard pre-increment
3949 instruction -- aesthetically more pleasing. */
3950 flags = CP_T_Pre | CP_T_UD;
3955 inst.instruction |= flags | offset;
3957 else if (skip_past_comma (&str) == FAIL
3958 || cp_address_required_here (&str) == FAIL)
3961 inst.error = BAD_ARGS;
3969 do_fp_dyadic (str, flags)
3971 unsigned long flags;
3973 skip_whitespace (str);
3975 switch (inst.suffix)
3980 inst.instruction |= 0x00000080;
3983 inst.instruction |= 0x00080000;
3989 if (fp_reg_required_here (&str, 12) == FAIL)
3992 inst.error = BAD_ARGS;
3996 if (skip_past_comma (&str) == FAIL
3997 || fp_reg_required_here (&str, 16) == FAIL)
4000 inst.error = BAD_ARGS;
4004 if (skip_past_comma (&str) == FAIL
4005 || fp_op2 (&str) == FAIL)
4008 inst.error = BAD_ARGS;
4012 inst.instruction |= flags;
4018 do_fp_monadic (str, flags)
4020 unsigned long flags;
4022 skip_whitespace (str);
4024 switch (inst.suffix)
4029 inst.instruction |= 0x00000080;
4032 inst.instruction |= 0x00080000;
4038 if (fp_reg_required_here (&str, 12) == FAIL)
4041 inst.error = BAD_ARGS;
4045 if (skip_past_comma (&str) == FAIL
4046 || fp_op2 (&str) == FAIL)
4049 inst.error = BAD_ARGS;
4053 inst.instruction |= flags;
4059 do_fp_cmp (str, flags)
4061 unsigned long flags;
4063 skip_whitespace (str);
4065 if (fp_reg_required_here (&str, 16) == FAIL)
4068 inst.error = BAD_ARGS;
4072 if (skip_past_comma (&str) == FAIL
4073 || fp_op2 (&str) == FAIL)
4076 inst.error = BAD_ARGS;
4080 inst.instruction |= flags;
4086 do_fp_from_reg (str, flags)
4088 unsigned long flags;
4090 skip_whitespace (str);
4092 switch (inst.suffix)
4097 inst.instruction |= 0x00000080;
4100 inst.instruction |= 0x00080000;
4106 if (fp_reg_required_here (&str, 16) == FAIL)
4109 inst.error = BAD_ARGS;
4113 if (skip_past_comma (&str) == FAIL
4114 || reg_required_here (&str, 12) == FAIL)
4117 inst.error = BAD_ARGS;
4121 inst.instruction |= flags;
4127 do_fp_to_reg (str, flags)
4129 unsigned long flags;
4131 skip_whitespace (str);
4133 if (reg_required_here (&str, 12) == FAIL)
4136 if (skip_past_comma (&str) == FAIL
4137 || fp_reg_required_here (&str, 0) == FAIL)
4140 inst.error = BAD_ARGS;
4144 inst.instruction |= flags;
4149 /* Thumb specific routines. */
4151 /* Parse and validate that a register is of the right form, this saves
4152 repeated checking of this information in many similar cases.
4153 Unlike the 32-bit case we do not insert the register into the opcode
4154 here, since the position is often unknown until the full instruction
4158 thumb_reg (strp, hi_lo)
4164 if ((reg = reg_required_here (strp, -1)) == FAIL)
4172 inst.error = _("lo register required");
4180 inst.error = _("hi register required");
4192 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4196 thumb_add_sub (str, subtract)
4200 int Rd, Rs, Rn = FAIL;
4202 skip_whitespace (str);
4204 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4205 || skip_past_comma (&str) == FAIL)
4208 inst.error = BAD_ARGS;
4212 if (is_immediate_prefix (*str))
4216 if (my_get_expression (&inst.reloc.exp, &str))
4221 if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4224 if (skip_past_comma (&str) == FAIL)
4226 /* Two operand format, shuffle the registers
4227 and pretend there are 3. */
4231 else if (is_immediate_prefix (*str))
4234 if (my_get_expression (&inst.reloc.exp, &str))
4237 else if ((Rn = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4241 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4242 for the latter case, EXPR contains the immediate that was found. */
4245 /* All register format. */
4246 if (Rd > 7 || Rs > 7 || Rn > 7)
4250 inst.error = _("dest and source1 must be the same register");
4254 /* Can't do this for SUB. */
4257 inst.error = _("subtract valid only on lo regs");
4261 inst.instruction = (T_OPCODE_ADD_HI
4262 | (Rd > 7 ? THUMB_H1 : 0)
4263 | (Rn > 7 ? THUMB_H2 : 0));
4264 inst.instruction |= (Rd & 7) | ((Rn & 7) << 3);
4268 inst.instruction = subtract ? T_OPCODE_SUB_R3 : T_OPCODE_ADD_R3;
4269 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
4274 /* Immediate expression, now things start to get nasty. */
4276 /* First deal with HI regs, only very restricted cases allowed:
4277 Adjusting SP, and using PC or SP to get an address. */
4278 if ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
4279 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC))
4281 inst.error = _("invalid Hi register with immediate");
4285 if (inst.reloc.exp.X_op != O_constant)
4287 /* Value isn't known yet, all we can do is store all the fragments
4288 we know about in the instruction and let the reloc hacking
4290 inst.instruction = (subtract ? 0x8000 : 0) | (Rd << 4) | Rs;
4291 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
4295 int offset = inst.reloc.exp.X_add_number;
4305 /* Quick check, in case offset is MIN_INT. */
4308 inst.error = _("immediate value out of range");
4317 if (offset & ~0x1fc)
4319 inst.error = _("invalid immediate value for stack adjust");
4322 inst.instruction = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
4323 inst.instruction |= offset >> 2;
4325 else if (Rs == REG_PC || Rs == REG_SP)
4328 || (offset & ~0x3fc))
4330 inst.error = _("invalid immediate for address calculation");
4333 inst.instruction = (Rs == REG_PC ? T_OPCODE_ADD_PC
4335 inst.instruction |= (Rd << 8) | (offset >> 2);
4341 inst.error = _("immediate value out of range");
4344 inst.instruction = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
4345 inst.instruction |= (Rd << 8) | offset;
4351 inst.error = _("immediate value out of range");
4354 inst.instruction = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
4355 inst.instruction |= Rd | (Rs << 3) | (offset << 6);
4364 thumb_shift (str, shift)
4368 int Rd, Rs, Rn = FAIL;
4370 skip_whitespace (str);
4372 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4373 || skip_past_comma (&str) == FAIL)
4376 inst.error = BAD_ARGS;
4380 if (is_immediate_prefix (*str))
4382 /* Two operand immediate format, set Rs to Rd. */
4385 if (my_get_expression (&inst.reloc.exp, &str))
4390 if ((Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4393 if (skip_past_comma (&str) == FAIL)
4395 /* Two operand format, shuffle the registers
4396 and pretend there are 3. */
4400 else if (is_immediate_prefix (*str))
4403 if (my_get_expression (&inst.reloc.exp, &str))
4406 else if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4410 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4411 for the latter case, EXPR contains the immediate that was found. */
4417 inst.error = _("source1 and dest must be same register");
4423 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_R; break;
4424 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_R; break;
4425 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_R; break;
4428 inst.instruction |= Rd | (Rn << 3);
4434 case THUMB_ASR: inst.instruction = T_OPCODE_ASR_I; break;
4435 case THUMB_LSL: inst.instruction = T_OPCODE_LSL_I; break;
4436 case THUMB_LSR: inst.instruction = T_OPCODE_LSR_I; break;
4439 if (inst.reloc.exp.X_op != O_constant)
4441 /* Value isn't known yet, create a dummy reloc and let reloc
4442 hacking fix it up. */
4443 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
4447 unsigned shift_value = inst.reloc.exp.X_add_number;
4449 if (shift_value > 32 || (shift_value == 32 && shift == THUMB_LSL))
4451 inst.error = _("Invalid immediate for shift");
4455 /* Shifts of zero are handled by converting to LSL. */
4456 if (shift_value == 0)
4457 inst.instruction = T_OPCODE_LSL_I;
4459 /* Shifts of 32 are encoded as a shift of zero. */
4460 if (shift_value == 32)
4463 inst.instruction |= shift_value << 6;
4466 inst.instruction |= Rd | (Rs << 3);
4473 thumb_mov_compare (str, move)
4479 skip_whitespace (str);
4481 if ((Rd = thumb_reg (&str, THUMB_REG_ANY)) == FAIL
4482 || skip_past_comma (&str) == FAIL)
4485 inst.error = BAD_ARGS;
4489 if (is_immediate_prefix (*str))
4492 if (my_get_expression (&inst.reloc.exp, &str))
4495 else if ((Rs = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4500 if (Rs < 8 && Rd < 8)
4502 if (move == THUMB_MOVE)
4503 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4504 since a MOV instruction produces unpredictable results. */
4505 inst.instruction = T_OPCODE_ADD_I3;
4507 inst.instruction = T_OPCODE_CMP_LR;
4508 inst.instruction |= Rd | (Rs << 3);
4512 if (move == THUMB_MOVE)
4513 inst.instruction = T_OPCODE_MOV_HR;
4515 inst.instruction = T_OPCODE_CMP_HR;
4518 inst.instruction |= THUMB_H1;
4521 inst.instruction |= THUMB_H2;
4523 inst.instruction |= (Rd & 7) | ((Rs & 7) << 3);
4530 inst.error = _("only lo regs allowed with immediate");
4534 if (move == THUMB_MOVE)
4535 inst.instruction = T_OPCODE_MOV_I8;
4537 inst.instruction = T_OPCODE_CMP_I8;
4539 inst.instruction |= Rd << 8;
4541 if (inst.reloc.exp.X_op != O_constant)
4542 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
4545 unsigned value = inst.reloc.exp.X_add_number;
4549 inst.error = _("invalid immediate");
4553 inst.instruction |= value;
4561 thumb_load_store (str, load_store, size)
4566 int Rd, Rb, Ro = FAIL;
4568 skip_whitespace (str);
4570 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4571 || skip_past_comma (&str) == FAIL)
4574 inst.error = BAD_ARGS;
4581 if ((Rb = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4584 if (skip_past_comma (&str) != FAIL)
4586 if (is_immediate_prefix (*str))
4589 if (my_get_expression (&inst.reloc.exp, &str))
4592 else if ((Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4597 inst.reloc.exp.X_op = O_constant;
4598 inst.reloc.exp.X_add_number = 0;
4603 inst.error = _("expected ']'");
4608 else if (*str == '=')
4610 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4613 skip_whitespace (str);
4615 if (my_get_expression (& inst.reloc.exp, & str))
4620 if ( inst.reloc.exp.X_op != O_constant
4621 && inst.reloc.exp.X_op != O_symbol)
4623 inst.error = "Constant expression expected";
4627 if (inst.reloc.exp.X_op == O_constant
4628 && ((inst.reloc.exp.X_add_number & ~0xFF) == 0))
4630 /* This can be done with a mov instruction. */
4632 inst.instruction = T_OPCODE_MOV_I8 | (Rd << 8);
4633 inst.instruction |= inst.reloc.exp.X_add_number;
4637 /* Insert into literal pool. */
4638 if (add_to_lit_pool () == FAIL)
4641 inst.error = "literal pool insertion failed";
4645 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4646 inst.reloc.pc_rel = 1;
4647 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4648 /* Adjust ARM pipeline offset to Thumb. */
4649 inst.reloc.exp.X_add_number += 4;
4655 if (my_get_expression (&inst.reloc.exp, &str))
4658 inst.instruction = T_OPCODE_LDR_PC | (Rd << 8);
4659 inst.reloc.pc_rel = 1;
4660 inst.reloc.exp.X_add_number -= 4; /* Pipeline offset. */
4661 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4666 if (Rb == REG_PC || Rb == REG_SP)
4668 if (size != THUMB_WORD)
4670 inst.error = _("byte or halfword not valid for base register");
4673 else if (Rb == REG_PC && load_store != THUMB_LOAD)
4675 inst.error = _("R15 based store not allowed");
4678 else if (Ro != FAIL)
4680 inst.error = _("Invalid base register for register offset");
4685 inst.instruction = T_OPCODE_LDR_PC;
4686 else if (load_store == THUMB_LOAD)
4687 inst.instruction = T_OPCODE_LDR_SP;
4689 inst.instruction = T_OPCODE_STR_SP;
4691 inst.instruction |= Rd << 8;
4692 if (inst.reloc.exp.X_op == O_constant)
4694 unsigned offset = inst.reloc.exp.X_add_number;
4696 if (offset & ~0x3fc)
4698 inst.error = _("invalid offset");
4702 inst.instruction |= offset >> 2;
4705 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4709 inst.error = _("invalid base register in load/store");
4712 else if (Ro == FAIL)
4714 /* Immediate offset. */
4715 if (size == THUMB_WORD)
4716 inst.instruction = (load_store == THUMB_LOAD
4717 ? T_OPCODE_LDR_IW : T_OPCODE_STR_IW);
4718 else if (size == THUMB_HALFWORD)
4719 inst.instruction = (load_store == THUMB_LOAD
4720 ? T_OPCODE_LDR_IH : T_OPCODE_STR_IH);
4722 inst.instruction = (load_store == THUMB_LOAD
4723 ? T_OPCODE_LDR_IB : T_OPCODE_STR_IB);
4725 inst.instruction |= Rd | (Rb << 3);
4727 if (inst.reloc.exp.X_op == O_constant)
4729 unsigned offset = inst.reloc.exp.X_add_number;
4731 if (offset & ~(0x1f << size))
4733 inst.error = _("Invalid offset");
4736 inst.instruction |= (offset >> size) << 6;
4739 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
4743 /* Register offset. */
4744 if (size == THUMB_WORD)
4745 inst.instruction = (load_store == THUMB_LOAD
4746 ? T_OPCODE_LDR_RW : T_OPCODE_STR_RW);
4747 else if (size == THUMB_HALFWORD)
4748 inst.instruction = (load_store == THUMB_LOAD
4749 ? T_OPCODE_LDR_RH : T_OPCODE_STR_RH);
4751 inst.instruction = (load_store == THUMB_LOAD
4752 ? T_OPCODE_LDR_RB : T_OPCODE_STR_RB);
4754 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
4769 /* Handle the Format 4 instructions that do not have equivalents in other
4770 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4779 skip_whitespace (str);
4781 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
4782 || skip_past_comma (&str) == FAIL
4783 || (Rs = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4785 inst.error = BAD_ARGS;
4789 if (skip_past_comma (&str) != FAIL)
4791 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4792 (It isn't allowed for CMP either, but that isn't handled by this
4794 if (inst.instruction == T_OPCODE_TST
4795 || inst.instruction == T_OPCODE_CMN
4796 || inst.instruction == T_OPCODE_NEG
4797 || inst.instruction == T_OPCODE_MVN)
4799 inst.error = BAD_ARGS;
4803 if ((Rn = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4808 inst.error = _("dest and source1 one must be the same register");
4814 if (inst.instruction == T_OPCODE_MUL
4816 as_tsktsk (_("Rs and Rd must be different in MUL"));
4818 inst.instruction |= Rd | (Rs << 3);
4826 thumb_add_sub (str, 0);
4833 thumb_shift (str, THUMB_ASR);
4840 if (my_get_expression (&inst.reloc.exp, &str))
4842 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
4843 inst.reloc.pc_rel = 1;
4851 if (my_get_expression (&inst.reloc.exp, &str))
4853 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
4854 inst.reloc.pc_rel = 1;
4858 /* Find the real, Thumb encoded start of a Thumb function. */
4861 find_real_start (symbolP)
4865 const char * name = S_GET_NAME (symbolP);
4866 symbolS * new_target;
4868 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
4869 #define STUB_NAME ".real_start_of"
4874 /* Names that start with '.' are local labels, not function entry points.
4875 The compiler may generate BL instructions to these labels because it
4876 needs to perform a branch to a far away location. */
4880 real_start = malloc (strlen (name) + strlen (STUB_NAME) + 1);
4881 sprintf (real_start, "%s%s", STUB_NAME, name);
4883 new_target = symbol_find (real_start);
4885 if (new_target == NULL)
4887 as_warn ("Failed to find real start of function: %s\n", name);
4888 new_target = symbolP;
4900 if (my_get_expression (& inst.reloc.exp, & str))
4903 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
4904 inst.reloc.pc_rel = 1;
4907 /* If the destination of the branch is a defined symbol which does not have
4908 the THUMB_FUNC attribute, then we must be calling a function which has
4909 the (interfacearm) attribute. We look for the Thumb entry point to that
4910 function and change the branch to refer to that function instead. */
4911 if ( inst.reloc.exp.X_op == O_symbol
4912 && inst.reloc.exp.X_add_symbol != NULL
4913 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
4914 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
4915 inst.reloc.exp.X_add_symbol =
4916 find_real_start (inst.reloc.exp.X_add_symbol);
4925 skip_whitespace (str);
4927 if ((reg = thumb_reg (&str, THUMB_REG_ANY)) == FAIL)
4930 /* This sets THUMB_H2 from the top bit of reg. */
4931 inst.instruction |= reg << 3;
4933 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4934 should cause the alignment to be checked once it is known. This is
4935 because BX PC only works if the instruction is word aligned. */
4944 thumb_mov_compare (str, THUMB_COMPARE);
4954 skip_whitespace (str);
4956 if ((Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL)
4960 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4964 if (skip_past_comma (&str) == FAIL
4965 || (range = reg_list (&str)) == FAIL)
4968 inst.error = BAD_ARGS;
4972 if (inst.reloc.type != BFD_RELOC_NONE)
4974 /* This really doesn't seem worth it. */
4975 inst.reloc.type = BFD_RELOC_NONE;
4976 inst.error = _("Expression too complex");
4982 inst.error = _("only lo-regs valid in load/store multiple");
4986 inst.instruction |= (Rb << 8) | range;
4994 thumb_load_store (str, THUMB_LOAD, THUMB_WORD);
5001 thumb_load_store (str, THUMB_LOAD, THUMB_BYTE);
5008 thumb_load_store (str, THUMB_LOAD, THUMB_HALFWORD);
5017 skip_whitespace (str);
5019 if ((Rd = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5020 || skip_past_comma (&str) == FAIL
5022 || (Rb = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5023 || skip_past_comma (&str) == FAIL
5024 || (Ro = thumb_reg (&str, THUMB_REG_LO)) == FAIL
5028 inst.error = _("Syntax: ldrs[b] Rd, [Rb, Ro]");
5032 inst.instruction |= Rd | (Rb << 3) | (Ro << 6);
5040 thumb_shift (str, THUMB_LSL);
5047 thumb_shift (str, THUMB_LSR);
5054 thumb_mov_compare (str, THUMB_MOVE);
5063 skip_whitespace (str);
5065 if ((range = reg_list (&str)) == FAIL)
5068 inst.error = BAD_ARGS;
5072 if (inst.reloc.type != BFD_RELOC_NONE)
5074 /* This really doesn't seem worth it. */
5075 inst.reloc.type = BFD_RELOC_NONE;
5076 inst.error = _("Expression too complex");
5082 if ((inst.instruction == T_OPCODE_PUSH
5083 && (range & ~0xff) == 1 << REG_LR)
5084 || (inst.instruction == T_OPCODE_POP
5085 && (range & ~0xff) == 1 << REG_PC))
5087 inst.instruction |= THUMB_PP_PC_LR;
5092 inst.error = _("invalid register list to push/pop instruction");
5097 inst.instruction |= range;
5105 thumb_load_store (str, THUMB_STORE, THUMB_WORD);
5112 thumb_load_store (str, THUMB_STORE, THUMB_BYTE);
5119 thumb_load_store (str, THUMB_STORE, THUMB_HALFWORD);
5126 thumb_add_sub (str, 1);
5133 skip_whitespace (str);
5135 if (my_get_expression (&inst.reloc.exp, &str))
5138 inst.reloc.type = BFD_RELOC_ARM_SWI;
5149 /* This is a pseudo-op of the form "adr rd, label" to be converted
5150 into a relative address of the form "add rd, pc, #label-.-4". */
5151 skip_whitespace (str);
5153 /* Store Rd in temporary location inside instruction. */
5154 if ((reg = reg_required_here (&str, 4)) == FAIL
5155 || (reg > 7) /* For Thumb reg must be r0..r7. */
5156 || skip_past_comma (&str) == FAIL
5157 || my_get_expression (&inst.reloc.exp, &str))
5160 inst.error = BAD_ARGS;
5164 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
5165 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
5166 inst.reloc.pc_rel = 1;
5167 inst.instruction |= REG_PC; /* Rd is already placed into the instruction. */
5176 int len = strlen (reg_table[entry].name) + 2;
5177 char * buf = (char *) xmalloc (len);
5178 char * buf2 = (char *) xmalloc (len);
5181 #ifdef REGISTER_PREFIX
5182 buf[i++] = REGISTER_PREFIX;
5185 strcpy (buf + i, reg_table[entry].name);
5187 for (i = 0; buf[i]; i++)
5188 buf2[i] = islower (buf[i]) ? toupper (buf[i]) : buf[i];
5192 hash_insert (arm_reg_hsh, buf, (PTR) & reg_table[entry]);
5193 hash_insert (arm_reg_hsh, buf2, (PTR) & reg_table[entry]);
5197 insert_reg_alias (str, regnum)
5201 struct reg_entry *new =
5202 (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
5203 char *name = xmalloc (strlen (str) + 1);
5207 new->number = regnum;
5209 hash_insert (arm_reg_hsh, name, (PTR) new);
5213 set_constant_flonums ()
5217 for (i = 0; i < NUM_FLOAT_VALS; i++)
5218 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
5228 if ( (arm_ops_hsh = hash_new ()) == NULL
5229 || (arm_tops_hsh = hash_new ()) == NULL
5230 || (arm_cond_hsh = hash_new ()) == NULL
5231 || (arm_shift_hsh = hash_new ()) == NULL
5232 || (arm_reg_hsh = hash_new ()) == NULL
5233 || (arm_psr_hsh = hash_new ()) == NULL)
5234 as_fatal (_("Virtual memory exhausted"));
5236 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
5237 hash_insert (arm_ops_hsh, insns[i].template, (PTR) (insns + i));
5238 for (i = 0; i < sizeof (tinsns) / sizeof (struct thumb_opcode); i++)
5239 hash_insert (arm_tops_hsh, tinsns[i].template, (PTR) (tinsns + i));
5240 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
5241 hash_insert (arm_cond_hsh, conds[i].template, (PTR) (conds + i));
5242 for (i = 0; i < sizeof (shift) / sizeof (struct asm_shift); i++)
5243 hash_insert (arm_shift_hsh, shift[i].template, (PTR) (shift + i));
5244 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
5245 hash_insert (arm_psr_hsh, psrs[i].template, (PTR) (psrs + i));
5247 for (i = 0; reg_table[i].name; i++)
5250 set_constant_flonums ();
5252 #if defined OBJ_COFF || defined OBJ_ELF
5254 unsigned int flags = 0;
5256 /* Set the flags in the private structure. */
5257 if (uses_apcs_26) flags |= F_APCS26;
5258 if (support_interwork) flags |= F_INTERWORK;
5259 if (uses_apcs_float) flags |= F_APCS_FLOAT;
5260 if (pic_code) flags |= F_PIC;
5261 if ((cpu_variant & FPU_ALL) == FPU_NONE) flags |= F_SOFT_FLOAT;
5263 bfd_set_private_flags (stdoutput, flags);
5267 /* Record the CPU type as well. */
5268 switch (cpu_variant & ARM_CPU_MASK)
5271 mach = bfd_mach_arm_2;
5274 case ARM_3: /* Also ARM_250. */
5275 mach = bfd_mach_arm_2a;
5279 case ARM_6 | ARM_3 | ARM_2: /* Actually no CPU type defined. */
5280 mach = bfd_mach_arm_4;
5283 case ARM_7: /* Also ARM_6. */
5284 mach = bfd_mach_arm_3;
5288 /* Catch special cases. */
5289 if (cpu_variant != (FPU_DEFAULT | CPU_DEFAULT))
5291 if (cpu_variant & (ARM_EXT_V5 & ARM_THUMB))
5292 mach = bfd_mach_arm_5T;
5293 else if (cpu_variant & ARM_EXT_V5)
5294 mach = bfd_mach_arm_5;
5295 else if (cpu_variant & ARM_THUMB)
5296 mach = bfd_mach_arm_4T;
5297 else if ((cpu_variant & ARM_ARCH_V4) == ARM_ARCH_V4)
5298 mach = bfd_mach_arm_4;
5299 else if (cpu_variant & ARM_LONGMUL)
5300 mach = bfd_mach_arm_3M;
5303 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
5306 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5307 for use in the a.out file, and stores them in the array pointed to by buf.
5308 This knows about the endian-ness of the target machine and does
5309 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5310 2 (short) and 4 (long) Floating numbers are put out as a series of
5311 LITTLENUMS (shorts, here at least). */
5314 md_number_to_chars (buf, val, n)
5319 if (target_big_endian)
5320 number_to_chars_bigendian (buf, val, n);
5322 number_to_chars_littleendian (buf, val, n);
5326 md_chars_to_number (buf, n)
5331 unsigned char * where = (unsigned char *) buf;
5333 if (target_big_endian)
5338 result |= (*where++ & 255);
5346 result |= (where[n] & 255);
5353 /* Turn a string in input_line_pointer into a floating point constant
5354 of type TYPE, and store the appropriate bytes in *LITP. The number
5355 of LITTLENUMS emitted is stored in *SIZEP. An error message is
5356 returned, or NULL on OK.
5358 Note that fp constants aren't represent in the normal way on the ARM.
5359 In big endian mode, things are as expected. However, in little endian
5360 mode fp constants are big-endian word-wise, and little-endian byte-wise
5361 within the words. For example, (double) 1.1 in big endian mode is
5362 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5363 the byte sequence 99 99 f1 3f 9a 99 99 99.
5365 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5368 md_atof (type, litP, sizeP)
5374 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5406 return _("Bad call to MD_ATOF()");
5409 t = atof_ieee (input_line_pointer, type, words);
5411 input_line_pointer = t;
5414 if (target_big_endian)
5416 for (i = 0; i < prec; i++)
5418 md_number_to_chars (litP, (valueT) words[i], 2);
5424 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5425 8 byte float the order is 1 0 3 2. */
5426 for (i = 0; i < prec; i += 2)
5428 md_number_to_chars (litP, (valueT) words[i + 1], 2);
5429 md_number_to_chars (litP + 2, (valueT) words[i], 2);
5437 /* The knowledge of the PC's pipeline offset is built into the insns
5441 md_pcrel_from (fixP)
5445 && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section
5446 && fixP->fx_subsy == NULL)
5449 if (fixP->fx_pcrel && (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_ADD))
5451 /* PC relative addressing on the Thumb is slightly odd
5452 as the bottom two bits of the PC are forced to zero
5453 for the calculation. */
5454 return (fixP->fx_where + fixP->fx_frag->fr_address) & ~3;
5458 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5459 so we un-adjust here to compensate for the accomodation. */
5460 return fixP->fx_where + fixP->fx_frag->fr_address + 8;
5462 return fixP->fx_where + fixP->fx_frag->fr_address;
5466 /* Round up a section size to the appropriate boundary. */
5469 md_section_align (segment, size)
5470 segT segment ATTRIBUTE_UNUSED;
5476 /* Round all sects to multiple of 4. */
5477 return (size + 3) & ~3;
5481 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5482 Otherwise we have no need to default values of symbols. */
5485 md_undefined_symbol (name)
5486 char * name ATTRIBUTE_UNUSED;
5489 if (name[0] == '_' && name[1] == 'G'
5490 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
5494 if (symbol_find (name))
5495 as_bad ("GOT already in the symbol table");
5497 GOT_symbol = symbol_new (name, undefined_section,
5498 (valueT) 0, & zero_address_frag);
5508 /* arm_reg_parse () := if it looks like a register, return its token and
5509 advance the pointer. */
5513 register char ** ccp;
5515 char * start = * ccp;
5518 struct reg_entry * reg;
5520 #ifdef REGISTER_PREFIX
5521 if (*start != REGISTER_PREFIX)
5526 #ifdef OPTIONAL_REGISTER_PREFIX
5527 if (*p == OPTIONAL_REGISTER_PREFIX)
5531 if (!isalpha (*p) || !is_name_beginner (*p))
5535 while (isalpha (c) || isdigit (c) || c == '_')
5539 reg = (struct reg_entry *) hash_find (arm_reg_hsh, start);
5552 md_apply_fix3 (fixP, val, seg)
5557 offsetT value = * val;
5559 unsigned int newimm;
5562 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
5563 arm_fix_data * arm_data = (arm_fix_data *) fixP->tc_fix_data;
5565 assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
5567 /* Note whether this will delete the relocation. */
5569 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
5570 doesn't work fully.) */
5571 if ((fixP->fx_addsy == 0 || symbol_constant_p (fixP->fx_addsy))
5574 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
5578 /* If this symbol is in a different section then we need to leave it for
5579 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5580 so we have to undo it's effects here. */
5583 if (fixP->fx_addsy != NULL
5584 && S_IS_DEFINED (fixP->fx_addsy)
5585 && S_GET_SEGMENT (fixP->fx_addsy) != seg)
5588 && (fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
5589 || fixP->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
5593 value += md_pcrel_from (fixP);
5597 /* Remember value for emit_reloc. */
5598 fixP->fx_addnumber = value;
5600 switch (fixP->fx_r_type)
5602 case BFD_RELOC_ARM_IMMEDIATE:
5603 newimm = validate_immediate (value);
5604 temp = md_chars_to_number (buf, INSN_SIZE);
5606 /* If the instruction will fail, see if we can fix things up by
5607 changing the opcode. */
5608 if (newimm == (unsigned int) FAIL
5609 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
5611 as_bad_where (fixP->fx_file, fixP->fx_line,
5612 _("invalid constant (%lx) after fixup"),
5613 (unsigned long) value);
5617 newimm |= (temp & 0xfffff000);
5618 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5621 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
5623 unsigned int highpart = 0;
5624 unsigned int newinsn = 0xe1a00000; /* nop. */
5625 newimm = validate_immediate (value);
5626 temp = md_chars_to_number (buf, INSN_SIZE);
5628 /* If the instruction will fail, see if we can fix things up by
5629 changing the opcode. */
5630 if (newimm == (unsigned int) FAIL
5631 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
5633 /* No ? OK - try using two ADD instructions to generate
5635 newimm = validate_immediate_twopart (value, & highpart);
5637 /* Yes - then make sure that the second instruction is
5639 if (newimm != (unsigned int) FAIL)
5641 /* Still No ? Try using a negated value. */
5642 else if (validate_immediate_twopart (- value, & highpart) != (unsigned int) FAIL)
5643 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
5644 /* Otherwise - give up. */
5647 as_bad_where (fixP->fx_file, fixP->fx_line,
5648 _("Unable to compute ADRL instructions for PC offset of 0x%x"),
5653 /* Replace the first operand in the 2nd instruction (which
5654 is the PC) with the destination register. We have
5655 already added in the PC in the first instruction and we
5656 do not want to do it again. */
5657 newinsn &= ~0xf0000;
5658 newinsn |= ((newinsn & 0x0f000) << 4);
5661 newimm |= (temp & 0xfffff000);
5662 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
5664 highpart |= (newinsn & 0xfffff000);
5665 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
5669 case BFD_RELOC_ARM_OFFSET_IMM:
5675 if (validate_offset_imm (value, 0) == FAIL)
5677 as_bad_where (fixP->fx_file, fixP->fx_line,
5678 _("bad immediate value for offset (%ld)"),
5683 newval = md_chars_to_number (buf, INSN_SIZE);
5684 newval &= 0xff7ff000;
5685 newval |= value | (sign ? INDEX_UP : 0);
5686 md_number_to_chars (buf, newval, INSN_SIZE);
5689 case BFD_RELOC_ARM_OFFSET_IMM8:
5690 case BFD_RELOC_ARM_HWLITERAL:
5696 if (validate_offset_imm (value, 1) == FAIL)
5698 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
5699 as_bad_where (fixP->fx_file, fixP->fx_line,
5700 _("invalid literal constant: pool needs to be closer"));
5702 as_bad (_("bad immediate value for half-word offset (%ld)"),
5707 newval = md_chars_to_number (buf, INSN_SIZE);
5708 newval &= 0xff7ff0f0;
5709 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
5710 md_number_to_chars (buf, newval, INSN_SIZE);
5713 case BFD_RELOC_ARM_LITERAL:
5719 if (validate_offset_imm (value, 0) == FAIL)
5721 as_bad_where (fixP->fx_file, fixP->fx_line,
5722 _("invalid literal constant: pool needs to be closer"));
5726 newval = md_chars_to_number (buf, INSN_SIZE);
5727 newval &= 0xff7ff000;
5728 newval |= value | (sign ? INDEX_UP : 0);
5729 md_number_to_chars (buf, newval, INSN_SIZE);
5732 case BFD_RELOC_ARM_SHIFT_IMM:
5733 newval = md_chars_to_number (buf, INSN_SIZE);
5734 if (((unsigned long) value) > 32
5736 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
5738 as_bad_where (fixP->fx_file, fixP->fx_line,
5739 _("shift expression is too large"));
5744 /* Shifts of zero must be done as lsl. */
5746 else if (value == 32)
5748 newval &= 0xfffff07f;
5749 newval |= (value & 0x1f) << 7;
5750 md_number_to_chars (buf, newval, INSN_SIZE);
5753 case BFD_RELOC_ARM_SWI:
5754 if (arm_data->thumb_mode)
5756 if (((unsigned long) value) > 0xff)
5757 as_bad_where (fixP->fx_file, fixP->fx_line,
5758 _("Invalid swi expression"));
5759 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xff00;
5761 md_number_to_chars (buf, newval, THUMB_SIZE);
5765 if (((unsigned long) value) > 0x00ffffff)
5766 as_bad_where (fixP->fx_file, fixP->fx_line,
5767 _("Invalid swi expression"));
5768 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff000000;
5770 md_number_to_chars (buf, newval, INSN_SIZE);
5774 case BFD_RELOC_ARM_MULTI:
5775 if (((unsigned long) value) > 0xffff)
5776 as_bad_where (fixP->fx_file, fixP->fx_line,
5777 _("Invalid expression in load/store multiple"));
5778 newval = value | md_chars_to_number (buf, INSN_SIZE);
5779 md_number_to_chars (buf, newval, INSN_SIZE);
5782 case BFD_RELOC_ARM_PCREL_BRANCH:
5783 newval = md_chars_to_number (buf, INSN_SIZE);
5785 /* Sign-extend a 24-bit number. */
5786 #define SEXT24(x) ((((x) & 0xffffff) ^ (~ 0x7fffff)) + 0x800000)
5790 value = fixP->fx_offset;
5793 /* We are going to store value (shifted right by two) in the
5794 instruction, in a 24 bit, signed field. Thus we need to check
5795 that none of the top 8 bits of the shifted value (top 7 bits of
5796 the unshifted, unsigned value) are set, or that they are all set. */
5797 if ((value & ~ ((offsetT) 0x1ffffff)) != 0
5798 && ((value & ~ ((offsetT) 0x1ffffff)) != ~ ((offsetT) 0x1ffffff)))
5801 /* Normally we would be stuck at this point, since we cannot store
5802 the absolute address that is the destination of the branch in the
5803 24 bits of the branch instruction. If however, we happen to know
5804 that the destination of the branch is in the same section as the
5805 branch instruciton itself, then we can compute the relocation for
5806 ourselves and not have to bother the linker with it.
5808 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5809 because I have not worked out how to do this for OBJ_COFF or
5812 && fixP->fx_addsy != NULL
5813 && S_IS_DEFINED (fixP->fx_addsy)
5814 && S_GET_SEGMENT (fixP->fx_addsy) == seg)
5816 /* Get pc relative value to go into the branch. */
5819 /* Permit a backward branch provided that enough bits
5820 are set. Allow a forwards branch, provided that
5821 enough bits are clear. */
5822 if ( (value & ~ ((offsetT) 0x1ffffff)) == ~ ((offsetT) 0x1ffffff)
5823 || (value & ~ ((offsetT) 0x1ffffff)) == 0)
5827 if (! fixP->fx_done)
5829 as_bad_where (fixP->fx_file, fixP->fx_line,
5830 _("gas can't handle same-section branch dest >= 0x04000000"));
5834 value += SEXT24 (newval);
5836 if ( (value & ~ ((offsetT) 0xffffff)) != 0
5837 && ((value & ~ ((offsetT) 0xffffff)) != ~ ((offsetT) 0xffffff)))
5838 as_bad_where (fixP->fx_file, fixP->fx_line,
5839 _("out of range branch"));
5841 newval = (value & 0x00ffffff) | (newval & 0xff000000);
5842 md_number_to_chars (buf, newval, INSN_SIZE);
5845 case BFD_RELOC_ARM_PCREL_BLX:
5848 newval = md_chars_to_number (buf, INSN_SIZE);
5852 value = fixP->fx_offset;
5854 hbit = (value >> 1) & 1;
5855 value = (value >> 2) & 0x00ffffff;
5856 value = (value + (newval & 0x00ffffff)) & 0x00ffffff;
5857 newval = value | (newval & 0xfe000000) | (hbit << 24);
5858 md_number_to_chars (buf, newval, INSN_SIZE);
5862 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
5863 newval = md_chars_to_number (buf, THUMB_SIZE);
5865 addressT diff = (newval & 0xff) << 1;
5870 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
5871 as_bad_where (fixP->fx_file, fixP->fx_line,
5872 _("Branch out of range"));
5873 newval = (newval & 0xff00) | ((value & 0x1ff) >> 1);
5875 md_number_to_chars (buf, newval, THUMB_SIZE);
5878 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
5879 newval = md_chars_to_number (buf, THUMB_SIZE);
5881 addressT diff = (newval & 0x7ff) << 1;
5886 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
5887 as_bad_where (fixP->fx_file, fixP->fx_line,
5888 _("Branch out of range"));
5889 newval = (newval & 0xf800) | ((value & 0xfff) >> 1);
5891 md_number_to_chars (buf, newval, THUMB_SIZE);
5894 case BFD_RELOC_THUMB_PCREL_BLX:
5895 case BFD_RELOC_THUMB_PCREL_BRANCH23:
5900 newval = md_chars_to_number (buf, THUMB_SIZE);
5901 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
5902 diff = ((newval & 0x7ff) << 12) | ((newval2 & 0x7ff) << 1);
5903 if (diff & 0x400000)
5906 value = fixP->fx_offset;
5909 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
5910 as_bad_where (fixP->fx_file, fixP->fx_line,
5911 _("Branch with link out of range"));
5913 newval = (newval & 0xf800) | ((value & 0x7fffff) >> 12);
5914 newval2 = (newval2 & 0xf800) | ((value & 0xfff) >> 1);
5915 md_number_to_chars (buf, newval, THUMB_SIZE);
5916 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
5921 if (fixP->fx_done || fixP->fx_pcrel)
5922 md_number_to_chars (buf, value, 1);
5924 else if (!target_oabi)
5926 value = fixP->fx_offset;
5927 md_number_to_chars (buf, value, 1);
5933 if (fixP->fx_done || fixP->fx_pcrel)
5934 md_number_to_chars (buf, value, 2);
5936 else if (!target_oabi)
5938 value = fixP->fx_offset;
5939 md_number_to_chars (buf, value, 2);
5945 case BFD_RELOC_ARM_GOT32:
5946 case BFD_RELOC_ARM_GOTOFF:
5947 md_number_to_chars (buf, 0, 4);
5953 if (fixP->fx_done || fixP->fx_pcrel)
5954 md_number_to_chars (buf, value, 4);
5956 else if (!target_oabi)
5958 value = fixP->fx_offset;
5959 md_number_to_chars (buf, value, 4);
5965 case BFD_RELOC_ARM_PLT32:
5966 /* It appears the instruction is fully prepared at this point. */
5970 case BFD_RELOC_ARM_GOTPC:
5971 md_number_to_chars (buf, value, 4);
5974 case BFD_RELOC_ARM_CP_OFF_IMM:
5976 if (value < -1023 || value > 1023 || (value & 3))
5977 as_bad_where (fixP->fx_file, fixP->fx_line,
5978 _("Illegal value for co-processor offset"));
5981 newval = md_chars_to_number (buf, INSN_SIZE) & 0xff7fff00;
5982 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
5983 md_number_to_chars (buf, newval, INSN_SIZE);
5986 case BFD_RELOC_ARM_THUMB_OFFSET:
5987 newval = md_chars_to_number (buf, THUMB_SIZE);
5988 /* Exactly what ranges, and where the offset is inserted depends
5989 on the type of instruction, we can establish this from the
5991 switch (newval >> 12)
5993 case 4: /* PC load. */
5994 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
5995 forced to zero for these loads, so we will need to round
5996 up the offset if the instruction address is not word
5997 aligned (since the final address produced must be, and
5998 we can only describe word-aligned immediate offsets). */
6000 if ((fixP->fx_frag->fr_address + fixP->fx_where + value) & 3)
6001 as_bad_where (fixP->fx_file, fixP->fx_line,
6002 _("Invalid offset, target not word aligned (0x%08X)"),
6003 (unsigned int) (fixP->fx_frag->fr_address
6004 + fixP->fx_where + value));
6006 if ((value + 2) & ~0x3fe)
6007 as_bad_where (fixP->fx_file, fixP->fx_line,
6008 _("Invalid offset, value too big (0x%08X)"), value);
6010 /* Round up, since pc will be rounded down. */
6011 newval |= (value + 2) >> 2;
6014 case 9: /* SP load/store. */
6016 as_bad_where (fixP->fx_file, fixP->fx_line,
6017 _("Invalid offset, value too big (0x%08X)"), value);
6018 newval |= value >> 2;
6021 case 6: /* Word load/store. */
6023 as_bad_where (fixP->fx_file, fixP->fx_line,
6024 _("Invalid offset, value too big (0x%08X)"), value);
6025 newval |= value << 4; /* 6 - 2. */
6028 case 7: /* Byte load/store. */
6030 as_bad_where (fixP->fx_file, fixP->fx_line,
6031 _("Invalid offset, value too big (0x%08X)"), value);
6032 newval |= value << 6;
6035 case 8: /* Halfword load/store. */
6037 as_bad_where (fixP->fx_file, fixP->fx_line,
6038 _("Invalid offset, value too big (0x%08X)"), value);
6039 newval |= value << 5; /* 6 - 1. */
6043 as_bad_where (fixP->fx_file, fixP->fx_line,
6044 "Unable to process relocation for thumb opcode: %lx",
6045 (unsigned long) newval);
6048 md_number_to_chars (buf, newval, THUMB_SIZE);
6051 case BFD_RELOC_ARM_THUMB_ADD:
6052 /* This is a complicated relocation, since we use it for all of
6053 the following immediate relocations:
6057 9bit ADD/SUB SP word-aligned
6058 10bit ADD PC/SP word-aligned
6060 The type of instruction being processed is encoded in the
6067 newval = md_chars_to_number (buf, THUMB_SIZE);
6069 int rd = (newval >> 4) & 0xf;
6070 int rs = newval & 0xf;
6071 int subtract = newval & 0x8000;
6076 as_bad_where (fixP->fx_file, fixP->fx_line,
6077 _("Invalid immediate for stack address calculation"));
6078 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
6079 newval |= value >> 2;
6081 else if (rs == REG_PC || rs == REG_SP)
6085 as_bad_where (fixP->fx_file, fixP->fx_line,
6086 _("Invalid immediate for address calculation (value = 0x%08lX)"),
6087 (unsigned long) value);
6088 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
6090 newval |= value >> 2;
6095 as_bad_where (fixP->fx_file, fixP->fx_line,
6096 _("Invalid 8bit immediate"));
6097 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
6098 newval |= (rd << 8) | value;
6103 as_bad_where (fixP->fx_file, fixP->fx_line,
6104 _("Invalid 3bit immediate"));
6105 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
6106 newval |= rd | (rs << 3) | (value << 6);
6109 md_number_to_chars (buf, newval, THUMB_SIZE);
6112 case BFD_RELOC_ARM_THUMB_IMM:
6113 newval = md_chars_to_number (buf, THUMB_SIZE);
6114 switch (newval >> 11)
6116 case 0x04: /* 8bit immediate MOV. */
6117 case 0x05: /* 8bit immediate CMP. */
6118 if (value < 0 || value > 255)
6119 as_bad_where (fixP->fx_file, fixP->fx_line,
6120 _("Invalid immediate: %ld is too large"),
6128 md_number_to_chars (buf, newval, THUMB_SIZE);
6131 case BFD_RELOC_ARM_THUMB_SHIFT:
6132 /* 5bit shift value (0..31). */
6133 if (value < 0 || value > 31)
6134 as_bad_where (fixP->fx_file, fixP->fx_line,
6135 _("Illegal Thumb shift value: %ld"), (long) value);
6136 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf03f;
6137 newval |= value << 6;
6138 md_number_to_chars (buf, newval, THUMB_SIZE);
6141 case BFD_RELOC_VTABLE_INHERIT:
6142 case BFD_RELOC_VTABLE_ENTRY:
6146 case BFD_RELOC_NONE:
6148 as_bad_where (fixP->fx_file, fixP->fx_line,
6149 _("Bad relocation fixup type (%d)"), fixP->fx_r_type);
6155 /* Translate internal representation of relocation info to BFD target
6159 tc_gen_reloc (section, fixp)
6160 asection * section ATTRIBUTE_UNUSED;
6164 bfd_reloc_code_real_type code;
6166 reloc = (arelent *) xmalloc (sizeof (arelent));
6168 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6169 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
6170 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
6172 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
6174 if (fixp->fx_pcrel == 0)
6175 reloc->addend = fixp->fx_offset;
6177 reloc->addend = fixp->fx_offset = reloc->address;
6179 reloc->addend = fixp->fx_offset;
6182 switch (fixp->fx_r_type)
6187 code = BFD_RELOC_8_PCREL;
6194 code = BFD_RELOC_16_PCREL;
6201 code = BFD_RELOC_32_PCREL;
6205 case BFD_RELOC_ARM_PCREL_BRANCH:
6206 case BFD_RELOC_ARM_PCREL_BLX:
6208 case BFD_RELOC_THUMB_PCREL_BRANCH9:
6209 case BFD_RELOC_THUMB_PCREL_BRANCH12:
6210 case BFD_RELOC_THUMB_PCREL_BRANCH23:
6211 case BFD_RELOC_THUMB_PCREL_BLX:
6212 case BFD_RELOC_VTABLE_ENTRY:
6213 case BFD_RELOC_VTABLE_INHERIT:
6214 code = fixp->fx_r_type;
6217 case BFD_RELOC_ARM_LITERAL:
6218 case BFD_RELOC_ARM_HWLITERAL:
6219 /* If this is called then the a literal has been referenced across
6220 a section boundary - possibly due to an implicit dump. */
6221 as_bad_where (fixp->fx_file, fixp->fx_line,
6222 _("Literal referenced across section boundary (Implicit dump?)"));
6226 case BFD_RELOC_ARM_GOT32:
6227 case BFD_RELOC_ARM_GOTOFF:
6228 case BFD_RELOC_ARM_PLT32:
6229 code = fixp->fx_r_type;
6233 case BFD_RELOC_ARM_IMMEDIATE:
6234 as_bad_where (fixp->fx_file, fixp->fx_line,
6235 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6239 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
6240 as_bad_where (fixp->fx_file, fixp->fx_line,
6241 _("ADRL used for a symbol not defined in the same file"),
6245 case BFD_RELOC_ARM_OFFSET_IMM:
6246 as_bad_where (fixp->fx_file, fixp->fx_line,
6247 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6255 switch (fixp->fx_r_type)
6257 case BFD_RELOC_ARM_IMMEDIATE: type = "IMMEDIATE"; break;
6258 case BFD_RELOC_ARM_OFFSET_IMM: type = "OFFSET_IMM"; break;
6259 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
6260 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
6261 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
6262 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
6263 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
6264 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
6265 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
6266 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
6267 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
6268 default: type = _("<unknown>"); break;
6270 as_bad_where (fixp->fx_file, fixp->fx_line,
6271 _("Can not represent %s relocation in this object file format (%d)"),
6272 type, fixp->fx_pcrel);
6278 if (code == BFD_RELOC_32_PCREL
6280 && fixp->fx_addsy == GOT_symbol)
6282 code = BFD_RELOC_ARM_GOTPC;
6283 reloc->addend = fixp->fx_offset = reloc->address;
6287 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6289 if (reloc->howto == NULL)
6291 as_bad_where (fixp->fx_file, fixp->fx_line,
6292 _("Can not represent %s relocation in this object file format"),
6293 bfd_get_reloc_code_name (code));
6297 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6298 vtable entry to be used in the relocation's section offset. */
6299 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6300 reloc->address = fixp->fx_offset;
6306 md_estimate_size_before_relax (fragP, segtype)
6307 fragS * fragP ATTRIBUTE_UNUSED;
6308 segT segtype ATTRIBUTE_UNUSED;
6310 as_fatal (_("md_estimate_size_before_relax\n"));
6315 output_inst PARAMS ((void))
6321 as_bad (inst.error);
6325 to = frag_more (inst.size);
6327 if (thumb_mode && (inst.size > THUMB_SIZE))
6329 assert (inst.size == (2 * THUMB_SIZE));
6330 md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
6331 md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
6333 else if (inst.size > INSN_SIZE)
6335 assert (inst.size == (2 * INSN_SIZE));
6336 md_number_to_chars (to, inst.instruction, INSN_SIZE);
6337 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
6340 md_number_to_chars (to, inst.instruction, inst.size);
6342 if (inst.reloc.type != BFD_RELOC_NONE)
6343 fix_new_arm (frag_now, to - frag_now->fr_literal,
6344 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
6359 /* Align the instruction.
6360 This may not be the right thing to do but ... */
6364 listing_prev_line (); /* Defined in listing.h. */
6366 /* Align the previous label if needed. */
6367 if (last_label_seen != NULL)
6369 symbol_set_frag (last_label_seen, frag_now);
6370 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
6371 S_SET_SEGMENT (last_label_seen, now_seg);
6374 memset (&inst, '\0', sizeof (inst));
6375 inst.reloc.type = BFD_RELOC_NONE;
6377 skip_whitespace (str);
6379 /* Scan up to the end of the op-code, which must end in white space or
6381 for (start = p = str; *p != '\0'; p++)
6387 as_bad (_("No operator -- statement `%s'\n"), str);
6393 CONST struct thumb_opcode * opcode;
6397 opcode = (CONST struct thumb_opcode *) hash_find (arm_tops_hsh, str);
6402 /* Check that this instruction is supported for this CPU. */
6403 if (thumb_mode == 1 && (opcode->variants & cpu_variant) == 0)
6405 as_bad (_("selected processor does not support this opcode"));
6409 inst.instruction = opcode->value;
6410 inst.size = opcode->size;
6411 (*opcode->parms) (p);
6418 CONST struct asm_opcode * opcode;
6419 unsigned long cond_code;
6421 inst.size = INSN_SIZE;
6422 /* P now points to the end of the opcode, probably white space, but we
6423 have to break the opcode up in case it contains condionals and flags;
6424 keep trying with progressively smaller basic instructions until one
6425 matches, or we run out of opcode. */
6426 q = (p - str > LONGEST_INST) ? str + LONGEST_INST : p;
6428 for (; q != str; q--)
6433 opcode = (CONST struct asm_opcode *) hash_find (arm_ops_hsh, str);
6436 if (opcode && opcode->template)
6438 unsigned long flag_bits = 0;
6441 /* Check that this instruction is supported for this CPU. */
6442 if ((opcode->variants & cpu_variant) == 0)
6445 inst.instruction = opcode->value;
6446 if (q == p) /* Just a simple opcode. */
6448 if (opcode->comp_suffix)
6450 if (*opcode->comp_suffix != '\0')
6451 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6452 str, opcode->comp_suffix);
6454 /* Not a conditional instruction. */
6455 (*opcode->parms) (q, 0);
6459 /* A conditional instruction with default condition. */
6460 inst.instruction |= COND_ALWAYS;
6461 (*opcode->parms) (q, 0);
6467 /* Not just a simple opcode. Check if extra is a
6472 CONST struct asm_cond *cond;
6476 cond = (CONST struct asm_cond *) hash_find (arm_cond_hsh, r);
6480 if (cond->value == 0xf0000000)
6482 _("Warning: Use of the 'nv' conditional is deprecated\n"));
6484 cond_code = cond->value;
6488 cond_code = COND_ALWAYS;
6491 cond_code = COND_ALWAYS;
6493 /* Apply the conditional, or complain it's not allowed. */
6494 if (opcode->comp_suffix && *opcode->comp_suffix == '\0')
6496 /* Instruction isn't conditional. */
6497 if (cond_code != COND_ALWAYS)
6499 as_bad (_("Opcode `%s' is unconditional\n"), str);
6504 /* Instruction is conditional: set the condition into it. */
6505 inst.instruction |= cond_code;
6507 /* If there is a compulsory suffix, it should come here
6508 before any optional flags. */
6509 if (opcode->comp_suffix && *opcode->comp_suffix != '\0')
6511 CONST char *s = opcode->comp_suffix;
6523 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6524 str, opcode->comp_suffix);
6531 /* The remainder, if any should now be flags for the instruction;
6532 Scan these checking each one found with the opcode. */
6536 CONST struct asm_flg *flag = opcode->flags;
6545 for (flagno = 0; flag[flagno].template; flagno++)
6547 if (streq (r, flag[flagno].template))
6549 flag_bits |= flag[flagno].set_bits;
6555 if (! flag[flagno].template)
6562 (*opcode->parms) (p, flag_bits);
6572 /* It wasn't an instruction, but it might be a register alias of the form
6575 skip_whitespace (q);
6580 if (*q && !strncmp (q, ".req ", 4))
6583 char * copy_of_str = str;
6587 skip_whitespace (q);
6589 for (r = q; *r != '\0'; r++)
6599 regnum = arm_reg_parse (& q);
6602 reg = arm_reg_parse (& str);
6607 insert_reg_alias (str, regnum);
6609 as_warn (_("register '%s' does not exist\n"), q);
6611 else if (regnum != FAIL)
6614 as_warn (_("ignoring redefinition of register alias '%s'"),
6617 /* Do not warn about redefinitions to the same alias. */
6620 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6624 as_warn (_("ignoring incomplete .req pseuso op"));
6631 as_bad (_("bad instruction `%s'"), start);
6635 Invocation line includes a switch not recognized by the base assembler.
6636 See if it's a processor-specific option. These are:
6637 Cpu variants, the arm part is optional:
6638 -m[arm]1 Currently not supported.
6639 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6640 -m[arm]3 Arm 3 processor
6641 -m[arm]6[xx], Arm 6 processors
6642 -m[arm]7[xx][t][[d]m] Arm 7 processors
6643 -m[arm]8[10] Arm 8 processors
6644 -m[arm]9[20][tdmi] Arm 9 processors
6645 -mstrongarm[110[0]] StrongARM processors
6646 -m[arm]v[2345[t]] Arm architectures
6647 -mall All (except the ARM1)
6649 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6650 -mfpe-old (No float load/store multiples)
6651 -mno-fpu Disable all floating point instructions
6652 Run-time endian selection:
6654 -EL little endian cpu
6655 ARM Procedure Calling Standard:
6656 -mapcs-32 32 bit APCS
6657 -mapcs-26 26 bit APCS
6658 -mapcs-float Pass floats in float regs
6659 -mapcs-reentrant Position independent code
6660 -mthumb-interwork Code supports Arm/Thumb interworking
6661 -moabi Old ELF ABI */
6663 CONST char * md_shortopts = "m:k";
6665 struct option md_longopts[] =
6667 #ifdef ARM_BI_ENDIAN
6668 #define OPTION_EB (OPTION_MD_BASE + 0)
6669 {"EB", no_argument, NULL, OPTION_EB},
6670 #define OPTION_EL (OPTION_MD_BASE + 1)
6671 {"EL", no_argument, NULL, OPTION_EL},
6673 #define OPTION_OABI (OPTION_MD_BASE +2)
6674 {"oabi", no_argument, NULL, OPTION_OABI},
6677 {NULL, no_argument, NULL, 0}
6680 size_t md_longopts_size = sizeof (md_longopts);
6683 md_parse_option (c, arg)
6691 #ifdef ARM_BI_ENDIAN
6693 target_big_endian = 1;
6696 target_big_endian = 0;
6704 if (streq (str, "fpa10"))
6705 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA10;
6706 else if (streq (str, "fpa11"))
6707 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_FPA11;
6708 else if (streq (str, "fpe-old"))
6709 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_CORE;
6715 if (streq (str, "no-fpu"))
6716 cpu_variant &= ~FPU_ALL;
6721 if (streq (str, "oabi"))
6727 /* Limit assembler to generating only Thumb instructions: */
6728 if (streq (str, "thumb"))
6730 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_THUMB;
6731 cpu_variant = (cpu_variant & ~FPU_ALL) | FPU_NONE;
6734 else if (streq (str, "thumb-interwork"))
6736 if ((cpu_variant & ARM_THUMB) == 0)
6737 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4T;
6738 #if defined OBJ_COFF || defined OBJ_ELF
6739 support_interwork = true;
6747 if (streq (str, "all"))
6749 cpu_variant = ARM_ALL | FPU_ALL;
6752 #if defined OBJ_COFF || defined OBJ_ELF
6753 if (! strncmp (str, "apcs-", 5))
6755 /* GCC passes on all command line options starting "-mapcs-..."
6756 to us, so we must parse them here. */
6760 if (streq (str, "32"))
6762 uses_apcs_26 = false;
6765 else if (streq (str, "26"))
6767 uses_apcs_26 = true;
6770 else if (streq (str, "frame"))
6772 /* Stack frames are being generated - does not affect
6776 else if (streq (str, "stack-check"))
6778 /* Stack checking is being performed - does not affect
6779 linkage, but does require that the functions
6780 __rt_stkovf_split_small and __rt_stkovf_split_big be
6781 present in the final link. */
6785 else if (streq (str, "float"))
6787 /* Floating point arguments are being passed in the floating
6788 point registers. This does affect linking, since this
6789 version of the APCS is incompatible with the version that
6790 passes floating points in the integer registers. */
6792 uses_apcs_float = true;
6795 else if (streq (str, "reentrant"))
6797 /* Reentrant code has been generated. This does affect
6798 linking, since there is no point in linking reentrant/
6799 position independent code with absolute position code. */
6804 as_bad (_("Unrecognised APCS switch -m%s"), arg);
6808 /* Strip off optional "arm". */
6809 if (! strncmp (str, "arm", 3))
6815 if (streq (str, "1"))
6816 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_1;
6822 if (streq (str, "2"))
6823 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6824 else if (streq (str, "250"))
6825 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_250;
6831 if (streq (str, "3"))
6832 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6838 switch (strtol (str, NULL, 10))
6845 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_6;
6853 /* Eat the processor name. */
6854 switch (strtol (str, & str, 10))
6867 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6873 cpu_variant |= (ARM_THUMB | ARM_ARCH_V4);
6877 cpu_variant |= ARM_LONGMUL;
6880 case 'f': /* fe => fp enabled cpu. */
6886 case 'c': /* Left over from 710c processor name. */
6887 case 'd': /* Debug. */
6888 case 'i': /* Embedded ICE. */
6889 /* Included for completeness in ARM processor naming. */
6899 if (streq (str, "8") || streq (str, "810"))
6900 cpu_variant = (cpu_variant & ~ARM_ANY)
6901 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6907 if (streq (str, "9"))
6908 cpu_variant = (cpu_variant & ~ARM_ANY)
6909 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6910 else if (streq (str, "920"))
6911 cpu_variant = (cpu_variant & ~ARM_ANY)
6912 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL;
6913 else if (streq (str, "920t"))
6914 cpu_variant = (cpu_variant & ~ARM_ANY)
6915 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6916 else if (streq (str, "9tdmi"))
6917 cpu_variant = (cpu_variant & ~ARM_ANY)
6918 | ARM_9 | ARM_ARCH_V4 | ARM_LONGMUL | ARM_THUMB;
6924 if (streq (str, "strongarm")
6925 || streq (str, "strongarm110")
6926 || streq (str, "strongarm1100"))
6927 cpu_variant = (cpu_variant & ~ARM_ANY)
6928 | ARM_8 | ARM_ARCH_V4 | ARM_LONGMUL;
6934 /* Select variant based on architecture rather than
6942 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_3;
6945 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_2;
6948 as_bad (_("Invalid architecture variant -m%s"), arg);
6954 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_7;
6958 case 'm': cpu_variant |= ARM_LONGMUL; break;
6961 as_bad (_("Invalid architecture variant -m%s"), arg);
6967 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V4;
6971 case 't': cpu_variant |= ARM_THUMB; break;
6974 as_bad (_("Invalid architecture variant -m%s"), arg);
6980 cpu_variant = (cpu_variant & ~ARM_ANY) | ARM_ARCH_V5;
6983 case 't': cpu_variant |= ARM_THUMB; break;
6986 as_bad (_("Invalid architecture variant -m%s"), arg);
6992 as_bad (_("Invalid architecture variant -m%s"), arg);
6999 as_bad (_("Invalid processor variant -m%s"), arg);
7005 #if defined OBJ_ELF || defined OBJ_COFF
7023 ARM Specific Assembler Options:\n\
7024 -m[arm][<processor name>] select processor variant\n\
7025 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
7026 -mthumb only allow Thumb instructions\n\
7027 -mthumb-interwork mark the assembled code as supporting interworking\n\
7028 -mall allow any instruction\n\
7029 -mfpa10, -mfpa11 select floating point architecture\n\
7030 -mfpe-old don't allow floating-point multiple instructions\n\
7031 -mno-fpu don't allow any floating-point instructions.\n\
7032 -k generate PIC code.\n"));
7033 #if defined OBJ_COFF || defined OBJ_ELF
7035 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
7036 -mapcs-float floating point args are passed in FP regs\n\
7037 -mapcs-reentrant the code is position independent/reentrant\n"));
7041 -moabi support the old ELF ABI\n"));
7043 #ifdef ARM_BI_ENDIAN
7045 -EB assemble code for a big endian cpu\n\
7046 -EL assemble code for a little endian cpu\n"));
7050 /* We need to be able to fix up arbitrary expressions in some statements.
7051 This is so that we can handle symbols that are an arbitrary distance from
7052 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7053 which returns part of an address in a form which will be valid for
7054 a data instruction. We do this by pushing the expression into a symbol
7055 in the expr_section, and creating a fix for that. */
7058 fix_new_arm (frag, where, size, exp, pc_rel, reloc)
7067 arm_fix_data * arm_data;
7075 new_fix = fix_new_exp (frag, where, size, exp, pc_rel, reloc);
7079 new_fix = fix_new (frag, where, size, make_expr_symbol (exp), 0,
7084 /* Mark whether the fix is to a THUMB instruction, or an ARM
7086 arm_data = (arm_fix_data *) obstack_alloc (& notes, sizeof (arm_fix_data));
7087 new_fix->tc_fix_data = (PTR) arm_data;
7088 arm_data->thumb_mode = thumb_mode;
7093 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7096 cons_fix_new_arm (frag, where, size, exp)
7102 bfd_reloc_code_real_type type;
7106 FIXME: @@ Should look at CPU word size. */
7113 type = BFD_RELOC_16;
7117 type = BFD_RELOC_32;
7120 type = BFD_RELOC_64;
7124 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
7127 /* A good place to do this, although this was probably not intended
7128 for this kind of use. We need to dump the literal pool before
7129 references are made to a null symbol pointer. */
7134 if (current_poolP == NULL)
7137 /* Put it at the end of text section. */
7138 subseg_set (text_section, 0);
7140 listing_prev_line ();
7144 arm_start_line_hook ()
7146 last_label_seen = NULL;
7150 arm_frob_label (sym)
7153 last_label_seen = sym;
7155 ARM_SET_THUMB (sym, thumb_mode);
7157 #if defined OBJ_COFF || defined OBJ_ELF
7158 ARM_SET_INTERWORK (sym, support_interwork);
7161 if (label_is_thumb_function_name)
7163 /* When the address of a Thumb function is taken the bottom
7164 bit of that address should be set. This will allow
7165 interworking between Arm and Thumb functions to work
7168 THUMB_SET_FUNC (sym, 1);
7170 label_is_thumb_function_name = false;
7174 /* Adjust the symbol table. This marks Thumb symbols as distinct from
7178 arm_adjust_symtab ()
7183 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7185 if (ARM_IS_THUMB (sym))
7187 if (THUMB_IS_FUNC (sym))
7189 /* Mark the symbol as a Thumb function. */
7190 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
7191 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
7192 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
7194 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
7195 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
7197 as_bad (_("%s: unexpected function type: %d"),
7198 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
7200 else switch (S_GET_STORAGE_CLASS (sym))
7203 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
7206 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
7209 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
7217 if (ARM_IS_INTERWORK (sym))
7218 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
7225 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
7227 if (ARM_IS_THUMB (sym))
7229 elf_symbol_type *elf_sym;
7231 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
7232 bind = ELF_ST_BIND (elf_sym);
7234 /* If it's a .thumb_func, declare it as so,
7235 otherwise tag label as .code 16. */
7236 if (THUMB_IS_FUNC (sym))
7237 elf_sym->internal_elf_sym.st_info =
7238 ELF_ST_INFO (bind, STT_ARM_TFUNC);
7240 elf_sym->internal_elf_sym.st_info =
7241 ELF_ST_INFO (bind, STT_ARM_16BIT);
7250 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
7252 *input_line_pointer = '/';
7253 input_line_pointer += 5;
7254 *input_line_pointer = 0;
7262 arm_canonicalize_symbol_name (name)
7267 if (thumb_mode && (len = strlen (name)) > 5
7268 && streq (name + len - 5, "/data"))
7269 *(name + len - 5) = 0;
7275 arm_validate_fix (fixP)
7278 /* If the destination of the branch is a defined symbol which does not have
7279 the THUMB_FUNC attribute, then we must be calling a function which has
7280 the (interfacearm) attribute. We look for the Thumb entry point to that
7281 function and change the branch to refer to that function instead. */
7282 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
7283 && fixP->fx_addsy != NULL
7284 && S_IS_DEFINED (fixP->fx_addsy)
7285 && ! THUMB_IS_FUNC (fixP->fx_addsy))
7287 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
7295 /* Relocations against Thumb function names must be left unadjusted,
7296 so that the linker can use this information to correctly set the
7297 bottom bit of their addresses. The MIPS version of this function
7298 also prevents relocations that are mips-16 specific, but I do not
7299 know why it does this.
7302 There is one other problem that ought to be addressed here, but
7303 which currently is not: Taking the address of a label (rather
7304 than a function) and then later jumping to that address. Such
7305 addresses also ought to have their bottom bit set (assuming that
7306 they reside in Thumb code), but at the moment they will not. */
7309 arm_fix_adjustable (fixP)
7312 if (fixP->fx_addsy == NULL)
7315 /* Prevent all adjustments to global symbols. */
7316 if (S_IS_EXTERN (fixP->fx_addsy))
7319 if (S_IS_WEAK (fixP->fx_addsy))
7322 if (THUMB_IS_FUNC (fixP->fx_addsy)
7323 && fixP->fx_subsy == NULL)
7326 /* We need the symbol name for the VTABLE entries. */
7327 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7328 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7335 elf32_arm_target_format ()
7337 if (target_big_endian)
7340 return "elf32-bigarm-oabi";
7342 return "elf32-bigarm";
7347 return "elf32-littlearm-oabi";
7349 return "elf32-littlearm";
7354 armelf_frob_symbol (symp, puntp)
7358 elf_frob_symbol (symp, puntp);
7362 arm_force_relocation (fixp)
7365 if ( fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
7366 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY
7367 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BRANCH
7368 || fixp->fx_r_type == BFD_RELOC_ARM_PCREL_BLX
7369 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX
7370 || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23)
7376 static bfd_reloc_code_real_type
7386 bfd_reloc_code_real_type reloc;
7390 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7391 MAP ("(got)", BFD_RELOC_ARM_GOT32),
7392 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF),
7393 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
7394 branch instructions generated by GCC for PLT relocs. */
7395 MAP ("(plt)", BFD_RELOC_ARM_PLT32),
7396 { NULL, 0, BFD_RELOC_UNUSED }
7400 for (i = 0, ip = input_line_pointer;
7401 i < sizeof (id) && (isalnum (*ip) || ispunct (*ip));
7403 id[i] = tolower (*ip);
7405 for (i = 0; reloc_map[i].str; i++)
7406 if (strncmp (id, reloc_map[i].str, reloc_map[i].len) == 0)
7409 input_line_pointer += reloc_map[i].len;
7411 return reloc_map[i].reloc;
7415 s_arm_elf_cons (nbytes)
7420 #ifdef md_flush_pending_output
7421 md_flush_pending_output ();
7424 if (is_it_end_of_statement ())
7426 demand_empty_rest_of_line ();
7430 #ifdef md_cons_align
7431 md_cons_align (nbytes);
7436 bfd_reloc_code_real_type reloc;
7440 if (exp.X_op == O_symbol
7441 && *input_line_pointer == '('
7442 && (reloc = arm_parse_reloc ()) != BFD_RELOC_UNUSED)
7444 reloc_howto_type *howto = bfd_reloc_type_lookup (stdoutput, reloc);
7445 int size = bfd_get_reloc_size (howto);
7448 as_bad ("%s relocations do not fit in %d bytes",
7449 howto->name, nbytes);
7452 register char *p = frag_more ((int) nbytes);
7453 int offset = nbytes - size;
7455 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7460 emit_expr (&exp, (unsigned int) nbytes);
7462 while (*input_line_pointer++ == ',');
7464 /* Put terminator back into stream. */
7465 input_line_pointer --;
7466 demand_empty_rest_of_line ();
7469 #endif /* OBJ_ELF */