1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994-2013 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
141 /* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
144 static const arm_feature_set *legacy_cpu = NULL;
145 static const arm_feature_set *legacy_fpu = NULL;
147 static const arm_feature_set *mcpu_cpu_opt = NULL;
148 static const arm_feature_set *mcpu_fpu_opt = NULL;
149 static const arm_feature_set *march_cpu_opt = NULL;
150 static const arm_feature_set *march_fpu_opt = NULL;
151 static const arm_feature_set *mfpu_opt = NULL;
152 static const arm_feature_set *object_arch = NULL;
154 /* Constants for known architecture features. */
155 static const arm_feature_set fpu_default = FPU_DEFAULT;
156 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
158 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
160 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166 static const arm_feature_set cpu_default = CPU_DEFAULT;
169 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177 static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
185 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
186 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
187 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
188 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
189 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
191 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
195 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
196 static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
197 static const arm_feature_set arm_ext_m =
198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
199 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
200 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
201 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
202 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
203 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
205 static const arm_feature_set arm_arch_any = ARM_ANY;
206 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
209 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
211 static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
213 static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215 static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217 static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221 static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
225 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
226 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
227 static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
229 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
232 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237 static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239 static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
241 static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
244 static int mfloat_abi_opt = -1;
245 /* Record user cpu selection for object attributes. */
246 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
247 /* Must be long enough to hold any of the names in arm_cpus. */
248 static char selected_cpu_name[16];
250 /* Return if no cpu was selected on command-line. */
252 no_cpu_selected (void)
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
260 static int meabi_flags = EABI_DEFAULT;
262 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
265 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
275 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
276 symbolS * GOT_symbol;
279 /* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
283 static int thumb_mode = 0;
284 /* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287 #define MODE_RECORDED (1 << 4)
289 /* Specifies the intrinsic IT insn behavior mode. */
290 enum implicit_it_mode
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
297 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
299 /* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
311 Important differences from the old Thumb mode:
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
322 static bfd_boolean unified_syntax = FALSE;
324 /* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
326 before a [, which can appear as the first operand for pld. */
327 const char arm_symbol_chars[] = "#[]";
342 enum neon_el_type type;
346 #define NEON_MAX_TYPE_ELS 4
350 struct neon_type_el el[NEON_MAX_TYPE_ELS];
354 enum it_instruction_type
359 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
360 if inside, should be the last one. */
361 NEUTRAL_IT_INSN, /* This could be either inside or outside,
362 i.e. BKPT and NOP. */
363 IT_INSN /* The IT insn has been parsed. */
366 /* The maximum number of operands we need. */
367 #define ARM_IT_MAX_OPERANDS 6
372 unsigned long instruction;
376 /* "uncond_value" is set to the value in place of the conditional field in
377 unconditional versions of the instruction, or -1 if nothing is
380 struct neon_type vectype;
381 /* This does not indicate an actual NEON instruction, only that
382 the mnemonic accepts neon-style type suffixes. */
384 /* Set to the opcode if the instruction needs relaxation.
385 Zero if the instruction is not relaxed. */
389 bfd_reloc_code_real_type type;
394 enum it_instruction_type it_insn_type;
400 struct neon_type_el vectype;
401 unsigned present : 1; /* Operand present. */
402 unsigned isreg : 1; /* Operand was a register. */
403 unsigned immisreg : 1; /* .imm field is a second register. */
404 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
405 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
406 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
407 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
408 instructions. This allows us to disambiguate ARM <-> vector insns. */
409 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
410 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
411 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
412 unsigned issingle : 1; /* Operand is VFP single-precision register. */
413 unsigned hasreloc : 1; /* Operand has relocation suffix. */
414 unsigned writeback : 1; /* Operand has trailing ! */
415 unsigned preind : 1; /* Preindexed address. */
416 unsigned postind : 1; /* Postindexed address. */
417 unsigned negative : 1; /* Index register was negated. */
418 unsigned shifted : 1; /* Shift applied to operation. */
419 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
420 } operands[ARM_IT_MAX_OPERANDS];
423 static struct arm_it inst;
425 #define NUM_FLOAT_VALS 8
427 const char * fp_const[] =
429 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
432 /* Number of littlenums required to hold an extended precision number. */
433 #define MAX_LITTLENUMS 6
435 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
445 #define CP_T_X 0x00008000
446 #define CP_T_Y 0x00400000
448 #define CONDS_BIT 0x00100000
449 #define LOAD_BIT 0x00100000
451 #define DOUBLE_LOAD_FLAG 0x00000001
455 const char * template_name;
459 #define COND_ALWAYS 0xE
463 const char * template_name;
467 struct asm_barrier_opt
469 const char * template_name;
471 const arm_feature_set arch;
474 /* The bit that distinguishes CPSR and SPSR. */
475 #define SPSR_BIT (1 << 22)
477 /* The individual PSR flag bits. */
478 #define PSR_c (1 << 16)
479 #define PSR_x (1 << 17)
480 #define PSR_s (1 << 18)
481 #define PSR_f (1 << 19)
486 bfd_reloc_code_real_type reloc;
491 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
492 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
497 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
500 /* Bits for DEFINED field in neon_typed_alias. */
501 #define NTA_HASTYPE 1
502 #define NTA_HASINDEX 2
504 struct neon_typed_alias
506 unsigned char defined;
508 struct neon_type_el eltype;
511 /* ARM register categories. This includes coprocessor numbers and various
512 architecture extensions' registers. */
539 /* Structure for a hash table entry for a register.
540 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
541 information which states whether a vector type or index is specified (for a
542 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
548 unsigned char builtin;
549 struct neon_typed_alias * neon;
552 /* Diagnostics used when we don't get a register of the expected type. */
553 const char * const reg_expected_msgs[] =
555 N_("ARM register expected"),
556 N_("bad or missing co-processor number"),
557 N_("co-processor register expected"),
558 N_("FPA register expected"),
559 N_("VFP single precision register expected"),
560 N_("VFP/Neon double precision register expected"),
561 N_("Neon quad precision register expected"),
562 N_("VFP single or double precision register expected"),
563 N_("Neon double or quad precision register expected"),
564 N_("VFP single, double or Neon quad precision register expected"),
565 N_("VFP system register expected"),
566 N_("Maverick MVF register expected"),
567 N_("Maverick MVD register expected"),
568 N_("Maverick MVFX register expected"),
569 N_("Maverick MVDX register expected"),
570 N_("Maverick MVAX register expected"),
571 N_("Maverick DSPSC register expected"),
572 N_("iWMMXt data register expected"),
573 N_("iWMMXt control register expected"),
574 N_("iWMMXt scalar register expected"),
575 N_("XScale accumulator register expected"),
578 /* Some well known registers that we refer to directly elsewhere. */
584 /* ARM instructions take 4bytes in the object file, Thumb instructions
590 /* Basic string to match. */
591 const char * template_name;
593 /* Parameters to instruction. */
594 unsigned int operands[8];
596 /* Conditional tag - see opcode_lookup. */
597 unsigned int tag : 4;
599 /* Basic instruction code. */
600 unsigned int avalue : 28;
602 /* Thumb-format instruction code. */
605 /* Which architecture variant provides this instruction. */
606 const arm_feature_set * avariant;
607 const arm_feature_set * tvariant;
609 /* Function to call to encode instruction in ARM format. */
610 void (* aencode) (void);
612 /* Function to call to encode instruction in Thumb format. */
613 void (* tencode) (void);
616 /* Defines for various bits that we will want to toggle. */
617 #define INST_IMMEDIATE 0x02000000
618 #define OFFSET_REG 0x02000000
619 #define HWOFFSET_IMM 0x00400000
620 #define SHIFT_BY_REG 0x00000010
621 #define PRE_INDEX 0x01000000
622 #define INDEX_UP 0x00800000
623 #define WRITE_BACK 0x00200000
624 #define LDM_TYPE_2_OR_3 0x00400000
625 #define CPSI_MMOD 0x00020000
627 #define LITERAL_MASK 0xf000f000
628 #define OPCODE_MASK 0xfe1fffff
629 #define V4_STR_BIT 0x00000020
631 #define T2_SUBS_PC_LR 0xf3de8f00
633 #define DATA_OP_SHIFT 21
635 #define T2_OPCODE_MASK 0xfe1fffff
636 #define T2_DATA_OP_SHIFT 21
638 #define A_COND_MASK 0xf0000000
639 #define A_PUSH_POP_OP_MASK 0x0fff0000
641 /* Opcodes for pushing/poping registers to/from the stack. */
642 #define A1_OPCODE_PUSH 0x092d0000
643 #define A2_OPCODE_PUSH 0x052d0004
644 #define A2_OPCODE_POP 0x049d0004
646 /* Codes to distinguish the arithmetic instructions. */
657 #define OPCODE_CMP 10
658 #define OPCODE_CMN 11
659 #define OPCODE_ORR 12
660 #define OPCODE_MOV 13
661 #define OPCODE_BIC 14
662 #define OPCODE_MVN 15
664 #define T2_OPCODE_AND 0
665 #define T2_OPCODE_BIC 1
666 #define T2_OPCODE_ORR 2
667 #define T2_OPCODE_ORN 3
668 #define T2_OPCODE_EOR 4
669 #define T2_OPCODE_ADD 8
670 #define T2_OPCODE_ADC 10
671 #define T2_OPCODE_SBC 11
672 #define T2_OPCODE_SUB 13
673 #define T2_OPCODE_RSB 14
675 #define T_OPCODE_MUL 0x4340
676 #define T_OPCODE_TST 0x4200
677 #define T_OPCODE_CMN 0x42c0
678 #define T_OPCODE_NEG 0x4240
679 #define T_OPCODE_MVN 0x43c0
681 #define T_OPCODE_ADD_R3 0x1800
682 #define T_OPCODE_SUB_R3 0x1a00
683 #define T_OPCODE_ADD_HI 0x4400
684 #define T_OPCODE_ADD_ST 0xb000
685 #define T_OPCODE_SUB_ST 0xb080
686 #define T_OPCODE_ADD_SP 0xa800
687 #define T_OPCODE_ADD_PC 0xa000
688 #define T_OPCODE_ADD_I8 0x3000
689 #define T_OPCODE_SUB_I8 0x3800
690 #define T_OPCODE_ADD_I3 0x1c00
691 #define T_OPCODE_SUB_I3 0x1e00
693 #define T_OPCODE_ASR_R 0x4100
694 #define T_OPCODE_LSL_R 0x4080
695 #define T_OPCODE_LSR_R 0x40c0
696 #define T_OPCODE_ROR_R 0x41c0
697 #define T_OPCODE_ASR_I 0x1000
698 #define T_OPCODE_LSL_I 0x0000
699 #define T_OPCODE_LSR_I 0x0800
701 #define T_OPCODE_MOV_I8 0x2000
702 #define T_OPCODE_CMP_I8 0x2800
703 #define T_OPCODE_CMP_LR 0x4280
704 #define T_OPCODE_MOV_HR 0x4600
705 #define T_OPCODE_CMP_HR 0x4500
707 #define T_OPCODE_LDR_PC 0x4800
708 #define T_OPCODE_LDR_SP 0x9800
709 #define T_OPCODE_STR_SP 0x9000
710 #define T_OPCODE_LDR_IW 0x6800
711 #define T_OPCODE_STR_IW 0x6000
712 #define T_OPCODE_LDR_IH 0x8800
713 #define T_OPCODE_STR_IH 0x8000
714 #define T_OPCODE_LDR_IB 0x7800
715 #define T_OPCODE_STR_IB 0x7000
716 #define T_OPCODE_LDR_RW 0x5800
717 #define T_OPCODE_STR_RW 0x5000
718 #define T_OPCODE_LDR_RH 0x5a00
719 #define T_OPCODE_STR_RH 0x5200
720 #define T_OPCODE_LDR_RB 0x5c00
721 #define T_OPCODE_STR_RB 0x5400
723 #define T_OPCODE_PUSH 0xb400
724 #define T_OPCODE_POP 0xbc00
726 #define T_OPCODE_BRANCH 0xe000
728 #define THUMB_SIZE 2 /* Size of thumb instruction. */
729 #define THUMB_PP_PC_LR 0x0100
730 #define THUMB_LOAD_BIT 0x0800
731 #define THUMB2_LOAD_BIT 0x00100000
733 #define BAD_ARGS _("bad arguments to instruction")
734 #define BAD_SP _("r13 not allowed here")
735 #define BAD_PC _("r15 not allowed here")
736 #define BAD_COND _("instruction cannot be conditional")
737 #define BAD_OVERLAP _("registers may not be the same")
738 #define BAD_HIREG _("lo register required")
739 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
740 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
741 #define BAD_BRANCH _("branch must be last instruction in IT block")
742 #define BAD_NOT_IT _("instruction not allowed in IT block")
743 #define BAD_FPU _("selected FPU does not support instruction")
744 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
745 #define BAD_IT_COND _("incorrect condition in IT block")
746 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
747 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
748 #define BAD_PC_ADDRESSING \
749 _("cannot use register index with PC-relative addressing")
750 #define BAD_PC_WRITEBACK \
751 _("cannot use writeback with PC-relative addressing")
752 #define BAD_RANGE _("branch out of range")
753 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
755 static struct hash_control * arm_ops_hsh;
756 static struct hash_control * arm_cond_hsh;
757 static struct hash_control * arm_shift_hsh;
758 static struct hash_control * arm_psr_hsh;
759 static struct hash_control * arm_v7m_psr_hsh;
760 static struct hash_control * arm_reg_hsh;
761 static struct hash_control * arm_reloc_hsh;
762 static struct hash_control * arm_barrier_opt_hsh;
764 /* Stuff needed to resolve the label ambiguity
773 symbolS * last_label_seen;
774 static int label_is_thumb_function_name = FALSE;
776 /* Literal pool structure. Held on a per-section
777 and per-sub-section basis. */
779 #define MAX_LITERAL_POOL_SIZE 1024
780 typedef struct literal_pool
782 expressionS literals [MAX_LITERAL_POOL_SIZE];
783 unsigned int next_free_entry;
789 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
791 struct literal_pool * next;
794 /* Pointer to a linked list of literal pools. */
795 literal_pool * list_of_pools = NULL;
798 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
800 static struct current_it now_it;
804 now_it_compatible (int cond)
806 return (cond & ~1) == (now_it.cc & ~1);
810 conditional_insn (void)
812 return inst.cond != COND_ALWAYS;
815 static int in_it_block (void);
817 static int handle_it_state (void);
819 static void force_automatic_it_block_close (void);
821 static void it_fsm_post_encode (void);
823 #define set_it_insn_type(type) \
826 inst.it_insn_type = type; \
827 if (handle_it_state () == FAIL) \
832 #define set_it_insn_type_nonvoid(type, failret) \
835 inst.it_insn_type = type; \
836 if (handle_it_state () == FAIL) \
841 #define set_it_insn_type_last() \
844 if (inst.cond == COND_ALWAYS) \
845 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
847 set_it_insn_type (INSIDE_IT_LAST_INSN); \
853 /* This array holds the chars that always start a comment. If the
854 pre-processor is disabled, these aren't very useful. */
855 const char comment_chars[] = "@";
857 /* This array holds the chars that only start a comment at the beginning of
858 a line. If the line seems to have the form '# 123 filename'
859 .line and .file directives will appear in the pre-processed output. */
860 /* Note that input_file.c hand checks for '#' at the beginning of the
861 first line of the input file. This is because the compiler outputs
862 #NO_APP at the beginning of its output. */
863 /* Also note that comments like this one will always work. */
864 const char line_comment_chars[] = "#";
866 const char line_separator_chars[] = ";";
868 /* Chars that can be used to separate mant
869 from exp in floating point numbers. */
870 const char EXP_CHARS[] = "eE";
872 /* Chars that mean this number is a floating point constant. */
876 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
878 /* Prefix characters that indicate the start of an immediate
880 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
882 /* Separator character handling. */
884 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
887 skip_past_char (char ** str, char c)
889 /* PR gas/14987: Allow for whitespace before the expected character. */
890 skip_whitespace (*str);
901 #define skip_past_comma(str) skip_past_char (str, ',')
903 /* Arithmetic expressions (possibly involving symbols). */
905 /* Return TRUE if anything in the expression is a bignum. */
908 walk_no_bignums (symbolS * sp)
910 if (symbol_get_value_expression (sp)->X_op == O_big)
913 if (symbol_get_value_expression (sp)->X_add_symbol)
915 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
916 || (symbol_get_value_expression (sp)->X_op_symbol
917 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
923 static int in_my_get_expression = 0;
925 /* Third argument to my_get_expression. */
926 #define GE_NO_PREFIX 0
927 #define GE_IMM_PREFIX 1
928 #define GE_OPT_PREFIX 2
929 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
930 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
931 #define GE_OPT_PREFIX_BIG 3
934 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
939 /* In unified syntax, all prefixes are optional. */
941 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
946 case GE_NO_PREFIX: break;
948 if (!is_immediate_prefix (**str))
950 inst.error = _("immediate expression requires a # prefix");
956 case GE_OPT_PREFIX_BIG:
957 if (is_immediate_prefix (**str))
963 memset (ep, 0, sizeof (expressionS));
965 save_in = input_line_pointer;
966 input_line_pointer = *str;
967 in_my_get_expression = 1;
968 seg = expression (ep);
969 in_my_get_expression = 0;
971 if (ep->X_op == O_illegal || ep->X_op == O_absent)
973 /* We found a bad or missing expression in md_operand(). */
974 *str = input_line_pointer;
975 input_line_pointer = save_in;
976 if (inst.error == NULL)
977 inst.error = (ep->X_op == O_absent
978 ? _("missing expression") :_("bad expression"));
983 if (seg != absolute_section
984 && seg != text_section
985 && seg != data_section
986 && seg != bss_section
987 && seg != undefined_section)
989 inst.error = _("bad segment");
990 *str = input_line_pointer;
991 input_line_pointer = save_in;
998 /* Get rid of any bignums now, so that we don't generate an error for which
999 we can't establish a line number later on. Big numbers are never valid
1000 in instructions, which is where this routine is always called. */
1001 if (prefix_mode != GE_OPT_PREFIX_BIG
1002 && (ep->X_op == O_big
1003 || (ep->X_add_symbol
1004 && (walk_no_bignums (ep->X_add_symbol)
1006 && walk_no_bignums (ep->X_op_symbol))))))
1008 inst.error = _("invalid constant");
1009 *str = input_line_pointer;
1010 input_line_pointer = save_in;
1014 *str = input_line_pointer;
1015 input_line_pointer = save_in;
1019 /* Turn a string in input_line_pointer into a floating point constant
1020 of type TYPE, and store the appropriate bytes in *LITP. The number
1021 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1022 returned, or NULL on OK.
1024 Note that fp constants aren't represent in the normal way on the ARM.
1025 In big endian mode, things are as expected. However, in little endian
1026 mode fp constants are big-endian word-wise, and little-endian byte-wise
1027 within the words. For example, (double) 1.1 in big endian mode is
1028 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1029 the byte sequence 99 99 f1 3f 9a 99 99 99.
1031 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1034 md_atof (int type, char * litP, int * sizeP)
1037 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1069 return _("Unrecognized or unsupported floating point constant");
1072 t = atof_ieee (input_line_pointer, type, words);
1074 input_line_pointer = t;
1075 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1077 if (target_big_endian)
1079 for (i = 0; i < prec; i++)
1081 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1082 litP += sizeof (LITTLENUM_TYPE);
1087 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1088 for (i = prec - 1; i >= 0; i--)
1090 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1091 litP += sizeof (LITTLENUM_TYPE);
1094 /* For a 4 byte float the order of elements in `words' is 1 0.
1095 For an 8 byte float the order is 1 0 3 2. */
1096 for (i = 0; i < prec; i += 2)
1098 md_number_to_chars (litP, (valueT) words[i + 1],
1099 sizeof (LITTLENUM_TYPE));
1100 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1101 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1102 litP += 2 * sizeof (LITTLENUM_TYPE);
1109 /* We handle all bad expressions here, so that we can report the faulty
1110 instruction in the error message. */
1112 md_operand (expressionS * exp)
1114 if (in_my_get_expression)
1115 exp->X_op = O_illegal;
1118 /* Immediate values. */
1120 /* Generic immediate-value read function for use in directives.
1121 Accepts anything that 'expression' can fold to a constant.
1122 *val receives the number. */
1125 immediate_for_directive (int *val)
1128 exp.X_op = O_illegal;
1130 if (is_immediate_prefix (*input_line_pointer))
1132 input_line_pointer++;
1136 if (exp.X_op != O_constant)
1138 as_bad (_("expected #constant"));
1139 ignore_rest_of_line ();
1142 *val = exp.X_add_number;
1147 /* Register parsing. */
1149 /* Generic register parser. CCP points to what should be the
1150 beginning of a register name. If it is indeed a valid register
1151 name, advance CCP over it and return the reg_entry structure;
1152 otherwise return NULL. Does not issue diagnostics. */
1154 static struct reg_entry *
1155 arm_reg_parse_multi (char **ccp)
1159 struct reg_entry *reg;
1161 #ifdef REGISTER_PREFIX
1162 if (*start != REGISTER_PREFIX)
1166 #ifdef OPTIONAL_REGISTER_PREFIX
1167 if (*start == OPTIONAL_REGISTER_PREFIX)
1172 if (!ISALPHA (*p) || !is_name_beginner (*p))
1177 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1179 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1189 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1190 enum arm_reg_type type)
1192 /* Alternative syntaxes are accepted for a few register classes. */
1199 /* Generic coprocessor register names are allowed for these. */
1200 if (reg && reg->type == REG_TYPE_CN)
1205 /* For backward compatibility, a bare number is valid here. */
1207 unsigned long processor = strtoul (start, ccp, 10);
1208 if (*ccp != start && processor <= 15)
1212 case REG_TYPE_MMXWC:
1213 /* WC includes WCG. ??? I'm not sure this is true for all
1214 instructions that take WC registers. */
1215 if (reg && reg->type == REG_TYPE_MMXWCG)
1226 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1227 return value is the register number or FAIL. */
1230 arm_reg_parse (char **ccp, enum arm_reg_type type)
1233 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1236 /* Do not allow a scalar (reg+index) to parse as a register. */
1237 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1240 if (reg && reg->type == type)
1243 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1250 /* Parse a Neon type specifier. *STR should point at the leading '.'
1251 character. Does no verification at this stage that the type fits the opcode
1258 Can all be legally parsed by this function.
1260 Fills in neon_type struct pointer with parsed information, and updates STR
1261 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1262 type, FAIL if not. */
1265 parse_neon_type (struct neon_type *type, char **str)
1272 while (type->elems < NEON_MAX_TYPE_ELS)
1274 enum neon_el_type thistype = NT_untyped;
1275 unsigned thissize = -1u;
1282 /* Just a size without an explicit type. */
1286 switch (TOLOWER (*ptr))
1288 case 'i': thistype = NT_integer; break;
1289 case 'f': thistype = NT_float; break;
1290 case 'p': thistype = NT_poly; break;
1291 case 's': thistype = NT_signed; break;
1292 case 'u': thistype = NT_unsigned; break;
1294 thistype = NT_float;
1299 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1305 /* .f is an abbreviation for .f32. */
1306 if (thistype == NT_float && !ISDIGIT (*ptr))
1311 thissize = strtoul (ptr, &ptr, 10);
1313 if (thissize != 8 && thissize != 16 && thissize != 32
1316 as_bad (_("bad size %d in type specifier"), thissize);
1324 type->el[type->elems].type = thistype;
1325 type->el[type->elems].size = thissize;
1330 /* Empty/missing type is not a successful parse. */
1331 if (type->elems == 0)
1339 /* Errors may be set multiple times during parsing or bit encoding
1340 (particularly in the Neon bits), but usually the earliest error which is set
1341 will be the most meaningful. Avoid overwriting it with later (cascading)
1342 errors by calling this function. */
1345 first_error (const char *err)
1351 /* Parse a single type, e.g. ".s32", leading period included. */
1353 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1356 struct neon_type optype;
1360 if (parse_neon_type (&optype, &str) == SUCCESS)
1362 if (optype.elems == 1)
1363 *vectype = optype.el[0];
1366 first_error (_("only one type should be specified for operand"));
1372 first_error (_("vector type expected"));
1384 /* Special meanings for indices (which have a range of 0-7), which will fit into
1387 #define NEON_ALL_LANES 15
1388 #define NEON_INTERLEAVE_LANES 14
1390 /* Parse either a register or a scalar, with an optional type. Return the
1391 register number, and optionally fill in the actual type of the register
1392 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1393 type/index information in *TYPEINFO. */
1396 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1397 enum arm_reg_type *rtype,
1398 struct neon_typed_alias *typeinfo)
1401 struct reg_entry *reg = arm_reg_parse_multi (&str);
1402 struct neon_typed_alias atype;
1403 struct neon_type_el parsetype;
1407 atype.eltype.type = NT_invtype;
1408 atype.eltype.size = -1;
1410 /* Try alternate syntax for some types of register. Note these are mutually
1411 exclusive with the Neon syntax extensions. */
1414 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1422 /* Undo polymorphism when a set of register types may be accepted. */
1423 if ((type == REG_TYPE_NDQ
1424 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1425 || (type == REG_TYPE_VFSD
1426 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1427 || (type == REG_TYPE_NSDQ
1428 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1429 || reg->type == REG_TYPE_NQ))
1430 || (type == REG_TYPE_MMXWC
1431 && (reg->type == REG_TYPE_MMXWCG)))
1432 type = (enum arm_reg_type) reg->type;
1434 if (type != reg->type)
1440 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1442 if ((atype.defined & NTA_HASTYPE) != 0)
1444 first_error (_("can't redefine type for operand"));
1447 atype.defined |= NTA_HASTYPE;
1448 atype.eltype = parsetype;
1451 if (skip_past_char (&str, '[') == SUCCESS)
1453 if (type != REG_TYPE_VFD)
1455 first_error (_("only D registers may be indexed"));
1459 if ((atype.defined & NTA_HASINDEX) != 0)
1461 first_error (_("can't change index for operand"));
1465 atype.defined |= NTA_HASINDEX;
1467 if (skip_past_char (&str, ']') == SUCCESS)
1468 atype.index = NEON_ALL_LANES;
1473 my_get_expression (&exp, &str, GE_NO_PREFIX);
1475 if (exp.X_op != O_constant)
1477 first_error (_("constant expression required"));
1481 if (skip_past_char (&str, ']') == FAIL)
1484 atype.index = exp.X_add_number;
1499 /* Like arm_reg_parse, but allow allow the following extra features:
1500 - If RTYPE is non-zero, return the (possibly restricted) type of the
1501 register (e.g. Neon double or quad reg when either has been requested).
1502 - If this is a Neon vector type with additional type information, fill
1503 in the struct pointed to by VECTYPE (if non-NULL).
1504 This function will fault on encountering a scalar. */
1507 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1508 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1510 struct neon_typed_alias atype;
1512 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1517 /* Do not allow regname(... to parse as a register. */
1521 /* Do not allow a scalar (reg+index) to parse as a register. */
1522 if ((atype.defined & NTA_HASINDEX) != 0)
1524 first_error (_("register operand expected, but got scalar"));
1529 *vectype = atype.eltype;
1536 #define NEON_SCALAR_REG(X) ((X) >> 4)
1537 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1539 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1540 have enough information to be able to do a good job bounds-checking. So, we
1541 just do easy checks here, and do further checks later. */
1544 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1548 struct neon_typed_alias atype;
1550 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1552 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1555 if (atype.index == NEON_ALL_LANES)
1557 first_error (_("scalar must have an index"));
1560 else if (atype.index >= 64 / elsize)
1562 first_error (_("scalar index out of range"));
1567 *type = atype.eltype;
1571 return reg * 16 + atype.index;
1574 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1577 parse_reg_list (char ** strp)
1579 char * str = * strp;
1583 /* We come back here if we get ranges concatenated by '+' or '|'. */
1598 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1600 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1610 first_error (_("bad range in register list"));
1614 for (i = cur_reg + 1; i < reg; i++)
1616 if (range & (1 << i))
1618 (_("Warning: duplicated register (r%d) in register list"),
1626 if (range & (1 << reg))
1627 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1629 else if (reg <= cur_reg)
1630 as_tsktsk (_("Warning: register range not in ascending order"));
1635 while (skip_past_comma (&str) != FAIL
1636 || (in_range = 1, *str++ == '-'));
1641 first_error (_("missing `}'"));
1649 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1652 if (exp.X_op == O_constant)
1654 if (exp.X_add_number
1655 != (exp.X_add_number & 0x0000ffff))
1657 inst.error = _("invalid register mask");
1661 if ((range & exp.X_add_number) != 0)
1663 int regno = range & exp.X_add_number;
1666 regno = (1 << regno) - 1;
1668 (_("Warning: duplicated register (r%d) in register list"),
1672 range |= exp.X_add_number;
1676 if (inst.reloc.type != 0)
1678 inst.error = _("expression too complex");
1682 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1683 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1684 inst.reloc.pc_rel = 0;
1688 if (*str == '|' || *str == '+')
1694 while (another_range);
1700 /* Types of registers in a list. */
1709 /* Parse a VFP register list. If the string is invalid return FAIL.
1710 Otherwise return the number of registers, and set PBASE to the first
1711 register. Parses registers of type ETYPE.
1712 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1713 - Q registers can be used to specify pairs of D registers
1714 - { } can be omitted from around a singleton register list
1715 FIXME: This is not implemented, as it would require backtracking in
1718 This could be done (the meaning isn't really ambiguous), but doesn't
1719 fit in well with the current parsing framework.
1720 - 32 D registers may be used (also true for VFPv3).
1721 FIXME: Types are ignored in these register lists, which is probably a
1725 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1730 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1734 unsigned long mask = 0;
1739 inst.error = _("expecting {");
1748 regtype = REG_TYPE_VFS;
1753 regtype = REG_TYPE_VFD;
1756 case REGLIST_NEON_D:
1757 regtype = REG_TYPE_NDQ;
1761 if (etype != REGLIST_VFP_S)
1763 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1764 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1768 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1771 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1778 base_reg = max_regs;
1782 int setmask = 1, addregs = 1;
1784 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1786 if (new_base == FAIL)
1788 first_error (_(reg_expected_msgs[regtype]));
1792 if (new_base >= max_regs)
1794 first_error (_("register out of range in list"));
1798 /* Note: a value of 2 * n is returned for the register Q<n>. */
1799 if (regtype == REG_TYPE_NQ)
1805 if (new_base < base_reg)
1806 base_reg = new_base;
1808 if (mask & (setmask << new_base))
1810 first_error (_("invalid register list"));
1814 if ((mask >> new_base) != 0 && ! warned)
1816 as_tsktsk (_("register list not in ascending order"));
1820 mask |= setmask << new_base;
1823 if (*str == '-') /* We have the start of a range expression */
1829 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1832 inst.error = gettext (reg_expected_msgs[regtype]);
1836 if (high_range >= max_regs)
1838 first_error (_("register out of range in list"));
1842 if (regtype == REG_TYPE_NQ)
1843 high_range = high_range + 1;
1845 if (high_range <= new_base)
1847 inst.error = _("register range not in ascending order");
1851 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1853 if (mask & (setmask << new_base))
1855 inst.error = _("invalid register list");
1859 mask |= setmask << new_base;
1864 while (skip_past_comma (&str) != FAIL);
1868 /* Sanity check -- should have raised a parse error above. */
1869 if (count == 0 || count > max_regs)
1874 /* Final test -- the registers must be consecutive. */
1876 for (i = 0; i < count; i++)
1878 if ((mask & (1u << i)) == 0)
1880 inst.error = _("non-contiguous register range");
1890 /* True if two alias types are the same. */
1893 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1901 if (a->defined != b->defined)
1904 if ((a->defined & NTA_HASTYPE) != 0
1905 && (a->eltype.type != b->eltype.type
1906 || a->eltype.size != b->eltype.size))
1909 if ((a->defined & NTA_HASINDEX) != 0
1910 && (a->index != b->index))
1916 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1917 The base register is put in *PBASE.
1918 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1920 The register stride (minus one) is put in bit 4 of the return value.
1921 Bits [6:5] encode the list length (minus one).
1922 The type of the list elements is put in *ELTYPE, if non-NULL. */
1924 #define NEON_LANE(X) ((X) & 0xf)
1925 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1926 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1929 parse_neon_el_struct_list (char **str, unsigned *pbase,
1930 struct neon_type_el *eltype)
1937 int leading_brace = 0;
1938 enum arm_reg_type rtype = REG_TYPE_NDQ;
1939 const char *const incr_error = _("register stride must be 1 or 2");
1940 const char *const type_error = _("mismatched element/structure types in list");
1941 struct neon_typed_alias firsttype;
1943 if (skip_past_char (&ptr, '{') == SUCCESS)
1948 struct neon_typed_alias atype;
1949 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1953 first_error (_(reg_expected_msgs[rtype]));
1960 if (rtype == REG_TYPE_NQ)
1966 else if (reg_incr == -1)
1968 reg_incr = getreg - base_reg;
1969 if (reg_incr < 1 || reg_incr > 2)
1971 first_error (_(incr_error));
1975 else if (getreg != base_reg + reg_incr * count)
1977 first_error (_(incr_error));
1981 if (! neon_alias_types_same (&atype, &firsttype))
1983 first_error (_(type_error));
1987 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1991 struct neon_typed_alias htype;
1992 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1994 lane = NEON_INTERLEAVE_LANES;
1995 else if (lane != NEON_INTERLEAVE_LANES)
1997 first_error (_(type_error));
2002 else if (reg_incr != 1)
2004 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2008 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2011 first_error (_(reg_expected_msgs[rtype]));
2014 if (! neon_alias_types_same (&htype, &firsttype))
2016 first_error (_(type_error));
2019 count += hireg + dregs - getreg;
2023 /* If we're using Q registers, we can't use [] or [n] syntax. */
2024 if (rtype == REG_TYPE_NQ)
2030 if ((atype.defined & NTA_HASINDEX) != 0)
2034 else if (lane != atype.index)
2036 first_error (_(type_error));
2040 else if (lane == -1)
2041 lane = NEON_INTERLEAVE_LANES;
2042 else if (lane != NEON_INTERLEAVE_LANES)
2044 first_error (_(type_error));
2049 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2051 /* No lane set by [x]. We must be interleaving structures. */
2053 lane = NEON_INTERLEAVE_LANES;
2056 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2057 || (count > 1 && reg_incr == -1))
2059 first_error (_("error parsing element/structure list"));
2063 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2065 first_error (_("expected }"));
2073 *eltype = firsttype.eltype;
2078 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2081 /* Parse an explicit relocation suffix on an expression. This is
2082 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2083 arm_reloc_hsh contains no entries, so this function can only
2084 succeed if there is no () after the word. Returns -1 on error,
2085 BFD_RELOC_UNUSED if there wasn't any suffix. */
2088 parse_reloc (char **str)
2090 struct reloc_entry *r;
2094 return BFD_RELOC_UNUSED;
2099 while (*q && *q != ')' && *q != ',')
2104 if ((r = (struct reloc_entry *)
2105 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2112 /* Directives: register aliases. */
2114 static struct reg_entry *
2115 insert_reg_alias (char *str, unsigned number, int type)
2117 struct reg_entry *new_reg;
2120 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2122 if (new_reg->builtin)
2123 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2125 /* Only warn about a redefinition if it's not defined as the
2127 else if (new_reg->number != number || new_reg->type != type)
2128 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2133 name = xstrdup (str);
2134 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2136 new_reg->name = name;
2137 new_reg->number = number;
2138 new_reg->type = type;
2139 new_reg->builtin = FALSE;
2140 new_reg->neon = NULL;
2142 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2149 insert_neon_reg_alias (char *str, int number, int type,
2150 struct neon_typed_alias *atype)
2152 struct reg_entry *reg = insert_reg_alias (str, number, type);
2156 first_error (_("attempt to redefine typed alias"));
2162 reg->neon = (struct neon_typed_alias *)
2163 xmalloc (sizeof (struct neon_typed_alias));
2164 *reg->neon = *atype;
2168 /* Look for the .req directive. This is of the form:
2170 new_register_name .req existing_register_name
2172 If we find one, or if it looks sufficiently like one that we want to
2173 handle any error here, return TRUE. Otherwise return FALSE. */
2176 create_register_alias (char * newname, char *p)
2178 struct reg_entry *old;
2179 char *oldname, *nbuf;
2182 /* The input scrubber ensures that whitespace after the mnemonic is
2183 collapsed to single spaces. */
2185 if (strncmp (oldname, " .req ", 6) != 0)
2189 if (*oldname == '\0')
2192 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2195 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2199 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2200 the desired alias name, and p points to its end. If not, then
2201 the desired alias name is in the global original_case_string. */
2202 #ifdef TC_CASE_SENSITIVE
2205 newname = original_case_string;
2206 nlen = strlen (newname);
2209 nbuf = (char *) alloca (nlen + 1);
2210 memcpy (nbuf, newname, nlen);
2213 /* Create aliases under the new name as stated; an all-lowercase
2214 version of the new name; and an all-uppercase version of the new
2216 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2218 for (p = nbuf; *p; p++)
2221 if (strncmp (nbuf, newname, nlen))
2223 /* If this attempt to create an additional alias fails, do not bother
2224 trying to create the all-lower case alias. We will fail and issue
2225 a second, duplicate error message. This situation arises when the
2226 programmer does something like:
2229 The second .req creates the "Foo" alias but then fails to create
2230 the artificial FOO alias because it has already been created by the
2232 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2236 for (p = nbuf; *p; p++)
2239 if (strncmp (nbuf, newname, nlen))
2240 insert_reg_alias (nbuf, old->number, old->type);
2246 /* Create a Neon typed/indexed register alias using directives, e.g.:
2251 These typed registers can be used instead of the types specified after the
2252 Neon mnemonic, so long as all operands given have types. Types can also be
2253 specified directly, e.g.:
2254 vadd d0.s32, d1.s32, d2.s32 */
2257 create_neon_reg_alias (char *newname, char *p)
2259 enum arm_reg_type basetype;
2260 struct reg_entry *basereg;
2261 struct reg_entry mybasereg;
2262 struct neon_type ntype;
2263 struct neon_typed_alias typeinfo;
2264 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2267 typeinfo.defined = 0;
2268 typeinfo.eltype.type = NT_invtype;
2269 typeinfo.eltype.size = -1;
2270 typeinfo.index = -1;
2274 if (strncmp (p, " .dn ", 5) == 0)
2275 basetype = REG_TYPE_VFD;
2276 else if (strncmp (p, " .qn ", 5) == 0)
2277 basetype = REG_TYPE_NQ;
2286 basereg = arm_reg_parse_multi (&p);
2288 if (basereg && basereg->type != basetype)
2290 as_bad (_("bad type for register"));
2294 if (basereg == NULL)
2297 /* Try parsing as an integer. */
2298 my_get_expression (&exp, &p, GE_NO_PREFIX);
2299 if (exp.X_op != O_constant)
2301 as_bad (_("expression must be constant"));
2304 basereg = &mybasereg;
2305 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2311 typeinfo = *basereg->neon;
2313 if (parse_neon_type (&ntype, &p) == SUCCESS)
2315 /* We got a type. */
2316 if (typeinfo.defined & NTA_HASTYPE)
2318 as_bad (_("can't redefine the type of a register alias"));
2322 typeinfo.defined |= NTA_HASTYPE;
2323 if (ntype.elems != 1)
2325 as_bad (_("you must specify a single type only"));
2328 typeinfo.eltype = ntype.el[0];
2331 if (skip_past_char (&p, '[') == SUCCESS)
2334 /* We got a scalar index. */
2336 if (typeinfo.defined & NTA_HASINDEX)
2338 as_bad (_("can't redefine the index of a scalar alias"));
2342 my_get_expression (&exp, &p, GE_NO_PREFIX);
2344 if (exp.X_op != O_constant)
2346 as_bad (_("scalar index must be constant"));
2350 typeinfo.defined |= NTA_HASINDEX;
2351 typeinfo.index = exp.X_add_number;
2353 if (skip_past_char (&p, ']') == FAIL)
2355 as_bad (_("expecting ]"));
2360 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2361 the desired alias name, and p points to its end. If not, then
2362 the desired alias name is in the global original_case_string. */
2363 #ifdef TC_CASE_SENSITIVE
2364 namelen = nameend - newname;
2366 newname = original_case_string;
2367 namelen = strlen (newname);
2370 namebuf = (char *) alloca (namelen + 1);
2371 strncpy (namebuf, newname, namelen);
2372 namebuf[namelen] = '\0';
2374 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2375 typeinfo.defined != 0 ? &typeinfo : NULL);
2377 /* Insert name in all uppercase. */
2378 for (p = namebuf; *p; p++)
2381 if (strncmp (namebuf, newname, namelen))
2382 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2383 typeinfo.defined != 0 ? &typeinfo : NULL);
2385 /* Insert name in all lowercase. */
2386 for (p = namebuf; *p; p++)
2389 if (strncmp (namebuf, newname, namelen))
2390 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2391 typeinfo.defined != 0 ? &typeinfo : NULL);
2396 /* Should never be called, as .req goes between the alias and the
2397 register name, not at the beginning of the line. */
2400 s_req (int a ATTRIBUTE_UNUSED)
2402 as_bad (_("invalid syntax for .req directive"));
2406 s_dn (int a ATTRIBUTE_UNUSED)
2408 as_bad (_("invalid syntax for .dn directive"));
2412 s_qn (int a ATTRIBUTE_UNUSED)
2414 as_bad (_("invalid syntax for .qn directive"));
2417 /* The .unreq directive deletes an alias which was previously defined
2418 by .req. For example:
2424 s_unreq (int a ATTRIBUTE_UNUSED)
2429 name = input_line_pointer;
2431 while (*input_line_pointer != 0
2432 && *input_line_pointer != ' '
2433 && *input_line_pointer != '\n')
2434 ++input_line_pointer;
2436 saved_char = *input_line_pointer;
2437 *input_line_pointer = 0;
2440 as_bad (_("invalid syntax for .unreq directive"));
2443 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2447 as_bad (_("unknown register alias '%s'"), name);
2448 else if (reg->builtin)
2449 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2456 hash_delete (arm_reg_hsh, name, FALSE);
2457 free ((char *) reg->name);
2462 /* Also locate the all upper case and all lower case versions.
2463 Do not complain if we cannot find one or the other as it
2464 was probably deleted above. */
2466 nbuf = strdup (name);
2467 for (p = nbuf; *p; p++)
2469 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2472 hash_delete (arm_reg_hsh, nbuf, FALSE);
2473 free ((char *) reg->name);
2479 for (p = nbuf; *p; p++)
2481 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2484 hash_delete (arm_reg_hsh, nbuf, FALSE);
2485 free ((char *) reg->name);
2495 *input_line_pointer = saved_char;
2496 demand_empty_rest_of_line ();
2499 /* Directives: Instruction set selection. */
2502 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2503 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2504 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2505 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2507 /* Create a new mapping symbol for the transition to STATE. */
2510 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2513 const char * symname;
2520 type = BSF_NO_FLAGS;
2524 type = BSF_NO_FLAGS;
2528 type = BSF_NO_FLAGS;
2534 symbolP = symbol_new (symname, now_seg, value, frag);
2535 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2540 THUMB_SET_FUNC (symbolP, 0);
2541 ARM_SET_THUMB (symbolP, 0);
2542 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 THUMB_SET_FUNC (symbolP, 1);
2547 ARM_SET_THUMB (symbolP, 1);
2548 ARM_SET_INTERWORK (symbolP, support_interwork);
2556 /* Save the mapping symbols for future reference. Also check that
2557 we do not place two mapping symbols at the same offset within a
2558 frag. We'll handle overlap between frags in
2559 check_mapping_symbols.
2561 If .fill or other data filling directive generates zero sized data,
2562 the mapping symbol for the following code will have the same value
2563 as the one generated for the data filling directive. In this case,
2564 we replace the old symbol with the new one at the same address. */
2567 if (frag->tc_frag_data.first_map != NULL)
2569 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2570 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2572 frag->tc_frag_data.first_map = symbolP;
2574 if (frag->tc_frag_data.last_map != NULL)
2576 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2577 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2578 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2580 frag->tc_frag_data.last_map = symbolP;
2583 /* We must sometimes convert a region marked as code to data during
2584 code alignment, if an odd number of bytes have to be padded. The
2585 code mapping symbol is pushed to an aligned address. */
2588 insert_data_mapping_symbol (enum mstate state,
2589 valueT value, fragS *frag, offsetT bytes)
2591 /* If there was already a mapping symbol, remove it. */
2592 if (frag->tc_frag_data.last_map != NULL
2593 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2595 symbolS *symp = frag->tc_frag_data.last_map;
2599 know (frag->tc_frag_data.first_map == symp);
2600 frag->tc_frag_data.first_map = NULL;
2602 frag->tc_frag_data.last_map = NULL;
2603 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2606 make_mapping_symbol (MAP_DATA, value, frag);
2607 make_mapping_symbol (state, value + bytes, frag);
2610 static void mapping_state_2 (enum mstate state, int max_chars);
2612 /* Set the mapping state to STATE. Only call this when about to
2613 emit some STATE bytes to the file. */
2616 mapping_state (enum mstate state)
2618 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2620 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2622 if (mapstate == state)
2623 /* The mapping symbol has already been emitted.
2624 There is nothing else to do. */
2627 if (state == MAP_ARM || state == MAP_THUMB)
2629 All ARM instructions require 4-byte alignment.
2630 (Almost) all Thumb instructions require 2-byte alignment.
2632 When emitting instructions into any section, mark the section
2635 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2636 but themselves require 2-byte alignment; this applies to some
2637 PC- relative forms. However, these cases will invovle implicit
2638 literal pool generation or an explicit .align >=2, both of
2639 which will cause the section to me marked with sufficient
2640 alignment. Thus, we don't handle those cases here. */
2641 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2643 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2644 /* This case will be evaluated later in the next else. */
2646 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2647 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2649 /* Only add the symbol if the offset is > 0:
2650 if we're at the first frag, check it's size > 0;
2651 if we're not at the first frag, then for sure
2652 the offset is > 0. */
2653 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2654 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2657 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2660 mapping_state_2 (state, 0);
2664 /* Same as mapping_state, but MAX_CHARS bytes have already been
2665 allocated. Put the mapping symbol that far back. */
2668 mapping_state_2 (enum mstate state, int max_chars)
2670 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2672 if (!SEG_NORMAL (now_seg))
2675 if (mapstate == state)
2676 /* The mapping symbol has already been emitted.
2677 There is nothing else to do. */
2680 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2681 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2684 #define mapping_state(x) ((void)0)
2685 #define mapping_state_2(x, y) ((void)0)
2688 /* Find the real, Thumb encoded start of a Thumb function. */
2692 find_real_start (symbolS * symbolP)
2695 const char * name = S_GET_NAME (symbolP);
2696 symbolS * new_target;
2698 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2699 #define STUB_NAME ".real_start_of"
2704 /* The compiler may generate BL instructions to local labels because
2705 it needs to perform a branch to a far away location. These labels
2706 do not have a corresponding ".real_start_of" label. We check
2707 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2708 the ".real_start_of" convention for nonlocal branches. */
2709 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2712 real_start = ACONCAT ((STUB_NAME, name, NULL));
2713 new_target = symbol_find (real_start);
2715 if (new_target == NULL)
2717 as_warn (_("Failed to find real start of function: %s\n"), name);
2718 new_target = symbolP;
2726 opcode_select (int width)
2733 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2734 as_bad (_("selected processor does not support THUMB opcodes"));
2737 /* No need to force the alignment, since we will have been
2738 coming from ARM mode, which is word-aligned. */
2739 record_alignment (now_seg, 1);
2746 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2747 as_bad (_("selected processor does not support ARM opcodes"));
2752 frag_align (2, 0, 0);
2754 record_alignment (now_seg, 1);
2759 as_bad (_("invalid instruction size selected (%d)"), width);
2764 s_arm (int ignore ATTRIBUTE_UNUSED)
2767 demand_empty_rest_of_line ();
2771 s_thumb (int ignore ATTRIBUTE_UNUSED)
2774 demand_empty_rest_of_line ();
2778 s_code (int unused ATTRIBUTE_UNUSED)
2782 temp = get_absolute_expression ();
2787 opcode_select (temp);
2791 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2796 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2798 /* If we are not already in thumb mode go into it, EVEN if
2799 the target processor does not support thumb instructions.
2800 This is used by gcc/config/arm/lib1funcs.asm for example
2801 to compile interworking support functions even if the
2802 target processor should not support interworking. */
2806 record_alignment (now_seg, 1);
2809 demand_empty_rest_of_line ();
2813 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2817 /* The following label is the name/address of the start of a Thumb function.
2818 We need to know this for the interworking support. */
2819 label_is_thumb_function_name = TRUE;
2822 /* Perform a .set directive, but also mark the alias as
2823 being a thumb function. */
2826 s_thumb_set (int equiv)
2828 /* XXX the following is a duplicate of the code for s_set() in read.c
2829 We cannot just call that code as we need to get at the symbol that
2836 /* Especial apologies for the random logic:
2837 This just grew, and could be parsed much more simply!
2839 name = input_line_pointer;
2840 delim = get_symbol_end ();
2841 end_name = input_line_pointer;
2844 if (*input_line_pointer != ',')
2847 as_bad (_("expected comma after name \"%s\""), name);
2849 ignore_rest_of_line ();
2853 input_line_pointer++;
2856 if (name[0] == '.' && name[1] == '\0')
2858 /* XXX - this should not happen to .thumb_set. */
2862 if ((symbolP = symbol_find (name)) == NULL
2863 && (symbolP = md_undefined_symbol (name)) == NULL)
2866 /* When doing symbol listings, play games with dummy fragments living
2867 outside the normal fragment chain to record the file and line info
2869 if (listing & LISTING_SYMBOLS)
2871 extern struct list_info_struct * listing_tail;
2872 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2874 memset (dummy_frag, 0, sizeof (fragS));
2875 dummy_frag->fr_type = rs_fill;
2876 dummy_frag->line = listing_tail;
2877 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2878 dummy_frag->fr_symbol = symbolP;
2882 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2885 /* "set" symbols are local unless otherwise specified. */
2886 SF_SET_LOCAL (symbolP);
2887 #endif /* OBJ_COFF */
2888 } /* Make a new symbol. */
2890 symbol_table_insert (symbolP);
2895 && S_IS_DEFINED (symbolP)
2896 && S_GET_SEGMENT (symbolP) != reg_section)
2897 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2899 pseudo_set (symbolP);
2901 demand_empty_rest_of_line ();
2903 /* XXX Now we come to the Thumb specific bit of code. */
2905 THUMB_SET_FUNC (symbolP, 1);
2906 ARM_SET_THUMB (symbolP, 1);
2907 #if defined OBJ_ELF || defined OBJ_COFF
2908 ARM_SET_INTERWORK (symbolP, support_interwork);
2912 /* Directives: Mode selection. */
2914 /* .syntax [unified|divided] - choose the new unified syntax
2915 (same for Arm and Thumb encoding, modulo slight differences in what
2916 can be represented) or the old divergent syntax for each mode. */
2918 s_syntax (int unused ATTRIBUTE_UNUSED)
2922 name = input_line_pointer;
2923 delim = get_symbol_end ();
2925 if (!strcasecmp (name, "unified"))
2926 unified_syntax = TRUE;
2927 else if (!strcasecmp (name, "divided"))
2928 unified_syntax = FALSE;
2931 as_bad (_("unrecognized syntax mode \"%s\""), name);
2934 *input_line_pointer = delim;
2935 demand_empty_rest_of_line ();
2938 /* Directives: sectioning and alignment. */
2940 /* Same as s_align_ptwo but align 0 => align 2. */
2943 s_align (int unused ATTRIBUTE_UNUSED)
2948 long max_alignment = 15;
2950 temp = get_absolute_expression ();
2951 if (temp > max_alignment)
2952 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2955 as_bad (_("alignment negative. 0 assumed."));
2959 if (*input_line_pointer == ',')
2961 input_line_pointer++;
2962 temp_fill = get_absolute_expression ();
2974 /* Only make a frag if we HAVE to. */
2975 if (temp && !need_pass_2)
2977 if (!fill_p && subseg_text_p (now_seg))
2978 frag_align_code (temp, 0);
2980 frag_align (temp, (int) temp_fill, 0);
2982 demand_empty_rest_of_line ();
2984 record_alignment (now_seg, temp);
2988 s_bss (int ignore ATTRIBUTE_UNUSED)
2990 /* We don't support putting frags in the BSS segment, we fake it by
2991 marking in_bss, then looking at s_skip for clues. */
2992 subseg_set (bss_section, 0);
2993 demand_empty_rest_of_line ();
2995 #ifdef md_elf_section_change_hook
2996 md_elf_section_change_hook ();
3001 s_even (int ignore ATTRIBUTE_UNUSED)
3003 /* Never make frag if expect extra pass. */
3005 frag_align (1, 0, 0);
3007 record_alignment (now_seg, 1);
3009 demand_empty_rest_of_line ();
3012 /* Directives: Literal pools. */
3014 static literal_pool *
3015 find_literal_pool (void)
3017 literal_pool * pool;
3019 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3021 if (pool->section == now_seg
3022 && pool->sub_section == now_subseg)
3029 static literal_pool *
3030 find_or_make_literal_pool (void)
3032 /* Next literal pool ID number. */
3033 static unsigned int latest_pool_num = 1;
3034 literal_pool * pool;
3036 pool = find_literal_pool ();
3040 /* Create a new pool. */
3041 pool = (literal_pool *) xmalloc (sizeof (* pool));
3045 pool->next_free_entry = 0;
3046 pool->section = now_seg;
3047 pool->sub_section = now_subseg;
3048 pool->next = list_of_pools;
3049 pool->symbol = NULL;
3051 /* Add it to the list. */
3052 list_of_pools = pool;
3055 /* New pools, and emptied pools, will have a NULL symbol. */
3056 if (pool->symbol == NULL)
3058 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3059 (valueT) 0, &zero_address_frag);
3060 pool->id = latest_pool_num ++;
3067 /* Add the literal in the global 'inst'
3068 structure to the relevant literal pool. */
3071 add_to_lit_pool (void)
3073 literal_pool * pool;
3076 pool = find_or_make_literal_pool ();
3078 /* Check if this literal value is already in the pool. */
3079 for (entry = 0; entry < pool->next_free_entry; entry ++)
3081 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3082 && (inst.reloc.exp.X_op == O_constant)
3083 && (pool->literals[entry].X_add_number
3084 == inst.reloc.exp.X_add_number)
3085 && (pool->literals[entry].X_unsigned
3086 == inst.reloc.exp.X_unsigned))
3089 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3090 && (inst.reloc.exp.X_op == O_symbol)
3091 && (pool->literals[entry].X_add_number
3092 == inst.reloc.exp.X_add_number)
3093 && (pool->literals[entry].X_add_symbol
3094 == inst.reloc.exp.X_add_symbol)
3095 && (pool->literals[entry].X_op_symbol
3096 == inst.reloc.exp.X_op_symbol))
3100 /* Do we need to create a new entry? */
3101 if (entry == pool->next_free_entry)
3103 if (entry >= MAX_LITERAL_POOL_SIZE)
3105 inst.error = _("literal pool overflow");
3109 pool->literals[entry] = inst.reloc.exp;
3111 /* PR ld/12974: Record the location of the first source line to reference
3112 this entry in the literal pool. If it turns out during linking that the
3113 symbol does not exist we will be able to give an accurate line number for
3114 the (first use of the) missing reference. */
3115 if (debug_type == DEBUG_DWARF2)
3116 dwarf2_where (pool->locs + entry);
3118 pool->next_free_entry += 1;
3121 inst.reloc.exp.X_op = O_symbol;
3122 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3123 inst.reloc.exp.X_add_symbol = pool->symbol;
3128 /* Can't use symbol_new here, so have to create a symbol and then at
3129 a later date assign it a value. Thats what these functions do. */
3132 symbol_locate (symbolS * symbolP,
3133 const char * name, /* It is copied, the caller can modify. */
3134 segT segment, /* Segment identifier (SEG_<something>). */
3135 valueT valu, /* Symbol value. */
3136 fragS * frag) /* Associated fragment. */
3138 unsigned int name_length;
3139 char * preserved_copy_of_name;
3141 name_length = strlen (name) + 1; /* +1 for \0. */
3142 obstack_grow (¬es, name, name_length);
3143 preserved_copy_of_name = (char *) obstack_finish (¬es);
3145 #ifdef tc_canonicalize_symbol_name
3146 preserved_copy_of_name =
3147 tc_canonicalize_symbol_name (preserved_copy_of_name);
3150 S_SET_NAME (symbolP, preserved_copy_of_name);
3152 S_SET_SEGMENT (symbolP, segment);
3153 S_SET_VALUE (symbolP, valu);
3154 symbol_clear_list_pointers (symbolP);
3156 symbol_set_frag (symbolP, frag);
3158 /* Link to end of symbol chain. */
3160 extern int symbol_table_frozen;
3162 if (symbol_table_frozen)
3166 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3168 obj_symbol_new_hook (symbolP);
3170 #ifdef tc_symbol_new_hook
3171 tc_symbol_new_hook (symbolP);
3175 verify_symbol_chain (symbol_rootP, symbol_lastP);
3176 #endif /* DEBUG_SYMS */
3181 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3184 literal_pool * pool;
3187 pool = find_literal_pool ();
3189 || pool->symbol == NULL
3190 || pool->next_free_entry == 0)
3193 mapping_state (MAP_DATA);
3195 /* Align pool as you have word accesses.
3196 Only make a frag if we have to. */
3198 frag_align (2, 0, 0);
3200 record_alignment (now_seg, 2);
3202 sprintf (sym_name, "$$lit_\002%x", pool->id);
3204 symbol_locate (pool->symbol, sym_name, now_seg,
3205 (valueT) frag_now_fix (), frag_now);
3206 symbol_table_insert (pool->symbol);
3208 ARM_SET_THUMB (pool->symbol, thumb_mode);
3210 #if defined OBJ_COFF || defined OBJ_ELF
3211 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3214 for (entry = 0; entry < pool->next_free_entry; entry ++)
3217 if (debug_type == DEBUG_DWARF2)
3218 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3220 /* First output the expression in the instruction to the pool. */
3221 emit_expr (&(pool->literals[entry]), 4); /* .word */
3224 /* Mark the pool as empty. */
3225 pool->next_free_entry = 0;
3226 pool->symbol = NULL;
3230 /* Forward declarations for functions below, in the MD interface
3232 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3233 static valueT create_unwind_entry (int);
3234 static void start_unwind_section (const segT, int);
3235 static void add_unwind_opcode (valueT, int);
3236 static void flush_pending_unwind (void);
3238 /* Directives: Data. */
3241 s_arm_elf_cons (int nbytes)
3245 #ifdef md_flush_pending_output
3246 md_flush_pending_output ();
3249 if (is_it_end_of_statement ())
3251 demand_empty_rest_of_line ();
3255 #ifdef md_cons_align
3256 md_cons_align (nbytes);
3259 mapping_state (MAP_DATA);
3263 char *base = input_line_pointer;
3267 if (exp.X_op != O_symbol)
3268 emit_expr (&exp, (unsigned int) nbytes);
3271 char *before_reloc = input_line_pointer;
3272 reloc = parse_reloc (&input_line_pointer);
3275 as_bad (_("unrecognized relocation suffix"));
3276 ignore_rest_of_line ();
3279 else if (reloc == BFD_RELOC_UNUSED)
3280 emit_expr (&exp, (unsigned int) nbytes);
3283 reloc_howto_type *howto = (reloc_howto_type *)
3284 bfd_reloc_type_lookup (stdoutput,
3285 (bfd_reloc_code_real_type) reloc);
3286 int size = bfd_get_reloc_size (howto);
3288 if (reloc == BFD_RELOC_ARM_PLT32)
3290 as_bad (_("(plt) is only valid on branch targets"));
3291 reloc = BFD_RELOC_UNUSED;
3296 as_bad (_("%s relocations do not fit in %d bytes"),
3297 howto->name, nbytes);
3300 /* We've parsed an expression stopping at O_symbol.
3301 But there may be more expression left now that we
3302 have parsed the relocation marker. Parse it again.
3303 XXX Surely there is a cleaner way to do this. */
3304 char *p = input_line_pointer;
3306 char *save_buf = (char *) alloca (input_line_pointer - base);
3307 memcpy (save_buf, base, input_line_pointer - base);
3308 memmove (base + (input_line_pointer - before_reloc),
3309 base, before_reloc - base);
3311 input_line_pointer = base + (input_line_pointer-before_reloc);
3313 memcpy (base, save_buf, p - base);
3315 offset = nbytes - size;
3316 p = frag_more ((int) nbytes);
3317 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3318 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3323 while (*input_line_pointer++ == ',');
3325 /* Put terminator back into stream. */
3326 input_line_pointer --;
3327 demand_empty_rest_of_line ();
3330 /* Emit an expression containing a 32-bit thumb instruction.
3331 Implementation based on put_thumb32_insn. */
3334 emit_thumb32_expr (expressionS * exp)
3336 expressionS exp_high = *exp;
3338 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3339 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3340 exp->X_add_number &= 0xffff;
3341 emit_expr (exp, (unsigned int) THUMB_SIZE);
3344 /* Guess the instruction size based on the opcode. */
3347 thumb_insn_size (int opcode)
3349 if ((unsigned int) opcode < 0xe800u)
3351 else if ((unsigned int) opcode >= 0xe8000000u)
3358 emit_insn (expressionS *exp, int nbytes)
3362 if (exp->X_op == O_constant)
3367 size = thumb_insn_size (exp->X_add_number);
3371 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3373 as_bad (_(".inst.n operand too big. "\
3374 "Use .inst.w instead"));
3379 if (now_it.state == AUTOMATIC_IT_BLOCK)
3380 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3382 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3384 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3385 emit_thumb32_expr (exp);
3387 emit_expr (exp, (unsigned int) size);
3389 it_fsm_post_encode ();
3393 as_bad (_("cannot determine Thumb instruction size. " \
3394 "Use .inst.n/.inst.w instead"));
3397 as_bad (_("constant expression required"));
3402 /* Like s_arm_elf_cons but do not use md_cons_align and
3403 set the mapping state to MAP_ARM/MAP_THUMB. */
3406 s_arm_elf_inst (int nbytes)
3408 if (is_it_end_of_statement ())
3410 demand_empty_rest_of_line ();
3414 /* Calling mapping_state () here will not change ARM/THUMB,
3415 but will ensure not to be in DATA state. */
3418 mapping_state (MAP_THUMB);
3423 as_bad (_("width suffixes are invalid in ARM mode"));
3424 ignore_rest_of_line ();
3430 mapping_state (MAP_ARM);
3439 if (! emit_insn (& exp, nbytes))
3441 ignore_rest_of_line ();
3445 while (*input_line_pointer++ == ',');
3447 /* Put terminator back into stream. */
3448 input_line_pointer --;
3449 demand_empty_rest_of_line ();
3452 /* Parse a .rel31 directive. */
3455 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3462 if (*input_line_pointer == '1')
3463 highbit = 0x80000000;
3464 else if (*input_line_pointer != '0')
3465 as_bad (_("expected 0 or 1"));
3467 input_line_pointer++;
3468 if (*input_line_pointer != ',')
3469 as_bad (_("missing comma"));
3470 input_line_pointer++;
3472 #ifdef md_flush_pending_output
3473 md_flush_pending_output ();
3476 #ifdef md_cons_align
3480 mapping_state (MAP_DATA);
3485 md_number_to_chars (p, highbit, 4);
3486 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3487 BFD_RELOC_ARM_PREL31);
3489 demand_empty_rest_of_line ();
3492 /* Directives: AEABI stack-unwind tables. */
3494 /* Parse an unwind_fnstart directive. Simply records the current location. */
3497 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3499 demand_empty_rest_of_line ();
3500 if (unwind.proc_start)
3502 as_bad (_("duplicate .fnstart directive"));
3506 /* Mark the start of the function. */
3507 unwind.proc_start = expr_build_dot ();
3509 /* Reset the rest of the unwind info. */
3510 unwind.opcode_count = 0;
3511 unwind.table_entry = NULL;
3512 unwind.personality_routine = NULL;
3513 unwind.personality_index = -1;
3514 unwind.frame_size = 0;
3515 unwind.fp_offset = 0;
3516 unwind.fp_reg = REG_SP;
3518 unwind.sp_restored = 0;
3522 /* Parse a handlerdata directive. Creates the exception handling table entry
3523 for the function. */
3526 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3528 demand_empty_rest_of_line ();
3529 if (!unwind.proc_start)
3530 as_bad (MISSING_FNSTART);
3532 if (unwind.table_entry)
3533 as_bad (_("duplicate .handlerdata directive"));
3535 create_unwind_entry (1);
3538 /* Parse an unwind_fnend directive. Generates the index table entry. */
3541 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3546 unsigned int marked_pr_dependency;
3548 demand_empty_rest_of_line ();
3550 if (!unwind.proc_start)
3552 as_bad (_(".fnend directive without .fnstart"));
3556 /* Add eh table entry. */
3557 if (unwind.table_entry == NULL)
3558 val = create_unwind_entry (0);
3562 /* Add index table entry. This is two words. */
3563 start_unwind_section (unwind.saved_seg, 1);
3564 frag_align (2, 0, 0);
3565 record_alignment (now_seg, 2);
3567 ptr = frag_more (8);
3569 where = frag_now_fix () - 8;
3571 /* Self relative offset of the function start. */
3572 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3573 BFD_RELOC_ARM_PREL31);
3575 /* Indicate dependency on EHABI-defined personality routines to the
3576 linker, if it hasn't been done already. */
3577 marked_pr_dependency
3578 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3579 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3580 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3582 static const char *const name[] =
3584 "__aeabi_unwind_cpp_pr0",
3585 "__aeabi_unwind_cpp_pr1",
3586 "__aeabi_unwind_cpp_pr2"
3588 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3589 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3590 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3591 |= 1 << unwind.personality_index;
3595 /* Inline exception table entry. */
3596 md_number_to_chars (ptr + 4, val, 4);
3598 /* Self relative offset of the table entry. */
3599 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3600 BFD_RELOC_ARM_PREL31);
3602 /* Restore the original section. */
3603 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3605 unwind.proc_start = NULL;
3609 /* Parse an unwind_cantunwind directive. */
3612 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3614 demand_empty_rest_of_line ();
3615 if (!unwind.proc_start)
3616 as_bad (MISSING_FNSTART);
3618 if (unwind.personality_routine || unwind.personality_index != -1)
3619 as_bad (_("personality routine specified for cantunwind frame"));
3621 unwind.personality_index = -2;
3625 /* Parse a personalityindex directive. */
3628 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3632 if (!unwind.proc_start)
3633 as_bad (MISSING_FNSTART);
3635 if (unwind.personality_routine || unwind.personality_index != -1)
3636 as_bad (_("duplicate .personalityindex directive"));
3640 if (exp.X_op != O_constant
3641 || exp.X_add_number < 0 || exp.X_add_number > 15)
3643 as_bad (_("bad personality routine number"));
3644 ignore_rest_of_line ();
3648 unwind.personality_index = exp.X_add_number;
3650 demand_empty_rest_of_line ();
3654 /* Parse a personality directive. */
3657 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3661 if (!unwind.proc_start)
3662 as_bad (MISSING_FNSTART);
3664 if (unwind.personality_routine || unwind.personality_index != -1)
3665 as_bad (_("duplicate .personality directive"));
3667 name = input_line_pointer;
3668 c = get_symbol_end ();
3669 p = input_line_pointer;
3670 unwind.personality_routine = symbol_find_or_make (name);
3672 demand_empty_rest_of_line ();
3676 /* Parse a directive saving core registers. */
3679 s_arm_unwind_save_core (void)
3685 range = parse_reg_list (&input_line_pointer);
3688 as_bad (_("expected register list"));
3689 ignore_rest_of_line ();
3693 demand_empty_rest_of_line ();
3695 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3696 into .unwind_save {..., sp...}. We aren't bothered about the value of
3697 ip because it is clobbered by calls. */
3698 if (unwind.sp_restored && unwind.fp_reg == 12
3699 && (range & 0x3000) == 0x1000)
3701 unwind.opcode_count--;
3702 unwind.sp_restored = 0;
3703 range = (range | 0x2000) & ~0x1000;
3704 unwind.pending_offset = 0;
3710 /* See if we can use the short opcodes. These pop a block of up to 8
3711 registers starting with r4, plus maybe r14. */
3712 for (n = 0; n < 8; n++)
3714 /* Break at the first non-saved register. */
3715 if ((range & (1 << (n + 4))) == 0)
3718 /* See if there are any other bits set. */
3719 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3721 /* Use the long form. */
3722 op = 0x8000 | ((range >> 4) & 0xfff);
3723 add_unwind_opcode (op, 2);
3727 /* Use the short form. */
3729 op = 0xa8; /* Pop r14. */
3731 op = 0xa0; /* Do not pop r14. */
3733 add_unwind_opcode (op, 1);
3740 op = 0xb100 | (range & 0xf);
3741 add_unwind_opcode (op, 2);
3744 /* Record the number of bytes pushed. */
3745 for (n = 0; n < 16; n++)
3747 if (range & (1 << n))
3748 unwind.frame_size += 4;
3753 /* Parse a directive saving FPA registers. */
3756 s_arm_unwind_save_fpa (int reg)
3762 /* Get Number of registers to transfer. */
3763 if (skip_past_comma (&input_line_pointer) != FAIL)
3766 exp.X_op = O_illegal;
3768 if (exp.X_op != O_constant)
3770 as_bad (_("expected , <constant>"));
3771 ignore_rest_of_line ();
3775 num_regs = exp.X_add_number;
3777 if (num_regs < 1 || num_regs > 4)
3779 as_bad (_("number of registers must be in the range [1:4]"));
3780 ignore_rest_of_line ();
3784 demand_empty_rest_of_line ();
3789 op = 0xb4 | (num_regs - 1);
3790 add_unwind_opcode (op, 1);
3795 op = 0xc800 | (reg << 4) | (num_regs - 1);
3796 add_unwind_opcode (op, 2);
3798 unwind.frame_size += num_regs * 12;
3802 /* Parse a directive saving VFP registers for ARMv6 and above. */
3805 s_arm_unwind_save_vfp_armv6 (void)
3810 int num_vfpv3_regs = 0;
3811 int num_regs_below_16;
3813 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3816 as_bad (_("expected register list"));
3817 ignore_rest_of_line ();
3821 demand_empty_rest_of_line ();
3823 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3824 than FSTMX/FLDMX-style ones). */
3826 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3828 num_vfpv3_regs = count;
3829 else if (start + count > 16)
3830 num_vfpv3_regs = start + count - 16;
3832 if (num_vfpv3_regs > 0)
3834 int start_offset = start > 16 ? start - 16 : 0;
3835 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3836 add_unwind_opcode (op, 2);
3839 /* Generate opcode for registers numbered in the range 0 .. 15. */
3840 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3841 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3842 if (num_regs_below_16 > 0)
3844 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3845 add_unwind_opcode (op, 2);
3848 unwind.frame_size += count * 8;
3852 /* Parse a directive saving VFP registers for pre-ARMv6. */
3855 s_arm_unwind_save_vfp (void)
3861 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3864 as_bad (_("expected register list"));
3865 ignore_rest_of_line ();
3869 demand_empty_rest_of_line ();
3874 op = 0xb8 | (count - 1);
3875 add_unwind_opcode (op, 1);
3880 op = 0xb300 | (reg << 4) | (count - 1);
3881 add_unwind_opcode (op, 2);
3883 unwind.frame_size += count * 8 + 4;
3887 /* Parse a directive saving iWMMXt data registers. */
3890 s_arm_unwind_save_mmxwr (void)
3898 if (*input_line_pointer == '{')
3899 input_line_pointer++;
3903 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3907 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3912 as_tsktsk (_("register list not in ascending order"));
3915 if (*input_line_pointer == '-')
3917 input_line_pointer++;
3918 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3921 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3924 else if (reg >= hi_reg)
3926 as_bad (_("bad register range"));
3929 for (; reg < hi_reg; reg++)
3933 while (skip_past_comma (&input_line_pointer) != FAIL);
3935 if (*input_line_pointer == '}')
3936 input_line_pointer++;
3938 demand_empty_rest_of_line ();
3940 /* Generate any deferred opcodes because we're going to be looking at
3942 flush_pending_unwind ();
3944 for (i = 0; i < 16; i++)
3946 if (mask & (1 << i))
3947 unwind.frame_size += 8;
3950 /* Attempt to combine with a previous opcode. We do this because gcc
3951 likes to output separate unwind directives for a single block of
3953 if (unwind.opcode_count > 0)
3955 i = unwind.opcodes[unwind.opcode_count - 1];
3956 if ((i & 0xf8) == 0xc0)
3959 /* Only merge if the blocks are contiguous. */
3962 if ((mask & 0xfe00) == (1 << 9))
3964 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3965 unwind.opcode_count--;
3968 else if (i == 6 && unwind.opcode_count >= 2)
3970 i = unwind.opcodes[unwind.opcode_count - 2];
3974 op = 0xffff << (reg - 1);
3976 && ((mask & op) == (1u << (reg - 1))))
3978 op = (1 << (reg + i + 1)) - 1;
3979 op &= ~((1 << reg) - 1);
3981 unwind.opcode_count -= 2;
3988 /* We want to generate opcodes in the order the registers have been
3989 saved, ie. descending order. */
3990 for (reg = 15; reg >= -1; reg--)
3992 /* Save registers in blocks. */
3994 || !(mask & (1 << reg)))
3996 /* We found an unsaved reg. Generate opcodes to save the
4003 op = 0xc0 | (hi_reg - 10);
4004 add_unwind_opcode (op, 1);
4009 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4010 add_unwind_opcode (op, 2);
4019 ignore_rest_of_line ();
4023 s_arm_unwind_save_mmxwcg (void)
4030 if (*input_line_pointer == '{')
4031 input_line_pointer++;
4035 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4039 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4045 as_tsktsk (_("register list not in ascending order"));
4048 if (*input_line_pointer == '-')
4050 input_line_pointer++;
4051 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4054 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4057 else if (reg >= hi_reg)
4059 as_bad (_("bad register range"));
4062 for (; reg < hi_reg; reg++)
4066 while (skip_past_comma (&input_line_pointer) != FAIL);
4068 if (*input_line_pointer == '}')
4069 input_line_pointer++;
4071 demand_empty_rest_of_line ();
4073 /* Generate any deferred opcodes because we're going to be looking at
4075 flush_pending_unwind ();
4077 for (reg = 0; reg < 16; reg++)
4079 if (mask & (1 << reg))
4080 unwind.frame_size += 4;
4083 add_unwind_opcode (op, 2);
4086 ignore_rest_of_line ();
4090 /* Parse an unwind_save directive.
4091 If the argument is non-zero, this is a .vsave directive. */
4094 s_arm_unwind_save (int arch_v6)
4097 struct reg_entry *reg;
4098 bfd_boolean had_brace = FALSE;
4100 if (!unwind.proc_start)
4101 as_bad (MISSING_FNSTART);
4103 /* Figure out what sort of save we have. */
4104 peek = input_line_pointer;
4112 reg = arm_reg_parse_multi (&peek);
4116 as_bad (_("register expected"));
4117 ignore_rest_of_line ();
4126 as_bad (_("FPA .unwind_save does not take a register list"));
4127 ignore_rest_of_line ();
4130 input_line_pointer = peek;
4131 s_arm_unwind_save_fpa (reg->number);
4134 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4137 s_arm_unwind_save_vfp_armv6 ();
4139 s_arm_unwind_save_vfp ();
4141 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4142 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4145 as_bad (_(".unwind_save does not support this kind of register"));
4146 ignore_rest_of_line ();
4151 /* Parse an unwind_movsp directive. */
4154 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4160 if (!unwind.proc_start)
4161 as_bad (MISSING_FNSTART);
4163 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4166 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4167 ignore_rest_of_line ();
4171 /* Optional constant. */
4172 if (skip_past_comma (&input_line_pointer) != FAIL)
4174 if (immediate_for_directive (&offset) == FAIL)
4180 demand_empty_rest_of_line ();
4182 if (reg == REG_SP || reg == REG_PC)
4184 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4188 if (unwind.fp_reg != REG_SP)
4189 as_bad (_("unexpected .unwind_movsp directive"));
4191 /* Generate opcode to restore the value. */
4193 add_unwind_opcode (op, 1);
4195 /* Record the information for later. */
4196 unwind.fp_reg = reg;
4197 unwind.fp_offset = unwind.frame_size - offset;
4198 unwind.sp_restored = 1;
4201 /* Parse an unwind_pad directive. */
4204 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4208 if (!unwind.proc_start)
4209 as_bad (MISSING_FNSTART);
4211 if (immediate_for_directive (&offset) == FAIL)
4216 as_bad (_("stack increment must be multiple of 4"));
4217 ignore_rest_of_line ();
4221 /* Don't generate any opcodes, just record the details for later. */
4222 unwind.frame_size += offset;
4223 unwind.pending_offset += offset;
4225 demand_empty_rest_of_line ();
4228 /* Parse an unwind_setfp directive. */
4231 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4237 if (!unwind.proc_start)
4238 as_bad (MISSING_FNSTART);
4240 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4241 if (skip_past_comma (&input_line_pointer) == FAIL)
4244 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4246 if (fp_reg == FAIL || sp_reg == FAIL)
4248 as_bad (_("expected <reg>, <reg>"));
4249 ignore_rest_of_line ();
4253 /* Optional constant. */
4254 if (skip_past_comma (&input_line_pointer) != FAIL)
4256 if (immediate_for_directive (&offset) == FAIL)
4262 demand_empty_rest_of_line ();
4264 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4266 as_bad (_("register must be either sp or set by a previous"
4267 "unwind_movsp directive"));
4271 /* Don't generate any opcodes, just record the information for later. */
4272 unwind.fp_reg = fp_reg;
4274 if (sp_reg == REG_SP)
4275 unwind.fp_offset = unwind.frame_size - offset;
4277 unwind.fp_offset -= offset;
4280 /* Parse an unwind_raw directive. */
4283 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4286 /* This is an arbitrary limit. */
4287 unsigned char op[16];
4290 if (!unwind.proc_start)
4291 as_bad (MISSING_FNSTART);
4294 if (exp.X_op == O_constant
4295 && skip_past_comma (&input_line_pointer) != FAIL)
4297 unwind.frame_size += exp.X_add_number;
4301 exp.X_op = O_illegal;
4303 if (exp.X_op != O_constant)
4305 as_bad (_("expected <offset>, <opcode>"));
4306 ignore_rest_of_line ();
4312 /* Parse the opcode. */
4317 as_bad (_("unwind opcode too long"));
4318 ignore_rest_of_line ();
4320 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4322 as_bad (_("invalid unwind opcode"));
4323 ignore_rest_of_line ();
4326 op[count++] = exp.X_add_number;
4328 /* Parse the next byte. */
4329 if (skip_past_comma (&input_line_pointer) == FAIL)
4335 /* Add the opcode bytes in reverse order. */
4337 add_unwind_opcode (op[count], 1);
4339 demand_empty_rest_of_line ();
4343 /* Parse a .eabi_attribute directive. */
4346 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4348 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4350 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4351 attributes_set_explicitly[tag] = 1;
4354 /* Emit a tls fix for the symbol. */
4357 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4361 #ifdef md_flush_pending_output
4362 md_flush_pending_output ();
4365 #ifdef md_cons_align
4369 /* Since we're just labelling the code, there's no need to define a
4372 p = obstack_next_free (&frchain_now->frch_obstack);
4373 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4374 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4375 : BFD_RELOC_ARM_TLS_DESCSEQ);
4377 #endif /* OBJ_ELF */
4379 static void s_arm_arch (int);
4380 static void s_arm_object_arch (int);
4381 static void s_arm_cpu (int);
4382 static void s_arm_fpu (int);
4383 static void s_arm_arch_extension (int);
4388 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4395 if (exp.X_op == O_symbol)
4396 exp.X_op = O_secrel;
4398 emit_expr (&exp, 4);
4400 while (*input_line_pointer++ == ',');
4402 input_line_pointer--;
4403 demand_empty_rest_of_line ();
4407 /* This table describes all the machine specific pseudo-ops the assembler
4408 has to support. The fields are:
4409 pseudo-op name without dot
4410 function to call to execute this pseudo-op
4411 Integer arg to pass to the function. */
4413 const pseudo_typeS md_pseudo_table[] =
4415 /* Never called because '.req' does not start a line. */
4416 { "req", s_req, 0 },
4417 /* Following two are likewise never called. */
4420 { "unreq", s_unreq, 0 },
4421 { "bss", s_bss, 0 },
4422 { "align", s_align, 0 },
4423 { "arm", s_arm, 0 },
4424 { "thumb", s_thumb, 0 },
4425 { "code", s_code, 0 },
4426 { "force_thumb", s_force_thumb, 0 },
4427 { "thumb_func", s_thumb_func, 0 },
4428 { "thumb_set", s_thumb_set, 0 },
4429 { "even", s_even, 0 },
4430 { "ltorg", s_ltorg, 0 },
4431 { "pool", s_ltorg, 0 },
4432 { "syntax", s_syntax, 0 },
4433 { "cpu", s_arm_cpu, 0 },
4434 { "arch", s_arm_arch, 0 },
4435 { "object_arch", s_arm_object_arch, 0 },
4436 { "fpu", s_arm_fpu, 0 },
4437 { "arch_extension", s_arm_arch_extension, 0 },
4439 { "word", s_arm_elf_cons, 4 },
4440 { "long", s_arm_elf_cons, 4 },
4441 { "inst.n", s_arm_elf_inst, 2 },
4442 { "inst.w", s_arm_elf_inst, 4 },
4443 { "inst", s_arm_elf_inst, 0 },
4444 { "rel31", s_arm_rel31, 0 },
4445 { "fnstart", s_arm_unwind_fnstart, 0 },
4446 { "fnend", s_arm_unwind_fnend, 0 },
4447 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4448 { "personality", s_arm_unwind_personality, 0 },
4449 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4450 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4451 { "save", s_arm_unwind_save, 0 },
4452 { "vsave", s_arm_unwind_save, 1 },
4453 { "movsp", s_arm_unwind_movsp, 0 },
4454 { "pad", s_arm_unwind_pad, 0 },
4455 { "setfp", s_arm_unwind_setfp, 0 },
4456 { "unwind_raw", s_arm_unwind_raw, 0 },
4457 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4458 { "tlsdescseq", s_arm_tls_descseq, 0 },
4462 /* These are used for dwarf. */
4466 /* These are used for dwarf2. */
4467 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4468 { "loc", dwarf2_directive_loc, 0 },
4469 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4471 { "extend", float_cons, 'x' },
4472 { "ldouble", float_cons, 'x' },
4473 { "packed", float_cons, 'p' },
4475 {"secrel32", pe_directive_secrel, 0},
4480 /* Parser functions used exclusively in instruction operands. */
4482 /* Generic immediate-value read function for use in insn parsing.
4483 STR points to the beginning of the immediate (the leading #);
4484 VAL receives the value; if the value is outside [MIN, MAX]
4485 issue an error. PREFIX_OPT is true if the immediate prefix is
4489 parse_immediate (char **str, int *val, int min, int max,
4490 bfd_boolean prefix_opt)
4493 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4494 if (exp.X_op != O_constant)
4496 inst.error = _("constant expression required");
4500 if (exp.X_add_number < min || exp.X_add_number > max)
4502 inst.error = _("immediate value out of range");
4506 *val = exp.X_add_number;
4510 /* Less-generic immediate-value read function with the possibility of loading a
4511 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4512 instructions. Puts the result directly in inst.operands[i]. */
4515 parse_big_immediate (char **str, int i)
4520 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4522 if (exp.X_op == O_constant)
4524 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4525 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4526 O_constant. We have to be careful not to break compilation for
4527 32-bit X_add_number, though. */
4528 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4530 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4531 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4532 inst.operands[i].regisimm = 1;
4535 else if (exp.X_op == O_big
4536 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4538 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4540 /* Bignums have their least significant bits in
4541 generic_bignum[0]. Make sure we put 32 bits in imm and
4542 32 bits in reg, in a (hopefully) portable way. */
4543 gas_assert (parts != 0);
4545 /* Make sure that the number is not too big.
4546 PR 11972: Bignums can now be sign-extended to the
4547 size of a .octa so check that the out of range bits
4548 are all zero or all one. */
4549 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4551 LITTLENUM_TYPE m = -1;
4553 if (generic_bignum[parts * 2] != 0
4554 && generic_bignum[parts * 2] != m)
4557 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4558 if (generic_bignum[j] != generic_bignum[j-1])
4562 inst.operands[i].imm = 0;
4563 for (j = 0; j < parts; j++, idx++)
4564 inst.operands[i].imm |= generic_bignum[idx]
4565 << (LITTLENUM_NUMBER_OF_BITS * j);
4566 inst.operands[i].reg = 0;
4567 for (j = 0; j < parts; j++, idx++)
4568 inst.operands[i].reg |= generic_bignum[idx]
4569 << (LITTLENUM_NUMBER_OF_BITS * j);
4570 inst.operands[i].regisimm = 1;
4580 /* Returns the pseudo-register number of an FPA immediate constant,
4581 or FAIL if there isn't a valid constant here. */
4584 parse_fpa_immediate (char ** str)
4586 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4592 /* First try and match exact strings, this is to guarantee
4593 that some formats will work even for cross assembly. */
4595 for (i = 0; fp_const[i]; i++)
4597 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4601 *str += strlen (fp_const[i]);
4602 if (is_end_of_line[(unsigned char) **str])
4608 /* Just because we didn't get a match doesn't mean that the constant
4609 isn't valid, just that it is in a format that we don't
4610 automatically recognize. Try parsing it with the standard
4611 expression routines. */
4613 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4615 /* Look for a raw floating point number. */
4616 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4617 && is_end_of_line[(unsigned char) *save_in])
4619 for (i = 0; i < NUM_FLOAT_VALS; i++)
4621 for (j = 0; j < MAX_LITTLENUMS; j++)
4623 if (words[j] != fp_values[i][j])
4627 if (j == MAX_LITTLENUMS)
4635 /* Try and parse a more complex expression, this will probably fail
4636 unless the code uses a floating point prefix (eg "0f"). */
4637 save_in = input_line_pointer;
4638 input_line_pointer = *str;
4639 if (expression (&exp) == absolute_section
4640 && exp.X_op == O_big
4641 && exp.X_add_number < 0)
4643 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4645 if (gen_to_words (words, 5, (long) 15) == 0)
4647 for (i = 0; i < NUM_FLOAT_VALS; i++)
4649 for (j = 0; j < MAX_LITTLENUMS; j++)
4651 if (words[j] != fp_values[i][j])
4655 if (j == MAX_LITTLENUMS)
4657 *str = input_line_pointer;
4658 input_line_pointer = save_in;
4665 *str = input_line_pointer;
4666 input_line_pointer = save_in;
4667 inst.error = _("invalid FPA immediate expression");
4671 /* Returns 1 if a number has "quarter-precision" float format
4672 0baBbbbbbc defgh000 00000000 00000000. */
4675 is_quarter_float (unsigned imm)
4677 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4678 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4681 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4682 0baBbbbbbc defgh000 00000000 00000000.
4683 The zero and minus-zero cases need special handling, since they can't be
4684 encoded in the "quarter-precision" float format, but can nonetheless be
4685 loaded as integer constants. */
4688 parse_qfloat_immediate (char **ccp, int *immed)
4692 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4693 int found_fpchar = 0;
4695 skip_past_char (&str, '#');
4697 /* We must not accidentally parse an integer as a floating-point number. Make
4698 sure that the value we parse is not an integer by checking for special
4699 characters '.' or 'e'.
4700 FIXME: This is a horrible hack, but doing better is tricky because type
4701 information isn't in a very usable state at parse time. */
4703 skip_whitespace (fpnum);
4705 if (strncmp (fpnum, "0x", 2) == 0)
4709 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4710 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4720 if ((str = atof_ieee (str, 's', words)) != NULL)
4722 unsigned fpword = 0;
4725 /* Our FP word must be 32 bits (single-precision FP). */
4726 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4728 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4732 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4745 /* Shift operands. */
4748 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4751 struct asm_shift_name
4754 enum shift_kind kind;
4757 /* Third argument to parse_shift. */
4758 enum parse_shift_mode
4760 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4761 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4762 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4763 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4764 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4767 /* Parse a <shift> specifier on an ARM data processing instruction.
4768 This has three forms:
4770 (LSL|LSR|ASL|ASR|ROR) Rs
4771 (LSL|LSR|ASL|ASR|ROR) #imm
4774 Note that ASL is assimilated to LSL in the instruction encoding, and
4775 RRX to ROR #0 (which cannot be written as such). */
4778 parse_shift (char **str, int i, enum parse_shift_mode mode)
4780 const struct asm_shift_name *shift_name;
4781 enum shift_kind shift;
4786 for (p = *str; ISALPHA (*p); p++)
4791 inst.error = _("shift expression expected");
4795 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4798 if (shift_name == NULL)
4800 inst.error = _("shift expression expected");
4804 shift = shift_name->kind;
4808 case NO_SHIFT_RESTRICT:
4809 case SHIFT_IMMEDIATE: break;
4811 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4812 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4814 inst.error = _("'LSL' or 'ASR' required");
4819 case SHIFT_LSL_IMMEDIATE:
4820 if (shift != SHIFT_LSL)
4822 inst.error = _("'LSL' required");
4827 case SHIFT_ASR_IMMEDIATE:
4828 if (shift != SHIFT_ASR)
4830 inst.error = _("'ASR' required");
4838 if (shift != SHIFT_RRX)
4840 /* Whitespace can appear here if the next thing is a bare digit. */
4841 skip_whitespace (p);
4843 if (mode == NO_SHIFT_RESTRICT
4844 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4846 inst.operands[i].imm = reg;
4847 inst.operands[i].immisreg = 1;
4849 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4852 inst.operands[i].shift_kind = shift;
4853 inst.operands[i].shifted = 1;
4858 /* Parse a <shifter_operand> for an ARM data processing instruction:
4861 #<immediate>, <rotate>
4865 where <shift> is defined by parse_shift above, and <rotate> is a
4866 multiple of 2 between 0 and 30. Validation of immediate operands
4867 is deferred to md_apply_fix. */
4870 parse_shifter_operand (char **str, int i)
4875 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4877 inst.operands[i].reg = value;
4878 inst.operands[i].isreg = 1;
4880 /* parse_shift will override this if appropriate */
4881 inst.reloc.exp.X_op = O_constant;
4882 inst.reloc.exp.X_add_number = 0;
4884 if (skip_past_comma (str) == FAIL)
4887 /* Shift operation on register. */
4888 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4891 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4894 if (skip_past_comma (str) == SUCCESS)
4896 /* #x, y -- ie explicit rotation by Y. */
4897 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4900 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4902 inst.error = _("constant expression expected");
4906 value = exp.X_add_number;
4907 if (value < 0 || value > 30 || value % 2 != 0)
4909 inst.error = _("invalid rotation");
4912 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4914 inst.error = _("invalid constant");
4918 /* Encode as specified. */
4919 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4923 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4924 inst.reloc.pc_rel = 0;
4928 /* Group relocation information. Each entry in the table contains the
4929 textual name of the relocation as may appear in assembler source
4930 and must end with a colon.
4931 Along with this textual name are the relocation codes to be used if
4932 the corresponding instruction is an ALU instruction (ADD or SUB only),
4933 an LDR, an LDRS, or an LDC. */
4935 struct group_reloc_table_entry
4946 /* Varieties of non-ALU group relocation. */
4953 static struct group_reloc_table_entry group_reloc_table[] =
4954 { /* Program counter relative: */
4956 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4962 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4963 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4964 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4971 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4972 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4973 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4974 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4976 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4977 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4978 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4979 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4980 /* Section base relative */
4982 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4987 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4988 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4989 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4990 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4992 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4997 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4998 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4999 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5000 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5002 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5003 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5004 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5005 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5007 /* Given the address of a pointer pointing to the textual name of a group
5008 relocation as may appear in assembler source, attempt to find its details
5009 in group_reloc_table. The pointer will be updated to the character after
5010 the trailing colon. On failure, FAIL will be returned; SUCCESS
5011 otherwise. On success, *entry will be updated to point at the relevant
5012 group_reloc_table entry. */
5015 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5018 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5020 int length = strlen (group_reloc_table[i].name);
5022 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5023 && (*str)[length] == ':')
5025 *out = &group_reloc_table[i];
5026 *str += (length + 1);
5034 /* Parse a <shifter_operand> for an ARM data processing instruction
5035 (as for parse_shifter_operand) where group relocations are allowed:
5038 #<immediate>, <rotate>
5039 #:<group_reloc>:<expression>
5043 where <group_reloc> is one of the strings defined in group_reloc_table.
5044 The hashes are optional.
5046 Everything else is as for parse_shifter_operand. */
5048 static parse_operand_result
5049 parse_shifter_operand_group_reloc (char **str, int i)
5051 /* Determine if we have the sequence of characters #: or just :
5052 coming next. If we do, then we check for a group relocation.
5053 If we don't, punt the whole lot to parse_shifter_operand. */
5055 if (((*str)[0] == '#' && (*str)[1] == ':')
5056 || (*str)[0] == ':')
5058 struct group_reloc_table_entry *entry;
5060 if ((*str)[0] == '#')
5065 /* Try to parse a group relocation. Anything else is an error. */
5066 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5068 inst.error = _("unknown group relocation");
5069 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5072 /* We now have the group relocation table entry corresponding to
5073 the name in the assembler source. Next, we parse the expression. */
5074 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5075 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5077 /* Record the relocation type (always the ALU variant here). */
5078 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5079 gas_assert (inst.reloc.type != 0);
5081 return PARSE_OPERAND_SUCCESS;
5084 return parse_shifter_operand (str, i) == SUCCESS
5085 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5087 /* Never reached. */
5090 /* Parse a Neon alignment expression. Information is written to
5091 inst.operands[i]. We assume the initial ':' has been skipped.
5093 align .imm = align << 8, .immisalign=1, .preind=0 */
5094 static parse_operand_result
5095 parse_neon_alignment (char **str, int i)
5100 my_get_expression (&exp, &p, GE_NO_PREFIX);
5102 if (exp.X_op != O_constant)
5104 inst.error = _("alignment must be constant");
5105 return PARSE_OPERAND_FAIL;
5108 inst.operands[i].imm = exp.X_add_number << 8;
5109 inst.operands[i].immisalign = 1;
5110 /* Alignments are not pre-indexes. */
5111 inst.operands[i].preind = 0;
5114 return PARSE_OPERAND_SUCCESS;
5117 /* Parse all forms of an ARM address expression. Information is written
5118 to inst.operands[i] and/or inst.reloc.
5120 Preindexed addressing (.preind=1):
5122 [Rn, #offset] .reg=Rn .reloc.exp=offset
5123 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5124 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5125 .shift_kind=shift .reloc.exp=shift_imm
5127 These three may have a trailing ! which causes .writeback to be set also.
5129 Postindexed addressing (.postind=1, .writeback=1):
5131 [Rn], #offset .reg=Rn .reloc.exp=offset
5132 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5133 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5134 .shift_kind=shift .reloc.exp=shift_imm
5136 Unindexed addressing (.preind=0, .postind=0):
5138 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5142 [Rn]{!} shorthand for [Rn,#0]{!}
5143 =immediate .isreg=0 .reloc.exp=immediate
5144 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5146 It is the caller's responsibility to check for addressing modes not
5147 supported by the instruction, and to set inst.reloc.type. */
5149 static parse_operand_result
5150 parse_address_main (char **str, int i, int group_relocations,
5151 group_reloc_type group_type)
5156 if (skip_past_char (&p, '[') == FAIL)
5158 if (skip_past_char (&p, '=') == FAIL)
5160 /* Bare address - translate to PC-relative offset. */
5161 inst.reloc.pc_rel = 1;
5162 inst.operands[i].reg = REG_PC;
5163 inst.operands[i].isreg = 1;
5164 inst.operands[i].preind = 1;
5166 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5168 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5169 return PARSE_OPERAND_FAIL;
5172 return PARSE_OPERAND_SUCCESS;
5175 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5176 skip_whitespace (p);
5178 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5180 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5181 return PARSE_OPERAND_FAIL;
5183 inst.operands[i].reg = reg;
5184 inst.operands[i].isreg = 1;
5186 if (skip_past_comma (&p) == SUCCESS)
5188 inst.operands[i].preind = 1;
5191 else if (*p == '-') p++, inst.operands[i].negative = 1;
5193 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5195 inst.operands[i].imm = reg;
5196 inst.operands[i].immisreg = 1;
5198 if (skip_past_comma (&p) == SUCCESS)
5199 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5200 return PARSE_OPERAND_FAIL;
5202 else if (skip_past_char (&p, ':') == SUCCESS)
5204 /* FIXME: '@' should be used here, but it's filtered out by generic
5205 code before we get to see it here. This may be subject to
5207 parse_operand_result result = parse_neon_alignment (&p, i);
5209 if (result != PARSE_OPERAND_SUCCESS)
5214 if (inst.operands[i].negative)
5216 inst.operands[i].negative = 0;
5220 if (group_relocations
5221 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5223 struct group_reloc_table_entry *entry;
5225 /* Skip over the #: or : sequence. */
5231 /* Try to parse a group relocation. Anything else is an
5233 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5235 inst.error = _("unknown group relocation");
5236 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5239 /* We now have the group relocation table entry corresponding to
5240 the name in the assembler source. Next, we parse the
5242 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5243 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5245 /* Record the relocation type. */
5249 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5253 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5257 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5264 if (inst.reloc.type == 0)
5266 inst.error = _("this group relocation is not allowed on this instruction");
5267 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5273 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5274 return PARSE_OPERAND_FAIL;
5275 /* If the offset is 0, find out if it's a +0 or -0. */
5276 if (inst.reloc.exp.X_op == O_constant
5277 && inst.reloc.exp.X_add_number == 0)
5279 skip_whitespace (q);
5283 skip_whitespace (q);
5286 inst.operands[i].negative = 1;
5291 else if (skip_past_char (&p, ':') == SUCCESS)
5293 /* FIXME: '@' should be used here, but it's filtered out by generic code
5294 before we get to see it here. This may be subject to change. */
5295 parse_operand_result result = parse_neon_alignment (&p, i);
5297 if (result != PARSE_OPERAND_SUCCESS)
5301 if (skip_past_char (&p, ']') == FAIL)
5303 inst.error = _("']' expected");
5304 return PARSE_OPERAND_FAIL;
5307 if (skip_past_char (&p, '!') == SUCCESS)
5308 inst.operands[i].writeback = 1;
5310 else if (skip_past_comma (&p) == SUCCESS)
5312 if (skip_past_char (&p, '{') == SUCCESS)
5314 /* [Rn], {expr} - unindexed, with option */
5315 if (parse_immediate (&p, &inst.operands[i].imm,
5316 0, 255, TRUE) == FAIL)
5317 return PARSE_OPERAND_FAIL;
5319 if (skip_past_char (&p, '}') == FAIL)
5321 inst.error = _("'}' expected at end of 'option' field");
5322 return PARSE_OPERAND_FAIL;
5324 if (inst.operands[i].preind)
5326 inst.error = _("cannot combine index with option");
5327 return PARSE_OPERAND_FAIL;
5330 return PARSE_OPERAND_SUCCESS;
5334 inst.operands[i].postind = 1;
5335 inst.operands[i].writeback = 1;
5337 if (inst.operands[i].preind)
5339 inst.error = _("cannot combine pre- and post-indexing");
5340 return PARSE_OPERAND_FAIL;
5344 else if (*p == '-') p++, inst.operands[i].negative = 1;
5346 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5348 /* We might be using the immediate for alignment already. If we
5349 are, OR the register number into the low-order bits. */
5350 if (inst.operands[i].immisalign)
5351 inst.operands[i].imm |= reg;
5353 inst.operands[i].imm = reg;
5354 inst.operands[i].immisreg = 1;
5356 if (skip_past_comma (&p) == SUCCESS)
5357 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5358 return PARSE_OPERAND_FAIL;
5363 if (inst.operands[i].negative)
5365 inst.operands[i].negative = 0;
5368 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5369 return PARSE_OPERAND_FAIL;
5370 /* If the offset is 0, find out if it's a +0 or -0. */
5371 if (inst.reloc.exp.X_op == O_constant
5372 && inst.reloc.exp.X_add_number == 0)
5374 skip_whitespace (q);
5378 skip_whitespace (q);
5381 inst.operands[i].negative = 1;
5387 /* If at this point neither .preind nor .postind is set, we have a
5388 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5389 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5391 inst.operands[i].preind = 1;
5392 inst.reloc.exp.X_op = O_constant;
5393 inst.reloc.exp.X_add_number = 0;
5396 return PARSE_OPERAND_SUCCESS;
5400 parse_address (char **str, int i)
5402 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5406 static parse_operand_result
5407 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5409 return parse_address_main (str, i, 1, type);
5412 /* Parse an operand for a MOVW or MOVT instruction. */
5414 parse_half (char **str)
5419 skip_past_char (&p, '#');
5420 if (strncasecmp (p, ":lower16:", 9) == 0)
5421 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5422 else if (strncasecmp (p, ":upper16:", 9) == 0)
5423 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5425 if (inst.reloc.type != BFD_RELOC_UNUSED)
5428 skip_whitespace (p);
5431 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5434 if (inst.reloc.type == BFD_RELOC_UNUSED)
5436 if (inst.reloc.exp.X_op != O_constant)
5438 inst.error = _("constant expression expected");
5441 if (inst.reloc.exp.X_add_number < 0
5442 || inst.reloc.exp.X_add_number > 0xffff)
5444 inst.error = _("immediate value out of range");
5452 /* Miscellaneous. */
5454 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5455 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5457 parse_psr (char **str, bfd_boolean lhs)
5460 unsigned long psr_field;
5461 const struct asm_psr *psr;
5463 bfd_boolean is_apsr = FALSE;
5464 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5466 /* PR gas/12698: If the user has specified -march=all then m_profile will
5467 be TRUE, but we want to ignore it in this case as we are building for any
5468 CPU type, including non-m variants. */
5469 if (selected_cpu.core == arm_arch_any.core)
5472 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5473 feature for ease of use and backwards compatibility. */
5475 if (strncasecmp (p, "SPSR", 4) == 0)
5478 goto unsupported_psr;
5480 psr_field = SPSR_BIT;
5482 else if (strncasecmp (p, "CPSR", 4) == 0)
5485 goto unsupported_psr;
5489 else if (strncasecmp (p, "APSR", 4) == 0)
5491 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5492 and ARMv7-R architecture CPUs. */
5501 while (ISALNUM (*p) || *p == '_');
5503 if (strncasecmp (start, "iapsr", 5) == 0
5504 || strncasecmp (start, "eapsr", 5) == 0
5505 || strncasecmp (start, "xpsr", 4) == 0
5506 || strncasecmp (start, "psr", 3) == 0)
5507 p = start + strcspn (start, "rR") + 1;
5509 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5515 /* If APSR is being written, a bitfield may be specified. Note that
5516 APSR itself is handled above. */
5517 if (psr->field <= 3)
5519 psr_field = psr->field;
5525 /* M-profile MSR instructions have the mask field set to "10", except
5526 *PSR variants which modify APSR, which may use a different mask (and
5527 have been handled already). Do that by setting the PSR_f field
5529 return psr->field | (lhs ? PSR_f : 0);
5532 goto unsupported_psr;
5538 /* A suffix follows. */
5544 while (ISALNUM (*p) || *p == '_');
5548 /* APSR uses a notation for bits, rather than fields. */
5549 unsigned int nzcvq_bits = 0;
5550 unsigned int g_bit = 0;
5553 for (bit = start; bit != p; bit++)
5555 switch (TOLOWER (*bit))
5558 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5562 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5566 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5570 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5574 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5578 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5582 inst.error = _("unexpected bit specified after APSR");
5587 if (nzcvq_bits == 0x1f)
5592 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5594 inst.error = _("selected processor does not "
5595 "support DSP extension");
5602 if ((nzcvq_bits & 0x20) != 0
5603 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5604 || (g_bit & 0x2) != 0)
5606 inst.error = _("bad bitmask specified after APSR");
5612 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5617 psr_field |= psr->field;
5623 goto error; /* Garbage after "[CS]PSR". */
5625 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5626 is deprecated, but allow it anyway. */
5630 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5633 else if (!m_profile)
5634 /* These bits are never right for M-profile devices: don't set them
5635 (only code paths which read/write APSR reach here). */
5636 psr_field |= (PSR_c | PSR_f);
5642 inst.error = _("selected processor does not support requested special "
5643 "purpose register");
5647 inst.error = _("flag for {c}psr instruction expected");
5651 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5652 value suitable for splatting into the AIF field of the instruction. */
5655 parse_cps_flags (char **str)
5664 case '\0': case ',':
5667 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5668 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5669 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5672 inst.error = _("unrecognized CPS flag");
5677 if (saw_a_flag == 0)
5679 inst.error = _("missing CPS flags");
5687 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5688 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5691 parse_endian_specifier (char **str)
5696 if (strncasecmp (s, "BE", 2))
5698 else if (strncasecmp (s, "LE", 2))
5702 inst.error = _("valid endian specifiers are be or le");
5706 if (ISALNUM (s[2]) || s[2] == '_')
5708 inst.error = _("valid endian specifiers are be or le");
5713 return little_endian;
5716 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5717 value suitable for poking into the rotate field of an sxt or sxta
5718 instruction, or FAIL on error. */
5721 parse_ror (char **str)
5726 if (strncasecmp (s, "ROR", 3) == 0)
5730 inst.error = _("missing rotation field after comma");
5734 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5739 case 0: *str = s; return 0x0;
5740 case 8: *str = s; return 0x1;
5741 case 16: *str = s; return 0x2;
5742 case 24: *str = s; return 0x3;
5745 inst.error = _("rotation can only be 0, 8, 16, or 24");
5750 /* Parse a conditional code (from conds[] below). The value returned is in the
5751 range 0 .. 14, or FAIL. */
5753 parse_cond (char **str)
5756 const struct asm_cond *c;
5758 /* Condition codes are always 2 characters, so matching up to
5759 3 characters is sufficient. */
5764 while (ISALPHA (*q) && n < 3)
5766 cond[n] = TOLOWER (*q);
5771 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5774 inst.error = _("condition required");
5782 /* If the given feature available in the selected CPU, mark it as used.
5783 Returns TRUE iff feature is available. */
5785 mark_feature_used (const arm_feature_set *feature)
5787 /* Ensure the option is valid on the current architecture. */
5788 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5791 /* Add the appropriate architecture feature for the barrier option used.
5794 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5796 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5801 /* Parse an option for a barrier instruction. Returns the encoding for the
5804 parse_barrier (char **str)
5807 const struct asm_barrier_opt *o;
5810 while (ISALPHA (*q))
5813 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5818 if (!mark_feature_used (&o->arch))
5825 /* Parse the operands of a table branch instruction. Similar to a memory
5828 parse_tb (char **str)
5833 if (skip_past_char (&p, '[') == FAIL)
5835 inst.error = _("'[' expected");
5839 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5841 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5844 inst.operands[0].reg = reg;
5846 if (skip_past_comma (&p) == FAIL)
5848 inst.error = _("',' expected");
5852 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5854 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5857 inst.operands[0].imm = reg;
5859 if (skip_past_comma (&p) == SUCCESS)
5861 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5863 if (inst.reloc.exp.X_add_number != 1)
5865 inst.error = _("invalid shift");
5868 inst.operands[0].shifted = 1;
5871 if (skip_past_char (&p, ']') == FAIL)
5873 inst.error = _("']' expected");
5880 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5881 information on the types the operands can take and how they are encoded.
5882 Up to four operands may be read; this function handles setting the
5883 ".present" field for each read operand itself.
5884 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5885 else returns FAIL. */
5888 parse_neon_mov (char **str, int *which_operand)
5890 int i = *which_operand, val;
5891 enum arm_reg_type rtype;
5893 struct neon_type_el optype;
5895 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5897 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5898 inst.operands[i].reg = val;
5899 inst.operands[i].isscalar = 1;
5900 inst.operands[i].vectype = optype;
5901 inst.operands[i++].present = 1;
5903 if (skip_past_comma (&ptr) == FAIL)
5906 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5909 inst.operands[i].reg = val;
5910 inst.operands[i].isreg = 1;
5911 inst.operands[i].present = 1;
5913 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5916 /* Cases 0, 1, 2, 3, 5 (D only). */
5917 if (skip_past_comma (&ptr) == FAIL)
5920 inst.operands[i].reg = val;
5921 inst.operands[i].isreg = 1;
5922 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5923 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5924 inst.operands[i].isvec = 1;
5925 inst.operands[i].vectype = optype;
5926 inst.operands[i++].present = 1;
5928 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5930 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5931 Case 13: VMOV <Sd>, <Rm> */
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i].present = 1;
5936 if (rtype == REG_TYPE_NQ)
5938 first_error (_("can't use Neon quad register here"));
5941 else if (rtype != REG_TYPE_VFS)
5944 if (skip_past_comma (&ptr) == FAIL)
5946 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5948 inst.operands[i].reg = val;
5949 inst.operands[i].isreg = 1;
5950 inst.operands[i].present = 1;
5953 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5956 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5957 Case 1: VMOV<c><q> <Dd>, <Dm>
5958 Case 8: VMOV.F32 <Sd>, <Sm>
5959 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5961 inst.operands[i].reg = val;
5962 inst.operands[i].isreg = 1;
5963 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5964 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5965 inst.operands[i].isvec = 1;
5966 inst.operands[i].vectype = optype;
5967 inst.operands[i].present = 1;
5969 if (skip_past_comma (&ptr) == SUCCESS)
5974 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5977 inst.operands[i].reg = val;
5978 inst.operands[i].isreg = 1;
5979 inst.operands[i++].present = 1;
5981 if (skip_past_comma (&ptr) == FAIL)
5984 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5987 inst.operands[i].reg = val;
5988 inst.operands[i].isreg = 1;
5989 inst.operands[i].present = 1;
5992 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5993 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5994 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5995 Case 10: VMOV.F32 <Sd>, #<imm>
5996 Case 11: VMOV.F64 <Dd>, #<imm> */
5997 inst.operands[i].immisfloat = 1;
5998 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5999 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6000 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6004 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6008 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6011 inst.operands[i].reg = val;
6012 inst.operands[i].isreg = 1;
6013 inst.operands[i++].present = 1;
6015 if (skip_past_comma (&ptr) == FAIL)
6018 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6020 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6021 inst.operands[i].reg = val;
6022 inst.operands[i].isscalar = 1;
6023 inst.operands[i].present = 1;
6024 inst.operands[i].vectype = optype;
6026 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6028 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6029 inst.operands[i].reg = val;
6030 inst.operands[i].isreg = 1;
6031 inst.operands[i++].present = 1;
6033 if (skip_past_comma (&ptr) == FAIL)
6036 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6039 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6043 inst.operands[i].reg = val;
6044 inst.operands[i].isreg = 1;
6045 inst.operands[i].isvec = 1;
6046 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6047 inst.operands[i].vectype = optype;
6048 inst.operands[i].present = 1;
6050 if (rtype == REG_TYPE_VFS)
6054 if (skip_past_comma (&ptr) == FAIL)
6056 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6059 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6062 inst.operands[i].reg = val;
6063 inst.operands[i].isreg = 1;
6064 inst.operands[i].isvec = 1;
6065 inst.operands[i].issingle = 1;
6066 inst.operands[i].vectype = optype;
6067 inst.operands[i].present = 1;
6070 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6074 inst.operands[i].reg = val;
6075 inst.operands[i].isreg = 1;
6076 inst.operands[i].isvec = 1;
6077 inst.operands[i].issingle = 1;
6078 inst.operands[i].vectype = optype;
6079 inst.operands[i].present = 1;
6084 first_error (_("parse error"));
6088 /* Successfully parsed the operands. Update args. */
6094 first_error (_("expected comma"));
6098 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6102 /* Use this macro when the operand constraints are different
6103 for ARM and THUMB (e.g. ldrd). */
6104 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6105 ((arm_operand) | ((thumb_operand) << 16))
6107 /* Matcher codes for parse_operands. */
6108 enum operand_parse_code
6110 OP_stop, /* end of line */
6112 OP_RR, /* ARM register */
6113 OP_RRnpc, /* ARM register, not r15 */
6114 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6115 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6116 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6117 optional trailing ! */
6118 OP_RRw, /* ARM register, not r15, optional trailing ! */
6119 OP_RCP, /* Coprocessor number */
6120 OP_RCN, /* Coprocessor register */
6121 OP_RF, /* FPA register */
6122 OP_RVS, /* VFP single precision register */
6123 OP_RVD, /* VFP double precision register (0..15) */
6124 OP_RND, /* Neon double precision register (0..31) */
6125 OP_RNQ, /* Neon quad precision register */
6126 OP_RVSD, /* VFP single or double precision register */
6127 OP_RNDQ, /* Neon double or quad precision register */
6128 OP_RNSDQ, /* Neon single, double or quad precision register */
6129 OP_RNSC, /* Neon scalar D[X] */
6130 OP_RVC, /* VFP control register */
6131 OP_RMF, /* Maverick F register */
6132 OP_RMD, /* Maverick D register */
6133 OP_RMFX, /* Maverick FX register */
6134 OP_RMDX, /* Maverick DX register */
6135 OP_RMAX, /* Maverick AX register */
6136 OP_RMDS, /* Maverick DSPSC register */
6137 OP_RIWR, /* iWMMXt wR register */
6138 OP_RIWC, /* iWMMXt wC register */
6139 OP_RIWG, /* iWMMXt wCG register */
6140 OP_RXA, /* XScale accumulator register */
6142 OP_REGLST, /* ARM register list */
6143 OP_VRSLST, /* VFP single-precision register list */
6144 OP_VRDLST, /* VFP double-precision register list */
6145 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6146 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6147 OP_NSTRLST, /* Neon element/structure list */
6149 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6150 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6151 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6152 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6153 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6154 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6155 OP_VMOV, /* Neon VMOV operands. */
6156 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6157 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6158 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6160 OP_I0, /* immediate zero */
6161 OP_I7, /* immediate value 0 .. 7 */
6162 OP_I15, /* 0 .. 15 */
6163 OP_I16, /* 1 .. 16 */
6164 OP_I16z, /* 0 .. 16 */
6165 OP_I31, /* 0 .. 31 */
6166 OP_I31w, /* 0 .. 31, optional trailing ! */
6167 OP_I32, /* 1 .. 32 */
6168 OP_I32z, /* 0 .. 32 */
6169 OP_I63, /* 0 .. 63 */
6170 OP_I63s, /* -64 .. 63 */
6171 OP_I64, /* 1 .. 64 */
6172 OP_I64z, /* 0 .. 64 */
6173 OP_I255, /* 0 .. 255 */
6175 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6176 OP_I7b, /* 0 .. 7 */
6177 OP_I15b, /* 0 .. 15 */
6178 OP_I31b, /* 0 .. 31 */
6180 OP_SH, /* shifter operand */
6181 OP_SHG, /* shifter operand with possible group relocation */
6182 OP_ADDR, /* Memory address expression (any mode) */
6183 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6184 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6185 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6186 OP_EXP, /* arbitrary expression */
6187 OP_EXPi, /* same, with optional immediate prefix */
6188 OP_EXPr, /* same, with optional relocation suffix */
6189 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6191 OP_CPSF, /* CPS flags */
6192 OP_ENDI, /* Endianness specifier */
6193 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6194 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6195 OP_COND, /* conditional code */
6196 OP_TB, /* Table branch. */
6198 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6200 OP_RRnpc_I0, /* ARM register or literal 0 */
6201 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6202 OP_RR_EXi, /* ARM register or expression with imm prefix */
6203 OP_RF_IF, /* FPA register or immediate */
6204 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6205 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6207 /* Optional operands. */
6208 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6209 OP_oI31b, /* 0 .. 31 */
6210 OP_oI32b, /* 1 .. 32 */
6211 OP_oI32z, /* 0 .. 32 */
6212 OP_oIffffb, /* 0 .. 65535 */
6213 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6215 OP_oRR, /* ARM register */
6216 OP_oRRnpc, /* ARM register, not the PC */
6217 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6218 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6219 OP_oRND, /* Optional Neon double precision register */
6220 OP_oRNQ, /* Optional Neon quad precision register */
6221 OP_oRNDQ, /* Optional Neon double or quad precision register */
6222 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6223 OP_oSHll, /* LSL immediate */
6224 OP_oSHar, /* ASR immediate */
6225 OP_oSHllar, /* LSL or ASR immediate */
6226 OP_oROR, /* ROR 0/8/16/24 */
6227 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6229 /* Some pre-defined mixed (ARM/THUMB) operands. */
6230 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6231 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6232 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6234 OP_FIRST_OPTIONAL = OP_oI7b
6237 /* Generic instruction operand parser. This does no encoding and no
6238 semantic validation; it merely squirrels values away in the inst
6239 structure. Returns SUCCESS or FAIL depending on whether the
6240 specified grammar matched. */
6242 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6244 unsigned const int *upat = pattern;
6245 char *backtrack_pos = 0;
6246 const char *backtrack_error = 0;
6247 int i, val = 0, backtrack_index = 0;
6248 enum arm_reg_type rtype;
6249 parse_operand_result result;
6250 unsigned int op_parse_code;
6252 #define po_char_or_fail(chr) \
6255 if (skip_past_char (&str, chr) == FAIL) \
6260 #define po_reg_or_fail(regtype) \
6263 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6264 & inst.operands[i].vectype); \
6267 first_error (_(reg_expected_msgs[regtype])); \
6270 inst.operands[i].reg = val; \
6271 inst.operands[i].isreg = 1; \
6272 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6273 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6274 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6275 || rtype == REG_TYPE_VFD \
6276 || rtype == REG_TYPE_NQ); \
6280 #define po_reg_or_goto(regtype, label) \
6283 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6284 & inst.operands[i].vectype); \
6288 inst.operands[i].reg = val; \
6289 inst.operands[i].isreg = 1; \
6290 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6291 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6292 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6293 || rtype == REG_TYPE_VFD \
6294 || rtype == REG_TYPE_NQ); \
6298 #define po_imm_or_fail(min, max, popt) \
6301 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6303 inst.operands[i].imm = val; \
6307 #define po_scalar_or_goto(elsz, label) \
6310 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6313 inst.operands[i].reg = val; \
6314 inst.operands[i].isscalar = 1; \
6318 #define po_misc_or_fail(expr) \
6326 #define po_misc_or_fail_no_backtrack(expr) \
6330 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6331 backtrack_pos = 0; \
6332 if (result != PARSE_OPERAND_SUCCESS) \
6337 #define po_barrier_or_imm(str) \
6340 val = parse_barrier (&str); \
6341 if (val == FAIL && ! ISALPHA (*str)) \
6344 /* ISB can only take SY as an option. */ \
6345 || ((inst.instruction & 0xf0) == 0x60 \
6348 inst.error = _("invalid barrier type"); \
6349 backtrack_pos = 0; \
6355 skip_whitespace (str);
6357 for (i = 0; upat[i] != OP_stop; i++)
6359 op_parse_code = upat[i];
6360 if (op_parse_code >= 1<<16)
6361 op_parse_code = thumb ? (op_parse_code >> 16)
6362 : (op_parse_code & ((1<<16)-1));
6364 if (op_parse_code >= OP_FIRST_OPTIONAL)
6366 /* Remember where we are in case we need to backtrack. */
6367 gas_assert (!backtrack_pos);
6368 backtrack_pos = str;
6369 backtrack_error = inst.error;
6370 backtrack_index = i;
6373 if (i > 0 && (i > 1 || inst.operands[0].present))
6374 po_char_or_fail (',');
6376 switch (op_parse_code)
6384 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6385 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6386 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6387 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6388 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6389 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6391 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6393 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6395 /* Also accept generic coprocessor regs for unknown registers. */
6397 po_reg_or_fail (REG_TYPE_CN);
6399 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6400 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6401 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6402 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6403 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6404 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6405 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6406 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6407 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6408 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6410 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6412 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6413 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6415 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6417 /* Neon scalar. Using an element size of 8 means that some invalid
6418 scalars are accepted here, so deal with those in later code. */
6419 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6423 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6426 po_imm_or_fail (0, 0, TRUE);
6431 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6436 po_scalar_or_goto (8, try_rr);
6439 po_reg_or_fail (REG_TYPE_RN);
6445 po_scalar_or_goto (8, try_nsdq);
6448 po_reg_or_fail (REG_TYPE_NSDQ);
6454 po_scalar_or_goto (8, try_ndq);
6457 po_reg_or_fail (REG_TYPE_NDQ);
6463 po_scalar_or_goto (8, try_vfd);
6466 po_reg_or_fail (REG_TYPE_VFD);
6471 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6472 not careful then bad things might happen. */
6473 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6478 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6481 /* There's a possibility of getting a 64-bit immediate here, so
6482 we need special handling. */
6483 if (parse_big_immediate (&str, i) == FAIL)
6485 inst.error = _("immediate value is out of range");
6493 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6496 po_imm_or_fail (0, 63, TRUE);
6501 po_char_or_fail ('[');
6502 po_reg_or_fail (REG_TYPE_RN);
6503 po_char_or_fail (']');
6509 po_reg_or_fail (REG_TYPE_RN);
6510 if (skip_past_char (&str, '!') == SUCCESS)
6511 inst.operands[i].writeback = 1;
6515 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6516 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6517 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6518 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6519 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6520 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6521 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6522 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6523 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6524 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6525 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6526 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6528 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6530 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6531 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6533 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6534 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6535 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6536 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6538 /* Immediate variants */
6540 po_char_or_fail ('{');
6541 po_imm_or_fail (0, 255, TRUE);
6542 po_char_or_fail ('}');
6546 /* The expression parser chokes on a trailing !, so we have
6547 to find it first and zap it. */
6550 while (*s && *s != ',')
6555 inst.operands[i].writeback = 1;
6557 po_imm_or_fail (0, 31, TRUE);
6565 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6570 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6575 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6577 if (inst.reloc.exp.X_op == O_symbol)
6579 val = parse_reloc (&str);
6582 inst.error = _("unrecognized relocation suffix");
6585 else if (val != BFD_RELOC_UNUSED)
6587 inst.operands[i].imm = val;
6588 inst.operands[i].hasreloc = 1;
6593 /* Operand for MOVW or MOVT. */
6595 po_misc_or_fail (parse_half (&str));
6598 /* Register or expression. */
6599 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6600 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6602 /* Register or immediate. */
6603 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6604 I0: po_imm_or_fail (0, 0, FALSE); break;
6606 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6608 if (!is_immediate_prefix (*str))
6611 val = parse_fpa_immediate (&str);
6614 /* FPA immediates are encoded as registers 8-15.
6615 parse_fpa_immediate has already applied the offset. */
6616 inst.operands[i].reg = val;
6617 inst.operands[i].isreg = 1;
6620 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6621 I32z: po_imm_or_fail (0, 32, FALSE); break;
6623 /* Two kinds of register. */
6626 struct reg_entry *rege = arm_reg_parse_multi (&str);
6628 || (rege->type != REG_TYPE_MMXWR
6629 && rege->type != REG_TYPE_MMXWC
6630 && rege->type != REG_TYPE_MMXWCG))
6632 inst.error = _("iWMMXt data or control register expected");
6635 inst.operands[i].reg = rege->number;
6636 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6642 struct reg_entry *rege = arm_reg_parse_multi (&str);
6644 || (rege->type != REG_TYPE_MMXWC
6645 && rege->type != REG_TYPE_MMXWCG))
6647 inst.error = _("iWMMXt control register expected");
6650 inst.operands[i].reg = rege->number;
6651 inst.operands[i].isreg = 1;
6656 case OP_CPSF: val = parse_cps_flags (&str); break;
6657 case OP_ENDI: val = parse_endian_specifier (&str); break;
6658 case OP_oROR: val = parse_ror (&str); break;
6659 case OP_COND: val = parse_cond (&str); break;
6660 case OP_oBARRIER_I15:
6661 po_barrier_or_imm (str); break;
6663 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6669 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6670 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6672 inst.error = _("Banked registers are not available with this "
6678 val = parse_psr (&str, op_parse_code == OP_wPSR);
6682 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6685 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6687 if (strncasecmp (str, "APSR_", 5) == 0)
6694 case 'c': found = (found & 1) ? 16 : found | 1; break;
6695 case 'n': found = (found & 2) ? 16 : found | 2; break;
6696 case 'z': found = (found & 4) ? 16 : found | 4; break;
6697 case 'v': found = (found & 8) ? 16 : found | 8; break;
6698 default: found = 16;
6702 inst.operands[i].isvec = 1;
6703 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6704 inst.operands[i].reg = REG_PC;
6711 po_misc_or_fail (parse_tb (&str));
6714 /* Register lists. */
6716 val = parse_reg_list (&str);
6719 inst.operands[1].writeback = 1;
6725 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6729 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6733 /* Allow Q registers too. */
6734 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6739 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6741 inst.operands[i].issingle = 1;
6746 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6751 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6752 &inst.operands[i].vectype);
6755 /* Addressing modes */
6757 po_misc_or_fail (parse_address (&str, i));
6761 po_misc_or_fail_no_backtrack (
6762 parse_address_group_reloc (&str, i, GROUP_LDR));
6766 po_misc_or_fail_no_backtrack (
6767 parse_address_group_reloc (&str, i, GROUP_LDRS));
6771 po_misc_or_fail_no_backtrack (
6772 parse_address_group_reloc (&str, i, GROUP_LDC));
6776 po_misc_or_fail (parse_shifter_operand (&str, i));
6780 po_misc_or_fail_no_backtrack (
6781 parse_shifter_operand_group_reloc (&str, i));
6785 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6789 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6793 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6797 as_fatal (_("unhandled operand code %d"), op_parse_code);
6800 /* Various value-based sanity checks and shared operations. We
6801 do not signal immediate failures for the register constraints;
6802 this allows a syntax error to take precedence. */
6803 switch (op_parse_code)
6811 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6812 inst.error = BAD_PC;
6817 if (inst.operands[i].isreg)
6819 if (inst.operands[i].reg == REG_PC)
6820 inst.error = BAD_PC;
6821 else if (inst.operands[i].reg == REG_SP)
6822 inst.error = BAD_SP;
6827 if (inst.operands[i].isreg
6828 && inst.operands[i].reg == REG_PC
6829 && (inst.operands[i].writeback || thumb))
6830 inst.error = BAD_PC;
6839 case OP_oBARRIER_I15:
6848 inst.operands[i].imm = val;
6855 /* If we get here, this operand was successfully parsed. */
6856 inst.operands[i].present = 1;
6860 inst.error = BAD_ARGS;
6865 /* The parse routine should already have set inst.error, but set a
6866 default here just in case. */
6868 inst.error = _("syntax error");
6872 /* Do not backtrack over a trailing optional argument that
6873 absorbed some text. We will only fail again, with the
6874 'garbage following instruction' error message, which is
6875 probably less helpful than the current one. */
6876 if (backtrack_index == i && backtrack_pos != str
6877 && upat[i+1] == OP_stop)
6880 inst.error = _("syntax error");
6884 /* Try again, skipping the optional argument at backtrack_pos. */
6885 str = backtrack_pos;
6886 inst.error = backtrack_error;
6887 inst.operands[backtrack_index].present = 0;
6888 i = backtrack_index;
6892 /* Check that we have parsed all the arguments. */
6893 if (*str != '\0' && !inst.error)
6894 inst.error = _("garbage following instruction");
6896 return inst.error ? FAIL : SUCCESS;
6899 #undef po_char_or_fail
6900 #undef po_reg_or_fail
6901 #undef po_reg_or_goto
6902 #undef po_imm_or_fail
6903 #undef po_scalar_or_fail
6904 #undef po_barrier_or_imm
6906 /* Shorthand macro for instruction encoding functions issuing errors. */
6907 #define constraint(expr, err) \
6918 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6919 instructions are unpredictable if these registers are used. This
6920 is the BadReg predicate in ARM's Thumb-2 documentation. */
6921 #define reject_bad_reg(reg) \
6923 if (reg == REG_SP || reg == REG_PC) \
6925 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6930 /* If REG is R13 (the stack pointer), warn that its use is
6932 #define warn_deprecated_sp(reg) \
6934 if (warn_on_deprecated && reg == REG_SP) \
6935 as_warn (_("use of r13 is deprecated")); \
6938 /* Functions for operand encoding. ARM, then Thumb. */
6940 #define rotate_left(v, n) (v << n | v >> (32 - n))
6942 /* If VAL can be encoded in the immediate field of an ARM instruction,
6943 return the encoded form. Otherwise, return FAIL. */
6946 encode_arm_immediate (unsigned int val)
6950 for (i = 0; i < 32; i += 2)
6951 if ((a = rotate_left (val, i)) <= 0xff)
6952 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6957 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6958 return the encoded form. Otherwise, return FAIL. */
6960 encode_thumb32_immediate (unsigned int val)
6967 for (i = 1; i <= 24; i++)
6970 if ((val & ~(0xff << i)) == 0)
6971 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6975 if (val == ((a << 16) | a))
6977 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6981 if (val == ((a << 16) | a))
6982 return 0x200 | (a >> 8);
6986 /* Encode a VFP SP or DP register number into inst.instruction. */
6989 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6991 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6994 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6997 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7000 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7005 first_error (_("D register out of range for selected VFP version"));
7013 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7017 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7021 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7025 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7029 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7033 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7041 /* Encode a <shift> in an ARM-format instruction. The immediate,
7042 if any, is handled by md_apply_fix. */
7044 encode_arm_shift (int i)
7046 if (inst.operands[i].shift_kind == SHIFT_RRX)
7047 inst.instruction |= SHIFT_ROR << 5;
7050 inst.instruction |= inst.operands[i].shift_kind << 5;
7051 if (inst.operands[i].immisreg)
7053 inst.instruction |= SHIFT_BY_REG;
7054 inst.instruction |= inst.operands[i].imm << 8;
7057 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7062 encode_arm_shifter_operand (int i)
7064 if (inst.operands[i].isreg)
7066 inst.instruction |= inst.operands[i].reg;
7067 encode_arm_shift (i);
7071 inst.instruction |= INST_IMMEDIATE;
7072 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7073 inst.instruction |= inst.operands[i].imm;
7077 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7079 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7082 Generate an error if the operand is not a register. */
7083 constraint (!inst.operands[i].isreg,
7084 _("Instruction does not support =N addresses"));
7086 inst.instruction |= inst.operands[i].reg << 16;
7088 if (inst.operands[i].preind)
7092 inst.error = _("instruction does not accept preindexed addressing");
7095 inst.instruction |= PRE_INDEX;
7096 if (inst.operands[i].writeback)
7097 inst.instruction |= WRITE_BACK;
7100 else if (inst.operands[i].postind)
7102 gas_assert (inst.operands[i].writeback);
7104 inst.instruction |= WRITE_BACK;
7106 else /* unindexed - only for coprocessor */
7108 inst.error = _("instruction does not accept unindexed addressing");
7112 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7113 && (((inst.instruction & 0x000f0000) >> 16)
7114 == ((inst.instruction & 0x0000f000) >> 12)))
7115 as_warn ((inst.instruction & LOAD_BIT)
7116 ? _("destination register same as write-back base")
7117 : _("source register same as write-back base"));
7120 /* inst.operands[i] was set up by parse_address. Encode it into an
7121 ARM-format mode 2 load or store instruction. If is_t is true,
7122 reject forms that cannot be used with a T instruction (i.e. not
7125 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7127 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7129 encode_arm_addr_mode_common (i, is_t);
7131 if (inst.operands[i].immisreg)
7133 constraint ((inst.operands[i].imm == REG_PC
7134 || (is_pc && inst.operands[i].writeback)),
7136 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7137 inst.instruction |= inst.operands[i].imm;
7138 if (!inst.operands[i].negative)
7139 inst.instruction |= INDEX_UP;
7140 if (inst.operands[i].shifted)
7142 if (inst.operands[i].shift_kind == SHIFT_RRX)
7143 inst.instruction |= SHIFT_ROR << 5;
7146 inst.instruction |= inst.operands[i].shift_kind << 5;
7147 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7151 else /* immediate offset in inst.reloc */
7153 if (is_pc && !inst.reloc.pc_rel)
7155 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7157 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7158 cannot use PC in addressing.
7159 PC cannot be used in writeback addressing, either. */
7160 constraint ((is_t || inst.operands[i].writeback),
7163 /* Use of PC in str is deprecated for ARMv7. */
7164 if (warn_on_deprecated
7166 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7167 as_warn (_("use of PC in this instruction is deprecated"));
7170 if (inst.reloc.type == BFD_RELOC_UNUSED)
7172 /* Prefer + for zero encoded value. */
7173 if (!inst.operands[i].negative)
7174 inst.instruction |= INDEX_UP;
7175 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7180 /* inst.operands[i] was set up by parse_address. Encode it into an
7181 ARM-format mode 3 load or store instruction. Reject forms that
7182 cannot be used with such instructions. If is_t is true, reject
7183 forms that cannot be used with a T instruction (i.e. not
7186 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7188 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7190 inst.error = _("instruction does not accept scaled register index");
7194 encode_arm_addr_mode_common (i, is_t);
7196 if (inst.operands[i].immisreg)
7198 constraint ((inst.operands[i].imm == REG_PC
7199 || inst.operands[i].reg == REG_PC),
7201 inst.instruction |= inst.operands[i].imm;
7202 if (!inst.operands[i].negative)
7203 inst.instruction |= INDEX_UP;
7205 else /* immediate offset in inst.reloc */
7207 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7208 && inst.operands[i].writeback),
7210 inst.instruction |= HWOFFSET_IMM;
7211 if (inst.reloc.type == BFD_RELOC_UNUSED)
7213 /* Prefer + for zero encoded value. */
7214 if (!inst.operands[i].negative)
7215 inst.instruction |= INDEX_UP;
7217 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7222 /* inst.operands[i] was set up by parse_address. Encode it into an
7223 ARM-format instruction. Reject all forms which cannot be encoded
7224 into a coprocessor load/store instruction. If wb_ok is false,
7225 reject use of writeback; if unind_ok is false, reject use of
7226 unindexed addressing. If reloc_override is not 0, use it instead
7227 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7228 (in which case it is preserved). */
7231 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7233 inst.instruction |= inst.operands[i].reg << 16;
7235 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7237 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7239 gas_assert (!inst.operands[i].writeback);
7242 inst.error = _("instruction does not support unindexed addressing");
7245 inst.instruction |= inst.operands[i].imm;
7246 inst.instruction |= INDEX_UP;
7250 if (inst.operands[i].preind)
7251 inst.instruction |= PRE_INDEX;
7253 if (inst.operands[i].writeback)
7255 if (inst.operands[i].reg == REG_PC)
7257 inst.error = _("pc may not be used with write-back");
7262 inst.error = _("instruction does not support writeback");
7265 inst.instruction |= WRITE_BACK;
7269 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7270 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7271 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7272 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7275 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7277 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7280 /* Prefer + for zero encoded value. */
7281 if (!inst.operands[i].negative)
7282 inst.instruction |= INDEX_UP;
7287 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7288 Determine whether it can be performed with a move instruction; if
7289 it can, convert inst.instruction to that move instruction and
7290 return TRUE; if it can't, convert inst.instruction to a literal-pool
7291 load and return FALSE. If this is not a valid thing to do in the
7292 current context, set inst.error and return TRUE.
7294 inst.operands[i] describes the destination register. */
7297 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7302 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7306 if ((inst.instruction & tbit) == 0)
7308 inst.error = _("invalid pseudo operation");
7311 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7313 inst.error = _("constant expression expected");
7316 if (inst.reloc.exp.X_op == O_constant)
7320 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7322 /* This can be done with a mov(1) instruction. */
7323 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7324 inst.instruction |= inst.reloc.exp.X_add_number;
7330 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7333 /* This can be done with a mov instruction. */
7334 inst.instruction &= LITERAL_MASK;
7335 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7336 inst.instruction |= value & 0xfff;
7340 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7343 /* This can be done with a mvn instruction. */
7344 inst.instruction &= LITERAL_MASK;
7345 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7346 inst.instruction |= value & 0xfff;
7352 if (add_to_lit_pool () == FAIL)
7354 inst.error = _("literal pool insertion failed");
7357 inst.operands[1].reg = REG_PC;
7358 inst.operands[1].isreg = 1;
7359 inst.operands[1].preind = 1;
7360 inst.reloc.pc_rel = 1;
7361 inst.reloc.type = (thumb_p
7362 ? BFD_RELOC_ARM_THUMB_OFFSET
7364 ? BFD_RELOC_ARM_HWLITERAL
7365 : BFD_RELOC_ARM_LITERAL));
7369 /* Functions for instruction encoding, sorted by sub-architecture.
7370 First some generics; their names are taken from the conventional
7371 bit positions for register arguments in ARM format instructions. */
7381 inst.instruction |= inst.operands[0].reg << 12;
7387 inst.instruction |= inst.operands[0].reg << 12;
7388 inst.instruction |= inst.operands[1].reg;
7394 inst.instruction |= inst.operands[0].reg;
7395 inst.instruction |= inst.operands[1].reg << 16;
7401 inst.instruction |= inst.operands[0].reg << 12;
7402 inst.instruction |= inst.operands[1].reg << 16;
7408 inst.instruction |= inst.operands[0].reg << 16;
7409 inst.instruction |= inst.operands[1].reg << 12;
7413 check_obsolete (const arm_feature_set *feature, const char *msg)
7415 if (ARM_CPU_IS_ANY (cpu_variant))
7417 as_warn ("%s", msg);
7420 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7432 unsigned Rn = inst.operands[2].reg;
7433 /* Enforce restrictions on SWP instruction. */
7434 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7436 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7437 _("Rn must not overlap other operands"));
7439 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7441 if (!check_obsolete (&arm_ext_v8,
7442 _("swp{b} use is obsoleted for ARMv8 and later"))
7443 && warn_on_deprecated
7444 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7445 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7448 inst.instruction |= inst.operands[0].reg << 12;
7449 inst.instruction |= inst.operands[1].reg;
7450 inst.instruction |= Rn << 16;
7456 inst.instruction |= inst.operands[0].reg << 12;
7457 inst.instruction |= inst.operands[1].reg << 16;
7458 inst.instruction |= inst.operands[2].reg;
7464 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7465 constraint (((inst.reloc.exp.X_op != O_constant
7466 && inst.reloc.exp.X_op != O_illegal)
7467 || inst.reloc.exp.X_add_number != 0),
7469 inst.instruction |= inst.operands[0].reg;
7470 inst.instruction |= inst.operands[1].reg << 12;
7471 inst.instruction |= inst.operands[2].reg << 16;
7477 inst.instruction |= inst.operands[0].imm;
7483 inst.instruction |= inst.operands[0].reg << 12;
7484 encode_arm_cp_address (1, TRUE, TRUE, 0);
7487 /* ARM instructions, in alphabetical order by function name (except
7488 that wrapper functions appear immediately after the function they
7491 /* This is a pseudo-op of the form "adr rd, label" to be converted
7492 into a relative address of the form "add rd, pc, #label-.-8". */
7497 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7499 /* Frag hacking will turn this into a sub instruction if the offset turns
7500 out to be negative. */
7501 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7502 inst.reloc.pc_rel = 1;
7503 inst.reloc.exp.X_add_number -= 8;
7506 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7507 into a relative address of the form:
7508 add rd, pc, #low(label-.-8)"
7509 add rd, rd, #high(label-.-8)" */
7514 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7516 /* Frag hacking will turn this into a sub instruction if the offset turns
7517 out to be negative. */
7518 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7519 inst.reloc.pc_rel = 1;
7520 inst.size = INSN_SIZE * 2;
7521 inst.reloc.exp.X_add_number -= 8;
7527 if (!inst.operands[1].present)
7528 inst.operands[1].reg = inst.operands[0].reg;
7529 inst.instruction |= inst.operands[0].reg << 12;
7530 inst.instruction |= inst.operands[1].reg << 16;
7531 encode_arm_shifter_operand (2);
7537 if (inst.operands[0].present)
7538 inst.instruction |= inst.operands[0].imm;
7540 inst.instruction |= 0xf;
7546 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7547 constraint (msb > 32, _("bit-field extends past end of register"));
7548 /* The instruction encoding stores the LSB and MSB,
7549 not the LSB and width. */
7550 inst.instruction |= inst.operands[0].reg << 12;
7551 inst.instruction |= inst.operands[1].imm << 7;
7552 inst.instruction |= (msb - 1) << 16;
7560 /* #0 in second position is alternative syntax for bfc, which is
7561 the same instruction but with REG_PC in the Rm field. */
7562 if (!inst.operands[1].isreg)
7563 inst.operands[1].reg = REG_PC;
7565 msb = inst.operands[2].imm + inst.operands[3].imm;
7566 constraint (msb > 32, _("bit-field extends past end of register"));
7567 /* The instruction encoding stores the LSB and MSB,
7568 not the LSB and width. */
7569 inst.instruction |= inst.operands[0].reg << 12;
7570 inst.instruction |= inst.operands[1].reg;
7571 inst.instruction |= inst.operands[2].imm << 7;
7572 inst.instruction |= (msb - 1) << 16;
7578 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7579 _("bit-field extends past end of register"));
7580 inst.instruction |= inst.operands[0].reg << 12;
7581 inst.instruction |= inst.operands[1].reg;
7582 inst.instruction |= inst.operands[2].imm << 7;
7583 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7586 /* ARM V5 breakpoint instruction (argument parse)
7587 BKPT <16 bit unsigned immediate>
7588 Instruction is not conditional.
7589 The bit pattern given in insns[] has the COND_ALWAYS condition,
7590 and it is an error if the caller tried to override that. */
7595 /* Top 12 of 16 bits to bits 19:8. */
7596 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7598 /* Bottom 4 of 16 bits to bits 3:0. */
7599 inst.instruction |= inst.operands[0].imm & 0xf;
7603 encode_branch (int default_reloc)
7605 if (inst.operands[0].hasreloc)
7607 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7608 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7609 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7610 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7611 ? BFD_RELOC_ARM_PLT32
7612 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7615 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7616 inst.reloc.pc_rel = 1;
7623 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7624 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7627 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7634 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7636 if (inst.cond == COND_ALWAYS)
7637 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7639 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7643 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7646 /* ARM V5 branch-link-exchange instruction (argument parse)
7647 BLX <target_addr> ie BLX(1)
7648 BLX{<condition>} <Rm> ie BLX(2)
7649 Unfortunately, there are two different opcodes for this mnemonic.
7650 So, the insns[].value is not used, and the code here zaps values
7651 into inst.instruction.
7652 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7657 if (inst.operands[0].isreg)
7659 /* Arg is a register; the opcode provided by insns[] is correct.
7660 It is not illegal to do "blx pc", just useless. */
7661 if (inst.operands[0].reg == REG_PC)
7662 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7664 inst.instruction |= inst.operands[0].reg;
7668 /* Arg is an address; this instruction cannot be executed
7669 conditionally, and the opcode must be adjusted.
7670 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7671 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7672 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7673 inst.instruction = 0xfa000000;
7674 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7681 bfd_boolean want_reloc;
7683 if (inst.operands[0].reg == REG_PC)
7684 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7686 inst.instruction |= inst.operands[0].reg;
7687 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7688 it is for ARMv4t or earlier. */
7689 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7690 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7694 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7699 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7703 /* ARM v5TEJ. Jump to Jazelle code. */
7708 if (inst.operands[0].reg == REG_PC)
7709 as_tsktsk (_("use of r15 in bxj is not really useful"));
7711 inst.instruction |= inst.operands[0].reg;
7714 /* Co-processor data operation:
7715 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7716 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7720 inst.instruction |= inst.operands[0].reg << 8;
7721 inst.instruction |= inst.operands[1].imm << 20;
7722 inst.instruction |= inst.operands[2].reg << 12;
7723 inst.instruction |= inst.operands[3].reg << 16;
7724 inst.instruction |= inst.operands[4].reg;
7725 inst.instruction |= inst.operands[5].imm << 5;
7731 inst.instruction |= inst.operands[0].reg << 16;
7732 encode_arm_shifter_operand (1);
7735 /* Transfer between coprocessor and ARM registers.
7736 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7741 No special properties. */
7743 struct deprecated_coproc_regs_s
7750 arm_feature_set deprecated;
7751 arm_feature_set obsoleted;
7752 const char *dep_msg;
7753 const char *obs_msg;
7756 #define DEPR_ACCESS_V8 \
7757 N_("This coprocessor register access is deprecated in ARMv8")
7759 /* Table of all deprecated coprocessor registers. */
7760 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7762 {15, 0, 7, 10, 5, /* CP15DMB. */
7763 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7764 DEPR_ACCESS_V8, NULL},
7765 {15, 0, 7, 10, 4, /* CP15DSB. */
7766 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7767 DEPR_ACCESS_V8, NULL},
7768 {15, 0, 7, 5, 4, /* CP15ISB. */
7769 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7770 DEPR_ACCESS_V8, NULL},
7771 {14, 6, 1, 0, 0, /* TEEHBR. */
7772 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7773 DEPR_ACCESS_V8, NULL},
7774 {14, 6, 0, 0, 0, /* TEECR. */
7775 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7776 DEPR_ACCESS_V8, NULL},
7779 #undef DEPR_ACCESS_V8
7781 static const size_t deprecated_coproc_reg_count =
7782 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7790 Rd = inst.operands[2].reg;
7793 if (inst.instruction == 0xee000010
7794 || inst.instruction == 0xfe000010)
7796 reject_bad_reg (Rd);
7799 constraint (Rd == REG_SP, BAD_SP);
7804 if (inst.instruction == 0xe000010)
7805 constraint (Rd == REG_PC, BAD_PC);
7808 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7810 const struct deprecated_coproc_regs_s *r =
7811 deprecated_coproc_regs + i;
7813 if (inst.operands[0].reg == r->cp
7814 && inst.operands[1].imm == r->opc1
7815 && inst.operands[3].reg == r->crn
7816 && inst.operands[4].reg == r->crm
7817 && inst.operands[5].imm == r->opc2)
7819 if (! ARM_CPU_IS_ANY (cpu_variant)
7820 && warn_on_deprecated
7821 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7822 as_warn ("%s", r->dep_msg);
7826 inst.instruction |= inst.operands[0].reg << 8;
7827 inst.instruction |= inst.operands[1].imm << 21;
7828 inst.instruction |= Rd << 12;
7829 inst.instruction |= inst.operands[3].reg << 16;
7830 inst.instruction |= inst.operands[4].reg;
7831 inst.instruction |= inst.operands[5].imm << 5;
7834 /* Transfer between coprocessor register and pair of ARM registers.
7835 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7840 Two XScale instructions are special cases of these:
7842 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7843 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7845 Result unpredictable if Rd or Rn is R15. */
7852 Rd = inst.operands[2].reg;
7853 Rn = inst.operands[3].reg;
7857 reject_bad_reg (Rd);
7858 reject_bad_reg (Rn);
7862 constraint (Rd == REG_PC, BAD_PC);
7863 constraint (Rn == REG_PC, BAD_PC);
7866 inst.instruction |= inst.operands[0].reg << 8;
7867 inst.instruction |= inst.operands[1].imm << 4;
7868 inst.instruction |= Rd << 12;
7869 inst.instruction |= Rn << 16;
7870 inst.instruction |= inst.operands[4].reg;
7876 inst.instruction |= inst.operands[0].imm << 6;
7877 if (inst.operands[1].present)
7879 inst.instruction |= CPSI_MMOD;
7880 inst.instruction |= inst.operands[1].imm;
7887 inst.instruction |= inst.operands[0].imm;
7893 unsigned Rd, Rn, Rm;
7895 Rd = inst.operands[0].reg;
7896 Rn = (inst.operands[1].present
7897 ? inst.operands[1].reg : Rd);
7898 Rm = inst.operands[2].reg;
7900 constraint ((Rd == REG_PC), BAD_PC);
7901 constraint ((Rn == REG_PC), BAD_PC);
7902 constraint ((Rm == REG_PC), BAD_PC);
7904 inst.instruction |= Rd << 16;
7905 inst.instruction |= Rn << 0;
7906 inst.instruction |= Rm << 8;
7912 /* There is no IT instruction in ARM mode. We
7913 process it to do the validation as if in
7914 thumb mode, just in case the code gets
7915 assembled for thumb using the unified syntax. */
7920 set_it_insn_type (IT_INSN);
7921 now_it.mask = (inst.instruction & 0xf) | 0x10;
7922 now_it.cc = inst.operands[0].imm;
7926 /* If there is only one register in the register list,
7927 then return its register number. Otherwise return -1. */
7929 only_one_reg_in_list (int range)
7931 int i = ffs (range) - 1;
7932 return (i > 15 || range != (1 << i)) ? -1 : i;
7936 encode_ldmstm(int from_push_pop_mnem)
7938 int base_reg = inst.operands[0].reg;
7939 int range = inst.operands[1].imm;
7942 inst.instruction |= base_reg << 16;
7943 inst.instruction |= range;
7945 if (inst.operands[1].writeback)
7946 inst.instruction |= LDM_TYPE_2_OR_3;
7948 if (inst.operands[0].writeback)
7950 inst.instruction |= WRITE_BACK;
7951 /* Check for unpredictable uses of writeback. */
7952 if (inst.instruction & LOAD_BIT)
7954 /* Not allowed in LDM type 2. */
7955 if ((inst.instruction & LDM_TYPE_2_OR_3)
7956 && ((range & (1 << REG_PC)) == 0))
7957 as_warn (_("writeback of base register is UNPREDICTABLE"));
7958 /* Only allowed if base reg not in list for other types. */
7959 else if (range & (1 << base_reg))
7960 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7964 /* Not allowed for type 2. */
7965 if (inst.instruction & LDM_TYPE_2_OR_3)
7966 as_warn (_("writeback of base register is UNPREDICTABLE"));
7967 /* Only allowed if base reg not in list, or first in list. */
7968 else if ((range & (1 << base_reg))
7969 && (range & ((1 << base_reg) - 1)))
7970 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7974 /* If PUSH/POP has only one register, then use the A2 encoding. */
7975 one_reg = only_one_reg_in_list (range);
7976 if (from_push_pop_mnem && one_reg >= 0)
7978 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7980 inst.instruction &= A_COND_MASK;
7981 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7982 inst.instruction |= one_reg << 12;
7989 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
7992 /* ARMv5TE load-consecutive (argument parse)
8001 constraint (inst.operands[0].reg % 2 != 0,
8002 _("first transfer register must be even"));
8003 constraint (inst.operands[1].present
8004 && inst.operands[1].reg != inst.operands[0].reg + 1,
8005 _("can only transfer two consecutive registers"));
8006 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8007 constraint (!inst.operands[2].isreg, _("'[' expected"));
8009 if (!inst.operands[1].present)
8010 inst.operands[1].reg = inst.operands[0].reg + 1;
8012 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8013 register and the first register written; we have to diagnose
8014 overlap between the base and the second register written here. */
8016 if (inst.operands[2].reg == inst.operands[1].reg
8017 && (inst.operands[2].writeback || inst.operands[2].postind))
8018 as_warn (_("base register written back, and overlaps "
8019 "second transfer register"));
8021 if (!(inst.instruction & V4_STR_BIT))
8023 /* For an index-register load, the index register must not overlap the
8024 destination (even if not write-back). */
8025 if (inst.operands[2].immisreg
8026 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8027 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8028 as_warn (_("index register overlaps transfer register"));
8030 inst.instruction |= inst.operands[0].reg << 12;
8031 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8037 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8038 || inst.operands[1].postind || inst.operands[1].writeback
8039 || inst.operands[1].immisreg || inst.operands[1].shifted
8040 || inst.operands[1].negative
8041 /* This can arise if the programmer has written
8043 or if they have mistakenly used a register name as the last
8046 It is very difficult to distinguish between these two cases
8047 because "rX" might actually be a label. ie the register
8048 name has been occluded by a symbol of the same name. So we
8049 just generate a general 'bad addressing mode' type error
8050 message and leave it up to the programmer to discover the
8051 true cause and fix their mistake. */
8052 || (inst.operands[1].reg == REG_PC),
8055 constraint (inst.reloc.exp.X_op != O_constant
8056 || inst.reloc.exp.X_add_number != 0,
8057 _("offset must be zero in ARM encoding"));
8059 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8061 inst.instruction |= inst.operands[0].reg << 12;
8062 inst.instruction |= inst.operands[1].reg << 16;
8063 inst.reloc.type = BFD_RELOC_UNUSED;
8069 constraint (inst.operands[0].reg % 2 != 0,
8070 _("even register required"));
8071 constraint (inst.operands[1].present
8072 && inst.operands[1].reg != inst.operands[0].reg + 1,
8073 _("can only load two consecutive registers"));
8074 /* If op 1 were present and equal to PC, this function wouldn't
8075 have been called in the first place. */
8076 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8078 inst.instruction |= inst.operands[0].reg << 12;
8079 inst.instruction |= inst.operands[2].reg << 16;
8082 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8083 which is not a multiple of four is UNPREDICTABLE. */
8085 check_ldr_r15_aligned (void)
8087 constraint (!(inst.operands[1].immisreg)
8088 && (inst.operands[0].reg == REG_PC
8089 && inst.operands[1].reg == REG_PC
8090 && (inst.reloc.exp.X_add_number & 0x3)),
8091 _("ldr to register 15 must be 4-byte alligned"));
8097 inst.instruction |= inst.operands[0].reg << 12;
8098 if (!inst.operands[1].isreg)
8099 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
8101 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8102 check_ldr_r15_aligned ();
8108 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8110 if (inst.operands[1].preind)
8112 constraint (inst.reloc.exp.X_op != O_constant
8113 || inst.reloc.exp.X_add_number != 0,
8114 _("this instruction requires a post-indexed address"));
8116 inst.operands[1].preind = 0;
8117 inst.operands[1].postind = 1;
8118 inst.operands[1].writeback = 1;
8120 inst.instruction |= inst.operands[0].reg << 12;
8121 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8124 /* Halfword and signed-byte load/store operations. */
8129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8130 inst.instruction |= inst.operands[0].reg << 12;
8131 if (!inst.operands[1].isreg)
8132 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
8134 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8140 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8142 if (inst.operands[1].preind)
8144 constraint (inst.reloc.exp.X_op != O_constant
8145 || inst.reloc.exp.X_add_number != 0,
8146 _("this instruction requires a post-indexed address"));
8148 inst.operands[1].preind = 0;
8149 inst.operands[1].postind = 1;
8150 inst.operands[1].writeback = 1;
8152 inst.instruction |= inst.operands[0].reg << 12;
8153 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8156 /* Co-processor register load/store.
8157 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8161 inst.instruction |= inst.operands[0].reg << 8;
8162 inst.instruction |= inst.operands[1].reg << 12;
8163 encode_arm_cp_address (2, TRUE, TRUE, 0);
8169 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8170 if (inst.operands[0].reg == inst.operands[1].reg
8171 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8172 && !(inst.instruction & 0x00400000))
8173 as_tsktsk (_("Rd and Rm should be different in mla"));
8175 inst.instruction |= inst.operands[0].reg << 16;
8176 inst.instruction |= inst.operands[1].reg;
8177 inst.instruction |= inst.operands[2].reg << 8;
8178 inst.instruction |= inst.operands[3].reg << 12;
8184 inst.instruction |= inst.operands[0].reg << 12;
8185 encode_arm_shifter_operand (1);
8188 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8195 top = (inst.instruction & 0x00400000) != 0;
8196 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8197 _(":lower16: not allowed this instruction"));
8198 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8199 _(":upper16: not allowed instruction"));
8200 inst.instruction |= inst.operands[0].reg << 12;
8201 if (inst.reloc.type == BFD_RELOC_UNUSED)
8203 imm = inst.reloc.exp.X_add_number;
8204 /* The value is in two pieces: 0:11, 16:19. */
8205 inst.instruction |= (imm & 0x00000fff);
8206 inst.instruction |= (imm & 0x0000f000) << 4;
8210 static void do_vfp_nsyn_opcode (const char *);
8213 do_vfp_nsyn_mrs (void)
8215 if (inst.operands[0].isvec)
8217 if (inst.operands[1].reg != 1)
8218 first_error (_("operand 1 must be FPSCR"));
8219 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8220 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8221 do_vfp_nsyn_opcode ("fmstat");
8223 else if (inst.operands[1].isvec)
8224 do_vfp_nsyn_opcode ("fmrx");
8232 do_vfp_nsyn_msr (void)
8234 if (inst.operands[0].isvec)
8235 do_vfp_nsyn_opcode ("fmxr");
8245 unsigned Rt = inst.operands[0].reg;
8247 if (thumb_mode && Rt == REG_SP)
8249 inst.error = BAD_SP;
8253 /* APSR_ sets isvec. All other refs to PC are illegal. */
8254 if (!inst.operands[0].isvec && Rt == REG_PC)
8256 inst.error = BAD_PC;
8260 /* If we get through parsing the register name, we just insert the number
8261 generated into the instruction without further validation. */
8262 inst.instruction |= (inst.operands[1].reg << 16);
8263 inst.instruction |= (Rt << 12);
8269 unsigned Rt = inst.operands[1].reg;
8272 reject_bad_reg (Rt);
8273 else if (Rt == REG_PC)
8275 inst.error = BAD_PC;
8279 /* If we get through parsing the register name, we just insert the number
8280 generated into the instruction without further validation. */
8281 inst.instruction |= (inst.operands[0].reg << 16);
8282 inst.instruction |= (Rt << 12);
8290 if (do_vfp_nsyn_mrs () == SUCCESS)
8293 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8294 inst.instruction |= inst.operands[0].reg << 12;
8296 if (inst.operands[1].isreg)
8298 br = inst.operands[1].reg;
8299 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8300 as_bad (_("bad register for mrs"));
8304 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8305 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8307 _("'APSR', 'CPSR' or 'SPSR' expected"));
8308 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8311 inst.instruction |= br;
8314 /* Two possible forms:
8315 "{C|S}PSR_<field>, Rm",
8316 "{C|S}PSR_f, #expression". */
8321 if (do_vfp_nsyn_msr () == SUCCESS)
8324 inst.instruction |= inst.operands[0].imm;
8325 if (inst.operands[1].isreg)
8326 inst.instruction |= inst.operands[1].reg;
8329 inst.instruction |= INST_IMMEDIATE;
8330 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8331 inst.reloc.pc_rel = 0;
8338 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8340 if (!inst.operands[2].present)
8341 inst.operands[2].reg = inst.operands[0].reg;
8342 inst.instruction |= inst.operands[0].reg << 16;
8343 inst.instruction |= inst.operands[1].reg;
8344 inst.instruction |= inst.operands[2].reg << 8;
8346 if (inst.operands[0].reg == inst.operands[1].reg
8347 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8348 as_tsktsk (_("Rd and Rm should be different in mul"));
8351 /* Long Multiply Parser
8352 UMULL RdLo, RdHi, Rm, Rs
8353 SMULL RdLo, RdHi, Rm, Rs
8354 UMLAL RdLo, RdHi, Rm, Rs
8355 SMLAL RdLo, RdHi, Rm, Rs. */
8360 inst.instruction |= inst.operands[0].reg << 12;
8361 inst.instruction |= inst.operands[1].reg << 16;
8362 inst.instruction |= inst.operands[2].reg;
8363 inst.instruction |= inst.operands[3].reg << 8;
8365 /* rdhi and rdlo must be different. */
8366 if (inst.operands[0].reg == inst.operands[1].reg)
8367 as_tsktsk (_("rdhi and rdlo must be different"));
8369 /* rdhi, rdlo and rm must all be different before armv6. */
8370 if ((inst.operands[0].reg == inst.operands[2].reg
8371 || inst.operands[1].reg == inst.operands[2].reg)
8372 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8373 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8379 if (inst.operands[0].present
8380 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8382 /* Architectural NOP hints are CPSR sets with no bits selected. */
8383 inst.instruction &= 0xf0000000;
8384 inst.instruction |= 0x0320f000;
8385 if (inst.operands[0].present)
8386 inst.instruction |= inst.operands[0].imm;
8390 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8391 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8392 Condition defaults to COND_ALWAYS.
8393 Error if Rd, Rn or Rm are R15. */
8398 inst.instruction |= inst.operands[0].reg << 12;
8399 inst.instruction |= inst.operands[1].reg << 16;
8400 inst.instruction |= inst.operands[2].reg;
8401 if (inst.operands[3].present)
8402 encode_arm_shift (3);
8405 /* ARM V6 PKHTB (Argument Parse). */
8410 if (!inst.operands[3].present)
8412 /* If the shift specifier is omitted, turn the instruction
8413 into pkhbt rd, rm, rn. */
8414 inst.instruction &= 0xfff00010;
8415 inst.instruction |= inst.operands[0].reg << 12;
8416 inst.instruction |= inst.operands[1].reg;
8417 inst.instruction |= inst.operands[2].reg << 16;
8421 inst.instruction |= inst.operands[0].reg << 12;
8422 inst.instruction |= inst.operands[1].reg << 16;
8423 inst.instruction |= inst.operands[2].reg;
8424 encode_arm_shift (3);
8428 /* ARMv5TE: Preload-Cache
8429 MP Extensions: Preload for write
8433 Syntactically, like LDR with B=1, W=0, L=1. */
8438 constraint (!inst.operands[0].isreg,
8439 _("'[' expected after PLD mnemonic"));
8440 constraint (inst.operands[0].postind,
8441 _("post-indexed expression used in preload instruction"));
8442 constraint (inst.operands[0].writeback,
8443 _("writeback used in preload instruction"));
8444 constraint (!inst.operands[0].preind,
8445 _("unindexed addressing used in preload instruction"));
8446 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8449 /* ARMv7: PLI <addr_mode> */
8453 constraint (!inst.operands[0].isreg,
8454 _("'[' expected after PLI mnemonic"));
8455 constraint (inst.operands[0].postind,
8456 _("post-indexed expression used in preload instruction"));
8457 constraint (inst.operands[0].writeback,
8458 _("writeback used in preload instruction"));
8459 constraint (!inst.operands[0].preind,
8460 _("unindexed addressing used in preload instruction"));
8461 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8462 inst.instruction &= ~PRE_INDEX;
8468 inst.operands[1] = inst.operands[0];
8469 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8470 inst.operands[0].isreg = 1;
8471 inst.operands[0].writeback = 1;
8472 inst.operands[0].reg = REG_SP;
8473 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
8476 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8477 word at the specified address and the following word
8479 Unconditionally executed.
8480 Error if Rn is R15. */
8485 inst.instruction |= inst.operands[0].reg << 16;
8486 if (inst.operands[0].writeback)
8487 inst.instruction |= WRITE_BACK;
8490 /* ARM V6 ssat (argument parse). */
8495 inst.instruction |= inst.operands[0].reg << 12;
8496 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8497 inst.instruction |= inst.operands[2].reg;
8499 if (inst.operands[3].present)
8500 encode_arm_shift (3);
8503 /* ARM V6 usat (argument parse). */
8508 inst.instruction |= inst.operands[0].reg << 12;
8509 inst.instruction |= inst.operands[1].imm << 16;
8510 inst.instruction |= inst.operands[2].reg;
8512 if (inst.operands[3].present)
8513 encode_arm_shift (3);
8516 /* ARM V6 ssat16 (argument parse). */
8521 inst.instruction |= inst.operands[0].reg << 12;
8522 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8523 inst.instruction |= inst.operands[2].reg;
8529 inst.instruction |= inst.operands[0].reg << 12;
8530 inst.instruction |= inst.operands[1].imm << 16;
8531 inst.instruction |= inst.operands[2].reg;
8534 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8535 preserving the other bits.
8537 setend <endian_specifier>, where <endian_specifier> is either
8543 if (warn_on_deprecated
8544 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8545 as_warn (_("setend use is deprecated for ARMv8"));
8547 if (inst.operands[0].imm)
8548 inst.instruction |= 0x200;
8554 unsigned int Rm = (inst.operands[1].present
8555 ? inst.operands[1].reg
8556 : inst.operands[0].reg);
8558 inst.instruction |= inst.operands[0].reg << 12;
8559 inst.instruction |= Rm;
8560 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8562 inst.instruction |= inst.operands[2].reg << 8;
8563 inst.instruction |= SHIFT_BY_REG;
8564 /* PR 12854: Error on extraneous shifts. */
8565 constraint (inst.operands[2].shifted,
8566 _("extraneous shift as part of operand to shift insn"));
8569 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8575 inst.reloc.type = BFD_RELOC_ARM_SMC;
8576 inst.reloc.pc_rel = 0;
8582 inst.reloc.type = BFD_RELOC_ARM_HVC;
8583 inst.reloc.pc_rel = 0;
8589 inst.reloc.type = BFD_RELOC_ARM_SWI;
8590 inst.reloc.pc_rel = 0;
8593 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8594 SMLAxy{cond} Rd,Rm,Rs,Rn
8595 SMLAWy{cond} Rd,Rm,Rs,Rn
8596 Error if any register is R15. */
8601 inst.instruction |= inst.operands[0].reg << 16;
8602 inst.instruction |= inst.operands[1].reg;
8603 inst.instruction |= inst.operands[2].reg << 8;
8604 inst.instruction |= inst.operands[3].reg << 12;
8607 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8608 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8609 Error if any register is R15.
8610 Warning if Rdlo == Rdhi. */
8615 inst.instruction |= inst.operands[0].reg << 12;
8616 inst.instruction |= inst.operands[1].reg << 16;
8617 inst.instruction |= inst.operands[2].reg;
8618 inst.instruction |= inst.operands[3].reg << 8;
8620 if (inst.operands[0].reg == inst.operands[1].reg)
8621 as_tsktsk (_("rdhi and rdlo must be different"));
8624 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8625 SMULxy{cond} Rd,Rm,Rs
8626 Error if any register is R15. */
8631 inst.instruction |= inst.operands[0].reg << 16;
8632 inst.instruction |= inst.operands[1].reg;
8633 inst.instruction |= inst.operands[2].reg << 8;
8636 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8637 the same for both ARM and Thumb-2. */
8644 if (inst.operands[0].present)
8646 reg = inst.operands[0].reg;
8647 constraint (reg != REG_SP, _("SRS base register must be r13"));
8652 inst.instruction |= reg << 16;
8653 inst.instruction |= inst.operands[1].imm;
8654 if (inst.operands[0].writeback || inst.operands[1].writeback)
8655 inst.instruction |= WRITE_BACK;
8658 /* ARM V6 strex (argument parse). */
8663 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8664 || inst.operands[2].postind || inst.operands[2].writeback
8665 || inst.operands[2].immisreg || inst.operands[2].shifted
8666 || inst.operands[2].negative
8667 /* See comment in do_ldrex(). */
8668 || (inst.operands[2].reg == REG_PC),
8671 constraint (inst.operands[0].reg == inst.operands[1].reg
8672 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8674 constraint (inst.reloc.exp.X_op != O_constant
8675 || inst.reloc.exp.X_add_number != 0,
8676 _("offset must be zero in ARM encoding"));
8678 inst.instruction |= inst.operands[0].reg << 12;
8679 inst.instruction |= inst.operands[1].reg;
8680 inst.instruction |= inst.operands[2].reg << 16;
8681 inst.reloc.type = BFD_RELOC_UNUSED;
8687 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8688 || inst.operands[2].postind || inst.operands[2].writeback
8689 || inst.operands[2].immisreg || inst.operands[2].shifted
8690 || inst.operands[2].negative,
8693 constraint (inst.operands[0].reg == inst.operands[1].reg
8694 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8702 constraint (inst.operands[1].reg % 2 != 0,
8703 _("even register required"));
8704 constraint (inst.operands[2].present
8705 && inst.operands[2].reg != inst.operands[1].reg + 1,
8706 _("can only store two consecutive registers"));
8707 /* If op 2 were present and equal to PC, this function wouldn't
8708 have been called in the first place. */
8709 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8711 constraint (inst.operands[0].reg == inst.operands[1].reg
8712 || inst.operands[0].reg == inst.operands[1].reg + 1
8713 || inst.operands[0].reg == inst.operands[3].reg,
8716 inst.instruction |= inst.operands[0].reg << 12;
8717 inst.instruction |= inst.operands[1].reg;
8718 inst.instruction |= inst.operands[3].reg << 16;
8725 constraint (inst.operands[0].reg == inst.operands[1].reg
8726 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8734 constraint (inst.operands[0].reg == inst.operands[1].reg
8735 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8740 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8741 extends it to 32-bits, and adds the result to a value in another
8742 register. You can specify a rotation by 0, 8, 16, or 24 bits
8743 before extracting the 16-bit value.
8744 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8745 Condition defaults to COND_ALWAYS.
8746 Error if any register uses R15. */
8751 inst.instruction |= inst.operands[0].reg << 12;
8752 inst.instruction |= inst.operands[1].reg << 16;
8753 inst.instruction |= inst.operands[2].reg;
8754 inst.instruction |= inst.operands[3].imm << 10;
8759 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8760 Condition defaults to COND_ALWAYS.
8761 Error if any register uses R15. */
8766 inst.instruction |= inst.operands[0].reg << 12;
8767 inst.instruction |= inst.operands[1].reg;
8768 inst.instruction |= inst.operands[2].imm << 10;
8771 /* VFP instructions. In a logical order: SP variant first, monad
8772 before dyad, arithmetic then move then load/store. */
8775 do_vfp_sp_monadic (void)
8777 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8778 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8782 do_vfp_sp_dyadic (void)
8784 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8785 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8786 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8790 do_vfp_sp_compare_z (void)
8792 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8796 do_vfp_dp_sp_cvt (void)
8798 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8799 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8803 do_vfp_sp_dp_cvt (void)
8805 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8806 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8810 do_vfp_reg_from_sp (void)
8812 inst.instruction |= inst.operands[0].reg << 12;
8813 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8817 do_vfp_reg2_from_sp2 (void)
8819 constraint (inst.operands[2].imm != 2,
8820 _("only two consecutive VFP SP registers allowed here"));
8821 inst.instruction |= inst.operands[0].reg << 12;
8822 inst.instruction |= inst.operands[1].reg << 16;
8823 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8827 do_vfp_sp_from_reg (void)
8829 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8830 inst.instruction |= inst.operands[1].reg << 12;
8834 do_vfp_sp2_from_reg2 (void)
8836 constraint (inst.operands[0].imm != 2,
8837 _("only two consecutive VFP SP registers allowed here"));
8838 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8839 inst.instruction |= inst.operands[1].reg << 12;
8840 inst.instruction |= inst.operands[2].reg << 16;
8844 do_vfp_sp_ldst (void)
8846 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8847 encode_arm_cp_address (1, FALSE, TRUE, 0);
8851 do_vfp_dp_ldst (void)
8853 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8854 encode_arm_cp_address (1, FALSE, TRUE, 0);
8859 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8861 if (inst.operands[0].writeback)
8862 inst.instruction |= WRITE_BACK;
8864 constraint (ldstm_type != VFP_LDSTMIA,
8865 _("this addressing mode requires base-register writeback"));
8866 inst.instruction |= inst.operands[0].reg << 16;
8867 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8868 inst.instruction |= inst.operands[1].imm;
8872 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8876 if (inst.operands[0].writeback)
8877 inst.instruction |= WRITE_BACK;
8879 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8880 _("this addressing mode requires base-register writeback"));
8882 inst.instruction |= inst.operands[0].reg << 16;
8883 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8885 count = inst.operands[1].imm << 1;
8886 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8889 inst.instruction |= count;
8893 do_vfp_sp_ldstmia (void)
8895 vfp_sp_ldstm (VFP_LDSTMIA);
8899 do_vfp_sp_ldstmdb (void)
8901 vfp_sp_ldstm (VFP_LDSTMDB);
8905 do_vfp_dp_ldstmia (void)
8907 vfp_dp_ldstm (VFP_LDSTMIA);
8911 do_vfp_dp_ldstmdb (void)
8913 vfp_dp_ldstm (VFP_LDSTMDB);
8917 do_vfp_xp_ldstmia (void)
8919 vfp_dp_ldstm (VFP_LDSTMIAX);
8923 do_vfp_xp_ldstmdb (void)
8925 vfp_dp_ldstm (VFP_LDSTMDBX);
8929 do_vfp_dp_rd_rm (void)
8931 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8932 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8936 do_vfp_dp_rn_rd (void)
8938 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8939 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8943 do_vfp_dp_rd_rn (void)
8945 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8946 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8950 do_vfp_dp_rd_rn_rm (void)
8952 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8953 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8954 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8960 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8964 do_vfp_dp_rm_rd_rn (void)
8966 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8967 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8968 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8971 /* VFPv3 instructions. */
8973 do_vfp_sp_const (void)
8975 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8976 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8977 inst.instruction |= (inst.operands[1].imm & 0x0f);
8981 do_vfp_dp_const (void)
8983 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8984 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8985 inst.instruction |= (inst.operands[1].imm & 0x0f);
8989 vfp_conv (int srcsize)
8991 int immbits = srcsize - inst.operands[1].imm;
8993 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8995 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8996 i.e. immbits must be in range 0 - 16. */
8997 inst.error = _("immediate value out of range, expected range [0, 16]");
9000 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9002 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9003 i.e. immbits must be in range 0 - 31. */
9004 inst.error = _("immediate value out of range, expected range [1, 32]");
9008 inst.instruction |= (immbits & 1) << 5;
9009 inst.instruction |= (immbits >> 1);
9013 do_vfp_sp_conv_16 (void)
9015 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9020 do_vfp_dp_conv_16 (void)
9022 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9027 do_vfp_sp_conv_32 (void)
9029 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9034 do_vfp_dp_conv_32 (void)
9036 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9040 /* FPA instructions. Also in a logical order. */
9045 inst.instruction |= inst.operands[0].reg << 16;
9046 inst.instruction |= inst.operands[1].reg;
9050 do_fpa_ldmstm (void)
9052 inst.instruction |= inst.operands[0].reg << 12;
9053 switch (inst.operands[1].imm)
9055 case 1: inst.instruction |= CP_T_X; break;
9056 case 2: inst.instruction |= CP_T_Y; break;
9057 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9062 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9064 /* The instruction specified "ea" or "fd", so we can only accept
9065 [Rn]{!}. The instruction does not really support stacking or
9066 unstacking, so we have to emulate these by setting appropriate
9067 bits and offsets. */
9068 constraint (inst.reloc.exp.X_op != O_constant
9069 || inst.reloc.exp.X_add_number != 0,
9070 _("this instruction does not support indexing"));
9072 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9073 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9075 if (!(inst.instruction & INDEX_UP))
9076 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9078 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9080 inst.operands[2].preind = 0;
9081 inst.operands[2].postind = 1;
9085 encode_arm_cp_address (2, TRUE, TRUE, 0);
9088 /* iWMMXt instructions: strictly in alphabetical order. */
9091 do_iwmmxt_tandorc (void)
9093 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9097 do_iwmmxt_textrc (void)
9099 inst.instruction |= inst.operands[0].reg << 12;
9100 inst.instruction |= inst.operands[1].imm;
9104 do_iwmmxt_textrm (void)
9106 inst.instruction |= inst.operands[0].reg << 12;
9107 inst.instruction |= inst.operands[1].reg << 16;
9108 inst.instruction |= inst.operands[2].imm;
9112 do_iwmmxt_tinsr (void)
9114 inst.instruction |= inst.operands[0].reg << 16;
9115 inst.instruction |= inst.operands[1].reg << 12;
9116 inst.instruction |= inst.operands[2].imm;
9120 do_iwmmxt_tmia (void)
9122 inst.instruction |= inst.operands[0].reg << 5;
9123 inst.instruction |= inst.operands[1].reg;
9124 inst.instruction |= inst.operands[2].reg << 12;
9128 do_iwmmxt_waligni (void)
9130 inst.instruction |= inst.operands[0].reg << 12;
9131 inst.instruction |= inst.operands[1].reg << 16;
9132 inst.instruction |= inst.operands[2].reg;
9133 inst.instruction |= inst.operands[3].imm << 20;
9137 do_iwmmxt_wmerge (void)
9139 inst.instruction |= inst.operands[0].reg << 12;
9140 inst.instruction |= inst.operands[1].reg << 16;
9141 inst.instruction |= inst.operands[2].reg;
9142 inst.instruction |= inst.operands[3].imm << 21;
9146 do_iwmmxt_wmov (void)
9148 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9149 inst.instruction |= inst.operands[0].reg << 12;
9150 inst.instruction |= inst.operands[1].reg << 16;
9151 inst.instruction |= inst.operands[1].reg;
9155 do_iwmmxt_wldstbh (void)
9158 inst.instruction |= inst.operands[0].reg << 12;
9160 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9162 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9163 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9167 do_iwmmxt_wldstw (void)
9169 /* RIWR_RIWC clears .isreg for a control register. */
9170 if (!inst.operands[0].isreg)
9172 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9173 inst.instruction |= 0xf0000000;
9176 inst.instruction |= inst.operands[0].reg << 12;
9177 encode_arm_cp_address (1, TRUE, TRUE, 0);
9181 do_iwmmxt_wldstd (void)
9183 inst.instruction |= inst.operands[0].reg << 12;
9184 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9185 && inst.operands[1].immisreg)
9187 inst.instruction &= ~0x1a000ff;
9188 inst.instruction |= (0xf << 28);
9189 if (inst.operands[1].preind)
9190 inst.instruction |= PRE_INDEX;
9191 if (!inst.operands[1].negative)
9192 inst.instruction |= INDEX_UP;
9193 if (inst.operands[1].writeback)
9194 inst.instruction |= WRITE_BACK;
9195 inst.instruction |= inst.operands[1].reg << 16;
9196 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9197 inst.instruction |= inst.operands[1].imm;
9200 encode_arm_cp_address (1, TRUE, FALSE, 0);
9204 do_iwmmxt_wshufh (void)
9206 inst.instruction |= inst.operands[0].reg << 12;
9207 inst.instruction |= inst.operands[1].reg << 16;
9208 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9209 inst.instruction |= (inst.operands[2].imm & 0x0f);
9213 do_iwmmxt_wzero (void)
9215 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9216 inst.instruction |= inst.operands[0].reg;
9217 inst.instruction |= inst.operands[0].reg << 12;
9218 inst.instruction |= inst.operands[0].reg << 16;
9222 do_iwmmxt_wrwrwr_or_imm5 (void)
9224 if (inst.operands[2].isreg)
9227 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9228 _("immediate operand requires iWMMXt2"));
9230 if (inst.operands[2].imm == 0)
9232 switch ((inst.instruction >> 20) & 0xf)
9238 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9239 inst.operands[2].imm = 16;
9240 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9246 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9247 inst.operands[2].imm = 32;
9248 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9255 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9257 wrn = (inst.instruction >> 16) & 0xf;
9258 inst.instruction &= 0xff0fff0f;
9259 inst.instruction |= wrn;
9260 /* Bail out here; the instruction is now assembled. */
9265 /* Map 32 -> 0, etc. */
9266 inst.operands[2].imm &= 0x1f;
9267 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9271 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9272 operations first, then control, shift, and load/store. */
9274 /* Insns like "foo X,Y,Z". */
9277 do_mav_triple (void)
9279 inst.instruction |= inst.operands[0].reg << 16;
9280 inst.instruction |= inst.operands[1].reg;
9281 inst.instruction |= inst.operands[2].reg << 12;
9284 /* Insns like "foo W,X,Y,Z".
9285 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9290 inst.instruction |= inst.operands[0].reg << 5;
9291 inst.instruction |= inst.operands[1].reg << 12;
9292 inst.instruction |= inst.operands[2].reg << 16;
9293 inst.instruction |= inst.operands[3].reg;
9296 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9300 inst.instruction |= inst.operands[1].reg << 12;
9303 /* Maverick shift immediate instructions.
9304 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9305 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9310 int imm = inst.operands[2].imm;
9312 inst.instruction |= inst.operands[0].reg << 12;
9313 inst.instruction |= inst.operands[1].reg << 16;
9315 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9316 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9317 Bit 4 should be 0. */
9318 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9320 inst.instruction |= imm;
9323 /* XScale instructions. Also sorted arithmetic before move. */
9325 /* Xscale multiply-accumulate (argument parse)
9328 MIAxycc acc0,Rm,Rs. */
9333 inst.instruction |= inst.operands[1].reg;
9334 inst.instruction |= inst.operands[2].reg << 12;
9337 /* Xscale move-accumulator-register (argument parse)
9339 MARcc acc0,RdLo,RdHi. */
9344 inst.instruction |= inst.operands[1].reg << 12;
9345 inst.instruction |= inst.operands[2].reg << 16;
9348 /* Xscale move-register-accumulator (argument parse)
9350 MRAcc RdLo,RdHi,acc0. */
9355 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9356 inst.instruction |= inst.operands[0].reg << 12;
9357 inst.instruction |= inst.operands[1].reg << 16;
9360 /* Encoding functions relevant only to Thumb. */
9362 /* inst.operands[i] is a shifted-register operand; encode
9363 it into inst.instruction in the format used by Thumb32. */
9366 encode_thumb32_shifted_operand (int i)
9368 unsigned int value = inst.reloc.exp.X_add_number;
9369 unsigned int shift = inst.operands[i].shift_kind;
9371 constraint (inst.operands[i].immisreg,
9372 _("shift by register not allowed in thumb mode"));
9373 inst.instruction |= inst.operands[i].reg;
9374 if (shift == SHIFT_RRX)
9375 inst.instruction |= SHIFT_ROR << 4;
9378 constraint (inst.reloc.exp.X_op != O_constant,
9379 _("expression too complex"));
9381 constraint (value > 32
9382 || (value == 32 && (shift == SHIFT_LSL
9383 || shift == SHIFT_ROR)),
9384 _("shift expression is too large"));
9388 else if (value == 32)
9391 inst.instruction |= shift << 4;
9392 inst.instruction |= (value & 0x1c) << 10;
9393 inst.instruction |= (value & 0x03) << 6;
9398 /* inst.operands[i] was set up by parse_address. Encode it into a
9399 Thumb32 format load or store instruction. Reject forms that cannot
9400 be used with such instructions. If is_t is true, reject forms that
9401 cannot be used with a T instruction; if is_d is true, reject forms
9402 that cannot be used with a D instruction. If it is a store insn,
9406 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9408 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9410 constraint (!inst.operands[i].isreg,
9411 _("Instruction does not support =N addresses"));
9413 inst.instruction |= inst.operands[i].reg << 16;
9414 if (inst.operands[i].immisreg)
9416 constraint (is_pc, BAD_PC_ADDRESSING);
9417 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9418 constraint (inst.operands[i].negative,
9419 _("Thumb does not support negative register indexing"));
9420 constraint (inst.operands[i].postind,
9421 _("Thumb does not support register post-indexing"));
9422 constraint (inst.operands[i].writeback,
9423 _("Thumb does not support register indexing with writeback"));
9424 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9425 _("Thumb supports only LSL in shifted register indexing"));
9427 inst.instruction |= inst.operands[i].imm;
9428 if (inst.operands[i].shifted)
9430 constraint (inst.reloc.exp.X_op != O_constant,
9431 _("expression too complex"));
9432 constraint (inst.reloc.exp.X_add_number < 0
9433 || inst.reloc.exp.X_add_number > 3,
9434 _("shift out of range"));
9435 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9437 inst.reloc.type = BFD_RELOC_UNUSED;
9439 else if (inst.operands[i].preind)
9441 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9442 constraint (is_t && inst.operands[i].writeback,
9443 _("cannot use writeback with this instruction"));
9444 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9449 inst.instruction |= 0x01000000;
9450 if (inst.operands[i].writeback)
9451 inst.instruction |= 0x00200000;
9455 inst.instruction |= 0x00000c00;
9456 if (inst.operands[i].writeback)
9457 inst.instruction |= 0x00000100;
9459 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9461 else if (inst.operands[i].postind)
9463 gas_assert (inst.operands[i].writeback);
9464 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9465 constraint (is_t, _("cannot use post-indexing with this instruction"));
9468 inst.instruction |= 0x00200000;
9470 inst.instruction |= 0x00000900;
9471 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9473 else /* unindexed - only for coprocessor */
9474 inst.error = _("instruction does not accept unindexed addressing");
9477 /* Table of Thumb instructions which exist in both 16- and 32-bit
9478 encodings (the latter only in post-V6T2 cores). The index is the
9479 value used in the insns table below. When there is more than one
9480 possible 16-bit encoding for the instruction, this table always
9482 Also contains several pseudo-instructions used during relaxation. */
9483 #define T16_32_TAB \
9484 X(_adc, 4140, eb400000), \
9485 X(_adcs, 4140, eb500000), \
9486 X(_add, 1c00, eb000000), \
9487 X(_adds, 1c00, eb100000), \
9488 X(_addi, 0000, f1000000), \
9489 X(_addis, 0000, f1100000), \
9490 X(_add_pc,000f, f20f0000), \
9491 X(_add_sp,000d, f10d0000), \
9492 X(_adr, 000f, f20f0000), \
9493 X(_and, 4000, ea000000), \
9494 X(_ands, 4000, ea100000), \
9495 X(_asr, 1000, fa40f000), \
9496 X(_asrs, 1000, fa50f000), \
9497 X(_b, e000, f000b000), \
9498 X(_bcond, d000, f0008000), \
9499 X(_bic, 4380, ea200000), \
9500 X(_bics, 4380, ea300000), \
9501 X(_cmn, 42c0, eb100f00), \
9502 X(_cmp, 2800, ebb00f00), \
9503 X(_cpsie, b660, f3af8400), \
9504 X(_cpsid, b670, f3af8600), \
9505 X(_cpy, 4600, ea4f0000), \
9506 X(_dec_sp,80dd, f1ad0d00), \
9507 X(_eor, 4040, ea800000), \
9508 X(_eors, 4040, ea900000), \
9509 X(_inc_sp,00dd, f10d0d00), \
9510 X(_ldmia, c800, e8900000), \
9511 X(_ldr, 6800, f8500000), \
9512 X(_ldrb, 7800, f8100000), \
9513 X(_ldrh, 8800, f8300000), \
9514 X(_ldrsb, 5600, f9100000), \
9515 X(_ldrsh, 5e00, f9300000), \
9516 X(_ldr_pc,4800, f85f0000), \
9517 X(_ldr_pc2,4800, f85f0000), \
9518 X(_ldr_sp,9800, f85d0000), \
9519 X(_lsl, 0000, fa00f000), \
9520 X(_lsls, 0000, fa10f000), \
9521 X(_lsr, 0800, fa20f000), \
9522 X(_lsrs, 0800, fa30f000), \
9523 X(_mov, 2000, ea4f0000), \
9524 X(_movs, 2000, ea5f0000), \
9525 X(_mul, 4340, fb00f000), \
9526 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9527 X(_mvn, 43c0, ea6f0000), \
9528 X(_mvns, 43c0, ea7f0000), \
9529 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9530 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9531 X(_orr, 4300, ea400000), \
9532 X(_orrs, 4300, ea500000), \
9533 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9534 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9535 X(_rev, ba00, fa90f080), \
9536 X(_rev16, ba40, fa90f090), \
9537 X(_revsh, bac0, fa90f0b0), \
9538 X(_ror, 41c0, fa60f000), \
9539 X(_rors, 41c0, fa70f000), \
9540 X(_sbc, 4180, eb600000), \
9541 X(_sbcs, 4180, eb700000), \
9542 X(_stmia, c000, e8800000), \
9543 X(_str, 6000, f8400000), \
9544 X(_strb, 7000, f8000000), \
9545 X(_strh, 8000, f8200000), \
9546 X(_str_sp,9000, f84d0000), \
9547 X(_sub, 1e00, eba00000), \
9548 X(_subs, 1e00, ebb00000), \
9549 X(_subi, 8000, f1a00000), \
9550 X(_subis, 8000, f1b00000), \
9551 X(_sxtb, b240, fa4ff080), \
9552 X(_sxth, b200, fa0ff080), \
9553 X(_tst, 4200, ea100f00), \
9554 X(_uxtb, b2c0, fa5ff080), \
9555 X(_uxth, b280, fa1ff080), \
9556 X(_nop, bf00, f3af8000), \
9557 X(_yield, bf10, f3af8001), \
9558 X(_wfe, bf20, f3af8002), \
9559 X(_wfi, bf30, f3af8003), \
9560 X(_sev, bf40, f3af8004), \
9561 X(_sevl, bf50, f3af8005)
9563 /* To catch errors in encoding functions, the codes are all offset by
9564 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9565 as 16-bit instructions. */
9566 #define X(a,b,c) T_MNEM##a
9567 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9570 #define X(a,b,c) 0x##b
9571 static const unsigned short thumb_op16[] = { T16_32_TAB };
9572 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9575 #define X(a,b,c) 0x##c
9576 static const unsigned int thumb_op32[] = { T16_32_TAB };
9577 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9578 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9582 /* Thumb instruction encoders, in alphabetical order. */
9587 do_t_add_sub_w (void)
9591 Rd = inst.operands[0].reg;
9592 Rn = inst.operands[1].reg;
9594 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9595 is the SP-{plus,minus}-immediate form of the instruction. */
9597 constraint (Rd == REG_PC, BAD_PC);
9599 reject_bad_reg (Rd);
9601 inst.instruction |= (Rn << 16) | (Rd << 8);
9602 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9605 /* Parse an add or subtract instruction. We get here with inst.instruction
9606 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9613 Rd = inst.operands[0].reg;
9614 Rs = (inst.operands[1].present
9615 ? inst.operands[1].reg /* Rd, Rs, foo */
9616 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9619 set_it_insn_type_last ();
9627 flags = (inst.instruction == T_MNEM_adds
9628 || inst.instruction == T_MNEM_subs);
9630 narrow = !in_it_block ();
9632 narrow = in_it_block ();
9633 if (!inst.operands[2].isreg)
9637 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9639 add = (inst.instruction == T_MNEM_add
9640 || inst.instruction == T_MNEM_adds);
9642 if (inst.size_req != 4)
9644 /* Attempt to use a narrow opcode, with relaxation if
9646 if (Rd == REG_SP && Rs == REG_SP && !flags)
9647 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9648 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9649 opcode = T_MNEM_add_sp;
9650 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9651 opcode = T_MNEM_add_pc;
9652 else if (Rd <= 7 && Rs <= 7 && narrow)
9655 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9657 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9661 inst.instruction = THUMB_OP16(opcode);
9662 inst.instruction |= (Rd << 4) | Rs;
9663 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9664 if (inst.size_req != 2)
9665 inst.relax = opcode;
9668 constraint (inst.size_req == 2, BAD_HIREG);
9670 if (inst.size_req == 4
9671 || (inst.size_req != 2 && !opcode))
9675 constraint (add, BAD_PC);
9676 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9677 _("only SUBS PC, LR, #const allowed"));
9678 constraint (inst.reloc.exp.X_op != O_constant,
9679 _("expression too complex"));
9680 constraint (inst.reloc.exp.X_add_number < 0
9681 || inst.reloc.exp.X_add_number > 0xff,
9682 _("immediate value out of range"));
9683 inst.instruction = T2_SUBS_PC_LR
9684 | inst.reloc.exp.X_add_number;
9685 inst.reloc.type = BFD_RELOC_UNUSED;
9688 else if (Rs == REG_PC)
9690 /* Always use addw/subw. */
9691 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9692 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9696 inst.instruction = THUMB_OP32 (inst.instruction);
9697 inst.instruction = (inst.instruction & 0xe1ffffff)
9700 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9702 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9704 inst.instruction |= Rd << 8;
9705 inst.instruction |= Rs << 16;
9710 unsigned int value = inst.reloc.exp.X_add_number;
9711 unsigned int shift = inst.operands[2].shift_kind;
9713 Rn = inst.operands[2].reg;
9714 /* See if we can do this with a 16-bit instruction. */
9715 if (!inst.operands[2].shifted && inst.size_req != 4)
9717 if (Rd > 7 || Rs > 7 || Rn > 7)
9722 inst.instruction = ((inst.instruction == T_MNEM_adds
9723 || inst.instruction == T_MNEM_add)
9726 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9730 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9732 /* Thumb-1 cores (except v6-M) require at least one high
9733 register in a narrow non flag setting add. */
9734 if (Rd > 7 || Rn > 7
9735 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9736 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9743 inst.instruction = T_OPCODE_ADD_HI;
9744 inst.instruction |= (Rd & 8) << 4;
9745 inst.instruction |= (Rd & 7);
9746 inst.instruction |= Rn << 3;
9752 constraint (Rd == REG_PC, BAD_PC);
9753 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9754 constraint (Rs == REG_PC, BAD_PC);
9755 reject_bad_reg (Rn);
9757 /* If we get here, it can't be done in 16 bits. */
9758 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9759 _("shift must be constant"));
9760 inst.instruction = THUMB_OP32 (inst.instruction);
9761 inst.instruction |= Rd << 8;
9762 inst.instruction |= Rs << 16;
9763 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9764 _("shift value over 3 not allowed in thumb mode"));
9765 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9766 _("only LSL shift allowed in thumb mode"));
9767 encode_thumb32_shifted_operand (2);
9772 constraint (inst.instruction == T_MNEM_adds
9773 || inst.instruction == T_MNEM_subs,
9776 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9778 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9779 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9782 inst.instruction = (inst.instruction == T_MNEM_add
9784 inst.instruction |= (Rd << 4) | Rs;
9785 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9789 Rn = inst.operands[2].reg;
9790 constraint (inst.operands[2].shifted, _("unshifted register required"));
9792 /* We now have Rd, Rs, and Rn set to registers. */
9793 if (Rd > 7 || Rs > 7 || Rn > 7)
9795 /* Can't do this for SUB. */
9796 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9797 inst.instruction = T_OPCODE_ADD_HI;
9798 inst.instruction |= (Rd & 8) << 4;
9799 inst.instruction |= (Rd & 7);
9801 inst.instruction |= Rn << 3;
9803 inst.instruction |= Rs << 3;
9805 constraint (1, _("dest must overlap one source register"));
9809 inst.instruction = (inst.instruction == T_MNEM_add
9810 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9811 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9821 Rd = inst.operands[0].reg;
9822 reject_bad_reg (Rd);
9824 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9826 /* Defer to section relaxation. */
9827 inst.relax = inst.instruction;
9828 inst.instruction = THUMB_OP16 (inst.instruction);
9829 inst.instruction |= Rd << 4;
9831 else if (unified_syntax && inst.size_req != 2)
9833 /* Generate a 32-bit opcode. */
9834 inst.instruction = THUMB_OP32 (inst.instruction);
9835 inst.instruction |= Rd << 8;
9836 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9837 inst.reloc.pc_rel = 1;
9841 /* Generate a 16-bit opcode. */
9842 inst.instruction = THUMB_OP16 (inst.instruction);
9843 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9844 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9845 inst.reloc.pc_rel = 1;
9847 inst.instruction |= Rd << 4;
9851 /* Arithmetic instructions for which there is just one 16-bit
9852 instruction encoding, and it allows only two low registers.
9853 For maximal compatibility with ARM syntax, we allow three register
9854 operands even when Thumb-32 instructions are not available, as long
9855 as the first two are identical. For instance, both "sbc r0,r1" and
9856 "sbc r0,r0,r1" are allowed. */
9862 Rd = inst.operands[0].reg;
9863 Rs = (inst.operands[1].present
9864 ? inst.operands[1].reg /* Rd, Rs, foo */
9865 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9866 Rn = inst.operands[2].reg;
9868 reject_bad_reg (Rd);
9869 reject_bad_reg (Rs);
9870 if (inst.operands[2].isreg)
9871 reject_bad_reg (Rn);
9875 if (!inst.operands[2].isreg)
9877 /* For an immediate, we always generate a 32-bit opcode;
9878 section relaxation will shrink it later if possible. */
9879 inst.instruction = THUMB_OP32 (inst.instruction);
9880 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9881 inst.instruction |= Rd << 8;
9882 inst.instruction |= Rs << 16;
9883 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9889 /* See if we can do this with a 16-bit instruction. */
9890 if (THUMB_SETS_FLAGS (inst.instruction))
9891 narrow = !in_it_block ();
9893 narrow = in_it_block ();
9895 if (Rd > 7 || Rn > 7 || Rs > 7)
9897 if (inst.operands[2].shifted)
9899 if (inst.size_req == 4)
9905 inst.instruction = THUMB_OP16 (inst.instruction);
9906 inst.instruction |= Rd;
9907 inst.instruction |= Rn << 3;
9911 /* If we get here, it can't be done in 16 bits. */
9912 constraint (inst.operands[2].shifted
9913 && inst.operands[2].immisreg,
9914 _("shift must be constant"));
9915 inst.instruction = THUMB_OP32 (inst.instruction);
9916 inst.instruction |= Rd << 8;
9917 inst.instruction |= Rs << 16;
9918 encode_thumb32_shifted_operand (2);
9923 /* On its face this is a lie - the instruction does set the
9924 flags. However, the only supported mnemonic in this mode
9926 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9928 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9929 _("unshifted register required"));
9930 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9931 constraint (Rd != Rs,
9932 _("dest and source1 must be the same register"));
9934 inst.instruction = THUMB_OP16 (inst.instruction);
9935 inst.instruction |= Rd;
9936 inst.instruction |= Rn << 3;
9940 /* Similarly, but for instructions where the arithmetic operation is
9941 commutative, so we can allow either of them to be different from
9942 the destination operand in a 16-bit instruction. For instance, all
9943 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9950 Rd = inst.operands[0].reg;
9951 Rs = (inst.operands[1].present
9952 ? inst.operands[1].reg /* Rd, Rs, foo */
9953 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9954 Rn = inst.operands[2].reg;
9956 reject_bad_reg (Rd);
9957 reject_bad_reg (Rs);
9958 if (inst.operands[2].isreg)
9959 reject_bad_reg (Rn);
9963 if (!inst.operands[2].isreg)
9965 /* For an immediate, we always generate a 32-bit opcode;
9966 section relaxation will shrink it later if possible. */
9967 inst.instruction = THUMB_OP32 (inst.instruction);
9968 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9969 inst.instruction |= Rd << 8;
9970 inst.instruction |= Rs << 16;
9971 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9977 /* See if we can do this with a 16-bit instruction. */
9978 if (THUMB_SETS_FLAGS (inst.instruction))
9979 narrow = !in_it_block ();
9981 narrow = in_it_block ();
9983 if (Rd > 7 || Rn > 7 || Rs > 7)
9985 if (inst.operands[2].shifted)
9987 if (inst.size_req == 4)
9994 inst.instruction = THUMB_OP16 (inst.instruction);
9995 inst.instruction |= Rd;
9996 inst.instruction |= Rn << 3;
10001 inst.instruction = THUMB_OP16 (inst.instruction);
10002 inst.instruction |= Rd;
10003 inst.instruction |= Rs << 3;
10008 /* If we get here, it can't be done in 16 bits. */
10009 constraint (inst.operands[2].shifted
10010 && inst.operands[2].immisreg,
10011 _("shift must be constant"));
10012 inst.instruction = THUMB_OP32 (inst.instruction);
10013 inst.instruction |= Rd << 8;
10014 inst.instruction |= Rs << 16;
10015 encode_thumb32_shifted_operand (2);
10020 /* On its face this is a lie - the instruction does set the
10021 flags. However, the only supported mnemonic in this mode
10022 says it doesn't. */
10023 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10025 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10026 _("unshifted register required"));
10027 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10029 inst.instruction = THUMB_OP16 (inst.instruction);
10030 inst.instruction |= Rd;
10033 inst.instruction |= Rn << 3;
10035 inst.instruction |= Rs << 3;
10037 constraint (1, _("dest must overlap one source register"));
10045 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10046 constraint (msb > 32, _("bit-field extends past end of register"));
10047 /* The instruction encoding stores the LSB and MSB,
10048 not the LSB and width. */
10049 Rd = inst.operands[0].reg;
10050 reject_bad_reg (Rd);
10051 inst.instruction |= Rd << 8;
10052 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10053 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10054 inst.instruction |= msb - 1;
10063 Rd = inst.operands[0].reg;
10064 reject_bad_reg (Rd);
10066 /* #0 in second position is alternative syntax for bfc, which is
10067 the same instruction but with REG_PC in the Rm field. */
10068 if (!inst.operands[1].isreg)
10072 Rn = inst.operands[1].reg;
10073 reject_bad_reg (Rn);
10076 msb = inst.operands[2].imm + inst.operands[3].imm;
10077 constraint (msb > 32, _("bit-field extends past end of register"));
10078 /* The instruction encoding stores the LSB and MSB,
10079 not the LSB and width. */
10080 inst.instruction |= Rd << 8;
10081 inst.instruction |= Rn << 16;
10082 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10083 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10084 inst.instruction |= msb - 1;
10092 Rd = inst.operands[0].reg;
10093 Rn = inst.operands[1].reg;
10095 reject_bad_reg (Rd);
10096 reject_bad_reg (Rn);
10098 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10099 _("bit-field extends past end of register"));
10100 inst.instruction |= Rd << 8;
10101 inst.instruction |= Rn << 16;
10102 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10103 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10104 inst.instruction |= inst.operands[3].imm - 1;
10107 /* ARM V5 Thumb BLX (argument parse)
10108 BLX <target_addr> which is BLX(1)
10109 BLX <Rm> which is BLX(2)
10110 Unfortunately, there are two different opcodes for this mnemonic.
10111 So, the insns[].value is not used, and the code here zaps values
10112 into inst.instruction.
10114 ??? How to take advantage of the additional two bits of displacement
10115 available in Thumb32 mode? Need new relocation? */
10120 set_it_insn_type_last ();
10122 if (inst.operands[0].isreg)
10124 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10125 /* We have a register, so this is BLX(2). */
10126 inst.instruction |= inst.operands[0].reg << 3;
10130 /* No register. This must be BLX(1). */
10131 inst.instruction = 0xf000e800;
10132 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10144 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10146 if (in_it_block ())
10148 /* Conditional branches inside IT blocks are encoded as unconditional
10150 cond = COND_ALWAYS;
10155 if (cond != COND_ALWAYS)
10156 opcode = T_MNEM_bcond;
10158 opcode = inst.instruction;
10161 && (inst.size_req == 4
10162 || (inst.size_req != 2
10163 && (inst.operands[0].hasreloc
10164 || inst.reloc.exp.X_op == O_constant))))
10166 inst.instruction = THUMB_OP32(opcode);
10167 if (cond == COND_ALWAYS)
10168 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10171 gas_assert (cond != 0xF);
10172 inst.instruction |= cond << 22;
10173 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10178 inst.instruction = THUMB_OP16(opcode);
10179 if (cond == COND_ALWAYS)
10180 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10183 inst.instruction |= cond << 8;
10184 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10186 /* Allow section relaxation. */
10187 if (unified_syntax && inst.size_req != 2)
10188 inst.relax = opcode;
10190 inst.reloc.type = reloc;
10191 inst.reloc.pc_rel = 1;
10194 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10195 between the two is the maximum immediate allowed - which is passed in
10198 do_t_bkpt_hlt1 (int range)
10200 constraint (inst.cond != COND_ALWAYS,
10201 _("instruction is always unconditional"));
10202 if (inst.operands[0].present)
10204 constraint (inst.operands[0].imm > range,
10205 _("immediate value out of range"));
10206 inst.instruction |= inst.operands[0].imm;
10209 set_it_insn_type (NEUTRAL_IT_INSN);
10215 do_t_bkpt_hlt1 (63);
10221 do_t_bkpt_hlt1 (255);
10225 do_t_branch23 (void)
10227 set_it_insn_type_last ();
10228 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10230 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10231 this file. We used to simply ignore the PLT reloc type here --
10232 the branch encoding is now needed to deal with TLSCALL relocs.
10233 So if we see a PLT reloc now, put it back to how it used to be to
10234 keep the preexisting behaviour. */
10235 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10236 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10238 #if defined(OBJ_COFF)
10239 /* If the destination of the branch is a defined symbol which does not have
10240 the THUMB_FUNC attribute, then we must be calling a function which has
10241 the (interfacearm) attribute. We look for the Thumb entry point to that
10242 function and change the branch to refer to that function instead. */
10243 if ( inst.reloc.exp.X_op == O_symbol
10244 && inst.reloc.exp.X_add_symbol != NULL
10245 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10246 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10247 inst.reloc.exp.X_add_symbol =
10248 find_real_start (inst.reloc.exp.X_add_symbol);
10255 set_it_insn_type_last ();
10256 inst.instruction |= inst.operands[0].reg << 3;
10257 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10258 should cause the alignment to be checked once it is known. This is
10259 because BX PC only works if the instruction is word aligned. */
10267 set_it_insn_type_last ();
10268 Rm = inst.operands[0].reg;
10269 reject_bad_reg (Rm);
10270 inst.instruction |= Rm << 16;
10279 Rd = inst.operands[0].reg;
10280 Rm = inst.operands[1].reg;
10282 reject_bad_reg (Rd);
10283 reject_bad_reg (Rm);
10285 inst.instruction |= Rd << 8;
10286 inst.instruction |= Rm << 16;
10287 inst.instruction |= Rm;
10293 set_it_insn_type (OUTSIDE_IT_INSN);
10294 inst.instruction |= inst.operands[0].imm;
10300 set_it_insn_type (OUTSIDE_IT_INSN);
10302 && (inst.operands[1].present || inst.size_req == 4)
10303 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10305 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10306 inst.instruction = 0xf3af8000;
10307 inst.instruction |= imod << 9;
10308 inst.instruction |= inst.operands[0].imm << 5;
10309 if (inst.operands[1].present)
10310 inst.instruction |= 0x100 | inst.operands[1].imm;
10314 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10315 && (inst.operands[0].imm & 4),
10316 _("selected processor does not support 'A' form "
10317 "of this instruction"));
10318 constraint (inst.operands[1].present || inst.size_req == 4,
10319 _("Thumb does not support the 2-argument "
10320 "form of this instruction"));
10321 inst.instruction |= inst.operands[0].imm;
10325 /* THUMB CPY instruction (argument parse). */
10330 if (inst.size_req == 4)
10332 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10333 inst.instruction |= inst.operands[0].reg << 8;
10334 inst.instruction |= inst.operands[1].reg;
10338 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10339 inst.instruction |= (inst.operands[0].reg & 0x7);
10340 inst.instruction |= inst.operands[1].reg << 3;
10347 set_it_insn_type (OUTSIDE_IT_INSN);
10348 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10349 inst.instruction |= inst.operands[0].reg;
10350 inst.reloc.pc_rel = 1;
10351 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10357 inst.instruction |= inst.operands[0].imm;
10363 unsigned Rd, Rn, Rm;
10365 Rd = inst.operands[0].reg;
10366 Rn = (inst.operands[1].present
10367 ? inst.operands[1].reg : Rd);
10368 Rm = inst.operands[2].reg;
10370 reject_bad_reg (Rd);
10371 reject_bad_reg (Rn);
10372 reject_bad_reg (Rm);
10374 inst.instruction |= Rd << 8;
10375 inst.instruction |= Rn << 16;
10376 inst.instruction |= Rm;
10382 if (unified_syntax && inst.size_req == 4)
10383 inst.instruction = THUMB_OP32 (inst.instruction);
10385 inst.instruction = THUMB_OP16 (inst.instruction);
10391 unsigned int cond = inst.operands[0].imm;
10393 set_it_insn_type (IT_INSN);
10394 now_it.mask = (inst.instruction & 0xf) | 0x10;
10396 now_it.warn_deprecated = FALSE;
10398 /* If the condition is a negative condition, invert the mask. */
10399 if ((cond & 0x1) == 0x0)
10401 unsigned int mask = inst.instruction & 0x000f;
10403 if ((mask & 0x7) == 0)
10405 /* No conversion needed. */
10406 now_it.block_length = 1;
10408 else if ((mask & 0x3) == 0)
10411 now_it.block_length = 2;
10413 else if ((mask & 0x1) == 0)
10416 now_it.block_length = 3;
10421 now_it.block_length = 4;
10424 inst.instruction &= 0xfff0;
10425 inst.instruction |= mask;
10428 inst.instruction |= cond << 4;
10431 /* Helper function used for both push/pop and ldm/stm. */
10433 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10437 load = (inst.instruction & (1 << 20)) != 0;
10439 if (mask & (1 << 13))
10440 inst.error = _("SP not allowed in register list");
10442 if ((mask & (1 << base)) != 0
10444 inst.error = _("having the base register in the register list when "
10445 "using write back is UNPREDICTABLE");
10449 if (mask & (1 << 15))
10451 if (mask & (1 << 14))
10452 inst.error = _("LR and PC should not both be in register list");
10454 set_it_insn_type_last ();
10459 if (mask & (1 << 15))
10460 inst.error = _("PC not allowed in register list");
10463 if ((mask & (mask - 1)) == 0)
10465 /* Single register transfers implemented as str/ldr. */
10468 if (inst.instruction & (1 << 23))
10469 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10471 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10475 if (inst.instruction & (1 << 23))
10476 inst.instruction = 0x00800000; /* ia -> [base] */
10478 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10481 inst.instruction |= 0xf8400000;
10483 inst.instruction |= 0x00100000;
10485 mask = ffs (mask) - 1;
10488 else if (writeback)
10489 inst.instruction |= WRITE_BACK;
10491 inst.instruction |= mask;
10492 inst.instruction |= base << 16;
10498 /* This really doesn't seem worth it. */
10499 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10500 _("expression too complex"));
10501 constraint (inst.operands[1].writeback,
10502 _("Thumb load/store multiple does not support {reglist}^"));
10504 if (unified_syntax)
10506 bfd_boolean narrow;
10510 /* See if we can use a 16-bit instruction. */
10511 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10512 && inst.size_req != 4
10513 && !(inst.operands[1].imm & ~0xff))
10515 mask = 1 << inst.operands[0].reg;
10517 if (inst.operands[0].reg <= 7)
10519 if (inst.instruction == T_MNEM_stmia
10520 ? inst.operands[0].writeback
10521 : (inst.operands[0].writeback
10522 == !(inst.operands[1].imm & mask)))
10524 if (inst.instruction == T_MNEM_stmia
10525 && (inst.operands[1].imm & mask)
10526 && (inst.operands[1].imm & (mask - 1)))
10527 as_warn (_("value stored for r%d is UNKNOWN"),
10528 inst.operands[0].reg);
10530 inst.instruction = THUMB_OP16 (inst.instruction);
10531 inst.instruction |= inst.operands[0].reg << 8;
10532 inst.instruction |= inst.operands[1].imm;
10535 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10537 /* This means 1 register in reg list one of 3 situations:
10538 1. Instruction is stmia, but without writeback.
10539 2. lmdia without writeback, but with Rn not in
10541 3. ldmia with writeback, but with Rn in reglist.
10542 Case 3 is UNPREDICTABLE behaviour, so we handle
10543 case 1 and 2 which can be converted into a 16-bit
10544 str or ldr. The SP cases are handled below. */
10545 unsigned long opcode;
10546 /* First, record an error for Case 3. */
10547 if (inst.operands[1].imm & mask
10548 && inst.operands[0].writeback)
10550 _("having the base register in the register list when "
10551 "using write back is UNPREDICTABLE");
10553 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10555 inst.instruction = THUMB_OP16 (opcode);
10556 inst.instruction |= inst.operands[0].reg << 3;
10557 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10561 else if (inst.operands[0] .reg == REG_SP)
10563 if (inst.operands[0].writeback)
10566 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10567 ? T_MNEM_push : T_MNEM_pop);
10568 inst.instruction |= inst.operands[1].imm;
10571 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10574 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10575 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10576 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10584 if (inst.instruction < 0xffff)
10585 inst.instruction = THUMB_OP32 (inst.instruction);
10587 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10588 inst.operands[0].writeback);
10593 constraint (inst.operands[0].reg > 7
10594 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10595 constraint (inst.instruction != T_MNEM_ldmia
10596 && inst.instruction != T_MNEM_stmia,
10597 _("Thumb-2 instruction only valid in unified syntax"));
10598 if (inst.instruction == T_MNEM_stmia)
10600 if (!inst.operands[0].writeback)
10601 as_warn (_("this instruction will write back the base register"));
10602 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10603 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10604 as_warn (_("value stored for r%d is UNKNOWN"),
10605 inst.operands[0].reg);
10609 if (!inst.operands[0].writeback
10610 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10611 as_warn (_("this instruction will write back the base register"));
10612 else if (inst.operands[0].writeback
10613 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10614 as_warn (_("this instruction will not write back the base register"));
10617 inst.instruction = THUMB_OP16 (inst.instruction);
10618 inst.instruction |= inst.operands[0].reg << 8;
10619 inst.instruction |= inst.operands[1].imm;
10626 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10627 || inst.operands[1].postind || inst.operands[1].writeback
10628 || inst.operands[1].immisreg || inst.operands[1].shifted
10629 || inst.operands[1].negative,
10632 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10634 inst.instruction |= inst.operands[0].reg << 12;
10635 inst.instruction |= inst.operands[1].reg << 16;
10636 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10642 if (!inst.operands[1].present)
10644 constraint (inst.operands[0].reg == REG_LR,
10645 _("r14 not allowed as first register "
10646 "when second register is omitted"));
10647 inst.operands[1].reg = inst.operands[0].reg + 1;
10649 constraint (inst.operands[0].reg == inst.operands[1].reg,
10652 inst.instruction |= inst.operands[0].reg << 12;
10653 inst.instruction |= inst.operands[1].reg << 8;
10654 inst.instruction |= inst.operands[2].reg << 16;
10660 unsigned long opcode;
10663 if (inst.operands[0].isreg
10664 && !inst.operands[0].preind
10665 && inst.operands[0].reg == REG_PC)
10666 set_it_insn_type_last ();
10668 opcode = inst.instruction;
10669 if (unified_syntax)
10671 if (!inst.operands[1].isreg)
10673 if (opcode <= 0xffff)
10674 inst.instruction = THUMB_OP32 (opcode);
10675 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10678 if (inst.operands[1].isreg
10679 && !inst.operands[1].writeback
10680 && !inst.operands[1].shifted && !inst.operands[1].postind
10681 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10682 && opcode <= 0xffff
10683 && inst.size_req != 4)
10685 /* Insn may have a 16-bit form. */
10686 Rn = inst.operands[1].reg;
10687 if (inst.operands[1].immisreg)
10689 inst.instruction = THUMB_OP16 (opcode);
10691 if (Rn <= 7 && inst.operands[1].imm <= 7)
10693 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10694 reject_bad_reg (inst.operands[1].imm);
10696 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10697 && opcode != T_MNEM_ldrsb)
10698 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10699 || (Rn == REG_SP && opcode == T_MNEM_str))
10706 if (inst.reloc.pc_rel)
10707 opcode = T_MNEM_ldr_pc2;
10709 opcode = T_MNEM_ldr_pc;
10713 if (opcode == T_MNEM_ldr)
10714 opcode = T_MNEM_ldr_sp;
10716 opcode = T_MNEM_str_sp;
10718 inst.instruction = inst.operands[0].reg << 8;
10722 inst.instruction = inst.operands[0].reg;
10723 inst.instruction |= inst.operands[1].reg << 3;
10725 inst.instruction |= THUMB_OP16 (opcode);
10726 if (inst.size_req == 2)
10727 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10729 inst.relax = opcode;
10733 /* Definitely a 32-bit variant. */
10735 /* Warning for Erratum 752419. */
10736 if (opcode == T_MNEM_ldr
10737 && inst.operands[0].reg == REG_SP
10738 && inst.operands[1].writeback == 1
10739 && !inst.operands[1].immisreg)
10741 if (no_cpu_selected ()
10742 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10743 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10744 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10745 as_warn (_("This instruction may be unpredictable "
10746 "if executed on M-profile cores "
10747 "with interrupts enabled."));
10750 /* Do some validations regarding addressing modes. */
10751 if (inst.operands[1].immisreg)
10752 reject_bad_reg (inst.operands[1].imm);
10754 constraint (inst.operands[1].writeback == 1
10755 && inst.operands[0].reg == inst.operands[1].reg,
10758 inst.instruction = THUMB_OP32 (opcode);
10759 inst.instruction |= inst.operands[0].reg << 12;
10760 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10761 check_ldr_r15_aligned ();
10765 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10767 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10769 /* Only [Rn,Rm] is acceptable. */
10770 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10771 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10772 || inst.operands[1].postind || inst.operands[1].shifted
10773 || inst.operands[1].negative,
10774 _("Thumb does not support this addressing mode"));
10775 inst.instruction = THUMB_OP16 (inst.instruction);
10779 inst.instruction = THUMB_OP16 (inst.instruction);
10780 if (!inst.operands[1].isreg)
10781 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10784 constraint (!inst.operands[1].preind
10785 || inst.operands[1].shifted
10786 || inst.operands[1].writeback,
10787 _("Thumb does not support this addressing mode"));
10788 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10790 constraint (inst.instruction & 0x0600,
10791 _("byte or halfword not valid for base register"));
10792 constraint (inst.operands[1].reg == REG_PC
10793 && !(inst.instruction & THUMB_LOAD_BIT),
10794 _("r15 based store not allowed"));
10795 constraint (inst.operands[1].immisreg,
10796 _("invalid base register for register offset"));
10798 if (inst.operands[1].reg == REG_PC)
10799 inst.instruction = T_OPCODE_LDR_PC;
10800 else if (inst.instruction & THUMB_LOAD_BIT)
10801 inst.instruction = T_OPCODE_LDR_SP;
10803 inst.instruction = T_OPCODE_STR_SP;
10805 inst.instruction |= inst.operands[0].reg << 8;
10806 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10810 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10811 if (!inst.operands[1].immisreg)
10813 /* Immediate offset. */
10814 inst.instruction |= inst.operands[0].reg;
10815 inst.instruction |= inst.operands[1].reg << 3;
10816 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10820 /* Register offset. */
10821 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10822 constraint (inst.operands[1].negative,
10823 _("Thumb does not support this addressing mode"));
10826 switch (inst.instruction)
10828 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10829 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10830 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10831 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10832 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10833 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10834 case 0x5600 /* ldrsb */:
10835 case 0x5e00 /* ldrsh */: break;
10839 inst.instruction |= inst.operands[0].reg;
10840 inst.instruction |= inst.operands[1].reg << 3;
10841 inst.instruction |= inst.operands[1].imm << 6;
10847 if (!inst.operands[1].present)
10849 inst.operands[1].reg = inst.operands[0].reg + 1;
10850 constraint (inst.operands[0].reg == REG_LR,
10851 _("r14 not allowed here"));
10852 constraint (inst.operands[0].reg == REG_R12,
10853 _("r12 not allowed here"));
10856 if (inst.operands[2].writeback
10857 && (inst.operands[0].reg == inst.operands[2].reg
10858 || inst.operands[1].reg == inst.operands[2].reg))
10859 as_warn (_("base register written back, and overlaps "
10860 "one of transfer registers"));
10862 inst.instruction |= inst.operands[0].reg << 12;
10863 inst.instruction |= inst.operands[1].reg << 8;
10864 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10870 inst.instruction |= inst.operands[0].reg << 12;
10871 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10877 unsigned Rd, Rn, Rm, Ra;
10879 Rd = inst.operands[0].reg;
10880 Rn = inst.operands[1].reg;
10881 Rm = inst.operands[2].reg;
10882 Ra = inst.operands[3].reg;
10884 reject_bad_reg (Rd);
10885 reject_bad_reg (Rn);
10886 reject_bad_reg (Rm);
10887 reject_bad_reg (Ra);
10889 inst.instruction |= Rd << 8;
10890 inst.instruction |= Rn << 16;
10891 inst.instruction |= Rm;
10892 inst.instruction |= Ra << 12;
10898 unsigned RdLo, RdHi, Rn, Rm;
10900 RdLo = inst.operands[0].reg;
10901 RdHi = inst.operands[1].reg;
10902 Rn = inst.operands[2].reg;
10903 Rm = inst.operands[3].reg;
10905 reject_bad_reg (RdLo);
10906 reject_bad_reg (RdHi);
10907 reject_bad_reg (Rn);
10908 reject_bad_reg (Rm);
10910 inst.instruction |= RdLo << 12;
10911 inst.instruction |= RdHi << 8;
10912 inst.instruction |= Rn << 16;
10913 inst.instruction |= Rm;
10917 do_t_mov_cmp (void)
10921 Rn = inst.operands[0].reg;
10922 Rm = inst.operands[1].reg;
10925 set_it_insn_type_last ();
10927 if (unified_syntax)
10929 int r0off = (inst.instruction == T_MNEM_mov
10930 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10931 unsigned long opcode;
10932 bfd_boolean narrow;
10933 bfd_boolean low_regs;
10935 low_regs = (Rn <= 7 && Rm <= 7);
10936 opcode = inst.instruction;
10937 if (in_it_block ())
10938 narrow = opcode != T_MNEM_movs;
10940 narrow = opcode != T_MNEM_movs || low_regs;
10941 if (inst.size_req == 4
10942 || inst.operands[1].shifted)
10945 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10946 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10947 && !inst.operands[1].shifted
10951 inst.instruction = T2_SUBS_PC_LR;
10955 if (opcode == T_MNEM_cmp)
10957 constraint (Rn == REG_PC, BAD_PC);
10960 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10962 warn_deprecated_sp (Rm);
10963 /* R15 was documented as a valid choice for Rm in ARMv6,
10964 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10965 tools reject R15, so we do too. */
10966 constraint (Rm == REG_PC, BAD_PC);
10969 reject_bad_reg (Rm);
10971 else if (opcode == T_MNEM_mov
10972 || opcode == T_MNEM_movs)
10974 if (inst.operands[1].isreg)
10976 if (opcode == T_MNEM_movs)
10978 reject_bad_reg (Rn);
10979 reject_bad_reg (Rm);
10983 /* This is mov.n. */
10984 if ((Rn == REG_SP || Rn == REG_PC)
10985 && (Rm == REG_SP || Rm == REG_PC))
10987 as_warn (_("Use of r%u as a source register is "
10988 "deprecated when r%u is the destination "
10989 "register."), Rm, Rn);
10994 /* This is mov.w. */
10995 constraint (Rn == REG_PC, BAD_PC);
10996 constraint (Rm == REG_PC, BAD_PC);
10997 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11001 reject_bad_reg (Rn);
11004 if (!inst.operands[1].isreg)
11006 /* Immediate operand. */
11007 if (!in_it_block () && opcode == T_MNEM_mov)
11009 if (low_regs && narrow)
11011 inst.instruction = THUMB_OP16 (opcode);
11012 inst.instruction |= Rn << 8;
11013 if (inst.size_req == 2)
11014 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11016 inst.relax = opcode;
11020 inst.instruction = THUMB_OP32 (inst.instruction);
11021 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11022 inst.instruction |= Rn << r0off;
11023 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11026 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11027 && (inst.instruction == T_MNEM_mov
11028 || inst.instruction == T_MNEM_movs))
11030 /* Register shifts are encoded as separate shift instructions. */
11031 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11033 if (in_it_block ())
11038 if (inst.size_req == 4)
11041 if (!low_regs || inst.operands[1].imm > 7)
11047 switch (inst.operands[1].shift_kind)
11050 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11053 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11056 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11059 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11065 inst.instruction = opcode;
11068 inst.instruction |= Rn;
11069 inst.instruction |= inst.operands[1].imm << 3;
11074 inst.instruction |= CONDS_BIT;
11076 inst.instruction |= Rn << 8;
11077 inst.instruction |= Rm << 16;
11078 inst.instruction |= inst.operands[1].imm;
11083 /* Some mov with immediate shift have narrow variants.
11084 Register shifts are handled above. */
11085 if (low_regs && inst.operands[1].shifted
11086 && (inst.instruction == T_MNEM_mov
11087 || inst.instruction == T_MNEM_movs))
11089 if (in_it_block ())
11090 narrow = (inst.instruction == T_MNEM_mov);
11092 narrow = (inst.instruction == T_MNEM_movs);
11097 switch (inst.operands[1].shift_kind)
11099 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11100 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11101 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11102 default: narrow = FALSE; break;
11108 inst.instruction |= Rn;
11109 inst.instruction |= Rm << 3;
11110 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11114 inst.instruction = THUMB_OP32 (inst.instruction);
11115 inst.instruction |= Rn << r0off;
11116 encode_thumb32_shifted_operand (1);
11120 switch (inst.instruction)
11123 /* In v4t or v5t a move of two lowregs produces unpredictable
11124 results. Don't allow this. */
11127 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11128 "MOV Rd, Rs with two low registers is not "
11129 "permitted on this architecture");
11130 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11134 inst.instruction = T_OPCODE_MOV_HR;
11135 inst.instruction |= (Rn & 0x8) << 4;
11136 inst.instruction |= (Rn & 0x7);
11137 inst.instruction |= Rm << 3;
11141 /* We know we have low registers at this point.
11142 Generate LSLS Rd, Rs, #0. */
11143 inst.instruction = T_OPCODE_LSL_I;
11144 inst.instruction |= Rn;
11145 inst.instruction |= Rm << 3;
11151 inst.instruction = T_OPCODE_CMP_LR;
11152 inst.instruction |= Rn;
11153 inst.instruction |= Rm << 3;
11157 inst.instruction = T_OPCODE_CMP_HR;
11158 inst.instruction |= (Rn & 0x8) << 4;
11159 inst.instruction |= (Rn & 0x7);
11160 inst.instruction |= Rm << 3;
11167 inst.instruction = THUMB_OP16 (inst.instruction);
11169 /* PR 10443: Do not silently ignore shifted operands. */
11170 constraint (inst.operands[1].shifted,
11171 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11173 if (inst.operands[1].isreg)
11175 if (Rn < 8 && Rm < 8)
11177 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11178 since a MOV instruction produces unpredictable results. */
11179 if (inst.instruction == T_OPCODE_MOV_I8)
11180 inst.instruction = T_OPCODE_ADD_I3;
11182 inst.instruction = T_OPCODE_CMP_LR;
11184 inst.instruction |= Rn;
11185 inst.instruction |= Rm << 3;
11189 if (inst.instruction == T_OPCODE_MOV_I8)
11190 inst.instruction = T_OPCODE_MOV_HR;
11192 inst.instruction = T_OPCODE_CMP_HR;
11198 constraint (Rn > 7,
11199 _("only lo regs allowed with immediate"));
11200 inst.instruction |= Rn << 8;
11201 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11212 top = (inst.instruction & 0x00800000) != 0;
11213 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11215 constraint (top, _(":lower16: not allowed this instruction"));
11216 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11218 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11220 constraint (!top, _(":upper16: not allowed this instruction"));
11221 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11224 Rd = inst.operands[0].reg;
11225 reject_bad_reg (Rd);
11227 inst.instruction |= Rd << 8;
11228 if (inst.reloc.type == BFD_RELOC_UNUSED)
11230 imm = inst.reloc.exp.X_add_number;
11231 inst.instruction |= (imm & 0xf000) << 4;
11232 inst.instruction |= (imm & 0x0800) << 15;
11233 inst.instruction |= (imm & 0x0700) << 4;
11234 inst.instruction |= (imm & 0x00ff);
11239 do_t_mvn_tst (void)
11243 Rn = inst.operands[0].reg;
11244 Rm = inst.operands[1].reg;
11246 if (inst.instruction == T_MNEM_cmp
11247 || inst.instruction == T_MNEM_cmn)
11248 constraint (Rn == REG_PC, BAD_PC);
11250 reject_bad_reg (Rn);
11251 reject_bad_reg (Rm);
11253 if (unified_syntax)
11255 int r0off = (inst.instruction == T_MNEM_mvn
11256 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11257 bfd_boolean narrow;
11259 if (inst.size_req == 4
11260 || inst.instruction > 0xffff
11261 || inst.operands[1].shifted
11262 || Rn > 7 || Rm > 7)
11264 else if (inst.instruction == T_MNEM_cmn)
11266 else if (THUMB_SETS_FLAGS (inst.instruction))
11267 narrow = !in_it_block ();
11269 narrow = in_it_block ();
11271 if (!inst.operands[1].isreg)
11273 /* For an immediate, we always generate a 32-bit opcode;
11274 section relaxation will shrink it later if possible. */
11275 if (inst.instruction < 0xffff)
11276 inst.instruction = THUMB_OP32 (inst.instruction);
11277 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11278 inst.instruction |= Rn << r0off;
11279 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11283 /* See if we can do this with a 16-bit instruction. */
11286 inst.instruction = THUMB_OP16 (inst.instruction);
11287 inst.instruction |= Rn;
11288 inst.instruction |= Rm << 3;
11292 constraint (inst.operands[1].shifted
11293 && inst.operands[1].immisreg,
11294 _("shift must be constant"));
11295 if (inst.instruction < 0xffff)
11296 inst.instruction = THUMB_OP32 (inst.instruction);
11297 inst.instruction |= Rn << r0off;
11298 encode_thumb32_shifted_operand (1);
11304 constraint (inst.instruction > 0xffff
11305 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11306 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11307 _("unshifted register required"));
11308 constraint (Rn > 7 || Rm > 7,
11311 inst.instruction = THUMB_OP16 (inst.instruction);
11312 inst.instruction |= Rn;
11313 inst.instruction |= Rm << 3;
11322 if (do_vfp_nsyn_mrs () == SUCCESS)
11325 Rd = inst.operands[0].reg;
11326 reject_bad_reg (Rd);
11327 inst.instruction |= Rd << 8;
11329 if (inst.operands[1].isreg)
11331 unsigned br = inst.operands[1].reg;
11332 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11333 as_bad (_("bad register for mrs"));
11335 inst.instruction |= br & (0xf << 16);
11336 inst.instruction |= (br & 0x300) >> 4;
11337 inst.instruction |= (br & SPSR_BIT) >> 2;
11341 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11343 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11345 /* PR gas/12698: The constraint is only applied for m_profile.
11346 If the user has specified -march=all, we want to ignore it as
11347 we are building for any CPU type, including non-m variants. */
11348 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11349 constraint ((flags != 0) && m_profile, _("selected processor does "
11350 "not support requested special purpose register"));
11353 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11355 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11356 _("'APSR', 'CPSR' or 'SPSR' expected"));
11358 inst.instruction |= (flags & SPSR_BIT) >> 2;
11359 inst.instruction |= inst.operands[1].imm & 0xff;
11360 inst.instruction |= 0xf0000;
11370 if (do_vfp_nsyn_msr () == SUCCESS)
11373 constraint (!inst.operands[1].isreg,
11374 _("Thumb encoding does not support an immediate here"));
11376 if (inst.operands[0].isreg)
11377 flags = (int)(inst.operands[0].reg);
11379 flags = inst.operands[0].imm;
11381 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11383 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11385 /* PR gas/12698: The constraint is only applied for m_profile.
11386 If the user has specified -march=all, we want to ignore it as
11387 we are building for any CPU type, including non-m variants. */
11388 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11389 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11390 && (bits & ~(PSR_s | PSR_f)) != 0)
11391 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11392 && bits != PSR_f)) && m_profile,
11393 _("selected processor does not support requested special "
11394 "purpose register"));
11397 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11398 "requested special purpose register"));
11400 Rn = inst.operands[1].reg;
11401 reject_bad_reg (Rn);
11403 inst.instruction |= (flags & SPSR_BIT) >> 2;
11404 inst.instruction |= (flags & 0xf0000) >> 8;
11405 inst.instruction |= (flags & 0x300) >> 4;
11406 inst.instruction |= (flags & 0xff);
11407 inst.instruction |= Rn << 16;
11413 bfd_boolean narrow;
11414 unsigned Rd, Rn, Rm;
11416 if (!inst.operands[2].present)
11417 inst.operands[2].reg = inst.operands[0].reg;
11419 Rd = inst.operands[0].reg;
11420 Rn = inst.operands[1].reg;
11421 Rm = inst.operands[2].reg;
11423 if (unified_syntax)
11425 if (inst.size_req == 4
11431 else if (inst.instruction == T_MNEM_muls)
11432 narrow = !in_it_block ();
11434 narrow = in_it_block ();
11438 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11439 constraint (Rn > 7 || Rm > 7,
11446 /* 16-bit MULS/Conditional MUL. */
11447 inst.instruction = THUMB_OP16 (inst.instruction);
11448 inst.instruction |= Rd;
11451 inst.instruction |= Rm << 3;
11453 inst.instruction |= Rn << 3;
11455 constraint (1, _("dest must overlap one source register"));
11459 constraint (inst.instruction != T_MNEM_mul,
11460 _("Thumb-2 MUL must not set flags"));
11462 inst.instruction = THUMB_OP32 (inst.instruction);
11463 inst.instruction |= Rd << 8;
11464 inst.instruction |= Rn << 16;
11465 inst.instruction |= Rm << 0;
11467 reject_bad_reg (Rd);
11468 reject_bad_reg (Rn);
11469 reject_bad_reg (Rm);
11476 unsigned RdLo, RdHi, Rn, Rm;
11478 RdLo = inst.operands[0].reg;
11479 RdHi = inst.operands[1].reg;
11480 Rn = inst.operands[2].reg;
11481 Rm = inst.operands[3].reg;
11483 reject_bad_reg (RdLo);
11484 reject_bad_reg (RdHi);
11485 reject_bad_reg (Rn);
11486 reject_bad_reg (Rm);
11488 inst.instruction |= RdLo << 12;
11489 inst.instruction |= RdHi << 8;
11490 inst.instruction |= Rn << 16;
11491 inst.instruction |= Rm;
11494 as_tsktsk (_("rdhi and rdlo must be different"));
11500 set_it_insn_type (NEUTRAL_IT_INSN);
11502 if (unified_syntax)
11504 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11506 inst.instruction = THUMB_OP32 (inst.instruction);
11507 inst.instruction |= inst.operands[0].imm;
11511 /* PR9722: Check for Thumb2 availability before
11512 generating a thumb2 nop instruction. */
11513 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11515 inst.instruction = THUMB_OP16 (inst.instruction);
11516 inst.instruction |= inst.operands[0].imm << 4;
11519 inst.instruction = 0x46c0;
11524 constraint (inst.operands[0].present,
11525 _("Thumb does not support NOP with hints"));
11526 inst.instruction = 0x46c0;
11533 if (unified_syntax)
11535 bfd_boolean narrow;
11537 if (THUMB_SETS_FLAGS (inst.instruction))
11538 narrow = !in_it_block ();
11540 narrow = in_it_block ();
11541 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11543 if (inst.size_req == 4)
11548 inst.instruction = THUMB_OP32 (inst.instruction);
11549 inst.instruction |= inst.operands[0].reg << 8;
11550 inst.instruction |= inst.operands[1].reg << 16;
11554 inst.instruction = THUMB_OP16 (inst.instruction);
11555 inst.instruction |= inst.operands[0].reg;
11556 inst.instruction |= inst.operands[1].reg << 3;
11561 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11563 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11565 inst.instruction = THUMB_OP16 (inst.instruction);
11566 inst.instruction |= inst.operands[0].reg;
11567 inst.instruction |= inst.operands[1].reg << 3;
11576 Rd = inst.operands[0].reg;
11577 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11579 reject_bad_reg (Rd);
11580 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11581 reject_bad_reg (Rn);
11583 inst.instruction |= Rd << 8;
11584 inst.instruction |= Rn << 16;
11586 if (!inst.operands[2].isreg)
11588 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11589 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11595 Rm = inst.operands[2].reg;
11596 reject_bad_reg (Rm);
11598 constraint (inst.operands[2].shifted
11599 && inst.operands[2].immisreg,
11600 _("shift must be constant"));
11601 encode_thumb32_shifted_operand (2);
11608 unsigned Rd, Rn, Rm;
11610 Rd = inst.operands[0].reg;
11611 Rn = inst.operands[1].reg;
11612 Rm = inst.operands[2].reg;
11614 reject_bad_reg (Rd);
11615 reject_bad_reg (Rn);
11616 reject_bad_reg (Rm);
11618 inst.instruction |= Rd << 8;
11619 inst.instruction |= Rn << 16;
11620 inst.instruction |= Rm;
11621 if (inst.operands[3].present)
11623 unsigned int val = inst.reloc.exp.X_add_number;
11624 constraint (inst.reloc.exp.X_op != O_constant,
11625 _("expression too complex"));
11626 inst.instruction |= (val & 0x1c) << 10;
11627 inst.instruction |= (val & 0x03) << 6;
11634 if (!inst.operands[3].present)
11638 inst.instruction &= ~0x00000020;
11640 /* PR 10168. Swap the Rm and Rn registers. */
11641 Rtmp = inst.operands[1].reg;
11642 inst.operands[1].reg = inst.operands[2].reg;
11643 inst.operands[2].reg = Rtmp;
11651 if (inst.operands[0].immisreg)
11652 reject_bad_reg (inst.operands[0].imm);
11654 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11658 do_t_push_pop (void)
11662 constraint (inst.operands[0].writeback,
11663 _("push/pop do not support {reglist}^"));
11664 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11665 _("expression too complex"));
11667 mask = inst.operands[0].imm;
11668 if ((mask & ~0xff) == 0)
11669 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11670 else if ((inst.instruction == T_MNEM_push
11671 && (mask & ~0xff) == 1 << REG_LR)
11672 || (inst.instruction == T_MNEM_pop
11673 && (mask & ~0xff) == 1 << REG_PC))
11675 inst.instruction = THUMB_OP16 (inst.instruction);
11676 inst.instruction |= THUMB_PP_PC_LR;
11677 inst.instruction |= mask & 0xff;
11679 else if (unified_syntax)
11681 inst.instruction = THUMB_OP32 (inst.instruction);
11682 encode_thumb2_ldmstm (13, mask, TRUE);
11686 inst.error = _("invalid register list to push/pop instruction");
11696 Rd = inst.operands[0].reg;
11697 Rm = inst.operands[1].reg;
11699 reject_bad_reg (Rd);
11700 reject_bad_reg (Rm);
11702 inst.instruction |= Rd << 8;
11703 inst.instruction |= Rm << 16;
11704 inst.instruction |= Rm;
11712 Rd = inst.operands[0].reg;
11713 Rm = inst.operands[1].reg;
11715 reject_bad_reg (Rd);
11716 reject_bad_reg (Rm);
11718 if (Rd <= 7 && Rm <= 7
11719 && inst.size_req != 4)
11721 inst.instruction = THUMB_OP16 (inst.instruction);
11722 inst.instruction |= Rd;
11723 inst.instruction |= Rm << 3;
11725 else if (unified_syntax)
11727 inst.instruction = THUMB_OP32 (inst.instruction);
11728 inst.instruction |= Rd << 8;
11729 inst.instruction |= Rm << 16;
11730 inst.instruction |= Rm;
11733 inst.error = BAD_HIREG;
11741 Rd = inst.operands[0].reg;
11742 Rm = inst.operands[1].reg;
11744 reject_bad_reg (Rd);
11745 reject_bad_reg (Rm);
11747 inst.instruction |= Rd << 8;
11748 inst.instruction |= Rm;
11756 Rd = inst.operands[0].reg;
11757 Rs = (inst.operands[1].present
11758 ? inst.operands[1].reg /* Rd, Rs, foo */
11759 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11761 reject_bad_reg (Rd);
11762 reject_bad_reg (Rs);
11763 if (inst.operands[2].isreg)
11764 reject_bad_reg (inst.operands[2].reg);
11766 inst.instruction |= Rd << 8;
11767 inst.instruction |= Rs << 16;
11768 if (!inst.operands[2].isreg)
11770 bfd_boolean narrow;
11772 if ((inst.instruction & 0x00100000) != 0)
11773 narrow = !in_it_block ();
11775 narrow = in_it_block ();
11777 if (Rd > 7 || Rs > 7)
11780 if (inst.size_req == 4 || !unified_syntax)
11783 if (inst.reloc.exp.X_op != O_constant
11784 || inst.reloc.exp.X_add_number != 0)
11787 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11788 relaxation, but it doesn't seem worth the hassle. */
11791 inst.reloc.type = BFD_RELOC_UNUSED;
11792 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11793 inst.instruction |= Rs << 3;
11794 inst.instruction |= Rd;
11798 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11799 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11803 encode_thumb32_shifted_operand (2);
11809 if (warn_on_deprecated
11810 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11811 as_warn (_("setend use is deprecated for ARMv8"));
11813 set_it_insn_type (OUTSIDE_IT_INSN);
11814 if (inst.operands[0].imm)
11815 inst.instruction |= 0x8;
11821 if (!inst.operands[1].present)
11822 inst.operands[1].reg = inst.operands[0].reg;
11824 if (unified_syntax)
11826 bfd_boolean narrow;
11829 switch (inst.instruction)
11832 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11834 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11836 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11838 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11842 if (THUMB_SETS_FLAGS (inst.instruction))
11843 narrow = !in_it_block ();
11845 narrow = in_it_block ();
11846 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11848 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11850 if (inst.operands[2].isreg
11851 && (inst.operands[1].reg != inst.operands[0].reg
11852 || inst.operands[2].reg > 7))
11854 if (inst.size_req == 4)
11857 reject_bad_reg (inst.operands[0].reg);
11858 reject_bad_reg (inst.operands[1].reg);
11862 if (inst.operands[2].isreg)
11864 reject_bad_reg (inst.operands[2].reg);
11865 inst.instruction = THUMB_OP32 (inst.instruction);
11866 inst.instruction |= inst.operands[0].reg << 8;
11867 inst.instruction |= inst.operands[1].reg << 16;
11868 inst.instruction |= inst.operands[2].reg;
11870 /* PR 12854: Error on extraneous shifts. */
11871 constraint (inst.operands[2].shifted,
11872 _("extraneous shift as part of operand to shift insn"));
11876 inst.operands[1].shifted = 1;
11877 inst.operands[1].shift_kind = shift_kind;
11878 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11879 ? T_MNEM_movs : T_MNEM_mov);
11880 inst.instruction |= inst.operands[0].reg << 8;
11881 encode_thumb32_shifted_operand (1);
11882 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11883 inst.reloc.type = BFD_RELOC_UNUSED;
11888 if (inst.operands[2].isreg)
11890 switch (shift_kind)
11892 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11893 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11894 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11895 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11899 inst.instruction |= inst.operands[0].reg;
11900 inst.instruction |= inst.operands[2].reg << 3;
11902 /* PR 12854: Error on extraneous shifts. */
11903 constraint (inst.operands[2].shifted,
11904 _("extraneous shift as part of operand to shift insn"));
11908 switch (shift_kind)
11910 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11911 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11912 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11915 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11916 inst.instruction |= inst.operands[0].reg;
11917 inst.instruction |= inst.operands[1].reg << 3;
11923 constraint (inst.operands[0].reg > 7
11924 || inst.operands[1].reg > 7, BAD_HIREG);
11925 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11927 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11929 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11930 constraint (inst.operands[0].reg != inst.operands[1].reg,
11931 _("source1 and dest must be same register"));
11933 switch (inst.instruction)
11935 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11936 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11937 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11938 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11942 inst.instruction |= inst.operands[0].reg;
11943 inst.instruction |= inst.operands[2].reg << 3;
11945 /* PR 12854: Error on extraneous shifts. */
11946 constraint (inst.operands[2].shifted,
11947 _("extraneous shift as part of operand to shift insn"));
11951 switch (inst.instruction)
11953 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11954 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11955 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11956 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11959 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11960 inst.instruction |= inst.operands[0].reg;
11961 inst.instruction |= inst.operands[1].reg << 3;
11969 unsigned Rd, Rn, Rm;
11971 Rd = inst.operands[0].reg;
11972 Rn = inst.operands[1].reg;
11973 Rm = inst.operands[2].reg;
11975 reject_bad_reg (Rd);
11976 reject_bad_reg (Rn);
11977 reject_bad_reg (Rm);
11979 inst.instruction |= Rd << 8;
11980 inst.instruction |= Rn << 16;
11981 inst.instruction |= Rm;
11987 unsigned Rd, Rn, Rm;
11989 Rd = inst.operands[0].reg;
11990 Rm = inst.operands[1].reg;
11991 Rn = inst.operands[2].reg;
11993 reject_bad_reg (Rd);
11994 reject_bad_reg (Rn);
11995 reject_bad_reg (Rm);
11997 inst.instruction |= Rd << 8;
11998 inst.instruction |= Rn << 16;
11999 inst.instruction |= Rm;
12005 unsigned int value = inst.reloc.exp.X_add_number;
12006 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12007 _("SMC is not permitted on this architecture"));
12008 constraint (inst.reloc.exp.X_op != O_constant,
12009 _("expression too complex"));
12010 inst.reloc.type = BFD_RELOC_UNUSED;
12011 inst.instruction |= (value & 0xf000) >> 12;
12012 inst.instruction |= (value & 0x0ff0);
12013 inst.instruction |= (value & 0x000f) << 16;
12019 unsigned int value = inst.reloc.exp.X_add_number;
12021 inst.reloc.type = BFD_RELOC_UNUSED;
12022 inst.instruction |= (value & 0x0fff);
12023 inst.instruction |= (value & 0xf000) << 4;
12027 do_t_ssat_usat (int bias)
12031 Rd = inst.operands[0].reg;
12032 Rn = inst.operands[2].reg;
12034 reject_bad_reg (Rd);
12035 reject_bad_reg (Rn);
12037 inst.instruction |= Rd << 8;
12038 inst.instruction |= inst.operands[1].imm - bias;
12039 inst.instruction |= Rn << 16;
12041 if (inst.operands[3].present)
12043 offsetT shift_amount = inst.reloc.exp.X_add_number;
12045 inst.reloc.type = BFD_RELOC_UNUSED;
12047 constraint (inst.reloc.exp.X_op != O_constant,
12048 _("expression too complex"));
12050 if (shift_amount != 0)
12052 constraint (shift_amount > 31,
12053 _("shift expression is too large"));
12055 if (inst.operands[3].shift_kind == SHIFT_ASR)
12056 inst.instruction |= 0x00200000; /* sh bit. */
12058 inst.instruction |= (shift_amount & 0x1c) << 10;
12059 inst.instruction |= (shift_amount & 0x03) << 6;
12067 do_t_ssat_usat (1);
12075 Rd = inst.operands[0].reg;
12076 Rn = inst.operands[2].reg;
12078 reject_bad_reg (Rd);
12079 reject_bad_reg (Rn);
12081 inst.instruction |= Rd << 8;
12082 inst.instruction |= inst.operands[1].imm - 1;
12083 inst.instruction |= Rn << 16;
12089 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12090 || inst.operands[2].postind || inst.operands[2].writeback
12091 || inst.operands[2].immisreg || inst.operands[2].shifted
12092 || inst.operands[2].negative,
12095 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12097 inst.instruction |= inst.operands[0].reg << 8;
12098 inst.instruction |= inst.operands[1].reg << 12;
12099 inst.instruction |= inst.operands[2].reg << 16;
12100 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12106 if (!inst.operands[2].present)
12107 inst.operands[2].reg = inst.operands[1].reg + 1;
12109 constraint (inst.operands[0].reg == inst.operands[1].reg
12110 || inst.operands[0].reg == inst.operands[2].reg
12111 || inst.operands[0].reg == inst.operands[3].reg,
12114 inst.instruction |= inst.operands[0].reg;
12115 inst.instruction |= inst.operands[1].reg << 12;
12116 inst.instruction |= inst.operands[2].reg << 8;
12117 inst.instruction |= inst.operands[3].reg << 16;
12123 unsigned Rd, Rn, Rm;
12125 Rd = inst.operands[0].reg;
12126 Rn = inst.operands[1].reg;
12127 Rm = inst.operands[2].reg;
12129 reject_bad_reg (Rd);
12130 reject_bad_reg (Rn);
12131 reject_bad_reg (Rm);
12133 inst.instruction |= Rd << 8;
12134 inst.instruction |= Rn << 16;
12135 inst.instruction |= Rm;
12136 inst.instruction |= inst.operands[3].imm << 4;
12144 Rd = inst.operands[0].reg;
12145 Rm = inst.operands[1].reg;
12147 reject_bad_reg (Rd);
12148 reject_bad_reg (Rm);
12150 if (inst.instruction <= 0xffff
12151 && inst.size_req != 4
12152 && Rd <= 7 && Rm <= 7
12153 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12155 inst.instruction = THUMB_OP16 (inst.instruction);
12156 inst.instruction |= Rd;
12157 inst.instruction |= Rm << 3;
12159 else if (unified_syntax)
12161 if (inst.instruction <= 0xffff)
12162 inst.instruction = THUMB_OP32 (inst.instruction);
12163 inst.instruction |= Rd << 8;
12164 inst.instruction |= Rm;
12165 inst.instruction |= inst.operands[2].imm << 4;
12169 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12170 _("Thumb encoding does not support rotation"));
12171 constraint (1, BAD_HIREG);
12178 /* We have to do the following check manually as ARM_EXT_OS only applies
12180 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12182 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12183 /* This only applies to the v6m howver, not later architectures. */
12184 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12185 as_bad (_("SVC is not permitted on this architecture"));
12186 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12189 inst.reloc.type = BFD_RELOC_ARM_SWI;
12198 half = (inst.instruction & 0x10) != 0;
12199 set_it_insn_type_last ();
12200 constraint (inst.operands[0].immisreg,
12201 _("instruction requires register index"));
12203 Rn = inst.operands[0].reg;
12204 Rm = inst.operands[0].imm;
12206 constraint (Rn == REG_SP, BAD_SP);
12207 reject_bad_reg (Rm);
12209 constraint (!half && inst.operands[0].shifted,
12210 _("instruction does not allow shifted index"));
12211 inst.instruction |= (Rn << 16) | Rm;
12217 do_t_ssat_usat (0);
12225 Rd = inst.operands[0].reg;
12226 Rn = inst.operands[2].reg;
12228 reject_bad_reg (Rd);
12229 reject_bad_reg (Rn);
12231 inst.instruction |= Rd << 8;
12232 inst.instruction |= inst.operands[1].imm;
12233 inst.instruction |= Rn << 16;
12236 /* Neon instruction encoder helpers. */
12238 /* Encodings for the different types for various Neon opcodes. */
12240 /* An "invalid" code for the following tables. */
12243 struct neon_tab_entry
12246 unsigned float_or_poly;
12247 unsigned scalar_or_imm;
12250 /* Map overloaded Neon opcodes to their respective encodings. */
12251 #define NEON_ENC_TAB \
12252 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12253 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12254 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12255 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12256 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12257 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12258 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12259 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12260 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12261 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12262 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12263 /* Register variants of the following two instructions are encoded as
12264 vcge / vcgt with the operands reversed. */ \
12265 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12266 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12267 X(vfma, N_INV, 0x0000c10, N_INV), \
12268 X(vfms, N_INV, 0x0200c10, N_INV), \
12269 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12270 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12271 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12272 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12273 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12274 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12275 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12276 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12277 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12278 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12279 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12280 X(vshl, 0x0000400, N_INV, 0x0800510), \
12281 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12282 X(vand, 0x0000110, N_INV, 0x0800030), \
12283 X(vbic, 0x0100110, N_INV, 0x0800030), \
12284 X(veor, 0x1000110, N_INV, N_INV), \
12285 X(vorn, 0x0300110, N_INV, 0x0800010), \
12286 X(vorr, 0x0200110, N_INV, 0x0800010), \
12287 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12288 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12289 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12290 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12291 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12292 X(vst1, 0x0000000, 0x0800000, N_INV), \
12293 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12294 X(vst2, 0x0000100, 0x0800100, N_INV), \
12295 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12296 X(vst3, 0x0000200, 0x0800200, N_INV), \
12297 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12298 X(vst4, 0x0000300, 0x0800300, N_INV), \
12299 X(vmovn, 0x1b20200, N_INV, N_INV), \
12300 X(vtrn, 0x1b20080, N_INV, N_INV), \
12301 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12302 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12303 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12304 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12305 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12306 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12307 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12308 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12309 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12310 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12311 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12312 X(vseleq, 0xe000a00, N_INV, N_INV), \
12313 X(vselvs, 0xe100a00, N_INV, N_INV), \
12314 X(vselge, 0xe200a00, N_INV, N_INV), \
12315 X(vselgt, 0xe300a00, N_INV, N_INV), \
12316 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12317 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12318 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12319 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12320 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12321 X(aes, 0x3b00300, N_INV, N_INV), \
12322 X(sha3op, 0x2000c00, N_INV, N_INV), \
12323 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12324 X(sha2op, 0x3ba0380, N_INV, N_INV)
12328 #define X(OPC,I,F,S) N_MNEM_##OPC
12333 static const struct neon_tab_entry neon_enc_tab[] =
12335 #define X(OPC,I,F,S) { (I), (F), (S) }
12340 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12341 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12342 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12343 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12344 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12345 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12346 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12347 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12348 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12349 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12350 #define NEON_ENC_SINGLE_(X) \
12351 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12352 #define NEON_ENC_DOUBLE_(X) \
12353 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12354 #define NEON_ENC_FPV8_(X) \
12355 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12357 #define NEON_ENCODE(type, inst) \
12360 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12361 inst.is_neon = 1; \
12365 #define check_neon_suffixes \
12368 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12370 as_bad (_("invalid neon suffix for non neon instruction")); \
12376 /* Define shapes for instruction operands. The following mnemonic characters
12377 are used in this table:
12379 F - VFP S<n> register
12380 D - Neon D<n> register
12381 Q - Neon Q<n> register
12385 L - D<n> register list
12387 This table is used to generate various data:
12388 - enumerations of the form NS_DDR to be used as arguments to
12390 - a table classifying shapes into single, double, quad, mixed.
12391 - a table used to drive neon_select_shape. */
12393 #define NEON_SHAPE_DEF \
12394 X(3, (D, D, D), DOUBLE), \
12395 X(3, (Q, Q, Q), QUAD), \
12396 X(3, (D, D, I), DOUBLE), \
12397 X(3, (Q, Q, I), QUAD), \
12398 X(3, (D, D, S), DOUBLE), \
12399 X(3, (Q, Q, S), QUAD), \
12400 X(2, (D, D), DOUBLE), \
12401 X(2, (Q, Q), QUAD), \
12402 X(2, (D, S), DOUBLE), \
12403 X(2, (Q, S), QUAD), \
12404 X(2, (D, R), DOUBLE), \
12405 X(2, (Q, R), QUAD), \
12406 X(2, (D, I), DOUBLE), \
12407 X(2, (Q, I), QUAD), \
12408 X(3, (D, L, D), DOUBLE), \
12409 X(2, (D, Q), MIXED), \
12410 X(2, (Q, D), MIXED), \
12411 X(3, (D, Q, I), MIXED), \
12412 X(3, (Q, D, I), MIXED), \
12413 X(3, (Q, D, D), MIXED), \
12414 X(3, (D, Q, Q), MIXED), \
12415 X(3, (Q, Q, D), MIXED), \
12416 X(3, (Q, D, S), MIXED), \
12417 X(3, (D, Q, S), MIXED), \
12418 X(4, (D, D, D, I), DOUBLE), \
12419 X(4, (Q, Q, Q, I), QUAD), \
12420 X(2, (F, F), SINGLE), \
12421 X(3, (F, F, F), SINGLE), \
12422 X(2, (F, I), SINGLE), \
12423 X(2, (F, D), MIXED), \
12424 X(2, (D, F), MIXED), \
12425 X(3, (F, F, I), MIXED), \
12426 X(4, (R, R, F, F), SINGLE), \
12427 X(4, (F, F, R, R), SINGLE), \
12428 X(3, (D, R, R), DOUBLE), \
12429 X(3, (R, R, D), DOUBLE), \
12430 X(2, (S, R), SINGLE), \
12431 X(2, (R, S), SINGLE), \
12432 X(2, (F, R), SINGLE), \
12433 X(2, (R, F), SINGLE)
12435 #define S2(A,B) NS_##A##B
12436 #define S3(A,B,C) NS_##A##B##C
12437 #define S4(A,B,C,D) NS_##A##B##C##D
12439 #define X(N, L, C) S##N L
12452 enum neon_shape_class
12460 #define X(N, L, C) SC_##C
12462 static enum neon_shape_class neon_shape_class[] =
12480 /* Register widths of above. */
12481 static unsigned neon_shape_el_size[] =
12492 struct neon_shape_info
12495 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12498 #define S2(A,B) { SE_##A, SE_##B }
12499 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12500 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12502 #define X(N, L, C) { N, S##N L }
12504 static struct neon_shape_info neon_shape_tab[] =
12514 /* Bit masks used in type checking given instructions.
12515 'N_EQK' means the type must be the same as (or based on in some way) the key
12516 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12517 set, various other bits can be set as well in order to modify the meaning of
12518 the type constraint. */
12520 enum neon_type_mask
12544 N_KEY = 0x1000000, /* Key element (main type specifier). */
12545 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12546 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12547 N_UNT = 0x8000000, /* Must be explicitly untyped. */
12548 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12549 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12550 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12551 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12552 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12553 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12554 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12556 N_MAX_NONSPECIAL = N_P64
12559 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12561 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12562 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12563 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12564 #define N_SUF_32 (N_SU_32 | N_F32)
12565 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12566 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12568 /* Pass this as the first type argument to neon_check_type to ignore types
12570 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12572 /* Select a "shape" for the current instruction (describing register types or
12573 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12574 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12575 function of operand parsing, so this function doesn't need to be called.
12576 Shapes should be listed in order of decreasing length. */
12578 static enum neon_shape
12579 neon_select_shape (enum neon_shape shape, ...)
12582 enum neon_shape first_shape = shape;
12584 /* Fix missing optional operands. FIXME: we don't know at this point how
12585 many arguments we should have, so this makes the assumption that we have
12586 > 1. This is true of all current Neon opcodes, I think, but may not be
12587 true in the future. */
12588 if (!inst.operands[1].present)
12589 inst.operands[1] = inst.operands[0];
12591 va_start (ap, shape);
12593 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12598 for (j = 0; j < neon_shape_tab[shape].els; j++)
12600 if (!inst.operands[j].present)
12606 switch (neon_shape_tab[shape].el[j])
12609 if (!(inst.operands[j].isreg
12610 && inst.operands[j].isvec
12611 && inst.operands[j].issingle
12612 && !inst.operands[j].isquad))
12617 if (!(inst.operands[j].isreg
12618 && inst.operands[j].isvec
12619 && !inst.operands[j].isquad
12620 && !inst.operands[j].issingle))
12625 if (!(inst.operands[j].isreg
12626 && !inst.operands[j].isvec))
12631 if (!(inst.operands[j].isreg
12632 && inst.operands[j].isvec
12633 && inst.operands[j].isquad
12634 && !inst.operands[j].issingle))
12639 if (!(!inst.operands[j].isreg
12640 && !inst.operands[j].isscalar))
12645 if (!(!inst.operands[j].isreg
12646 && inst.operands[j].isscalar))
12656 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12657 /* We've matched all the entries in the shape table, and we don't
12658 have any left over operands which have not been matched. */
12664 if (shape == NS_NULL && first_shape != NS_NULL)
12665 first_error (_("invalid instruction shape"));
12670 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12671 means the Q bit should be set). */
12674 neon_quad (enum neon_shape shape)
12676 return neon_shape_class[shape] == SC_QUAD;
12680 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12683 /* Allow modification to be made to types which are constrained to be
12684 based on the key element, based on bits set alongside N_EQK. */
12685 if ((typebits & N_EQK) != 0)
12687 if ((typebits & N_HLF) != 0)
12689 else if ((typebits & N_DBL) != 0)
12691 if ((typebits & N_SGN) != 0)
12692 *g_type = NT_signed;
12693 else if ((typebits & N_UNS) != 0)
12694 *g_type = NT_unsigned;
12695 else if ((typebits & N_INT) != 0)
12696 *g_type = NT_integer;
12697 else if ((typebits & N_FLT) != 0)
12698 *g_type = NT_float;
12699 else if ((typebits & N_SIZ) != 0)
12700 *g_type = NT_untyped;
12704 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12705 operand type, i.e. the single type specified in a Neon instruction when it
12706 is the only one given. */
12708 static struct neon_type_el
12709 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12711 struct neon_type_el dest = *key;
12713 gas_assert ((thisarg & N_EQK) != 0);
12715 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12720 /* Convert Neon type and size into compact bitmask representation. */
12722 static enum neon_type_mask
12723 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12730 case 8: return N_8;
12731 case 16: return N_16;
12732 case 32: return N_32;
12733 case 64: return N_64;
12741 case 8: return N_I8;
12742 case 16: return N_I16;
12743 case 32: return N_I32;
12744 case 64: return N_I64;
12752 case 16: return N_F16;
12753 case 32: return N_F32;
12754 case 64: return N_F64;
12762 case 8: return N_P8;
12763 case 16: return N_P16;
12764 case 64: return N_P64;
12772 case 8: return N_S8;
12773 case 16: return N_S16;
12774 case 32: return N_S32;
12775 case 64: return N_S64;
12783 case 8: return N_U8;
12784 case 16: return N_U16;
12785 case 32: return N_U32;
12786 case 64: return N_U64;
12797 /* Convert compact Neon bitmask type representation to a type and size. Only
12798 handles the case where a single bit is set in the mask. */
12801 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12802 enum neon_type_mask mask)
12804 if ((mask & N_EQK) != 0)
12807 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12809 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
12811 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12813 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
12818 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12820 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12821 *type = NT_unsigned;
12822 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12823 *type = NT_integer;
12824 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12825 *type = NT_untyped;
12826 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
12828 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
12836 /* Modify a bitmask of allowed types. This is only needed for type
12840 modify_types_allowed (unsigned allowed, unsigned mods)
12843 enum neon_el_type type;
12849 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12851 if (el_type_of_type_chk (&type, &size,
12852 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12854 neon_modify_type_size (mods, &type, &size);
12855 destmask |= type_chk_of_el_type (type, size);
12862 /* Check type and return type classification.
12863 The manual states (paraphrase): If one datatype is given, it indicates the
12865 - the second operand, if there is one
12866 - the operand, if there is no second operand
12867 - the result, if there are no operands.
12868 This isn't quite good enough though, so we use a concept of a "key" datatype
12869 which is set on a per-instruction basis, which is the one which matters when
12870 only one data type is written.
12871 Note: this function has side-effects (e.g. filling in missing operands). All
12872 Neon instructions should call it before performing bit encoding. */
12874 static struct neon_type_el
12875 neon_check_type (unsigned els, enum neon_shape ns, ...)
12878 unsigned i, pass, key_el = 0;
12879 unsigned types[NEON_MAX_TYPE_ELS];
12880 enum neon_el_type k_type = NT_invtype;
12881 unsigned k_size = -1u;
12882 struct neon_type_el badtype = {NT_invtype, -1};
12883 unsigned key_allowed = 0;
12885 /* Optional registers in Neon instructions are always (not) in operand 1.
12886 Fill in the missing operand here, if it was omitted. */
12887 if (els > 1 && !inst.operands[1].present)
12888 inst.operands[1] = inst.operands[0];
12890 /* Suck up all the varargs. */
12892 for (i = 0; i < els; i++)
12894 unsigned thisarg = va_arg (ap, unsigned);
12895 if (thisarg == N_IGNORE_TYPE)
12900 types[i] = thisarg;
12901 if ((thisarg & N_KEY) != 0)
12906 if (inst.vectype.elems > 0)
12907 for (i = 0; i < els; i++)
12908 if (inst.operands[i].vectype.type != NT_invtype)
12910 first_error (_("types specified in both the mnemonic and operands"));
12914 /* Duplicate inst.vectype elements here as necessary.
12915 FIXME: No idea if this is exactly the same as the ARM assembler,
12916 particularly when an insn takes one register and one non-register
12918 if (inst.vectype.elems == 1 && els > 1)
12921 inst.vectype.elems = els;
12922 inst.vectype.el[key_el] = inst.vectype.el[0];
12923 for (j = 0; j < els; j++)
12925 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12928 else if (inst.vectype.elems == 0 && els > 0)
12931 /* No types were given after the mnemonic, so look for types specified
12932 after each operand. We allow some flexibility here; as long as the
12933 "key" operand has a type, we can infer the others. */
12934 for (j = 0; j < els; j++)
12935 if (inst.operands[j].vectype.type != NT_invtype)
12936 inst.vectype.el[j] = inst.operands[j].vectype;
12938 if (inst.operands[key_el].vectype.type != NT_invtype)
12940 for (j = 0; j < els; j++)
12941 if (inst.operands[j].vectype.type == NT_invtype)
12942 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12947 first_error (_("operand types can't be inferred"));
12951 else if (inst.vectype.elems != els)
12953 first_error (_("type specifier has the wrong number of parts"));
12957 for (pass = 0; pass < 2; pass++)
12959 for (i = 0; i < els; i++)
12961 unsigned thisarg = types[i];
12962 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12963 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12964 enum neon_el_type g_type = inst.vectype.el[i].type;
12965 unsigned g_size = inst.vectype.el[i].size;
12967 /* Decay more-specific signed & unsigned types to sign-insensitive
12968 integer types if sign-specific variants are unavailable. */
12969 if ((g_type == NT_signed || g_type == NT_unsigned)
12970 && (types_allowed & N_SU_ALL) == 0)
12971 g_type = NT_integer;
12973 /* If only untyped args are allowed, decay any more specific types to
12974 them. Some instructions only care about signs for some element
12975 sizes, so handle that properly. */
12976 if (((types_allowed & N_UNT) == 0)
12977 && ((g_size == 8 && (types_allowed & N_8) != 0)
12978 || (g_size == 16 && (types_allowed & N_16) != 0)
12979 || (g_size == 32 && (types_allowed & N_32) != 0)
12980 || (g_size == 64 && (types_allowed & N_64) != 0)))
12981 g_type = NT_untyped;
12985 if ((thisarg & N_KEY) != 0)
12989 key_allowed = thisarg & ~N_KEY;
12994 if ((thisarg & N_VFP) != 0)
12996 enum neon_shape_el regshape;
12997 unsigned regwidth, match;
12999 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13002 first_error (_("invalid instruction shape"));
13005 regshape = neon_shape_tab[ns].el[i];
13006 regwidth = neon_shape_el_size[regshape];
13008 /* In VFP mode, operands must match register widths. If we
13009 have a key operand, use its width, else use the width of
13010 the current operand. */
13016 if (regwidth != match)
13018 first_error (_("operand size must match register width"));
13023 if ((thisarg & N_EQK) == 0)
13025 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13027 if ((given_type & types_allowed) == 0)
13029 first_error (_("bad type in Neon instruction"));
13035 enum neon_el_type mod_k_type = k_type;
13036 unsigned mod_k_size = k_size;
13037 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13038 if (g_type != mod_k_type || g_size != mod_k_size)
13040 first_error (_("inconsistent types in Neon instruction"));
13048 return inst.vectype.el[key_el];
13051 /* Neon-style VFP instruction forwarding. */
13053 /* Thumb VFP instructions have 0xE in the condition field. */
13056 do_vfp_cond_or_thumb (void)
13061 inst.instruction |= 0xe0000000;
13063 inst.instruction |= inst.cond << 28;
13066 /* Look up and encode a simple mnemonic, for use as a helper function for the
13067 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13068 etc. It is assumed that operand parsing has already been done, and that the
13069 operands are in the form expected by the given opcode (this isn't necessarily
13070 the same as the form in which they were parsed, hence some massaging must
13071 take place before this function is called).
13072 Checks current arch version against that in the looked-up opcode. */
13075 do_vfp_nsyn_opcode (const char *opname)
13077 const struct asm_opcode *opcode;
13079 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13084 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13085 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13092 inst.instruction = opcode->tvalue;
13093 opcode->tencode ();
13097 inst.instruction = (inst.cond << 28) | opcode->avalue;
13098 opcode->aencode ();
13103 do_vfp_nsyn_add_sub (enum neon_shape rs)
13105 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13110 do_vfp_nsyn_opcode ("fadds");
13112 do_vfp_nsyn_opcode ("fsubs");
13117 do_vfp_nsyn_opcode ("faddd");
13119 do_vfp_nsyn_opcode ("fsubd");
13123 /* Check operand types to see if this is a VFP instruction, and if so call
13127 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13129 enum neon_shape rs;
13130 struct neon_type_el et;
13135 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13136 et = neon_check_type (2, rs,
13137 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13141 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13142 et = neon_check_type (3, rs,
13143 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13150 if (et.type != NT_invtype)
13161 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13163 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13168 do_vfp_nsyn_opcode ("fmacs");
13170 do_vfp_nsyn_opcode ("fnmacs");
13175 do_vfp_nsyn_opcode ("fmacd");
13177 do_vfp_nsyn_opcode ("fnmacd");
13182 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13184 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13189 do_vfp_nsyn_opcode ("ffmas");
13191 do_vfp_nsyn_opcode ("ffnmas");
13196 do_vfp_nsyn_opcode ("ffmad");
13198 do_vfp_nsyn_opcode ("ffnmad");
13203 do_vfp_nsyn_mul (enum neon_shape rs)
13206 do_vfp_nsyn_opcode ("fmuls");
13208 do_vfp_nsyn_opcode ("fmuld");
13212 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13214 int is_neg = (inst.instruction & 0x80) != 0;
13215 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13220 do_vfp_nsyn_opcode ("fnegs");
13222 do_vfp_nsyn_opcode ("fabss");
13227 do_vfp_nsyn_opcode ("fnegd");
13229 do_vfp_nsyn_opcode ("fabsd");
13233 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13234 insns belong to Neon, and are handled elsewhere. */
13237 do_vfp_nsyn_ldm_stm (int is_dbmode)
13239 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13243 do_vfp_nsyn_opcode ("fldmdbs");
13245 do_vfp_nsyn_opcode ("fldmias");
13250 do_vfp_nsyn_opcode ("fstmdbs");
13252 do_vfp_nsyn_opcode ("fstmias");
13257 do_vfp_nsyn_sqrt (void)
13259 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13260 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13263 do_vfp_nsyn_opcode ("fsqrts");
13265 do_vfp_nsyn_opcode ("fsqrtd");
13269 do_vfp_nsyn_div (void)
13271 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13272 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13273 N_F32 | N_F64 | N_KEY | N_VFP);
13276 do_vfp_nsyn_opcode ("fdivs");
13278 do_vfp_nsyn_opcode ("fdivd");
13282 do_vfp_nsyn_nmul (void)
13284 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13285 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13286 N_F32 | N_F64 | N_KEY | N_VFP);
13290 NEON_ENCODE (SINGLE, inst);
13291 do_vfp_sp_dyadic ();
13295 NEON_ENCODE (DOUBLE, inst);
13296 do_vfp_dp_rd_rn_rm ();
13298 do_vfp_cond_or_thumb ();
13302 do_vfp_nsyn_cmp (void)
13304 if (inst.operands[1].isreg)
13306 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13307 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13311 NEON_ENCODE (SINGLE, inst);
13312 do_vfp_sp_monadic ();
13316 NEON_ENCODE (DOUBLE, inst);
13317 do_vfp_dp_rd_rm ();
13322 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13323 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13325 switch (inst.instruction & 0x0fffffff)
13328 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13331 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13339 NEON_ENCODE (SINGLE, inst);
13340 do_vfp_sp_compare_z ();
13344 NEON_ENCODE (DOUBLE, inst);
13348 do_vfp_cond_or_thumb ();
13352 nsyn_insert_sp (void)
13354 inst.operands[1] = inst.operands[0];
13355 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13356 inst.operands[0].reg = REG_SP;
13357 inst.operands[0].isreg = 1;
13358 inst.operands[0].writeback = 1;
13359 inst.operands[0].present = 1;
13363 do_vfp_nsyn_push (void)
13366 if (inst.operands[1].issingle)
13367 do_vfp_nsyn_opcode ("fstmdbs");
13369 do_vfp_nsyn_opcode ("fstmdbd");
13373 do_vfp_nsyn_pop (void)
13376 if (inst.operands[1].issingle)
13377 do_vfp_nsyn_opcode ("fldmias");
13379 do_vfp_nsyn_opcode ("fldmiad");
13382 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13383 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13386 neon_dp_fixup (struct arm_it* insn)
13388 unsigned int i = insn->instruction;
13393 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13404 insn->instruction = i;
13407 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13411 neon_logbits (unsigned x)
13413 return ffs (x) - 4;
13416 #define LOW4(R) ((R) & 0xf)
13417 #define HI1(R) (((R) >> 4) & 1)
13419 /* Encode insns with bit pattern:
13421 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13422 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13424 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13425 different meaning for some instruction. */
13428 neon_three_same (int isquad, int ubit, int size)
13430 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13431 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13432 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13433 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13434 inst.instruction |= LOW4 (inst.operands[2].reg);
13435 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13436 inst.instruction |= (isquad != 0) << 6;
13437 inst.instruction |= (ubit != 0) << 24;
13439 inst.instruction |= neon_logbits (size) << 20;
13441 neon_dp_fixup (&inst);
13444 /* Encode instructions of the form:
13446 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13447 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13449 Don't write size if SIZE == -1. */
13452 neon_two_same (int qbit, int ubit, int size)
13454 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13455 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13456 inst.instruction |= LOW4 (inst.operands[1].reg);
13457 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13458 inst.instruction |= (qbit != 0) << 6;
13459 inst.instruction |= (ubit != 0) << 24;
13462 inst.instruction |= neon_logbits (size) << 18;
13464 neon_dp_fixup (&inst);
13467 /* Neon instruction encoders, in approximate order of appearance. */
13470 do_neon_dyadic_i_su (void)
13472 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13473 struct neon_type_el et = neon_check_type (3, rs,
13474 N_EQK, N_EQK, N_SU_32 | N_KEY);
13475 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13479 do_neon_dyadic_i64_su (void)
13481 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13482 struct neon_type_el et = neon_check_type (3, rs,
13483 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13484 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13488 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13491 unsigned size = et.size >> 3;
13492 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13493 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13494 inst.instruction |= LOW4 (inst.operands[1].reg);
13495 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13496 inst.instruction |= (isquad != 0) << 6;
13497 inst.instruction |= immbits << 16;
13498 inst.instruction |= (size >> 3) << 7;
13499 inst.instruction |= (size & 0x7) << 19;
13501 inst.instruction |= (uval != 0) << 24;
13503 neon_dp_fixup (&inst);
13507 do_neon_shl_imm (void)
13509 if (!inst.operands[2].isreg)
13511 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13512 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13513 NEON_ENCODE (IMMED, inst);
13514 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13518 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13519 struct neon_type_el et = neon_check_type (3, rs,
13520 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13523 /* VSHL/VQSHL 3-register variants have syntax such as:
13525 whereas other 3-register operations encoded by neon_three_same have
13528 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13530 tmp = inst.operands[2].reg;
13531 inst.operands[2].reg = inst.operands[1].reg;
13532 inst.operands[1].reg = tmp;
13533 NEON_ENCODE (INTEGER, inst);
13534 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13539 do_neon_qshl_imm (void)
13541 if (!inst.operands[2].isreg)
13543 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13544 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13546 NEON_ENCODE (IMMED, inst);
13547 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13548 inst.operands[2].imm);
13552 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13553 struct neon_type_el et = neon_check_type (3, rs,
13554 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13557 /* See note in do_neon_shl_imm. */
13558 tmp = inst.operands[2].reg;
13559 inst.operands[2].reg = inst.operands[1].reg;
13560 inst.operands[1].reg = tmp;
13561 NEON_ENCODE (INTEGER, inst);
13562 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13567 do_neon_rshl (void)
13569 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13570 struct neon_type_el et = neon_check_type (3, rs,
13571 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13574 tmp = inst.operands[2].reg;
13575 inst.operands[2].reg = inst.operands[1].reg;
13576 inst.operands[1].reg = tmp;
13577 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13581 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13583 /* Handle .I8 pseudo-instructions. */
13586 /* Unfortunately, this will make everything apart from zero out-of-range.
13587 FIXME is this the intended semantics? There doesn't seem much point in
13588 accepting .I8 if so. */
13589 immediate |= immediate << 8;
13595 if (immediate == (immediate & 0x000000ff))
13597 *immbits = immediate;
13600 else if (immediate == (immediate & 0x0000ff00))
13602 *immbits = immediate >> 8;
13605 else if (immediate == (immediate & 0x00ff0000))
13607 *immbits = immediate >> 16;
13610 else if (immediate == (immediate & 0xff000000))
13612 *immbits = immediate >> 24;
13615 if ((immediate & 0xffff) != (immediate >> 16))
13616 goto bad_immediate;
13617 immediate &= 0xffff;
13620 if (immediate == (immediate & 0x000000ff))
13622 *immbits = immediate;
13625 else if (immediate == (immediate & 0x0000ff00))
13627 *immbits = immediate >> 8;
13632 first_error (_("immediate value out of range"));
13636 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13640 neon_bits_same_in_bytes (unsigned imm)
13642 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13643 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13644 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13645 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13648 /* For immediate of above form, return 0bABCD. */
13651 neon_squash_bits (unsigned imm)
13653 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13654 | ((imm & 0x01000000) >> 21);
13657 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13660 neon_qfloat_bits (unsigned imm)
13662 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13665 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13666 the instruction. *OP is passed as the initial value of the op field, and
13667 may be set to a different value depending on the constant (i.e.
13668 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13669 MVN). If the immediate looks like a repeated pattern then also
13670 try smaller element sizes. */
13673 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13674 unsigned *immbits, int *op, int size,
13675 enum neon_el_type type)
13677 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13679 if (type == NT_float && !float_p)
13682 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13684 if (size != 32 || *op == 1)
13686 *immbits = neon_qfloat_bits (immlo);
13692 if (neon_bits_same_in_bytes (immhi)
13693 && neon_bits_same_in_bytes (immlo))
13697 *immbits = (neon_squash_bits (immhi) << 4)
13698 | neon_squash_bits (immlo);
13703 if (immhi != immlo)
13709 if (immlo == (immlo & 0x000000ff))
13714 else if (immlo == (immlo & 0x0000ff00))
13716 *immbits = immlo >> 8;
13719 else if (immlo == (immlo & 0x00ff0000))
13721 *immbits = immlo >> 16;
13724 else if (immlo == (immlo & 0xff000000))
13726 *immbits = immlo >> 24;
13729 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13731 *immbits = (immlo >> 8) & 0xff;
13734 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13736 *immbits = (immlo >> 16) & 0xff;
13740 if ((immlo & 0xffff) != (immlo >> 16))
13747 if (immlo == (immlo & 0x000000ff))
13752 else if (immlo == (immlo & 0x0000ff00))
13754 *immbits = immlo >> 8;
13758 if ((immlo & 0xff) != (immlo >> 8))
13763 if (immlo == (immlo & 0x000000ff))
13765 /* Don't allow MVN with 8-bit immediate. */
13775 /* Write immediate bits [7:0] to the following locations:
13777 |28/24|23 19|18 16|15 4|3 0|
13778 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13780 This function is used by VMOV/VMVN/VORR/VBIC. */
13783 neon_write_immbits (unsigned immbits)
13785 inst.instruction |= immbits & 0xf;
13786 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13787 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13790 /* Invert low-order SIZE bits of XHI:XLO. */
13793 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13795 unsigned immlo = xlo ? *xlo : 0;
13796 unsigned immhi = xhi ? *xhi : 0;
13801 immlo = (~immlo) & 0xff;
13805 immlo = (~immlo) & 0xffff;
13809 immhi = (~immhi) & 0xffffffff;
13810 /* fall through. */
13813 immlo = (~immlo) & 0xffffffff;
13828 do_neon_logic (void)
13830 if (inst.operands[2].present && inst.operands[2].isreg)
13832 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13833 neon_check_type (3, rs, N_IGNORE_TYPE);
13834 /* U bit and size field were set as part of the bitmask. */
13835 NEON_ENCODE (INTEGER, inst);
13836 neon_three_same (neon_quad (rs), 0, -1);
13840 const int three_ops_form = (inst.operands[2].present
13841 && !inst.operands[2].isreg);
13842 const int immoperand = (three_ops_form ? 2 : 1);
13843 enum neon_shape rs = (three_ops_form
13844 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13845 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13846 struct neon_type_el et = neon_check_type (2, rs,
13847 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13848 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13852 if (et.type == NT_invtype)
13855 if (three_ops_form)
13856 constraint (inst.operands[0].reg != inst.operands[1].reg,
13857 _("first and second operands shall be the same register"));
13859 NEON_ENCODE (IMMED, inst);
13861 immbits = inst.operands[immoperand].imm;
13864 /* .i64 is a pseudo-op, so the immediate must be a repeating
13866 if (immbits != (inst.operands[immoperand].regisimm ?
13867 inst.operands[immoperand].reg : 0))
13869 /* Set immbits to an invalid constant. */
13870 immbits = 0xdeadbeef;
13877 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13881 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13885 /* Pseudo-instruction for VBIC. */
13886 neon_invert_size (&immbits, 0, et.size);
13887 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13891 /* Pseudo-instruction for VORR. */
13892 neon_invert_size (&immbits, 0, et.size);
13893 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13903 inst.instruction |= neon_quad (rs) << 6;
13904 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13905 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13906 inst.instruction |= cmode << 8;
13907 neon_write_immbits (immbits);
13909 neon_dp_fixup (&inst);
13914 do_neon_bitfield (void)
13916 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13917 neon_check_type (3, rs, N_IGNORE_TYPE);
13918 neon_three_same (neon_quad (rs), 0, -1);
13922 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13925 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13926 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13928 if (et.type == NT_float)
13930 NEON_ENCODE (FLOAT, inst);
13931 neon_three_same (neon_quad (rs), 0, -1);
13935 NEON_ENCODE (INTEGER, inst);
13936 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13941 do_neon_dyadic_if_su (void)
13943 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13947 do_neon_dyadic_if_su_d (void)
13949 /* This version only allow D registers, but that constraint is enforced during
13950 operand parsing so we don't need to do anything extra here. */
13951 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13955 do_neon_dyadic_if_i_d (void)
13957 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13958 affected if we specify unsigned args. */
13959 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13962 enum vfp_or_neon_is_neon_bits
13965 NEON_CHECK_ARCH = 2,
13966 NEON_CHECK_ARCH8 = 4
13969 /* Call this function if an instruction which may have belonged to the VFP or
13970 Neon instruction sets, but turned out to be a Neon instruction (due to the
13971 operand types involved, etc.). We have to check and/or fix-up a couple of
13974 - Make sure the user hasn't attempted to make a Neon instruction
13976 - Alter the value in the condition code field if necessary.
13977 - Make sure that the arch supports Neon instructions.
13979 Which of these operations take place depends on bits from enum
13980 vfp_or_neon_is_neon_bits.
13982 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13983 current instruction's condition is COND_ALWAYS, the condition field is
13984 changed to inst.uncond_value. This is necessary because instructions shared
13985 between VFP and Neon may be conditional for the VFP variants only, and the
13986 unconditional Neon version must have, e.g., 0xF in the condition field. */
13989 vfp_or_neon_is_neon (unsigned check)
13991 /* Conditions are always legal in Thumb mode (IT blocks). */
13992 if (!thumb_mode && (check & NEON_CHECK_CC))
13994 if (inst.cond != COND_ALWAYS)
13996 first_error (_(BAD_COND));
13999 if (inst.uncond_value != -1)
14000 inst.instruction |= inst.uncond_value << 28;
14003 if ((check & NEON_CHECK_ARCH)
14004 && !mark_feature_used (&fpu_neon_ext_v1))
14006 first_error (_(BAD_FPU));
14010 if ((check & NEON_CHECK_ARCH8)
14011 && !mark_feature_used (&fpu_neon_ext_armv8))
14013 first_error (_(BAD_FPU));
14021 do_neon_addsub_if_i (void)
14023 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14026 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14029 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14030 affected if we specify unsigned args. */
14031 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14034 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14036 V<op> A,B (A is operand 0, B is operand 2)
14041 so handle that case specially. */
14044 neon_exchange_operands (void)
14046 void *scratch = alloca (sizeof (inst.operands[0]));
14047 if (inst.operands[1].present)
14049 /* Swap operands[1] and operands[2]. */
14050 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14051 inst.operands[1] = inst.operands[2];
14052 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14056 inst.operands[1] = inst.operands[2];
14057 inst.operands[2] = inst.operands[0];
14062 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14064 if (inst.operands[2].isreg)
14067 neon_exchange_operands ();
14068 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14072 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14073 struct neon_type_el et = neon_check_type (2, rs,
14074 N_EQK | N_SIZ, immtypes | N_KEY);
14076 NEON_ENCODE (IMMED, inst);
14077 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14078 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14079 inst.instruction |= LOW4 (inst.operands[1].reg);
14080 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14081 inst.instruction |= neon_quad (rs) << 6;
14082 inst.instruction |= (et.type == NT_float) << 10;
14083 inst.instruction |= neon_logbits (et.size) << 18;
14085 neon_dp_fixup (&inst);
14092 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14096 do_neon_cmp_inv (void)
14098 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14104 neon_compare (N_IF_32, N_IF_32, FALSE);
14107 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14108 scalars, which are encoded in 5 bits, M : Rm.
14109 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14110 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14114 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14116 unsigned regno = NEON_SCALAR_REG (scalar);
14117 unsigned elno = NEON_SCALAR_INDEX (scalar);
14122 if (regno > 7 || elno > 3)
14124 return regno | (elno << 3);
14127 if (regno > 15 || elno > 1)
14129 return regno | (elno << 4);
14133 first_error (_("scalar out of range for multiply instruction"));
14139 /* Encode multiply / multiply-accumulate scalar instructions. */
14142 neon_mul_mac (struct neon_type_el et, int ubit)
14146 /* Give a more helpful error message if we have an invalid type. */
14147 if (et.type == NT_invtype)
14150 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14151 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14152 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14153 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14154 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14155 inst.instruction |= LOW4 (scalar);
14156 inst.instruction |= HI1 (scalar) << 5;
14157 inst.instruction |= (et.type == NT_float) << 8;
14158 inst.instruction |= neon_logbits (et.size) << 20;
14159 inst.instruction |= (ubit != 0) << 24;
14161 neon_dp_fixup (&inst);
14165 do_neon_mac_maybe_scalar (void)
14167 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14170 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14173 if (inst.operands[2].isscalar)
14175 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14176 struct neon_type_el et = neon_check_type (3, rs,
14177 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14178 NEON_ENCODE (SCALAR, inst);
14179 neon_mul_mac (et, neon_quad (rs));
14183 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14184 affected if we specify unsigned args. */
14185 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14190 do_neon_fmac (void)
14192 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14195 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14198 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14204 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14205 struct neon_type_el et = neon_check_type (3, rs,
14206 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14207 neon_three_same (neon_quad (rs), 0, et.size);
14210 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14211 same types as the MAC equivalents. The polynomial type for this instruction
14212 is encoded the same as the integer type. */
14217 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14220 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14223 if (inst.operands[2].isscalar)
14224 do_neon_mac_maybe_scalar ();
14226 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14230 do_neon_qdmulh (void)
14232 if (inst.operands[2].isscalar)
14234 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14235 struct neon_type_el et = neon_check_type (3, rs,
14236 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14237 NEON_ENCODE (SCALAR, inst);
14238 neon_mul_mac (et, neon_quad (rs));
14242 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14243 struct neon_type_el et = neon_check_type (3, rs,
14244 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14245 NEON_ENCODE (INTEGER, inst);
14246 /* The U bit (rounding) comes from bit mask. */
14247 neon_three_same (neon_quad (rs), 0, et.size);
14252 do_neon_fcmp_absolute (void)
14254 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14255 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14256 /* Size field comes from bit mask. */
14257 neon_three_same (neon_quad (rs), 1, -1);
14261 do_neon_fcmp_absolute_inv (void)
14263 neon_exchange_operands ();
14264 do_neon_fcmp_absolute ();
14268 do_neon_step (void)
14270 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14271 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14272 neon_three_same (neon_quad (rs), 0, -1);
14276 do_neon_abs_neg (void)
14278 enum neon_shape rs;
14279 struct neon_type_el et;
14281 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14284 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14287 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14288 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14290 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14291 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14292 inst.instruction |= LOW4 (inst.operands[1].reg);
14293 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14294 inst.instruction |= neon_quad (rs) << 6;
14295 inst.instruction |= (et.type == NT_float) << 10;
14296 inst.instruction |= neon_logbits (et.size) << 18;
14298 neon_dp_fixup (&inst);
14304 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14305 struct neon_type_el et = neon_check_type (2, rs,
14306 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14307 int imm = inst.operands[2].imm;
14308 constraint (imm < 0 || (unsigned)imm >= et.size,
14309 _("immediate out of range for insert"));
14310 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14316 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14317 struct neon_type_el et = neon_check_type (2, rs,
14318 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14319 int imm = inst.operands[2].imm;
14320 constraint (imm < 1 || (unsigned)imm > et.size,
14321 _("immediate out of range for insert"));
14322 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14326 do_neon_qshlu_imm (void)
14328 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14329 struct neon_type_el et = neon_check_type (2, rs,
14330 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14331 int imm = inst.operands[2].imm;
14332 constraint (imm < 0 || (unsigned)imm >= et.size,
14333 _("immediate out of range for shift"));
14334 /* Only encodes the 'U present' variant of the instruction.
14335 In this case, signed types have OP (bit 8) set to 0.
14336 Unsigned types have OP set to 1. */
14337 inst.instruction |= (et.type == NT_unsigned) << 8;
14338 /* The rest of the bits are the same as other immediate shifts. */
14339 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14343 do_neon_qmovn (void)
14345 struct neon_type_el et = neon_check_type (2, NS_DQ,
14346 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14347 /* Saturating move where operands can be signed or unsigned, and the
14348 destination has the same signedness. */
14349 NEON_ENCODE (INTEGER, inst);
14350 if (et.type == NT_unsigned)
14351 inst.instruction |= 0xc0;
14353 inst.instruction |= 0x80;
14354 neon_two_same (0, 1, et.size / 2);
14358 do_neon_qmovun (void)
14360 struct neon_type_el et = neon_check_type (2, NS_DQ,
14361 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14362 /* Saturating move with unsigned results. Operands must be signed. */
14363 NEON_ENCODE (INTEGER, inst);
14364 neon_two_same (0, 1, et.size / 2);
14368 do_neon_rshift_sat_narrow (void)
14370 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14371 or unsigned. If operands are unsigned, results must also be unsigned. */
14372 struct neon_type_el et = neon_check_type (2, NS_DQI,
14373 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14374 int imm = inst.operands[2].imm;
14375 /* This gets the bounds check, size encoding and immediate bits calculation
14379 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14380 VQMOVN.I<size> <Dd>, <Qm>. */
14383 inst.operands[2].present = 0;
14384 inst.instruction = N_MNEM_vqmovn;
14389 constraint (imm < 1 || (unsigned)imm > et.size,
14390 _("immediate out of range"));
14391 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14395 do_neon_rshift_sat_narrow_u (void)
14397 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14398 or unsigned. If operands are unsigned, results must also be unsigned. */
14399 struct neon_type_el et = neon_check_type (2, NS_DQI,
14400 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14401 int imm = inst.operands[2].imm;
14402 /* This gets the bounds check, size encoding and immediate bits calculation
14406 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14407 VQMOVUN.I<size> <Dd>, <Qm>. */
14410 inst.operands[2].present = 0;
14411 inst.instruction = N_MNEM_vqmovun;
14416 constraint (imm < 1 || (unsigned)imm > et.size,
14417 _("immediate out of range"));
14418 /* FIXME: The manual is kind of unclear about what value U should have in
14419 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14421 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14425 do_neon_movn (void)
14427 struct neon_type_el et = neon_check_type (2, NS_DQ,
14428 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14429 NEON_ENCODE (INTEGER, inst);
14430 neon_two_same (0, 1, et.size / 2);
14434 do_neon_rshift_narrow (void)
14436 struct neon_type_el et = neon_check_type (2, NS_DQI,
14437 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14438 int imm = inst.operands[2].imm;
14439 /* This gets the bounds check, size encoding and immediate bits calculation
14443 /* If immediate is zero then we are a pseudo-instruction for
14444 VMOVN.I<size> <Dd>, <Qm> */
14447 inst.operands[2].present = 0;
14448 inst.instruction = N_MNEM_vmovn;
14453 constraint (imm < 1 || (unsigned)imm > et.size,
14454 _("immediate out of range for narrowing operation"));
14455 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14459 do_neon_shll (void)
14461 /* FIXME: Type checking when lengthening. */
14462 struct neon_type_el et = neon_check_type (2, NS_QDI,
14463 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14464 unsigned imm = inst.operands[2].imm;
14466 if (imm == et.size)
14468 /* Maximum shift variant. */
14469 NEON_ENCODE (INTEGER, inst);
14470 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14471 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14472 inst.instruction |= LOW4 (inst.operands[1].reg);
14473 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14474 inst.instruction |= neon_logbits (et.size) << 18;
14476 neon_dp_fixup (&inst);
14480 /* A more-specific type check for non-max versions. */
14481 et = neon_check_type (2, NS_QDI,
14482 N_EQK | N_DBL, N_SU_32 | N_KEY);
14483 NEON_ENCODE (IMMED, inst);
14484 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14488 /* Check the various types for the VCVT instruction, and return which version
14489 the current instruction is. */
14491 #define CVT_FLAVOUR_VAR \
14492 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14493 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14494 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14495 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14496 /* Half-precision conversions. */ \
14497 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14498 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14499 /* VFP instructions. */ \
14500 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14501 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14502 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14503 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14504 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14505 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14506 /* VFP instructions with bitshift. */ \
14507 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14508 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14509 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14510 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14511 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14512 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14513 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14514 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14516 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14517 neon_cvt_flavour_##C,
14519 /* The different types of conversions we can do. */
14520 enum neon_cvt_flavour
14523 neon_cvt_flavour_invalid,
14524 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14529 static enum neon_cvt_flavour
14530 get_neon_cvt_flavour (enum neon_shape rs)
14532 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14533 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14534 if (et.type != NT_invtype) \
14536 inst.error = NULL; \
14537 return (neon_cvt_flavour_##C); \
14540 struct neon_type_el et;
14541 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14542 || rs == NS_FF) ? N_VFP : 0;
14543 /* The instruction versions which take an immediate take one register
14544 argument, which is extended to the width of the full register. Thus the
14545 "source" and "destination" registers must have the same width. Hack that
14546 here by making the size equal to the key (wider, in this case) operand. */
14547 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14551 return neon_cvt_flavour_invalid;
14566 /* Neon-syntax VFP conversions. */
14569 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
14571 const char *opname = 0;
14573 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14575 /* Conversions with immediate bitshift. */
14576 const char *enc[] =
14578 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14584 if (flavour < (int) ARRAY_SIZE (enc))
14586 opname = enc[flavour];
14587 constraint (inst.operands[0].reg != inst.operands[1].reg,
14588 _("operands 0 and 1 must be the same register"));
14589 inst.operands[1] = inst.operands[2];
14590 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14595 /* Conversions without bitshift. */
14596 const char *enc[] =
14598 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14604 if (flavour < (int) ARRAY_SIZE (enc))
14605 opname = enc[flavour];
14609 do_vfp_nsyn_opcode (opname);
14613 do_vfp_nsyn_cvtz (void)
14615 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14616 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14617 const char *enc[] =
14619 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14625 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14626 do_vfp_nsyn_opcode (enc[flavour]);
14630 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
14631 enum neon_cvt_mode mode)
14636 set_it_insn_type (OUTSIDE_IT_INSN);
14640 case neon_cvt_flavour_s32_f64:
14644 case neon_cvt_flavour_s32_f32:
14648 case neon_cvt_flavour_u32_f64:
14652 case neon_cvt_flavour_u32_f32:
14657 first_error (_("invalid instruction shape"));
14663 case neon_cvt_mode_a: rm = 0; break;
14664 case neon_cvt_mode_n: rm = 1; break;
14665 case neon_cvt_mode_p: rm = 2; break;
14666 case neon_cvt_mode_m: rm = 3; break;
14667 default: first_error (_("invalid rounding mode")); return;
14670 NEON_ENCODE (FPV8, inst);
14671 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14672 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14673 inst.instruction |= sz << 8;
14674 inst.instruction |= op << 7;
14675 inst.instruction |= rm << 16;
14676 inst.instruction |= 0xf0000000;
14677 inst.is_neon = TRUE;
14681 do_neon_cvt_1 (enum neon_cvt_mode mode)
14683 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14684 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14685 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
14687 /* PR11109: Handle round-to-zero for VCVT conversions. */
14688 if (mode == neon_cvt_mode_z
14689 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14690 && (flavour == neon_cvt_flavour_s32_f32
14691 || flavour == neon_cvt_flavour_u32_f32
14692 || flavour == neon_cvt_flavour_s32_f64
14693 || flavour == neon_cvt_flavour_u32_f64)
14694 && (rs == NS_FD || rs == NS_FF))
14696 do_vfp_nsyn_cvtz ();
14700 /* VFP rather than Neon conversions. */
14701 if (flavour >= neon_cvt_flavour_first_fp)
14703 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14704 do_vfp_nsyn_cvt (rs, flavour);
14706 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14717 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14719 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14722 /* Fixed-point conversion with #0 immediate is encoded as an
14723 integer conversion. */
14724 if (inst.operands[2].present && inst.operands[2].imm == 0)
14726 immbits = 32 - inst.operands[2].imm;
14727 NEON_ENCODE (IMMED, inst);
14728 if (flavour != neon_cvt_flavour_invalid)
14729 inst.instruction |= enctab[flavour];
14730 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14731 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14732 inst.instruction |= LOW4 (inst.operands[1].reg);
14733 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14734 inst.instruction |= neon_quad (rs) << 6;
14735 inst.instruction |= 1 << 21;
14736 inst.instruction |= immbits << 16;
14738 neon_dp_fixup (&inst);
14744 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14746 NEON_ENCODE (FLOAT, inst);
14747 set_it_insn_type (OUTSIDE_IT_INSN);
14749 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14752 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14753 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14754 inst.instruction |= LOW4 (inst.operands[1].reg);
14755 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14756 inst.instruction |= neon_quad (rs) << 6;
14757 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14758 inst.instruction |= mode << 8;
14760 inst.instruction |= 0xfc000000;
14762 inst.instruction |= 0xf0000000;
14768 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14770 NEON_ENCODE (INTEGER, inst);
14772 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14775 if (flavour != neon_cvt_flavour_invalid)
14776 inst.instruction |= enctab[flavour];
14778 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14779 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14780 inst.instruction |= LOW4 (inst.operands[1].reg);
14781 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14782 inst.instruction |= neon_quad (rs) << 6;
14783 inst.instruction |= 2 << 18;
14785 neon_dp_fixup (&inst);
14790 /* Half-precision conversions for Advanced SIMD -- neon. */
14795 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14797 as_bad (_("operand size must match register width"));
14802 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14804 as_bad (_("operand size must match register width"));
14809 inst.instruction = 0x3b60600;
14811 inst.instruction = 0x3b60700;
14813 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14814 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14815 inst.instruction |= LOW4 (inst.operands[1].reg);
14816 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14817 neon_dp_fixup (&inst);
14821 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14822 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14823 do_vfp_nsyn_cvt (rs, flavour);
14825 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14830 do_neon_cvtr (void)
14832 do_neon_cvt_1 (neon_cvt_mode_x);
14838 do_neon_cvt_1 (neon_cvt_mode_z);
14842 do_neon_cvta (void)
14844 do_neon_cvt_1 (neon_cvt_mode_a);
14848 do_neon_cvtn (void)
14850 do_neon_cvt_1 (neon_cvt_mode_n);
14854 do_neon_cvtp (void)
14856 do_neon_cvt_1 (neon_cvt_mode_p);
14860 do_neon_cvtm (void)
14862 do_neon_cvt_1 (neon_cvt_mode_m);
14866 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
14869 mark_feature_used (&fpu_vfp_ext_armv8);
14871 encode_arm_vfp_reg (inst.operands[0].reg,
14872 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14873 encode_arm_vfp_reg (inst.operands[1].reg,
14874 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14875 inst.instruction |= to ? 0x10000 : 0;
14876 inst.instruction |= t ? 0x80 : 0;
14877 inst.instruction |= is_double ? 0x100 : 0;
14878 do_vfp_cond_or_thumb ();
14882 do_neon_cvttb_1 (bfd_boolean t)
14884 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
14888 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14891 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14893 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14896 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14898 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14901 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14903 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14906 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14913 do_neon_cvtb (void)
14915 do_neon_cvttb_1 (FALSE);
14920 do_neon_cvtt (void)
14922 do_neon_cvttb_1 (TRUE);
14926 neon_move_immediate (void)
14928 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14929 struct neon_type_el et = neon_check_type (2, rs,
14930 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14931 unsigned immlo, immhi = 0, immbits;
14932 int op, cmode, float_p;
14934 constraint (et.type == NT_invtype,
14935 _("operand size must be specified for immediate VMOV"));
14937 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14938 op = (inst.instruction & (1 << 5)) != 0;
14940 immlo = inst.operands[1].imm;
14941 if (inst.operands[1].regisimm)
14942 immhi = inst.operands[1].reg;
14944 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14945 _("immediate has bits set outside the operand size"));
14947 float_p = inst.operands[1].immisfloat;
14949 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14950 et.size, et.type)) == FAIL)
14952 /* Invert relevant bits only. */
14953 neon_invert_size (&immlo, &immhi, et.size);
14954 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14955 with one or the other; those cases are caught by
14956 neon_cmode_for_move_imm. */
14958 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14959 &op, et.size, et.type)) == FAIL)
14961 first_error (_("immediate out of range"));
14966 inst.instruction &= ~(1 << 5);
14967 inst.instruction |= op << 5;
14969 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14970 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14971 inst.instruction |= neon_quad (rs) << 6;
14972 inst.instruction |= cmode << 8;
14974 neon_write_immbits (immbits);
14980 if (inst.operands[1].isreg)
14982 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14984 NEON_ENCODE (INTEGER, inst);
14985 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14986 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14987 inst.instruction |= LOW4 (inst.operands[1].reg);
14988 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14989 inst.instruction |= neon_quad (rs) << 6;
14993 NEON_ENCODE (IMMED, inst);
14994 neon_move_immediate ();
14997 neon_dp_fixup (&inst);
15000 /* Encode instructions of form:
15002 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15003 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15006 neon_mixed_length (struct neon_type_el et, unsigned size)
15008 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15009 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15010 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15011 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15012 inst.instruction |= LOW4 (inst.operands[2].reg);
15013 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15014 inst.instruction |= (et.type == NT_unsigned) << 24;
15015 inst.instruction |= neon_logbits (size) << 20;
15017 neon_dp_fixup (&inst);
15021 do_neon_dyadic_long (void)
15023 /* FIXME: Type checking for lengthening op. */
15024 struct neon_type_el et = neon_check_type (3, NS_QDD,
15025 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15026 neon_mixed_length (et, et.size);
15030 do_neon_abal (void)
15032 struct neon_type_el et = neon_check_type (3, NS_QDD,
15033 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15034 neon_mixed_length (et, et.size);
15038 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15040 if (inst.operands[2].isscalar)
15042 struct neon_type_el et = neon_check_type (3, NS_QDS,
15043 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15044 NEON_ENCODE (SCALAR, inst);
15045 neon_mul_mac (et, et.type == NT_unsigned);
15049 struct neon_type_el et = neon_check_type (3, NS_QDD,
15050 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15051 NEON_ENCODE (INTEGER, inst);
15052 neon_mixed_length (et, et.size);
15057 do_neon_mac_maybe_scalar_long (void)
15059 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15063 do_neon_dyadic_wide (void)
15065 struct neon_type_el et = neon_check_type (3, NS_QQD,
15066 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15067 neon_mixed_length (et, et.size);
15071 do_neon_dyadic_narrow (void)
15073 struct neon_type_el et = neon_check_type (3, NS_QDD,
15074 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15075 /* Operand sign is unimportant, and the U bit is part of the opcode,
15076 so force the operand type to integer. */
15077 et.type = NT_integer;
15078 neon_mixed_length (et, et.size / 2);
15082 do_neon_mul_sat_scalar_long (void)
15084 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15088 do_neon_vmull (void)
15090 if (inst.operands[2].isscalar)
15091 do_neon_mac_maybe_scalar_long ();
15094 struct neon_type_el et = neon_check_type (3, NS_QDD,
15095 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15097 if (et.type == NT_poly)
15098 NEON_ENCODE (POLY, inst);
15100 NEON_ENCODE (INTEGER, inst);
15102 /* For polynomial encoding the U bit must be zero, and the size must
15103 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15104 obviously, as 0b10). */
15107 /* Check we're on the correct architecture. */
15108 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15110 _("Instruction form not available on this architecture.");
15115 neon_mixed_length (et, et.size);
15122 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15123 struct neon_type_el et = neon_check_type (3, rs,
15124 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15125 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15127 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15128 _("shift out of range"));
15129 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15130 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15131 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15132 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15133 inst.instruction |= LOW4 (inst.operands[2].reg);
15134 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15135 inst.instruction |= neon_quad (rs) << 6;
15136 inst.instruction |= imm << 8;
15138 neon_dp_fixup (&inst);
15144 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15145 struct neon_type_el et = neon_check_type (2, rs,
15146 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15147 unsigned op = (inst.instruction >> 7) & 3;
15148 /* N (width of reversed regions) is encoded as part of the bitmask. We
15149 extract it here to check the elements to be reversed are smaller.
15150 Otherwise we'd get a reserved instruction. */
15151 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15152 gas_assert (elsize != 0);
15153 constraint (et.size >= elsize,
15154 _("elements must be smaller than reversal region"));
15155 neon_two_same (neon_quad (rs), 1, et.size);
15161 if (inst.operands[1].isscalar)
15163 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15164 struct neon_type_el et = neon_check_type (2, rs,
15165 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15166 unsigned sizebits = et.size >> 3;
15167 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15168 int logsize = neon_logbits (et.size);
15169 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15171 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15174 NEON_ENCODE (SCALAR, inst);
15175 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15176 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15177 inst.instruction |= LOW4 (dm);
15178 inst.instruction |= HI1 (dm) << 5;
15179 inst.instruction |= neon_quad (rs) << 6;
15180 inst.instruction |= x << 17;
15181 inst.instruction |= sizebits << 16;
15183 neon_dp_fixup (&inst);
15187 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15188 struct neon_type_el et = neon_check_type (2, rs,
15189 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15190 /* Duplicate ARM register to lanes of vector. */
15191 NEON_ENCODE (ARMREG, inst);
15194 case 8: inst.instruction |= 0x400000; break;
15195 case 16: inst.instruction |= 0x000020; break;
15196 case 32: inst.instruction |= 0x000000; break;
15199 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15200 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15201 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15202 inst.instruction |= neon_quad (rs) << 21;
15203 /* The encoding for this instruction is identical for the ARM and Thumb
15204 variants, except for the condition field. */
15205 do_vfp_cond_or_thumb ();
15209 /* VMOV has particularly many variations. It can be one of:
15210 0. VMOV<c><q> <Qd>, <Qm>
15211 1. VMOV<c><q> <Dd>, <Dm>
15212 (Register operations, which are VORR with Rm = Rn.)
15213 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15214 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15216 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15217 (ARM register to scalar.)
15218 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15219 (Two ARM registers to vector.)
15220 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15221 (Scalar to ARM register.)
15222 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15223 (Vector to two ARM registers.)
15224 8. VMOV.F32 <Sd>, <Sm>
15225 9. VMOV.F64 <Dd>, <Dm>
15226 (VFP register moves.)
15227 10. VMOV.F32 <Sd>, #imm
15228 11. VMOV.F64 <Dd>, #imm
15229 (VFP float immediate load.)
15230 12. VMOV <Rd>, <Sm>
15231 (VFP single to ARM reg.)
15232 13. VMOV <Sd>, <Rm>
15233 (ARM reg to VFP single.)
15234 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15235 (Two ARM regs to two VFP singles.)
15236 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15237 (Two VFP singles to two ARM regs.)
15239 These cases can be disambiguated using neon_select_shape, except cases 1/9
15240 and 3/11 which depend on the operand type too.
15242 All the encoded bits are hardcoded by this function.
15244 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15245 Cases 5, 7 may be used with VFPv2 and above.
15247 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15248 can specify a type where it doesn't make sense to, and is ignored). */
15253 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15254 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15256 struct neon_type_el et;
15257 const char *ldconst = 0;
15261 case NS_DD: /* case 1/9. */
15262 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15263 /* It is not an error here if no type is given. */
15265 if (et.type == NT_float && et.size == 64)
15267 do_vfp_nsyn_opcode ("fcpyd");
15270 /* fall through. */
15272 case NS_QQ: /* case 0/1. */
15274 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15276 /* The architecture manual I have doesn't explicitly state which
15277 value the U bit should have for register->register moves, but
15278 the equivalent VORR instruction has U = 0, so do that. */
15279 inst.instruction = 0x0200110;
15280 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15281 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15282 inst.instruction |= LOW4 (inst.operands[1].reg);
15283 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15284 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15285 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15286 inst.instruction |= neon_quad (rs) << 6;
15288 neon_dp_fixup (&inst);
15292 case NS_DI: /* case 3/11. */
15293 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15295 if (et.type == NT_float && et.size == 64)
15297 /* case 11 (fconstd). */
15298 ldconst = "fconstd";
15299 goto encode_fconstd;
15301 /* fall through. */
15303 case NS_QI: /* case 2/3. */
15304 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15306 inst.instruction = 0x0800010;
15307 neon_move_immediate ();
15308 neon_dp_fixup (&inst);
15311 case NS_SR: /* case 4. */
15313 unsigned bcdebits = 0;
15315 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15316 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15318 /* .<size> is optional here, defaulting to .32. */
15319 if (inst.vectype.elems == 0
15320 && inst.operands[0].vectype.type == NT_invtype
15321 && inst.operands[1].vectype.type == NT_invtype)
15323 inst.vectype.el[0].type = NT_untyped;
15324 inst.vectype.el[0].size = 32;
15325 inst.vectype.elems = 1;
15328 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15329 logsize = neon_logbits (et.size);
15331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15333 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15334 && et.size != 32, _(BAD_FPU));
15335 constraint (et.type == NT_invtype, _("bad type for scalar"));
15336 constraint (x >= 64 / et.size, _("scalar index out of range"));
15340 case 8: bcdebits = 0x8; break;
15341 case 16: bcdebits = 0x1; break;
15342 case 32: bcdebits = 0x0; break;
15346 bcdebits |= x << logsize;
15348 inst.instruction = 0xe000b10;
15349 do_vfp_cond_or_thumb ();
15350 inst.instruction |= LOW4 (dn) << 16;
15351 inst.instruction |= HI1 (dn) << 7;
15352 inst.instruction |= inst.operands[1].reg << 12;
15353 inst.instruction |= (bcdebits & 3) << 5;
15354 inst.instruction |= (bcdebits >> 2) << 21;
15358 case NS_DRR: /* case 5 (fmdrr). */
15359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15362 inst.instruction = 0xc400b10;
15363 do_vfp_cond_or_thumb ();
15364 inst.instruction |= LOW4 (inst.operands[0].reg);
15365 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15366 inst.instruction |= inst.operands[1].reg << 12;
15367 inst.instruction |= inst.operands[2].reg << 16;
15370 case NS_RS: /* case 6. */
15373 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15374 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15375 unsigned abcdebits = 0;
15377 /* .<dt> is optional here, defaulting to .32. */
15378 if (inst.vectype.elems == 0
15379 && inst.operands[0].vectype.type == NT_invtype
15380 && inst.operands[1].vectype.type == NT_invtype)
15382 inst.vectype.el[0].type = NT_untyped;
15383 inst.vectype.el[0].size = 32;
15384 inst.vectype.elems = 1;
15387 et = neon_check_type (2, NS_NULL,
15388 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15389 logsize = neon_logbits (et.size);
15391 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15394 && et.size != 32, _(BAD_FPU));
15395 constraint (et.type == NT_invtype, _("bad type for scalar"));
15396 constraint (x >= 64 / et.size, _("scalar index out of range"));
15400 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15401 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15402 case 32: abcdebits = 0x00; break;
15406 abcdebits |= x << logsize;
15407 inst.instruction = 0xe100b10;
15408 do_vfp_cond_or_thumb ();
15409 inst.instruction |= LOW4 (dn) << 16;
15410 inst.instruction |= HI1 (dn) << 7;
15411 inst.instruction |= inst.operands[0].reg << 12;
15412 inst.instruction |= (abcdebits & 3) << 5;
15413 inst.instruction |= (abcdebits >> 2) << 21;
15417 case NS_RRD: /* case 7 (fmrrd). */
15418 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15421 inst.instruction = 0xc500b10;
15422 do_vfp_cond_or_thumb ();
15423 inst.instruction |= inst.operands[0].reg << 12;
15424 inst.instruction |= inst.operands[1].reg << 16;
15425 inst.instruction |= LOW4 (inst.operands[2].reg);
15426 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15429 case NS_FF: /* case 8 (fcpys). */
15430 do_vfp_nsyn_opcode ("fcpys");
15433 case NS_FI: /* case 10 (fconsts). */
15434 ldconst = "fconsts";
15436 if (is_quarter_float (inst.operands[1].imm))
15438 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15439 do_vfp_nsyn_opcode (ldconst);
15442 first_error (_("immediate out of range"));
15445 case NS_RF: /* case 12 (fmrs). */
15446 do_vfp_nsyn_opcode ("fmrs");
15449 case NS_FR: /* case 13 (fmsr). */
15450 do_vfp_nsyn_opcode ("fmsr");
15453 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15454 (one of which is a list), but we have parsed four. Do some fiddling to
15455 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15457 case NS_RRFF: /* case 14 (fmrrs). */
15458 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15459 _("VFP registers must be adjacent"));
15460 inst.operands[2].imm = 2;
15461 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15462 do_vfp_nsyn_opcode ("fmrrs");
15465 case NS_FFRR: /* case 15 (fmsrr). */
15466 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15467 _("VFP registers must be adjacent"));
15468 inst.operands[1] = inst.operands[2];
15469 inst.operands[2] = inst.operands[3];
15470 inst.operands[0].imm = 2;
15471 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15472 do_vfp_nsyn_opcode ("fmsrr");
15476 /* neon_select_shape has determined that the instruction
15477 shape is wrong and has already set the error message. */
15486 do_neon_rshift_round_imm (void)
15488 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15489 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15490 int imm = inst.operands[2].imm;
15492 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15495 inst.operands[2].present = 0;
15500 constraint (imm < 1 || (unsigned)imm > et.size,
15501 _("immediate out of range for shift"));
15502 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15507 do_neon_movl (void)
15509 struct neon_type_el et = neon_check_type (2, NS_QD,
15510 N_EQK | N_DBL, N_SU_32 | N_KEY);
15511 unsigned sizebits = et.size >> 3;
15512 inst.instruction |= sizebits << 19;
15513 neon_two_same (0, et.type == NT_unsigned, -1);
15519 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15520 struct neon_type_el et = neon_check_type (2, rs,
15521 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15522 NEON_ENCODE (INTEGER, inst);
15523 neon_two_same (neon_quad (rs), 1, et.size);
15527 do_neon_zip_uzp (void)
15529 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15530 struct neon_type_el et = neon_check_type (2, rs,
15531 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15532 if (rs == NS_DD && et.size == 32)
15534 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15535 inst.instruction = N_MNEM_vtrn;
15539 neon_two_same (neon_quad (rs), 1, et.size);
15543 do_neon_sat_abs_neg (void)
15545 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15546 struct neon_type_el et = neon_check_type (2, rs,
15547 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15548 neon_two_same (neon_quad (rs), 1, et.size);
15552 do_neon_pair_long (void)
15554 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15555 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15556 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15557 inst.instruction |= (et.type == NT_unsigned) << 7;
15558 neon_two_same (neon_quad (rs), 1, et.size);
15562 do_neon_recip_est (void)
15564 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15565 struct neon_type_el et = neon_check_type (2, rs,
15566 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15567 inst.instruction |= (et.type == NT_float) << 8;
15568 neon_two_same (neon_quad (rs), 1, et.size);
15574 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15575 struct neon_type_el et = neon_check_type (2, rs,
15576 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15577 neon_two_same (neon_quad (rs), 1, et.size);
15583 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15584 struct neon_type_el et = neon_check_type (2, rs,
15585 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15586 neon_two_same (neon_quad (rs), 1, et.size);
15592 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15593 struct neon_type_el et = neon_check_type (2, rs,
15594 N_EQK | N_INT, N_8 | N_KEY);
15595 neon_two_same (neon_quad (rs), 1, et.size);
15601 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15602 neon_two_same (neon_quad (rs), 1, -1);
15606 do_neon_tbl_tbx (void)
15608 unsigned listlenbits;
15609 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15611 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15613 first_error (_("bad list length for table lookup"));
15617 listlenbits = inst.operands[1].imm - 1;
15618 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15619 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15620 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15621 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15622 inst.instruction |= LOW4 (inst.operands[2].reg);
15623 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15624 inst.instruction |= listlenbits << 8;
15626 neon_dp_fixup (&inst);
15630 do_neon_ldm_stm (void)
15632 /* P, U and L bits are part of bitmask. */
15633 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15634 unsigned offsetbits = inst.operands[1].imm * 2;
15636 if (inst.operands[1].issingle)
15638 do_vfp_nsyn_ldm_stm (is_dbmode);
15642 constraint (is_dbmode && !inst.operands[0].writeback,
15643 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15645 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15646 _("register list must contain at least 1 and at most 16 "
15649 inst.instruction |= inst.operands[0].reg << 16;
15650 inst.instruction |= inst.operands[0].writeback << 21;
15651 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15652 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15654 inst.instruction |= offsetbits;
15656 do_vfp_cond_or_thumb ();
15660 do_neon_ldr_str (void)
15662 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15664 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15665 And is UNPREDICTABLE in thumb mode. */
15667 && inst.operands[1].reg == REG_PC
15668 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
15671 inst.error = _("Use of PC here is UNPREDICTABLE");
15672 else if (warn_on_deprecated)
15673 as_warn (_("Use of PC here is deprecated"));
15676 if (inst.operands[0].issingle)
15679 do_vfp_nsyn_opcode ("flds");
15681 do_vfp_nsyn_opcode ("fsts");
15686 do_vfp_nsyn_opcode ("fldd");
15688 do_vfp_nsyn_opcode ("fstd");
15692 /* "interleave" version also handles non-interleaving register VLD1/VST1
15696 do_neon_ld_st_interleave (void)
15698 struct neon_type_el et = neon_check_type (1, NS_NULL,
15699 N_8 | N_16 | N_32 | N_64);
15700 unsigned alignbits = 0;
15702 /* The bits in this table go:
15703 0: register stride of one (0) or two (1)
15704 1,2: register list length, minus one (1, 2, 3, 4).
15705 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15706 We use -1 for invalid entries. */
15707 const int typetable[] =
15709 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15710 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15711 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15712 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15716 if (et.type == NT_invtype)
15719 if (inst.operands[1].immisalign)
15720 switch (inst.operands[1].imm >> 8)
15722 case 64: alignbits = 1; break;
15724 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15725 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15726 goto bad_alignment;
15730 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15731 goto bad_alignment;
15736 first_error (_("bad alignment"));
15740 inst.instruction |= alignbits << 4;
15741 inst.instruction |= neon_logbits (et.size) << 6;
15743 /* Bits [4:6] of the immediate in a list specifier encode register stride
15744 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15745 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15746 up the right value for "type" in a table based on this value and the given
15747 list style, then stick it back. */
15748 idx = ((inst.operands[0].imm >> 4) & 7)
15749 | (((inst.instruction >> 8) & 3) << 3);
15751 typebits = typetable[idx];
15753 constraint (typebits == -1, _("bad list type for instruction"));
15755 inst.instruction &= ~0xf00;
15756 inst.instruction |= typebits << 8;
15759 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15760 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15761 otherwise. The variable arguments are a list of pairs of legal (size, align)
15762 values, terminated with -1. */
15765 neon_alignment_bit (int size, int align, int *do_align, ...)
15768 int result = FAIL, thissize, thisalign;
15770 if (!inst.operands[1].immisalign)
15776 va_start (ap, do_align);
15780 thissize = va_arg (ap, int);
15781 if (thissize == -1)
15783 thisalign = va_arg (ap, int);
15785 if (size == thissize && align == thisalign)
15788 while (result != SUCCESS);
15792 if (result == SUCCESS)
15795 first_error (_("unsupported alignment for instruction"));
15801 do_neon_ld_st_lane (void)
15803 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15804 int align_good, do_align = 0;
15805 int logsize = neon_logbits (et.size);
15806 int align = inst.operands[1].imm >> 8;
15807 int n = (inst.instruction >> 8) & 3;
15808 int max_el = 64 / et.size;
15810 if (et.type == NT_invtype)
15813 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15814 _("bad list length"));
15815 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15816 _("scalar index out of range"));
15817 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15819 _("stride of 2 unavailable when element size is 8"));
15823 case 0: /* VLD1 / VST1. */
15824 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15826 if (align_good == FAIL)
15830 unsigned alignbits = 0;
15833 case 16: alignbits = 0x1; break;
15834 case 32: alignbits = 0x3; break;
15837 inst.instruction |= alignbits << 4;
15841 case 1: /* VLD2 / VST2. */
15842 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15844 if (align_good == FAIL)
15847 inst.instruction |= 1 << 4;
15850 case 2: /* VLD3 / VST3. */
15851 constraint (inst.operands[1].immisalign,
15852 _("can't use alignment with this instruction"));
15855 case 3: /* VLD4 / VST4. */
15856 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15857 16, 64, 32, 64, 32, 128, -1);
15858 if (align_good == FAIL)
15862 unsigned alignbits = 0;
15865 case 8: alignbits = 0x1; break;
15866 case 16: alignbits = 0x1; break;
15867 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15870 inst.instruction |= alignbits << 4;
15877 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15878 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15879 inst.instruction |= 1 << (4 + logsize);
15881 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15882 inst.instruction |= logsize << 10;
15885 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15888 do_neon_ld_dup (void)
15890 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15891 int align_good, do_align = 0;
15893 if (et.type == NT_invtype)
15896 switch ((inst.instruction >> 8) & 3)
15898 case 0: /* VLD1. */
15899 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15900 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15901 &do_align, 16, 16, 32, 32, -1);
15902 if (align_good == FAIL)
15904 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15907 case 2: inst.instruction |= 1 << 5; break;
15908 default: first_error (_("bad list length")); return;
15910 inst.instruction |= neon_logbits (et.size) << 6;
15913 case 1: /* VLD2. */
15914 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15915 &do_align, 8, 16, 16, 32, 32, 64, -1);
15916 if (align_good == FAIL)
15918 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15919 _("bad list length"));
15920 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15921 inst.instruction |= 1 << 5;
15922 inst.instruction |= neon_logbits (et.size) << 6;
15925 case 2: /* VLD3. */
15926 constraint (inst.operands[1].immisalign,
15927 _("can't use alignment with this instruction"));
15928 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15929 _("bad list length"));
15930 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15931 inst.instruction |= 1 << 5;
15932 inst.instruction |= neon_logbits (et.size) << 6;
15935 case 3: /* VLD4. */
15937 int align = inst.operands[1].imm >> 8;
15938 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15939 16, 64, 32, 64, 32, 128, -1);
15940 if (align_good == FAIL)
15942 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15943 _("bad list length"));
15944 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15945 inst.instruction |= 1 << 5;
15946 if (et.size == 32 && align == 128)
15947 inst.instruction |= 0x3 << 6;
15949 inst.instruction |= neon_logbits (et.size) << 6;
15956 inst.instruction |= do_align << 4;
15959 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15960 apart from bits [11:4]. */
15963 do_neon_ldx_stx (void)
15965 if (inst.operands[1].isreg)
15966 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15968 switch (NEON_LANE (inst.operands[0].imm))
15970 case NEON_INTERLEAVE_LANES:
15971 NEON_ENCODE (INTERLV, inst);
15972 do_neon_ld_st_interleave ();
15975 case NEON_ALL_LANES:
15976 NEON_ENCODE (DUP, inst);
15977 if (inst.instruction == N_INV)
15979 first_error ("only loads support such operands");
15986 NEON_ENCODE (LANE, inst);
15987 do_neon_ld_st_lane ();
15990 /* L bit comes from bit mask. */
15991 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15992 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15993 inst.instruction |= inst.operands[1].reg << 16;
15995 if (inst.operands[1].postind)
15997 int postreg = inst.operands[1].imm & 0xf;
15998 constraint (!inst.operands[1].immisreg,
15999 _("post-index must be a register"));
16000 constraint (postreg == 0xd || postreg == 0xf,
16001 _("bad register for post-index"));
16002 inst.instruction |= postreg;
16004 else if (inst.operands[1].writeback)
16006 inst.instruction |= 0xd;
16009 inst.instruction |= 0xf;
16012 inst.instruction |= 0xf9000000;
16014 inst.instruction |= 0xf4000000;
16019 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16021 NEON_ENCODE (FPV8, inst);
16024 do_vfp_sp_dyadic ();
16026 do_vfp_dp_rd_rn_rm ();
16029 inst.instruction |= 0x100;
16031 inst.instruction |= 0xf0000000;
16037 set_it_insn_type (OUTSIDE_IT_INSN);
16039 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16040 first_error (_("invalid instruction shape"));
16046 set_it_insn_type (OUTSIDE_IT_INSN);
16048 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16051 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16054 neon_dyadic_misc (NT_untyped, N_F32, 0);
16058 do_vrint_1 (enum neon_cvt_mode mode)
16060 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16061 struct neon_type_el et;
16066 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16067 if (et.type != NT_invtype)
16069 /* VFP encodings. */
16070 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16071 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16072 set_it_insn_type (OUTSIDE_IT_INSN);
16074 NEON_ENCODE (FPV8, inst);
16076 do_vfp_sp_monadic ();
16078 do_vfp_dp_rd_rm ();
16082 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16083 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16084 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16085 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16086 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16087 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16088 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16092 inst.instruction |= (rs == NS_DD) << 8;
16093 do_vfp_cond_or_thumb ();
16097 /* Neon encodings (or something broken...). */
16099 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16101 if (et.type == NT_invtype)
16104 set_it_insn_type (OUTSIDE_IT_INSN);
16105 NEON_ENCODE (FLOAT, inst);
16107 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16110 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16111 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16112 inst.instruction |= LOW4 (inst.operands[1].reg);
16113 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16114 inst.instruction |= neon_quad (rs) << 6;
16117 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16118 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16119 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16120 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16121 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16122 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16123 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16128 inst.instruction |= 0xfc000000;
16130 inst.instruction |= 0xf0000000;
16137 do_vrint_1 (neon_cvt_mode_x);
16143 do_vrint_1 (neon_cvt_mode_z);
16149 do_vrint_1 (neon_cvt_mode_r);
16155 do_vrint_1 (neon_cvt_mode_a);
16161 do_vrint_1 (neon_cvt_mode_n);
16167 do_vrint_1 (neon_cvt_mode_p);
16173 do_vrint_1 (neon_cvt_mode_m);
16176 /* Crypto v1 instructions. */
16178 do_crypto_2op_1 (unsigned elttype, int op)
16180 set_it_insn_type (OUTSIDE_IT_INSN);
16182 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16188 NEON_ENCODE (INTEGER, inst);
16189 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16190 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16191 inst.instruction |= LOW4 (inst.operands[1].reg);
16192 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16194 inst.instruction |= op << 6;
16197 inst.instruction |= 0xfc000000;
16199 inst.instruction |= 0xf0000000;
16203 do_crypto_3op_1 (int u, int op)
16205 set_it_insn_type (OUTSIDE_IT_INSN);
16207 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16208 N_32 | N_UNT | N_KEY).type == NT_invtype)
16213 NEON_ENCODE (INTEGER, inst);
16214 neon_three_same (1, u, 8 << op);
16220 do_crypto_2op_1 (N_8, 0);
16226 do_crypto_2op_1 (N_8, 1);
16232 do_crypto_2op_1 (N_8, 2);
16238 do_crypto_2op_1 (N_8, 3);
16244 do_crypto_3op_1 (0, 0);
16250 do_crypto_3op_1 (0, 1);
16256 do_crypto_3op_1 (0, 2);
16262 do_crypto_3op_1 (0, 3);
16268 do_crypto_3op_1 (1, 0);
16274 do_crypto_3op_1 (1, 1);
16278 do_sha256su1 (void)
16280 do_crypto_3op_1 (1, 2);
16286 do_crypto_2op_1 (N_32, -1);
16292 do_crypto_2op_1 (N_32, 0);
16296 do_sha256su0 (void)
16298 do_crypto_2op_1 (N_32, 1);
16302 do_crc32_1 (unsigned int poly, unsigned int sz)
16304 unsigned int Rd = inst.operands[0].reg;
16305 unsigned int Rn = inst.operands[1].reg;
16306 unsigned int Rm = inst.operands[2].reg;
16308 set_it_insn_type (OUTSIDE_IT_INSN);
16309 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16310 inst.instruction |= LOW4 (Rn) << 16;
16311 inst.instruction |= LOW4 (Rm);
16312 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16313 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16315 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16316 as_warn (UNPRED_REG ("r15"));
16317 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16318 as_warn (UNPRED_REG ("r13"));
16358 /* Overall per-instruction processing. */
16360 /* We need to be able to fix up arbitrary expressions in some statements.
16361 This is so that we can handle symbols that are an arbitrary distance from
16362 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16363 which returns part of an address in a form which will be valid for
16364 a data instruction. We do this by pushing the expression into a symbol
16365 in the expr_section, and creating a fix for that. */
16368 fix_new_arm (fragS * frag,
16382 /* Create an absolute valued symbol, so we have something to
16383 refer to in the object file. Unfortunately for us, gas's
16384 generic expression parsing will already have folded out
16385 any use of .set foo/.type foo %function that may have
16386 been used to set type information of the target location,
16387 that's being specified symbolically. We have to presume
16388 the user knows what they are doing. */
16392 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16394 symbol = symbol_find_or_make (name);
16395 S_SET_SEGMENT (symbol, absolute_section);
16396 symbol_set_frag (symbol, &zero_address_frag);
16397 S_SET_VALUE (symbol, exp->X_add_number);
16398 exp->X_op = O_symbol;
16399 exp->X_add_symbol = symbol;
16400 exp->X_add_number = 0;
16406 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
16407 (enum bfd_reloc_code_real) reloc);
16411 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
16412 pc_rel, (enum bfd_reloc_code_real) reloc);
16416 /* Mark whether the fix is to a THUMB instruction, or an ARM
16418 new_fix->tc_fix_data = thumb_mode;
16421 /* Create a frg for an instruction requiring relaxation. */
16423 output_relax_insn (void)
16429 /* The size of the instruction is unknown, so tie the debug info to the
16430 start of the instruction. */
16431 dwarf2_emit_insn (0);
16433 switch (inst.reloc.exp.X_op)
16436 sym = inst.reloc.exp.X_add_symbol;
16437 offset = inst.reloc.exp.X_add_number;
16441 offset = inst.reloc.exp.X_add_number;
16444 sym = make_expr_symbol (&inst.reloc.exp);
16448 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16449 inst.relax, sym, offset, NULL/*offset, opcode*/);
16450 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
16453 /* Write a 32-bit thumb instruction to buf. */
16455 put_thumb32_insn (char * buf, unsigned long insn)
16457 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16458 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16462 output_inst (const char * str)
16468 as_bad ("%s -- `%s'", inst.error, str);
16473 output_relax_insn ();
16476 if (inst.size == 0)
16479 to = frag_more (inst.size);
16480 /* PR 9814: Record the thumb mode into the current frag so that we know
16481 what type of NOP padding to use, if necessary. We override any previous
16482 setting so that if the mode has changed then the NOPS that we use will
16483 match the encoding of the last instruction in the frag. */
16484 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
16486 if (thumb_mode && (inst.size > THUMB_SIZE))
16488 gas_assert (inst.size == (2 * THUMB_SIZE));
16489 put_thumb32_insn (to, inst.instruction);
16491 else if (inst.size > INSN_SIZE)
16493 gas_assert (inst.size == (2 * INSN_SIZE));
16494 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16495 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
16498 md_number_to_chars (to, inst.instruction, inst.size);
16500 if (inst.reloc.type != BFD_RELOC_UNUSED)
16501 fix_new_arm (frag_now, to - frag_now->fr_literal,
16502 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16505 dwarf2_emit_insn (inst.size);
16509 output_it_inst (int cond, int mask, char * to)
16511 unsigned long instruction = 0xbf00;
16514 instruction |= mask;
16515 instruction |= cond << 4;
16519 to = frag_more (2);
16521 dwarf2_emit_insn (2);
16525 md_number_to_chars (to, instruction, 2);
16530 /* Tag values used in struct asm_opcode's tag field. */
16533 OT_unconditional, /* Instruction cannot be conditionalized.
16534 The ARM condition field is still 0xE. */
16535 OT_unconditionalF, /* Instruction cannot be conditionalized
16536 and carries 0xF in its ARM condition field. */
16537 OT_csuffix, /* Instruction takes a conditional suffix. */
16538 OT_csuffixF, /* Some forms of the instruction take a conditional
16539 suffix, others place 0xF where the condition field
16541 OT_cinfix3, /* Instruction takes a conditional infix,
16542 beginning at character index 3. (In
16543 unified mode, it becomes a suffix.) */
16544 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16545 tsts, cmps, cmns, and teqs. */
16546 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16547 character index 3, even in unified mode. Used for
16548 legacy instructions where suffix and infix forms
16549 may be ambiguous. */
16550 OT_csuf_or_in3, /* Instruction takes either a conditional
16551 suffix or an infix at character index 3. */
16552 OT_odd_infix_unc, /* This is the unconditional variant of an
16553 instruction that takes a conditional infix
16554 at an unusual position. In unified mode,
16555 this variant will accept a suffix. */
16556 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16557 are the conditional variants of instructions that
16558 take conditional infixes in unusual positions.
16559 The infix appears at character index
16560 (tag - OT_odd_infix_0). These are not accepted
16561 in unified mode. */
16564 /* Subroutine of md_assemble, responsible for looking up the primary
16565 opcode from the mnemonic the user wrote. STR points to the
16566 beginning of the mnemonic.
16568 This is not simply a hash table lookup, because of conditional
16569 variants. Most instructions have conditional variants, which are
16570 expressed with a _conditional affix_ to the mnemonic. If we were
16571 to encode each conditional variant as a literal string in the opcode
16572 table, it would have approximately 20,000 entries.
16574 Most mnemonics take this affix as a suffix, and in unified syntax,
16575 'most' is upgraded to 'all'. However, in the divided syntax, some
16576 instructions take the affix as an infix, notably the s-variants of
16577 the arithmetic instructions. Of those instructions, all but six
16578 have the infix appear after the third character of the mnemonic.
16580 Accordingly, the algorithm for looking up primary opcodes given
16583 1. Look up the identifier in the opcode table.
16584 If we find a match, go to step U.
16586 2. Look up the last two characters of the identifier in the
16587 conditions table. If we find a match, look up the first N-2
16588 characters of the identifier in the opcode table. If we
16589 find a match, go to step CE.
16591 3. Look up the fourth and fifth characters of the identifier in
16592 the conditions table. If we find a match, extract those
16593 characters from the identifier, and look up the remaining
16594 characters in the opcode table. If we find a match, go
16599 U. Examine the tag field of the opcode structure, in case this is
16600 one of the six instructions with its conditional infix in an
16601 unusual place. If it is, the tag tells us where to find the
16602 infix; look it up in the conditions table and set inst.cond
16603 accordingly. Otherwise, this is an unconditional instruction.
16604 Again set inst.cond accordingly. Return the opcode structure.
16606 CE. Examine the tag field to make sure this is an instruction that
16607 should receive a conditional suffix. If it is not, fail.
16608 Otherwise, set inst.cond from the suffix we already looked up,
16609 and return the opcode structure.
16611 CM. Examine the tag field to make sure this is an instruction that
16612 should receive a conditional infix after the third character.
16613 If it is not, fail. Otherwise, undo the edits to the current
16614 line of input and proceed as for case CE. */
16616 static const struct asm_opcode *
16617 opcode_lookup (char **str)
16621 const struct asm_opcode *opcode;
16622 const struct asm_cond *cond;
16625 /* Scan up to the end of the mnemonic, which must end in white space,
16626 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16627 for (base = end = *str; *end != '\0'; end++)
16628 if (*end == ' ' || *end == '.')
16634 /* Handle a possible width suffix and/or Neon type suffix. */
16639 /* The .w and .n suffixes are only valid if the unified syntax is in
16641 if (unified_syntax && end[1] == 'w')
16643 else if (unified_syntax && end[1] == 'n')
16648 inst.vectype.elems = 0;
16650 *str = end + offset;
16652 if (end[offset] == '.')
16654 /* See if we have a Neon type suffix (possible in either unified or
16655 non-unified ARM syntax mode). */
16656 if (parse_neon_type (&inst.vectype, str) == FAIL)
16659 else if (end[offset] != '\0' && end[offset] != ' ')
16665 /* Look for unaffixed or special-case affixed mnemonic. */
16666 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16671 if (opcode->tag < OT_odd_infix_0)
16673 inst.cond = COND_ALWAYS;
16677 if (warn_on_deprecated && unified_syntax)
16678 as_warn (_("conditional infixes are deprecated in unified syntax"));
16679 affix = base + (opcode->tag - OT_odd_infix_0);
16680 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16683 inst.cond = cond->value;
16687 /* Cannot have a conditional suffix on a mnemonic of less than two
16689 if (end - base < 3)
16692 /* Look for suffixed mnemonic. */
16694 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16695 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16697 if (opcode && cond)
16700 switch (opcode->tag)
16702 case OT_cinfix3_legacy:
16703 /* Ignore conditional suffixes matched on infix only mnemonics. */
16707 case OT_cinfix3_deprecated:
16708 case OT_odd_infix_unc:
16709 if (!unified_syntax)
16711 /* else fall through */
16715 case OT_csuf_or_in3:
16716 inst.cond = cond->value;
16719 case OT_unconditional:
16720 case OT_unconditionalF:
16722 inst.cond = cond->value;
16725 /* Delayed diagnostic. */
16726 inst.error = BAD_COND;
16727 inst.cond = COND_ALWAYS;
16736 /* Cannot have a usual-position infix on a mnemonic of less than
16737 six characters (five would be a suffix). */
16738 if (end - base < 6)
16741 /* Look for infixed mnemonic in the usual position. */
16743 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16747 memcpy (save, affix, 2);
16748 memmove (affix, affix + 2, (end - affix) - 2);
16749 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
16751 memmove (affix + 2, affix, (end - affix) - 2);
16752 memcpy (affix, save, 2);
16755 && (opcode->tag == OT_cinfix3
16756 || opcode->tag == OT_cinfix3_deprecated
16757 || opcode->tag == OT_csuf_or_in3
16758 || opcode->tag == OT_cinfix3_legacy))
16761 if (warn_on_deprecated && unified_syntax
16762 && (opcode->tag == OT_cinfix3
16763 || opcode->tag == OT_cinfix3_deprecated))
16764 as_warn (_("conditional infixes are deprecated in unified syntax"));
16766 inst.cond = cond->value;
16773 /* This function generates an initial IT instruction, leaving its block
16774 virtually open for the new instructions. Eventually,
16775 the mask will be updated by now_it_add_mask () each time
16776 a new instruction needs to be included in the IT block.
16777 Finally, the block is closed with close_automatic_it_block ().
16778 The block closure can be requested either from md_assemble (),
16779 a tencode (), or due to a label hook. */
16782 new_automatic_it_block (int cond)
16784 now_it.state = AUTOMATIC_IT_BLOCK;
16785 now_it.mask = 0x18;
16787 now_it.block_length = 1;
16788 mapping_state (MAP_THUMB);
16789 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16790 now_it.warn_deprecated = FALSE;
16791 now_it.insn_cond = TRUE;
16794 /* Close an automatic IT block.
16795 See comments in new_automatic_it_block (). */
16798 close_automatic_it_block (void)
16800 now_it.mask = 0x10;
16801 now_it.block_length = 0;
16804 /* Update the mask of the current automatically-generated IT
16805 instruction. See comments in new_automatic_it_block (). */
16808 now_it_add_mask (int cond)
16810 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16811 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16812 | ((bitvalue) << (nbit)))
16813 const int resulting_bit = (cond & 1);
16815 now_it.mask &= 0xf;
16816 now_it.mask = SET_BIT_VALUE (now_it.mask,
16818 (5 - now_it.block_length));
16819 now_it.mask = SET_BIT_VALUE (now_it.mask,
16821 ((5 - now_it.block_length) - 1) );
16822 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16825 #undef SET_BIT_VALUE
16828 /* The IT blocks handling machinery is accessed through the these functions:
16829 it_fsm_pre_encode () from md_assemble ()
16830 set_it_insn_type () optional, from the tencode functions
16831 set_it_insn_type_last () ditto
16832 in_it_block () ditto
16833 it_fsm_post_encode () from md_assemble ()
16834 force_automatic_it_block_close () from label habdling functions
16837 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16838 initializing the IT insn type with a generic initial value depending
16839 on the inst.condition.
16840 2) During the tencode function, two things may happen:
16841 a) The tencode function overrides the IT insn type by
16842 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16843 b) The tencode function queries the IT block state by
16844 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16846 Both set_it_insn_type and in_it_block run the internal FSM state
16847 handling function (handle_it_state), because: a) setting the IT insn
16848 type may incur in an invalid state (exiting the function),
16849 and b) querying the state requires the FSM to be updated.
16850 Specifically we want to avoid creating an IT block for conditional
16851 branches, so it_fsm_pre_encode is actually a guess and we can't
16852 determine whether an IT block is required until the tencode () routine
16853 has decided what type of instruction this actually it.
16854 Because of this, if set_it_insn_type and in_it_block have to be used,
16855 set_it_insn_type has to be called first.
16857 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16858 determines the insn IT type depending on the inst.cond code.
16859 When a tencode () routine encodes an instruction that can be
16860 either outside an IT block, or, in the case of being inside, has to be
16861 the last one, set_it_insn_type_last () will determine the proper
16862 IT instruction type based on the inst.cond code. Otherwise,
16863 set_it_insn_type can be called for overriding that logic or
16864 for covering other cases.
16866 Calling handle_it_state () may not transition the IT block state to
16867 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16868 still queried. Instead, if the FSM determines that the state should
16869 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16870 after the tencode () function: that's what it_fsm_post_encode () does.
16872 Since in_it_block () calls the state handling function to get an
16873 updated state, an error may occur (due to invalid insns combination).
16874 In that case, inst.error is set.
16875 Therefore, inst.error has to be checked after the execution of
16876 the tencode () routine.
16878 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16879 any pending state change (if any) that didn't take place in
16880 handle_it_state () as explained above. */
16883 it_fsm_pre_encode (void)
16885 if (inst.cond != COND_ALWAYS)
16886 inst.it_insn_type = INSIDE_IT_INSN;
16888 inst.it_insn_type = OUTSIDE_IT_INSN;
16890 now_it.state_handled = 0;
16893 /* IT state FSM handling function. */
16896 handle_it_state (void)
16898 now_it.state_handled = 1;
16899 now_it.insn_cond = FALSE;
16901 switch (now_it.state)
16903 case OUTSIDE_IT_BLOCK:
16904 switch (inst.it_insn_type)
16906 case OUTSIDE_IT_INSN:
16909 case INSIDE_IT_INSN:
16910 case INSIDE_IT_LAST_INSN:
16911 if (thumb_mode == 0)
16914 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16915 as_tsktsk (_("Warning: conditional outside an IT block"\
16920 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16921 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16923 /* Automatically generate the IT instruction. */
16924 new_automatic_it_block (inst.cond);
16925 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16926 close_automatic_it_block ();
16930 inst.error = BAD_OUT_IT;
16936 case IF_INSIDE_IT_LAST_INSN:
16937 case NEUTRAL_IT_INSN:
16941 now_it.state = MANUAL_IT_BLOCK;
16942 now_it.block_length = 0;
16947 case AUTOMATIC_IT_BLOCK:
16948 /* Three things may happen now:
16949 a) We should increment current it block size;
16950 b) We should close current it block (closing insn or 4 insns);
16951 c) We should close current it block and start a new one (due
16952 to incompatible conditions or
16953 4 insns-length block reached). */
16955 switch (inst.it_insn_type)
16957 case OUTSIDE_IT_INSN:
16958 /* The closure of the block shall happen immediatelly,
16959 so any in_it_block () call reports the block as closed. */
16960 force_automatic_it_block_close ();
16963 case INSIDE_IT_INSN:
16964 case INSIDE_IT_LAST_INSN:
16965 case IF_INSIDE_IT_LAST_INSN:
16966 now_it.block_length++;
16968 if (now_it.block_length > 4
16969 || !now_it_compatible (inst.cond))
16971 force_automatic_it_block_close ();
16972 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16973 new_automatic_it_block (inst.cond);
16977 now_it.insn_cond = TRUE;
16978 now_it_add_mask (inst.cond);
16981 if (now_it.state == AUTOMATIC_IT_BLOCK
16982 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16983 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16984 close_automatic_it_block ();
16987 case NEUTRAL_IT_INSN:
16988 now_it.block_length++;
16989 now_it.insn_cond = TRUE;
16991 if (now_it.block_length > 4)
16992 force_automatic_it_block_close ();
16994 now_it_add_mask (now_it.cc & 1);
16998 close_automatic_it_block ();
16999 now_it.state = MANUAL_IT_BLOCK;
17004 case MANUAL_IT_BLOCK:
17006 /* Check conditional suffixes. */
17007 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17010 now_it.mask &= 0x1f;
17011 is_last = (now_it.mask == 0x10);
17012 now_it.insn_cond = TRUE;
17014 switch (inst.it_insn_type)
17016 case OUTSIDE_IT_INSN:
17017 inst.error = BAD_NOT_IT;
17020 case INSIDE_IT_INSN:
17021 if (cond != inst.cond)
17023 inst.error = BAD_IT_COND;
17028 case INSIDE_IT_LAST_INSN:
17029 case IF_INSIDE_IT_LAST_INSN:
17030 if (cond != inst.cond)
17032 inst.error = BAD_IT_COND;
17037 inst.error = BAD_BRANCH;
17042 case NEUTRAL_IT_INSN:
17043 /* The BKPT instruction is unconditional even in an IT block. */
17047 inst.error = BAD_IT_IT;
17057 struct depr_insn_mask
17059 unsigned long pattern;
17060 unsigned long mask;
17061 const char* description;
17064 /* List of 16-bit instruction patterns deprecated in an IT block in
17066 static const struct depr_insn_mask depr_it_insns[] = {
17067 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17068 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17069 { 0xa000, 0xb800, N_("ADR") },
17070 { 0x4800, 0xf800, N_("Literal loads") },
17071 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17072 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17077 it_fsm_post_encode (void)
17081 if (!now_it.state_handled)
17082 handle_it_state ();
17084 if (now_it.insn_cond
17085 && !now_it.warn_deprecated
17086 && warn_on_deprecated
17087 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17089 if (inst.instruction >= 0x10000)
17091 as_warn (_("it blocks containing wide Thumb instructions are "
17092 "deprecated in ARMv8"));
17093 now_it.warn_deprecated = TRUE;
17097 const struct depr_insn_mask *p = depr_it_insns;
17099 while (p->mask != 0)
17101 if ((inst.instruction & p->mask) == p->pattern)
17103 as_warn (_("it blocks containing 16-bit Thumb intsructions "
17104 "of the following class are deprecated in ARMv8: "
17105 "%s"), p->description);
17106 now_it.warn_deprecated = TRUE;
17114 if (now_it.block_length > 1)
17116 as_warn (_("it blocks of more than one conditional instruction are "
17117 "deprecated in ARMv8"));
17118 now_it.warn_deprecated = TRUE;
17122 is_last = (now_it.mask == 0x10);
17125 now_it.state = OUTSIDE_IT_BLOCK;
17131 force_automatic_it_block_close (void)
17133 if (now_it.state == AUTOMATIC_IT_BLOCK)
17135 close_automatic_it_block ();
17136 now_it.state = OUTSIDE_IT_BLOCK;
17144 if (!now_it.state_handled)
17145 handle_it_state ();
17147 return now_it.state != OUTSIDE_IT_BLOCK;
17151 md_assemble (char *str)
17154 const struct asm_opcode * opcode;
17156 /* Align the previous label if needed. */
17157 if (last_label_seen != NULL)
17159 symbol_set_frag (last_label_seen, frag_now);
17160 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17161 S_SET_SEGMENT (last_label_seen, now_seg);
17164 memset (&inst, '\0', sizeof (inst));
17165 inst.reloc.type = BFD_RELOC_UNUSED;
17167 opcode = opcode_lookup (&p);
17170 /* It wasn't an instruction, but it might be a register alias of
17171 the form alias .req reg, or a Neon .dn/.qn directive. */
17172 if (! create_register_alias (str, p)
17173 && ! create_neon_reg_alias (str, p))
17174 as_bad (_("bad instruction `%s'"), str);
17179 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17180 as_warn (_("s suffix on comparison instruction is deprecated"));
17182 /* The value which unconditional instructions should have in place of the
17183 condition field. */
17184 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17188 arm_feature_set variant;
17190 variant = cpu_variant;
17191 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17192 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17193 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17194 /* Check that this instruction is supported for this CPU. */
17195 if (!opcode->tvariant
17196 || (thumb_mode == 1
17197 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17199 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17202 if (inst.cond != COND_ALWAYS && !unified_syntax
17203 && opcode->tencode != do_t_branch)
17205 as_bad (_("Thumb does not support conditional execution"));
17209 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17211 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17212 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17213 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17215 /* Two things are addressed here.
17216 1) Implicit require narrow instructions on Thumb-1.
17217 This avoids relaxation accidentally introducing Thumb-2
17219 2) Reject wide instructions in non Thumb-2 cores. */
17220 if (inst.size_req == 0)
17222 else if (inst.size_req == 4)
17224 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17230 inst.instruction = opcode->tvalue;
17232 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17234 /* Prepare the it_insn_type for those encodings that don't set
17236 it_fsm_pre_encode ();
17238 opcode->tencode ();
17240 it_fsm_post_encode ();
17243 if (!(inst.error || inst.relax))
17245 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17246 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17247 if (inst.size_req && inst.size_req != inst.size)
17249 as_bad (_("cannot honor width suffix -- `%s'"), str);
17254 /* Something has gone badly wrong if we try to relax a fixed size
17256 gas_assert (inst.size_req == 0 || !inst.relax);
17258 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17259 *opcode->tvariant);
17260 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17261 set those bits when Thumb-2 32-bit instructions are seen. ie.
17262 anything other than bl/blx and v6-M instructions.
17263 This is overly pessimistic for relaxable instructions. */
17264 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17266 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17267 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17268 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17271 check_neon_suffixes;
17275 mapping_state (MAP_THUMB);
17278 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17282 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17283 is_bx = (opcode->aencode == do_bx);
17285 /* Check that this instruction is supported for this CPU. */
17286 if (!(is_bx && fix_v4bx)
17287 && !(opcode->avariant &&
17288 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17290 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17295 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17299 inst.instruction = opcode->avalue;
17300 if (opcode->tag == OT_unconditionalF)
17301 inst.instruction |= 0xF << 28;
17303 inst.instruction |= inst.cond << 28;
17304 inst.size = INSN_SIZE;
17305 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17307 it_fsm_pre_encode ();
17308 opcode->aencode ();
17309 it_fsm_post_encode ();
17311 /* Arm mode bx is marked as both v4T and v5 because it's still required
17312 on a hypothetical non-thumb v5 core. */
17314 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17316 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17317 *opcode->avariant);
17319 check_neon_suffixes;
17323 mapping_state (MAP_ARM);
17328 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17336 check_it_blocks_finished (void)
17341 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17342 if (seg_info (sect)->tc_segment_info_data.current_it.state
17343 == MANUAL_IT_BLOCK)
17345 as_warn (_("section '%s' finished with an open IT block."),
17349 if (now_it.state == MANUAL_IT_BLOCK)
17350 as_warn (_("file finished with an open IT block."));
17354 /* Various frobbings of labels and their addresses. */
17357 arm_start_line_hook (void)
17359 last_label_seen = NULL;
17363 arm_frob_label (symbolS * sym)
17365 last_label_seen = sym;
17367 ARM_SET_THUMB (sym, thumb_mode);
17369 #if defined OBJ_COFF || defined OBJ_ELF
17370 ARM_SET_INTERWORK (sym, support_interwork);
17373 force_automatic_it_block_close ();
17375 /* Note - do not allow local symbols (.Lxxx) to be labelled
17376 as Thumb functions. This is because these labels, whilst
17377 they exist inside Thumb code, are not the entry points for
17378 possible ARM->Thumb calls. Also, these labels can be used
17379 as part of a computed goto or switch statement. eg gcc
17380 can generate code that looks like this:
17382 ldr r2, [pc, .Laaa]
17392 The first instruction loads the address of the jump table.
17393 The second instruction converts a table index into a byte offset.
17394 The third instruction gets the jump address out of the table.
17395 The fourth instruction performs the jump.
17397 If the address stored at .Laaa is that of a symbol which has the
17398 Thumb_Func bit set, then the linker will arrange for this address
17399 to have the bottom bit set, which in turn would mean that the
17400 address computation performed by the third instruction would end
17401 up with the bottom bit set. Since the ARM is capable of unaligned
17402 word loads, the instruction would then load the incorrect address
17403 out of the jump table, and chaos would ensue. */
17404 if (label_is_thumb_function_name
17405 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17406 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
17408 /* When the address of a Thumb function is taken the bottom
17409 bit of that address should be set. This will allow
17410 interworking between Arm and Thumb functions to work
17413 THUMB_SET_FUNC (sym, 1);
17415 label_is_thumb_function_name = FALSE;
17418 dwarf2_emit_label (sym);
17422 arm_data_in_code (void)
17424 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
17426 *input_line_pointer = '/';
17427 input_line_pointer += 5;
17428 *input_line_pointer = 0;
17436 arm_canonicalize_symbol_name (char * name)
17440 if (thumb_mode && (len = strlen (name)) > 5
17441 && streq (name + len - 5, "/data"))
17442 *(name + len - 5) = 0;
17447 /* Table of all register names defined by default. The user can
17448 define additional names with .req. Note that all register names
17449 should appear in both upper and lowercase variants. Some registers
17450 also have mixed-case names. */
17452 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17453 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17454 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17455 #define REGSET(p,t) \
17456 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17457 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17458 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17459 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17460 #define REGSETH(p,t) \
17461 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17462 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17463 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17464 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17465 #define REGSET2(p,t) \
17466 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17467 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17468 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17469 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17470 #define SPLRBANK(base,bank,t) \
17471 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17472 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17473 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17474 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17475 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17476 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17478 static const struct reg_entry reg_names[] =
17480 /* ARM integer registers. */
17481 REGSET(r, RN), REGSET(R, RN),
17483 /* ATPCS synonyms. */
17484 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17485 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17486 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
17488 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17489 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17490 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
17492 /* Well-known aliases. */
17493 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17494 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17496 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17497 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17499 /* Coprocessor numbers. */
17500 REGSET(p, CP), REGSET(P, CP),
17502 /* Coprocessor register numbers. The "cr" variants are for backward
17504 REGSET(c, CN), REGSET(C, CN),
17505 REGSET(cr, CN), REGSET(CR, CN),
17507 /* ARM banked registers. */
17508 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17509 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17510 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17511 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17512 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17513 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17514 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17516 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17517 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17518 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17519 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17520 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
17521 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
17522 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17523 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17525 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17526 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17527 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17528 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17529 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17530 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17531 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
17532 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
17533 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17535 /* FPA registers. */
17536 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17537 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17539 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17540 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17542 /* VFP SP registers. */
17543 REGSET(s,VFS), REGSET(S,VFS),
17544 REGSETH(s,VFS), REGSETH(S,VFS),
17546 /* VFP DP Registers. */
17547 REGSET(d,VFD), REGSET(D,VFD),
17548 /* Extra Neon DP registers. */
17549 REGSETH(d,VFD), REGSETH(D,VFD),
17551 /* Neon QP registers. */
17552 REGSET2(q,NQ), REGSET2(Q,NQ),
17554 /* VFP control registers. */
17555 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17556 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
17557 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17558 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17559 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17560 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
17562 /* Maverick DSP coprocessor registers. */
17563 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17564 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17566 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17567 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17568 REGDEF(dspsc,0,DSPSC),
17570 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17571 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17572 REGDEF(DSPSC,0,DSPSC),
17574 /* iWMMXt data registers - p0, c0-15. */
17575 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17577 /* iWMMXt control registers - p1, c0-3. */
17578 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17579 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17580 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17581 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17583 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17584 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17585 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17586 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17587 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17589 /* XScale accumulator registers. */
17590 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17596 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17597 within psr_required_here. */
17598 static const struct asm_psr psrs[] =
17600 /* Backward compatibility notation. Note that "all" is no longer
17601 truly all possible PSR bits. */
17602 {"all", PSR_c | PSR_f},
17606 /* Individual flags. */
17612 /* Combinations of flags. */
17613 {"fs", PSR_f | PSR_s},
17614 {"fx", PSR_f | PSR_x},
17615 {"fc", PSR_f | PSR_c},
17616 {"sf", PSR_s | PSR_f},
17617 {"sx", PSR_s | PSR_x},
17618 {"sc", PSR_s | PSR_c},
17619 {"xf", PSR_x | PSR_f},
17620 {"xs", PSR_x | PSR_s},
17621 {"xc", PSR_x | PSR_c},
17622 {"cf", PSR_c | PSR_f},
17623 {"cs", PSR_c | PSR_s},
17624 {"cx", PSR_c | PSR_x},
17625 {"fsx", PSR_f | PSR_s | PSR_x},
17626 {"fsc", PSR_f | PSR_s | PSR_c},
17627 {"fxs", PSR_f | PSR_x | PSR_s},
17628 {"fxc", PSR_f | PSR_x | PSR_c},
17629 {"fcs", PSR_f | PSR_c | PSR_s},
17630 {"fcx", PSR_f | PSR_c | PSR_x},
17631 {"sfx", PSR_s | PSR_f | PSR_x},
17632 {"sfc", PSR_s | PSR_f | PSR_c},
17633 {"sxf", PSR_s | PSR_x | PSR_f},
17634 {"sxc", PSR_s | PSR_x | PSR_c},
17635 {"scf", PSR_s | PSR_c | PSR_f},
17636 {"scx", PSR_s | PSR_c | PSR_x},
17637 {"xfs", PSR_x | PSR_f | PSR_s},
17638 {"xfc", PSR_x | PSR_f | PSR_c},
17639 {"xsf", PSR_x | PSR_s | PSR_f},
17640 {"xsc", PSR_x | PSR_s | PSR_c},
17641 {"xcf", PSR_x | PSR_c | PSR_f},
17642 {"xcs", PSR_x | PSR_c | PSR_s},
17643 {"cfs", PSR_c | PSR_f | PSR_s},
17644 {"cfx", PSR_c | PSR_f | PSR_x},
17645 {"csf", PSR_c | PSR_s | PSR_f},
17646 {"csx", PSR_c | PSR_s | PSR_x},
17647 {"cxf", PSR_c | PSR_x | PSR_f},
17648 {"cxs", PSR_c | PSR_x | PSR_s},
17649 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17650 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17651 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17652 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17653 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17654 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17655 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17656 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17657 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17658 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17659 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17660 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17661 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17662 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17663 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17664 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17665 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17666 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17667 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17668 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17669 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17670 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17671 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17672 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17675 /* Table of V7M psr names. */
17676 static const struct asm_psr v7m_psrs[] =
17678 {"apsr", 0 }, {"APSR", 0 },
17679 {"iapsr", 1 }, {"IAPSR", 1 },
17680 {"eapsr", 2 }, {"EAPSR", 2 },
17681 {"psr", 3 }, {"PSR", 3 },
17682 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17683 {"ipsr", 5 }, {"IPSR", 5 },
17684 {"epsr", 6 }, {"EPSR", 6 },
17685 {"iepsr", 7 }, {"IEPSR", 7 },
17686 {"msp", 8 }, {"MSP", 8 },
17687 {"psp", 9 }, {"PSP", 9 },
17688 {"primask", 16}, {"PRIMASK", 16},
17689 {"basepri", 17}, {"BASEPRI", 17},
17690 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17691 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17692 {"faultmask", 19}, {"FAULTMASK", 19},
17693 {"control", 20}, {"CONTROL", 20}
17696 /* Table of all shift-in-operand names. */
17697 static const struct asm_shift_name shift_names [] =
17699 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17700 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17701 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17702 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17703 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17704 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17707 /* Table of all explicit relocation names. */
17709 static struct reloc_entry reloc_names[] =
17711 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17712 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17713 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17714 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17715 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17716 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17717 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17718 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17719 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17720 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
17721 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
17722 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17723 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
17724 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
17725 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
17726 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
17727 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
17728 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
17732 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17733 static const struct asm_cond conds[] =
17737 {"cs", 0x2}, {"hs", 0x2},
17738 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17752 #define UL_BARRIER(L,U,CODE,FEAT) \
17753 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17754 { U, CODE, ARM_FEATURE (FEAT, 0) }
17756 static struct asm_barrier_opt barrier_opt_names[] =
17758 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17759 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17760 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17761 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17762 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17763 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17764 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17765 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17766 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17767 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17768 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17769 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17770 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17771 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17772 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17773 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
17778 /* Table of ARM-format instructions. */
17780 /* Macros for gluing together operand strings. N.B. In all cases
17781 other than OPS0, the trailing OP_stop comes from default
17782 zero-initialization of the unspecified elements of the array. */
17783 #define OPS0() { OP_stop, }
17784 #define OPS1(a) { OP_##a, }
17785 #define OPS2(a,b) { OP_##a,OP_##b, }
17786 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17787 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17788 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17789 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17791 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17792 This is useful when mixing operands for ARM and THUMB, i.e. using the
17793 MIX_ARM_THUMB_OPERANDS macro.
17794 In order to use these macros, prefix the number of operands with _
17796 #define OPS_1(a) { a, }
17797 #define OPS_2(a,b) { a,b, }
17798 #define OPS_3(a,b,c) { a,b,c, }
17799 #define OPS_4(a,b,c,d) { a,b,c,d, }
17800 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17801 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17803 /* These macros abstract out the exact format of the mnemonic table and
17804 save some repeated characters. */
17806 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17807 #define TxCE(mnem, op, top, nops, ops, ae, te) \
17808 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
17809 THUMB_VARIANT, do_##ae, do_##te }
17811 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17812 a T_MNEM_xyz enumerator. */
17813 #define TCE(mnem, aop, top, nops, ops, ae, te) \
17814 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
17815 #define tCE(mnem, aop, top, nops, ops, ae, te) \
17816 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17818 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17819 infix after the third character. */
17820 #define TxC3(mnem, op, top, nops, ops, ae, te) \
17821 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
17822 THUMB_VARIANT, do_##ae, do_##te }
17823 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
17824 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
17825 THUMB_VARIANT, do_##ae, do_##te }
17826 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17827 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17828 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17829 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17830 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17831 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17832 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17833 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17835 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17836 field is still 0xE. Many of the Thumb variants can be executed
17837 conditionally, so this is checked separately. */
17838 #define TUE(mnem, op, top, nops, ops, ae, te) \
17839 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17840 THUMB_VARIANT, do_##ae, do_##te }
17842 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17843 Used by mnemonics that have very minimal differences in the encoding for
17844 ARM and Thumb variants and can be handled in a common function. */
17845 #define TUEc(mnem, op, top, nops, ops, en) \
17846 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17847 THUMB_VARIANT, do_##en, do_##en }
17849 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17850 condition code field. */
17851 #define TUF(mnem, op, top, nops, ops, ae, te) \
17852 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17853 THUMB_VARIANT, do_##ae, do_##te }
17855 /* ARM-only variants of all the above. */
17856 #define CE(mnem, op, nops, ops, ae) \
17857 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17859 #define C3(mnem, op, nops, ops, ae) \
17860 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17862 /* Legacy mnemonics that always have conditional infix after the third
17864 #define CL(mnem, op, nops, ops, ae) \
17865 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17866 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17868 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17869 #define cCE(mnem, op, nops, ops, ae) \
17870 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17872 /* Legacy coprocessor instructions where conditional infix and conditional
17873 suffix are ambiguous. For consistency this includes all FPA instructions,
17874 not just the potentially ambiguous ones. */
17875 #define cCL(mnem, op, nops, ops, ae) \
17876 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17877 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17879 /* Coprocessor, takes either a suffix or a position-3 infix
17880 (for an FPA corner case). */
17881 #define C3E(mnem, op, nops, ops, ae) \
17882 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17883 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17885 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17886 { m1 #m2 m3, OPS##nops ops, \
17887 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17888 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17890 #define CM(m1, m2, op, nops, ops, ae) \
17891 xCM_ (m1, , m2, op, nops, ops, ae), \
17892 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17893 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17894 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17895 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17896 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17897 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17898 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17899 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17900 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17901 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17902 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17903 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17904 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17905 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17906 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17907 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17908 xCM_ (m1, le, m2, op, nops, ops, ae), \
17909 xCM_ (m1, al, m2, op, nops, ops, ae)
17911 #define UE(mnem, op, nops, ops, ae) \
17912 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17914 #define UF(mnem, op, nops, ops, ae) \
17915 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17917 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17918 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17919 use the same encoding function for each. */
17920 #define NUF(mnem, op, nops, ops, enc) \
17921 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17922 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17924 /* Neon data processing, version which indirects through neon_enc_tab for
17925 the various overloaded versions of opcodes. */
17926 #define nUF(mnem, op, nops, ops, enc) \
17927 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17928 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17930 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17932 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17933 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17934 THUMB_VARIANT, do_##enc, do_##enc }
17936 #define NCE(mnem, op, nops, ops, enc) \
17937 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17939 #define NCEF(mnem, op, nops, ops, enc) \
17940 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17942 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17943 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17944 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17945 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17947 #define nCE(mnem, op, nops, ops, enc) \
17948 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17950 #define nCEF(mnem, op, nops, ops, enc) \
17951 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17955 static const struct asm_opcode insns[] =
17957 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17958 #define THUMB_VARIANT &arm_ext_v4t
17959 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17960 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17961 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17962 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17963 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17964 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17965 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17966 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17967 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17968 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17969 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17970 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17971 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17972 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17973 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17974 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17976 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17977 for setting PSR flag bits. They are obsolete in V6 and do not
17978 have Thumb equivalents. */
17979 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17980 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17981 CL("tstp", 110f000, 2, (RR, SH), cmp),
17982 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17983 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17984 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17985 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17986 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17987 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17989 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17990 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17991 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17992 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17994 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17995 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17996 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17998 OP_ADDRGLDR),ldst, t_ldst),
17999 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18001 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18002 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18003 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18004 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18005 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18006 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18008 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18009 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18010 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18011 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18014 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18015 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18016 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18018 /* Thumb-compatibility pseudo ops. */
18019 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18020 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18021 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18022 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18023 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18024 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18025 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18026 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18027 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18028 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18029 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18030 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18032 /* These may simplify to neg. */
18033 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18034 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18036 #undef THUMB_VARIANT
18037 #define THUMB_VARIANT & arm_ext_v6
18039 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18041 /* V1 instructions with no Thumb analogue prior to V6T2. */
18042 #undef THUMB_VARIANT
18043 #define THUMB_VARIANT & arm_ext_v6t2
18045 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18046 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18047 CL("teqp", 130f000, 2, (RR, SH), cmp),
18049 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18050 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18051 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18052 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18054 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18055 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18057 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18058 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18060 /* V1 instructions with no Thumb analogue at all. */
18061 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18062 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18064 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18065 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18066 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18067 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18068 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18069 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18070 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18071 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18074 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18075 #undef THUMB_VARIANT
18076 #define THUMB_VARIANT & arm_ext_v4t
18078 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18079 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18081 #undef THUMB_VARIANT
18082 #define THUMB_VARIANT & arm_ext_v6t2
18084 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18085 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18087 /* Generic coprocessor instructions. */
18088 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18089 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18090 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18091 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18092 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18093 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18094 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18097 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18099 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18100 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18103 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18104 #undef THUMB_VARIANT
18105 #define THUMB_VARIANT & arm_ext_msr
18107 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18108 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18111 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18112 #undef THUMB_VARIANT
18113 #define THUMB_VARIANT & arm_ext_v6t2
18115 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18116 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18117 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18118 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18119 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18120 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18121 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18122 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18125 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18126 #undef THUMB_VARIANT
18127 #define THUMB_VARIANT & arm_ext_v4t
18129 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18130 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18131 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18132 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18133 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18134 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18137 #define ARM_VARIANT & arm_ext_v4t_5
18139 /* ARM Architecture 4T. */
18140 /* Note: bx (and blx) are required on V5, even if the processor does
18141 not support Thumb. */
18142 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18145 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18146 #undef THUMB_VARIANT
18147 #define THUMB_VARIANT & arm_ext_v5t
18149 /* Note: blx has 2 variants; the .value coded here is for
18150 BLX(2). Only this variant has conditional execution. */
18151 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18152 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18154 #undef THUMB_VARIANT
18155 #define THUMB_VARIANT & arm_ext_v6t2
18157 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18158 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18159 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18160 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18161 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18162 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18163 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18164 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18167 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18168 #undef THUMB_VARIANT
18169 #define THUMB_VARIANT &arm_ext_v5exp
18171 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18172 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18173 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18174 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18176 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18177 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18179 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18180 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18181 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18182 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18184 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18185 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18186 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18187 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18189 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18190 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18192 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18193 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18194 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18195 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18198 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18199 #undef THUMB_VARIANT
18200 #define THUMB_VARIANT &arm_ext_v6t2
18202 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18203 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18205 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18206 ADDRGLDRS), ldrd, t_ldstd),
18208 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18209 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18212 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18214 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18217 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18218 #undef THUMB_VARIANT
18219 #define THUMB_VARIANT & arm_ext_v6
18221 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18222 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18223 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18224 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18225 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18226 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18227 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18228 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18229 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18230 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18232 #undef THUMB_VARIANT
18233 #define THUMB_VARIANT & arm_ext_v6t2
18235 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18236 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18238 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18239 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18241 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18242 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18244 /* ARM V6 not included in V7M. */
18245 #undef THUMB_VARIANT
18246 #define THUMB_VARIANT & arm_ext_v6_notm
18247 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18248 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18249 UF(rfeib, 9900a00, 1, (RRw), rfe),
18250 UF(rfeda, 8100a00, 1, (RRw), rfe),
18251 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18252 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18253 UF(rfefa, 8100a00, 1, (RRw), rfe),
18254 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18255 UF(rfeed, 9900a00, 1, (RRw), rfe),
18256 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18257 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18258 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18259 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18260 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18261 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18262 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18263 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18264 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18266 /* ARM V6 not included in V7M (eg. integer SIMD). */
18267 #undef THUMB_VARIANT
18268 #define THUMB_VARIANT & arm_ext_v6_dsp
18269 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18270 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18271 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18272 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18273 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18274 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18275 /* Old name for QASX. */
18276 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18277 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18278 /* Old name for QSAX. */
18279 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18280 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18281 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18282 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18283 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18284 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18285 /* Old name for SASX. */
18286 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18287 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18288 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18289 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18290 /* Old name for SHASX. */
18291 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18292 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18293 /* Old name for SHSAX. */
18294 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18295 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18296 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18297 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18298 /* Old name for SSAX. */
18299 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18300 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18301 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18302 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18303 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18304 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18305 /* Old name for UASX. */
18306 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18307 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18308 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18309 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18310 /* Old name for UHASX. */
18311 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18312 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18313 /* Old name for UHSAX. */
18314 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18315 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18316 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18317 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18318 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18320 /* Old name for UQASX. */
18321 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 /* Old name for UQSAX. */
18324 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18326 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18327 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18328 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 /* Old name for USAX. */
18330 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18331 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18333 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18334 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18335 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18336 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18337 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18338 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18339 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18340 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18341 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18342 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18343 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18344 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18345 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18346 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18347 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18348 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18349 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18350 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18351 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18352 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18353 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18354 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18355 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18356 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18357 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18358 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18359 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18360 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18361 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18362 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18363 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18366 #define ARM_VARIANT & arm_ext_v6k
18367 #undef THUMB_VARIANT
18368 #define THUMB_VARIANT & arm_ext_v6k
18370 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18371 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18372 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18373 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18375 #undef THUMB_VARIANT
18376 #define THUMB_VARIANT & arm_ext_v6_notm
18377 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18379 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18380 RRnpcb), strexd, t_strexd),
18382 #undef THUMB_VARIANT
18383 #define THUMB_VARIANT & arm_ext_v6t2
18384 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18386 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18388 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18390 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18392 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18395 #define ARM_VARIANT & arm_ext_sec
18396 #undef THUMB_VARIANT
18397 #define THUMB_VARIANT & arm_ext_sec
18399 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
18402 #define ARM_VARIANT & arm_ext_virt
18403 #undef THUMB_VARIANT
18404 #define THUMB_VARIANT & arm_ext_virt
18406 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18407 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18410 #define ARM_VARIANT & arm_ext_v6t2
18411 #undef THUMB_VARIANT
18412 #define THUMB_VARIANT & arm_ext_v6t2
18414 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18415 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18416 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18417 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18419 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18420 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18421 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18422 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
18424 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18425 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18426 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18427 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18429 /* Thumb-only instructions. */
18431 #define ARM_VARIANT NULL
18432 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18433 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
18435 /* ARM does not really have an IT instruction, so always allow it.
18436 The opcode is copied from Thumb in order to allow warnings in
18437 -mimplicit-it=[never | arm] modes. */
18439 #define ARM_VARIANT & arm_ext_v1
18441 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18442 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18443 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18444 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18445 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18446 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18447 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18448 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18449 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18450 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18451 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18452 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18453 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18454 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18455 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
18456 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18457 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18458 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
18460 /* Thumb2 only instructions. */
18462 #define ARM_VARIANT NULL
18464 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18465 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18466 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18467 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18468 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18469 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
18471 /* Hardware division instructions. */
18473 #define ARM_VARIANT & arm_ext_adiv
18474 #undef THUMB_VARIANT
18475 #define THUMB_VARIANT & arm_ext_div
18477 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18478 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
18480 /* ARM V6M/V7 instructions. */
18482 #define ARM_VARIANT & arm_ext_barrier
18483 #undef THUMB_VARIANT
18484 #define THUMB_VARIANT & arm_ext_barrier
18486 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18487 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18488 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
18490 /* ARM V7 instructions. */
18492 #define ARM_VARIANT & arm_ext_v7
18493 #undef THUMB_VARIANT
18494 #define THUMB_VARIANT & arm_ext_v7
18496 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18497 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
18500 #define ARM_VARIANT & arm_ext_mp
18501 #undef THUMB_VARIANT
18502 #define THUMB_VARIANT & arm_ext_mp
18504 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18506 /* AArchv8 instructions. */
18508 #define ARM_VARIANT & arm_ext_v8
18509 #undef THUMB_VARIANT
18510 #define THUMB_VARIANT & arm_ext_v8
18512 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
18513 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
18514 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18515 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
18517 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18518 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18519 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18521 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
18523 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18525 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18527 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18528 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18529 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18530 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18531 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18532 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18534 /* ARMv8 T32 only. */
18536 #define ARM_VARIANT NULL
18537 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18538 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18539 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18541 /* FP for ARMv8. */
18543 #define ARM_VARIANT & fpu_vfp_ext_armv8
18544 #undef THUMB_VARIANT
18545 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18547 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18548 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18549 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18550 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
18551 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18552 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18553 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18554 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18555 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18556 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
18557 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18558 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18559 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18560 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18561 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18562 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18563 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
18565 /* Crypto v1 extensions. */
18567 #define ARM_VARIANT & fpu_crypto_ext_armv8
18568 #undef THUMB_VARIANT
18569 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18571 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18572 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18573 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18574 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
18575 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18576 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18577 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18578 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18579 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18580 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18581 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
18582 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18583 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18584 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
18587 #define ARM_VARIANT & crc_ext_armv8
18588 #undef THUMB_VARIANT
18589 #define THUMB_VARIANT & crc_ext_armv8
18590 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18591 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18592 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18593 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18594 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18595 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18598 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18599 #undef THUMB_VARIANT
18600 #define THUMB_VARIANT NULL
18602 cCE("wfs", e200110, 1, (RR), rd),
18603 cCE("rfs", e300110, 1, (RR), rd),
18604 cCE("wfc", e400110, 1, (RR), rd),
18605 cCE("rfc", e500110, 1, (RR), rd),
18607 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18608 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18609 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18610 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18612 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18613 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18614 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18615 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18617 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18618 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18619 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18620 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18621 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18622 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18623 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18624 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18625 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18626 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18627 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18628 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18630 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18631 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18632 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18633 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18634 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18635 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18636 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18637 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18638 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18639 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18640 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18641 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18643 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18644 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18645 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18646 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18647 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18648 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18649 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18650 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18651 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18652 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18653 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18654 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18656 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18657 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18658 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18659 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18660 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18661 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18662 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18663 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18664 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18665 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18666 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18667 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18669 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18670 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18671 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18672 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18673 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18674 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18675 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18676 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18677 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18678 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18679 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18680 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18682 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18683 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18684 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18685 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18686 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18687 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18688 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18689 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18690 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18691 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18692 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18693 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18695 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18696 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18697 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18698 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18699 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18700 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18701 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18702 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18703 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18704 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18705 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18706 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18708 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18709 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18710 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18711 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18712 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18713 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18714 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18715 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18716 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18717 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18718 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18719 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18721 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18722 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18723 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18724 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18725 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18726 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18727 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18728 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18729 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18730 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18731 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18732 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18734 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18735 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18736 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18737 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18738 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18739 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18740 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18741 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18742 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18743 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18744 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18745 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18747 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18748 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18749 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18750 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18751 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18752 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18753 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18754 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18755 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18756 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18757 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18758 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18760 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18761 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18762 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18763 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18764 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18765 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18766 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18767 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18768 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18769 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18770 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18771 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18773 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18774 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18775 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18776 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18777 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18778 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18779 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18780 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18781 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18782 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18783 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18784 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18786 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18787 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18788 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18789 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18790 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18791 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18792 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18793 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18794 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18795 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18796 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18797 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18799 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18800 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18801 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18802 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18803 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18804 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18805 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18806 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18807 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18808 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18809 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18810 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18812 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18813 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18814 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18815 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18816 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18817 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18818 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18819 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18820 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18821 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18822 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18823 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18825 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18826 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18827 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18828 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18829 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18830 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18831 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18832 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18833 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18834 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18835 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18836 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18838 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18839 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18840 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18841 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18842 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18843 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18844 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18845 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18846 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18847 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18848 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18849 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18851 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18852 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18857 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18858 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18859 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18864 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18865 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18870 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18871 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18883 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18884 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18896 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18897 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18909 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18910 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18922 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18923 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18935 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18936 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18943 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18948 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18949 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18956 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18961 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18962 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18969 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18974 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18975 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18982 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18987 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18988 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18995 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18996 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18997 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18999 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19000 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19001 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19002 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19003 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19004 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19005 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19006 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19007 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19008 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19009 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19010 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19012 /* The implementation of the FIX instruction is broken on some
19013 assemblers, in that it accepts a precision specifier as well as a
19014 rounding specifier, despite the fact that this is meaningless.
19015 To be more compatible, we accept it as well, though of course it
19016 does not set any bits. */
19017 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19018 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19019 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19020 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19021 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19022 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19023 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19024 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19025 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19026 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19027 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19028 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19029 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19031 /* Instructions that were new with the real FPA, call them V2. */
19033 #define ARM_VARIANT & fpu_fpa_ext_v2
19035 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19036 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19037 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19038 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19039 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19040 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19043 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19045 /* Moves and type conversions. */
19046 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19047 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19048 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19049 cCE("fmstat", ef1fa10, 0, (), noargs),
19050 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19051 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19052 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19053 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19054 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19055 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19056 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19057 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19058 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19059 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19061 /* Memory operations. */
19062 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19063 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19064 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19065 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19066 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19067 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19068 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19069 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19070 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19071 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19072 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19073 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19074 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19075 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19076 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19077 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19078 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19079 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19081 /* Monadic operations. */
19082 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19083 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19084 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19086 /* Dyadic operations. */
19087 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19088 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19089 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19090 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19091 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19092 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19093 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19094 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19095 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19098 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19099 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19100 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19101 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19103 /* Double precision load/store are still present on single precision
19104 implementations. */
19105 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19106 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19107 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19108 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19109 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19110 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19111 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19112 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19113 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19114 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19117 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19119 /* Moves and type conversions. */
19120 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19121 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19122 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19123 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19124 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19125 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19126 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19127 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19128 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19129 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19130 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19131 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19132 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19134 /* Monadic operations. */
19135 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19136 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19137 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19139 /* Dyadic operations. */
19140 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19141 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19142 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19143 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19144 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19145 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19146 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19147 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19148 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19151 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19152 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19153 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19154 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19157 #define ARM_VARIANT & fpu_vfp_ext_v2
19159 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19160 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19161 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19162 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19164 /* Instructions which may belong to either the Neon or VFP instruction sets.
19165 Individual encoder functions perform additional architecture checks. */
19167 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19168 #undef THUMB_VARIANT
19169 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19171 /* These mnemonics are unique to VFP. */
19172 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19173 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19174 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19175 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19176 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19177 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19178 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19179 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19180 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19181 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19183 /* Mnemonics shared by Neon and VFP. */
19184 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19185 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19186 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19188 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19189 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19191 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19192 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19194 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19195 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19196 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19197 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19198 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19199 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19200 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19201 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19203 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19204 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19205 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19206 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19209 /* NOTE: All VMOV encoding is special-cased! */
19210 NCE(vmov, 0, 1, (VMOV), neon_mov),
19211 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19213 #undef THUMB_VARIANT
19214 #define THUMB_VARIANT & fpu_neon_ext_v1
19216 #define ARM_VARIANT & fpu_neon_ext_v1
19218 /* Data processing with three registers of the same length. */
19219 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19220 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19221 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19222 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19223 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19224 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19225 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19226 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19227 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19228 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19229 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19230 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19231 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19232 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19233 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19234 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19235 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19236 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19237 /* If not immediate, fall back to neon_dyadic_i64_su.
19238 shl_imm should accept I8 I16 I32 I64,
19239 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19240 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19241 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19242 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19243 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19244 /* Logic ops, types optional & ignored. */
19245 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19246 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19247 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19248 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19249 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19250 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19251 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19252 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19253 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19254 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19255 /* Bitfield ops, untyped. */
19256 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19257 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19258 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19259 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19260 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19261 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19262 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19263 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19264 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19265 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19266 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19267 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19268 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19269 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19270 back to neon_dyadic_if_su. */
19271 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19272 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19273 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19274 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19275 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19276 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19277 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19278 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19279 /* Comparison. Type I8 I16 I32 F32. */
19280 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19281 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19282 /* As above, D registers only. */
19283 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19284 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19285 /* Int and float variants, signedness unimportant. */
19286 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19287 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19288 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19289 /* Add/sub take types I8 I16 I32 I64 F32. */
19290 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19291 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19292 /* vtst takes sizes 8, 16, 32. */
19293 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19294 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19295 /* VMUL takes I8 I16 I32 F32 P8. */
19296 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19297 /* VQD{R}MULH takes S16 S32. */
19298 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19299 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19300 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19301 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19302 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19303 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19304 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19305 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19306 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19307 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19308 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19309 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19310 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19311 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19312 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19313 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19315 /* Two address, int/float. Types S8 S16 S32 F32. */
19316 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19317 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19319 /* Data processing with two registers and a shift amount. */
19320 /* Right shifts, and variants with rounding.
19321 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19322 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19323 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19324 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19325 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19326 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19327 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19328 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19329 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19330 /* Shift and insert. Sizes accepted 8 16 32 64. */
19331 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19332 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19333 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19334 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19335 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19336 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19337 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19338 /* Right shift immediate, saturating & narrowing, with rounding variants.
19339 Types accepted S16 S32 S64 U16 U32 U64. */
19340 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19341 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19342 /* As above, unsigned. Types accepted S16 S32 S64. */
19343 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19344 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19345 /* Right shift narrowing. Types accepted I16 I32 I64. */
19346 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19347 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19348 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19349 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19350 /* CVT with optional immediate for fixed-point variant. */
19351 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19353 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19354 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19356 /* Data processing, three registers of different lengths. */
19357 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19358 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19359 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19360 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19361 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19362 /* If not scalar, fall back to neon_dyadic_long.
19363 Vector types as above, scalar types S16 S32 U16 U32. */
19364 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19365 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19366 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19367 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19368 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19369 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19370 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19371 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19372 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19373 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19374 /* Saturating doubling multiplies. Types S16 S32. */
19375 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19376 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19377 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19378 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19379 S16 S32 U16 U32. */
19380 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19382 /* Extract. Size 8. */
19383 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19384 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
19386 /* Two registers, miscellaneous. */
19387 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19388 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19389 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19390 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19391 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19392 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19393 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19394 /* Vector replicate. Sizes 8 16 32. */
19395 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19396 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
19397 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19398 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19399 /* VMOVN. Types I16 I32 I64. */
19400 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
19401 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19402 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
19403 /* VQMOVUN. Types S16 S32 S64. */
19404 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
19405 /* VZIP / VUZP. Sizes 8 16 32. */
19406 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19407 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19408 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19409 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19410 /* VQABS / VQNEG. Types S8 S16 S32. */
19411 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19412 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19413 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19414 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19415 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19416 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19417 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19418 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19419 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19420 /* Reciprocal estimates. Types U32 F32. */
19421 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19422 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19423 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19424 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19425 /* VCLS. Types S8 S16 S32. */
19426 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19427 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19428 /* VCLZ. Types I8 I16 I32. */
19429 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19430 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19431 /* VCNT. Size 8. */
19432 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19433 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19434 /* Two address, untyped. */
19435 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19436 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19437 /* VTRN. Sizes 8 16 32. */
19438 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19439 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
19441 /* Table lookup. Size 8. */
19442 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19443 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19445 #undef THUMB_VARIANT
19446 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19448 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19450 /* Neon element/structure load/store. */
19451 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19452 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19453 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19454 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19455 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19456 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19457 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19458 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19460 #undef THUMB_VARIANT
19461 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
19463 #define ARM_VARIANT &fpu_vfp_ext_v3xd
19464 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19465 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19466 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19467 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19468 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19469 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19470 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19471 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19472 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19474 #undef THUMB_VARIANT
19475 #define THUMB_VARIANT & fpu_vfp_ext_v3
19477 #define ARM_VARIANT & fpu_vfp_ext_v3
19479 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
19480 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19481 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19482 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19483 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19484 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19485 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19486 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
19487 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
19490 #define ARM_VARIANT &fpu_vfp_ext_fma
19491 #undef THUMB_VARIANT
19492 #define THUMB_VARIANT &fpu_vfp_ext_fma
19493 /* Mnemonics shared by Neon and VFP. These are included in the
19494 VFP FMA variant; NEON and VFP FMA always includes the NEON
19495 FMA instructions. */
19496 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19497 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19498 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19499 the v form should always be used. */
19500 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19501 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19502 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19503 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19504 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19505 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19507 #undef THUMB_VARIANT
19509 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19511 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19512 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19513 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19514 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19515 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19516 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19517 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19518 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
19521 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19523 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19524 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19525 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19526 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19527 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19528 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19529 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19530 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19531 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19532 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19533 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19534 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19535 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19536 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19537 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19538 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19539 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19540 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19541 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19542 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19543 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19544 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19545 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19546 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19547 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19548 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19549 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19550 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19551 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19552 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19553 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19554 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19555 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19556 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19557 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19558 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19559 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19560 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19561 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19562 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19563 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19564 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19565 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19566 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19567 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19568 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19569 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19570 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19571 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19572 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19573 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19574 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19575 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19576 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19577 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19578 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19579 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19580 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19581 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19582 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19583 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19584 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19585 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19586 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19587 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19588 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19589 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19590 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19591 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19592 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19593 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19597 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19598 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19599 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19600 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19601 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19602 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19605 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19606 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19607 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19611 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19612 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19619 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19624 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19625 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19626 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19627 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19628 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19629 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19631 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19632 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19633 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19634 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19635 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19636 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19637 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19638 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19639 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19640 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19641 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19642 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19643 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19644 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19645 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19646 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19647 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19648 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19649 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19650 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19651 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19652 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19653 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19654 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19655 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19656 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19657 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19658 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19659 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19660 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19661 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19662 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19663 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19666 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19667 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19668 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19669 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19670 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19671 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19673 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19674 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19675 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19676 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19677 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19678 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19679 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19680 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19681 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19682 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19683 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19684 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
19687 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19689 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19690 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19691 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19692 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19693 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19694 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19695 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19696 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19697 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19698 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19699 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19700 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19701 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19702 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19703 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19704 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19705 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19706 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19707 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19708 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19709 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19710 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19711 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19712 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19713 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19714 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19715 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19716 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19717 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19718 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19719 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19720 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19721 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19722 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19723 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19725 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19727 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19728 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19729 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19730 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19731 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19732 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19733 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19734 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19735 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19736 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19737 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19738 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19739 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19740 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19750 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19751 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19752 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19753 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19754 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19755 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19756 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19757 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19758 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19759 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19760 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19761 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19762 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19763 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19764 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19765 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19766 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19767 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19768 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19769 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19770 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19771 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19772 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19773 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19774 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19775 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19776 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19777 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19778 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19779 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19780 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19781 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19782 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19783 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19784 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19785 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19786 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19787 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19788 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19789 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19790 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19791 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19792 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19793 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19794 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19795 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19796 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19797 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19798 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19799 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19800 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19801 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19802 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19803 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19804 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19805 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19806 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19807 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19808 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19809 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19810 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19811 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19812 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19813 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19814 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19815 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19816 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19817 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19818 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19819 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19820 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19821 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19822 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19823 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19824 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19825 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19828 #undef THUMB_VARIANT
19854 /* MD interface: bits in the object file. */
19856 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19857 for use in the a.out file, and stores them in the array pointed to by buf.
19858 This knows about the endian-ness of the target machine and does
19859 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19860 2 (short) and 4 (long) Floating numbers are put out as a series of
19861 LITTLENUMS (shorts, here at least). */
19864 md_number_to_chars (char * buf, valueT val, int n)
19866 if (target_big_endian)
19867 number_to_chars_bigendian (buf, val, n);
19869 number_to_chars_littleendian (buf, val, n);
19873 md_chars_to_number (char * buf, int n)
19876 unsigned char * where = (unsigned char *) buf;
19878 if (target_big_endian)
19883 result |= (*where++ & 255);
19891 result |= (where[n] & 255);
19898 /* MD interface: Sections. */
19900 /* Calculate the maximum variable size (i.e., excluding fr_fix)
19901 that an rs_machine_dependent frag may reach. */
19904 arm_frag_max_var (fragS *fragp)
19906 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19907 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19909 Note that we generate relaxable instructions even for cases that don't
19910 really need it, like an immediate that's a trivial constant. So we're
19911 overestimating the instruction size for some of those cases. Rather
19912 than putting more intelligence here, it would probably be better to
19913 avoid generating a relaxation frag in the first place when it can be
19914 determined up front that a short instruction will suffice. */
19916 gas_assert (fragp->fr_type == rs_machine_dependent);
19920 /* Estimate the size of a frag before relaxing. Assume everything fits in
19924 md_estimate_size_before_relax (fragS * fragp,
19925 segT segtype ATTRIBUTE_UNUSED)
19931 /* Convert a machine dependent frag. */
19934 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19936 unsigned long insn;
19937 unsigned long old_op;
19945 buf = fragp->fr_literal + fragp->fr_fix;
19947 old_op = bfd_get_16(abfd, buf);
19948 if (fragp->fr_symbol)
19950 exp.X_op = O_symbol;
19951 exp.X_add_symbol = fragp->fr_symbol;
19955 exp.X_op = O_constant;
19957 exp.X_add_number = fragp->fr_offset;
19958 opcode = fragp->fr_subtype;
19961 case T_MNEM_ldr_pc:
19962 case T_MNEM_ldr_pc2:
19963 case T_MNEM_ldr_sp:
19964 case T_MNEM_str_sp:
19971 if (fragp->fr_var == 4)
19973 insn = THUMB_OP32 (opcode);
19974 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19976 insn |= (old_op & 0x700) << 4;
19980 insn |= (old_op & 7) << 12;
19981 insn |= (old_op & 0x38) << 13;
19983 insn |= 0x00000c00;
19984 put_thumb32_insn (buf, insn);
19985 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19989 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19991 pc_rel = (opcode == T_MNEM_ldr_pc2);
19994 if (fragp->fr_var == 4)
19996 insn = THUMB_OP32 (opcode);
19997 insn |= (old_op & 0xf0) << 4;
19998 put_thumb32_insn (buf, insn);
19999 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20003 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20004 exp.X_add_number -= 4;
20012 if (fragp->fr_var == 4)
20014 int r0off = (opcode == T_MNEM_mov
20015 || opcode == T_MNEM_movs) ? 0 : 8;
20016 insn = THUMB_OP32 (opcode);
20017 insn = (insn & 0xe1ffffff) | 0x10000000;
20018 insn |= (old_op & 0x700) << r0off;
20019 put_thumb32_insn (buf, insn);
20020 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20024 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20029 if (fragp->fr_var == 4)
20031 insn = THUMB_OP32(opcode);
20032 put_thumb32_insn (buf, insn);
20033 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20036 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20040 if (fragp->fr_var == 4)
20042 insn = THUMB_OP32(opcode);
20043 insn |= (old_op & 0xf00) << 14;
20044 put_thumb32_insn (buf, insn);
20045 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20048 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20051 case T_MNEM_add_sp:
20052 case T_MNEM_add_pc:
20053 case T_MNEM_inc_sp:
20054 case T_MNEM_dec_sp:
20055 if (fragp->fr_var == 4)
20057 /* ??? Choose between add and addw. */
20058 insn = THUMB_OP32 (opcode);
20059 insn |= (old_op & 0xf0) << 4;
20060 put_thumb32_insn (buf, insn);
20061 if (opcode == T_MNEM_add_pc)
20062 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20064 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20067 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20075 if (fragp->fr_var == 4)
20077 insn = THUMB_OP32 (opcode);
20078 insn |= (old_op & 0xf0) << 4;
20079 insn |= (old_op & 0xf) << 16;
20080 put_thumb32_insn (buf, insn);
20081 if (insn & (1 << 20))
20082 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20084 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20087 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20093 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20094 (enum bfd_reloc_code_real) reloc_type);
20095 fixp->fx_file = fragp->fr_file;
20096 fixp->fx_line = fragp->fr_line;
20097 fragp->fr_fix += fragp->fr_var;
20100 /* Return the size of a relaxable immediate operand instruction.
20101 SHIFT and SIZE specify the form of the allowable immediate. */
20103 relax_immediate (fragS *fragp, int size, int shift)
20109 /* ??? Should be able to do better than this. */
20110 if (fragp->fr_symbol)
20113 low = (1 << shift) - 1;
20114 mask = (1 << (shift + size)) - (1 << shift);
20115 offset = fragp->fr_offset;
20116 /* Force misaligned offsets to 32-bit variant. */
20119 if (offset & ~mask)
20124 /* Get the address of a symbol during relaxation. */
20126 relaxed_symbol_addr (fragS *fragp, long stretch)
20132 sym = fragp->fr_symbol;
20133 sym_frag = symbol_get_frag (sym);
20134 know (S_GET_SEGMENT (sym) != absolute_section
20135 || sym_frag == &zero_address_frag);
20136 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20138 /* If frag has yet to be reached on this pass, assume it will
20139 move by STRETCH just as we did. If this is not so, it will
20140 be because some frag between grows, and that will force
20144 && sym_frag->relax_marker != fragp->relax_marker)
20148 /* Adjust stretch for any alignment frag. Note that if have
20149 been expanding the earlier code, the symbol may be
20150 defined in what appears to be an earlier frag. FIXME:
20151 This doesn't handle the fr_subtype field, which specifies
20152 a maximum number of bytes to skip when doing an
20154 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20156 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20159 stretch = - ((- stretch)
20160 & ~ ((1 << (int) f->fr_offset) - 1));
20162 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20174 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20177 relax_adr (fragS *fragp, asection *sec, long stretch)
20182 /* Assume worst case for symbols not known to be in the same section. */
20183 if (fragp->fr_symbol == NULL
20184 || !S_IS_DEFINED (fragp->fr_symbol)
20185 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20186 || S_IS_WEAK (fragp->fr_symbol))
20189 val = relaxed_symbol_addr (fragp, stretch);
20190 addr = fragp->fr_address + fragp->fr_fix;
20191 addr = (addr + 4) & ~3;
20192 /* Force misaligned targets to 32-bit variant. */
20196 if (val < 0 || val > 1020)
20201 /* Return the size of a relaxable add/sub immediate instruction. */
20203 relax_addsub (fragS *fragp, asection *sec)
20208 buf = fragp->fr_literal + fragp->fr_fix;
20209 op = bfd_get_16(sec->owner, buf);
20210 if ((op & 0xf) == ((op >> 4) & 0xf))
20211 return relax_immediate (fragp, 8, 0);
20213 return relax_immediate (fragp, 3, 0);
20217 /* Return the size of a relaxable branch instruction. BITS is the
20218 size of the offset field in the narrow instruction. */
20221 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20227 /* Assume worst case for symbols not known to be in the same section. */
20228 if (!S_IS_DEFINED (fragp->fr_symbol)
20229 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20230 || S_IS_WEAK (fragp->fr_symbol))
20234 if (S_IS_DEFINED (fragp->fr_symbol)
20235 && ARM_IS_FUNC (fragp->fr_symbol))
20238 /* PR 12532. Global symbols with default visibility might
20239 be preempted, so do not relax relocations to them. */
20240 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
20241 && (! S_IS_LOCAL (fragp->fr_symbol)))
20245 val = relaxed_symbol_addr (fragp, stretch);
20246 addr = fragp->fr_address + fragp->fr_fix + 4;
20249 /* Offset is a signed value *2 */
20251 if (val >= limit || val < -limit)
20257 /* Relax a machine dependent frag. This returns the amount by which
20258 the current size of the frag should change. */
20261 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20266 oldsize = fragp->fr_var;
20267 switch (fragp->fr_subtype)
20269 case T_MNEM_ldr_pc2:
20270 newsize = relax_adr (fragp, sec, stretch);
20272 case T_MNEM_ldr_pc:
20273 case T_MNEM_ldr_sp:
20274 case T_MNEM_str_sp:
20275 newsize = relax_immediate (fragp, 8, 2);
20279 newsize = relax_immediate (fragp, 5, 2);
20283 newsize = relax_immediate (fragp, 5, 1);
20287 newsize = relax_immediate (fragp, 5, 0);
20290 newsize = relax_adr (fragp, sec, stretch);
20296 newsize = relax_immediate (fragp, 8, 0);
20299 newsize = relax_branch (fragp, sec, 11, stretch);
20302 newsize = relax_branch (fragp, sec, 8, stretch);
20304 case T_MNEM_add_sp:
20305 case T_MNEM_add_pc:
20306 newsize = relax_immediate (fragp, 8, 2);
20308 case T_MNEM_inc_sp:
20309 case T_MNEM_dec_sp:
20310 newsize = relax_immediate (fragp, 7, 2);
20316 newsize = relax_addsub (fragp, sec);
20322 fragp->fr_var = newsize;
20323 /* Freeze wide instructions that are at or before the same location as
20324 in the previous pass. This avoids infinite loops.
20325 Don't freeze them unconditionally because targets may be artificially
20326 misaligned by the expansion of preceding frags. */
20327 if (stretch <= 0 && newsize > 2)
20329 md_convert_frag (sec->owner, sec, fragp);
20333 return newsize - oldsize;
20336 /* Round up a section size to the appropriate boundary. */
20339 md_section_align (segT segment ATTRIBUTE_UNUSED,
20342 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20343 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20345 /* For a.out, force the section size to be aligned. If we don't do
20346 this, BFD will align it for us, but it will not write out the
20347 final bytes of the section. This may be a bug in BFD, but it is
20348 easier to fix it here since that is how the other a.out targets
20352 align = bfd_get_section_alignment (stdoutput, segment);
20353 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20360 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20361 of an rs_align_code fragment. */
20364 arm_handle_align (fragS * fragP)
20366 static char const arm_noop[2][2][4] =
20369 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20370 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20373 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20374 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20377 static char const thumb_noop[2][2][2] =
20380 {0xc0, 0x46}, /* LE */
20381 {0x46, 0xc0}, /* BE */
20384 {0x00, 0xbf}, /* LE */
20385 {0xbf, 0x00} /* BE */
20388 static char const wide_thumb_noop[2][4] =
20389 { /* Wide Thumb-2 */
20390 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20391 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20394 unsigned bytes, fix, noop_size;
20397 const char *narrow_noop = NULL;
20402 if (fragP->fr_type != rs_align_code)
20405 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20406 p = fragP->fr_literal + fragP->fr_fix;
20409 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20410 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
20412 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
20414 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
20416 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20418 narrow_noop = thumb_noop[1][target_big_endian];
20419 noop = wide_thumb_noop[target_big_endian];
20422 noop = thumb_noop[0][target_big_endian];
20430 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20431 [target_big_endian];
20438 fragP->fr_var = noop_size;
20440 if (bytes & (noop_size - 1))
20442 fix = bytes & (noop_size - 1);
20444 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20446 memset (p, 0, fix);
20453 if (bytes & noop_size)
20455 /* Insert a narrow noop. */
20456 memcpy (p, narrow_noop, noop_size);
20458 bytes -= noop_size;
20462 /* Use wide noops for the remainder */
20466 while (bytes >= noop_size)
20468 memcpy (p, noop, noop_size);
20470 bytes -= noop_size;
20474 fragP->fr_fix += fix;
20477 /* Called from md_do_align. Used to create an alignment
20478 frag in a code section. */
20481 arm_frag_align_code (int n, int max)
20485 /* We assume that there will never be a requirement
20486 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20487 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
20492 _("alignments greater than %d bytes not supported in .text sections."),
20493 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20494 as_fatal ("%s", err_msg);
20497 p = frag_var (rs_align_code,
20498 MAX_MEM_FOR_RS_ALIGN_CODE,
20500 (relax_substateT) max,
20507 /* Perform target specific initialisation of a frag.
20508 Note - despite the name this initialisation is not done when the frag
20509 is created, but only when its type is assigned. A frag can be created
20510 and used a long time before its type is set, so beware of assuming that
20511 this initialisationis performed first. */
20515 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20517 /* Record whether this frag is in an ARM or a THUMB area. */
20518 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20521 #else /* OBJ_ELF is defined. */
20523 arm_init_frag (fragS * fragP, int max_chars)
20525 /* If the current ARM vs THUMB mode has not already
20526 been recorded into this frag then do so now. */
20527 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20529 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20531 /* Record a mapping symbol for alignment frags. We will delete this
20532 later if the alignment ends up empty. */
20533 switch (fragP->fr_type)
20536 case rs_align_test:
20538 mapping_state_2 (MAP_DATA, max_chars);
20540 case rs_align_code:
20541 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20549 /* When we change sections we need to issue a new mapping symbol. */
20552 arm_elf_change_section (void)
20554 /* Link an unlinked unwind index table section to the .text section. */
20555 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20556 && elf_linked_to_section (now_seg) == NULL)
20557 elf_linked_to_section (now_seg) = text_section;
20561 arm_elf_section_type (const char * str, size_t len)
20563 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20564 return SHT_ARM_EXIDX;
20569 /* Code to deal with unwinding tables. */
20571 static void add_unwind_adjustsp (offsetT);
20573 /* Generate any deferred unwind frame offset. */
20576 flush_pending_unwind (void)
20580 offset = unwind.pending_offset;
20581 unwind.pending_offset = 0;
20583 add_unwind_adjustsp (offset);
20586 /* Add an opcode to this list for this function. Two-byte opcodes should
20587 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20591 add_unwind_opcode (valueT op, int length)
20593 /* Add any deferred stack adjustment. */
20594 if (unwind.pending_offset)
20595 flush_pending_unwind ();
20597 unwind.sp_restored = 0;
20599 if (unwind.opcode_count + length > unwind.opcode_alloc)
20601 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20602 if (unwind.opcodes)
20603 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
20604 unwind.opcode_alloc);
20606 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
20611 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20613 unwind.opcode_count++;
20617 /* Add unwind opcodes to adjust the stack pointer. */
20620 add_unwind_adjustsp (offsetT offset)
20624 if (offset > 0x200)
20626 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20631 /* Long form: 0xb2, uleb128. */
20632 /* This might not fit in a word so add the individual bytes,
20633 remembering the list is built in reverse order. */
20634 o = (valueT) ((offset - 0x204) >> 2);
20636 add_unwind_opcode (0, 1);
20638 /* Calculate the uleb128 encoding of the offset. */
20642 bytes[n] = o & 0x7f;
20648 /* Add the insn. */
20650 add_unwind_opcode (bytes[n - 1], 1);
20651 add_unwind_opcode (0xb2, 1);
20653 else if (offset > 0x100)
20655 /* Two short opcodes. */
20656 add_unwind_opcode (0x3f, 1);
20657 op = (offset - 0x104) >> 2;
20658 add_unwind_opcode (op, 1);
20660 else if (offset > 0)
20662 /* Short opcode. */
20663 op = (offset - 4) >> 2;
20664 add_unwind_opcode (op, 1);
20666 else if (offset < 0)
20669 while (offset > 0x100)
20671 add_unwind_opcode (0x7f, 1);
20674 op = ((offset - 4) >> 2) | 0x40;
20675 add_unwind_opcode (op, 1);
20679 /* Finish the list of unwind opcodes for this function. */
20681 finish_unwind_opcodes (void)
20685 if (unwind.fp_used)
20687 /* Adjust sp as necessary. */
20688 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20689 flush_pending_unwind ();
20691 /* After restoring sp from the frame pointer. */
20692 op = 0x90 | unwind.fp_reg;
20693 add_unwind_opcode (op, 1);
20696 flush_pending_unwind ();
20700 /* Start an exception table entry. If idx is nonzero this is an index table
20704 start_unwind_section (const segT text_seg, int idx)
20706 const char * text_name;
20707 const char * prefix;
20708 const char * prefix_once;
20709 const char * group_name;
20713 size_t sec_name_len;
20720 prefix = ELF_STRING_ARM_unwind;
20721 prefix_once = ELF_STRING_ARM_unwind_once;
20722 type = SHT_ARM_EXIDX;
20726 prefix = ELF_STRING_ARM_unwind_info;
20727 prefix_once = ELF_STRING_ARM_unwind_info_once;
20728 type = SHT_PROGBITS;
20731 text_name = segment_name (text_seg);
20732 if (streq (text_name, ".text"))
20735 if (strncmp (text_name, ".gnu.linkonce.t.",
20736 strlen (".gnu.linkonce.t.")) == 0)
20738 prefix = prefix_once;
20739 text_name += strlen (".gnu.linkonce.t.");
20742 prefix_len = strlen (prefix);
20743 text_len = strlen (text_name);
20744 sec_name_len = prefix_len + text_len;
20745 sec_name = (char *) xmalloc (sec_name_len + 1);
20746 memcpy (sec_name, prefix, prefix_len);
20747 memcpy (sec_name + prefix_len, text_name, text_len);
20748 sec_name[prefix_len + text_len] = '\0';
20754 /* Handle COMDAT group. */
20755 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
20757 group_name = elf_group_name (text_seg);
20758 if (group_name == NULL)
20760 as_bad (_("Group section `%s' has no group signature"),
20761 segment_name (text_seg));
20762 ignore_rest_of_line ();
20765 flags |= SHF_GROUP;
20769 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
20771 /* Set the section link for index tables. */
20773 elf_linked_to_section (now_seg) = text_seg;
20777 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20778 personality routine data. Returns zero, or the index table value for
20779 and inline entry. */
20782 create_unwind_entry (int have_data)
20787 /* The current word of data. */
20789 /* The number of bytes left in this word. */
20792 finish_unwind_opcodes ();
20794 /* Remember the current text section. */
20795 unwind.saved_seg = now_seg;
20796 unwind.saved_subseg = now_subseg;
20798 start_unwind_section (now_seg, 0);
20800 if (unwind.personality_routine == NULL)
20802 if (unwind.personality_index == -2)
20805 as_bad (_("handlerdata in cantunwind frame"));
20806 return 1; /* EXIDX_CANTUNWIND. */
20809 /* Use a default personality routine if none is specified. */
20810 if (unwind.personality_index == -1)
20812 if (unwind.opcode_count > 3)
20813 unwind.personality_index = 1;
20815 unwind.personality_index = 0;
20818 /* Space for the personality routine entry. */
20819 if (unwind.personality_index == 0)
20821 if (unwind.opcode_count > 3)
20822 as_bad (_("too many unwind opcodes for personality routine 0"));
20826 /* All the data is inline in the index table. */
20829 while (unwind.opcode_count > 0)
20831 unwind.opcode_count--;
20832 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20836 /* Pad with "finish" opcodes. */
20838 data = (data << 8) | 0xb0;
20845 /* We get two opcodes "free" in the first word. */
20846 size = unwind.opcode_count - 2;
20850 gas_assert (unwind.personality_index == -1);
20852 /* An extra byte is required for the opcode count. */
20853 size = unwind.opcode_count + 1;
20856 size = (size + 3) >> 2;
20858 as_bad (_("too many unwind opcodes"));
20860 frag_align (2, 0, 0);
20861 record_alignment (now_seg, 2);
20862 unwind.table_entry = expr_build_dot ();
20864 /* Allocate the table entry. */
20865 ptr = frag_more ((size << 2) + 4);
20866 /* PR 13449: Zero the table entries in case some of them are not used. */
20867 memset (ptr, 0, (size << 2) + 4);
20868 where = frag_now_fix () - ((size << 2) + 4);
20870 switch (unwind.personality_index)
20873 /* ??? Should this be a PLT generating relocation? */
20874 /* Custom personality routine. */
20875 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20876 BFD_RELOC_ARM_PREL31);
20881 /* Set the first byte to the number of additional words. */
20882 data = size > 0 ? size - 1 : 0;
20886 /* ABI defined personality routines. */
20888 /* Three opcodes bytes are packed into the first word. */
20895 /* The size and first two opcode bytes go in the first word. */
20896 data = ((0x80 + unwind.personality_index) << 8) | size;
20901 /* Should never happen. */
20905 /* Pack the opcodes into words (MSB first), reversing the list at the same
20907 while (unwind.opcode_count > 0)
20911 md_number_to_chars (ptr, data, 4);
20916 unwind.opcode_count--;
20918 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20921 /* Finish off the last word. */
20924 /* Pad with "finish" opcodes. */
20926 data = (data << 8) | 0xb0;
20928 md_number_to_chars (ptr, data, 4);
20933 /* Add an empty descriptor if there is no user-specified data. */
20934 ptr = frag_more (4);
20935 md_number_to_chars (ptr, 0, 4);
20942 /* Initialize the DWARF-2 unwind information for this procedure. */
20945 tc_arm_frame_initial_instructions (void)
20947 cfi_add_CFA_def_cfa (REG_SP, 0);
20949 #endif /* OBJ_ELF */
20951 /* Convert REGNAME to a DWARF-2 register number. */
20954 tc_arm_regname_to_dw2regnum (char *regname)
20956 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20966 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20970 exp.X_op = O_secrel;
20971 exp.X_add_symbol = symbol;
20972 exp.X_add_number = 0;
20973 emit_expr (&exp, size);
20977 /* MD interface: Symbol and relocation handling. */
20979 /* Return the address within the segment that a PC-relative fixup is
20980 relative to. For ARM, PC-relative fixups applied to instructions
20981 are generally relative to the location of the fixup plus 8 bytes.
20982 Thumb branches are offset by 4, and Thumb loads relative to PC
20983 require special handling. */
20986 md_pcrel_from_section (fixS * fixP, segT seg)
20988 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20990 /* If this is pc-relative and we are going to emit a relocation
20991 then we just want to put out any pipeline compensation that the linker
20992 will need. Otherwise we want to use the calculated base.
20993 For WinCE we skip the bias for externals as well, since this
20994 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20996 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20997 || (arm_force_relocation (fixP)
20999 && !S_IS_EXTERNAL (fixP->fx_addsy)
21005 switch (fixP->fx_r_type)
21007 /* PC relative addressing on the Thumb is slightly odd as the
21008 bottom two bits of the PC are forced to zero for the
21009 calculation. This happens *after* application of the
21010 pipeline offset. However, Thumb adrl already adjusts for
21011 this, so we need not do it again. */
21012 case BFD_RELOC_ARM_THUMB_ADD:
21015 case BFD_RELOC_ARM_THUMB_OFFSET:
21016 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21017 case BFD_RELOC_ARM_T32_ADD_PC12:
21018 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21019 return (base + 4) & ~3;
21021 /* Thumb branches are simply offset by +4. */
21022 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21023 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21024 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21025 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21026 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21029 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21031 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21032 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21033 && ARM_IS_FUNC (fixP->fx_addsy)
21034 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21035 base = fixP->fx_where + fixP->fx_frag->fr_address;
21038 /* BLX is like branches above, but forces the low two bits of PC to
21040 case BFD_RELOC_THUMB_PCREL_BLX:
21042 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21043 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21044 && THUMB_IS_FUNC (fixP->fx_addsy)
21045 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21046 base = fixP->fx_where + fixP->fx_frag->fr_address;
21047 return (base + 4) & ~3;
21049 /* ARM mode branches are offset by +8. However, the Windows CE
21050 loader expects the relocation not to take this into account. */
21051 case BFD_RELOC_ARM_PCREL_BLX:
21053 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21054 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21055 && ARM_IS_FUNC (fixP->fx_addsy)
21056 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21057 base = fixP->fx_where + fixP->fx_frag->fr_address;
21060 case BFD_RELOC_ARM_PCREL_CALL:
21062 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21063 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21064 && THUMB_IS_FUNC (fixP->fx_addsy)
21065 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21066 base = fixP->fx_where + fixP->fx_frag->fr_address;
21069 case BFD_RELOC_ARM_PCREL_BRANCH:
21070 case BFD_RELOC_ARM_PCREL_JUMP:
21071 case BFD_RELOC_ARM_PLT32:
21073 /* When handling fixups immediately, because we have already
21074 discovered the value of a symbol, or the address of the frag involved
21075 we must account for the offset by +8, as the OS loader will never see the reloc.
21076 see fixup_segment() in write.c
21077 The S_IS_EXTERNAL test handles the case of global symbols.
21078 Those need the calculated base, not just the pipe compensation the linker will need. */
21080 && fixP->fx_addsy != NULL
21081 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21082 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21090 /* ARM mode loads relative to PC are also offset by +8. Unlike
21091 branches, the Windows CE loader *does* expect the relocation
21092 to take this into account. */
21093 case BFD_RELOC_ARM_OFFSET_IMM:
21094 case BFD_RELOC_ARM_OFFSET_IMM8:
21095 case BFD_RELOC_ARM_HWLITERAL:
21096 case BFD_RELOC_ARM_LITERAL:
21097 case BFD_RELOC_ARM_CP_OFF_IMM:
21101 /* Other PC-relative relocations are un-offset. */
21107 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21108 Otherwise we have no need to default values of symbols. */
21111 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21114 if (name[0] == '_' && name[1] == 'G'
21115 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21119 if (symbol_find (name))
21120 as_bad (_("GOT already in the symbol table"));
21122 GOT_symbol = symbol_new (name, undefined_section,
21123 (valueT) 0, & zero_address_frag);
21133 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21134 computed as two separate immediate values, added together. We
21135 already know that this value cannot be computed by just one ARM
21138 static unsigned int
21139 validate_immediate_twopart (unsigned int val,
21140 unsigned int * highpart)
21145 for (i = 0; i < 32; i += 2)
21146 if (((a = rotate_left (val, i)) & 0xff) != 0)
21152 * highpart = (a >> 8) | ((i + 24) << 7);
21154 else if (a & 0xff0000)
21156 if (a & 0xff000000)
21158 * highpart = (a >> 16) | ((i + 16) << 7);
21162 gas_assert (a & 0xff000000);
21163 * highpart = (a >> 24) | ((i + 8) << 7);
21166 return (a & 0xff) | (i << 7);
21173 validate_offset_imm (unsigned int val, int hwse)
21175 if ((hwse && val > 255) || val > 4095)
21180 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21181 negative immediate constant by altering the instruction. A bit of
21186 by inverting the second operand, and
21189 by negating the second operand. */
21192 negate_data_op (unsigned long * instruction,
21193 unsigned long value)
21196 unsigned long negated, inverted;
21198 negated = encode_arm_immediate (-value);
21199 inverted = encode_arm_immediate (~value);
21201 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21204 /* First negates. */
21205 case OPCODE_SUB: /* ADD <-> SUB */
21206 new_inst = OPCODE_ADD;
21211 new_inst = OPCODE_SUB;
21215 case OPCODE_CMP: /* CMP <-> CMN */
21216 new_inst = OPCODE_CMN;
21221 new_inst = OPCODE_CMP;
21225 /* Now Inverted ops. */
21226 case OPCODE_MOV: /* MOV <-> MVN */
21227 new_inst = OPCODE_MVN;
21232 new_inst = OPCODE_MOV;
21236 case OPCODE_AND: /* AND <-> BIC */
21237 new_inst = OPCODE_BIC;
21242 new_inst = OPCODE_AND;
21246 case OPCODE_ADC: /* ADC <-> SBC */
21247 new_inst = OPCODE_SBC;
21252 new_inst = OPCODE_ADC;
21256 /* We cannot do anything. */
21261 if (value == (unsigned) FAIL)
21264 *instruction &= OPCODE_MASK;
21265 *instruction |= new_inst << DATA_OP_SHIFT;
21269 /* Like negate_data_op, but for Thumb-2. */
21271 static unsigned int
21272 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21276 unsigned int negated, inverted;
21278 negated = encode_thumb32_immediate (-value);
21279 inverted = encode_thumb32_immediate (~value);
21281 rd = (*instruction >> 8) & 0xf;
21282 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21285 /* ADD <-> SUB. Includes CMP <-> CMN. */
21286 case T2_OPCODE_SUB:
21287 new_inst = T2_OPCODE_ADD;
21291 case T2_OPCODE_ADD:
21292 new_inst = T2_OPCODE_SUB;
21296 /* ORR <-> ORN. Includes MOV <-> MVN. */
21297 case T2_OPCODE_ORR:
21298 new_inst = T2_OPCODE_ORN;
21302 case T2_OPCODE_ORN:
21303 new_inst = T2_OPCODE_ORR;
21307 /* AND <-> BIC. TST has no inverted equivalent. */
21308 case T2_OPCODE_AND:
21309 new_inst = T2_OPCODE_BIC;
21316 case T2_OPCODE_BIC:
21317 new_inst = T2_OPCODE_AND;
21322 case T2_OPCODE_ADC:
21323 new_inst = T2_OPCODE_SBC;
21327 case T2_OPCODE_SBC:
21328 new_inst = T2_OPCODE_ADC;
21332 /* We cannot do anything. */
21337 if (value == (unsigned int)FAIL)
21340 *instruction &= T2_OPCODE_MASK;
21341 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21345 /* Read a 32-bit thumb instruction from buf. */
21346 static unsigned long
21347 get_thumb32_insn (char * buf)
21349 unsigned long insn;
21350 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21351 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21357 /* We usually want to set the low bit on the address of thumb function
21358 symbols. In particular .word foo - . should have the low bit set.
21359 Generic code tries to fold the difference of two symbols to
21360 a constant. Prevent this and force a relocation when the first symbols
21361 is a thumb function. */
21364 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21366 if (op == O_subtract
21367 && l->X_op == O_symbol
21368 && r->X_op == O_symbol
21369 && THUMB_IS_FUNC (l->X_add_symbol))
21371 l->X_op = O_subtract;
21372 l->X_op_symbol = r->X_add_symbol;
21373 l->X_add_number -= r->X_add_number;
21377 /* Process as normal. */
21381 /* Encode Thumb2 unconditional branches and calls. The encoding
21382 for the 2 are identical for the immediate values. */
21385 encode_thumb2_b_bl_offset (char * buf, offsetT value)
21387 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21390 addressT S, I1, I2, lo, hi;
21392 S = (value >> 24) & 0x01;
21393 I1 = (value >> 23) & 0x01;
21394 I2 = (value >> 22) & 0x01;
21395 hi = (value >> 12) & 0x3ff;
21396 lo = (value >> 1) & 0x7ff;
21397 newval = md_chars_to_number (buf, THUMB_SIZE);
21398 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21399 newval |= (S << 10) | hi;
21400 newval2 &= ~T2I1I2MASK;
21401 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21402 md_number_to_chars (buf, newval, THUMB_SIZE);
21403 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21407 md_apply_fix (fixS * fixP,
21411 offsetT value = * valP;
21413 unsigned int newimm;
21414 unsigned long temp;
21416 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
21418 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
21420 /* Note whether this will delete the relocation. */
21422 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21425 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21426 consistency with the behaviour on 32-bit hosts. Remember value
21428 value &= 0xffffffff;
21429 value ^= 0x80000000;
21430 value -= 0x80000000;
21433 fixP->fx_addnumber = value;
21435 /* Same treatment for fixP->fx_offset. */
21436 fixP->fx_offset &= 0xffffffff;
21437 fixP->fx_offset ^= 0x80000000;
21438 fixP->fx_offset -= 0x80000000;
21440 switch (fixP->fx_r_type)
21442 case BFD_RELOC_NONE:
21443 /* This will need to go in the object file. */
21447 case BFD_RELOC_ARM_IMMEDIATE:
21448 /* We claim that this fixup has been processed here,
21449 even if in fact we generate an error because we do
21450 not have a reloc for it, so tc_gen_reloc will reject it. */
21453 if (fixP->fx_addsy)
21455 const char *msg = 0;
21457 if (! S_IS_DEFINED (fixP->fx_addsy))
21458 msg = _("undefined symbol %s used as an immediate value");
21459 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21460 msg = _("symbol %s is in a different section");
21461 else if (S_IS_WEAK (fixP->fx_addsy))
21462 msg = _("symbol %s is weak and may be overridden later");
21466 as_bad_where (fixP->fx_file, fixP->fx_line,
21467 msg, S_GET_NAME (fixP->fx_addsy));
21472 temp = md_chars_to_number (buf, INSN_SIZE);
21474 /* If the offset is negative, we should use encoding A2 for ADR. */
21475 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21476 newimm = negate_data_op (&temp, value);
21479 newimm = encode_arm_immediate (value);
21481 /* If the instruction will fail, see if we can fix things up by
21482 changing the opcode. */
21483 if (newimm == (unsigned int) FAIL)
21484 newimm = negate_data_op (&temp, value);
21487 if (newimm == (unsigned int) FAIL)
21489 as_bad_where (fixP->fx_file, fixP->fx_line,
21490 _("invalid constant (%lx) after fixup"),
21491 (unsigned long) value);
21495 newimm |= (temp & 0xfffff000);
21496 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21499 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21501 unsigned int highpart = 0;
21502 unsigned int newinsn = 0xe1a00000; /* nop. */
21504 if (fixP->fx_addsy)
21506 const char *msg = 0;
21508 if (! S_IS_DEFINED (fixP->fx_addsy))
21509 msg = _("undefined symbol %s used as an immediate value");
21510 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21511 msg = _("symbol %s is in a different section");
21512 else if (S_IS_WEAK (fixP->fx_addsy))
21513 msg = _("symbol %s is weak and may be overridden later");
21517 as_bad_where (fixP->fx_file, fixP->fx_line,
21518 msg, S_GET_NAME (fixP->fx_addsy));
21523 newimm = encode_arm_immediate (value);
21524 temp = md_chars_to_number (buf, INSN_SIZE);
21526 /* If the instruction will fail, see if we can fix things up by
21527 changing the opcode. */
21528 if (newimm == (unsigned int) FAIL
21529 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21531 /* No ? OK - try using two ADD instructions to generate
21533 newimm = validate_immediate_twopart (value, & highpart);
21535 /* Yes - then make sure that the second instruction is
21537 if (newimm != (unsigned int) FAIL)
21539 /* Still No ? Try using a negated value. */
21540 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21541 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21542 /* Otherwise - give up. */
21545 as_bad_where (fixP->fx_file, fixP->fx_line,
21546 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21551 /* Replace the first operand in the 2nd instruction (which
21552 is the PC) with the destination register. We have
21553 already added in the PC in the first instruction and we
21554 do not want to do it again. */
21555 newinsn &= ~ 0xf0000;
21556 newinsn |= ((newinsn & 0x0f000) << 4);
21559 newimm |= (temp & 0xfffff000);
21560 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21562 highpart |= (newinsn & 0xfffff000);
21563 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21567 case BFD_RELOC_ARM_OFFSET_IMM:
21568 if (!fixP->fx_done && seg->use_rela_p)
21571 case BFD_RELOC_ARM_LITERAL:
21577 if (validate_offset_imm (value, 0) == FAIL)
21579 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21580 as_bad_where (fixP->fx_file, fixP->fx_line,
21581 _("invalid literal constant: pool needs to be closer"));
21583 as_bad_where (fixP->fx_file, fixP->fx_line,
21584 _("bad immediate value for offset (%ld)"),
21589 newval = md_chars_to_number (buf, INSN_SIZE);
21591 newval &= 0xfffff000;
21594 newval &= 0xff7ff000;
21595 newval |= value | (sign ? INDEX_UP : 0);
21597 md_number_to_chars (buf, newval, INSN_SIZE);
21600 case BFD_RELOC_ARM_OFFSET_IMM8:
21601 case BFD_RELOC_ARM_HWLITERAL:
21607 if (validate_offset_imm (value, 1) == FAIL)
21609 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21610 as_bad_where (fixP->fx_file, fixP->fx_line,
21611 _("invalid literal constant: pool needs to be closer"));
21613 as_bad_where (fixP->fx_file, fixP->fx_line,
21614 _("bad immediate value for 8-bit offset (%ld)"),
21619 newval = md_chars_to_number (buf, INSN_SIZE);
21621 newval &= 0xfffff0f0;
21624 newval &= 0xff7ff0f0;
21625 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21627 md_number_to_chars (buf, newval, INSN_SIZE);
21630 case BFD_RELOC_ARM_T32_OFFSET_U8:
21631 if (value < 0 || value > 1020 || value % 4 != 0)
21632 as_bad_where (fixP->fx_file, fixP->fx_line,
21633 _("bad immediate value for offset (%ld)"), (long) value);
21636 newval = md_chars_to_number (buf+2, THUMB_SIZE);
21638 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21641 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21642 /* This is a complicated relocation used for all varieties of Thumb32
21643 load/store instruction with immediate offset:
21645 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21646 *4, optional writeback(W)
21647 (doubleword load/store)
21649 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21650 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21651 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21652 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21653 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21655 Uppercase letters indicate bits that are already encoded at
21656 this point. Lowercase letters are our problem. For the
21657 second block of instructions, the secondary opcode nybble
21658 (bits 8..11) is present, and bit 23 is zero, even if this is
21659 a PC-relative operation. */
21660 newval = md_chars_to_number (buf, THUMB_SIZE);
21662 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
21664 if ((newval & 0xf0000000) == 0xe0000000)
21666 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21668 newval |= (1 << 23);
21671 if (value % 4 != 0)
21673 as_bad_where (fixP->fx_file, fixP->fx_line,
21674 _("offset not a multiple of 4"));
21680 as_bad_where (fixP->fx_file, fixP->fx_line,
21681 _("offset out of range"));
21686 else if ((newval & 0x000f0000) == 0x000f0000)
21688 /* PC-relative, 12-bit offset. */
21690 newval |= (1 << 23);
21695 as_bad_where (fixP->fx_file, fixP->fx_line,
21696 _("offset out of range"));
21701 else if ((newval & 0x00000100) == 0x00000100)
21703 /* Writeback: 8-bit, +/- offset. */
21705 newval |= (1 << 9);
21710 as_bad_where (fixP->fx_file, fixP->fx_line,
21711 _("offset out of range"));
21716 else if ((newval & 0x00000f00) == 0x00000e00)
21718 /* T-instruction: positive 8-bit offset. */
21719 if (value < 0 || value > 0xff)
21721 as_bad_where (fixP->fx_file, fixP->fx_line,
21722 _("offset out of range"));
21730 /* Positive 12-bit or negative 8-bit offset. */
21734 newval |= (1 << 23);
21744 as_bad_where (fixP->fx_file, fixP->fx_line,
21745 _("offset out of range"));
21752 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21753 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21756 case BFD_RELOC_ARM_SHIFT_IMM:
21757 newval = md_chars_to_number (buf, INSN_SIZE);
21758 if (((unsigned long) value) > 32
21760 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21762 as_bad_where (fixP->fx_file, fixP->fx_line,
21763 _("shift expression is too large"));
21768 /* Shifts of zero must be done as lsl. */
21770 else if (value == 32)
21772 newval &= 0xfffff07f;
21773 newval |= (value & 0x1f) << 7;
21774 md_number_to_chars (buf, newval, INSN_SIZE);
21777 case BFD_RELOC_ARM_T32_IMMEDIATE:
21778 case BFD_RELOC_ARM_T32_ADD_IMM:
21779 case BFD_RELOC_ARM_T32_IMM12:
21780 case BFD_RELOC_ARM_T32_ADD_PC12:
21781 /* We claim that this fixup has been processed here,
21782 even if in fact we generate an error because we do
21783 not have a reloc for it, so tc_gen_reloc will reject it. */
21787 && ! S_IS_DEFINED (fixP->fx_addsy))
21789 as_bad_where (fixP->fx_file, fixP->fx_line,
21790 _("undefined symbol %s used as an immediate value"),
21791 S_GET_NAME (fixP->fx_addsy));
21795 newval = md_chars_to_number (buf, THUMB_SIZE);
21797 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
21800 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21801 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21803 newimm = encode_thumb32_immediate (value);
21804 if (newimm == (unsigned int) FAIL)
21805 newimm = thumb32_negate_data_op (&newval, value);
21807 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21808 && newimm == (unsigned int) FAIL)
21810 /* Turn add/sum into addw/subw. */
21811 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21812 newval = (newval & 0xfeffffff) | 0x02000000;
21813 /* No flat 12-bit imm encoding for addsw/subsw. */
21814 if ((newval & 0x00100000) == 0)
21816 /* 12 bit immediate for addw/subw. */
21820 newval ^= 0x00a00000;
21823 newimm = (unsigned int) FAIL;
21829 if (newimm == (unsigned int)FAIL)
21831 as_bad_where (fixP->fx_file, fixP->fx_line,
21832 _("invalid constant (%lx) after fixup"),
21833 (unsigned long) value);
21837 newval |= (newimm & 0x800) << 15;
21838 newval |= (newimm & 0x700) << 4;
21839 newval |= (newimm & 0x0ff);
21841 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21842 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21845 case BFD_RELOC_ARM_SMC:
21846 if (((unsigned long) value) > 0xffff)
21847 as_bad_where (fixP->fx_file, fixP->fx_line,
21848 _("invalid smc expression"));
21849 newval = md_chars_to_number (buf, INSN_SIZE);
21850 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21851 md_number_to_chars (buf, newval, INSN_SIZE);
21854 case BFD_RELOC_ARM_HVC:
21855 if (((unsigned long) value) > 0xffff)
21856 as_bad_where (fixP->fx_file, fixP->fx_line,
21857 _("invalid hvc expression"));
21858 newval = md_chars_to_number (buf, INSN_SIZE);
21859 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21860 md_number_to_chars (buf, newval, INSN_SIZE);
21863 case BFD_RELOC_ARM_SWI:
21864 if (fixP->tc_fix_data != 0)
21866 if (((unsigned long) value) > 0xff)
21867 as_bad_where (fixP->fx_file, fixP->fx_line,
21868 _("invalid swi expression"));
21869 newval = md_chars_to_number (buf, THUMB_SIZE);
21871 md_number_to_chars (buf, newval, THUMB_SIZE);
21875 if (((unsigned long) value) > 0x00ffffff)
21876 as_bad_where (fixP->fx_file, fixP->fx_line,
21877 _("invalid swi expression"));
21878 newval = md_chars_to_number (buf, INSN_SIZE);
21880 md_number_to_chars (buf, newval, INSN_SIZE);
21884 case BFD_RELOC_ARM_MULTI:
21885 if (((unsigned long) value) > 0xffff)
21886 as_bad_where (fixP->fx_file, fixP->fx_line,
21887 _("invalid expression in load/store multiple"));
21888 newval = value | md_chars_to_number (buf, INSN_SIZE);
21889 md_number_to_chars (buf, newval, INSN_SIZE);
21893 case BFD_RELOC_ARM_PCREL_CALL:
21895 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21897 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21898 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21899 && THUMB_IS_FUNC (fixP->fx_addsy))
21900 /* Flip the bl to blx. This is a simple flip
21901 bit here because we generate PCREL_CALL for
21902 unconditional bls. */
21904 newval = md_chars_to_number (buf, INSN_SIZE);
21905 newval = newval | 0x10000000;
21906 md_number_to_chars (buf, newval, INSN_SIZE);
21912 goto arm_branch_common;
21914 case BFD_RELOC_ARM_PCREL_JUMP:
21915 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21917 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21918 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21919 && THUMB_IS_FUNC (fixP->fx_addsy))
21921 /* This would map to a bl<cond>, b<cond>,
21922 b<always> to a Thumb function. We
21923 need to force a relocation for this particular
21925 newval = md_chars_to_number (buf, INSN_SIZE);
21929 case BFD_RELOC_ARM_PLT32:
21931 case BFD_RELOC_ARM_PCREL_BRANCH:
21933 goto arm_branch_common;
21935 case BFD_RELOC_ARM_PCREL_BLX:
21938 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21940 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21941 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21942 && ARM_IS_FUNC (fixP->fx_addsy))
21944 /* Flip the blx to a bl and warn. */
21945 const char *name = S_GET_NAME (fixP->fx_addsy);
21946 newval = 0xeb000000;
21947 as_warn_where (fixP->fx_file, fixP->fx_line,
21948 _("blx to '%s' an ARM ISA state function changed to bl"),
21950 md_number_to_chars (buf, newval, INSN_SIZE);
21956 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21957 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21961 /* We are going to store value (shifted right by two) in the
21962 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21963 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21964 also be be clear. */
21966 as_bad_where (fixP->fx_file, fixP->fx_line,
21967 _("misaligned branch destination"));
21968 if ((value & (offsetT)0xfe000000) != (offsetT)0
21969 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21970 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21972 if (fixP->fx_done || !seg->use_rela_p)
21974 newval = md_chars_to_number (buf, INSN_SIZE);
21975 newval |= (value >> 2) & 0x00ffffff;
21976 /* Set the H bit on BLX instructions. */
21980 newval |= 0x01000000;
21982 newval &= ~0x01000000;
21984 md_number_to_chars (buf, newval, INSN_SIZE);
21988 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21989 /* CBZ can only branch forward. */
21991 /* Attempts to use CBZ to branch to the next instruction
21992 (which, strictly speaking, are prohibited) will be turned into
21995 FIXME: It may be better to remove the instruction completely and
21996 perform relaxation. */
21999 newval = md_chars_to_number (buf, THUMB_SIZE);
22000 newval = 0xbf00; /* NOP encoding T1 */
22001 md_number_to_chars (buf, newval, THUMB_SIZE);
22006 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22008 if (fixP->fx_done || !seg->use_rela_p)
22010 newval = md_chars_to_number (buf, THUMB_SIZE);
22011 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22012 md_number_to_chars (buf, newval, THUMB_SIZE);
22017 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22018 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22019 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22021 if (fixP->fx_done || !seg->use_rela_p)
22023 newval = md_chars_to_number (buf, THUMB_SIZE);
22024 newval |= (value & 0x1ff) >> 1;
22025 md_number_to_chars (buf, newval, THUMB_SIZE);
22029 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22030 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22031 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22033 if (fixP->fx_done || !seg->use_rela_p)
22035 newval = md_chars_to_number (buf, THUMB_SIZE);
22036 newval |= (value & 0xfff) >> 1;
22037 md_number_to_chars (buf, newval, THUMB_SIZE);
22041 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22043 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22044 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22045 && ARM_IS_FUNC (fixP->fx_addsy)
22046 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22048 /* Force a relocation for a branch 20 bits wide. */
22051 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22052 as_bad_where (fixP->fx_file, fixP->fx_line,
22053 _("conditional branch out of range"));
22055 if (fixP->fx_done || !seg->use_rela_p)
22058 addressT S, J1, J2, lo, hi;
22060 S = (value & 0x00100000) >> 20;
22061 J2 = (value & 0x00080000) >> 19;
22062 J1 = (value & 0x00040000) >> 18;
22063 hi = (value & 0x0003f000) >> 12;
22064 lo = (value & 0x00000ffe) >> 1;
22066 newval = md_chars_to_number (buf, THUMB_SIZE);
22067 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22068 newval |= (S << 10) | hi;
22069 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22070 md_number_to_chars (buf, newval, THUMB_SIZE);
22071 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22075 case BFD_RELOC_THUMB_PCREL_BLX:
22076 /* If there is a blx from a thumb state function to
22077 another thumb function flip this to a bl and warn
22081 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22082 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22083 && THUMB_IS_FUNC (fixP->fx_addsy))
22085 const char *name = S_GET_NAME (fixP->fx_addsy);
22086 as_warn_where (fixP->fx_file, fixP->fx_line,
22087 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22089 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22090 newval = newval | 0x1000;
22091 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22092 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22097 goto thumb_bl_common;
22099 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22100 /* A bl from Thumb state ISA to an internal ARM state function
22101 is converted to a blx. */
22103 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22104 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22105 && ARM_IS_FUNC (fixP->fx_addsy)
22106 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22108 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22109 newval = newval & ~0x1000;
22110 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22111 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22117 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22118 /* For a BLX instruction, make sure that the relocation is rounded up
22119 to a word boundary. This follows the semantics of the instruction
22120 which specifies that bit 1 of the target address will come from bit
22121 1 of the base address. */
22122 value = (value + 3) & ~ 3;
22125 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22126 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22127 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22130 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22132 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22133 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22134 else if ((value & ~0x1ffffff)
22135 && ((value & ~0x1ffffff) != ~0x1ffffff))
22136 as_bad_where (fixP->fx_file, fixP->fx_line,
22137 _("Thumb2 branch out of range"));
22140 if (fixP->fx_done || !seg->use_rela_p)
22141 encode_thumb2_b_bl_offset (buf, value);
22145 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22146 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22147 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22149 if (fixP->fx_done || !seg->use_rela_p)
22150 encode_thumb2_b_bl_offset (buf, value);
22155 if (fixP->fx_done || !seg->use_rela_p)
22156 md_number_to_chars (buf, value, 1);
22160 if (fixP->fx_done || !seg->use_rela_p)
22161 md_number_to_chars (buf, value, 2);
22165 case BFD_RELOC_ARM_TLS_CALL:
22166 case BFD_RELOC_ARM_THM_TLS_CALL:
22167 case BFD_RELOC_ARM_TLS_DESCSEQ:
22168 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22169 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22172 case BFD_RELOC_ARM_TLS_GOTDESC:
22173 case BFD_RELOC_ARM_TLS_GD32:
22174 case BFD_RELOC_ARM_TLS_LE32:
22175 case BFD_RELOC_ARM_TLS_IE32:
22176 case BFD_RELOC_ARM_TLS_LDM32:
22177 case BFD_RELOC_ARM_TLS_LDO32:
22178 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22181 case BFD_RELOC_ARM_GOT32:
22182 case BFD_RELOC_ARM_GOTOFF:
22183 if (fixP->fx_done || !seg->use_rela_p)
22184 md_number_to_chars (buf, 0, 4);
22187 case BFD_RELOC_ARM_GOT_PREL:
22188 if (fixP->fx_done || !seg->use_rela_p)
22189 md_number_to_chars (buf, value, 4);
22192 case BFD_RELOC_ARM_TARGET2:
22193 /* TARGET2 is not partial-inplace, so we need to write the
22194 addend here for REL targets, because it won't be written out
22195 during reloc processing later. */
22196 if (fixP->fx_done || !seg->use_rela_p)
22197 md_number_to_chars (buf, fixP->fx_offset, 4);
22201 case BFD_RELOC_RVA:
22203 case BFD_RELOC_ARM_TARGET1:
22204 case BFD_RELOC_ARM_ROSEGREL32:
22205 case BFD_RELOC_ARM_SBREL32:
22206 case BFD_RELOC_32_PCREL:
22208 case BFD_RELOC_32_SECREL:
22210 if (fixP->fx_done || !seg->use_rela_p)
22212 /* For WinCE we only do this for pcrel fixups. */
22213 if (fixP->fx_done || fixP->fx_pcrel)
22215 md_number_to_chars (buf, value, 4);
22219 case BFD_RELOC_ARM_PREL31:
22220 if (fixP->fx_done || !seg->use_rela_p)
22222 newval = md_chars_to_number (buf, 4) & 0x80000000;
22223 if ((value ^ (value >> 1)) & 0x40000000)
22225 as_bad_where (fixP->fx_file, fixP->fx_line,
22226 _("rel31 relocation overflow"));
22228 newval |= value & 0x7fffffff;
22229 md_number_to_chars (buf, newval, 4);
22234 case BFD_RELOC_ARM_CP_OFF_IMM:
22235 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22236 if (value < -1023 || value > 1023 || (value & 3))
22237 as_bad_where (fixP->fx_file, fixP->fx_line,
22238 _("co-processor offset out of range"));
22243 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22244 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22245 newval = md_chars_to_number (buf, INSN_SIZE);
22247 newval = get_thumb32_insn (buf);
22249 newval &= 0xffffff00;
22252 newval &= 0xff7fff00;
22253 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22255 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22256 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22257 md_number_to_chars (buf, newval, INSN_SIZE);
22259 put_thumb32_insn (buf, newval);
22262 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22263 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22264 if (value < -255 || value > 255)
22265 as_bad_where (fixP->fx_file, fixP->fx_line,
22266 _("co-processor offset out of range"));
22268 goto cp_off_common;
22270 case BFD_RELOC_ARM_THUMB_OFFSET:
22271 newval = md_chars_to_number (buf, THUMB_SIZE);
22272 /* Exactly what ranges, and where the offset is inserted depends
22273 on the type of instruction, we can establish this from the
22275 switch (newval >> 12)
22277 case 4: /* PC load. */
22278 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22279 forced to zero for these loads; md_pcrel_from has already
22280 compensated for this. */
22282 as_bad_where (fixP->fx_file, fixP->fx_line,
22283 _("invalid offset, target not word aligned (0x%08lX)"),
22284 (((unsigned long) fixP->fx_frag->fr_address
22285 + (unsigned long) fixP->fx_where) & ~3)
22286 + (unsigned long) value);
22288 if (value & ~0x3fc)
22289 as_bad_where (fixP->fx_file, fixP->fx_line,
22290 _("invalid offset, value too big (0x%08lX)"),
22293 newval |= value >> 2;
22296 case 9: /* SP load/store. */
22297 if (value & ~0x3fc)
22298 as_bad_where (fixP->fx_file, fixP->fx_line,
22299 _("invalid offset, value too big (0x%08lX)"),
22301 newval |= value >> 2;
22304 case 6: /* Word load/store. */
22306 as_bad_where (fixP->fx_file, fixP->fx_line,
22307 _("invalid offset, value too big (0x%08lX)"),
22309 newval |= value << 4; /* 6 - 2. */
22312 case 7: /* Byte load/store. */
22314 as_bad_where (fixP->fx_file, fixP->fx_line,
22315 _("invalid offset, value too big (0x%08lX)"),
22317 newval |= value << 6;
22320 case 8: /* Halfword load/store. */
22322 as_bad_where (fixP->fx_file, fixP->fx_line,
22323 _("invalid offset, value too big (0x%08lX)"),
22325 newval |= value << 5; /* 6 - 1. */
22329 as_bad_where (fixP->fx_file, fixP->fx_line,
22330 "Unable to process relocation for thumb opcode: %lx",
22331 (unsigned long) newval);
22334 md_number_to_chars (buf, newval, THUMB_SIZE);
22337 case BFD_RELOC_ARM_THUMB_ADD:
22338 /* This is a complicated relocation, since we use it for all of
22339 the following immediate relocations:
22343 9bit ADD/SUB SP word-aligned
22344 10bit ADD PC/SP word-aligned
22346 The type of instruction being processed is encoded in the
22353 newval = md_chars_to_number (buf, THUMB_SIZE);
22355 int rd = (newval >> 4) & 0xf;
22356 int rs = newval & 0xf;
22357 int subtract = !!(newval & 0x8000);
22359 /* Check for HI regs, only very restricted cases allowed:
22360 Adjusting SP, and using PC or SP to get an address. */
22361 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22362 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22363 as_bad_where (fixP->fx_file, fixP->fx_line,
22364 _("invalid Hi register with immediate"));
22366 /* If value is negative, choose the opposite instruction. */
22370 subtract = !subtract;
22372 as_bad_where (fixP->fx_file, fixP->fx_line,
22373 _("immediate value out of range"));
22378 if (value & ~0x1fc)
22379 as_bad_where (fixP->fx_file, fixP->fx_line,
22380 _("invalid immediate for stack address calculation"));
22381 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22382 newval |= value >> 2;
22384 else if (rs == REG_PC || rs == REG_SP)
22386 if (subtract || value & ~0x3fc)
22387 as_bad_where (fixP->fx_file, fixP->fx_line,
22388 _("invalid immediate for address calculation (value = 0x%08lX)"),
22389 (unsigned long) value);
22390 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22392 newval |= value >> 2;
22397 as_bad_where (fixP->fx_file, fixP->fx_line,
22398 _("immediate value out of range"));
22399 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22400 newval |= (rd << 8) | value;
22405 as_bad_where (fixP->fx_file, fixP->fx_line,
22406 _("immediate value out of range"));
22407 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22408 newval |= rd | (rs << 3) | (value << 6);
22411 md_number_to_chars (buf, newval, THUMB_SIZE);
22414 case BFD_RELOC_ARM_THUMB_IMM:
22415 newval = md_chars_to_number (buf, THUMB_SIZE);
22416 if (value < 0 || value > 255)
22417 as_bad_where (fixP->fx_file, fixP->fx_line,
22418 _("invalid immediate: %ld is out of range"),
22421 md_number_to_chars (buf, newval, THUMB_SIZE);
22424 case BFD_RELOC_ARM_THUMB_SHIFT:
22425 /* 5bit shift value (0..32). LSL cannot take 32. */
22426 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22427 temp = newval & 0xf800;
22428 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22429 as_bad_where (fixP->fx_file, fixP->fx_line,
22430 _("invalid shift value: %ld"), (long) value);
22431 /* Shifts of zero must be encoded as LSL. */
22433 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22434 /* Shifts of 32 are encoded as zero. */
22435 else if (value == 32)
22437 newval |= value << 6;
22438 md_number_to_chars (buf, newval, THUMB_SIZE);
22441 case BFD_RELOC_VTABLE_INHERIT:
22442 case BFD_RELOC_VTABLE_ENTRY:
22446 case BFD_RELOC_ARM_MOVW:
22447 case BFD_RELOC_ARM_MOVT:
22448 case BFD_RELOC_ARM_THUMB_MOVW:
22449 case BFD_RELOC_ARM_THUMB_MOVT:
22450 if (fixP->fx_done || !seg->use_rela_p)
22452 /* REL format relocations are limited to a 16-bit addend. */
22453 if (!fixP->fx_done)
22455 if (value < -0x8000 || value > 0x7fff)
22456 as_bad_where (fixP->fx_file, fixP->fx_line,
22457 _("offset out of range"));
22459 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22460 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22465 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22466 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22468 newval = get_thumb32_insn (buf);
22469 newval &= 0xfbf08f00;
22470 newval |= (value & 0xf000) << 4;
22471 newval |= (value & 0x0800) << 15;
22472 newval |= (value & 0x0700) << 4;
22473 newval |= (value & 0x00ff);
22474 put_thumb32_insn (buf, newval);
22478 newval = md_chars_to_number (buf, 4);
22479 newval &= 0xfff0f000;
22480 newval |= value & 0x0fff;
22481 newval |= (value & 0xf000) << 4;
22482 md_number_to_chars (buf, newval, 4);
22487 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22488 case BFD_RELOC_ARM_ALU_PC_G0:
22489 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22490 case BFD_RELOC_ARM_ALU_PC_G1:
22491 case BFD_RELOC_ARM_ALU_PC_G2:
22492 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22493 case BFD_RELOC_ARM_ALU_SB_G0:
22494 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22495 case BFD_RELOC_ARM_ALU_SB_G1:
22496 case BFD_RELOC_ARM_ALU_SB_G2:
22497 gas_assert (!fixP->fx_done);
22498 if (!seg->use_rela_p)
22501 bfd_vma encoded_addend;
22502 bfd_vma addend_abs = abs (value);
22504 /* Check that the absolute value of the addend can be
22505 expressed as an 8-bit constant plus a rotation. */
22506 encoded_addend = encode_arm_immediate (addend_abs);
22507 if (encoded_addend == (unsigned int) FAIL)
22508 as_bad_where (fixP->fx_file, fixP->fx_line,
22509 _("the offset 0x%08lX is not representable"),
22510 (unsigned long) addend_abs);
22512 /* Extract the instruction. */
22513 insn = md_chars_to_number (buf, INSN_SIZE);
22515 /* If the addend is positive, use an ADD instruction.
22516 Otherwise use a SUB. Take care not to destroy the S bit. */
22517 insn &= 0xff1fffff;
22523 /* Place the encoded addend into the first 12 bits of the
22525 insn &= 0xfffff000;
22526 insn |= encoded_addend;
22528 /* Update the instruction. */
22529 md_number_to_chars (buf, insn, INSN_SIZE);
22533 case BFD_RELOC_ARM_LDR_PC_G0:
22534 case BFD_RELOC_ARM_LDR_PC_G1:
22535 case BFD_RELOC_ARM_LDR_PC_G2:
22536 case BFD_RELOC_ARM_LDR_SB_G0:
22537 case BFD_RELOC_ARM_LDR_SB_G1:
22538 case BFD_RELOC_ARM_LDR_SB_G2:
22539 gas_assert (!fixP->fx_done);
22540 if (!seg->use_rela_p)
22543 bfd_vma addend_abs = abs (value);
22545 /* Check that the absolute value of the addend can be
22546 encoded in 12 bits. */
22547 if (addend_abs >= 0x1000)
22548 as_bad_where (fixP->fx_file, fixP->fx_line,
22549 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22550 (unsigned long) addend_abs);
22552 /* Extract the instruction. */
22553 insn = md_chars_to_number (buf, INSN_SIZE);
22555 /* If the addend is negative, clear bit 23 of the instruction.
22556 Otherwise set it. */
22558 insn &= ~(1 << 23);
22562 /* Place the absolute value of the addend into the first 12 bits
22563 of the instruction. */
22564 insn &= 0xfffff000;
22565 insn |= addend_abs;
22567 /* Update the instruction. */
22568 md_number_to_chars (buf, insn, INSN_SIZE);
22572 case BFD_RELOC_ARM_LDRS_PC_G0:
22573 case BFD_RELOC_ARM_LDRS_PC_G1:
22574 case BFD_RELOC_ARM_LDRS_PC_G2:
22575 case BFD_RELOC_ARM_LDRS_SB_G0:
22576 case BFD_RELOC_ARM_LDRS_SB_G1:
22577 case BFD_RELOC_ARM_LDRS_SB_G2:
22578 gas_assert (!fixP->fx_done);
22579 if (!seg->use_rela_p)
22582 bfd_vma addend_abs = abs (value);
22584 /* Check that the absolute value of the addend can be
22585 encoded in 8 bits. */
22586 if (addend_abs >= 0x100)
22587 as_bad_where (fixP->fx_file, fixP->fx_line,
22588 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22589 (unsigned long) addend_abs);
22591 /* Extract the instruction. */
22592 insn = md_chars_to_number (buf, INSN_SIZE);
22594 /* If the addend is negative, clear bit 23 of the instruction.
22595 Otherwise set it. */
22597 insn &= ~(1 << 23);
22601 /* Place the first four bits of the absolute value of the addend
22602 into the first 4 bits of the instruction, and the remaining
22603 four into bits 8 .. 11. */
22604 insn &= 0xfffff0f0;
22605 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22607 /* Update the instruction. */
22608 md_number_to_chars (buf, insn, INSN_SIZE);
22612 case BFD_RELOC_ARM_LDC_PC_G0:
22613 case BFD_RELOC_ARM_LDC_PC_G1:
22614 case BFD_RELOC_ARM_LDC_PC_G2:
22615 case BFD_RELOC_ARM_LDC_SB_G0:
22616 case BFD_RELOC_ARM_LDC_SB_G1:
22617 case BFD_RELOC_ARM_LDC_SB_G2:
22618 gas_assert (!fixP->fx_done);
22619 if (!seg->use_rela_p)
22622 bfd_vma addend_abs = abs (value);
22624 /* Check that the absolute value of the addend is a multiple of
22625 four and, when divided by four, fits in 8 bits. */
22626 if (addend_abs & 0x3)
22627 as_bad_where (fixP->fx_file, fixP->fx_line,
22628 _("bad offset 0x%08lX (must be word-aligned)"),
22629 (unsigned long) addend_abs);
22631 if ((addend_abs >> 2) > 0xff)
22632 as_bad_where (fixP->fx_file, fixP->fx_line,
22633 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22634 (unsigned long) addend_abs);
22636 /* Extract the instruction. */
22637 insn = md_chars_to_number (buf, INSN_SIZE);
22639 /* If the addend is negative, clear bit 23 of the instruction.
22640 Otherwise set it. */
22642 insn &= ~(1 << 23);
22646 /* Place the addend (divided by four) into the first eight
22647 bits of the instruction. */
22648 insn &= 0xfffffff0;
22649 insn |= addend_abs >> 2;
22651 /* Update the instruction. */
22652 md_number_to_chars (buf, insn, INSN_SIZE);
22656 case BFD_RELOC_ARM_V4BX:
22657 /* This will need to go in the object file. */
22661 case BFD_RELOC_UNUSED:
22663 as_bad_where (fixP->fx_file, fixP->fx_line,
22664 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22668 /* Translate internal representation of relocation info to BFD target
22672 tc_gen_reloc (asection *section, fixS *fixp)
22675 bfd_reloc_code_real_type code;
22677 reloc = (arelent *) xmalloc (sizeof (arelent));
22679 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
22680 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22681 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
22683 if (fixp->fx_pcrel)
22685 if (section->use_rela_p)
22686 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22688 fixp->fx_offset = reloc->address;
22690 reloc->addend = fixp->fx_offset;
22692 switch (fixp->fx_r_type)
22695 if (fixp->fx_pcrel)
22697 code = BFD_RELOC_8_PCREL;
22702 if (fixp->fx_pcrel)
22704 code = BFD_RELOC_16_PCREL;
22709 if (fixp->fx_pcrel)
22711 code = BFD_RELOC_32_PCREL;
22715 case BFD_RELOC_ARM_MOVW:
22716 if (fixp->fx_pcrel)
22718 code = BFD_RELOC_ARM_MOVW_PCREL;
22722 case BFD_RELOC_ARM_MOVT:
22723 if (fixp->fx_pcrel)
22725 code = BFD_RELOC_ARM_MOVT_PCREL;
22729 case BFD_RELOC_ARM_THUMB_MOVW:
22730 if (fixp->fx_pcrel)
22732 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22736 case BFD_RELOC_ARM_THUMB_MOVT:
22737 if (fixp->fx_pcrel)
22739 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22743 case BFD_RELOC_NONE:
22744 case BFD_RELOC_ARM_PCREL_BRANCH:
22745 case BFD_RELOC_ARM_PCREL_BLX:
22746 case BFD_RELOC_RVA:
22747 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22748 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22749 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22750 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22751 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22752 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22753 case BFD_RELOC_VTABLE_ENTRY:
22754 case BFD_RELOC_VTABLE_INHERIT:
22756 case BFD_RELOC_32_SECREL:
22758 code = fixp->fx_r_type;
22761 case BFD_RELOC_THUMB_PCREL_BLX:
22763 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22764 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22767 code = BFD_RELOC_THUMB_PCREL_BLX;
22770 case BFD_RELOC_ARM_LITERAL:
22771 case BFD_RELOC_ARM_HWLITERAL:
22772 /* If this is called then the a literal has
22773 been referenced across a section boundary. */
22774 as_bad_where (fixp->fx_file, fixp->fx_line,
22775 _("literal referenced across section boundary"));
22779 case BFD_RELOC_ARM_TLS_CALL:
22780 case BFD_RELOC_ARM_THM_TLS_CALL:
22781 case BFD_RELOC_ARM_TLS_DESCSEQ:
22782 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22783 case BFD_RELOC_ARM_GOT32:
22784 case BFD_RELOC_ARM_GOTOFF:
22785 case BFD_RELOC_ARM_GOT_PREL:
22786 case BFD_RELOC_ARM_PLT32:
22787 case BFD_RELOC_ARM_TARGET1:
22788 case BFD_RELOC_ARM_ROSEGREL32:
22789 case BFD_RELOC_ARM_SBREL32:
22790 case BFD_RELOC_ARM_PREL31:
22791 case BFD_RELOC_ARM_TARGET2:
22792 case BFD_RELOC_ARM_TLS_LE32:
22793 case BFD_RELOC_ARM_TLS_LDO32:
22794 case BFD_RELOC_ARM_PCREL_CALL:
22795 case BFD_RELOC_ARM_PCREL_JUMP:
22796 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22797 case BFD_RELOC_ARM_ALU_PC_G0:
22798 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22799 case BFD_RELOC_ARM_ALU_PC_G1:
22800 case BFD_RELOC_ARM_ALU_PC_G2:
22801 case BFD_RELOC_ARM_LDR_PC_G0:
22802 case BFD_RELOC_ARM_LDR_PC_G1:
22803 case BFD_RELOC_ARM_LDR_PC_G2:
22804 case BFD_RELOC_ARM_LDRS_PC_G0:
22805 case BFD_RELOC_ARM_LDRS_PC_G1:
22806 case BFD_RELOC_ARM_LDRS_PC_G2:
22807 case BFD_RELOC_ARM_LDC_PC_G0:
22808 case BFD_RELOC_ARM_LDC_PC_G1:
22809 case BFD_RELOC_ARM_LDC_PC_G2:
22810 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22811 case BFD_RELOC_ARM_ALU_SB_G0:
22812 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22813 case BFD_RELOC_ARM_ALU_SB_G1:
22814 case BFD_RELOC_ARM_ALU_SB_G2:
22815 case BFD_RELOC_ARM_LDR_SB_G0:
22816 case BFD_RELOC_ARM_LDR_SB_G1:
22817 case BFD_RELOC_ARM_LDR_SB_G2:
22818 case BFD_RELOC_ARM_LDRS_SB_G0:
22819 case BFD_RELOC_ARM_LDRS_SB_G1:
22820 case BFD_RELOC_ARM_LDRS_SB_G2:
22821 case BFD_RELOC_ARM_LDC_SB_G0:
22822 case BFD_RELOC_ARM_LDC_SB_G1:
22823 case BFD_RELOC_ARM_LDC_SB_G2:
22824 case BFD_RELOC_ARM_V4BX:
22825 code = fixp->fx_r_type;
22828 case BFD_RELOC_ARM_TLS_GOTDESC:
22829 case BFD_RELOC_ARM_TLS_GD32:
22830 case BFD_RELOC_ARM_TLS_IE32:
22831 case BFD_RELOC_ARM_TLS_LDM32:
22832 /* BFD will include the symbol's address in the addend.
22833 But we don't want that, so subtract it out again here. */
22834 if (!S_IS_COMMON (fixp->fx_addsy))
22835 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22836 code = fixp->fx_r_type;
22840 case BFD_RELOC_ARM_IMMEDIATE:
22841 as_bad_where (fixp->fx_file, fixp->fx_line,
22842 _("internal relocation (type: IMMEDIATE) not fixed up"));
22845 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22846 as_bad_where (fixp->fx_file, fixp->fx_line,
22847 _("ADRL used for a symbol not defined in the same file"));
22850 case BFD_RELOC_ARM_OFFSET_IMM:
22851 if (section->use_rela_p)
22853 code = fixp->fx_r_type;
22857 if (fixp->fx_addsy != NULL
22858 && !S_IS_DEFINED (fixp->fx_addsy)
22859 && S_IS_LOCAL (fixp->fx_addsy))
22861 as_bad_where (fixp->fx_file, fixp->fx_line,
22862 _("undefined local label `%s'"),
22863 S_GET_NAME (fixp->fx_addsy));
22867 as_bad_where (fixp->fx_file, fixp->fx_line,
22868 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22875 switch (fixp->fx_r_type)
22877 case BFD_RELOC_NONE: type = "NONE"; break;
22878 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22879 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
22880 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
22881 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22882 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22883 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
22884 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
22885 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
22886 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22887 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22888 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22889 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22890 default: type = _("<unknown>"); break;
22892 as_bad_where (fixp->fx_file, fixp->fx_line,
22893 _("cannot represent %s relocation in this object file format"),
22900 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22902 && fixp->fx_addsy == GOT_symbol)
22904 code = BFD_RELOC_ARM_GOTPC;
22905 reloc->addend = fixp->fx_offset = reloc->address;
22909 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
22911 if (reloc->howto == NULL)
22913 as_bad_where (fixp->fx_file, fixp->fx_line,
22914 _("cannot represent %s relocation in this object file format"),
22915 bfd_get_reloc_code_name (code));
22919 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22920 vtable entry to be used in the relocation's section offset. */
22921 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22922 reloc->address = fixp->fx_offset;
22927 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
22930 cons_fix_new_arm (fragS * frag,
22935 bfd_reloc_code_real_type type;
22939 FIXME: @@ Should look at CPU word size. */
22943 type = BFD_RELOC_8;
22946 type = BFD_RELOC_16;
22950 type = BFD_RELOC_32;
22953 type = BFD_RELOC_64;
22958 if (exp->X_op == O_secrel)
22960 exp->X_op = O_symbol;
22961 type = BFD_RELOC_32_SECREL;
22965 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22968 #if defined (OBJ_COFF)
22970 arm_validate_fix (fixS * fixP)
22972 /* If the destination of the branch is a defined symbol which does not have
22973 the THUMB_FUNC attribute, then we must be calling a function which has
22974 the (interfacearm) attribute. We look for the Thumb entry point to that
22975 function and change the branch to refer to that function instead. */
22976 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22977 && fixP->fx_addsy != NULL
22978 && S_IS_DEFINED (fixP->fx_addsy)
22979 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22981 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22988 arm_force_relocation (struct fix * fixp)
22990 #if defined (OBJ_COFF) && defined (TE_PE)
22991 if (fixp->fx_r_type == BFD_RELOC_RVA)
22995 /* In case we have a call or a branch to a function in ARM ISA mode from
22996 a thumb function or vice-versa force the relocation. These relocations
22997 are cleared off for some cores that might have blx and simple transformations
23001 switch (fixp->fx_r_type)
23003 case BFD_RELOC_ARM_PCREL_JUMP:
23004 case BFD_RELOC_ARM_PCREL_CALL:
23005 case BFD_RELOC_THUMB_PCREL_BLX:
23006 if (THUMB_IS_FUNC (fixp->fx_addsy))
23010 case BFD_RELOC_ARM_PCREL_BLX:
23011 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23012 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23013 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23014 if (ARM_IS_FUNC (fixp->fx_addsy))
23023 /* Resolve these relocations even if the symbol is extern or weak.
23024 Technically this is probably wrong due to symbol preemption.
23025 In practice these relocations do not have enough range to be useful
23026 at dynamic link time, and some code (e.g. in the Linux kernel)
23027 expects these references to be resolved. */
23028 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23029 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23030 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23031 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23032 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23033 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23034 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23035 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23036 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23037 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23038 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23039 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23040 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23041 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23044 /* Always leave these relocations for the linker. */
23045 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23046 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23047 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23050 /* Always generate relocations against function symbols. */
23051 if (fixp->fx_r_type == BFD_RELOC_32
23053 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23056 return generic_force_reloc (fixp);
23059 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23060 /* Relocations against function names must be left unadjusted,
23061 so that the linker can use this information to generate interworking
23062 stubs. The MIPS version of this function
23063 also prevents relocations that are mips-16 specific, but I do not
23064 know why it does this.
23067 There is one other problem that ought to be addressed here, but
23068 which currently is not: Taking the address of a label (rather
23069 than a function) and then later jumping to that address. Such
23070 addresses also ought to have their bottom bit set (assuming that
23071 they reside in Thumb code), but at the moment they will not. */
23074 arm_fix_adjustable (fixS * fixP)
23076 if (fixP->fx_addsy == NULL)
23079 /* Preserve relocations against symbols with function type. */
23080 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23083 if (THUMB_IS_FUNC (fixP->fx_addsy)
23084 && fixP->fx_subsy == NULL)
23087 /* We need the symbol name for the VTABLE entries. */
23088 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23089 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23092 /* Don't allow symbols to be discarded on GOT related relocs. */
23093 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23094 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23095 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23096 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23097 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23098 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23099 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23100 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23101 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23102 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23103 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23104 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23105 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23106 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23109 /* Similarly for group relocations. */
23110 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23111 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23112 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23115 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23116 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23117 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23118 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23119 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23120 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23121 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23122 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23123 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23128 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23133 elf32_arm_target_format (void)
23136 return (target_big_endian
23137 ? "elf32-bigarm-symbian"
23138 : "elf32-littlearm-symbian");
23139 #elif defined (TE_VXWORKS)
23140 return (target_big_endian
23141 ? "elf32-bigarm-vxworks"
23142 : "elf32-littlearm-vxworks");
23143 #elif defined (TE_NACL)
23144 return (target_big_endian
23145 ? "elf32-bigarm-nacl"
23146 : "elf32-littlearm-nacl");
23148 if (target_big_endian)
23149 return "elf32-bigarm";
23151 return "elf32-littlearm";
23156 armelf_frob_symbol (symbolS * symp,
23159 elf_frob_symbol (symp, puntp);
23163 /* MD interface: Finalization. */
23168 literal_pool * pool;
23170 /* Ensure that all the IT blocks are properly closed. */
23171 check_it_blocks_finished ();
23173 for (pool = list_of_pools; pool; pool = pool->next)
23175 /* Put it at the end of the relevant section. */
23176 subseg_set (pool->section, pool->sub_section);
23178 arm_elf_change_section ();
23185 /* Remove any excess mapping symbols generated for alignment frags in
23186 SEC. We may have created a mapping symbol before a zero byte
23187 alignment; remove it if there's a mapping symbol after the
23190 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23191 void *dummy ATTRIBUTE_UNUSED)
23193 segment_info_type *seginfo = seg_info (sec);
23196 if (seginfo == NULL || seginfo->frchainP == NULL)
23199 for (fragp = seginfo->frchainP->frch_root;
23201 fragp = fragp->fr_next)
23203 symbolS *sym = fragp->tc_frag_data.last_map;
23204 fragS *next = fragp->fr_next;
23206 /* Variable-sized frags have been converted to fixed size by
23207 this point. But if this was variable-sized to start with,
23208 there will be a fixed-size frag after it. So don't handle
23210 if (sym == NULL || next == NULL)
23213 if (S_GET_VALUE (sym) < next->fr_address)
23214 /* Not at the end of this frag. */
23216 know (S_GET_VALUE (sym) == next->fr_address);
23220 if (next->tc_frag_data.first_map != NULL)
23222 /* Next frag starts with a mapping symbol. Discard this
23224 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23228 if (next->fr_next == NULL)
23230 /* This mapping symbol is at the end of the section. Discard
23232 know (next->fr_fix == 0 && next->fr_var == 0);
23233 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23237 /* As long as we have empty frags without any mapping symbols,
23239 /* If the next frag is non-empty and does not start with a
23240 mapping symbol, then this mapping symbol is required. */
23241 if (next->fr_address != next->fr_next->fr_address)
23244 next = next->fr_next;
23246 while (next != NULL);
23251 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23255 arm_adjust_symtab (void)
23260 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23262 if (ARM_IS_THUMB (sym))
23264 if (THUMB_IS_FUNC (sym))
23266 /* Mark the symbol as a Thumb function. */
23267 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23268 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23269 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23271 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23272 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23274 as_bad (_("%s: unexpected function type: %d"),
23275 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23277 else switch (S_GET_STORAGE_CLASS (sym))
23280 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23283 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23286 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23294 if (ARM_IS_INTERWORK (sym))
23295 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
23302 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23304 if (ARM_IS_THUMB (sym))
23306 elf_symbol_type * elf_sym;
23308 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23309 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
23311 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23312 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
23314 /* If it's a .thumb_func, declare it as so,
23315 otherwise tag label as .code 16. */
23316 if (THUMB_IS_FUNC (sym))
23317 elf_sym->internal_elf_sym.st_target_internal
23318 = ST_BRANCH_TO_THUMB;
23319 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23320 elf_sym->internal_elf_sym.st_info =
23321 ELF_ST_INFO (bind, STT_ARM_16BIT);
23326 /* Remove any overlapping mapping symbols generated by alignment frags. */
23327 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
23328 /* Now do generic ELF adjustments. */
23329 elf_adjust_symtab ();
23333 /* MD interface: Initialization. */
23336 set_constant_flonums (void)
23340 for (i = 0; i < NUM_FLOAT_VALS; i++)
23341 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23345 /* Auto-select Thumb mode if it's the only available instruction set for the
23346 given architecture. */
23349 autoselect_thumb_from_cpu_variant (void)
23351 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23352 opcode_select (16);
23361 if ( (arm_ops_hsh = hash_new ()) == NULL
23362 || (arm_cond_hsh = hash_new ()) == NULL
23363 || (arm_shift_hsh = hash_new ()) == NULL
23364 || (arm_psr_hsh = hash_new ()) == NULL
23365 || (arm_v7m_psr_hsh = hash_new ()) == NULL
23366 || (arm_reg_hsh = hash_new ()) == NULL
23367 || (arm_reloc_hsh = hash_new ()) == NULL
23368 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
23369 as_fatal (_("virtual memory exhausted"));
23371 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
23372 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
23373 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
23374 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
23375 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
23376 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
23377 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
23378 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
23379 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
23380 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
23381 (void *) (v7m_psrs + i));
23382 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
23383 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
23385 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23387 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
23388 (void *) (barrier_opt_names + i));
23390 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23392 struct reloc_entry * entry = reloc_names + i;
23394 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23395 /* This makes encode_branch() use the EABI versions of this relocation. */
23396 entry->reloc = BFD_RELOC_UNUSED;
23398 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23402 set_constant_flonums ();
23404 /* Set the cpu variant based on the command-line options. We prefer
23405 -mcpu= over -march= if both are set (as for GCC); and we prefer
23406 -mfpu= over any other way of setting the floating point unit.
23407 Use of legacy options with new options are faulted. */
23410 if (mcpu_cpu_opt || march_cpu_opt)
23411 as_bad (_("use of old and new-style options to set CPU type"));
23413 mcpu_cpu_opt = legacy_cpu;
23415 else if (!mcpu_cpu_opt)
23416 mcpu_cpu_opt = march_cpu_opt;
23421 as_bad (_("use of old and new-style options to set FPU type"));
23423 mfpu_opt = legacy_fpu;
23425 else if (!mfpu_opt)
23427 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23428 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23429 /* Some environments specify a default FPU. If they don't, infer it
23430 from the processor. */
23432 mfpu_opt = mcpu_fpu_opt;
23434 mfpu_opt = march_fpu_opt;
23436 mfpu_opt = &fpu_default;
23442 if (mcpu_cpu_opt != NULL)
23443 mfpu_opt = &fpu_default;
23444 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
23445 mfpu_opt = &fpu_arch_vfp_v2;
23447 mfpu_opt = &fpu_arch_fpa;
23453 mcpu_cpu_opt = &cpu_default;
23454 selected_cpu = cpu_default;
23458 selected_cpu = *mcpu_cpu_opt;
23460 mcpu_cpu_opt = &arm_arch_any;
23463 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23465 autoselect_thumb_from_cpu_variant ();
23467 arm_arch_used = thumb_arch_used = arm_arch_none;
23469 #if defined OBJ_COFF || defined OBJ_ELF
23471 unsigned int flags = 0;
23473 #if defined OBJ_ELF
23474 flags = meabi_flags;
23476 switch (meabi_flags)
23478 case EF_ARM_EABI_UNKNOWN:
23480 /* Set the flags in the private structure. */
23481 if (uses_apcs_26) flags |= F_APCS26;
23482 if (support_interwork) flags |= F_INTERWORK;
23483 if (uses_apcs_float) flags |= F_APCS_FLOAT;
23484 if (pic_code) flags |= F_PIC;
23485 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
23486 flags |= F_SOFT_FLOAT;
23488 switch (mfloat_abi_opt)
23490 case ARM_FLOAT_ABI_SOFT:
23491 case ARM_FLOAT_ABI_SOFTFP:
23492 flags |= F_SOFT_FLOAT;
23495 case ARM_FLOAT_ABI_HARD:
23496 if (flags & F_SOFT_FLOAT)
23497 as_bad (_("hard-float conflicts with specified fpu"));
23501 /* Using pure-endian doubles (even if soft-float). */
23502 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
23503 flags |= F_VFP_FLOAT;
23505 #if defined OBJ_ELF
23506 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
23507 flags |= EF_ARM_MAVERICK_FLOAT;
23510 case EF_ARM_EABI_VER4:
23511 case EF_ARM_EABI_VER5:
23512 /* No additional flags to set. */
23519 bfd_set_private_flags (stdoutput, flags);
23521 /* We have run out flags in the COFF header to encode the
23522 status of ATPCS support, so instead we create a dummy,
23523 empty, debug section called .arm.atpcs. */
23528 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23532 bfd_set_section_flags
23533 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23534 bfd_set_section_size (stdoutput, sec, 0);
23535 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23541 /* Record the CPU type as well. */
23542 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23543 mach = bfd_mach_arm_iWMMXt2;
23544 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
23545 mach = bfd_mach_arm_iWMMXt;
23546 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
23547 mach = bfd_mach_arm_XScale;
23548 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
23549 mach = bfd_mach_arm_ep9312;
23550 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
23551 mach = bfd_mach_arm_5TE;
23552 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
23554 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23555 mach = bfd_mach_arm_5T;
23557 mach = bfd_mach_arm_5;
23559 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
23561 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
23562 mach = bfd_mach_arm_4T;
23564 mach = bfd_mach_arm_4;
23566 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
23567 mach = bfd_mach_arm_3M;
23568 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23569 mach = bfd_mach_arm_3;
23570 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23571 mach = bfd_mach_arm_2a;
23572 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23573 mach = bfd_mach_arm_2;
23575 mach = bfd_mach_arm_unknown;
23577 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23580 /* Command line processing. */
23583 Invocation line includes a switch not recognized by the base assembler.
23584 See if it's a processor-specific option.
23586 This routine is somewhat complicated by the need for backwards
23587 compatibility (since older releases of gcc can't be changed).
23588 The new options try to make the interface as compatible as
23591 New options (supported) are:
23593 -mcpu=<cpu name> Assemble for selected processor
23594 -march=<architecture name> Assemble for selected architecture
23595 -mfpu=<fpu architecture> Assemble for selected FPU.
23596 -EB/-mbig-endian Big-endian
23597 -EL/-mlittle-endian Little-endian
23598 -k Generate PIC code
23599 -mthumb Start in Thumb mode
23600 -mthumb-interwork Code supports ARM/Thumb interworking
23602 -m[no-]warn-deprecated Warn about deprecated features
23604 For now we will also provide support for:
23606 -mapcs-32 32-bit Program counter
23607 -mapcs-26 26-bit Program counter
23608 -macps-float Floats passed in FP registers
23609 -mapcs-reentrant Reentrant code
23611 (sometime these will probably be replaced with -mapcs=<list of options>
23612 and -matpcs=<list of options>)
23614 The remaining options are only supported for back-wards compatibility.
23615 Cpu variants, the arm part is optional:
23616 -m[arm]1 Currently not supported.
23617 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23618 -m[arm]3 Arm 3 processor
23619 -m[arm]6[xx], Arm 6 processors
23620 -m[arm]7[xx][t][[d]m] Arm 7 processors
23621 -m[arm]8[10] Arm 8 processors
23622 -m[arm]9[20][tdmi] Arm 9 processors
23623 -mstrongarm[110[0]] StrongARM processors
23624 -mxscale XScale processors
23625 -m[arm]v[2345[t[e]]] Arm architectures
23626 -mall All (except the ARM1)
23628 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23629 -mfpe-old (No float load/store multiples)
23630 -mvfpxd VFP Single precision
23632 -mno-fpu Disable all floating point instructions
23634 The following CPU names are recognized:
23635 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23636 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23637 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23638 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23639 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23640 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23641 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23645 const char * md_shortopts = "m:k";
23647 #ifdef ARM_BI_ENDIAN
23648 #define OPTION_EB (OPTION_MD_BASE + 0)
23649 #define OPTION_EL (OPTION_MD_BASE + 1)
23651 #if TARGET_BYTES_BIG_ENDIAN
23652 #define OPTION_EB (OPTION_MD_BASE + 0)
23654 #define OPTION_EL (OPTION_MD_BASE + 1)
23657 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23659 struct option md_longopts[] =
23662 {"EB", no_argument, NULL, OPTION_EB},
23665 {"EL", no_argument, NULL, OPTION_EL},
23667 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
23668 {NULL, no_argument, NULL, 0}
23671 size_t md_longopts_size = sizeof (md_longopts);
23673 struct arm_option_table
23675 char *option; /* Option name to match. */
23676 char *help; /* Help information. */
23677 int *var; /* Variable to change. */
23678 int value; /* What to change it to. */
23679 char *deprecated; /* If non-null, print this message. */
23682 struct arm_option_table arm_opts[] =
23684 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23685 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23686 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23687 &support_interwork, 1, NULL},
23688 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23689 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23690 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23692 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23693 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23694 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23695 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23698 /* These are recognized by the assembler, but have no affect on code. */
23699 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23700 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
23702 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23703 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23704 &warn_on_deprecated, 0, NULL},
23705 {NULL, NULL, NULL, 0, NULL}
23708 struct arm_legacy_option_table
23710 char *option; /* Option name to match. */
23711 const arm_feature_set **var; /* Variable to change. */
23712 const arm_feature_set value; /* What to change it to. */
23713 char *deprecated; /* If non-null, print this message. */
23716 const struct arm_legacy_option_table arm_legacy_opts[] =
23718 /* DON'T add any new processors to this list -- we want the whole list
23719 to go away... Add them to the processors table instead. */
23720 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23721 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23722 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23723 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23724 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23725 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23726 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23727 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23728 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23729 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23730 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23731 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23732 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23733 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23734 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23735 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23736 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23737 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23738 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23739 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23740 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23741 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23742 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23743 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23744 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23745 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23746 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23747 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23748 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23749 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23750 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23751 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23752 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23753 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23754 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23755 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23756 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23757 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23758 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23759 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23760 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23761 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23762 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23763 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23764 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23765 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23766 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23767 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23768 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23769 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23770 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23771 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23772 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23773 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23774 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23775 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23776 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23777 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23778 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23779 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23780 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23781 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23782 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23783 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23784 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23785 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23786 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23787 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23788 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23789 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
23790 N_("use -mcpu=strongarm110")},
23791 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
23792 N_("use -mcpu=strongarm1100")},
23793 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
23794 N_("use -mcpu=strongarm1110")},
23795 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23796 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23797 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
23799 /* Architecture variants -- don't add any more to this list either. */
23800 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23801 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23802 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23803 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23804 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23805 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23806 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23807 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23808 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23809 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23810 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23811 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23812 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23813 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23814 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23815 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23816 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23817 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23819 /* Floating point variants -- don't add any more to this list either. */
23820 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23821 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23822 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23823 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
23824 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
23826 {NULL, NULL, ARM_ARCH_NONE, NULL}
23829 struct arm_cpu_option_table
23833 const arm_feature_set value;
23834 /* For some CPUs we assume an FPU unless the user explicitly sets
23836 const arm_feature_set default_fpu;
23837 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23839 const char *canonical_name;
23842 /* This list should, at a minimum, contain all the cpu names
23843 recognized by GCC. */
23844 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
23845 static const struct arm_cpu_option_table arm_cpus[] =
23847 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23848 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23849 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23850 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23851 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23852 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23853 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23854 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23855 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23856 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23857 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23858 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23859 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23860 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23861 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23862 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23863 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23864 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23865 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23866 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23867 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23868 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23869 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23870 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23871 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23872 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23873 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23874 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23875 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23876 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23877 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23878 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23879 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23880 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23881 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23882 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23883 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23884 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23885 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23886 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23887 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23888 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23889 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23890 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23891 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23892 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23893 /* For V5 or later processors we default to using VFP; but the user
23894 should really set the FPU type explicitly. */
23895 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23896 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23897 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23898 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23899 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23900 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23901 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23902 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23903 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23904 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23905 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23906 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23907 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23908 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23909 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23910 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23911 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23912 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23913 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23914 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23916 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23917 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23918 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23919 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23920 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23921 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23922 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23923 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23924 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23926 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23927 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23928 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23929 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23930 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23931 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23932 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23933 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23934 FPU_NONE, "Cortex-A5"),
23935 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23936 FPU_ARCH_NEON_VFP_V4,
23938 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23939 ARM_FEATURE (0, FPU_VFP_V3
23940 | FPU_NEON_EXT_V1),
23942 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23943 ARM_FEATURE (0, FPU_VFP_V3
23944 | FPU_NEON_EXT_V1),
23946 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23947 FPU_ARCH_NEON_VFP_V4,
23949 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23951 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
23953 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23954 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23956 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23957 FPU_NONE, "Cortex-R5"),
23958 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
23959 FPU_ARCH_VFP_V3D16,
23961 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23962 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23963 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23964 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23965 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
23966 /* ??? XSCALE is really an architecture. */
23967 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23968 /* ??? iwmmxt is not a processor. */
23969 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23970 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23971 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23973 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23974 FPU_ARCH_MAVERICK, "ARM920T"),
23975 /* Marvell processors. */
23976 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
23977 FPU_ARCH_VFP_V3D16, NULL),
23979 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23983 struct arm_arch_option_table
23987 const arm_feature_set value;
23988 const arm_feature_set default_fpu;
23991 /* This list should, at a minimum, contain all the architecture names
23992 recognized by GCC. */
23993 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23994 static const struct arm_arch_option_table arm_archs[] =
23996 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23997 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23998 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23999 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24000 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24001 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24002 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24003 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24004 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24005 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24006 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24007 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24008 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24009 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24010 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24011 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24012 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24013 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24014 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24015 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24016 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24017 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24018 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24019 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24020 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24021 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24022 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24023 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24024 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24025 /* The official spelling of the ARMv7 profile variants is the dashed form.
24026 Accept the non-dashed form for compatibility with old toolchains. */
24027 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24028 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24029 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24030 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24031 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24032 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24033 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24034 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24035 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24036 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24037 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24038 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24040 #undef ARM_ARCH_OPT
24042 /* ISA extensions in the co-processor and main instruction set space. */
24043 struct arm_option_extension_value_table
24047 const arm_feature_set value;
24048 const arm_feature_set allowed_archs;
24051 /* The following table must be in alphabetical order with a NULL last entry.
24053 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24054 static const struct arm_option_extension_value_table arm_extensions[] =
24056 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
24057 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24058 ARM_FEATURE (ARM_EXT_V8, 0)),
24059 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24060 ARM_FEATURE (ARM_EXT_V8, 0)),
24061 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24062 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24063 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24064 ARM_EXT_OPT ("iwmmxt2",
24065 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24066 ARM_EXT_OPT ("maverick",
24067 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
24068 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24069 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24070 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24071 ARM_FEATURE (ARM_EXT_V8, 0)),
24072 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24073 ARM_FEATURE (ARM_EXT_V6M, 0)),
24074 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24075 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24076 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24078 ARM_FEATURE (ARM_EXT_V7A, 0)),
24079 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24080 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24084 /* ISA floating-point and Advanced SIMD extensions. */
24085 struct arm_option_fpu_value_table
24088 const arm_feature_set value;
24091 /* This list should, at a minimum, contain all the fpu names
24092 recognized by GCC. */
24093 static const struct arm_option_fpu_value_table arm_fpus[] =
24095 {"softfpa", FPU_NONE},
24096 {"fpe", FPU_ARCH_FPE},
24097 {"fpe2", FPU_ARCH_FPE},
24098 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24099 {"fpa", FPU_ARCH_FPA},
24100 {"fpa10", FPU_ARCH_FPA},
24101 {"fpa11", FPU_ARCH_FPA},
24102 {"arm7500fe", FPU_ARCH_FPA},
24103 {"softvfp", FPU_ARCH_VFP},
24104 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24105 {"vfp", FPU_ARCH_VFP_V2},
24106 {"vfp9", FPU_ARCH_VFP_V2},
24107 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24108 {"vfp10", FPU_ARCH_VFP_V2},
24109 {"vfp10-r0", FPU_ARCH_VFP_V1},
24110 {"vfpxd", FPU_ARCH_VFP_V1xD},
24111 {"vfpv2", FPU_ARCH_VFP_V2},
24112 {"vfpv3", FPU_ARCH_VFP_V3},
24113 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24114 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24115 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24116 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24117 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24118 {"arm1020t", FPU_ARCH_VFP_V1},
24119 {"arm1020e", FPU_ARCH_VFP_V2},
24120 {"arm1136jfs", FPU_ARCH_VFP_V2},
24121 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24122 {"maverick", FPU_ARCH_MAVERICK},
24123 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24124 {"neon-fp16", FPU_ARCH_NEON_FP16},
24125 {"vfpv4", FPU_ARCH_VFP_V4},
24126 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24127 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24128 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24129 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24130 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24131 {"crypto-neon-fp-armv8",
24132 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24133 {NULL, ARM_ARCH_NONE}
24136 struct arm_option_value_table
24142 static const struct arm_option_value_table arm_float_abis[] =
24144 {"hard", ARM_FLOAT_ABI_HARD},
24145 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24146 {"soft", ARM_FLOAT_ABI_SOFT},
24151 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24152 static const struct arm_option_value_table arm_eabis[] =
24154 {"gnu", EF_ARM_EABI_UNKNOWN},
24155 {"4", EF_ARM_EABI_VER4},
24156 {"5", EF_ARM_EABI_VER5},
24161 struct arm_long_option_table
24163 char * option; /* Substring to match. */
24164 char * help; /* Help information. */
24165 int (* func) (char * subopt); /* Function to decode sub-option. */
24166 char * deprecated; /* If non-null, print this message. */
24170 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24172 arm_feature_set *ext_set = (arm_feature_set *)
24173 xmalloc (sizeof (arm_feature_set));
24175 /* We insist on extensions being specified in alphabetical order, and with
24176 extensions being added before being removed. We achieve this by having
24177 the global ARM_EXTENSIONS table in alphabetical order, and using the
24178 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24179 or removing it (0) and only allowing it to change in the order
24181 const struct arm_option_extension_value_table * opt = NULL;
24182 int adding_value = -1;
24184 /* Copy the feature set, so that we can modify it. */
24185 *ext_set = **opt_p;
24188 while (str != NULL && *str != 0)
24195 as_bad (_("invalid architectural extension"));
24200 ext = strchr (str, '+');
24205 len = strlen (str);
24207 if (len >= 2 && strncmp (str, "no", 2) == 0)
24209 if (adding_value != 0)
24212 opt = arm_extensions;
24220 if (adding_value == -1)
24223 opt = arm_extensions;
24225 else if (adding_value != 1)
24227 as_bad (_("must specify extensions to add before specifying "
24228 "those to remove"));
24235 as_bad (_("missing architectural extension"));
24239 gas_assert (adding_value != -1);
24240 gas_assert (opt != NULL);
24242 /* Scan over the options table trying to find an exact match. */
24243 for (; opt->name != NULL; opt++)
24244 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24246 /* Check we can apply the extension to this architecture. */
24247 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24249 as_bad (_("extension does not apply to the base architecture"));
24253 /* Add or remove the extension. */
24255 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24257 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24262 if (opt->name == NULL)
24264 /* Did we fail to find an extension because it wasn't specified in
24265 alphabetical order, or because it does not exist? */
24267 for (opt = arm_extensions; opt->name != NULL; opt++)
24268 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24271 if (opt->name == NULL)
24272 as_bad (_("unknown architectural extension `%s'"), str);
24274 as_bad (_("architectural extensions must be specified in "
24275 "alphabetical order"));
24281 /* We should skip the extension we've just matched the next time
24293 arm_parse_cpu (char *str)
24295 const struct arm_cpu_option_table *opt;
24296 char *ext = strchr (str, '+');
24302 len = strlen (str);
24306 as_bad (_("missing cpu name `%s'"), str);
24310 for (opt = arm_cpus; opt->name != NULL; opt++)
24311 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24313 mcpu_cpu_opt = &opt->value;
24314 mcpu_fpu_opt = &opt->default_fpu;
24315 if (opt->canonical_name)
24316 strcpy (selected_cpu_name, opt->canonical_name);
24321 for (i = 0; i < len; i++)
24322 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24323 selected_cpu_name[i] = 0;
24327 return arm_parse_extension (ext, &mcpu_cpu_opt);
24332 as_bad (_("unknown cpu `%s'"), str);
24337 arm_parse_arch (char *str)
24339 const struct arm_arch_option_table *opt;
24340 char *ext = strchr (str, '+');
24346 len = strlen (str);
24350 as_bad (_("missing architecture name `%s'"), str);
24354 for (opt = arm_archs; opt->name != NULL; opt++)
24355 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24357 march_cpu_opt = &opt->value;
24358 march_fpu_opt = &opt->default_fpu;
24359 strcpy (selected_cpu_name, opt->name);
24362 return arm_parse_extension (ext, &march_cpu_opt);
24367 as_bad (_("unknown architecture `%s'\n"), str);
24372 arm_parse_fpu (char * str)
24374 const struct arm_option_fpu_value_table * opt;
24376 for (opt = arm_fpus; opt->name != NULL; opt++)
24377 if (streq (opt->name, str))
24379 mfpu_opt = &opt->value;
24383 as_bad (_("unknown floating point format `%s'\n"), str);
24388 arm_parse_float_abi (char * str)
24390 const struct arm_option_value_table * opt;
24392 for (opt = arm_float_abis; opt->name != NULL; opt++)
24393 if (streq (opt->name, str))
24395 mfloat_abi_opt = opt->value;
24399 as_bad (_("unknown floating point abi `%s'\n"), str);
24405 arm_parse_eabi (char * str)
24407 const struct arm_option_value_table *opt;
24409 for (opt = arm_eabis; opt->name != NULL; opt++)
24410 if (streq (opt->name, str))
24412 meabi_flags = opt->value;
24415 as_bad (_("unknown EABI `%s'\n"), str);
24421 arm_parse_it_mode (char * str)
24423 bfd_boolean ret = TRUE;
24425 if (streq ("arm", str))
24426 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24427 else if (streq ("thumb", str))
24428 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24429 else if (streq ("always", str))
24430 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24431 else if (streq ("never", str))
24432 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24435 as_bad (_("unknown implicit IT mode `%s', should be "\
24436 "arm, thumb, always, or never."), str);
24443 struct arm_long_option_table arm_long_opts[] =
24445 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24446 arm_parse_cpu, NULL},
24447 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24448 arm_parse_arch, NULL},
24449 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24450 arm_parse_fpu, NULL},
24451 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24452 arm_parse_float_abi, NULL},
24454 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24455 arm_parse_eabi, NULL},
24457 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24458 arm_parse_it_mode, NULL},
24459 {NULL, NULL, 0, NULL}
24463 md_parse_option (int c, char * arg)
24465 struct arm_option_table *opt;
24466 const struct arm_legacy_option_table *fopt;
24467 struct arm_long_option_table *lopt;
24473 target_big_endian = 1;
24479 target_big_endian = 0;
24483 case OPTION_FIX_V4BX:
24488 /* Listing option. Just ignore these, we don't support additional
24493 for (opt = arm_opts; opt->option != NULL; opt++)
24495 if (c == opt->option[0]
24496 && ((arg == NULL && opt->option[1] == 0)
24497 || streq (arg, opt->option + 1)))
24499 /* If the option is deprecated, tell the user. */
24500 if (warn_on_deprecated && opt->deprecated != NULL)
24501 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24502 arg ? arg : "", _(opt->deprecated));
24504 if (opt->var != NULL)
24505 *opt->var = opt->value;
24511 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24513 if (c == fopt->option[0]
24514 && ((arg == NULL && fopt->option[1] == 0)
24515 || streq (arg, fopt->option + 1)))
24517 /* If the option is deprecated, tell the user. */
24518 if (warn_on_deprecated && fopt->deprecated != NULL)
24519 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24520 arg ? arg : "", _(fopt->deprecated));
24522 if (fopt->var != NULL)
24523 *fopt->var = &fopt->value;
24529 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24531 /* These options are expected to have an argument. */
24532 if (c == lopt->option[0]
24534 && strncmp (arg, lopt->option + 1,
24535 strlen (lopt->option + 1)) == 0)
24537 /* If the option is deprecated, tell the user. */
24538 if (warn_on_deprecated && lopt->deprecated != NULL)
24539 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24540 _(lopt->deprecated));
24542 /* Call the sup-option parser. */
24543 return lopt->func (arg + strlen (lopt->option) - 1);
24554 md_show_usage (FILE * fp)
24556 struct arm_option_table *opt;
24557 struct arm_long_option_table *lopt;
24559 fprintf (fp, _(" ARM-specific assembler options:\n"));
24561 for (opt = arm_opts; opt->option != NULL; opt++)
24562 if (opt->help != NULL)
24563 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
24565 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24566 if (lopt->help != NULL)
24567 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
24571 -EB assemble code for a big-endian cpu\n"));
24576 -EL assemble code for a little-endian cpu\n"));
24580 --fix-v4bx Allow BX in ARMv4 code\n"));
24588 arm_feature_set flags;
24589 } cpu_arch_ver_table;
24591 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24592 least features first. */
24593 static const cpu_arch_ver_table cpu_arch_ver[] =
24599 {4, ARM_ARCH_V5TE},
24600 {5, ARM_ARCH_V5TEJ},
24604 {11, ARM_ARCH_V6M},
24605 {12, ARM_ARCH_V6SM},
24606 {8, ARM_ARCH_V6T2},
24607 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
24608 {10, ARM_ARCH_V7R},
24609 {10, ARM_ARCH_V7M},
24610 {14, ARM_ARCH_V8A},
24614 /* Set an attribute if it has not already been set by the user. */
24616 aeabi_set_attribute_int (int tag, int value)
24619 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24620 || !attributes_set_explicitly[tag])
24621 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24625 aeabi_set_attribute_string (int tag, const char *value)
24628 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24629 || !attributes_set_explicitly[tag])
24630 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24633 /* Set the public EABI object attributes. */
24635 aeabi_set_public_attributes (void)
24640 int fp16_optional = 0;
24641 arm_feature_set flags;
24642 arm_feature_set tmp;
24643 const cpu_arch_ver_table *p;
24645 /* Choose the architecture based on the capabilities of the requested cpu
24646 (if any) and/or the instructions actually used. */
24647 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24648 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24649 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
24651 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24652 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24654 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24655 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24657 /* Allow the user to override the reported architecture. */
24660 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24661 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24664 /* We need to make sure that the attributes do not identify us as v6S-M
24665 when the only v6S-M feature in use is the Operating System Extensions. */
24666 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24667 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
24668 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
24672 for (p = cpu_arch_ver; p->val; p++)
24674 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24677 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24681 /* The table lookup above finds the last architecture to contribute
24682 a new feature. Unfortunately, Tag13 is a subset of the union of
24683 v6T2 and v7-M, so it is never seen as contributing a new feature.
24684 We can not search for the last entry which is entirely used,
24685 because if no CPU is specified we build up only those flags
24686 actually used. Perhaps we should separate out the specified
24687 and implicit cases. Avoid taking this path for -march=all by
24688 checking for contradictory v7-A / v7-M features. */
24690 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24691 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24692 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24695 /* Tag_CPU_name. */
24696 if (selected_cpu_name[0])
24700 q = selected_cpu_name;
24701 if (strncmp (q, "armv", 4) == 0)
24706 for (i = 0; q[i]; i++)
24707 q[i] = TOUPPER (q[i]);
24709 aeabi_set_attribute_string (Tag_CPU_name, q);
24712 /* Tag_CPU_arch. */
24713 aeabi_set_attribute_int (Tag_CPU_arch, arch);
24715 /* Tag_CPU_arch_profile. */
24716 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
24718 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
24720 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
24725 if (profile != '\0')
24726 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
24728 /* Tag_ARM_ISA_use. */
24729 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24731 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
24733 /* Tag_THUMB_ISA_use. */
24734 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24736 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24737 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
24739 /* Tag_VFP_arch. */
24740 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24741 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24742 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
24743 aeabi_set_attribute_int (Tag_VFP_arch,
24744 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24746 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
24749 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24751 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
24753 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24756 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24757 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24758 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
24759 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
24760 aeabi_set_attribute_int (Tag_VFP_arch, 1);
24762 /* Tag_ABI_HardFP_use. */
24763 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24764 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24765 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24767 /* Tag_WMMX_arch. */
24768 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24769 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24770 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24771 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
24773 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
24774 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24775 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24776 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24778 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24780 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24784 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24789 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
24790 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
24791 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
24795 We set Tag_DIV_use to two when integer divide instructions have been used
24796 in ARM state, or when Thumb integer divide instructions have been used,
24797 but we have no architecture profile set, nor have we any ARM instructions.
24799 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24802 For new architectures we will have to check these tests. */
24803 gas_assert (arch <= TAG_CPU_ARCH_V8);
24804 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24805 aeabi_set_attribute_int (Tag_DIV_use, 0);
24806 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24807 || (profile == '\0'
24808 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24809 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
24810 aeabi_set_attribute_int (Tag_DIV_use, 2);
24812 /* Tag_MP_extension_use. */
24813 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24814 aeabi_set_attribute_int (Tag_MPextension_use, 1);
24816 /* Tag Virtualization_use. */
24817 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
24819 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24822 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
24825 /* Add the default contents for the .ARM.attributes section. */
24829 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24832 aeabi_set_public_attributes ();
24834 #endif /* OBJ_ELF */
24837 /* Parse a .cpu directive. */
24840 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24842 const struct arm_cpu_option_table *opt;
24846 name = input_line_pointer;
24847 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24848 input_line_pointer++;
24849 saved_char = *input_line_pointer;
24850 *input_line_pointer = 0;
24852 /* Skip the first "all" entry. */
24853 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24854 if (streq (opt->name, name))
24856 mcpu_cpu_opt = &opt->value;
24857 selected_cpu = opt->value;
24858 if (opt->canonical_name)
24859 strcpy (selected_cpu_name, opt->canonical_name);
24863 for (i = 0; opt->name[i]; i++)
24864 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24866 selected_cpu_name[i] = 0;
24868 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24869 *input_line_pointer = saved_char;
24870 demand_empty_rest_of_line ();
24873 as_bad (_("unknown cpu `%s'"), name);
24874 *input_line_pointer = saved_char;
24875 ignore_rest_of_line ();
24879 /* Parse a .arch directive. */
24882 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24884 const struct arm_arch_option_table *opt;
24888 name = input_line_pointer;
24889 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24890 input_line_pointer++;
24891 saved_char = *input_line_pointer;
24892 *input_line_pointer = 0;
24894 /* Skip the first "all" entry. */
24895 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24896 if (streq (opt->name, name))
24898 mcpu_cpu_opt = &opt->value;
24899 selected_cpu = opt->value;
24900 strcpy (selected_cpu_name, opt->name);
24901 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24902 *input_line_pointer = saved_char;
24903 demand_empty_rest_of_line ();
24907 as_bad (_("unknown architecture `%s'\n"), name);
24908 *input_line_pointer = saved_char;
24909 ignore_rest_of_line ();
24913 /* Parse a .object_arch directive. */
24916 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24918 const struct arm_arch_option_table *opt;
24922 name = input_line_pointer;
24923 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24924 input_line_pointer++;
24925 saved_char = *input_line_pointer;
24926 *input_line_pointer = 0;
24928 /* Skip the first "all" entry. */
24929 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24930 if (streq (opt->name, name))
24932 object_arch = &opt->value;
24933 *input_line_pointer = saved_char;
24934 demand_empty_rest_of_line ();
24938 as_bad (_("unknown architecture `%s'\n"), name);
24939 *input_line_pointer = saved_char;
24940 ignore_rest_of_line ();
24943 /* Parse a .arch_extension directive. */
24946 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24948 const struct arm_option_extension_value_table *opt;
24951 int adding_value = 1;
24953 name = input_line_pointer;
24954 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24955 input_line_pointer++;
24956 saved_char = *input_line_pointer;
24957 *input_line_pointer = 0;
24959 if (strlen (name) >= 2
24960 && strncmp (name, "no", 2) == 0)
24966 for (opt = arm_extensions; opt->name != NULL; opt++)
24967 if (streq (opt->name, name))
24969 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
24971 as_bad (_("architectural extension `%s' is not allowed for the "
24972 "current base architecture"), name);
24977 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
24979 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
24981 mcpu_cpu_opt = &selected_cpu;
24982 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24983 *input_line_pointer = saved_char;
24984 demand_empty_rest_of_line ();
24988 if (opt->name == NULL)
24989 as_bad (_("unknown architecture `%s'\n"), name);
24991 *input_line_pointer = saved_char;
24992 ignore_rest_of_line ();
24995 /* Parse a .fpu directive. */
24998 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25000 const struct arm_option_fpu_value_table *opt;
25004 name = input_line_pointer;
25005 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25006 input_line_pointer++;
25007 saved_char = *input_line_pointer;
25008 *input_line_pointer = 0;
25010 for (opt = arm_fpus; opt->name != NULL; opt++)
25011 if (streq (opt->name, name))
25013 mfpu_opt = &opt->value;
25014 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25015 *input_line_pointer = saved_char;
25016 demand_empty_rest_of_line ();
25020 as_bad (_("unknown floating point format `%s'\n"), name);
25021 *input_line_pointer = saved_char;
25022 ignore_rest_of_line ();
25025 /* Copy symbol information. */
25028 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25030 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25034 /* Given a symbolic attribute NAME, return the proper integer value.
25035 Returns -1 if the attribute is not known. */
25038 arm_convert_symbolic_attribute (const char *name)
25040 static const struct
25045 attribute_table[] =
25047 /* When you modify this table you should
25048 also modify the list in doc/c-arm.texi. */
25049 #define T(tag) {#tag, tag}
25050 T (Tag_CPU_raw_name),
25053 T (Tag_CPU_arch_profile),
25054 T (Tag_ARM_ISA_use),
25055 T (Tag_THUMB_ISA_use),
25059 T (Tag_Advanced_SIMD_arch),
25060 T (Tag_PCS_config),
25061 T (Tag_ABI_PCS_R9_use),
25062 T (Tag_ABI_PCS_RW_data),
25063 T (Tag_ABI_PCS_RO_data),
25064 T (Tag_ABI_PCS_GOT_use),
25065 T (Tag_ABI_PCS_wchar_t),
25066 T (Tag_ABI_FP_rounding),
25067 T (Tag_ABI_FP_denormal),
25068 T (Tag_ABI_FP_exceptions),
25069 T (Tag_ABI_FP_user_exceptions),
25070 T (Tag_ABI_FP_number_model),
25071 T (Tag_ABI_align_needed),
25072 T (Tag_ABI_align8_needed),
25073 T (Tag_ABI_align_preserved),
25074 T (Tag_ABI_align8_preserved),
25075 T (Tag_ABI_enum_size),
25076 T (Tag_ABI_HardFP_use),
25077 T (Tag_ABI_VFP_args),
25078 T (Tag_ABI_WMMX_args),
25079 T (Tag_ABI_optimization_goals),
25080 T (Tag_ABI_FP_optimization_goals),
25081 T (Tag_compatibility),
25082 T (Tag_CPU_unaligned_access),
25083 T (Tag_FP_HP_extension),
25084 T (Tag_VFP_HP_extension),
25085 T (Tag_ABI_FP_16bit_format),
25086 T (Tag_MPextension_use),
25088 T (Tag_nodefaults),
25089 T (Tag_also_compatible_with),
25090 T (Tag_conformance),
25092 T (Tag_Virtualization_use),
25093 /* We deliberately do not include Tag_MPextension_use_legacy. */
25101 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25102 if (streq (name, attribute_table[i].name))
25103 return attribute_table[i].tag;
25109 /* Apply sym value for relocations only in the case that
25110 they are for local symbols and you have the respective
25111 architectural feature for blx and simple switches. */
25113 arm_apply_sym_value (struct fix * fixP)
25116 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25117 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25119 switch (fixP->fx_r_type)
25121 case BFD_RELOC_ARM_PCREL_BLX:
25122 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25123 if (ARM_IS_FUNC (fixP->fx_addsy))
25127 case BFD_RELOC_ARM_PCREL_CALL:
25128 case BFD_RELOC_THUMB_PCREL_BLX:
25129 if (THUMB_IS_FUNC (fixP->fx_addsy))
25140 #endif /* OBJ_ELF */