1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
357 unsigned long instruction;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type;
379 enum it_instruction_type it_insn_type;
385 struct neon_type_el vectype;
386 unsigned present : 1; /* Operand present. */
387 unsigned isreg : 1; /* Operand was a register. */
388 unsigned immisreg : 1; /* .imm field is a second register. */
389 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle : 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc : 1; /* Operand has relocation suffix. */
399 unsigned writeback : 1; /* Operand has trailing ! */
400 unsigned preind : 1; /* Preindexed address. */
401 unsigned postind : 1; /* Postindexed address. */
402 unsigned negative : 1; /* Index register was negated. */
403 unsigned shifted : 1; /* Shift applied to operation. */
404 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name;
444 #define COND_ALWAYS 0xE
448 const char * template_name;
452 struct asm_barrier_opt
454 const char * template_name;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc;
475 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
476 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
481 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined;
492 struct neon_type_el eltype;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin;
533 struct neon_typed_alias * neon;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name;
576 /* Parameters to instruction. */
577 unsigned int operands[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag : 4;
582 /* Basic instruction code. */
583 unsigned int avalue : 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set * avariant;
590 const arm_feature_set * tvariant;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
727 #define BAD_RANGE _("branch out of range")
729 static struct hash_control * arm_ops_hsh;
730 static struct hash_control * arm_cond_hsh;
731 static struct hash_control * arm_shift_hsh;
732 static struct hash_control * arm_psr_hsh;
733 static struct hash_control * arm_v7m_psr_hsh;
734 static struct hash_control * arm_reg_hsh;
735 static struct hash_control * arm_reloc_hsh;
736 static struct hash_control * arm_barrier_opt_hsh;
738 /* Stuff needed to resolve the label ambiguity
747 symbolS * last_label_seen;
748 static int label_is_thumb_function_name = FALSE;
750 /* Literal pool structure. Held on a per-section
751 and per-sub-section basis. */
753 #define MAX_LITERAL_POOL_SIZE 1024
754 typedef struct literal_pool
756 expressionS literals [MAX_LITERAL_POOL_SIZE];
757 unsigned int next_free_entry;
763 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
765 struct literal_pool * next;
768 /* Pointer to a linked list of literal pools. */
769 literal_pool * list_of_pools = NULL;
772 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
774 static struct current_it now_it;
778 now_it_compatible (int cond)
780 return (cond & ~1) == (now_it.cc & ~1);
784 conditional_insn (void)
786 return inst.cond != COND_ALWAYS;
789 static int in_it_block (void);
791 static int handle_it_state (void);
793 static void force_automatic_it_block_close (void);
795 static void it_fsm_post_encode (void);
797 #define set_it_insn_type(type) \
800 inst.it_insn_type = type; \
801 if (handle_it_state () == FAIL) \
806 #define set_it_insn_type_nonvoid(type, failret) \
809 inst.it_insn_type = type; \
810 if (handle_it_state () == FAIL) \
815 #define set_it_insn_type_last() \
818 if (inst.cond == COND_ALWAYS) \
819 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
821 set_it_insn_type (INSIDE_IT_LAST_INSN); \
827 /* This array holds the chars that always start a comment. If the
828 pre-processor is disabled, these aren't very useful. */
829 const char comment_chars[] = "@";
831 /* This array holds the chars that only start a comment at the beginning of
832 a line. If the line seems to have the form '# 123 filename'
833 .line and .file directives will appear in the pre-processed output. */
834 /* Note that input_file.c hand checks for '#' at the beginning of the
835 first line of the input file. This is because the compiler outputs
836 #NO_APP at the beginning of its output. */
837 /* Also note that comments like this one will always work. */
838 const char line_comment_chars[] = "#";
840 const char line_separator_chars[] = ";";
842 /* Chars that can be used to separate mant
843 from exp in floating point numbers. */
844 const char EXP_CHARS[] = "eE";
846 /* Chars that mean this number is a floating point constant. */
850 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
852 /* Prefix characters that indicate the start of an immediate
854 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
856 /* Separator character handling. */
858 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
861 skip_past_char (char ** str, char c)
872 #define skip_past_comma(str) skip_past_char (str, ',')
874 /* Arithmetic expressions (possibly involving symbols). */
876 /* Return TRUE if anything in the expression is a bignum. */
879 walk_no_bignums (symbolS * sp)
881 if (symbol_get_value_expression (sp)->X_op == O_big)
884 if (symbol_get_value_expression (sp)->X_add_symbol)
886 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
887 || (symbol_get_value_expression (sp)->X_op_symbol
888 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
894 static int in_my_get_expression = 0;
896 /* Third argument to my_get_expression. */
897 #define GE_NO_PREFIX 0
898 #define GE_IMM_PREFIX 1
899 #define GE_OPT_PREFIX 2
900 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
901 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
902 #define GE_OPT_PREFIX_BIG 3
905 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
910 /* In unified syntax, all prefixes are optional. */
912 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
917 case GE_NO_PREFIX: break;
919 if (!is_immediate_prefix (**str))
921 inst.error = _("immediate expression requires a # prefix");
927 case GE_OPT_PREFIX_BIG:
928 if (is_immediate_prefix (**str))
934 memset (ep, 0, sizeof (expressionS));
936 save_in = input_line_pointer;
937 input_line_pointer = *str;
938 in_my_get_expression = 1;
939 seg = expression (ep);
940 in_my_get_expression = 0;
942 if (ep->X_op == O_illegal || ep->X_op == O_absent)
944 /* We found a bad or missing expression in md_operand(). */
945 *str = input_line_pointer;
946 input_line_pointer = save_in;
947 if (inst.error == NULL)
948 inst.error = (ep->X_op == O_absent
949 ? _("missing expression") :_("bad expression"));
954 if (seg != absolute_section
955 && seg != text_section
956 && seg != data_section
957 && seg != bss_section
958 && seg != undefined_section)
960 inst.error = _("bad segment");
961 *str = input_line_pointer;
962 input_line_pointer = save_in;
969 /* Get rid of any bignums now, so that we don't generate an error for which
970 we can't establish a line number later on. Big numbers are never valid
971 in instructions, which is where this routine is always called. */
972 if (prefix_mode != GE_OPT_PREFIX_BIG
973 && (ep->X_op == O_big
975 && (walk_no_bignums (ep->X_add_symbol)
977 && walk_no_bignums (ep->X_op_symbol))))))
979 inst.error = _("invalid constant");
980 *str = input_line_pointer;
981 input_line_pointer = save_in;
985 *str = input_line_pointer;
986 input_line_pointer = save_in;
990 /* Turn a string in input_line_pointer into a floating point constant
991 of type TYPE, and store the appropriate bytes in *LITP. The number
992 of LITTLENUMS emitted is stored in *SIZEP. An error message is
993 returned, or NULL on OK.
995 Note that fp constants aren't represent in the normal way on the ARM.
996 In big endian mode, things are as expected. However, in little endian
997 mode fp constants are big-endian word-wise, and little-endian byte-wise
998 within the words. For example, (double) 1.1 in big endian mode is
999 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1000 the byte sequence 99 99 f1 3f 9a 99 99 99.
1002 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1005 md_atof (int type, char * litP, int * sizeP)
1008 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1040 return _("Unrecognized or unsupported floating point constant");
1043 t = atof_ieee (input_line_pointer, type, words);
1045 input_line_pointer = t;
1046 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1048 if (target_big_endian)
1050 for (i = 0; i < prec; i++)
1052 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1053 litP += sizeof (LITTLENUM_TYPE);
1058 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1059 for (i = prec - 1; i >= 0; i--)
1061 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1062 litP += sizeof (LITTLENUM_TYPE);
1065 /* For a 4 byte float the order of elements in `words' is 1 0.
1066 For an 8 byte float the order is 1 0 3 2. */
1067 for (i = 0; i < prec; i += 2)
1069 md_number_to_chars (litP, (valueT) words[i + 1],
1070 sizeof (LITTLENUM_TYPE));
1071 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1072 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1073 litP += 2 * sizeof (LITTLENUM_TYPE);
1080 /* We handle all bad expressions here, so that we can report the faulty
1081 instruction in the error message. */
1083 md_operand (expressionS * exp)
1085 if (in_my_get_expression)
1086 exp->X_op = O_illegal;
1089 /* Immediate values. */
1091 /* Generic immediate-value read function for use in directives.
1092 Accepts anything that 'expression' can fold to a constant.
1093 *val receives the number. */
1096 immediate_for_directive (int *val)
1099 exp.X_op = O_illegal;
1101 if (is_immediate_prefix (*input_line_pointer))
1103 input_line_pointer++;
1107 if (exp.X_op != O_constant)
1109 as_bad (_("expected #constant"));
1110 ignore_rest_of_line ();
1113 *val = exp.X_add_number;
1118 /* Register parsing. */
1120 /* Generic register parser. CCP points to what should be the
1121 beginning of a register name. If it is indeed a valid register
1122 name, advance CCP over it and return the reg_entry structure;
1123 otherwise return NULL. Does not issue diagnostics. */
1125 static struct reg_entry *
1126 arm_reg_parse_multi (char **ccp)
1130 struct reg_entry *reg;
1132 #ifdef REGISTER_PREFIX
1133 if (*start != REGISTER_PREFIX)
1137 #ifdef OPTIONAL_REGISTER_PREFIX
1138 if (*start == OPTIONAL_REGISTER_PREFIX)
1143 if (!ISALPHA (*p) || !is_name_beginner (*p))
1148 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1150 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1160 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1161 enum arm_reg_type type)
1163 /* Alternative syntaxes are accepted for a few register classes. */
1170 /* Generic coprocessor register names are allowed for these. */
1171 if (reg && reg->type == REG_TYPE_CN)
1176 /* For backward compatibility, a bare number is valid here. */
1178 unsigned long processor = strtoul (start, ccp, 10);
1179 if (*ccp != start && processor <= 15)
1183 case REG_TYPE_MMXWC:
1184 /* WC includes WCG. ??? I'm not sure this is true for all
1185 instructions that take WC registers. */
1186 if (reg && reg->type == REG_TYPE_MMXWCG)
1197 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1198 return value is the register number or FAIL. */
1201 arm_reg_parse (char **ccp, enum arm_reg_type type)
1204 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1207 /* Do not allow a scalar (reg+index) to parse as a register. */
1208 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1211 if (reg && reg->type == type)
1214 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1221 /* Parse a Neon type specifier. *STR should point at the leading '.'
1222 character. Does no verification at this stage that the type fits the opcode
1229 Can all be legally parsed by this function.
1231 Fills in neon_type struct pointer with parsed information, and updates STR
1232 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1233 type, FAIL if not. */
1236 parse_neon_type (struct neon_type *type, char **str)
1243 while (type->elems < NEON_MAX_TYPE_ELS)
1245 enum neon_el_type thistype = NT_untyped;
1246 unsigned thissize = -1u;
1253 /* Just a size without an explicit type. */
1257 switch (TOLOWER (*ptr))
1259 case 'i': thistype = NT_integer; break;
1260 case 'f': thistype = NT_float; break;
1261 case 'p': thistype = NT_poly; break;
1262 case 's': thistype = NT_signed; break;
1263 case 'u': thistype = NT_unsigned; break;
1265 thistype = NT_float;
1270 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1276 /* .f is an abbreviation for .f32. */
1277 if (thistype == NT_float && !ISDIGIT (*ptr))
1282 thissize = strtoul (ptr, &ptr, 10);
1284 if (thissize != 8 && thissize != 16 && thissize != 32
1287 as_bad (_("bad size %d in type specifier"), thissize);
1295 type->el[type->elems].type = thistype;
1296 type->el[type->elems].size = thissize;
1301 /* Empty/missing type is not a successful parse. */
1302 if (type->elems == 0)
1310 /* Errors may be set multiple times during parsing or bit encoding
1311 (particularly in the Neon bits), but usually the earliest error which is set
1312 will be the most meaningful. Avoid overwriting it with later (cascading)
1313 errors by calling this function. */
1316 first_error (const char *err)
1322 /* Parse a single type, e.g. ".s32", leading period included. */
1324 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1327 struct neon_type optype;
1331 if (parse_neon_type (&optype, &str) == SUCCESS)
1333 if (optype.elems == 1)
1334 *vectype = optype.el[0];
1337 first_error (_("only one type should be specified for operand"));
1343 first_error (_("vector type expected"));
1355 /* Special meanings for indices (which have a range of 0-7), which will fit into
1358 #define NEON_ALL_LANES 15
1359 #define NEON_INTERLEAVE_LANES 14
1361 /* Parse either a register or a scalar, with an optional type. Return the
1362 register number, and optionally fill in the actual type of the register
1363 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1364 type/index information in *TYPEINFO. */
1367 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1368 enum arm_reg_type *rtype,
1369 struct neon_typed_alias *typeinfo)
1372 struct reg_entry *reg = arm_reg_parse_multi (&str);
1373 struct neon_typed_alias atype;
1374 struct neon_type_el parsetype;
1378 atype.eltype.type = NT_invtype;
1379 atype.eltype.size = -1;
1381 /* Try alternate syntax for some types of register. Note these are mutually
1382 exclusive with the Neon syntax extensions. */
1385 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1393 /* Undo polymorphism when a set of register types may be accepted. */
1394 if ((type == REG_TYPE_NDQ
1395 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1396 || (type == REG_TYPE_VFSD
1397 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1398 || (type == REG_TYPE_NSDQ
1399 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1400 || reg->type == REG_TYPE_NQ))
1401 || (type == REG_TYPE_MMXWC
1402 && (reg->type == REG_TYPE_MMXWCG)))
1403 type = (enum arm_reg_type) reg->type;
1405 if (type != reg->type)
1411 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1413 if ((atype.defined & NTA_HASTYPE) != 0)
1415 first_error (_("can't redefine type for operand"));
1418 atype.defined |= NTA_HASTYPE;
1419 atype.eltype = parsetype;
1422 if (skip_past_char (&str, '[') == SUCCESS)
1424 if (type != REG_TYPE_VFD)
1426 first_error (_("only D registers may be indexed"));
1430 if ((atype.defined & NTA_HASINDEX) != 0)
1432 first_error (_("can't change index for operand"));
1436 atype.defined |= NTA_HASINDEX;
1438 if (skip_past_char (&str, ']') == SUCCESS)
1439 atype.index = NEON_ALL_LANES;
1444 my_get_expression (&exp, &str, GE_NO_PREFIX);
1446 if (exp.X_op != O_constant)
1448 first_error (_("constant expression required"));
1452 if (skip_past_char (&str, ']') == FAIL)
1455 atype.index = exp.X_add_number;
1470 /* Like arm_reg_parse, but allow allow the following extra features:
1471 - If RTYPE is non-zero, return the (possibly restricted) type of the
1472 register (e.g. Neon double or quad reg when either has been requested).
1473 - If this is a Neon vector type with additional type information, fill
1474 in the struct pointed to by VECTYPE (if non-NULL).
1475 This function will fault on encountering a scalar. */
1478 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1479 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1481 struct neon_typed_alias atype;
1483 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1488 /* Do not allow regname(... to parse as a register. */
1492 /* Do not allow a scalar (reg+index) to parse as a register. */
1493 if ((atype.defined & NTA_HASINDEX) != 0)
1495 first_error (_("register operand expected, but got scalar"));
1500 *vectype = atype.eltype;
1507 #define NEON_SCALAR_REG(X) ((X) >> 4)
1508 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1510 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1511 have enough information to be able to do a good job bounds-checking. So, we
1512 just do easy checks here, and do further checks later. */
1515 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1519 struct neon_typed_alias atype;
1521 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1523 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1526 if (atype.index == NEON_ALL_LANES)
1528 first_error (_("scalar must have an index"));
1531 else if (atype.index >= 64 / elsize)
1533 first_error (_("scalar index out of range"));
1538 *type = atype.eltype;
1542 return reg * 16 + atype.index;
1545 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1548 parse_reg_list (char ** strp)
1550 char * str = * strp;
1554 /* We come back here if we get ranges concatenated by '+' or '|'. */
1569 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1571 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1581 first_error (_("bad range in register list"));
1585 for (i = cur_reg + 1; i < reg; i++)
1587 if (range & (1 << i))
1589 (_("Warning: duplicated register (r%d) in register list"),
1597 if (range & (1 << reg))
1598 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1600 else if (reg <= cur_reg)
1601 as_tsktsk (_("Warning: register range not in ascending order"));
1606 while (skip_past_comma (&str) != FAIL
1607 || (in_range = 1, *str++ == '-'));
1612 first_error (_("missing `}'"));
1620 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1623 if (exp.X_op == O_constant)
1625 if (exp.X_add_number
1626 != (exp.X_add_number & 0x0000ffff))
1628 inst.error = _("invalid register mask");
1632 if ((range & exp.X_add_number) != 0)
1634 int regno = range & exp.X_add_number;
1637 regno = (1 << regno) - 1;
1639 (_("Warning: duplicated register (r%d) in register list"),
1643 range |= exp.X_add_number;
1647 if (inst.reloc.type != 0)
1649 inst.error = _("expression too complex");
1653 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1654 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1655 inst.reloc.pc_rel = 0;
1659 if (*str == '|' || *str == '+')
1665 while (another_range);
1671 /* Types of registers in a list. */
1680 /* Parse a VFP register list. If the string is invalid return FAIL.
1681 Otherwise return the number of registers, and set PBASE to the first
1682 register. Parses registers of type ETYPE.
1683 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1684 - Q registers can be used to specify pairs of D registers
1685 - { } can be omitted from around a singleton register list
1686 FIXME: This is not implemented, as it would require backtracking in
1689 This could be done (the meaning isn't really ambiguous), but doesn't
1690 fit in well with the current parsing framework.
1691 - 32 D registers may be used (also true for VFPv3).
1692 FIXME: Types are ignored in these register lists, which is probably a
1696 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1701 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1705 unsigned long mask = 0;
1710 inst.error = _("expecting {");
1719 regtype = REG_TYPE_VFS;
1724 regtype = REG_TYPE_VFD;
1727 case REGLIST_NEON_D:
1728 regtype = REG_TYPE_NDQ;
1732 if (etype != REGLIST_VFP_S)
1734 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1735 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1739 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1742 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1749 base_reg = max_regs;
1753 int setmask = 1, addregs = 1;
1755 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1757 if (new_base == FAIL)
1759 first_error (_(reg_expected_msgs[regtype]));
1763 if (new_base >= max_regs)
1765 first_error (_("register out of range in list"));
1769 /* Note: a value of 2 * n is returned for the register Q<n>. */
1770 if (regtype == REG_TYPE_NQ)
1776 if (new_base < base_reg)
1777 base_reg = new_base;
1779 if (mask & (setmask << new_base))
1781 first_error (_("invalid register list"));
1785 if ((mask >> new_base) != 0 && ! warned)
1787 as_tsktsk (_("register list not in ascending order"));
1791 mask |= setmask << new_base;
1794 if (*str == '-') /* We have the start of a range expression */
1800 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1803 inst.error = gettext (reg_expected_msgs[regtype]);
1807 if (high_range >= max_regs)
1809 first_error (_("register out of range in list"));
1813 if (regtype == REG_TYPE_NQ)
1814 high_range = high_range + 1;
1816 if (high_range <= new_base)
1818 inst.error = _("register range not in ascending order");
1822 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1824 if (mask & (setmask << new_base))
1826 inst.error = _("invalid register list");
1830 mask |= setmask << new_base;
1835 while (skip_past_comma (&str) != FAIL);
1839 /* Sanity check -- should have raised a parse error above. */
1840 if (count == 0 || count > max_regs)
1845 /* Final test -- the registers must be consecutive. */
1847 for (i = 0; i < count; i++)
1849 if ((mask & (1u << i)) == 0)
1851 inst.error = _("non-contiguous register range");
1861 /* True if two alias types are the same. */
1864 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1872 if (a->defined != b->defined)
1875 if ((a->defined & NTA_HASTYPE) != 0
1876 && (a->eltype.type != b->eltype.type
1877 || a->eltype.size != b->eltype.size))
1880 if ((a->defined & NTA_HASINDEX) != 0
1881 && (a->index != b->index))
1887 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1888 The base register is put in *PBASE.
1889 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1891 The register stride (minus one) is put in bit 4 of the return value.
1892 Bits [6:5] encode the list length (minus one).
1893 The type of the list elements is put in *ELTYPE, if non-NULL. */
1895 #define NEON_LANE(X) ((X) & 0xf)
1896 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1897 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1900 parse_neon_el_struct_list (char **str, unsigned *pbase,
1901 struct neon_type_el *eltype)
1908 int leading_brace = 0;
1909 enum arm_reg_type rtype = REG_TYPE_NDQ;
1910 const char *const incr_error = _("register stride must be 1 or 2");
1911 const char *const type_error = _("mismatched element/structure types in list");
1912 struct neon_typed_alias firsttype;
1914 if (skip_past_char (&ptr, '{') == SUCCESS)
1919 struct neon_typed_alias atype;
1920 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1924 first_error (_(reg_expected_msgs[rtype]));
1931 if (rtype == REG_TYPE_NQ)
1937 else if (reg_incr == -1)
1939 reg_incr = getreg - base_reg;
1940 if (reg_incr < 1 || reg_incr > 2)
1942 first_error (_(incr_error));
1946 else if (getreg != base_reg + reg_incr * count)
1948 first_error (_(incr_error));
1952 if (! neon_alias_types_same (&atype, &firsttype))
1954 first_error (_(type_error));
1958 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1962 struct neon_typed_alias htype;
1963 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1965 lane = NEON_INTERLEAVE_LANES;
1966 else if (lane != NEON_INTERLEAVE_LANES)
1968 first_error (_(type_error));
1973 else if (reg_incr != 1)
1975 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1979 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1982 first_error (_(reg_expected_msgs[rtype]));
1985 if (! neon_alias_types_same (&htype, &firsttype))
1987 first_error (_(type_error));
1990 count += hireg + dregs - getreg;
1994 /* If we're using Q registers, we can't use [] or [n] syntax. */
1995 if (rtype == REG_TYPE_NQ)
2001 if ((atype.defined & NTA_HASINDEX) != 0)
2005 else if (lane != atype.index)
2007 first_error (_(type_error));
2011 else if (lane == -1)
2012 lane = NEON_INTERLEAVE_LANES;
2013 else if (lane != NEON_INTERLEAVE_LANES)
2015 first_error (_(type_error));
2020 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2022 /* No lane set by [x]. We must be interleaving structures. */
2024 lane = NEON_INTERLEAVE_LANES;
2027 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2028 || (count > 1 && reg_incr == -1))
2030 first_error (_("error parsing element/structure list"));
2034 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2036 first_error (_("expected }"));
2044 *eltype = firsttype.eltype;
2049 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2052 /* Parse an explicit relocation suffix on an expression. This is
2053 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2054 arm_reloc_hsh contains no entries, so this function can only
2055 succeed if there is no () after the word. Returns -1 on error,
2056 BFD_RELOC_UNUSED if there wasn't any suffix. */
2059 parse_reloc (char **str)
2061 struct reloc_entry *r;
2065 return BFD_RELOC_UNUSED;
2070 while (*q && *q != ')' && *q != ',')
2075 if ((r = (struct reloc_entry *)
2076 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2083 /* Directives: register aliases. */
2085 static struct reg_entry *
2086 insert_reg_alias (char *str, unsigned number, int type)
2088 struct reg_entry *new_reg;
2091 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2093 if (new_reg->builtin)
2094 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2096 /* Only warn about a redefinition if it's not defined as the
2098 else if (new_reg->number != number || new_reg->type != type)
2099 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2104 name = xstrdup (str);
2105 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2107 new_reg->name = name;
2108 new_reg->number = number;
2109 new_reg->type = type;
2110 new_reg->builtin = FALSE;
2111 new_reg->neon = NULL;
2113 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2120 insert_neon_reg_alias (char *str, int number, int type,
2121 struct neon_typed_alias *atype)
2123 struct reg_entry *reg = insert_reg_alias (str, number, type);
2127 first_error (_("attempt to redefine typed alias"));
2133 reg->neon = (struct neon_typed_alias *)
2134 xmalloc (sizeof (struct neon_typed_alias));
2135 *reg->neon = *atype;
2139 /* Look for the .req directive. This is of the form:
2141 new_register_name .req existing_register_name
2143 If we find one, or if it looks sufficiently like one that we want to
2144 handle any error here, return TRUE. Otherwise return FALSE. */
2147 create_register_alias (char * newname, char *p)
2149 struct reg_entry *old;
2150 char *oldname, *nbuf;
2153 /* The input scrubber ensures that whitespace after the mnemonic is
2154 collapsed to single spaces. */
2156 if (strncmp (oldname, " .req ", 6) != 0)
2160 if (*oldname == '\0')
2163 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2166 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2170 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2171 the desired alias name, and p points to its end. If not, then
2172 the desired alias name is in the global original_case_string. */
2173 #ifdef TC_CASE_SENSITIVE
2176 newname = original_case_string;
2177 nlen = strlen (newname);
2180 nbuf = (char *) alloca (nlen + 1);
2181 memcpy (nbuf, newname, nlen);
2184 /* Create aliases under the new name as stated; an all-lowercase
2185 version of the new name; and an all-uppercase version of the new
2187 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2189 for (p = nbuf; *p; p++)
2192 if (strncmp (nbuf, newname, nlen))
2194 /* If this attempt to create an additional alias fails, do not bother
2195 trying to create the all-lower case alias. We will fail and issue
2196 a second, duplicate error message. This situation arises when the
2197 programmer does something like:
2200 The second .req creates the "Foo" alias but then fails to create
2201 the artificial FOO alias because it has already been created by the
2203 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2207 for (p = nbuf; *p; p++)
2210 if (strncmp (nbuf, newname, nlen))
2211 insert_reg_alias (nbuf, old->number, old->type);
2217 /* Create a Neon typed/indexed register alias using directives, e.g.:
2222 These typed registers can be used instead of the types specified after the
2223 Neon mnemonic, so long as all operands given have types. Types can also be
2224 specified directly, e.g.:
2225 vadd d0.s32, d1.s32, d2.s32 */
2228 create_neon_reg_alias (char *newname, char *p)
2230 enum arm_reg_type basetype;
2231 struct reg_entry *basereg;
2232 struct reg_entry mybasereg;
2233 struct neon_type ntype;
2234 struct neon_typed_alias typeinfo;
2235 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2238 typeinfo.defined = 0;
2239 typeinfo.eltype.type = NT_invtype;
2240 typeinfo.eltype.size = -1;
2241 typeinfo.index = -1;
2245 if (strncmp (p, " .dn ", 5) == 0)
2246 basetype = REG_TYPE_VFD;
2247 else if (strncmp (p, " .qn ", 5) == 0)
2248 basetype = REG_TYPE_NQ;
2257 basereg = arm_reg_parse_multi (&p);
2259 if (basereg && basereg->type != basetype)
2261 as_bad (_("bad type for register"));
2265 if (basereg == NULL)
2268 /* Try parsing as an integer. */
2269 my_get_expression (&exp, &p, GE_NO_PREFIX);
2270 if (exp.X_op != O_constant)
2272 as_bad (_("expression must be constant"));
2275 basereg = &mybasereg;
2276 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2282 typeinfo = *basereg->neon;
2284 if (parse_neon_type (&ntype, &p) == SUCCESS)
2286 /* We got a type. */
2287 if (typeinfo.defined & NTA_HASTYPE)
2289 as_bad (_("can't redefine the type of a register alias"));
2293 typeinfo.defined |= NTA_HASTYPE;
2294 if (ntype.elems != 1)
2296 as_bad (_("you must specify a single type only"));
2299 typeinfo.eltype = ntype.el[0];
2302 if (skip_past_char (&p, '[') == SUCCESS)
2305 /* We got a scalar index. */
2307 if (typeinfo.defined & NTA_HASINDEX)
2309 as_bad (_("can't redefine the index of a scalar alias"));
2313 my_get_expression (&exp, &p, GE_NO_PREFIX);
2315 if (exp.X_op != O_constant)
2317 as_bad (_("scalar index must be constant"));
2321 typeinfo.defined |= NTA_HASINDEX;
2322 typeinfo.index = exp.X_add_number;
2324 if (skip_past_char (&p, ']') == FAIL)
2326 as_bad (_("expecting ]"));
2331 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2332 the desired alias name, and p points to its end. If not, then
2333 the desired alias name is in the global original_case_string. */
2334 #ifdef TC_CASE_SENSITIVE
2335 namelen = nameend - newname;
2337 newname = original_case_string;
2338 namelen = strlen (newname);
2341 namebuf = (char *) alloca (namelen + 1);
2342 strncpy (namebuf, newname, namelen);
2343 namebuf[namelen] = '\0';
2345 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2346 typeinfo.defined != 0 ? &typeinfo : NULL);
2348 /* Insert name in all uppercase. */
2349 for (p = namebuf; *p; p++)
2352 if (strncmp (namebuf, newname, namelen))
2353 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2354 typeinfo.defined != 0 ? &typeinfo : NULL);
2356 /* Insert name in all lowercase. */
2357 for (p = namebuf; *p; p++)
2360 if (strncmp (namebuf, newname, namelen))
2361 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2362 typeinfo.defined != 0 ? &typeinfo : NULL);
2367 /* Should never be called, as .req goes between the alias and the
2368 register name, not at the beginning of the line. */
2371 s_req (int a ATTRIBUTE_UNUSED)
2373 as_bad (_("invalid syntax for .req directive"));
2377 s_dn (int a ATTRIBUTE_UNUSED)
2379 as_bad (_("invalid syntax for .dn directive"));
2383 s_qn (int a ATTRIBUTE_UNUSED)
2385 as_bad (_("invalid syntax for .qn directive"));
2388 /* The .unreq directive deletes an alias which was previously defined
2389 by .req. For example:
2395 s_unreq (int a ATTRIBUTE_UNUSED)
2400 name = input_line_pointer;
2402 while (*input_line_pointer != 0
2403 && *input_line_pointer != ' '
2404 && *input_line_pointer != '\n')
2405 ++input_line_pointer;
2407 saved_char = *input_line_pointer;
2408 *input_line_pointer = 0;
2411 as_bad (_("invalid syntax for .unreq directive"));
2414 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2418 as_bad (_("unknown register alias '%s'"), name);
2419 else if (reg->builtin)
2420 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2427 hash_delete (arm_reg_hsh, name, FALSE);
2428 free ((char *) reg->name);
2433 /* Also locate the all upper case and all lower case versions.
2434 Do not complain if we cannot find one or the other as it
2435 was probably deleted above. */
2437 nbuf = strdup (name);
2438 for (p = nbuf; *p; p++)
2440 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2443 hash_delete (arm_reg_hsh, nbuf, FALSE);
2444 free ((char *) reg->name);
2450 for (p = nbuf; *p; p++)
2452 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2455 hash_delete (arm_reg_hsh, nbuf, FALSE);
2456 free ((char *) reg->name);
2466 *input_line_pointer = saved_char;
2467 demand_empty_rest_of_line ();
2470 /* Directives: Instruction set selection. */
2473 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2474 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2475 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2476 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2478 /* Create a new mapping symbol for the transition to STATE. */
2481 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2484 const char * symname;
2491 type = BSF_NO_FLAGS;
2495 type = BSF_NO_FLAGS;
2499 type = BSF_NO_FLAGS;
2505 symbolP = symbol_new (symname, now_seg, value, frag);
2506 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2511 THUMB_SET_FUNC (symbolP, 0);
2512 ARM_SET_THUMB (symbolP, 0);
2513 ARM_SET_INTERWORK (symbolP, support_interwork);
2517 THUMB_SET_FUNC (symbolP, 1);
2518 ARM_SET_THUMB (symbolP, 1);
2519 ARM_SET_INTERWORK (symbolP, support_interwork);
2527 /* Save the mapping symbols for future reference. Also check that
2528 we do not place two mapping symbols at the same offset within a
2529 frag. We'll handle overlap between frags in
2530 check_mapping_symbols.
2532 If .fill or other data filling directive generates zero sized data,
2533 the mapping symbol for the following code will have the same value
2534 as the one generated for the data filling directive. In this case,
2535 we replace the old symbol with the new one at the same address. */
2538 if (frag->tc_frag_data.first_map != NULL)
2540 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2541 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2543 frag->tc_frag_data.first_map = symbolP;
2545 if (frag->tc_frag_data.last_map != NULL)
2547 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2548 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2549 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2551 frag->tc_frag_data.last_map = symbolP;
2554 /* We must sometimes convert a region marked as code to data during
2555 code alignment, if an odd number of bytes have to be padded. The
2556 code mapping symbol is pushed to an aligned address. */
2559 insert_data_mapping_symbol (enum mstate state,
2560 valueT value, fragS *frag, offsetT bytes)
2562 /* If there was already a mapping symbol, remove it. */
2563 if (frag->tc_frag_data.last_map != NULL
2564 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2566 symbolS *symp = frag->tc_frag_data.last_map;
2570 know (frag->tc_frag_data.first_map == symp);
2571 frag->tc_frag_data.first_map = NULL;
2573 frag->tc_frag_data.last_map = NULL;
2574 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2577 make_mapping_symbol (MAP_DATA, value, frag);
2578 make_mapping_symbol (state, value + bytes, frag);
2581 static void mapping_state_2 (enum mstate state, int max_chars);
2583 /* Set the mapping state to STATE. Only call this when about to
2584 emit some STATE bytes to the file. */
2587 mapping_state (enum mstate state)
2589 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2591 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2593 if (mapstate == state)
2594 /* The mapping symbol has already been emitted.
2595 There is nothing else to do. */
2598 if (state == MAP_ARM || state == MAP_THUMB)
2600 All ARM instructions require 4-byte alignment.
2601 (Almost) all Thumb instructions require 2-byte alignment.
2603 When emitting instructions into any section, mark the section
2606 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2607 but themselves require 2-byte alignment; this applies to some
2608 PC- relative forms. However, these cases will invovle implicit
2609 literal pool generation or an explicit .align >=2, both of
2610 which will cause the section to me marked with sufficient
2611 alignment. Thus, we don't handle those cases here. */
2612 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2614 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2615 /* This case will be evaluated later in the next else. */
2617 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2618 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2620 /* Only add the symbol if the offset is > 0:
2621 if we're at the first frag, check it's size > 0;
2622 if we're not at the first frag, then for sure
2623 the offset is > 0. */
2624 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2625 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2628 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2631 mapping_state_2 (state, 0);
2635 /* Same as mapping_state, but MAX_CHARS bytes have already been
2636 allocated. Put the mapping symbol that far back. */
2639 mapping_state_2 (enum mstate state, int max_chars)
2641 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2643 if (!SEG_NORMAL (now_seg))
2646 if (mapstate == state)
2647 /* The mapping symbol has already been emitted.
2648 There is nothing else to do. */
2651 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2652 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2655 #define mapping_state(x) ((void)0)
2656 #define mapping_state_2(x, y) ((void)0)
2659 /* Find the real, Thumb encoded start of a Thumb function. */
2663 find_real_start (symbolS * symbolP)
2666 const char * name = S_GET_NAME (symbolP);
2667 symbolS * new_target;
2669 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2670 #define STUB_NAME ".real_start_of"
2675 /* The compiler may generate BL instructions to local labels because
2676 it needs to perform a branch to a far away location. These labels
2677 do not have a corresponding ".real_start_of" label. We check
2678 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2679 the ".real_start_of" convention for nonlocal branches. */
2680 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2683 real_start = ACONCAT ((STUB_NAME, name, NULL));
2684 new_target = symbol_find (real_start);
2686 if (new_target == NULL)
2688 as_warn (_("Failed to find real start of function: %s\n"), name);
2689 new_target = symbolP;
2697 opcode_select (int width)
2704 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2705 as_bad (_("selected processor does not support THUMB opcodes"));
2708 /* No need to force the alignment, since we will have been
2709 coming from ARM mode, which is word-aligned. */
2710 record_alignment (now_seg, 1);
2717 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2718 as_bad (_("selected processor does not support ARM opcodes"));
2723 frag_align (2, 0, 0);
2725 record_alignment (now_seg, 1);
2730 as_bad (_("invalid instruction size selected (%d)"), width);
2735 s_arm (int ignore ATTRIBUTE_UNUSED)
2738 demand_empty_rest_of_line ();
2742 s_thumb (int ignore ATTRIBUTE_UNUSED)
2745 demand_empty_rest_of_line ();
2749 s_code (int unused ATTRIBUTE_UNUSED)
2753 temp = get_absolute_expression ();
2758 opcode_select (temp);
2762 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2767 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2769 /* If we are not already in thumb mode go into it, EVEN if
2770 the target processor does not support thumb instructions.
2771 This is used by gcc/config/arm/lib1funcs.asm for example
2772 to compile interworking support functions even if the
2773 target processor should not support interworking. */
2777 record_alignment (now_seg, 1);
2780 demand_empty_rest_of_line ();
2784 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2788 /* The following label is the name/address of the start of a Thumb function.
2789 We need to know this for the interworking support. */
2790 label_is_thumb_function_name = TRUE;
2793 /* Perform a .set directive, but also mark the alias as
2794 being a thumb function. */
2797 s_thumb_set (int equiv)
2799 /* XXX the following is a duplicate of the code for s_set() in read.c
2800 We cannot just call that code as we need to get at the symbol that
2807 /* Especial apologies for the random logic:
2808 This just grew, and could be parsed much more simply!
2810 name = input_line_pointer;
2811 delim = get_symbol_end ();
2812 end_name = input_line_pointer;
2815 if (*input_line_pointer != ',')
2818 as_bad (_("expected comma after name \"%s\""), name);
2820 ignore_rest_of_line ();
2824 input_line_pointer++;
2827 if (name[0] == '.' && name[1] == '\0')
2829 /* XXX - this should not happen to .thumb_set. */
2833 if ((symbolP = symbol_find (name)) == NULL
2834 && (symbolP = md_undefined_symbol (name)) == NULL)
2837 /* When doing symbol listings, play games with dummy fragments living
2838 outside the normal fragment chain to record the file and line info
2840 if (listing & LISTING_SYMBOLS)
2842 extern struct list_info_struct * listing_tail;
2843 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2845 memset (dummy_frag, 0, sizeof (fragS));
2846 dummy_frag->fr_type = rs_fill;
2847 dummy_frag->line = listing_tail;
2848 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2849 dummy_frag->fr_symbol = symbolP;
2853 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2856 /* "set" symbols are local unless otherwise specified. */
2857 SF_SET_LOCAL (symbolP);
2858 #endif /* OBJ_COFF */
2859 } /* Make a new symbol. */
2861 symbol_table_insert (symbolP);
2866 && S_IS_DEFINED (symbolP)
2867 && S_GET_SEGMENT (symbolP) != reg_section)
2868 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2870 pseudo_set (symbolP);
2872 demand_empty_rest_of_line ();
2874 /* XXX Now we come to the Thumb specific bit of code. */
2876 THUMB_SET_FUNC (symbolP, 1);
2877 ARM_SET_THUMB (symbolP, 1);
2878 #if defined OBJ_ELF || defined OBJ_COFF
2879 ARM_SET_INTERWORK (symbolP, support_interwork);
2883 /* Directives: Mode selection. */
2885 /* .syntax [unified|divided] - choose the new unified syntax
2886 (same for Arm and Thumb encoding, modulo slight differences in what
2887 can be represented) or the old divergent syntax for each mode. */
2889 s_syntax (int unused ATTRIBUTE_UNUSED)
2893 name = input_line_pointer;
2894 delim = get_symbol_end ();
2896 if (!strcasecmp (name, "unified"))
2897 unified_syntax = TRUE;
2898 else if (!strcasecmp (name, "divided"))
2899 unified_syntax = FALSE;
2902 as_bad (_("unrecognized syntax mode \"%s\""), name);
2905 *input_line_pointer = delim;
2906 demand_empty_rest_of_line ();
2909 /* Directives: sectioning and alignment. */
2911 /* Same as s_align_ptwo but align 0 => align 2. */
2914 s_align (int unused ATTRIBUTE_UNUSED)
2919 long max_alignment = 15;
2921 temp = get_absolute_expression ();
2922 if (temp > max_alignment)
2923 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2926 as_bad (_("alignment negative. 0 assumed."));
2930 if (*input_line_pointer == ',')
2932 input_line_pointer++;
2933 temp_fill = get_absolute_expression ();
2945 /* Only make a frag if we HAVE to. */
2946 if (temp && !need_pass_2)
2948 if (!fill_p && subseg_text_p (now_seg))
2949 frag_align_code (temp, 0);
2951 frag_align (temp, (int) temp_fill, 0);
2953 demand_empty_rest_of_line ();
2955 record_alignment (now_seg, temp);
2959 s_bss (int ignore ATTRIBUTE_UNUSED)
2961 /* We don't support putting frags in the BSS segment, we fake it by
2962 marking in_bss, then looking at s_skip for clues. */
2963 subseg_set (bss_section, 0);
2964 demand_empty_rest_of_line ();
2966 #ifdef md_elf_section_change_hook
2967 md_elf_section_change_hook ();
2972 s_even (int ignore ATTRIBUTE_UNUSED)
2974 /* Never make frag if expect extra pass. */
2976 frag_align (1, 0, 0);
2978 record_alignment (now_seg, 1);
2980 demand_empty_rest_of_line ();
2983 /* Directives: Literal pools. */
2985 static literal_pool *
2986 find_literal_pool (void)
2988 literal_pool * pool;
2990 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2992 if (pool->section == now_seg
2993 && pool->sub_section == now_subseg)
3000 static literal_pool *
3001 find_or_make_literal_pool (void)
3003 /* Next literal pool ID number. */
3004 static unsigned int latest_pool_num = 1;
3005 literal_pool * pool;
3007 pool = find_literal_pool ();
3011 /* Create a new pool. */
3012 pool = (literal_pool *) xmalloc (sizeof (* pool));
3016 pool->next_free_entry = 0;
3017 pool->section = now_seg;
3018 pool->sub_section = now_subseg;
3019 pool->next = list_of_pools;
3020 pool->symbol = NULL;
3022 /* Add it to the list. */
3023 list_of_pools = pool;
3026 /* New pools, and emptied pools, will have a NULL symbol. */
3027 if (pool->symbol == NULL)
3029 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3030 (valueT) 0, &zero_address_frag);
3031 pool->id = latest_pool_num ++;
3038 /* Add the literal in the global 'inst'
3039 structure to the relevant literal pool. */
3042 add_to_lit_pool (void)
3044 literal_pool * pool;
3047 pool = find_or_make_literal_pool ();
3049 /* Check if this literal value is already in the pool. */
3050 for (entry = 0; entry < pool->next_free_entry; entry ++)
3052 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3053 && (inst.reloc.exp.X_op == O_constant)
3054 && (pool->literals[entry].X_add_number
3055 == inst.reloc.exp.X_add_number)
3056 && (pool->literals[entry].X_unsigned
3057 == inst.reloc.exp.X_unsigned))
3060 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3061 && (inst.reloc.exp.X_op == O_symbol)
3062 && (pool->literals[entry].X_add_number
3063 == inst.reloc.exp.X_add_number)
3064 && (pool->literals[entry].X_add_symbol
3065 == inst.reloc.exp.X_add_symbol)
3066 && (pool->literals[entry].X_op_symbol
3067 == inst.reloc.exp.X_op_symbol))
3071 /* Do we need to create a new entry? */
3072 if (entry == pool->next_free_entry)
3074 if (entry >= MAX_LITERAL_POOL_SIZE)
3076 inst.error = _("literal pool overflow");
3080 pool->literals[entry] = inst.reloc.exp;
3082 /* PR ld/12974: Record the location of the first source line to reference
3083 this entry in the literal pool. If it turns out during linking that the
3084 symbol does not exist we will be able to give an accurate line number for
3085 the (first use of the) missing reference. */
3086 if (debug_type == DEBUG_DWARF2)
3087 dwarf2_where (pool->locs + entry);
3089 pool->next_free_entry += 1;
3092 inst.reloc.exp.X_op = O_symbol;
3093 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3094 inst.reloc.exp.X_add_symbol = pool->symbol;
3099 /* Can't use symbol_new here, so have to create a symbol and then at
3100 a later date assign it a value. Thats what these functions do. */
3103 symbol_locate (symbolS * symbolP,
3104 const char * name, /* It is copied, the caller can modify. */
3105 segT segment, /* Segment identifier (SEG_<something>). */
3106 valueT valu, /* Symbol value. */
3107 fragS * frag) /* Associated fragment. */
3109 unsigned int name_length;
3110 char * preserved_copy_of_name;
3112 name_length = strlen (name) + 1; /* +1 for \0. */
3113 obstack_grow (¬es, name, name_length);
3114 preserved_copy_of_name = (char *) obstack_finish (¬es);
3116 #ifdef tc_canonicalize_symbol_name
3117 preserved_copy_of_name =
3118 tc_canonicalize_symbol_name (preserved_copy_of_name);
3121 S_SET_NAME (symbolP, preserved_copy_of_name);
3123 S_SET_SEGMENT (symbolP, segment);
3124 S_SET_VALUE (symbolP, valu);
3125 symbol_clear_list_pointers (symbolP);
3127 symbol_set_frag (symbolP, frag);
3129 /* Link to end of symbol chain. */
3131 extern int symbol_table_frozen;
3133 if (symbol_table_frozen)
3137 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3139 obj_symbol_new_hook (symbolP);
3141 #ifdef tc_symbol_new_hook
3142 tc_symbol_new_hook (symbolP);
3146 verify_symbol_chain (symbol_rootP, symbol_lastP);
3147 #endif /* DEBUG_SYMS */
3152 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3155 literal_pool * pool;
3158 pool = find_literal_pool ();
3160 || pool->symbol == NULL
3161 || pool->next_free_entry == 0)
3164 mapping_state (MAP_DATA);
3166 /* Align pool as you have word accesses.
3167 Only make a frag if we have to. */
3169 frag_align (2, 0, 0);
3171 record_alignment (now_seg, 2);
3173 sprintf (sym_name, "$$lit_\002%x", pool->id);
3175 symbol_locate (pool->symbol, sym_name, now_seg,
3176 (valueT) frag_now_fix (), frag_now);
3177 symbol_table_insert (pool->symbol);
3179 ARM_SET_THUMB (pool->symbol, thumb_mode);
3181 #if defined OBJ_COFF || defined OBJ_ELF
3182 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3185 for (entry = 0; entry < pool->next_free_entry; entry ++)
3188 if (debug_type == DEBUG_DWARF2)
3189 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3191 /* First output the expression in the instruction to the pool. */
3192 emit_expr (&(pool->literals[entry]), 4); /* .word */
3195 /* Mark the pool as empty. */
3196 pool->next_free_entry = 0;
3197 pool->symbol = NULL;
3201 /* Forward declarations for functions below, in the MD interface
3203 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3204 static valueT create_unwind_entry (int);
3205 static void start_unwind_section (const segT, int);
3206 static void add_unwind_opcode (valueT, int);
3207 static void flush_pending_unwind (void);
3209 /* Directives: Data. */
3212 s_arm_elf_cons (int nbytes)
3216 #ifdef md_flush_pending_output
3217 md_flush_pending_output ();
3220 if (is_it_end_of_statement ())
3222 demand_empty_rest_of_line ();
3226 #ifdef md_cons_align
3227 md_cons_align (nbytes);
3230 mapping_state (MAP_DATA);
3234 char *base = input_line_pointer;
3238 if (exp.X_op != O_symbol)
3239 emit_expr (&exp, (unsigned int) nbytes);
3242 char *before_reloc = input_line_pointer;
3243 reloc = parse_reloc (&input_line_pointer);
3246 as_bad (_("unrecognized relocation suffix"));
3247 ignore_rest_of_line ();
3250 else if (reloc == BFD_RELOC_UNUSED)
3251 emit_expr (&exp, (unsigned int) nbytes);
3254 reloc_howto_type *howto = (reloc_howto_type *)
3255 bfd_reloc_type_lookup (stdoutput,
3256 (bfd_reloc_code_real_type) reloc);
3257 int size = bfd_get_reloc_size (howto);
3259 if (reloc == BFD_RELOC_ARM_PLT32)
3261 as_bad (_("(plt) is only valid on branch targets"));
3262 reloc = BFD_RELOC_UNUSED;
3267 as_bad (_("%s relocations do not fit in %d bytes"),
3268 howto->name, nbytes);
3271 /* We've parsed an expression stopping at O_symbol.
3272 But there may be more expression left now that we
3273 have parsed the relocation marker. Parse it again.
3274 XXX Surely there is a cleaner way to do this. */
3275 char *p = input_line_pointer;
3277 char *save_buf = (char *) alloca (input_line_pointer - base);
3278 memcpy (save_buf, base, input_line_pointer - base);
3279 memmove (base + (input_line_pointer - before_reloc),
3280 base, before_reloc - base);
3282 input_line_pointer = base + (input_line_pointer-before_reloc);
3284 memcpy (base, save_buf, p - base);
3286 offset = nbytes - size;
3287 p = frag_more ((int) nbytes);
3288 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3289 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3294 while (*input_line_pointer++ == ',');
3296 /* Put terminator back into stream. */
3297 input_line_pointer --;
3298 demand_empty_rest_of_line ();
3301 /* Emit an expression containing a 32-bit thumb instruction.
3302 Implementation based on put_thumb32_insn. */
3305 emit_thumb32_expr (expressionS * exp)
3307 expressionS exp_high = *exp;
3309 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3310 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3311 exp->X_add_number &= 0xffff;
3312 emit_expr (exp, (unsigned int) THUMB_SIZE);
3315 /* Guess the instruction size based on the opcode. */
3318 thumb_insn_size (int opcode)
3320 if ((unsigned int) opcode < 0xe800u)
3322 else if ((unsigned int) opcode >= 0xe8000000u)
3329 emit_insn (expressionS *exp, int nbytes)
3333 if (exp->X_op == O_constant)
3338 size = thumb_insn_size (exp->X_add_number);
3342 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3344 as_bad (_(".inst.n operand too big. "\
3345 "Use .inst.w instead"));
3350 if (now_it.state == AUTOMATIC_IT_BLOCK)
3351 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3353 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3355 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3356 emit_thumb32_expr (exp);
3358 emit_expr (exp, (unsigned int) size);
3360 it_fsm_post_encode ();
3364 as_bad (_("cannot determine Thumb instruction size. " \
3365 "Use .inst.n/.inst.w instead"));
3368 as_bad (_("constant expression required"));
3373 /* Like s_arm_elf_cons but do not use md_cons_align and
3374 set the mapping state to MAP_ARM/MAP_THUMB. */
3377 s_arm_elf_inst (int nbytes)
3379 if (is_it_end_of_statement ())
3381 demand_empty_rest_of_line ();
3385 /* Calling mapping_state () here will not change ARM/THUMB,
3386 but will ensure not to be in DATA state. */
3389 mapping_state (MAP_THUMB);
3394 as_bad (_("width suffixes are invalid in ARM mode"));
3395 ignore_rest_of_line ();
3401 mapping_state (MAP_ARM);
3410 if (! emit_insn (& exp, nbytes))
3412 ignore_rest_of_line ();
3416 while (*input_line_pointer++ == ',');
3418 /* Put terminator back into stream. */
3419 input_line_pointer --;
3420 demand_empty_rest_of_line ();
3423 /* Parse a .rel31 directive. */
3426 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3433 if (*input_line_pointer == '1')
3434 highbit = 0x80000000;
3435 else if (*input_line_pointer != '0')
3436 as_bad (_("expected 0 or 1"));
3438 input_line_pointer++;
3439 if (*input_line_pointer != ',')
3440 as_bad (_("missing comma"));
3441 input_line_pointer++;
3443 #ifdef md_flush_pending_output
3444 md_flush_pending_output ();
3447 #ifdef md_cons_align
3451 mapping_state (MAP_DATA);
3456 md_number_to_chars (p, highbit, 4);
3457 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3458 BFD_RELOC_ARM_PREL31);
3460 demand_empty_rest_of_line ();
3463 /* Directives: AEABI stack-unwind tables. */
3465 /* Parse an unwind_fnstart directive. Simply records the current location. */
3468 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3470 demand_empty_rest_of_line ();
3471 if (unwind.proc_start)
3473 as_bad (_("duplicate .fnstart directive"));
3477 /* Mark the start of the function. */
3478 unwind.proc_start = expr_build_dot ();
3480 /* Reset the rest of the unwind info. */
3481 unwind.opcode_count = 0;
3482 unwind.table_entry = NULL;
3483 unwind.personality_routine = NULL;
3484 unwind.personality_index = -1;
3485 unwind.frame_size = 0;
3486 unwind.fp_offset = 0;
3487 unwind.fp_reg = REG_SP;
3489 unwind.sp_restored = 0;
3493 /* Parse a handlerdata directive. Creates the exception handling table entry
3494 for the function. */
3497 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3499 demand_empty_rest_of_line ();
3500 if (!unwind.proc_start)
3501 as_bad (MISSING_FNSTART);
3503 if (unwind.table_entry)
3504 as_bad (_("duplicate .handlerdata directive"));
3506 create_unwind_entry (1);
3509 /* Parse an unwind_fnend directive. Generates the index table entry. */
3512 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3517 unsigned int marked_pr_dependency;
3519 demand_empty_rest_of_line ();
3521 if (!unwind.proc_start)
3523 as_bad (_(".fnend directive without .fnstart"));
3527 /* Add eh table entry. */
3528 if (unwind.table_entry == NULL)
3529 val = create_unwind_entry (0);
3533 /* Add index table entry. This is two words. */
3534 start_unwind_section (unwind.saved_seg, 1);
3535 frag_align (2, 0, 0);
3536 record_alignment (now_seg, 2);
3538 ptr = frag_more (8);
3539 where = frag_now_fix () - 8;
3541 /* Self relative offset of the function start. */
3542 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3543 BFD_RELOC_ARM_PREL31);
3545 /* Indicate dependency on EHABI-defined personality routines to the
3546 linker, if it hasn't been done already. */
3547 marked_pr_dependency
3548 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3549 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3550 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3552 static const char *const name[] =
3554 "__aeabi_unwind_cpp_pr0",
3555 "__aeabi_unwind_cpp_pr1",
3556 "__aeabi_unwind_cpp_pr2"
3558 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3559 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3560 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3561 |= 1 << unwind.personality_index;
3565 /* Inline exception table entry. */
3566 md_number_to_chars (ptr + 4, val, 4);
3568 /* Self relative offset of the table entry. */
3569 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3570 BFD_RELOC_ARM_PREL31);
3572 /* Restore the original section. */
3573 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3575 unwind.proc_start = NULL;
3579 /* Parse an unwind_cantunwind directive. */
3582 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3584 demand_empty_rest_of_line ();
3585 if (!unwind.proc_start)
3586 as_bad (MISSING_FNSTART);
3588 if (unwind.personality_routine || unwind.personality_index != -1)
3589 as_bad (_("personality routine specified for cantunwind frame"));
3591 unwind.personality_index = -2;
3595 /* Parse a personalityindex directive. */
3598 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3602 if (!unwind.proc_start)
3603 as_bad (MISSING_FNSTART);
3605 if (unwind.personality_routine || unwind.personality_index != -1)
3606 as_bad (_("duplicate .personalityindex directive"));
3610 if (exp.X_op != O_constant
3611 || exp.X_add_number < 0 || exp.X_add_number > 15)
3613 as_bad (_("bad personality routine number"));
3614 ignore_rest_of_line ();
3618 unwind.personality_index = exp.X_add_number;
3620 demand_empty_rest_of_line ();
3624 /* Parse a personality directive. */
3627 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3631 if (!unwind.proc_start)
3632 as_bad (MISSING_FNSTART);
3634 if (unwind.personality_routine || unwind.personality_index != -1)
3635 as_bad (_("duplicate .personality directive"));
3637 name = input_line_pointer;
3638 c = get_symbol_end ();
3639 p = input_line_pointer;
3640 unwind.personality_routine = symbol_find_or_make (name);
3642 demand_empty_rest_of_line ();
3646 /* Parse a directive saving core registers. */
3649 s_arm_unwind_save_core (void)
3655 range = parse_reg_list (&input_line_pointer);
3658 as_bad (_("expected register list"));
3659 ignore_rest_of_line ();
3663 demand_empty_rest_of_line ();
3665 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3666 into .unwind_save {..., sp...}. We aren't bothered about the value of
3667 ip because it is clobbered by calls. */
3668 if (unwind.sp_restored && unwind.fp_reg == 12
3669 && (range & 0x3000) == 0x1000)
3671 unwind.opcode_count--;
3672 unwind.sp_restored = 0;
3673 range = (range | 0x2000) & ~0x1000;
3674 unwind.pending_offset = 0;
3680 /* See if we can use the short opcodes. These pop a block of up to 8
3681 registers starting with r4, plus maybe r14. */
3682 for (n = 0; n < 8; n++)
3684 /* Break at the first non-saved register. */
3685 if ((range & (1 << (n + 4))) == 0)
3688 /* See if there are any other bits set. */
3689 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3691 /* Use the long form. */
3692 op = 0x8000 | ((range >> 4) & 0xfff);
3693 add_unwind_opcode (op, 2);
3697 /* Use the short form. */
3699 op = 0xa8; /* Pop r14. */
3701 op = 0xa0; /* Do not pop r14. */
3703 add_unwind_opcode (op, 1);
3710 op = 0xb100 | (range & 0xf);
3711 add_unwind_opcode (op, 2);
3714 /* Record the number of bytes pushed. */
3715 for (n = 0; n < 16; n++)
3717 if (range & (1 << n))
3718 unwind.frame_size += 4;
3723 /* Parse a directive saving FPA registers. */
3726 s_arm_unwind_save_fpa (int reg)
3732 /* Get Number of registers to transfer. */
3733 if (skip_past_comma (&input_line_pointer) != FAIL)
3736 exp.X_op = O_illegal;
3738 if (exp.X_op != O_constant)
3740 as_bad (_("expected , <constant>"));
3741 ignore_rest_of_line ();
3745 num_regs = exp.X_add_number;
3747 if (num_regs < 1 || num_regs > 4)
3749 as_bad (_("number of registers must be in the range [1:4]"));
3750 ignore_rest_of_line ();
3754 demand_empty_rest_of_line ();
3759 op = 0xb4 | (num_regs - 1);
3760 add_unwind_opcode (op, 1);
3765 op = 0xc800 | (reg << 4) | (num_regs - 1);
3766 add_unwind_opcode (op, 2);
3768 unwind.frame_size += num_regs * 12;
3772 /* Parse a directive saving VFP registers for ARMv6 and above. */
3775 s_arm_unwind_save_vfp_armv6 (void)
3780 int num_vfpv3_regs = 0;
3781 int num_regs_below_16;
3783 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3786 as_bad (_("expected register list"));
3787 ignore_rest_of_line ();
3791 demand_empty_rest_of_line ();
3793 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3794 than FSTMX/FLDMX-style ones). */
3796 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3798 num_vfpv3_regs = count;
3799 else if (start + count > 16)
3800 num_vfpv3_regs = start + count - 16;
3802 if (num_vfpv3_regs > 0)
3804 int start_offset = start > 16 ? start - 16 : 0;
3805 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3806 add_unwind_opcode (op, 2);
3809 /* Generate opcode for registers numbered in the range 0 .. 15. */
3810 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3811 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3812 if (num_regs_below_16 > 0)
3814 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3815 add_unwind_opcode (op, 2);
3818 unwind.frame_size += count * 8;
3822 /* Parse a directive saving VFP registers for pre-ARMv6. */
3825 s_arm_unwind_save_vfp (void)
3831 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3834 as_bad (_("expected register list"));
3835 ignore_rest_of_line ();
3839 demand_empty_rest_of_line ();
3844 op = 0xb8 | (count - 1);
3845 add_unwind_opcode (op, 1);
3850 op = 0xb300 | (reg << 4) | (count - 1);
3851 add_unwind_opcode (op, 2);
3853 unwind.frame_size += count * 8 + 4;
3857 /* Parse a directive saving iWMMXt data registers. */
3860 s_arm_unwind_save_mmxwr (void)
3868 if (*input_line_pointer == '{')
3869 input_line_pointer++;
3873 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3877 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3882 as_tsktsk (_("register list not in ascending order"));
3885 if (*input_line_pointer == '-')
3887 input_line_pointer++;
3888 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3891 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3894 else if (reg >= hi_reg)
3896 as_bad (_("bad register range"));
3899 for (; reg < hi_reg; reg++)
3903 while (skip_past_comma (&input_line_pointer) != FAIL);
3905 if (*input_line_pointer == '}')
3906 input_line_pointer++;
3908 demand_empty_rest_of_line ();
3910 /* Generate any deferred opcodes because we're going to be looking at
3912 flush_pending_unwind ();
3914 for (i = 0; i < 16; i++)
3916 if (mask & (1 << i))
3917 unwind.frame_size += 8;
3920 /* Attempt to combine with a previous opcode. We do this because gcc
3921 likes to output separate unwind directives for a single block of
3923 if (unwind.opcode_count > 0)
3925 i = unwind.opcodes[unwind.opcode_count - 1];
3926 if ((i & 0xf8) == 0xc0)
3929 /* Only merge if the blocks are contiguous. */
3932 if ((mask & 0xfe00) == (1 << 9))
3934 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3935 unwind.opcode_count--;
3938 else if (i == 6 && unwind.opcode_count >= 2)
3940 i = unwind.opcodes[unwind.opcode_count - 2];
3944 op = 0xffff << (reg - 1);
3946 && ((mask & op) == (1u << (reg - 1))))
3948 op = (1 << (reg + i + 1)) - 1;
3949 op &= ~((1 << reg) - 1);
3951 unwind.opcode_count -= 2;
3958 /* We want to generate opcodes in the order the registers have been
3959 saved, ie. descending order. */
3960 for (reg = 15; reg >= -1; reg--)
3962 /* Save registers in blocks. */
3964 || !(mask & (1 << reg)))
3966 /* We found an unsaved reg. Generate opcodes to save the
3973 op = 0xc0 | (hi_reg - 10);
3974 add_unwind_opcode (op, 1);
3979 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3980 add_unwind_opcode (op, 2);
3989 ignore_rest_of_line ();
3993 s_arm_unwind_save_mmxwcg (void)
4000 if (*input_line_pointer == '{')
4001 input_line_pointer++;
4005 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4009 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4015 as_tsktsk (_("register list not in ascending order"));
4018 if (*input_line_pointer == '-')
4020 input_line_pointer++;
4021 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4024 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4027 else if (reg >= hi_reg)
4029 as_bad (_("bad register range"));
4032 for (; reg < hi_reg; reg++)
4036 while (skip_past_comma (&input_line_pointer) != FAIL);
4038 if (*input_line_pointer == '}')
4039 input_line_pointer++;
4041 demand_empty_rest_of_line ();
4043 /* Generate any deferred opcodes because we're going to be looking at
4045 flush_pending_unwind ();
4047 for (reg = 0; reg < 16; reg++)
4049 if (mask & (1 << reg))
4050 unwind.frame_size += 4;
4053 add_unwind_opcode (op, 2);
4056 ignore_rest_of_line ();
4060 /* Parse an unwind_save directive.
4061 If the argument is non-zero, this is a .vsave directive. */
4064 s_arm_unwind_save (int arch_v6)
4067 struct reg_entry *reg;
4068 bfd_boolean had_brace = FALSE;
4070 if (!unwind.proc_start)
4071 as_bad (MISSING_FNSTART);
4073 /* Figure out what sort of save we have. */
4074 peek = input_line_pointer;
4082 reg = arm_reg_parse_multi (&peek);
4086 as_bad (_("register expected"));
4087 ignore_rest_of_line ();
4096 as_bad (_("FPA .unwind_save does not take a register list"));
4097 ignore_rest_of_line ();
4100 input_line_pointer = peek;
4101 s_arm_unwind_save_fpa (reg->number);
4104 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4107 s_arm_unwind_save_vfp_armv6 ();
4109 s_arm_unwind_save_vfp ();
4111 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4112 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4115 as_bad (_(".unwind_save does not support this kind of register"));
4116 ignore_rest_of_line ();
4121 /* Parse an unwind_movsp directive. */
4124 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4130 if (!unwind.proc_start)
4131 as_bad (MISSING_FNSTART);
4133 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4136 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4137 ignore_rest_of_line ();
4141 /* Optional constant. */
4142 if (skip_past_comma (&input_line_pointer) != FAIL)
4144 if (immediate_for_directive (&offset) == FAIL)
4150 demand_empty_rest_of_line ();
4152 if (reg == REG_SP || reg == REG_PC)
4154 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4158 if (unwind.fp_reg != REG_SP)
4159 as_bad (_("unexpected .unwind_movsp directive"));
4161 /* Generate opcode to restore the value. */
4163 add_unwind_opcode (op, 1);
4165 /* Record the information for later. */
4166 unwind.fp_reg = reg;
4167 unwind.fp_offset = unwind.frame_size - offset;
4168 unwind.sp_restored = 1;
4171 /* Parse an unwind_pad directive. */
4174 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4178 if (!unwind.proc_start)
4179 as_bad (MISSING_FNSTART);
4181 if (immediate_for_directive (&offset) == FAIL)
4186 as_bad (_("stack increment must be multiple of 4"));
4187 ignore_rest_of_line ();
4191 /* Don't generate any opcodes, just record the details for later. */
4192 unwind.frame_size += offset;
4193 unwind.pending_offset += offset;
4195 demand_empty_rest_of_line ();
4198 /* Parse an unwind_setfp directive. */
4201 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4207 if (!unwind.proc_start)
4208 as_bad (MISSING_FNSTART);
4210 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4211 if (skip_past_comma (&input_line_pointer) == FAIL)
4214 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4216 if (fp_reg == FAIL || sp_reg == FAIL)
4218 as_bad (_("expected <reg>, <reg>"));
4219 ignore_rest_of_line ();
4223 /* Optional constant. */
4224 if (skip_past_comma (&input_line_pointer) != FAIL)
4226 if (immediate_for_directive (&offset) == FAIL)
4232 demand_empty_rest_of_line ();
4234 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4236 as_bad (_("register must be either sp or set by a previous"
4237 "unwind_movsp directive"));
4241 /* Don't generate any opcodes, just record the information for later. */
4242 unwind.fp_reg = fp_reg;
4244 if (sp_reg == REG_SP)
4245 unwind.fp_offset = unwind.frame_size - offset;
4247 unwind.fp_offset -= offset;
4250 /* Parse an unwind_raw directive. */
4253 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4256 /* This is an arbitrary limit. */
4257 unsigned char op[16];
4260 if (!unwind.proc_start)
4261 as_bad (MISSING_FNSTART);
4264 if (exp.X_op == O_constant
4265 && skip_past_comma (&input_line_pointer) != FAIL)
4267 unwind.frame_size += exp.X_add_number;
4271 exp.X_op = O_illegal;
4273 if (exp.X_op != O_constant)
4275 as_bad (_("expected <offset>, <opcode>"));
4276 ignore_rest_of_line ();
4282 /* Parse the opcode. */
4287 as_bad (_("unwind opcode too long"));
4288 ignore_rest_of_line ();
4290 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4292 as_bad (_("invalid unwind opcode"));
4293 ignore_rest_of_line ();
4296 op[count++] = exp.X_add_number;
4298 /* Parse the next byte. */
4299 if (skip_past_comma (&input_line_pointer) == FAIL)
4305 /* Add the opcode bytes in reverse order. */
4307 add_unwind_opcode (op[count], 1);
4309 demand_empty_rest_of_line ();
4313 /* Parse a .eabi_attribute directive. */
4316 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4318 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4320 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4321 attributes_set_explicitly[tag] = 1;
4324 /* Emit a tls fix for the symbol. */
4327 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4331 #ifdef md_flush_pending_output
4332 md_flush_pending_output ();
4335 #ifdef md_cons_align
4339 /* Since we're just labelling the code, there's no need to define a
4342 p = obstack_next_free (&frchain_now->frch_obstack);
4343 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4344 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4345 : BFD_RELOC_ARM_TLS_DESCSEQ);
4347 #endif /* OBJ_ELF */
4349 static void s_arm_arch (int);
4350 static void s_arm_object_arch (int);
4351 static void s_arm_cpu (int);
4352 static void s_arm_fpu (int);
4353 static void s_arm_arch_extension (int);
4358 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4365 if (exp.X_op == O_symbol)
4366 exp.X_op = O_secrel;
4368 emit_expr (&exp, 4);
4370 while (*input_line_pointer++ == ',');
4372 input_line_pointer--;
4373 demand_empty_rest_of_line ();
4377 /* This table describes all the machine specific pseudo-ops the assembler
4378 has to support. The fields are:
4379 pseudo-op name without dot
4380 function to call to execute this pseudo-op
4381 Integer arg to pass to the function. */
4383 const pseudo_typeS md_pseudo_table[] =
4385 /* Never called because '.req' does not start a line. */
4386 { "req", s_req, 0 },
4387 /* Following two are likewise never called. */
4390 { "unreq", s_unreq, 0 },
4391 { "bss", s_bss, 0 },
4392 { "align", s_align, 0 },
4393 { "arm", s_arm, 0 },
4394 { "thumb", s_thumb, 0 },
4395 { "code", s_code, 0 },
4396 { "force_thumb", s_force_thumb, 0 },
4397 { "thumb_func", s_thumb_func, 0 },
4398 { "thumb_set", s_thumb_set, 0 },
4399 { "even", s_even, 0 },
4400 { "ltorg", s_ltorg, 0 },
4401 { "pool", s_ltorg, 0 },
4402 { "syntax", s_syntax, 0 },
4403 { "cpu", s_arm_cpu, 0 },
4404 { "arch", s_arm_arch, 0 },
4405 { "object_arch", s_arm_object_arch, 0 },
4406 { "fpu", s_arm_fpu, 0 },
4407 { "arch_extension", s_arm_arch_extension, 0 },
4409 { "word", s_arm_elf_cons, 4 },
4410 { "long", s_arm_elf_cons, 4 },
4411 { "inst.n", s_arm_elf_inst, 2 },
4412 { "inst.w", s_arm_elf_inst, 4 },
4413 { "inst", s_arm_elf_inst, 0 },
4414 { "rel31", s_arm_rel31, 0 },
4415 { "fnstart", s_arm_unwind_fnstart, 0 },
4416 { "fnend", s_arm_unwind_fnend, 0 },
4417 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4418 { "personality", s_arm_unwind_personality, 0 },
4419 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4420 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4421 { "save", s_arm_unwind_save, 0 },
4422 { "vsave", s_arm_unwind_save, 1 },
4423 { "movsp", s_arm_unwind_movsp, 0 },
4424 { "pad", s_arm_unwind_pad, 0 },
4425 { "setfp", s_arm_unwind_setfp, 0 },
4426 { "unwind_raw", s_arm_unwind_raw, 0 },
4427 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4428 { "tlsdescseq", s_arm_tls_descseq, 0 },
4432 /* These are used for dwarf. */
4436 /* These are used for dwarf2. */
4437 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4438 { "loc", dwarf2_directive_loc, 0 },
4439 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4441 { "extend", float_cons, 'x' },
4442 { "ldouble", float_cons, 'x' },
4443 { "packed", float_cons, 'p' },
4445 {"secrel32", pe_directive_secrel, 0},
4450 /* Parser functions used exclusively in instruction operands. */
4452 /* Generic immediate-value read function for use in insn parsing.
4453 STR points to the beginning of the immediate (the leading #);
4454 VAL receives the value; if the value is outside [MIN, MAX]
4455 issue an error. PREFIX_OPT is true if the immediate prefix is
4459 parse_immediate (char **str, int *val, int min, int max,
4460 bfd_boolean prefix_opt)
4463 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4464 if (exp.X_op != O_constant)
4466 inst.error = _("constant expression required");
4470 if (exp.X_add_number < min || exp.X_add_number > max)
4472 inst.error = _("immediate value out of range");
4476 *val = exp.X_add_number;
4480 /* Less-generic immediate-value read function with the possibility of loading a
4481 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4482 instructions. Puts the result directly in inst.operands[i]. */
4485 parse_big_immediate (char **str, int i)
4490 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4492 if (exp.X_op == O_constant)
4494 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4495 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4496 O_constant. We have to be careful not to break compilation for
4497 32-bit X_add_number, though. */
4498 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4500 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4501 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4502 inst.operands[i].regisimm = 1;
4505 else if (exp.X_op == O_big
4506 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4508 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4510 /* Bignums have their least significant bits in
4511 generic_bignum[0]. Make sure we put 32 bits in imm and
4512 32 bits in reg, in a (hopefully) portable way. */
4513 gas_assert (parts != 0);
4515 /* Make sure that the number is not too big.
4516 PR 11972: Bignums can now be sign-extended to the
4517 size of a .octa so check that the out of range bits
4518 are all zero or all one. */
4519 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4521 LITTLENUM_TYPE m = -1;
4523 if (generic_bignum[parts * 2] != 0
4524 && generic_bignum[parts * 2] != m)
4527 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4528 if (generic_bignum[j] != generic_bignum[j-1])
4532 inst.operands[i].imm = 0;
4533 for (j = 0; j < parts; j++, idx++)
4534 inst.operands[i].imm |= generic_bignum[idx]
4535 << (LITTLENUM_NUMBER_OF_BITS * j);
4536 inst.operands[i].reg = 0;
4537 for (j = 0; j < parts; j++, idx++)
4538 inst.operands[i].reg |= generic_bignum[idx]
4539 << (LITTLENUM_NUMBER_OF_BITS * j);
4540 inst.operands[i].regisimm = 1;
4550 /* Returns the pseudo-register number of an FPA immediate constant,
4551 or FAIL if there isn't a valid constant here. */
4554 parse_fpa_immediate (char ** str)
4556 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4562 /* First try and match exact strings, this is to guarantee
4563 that some formats will work even for cross assembly. */
4565 for (i = 0; fp_const[i]; i++)
4567 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4571 *str += strlen (fp_const[i]);
4572 if (is_end_of_line[(unsigned char) **str])
4578 /* Just because we didn't get a match doesn't mean that the constant
4579 isn't valid, just that it is in a format that we don't
4580 automatically recognize. Try parsing it with the standard
4581 expression routines. */
4583 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4585 /* Look for a raw floating point number. */
4586 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4587 && is_end_of_line[(unsigned char) *save_in])
4589 for (i = 0; i < NUM_FLOAT_VALS; i++)
4591 for (j = 0; j < MAX_LITTLENUMS; j++)
4593 if (words[j] != fp_values[i][j])
4597 if (j == MAX_LITTLENUMS)
4605 /* Try and parse a more complex expression, this will probably fail
4606 unless the code uses a floating point prefix (eg "0f"). */
4607 save_in = input_line_pointer;
4608 input_line_pointer = *str;
4609 if (expression (&exp) == absolute_section
4610 && exp.X_op == O_big
4611 && exp.X_add_number < 0)
4613 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4615 if (gen_to_words (words, 5, (long) 15) == 0)
4617 for (i = 0; i < NUM_FLOAT_VALS; i++)
4619 for (j = 0; j < MAX_LITTLENUMS; j++)
4621 if (words[j] != fp_values[i][j])
4625 if (j == MAX_LITTLENUMS)
4627 *str = input_line_pointer;
4628 input_line_pointer = save_in;
4635 *str = input_line_pointer;
4636 input_line_pointer = save_in;
4637 inst.error = _("invalid FPA immediate expression");
4641 /* Returns 1 if a number has "quarter-precision" float format
4642 0baBbbbbbc defgh000 00000000 00000000. */
4645 is_quarter_float (unsigned imm)
4647 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4648 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4651 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4652 0baBbbbbbc defgh000 00000000 00000000.
4653 The zero and minus-zero cases need special handling, since they can't be
4654 encoded in the "quarter-precision" float format, but can nonetheless be
4655 loaded as integer constants. */
4658 parse_qfloat_immediate (char **ccp, int *immed)
4662 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4663 int found_fpchar = 0;
4665 skip_past_char (&str, '#');
4667 /* We must not accidentally parse an integer as a floating-point number. Make
4668 sure that the value we parse is not an integer by checking for special
4669 characters '.' or 'e'.
4670 FIXME: This is a horrible hack, but doing better is tricky because type
4671 information isn't in a very usable state at parse time. */
4673 skip_whitespace (fpnum);
4675 if (strncmp (fpnum, "0x", 2) == 0)
4679 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4680 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4690 if ((str = atof_ieee (str, 's', words)) != NULL)
4692 unsigned fpword = 0;
4695 /* Our FP word must be 32 bits (single-precision FP). */
4696 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4698 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4702 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4715 /* Shift operands. */
4718 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4721 struct asm_shift_name
4724 enum shift_kind kind;
4727 /* Third argument to parse_shift. */
4728 enum parse_shift_mode
4730 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4731 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4732 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4733 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4734 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4737 /* Parse a <shift> specifier on an ARM data processing instruction.
4738 This has three forms:
4740 (LSL|LSR|ASL|ASR|ROR) Rs
4741 (LSL|LSR|ASL|ASR|ROR) #imm
4744 Note that ASL is assimilated to LSL in the instruction encoding, and
4745 RRX to ROR #0 (which cannot be written as such). */
4748 parse_shift (char **str, int i, enum parse_shift_mode mode)
4750 const struct asm_shift_name *shift_name;
4751 enum shift_kind shift;
4756 for (p = *str; ISALPHA (*p); p++)
4761 inst.error = _("shift expression expected");
4765 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4768 if (shift_name == NULL)
4770 inst.error = _("shift expression expected");
4774 shift = shift_name->kind;
4778 case NO_SHIFT_RESTRICT:
4779 case SHIFT_IMMEDIATE: break;
4781 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4782 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4784 inst.error = _("'LSL' or 'ASR' required");
4789 case SHIFT_LSL_IMMEDIATE:
4790 if (shift != SHIFT_LSL)
4792 inst.error = _("'LSL' required");
4797 case SHIFT_ASR_IMMEDIATE:
4798 if (shift != SHIFT_ASR)
4800 inst.error = _("'ASR' required");
4808 if (shift != SHIFT_RRX)
4810 /* Whitespace can appear here if the next thing is a bare digit. */
4811 skip_whitespace (p);
4813 if (mode == NO_SHIFT_RESTRICT
4814 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4816 inst.operands[i].imm = reg;
4817 inst.operands[i].immisreg = 1;
4819 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4822 inst.operands[i].shift_kind = shift;
4823 inst.operands[i].shifted = 1;
4828 /* Parse a <shifter_operand> for an ARM data processing instruction:
4831 #<immediate>, <rotate>
4835 where <shift> is defined by parse_shift above, and <rotate> is a
4836 multiple of 2 between 0 and 30. Validation of immediate operands
4837 is deferred to md_apply_fix. */
4840 parse_shifter_operand (char **str, int i)
4845 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4847 inst.operands[i].reg = value;
4848 inst.operands[i].isreg = 1;
4850 /* parse_shift will override this if appropriate */
4851 inst.reloc.exp.X_op = O_constant;
4852 inst.reloc.exp.X_add_number = 0;
4854 if (skip_past_comma (str) == FAIL)
4857 /* Shift operation on register. */
4858 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4861 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4864 if (skip_past_comma (str) == SUCCESS)
4866 /* #x, y -- ie explicit rotation by Y. */
4867 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4870 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4872 inst.error = _("constant expression expected");
4876 value = exp.X_add_number;
4877 if (value < 0 || value > 30 || value % 2 != 0)
4879 inst.error = _("invalid rotation");
4882 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4884 inst.error = _("invalid constant");
4888 /* Encode as specified. */
4889 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4893 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4894 inst.reloc.pc_rel = 0;
4898 /* Group relocation information. Each entry in the table contains the
4899 textual name of the relocation as may appear in assembler source
4900 and must end with a colon.
4901 Along with this textual name are the relocation codes to be used if
4902 the corresponding instruction is an ALU instruction (ADD or SUB only),
4903 an LDR, an LDRS, or an LDC. */
4905 struct group_reloc_table_entry
4916 /* Varieties of non-ALU group relocation. */
4923 static struct group_reloc_table_entry group_reloc_table[] =
4924 { /* Program counter relative: */
4926 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4931 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4932 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4933 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4934 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4936 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4941 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4942 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4943 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4944 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4946 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4947 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4948 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4949 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4950 /* Section base relative */
4952 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4957 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4958 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4959 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4960 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4962 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4967 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4968 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4969 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4970 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4972 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4973 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4974 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4975 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4977 /* Given the address of a pointer pointing to the textual name of a group
4978 relocation as may appear in assembler source, attempt to find its details
4979 in group_reloc_table. The pointer will be updated to the character after
4980 the trailing colon. On failure, FAIL will be returned; SUCCESS
4981 otherwise. On success, *entry will be updated to point at the relevant
4982 group_reloc_table entry. */
4985 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4988 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4990 int length = strlen (group_reloc_table[i].name);
4992 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4993 && (*str)[length] == ':')
4995 *out = &group_reloc_table[i];
4996 *str += (length + 1);
5004 /* Parse a <shifter_operand> for an ARM data processing instruction
5005 (as for parse_shifter_operand) where group relocations are allowed:
5008 #<immediate>, <rotate>
5009 #:<group_reloc>:<expression>
5013 where <group_reloc> is one of the strings defined in group_reloc_table.
5014 The hashes are optional.
5016 Everything else is as for parse_shifter_operand. */
5018 static parse_operand_result
5019 parse_shifter_operand_group_reloc (char **str, int i)
5021 /* Determine if we have the sequence of characters #: or just :
5022 coming next. If we do, then we check for a group relocation.
5023 If we don't, punt the whole lot to parse_shifter_operand. */
5025 if (((*str)[0] == '#' && (*str)[1] == ':')
5026 || (*str)[0] == ':')
5028 struct group_reloc_table_entry *entry;
5030 if ((*str)[0] == '#')
5035 /* Try to parse a group relocation. Anything else is an error. */
5036 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5038 inst.error = _("unknown group relocation");
5039 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5042 /* We now have the group relocation table entry corresponding to
5043 the name in the assembler source. Next, we parse the expression. */
5044 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5045 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5047 /* Record the relocation type (always the ALU variant here). */
5048 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5049 gas_assert (inst.reloc.type != 0);
5051 return PARSE_OPERAND_SUCCESS;
5054 return parse_shifter_operand (str, i) == SUCCESS
5055 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5057 /* Never reached. */
5060 /* Parse a Neon alignment expression. Information is written to
5061 inst.operands[i]. We assume the initial ':' has been skipped.
5063 align .imm = align << 8, .immisalign=1, .preind=0 */
5064 static parse_operand_result
5065 parse_neon_alignment (char **str, int i)
5070 my_get_expression (&exp, &p, GE_NO_PREFIX);
5072 if (exp.X_op != O_constant)
5074 inst.error = _("alignment must be constant");
5075 return PARSE_OPERAND_FAIL;
5078 inst.operands[i].imm = exp.X_add_number << 8;
5079 inst.operands[i].immisalign = 1;
5080 /* Alignments are not pre-indexes. */
5081 inst.operands[i].preind = 0;
5084 return PARSE_OPERAND_SUCCESS;
5087 /* Parse all forms of an ARM address expression. Information is written
5088 to inst.operands[i] and/or inst.reloc.
5090 Preindexed addressing (.preind=1):
5092 [Rn, #offset] .reg=Rn .reloc.exp=offset
5093 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5094 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5095 .shift_kind=shift .reloc.exp=shift_imm
5097 These three may have a trailing ! which causes .writeback to be set also.
5099 Postindexed addressing (.postind=1, .writeback=1):
5101 [Rn], #offset .reg=Rn .reloc.exp=offset
5102 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5103 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5104 .shift_kind=shift .reloc.exp=shift_imm
5106 Unindexed addressing (.preind=0, .postind=0):
5108 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5112 [Rn]{!} shorthand for [Rn,#0]{!}
5113 =immediate .isreg=0 .reloc.exp=immediate
5114 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5116 It is the caller's responsibility to check for addressing modes not
5117 supported by the instruction, and to set inst.reloc.type. */
5119 static parse_operand_result
5120 parse_address_main (char **str, int i, int group_relocations,
5121 group_reloc_type group_type)
5126 if (skip_past_char (&p, '[') == FAIL)
5128 if (skip_past_char (&p, '=') == FAIL)
5130 /* Bare address - translate to PC-relative offset. */
5131 inst.reloc.pc_rel = 1;
5132 inst.operands[i].reg = REG_PC;
5133 inst.operands[i].isreg = 1;
5134 inst.operands[i].preind = 1;
5136 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5138 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5139 return PARSE_OPERAND_FAIL;
5142 return PARSE_OPERAND_SUCCESS;
5145 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5147 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5148 return PARSE_OPERAND_FAIL;
5150 inst.operands[i].reg = reg;
5151 inst.operands[i].isreg = 1;
5153 if (skip_past_comma (&p) == SUCCESS)
5155 inst.operands[i].preind = 1;
5158 else if (*p == '-') p++, inst.operands[i].negative = 1;
5160 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5162 inst.operands[i].imm = reg;
5163 inst.operands[i].immisreg = 1;
5165 if (skip_past_comma (&p) == SUCCESS)
5166 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5167 return PARSE_OPERAND_FAIL;
5169 else if (skip_past_char (&p, ':') == SUCCESS)
5171 /* FIXME: '@' should be used here, but it's filtered out by generic
5172 code before we get to see it here. This may be subject to
5174 parse_operand_result result = parse_neon_alignment (&p, i);
5176 if (result != PARSE_OPERAND_SUCCESS)
5181 if (inst.operands[i].negative)
5183 inst.operands[i].negative = 0;
5187 if (group_relocations
5188 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5190 struct group_reloc_table_entry *entry;
5192 /* Skip over the #: or : sequence. */
5198 /* Try to parse a group relocation. Anything else is an
5200 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5202 inst.error = _("unknown group relocation");
5203 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5206 /* We now have the group relocation table entry corresponding to
5207 the name in the assembler source. Next, we parse the
5209 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5210 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5212 /* Record the relocation type. */
5216 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5220 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5224 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5231 if (inst.reloc.type == 0)
5233 inst.error = _("this group relocation is not allowed on this instruction");
5234 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5240 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5241 return PARSE_OPERAND_FAIL;
5242 /* If the offset is 0, find out if it's a +0 or -0. */
5243 if (inst.reloc.exp.X_op == O_constant
5244 && inst.reloc.exp.X_add_number == 0)
5246 skip_whitespace (q);
5250 skip_whitespace (q);
5253 inst.operands[i].negative = 1;
5258 else if (skip_past_char (&p, ':') == SUCCESS)
5260 /* FIXME: '@' should be used here, but it's filtered out by generic code
5261 before we get to see it here. This may be subject to change. */
5262 parse_operand_result result = parse_neon_alignment (&p, i);
5264 if (result != PARSE_OPERAND_SUCCESS)
5268 if (skip_past_char (&p, ']') == FAIL)
5270 inst.error = _("']' expected");
5271 return PARSE_OPERAND_FAIL;
5274 if (skip_past_char (&p, '!') == SUCCESS)
5275 inst.operands[i].writeback = 1;
5277 else if (skip_past_comma (&p) == SUCCESS)
5279 if (skip_past_char (&p, '{') == SUCCESS)
5281 /* [Rn], {expr} - unindexed, with option */
5282 if (parse_immediate (&p, &inst.operands[i].imm,
5283 0, 255, TRUE) == FAIL)
5284 return PARSE_OPERAND_FAIL;
5286 if (skip_past_char (&p, '}') == FAIL)
5288 inst.error = _("'}' expected at end of 'option' field");
5289 return PARSE_OPERAND_FAIL;
5291 if (inst.operands[i].preind)
5293 inst.error = _("cannot combine index with option");
5294 return PARSE_OPERAND_FAIL;
5297 return PARSE_OPERAND_SUCCESS;
5301 inst.operands[i].postind = 1;
5302 inst.operands[i].writeback = 1;
5304 if (inst.operands[i].preind)
5306 inst.error = _("cannot combine pre- and post-indexing");
5307 return PARSE_OPERAND_FAIL;
5311 else if (*p == '-') p++, inst.operands[i].negative = 1;
5313 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5315 /* We might be using the immediate for alignment already. If we
5316 are, OR the register number into the low-order bits. */
5317 if (inst.operands[i].immisalign)
5318 inst.operands[i].imm |= reg;
5320 inst.operands[i].imm = reg;
5321 inst.operands[i].immisreg = 1;
5323 if (skip_past_comma (&p) == SUCCESS)
5324 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5325 return PARSE_OPERAND_FAIL;
5330 if (inst.operands[i].negative)
5332 inst.operands[i].negative = 0;
5335 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5336 return PARSE_OPERAND_FAIL;
5337 /* If the offset is 0, find out if it's a +0 or -0. */
5338 if (inst.reloc.exp.X_op == O_constant
5339 && inst.reloc.exp.X_add_number == 0)
5341 skip_whitespace (q);
5345 skip_whitespace (q);
5348 inst.operands[i].negative = 1;
5354 /* If at this point neither .preind nor .postind is set, we have a
5355 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5356 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5358 inst.operands[i].preind = 1;
5359 inst.reloc.exp.X_op = O_constant;
5360 inst.reloc.exp.X_add_number = 0;
5363 return PARSE_OPERAND_SUCCESS;
5367 parse_address (char **str, int i)
5369 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5373 static parse_operand_result
5374 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5376 return parse_address_main (str, i, 1, type);
5379 /* Parse an operand for a MOVW or MOVT instruction. */
5381 parse_half (char **str)
5386 skip_past_char (&p, '#');
5387 if (strncasecmp (p, ":lower16:", 9) == 0)
5388 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5389 else if (strncasecmp (p, ":upper16:", 9) == 0)
5390 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5392 if (inst.reloc.type != BFD_RELOC_UNUSED)
5395 skip_whitespace (p);
5398 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5401 if (inst.reloc.type == BFD_RELOC_UNUSED)
5403 if (inst.reloc.exp.X_op != O_constant)
5405 inst.error = _("constant expression expected");
5408 if (inst.reloc.exp.X_add_number < 0
5409 || inst.reloc.exp.X_add_number > 0xffff)
5411 inst.error = _("immediate value out of range");
5419 /* Miscellaneous. */
5421 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5422 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5424 parse_psr (char **str, bfd_boolean lhs)
5427 unsigned long psr_field;
5428 const struct asm_psr *psr;
5430 bfd_boolean is_apsr = FALSE;
5431 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5433 /* PR gas/12698: If the user has specified -march=all then m_profile will
5434 be TRUE, but we want to ignore it in this case as we are building for any
5435 CPU type, including non-m variants. */
5436 if (selected_cpu.core == arm_arch_any.core)
5439 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5440 feature for ease of use and backwards compatibility. */
5442 if (strncasecmp (p, "SPSR", 4) == 0)
5445 goto unsupported_psr;
5447 psr_field = SPSR_BIT;
5449 else if (strncasecmp (p, "CPSR", 4) == 0)
5452 goto unsupported_psr;
5456 else if (strncasecmp (p, "APSR", 4) == 0)
5458 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5459 and ARMv7-R architecture CPUs. */
5468 while (ISALNUM (*p) || *p == '_');
5470 if (strncasecmp (start, "iapsr", 5) == 0
5471 || strncasecmp (start, "eapsr", 5) == 0
5472 || strncasecmp (start, "xpsr", 4) == 0
5473 || strncasecmp (start, "psr", 3) == 0)
5474 p = start + strcspn (start, "rR") + 1;
5476 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5482 /* If APSR is being written, a bitfield may be specified. Note that
5483 APSR itself is handled above. */
5484 if (psr->field <= 3)
5486 psr_field = psr->field;
5492 /* M-profile MSR instructions have the mask field set to "10", except
5493 *PSR variants which modify APSR, which may use a different mask (and
5494 have been handled already). Do that by setting the PSR_f field
5496 return psr->field | (lhs ? PSR_f : 0);
5499 goto unsupported_psr;
5505 /* A suffix follows. */
5511 while (ISALNUM (*p) || *p == '_');
5515 /* APSR uses a notation for bits, rather than fields. */
5516 unsigned int nzcvq_bits = 0;
5517 unsigned int g_bit = 0;
5520 for (bit = start; bit != p; bit++)
5522 switch (TOLOWER (*bit))
5525 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5529 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5533 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5537 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5541 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5545 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5549 inst.error = _("unexpected bit specified after APSR");
5554 if (nzcvq_bits == 0x1f)
5559 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5561 inst.error = _("selected processor does not "
5562 "support DSP extension");
5569 if ((nzcvq_bits & 0x20) != 0
5570 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5571 || (g_bit & 0x2) != 0)
5573 inst.error = _("bad bitmask specified after APSR");
5579 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5584 psr_field |= psr->field;
5590 goto error; /* Garbage after "[CS]PSR". */
5592 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5593 is deprecated, but allow it anyway. */
5597 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5600 else if (!m_profile)
5601 /* These bits are never right for M-profile devices: don't set them
5602 (only code paths which read/write APSR reach here). */
5603 psr_field |= (PSR_c | PSR_f);
5609 inst.error = _("selected processor does not support requested special "
5610 "purpose register");
5614 inst.error = _("flag for {c}psr instruction expected");
5618 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5619 value suitable for splatting into the AIF field of the instruction. */
5622 parse_cps_flags (char **str)
5631 case '\0': case ',':
5634 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5635 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5636 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5639 inst.error = _("unrecognized CPS flag");
5644 if (saw_a_flag == 0)
5646 inst.error = _("missing CPS flags");
5654 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5655 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5658 parse_endian_specifier (char **str)
5663 if (strncasecmp (s, "BE", 2))
5665 else if (strncasecmp (s, "LE", 2))
5669 inst.error = _("valid endian specifiers are be or le");
5673 if (ISALNUM (s[2]) || s[2] == '_')
5675 inst.error = _("valid endian specifiers are be or le");
5680 return little_endian;
5683 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5684 value suitable for poking into the rotate field of an sxt or sxta
5685 instruction, or FAIL on error. */
5688 parse_ror (char **str)
5693 if (strncasecmp (s, "ROR", 3) == 0)
5697 inst.error = _("missing rotation field after comma");
5701 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5706 case 0: *str = s; return 0x0;
5707 case 8: *str = s; return 0x1;
5708 case 16: *str = s; return 0x2;
5709 case 24: *str = s; return 0x3;
5712 inst.error = _("rotation can only be 0, 8, 16, or 24");
5717 /* Parse a conditional code (from conds[] below). The value returned is in the
5718 range 0 .. 14, or FAIL. */
5720 parse_cond (char **str)
5723 const struct asm_cond *c;
5725 /* Condition codes are always 2 characters, so matching up to
5726 3 characters is sufficient. */
5731 while (ISALPHA (*q) && n < 3)
5733 cond[n] = TOLOWER (*q);
5738 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5741 inst.error = _("condition required");
5749 /* Parse an option for a barrier instruction. Returns the encoding for the
5752 parse_barrier (char **str)
5755 const struct asm_barrier_opt *o;
5758 while (ISALPHA (*q))
5761 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5770 /* Parse the operands of a table branch instruction. Similar to a memory
5773 parse_tb (char **str)
5778 if (skip_past_char (&p, '[') == FAIL)
5780 inst.error = _("'[' expected");
5784 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5786 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5789 inst.operands[0].reg = reg;
5791 if (skip_past_comma (&p) == FAIL)
5793 inst.error = _("',' expected");
5797 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5799 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5802 inst.operands[0].imm = reg;
5804 if (skip_past_comma (&p) == SUCCESS)
5806 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5808 if (inst.reloc.exp.X_add_number != 1)
5810 inst.error = _("invalid shift");
5813 inst.operands[0].shifted = 1;
5816 if (skip_past_char (&p, ']') == FAIL)
5818 inst.error = _("']' expected");
5825 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5826 information on the types the operands can take and how they are encoded.
5827 Up to four operands may be read; this function handles setting the
5828 ".present" field for each read operand itself.
5829 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5830 else returns FAIL. */
5833 parse_neon_mov (char **str, int *which_operand)
5835 int i = *which_operand, val;
5836 enum arm_reg_type rtype;
5838 struct neon_type_el optype;
5840 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5842 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5843 inst.operands[i].reg = val;
5844 inst.operands[i].isscalar = 1;
5845 inst.operands[i].vectype = optype;
5846 inst.operands[i++].present = 1;
5848 if (skip_past_comma (&ptr) == FAIL)
5851 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5854 inst.operands[i].reg = val;
5855 inst.operands[i].isreg = 1;
5856 inst.operands[i].present = 1;
5858 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5861 /* Cases 0, 1, 2, 3, 5 (D only). */
5862 if (skip_past_comma (&ptr) == FAIL)
5865 inst.operands[i].reg = val;
5866 inst.operands[i].isreg = 1;
5867 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5868 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5869 inst.operands[i].isvec = 1;
5870 inst.operands[i].vectype = optype;
5871 inst.operands[i++].present = 1;
5873 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5875 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5876 Case 13: VMOV <Sd>, <Rm> */
5877 inst.operands[i].reg = val;
5878 inst.operands[i].isreg = 1;
5879 inst.operands[i].present = 1;
5881 if (rtype == REG_TYPE_NQ)
5883 first_error (_("can't use Neon quad register here"));
5886 else if (rtype != REG_TYPE_VFS)
5889 if (skip_past_comma (&ptr) == FAIL)
5891 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5893 inst.operands[i].reg = val;
5894 inst.operands[i].isreg = 1;
5895 inst.operands[i].present = 1;
5898 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5901 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5902 Case 1: VMOV<c><q> <Dd>, <Dm>
5903 Case 8: VMOV.F32 <Sd>, <Sm>
5904 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5906 inst.operands[i].reg = val;
5907 inst.operands[i].isreg = 1;
5908 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5909 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5910 inst.operands[i].isvec = 1;
5911 inst.operands[i].vectype = optype;
5912 inst.operands[i].present = 1;
5914 if (skip_past_comma (&ptr) == SUCCESS)
5919 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5922 inst.operands[i].reg = val;
5923 inst.operands[i].isreg = 1;
5924 inst.operands[i++].present = 1;
5926 if (skip_past_comma (&ptr) == FAIL)
5929 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5932 inst.operands[i].reg = val;
5933 inst.operands[i].isreg = 1;
5934 inst.operands[i++].present = 1;
5937 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5938 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5939 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5940 Case 10: VMOV.F32 <Sd>, #<imm>
5941 Case 11: VMOV.F64 <Dd>, #<imm> */
5942 inst.operands[i].immisfloat = 1;
5943 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5944 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5945 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5949 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5953 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5956 inst.operands[i].reg = val;
5957 inst.operands[i].isreg = 1;
5958 inst.operands[i++].present = 1;
5960 if (skip_past_comma (&ptr) == FAIL)
5963 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5965 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5966 inst.operands[i].reg = val;
5967 inst.operands[i].isscalar = 1;
5968 inst.operands[i].present = 1;
5969 inst.operands[i].vectype = optype;
5971 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5973 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5974 inst.operands[i].reg = val;
5975 inst.operands[i].isreg = 1;
5976 inst.operands[i++].present = 1;
5978 if (skip_past_comma (&ptr) == FAIL)
5981 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5984 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5988 inst.operands[i].reg = val;
5989 inst.operands[i].isreg = 1;
5990 inst.operands[i].isvec = 1;
5991 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5992 inst.operands[i].vectype = optype;
5993 inst.operands[i].present = 1;
5995 if (rtype == REG_TYPE_VFS)
5999 if (skip_past_comma (&ptr) == FAIL)
6001 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6004 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6007 inst.operands[i].reg = val;
6008 inst.operands[i].isreg = 1;
6009 inst.operands[i].isvec = 1;
6010 inst.operands[i].issingle = 1;
6011 inst.operands[i].vectype = optype;
6012 inst.operands[i].present = 1;
6015 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6019 inst.operands[i].reg = val;
6020 inst.operands[i].isreg = 1;
6021 inst.operands[i].isvec = 1;
6022 inst.operands[i].issingle = 1;
6023 inst.operands[i].vectype = optype;
6024 inst.operands[i++].present = 1;
6029 first_error (_("parse error"));
6033 /* Successfully parsed the operands. Update args. */
6039 first_error (_("expected comma"));
6043 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6047 /* Use this macro when the operand constraints are different
6048 for ARM and THUMB (e.g. ldrd). */
6049 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6050 ((arm_operand) | ((thumb_operand) << 16))
6052 /* Matcher codes for parse_operands. */
6053 enum operand_parse_code
6055 OP_stop, /* end of line */
6057 OP_RR, /* ARM register */
6058 OP_RRnpc, /* ARM register, not r15 */
6059 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6060 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6061 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6062 optional trailing ! */
6063 OP_RRw, /* ARM register, not r15, optional trailing ! */
6064 OP_RCP, /* Coprocessor number */
6065 OP_RCN, /* Coprocessor register */
6066 OP_RF, /* FPA register */
6067 OP_RVS, /* VFP single precision register */
6068 OP_RVD, /* VFP double precision register (0..15) */
6069 OP_RND, /* Neon double precision register (0..31) */
6070 OP_RNQ, /* Neon quad precision register */
6071 OP_RVSD, /* VFP single or double precision register */
6072 OP_RNDQ, /* Neon double or quad precision register */
6073 OP_RNSDQ, /* Neon single, double or quad precision register */
6074 OP_RNSC, /* Neon scalar D[X] */
6075 OP_RVC, /* VFP control register */
6076 OP_RMF, /* Maverick F register */
6077 OP_RMD, /* Maverick D register */
6078 OP_RMFX, /* Maverick FX register */
6079 OP_RMDX, /* Maverick DX register */
6080 OP_RMAX, /* Maverick AX register */
6081 OP_RMDS, /* Maverick DSPSC register */
6082 OP_RIWR, /* iWMMXt wR register */
6083 OP_RIWC, /* iWMMXt wC register */
6084 OP_RIWG, /* iWMMXt wCG register */
6085 OP_RXA, /* XScale accumulator register */
6087 OP_REGLST, /* ARM register list */
6088 OP_VRSLST, /* VFP single-precision register list */
6089 OP_VRDLST, /* VFP double-precision register list */
6090 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6091 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6092 OP_NSTRLST, /* Neon element/structure list */
6094 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6095 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6096 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6097 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6098 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6099 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6100 OP_VMOV, /* Neon VMOV operands. */
6101 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6102 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6103 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6105 OP_I0, /* immediate zero */
6106 OP_I7, /* immediate value 0 .. 7 */
6107 OP_I15, /* 0 .. 15 */
6108 OP_I16, /* 1 .. 16 */
6109 OP_I16z, /* 0 .. 16 */
6110 OP_I31, /* 0 .. 31 */
6111 OP_I31w, /* 0 .. 31, optional trailing ! */
6112 OP_I32, /* 1 .. 32 */
6113 OP_I32z, /* 0 .. 32 */
6114 OP_I63, /* 0 .. 63 */
6115 OP_I63s, /* -64 .. 63 */
6116 OP_I64, /* 1 .. 64 */
6117 OP_I64z, /* 0 .. 64 */
6118 OP_I255, /* 0 .. 255 */
6120 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6121 OP_I7b, /* 0 .. 7 */
6122 OP_I15b, /* 0 .. 15 */
6123 OP_I31b, /* 0 .. 31 */
6125 OP_SH, /* shifter operand */
6126 OP_SHG, /* shifter operand with possible group relocation */
6127 OP_ADDR, /* Memory address expression (any mode) */
6128 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6129 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6130 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6131 OP_EXP, /* arbitrary expression */
6132 OP_EXPi, /* same, with optional immediate prefix */
6133 OP_EXPr, /* same, with optional relocation suffix */
6134 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6136 OP_CPSF, /* CPS flags */
6137 OP_ENDI, /* Endianness specifier */
6138 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6139 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6140 OP_COND, /* conditional code */
6141 OP_TB, /* Table branch. */
6143 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6145 OP_RRnpc_I0, /* ARM register or literal 0 */
6146 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6147 OP_RR_EXi, /* ARM register or expression with imm prefix */
6148 OP_RF_IF, /* FPA register or immediate */
6149 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6150 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6152 /* Optional operands. */
6153 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6154 OP_oI31b, /* 0 .. 31 */
6155 OP_oI32b, /* 1 .. 32 */
6156 OP_oI32z, /* 0 .. 32 */
6157 OP_oIffffb, /* 0 .. 65535 */
6158 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6160 OP_oRR, /* ARM register */
6161 OP_oRRnpc, /* ARM register, not the PC */
6162 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6163 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6164 OP_oRND, /* Optional Neon double precision register */
6165 OP_oRNQ, /* Optional Neon quad precision register */
6166 OP_oRNDQ, /* Optional Neon double or quad precision register */
6167 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6168 OP_oSHll, /* LSL immediate */
6169 OP_oSHar, /* ASR immediate */
6170 OP_oSHllar, /* LSL or ASR immediate */
6171 OP_oROR, /* ROR 0/8/16/24 */
6172 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6174 /* Some pre-defined mixed (ARM/THUMB) operands. */
6175 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6176 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6177 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6179 OP_FIRST_OPTIONAL = OP_oI7b
6182 /* Generic instruction operand parser. This does no encoding and no
6183 semantic validation; it merely squirrels values away in the inst
6184 structure. Returns SUCCESS or FAIL depending on whether the
6185 specified grammar matched. */
6187 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6189 unsigned const int *upat = pattern;
6190 char *backtrack_pos = 0;
6191 const char *backtrack_error = 0;
6192 int i, val, backtrack_index = 0;
6193 enum arm_reg_type rtype;
6194 parse_operand_result result;
6195 unsigned int op_parse_code;
6197 #define po_char_or_fail(chr) \
6200 if (skip_past_char (&str, chr) == FAIL) \
6205 #define po_reg_or_fail(regtype) \
6208 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6209 & inst.operands[i].vectype); \
6212 first_error (_(reg_expected_msgs[regtype])); \
6215 inst.operands[i].reg = val; \
6216 inst.operands[i].isreg = 1; \
6217 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6218 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6219 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6220 || rtype == REG_TYPE_VFD \
6221 || rtype == REG_TYPE_NQ); \
6225 #define po_reg_or_goto(regtype, label) \
6228 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6229 & inst.operands[i].vectype); \
6233 inst.operands[i].reg = val; \
6234 inst.operands[i].isreg = 1; \
6235 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6236 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6237 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6238 || rtype == REG_TYPE_VFD \
6239 || rtype == REG_TYPE_NQ); \
6243 #define po_imm_or_fail(min, max, popt) \
6246 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6248 inst.operands[i].imm = val; \
6252 #define po_scalar_or_goto(elsz, label) \
6255 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6258 inst.operands[i].reg = val; \
6259 inst.operands[i].isscalar = 1; \
6263 #define po_misc_or_fail(expr) \
6271 #define po_misc_or_fail_no_backtrack(expr) \
6275 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6276 backtrack_pos = 0; \
6277 if (result != PARSE_OPERAND_SUCCESS) \
6282 #define po_barrier_or_imm(str) \
6285 val = parse_barrier (&str); \
6288 if (ISALPHA (*str)) \
6295 if ((inst.instruction & 0xf0) == 0x60 \
6298 /* ISB can only take SY as an option. */ \
6299 inst.error = _("invalid barrier type"); \
6306 skip_whitespace (str);
6308 for (i = 0; upat[i] != OP_stop; i++)
6310 op_parse_code = upat[i];
6311 if (op_parse_code >= 1<<16)
6312 op_parse_code = thumb ? (op_parse_code >> 16)
6313 : (op_parse_code & ((1<<16)-1));
6315 if (op_parse_code >= OP_FIRST_OPTIONAL)
6317 /* Remember where we are in case we need to backtrack. */
6318 gas_assert (!backtrack_pos);
6319 backtrack_pos = str;
6320 backtrack_error = inst.error;
6321 backtrack_index = i;
6324 if (i > 0 && (i > 1 || inst.operands[0].present))
6325 po_char_or_fail (',');
6327 switch (op_parse_code)
6335 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6336 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6337 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6338 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6339 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6340 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6342 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6344 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6346 /* Also accept generic coprocessor regs for unknown registers. */
6348 po_reg_or_fail (REG_TYPE_CN);
6350 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6351 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6352 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6353 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6354 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6355 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6356 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6357 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6358 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6359 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6361 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6363 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6364 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6366 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6368 /* Neon scalar. Using an element size of 8 means that some invalid
6369 scalars are accepted here, so deal with those in later code. */
6370 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6374 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6377 po_imm_or_fail (0, 0, TRUE);
6382 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6387 po_scalar_or_goto (8, try_rr);
6390 po_reg_or_fail (REG_TYPE_RN);
6396 po_scalar_or_goto (8, try_nsdq);
6399 po_reg_or_fail (REG_TYPE_NSDQ);
6405 po_scalar_or_goto (8, try_ndq);
6408 po_reg_or_fail (REG_TYPE_NDQ);
6414 po_scalar_or_goto (8, try_vfd);
6417 po_reg_or_fail (REG_TYPE_VFD);
6422 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6423 not careful then bad things might happen. */
6424 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6429 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6432 /* There's a possibility of getting a 64-bit immediate here, so
6433 we need special handling. */
6434 if (parse_big_immediate (&str, i) == FAIL)
6436 inst.error = _("immediate value is out of range");
6444 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6447 po_imm_or_fail (0, 63, TRUE);
6452 po_char_or_fail ('[');
6453 po_reg_or_fail (REG_TYPE_RN);
6454 po_char_or_fail (']');
6460 po_reg_or_fail (REG_TYPE_RN);
6461 if (skip_past_char (&str, '!') == SUCCESS)
6462 inst.operands[i].writeback = 1;
6466 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6467 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6468 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6469 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6470 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6471 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6472 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6473 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6474 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6475 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6476 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6477 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6479 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6481 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6482 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6484 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6485 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6486 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6487 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6489 /* Immediate variants */
6491 po_char_or_fail ('{');
6492 po_imm_or_fail (0, 255, TRUE);
6493 po_char_or_fail ('}');
6497 /* The expression parser chokes on a trailing !, so we have
6498 to find it first and zap it. */
6501 while (*s && *s != ',')
6506 inst.operands[i].writeback = 1;
6508 po_imm_or_fail (0, 31, TRUE);
6516 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6521 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6526 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6528 if (inst.reloc.exp.X_op == O_symbol)
6530 val = parse_reloc (&str);
6533 inst.error = _("unrecognized relocation suffix");
6536 else if (val != BFD_RELOC_UNUSED)
6538 inst.operands[i].imm = val;
6539 inst.operands[i].hasreloc = 1;
6544 /* Operand for MOVW or MOVT. */
6546 po_misc_or_fail (parse_half (&str));
6549 /* Register or expression. */
6550 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6551 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6553 /* Register or immediate. */
6554 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6555 I0: po_imm_or_fail (0, 0, FALSE); break;
6557 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6559 if (!is_immediate_prefix (*str))
6562 val = parse_fpa_immediate (&str);
6565 /* FPA immediates are encoded as registers 8-15.
6566 parse_fpa_immediate has already applied the offset. */
6567 inst.operands[i].reg = val;
6568 inst.operands[i].isreg = 1;
6571 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6572 I32z: po_imm_or_fail (0, 32, FALSE); break;
6574 /* Two kinds of register. */
6577 struct reg_entry *rege = arm_reg_parse_multi (&str);
6579 || (rege->type != REG_TYPE_MMXWR
6580 && rege->type != REG_TYPE_MMXWC
6581 && rege->type != REG_TYPE_MMXWCG))
6583 inst.error = _("iWMMXt data or control register expected");
6586 inst.operands[i].reg = rege->number;
6587 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6593 struct reg_entry *rege = arm_reg_parse_multi (&str);
6595 || (rege->type != REG_TYPE_MMXWC
6596 && rege->type != REG_TYPE_MMXWCG))
6598 inst.error = _("iWMMXt control register expected");
6601 inst.operands[i].reg = rege->number;
6602 inst.operands[i].isreg = 1;
6607 case OP_CPSF: val = parse_cps_flags (&str); break;
6608 case OP_ENDI: val = parse_endian_specifier (&str); break;
6609 case OP_oROR: val = parse_ror (&str); break;
6610 case OP_COND: val = parse_cond (&str); break;
6611 case OP_oBARRIER_I15:
6612 po_barrier_or_imm (str); break;
6614 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6620 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6621 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6623 inst.error = _("Banked registers are not available with this "
6629 val = parse_psr (&str, op_parse_code == OP_wPSR);
6633 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6636 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6638 if (strncasecmp (str, "APSR_", 5) == 0)
6645 case 'c': found = (found & 1) ? 16 : found | 1; break;
6646 case 'n': found = (found & 2) ? 16 : found | 2; break;
6647 case 'z': found = (found & 4) ? 16 : found | 4; break;
6648 case 'v': found = (found & 8) ? 16 : found | 8; break;
6649 default: found = 16;
6653 inst.operands[i].isvec = 1;
6654 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6655 inst.operands[i].reg = REG_PC;
6662 po_misc_or_fail (parse_tb (&str));
6665 /* Register lists. */
6667 val = parse_reg_list (&str);
6670 inst.operands[1].writeback = 1;
6676 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6680 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6684 /* Allow Q registers too. */
6685 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6690 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6692 inst.operands[i].issingle = 1;
6697 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6702 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6703 &inst.operands[i].vectype);
6706 /* Addressing modes */
6708 po_misc_or_fail (parse_address (&str, i));
6712 po_misc_or_fail_no_backtrack (
6713 parse_address_group_reloc (&str, i, GROUP_LDR));
6717 po_misc_or_fail_no_backtrack (
6718 parse_address_group_reloc (&str, i, GROUP_LDRS));
6722 po_misc_or_fail_no_backtrack (
6723 parse_address_group_reloc (&str, i, GROUP_LDC));
6727 po_misc_or_fail (parse_shifter_operand (&str, i));
6731 po_misc_or_fail_no_backtrack (
6732 parse_shifter_operand_group_reloc (&str, i));
6736 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6740 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6744 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6748 as_fatal (_("unhandled operand code %d"), op_parse_code);
6751 /* Various value-based sanity checks and shared operations. We
6752 do not signal immediate failures for the register constraints;
6753 this allows a syntax error to take precedence. */
6754 switch (op_parse_code)
6762 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6763 inst.error = BAD_PC;
6768 if (inst.operands[i].isreg)
6770 if (inst.operands[i].reg == REG_PC)
6771 inst.error = BAD_PC;
6772 else if (inst.operands[i].reg == REG_SP)
6773 inst.error = BAD_SP;
6778 if (inst.operands[i].isreg
6779 && inst.operands[i].reg == REG_PC
6780 && (inst.operands[i].writeback || thumb))
6781 inst.error = BAD_PC;
6790 case OP_oBARRIER_I15:
6799 inst.operands[i].imm = val;
6806 /* If we get here, this operand was successfully parsed. */
6807 inst.operands[i].present = 1;
6811 inst.error = BAD_ARGS;
6816 /* The parse routine should already have set inst.error, but set a
6817 default here just in case. */
6819 inst.error = _("syntax error");
6823 /* Do not backtrack over a trailing optional argument that
6824 absorbed some text. We will only fail again, with the
6825 'garbage following instruction' error message, which is
6826 probably less helpful than the current one. */
6827 if (backtrack_index == i && backtrack_pos != str
6828 && upat[i+1] == OP_stop)
6831 inst.error = _("syntax error");
6835 /* Try again, skipping the optional argument at backtrack_pos. */
6836 str = backtrack_pos;
6837 inst.error = backtrack_error;
6838 inst.operands[backtrack_index].present = 0;
6839 i = backtrack_index;
6843 /* Check that we have parsed all the arguments. */
6844 if (*str != '\0' && !inst.error)
6845 inst.error = _("garbage following instruction");
6847 return inst.error ? FAIL : SUCCESS;
6850 #undef po_char_or_fail
6851 #undef po_reg_or_fail
6852 #undef po_reg_or_goto
6853 #undef po_imm_or_fail
6854 #undef po_scalar_or_fail
6855 #undef po_barrier_or_imm
6857 /* Shorthand macro for instruction encoding functions issuing errors. */
6858 #define constraint(expr, err) \
6869 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6870 instructions are unpredictable if these registers are used. This
6871 is the BadReg predicate in ARM's Thumb-2 documentation. */
6872 #define reject_bad_reg(reg) \
6874 if (reg == REG_SP || reg == REG_PC) \
6876 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6881 /* If REG is R13 (the stack pointer), warn that its use is
6883 #define warn_deprecated_sp(reg) \
6885 if (warn_on_deprecated && reg == REG_SP) \
6886 as_warn (_("use of r13 is deprecated")); \
6889 /* Functions for operand encoding. ARM, then Thumb. */
6891 #define rotate_left(v, n) (v << n | v >> (32 - n))
6893 /* If VAL can be encoded in the immediate field of an ARM instruction,
6894 return the encoded form. Otherwise, return FAIL. */
6897 encode_arm_immediate (unsigned int val)
6901 for (i = 0; i < 32; i += 2)
6902 if ((a = rotate_left (val, i)) <= 0xff)
6903 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6908 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6909 return the encoded form. Otherwise, return FAIL. */
6911 encode_thumb32_immediate (unsigned int val)
6918 for (i = 1; i <= 24; i++)
6921 if ((val & ~(0xff << i)) == 0)
6922 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6926 if (val == ((a << 16) | a))
6928 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6932 if (val == ((a << 16) | a))
6933 return 0x200 | (a >> 8);
6937 /* Encode a VFP SP or DP register number into inst.instruction. */
6940 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6942 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6945 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6948 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6951 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6956 first_error (_("D register out of range for selected VFP version"));
6964 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6968 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6972 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6976 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6980 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6984 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6992 /* Encode a <shift> in an ARM-format instruction. The immediate,
6993 if any, is handled by md_apply_fix. */
6995 encode_arm_shift (int i)
6997 if (inst.operands[i].shift_kind == SHIFT_RRX)
6998 inst.instruction |= SHIFT_ROR << 5;
7001 inst.instruction |= inst.operands[i].shift_kind << 5;
7002 if (inst.operands[i].immisreg)
7004 inst.instruction |= SHIFT_BY_REG;
7005 inst.instruction |= inst.operands[i].imm << 8;
7008 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7013 encode_arm_shifter_operand (int i)
7015 if (inst.operands[i].isreg)
7017 inst.instruction |= inst.operands[i].reg;
7018 encode_arm_shift (i);
7022 inst.instruction |= INST_IMMEDIATE;
7023 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7024 inst.instruction |= inst.operands[i].imm;
7028 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7030 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7032 gas_assert (inst.operands[i].isreg);
7033 inst.instruction |= inst.operands[i].reg << 16;
7035 if (inst.operands[i].preind)
7039 inst.error = _("instruction does not accept preindexed addressing");
7042 inst.instruction |= PRE_INDEX;
7043 if (inst.operands[i].writeback)
7044 inst.instruction |= WRITE_BACK;
7047 else if (inst.operands[i].postind)
7049 gas_assert (inst.operands[i].writeback);
7051 inst.instruction |= WRITE_BACK;
7053 else /* unindexed - only for coprocessor */
7055 inst.error = _("instruction does not accept unindexed addressing");
7059 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7060 && (((inst.instruction & 0x000f0000) >> 16)
7061 == ((inst.instruction & 0x0000f000) >> 12)))
7062 as_warn ((inst.instruction & LOAD_BIT)
7063 ? _("destination register same as write-back base")
7064 : _("source register same as write-back base"));
7067 /* inst.operands[i] was set up by parse_address. Encode it into an
7068 ARM-format mode 2 load or store instruction. If is_t is true,
7069 reject forms that cannot be used with a T instruction (i.e. not
7072 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7074 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7076 encode_arm_addr_mode_common (i, is_t);
7078 if (inst.operands[i].immisreg)
7080 constraint ((inst.operands[i].imm == REG_PC
7081 || (is_pc && inst.operands[i].writeback)),
7083 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7084 inst.instruction |= inst.operands[i].imm;
7085 if (!inst.operands[i].negative)
7086 inst.instruction |= INDEX_UP;
7087 if (inst.operands[i].shifted)
7089 if (inst.operands[i].shift_kind == SHIFT_RRX)
7090 inst.instruction |= SHIFT_ROR << 5;
7093 inst.instruction |= inst.operands[i].shift_kind << 5;
7094 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7098 else /* immediate offset in inst.reloc */
7100 if (is_pc && !inst.reloc.pc_rel)
7102 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7104 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7105 cannot use PC in addressing.
7106 PC cannot be used in writeback addressing, either. */
7107 constraint ((is_t || inst.operands[i].writeback),
7110 /* Use of PC in str is deprecated for ARMv7. */
7111 if (warn_on_deprecated
7113 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7114 as_warn (_("use of PC in this instruction is deprecated"));
7117 if (inst.reloc.type == BFD_RELOC_UNUSED)
7119 /* Prefer + for zero encoded value. */
7120 if (!inst.operands[i].negative)
7121 inst.instruction |= INDEX_UP;
7122 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7127 /* inst.operands[i] was set up by parse_address. Encode it into an
7128 ARM-format mode 3 load or store instruction. Reject forms that
7129 cannot be used with such instructions. If is_t is true, reject
7130 forms that cannot be used with a T instruction (i.e. not
7133 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7135 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7137 inst.error = _("instruction does not accept scaled register index");
7141 encode_arm_addr_mode_common (i, is_t);
7143 if (inst.operands[i].immisreg)
7145 constraint ((inst.operands[i].imm == REG_PC
7146 || inst.operands[i].reg == REG_PC),
7148 inst.instruction |= inst.operands[i].imm;
7149 if (!inst.operands[i].negative)
7150 inst.instruction |= INDEX_UP;
7152 else /* immediate offset in inst.reloc */
7154 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7155 && inst.operands[i].writeback),
7157 inst.instruction |= HWOFFSET_IMM;
7158 if (inst.reloc.type == BFD_RELOC_UNUSED)
7160 /* Prefer + for zero encoded value. */
7161 if (!inst.operands[i].negative)
7162 inst.instruction |= INDEX_UP;
7164 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7169 /* inst.operands[i] was set up by parse_address. Encode it into an
7170 ARM-format instruction. Reject all forms which cannot be encoded
7171 into a coprocessor load/store instruction. If wb_ok is false,
7172 reject use of writeback; if unind_ok is false, reject use of
7173 unindexed addressing. If reloc_override is not 0, use it instead
7174 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7175 (in which case it is preserved). */
7178 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7180 inst.instruction |= inst.operands[i].reg << 16;
7182 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7184 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7186 gas_assert (!inst.operands[i].writeback);
7189 inst.error = _("instruction does not support unindexed addressing");
7192 inst.instruction |= inst.operands[i].imm;
7193 inst.instruction |= INDEX_UP;
7197 if (inst.operands[i].preind)
7198 inst.instruction |= PRE_INDEX;
7200 if (inst.operands[i].writeback)
7202 if (inst.operands[i].reg == REG_PC)
7204 inst.error = _("pc may not be used with write-back");
7209 inst.error = _("instruction does not support writeback");
7212 inst.instruction |= WRITE_BACK;
7216 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7217 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7218 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7219 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7222 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7224 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7227 /* Prefer + for zero encoded value. */
7228 if (!inst.operands[i].negative)
7229 inst.instruction |= INDEX_UP;
7234 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7235 Determine whether it can be performed with a move instruction; if
7236 it can, convert inst.instruction to that move instruction and
7237 return TRUE; if it can't, convert inst.instruction to a literal-pool
7238 load and return FALSE. If this is not a valid thing to do in the
7239 current context, set inst.error and return TRUE.
7241 inst.operands[i] describes the destination register. */
7244 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7249 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7253 if ((inst.instruction & tbit) == 0)
7255 inst.error = _("invalid pseudo operation");
7258 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7260 inst.error = _("constant expression expected");
7263 if (inst.reloc.exp.X_op == O_constant)
7267 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7269 /* This can be done with a mov(1) instruction. */
7270 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7271 inst.instruction |= inst.reloc.exp.X_add_number;
7277 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7280 /* This can be done with a mov instruction. */
7281 inst.instruction &= LITERAL_MASK;
7282 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7283 inst.instruction |= value & 0xfff;
7287 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7290 /* This can be done with a mvn instruction. */
7291 inst.instruction &= LITERAL_MASK;
7292 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7293 inst.instruction |= value & 0xfff;
7299 if (add_to_lit_pool () == FAIL)
7301 inst.error = _("literal pool insertion failed");
7304 inst.operands[1].reg = REG_PC;
7305 inst.operands[1].isreg = 1;
7306 inst.operands[1].preind = 1;
7307 inst.reloc.pc_rel = 1;
7308 inst.reloc.type = (thumb_p
7309 ? BFD_RELOC_ARM_THUMB_OFFSET
7311 ? BFD_RELOC_ARM_HWLITERAL
7312 : BFD_RELOC_ARM_LITERAL));
7316 /* Functions for instruction encoding, sorted by sub-architecture.
7317 First some generics; their names are taken from the conventional
7318 bit positions for register arguments in ARM format instructions. */
7328 inst.instruction |= inst.operands[0].reg << 12;
7334 inst.instruction |= inst.operands[0].reg << 12;
7335 inst.instruction |= inst.operands[1].reg;
7341 inst.instruction |= inst.operands[0].reg << 12;
7342 inst.instruction |= inst.operands[1].reg << 16;
7348 inst.instruction |= inst.operands[0].reg << 16;
7349 inst.instruction |= inst.operands[1].reg << 12;
7355 unsigned Rn = inst.operands[2].reg;
7356 /* Enforce restrictions on SWP instruction. */
7357 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7359 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7360 _("Rn must not overlap other operands"));
7362 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7363 if (warn_on_deprecated
7364 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7365 as_warn (_("swp{b} use is deprecated for this architecture"));
7368 inst.instruction |= inst.operands[0].reg << 12;
7369 inst.instruction |= inst.operands[1].reg;
7370 inst.instruction |= Rn << 16;
7376 inst.instruction |= inst.operands[0].reg << 12;
7377 inst.instruction |= inst.operands[1].reg << 16;
7378 inst.instruction |= inst.operands[2].reg;
7384 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7385 constraint (((inst.reloc.exp.X_op != O_constant
7386 && inst.reloc.exp.X_op != O_illegal)
7387 || inst.reloc.exp.X_add_number != 0),
7389 inst.instruction |= inst.operands[0].reg;
7390 inst.instruction |= inst.operands[1].reg << 12;
7391 inst.instruction |= inst.operands[2].reg << 16;
7397 inst.instruction |= inst.operands[0].imm;
7403 inst.instruction |= inst.operands[0].reg << 12;
7404 encode_arm_cp_address (1, TRUE, TRUE, 0);
7407 /* ARM instructions, in alphabetical order by function name (except
7408 that wrapper functions appear immediately after the function they
7411 /* This is a pseudo-op of the form "adr rd, label" to be converted
7412 into a relative address of the form "add rd, pc, #label-.-8". */
7417 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7419 /* Frag hacking will turn this into a sub instruction if the offset turns
7420 out to be negative. */
7421 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7422 inst.reloc.pc_rel = 1;
7423 inst.reloc.exp.X_add_number -= 8;
7426 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7427 into a relative address of the form:
7428 add rd, pc, #low(label-.-8)"
7429 add rd, rd, #high(label-.-8)" */
7434 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7436 /* Frag hacking will turn this into a sub instruction if the offset turns
7437 out to be negative. */
7438 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7439 inst.reloc.pc_rel = 1;
7440 inst.size = INSN_SIZE * 2;
7441 inst.reloc.exp.X_add_number -= 8;
7447 if (!inst.operands[1].present)
7448 inst.operands[1].reg = inst.operands[0].reg;
7449 inst.instruction |= inst.operands[0].reg << 12;
7450 inst.instruction |= inst.operands[1].reg << 16;
7451 encode_arm_shifter_operand (2);
7457 if (inst.operands[0].present)
7459 constraint ((inst.instruction & 0xf0) != 0x40
7460 && inst.operands[0].imm > 0xf
7461 && inst.operands[0].imm < 0x0,
7462 _("bad barrier type"));
7463 inst.instruction |= inst.operands[0].imm;
7466 inst.instruction |= 0xf;
7472 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7473 constraint (msb > 32, _("bit-field extends past end of register"));
7474 /* The instruction encoding stores the LSB and MSB,
7475 not the LSB and width. */
7476 inst.instruction |= inst.operands[0].reg << 12;
7477 inst.instruction |= inst.operands[1].imm << 7;
7478 inst.instruction |= (msb - 1) << 16;
7486 /* #0 in second position is alternative syntax for bfc, which is
7487 the same instruction but with REG_PC in the Rm field. */
7488 if (!inst.operands[1].isreg)
7489 inst.operands[1].reg = REG_PC;
7491 msb = inst.operands[2].imm + inst.operands[3].imm;
7492 constraint (msb > 32, _("bit-field extends past end of register"));
7493 /* The instruction encoding stores the LSB and MSB,
7494 not the LSB and width. */
7495 inst.instruction |= inst.operands[0].reg << 12;
7496 inst.instruction |= inst.operands[1].reg;
7497 inst.instruction |= inst.operands[2].imm << 7;
7498 inst.instruction |= (msb - 1) << 16;
7504 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7505 _("bit-field extends past end of register"));
7506 inst.instruction |= inst.operands[0].reg << 12;
7507 inst.instruction |= inst.operands[1].reg;
7508 inst.instruction |= inst.operands[2].imm << 7;
7509 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7512 /* ARM V5 breakpoint instruction (argument parse)
7513 BKPT <16 bit unsigned immediate>
7514 Instruction is not conditional.
7515 The bit pattern given in insns[] has the COND_ALWAYS condition,
7516 and it is an error if the caller tried to override that. */
7521 /* Top 12 of 16 bits to bits 19:8. */
7522 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7524 /* Bottom 4 of 16 bits to bits 3:0. */
7525 inst.instruction |= inst.operands[0].imm & 0xf;
7529 encode_branch (int default_reloc)
7531 if (inst.operands[0].hasreloc)
7533 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7534 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7535 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7536 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7537 ? BFD_RELOC_ARM_PLT32
7538 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7541 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7542 inst.reloc.pc_rel = 1;
7549 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7550 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7553 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7560 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7562 if (inst.cond == COND_ALWAYS)
7563 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7565 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7569 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7572 /* ARM V5 branch-link-exchange instruction (argument parse)
7573 BLX <target_addr> ie BLX(1)
7574 BLX{<condition>} <Rm> ie BLX(2)
7575 Unfortunately, there are two different opcodes for this mnemonic.
7576 So, the insns[].value is not used, and the code here zaps values
7577 into inst.instruction.
7578 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7583 if (inst.operands[0].isreg)
7585 /* Arg is a register; the opcode provided by insns[] is correct.
7586 It is not illegal to do "blx pc", just useless. */
7587 if (inst.operands[0].reg == REG_PC)
7588 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7590 inst.instruction |= inst.operands[0].reg;
7594 /* Arg is an address; this instruction cannot be executed
7595 conditionally, and the opcode must be adjusted.
7596 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7597 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7598 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7599 inst.instruction = 0xfa000000;
7600 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7607 bfd_boolean want_reloc;
7609 if (inst.operands[0].reg == REG_PC)
7610 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7612 inst.instruction |= inst.operands[0].reg;
7613 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7614 it is for ARMv4t or earlier. */
7615 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7616 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7620 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7625 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7629 /* ARM v5TEJ. Jump to Jazelle code. */
7634 if (inst.operands[0].reg == REG_PC)
7635 as_tsktsk (_("use of r15 in bxj is not really useful"));
7637 inst.instruction |= inst.operands[0].reg;
7640 /* Co-processor data operation:
7641 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7642 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7646 inst.instruction |= inst.operands[0].reg << 8;
7647 inst.instruction |= inst.operands[1].imm << 20;
7648 inst.instruction |= inst.operands[2].reg << 12;
7649 inst.instruction |= inst.operands[3].reg << 16;
7650 inst.instruction |= inst.operands[4].reg;
7651 inst.instruction |= inst.operands[5].imm << 5;
7657 inst.instruction |= inst.operands[0].reg << 16;
7658 encode_arm_shifter_operand (1);
7661 /* Transfer between coprocessor and ARM registers.
7662 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7667 No special properties. */
7674 Rd = inst.operands[2].reg;
7677 if (inst.instruction == 0xee000010
7678 || inst.instruction == 0xfe000010)
7680 reject_bad_reg (Rd);
7683 constraint (Rd == REG_SP, BAD_SP);
7688 if (inst.instruction == 0xe000010)
7689 constraint (Rd == REG_PC, BAD_PC);
7693 inst.instruction |= inst.operands[0].reg << 8;
7694 inst.instruction |= inst.operands[1].imm << 21;
7695 inst.instruction |= Rd << 12;
7696 inst.instruction |= inst.operands[3].reg << 16;
7697 inst.instruction |= inst.operands[4].reg;
7698 inst.instruction |= inst.operands[5].imm << 5;
7701 /* Transfer between coprocessor register and pair of ARM registers.
7702 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7707 Two XScale instructions are special cases of these:
7709 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7710 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7712 Result unpredictable if Rd or Rn is R15. */
7719 Rd = inst.operands[2].reg;
7720 Rn = inst.operands[3].reg;
7724 reject_bad_reg (Rd);
7725 reject_bad_reg (Rn);
7729 constraint (Rd == REG_PC, BAD_PC);
7730 constraint (Rn == REG_PC, BAD_PC);
7733 inst.instruction |= inst.operands[0].reg << 8;
7734 inst.instruction |= inst.operands[1].imm << 4;
7735 inst.instruction |= Rd << 12;
7736 inst.instruction |= Rn << 16;
7737 inst.instruction |= inst.operands[4].reg;
7743 inst.instruction |= inst.operands[0].imm << 6;
7744 if (inst.operands[1].present)
7746 inst.instruction |= CPSI_MMOD;
7747 inst.instruction |= inst.operands[1].imm;
7754 inst.instruction |= inst.operands[0].imm;
7760 unsigned Rd, Rn, Rm;
7762 Rd = inst.operands[0].reg;
7763 Rn = (inst.operands[1].present
7764 ? inst.operands[1].reg : Rd);
7765 Rm = inst.operands[2].reg;
7767 constraint ((Rd == REG_PC), BAD_PC);
7768 constraint ((Rn == REG_PC), BAD_PC);
7769 constraint ((Rm == REG_PC), BAD_PC);
7771 inst.instruction |= Rd << 16;
7772 inst.instruction |= Rn << 0;
7773 inst.instruction |= Rm << 8;
7779 /* There is no IT instruction in ARM mode. We
7780 process it to do the validation as if in
7781 thumb mode, just in case the code gets
7782 assembled for thumb using the unified syntax. */
7787 set_it_insn_type (IT_INSN);
7788 now_it.mask = (inst.instruction & 0xf) | 0x10;
7789 now_it.cc = inst.operands[0].imm;
7796 int base_reg = inst.operands[0].reg;
7797 int range = inst.operands[1].imm;
7799 inst.instruction |= base_reg << 16;
7800 inst.instruction |= range;
7802 if (inst.operands[1].writeback)
7803 inst.instruction |= LDM_TYPE_2_OR_3;
7805 if (inst.operands[0].writeback)
7807 inst.instruction |= WRITE_BACK;
7808 /* Check for unpredictable uses of writeback. */
7809 if (inst.instruction & LOAD_BIT)
7811 /* Not allowed in LDM type 2. */
7812 if ((inst.instruction & LDM_TYPE_2_OR_3)
7813 && ((range & (1 << REG_PC)) == 0))
7814 as_warn (_("writeback of base register is UNPREDICTABLE"));
7815 /* Only allowed if base reg not in list for other types. */
7816 else if (range & (1 << base_reg))
7817 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7821 /* Not allowed for type 2. */
7822 if (inst.instruction & LDM_TYPE_2_OR_3)
7823 as_warn (_("writeback of base register is UNPREDICTABLE"));
7824 /* Only allowed if base reg not in list, or first in list. */
7825 else if ((range & (1 << base_reg))
7826 && (range & ((1 << base_reg) - 1)))
7827 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7832 /* ARMv5TE load-consecutive (argument parse)
7841 constraint (inst.operands[0].reg % 2 != 0,
7842 _("first transfer register must be even"));
7843 constraint (inst.operands[1].present
7844 && inst.operands[1].reg != inst.operands[0].reg + 1,
7845 _("can only transfer two consecutive registers"));
7846 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7847 constraint (!inst.operands[2].isreg, _("'[' expected"));
7849 if (!inst.operands[1].present)
7850 inst.operands[1].reg = inst.operands[0].reg + 1;
7852 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7853 register and the first register written; we have to diagnose
7854 overlap between the base and the second register written here. */
7856 if (inst.operands[2].reg == inst.operands[1].reg
7857 && (inst.operands[2].writeback || inst.operands[2].postind))
7858 as_warn (_("base register written back, and overlaps "
7859 "second transfer register"));
7861 if (!(inst.instruction & V4_STR_BIT))
7863 /* For an index-register load, the index register must not overlap the
7864 destination (even if not write-back). */
7865 if (inst.operands[2].immisreg
7866 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7867 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7868 as_warn (_("index register overlaps transfer register"));
7870 inst.instruction |= inst.operands[0].reg << 12;
7871 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7877 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7878 || inst.operands[1].postind || inst.operands[1].writeback
7879 || inst.operands[1].immisreg || inst.operands[1].shifted
7880 || inst.operands[1].negative
7881 /* This can arise if the programmer has written
7883 or if they have mistakenly used a register name as the last
7886 It is very difficult to distinguish between these two cases
7887 because "rX" might actually be a label. ie the register
7888 name has been occluded by a symbol of the same name. So we
7889 just generate a general 'bad addressing mode' type error
7890 message and leave it up to the programmer to discover the
7891 true cause and fix their mistake. */
7892 || (inst.operands[1].reg == REG_PC),
7895 constraint (inst.reloc.exp.X_op != O_constant
7896 || inst.reloc.exp.X_add_number != 0,
7897 _("offset must be zero in ARM encoding"));
7899 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7901 inst.instruction |= inst.operands[0].reg << 12;
7902 inst.instruction |= inst.operands[1].reg << 16;
7903 inst.reloc.type = BFD_RELOC_UNUSED;
7909 constraint (inst.operands[0].reg % 2 != 0,
7910 _("even register required"));
7911 constraint (inst.operands[1].present
7912 && inst.operands[1].reg != inst.operands[0].reg + 1,
7913 _("can only load two consecutive registers"));
7914 /* If op 1 were present and equal to PC, this function wouldn't
7915 have been called in the first place. */
7916 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7918 inst.instruction |= inst.operands[0].reg << 12;
7919 inst.instruction |= inst.operands[2].reg << 16;
7922 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7923 which is not a multiple of four is UNPREDICTABLE. */
7925 check_ldr_r15_aligned (void)
7927 constraint (!(inst.operands[1].immisreg)
7928 && (inst.operands[0].reg == REG_PC
7929 && inst.operands[1].reg == REG_PC
7930 && (inst.reloc.exp.X_add_number & 0x3)),
7931 _("ldr to register 15 must be 4-byte alligned"));
7937 inst.instruction |= inst.operands[0].reg << 12;
7938 if (!inst.operands[1].isreg)
7939 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7941 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7942 check_ldr_r15_aligned ();
7948 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7950 if (inst.operands[1].preind)
7952 constraint (inst.reloc.exp.X_op != O_constant
7953 || inst.reloc.exp.X_add_number != 0,
7954 _("this instruction requires a post-indexed address"));
7956 inst.operands[1].preind = 0;
7957 inst.operands[1].postind = 1;
7958 inst.operands[1].writeback = 1;
7960 inst.instruction |= inst.operands[0].reg << 12;
7961 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7964 /* Halfword and signed-byte load/store operations. */
7969 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7970 inst.instruction |= inst.operands[0].reg << 12;
7971 if (!inst.operands[1].isreg)
7972 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7974 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7980 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7982 if (inst.operands[1].preind)
7984 constraint (inst.reloc.exp.X_op != O_constant
7985 || inst.reloc.exp.X_add_number != 0,
7986 _("this instruction requires a post-indexed address"));
7988 inst.operands[1].preind = 0;
7989 inst.operands[1].postind = 1;
7990 inst.operands[1].writeback = 1;
7992 inst.instruction |= inst.operands[0].reg << 12;
7993 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
7996 /* Co-processor register load/store.
7997 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8001 inst.instruction |= inst.operands[0].reg << 8;
8002 inst.instruction |= inst.operands[1].reg << 12;
8003 encode_arm_cp_address (2, TRUE, TRUE, 0);
8009 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8010 if (inst.operands[0].reg == inst.operands[1].reg
8011 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8012 && !(inst.instruction & 0x00400000))
8013 as_tsktsk (_("Rd and Rm should be different in mla"));
8015 inst.instruction |= inst.operands[0].reg << 16;
8016 inst.instruction |= inst.operands[1].reg;
8017 inst.instruction |= inst.operands[2].reg << 8;
8018 inst.instruction |= inst.operands[3].reg << 12;
8024 inst.instruction |= inst.operands[0].reg << 12;
8025 encode_arm_shifter_operand (1);
8028 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8035 top = (inst.instruction & 0x00400000) != 0;
8036 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8037 _(":lower16: not allowed this instruction"));
8038 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8039 _(":upper16: not allowed instruction"));
8040 inst.instruction |= inst.operands[0].reg << 12;
8041 if (inst.reloc.type == BFD_RELOC_UNUSED)
8043 imm = inst.reloc.exp.X_add_number;
8044 /* The value is in two pieces: 0:11, 16:19. */
8045 inst.instruction |= (imm & 0x00000fff);
8046 inst.instruction |= (imm & 0x0000f000) << 4;
8050 static void do_vfp_nsyn_opcode (const char *);
8053 do_vfp_nsyn_mrs (void)
8055 if (inst.operands[0].isvec)
8057 if (inst.operands[1].reg != 1)
8058 first_error (_("operand 1 must be FPSCR"));
8059 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8060 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8061 do_vfp_nsyn_opcode ("fmstat");
8063 else if (inst.operands[1].isvec)
8064 do_vfp_nsyn_opcode ("fmrx");
8072 do_vfp_nsyn_msr (void)
8074 if (inst.operands[0].isvec)
8075 do_vfp_nsyn_opcode ("fmxr");
8085 unsigned Rt = inst.operands[0].reg;
8087 if (thumb_mode && inst.operands[0].reg == REG_SP)
8089 inst.error = BAD_SP;
8093 /* APSR_ sets isvec. All other refs to PC are illegal. */
8094 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8096 inst.error = BAD_PC;
8100 if (inst.operands[1].reg != 1)
8101 first_error (_("operand 1 must be FPSCR"));
8103 inst.instruction |= (Rt << 12);
8109 unsigned Rt = inst.operands[1].reg;
8112 reject_bad_reg (Rt);
8113 else if (Rt == REG_PC)
8115 inst.error = BAD_PC;
8119 if (inst.operands[0].reg != 1)
8120 first_error (_("operand 0 must be FPSCR"));
8122 inst.instruction |= (Rt << 12);
8130 if (do_vfp_nsyn_mrs () == SUCCESS)
8133 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8134 inst.instruction |= inst.operands[0].reg << 12;
8136 if (inst.operands[1].isreg)
8138 br = inst.operands[1].reg;
8139 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8140 as_bad (_("bad register for mrs"));
8144 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8145 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8147 _("'APSR', 'CPSR' or 'SPSR' expected"));
8148 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8151 inst.instruction |= br;
8154 /* Two possible forms:
8155 "{C|S}PSR_<field>, Rm",
8156 "{C|S}PSR_f, #expression". */
8161 if (do_vfp_nsyn_msr () == SUCCESS)
8164 inst.instruction |= inst.operands[0].imm;
8165 if (inst.operands[1].isreg)
8166 inst.instruction |= inst.operands[1].reg;
8169 inst.instruction |= INST_IMMEDIATE;
8170 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8171 inst.reloc.pc_rel = 0;
8178 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8180 if (!inst.operands[2].present)
8181 inst.operands[2].reg = inst.operands[0].reg;
8182 inst.instruction |= inst.operands[0].reg << 16;
8183 inst.instruction |= inst.operands[1].reg;
8184 inst.instruction |= inst.operands[2].reg << 8;
8186 if (inst.operands[0].reg == inst.operands[1].reg
8187 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8188 as_tsktsk (_("Rd and Rm should be different in mul"));
8191 /* Long Multiply Parser
8192 UMULL RdLo, RdHi, Rm, Rs
8193 SMULL RdLo, RdHi, Rm, Rs
8194 UMLAL RdLo, RdHi, Rm, Rs
8195 SMLAL RdLo, RdHi, Rm, Rs. */
8200 inst.instruction |= inst.operands[0].reg << 12;
8201 inst.instruction |= inst.operands[1].reg << 16;
8202 inst.instruction |= inst.operands[2].reg;
8203 inst.instruction |= inst.operands[3].reg << 8;
8205 /* rdhi and rdlo must be different. */
8206 if (inst.operands[0].reg == inst.operands[1].reg)
8207 as_tsktsk (_("rdhi and rdlo must be different"));
8209 /* rdhi, rdlo and rm must all be different before armv6. */
8210 if ((inst.operands[0].reg == inst.operands[2].reg
8211 || inst.operands[1].reg == inst.operands[2].reg)
8212 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8213 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8219 if (inst.operands[0].present
8220 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8222 /* Architectural NOP hints are CPSR sets with no bits selected. */
8223 inst.instruction &= 0xf0000000;
8224 inst.instruction |= 0x0320f000;
8225 if (inst.operands[0].present)
8226 inst.instruction |= inst.operands[0].imm;
8230 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8231 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8232 Condition defaults to COND_ALWAYS.
8233 Error if Rd, Rn or Rm are R15. */
8238 inst.instruction |= inst.operands[0].reg << 12;
8239 inst.instruction |= inst.operands[1].reg << 16;
8240 inst.instruction |= inst.operands[2].reg;
8241 if (inst.operands[3].present)
8242 encode_arm_shift (3);
8245 /* ARM V6 PKHTB (Argument Parse). */
8250 if (!inst.operands[3].present)
8252 /* If the shift specifier is omitted, turn the instruction
8253 into pkhbt rd, rm, rn. */
8254 inst.instruction &= 0xfff00010;
8255 inst.instruction |= inst.operands[0].reg << 12;
8256 inst.instruction |= inst.operands[1].reg;
8257 inst.instruction |= inst.operands[2].reg << 16;
8261 inst.instruction |= inst.operands[0].reg << 12;
8262 inst.instruction |= inst.operands[1].reg << 16;
8263 inst.instruction |= inst.operands[2].reg;
8264 encode_arm_shift (3);
8268 /* ARMv5TE: Preload-Cache
8269 MP Extensions: Preload for write
8273 Syntactically, like LDR with B=1, W=0, L=1. */
8278 constraint (!inst.operands[0].isreg,
8279 _("'[' expected after PLD mnemonic"));
8280 constraint (inst.operands[0].postind,
8281 _("post-indexed expression used in preload instruction"));
8282 constraint (inst.operands[0].writeback,
8283 _("writeback used in preload instruction"));
8284 constraint (!inst.operands[0].preind,
8285 _("unindexed addressing used in preload instruction"));
8286 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8289 /* ARMv7: PLI <addr_mode> */
8293 constraint (!inst.operands[0].isreg,
8294 _("'[' expected after PLI mnemonic"));
8295 constraint (inst.operands[0].postind,
8296 _("post-indexed expression used in preload instruction"));
8297 constraint (inst.operands[0].writeback,
8298 _("writeback used in preload instruction"));
8299 constraint (!inst.operands[0].preind,
8300 _("unindexed addressing used in preload instruction"));
8301 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8302 inst.instruction &= ~PRE_INDEX;
8308 inst.operands[1] = inst.operands[0];
8309 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8310 inst.operands[0].isreg = 1;
8311 inst.operands[0].writeback = 1;
8312 inst.operands[0].reg = REG_SP;
8316 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8317 word at the specified address and the following word
8319 Unconditionally executed.
8320 Error if Rn is R15. */
8325 inst.instruction |= inst.operands[0].reg << 16;
8326 if (inst.operands[0].writeback)
8327 inst.instruction |= WRITE_BACK;
8330 /* ARM V6 ssat (argument parse). */
8335 inst.instruction |= inst.operands[0].reg << 12;
8336 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8337 inst.instruction |= inst.operands[2].reg;
8339 if (inst.operands[3].present)
8340 encode_arm_shift (3);
8343 /* ARM V6 usat (argument parse). */
8348 inst.instruction |= inst.operands[0].reg << 12;
8349 inst.instruction |= inst.operands[1].imm << 16;
8350 inst.instruction |= inst.operands[2].reg;
8352 if (inst.operands[3].present)
8353 encode_arm_shift (3);
8356 /* ARM V6 ssat16 (argument parse). */
8361 inst.instruction |= inst.operands[0].reg << 12;
8362 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8363 inst.instruction |= inst.operands[2].reg;
8369 inst.instruction |= inst.operands[0].reg << 12;
8370 inst.instruction |= inst.operands[1].imm << 16;
8371 inst.instruction |= inst.operands[2].reg;
8374 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8375 preserving the other bits.
8377 setend <endian_specifier>, where <endian_specifier> is either
8383 if (inst.operands[0].imm)
8384 inst.instruction |= 0x200;
8390 unsigned int Rm = (inst.operands[1].present
8391 ? inst.operands[1].reg
8392 : inst.operands[0].reg);
8394 inst.instruction |= inst.operands[0].reg << 12;
8395 inst.instruction |= Rm;
8396 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8398 inst.instruction |= inst.operands[2].reg << 8;
8399 inst.instruction |= SHIFT_BY_REG;
8400 /* PR 12854: Error on extraneous shifts. */
8401 constraint (inst.operands[2].shifted,
8402 _("extraneous shift as part of operand to shift insn"));
8405 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8411 inst.reloc.type = BFD_RELOC_ARM_SMC;
8412 inst.reloc.pc_rel = 0;
8418 inst.reloc.type = BFD_RELOC_ARM_HVC;
8419 inst.reloc.pc_rel = 0;
8425 inst.reloc.type = BFD_RELOC_ARM_SWI;
8426 inst.reloc.pc_rel = 0;
8429 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8430 SMLAxy{cond} Rd,Rm,Rs,Rn
8431 SMLAWy{cond} Rd,Rm,Rs,Rn
8432 Error if any register is R15. */
8437 inst.instruction |= inst.operands[0].reg << 16;
8438 inst.instruction |= inst.operands[1].reg;
8439 inst.instruction |= inst.operands[2].reg << 8;
8440 inst.instruction |= inst.operands[3].reg << 12;
8443 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8444 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8445 Error if any register is R15.
8446 Warning if Rdlo == Rdhi. */
8451 inst.instruction |= inst.operands[0].reg << 12;
8452 inst.instruction |= inst.operands[1].reg << 16;
8453 inst.instruction |= inst.operands[2].reg;
8454 inst.instruction |= inst.operands[3].reg << 8;
8456 if (inst.operands[0].reg == inst.operands[1].reg)
8457 as_tsktsk (_("rdhi and rdlo must be different"));
8460 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8461 SMULxy{cond} Rd,Rm,Rs
8462 Error if any register is R15. */
8467 inst.instruction |= inst.operands[0].reg << 16;
8468 inst.instruction |= inst.operands[1].reg;
8469 inst.instruction |= inst.operands[2].reg << 8;
8472 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8473 the same for both ARM and Thumb-2. */
8480 if (inst.operands[0].present)
8482 reg = inst.operands[0].reg;
8483 constraint (reg != REG_SP, _("SRS base register must be r13"));
8488 inst.instruction |= reg << 16;
8489 inst.instruction |= inst.operands[1].imm;
8490 if (inst.operands[0].writeback || inst.operands[1].writeback)
8491 inst.instruction |= WRITE_BACK;
8494 /* ARM V6 strex (argument parse). */
8499 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8500 || inst.operands[2].postind || inst.operands[2].writeback
8501 || inst.operands[2].immisreg || inst.operands[2].shifted
8502 || inst.operands[2].negative
8503 /* See comment in do_ldrex(). */
8504 || (inst.operands[2].reg == REG_PC),
8507 constraint (inst.operands[0].reg == inst.operands[1].reg
8508 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8510 constraint (inst.reloc.exp.X_op != O_constant
8511 || inst.reloc.exp.X_add_number != 0,
8512 _("offset must be zero in ARM encoding"));
8514 inst.instruction |= inst.operands[0].reg << 12;
8515 inst.instruction |= inst.operands[1].reg;
8516 inst.instruction |= inst.operands[2].reg << 16;
8517 inst.reloc.type = BFD_RELOC_UNUSED;
8523 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8524 || inst.operands[2].postind || inst.operands[2].writeback
8525 || inst.operands[2].immisreg || inst.operands[2].shifted
8526 || inst.operands[2].negative,
8529 constraint (inst.operands[0].reg == inst.operands[1].reg
8530 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8538 constraint (inst.operands[1].reg % 2 != 0,
8539 _("even register required"));
8540 constraint (inst.operands[2].present
8541 && inst.operands[2].reg != inst.operands[1].reg + 1,
8542 _("can only store two consecutive registers"));
8543 /* If op 2 were present and equal to PC, this function wouldn't
8544 have been called in the first place. */
8545 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8547 constraint (inst.operands[0].reg == inst.operands[1].reg
8548 || inst.operands[0].reg == inst.operands[1].reg + 1
8549 || inst.operands[0].reg == inst.operands[3].reg,
8552 inst.instruction |= inst.operands[0].reg << 12;
8553 inst.instruction |= inst.operands[1].reg;
8554 inst.instruction |= inst.operands[3].reg << 16;
8557 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8558 extends it to 32-bits, and adds the result to a value in another
8559 register. You can specify a rotation by 0, 8, 16, or 24 bits
8560 before extracting the 16-bit value.
8561 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8562 Condition defaults to COND_ALWAYS.
8563 Error if any register uses R15. */
8568 inst.instruction |= inst.operands[0].reg << 12;
8569 inst.instruction |= inst.operands[1].reg << 16;
8570 inst.instruction |= inst.operands[2].reg;
8571 inst.instruction |= inst.operands[3].imm << 10;
8576 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8577 Condition defaults to COND_ALWAYS.
8578 Error if any register uses R15. */
8583 inst.instruction |= inst.operands[0].reg << 12;
8584 inst.instruction |= inst.operands[1].reg;
8585 inst.instruction |= inst.operands[2].imm << 10;
8588 /* VFP instructions. In a logical order: SP variant first, monad
8589 before dyad, arithmetic then move then load/store. */
8592 do_vfp_sp_monadic (void)
8594 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8595 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8599 do_vfp_sp_dyadic (void)
8601 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8602 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8603 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8607 do_vfp_sp_compare_z (void)
8609 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8613 do_vfp_dp_sp_cvt (void)
8615 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8616 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8620 do_vfp_sp_dp_cvt (void)
8622 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8623 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8627 do_vfp_reg_from_sp (void)
8629 inst.instruction |= inst.operands[0].reg << 12;
8630 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8634 do_vfp_reg2_from_sp2 (void)
8636 constraint (inst.operands[2].imm != 2,
8637 _("only two consecutive VFP SP registers allowed here"));
8638 inst.instruction |= inst.operands[0].reg << 12;
8639 inst.instruction |= inst.operands[1].reg << 16;
8640 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8644 do_vfp_sp_from_reg (void)
8646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8647 inst.instruction |= inst.operands[1].reg << 12;
8651 do_vfp_sp2_from_reg2 (void)
8653 constraint (inst.operands[0].imm != 2,
8654 _("only two consecutive VFP SP registers allowed here"));
8655 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8656 inst.instruction |= inst.operands[1].reg << 12;
8657 inst.instruction |= inst.operands[2].reg << 16;
8661 do_vfp_sp_ldst (void)
8663 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8664 encode_arm_cp_address (1, FALSE, TRUE, 0);
8668 do_vfp_dp_ldst (void)
8670 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8671 encode_arm_cp_address (1, FALSE, TRUE, 0);
8676 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8678 if (inst.operands[0].writeback)
8679 inst.instruction |= WRITE_BACK;
8681 constraint (ldstm_type != VFP_LDSTMIA,
8682 _("this addressing mode requires base-register writeback"));
8683 inst.instruction |= inst.operands[0].reg << 16;
8684 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8685 inst.instruction |= inst.operands[1].imm;
8689 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8693 if (inst.operands[0].writeback)
8694 inst.instruction |= WRITE_BACK;
8696 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8697 _("this addressing mode requires base-register writeback"));
8699 inst.instruction |= inst.operands[0].reg << 16;
8700 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8702 count = inst.operands[1].imm << 1;
8703 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8706 inst.instruction |= count;
8710 do_vfp_sp_ldstmia (void)
8712 vfp_sp_ldstm (VFP_LDSTMIA);
8716 do_vfp_sp_ldstmdb (void)
8718 vfp_sp_ldstm (VFP_LDSTMDB);
8722 do_vfp_dp_ldstmia (void)
8724 vfp_dp_ldstm (VFP_LDSTMIA);
8728 do_vfp_dp_ldstmdb (void)
8730 vfp_dp_ldstm (VFP_LDSTMDB);
8734 do_vfp_xp_ldstmia (void)
8736 vfp_dp_ldstm (VFP_LDSTMIAX);
8740 do_vfp_xp_ldstmdb (void)
8742 vfp_dp_ldstm (VFP_LDSTMDBX);
8746 do_vfp_dp_rd_rm (void)
8748 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8749 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8753 do_vfp_dp_rn_rd (void)
8755 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8756 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8760 do_vfp_dp_rd_rn (void)
8762 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8763 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8767 do_vfp_dp_rd_rn_rm (void)
8769 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8770 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8771 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8777 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8781 do_vfp_dp_rm_rd_rn (void)
8783 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8784 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8785 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8788 /* VFPv3 instructions. */
8790 do_vfp_sp_const (void)
8792 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8793 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8794 inst.instruction |= (inst.operands[1].imm & 0x0f);
8798 do_vfp_dp_const (void)
8800 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8801 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8802 inst.instruction |= (inst.operands[1].imm & 0x0f);
8806 vfp_conv (int srcsize)
8808 int immbits = srcsize - inst.operands[1].imm;
8810 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8812 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8813 i.e. immbits must be in range 0 - 16. */
8814 inst.error = _("immediate value out of range, expected range [0, 16]");
8817 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8819 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8820 i.e. immbits must be in range 0 - 31. */
8821 inst.error = _("immediate value out of range, expected range [1, 32]");
8825 inst.instruction |= (immbits & 1) << 5;
8826 inst.instruction |= (immbits >> 1);
8830 do_vfp_sp_conv_16 (void)
8832 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8837 do_vfp_dp_conv_16 (void)
8839 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8844 do_vfp_sp_conv_32 (void)
8846 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8851 do_vfp_dp_conv_32 (void)
8853 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8857 /* FPA instructions. Also in a logical order. */
8862 inst.instruction |= inst.operands[0].reg << 16;
8863 inst.instruction |= inst.operands[1].reg;
8867 do_fpa_ldmstm (void)
8869 inst.instruction |= inst.operands[0].reg << 12;
8870 switch (inst.operands[1].imm)
8872 case 1: inst.instruction |= CP_T_X; break;
8873 case 2: inst.instruction |= CP_T_Y; break;
8874 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8879 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8881 /* The instruction specified "ea" or "fd", so we can only accept
8882 [Rn]{!}. The instruction does not really support stacking or
8883 unstacking, so we have to emulate these by setting appropriate
8884 bits and offsets. */
8885 constraint (inst.reloc.exp.X_op != O_constant
8886 || inst.reloc.exp.X_add_number != 0,
8887 _("this instruction does not support indexing"));
8889 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8890 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8892 if (!(inst.instruction & INDEX_UP))
8893 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8895 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8897 inst.operands[2].preind = 0;
8898 inst.operands[2].postind = 1;
8902 encode_arm_cp_address (2, TRUE, TRUE, 0);
8905 /* iWMMXt instructions: strictly in alphabetical order. */
8908 do_iwmmxt_tandorc (void)
8910 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8914 do_iwmmxt_textrc (void)
8916 inst.instruction |= inst.operands[0].reg << 12;
8917 inst.instruction |= inst.operands[1].imm;
8921 do_iwmmxt_textrm (void)
8923 inst.instruction |= inst.operands[0].reg << 12;
8924 inst.instruction |= inst.operands[1].reg << 16;
8925 inst.instruction |= inst.operands[2].imm;
8929 do_iwmmxt_tinsr (void)
8931 inst.instruction |= inst.operands[0].reg << 16;
8932 inst.instruction |= inst.operands[1].reg << 12;
8933 inst.instruction |= inst.operands[2].imm;
8937 do_iwmmxt_tmia (void)
8939 inst.instruction |= inst.operands[0].reg << 5;
8940 inst.instruction |= inst.operands[1].reg;
8941 inst.instruction |= inst.operands[2].reg << 12;
8945 do_iwmmxt_waligni (void)
8947 inst.instruction |= inst.operands[0].reg << 12;
8948 inst.instruction |= inst.operands[1].reg << 16;
8949 inst.instruction |= inst.operands[2].reg;
8950 inst.instruction |= inst.operands[3].imm << 20;
8954 do_iwmmxt_wmerge (void)
8956 inst.instruction |= inst.operands[0].reg << 12;
8957 inst.instruction |= inst.operands[1].reg << 16;
8958 inst.instruction |= inst.operands[2].reg;
8959 inst.instruction |= inst.operands[3].imm << 21;
8963 do_iwmmxt_wmov (void)
8965 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8966 inst.instruction |= inst.operands[0].reg << 12;
8967 inst.instruction |= inst.operands[1].reg << 16;
8968 inst.instruction |= inst.operands[1].reg;
8972 do_iwmmxt_wldstbh (void)
8975 inst.instruction |= inst.operands[0].reg << 12;
8977 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8979 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8980 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8984 do_iwmmxt_wldstw (void)
8986 /* RIWR_RIWC clears .isreg for a control register. */
8987 if (!inst.operands[0].isreg)
8989 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8990 inst.instruction |= 0xf0000000;
8993 inst.instruction |= inst.operands[0].reg << 12;
8994 encode_arm_cp_address (1, TRUE, TRUE, 0);
8998 do_iwmmxt_wldstd (void)
9000 inst.instruction |= inst.operands[0].reg << 12;
9001 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9002 && inst.operands[1].immisreg)
9004 inst.instruction &= ~0x1a000ff;
9005 inst.instruction |= (0xf << 28);
9006 if (inst.operands[1].preind)
9007 inst.instruction |= PRE_INDEX;
9008 if (!inst.operands[1].negative)
9009 inst.instruction |= INDEX_UP;
9010 if (inst.operands[1].writeback)
9011 inst.instruction |= WRITE_BACK;
9012 inst.instruction |= inst.operands[1].reg << 16;
9013 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9014 inst.instruction |= inst.operands[1].imm;
9017 encode_arm_cp_address (1, TRUE, FALSE, 0);
9021 do_iwmmxt_wshufh (void)
9023 inst.instruction |= inst.operands[0].reg << 12;
9024 inst.instruction |= inst.operands[1].reg << 16;
9025 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9026 inst.instruction |= (inst.operands[2].imm & 0x0f);
9030 do_iwmmxt_wzero (void)
9032 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9033 inst.instruction |= inst.operands[0].reg;
9034 inst.instruction |= inst.operands[0].reg << 12;
9035 inst.instruction |= inst.operands[0].reg << 16;
9039 do_iwmmxt_wrwrwr_or_imm5 (void)
9041 if (inst.operands[2].isreg)
9044 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9045 _("immediate operand requires iWMMXt2"));
9047 if (inst.operands[2].imm == 0)
9049 switch ((inst.instruction >> 20) & 0xf)
9055 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9056 inst.operands[2].imm = 16;
9057 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9063 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9064 inst.operands[2].imm = 32;
9065 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9072 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9074 wrn = (inst.instruction >> 16) & 0xf;
9075 inst.instruction &= 0xff0fff0f;
9076 inst.instruction |= wrn;
9077 /* Bail out here; the instruction is now assembled. */
9082 /* Map 32 -> 0, etc. */
9083 inst.operands[2].imm &= 0x1f;
9084 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9088 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9089 operations first, then control, shift, and load/store. */
9091 /* Insns like "foo X,Y,Z". */
9094 do_mav_triple (void)
9096 inst.instruction |= inst.operands[0].reg << 16;
9097 inst.instruction |= inst.operands[1].reg;
9098 inst.instruction |= inst.operands[2].reg << 12;
9101 /* Insns like "foo W,X,Y,Z".
9102 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9107 inst.instruction |= inst.operands[0].reg << 5;
9108 inst.instruction |= inst.operands[1].reg << 12;
9109 inst.instruction |= inst.operands[2].reg << 16;
9110 inst.instruction |= inst.operands[3].reg;
9113 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9117 inst.instruction |= inst.operands[1].reg << 12;
9120 /* Maverick shift immediate instructions.
9121 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9122 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9127 int imm = inst.operands[2].imm;
9129 inst.instruction |= inst.operands[0].reg << 12;
9130 inst.instruction |= inst.operands[1].reg << 16;
9132 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9133 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9134 Bit 4 should be 0. */
9135 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9137 inst.instruction |= imm;
9140 /* XScale instructions. Also sorted arithmetic before move. */
9142 /* Xscale multiply-accumulate (argument parse)
9145 MIAxycc acc0,Rm,Rs. */
9150 inst.instruction |= inst.operands[1].reg;
9151 inst.instruction |= inst.operands[2].reg << 12;
9154 /* Xscale move-accumulator-register (argument parse)
9156 MARcc acc0,RdLo,RdHi. */
9161 inst.instruction |= inst.operands[1].reg << 12;
9162 inst.instruction |= inst.operands[2].reg << 16;
9165 /* Xscale move-register-accumulator (argument parse)
9167 MRAcc RdLo,RdHi,acc0. */
9172 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9173 inst.instruction |= inst.operands[0].reg << 12;
9174 inst.instruction |= inst.operands[1].reg << 16;
9177 /* Encoding functions relevant only to Thumb. */
9179 /* inst.operands[i] is a shifted-register operand; encode
9180 it into inst.instruction in the format used by Thumb32. */
9183 encode_thumb32_shifted_operand (int i)
9185 unsigned int value = inst.reloc.exp.X_add_number;
9186 unsigned int shift = inst.operands[i].shift_kind;
9188 constraint (inst.operands[i].immisreg,
9189 _("shift by register not allowed in thumb mode"));
9190 inst.instruction |= inst.operands[i].reg;
9191 if (shift == SHIFT_RRX)
9192 inst.instruction |= SHIFT_ROR << 4;
9195 constraint (inst.reloc.exp.X_op != O_constant,
9196 _("expression too complex"));
9198 constraint (value > 32
9199 || (value == 32 && (shift == SHIFT_LSL
9200 || shift == SHIFT_ROR)),
9201 _("shift expression is too large"));
9205 else if (value == 32)
9208 inst.instruction |= shift << 4;
9209 inst.instruction |= (value & 0x1c) << 10;
9210 inst.instruction |= (value & 0x03) << 6;
9215 /* inst.operands[i] was set up by parse_address. Encode it into a
9216 Thumb32 format load or store instruction. Reject forms that cannot
9217 be used with such instructions. If is_t is true, reject forms that
9218 cannot be used with a T instruction; if is_d is true, reject forms
9219 that cannot be used with a D instruction. If it is a store insn,
9223 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9225 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9227 constraint (!inst.operands[i].isreg,
9228 _("Instruction does not support =N addresses"));
9230 inst.instruction |= inst.operands[i].reg << 16;
9231 if (inst.operands[i].immisreg)
9233 constraint (is_pc, BAD_PC_ADDRESSING);
9234 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9235 constraint (inst.operands[i].negative,
9236 _("Thumb does not support negative register indexing"));
9237 constraint (inst.operands[i].postind,
9238 _("Thumb does not support register post-indexing"));
9239 constraint (inst.operands[i].writeback,
9240 _("Thumb does not support register indexing with writeback"));
9241 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9242 _("Thumb supports only LSL in shifted register indexing"));
9244 inst.instruction |= inst.operands[i].imm;
9245 if (inst.operands[i].shifted)
9247 constraint (inst.reloc.exp.X_op != O_constant,
9248 _("expression too complex"));
9249 constraint (inst.reloc.exp.X_add_number < 0
9250 || inst.reloc.exp.X_add_number > 3,
9251 _("shift out of range"));
9252 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9254 inst.reloc.type = BFD_RELOC_UNUSED;
9256 else if (inst.operands[i].preind)
9258 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9259 constraint (is_t && inst.operands[i].writeback,
9260 _("cannot use writeback with this instruction"));
9261 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9262 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9266 inst.instruction |= 0x01000000;
9267 if (inst.operands[i].writeback)
9268 inst.instruction |= 0x00200000;
9272 inst.instruction |= 0x00000c00;
9273 if (inst.operands[i].writeback)
9274 inst.instruction |= 0x00000100;
9276 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9278 else if (inst.operands[i].postind)
9280 gas_assert (inst.operands[i].writeback);
9281 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9282 constraint (is_t, _("cannot use post-indexing with this instruction"));
9285 inst.instruction |= 0x00200000;
9287 inst.instruction |= 0x00000900;
9288 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9290 else /* unindexed - only for coprocessor */
9291 inst.error = _("instruction does not accept unindexed addressing");
9294 /* Table of Thumb instructions which exist in both 16- and 32-bit
9295 encodings (the latter only in post-V6T2 cores). The index is the
9296 value used in the insns table below. When there is more than one
9297 possible 16-bit encoding for the instruction, this table always
9299 Also contains several pseudo-instructions used during relaxation. */
9300 #define T16_32_TAB \
9301 X(_adc, 4140, eb400000), \
9302 X(_adcs, 4140, eb500000), \
9303 X(_add, 1c00, eb000000), \
9304 X(_adds, 1c00, eb100000), \
9305 X(_addi, 0000, f1000000), \
9306 X(_addis, 0000, f1100000), \
9307 X(_add_pc,000f, f20f0000), \
9308 X(_add_sp,000d, f10d0000), \
9309 X(_adr, 000f, f20f0000), \
9310 X(_and, 4000, ea000000), \
9311 X(_ands, 4000, ea100000), \
9312 X(_asr, 1000, fa40f000), \
9313 X(_asrs, 1000, fa50f000), \
9314 X(_b, e000, f000b000), \
9315 X(_bcond, d000, f0008000), \
9316 X(_bic, 4380, ea200000), \
9317 X(_bics, 4380, ea300000), \
9318 X(_cmn, 42c0, eb100f00), \
9319 X(_cmp, 2800, ebb00f00), \
9320 X(_cpsie, b660, f3af8400), \
9321 X(_cpsid, b670, f3af8600), \
9322 X(_cpy, 4600, ea4f0000), \
9323 X(_dec_sp,80dd, f1ad0d00), \
9324 X(_eor, 4040, ea800000), \
9325 X(_eors, 4040, ea900000), \
9326 X(_inc_sp,00dd, f10d0d00), \
9327 X(_ldmia, c800, e8900000), \
9328 X(_ldr, 6800, f8500000), \
9329 X(_ldrb, 7800, f8100000), \
9330 X(_ldrh, 8800, f8300000), \
9331 X(_ldrsb, 5600, f9100000), \
9332 X(_ldrsh, 5e00, f9300000), \
9333 X(_ldr_pc,4800, f85f0000), \
9334 X(_ldr_pc2,4800, f85f0000), \
9335 X(_ldr_sp,9800, f85d0000), \
9336 X(_lsl, 0000, fa00f000), \
9337 X(_lsls, 0000, fa10f000), \
9338 X(_lsr, 0800, fa20f000), \
9339 X(_lsrs, 0800, fa30f000), \
9340 X(_mov, 2000, ea4f0000), \
9341 X(_movs, 2000, ea5f0000), \
9342 X(_mul, 4340, fb00f000), \
9343 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9344 X(_mvn, 43c0, ea6f0000), \
9345 X(_mvns, 43c0, ea7f0000), \
9346 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9347 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9348 X(_orr, 4300, ea400000), \
9349 X(_orrs, 4300, ea500000), \
9350 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9351 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9352 X(_rev, ba00, fa90f080), \
9353 X(_rev16, ba40, fa90f090), \
9354 X(_revsh, bac0, fa90f0b0), \
9355 X(_ror, 41c0, fa60f000), \
9356 X(_rors, 41c0, fa70f000), \
9357 X(_sbc, 4180, eb600000), \
9358 X(_sbcs, 4180, eb700000), \
9359 X(_stmia, c000, e8800000), \
9360 X(_str, 6000, f8400000), \
9361 X(_strb, 7000, f8000000), \
9362 X(_strh, 8000, f8200000), \
9363 X(_str_sp,9000, f84d0000), \
9364 X(_sub, 1e00, eba00000), \
9365 X(_subs, 1e00, ebb00000), \
9366 X(_subi, 8000, f1a00000), \
9367 X(_subis, 8000, f1b00000), \
9368 X(_sxtb, b240, fa4ff080), \
9369 X(_sxth, b200, fa0ff080), \
9370 X(_tst, 4200, ea100f00), \
9371 X(_uxtb, b2c0, fa5ff080), \
9372 X(_uxth, b280, fa1ff080), \
9373 X(_nop, bf00, f3af8000), \
9374 X(_yield, bf10, f3af8001), \
9375 X(_wfe, bf20, f3af8002), \
9376 X(_wfi, bf30, f3af8003), \
9377 X(_sev, bf40, f3af8004),
9379 /* To catch errors in encoding functions, the codes are all offset by
9380 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9381 as 16-bit instructions. */
9382 #define X(a,b,c) T_MNEM##a
9383 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9386 #define X(a,b,c) 0x##b
9387 static const unsigned short thumb_op16[] = { T16_32_TAB };
9388 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9391 #define X(a,b,c) 0x##c
9392 static const unsigned int thumb_op32[] = { T16_32_TAB };
9393 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9394 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9398 /* Thumb instruction encoders, in alphabetical order. */
9403 do_t_add_sub_w (void)
9407 Rd = inst.operands[0].reg;
9408 Rn = inst.operands[1].reg;
9410 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9411 is the SP-{plus,minus}-immediate form of the instruction. */
9413 constraint (Rd == REG_PC, BAD_PC);
9415 reject_bad_reg (Rd);
9417 inst.instruction |= (Rn << 16) | (Rd << 8);
9418 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9421 /* Parse an add or subtract instruction. We get here with inst.instruction
9422 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9429 Rd = inst.operands[0].reg;
9430 Rs = (inst.operands[1].present
9431 ? inst.operands[1].reg /* Rd, Rs, foo */
9432 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9435 set_it_insn_type_last ();
9443 flags = (inst.instruction == T_MNEM_adds
9444 || inst.instruction == T_MNEM_subs);
9446 narrow = !in_it_block ();
9448 narrow = in_it_block ();
9449 if (!inst.operands[2].isreg)
9453 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9455 add = (inst.instruction == T_MNEM_add
9456 || inst.instruction == T_MNEM_adds);
9458 if (inst.size_req != 4)
9460 /* Attempt to use a narrow opcode, with relaxation if
9462 if (Rd == REG_SP && Rs == REG_SP && !flags)
9463 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9464 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9465 opcode = T_MNEM_add_sp;
9466 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9467 opcode = T_MNEM_add_pc;
9468 else if (Rd <= 7 && Rs <= 7 && narrow)
9471 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9473 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9477 inst.instruction = THUMB_OP16(opcode);
9478 inst.instruction |= (Rd << 4) | Rs;
9479 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9480 if (inst.size_req != 2)
9481 inst.relax = opcode;
9484 constraint (inst.size_req == 2, BAD_HIREG);
9486 if (inst.size_req == 4
9487 || (inst.size_req != 2 && !opcode))
9491 constraint (add, BAD_PC);
9492 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9493 _("only SUBS PC, LR, #const allowed"));
9494 constraint (inst.reloc.exp.X_op != O_constant,
9495 _("expression too complex"));
9496 constraint (inst.reloc.exp.X_add_number < 0
9497 || inst.reloc.exp.X_add_number > 0xff,
9498 _("immediate value out of range"));
9499 inst.instruction = T2_SUBS_PC_LR
9500 | inst.reloc.exp.X_add_number;
9501 inst.reloc.type = BFD_RELOC_UNUSED;
9504 else if (Rs == REG_PC)
9506 /* Always use addw/subw. */
9507 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9508 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9512 inst.instruction = THUMB_OP32 (inst.instruction);
9513 inst.instruction = (inst.instruction & 0xe1ffffff)
9516 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9518 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9520 inst.instruction |= Rd << 8;
9521 inst.instruction |= Rs << 16;
9526 unsigned int value = inst.reloc.exp.X_add_number;
9527 unsigned int shift = inst.operands[2].shift_kind;
9529 Rn = inst.operands[2].reg;
9530 /* See if we can do this with a 16-bit instruction. */
9531 if (!inst.operands[2].shifted && inst.size_req != 4)
9533 if (Rd > 7 || Rs > 7 || Rn > 7)
9538 inst.instruction = ((inst.instruction == T_MNEM_adds
9539 || inst.instruction == T_MNEM_add)
9542 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9546 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9548 /* Thumb-1 cores (except v6-M) require at least one high
9549 register in a narrow non flag setting add. */
9550 if (Rd > 7 || Rn > 7
9551 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9552 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9559 inst.instruction = T_OPCODE_ADD_HI;
9560 inst.instruction |= (Rd & 8) << 4;
9561 inst.instruction |= (Rd & 7);
9562 inst.instruction |= Rn << 3;
9568 constraint (Rd == REG_PC, BAD_PC);
9569 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9570 constraint (Rs == REG_PC, BAD_PC);
9571 reject_bad_reg (Rn);
9573 /* If we get here, it can't be done in 16 bits. */
9574 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9575 _("shift must be constant"));
9576 inst.instruction = THUMB_OP32 (inst.instruction);
9577 inst.instruction |= Rd << 8;
9578 inst.instruction |= Rs << 16;
9579 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9580 _("shift value over 3 not allowed in thumb mode"));
9581 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9582 _("only LSL shift allowed in thumb mode"));
9583 encode_thumb32_shifted_operand (2);
9588 constraint (inst.instruction == T_MNEM_adds
9589 || inst.instruction == T_MNEM_subs,
9592 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9594 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9595 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9598 inst.instruction = (inst.instruction == T_MNEM_add
9600 inst.instruction |= (Rd << 4) | Rs;
9601 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9605 Rn = inst.operands[2].reg;
9606 constraint (inst.operands[2].shifted, _("unshifted register required"));
9608 /* We now have Rd, Rs, and Rn set to registers. */
9609 if (Rd > 7 || Rs > 7 || Rn > 7)
9611 /* Can't do this for SUB. */
9612 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9613 inst.instruction = T_OPCODE_ADD_HI;
9614 inst.instruction |= (Rd & 8) << 4;
9615 inst.instruction |= (Rd & 7);
9617 inst.instruction |= Rn << 3;
9619 inst.instruction |= Rs << 3;
9621 constraint (1, _("dest must overlap one source register"));
9625 inst.instruction = (inst.instruction == T_MNEM_add
9626 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9627 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9637 Rd = inst.operands[0].reg;
9638 reject_bad_reg (Rd);
9640 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9642 /* Defer to section relaxation. */
9643 inst.relax = inst.instruction;
9644 inst.instruction = THUMB_OP16 (inst.instruction);
9645 inst.instruction |= Rd << 4;
9647 else if (unified_syntax && inst.size_req != 2)
9649 /* Generate a 32-bit opcode. */
9650 inst.instruction = THUMB_OP32 (inst.instruction);
9651 inst.instruction |= Rd << 8;
9652 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9653 inst.reloc.pc_rel = 1;
9657 /* Generate a 16-bit opcode. */
9658 inst.instruction = THUMB_OP16 (inst.instruction);
9659 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9660 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9661 inst.reloc.pc_rel = 1;
9663 inst.instruction |= Rd << 4;
9667 /* Arithmetic instructions for which there is just one 16-bit
9668 instruction encoding, and it allows only two low registers.
9669 For maximal compatibility with ARM syntax, we allow three register
9670 operands even when Thumb-32 instructions are not available, as long
9671 as the first two are identical. For instance, both "sbc r0,r1" and
9672 "sbc r0,r0,r1" are allowed. */
9678 Rd = inst.operands[0].reg;
9679 Rs = (inst.operands[1].present
9680 ? inst.operands[1].reg /* Rd, Rs, foo */
9681 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9682 Rn = inst.operands[2].reg;
9684 reject_bad_reg (Rd);
9685 reject_bad_reg (Rs);
9686 if (inst.operands[2].isreg)
9687 reject_bad_reg (Rn);
9691 if (!inst.operands[2].isreg)
9693 /* For an immediate, we always generate a 32-bit opcode;
9694 section relaxation will shrink it later if possible. */
9695 inst.instruction = THUMB_OP32 (inst.instruction);
9696 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9697 inst.instruction |= Rd << 8;
9698 inst.instruction |= Rs << 16;
9699 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9705 /* See if we can do this with a 16-bit instruction. */
9706 if (THUMB_SETS_FLAGS (inst.instruction))
9707 narrow = !in_it_block ();
9709 narrow = in_it_block ();
9711 if (Rd > 7 || Rn > 7 || Rs > 7)
9713 if (inst.operands[2].shifted)
9715 if (inst.size_req == 4)
9721 inst.instruction = THUMB_OP16 (inst.instruction);
9722 inst.instruction |= Rd;
9723 inst.instruction |= Rn << 3;
9727 /* If we get here, it can't be done in 16 bits. */
9728 constraint (inst.operands[2].shifted
9729 && inst.operands[2].immisreg,
9730 _("shift must be constant"));
9731 inst.instruction = THUMB_OP32 (inst.instruction);
9732 inst.instruction |= Rd << 8;
9733 inst.instruction |= Rs << 16;
9734 encode_thumb32_shifted_operand (2);
9739 /* On its face this is a lie - the instruction does set the
9740 flags. However, the only supported mnemonic in this mode
9742 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9744 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9745 _("unshifted register required"));
9746 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9747 constraint (Rd != Rs,
9748 _("dest and source1 must be the same register"));
9750 inst.instruction = THUMB_OP16 (inst.instruction);
9751 inst.instruction |= Rd;
9752 inst.instruction |= Rn << 3;
9756 /* Similarly, but for instructions where the arithmetic operation is
9757 commutative, so we can allow either of them to be different from
9758 the destination operand in a 16-bit instruction. For instance, all
9759 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9766 Rd = inst.operands[0].reg;
9767 Rs = (inst.operands[1].present
9768 ? inst.operands[1].reg /* Rd, Rs, foo */
9769 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9770 Rn = inst.operands[2].reg;
9772 reject_bad_reg (Rd);
9773 reject_bad_reg (Rs);
9774 if (inst.operands[2].isreg)
9775 reject_bad_reg (Rn);
9779 if (!inst.operands[2].isreg)
9781 /* For an immediate, we always generate a 32-bit opcode;
9782 section relaxation will shrink it later if possible. */
9783 inst.instruction = THUMB_OP32 (inst.instruction);
9784 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9785 inst.instruction |= Rd << 8;
9786 inst.instruction |= Rs << 16;
9787 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9793 /* See if we can do this with a 16-bit instruction. */
9794 if (THUMB_SETS_FLAGS (inst.instruction))
9795 narrow = !in_it_block ();
9797 narrow = in_it_block ();
9799 if (Rd > 7 || Rn > 7 || Rs > 7)
9801 if (inst.operands[2].shifted)
9803 if (inst.size_req == 4)
9810 inst.instruction = THUMB_OP16 (inst.instruction);
9811 inst.instruction |= Rd;
9812 inst.instruction |= Rn << 3;
9817 inst.instruction = THUMB_OP16 (inst.instruction);
9818 inst.instruction |= Rd;
9819 inst.instruction |= Rs << 3;
9824 /* If we get here, it can't be done in 16 bits. */
9825 constraint (inst.operands[2].shifted
9826 && inst.operands[2].immisreg,
9827 _("shift must be constant"));
9828 inst.instruction = THUMB_OP32 (inst.instruction);
9829 inst.instruction |= Rd << 8;
9830 inst.instruction |= Rs << 16;
9831 encode_thumb32_shifted_operand (2);
9836 /* On its face this is a lie - the instruction does set the
9837 flags. However, the only supported mnemonic in this mode
9839 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9841 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9842 _("unshifted register required"));
9843 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9845 inst.instruction = THUMB_OP16 (inst.instruction);
9846 inst.instruction |= Rd;
9849 inst.instruction |= Rn << 3;
9851 inst.instruction |= Rs << 3;
9853 constraint (1, _("dest must overlap one source register"));
9860 if (inst.operands[0].present)
9862 constraint ((inst.instruction & 0xf0) != 0x40
9863 && inst.operands[0].imm > 0xf
9864 && inst.operands[0].imm < 0x0,
9865 _("bad barrier type"));
9866 inst.instruction |= inst.operands[0].imm;
9869 inst.instruction |= 0xf;
9876 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9877 constraint (msb > 32, _("bit-field extends past end of register"));
9878 /* The instruction encoding stores the LSB and MSB,
9879 not the LSB and width. */
9880 Rd = inst.operands[0].reg;
9881 reject_bad_reg (Rd);
9882 inst.instruction |= Rd << 8;
9883 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9884 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9885 inst.instruction |= msb - 1;
9894 Rd = inst.operands[0].reg;
9895 reject_bad_reg (Rd);
9897 /* #0 in second position is alternative syntax for bfc, which is
9898 the same instruction but with REG_PC in the Rm field. */
9899 if (!inst.operands[1].isreg)
9903 Rn = inst.operands[1].reg;
9904 reject_bad_reg (Rn);
9907 msb = inst.operands[2].imm + inst.operands[3].imm;
9908 constraint (msb > 32, _("bit-field extends past end of register"));
9909 /* The instruction encoding stores the LSB and MSB,
9910 not the LSB and width. */
9911 inst.instruction |= Rd << 8;
9912 inst.instruction |= Rn << 16;
9913 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9914 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9915 inst.instruction |= msb - 1;
9923 Rd = inst.operands[0].reg;
9924 Rn = inst.operands[1].reg;
9926 reject_bad_reg (Rd);
9927 reject_bad_reg (Rn);
9929 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9930 _("bit-field extends past end of register"));
9931 inst.instruction |= Rd << 8;
9932 inst.instruction |= Rn << 16;
9933 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9934 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9935 inst.instruction |= inst.operands[3].imm - 1;
9938 /* ARM V5 Thumb BLX (argument parse)
9939 BLX <target_addr> which is BLX(1)
9940 BLX <Rm> which is BLX(2)
9941 Unfortunately, there are two different opcodes for this mnemonic.
9942 So, the insns[].value is not used, and the code here zaps values
9943 into inst.instruction.
9945 ??? How to take advantage of the additional two bits of displacement
9946 available in Thumb32 mode? Need new relocation? */
9951 set_it_insn_type_last ();
9953 if (inst.operands[0].isreg)
9955 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9956 /* We have a register, so this is BLX(2). */
9957 inst.instruction |= inst.operands[0].reg << 3;
9961 /* No register. This must be BLX(1). */
9962 inst.instruction = 0xf000e800;
9963 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9975 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9979 /* Conditional branches inside IT blocks are encoded as unconditional
9986 if (cond != COND_ALWAYS)
9987 opcode = T_MNEM_bcond;
9989 opcode = inst.instruction;
9992 && (inst.size_req == 4
9993 || (inst.size_req != 2
9994 && (inst.operands[0].hasreloc
9995 || inst.reloc.exp.X_op == O_constant))))
9997 inst.instruction = THUMB_OP32(opcode);
9998 if (cond == COND_ALWAYS)
9999 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10002 gas_assert (cond != 0xF);
10003 inst.instruction |= cond << 22;
10004 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10009 inst.instruction = THUMB_OP16(opcode);
10010 if (cond == COND_ALWAYS)
10011 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10014 inst.instruction |= cond << 8;
10015 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10017 /* Allow section relaxation. */
10018 if (unified_syntax && inst.size_req != 2)
10019 inst.relax = opcode;
10021 inst.reloc.type = reloc;
10022 inst.reloc.pc_rel = 1;
10028 constraint (inst.cond != COND_ALWAYS,
10029 _("instruction is always unconditional"));
10030 if (inst.operands[0].present)
10032 constraint (inst.operands[0].imm > 255,
10033 _("immediate value out of range"));
10034 inst.instruction |= inst.operands[0].imm;
10035 set_it_insn_type (NEUTRAL_IT_INSN);
10040 do_t_branch23 (void)
10042 set_it_insn_type_last ();
10043 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10045 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10046 this file. We used to simply ignore the PLT reloc type here --
10047 the branch encoding is now needed to deal with TLSCALL relocs.
10048 So if we see a PLT reloc now, put it back to how it used to be to
10049 keep the preexisting behaviour. */
10050 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10051 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10053 #if defined(OBJ_COFF)
10054 /* If the destination of the branch is a defined symbol which does not have
10055 the THUMB_FUNC attribute, then we must be calling a function which has
10056 the (interfacearm) attribute. We look for the Thumb entry point to that
10057 function and change the branch to refer to that function instead. */
10058 if ( inst.reloc.exp.X_op == O_symbol
10059 && inst.reloc.exp.X_add_symbol != NULL
10060 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10061 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10062 inst.reloc.exp.X_add_symbol =
10063 find_real_start (inst.reloc.exp.X_add_symbol);
10070 set_it_insn_type_last ();
10071 inst.instruction |= inst.operands[0].reg << 3;
10072 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10073 should cause the alignment to be checked once it is known. This is
10074 because BX PC only works if the instruction is word aligned. */
10082 set_it_insn_type_last ();
10083 Rm = inst.operands[0].reg;
10084 reject_bad_reg (Rm);
10085 inst.instruction |= Rm << 16;
10094 Rd = inst.operands[0].reg;
10095 Rm = inst.operands[1].reg;
10097 reject_bad_reg (Rd);
10098 reject_bad_reg (Rm);
10100 inst.instruction |= Rd << 8;
10101 inst.instruction |= Rm << 16;
10102 inst.instruction |= Rm;
10108 set_it_insn_type (OUTSIDE_IT_INSN);
10109 inst.instruction |= inst.operands[0].imm;
10115 set_it_insn_type (OUTSIDE_IT_INSN);
10117 && (inst.operands[1].present || inst.size_req == 4)
10118 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10120 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10121 inst.instruction = 0xf3af8000;
10122 inst.instruction |= imod << 9;
10123 inst.instruction |= inst.operands[0].imm << 5;
10124 if (inst.operands[1].present)
10125 inst.instruction |= 0x100 | inst.operands[1].imm;
10129 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10130 && (inst.operands[0].imm & 4),
10131 _("selected processor does not support 'A' form "
10132 "of this instruction"));
10133 constraint (inst.operands[1].present || inst.size_req == 4,
10134 _("Thumb does not support the 2-argument "
10135 "form of this instruction"));
10136 inst.instruction |= inst.operands[0].imm;
10140 /* THUMB CPY instruction (argument parse). */
10145 if (inst.size_req == 4)
10147 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10148 inst.instruction |= inst.operands[0].reg << 8;
10149 inst.instruction |= inst.operands[1].reg;
10153 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10154 inst.instruction |= (inst.operands[0].reg & 0x7);
10155 inst.instruction |= inst.operands[1].reg << 3;
10162 set_it_insn_type (OUTSIDE_IT_INSN);
10163 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10164 inst.instruction |= inst.operands[0].reg;
10165 inst.reloc.pc_rel = 1;
10166 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10172 inst.instruction |= inst.operands[0].imm;
10178 unsigned Rd, Rn, Rm;
10180 Rd = inst.operands[0].reg;
10181 Rn = (inst.operands[1].present
10182 ? inst.operands[1].reg : Rd);
10183 Rm = inst.operands[2].reg;
10185 reject_bad_reg (Rd);
10186 reject_bad_reg (Rn);
10187 reject_bad_reg (Rm);
10189 inst.instruction |= Rd << 8;
10190 inst.instruction |= Rn << 16;
10191 inst.instruction |= Rm;
10197 if (unified_syntax && inst.size_req == 4)
10198 inst.instruction = THUMB_OP32 (inst.instruction);
10200 inst.instruction = THUMB_OP16 (inst.instruction);
10206 unsigned int cond = inst.operands[0].imm;
10208 set_it_insn_type (IT_INSN);
10209 now_it.mask = (inst.instruction & 0xf) | 0x10;
10212 /* If the condition is a negative condition, invert the mask. */
10213 if ((cond & 0x1) == 0x0)
10215 unsigned int mask = inst.instruction & 0x000f;
10217 if ((mask & 0x7) == 0)
10218 /* no conversion needed */;
10219 else if ((mask & 0x3) == 0)
10221 else if ((mask & 0x1) == 0)
10226 inst.instruction &= 0xfff0;
10227 inst.instruction |= mask;
10230 inst.instruction |= cond << 4;
10233 /* Helper function used for both push/pop and ldm/stm. */
10235 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10239 load = (inst.instruction & (1 << 20)) != 0;
10241 if (mask & (1 << 13))
10242 inst.error = _("SP not allowed in register list");
10244 if ((mask & (1 << base)) != 0
10246 inst.error = _("having the base register in the register list when "
10247 "using write back is UNPREDICTABLE");
10251 if (mask & (1 << 15))
10253 if (mask & (1 << 14))
10254 inst.error = _("LR and PC should not both be in register list");
10256 set_it_insn_type_last ();
10261 if (mask & (1 << 15))
10262 inst.error = _("PC not allowed in register list");
10265 if ((mask & (mask - 1)) == 0)
10267 /* Single register transfers implemented as str/ldr. */
10270 if (inst.instruction & (1 << 23))
10271 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10273 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10277 if (inst.instruction & (1 << 23))
10278 inst.instruction = 0x00800000; /* ia -> [base] */
10280 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10283 inst.instruction |= 0xf8400000;
10285 inst.instruction |= 0x00100000;
10287 mask = ffs (mask) - 1;
10290 else if (writeback)
10291 inst.instruction |= WRITE_BACK;
10293 inst.instruction |= mask;
10294 inst.instruction |= base << 16;
10300 /* This really doesn't seem worth it. */
10301 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10302 _("expression too complex"));
10303 constraint (inst.operands[1].writeback,
10304 _("Thumb load/store multiple does not support {reglist}^"));
10306 if (unified_syntax)
10308 bfd_boolean narrow;
10312 /* See if we can use a 16-bit instruction. */
10313 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10314 && inst.size_req != 4
10315 && !(inst.operands[1].imm & ~0xff))
10317 mask = 1 << inst.operands[0].reg;
10319 if (inst.operands[0].reg <= 7)
10321 if (inst.instruction == T_MNEM_stmia
10322 ? inst.operands[0].writeback
10323 : (inst.operands[0].writeback
10324 == !(inst.operands[1].imm & mask)))
10326 if (inst.instruction == T_MNEM_stmia
10327 && (inst.operands[1].imm & mask)
10328 && (inst.operands[1].imm & (mask - 1)))
10329 as_warn (_("value stored for r%d is UNKNOWN"),
10330 inst.operands[0].reg);
10332 inst.instruction = THUMB_OP16 (inst.instruction);
10333 inst.instruction |= inst.operands[0].reg << 8;
10334 inst.instruction |= inst.operands[1].imm;
10337 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10339 /* This means 1 register in reg list one of 3 situations:
10340 1. Instruction is stmia, but without writeback.
10341 2. lmdia without writeback, but with Rn not in
10343 3. ldmia with writeback, but with Rn in reglist.
10344 Case 3 is UNPREDICTABLE behaviour, so we handle
10345 case 1 and 2 which can be converted into a 16-bit
10346 str or ldr. The SP cases are handled below. */
10347 unsigned long opcode;
10348 /* First, record an error for Case 3. */
10349 if (inst.operands[1].imm & mask
10350 && inst.operands[0].writeback)
10352 _("having the base register in the register list when "
10353 "using write back is UNPREDICTABLE");
10355 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10357 inst.instruction = THUMB_OP16 (opcode);
10358 inst.instruction |= inst.operands[0].reg << 3;
10359 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10363 else if (inst.operands[0] .reg == REG_SP)
10365 if (inst.operands[0].writeback)
10368 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10369 ? T_MNEM_push : T_MNEM_pop);
10370 inst.instruction |= inst.operands[1].imm;
10373 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10376 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10377 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10378 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10386 if (inst.instruction < 0xffff)
10387 inst.instruction = THUMB_OP32 (inst.instruction);
10389 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10390 inst.operands[0].writeback);
10395 constraint (inst.operands[0].reg > 7
10396 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10397 constraint (inst.instruction != T_MNEM_ldmia
10398 && inst.instruction != T_MNEM_stmia,
10399 _("Thumb-2 instruction only valid in unified syntax"));
10400 if (inst.instruction == T_MNEM_stmia)
10402 if (!inst.operands[0].writeback)
10403 as_warn (_("this instruction will write back the base register"));
10404 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10405 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10406 as_warn (_("value stored for r%d is UNKNOWN"),
10407 inst.operands[0].reg);
10411 if (!inst.operands[0].writeback
10412 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10413 as_warn (_("this instruction will write back the base register"));
10414 else if (inst.operands[0].writeback
10415 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10416 as_warn (_("this instruction will not write back the base register"));
10419 inst.instruction = THUMB_OP16 (inst.instruction);
10420 inst.instruction |= inst.operands[0].reg << 8;
10421 inst.instruction |= inst.operands[1].imm;
10428 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10429 || inst.operands[1].postind || inst.operands[1].writeback
10430 || inst.operands[1].immisreg || inst.operands[1].shifted
10431 || inst.operands[1].negative,
10434 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10436 inst.instruction |= inst.operands[0].reg << 12;
10437 inst.instruction |= inst.operands[1].reg << 16;
10438 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10444 if (!inst.operands[1].present)
10446 constraint (inst.operands[0].reg == REG_LR,
10447 _("r14 not allowed as first register "
10448 "when second register is omitted"));
10449 inst.operands[1].reg = inst.operands[0].reg + 1;
10451 constraint (inst.operands[0].reg == inst.operands[1].reg,
10454 inst.instruction |= inst.operands[0].reg << 12;
10455 inst.instruction |= inst.operands[1].reg << 8;
10456 inst.instruction |= inst.operands[2].reg << 16;
10462 unsigned long opcode;
10465 if (inst.operands[0].isreg
10466 && !inst.operands[0].preind
10467 && inst.operands[0].reg == REG_PC)
10468 set_it_insn_type_last ();
10470 opcode = inst.instruction;
10471 if (unified_syntax)
10473 if (!inst.operands[1].isreg)
10475 if (opcode <= 0xffff)
10476 inst.instruction = THUMB_OP32 (opcode);
10477 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10480 if (inst.operands[1].isreg
10481 && !inst.operands[1].writeback
10482 && !inst.operands[1].shifted && !inst.operands[1].postind
10483 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10484 && opcode <= 0xffff
10485 && inst.size_req != 4)
10487 /* Insn may have a 16-bit form. */
10488 Rn = inst.operands[1].reg;
10489 if (inst.operands[1].immisreg)
10491 inst.instruction = THUMB_OP16 (opcode);
10493 if (Rn <= 7 && inst.operands[1].imm <= 7)
10495 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10496 reject_bad_reg (inst.operands[1].imm);
10498 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10499 && opcode != T_MNEM_ldrsb)
10500 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10501 || (Rn == REG_SP && opcode == T_MNEM_str))
10508 if (inst.reloc.pc_rel)
10509 opcode = T_MNEM_ldr_pc2;
10511 opcode = T_MNEM_ldr_pc;
10515 if (opcode == T_MNEM_ldr)
10516 opcode = T_MNEM_ldr_sp;
10518 opcode = T_MNEM_str_sp;
10520 inst.instruction = inst.operands[0].reg << 8;
10524 inst.instruction = inst.operands[0].reg;
10525 inst.instruction |= inst.operands[1].reg << 3;
10527 inst.instruction |= THUMB_OP16 (opcode);
10528 if (inst.size_req == 2)
10529 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10531 inst.relax = opcode;
10535 /* Definitely a 32-bit variant. */
10537 /* Warning for Erratum 752419. */
10538 if (opcode == T_MNEM_ldr
10539 && inst.operands[0].reg == REG_SP
10540 && inst.operands[1].writeback == 1
10541 && !inst.operands[1].immisreg)
10543 if (no_cpu_selected ()
10544 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10545 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10546 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10547 as_warn (_("This instruction may be unpredictable "
10548 "if executed on M-profile cores "
10549 "with interrupts enabled."));
10552 /* Do some validations regarding addressing modes. */
10553 if (inst.operands[1].immisreg)
10554 reject_bad_reg (inst.operands[1].imm);
10556 constraint (inst.operands[1].writeback == 1
10557 && inst.operands[0].reg == inst.operands[1].reg,
10560 inst.instruction = THUMB_OP32 (opcode);
10561 inst.instruction |= inst.operands[0].reg << 12;
10562 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10563 check_ldr_r15_aligned ();
10567 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10569 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10571 /* Only [Rn,Rm] is acceptable. */
10572 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10573 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10574 || inst.operands[1].postind || inst.operands[1].shifted
10575 || inst.operands[1].negative,
10576 _("Thumb does not support this addressing mode"));
10577 inst.instruction = THUMB_OP16 (inst.instruction);
10581 inst.instruction = THUMB_OP16 (inst.instruction);
10582 if (!inst.operands[1].isreg)
10583 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10586 constraint (!inst.operands[1].preind
10587 || inst.operands[1].shifted
10588 || inst.operands[1].writeback,
10589 _("Thumb does not support this addressing mode"));
10590 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10592 constraint (inst.instruction & 0x0600,
10593 _("byte or halfword not valid for base register"));
10594 constraint (inst.operands[1].reg == REG_PC
10595 && !(inst.instruction & THUMB_LOAD_BIT),
10596 _("r15 based store not allowed"));
10597 constraint (inst.operands[1].immisreg,
10598 _("invalid base register for register offset"));
10600 if (inst.operands[1].reg == REG_PC)
10601 inst.instruction = T_OPCODE_LDR_PC;
10602 else if (inst.instruction & THUMB_LOAD_BIT)
10603 inst.instruction = T_OPCODE_LDR_SP;
10605 inst.instruction = T_OPCODE_STR_SP;
10607 inst.instruction |= inst.operands[0].reg << 8;
10608 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10612 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10613 if (!inst.operands[1].immisreg)
10615 /* Immediate offset. */
10616 inst.instruction |= inst.operands[0].reg;
10617 inst.instruction |= inst.operands[1].reg << 3;
10618 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10622 /* Register offset. */
10623 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10624 constraint (inst.operands[1].negative,
10625 _("Thumb does not support this addressing mode"));
10628 switch (inst.instruction)
10630 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10631 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10632 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10633 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10634 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10635 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10636 case 0x5600 /* ldrsb */:
10637 case 0x5e00 /* ldrsh */: break;
10641 inst.instruction |= inst.operands[0].reg;
10642 inst.instruction |= inst.operands[1].reg << 3;
10643 inst.instruction |= inst.operands[1].imm << 6;
10649 if (!inst.operands[1].present)
10651 inst.operands[1].reg = inst.operands[0].reg + 1;
10652 constraint (inst.operands[0].reg == REG_LR,
10653 _("r14 not allowed here"));
10655 inst.instruction |= inst.operands[0].reg << 12;
10656 inst.instruction |= inst.operands[1].reg << 8;
10657 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10663 inst.instruction |= inst.operands[0].reg << 12;
10664 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10670 unsigned Rd, Rn, Rm, Ra;
10672 Rd = inst.operands[0].reg;
10673 Rn = inst.operands[1].reg;
10674 Rm = inst.operands[2].reg;
10675 Ra = inst.operands[3].reg;
10677 reject_bad_reg (Rd);
10678 reject_bad_reg (Rn);
10679 reject_bad_reg (Rm);
10680 reject_bad_reg (Ra);
10682 inst.instruction |= Rd << 8;
10683 inst.instruction |= Rn << 16;
10684 inst.instruction |= Rm;
10685 inst.instruction |= Ra << 12;
10691 unsigned RdLo, RdHi, Rn, Rm;
10693 RdLo = inst.operands[0].reg;
10694 RdHi = inst.operands[1].reg;
10695 Rn = inst.operands[2].reg;
10696 Rm = inst.operands[3].reg;
10698 reject_bad_reg (RdLo);
10699 reject_bad_reg (RdHi);
10700 reject_bad_reg (Rn);
10701 reject_bad_reg (Rm);
10703 inst.instruction |= RdLo << 12;
10704 inst.instruction |= RdHi << 8;
10705 inst.instruction |= Rn << 16;
10706 inst.instruction |= Rm;
10710 do_t_mov_cmp (void)
10714 Rn = inst.operands[0].reg;
10715 Rm = inst.operands[1].reg;
10718 set_it_insn_type_last ();
10720 if (unified_syntax)
10722 int r0off = (inst.instruction == T_MNEM_mov
10723 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10724 unsigned long opcode;
10725 bfd_boolean narrow;
10726 bfd_boolean low_regs;
10728 low_regs = (Rn <= 7 && Rm <= 7);
10729 opcode = inst.instruction;
10730 if (in_it_block ())
10731 narrow = opcode != T_MNEM_movs;
10733 narrow = opcode != T_MNEM_movs || low_regs;
10734 if (inst.size_req == 4
10735 || inst.operands[1].shifted)
10738 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10739 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10740 && !inst.operands[1].shifted
10744 inst.instruction = T2_SUBS_PC_LR;
10748 if (opcode == T_MNEM_cmp)
10750 constraint (Rn == REG_PC, BAD_PC);
10753 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10755 warn_deprecated_sp (Rm);
10756 /* R15 was documented as a valid choice for Rm in ARMv6,
10757 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10758 tools reject R15, so we do too. */
10759 constraint (Rm == REG_PC, BAD_PC);
10762 reject_bad_reg (Rm);
10764 else if (opcode == T_MNEM_mov
10765 || opcode == T_MNEM_movs)
10767 if (inst.operands[1].isreg)
10769 if (opcode == T_MNEM_movs)
10771 reject_bad_reg (Rn);
10772 reject_bad_reg (Rm);
10776 /* This is mov.n. */
10777 if ((Rn == REG_SP || Rn == REG_PC)
10778 && (Rm == REG_SP || Rm == REG_PC))
10780 as_warn (_("Use of r%u as a source register is "
10781 "deprecated when r%u is the destination "
10782 "register."), Rm, Rn);
10787 /* This is mov.w. */
10788 constraint (Rn == REG_PC, BAD_PC);
10789 constraint (Rm == REG_PC, BAD_PC);
10790 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10794 reject_bad_reg (Rn);
10797 if (!inst.operands[1].isreg)
10799 /* Immediate operand. */
10800 if (!in_it_block () && opcode == T_MNEM_mov)
10802 if (low_regs && narrow)
10804 inst.instruction = THUMB_OP16 (opcode);
10805 inst.instruction |= Rn << 8;
10806 if (inst.size_req == 2)
10807 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10809 inst.relax = opcode;
10813 inst.instruction = THUMB_OP32 (inst.instruction);
10814 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10815 inst.instruction |= Rn << r0off;
10816 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10819 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10820 && (inst.instruction == T_MNEM_mov
10821 || inst.instruction == T_MNEM_movs))
10823 /* Register shifts are encoded as separate shift instructions. */
10824 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10826 if (in_it_block ())
10831 if (inst.size_req == 4)
10834 if (!low_regs || inst.operands[1].imm > 7)
10840 switch (inst.operands[1].shift_kind)
10843 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10846 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10849 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10852 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10858 inst.instruction = opcode;
10861 inst.instruction |= Rn;
10862 inst.instruction |= inst.operands[1].imm << 3;
10867 inst.instruction |= CONDS_BIT;
10869 inst.instruction |= Rn << 8;
10870 inst.instruction |= Rm << 16;
10871 inst.instruction |= inst.operands[1].imm;
10876 /* Some mov with immediate shift have narrow variants.
10877 Register shifts are handled above. */
10878 if (low_regs && inst.operands[1].shifted
10879 && (inst.instruction == T_MNEM_mov
10880 || inst.instruction == T_MNEM_movs))
10882 if (in_it_block ())
10883 narrow = (inst.instruction == T_MNEM_mov);
10885 narrow = (inst.instruction == T_MNEM_movs);
10890 switch (inst.operands[1].shift_kind)
10892 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10893 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10894 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10895 default: narrow = FALSE; break;
10901 inst.instruction |= Rn;
10902 inst.instruction |= Rm << 3;
10903 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10907 inst.instruction = THUMB_OP32 (inst.instruction);
10908 inst.instruction |= Rn << r0off;
10909 encode_thumb32_shifted_operand (1);
10913 switch (inst.instruction)
10916 /* In v4t or v5t a move of two lowregs produces unpredictable
10917 results. Don't allow this. */
10920 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
10921 "MOV Rd, Rs with two low registers is not "
10922 "permitted on this architecture");
10923 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
10927 inst.instruction = T_OPCODE_MOV_HR;
10928 inst.instruction |= (Rn & 0x8) << 4;
10929 inst.instruction |= (Rn & 0x7);
10930 inst.instruction |= Rm << 3;
10934 /* We know we have low registers at this point.
10935 Generate LSLS Rd, Rs, #0. */
10936 inst.instruction = T_OPCODE_LSL_I;
10937 inst.instruction |= Rn;
10938 inst.instruction |= Rm << 3;
10944 inst.instruction = T_OPCODE_CMP_LR;
10945 inst.instruction |= Rn;
10946 inst.instruction |= Rm << 3;
10950 inst.instruction = T_OPCODE_CMP_HR;
10951 inst.instruction |= (Rn & 0x8) << 4;
10952 inst.instruction |= (Rn & 0x7);
10953 inst.instruction |= Rm << 3;
10960 inst.instruction = THUMB_OP16 (inst.instruction);
10962 /* PR 10443: Do not silently ignore shifted operands. */
10963 constraint (inst.operands[1].shifted,
10964 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10966 if (inst.operands[1].isreg)
10968 if (Rn < 8 && Rm < 8)
10970 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10971 since a MOV instruction produces unpredictable results. */
10972 if (inst.instruction == T_OPCODE_MOV_I8)
10973 inst.instruction = T_OPCODE_ADD_I3;
10975 inst.instruction = T_OPCODE_CMP_LR;
10977 inst.instruction |= Rn;
10978 inst.instruction |= Rm << 3;
10982 if (inst.instruction == T_OPCODE_MOV_I8)
10983 inst.instruction = T_OPCODE_MOV_HR;
10985 inst.instruction = T_OPCODE_CMP_HR;
10991 constraint (Rn > 7,
10992 _("only lo regs allowed with immediate"));
10993 inst.instruction |= Rn << 8;
10994 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11005 top = (inst.instruction & 0x00800000) != 0;
11006 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11008 constraint (top, _(":lower16: not allowed this instruction"));
11009 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11011 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11013 constraint (!top, _(":upper16: not allowed this instruction"));
11014 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11017 Rd = inst.operands[0].reg;
11018 reject_bad_reg (Rd);
11020 inst.instruction |= Rd << 8;
11021 if (inst.reloc.type == BFD_RELOC_UNUSED)
11023 imm = inst.reloc.exp.X_add_number;
11024 inst.instruction |= (imm & 0xf000) << 4;
11025 inst.instruction |= (imm & 0x0800) << 15;
11026 inst.instruction |= (imm & 0x0700) << 4;
11027 inst.instruction |= (imm & 0x00ff);
11032 do_t_mvn_tst (void)
11036 Rn = inst.operands[0].reg;
11037 Rm = inst.operands[1].reg;
11039 if (inst.instruction == T_MNEM_cmp
11040 || inst.instruction == T_MNEM_cmn)
11041 constraint (Rn == REG_PC, BAD_PC);
11043 reject_bad_reg (Rn);
11044 reject_bad_reg (Rm);
11046 if (unified_syntax)
11048 int r0off = (inst.instruction == T_MNEM_mvn
11049 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11050 bfd_boolean narrow;
11052 if (inst.size_req == 4
11053 || inst.instruction > 0xffff
11054 || inst.operands[1].shifted
11055 || Rn > 7 || Rm > 7)
11057 else if (inst.instruction == T_MNEM_cmn)
11059 else if (THUMB_SETS_FLAGS (inst.instruction))
11060 narrow = !in_it_block ();
11062 narrow = in_it_block ();
11064 if (!inst.operands[1].isreg)
11066 /* For an immediate, we always generate a 32-bit opcode;
11067 section relaxation will shrink it later if possible. */
11068 if (inst.instruction < 0xffff)
11069 inst.instruction = THUMB_OP32 (inst.instruction);
11070 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11071 inst.instruction |= Rn << r0off;
11072 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11076 /* See if we can do this with a 16-bit instruction. */
11079 inst.instruction = THUMB_OP16 (inst.instruction);
11080 inst.instruction |= Rn;
11081 inst.instruction |= Rm << 3;
11085 constraint (inst.operands[1].shifted
11086 && inst.operands[1].immisreg,
11087 _("shift must be constant"));
11088 if (inst.instruction < 0xffff)
11089 inst.instruction = THUMB_OP32 (inst.instruction);
11090 inst.instruction |= Rn << r0off;
11091 encode_thumb32_shifted_operand (1);
11097 constraint (inst.instruction > 0xffff
11098 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11099 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11100 _("unshifted register required"));
11101 constraint (Rn > 7 || Rm > 7,
11104 inst.instruction = THUMB_OP16 (inst.instruction);
11105 inst.instruction |= Rn;
11106 inst.instruction |= Rm << 3;
11115 if (do_vfp_nsyn_mrs () == SUCCESS)
11118 Rd = inst.operands[0].reg;
11119 reject_bad_reg (Rd);
11120 inst.instruction |= Rd << 8;
11122 if (inst.operands[1].isreg)
11124 unsigned br = inst.operands[1].reg;
11125 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11126 as_bad (_("bad register for mrs"));
11128 inst.instruction |= br & (0xf << 16);
11129 inst.instruction |= (br & 0x300) >> 4;
11130 inst.instruction |= (br & SPSR_BIT) >> 2;
11134 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11136 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11137 constraint (flags != 0, _("selected processor does not support "
11138 "requested special purpose register"));
11140 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11142 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11143 _("'APSR', 'CPSR' or 'SPSR' expected"));
11145 inst.instruction |= (flags & SPSR_BIT) >> 2;
11146 inst.instruction |= inst.operands[1].imm & 0xff;
11147 inst.instruction |= 0xf0000;
11157 if (do_vfp_nsyn_msr () == SUCCESS)
11160 constraint (!inst.operands[1].isreg,
11161 _("Thumb encoding does not support an immediate here"));
11163 if (inst.operands[0].isreg)
11164 flags = (int)(inst.operands[0].reg);
11166 flags = inst.operands[0].imm;
11168 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11170 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11172 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11173 && (bits & ~(PSR_s | PSR_f)) != 0)
11174 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11176 _("selected processor does not support requested special "
11177 "purpose register"));
11180 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11181 "requested special purpose register"));
11183 Rn = inst.operands[1].reg;
11184 reject_bad_reg (Rn);
11186 inst.instruction |= (flags & SPSR_BIT) >> 2;
11187 inst.instruction |= (flags & 0xf0000) >> 8;
11188 inst.instruction |= (flags & 0x300) >> 4;
11189 inst.instruction |= (flags & 0xff);
11190 inst.instruction |= Rn << 16;
11196 bfd_boolean narrow;
11197 unsigned Rd, Rn, Rm;
11199 if (!inst.operands[2].present)
11200 inst.operands[2].reg = inst.operands[0].reg;
11202 Rd = inst.operands[0].reg;
11203 Rn = inst.operands[1].reg;
11204 Rm = inst.operands[2].reg;
11206 if (unified_syntax)
11208 if (inst.size_req == 4
11214 else if (inst.instruction == T_MNEM_muls)
11215 narrow = !in_it_block ();
11217 narrow = in_it_block ();
11221 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11222 constraint (Rn > 7 || Rm > 7,
11229 /* 16-bit MULS/Conditional MUL. */
11230 inst.instruction = THUMB_OP16 (inst.instruction);
11231 inst.instruction |= Rd;
11234 inst.instruction |= Rm << 3;
11236 inst.instruction |= Rn << 3;
11238 constraint (1, _("dest must overlap one source register"));
11242 constraint (inst.instruction != T_MNEM_mul,
11243 _("Thumb-2 MUL must not set flags"));
11245 inst.instruction = THUMB_OP32 (inst.instruction);
11246 inst.instruction |= Rd << 8;
11247 inst.instruction |= Rn << 16;
11248 inst.instruction |= Rm << 0;
11250 reject_bad_reg (Rd);
11251 reject_bad_reg (Rn);
11252 reject_bad_reg (Rm);
11259 unsigned RdLo, RdHi, Rn, Rm;
11261 RdLo = inst.operands[0].reg;
11262 RdHi = inst.operands[1].reg;
11263 Rn = inst.operands[2].reg;
11264 Rm = inst.operands[3].reg;
11266 reject_bad_reg (RdLo);
11267 reject_bad_reg (RdHi);
11268 reject_bad_reg (Rn);
11269 reject_bad_reg (Rm);
11271 inst.instruction |= RdLo << 12;
11272 inst.instruction |= RdHi << 8;
11273 inst.instruction |= Rn << 16;
11274 inst.instruction |= Rm;
11277 as_tsktsk (_("rdhi and rdlo must be different"));
11283 set_it_insn_type (NEUTRAL_IT_INSN);
11285 if (unified_syntax)
11287 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11289 inst.instruction = THUMB_OP32 (inst.instruction);
11290 inst.instruction |= inst.operands[0].imm;
11294 /* PR9722: Check for Thumb2 availability before
11295 generating a thumb2 nop instruction. */
11296 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11298 inst.instruction = THUMB_OP16 (inst.instruction);
11299 inst.instruction |= inst.operands[0].imm << 4;
11302 inst.instruction = 0x46c0;
11307 constraint (inst.operands[0].present,
11308 _("Thumb does not support NOP with hints"));
11309 inst.instruction = 0x46c0;
11316 if (unified_syntax)
11318 bfd_boolean narrow;
11320 if (THUMB_SETS_FLAGS (inst.instruction))
11321 narrow = !in_it_block ();
11323 narrow = in_it_block ();
11324 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11326 if (inst.size_req == 4)
11331 inst.instruction = THUMB_OP32 (inst.instruction);
11332 inst.instruction |= inst.operands[0].reg << 8;
11333 inst.instruction |= inst.operands[1].reg << 16;
11337 inst.instruction = THUMB_OP16 (inst.instruction);
11338 inst.instruction |= inst.operands[0].reg;
11339 inst.instruction |= inst.operands[1].reg << 3;
11344 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11346 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11348 inst.instruction = THUMB_OP16 (inst.instruction);
11349 inst.instruction |= inst.operands[0].reg;
11350 inst.instruction |= inst.operands[1].reg << 3;
11359 Rd = inst.operands[0].reg;
11360 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11362 reject_bad_reg (Rd);
11363 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11364 reject_bad_reg (Rn);
11366 inst.instruction |= Rd << 8;
11367 inst.instruction |= Rn << 16;
11369 if (!inst.operands[2].isreg)
11371 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11372 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11378 Rm = inst.operands[2].reg;
11379 reject_bad_reg (Rm);
11381 constraint (inst.operands[2].shifted
11382 && inst.operands[2].immisreg,
11383 _("shift must be constant"));
11384 encode_thumb32_shifted_operand (2);
11391 unsigned Rd, Rn, Rm;
11393 Rd = inst.operands[0].reg;
11394 Rn = inst.operands[1].reg;
11395 Rm = inst.operands[2].reg;
11397 reject_bad_reg (Rd);
11398 reject_bad_reg (Rn);
11399 reject_bad_reg (Rm);
11401 inst.instruction |= Rd << 8;
11402 inst.instruction |= Rn << 16;
11403 inst.instruction |= Rm;
11404 if (inst.operands[3].present)
11406 unsigned int val = inst.reloc.exp.X_add_number;
11407 constraint (inst.reloc.exp.X_op != O_constant,
11408 _("expression too complex"));
11409 inst.instruction |= (val & 0x1c) << 10;
11410 inst.instruction |= (val & 0x03) << 6;
11417 if (!inst.operands[3].present)
11421 inst.instruction &= ~0x00000020;
11423 /* PR 10168. Swap the Rm and Rn registers. */
11424 Rtmp = inst.operands[1].reg;
11425 inst.operands[1].reg = inst.operands[2].reg;
11426 inst.operands[2].reg = Rtmp;
11434 if (inst.operands[0].immisreg)
11435 reject_bad_reg (inst.operands[0].imm);
11437 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11441 do_t_push_pop (void)
11445 constraint (inst.operands[0].writeback,
11446 _("push/pop do not support {reglist}^"));
11447 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11448 _("expression too complex"));
11450 mask = inst.operands[0].imm;
11451 if ((mask & ~0xff) == 0)
11452 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11453 else if ((inst.instruction == T_MNEM_push
11454 && (mask & ~0xff) == 1 << REG_LR)
11455 || (inst.instruction == T_MNEM_pop
11456 && (mask & ~0xff) == 1 << REG_PC))
11458 inst.instruction = THUMB_OP16 (inst.instruction);
11459 inst.instruction |= THUMB_PP_PC_LR;
11460 inst.instruction |= mask & 0xff;
11462 else if (unified_syntax)
11464 inst.instruction = THUMB_OP32 (inst.instruction);
11465 encode_thumb2_ldmstm (13, mask, TRUE);
11469 inst.error = _("invalid register list to push/pop instruction");
11479 Rd = inst.operands[0].reg;
11480 Rm = inst.operands[1].reg;
11482 reject_bad_reg (Rd);
11483 reject_bad_reg (Rm);
11485 inst.instruction |= Rd << 8;
11486 inst.instruction |= Rm << 16;
11487 inst.instruction |= Rm;
11495 Rd = inst.operands[0].reg;
11496 Rm = inst.operands[1].reg;
11498 reject_bad_reg (Rd);
11499 reject_bad_reg (Rm);
11501 if (Rd <= 7 && Rm <= 7
11502 && inst.size_req != 4)
11504 inst.instruction = THUMB_OP16 (inst.instruction);
11505 inst.instruction |= Rd;
11506 inst.instruction |= Rm << 3;
11508 else if (unified_syntax)
11510 inst.instruction = THUMB_OP32 (inst.instruction);
11511 inst.instruction |= Rd << 8;
11512 inst.instruction |= Rm << 16;
11513 inst.instruction |= Rm;
11516 inst.error = BAD_HIREG;
11524 Rd = inst.operands[0].reg;
11525 Rm = inst.operands[1].reg;
11527 reject_bad_reg (Rd);
11528 reject_bad_reg (Rm);
11530 inst.instruction |= Rd << 8;
11531 inst.instruction |= Rm;
11539 Rd = inst.operands[0].reg;
11540 Rs = (inst.operands[1].present
11541 ? inst.operands[1].reg /* Rd, Rs, foo */
11542 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11544 reject_bad_reg (Rd);
11545 reject_bad_reg (Rs);
11546 if (inst.operands[2].isreg)
11547 reject_bad_reg (inst.operands[2].reg);
11549 inst.instruction |= Rd << 8;
11550 inst.instruction |= Rs << 16;
11551 if (!inst.operands[2].isreg)
11553 bfd_boolean narrow;
11555 if ((inst.instruction & 0x00100000) != 0)
11556 narrow = !in_it_block ();
11558 narrow = in_it_block ();
11560 if (Rd > 7 || Rs > 7)
11563 if (inst.size_req == 4 || !unified_syntax)
11566 if (inst.reloc.exp.X_op != O_constant
11567 || inst.reloc.exp.X_add_number != 0)
11570 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11571 relaxation, but it doesn't seem worth the hassle. */
11574 inst.reloc.type = BFD_RELOC_UNUSED;
11575 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11576 inst.instruction |= Rs << 3;
11577 inst.instruction |= Rd;
11581 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11582 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11586 encode_thumb32_shifted_operand (2);
11592 set_it_insn_type (OUTSIDE_IT_INSN);
11593 if (inst.operands[0].imm)
11594 inst.instruction |= 0x8;
11600 if (!inst.operands[1].present)
11601 inst.operands[1].reg = inst.operands[0].reg;
11603 if (unified_syntax)
11605 bfd_boolean narrow;
11608 switch (inst.instruction)
11611 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11613 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11615 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11617 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11621 if (THUMB_SETS_FLAGS (inst.instruction))
11622 narrow = !in_it_block ();
11624 narrow = in_it_block ();
11625 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11627 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11629 if (inst.operands[2].isreg
11630 && (inst.operands[1].reg != inst.operands[0].reg
11631 || inst.operands[2].reg > 7))
11633 if (inst.size_req == 4)
11636 reject_bad_reg (inst.operands[0].reg);
11637 reject_bad_reg (inst.operands[1].reg);
11641 if (inst.operands[2].isreg)
11643 reject_bad_reg (inst.operands[2].reg);
11644 inst.instruction = THUMB_OP32 (inst.instruction);
11645 inst.instruction |= inst.operands[0].reg << 8;
11646 inst.instruction |= inst.operands[1].reg << 16;
11647 inst.instruction |= inst.operands[2].reg;
11649 /* PR 12854: Error on extraneous shifts. */
11650 constraint (inst.operands[2].shifted,
11651 _("extraneous shift as part of operand to shift insn"));
11655 inst.operands[1].shifted = 1;
11656 inst.operands[1].shift_kind = shift_kind;
11657 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11658 ? T_MNEM_movs : T_MNEM_mov);
11659 inst.instruction |= inst.operands[0].reg << 8;
11660 encode_thumb32_shifted_operand (1);
11661 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11662 inst.reloc.type = BFD_RELOC_UNUSED;
11667 if (inst.operands[2].isreg)
11669 switch (shift_kind)
11671 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11672 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11673 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11674 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11678 inst.instruction |= inst.operands[0].reg;
11679 inst.instruction |= inst.operands[2].reg << 3;
11681 /* PR 12854: Error on extraneous shifts. */
11682 constraint (inst.operands[2].shifted,
11683 _("extraneous shift as part of operand to shift insn"));
11687 switch (shift_kind)
11689 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11690 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11691 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11694 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11695 inst.instruction |= inst.operands[0].reg;
11696 inst.instruction |= inst.operands[1].reg << 3;
11702 constraint (inst.operands[0].reg > 7
11703 || inst.operands[1].reg > 7, BAD_HIREG);
11704 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11706 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11708 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11709 constraint (inst.operands[0].reg != inst.operands[1].reg,
11710 _("source1 and dest must be same register"));
11712 switch (inst.instruction)
11714 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11715 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11716 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11717 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11721 inst.instruction |= inst.operands[0].reg;
11722 inst.instruction |= inst.operands[2].reg << 3;
11724 /* PR 12854: Error on extraneous shifts. */
11725 constraint (inst.operands[2].shifted,
11726 _("extraneous shift as part of operand to shift insn"));
11730 switch (inst.instruction)
11732 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11733 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11734 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11735 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11738 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11739 inst.instruction |= inst.operands[0].reg;
11740 inst.instruction |= inst.operands[1].reg << 3;
11748 unsigned Rd, Rn, Rm;
11750 Rd = inst.operands[0].reg;
11751 Rn = inst.operands[1].reg;
11752 Rm = inst.operands[2].reg;
11754 reject_bad_reg (Rd);
11755 reject_bad_reg (Rn);
11756 reject_bad_reg (Rm);
11758 inst.instruction |= Rd << 8;
11759 inst.instruction |= Rn << 16;
11760 inst.instruction |= Rm;
11766 unsigned Rd, Rn, Rm;
11768 Rd = inst.operands[0].reg;
11769 Rm = inst.operands[1].reg;
11770 Rn = inst.operands[2].reg;
11772 reject_bad_reg (Rd);
11773 reject_bad_reg (Rn);
11774 reject_bad_reg (Rm);
11776 inst.instruction |= Rd << 8;
11777 inst.instruction |= Rn << 16;
11778 inst.instruction |= Rm;
11784 unsigned int value = inst.reloc.exp.X_add_number;
11785 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11786 _("SMC is not permitted on this architecture"));
11787 constraint (inst.reloc.exp.X_op != O_constant,
11788 _("expression too complex"));
11789 inst.reloc.type = BFD_RELOC_UNUSED;
11790 inst.instruction |= (value & 0xf000) >> 12;
11791 inst.instruction |= (value & 0x0ff0);
11792 inst.instruction |= (value & 0x000f) << 16;
11798 unsigned int value = inst.reloc.exp.X_add_number;
11800 inst.reloc.type = BFD_RELOC_UNUSED;
11801 inst.instruction |= (value & 0x0fff);
11802 inst.instruction |= (value & 0xf000) << 4;
11806 do_t_ssat_usat (int bias)
11810 Rd = inst.operands[0].reg;
11811 Rn = inst.operands[2].reg;
11813 reject_bad_reg (Rd);
11814 reject_bad_reg (Rn);
11816 inst.instruction |= Rd << 8;
11817 inst.instruction |= inst.operands[1].imm - bias;
11818 inst.instruction |= Rn << 16;
11820 if (inst.operands[3].present)
11822 offsetT shift_amount = inst.reloc.exp.X_add_number;
11824 inst.reloc.type = BFD_RELOC_UNUSED;
11826 constraint (inst.reloc.exp.X_op != O_constant,
11827 _("expression too complex"));
11829 if (shift_amount != 0)
11831 constraint (shift_amount > 31,
11832 _("shift expression is too large"));
11834 if (inst.operands[3].shift_kind == SHIFT_ASR)
11835 inst.instruction |= 0x00200000; /* sh bit. */
11837 inst.instruction |= (shift_amount & 0x1c) << 10;
11838 inst.instruction |= (shift_amount & 0x03) << 6;
11846 do_t_ssat_usat (1);
11854 Rd = inst.operands[0].reg;
11855 Rn = inst.operands[2].reg;
11857 reject_bad_reg (Rd);
11858 reject_bad_reg (Rn);
11860 inst.instruction |= Rd << 8;
11861 inst.instruction |= inst.operands[1].imm - 1;
11862 inst.instruction |= Rn << 16;
11868 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11869 || inst.operands[2].postind || inst.operands[2].writeback
11870 || inst.operands[2].immisreg || inst.operands[2].shifted
11871 || inst.operands[2].negative,
11874 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11876 inst.instruction |= inst.operands[0].reg << 8;
11877 inst.instruction |= inst.operands[1].reg << 12;
11878 inst.instruction |= inst.operands[2].reg << 16;
11879 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11885 if (!inst.operands[2].present)
11886 inst.operands[2].reg = inst.operands[1].reg + 1;
11888 constraint (inst.operands[0].reg == inst.operands[1].reg
11889 || inst.operands[0].reg == inst.operands[2].reg
11890 || inst.operands[0].reg == inst.operands[3].reg,
11893 inst.instruction |= inst.operands[0].reg;
11894 inst.instruction |= inst.operands[1].reg << 12;
11895 inst.instruction |= inst.operands[2].reg << 8;
11896 inst.instruction |= inst.operands[3].reg << 16;
11902 unsigned Rd, Rn, Rm;
11904 Rd = inst.operands[0].reg;
11905 Rn = inst.operands[1].reg;
11906 Rm = inst.operands[2].reg;
11908 reject_bad_reg (Rd);
11909 reject_bad_reg (Rn);
11910 reject_bad_reg (Rm);
11912 inst.instruction |= Rd << 8;
11913 inst.instruction |= Rn << 16;
11914 inst.instruction |= Rm;
11915 inst.instruction |= inst.operands[3].imm << 4;
11923 Rd = inst.operands[0].reg;
11924 Rm = inst.operands[1].reg;
11926 reject_bad_reg (Rd);
11927 reject_bad_reg (Rm);
11929 if (inst.instruction <= 0xffff
11930 && inst.size_req != 4
11931 && Rd <= 7 && Rm <= 7
11932 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11934 inst.instruction = THUMB_OP16 (inst.instruction);
11935 inst.instruction |= Rd;
11936 inst.instruction |= Rm << 3;
11938 else if (unified_syntax)
11940 if (inst.instruction <= 0xffff)
11941 inst.instruction = THUMB_OP32 (inst.instruction);
11942 inst.instruction |= Rd << 8;
11943 inst.instruction |= Rm;
11944 inst.instruction |= inst.operands[2].imm << 4;
11948 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11949 _("Thumb encoding does not support rotation"));
11950 constraint (1, BAD_HIREG);
11957 /* We have to do the following check manually as ARM_EXT_OS only applies
11959 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11961 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11962 /* This only applies to the v6m howver, not later architectures. */
11963 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11964 as_bad (_("SVC is not permitted on this architecture"));
11965 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11968 inst.reloc.type = BFD_RELOC_ARM_SWI;
11977 half = (inst.instruction & 0x10) != 0;
11978 set_it_insn_type_last ();
11979 constraint (inst.operands[0].immisreg,
11980 _("instruction requires register index"));
11982 Rn = inst.operands[0].reg;
11983 Rm = inst.operands[0].imm;
11985 constraint (Rn == REG_SP, BAD_SP);
11986 reject_bad_reg (Rm);
11988 constraint (!half && inst.operands[0].shifted,
11989 _("instruction does not allow shifted index"));
11990 inst.instruction |= (Rn << 16) | Rm;
11996 do_t_ssat_usat (0);
12004 Rd = inst.operands[0].reg;
12005 Rn = inst.operands[2].reg;
12007 reject_bad_reg (Rd);
12008 reject_bad_reg (Rn);
12010 inst.instruction |= Rd << 8;
12011 inst.instruction |= inst.operands[1].imm;
12012 inst.instruction |= Rn << 16;
12015 /* Neon instruction encoder helpers. */
12017 /* Encodings for the different types for various Neon opcodes. */
12019 /* An "invalid" code for the following tables. */
12022 struct neon_tab_entry
12025 unsigned float_or_poly;
12026 unsigned scalar_or_imm;
12029 /* Map overloaded Neon opcodes to their respective encodings. */
12030 #define NEON_ENC_TAB \
12031 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12032 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12033 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12034 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12035 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12036 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12037 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12038 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12039 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12040 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12041 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12042 /* Register variants of the following two instructions are encoded as
12043 vcge / vcgt with the operands reversed. */ \
12044 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12045 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12046 X(vfma, N_INV, 0x0000c10, N_INV), \
12047 X(vfms, N_INV, 0x0200c10, N_INV), \
12048 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12049 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12050 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12051 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12052 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12053 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12054 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12055 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12056 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12057 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12058 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12059 X(vshl, 0x0000400, N_INV, 0x0800510), \
12060 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12061 X(vand, 0x0000110, N_INV, 0x0800030), \
12062 X(vbic, 0x0100110, N_INV, 0x0800030), \
12063 X(veor, 0x1000110, N_INV, N_INV), \
12064 X(vorn, 0x0300110, N_INV, 0x0800010), \
12065 X(vorr, 0x0200110, N_INV, 0x0800010), \
12066 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12067 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12068 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12069 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12070 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12071 X(vst1, 0x0000000, 0x0800000, N_INV), \
12072 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12073 X(vst2, 0x0000100, 0x0800100, N_INV), \
12074 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12075 X(vst3, 0x0000200, 0x0800200, N_INV), \
12076 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12077 X(vst4, 0x0000300, 0x0800300, N_INV), \
12078 X(vmovn, 0x1b20200, N_INV, N_INV), \
12079 X(vtrn, 0x1b20080, N_INV, N_INV), \
12080 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12081 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12082 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12083 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12084 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12085 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12086 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12087 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12088 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12089 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12090 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12094 #define X(OPC,I,F,S) N_MNEM_##OPC
12099 static const struct neon_tab_entry neon_enc_tab[] =
12101 #define X(OPC,I,F,S) { (I), (F), (S) }
12106 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12107 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12108 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12109 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12110 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12111 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12112 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12113 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12114 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12115 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12116 #define NEON_ENC_SINGLE_(X) \
12117 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12118 #define NEON_ENC_DOUBLE_(X) \
12119 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12121 #define NEON_ENCODE(type, inst) \
12124 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12125 inst.is_neon = 1; \
12129 #define check_neon_suffixes \
12132 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12134 as_bad (_("invalid neon suffix for non neon instruction")); \
12140 /* Define shapes for instruction operands. The following mnemonic characters
12141 are used in this table:
12143 F - VFP S<n> register
12144 D - Neon D<n> register
12145 Q - Neon Q<n> register
12149 L - D<n> register list
12151 This table is used to generate various data:
12152 - enumerations of the form NS_DDR to be used as arguments to
12154 - a table classifying shapes into single, double, quad, mixed.
12155 - a table used to drive neon_select_shape. */
12157 #define NEON_SHAPE_DEF \
12158 X(3, (D, D, D), DOUBLE), \
12159 X(3, (Q, Q, Q), QUAD), \
12160 X(3, (D, D, I), DOUBLE), \
12161 X(3, (Q, Q, I), QUAD), \
12162 X(3, (D, D, S), DOUBLE), \
12163 X(3, (Q, Q, S), QUAD), \
12164 X(2, (D, D), DOUBLE), \
12165 X(2, (Q, Q), QUAD), \
12166 X(2, (D, S), DOUBLE), \
12167 X(2, (Q, S), QUAD), \
12168 X(2, (D, R), DOUBLE), \
12169 X(2, (Q, R), QUAD), \
12170 X(2, (D, I), DOUBLE), \
12171 X(2, (Q, I), QUAD), \
12172 X(3, (D, L, D), DOUBLE), \
12173 X(2, (D, Q), MIXED), \
12174 X(2, (Q, D), MIXED), \
12175 X(3, (D, Q, I), MIXED), \
12176 X(3, (Q, D, I), MIXED), \
12177 X(3, (Q, D, D), MIXED), \
12178 X(3, (D, Q, Q), MIXED), \
12179 X(3, (Q, Q, D), MIXED), \
12180 X(3, (Q, D, S), MIXED), \
12181 X(3, (D, Q, S), MIXED), \
12182 X(4, (D, D, D, I), DOUBLE), \
12183 X(4, (Q, Q, Q, I), QUAD), \
12184 X(2, (F, F), SINGLE), \
12185 X(3, (F, F, F), SINGLE), \
12186 X(2, (F, I), SINGLE), \
12187 X(2, (F, D), MIXED), \
12188 X(2, (D, F), MIXED), \
12189 X(3, (F, F, I), MIXED), \
12190 X(4, (R, R, F, F), SINGLE), \
12191 X(4, (F, F, R, R), SINGLE), \
12192 X(3, (D, R, R), DOUBLE), \
12193 X(3, (R, R, D), DOUBLE), \
12194 X(2, (S, R), SINGLE), \
12195 X(2, (R, S), SINGLE), \
12196 X(2, (F, R), SINGLE), \
12197 X(2, (R, F), SINGLE)
12199 #define S2(A,B) NS_##A##B
12200 #define S3(A,B,C) NS_##A##B##C
12201 #define S4(A,B,C,D) NS_##A##B##C##D
12203 #define X(N, L, C) S##N L
12216 enum neon_shape_class
12224 #define X(N, L, C) SC_##C
12226 static enum neon_shape_class neon_shape_class[] =
12244 /* Register widths of above. */
12245 static unsigned neon_shape_el_size[] =
12256 struct neon_shape_info
12259 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12262 #define S2(A,B) { SE_##A, SE_##B }
12263 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12264 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12266 #define X(N, L, C) { N, S##N L }
12268 static struct neon_shape_info neon_shape_tab[] =
12278 /* Bit masks used in type checking given instructions.
12279 'N_EQK' means the type must be the same as (or based on in some way) the key
12280 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12281 set, various other bits can be set as well in order to modify the meaning of
12282 the type constraint. */
12284 enum neon_type_mask
12307 N_KEY = 0x1000000, /* Key element (main type specifier). */
12308 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12309 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12310 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12311 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12312 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12313 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12314 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12315 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12316 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12318 N_MAX_NONSPECIAL = N_F64
12321 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12323 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12324 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12325 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12326 #define N_SUF_32 (N_SU_32 | N_F32)
12327 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12328 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12330 /* Pass this as the first type argument to neon_check_type to ignore types
12332 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12334 /* Select a "shape" for the current instruction (describing register types or
12335 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12336 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12337 function of operand parsing, so this function doesn't need to be called.
12338 Shapes should be listed in order of decreasing length. */
12340 static enum neon_shape
12341 neon_select_shape (enum neon_shape shape, ...)
12344 enum neon_shape first_shape = shape;
12346 /* Fix missing optional operands. FIXME: we don't know at this point how
12347 many arguments we should have, so this makes the assumption that we have
12348 > 1. This is true of all current Neon opcodes, I think, but may not be
12349 true in the future. */
12350 if (!inst.operands[1].present)
12351 inst.operands[1] = inst.operands[0];
12353 va_start (ap, shape);
12355 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12360 for (j = 0; j < neon_shape_tab[shape].els; j++)
12362 if (!inst.operands[j].present)
12368 switch (neon_shape_tab[shape].el[j])
12371 if (!(inst.operands[j].isreg
12372 && inst.operands[j].isvec
12373 && inst.operands[j].issingle
12374 && !inst.operands[j].isquad))
12379 if (!(inst.operands[j].isreg
12380 && inst.operands[j].isvec
12381 && !inst.operands[j].isquad
12382 && !inst.operands[j].issingle))
12387 if (!(inst.operands[j].isreg
12388 && !inst.operands[j].isvec))
12393 if (!(inst.operands[j].isreg
12394 && inst.operands[j].isvec
12395 && inst.operands[j].isquad
12396 && !inst.operands[j].issingle))
12401 if (!(!inst.operands[j].isreg
12402 && !inst.operands[j].isscalar))
12407 if (!(!inst.operands[j].isreg
12408 && inst.operands[j].isscalar))
12424 if (shape == NS_NULL && first_shape != NS_NULL)
12425 first_error (_("invalid instruction shape"));
12430 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12431 means the Q bit should be set). */
12434 neon_quad (enum neon_shape shape)
12436 return neon_shape_class[shape] == SC_QUAD;
12440 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12443 /* Allow modification to be made to types which are constrained to be
12444 based on the key element, based on bits set alongside N_EQK. */
12445 if ((typebits & N_EQK) != 0)
12447 if ((typebits & N_HLF) != 0)
12449 else if ((typebits & N_DBL) != 0)
12451 if ((typebits & N_SGN) != 0)
12452 *g_type = NT_signed;
12453 else if ((typebits & N_UNS) != 0)
12454 *g_type = NT_unsigned;
12455 else if ((typebits & N_INT) != 0)
12456 *g_type = NT_integer;
12457 else if ((typebits & N_FLT) != 0)
12458 *g_type = NT_float;
12459 else if ((typebits & N_SIZ) != 0)
12460 *g_type = NT_untyped;
12464 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12465 operand type, i.e. the single type specified in a Neon instruction when it
12466 is the only one given. */
12468 static struct neon_type_el
12469 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12471 struct neon_type_el dest = *key;
12473 gas_assert ((thisarg & N_EQK) != 0);
12475 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12480 /* Convert Neon type and size into compact bitmask representation. */
12482 static enum neon_type_mask
12483 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12490 case 8: return N_8;
12491 case 16: return N_16;
12492 case 32: return N_32;
12493 case 64: return N_64;
12501 case 8: return N_I8;
12502 case 16: return N_I16;
12503 case 32: return N_I32;
12504 case 64: return N_I64;
12512 case 16: return N_F16;
12513 case 32: return N_F32;
12514 case 64: return N_F64;
12522 case 8: return N_P8;
12523 case 16: return N_P16;
12531 case 8: return N_S8;
12532 case 16: return N_S16;
12533 case 32: return N_S32;
12534 case 64: return N_S64;
12542 case 8: return N_U8;
12543 case 16: return N_U16;
12544 case 32: return N_U32;
12545 case 64: return N_U64;
12556 /* Convert compact Neon bitmask type representation to a type and size. Only
12557 handles the case where a single bit is set in the mask. */
12560 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12561 enum neon_type_mask mask)
12563 if ((mask & N_EQK) != 0)
12566 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12568 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12570 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12572 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12577 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12579 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12580 *type = NT_unsigned;
12581 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12582 *type = NT_integer;
12583 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12584 *type = NT_untyped;
12585 else if ((mask & (N_P8 | N_P16)) != 0)
12587 else if ((mask & (N_F32 | N_F64)) != 0)
12595 /* Modify a bitmask of allowed types. This is only needed for type
12599 modify_types_allowed (unsigned allowed, unsigned mods)
12602 enum neon_el_type type;
12608 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12610 if (el_type_of_type_chk (&type, &size,
12611 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12613 neon_modify_type_size (mods, &type, &size);
12614 destmask |= type_chk_of_el_type (type, size);
12621 /* Check type and return type classification.
12622 The manual states (paraphrase): If one datatype is given, it indicates the
12624 - the second operand, if there is one
12625 - the operand, if there is no second operand
12626 - the result, if there are no operands.
12627 This isn't quite good enough though, so we use a concept of a "key" datatype
12628 which is set on a per-instruction basis, which is the one which matters when
12629 only one data type is written.
12630 Note: this function has side-effects (e.g. filling in missing operands). All
12631 Neon instructions should call it before performing bit encoding. */
12633 static struct neon_type_el
12634 neon_check_type (unsigned els, enum neon_shape ns, ...)
12637 unsigned i, pass, key_el = 0;
12638 unsigned types[NEON_MAX_TYPE_ELS];
12639 enum neon_el_type k_type = NT_invtype;
12640 unsigned k_size = -1u;
12641 struct neon_type_el badtype = {NT_invtype, -1};
12642 unsigned key_allowed = 0;
12644 /* Optional registers in Neon instructions are always (not) in operand 1.
12645 Fill in the missing operand here, if it was omitted. */
12646 if (els > 1 && !inst.operands[1].present)
12647 inst.operands[1] = inst.operands[0];
12649 /* Suck up all the varargs. */
12651 for (i = 0; i < els; i++)
12653 unsigned thisarg = va_arg (ap, unsigned);
12654 if (thisarg == N_IGNORE_TYPE)
12659 types[i] = thisarg;
12660 if ((thisarg & N_KEY) != 0)
12665 if (inst.vectype.elems > 0)
12666 for (i = 0; i < els; i++)
12667 if (inst.operands[i].vectype.type != NT_invtype)
12669 first_error (_("types specified in both the mnemonic and operands"));
12673 /* Duplicate inst.vectype elements here as necessary.
12674 FIXME: No idea if this is exactly the same as the ARM assembler,
12675 particularly when an insn takes one register and one non-register
12677 if (inst.vectype.elems == 1 && els > 1)
12680 inst.vectype.elems = els;
12681 inst.vectype.el[key_el] = inst.vectype.el[0];
12682 for (j = 0; j < els; j++)
12684 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12687 else if (inst.vectype.elems == 0 && els > 0)
12690 /* No types were given after the mnemonic, so look for types specified
12691 after each operand. We allow some flexibility here; as long as the
12692 "key" operand has a type, we can infer the others. */
12693 for (j = 0; j < els; j++)
12694 if (inst.operands[j].vectype.type != NT_invtype)
12695 inst.vectype.el[j] = inst.operands[j].vectype;
12697 if (inst.operands[key_el].vectype.type != NT_invtype)
12699 for (j = 0; j < els; j++)
12700 if (inst.operands[j].vectype.type == NT_invtype)
12701 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12706 first_error (_("operand types can't be inferred"));
12710 else if (inst.vectype.elems != els)
12712 first_error (_("type specifier has the wrong number of parts"));
12716 for (pass = 0; pass < 2; pass++)
12718 for (i = 0; i < els; i++)
12720 unsigned thisarg = types[i];
12721 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12722 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12723 enum neon_el_type g_type = inst.vectype.el[i].type;
12724 unsigned g_size = inst.vectype.el[i].size;
12726 /* Decay more-specific signed & unsigned types to sign-insensitive
12727 integer types if sign-specific variants are unavailable. */
12728 if ((g_type == NT_signed || g_type == NT_unsigned)
12729 && (types_allowed & N_SU_ALL) == 0)
12730 g_type = NT_integer;
12732 /* If only untyped args are allowed, decay any more specific types to
12733 them. Some instructions only care about signs for some element
12734 sizes, so handle that properly. */
12735 if ((g_size == 8 && (types_allowed & N_8) != 0)
12736 || (g_size == 16 && (types_allowed & N_16) != 0)
12737 || (g_size == 32 && (types_allowed & N_32) != 0)
12738 || (g_size == 64 && (types_allowed & N_64) != 0))
12739 g_type = NT_untyped;
12743 if ((thisarg & N_KEY) != 0)
12747 key_allowed = thisarg & ~N_KEY;
12752 if ((thisarg & N_VFP) != 0)
12754 enum neon_shape_el regshape;
12755 unsigned regwidth, match;
12757 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12760 first_error (_("invalid instruction shape"));
12763 regshape = neon_shape_tab[ns].el[i];
12764 regwidth = neon_shape_el_size[regshape];
12766 /* In VFP mode, operands must match register widths. If we
12767 have a key operand, use its width, else use the width of
12768 the current operand. */
12774 if (regwidth != match)
12776 first_error (_("operand size must match register width"));
12781 if ((thisarg & N_EQK) == 0)
12783 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12785 if ((given_type & types_allowed) == 0)
12787 first_error (_("bad type in Neon instruction"));
12793 enum neon_el_type mod_k_type = k_type;
12794 unsigned mod_k_size = k_size;
12795 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12796 if (g_type != mod_k_type || g_size != mod_k_size)
12798 first_error (_("inconsistent types in Neon instruction"));
12806 return inst.vectype.el[key_el];
12809 /* Neon-style VFP instruction forwarding. */
12811 /* Thumb VFP instructions have 0xE in the condition field. */
12814 do_vfp_cond_or_thumb (void)
12819 inst.instruction |= 0xe0000000;
12821 inst.instruction |= inst.cond << 28;
12824 /* Look up and encode a simple mnemonic, for use as a helper function for the
12825 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12826 etc. It is assumed that operand parsing has already been done, and that the
12827 operands are in the form expected by the given opcode (this isn't necessarily
12828 the same as the form in which they were parsed, hence some massaging must
12829 take place before this function is called).
12830 Checks current arch version against that in the looked-up opcode. */
12833 do_vfp_nsyn_opcode (const char *opname)
12835 const struct asm_opcode *opcode;
12837 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12842 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12843 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12850 inst.instruction = opcode->tvalue;
12851 opcode->tencode ();
12855 inst.instruction = (inst.cond << 28) | opcode->avalue;
12856 opcode->aencode ();
12861 do_vfp_nsyn_add_sub (enum neon_shape rs)
12863 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12868 do_vfp_nsyn_opcode ("fadds");
12870 do_vfp_nsyn_opcode ("fsubs");
12875 do_vfp_nsyn_opcode ("faddd");
12877 do_vfp_nsyn_opcode ("fsubd");
12881 /* Check operand types to see if this is a VFP instruction, and if so call
12885 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12887 enum neon_shape rs;
12888 struct neon_type_el et;
12893 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12894 et = neon_check_type (2, rs,
12895 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12899 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12900 et = neon_check_type (3, rs,
12901 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12908 if (et.type != NT_invtype)
12919 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12921 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12926 do_vfp_nsyn_opcode ("fmacs");
12928 do_vfp_nsyn_opcode ("fnmacs");
12933 do_vfp_nsyn_opcode ("fmacd");
12935 do_vfp_nsyn_opcode ("fnmacd");
12940 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12942 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12947 do_vfp_nsyn_opcode ("ffmas");
12949 do_vfp_nsyn_opcode ("ffnmas");
12954 do_vfp_nsyn_opcode ("ffmad");
12956 do_vfp_nsyn_opcode ("ffnmad");
12961 do_vfp_nsyn_mul (enum neon_shape rs)
12964 do_vfp_nsyn_opcode ("fmuls");
12966 do_vfp_nsyn_opcode ("fmuld");
12970 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12972 int is_neg = (inst.instruction & 0x80) != 0;
12973 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12978 do_vfp_nsyn_opcode ("fnegs");
12980 do_vfp_nsyn_opcode ("fabss");
12985 do_vfp_nsyn_opcode ("fnegd");
12987 do_vfp_nsyn_opcode ("fabsd");
12991 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12992 insns belong to Neon, and are handled elsewhere. */
12995 do_vfp_nsyn_ldm_stm (int is_dbmode)
12997 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13001 do_vfp_nsyn_opcode ("fldmdbs");
13003 do_vfp_nsyn_opcode ("fldmias");
13008 do_vfp_nsyn_opcode ("fstmdbs");
13010 do_vfp_nsyn_opcode ("fstmias");
13015 do_vfp_nsyn_sqrt (void)
13017 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13018 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13021 do_vfp_nsyn_opcode ("fsqrts");
13023 do_vfp_nsyn_opcode ("fsqrtd");
13027 do_vfp_nsyn_div (void)
13029 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13030 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13031 N_F32 | N_F64 | N_KEY | N_VFP);
13034 do_vfp_nsyn_opcode ("fdivs");
13036 do_vfp_nsyn_opcode ("fdivd");
13040 do_vfp_nsyn_nmul (void)
13042 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13043 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13044 N_F32 | N_F64 | N_KEY | N_VFP);
13048 NEON_ENCODE (SINGLE, inst);
13049 do_vfp_sp_dyadic ();
13053 NEON_ENCODE (DOUBLE, inst);
13054 do_vfp_dp_rd_rn_rm ();
13056 do_vfp_cond_or_thumb ();
13060 do_vfp_nsyn_cmp (void)
13062 if (inst.operands[1].isreg)
13064 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13065 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13069 NEON_ENCODE (SINGLE, inst);
13070 do_vfp_sp_monadic ();
13074 NEON_ENCODE (DOUBLE, inst);
13075 do_vfp_dp_rd_rm ();
13080 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13081 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13083 switch (inst.instruction & 0x0fffffff)
13086 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13089 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13097 NEON_ENCODE (SINGLE, inst);
13098 do_vfp_sp_compare_z ();
13102 NEON_ENCODE (DOUBLE, inst);
13106 do_vfp_cond_or_thumb ();
13110 nsyn_insert_sp (void)
13112 inst.operands[1] = inst.operands[0];
13113 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13114 inst.operands[0].reg = REG_SP;
13115 inst.operands[0].isreg = 1;
13116 inst.operands[0].writeback = 1;
13117 inst.operands[0].present = 1;
13121 do_vfp_nsyn_push (void)
13124 if (inst.operands[1].issingle)
13125 do_vfp_nsyn_opcode ("fstmdbs");
13127 do_vfp_nsyn_opcode ("fstmdbd");
13131 do_vfp_nsyn_pop (void)
13134 if (inst.operands[1].issingle)
13135 do_vfp_nsyn_opcode ("fldmias");
13137 do_vfp_nsyn_opcode ("fldmiad");
13140 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13141 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13144 neon_dp_fixup (struct arm_it* insn)
13146 unsigned int i = insn->instruction;
13151 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13162 insn->instruction = i;
13165 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13169 neon_logbits (unsigned x)
13171 return ffs (x) - 4;
13174 #define LOW4(R) ((R) & 0xf)
13175 #define HI1(R) (((R) >> 4) & 1)
13177 /* Encode insns with bit pattern:
13179 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13180 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13182 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13183 different meaning for some instruction. */
13186 neon_three_same (int isquad, int ubit, int size)
13188 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13189 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13190 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13191 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13192 inst.instruction |= LOW4 (inst.operands[2].reg);
13193 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13194 inst.instruction |= (isquad != 0) << 6;
13195 inst.instruction |= (ubit != 0) << 24;
13197 inst.instruction |= neon_logbits (size) << 20;
13199 neon_dp_fixup (&inst);
13202 /* Encode instructions of the form:
13204 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13205 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13207 Don't write size if SIZE == -1. */
13210 neon_two_same (int qbit, int ubit, int size)
13212 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13213 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13214 inst.instruction |= LOW4 (inst.operands[1].reg);
13215 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13216 inst.instruction |= (qbit != 0) << 6;
13217 inst.instruction |= (ubit != 0) << 24;
13220 inst.instruction |= neon_logbits (size) << 18;
13222 neon_dp_fixup (&inst);
13225 /* Neon instruction encoders, in approximate order of appearance. */
13228 do_neon_dyadic_i_su (void)
13230 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13231 struct neon_type_el et = neon_check_type (3, rs,
13232 N_EQK, N_EQK, N_SU_32 | N_KEY);
13233 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13237 do_neon_dyadic_i64_su (void)
13239 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13240 struct neon_type_el et = neon_check_type (3, rs,
13241 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13242 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13246 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13249 unsigned size = et.size >> 3;
13250 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13251 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13252 inst.instruction |= LOW4 (inst.operands[1].reg);
13253 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13254 inst.instruction |= (isquad != 0) << 6;
13255 inst.instruction |= immbits << 16;
13256 inst.instruction |= (size >> 3) << 7;
13257 inst.instruction |= (size & 0x7) << 19;
13259 inst.instruction |= (uval != 0) << 24;
13261 neon_dp_fixup (&inst);
13265 do_neon_shl_imm (void)
13267 if (!inst.operands[2].isreg)
13269 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13270 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13271 NEON_ENCODE (IMMED, inst);
13272 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13276 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13277 struct neon_type_el et = neon_check_type (3, rs,
13278 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13281 /* VSHL/VQSHL 3-register variants have syntax such as:
13283 whereas other 3-register operations encoded by neon_three_same have
13286 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13288 tmp = inst.operands[2].reg;
13289 inst.operands[2].reg = inst.operands[1].reg;
13290 inst.operands[1].reg = tmp;
13291 NEON_ENCODE (INTEGER, inst);
13292 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13297 do_neon_qshl_imm (void)
13299 if (!inst.operands[2].isreg)
13301 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13302 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13304 NEON_ENCODE (IMMED, inst);
13305 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13306 inst.operands[2].imm);
13310 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13311 struct neon_type_el et = neon_check_type (3, rs,
13312 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13315 /* See note in do_neon_shl_imm. */
13316 tmp = inst.operands[2].reg;
13317 inst.operands[2].reg = inst.operands[1].reg;
13318 inst.operands[1].reg = tmp;
13319 NEON_ENCODE (INTEGER, inst);
13320 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13325 do_neon_rshl (void)
13327 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13328 struct neon_type_el et = neon_check_type (3, rs,
13329 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13332 tmp = inst.operands[2].reg;
13333 inst.operands[2].reg = inst.operands[1].reg;
13334 inst.operands[1].reg = tmp;
13335 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13339 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13341 /* Handle .I8 pseudo-instructions. */
13344 /* Unfortunately, this will make everything apart from zero out-of-range.
13345 FIXME is this the intended semantics? There doesn't seem much point in
13346 accepting .I8 if so. */
13347 immediate |= immediate << 8;
13353 if (immediate == (immediate & 0x000000ff))
13355 *immbits = immediate;
13358 else if (immediate == (immediate & 0x0000ff00))
13360 *immbits = immediate >> 8;
13363 else if (immediate == (immediate & 0x00ff0000))
13365 *immbits = immediate >> 16;
13368 else if (immediate == (immediate & 0xff000000))
13370 *immbits = immediate >> 24;
13373 if ((immediate & 0xffff) != (immediate >> 16))
13374 goto bad_immediate;
13375 immediate &= 0xffff;
13378 if (immediate == (immediate & 0x000000ff))
13380 *immbits = immediate;
13383 else if (immediate == (immediate & 0x0000ff00))
13385 *immbits = immediate >> 8;
13390 first_error (_("immediate value out of range"));
13394 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13398 neon_bits_same_in_bytes (unsigned imm)
13400 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13401 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13402 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13403 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13406 /* For immediate of above form, return 0bABCD. */
13409 neon_squash_bits (unsigned imm)
13411 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13412 | ((imm & 0x01000000) >> 21);
13415 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13418 neon_qfloat_bits (unsigned imm)
13420 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13423 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13424 the instruction. *OP is passed as the initial value of the op field, and
13425 may be set to a different value depending on the constant (i.e.
13426 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13427 MVN). If the immediate looks like a repeated pattern then also
13428 try smaller element sizes. */
13431 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13432 unsigned *immbits, int *op, int size,
13433 enum neon_el_type type)
13435 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13437 if (type == NT_float && !float_p)
13440 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13442 if (size != 32 || *op == 1)
13444 *immbits = neon_qfloat_bits (immlo);
13450 if (neon_bits_same_in_bytes (immhi)
13451 && neon_bits_same_in_bytes (immlo))
13455 *immbits = (neon_squash_bits (immhi) << 4)
13456 | neon_squash_bits (immlo);
13461 if (immhi != immlo)
13467 if (immlo == (immlo & 0x000000ff))
13472 else if (immlo == (immlo & 0x0000ff00))
13474 *immbits = immlo >> 8;
13477 else if (immlo == (immlo & 0x00ff0000))
13479 *immbits = immlo >> 16;
13482 else if (immlo == (immlo & 0xff000000))
13484 *immbits = immlo >> 24;
13487 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13489 *immbits = (immlo >> 8) & 0xff;
13492 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13494 *immbits = (immlo >> 16) & 0xff;
13498 if ((immlo & 0xffff) != (immlo >> 16))
13505 if (immlo == (immlo & 0x000000ff))
13510 else if (immlo == (immlo & 0x0000ff00))
13512 *immbits = immlo >> 8;
13516 if ((immlo & 0xff) != (immlo >> 8))
13521 if (immlo == (immlo & 0x000000ff))
13523 /* Don't allow MVN with 8-bit immediate. */
13533 /* Write immediate bits [7:0] to the following locations:
13535 |28/24|23 19|18 16|15 4|3 0|
13536 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13538 This function is used by VMOV/VMVN/VORR/VBIC. */
13541 neon_write_immbits (unsigned immbits)
13543 inst.instruction |= immbits & 0xf;
13544 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13545 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13548 /* Invert low-order SIZE bits of XHI:XLO. */
13551 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13553 unsigned immlo = xlo ? *xlo : 0;
13554 unsigned immhi = xhi ? *xhi : 0;
13559 immlo = (~immlo) & 0xff;
13563 immlo = (~immlo) & 0xffff;
13567 immhi = (~immhi) & 0xffffffff;
13568 /* fall through. */
13571 immlo = (~immlo) & 0xffffffff;
13586 do_neon_logic (void)
13588 if (inst.operands[2].present && inst.operands[2].isreg)
13590 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13591 neon_check_type (3, rs, N_IGNORE_TYPE);
13592 /* U bit and size field were set as part of the bitmask. */
13593 NEON_ENCODE (INTEGER, inst);
13594 neon_three_same (neon_quad (rs), 0, -1);
13598 const int three_ops_form = (inst.operands[2].present
13599 && !inst.operands[2].isreg);
13600 const int immoperand = (three_ops_form ? 2 : 1);
13601 enum neon_shape rs = (three_ops_form
13602 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13603 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13604 struct neon_type_el et = neon_check_type (2, rs,
13605 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13606 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13610 if (et.type == NT_invtype)
13613 if (three_ops_form)
13614 constraint (inst.operands[0].reg != inst.operands[1].reg,
13615 _("first and second operands shall be the same register"));
13617 NEON_ENCODE (IMMED, inst);
13619 immbits = inst.operands[immoperand].imm;
13622 /* .i64 is a pseudo-op, so the immediate must be a repeating
13624 if (immbits != (inst.operands[immoperand].regisimm ?
13625 inst.operands[immoperand].reg : 0))
13627 /* Set immbits to an invalid constant. */
13628 immbits = 0xdeadbeef;
13635 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13639 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13643 /* Pseudo-instruction for VBIC. */
13644 neon_invert_size (&immbits, 0, et.size);
13645 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13649 /* Pseudo-instruction for VORR. */
13650 neon_invert_size (&immbits, 0, et.size);
13651 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13661 inst.instruction |= neon_quad (rs) << 6;
13662 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13663 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13664 inst.instruction |= cmode << 8;
13665 neon_write_immbits (immbits);
13667 neon_dp_fixup (&inst);
13672 do_neon_bitfield (void)
13674 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13675 neon_check_type (3, rs, N_IGNORE_TYPE);
13676 neon_three_same (neon_quad (rs), 0, -1);
13680 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13683 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13684 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13686 if (et.type == NT_float)
13688 NEON_ENCODE (FLOAT, inst);
13689 neon_three_same (neon_quad (rs), 0, -1);
13693 NEON_ENCODE (INTEGER, inst);
13694 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13699 do_neon_dyadic_if_su (void)
13701 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13705 do_neon_dyadic_if_su_d (void)
13707 /* This version only allow D registers, but that constraint is enforced during
13708 operand parsing so we don't need to do anything extra here. */
13709 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13713 do_neon_dyadic_if_i_d (void)
13715 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13716 affected if we specify unsigned args. */
13717 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13720 enum vfp_or_neon_is_neon_bits
13723 NEON_CHECK_ARCH = 2
13726 /* Call this function if an instruction which may have belonged to the VFP or
13727 Neon instruction sets, but turned out to be a Neon instruction (due to the
13728 operand types involved, etc.). We have to check and/or fix-up a couple of
13731 - Make sure the user hasn't attempted to make a Neon instruction
13733 - Alter the value in the condition code field if necessary.
13734 - Make sure that the arch supports Neon instructions.
13736 Which of these operations take place depends on bits from enum
13737 vfp_or_neon_is_neon_bits.
13739 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13740 current instruction's condition is COND_ALWAYS, the condition field is
13741 changed to inst.uncond_value. This is necessary because instructions shared
13742 between VFP and Neon may be conditional for the VFP variants only, and the
13743 unconditional Neon version must have, e.g., 0xF in the condition field. */
13746 vfp_or_neon_is_neon (unsigned check)
13748 /* Conditions are always legal in Thumb mode (IT blocks). */
13749 if (!thumb_mode && (check & NEON_CHECK_CC))
13751 if (inst.cond != COND_ALWAYS)
13753 first_error (_(BAD_COND));
13756 if (inst.uncond_value != -1)
13757 inst.instruction |= inst.uncond_value << 28;
13760 if ((check & NEON_CHECK_ARCH)
13761 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13763 first_error (_(BAD_FPU));
13771 do_neon_addsub_if_i (void)
13773 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13776 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13779 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13780 affected if we specify unsigned args. */
13781 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13784 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13786 V<op> A,B (A is operand 0, B is operand 2)
13791 so handle that case specially. */
13794 neon_exchange_operands (void)
13796 void *scratch = alloca (sizeof (inst.operands[0]));
13797 if (inst.operands[1].present)
13799 /* Swap operands[1] and operands[2]. */
13800 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13801 inst.operands[1] = inst.operands[2];
13802 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13806 inst.operands[1] = inst.operands[2];
13807 inst.operands[2] = inst.operands[0];
13812 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13814 if (inst.operands[2].isreg)
13817 neon_exchange_operands ();
13818 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13822 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13823 struct neon_type_el et = neon_check_type (2, rs,
13824 N_EQK | N_SIZ, immtypes | N_KEY);
13826 NEON_ENCODE (IMMED, inst);
13827 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13828 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13829 inst.instruction |= LOW4 (inst.operands[1].reg);
13830 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13831 inst.instruction |= neon_quad (rs) << 6;
13832 inst.instruction |= (et.type == NT_float) << 10;
13833 inst.instruction |= neon_logbits (et.size) << 18;
13835 neon_dp_fixup (&inst);
13842 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13846 do_neon_cmp_inv (void)
13848 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13854 neon_compare (N_IF_32, N_IF_32, FALSE);
13857 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13858 scalars, which are encoded in 5 bits, M : Rm.
13859 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13860 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13864 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13866 unsigned regno = NEON_SCALAR_REG (scalar);
13867 unsigned elno = NEON_SCALAR_INDEX (scalar);
13872 if (regno > 7 || elno > 3)
13874 return regno | (elno << 3);
13877 if (regno > 15 || elno > 1)
13879 return regno | (elno << 4);
13883 first_error (_("scalar out of range for multiply instruction"));
13889 /* Encode multiply / multiply-accumulate scalar instructions. */
13892 neon_mul_mac (struct neon_type_el et, int ubit)
13896 /* Give a more helpful error message if we have an invalid type. */
13897 if (et.type == NT_invtype)
13900 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13901 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13902 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13903 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13904 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13905 inst.instruction |= LOW4 (scalar);
13906 inst.instruction |= HI1 (scalar) << 5;
13907 inst.instruction |= (et.type == NT_float) << 8;
13908 inst.instruction |= neon_logbits (et.size) << 20;
13909 inst.instruction |= (ubit != 0) << 24;
13911 neon_dp_fixup (&inst);
13915 do_neon_mac_maybe_scalar (void)
13917 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13920 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13923 if (inst.operands[2].isscalar)
13925 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13926 struct neon_type_el et = neon_check_type (3, rs,
13927 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13928 NEON_ENCODE (SCALAR, inst);
13929 neon_mul_mac (et, neon_quad (rs));
13933 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13934 affected if we specify unsigned args. */
13935 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13940 do_neon_fmac (void)
13942 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13945 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13948 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13954 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13955 struct neon_type_el et = neon_check_type (3, rs,
13956 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13957 neon_three_same (neon_quad (rs), 0, et.size);
13960 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13961 same types as the MAC equivalents. The polynomial type for this instruction
13962 is encoded the same as the integer type. */
13967 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13970 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13973 if (inst.operands[2].isscalar)
13974 do_neon_mac_maybe_scalar ();
13976 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13980 do_neon_qdmulh (void)
13982 if (inst.operands[2].isscalar)
13984 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13985 struct neon_type_el et = neon_check_type (3, rs,
13986 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13987 NEON_ENCODE (SCALAR, inst);
13988 neon_mul_mac (et, neon_quad (rs));
13992 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13993 struct neon_type_el et = neon_check_type (3, rs,
13994 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
13995 NEON_ENCODE (INTEGER, inst);
13996 /* The U bit (rounding) comes from bit mask. */
13997 neon_three_same (neon_quad (rs), 0, et.size);
14002 do_neon_fcmp_absolute (void)
14004 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14005 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14006 /* Size field comes from bit mask. */
14007 neon_three_same (neon_quad (rs), 1, -1);
14011 do_neon_fcmp_absolute_inv (void)
14013 neon_exchange_operands ();
14014 do_neon_fcmp_absolute ();
14018 do_neon_step (void)
14020 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14021 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14022 neon_three_same (neon_quad (rs), 0, -1);
14026 do_neon_abs_neg (void)
14028 enum neon_shape rs;
14029 struct neon_type_el et;
14031 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14034 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14037 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14038 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14040 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14041 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14042 inst.instruction |= LOW4 (inst.operands[1].reg);
14043 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14044 inst.instruction |= neon_quad (rs) << 6;
14045 inst.instruction |= (et.type == NT_float) << 10;
14046 inst.instruction |= neon_logbits (et.size) << 18;
14048 neon_dp_fixup (&inst);
14054 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14055 struct neon_type_el et = neon_check_type (2, rs,
14056 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14057 int imm = inst.operands[2].imm;
14058 constraint (imm < 0 || (unsigned)imm >= et.size,
14059 _("immediate out of range for insert"));
14060 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14066 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14067 struct neon_type_el et = neon_check_type (2, rs,
14068 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14069 int imm = inst.operands[2].imm;
14070 constraint (imm < 1 || (unsigned)imm > et.size,
14071 _("immediate out of range for insert"));
14072 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14076 do_neon_qshlu_imm (void)
14078 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14079 struct neon_type_el et = neon_check_type (2, rs,
14080 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14081 int imm = inst.operands[2].imm;
14082 constraint (imm < 0 || (unsigned)imm >= et.size,
14083 _("immediate out of range for shift"));
14084 /* Only encodes the 'U present' variant of the instruction.
14085 In this case, signed types have OP (bit 8) set to 0.
14086 Unsigned types have OP set to 1. */
14087 inst.instruction |= (et.type == NT_unsigned) << 8;
14088 /* The rest of the bits are the same as other immediate shifts. */
14089 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14093 do_neon_qmovn (void)
14095 struct neon_type_el et = neon_check_type (2, NS_DQ,
14096 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14097 /* Saturating move where operands can be signed or unsigned, and the
14098 destination has the same signedness. */
14099 NEON_ENCODE (INTEGER, inst);
14100 if (et.type == NT_unsigned)
14101 inst.instruction |= 0xc0;
14103 inst.instruction |= 0x80;
14104 neon_two_same (0, 1, et.size / 2);
14108 do_neon_qmovun (void)
14110 struct neon_type_el et = neon_check_type (2, NS_DQ,
14111 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14112 /* Saturating move with unsigned results. Operands must be signed. */
14113 NEON_ENCODE (INTEGER, inst);
14114 neon_two_same (0, 1, et.size / 2);
14118 do_neon_rshift_sat_narrow (void)
14120 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14121 or unsigned. If operands are unsigned, results must also be unsigned. */
14122 struct neon_type_el et = neon_check_type (2, NS_DQI,
14123 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14124 int imm = inst.operands[2].imm;
14125 /* This gets the bounds check, size encoding and immediate bits calculation
14129 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14130 VQMOVN.I<size> <Dd>, <Qm>. */
14133 inst.operands[2].present = 0;
14134 inst.instruction = N_MNEM_vqmovn;
14139 constraint (imm < 1 || (unsigned)imm > et.size,
14140 _("immediate out of range"));
14141 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14145 do_neon_rshift_sat_narrow_u (void)
14147 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14148 or unsigned. If operands are unsigned, results must also be unsigned. */
14149 struct neon_type_el et = neon_check_type (2, NS_DQI,
14150 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14151 int imm = inst.operands[2].imm;
14152 /* This gets the bounds check, size encoding and immediate bits calculation
14156 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14157 VQMOVUN.I<size> <Dd>, <Qm>. */
14160 inst.operands[2].present = 0;
14161 inst.instruction = N_MNEM_vqmovun;
14166 constraint (imm < 1 || (unsigned)imm > et.size,
14167 _("immediate out of range"));
14168 /* FIXME: The manual is kind of unclear about what value U should have in
14169 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14171 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14175 do_neon_movn (void)
14177 struct neon_type_el et = neon_check_type (2, NS_DQ,
14178 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14179 NEON_ENCODE (INTEGER, inst);
14180 neon_two_same (0, 1, et.size / 2);
14184 do_neon_rshift_narrow (void)
14186 struct neon_type_el et = neon_check_type (2, NS_DQI,
14187 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14188 int imm = inst.operands[2].imm;
14189 /* This gets the bounds check, size encoding and immediate bits calculation
14193 /* If immediate is zero then we are a pseudo-instruction for
14194 VMOVN.I<size> <Dd>, <Qm> */
14197 inst.operands[2].present = 0;
14198 inst.instruction = N_MNEM_vmovn;
14203 constraint (imm < 1 || (unsigned)imm > et.size,
14204 _("immediate out of range for narrowing operation"));
14205 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14209 do_neon_shll (void)
14211 /* FIXME: Type checking when lengthening. */
14212 struct neon_type_el et = neon_check_type (2, NS_QDI,
14213 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14214 unsigned imm = inst.operands[2].imm;
14216 if (imm == et.size)
14218 /* Maximum shift variant. */
14219 NEON_ENCODE (INTEGER, inst);
14220 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14221 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14222 inst.instruction |= LOW4 (inst.operands[1].reg);
14223 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14224 inst.instruction |= neon_logbits (et.size) << 18;
14226 neon_dp_fixup (&inst);
14230 /* A more-specific type check for non-max versions. */
14231 et = neon_check_type (2, NS_QDI,
14232 N_EQK | N_DBL, N_SU_32 | N_KEY);
14233 NEON_ENCODE (IMMED, inst);
14234 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14238 /* Check the various types for the VCVT instruction, and return which version
14239 the current instruction is. */
14242 neon_cvt_flavour (enum neon_shape rs)
14244 #define CVT_VAR(C,X,Y) \
14245 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14246 if (et.type != NT_invtype) \
14248 inst.error = NULL; \
14251 struct neon_type_el et;
14252 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14253 || rs == NS_FF) ? N_VFP : 0;
14254 /* The instruction versions which take an immediate take one register
14255 argument, which is extended to the width of the full register. Thus the
14256 "source" and "destination" registers must have the same width. Hack that
14257 here by making the size equal to the key (wider, in this case) operand. */
14258 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14260 CVT_VAR (0, N_S32, N_F32);
14261 CVT_VAR (1, N_U32, N_F32);
14262 CVT_VAR (2, N_F32, N_S32);
14263 CVT_VAR (3, N_F32, N_U32);
14264 /* Half-precision conversions. */
14265 CVT_VAR (4, N_F32, N_F16);
14266 CVT_VAR (5, N_F16, N_F32);
14270 /* VFP instructions. */
14271 CVT_VAR (6, N_F32, N_F64);
14272 CVT_VAR (7, N_F64, N_F32);
14273 CVT_VAR (8, N_S32, N_F64 | key);
14274 CVT_VAR (9, N_U32, N_F64 | key);
14275 CVT_VAR (10, N_F64 | key, N_S32);
14276 CVT_VAR (11, N_F64 | key, N_U32);
14277 /* VFP instructions with bitshift. */
14278 CVT_VAR (12, N_F32 | key, N_S16);
14279 CVT_VAR (13, N_F32 | key, N_U16);
14280 CVT_VAR (14, N_F64 | key, N_S16);
14281 CVT_VAR (15, N_F64 | key, N_U16);
14282 CVT_VAR (16, N_S16, N_F32 | key);
14283 CVT_VAR (17, N_U16, N_F32 | key);
14284 CVT_VAR (18, N_S16, N_F64 | key);
14285 CVT_VAR (19, N_U16, N_F64 | key);
14291 /* Neon-syntax VFP conversions. */
14294 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14296 const char *opname = 0;
14298 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14300 /* Conversions with immediate bitshift. */
14301 const char *enc[] =
14325 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14327 opname = enc[flavour];
14328 constraint (inst.operands[0].reg != inst.operands[1].reg,
14329 _("operands 0 and 1 must be the same register"));
14330 inst.operands[1] = inst.operands[2];
14331 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14336 /* Conversions without bitshift. */
14337 const char *enc[] =
14353 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14354 opname = enc[flavour];
14358 do_vfp_nsyn_opcode (opname);
14362 do_vfp_nsyn_cvtz (void)
14364 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14365 int flavour = neon_cvt_flavour (rs);
14366 const char *enc[] =
14380 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14381 do_vfp_nsyn_opcode (enc[flavour]);
14385 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14387 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14388 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14389 int flavour = neon_cvt_flavour (rs);
14391 /* PR11109: Handle round-to-zero for VCVT conversions. */
14393 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14394 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14395 && (rs == NS_FD || rs == NS_FF))
14397 do_vfp_nsyn_cvtz ();
14401 /* VFP rather than Neon conversions. */
14404 do_vfp_nsyn_cvt (rs, flavour);
14414 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14416 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14419 /* Fixed-point conversion with #0 immediate is encoded as an
14420 integer conversion. */
14421 if (inst.operands[2].present && inst.operands[2].imm == 0)
14423 immbits = 32 - inst.operands[2].imm;
14424 NEON_ENCODE (IMMED, inst);
14426 inst.instruction |= enctab[flavour];
14427 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14428 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14429 inst.instruction |= LOW4 (inst.operands[1].reg);
14430 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14431 inst.instruction |= neon_quad (rs) << 6;
14432 inst.instruction |= 1 << 21;
14433 inst.instruction |= immbits << 16;
14435 neon_dp_fixup (&inst);
14443 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14445 NEON_ENCODE (INTEGER, inst);
14447 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14451 inst.instruction |= enctab[flavour];
14453 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14454 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14455 inst.instruction |= LOW4 (inst.operands[1].reg);
14456 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14457 inst.instruction |= neon_quad (rs) << 6;
14458 inst.instruction |= 2 << 18;
14460 neon_dp_fixup (&inst);
14464 /* Half-precision conversions for Advanced SIMD -- neon. */
14469 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14471 as_bad (_("operand size must match register width"));
14476 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14478 as_bad (_("operand size must match register width"));
14483 inst.instruction = 0x3b60600;
14485 inst.instruction = 0x3b60700;
14487 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14488 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14489 inst.instruction |= LOW4 (inst.operands[1].reg);
14490 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14491 neon_dp_fixup (&inst);
14495 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14496 do_vfp_nsyn_cvt (rs, flavour);
14501 do_neon_cvtr (void)
14503 do_neon_cvt_1 (FALSE);
14509 do_neon_cvt_1 (TRUE);
14513 do_neon_cvtb (void)
14515 inst.instruction = 0xeb20a40;
14517 /* The sizes are attached to the mnemonic. */
14518 if (inst.vectype.el[0].type != NT_invtype
14519 && inst.vectype.el[0].size == 16)
14520 inst.instruction |= 0x00010000;
14522 /* Programmer's syntax: the sizes are attached to the operands. */
14523 else if (inst.operands[0].vectype.type != NT_invtype
14524 && inst.operands[0].vectype.size == 16)
14525 inst.instruction |= 0x00010000;
14527 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14528 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14529 do_vfp_cond_or_thumb ();
14534 do_neon_cvtt (void)
14537 inst.instruction |= 0x80;
14541 neon_move_immediate (void)
14543 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14544 struct neon_type_el et = neon_check_type (2, rs,
14545 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14546 unsigned immlo, immhi = 0, immbits;
14547 int op, cmode, float_p;
14549 constraint (et.type == NT_invtype,
14550 _("operand size must be specified for immediate VMOV"));
14552 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14553 op = (inst.instruction & (1 << 5)) != 0;
14555 immlo = inst.operands[1].imm;
14556 if (inst.operands[1].regisimm)
14557 immhi = inst.operands[1].reg;
14559 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14560 _("immediate has bits set outside the operand size"));
14562 float_p = inst.operands[1].immisfloat;
14564 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14565 et.size, et.type)) == FAIL)
14567 /* Invert relevant bits only. */
14568 neon_invert_size (&immlo, &immhi, et.size);
14569 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14570 with one or the other; those cases are caught by
14571 neon_cmode_for_move_imm. */
14573 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14574 &op, et.size, et.type)) == FAIL)
14576 first_error (_("immediate out of range"));
14581 inst.instruction &= ~(1 << 5);
14582 inst.instruction |= op << 5;
14584 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14585 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14586 inst.instruction |= neon_quad (rs) << 6;
14587 inst.instruction |= cmode << 8;
14589 neon_write_immbits (immbits);
14595 if (inst.operands[1].isreg)
14597 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14599 NEON_ENCODE (INTEGER, inst);
14600 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14601 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14602 inst.instruction |= LOW4 (inst.operands[1].reg);
14603 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14604 inst.instruction |= neon_quad (rs) << 6;
14608 NEON_ENCODE (IMMED, inst);
14609 neon_move_immediate ();
14612 neon_dp_fixup (&inst);
14615 /* Encode instructions of form:
14617 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14618 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14621 neon_mixed_length (struct neon_type_el et, unsigned size)
14623 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14624 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14625 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14626 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14627 inst.instruction |= LOW4 (inst.operands[2].reg);
14628 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14629 inst.instruction |= (et.type == NT_unsigned) << 24;
14630 inst.instruction |= neon_logbits (size) << 20;
14632 neon_dp_fixup (&inst);
14636 do_neon_dyadic_long (void)
14638 /* FIXME: Type checking for lengthening op. */
14639 struct neon_type_el et = neon_check_type (3, NS_QDD,
14640 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14641 neon_mixed_length (et, et.size);
14645 do_neon_abal (void)
14647 struct neon_type_el et = neon_check_type (3, NS_QDD,
14648 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14649 neon_mixed_length (et, et.size);
14653 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14655 if (inst.operands[2].isscalar)
14657 struct neon_type_el et = neon_check_type (3, NS_QDS,
14658 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14659 NEON_ENCODE (SCALAR, inst);
14660 neon_mul_mac (et, et.type == NT_unsigned);
14664 struct neon_type_el et = neon_check_type (3, NS_QDD,
14665 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14666 NEON_ENCODE (INTEGER, inst);
14667 neon_mixed_length (et, et.size);
14672 do_neon_mac_maybe_scalar_long (void)
14674 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14678 do_neon_dyadic_wide (void)
14680 struct neon_type_el et = neon_check_type (3, NS_QQD,
14681 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14682 neon_mixed_length (et, et.size);
14686 do_neon_dyadic_narrow (void)
14688 struct neon_type_el et = neon_check_type (3, NS_QDD,
14689 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14690 /* Operand sign is unimportant, and the U bit is part of the opcode,
14691 so force the operand type to integer. */
14692 et.type = NT_integer;
14693 neon_mixed_length (et, et.size / 2);
14697 do_neon_mul_sat_scalar_long (void)
14699 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14703 do_neon_vmull (void)
14705 if (inst.operands[2].isscalar)
14706 do_neon_mac_maybe_scalar_long ();
14709 struct neon_type_el et = neon_check_type (3, NS_QDD,
14710 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14711 if (et.type == NT_poly)
14712 NEON_ENCODE (POLY, inst);
14714 NEON_ENCODE (INTEGER, inst);
14715 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14716 zero. Should be OK as-is. */
14717 neon_mixed_length (et, et.size);
14724 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14725 struct neon_type_el et = neon_check_type (3, rs,
14726 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14727 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14729 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14730 _("shift out of range"));
14731 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14732 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14733 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14734 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14735 inst.instruction |= LOW4 (inst.operands[2].reg);
14736 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14737 inst.instruction |= neon_quad (rs) << 6;
14738 inst.instruction |= imm << 8;
14740 neon_dp_fixup (&inst);
14746 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14747 struct neon_type_el et = neon_check_type (2, rs,
14748 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14749 unsigned op = (inst.instruction >> 7) & 3;
14750 /* N (width of reversed regions) is encoded as part of the bitmask. We
14751 extract it here to check the elements to be reversed are smaller.
14752 Otherwise we'd get a reserved instruction. */
14753 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14754 gas_assert (elsize != 0);
14755 constraint (et.size >= elsize,
14756 _("elements must be smaller than reversal region"));
14757 neon_two_same (neon_quad (rs), 1, et.size);
14763 if (inst.operands[1].isscalar)
14765 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14766 struct neon_type_el et = neon_check_type (2, rs,
14767 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14768 unsigned sizebits = et.size >> 3;
14769 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14770 int logsize = neon_logbits (et.size);
14771 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14773 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14776 NEON_ENCODE (SCALAR, inst);
14777 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14778 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14779 inst.instruction |= LOW4 (dm);
14780 inst.instruction |= HI1 (dm) << 5;
14781 inst.instruction |= neon_quad (rs) << 6;
14782 inst.instruction |= x << 17;
14783 inst.instruction |= sizebits << 16;
14785 neon_dp_fixup (&inst);
14789 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14790 struct neon_type_el et = neon_check_type (2, rs,
14791 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14792 /* Duplicate ARM register to lanes of vector. */
14793 NEON_ENCODE (ARMREG, inst);
14796 case 8: inst.instruction |= 0x400000; break;
14797 case 16: inst.instruction |= 0x000020; break;
14798 case 32: inst.instruction |= 0x000000; break;
14801 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14802 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14803 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14804 inst.instruction |= neon_quad (rs) << 21;
14805 /* The encoding for this instruction is identical for the ARM and Thumb
14806 variants, except for the condition field. */
14807 do_vfp_cond_or_thumb ();
14811 /* VMOV has particularly many variations. It can be one of:
14812 0. VMOV<c><q> <Qd>, <Qm>
14813 1. VMOV<c><q> <Dd>, <Dm>
14814 (Register operations, which are VORR with Rm = Rn.)
14815 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14816 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14818 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14819 (ARM register to scalar.)
14820 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14821 (Two ARM registers to vector.)
14822 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14823 (Scalar to ARM register.)
14824 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14825 (Vector to two ARM registers.)
14826 8. VMOV.F32 <Sd>, <Sm>
14827 9. VMOV.F64 <Dd>, <Dm>
14828 (VFP register moves.)
14829 10. VMOV.F32 <Sd>, #imm
14830 11. VMOV.F64 <Dd>, #imm
14831 (VFP float immediate load.)
14832 12. VMOV <Rd>, <Sm>
14833 (VFP single to ARM reg.)
14834 13. VMOV <Sd>, <Rm>
14835 (ARM reg to VFP single.)
14836 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14837 (Two ARM regs to two VFP singles.)
14838 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14839 (Two VFP singles to two ARM regs.)
14841 These cases can be disambiguated using neon_select_shape, except cases 1/9
14842 and 3/11 which depend on the operand type too.
14844 All the encoded bits are hardcoded by this function.
14846 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14847 Cases 5, 7 may be used with VFPv2 and above.
14849 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14850 can specify a type where it doesn't make sense to, and is ignored). */
14855 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14856 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14858 struct neon_type_el et;
14859 const char *ldconst = 0;
14863 case NS_DD: /* case 1/9. */
14864 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14865 /* It is not an error here if no type is given. */
14867 if (et.type == NT_float && et.size == 64)
14869 do_vfp_nsyn_opcode ("fcpyd");
14872 /* fall through. */
14874 case NS_QQ: /* case 0/1. */
14876 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14878 /* The architecture manual I have doesn't explicitly state which
14879 value the U bit should have for register->register moves, but
14880 the equivalent VORR instruction has U = 0, so do that. */
14881 inst.instruction = 0x0200110;
14882 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14883 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14884 inst.instruction |= LOW4 (inst.operands[1].reg);
14885 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14886 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14887 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14888 inst.instruction |= neon_quad (rs) << 6;
14890 neon_dp_fixup (&inst);
14894 case NS_DI: /* case 3/11. */
14895 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14897 if (et.type == NT_float && et.size == 64)
14899 /* case 11 (fconstd). */
14900 ldconst = "fconstd";
14901 goto encode_fconstd;
14903 /* fall through. */
14905 case NS_QI: /* case 2/3. */
14906 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14908 inst.instruction = 0x0800010;
14909 neon_move_immediate ();
14910 neon_dp_fixup (&inst);
14913 case NS_SR: /* case 4. */
14915 unsigned bcdebits = 0;
14917 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14918 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14920 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14921 logsize = neon_logbits (et.size);
14923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14925 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14926 && et.size != 32, _(BAD_FPU));
14927 constraint (et.type == NT_invtype, _("bad type for scalar"));
14928 constraint (x >= 64 / et.size, _("scalar index out of range"));
14932 case 8: bcdebits = 0x8; break;
14933 case 16: bcdebits = 0x1; break;
14934 case 32: bcdebits = 0x0; break;
14938 bcdebits |= x << logsize;
14940 inst.instruction = 0xe000b10;
14941 do_vfp_cond_or_thumb ();
14942 inst.instruction |= LOW4 (dn) << 16;
14943 inst.instruction |= HI1 (dn) << 7;
14944 inst.instruction |= inst.operands[1].reg << 12;
14945 inst.instruction |= (bcdebits & 3) << 5;
14946 inst.instruction |= (bcdebits >> 2) << 21;
14950 case NS_DRR: /* case 5 (fmdrr). */
14951 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14954 inst.instruction = 0xc400b10;
14955 do_vfp_cond_or_thumb ();
14956 inst.instruction |= LOW4 (inst.operands[0].reg);
14957 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14958 inst.instruction |= inst.operands[1].reg << 12;
14959 inst.instruction |= inst.operands[2].reg << 16;
14962 case NS_RS: /* case 6. */
14965 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14966 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14967 unsigned abcdebits = 0;
14969 et = neon_check_type (2, NS_NULL,
14970 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14971 logsize = neon_logbits (et.size);
14973 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14975 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14976 && et.size != 32, _(BAD_FPU));
14977 constraint (et.type == NT_invtype, _("bad type for scalar"));
14978 constraint (x >= 64 / et.size, _("scalar index out of range"));
14982 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14983 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14984 case 32: abcdebits = 0x00; break;
14988 abcdebits |= x << logsize;
14989 inst.instruction = 0xe100b10;
14990 do_vfp_cond_or_thumb ();
14991 inst.instruction |= LOW4 (dn) << 16;
14992 inst.instruction |= HI1 (dn) << 7;
14993 inst.instruction |= inst.operands[0].reg << 12;
14994 inst.instruction |= (abcdebits & 3) << 5;
14995 inst.instruction |= (abcdebits >> 2) << 21;
14999 case NS_RRD: /* case 7 (fmrrd). */
15000 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15003 inst.instruction = 0xc500b10;
15004 do_vfp_cond_or_thumb ();
15005 inst.instruction |= inst.operands[0].reg << 12;
15006 inst.instruction |= inst.operands[1].reg << 16;
15007 inst.instruction |= LOW4 (inst.operands[2].reg);
15008 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15011 case NS_FF: /* case 8 (fcpys). */
15012 do_vfp_nsyn_opcode ("fcpys");
15015 case NS_FI: /* case 10 (fconsts). */
15016 ldconst = "fconsts";
15018 if (is_quarter_float (inst.operands[1].imm))
15020 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15021 do_vfp_nsyn_opcode (ldconst);
15024 first_error (_("immediate out of range"));
15027 case NS_RF: /* case 12 (fmrs). */
15028 do_vfp_nsyn_opcode ("fmrs");
15031 case NS_FR: /* case 13 (fmsr). */
15032 do_vfp_nsyn_opcode ("fmsr");
15035 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15036 (one of which is a list), but we have parsed four. Do some fiddling to
15037 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15039 case NS_RRFF: /* case 14 (fmrrs). */
15040 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15041 _("VFP registers must be adjacent"));
15042 inst.operands[2].imm = 2;
15043 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15044 do_vfp_nsyn_opcode ("fmrrs");
15047 case NS_FFRR: /* case 15 (fmsrr). */
15048 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15049 _("VFP registers must be adjacent"));
15050 inst.operands[1] = inst.operands[2];
15051 inst.operands[2] = inst.operands[3];
15052 inst.operands[0].imm = 2;
15053 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15054 do_vfp_nsyn_opcode ("fmsrr");
15063 do_neon_rshift_round_imm (void)
15065 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15066 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15067 int imm = inst.operands[2].imm;
15069 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15072 inst.operands[2].present = 0;
15077 constraint (imm < 1 || (unsigned)imm > et.size,
15078 _("immediate out of range for shift"));
15079 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15084 do_neon_movl (void)
15086 struct neon_type_el et = neon_check_type (2, NS_QD,
15087 N_EQK | N_DBL, N_SU_32 | N_KEY);
15088 unsigned sizebits = et.size >> 3;
15089 inst.instruction |= sizebits << 19;
15090 neon_two_same (0, et.type == NT_unsigned, -1);
15096 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15097 struct neon_type_el et = neon_check_type (2, rs,
15098 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15099 NEON_ENCODE (INTEGER, inst);
15100 neon_two_same (neon_quad (rs), 1, et.size);
15104 do_neon_zip_uzp (void)
15106 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15107 struct neon_type_el et = neon_check_type (2, rs,
15108 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15109 if (rs == NS_DD && et.size == 32)
15111 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15112 inst.instruction = N_MNEM_vtrn;
15116 neon_two_same (neon_quad (rs), 1, et.size);
15120 do_neon_sat_abs_neg (void)
15122 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15123 struct neon_type_el et = neon_check_type (2, rs,
15124 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15125 neon_two_same (neon_quad (rs), 1, et.size);
15129 do_neon_pair_long (void)
15131 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15132 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15133 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15134 inst.instruction |= (et.type == NT_unsigned) << 7;
15135 neon_two_same (neon_quad (rs), 1, et.size);
15139 do_neon_recip_est (void)
15141 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15142 struct neon_type_el et = neon_check_type (2, rs,
15143 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15144 inst.instruction |= (et.type == NT_float) << 8;
15145 neon_two_same (neon_quad (rs), 1, et.size);
15151 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15152 struct neon_type_el et = neon_check_type (2, rs,
15153 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15154 neon_two_same (neon_quad (rs), 1, et.size);
15160 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15161 struct neon_type_el et = neon_check_type (2, rs,
15162 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15163 neon_two_same (neon_quad (rs), 1, et.size);
15169 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15170 struct neon_type_el et = neon_check_type (2, rs,
15171 N_EQK | N_INT, N_8 | N_KEY);
15172 neon_two_same (neon_quad (rs), 1, et.size);
15178 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15179 neon_two_same (neon_quad (rs), 1, -1);
15183 do_neon_tbl_tbx (void)
15185 unsigned listlenbits;
15186 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15188 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15190 first_error (_("bad list length for table lookup"));
15194 listlenbits = inst.operands[1].imm - 1;
15195 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15196 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15197 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15198 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15199 inst.instruction |= LOW4 (inst.operands[2].reg);
15200 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15201 inst.instruction |= listlenbits << 8;
15203 neon_dp_fixup (&inst);
15207 do_neon_ldm_stm (void)
15209 /* P, U and L bits are part of bitmask. */
15210 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15211 unsigned offsetbits = inst.operands[1].imm * 2;
15213 if (inst.operands[1].issingle)
15215 do_vfp_nsyn_ldm_stm (is_dbmode);
15219 constraint (is_dbmode && !inst.operands[0].writeback,
15220 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15222 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15223 _("register list must contain at least 1 and at most 16 "
15226 inst.instruction |= inst.operands[0].reg << 16;
15227 inst.instruction |= inst.operands[0].writeback << 21;
15228 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15229 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15231 inst.instruction |= offsetbits;
15233 do_vfp_cond_or_thumb ();
15237 do_neon_ldr_str (void)
15239 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15241 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15242 And is UNPREDICTABLE in thumb mode. */
15244 && inst.operands[1].reg == REG_PC
15245 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15247 if (!thumb_mode && warn_on_deprecated)
15248 as_warn (_("Use of PC here is deprecated"));
15250 inst.error = _("Use of PC here is UNPREDICTABLE");
15253 if (inst.operands[0].issingle)
15256 do_vfp_nsyn_opcode ("flds");
15258 do_vfp_nsyn_opcode ("fsts");
15263 do_vfp_nsyn_opcode ("fldd");
15265 do_vfp_nsyn_opcode ("fstd");
15269 /* "interleave" version also handles non-interleaving register VLD1/VST1
15273 do_neon_ld_st_interleave (void)
15275 struct neon_type_el et = neon_check_type (1, NS_NULL,
15276 N_8 | N_16 | N_32 | N_64);
15277 unsigned alignbits = 0;
15279 /* The bits in this table go:
15280 0: register stride of one (0) or two (1)
15281 1,2: register list length, minus one (1, 2, 3, 4).
15282 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15283 We use -1 for invalid entries. */
15284 const int typetable[] =
15286 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15287 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15288 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15289 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15293 if (et.type == NT_invtype)
15296 if (inst.operands[1].immisalign)
15297 switch (inst.operands[1].imm >> 8)
15299 case 64: alignbits = 1; break;
15301 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15302 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15303 goto bad_alignment;
15307 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15308 goto bad_alignment;
15313 first_error (_("bad alignment"));
15317 inst.instruction |= alignbits << 4;
15318 inst.instruction |= neon_logbits (et.size) << 6;
15320 /* Bits [4:6] of the immediate in a list specifier encode register stride
15321 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15322 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15323 up the right value for "type" in a table based on this value and the given
15324 list style, then stick it back. */
15325 idx = ((inst.operands[0].imm >> 4) & 7)
15326 | (((inst.instruction >> 8) & 3) << 3);
15328 typebits = typetable[idx];
15330 constraint (typebits == -1, _("bad list type for instruction"));
15332 inst.instruction &= ~0xf00;
15333 inst.instruction |= typebits << 8;
15336 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15337 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15338 otherwise. The variable arguments are a list of pairs of legal (size, align)
15339 values, terminated with -1. */
15342 neon_alignment_bit (int size, int align, int *do_align, ...)
15345 int result = FAIL, thissize, thisalign;
15347 if (!inst.operands[1].immisalign)
15353 va_start (ap, do_align);
15357 thissize = va_arg (ap, int);
15358 if (thissize == -1)
15360 thisalign = va_arg (ap, int);
15362 if (size == thissize && align == thisalign)
15365 while (result != SUCCESS);
15369 if (result == SUCCESS)
15372 first_error (_("unsupported alignment for instruction"));
15378 do_neon_ld_st_lane (void)
15380 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15381 int align_good, do_align = 0;
15382 int logsize = neon_logbits (et.size);
15383 int align = inst.operands[1].imm >> 8;
15384 int n = (inst.instruction >> 8) & 3;
15385 int max_el = 64 / et.size;
15387 if (et.type == NT_invtype)
15390 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15391 _("bad list length"));
15392 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15393 _("scalar index out of range"));
15394 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15396 _("stride of 2 unavailable when element size is 8"));
15400 case 0: /* VLD1 / VST1. */
15401 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15403 if (align_good == FAIL)
15407 unsigned alignbits = 0;
15410 case 16: alignbits = 0x1; break;
15411 case 32: alignbits = 0x3; break;
15414 inst.instruction |= alignbits << 4;
15418 case 1: /* VLD2 / VST2. */
15419 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15421 if (align_good == FAIL)
15424 inst.instruction |= 1 << 4;
15427 case 2: /* VLD3 / VST3. */
15428 constraint (inst.operands[1].immisalign,
15429 _("can't use alignment with this instruction"));
15432 case 3: /* VLD4 / VST4. */
15433 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15434 16, 64, 32, 64, 32, 128, -1);
15435 if (align_good == FAIL)
15439 unsigned alignbits = 0;
15442 case 8: alignbits = 0x1; break;
15443 case 16: alignbits = 0x1; break;
15444 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15447 inst.instruction |= alignbits << 4;
15454 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15455 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15456 inst.instruction |= 1 << (4 + logsize);
15458 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15459 inst.instruction |= logsize << 10;
15462 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15465 do_neon_ld_dup (void)
15467 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15468 int align_good, do_align = 0;
15470 if (et.type == NT_invtype)
15473 switch ((inst.instruction >> 8) & 3)
15475 case 0: /* VLD1. */
15476 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15477 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15478 &do_align, 16, 16, 32, 32, -1);
15479 if (align_good == FAIL)
15481 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15484 case 2: inst.instruction |= 1 << 5; break;
15485 default: first_error (_("bad list length")); return;
15487 inst.instruction |= neon_logbits (et.size) << 6;
15490 case 1: /* VLD2. */
15491 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15492 &do_align, 8, 16, 16, 32, 32, 64, -1);
15493 if (align_good == FAIL)
15495 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15496 _("bad list length"));
15497 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15498 inst.instruction |= 1 << 5;
15499 inst.instruction |= neon_logbits (et.size) << 6;
15502 case 2: /* VLD3. */
15503 constraint (inst.operands[1].immisalign,
15504 _("can't use alignment with this instruction"));
15505 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15506 _("bad list length"));
15507 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15508 inst.instruction |= 1 << 5;
15509 inst.instruction |= neon_logbits (et.size) << 6;
15512 case 3: /* VLD4. */
15514 int align = inst.operands[1].imm >> 8;
15515 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15516 16, 64, 32, 64, 32, 128, -1);
15517 if (align_good == FAIL)
15519 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15520 _("bad list length"));
15521 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15522 inst.instruction |= 1 << 5;
15523 if (et.size == 32 && align == 128)
15524 inst.instruction |= 0x3 << 6;
15526 inst.instruction |= neon_logbits (et.size) << 6;
15533 inst.instruction |= do_align << 4;
15536 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15537 apart from bits [11:4]. */
15540 do_neon_ldx_stx (void)
15542 if (inst.operands[1].isreg)
15543 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15545 switch (NEON_LANE (inst.operands[0].imm))
15547 case NEON_INTERLEAVE_LANES:
15548 NEON_ENCODE (INTERLV, inst);
15549 do_neon_ld_st_interleave ();
15552 case NEON_ALL_LANES:
15553 NEON_ENCODE (DUP, inst);
15558 NEON_ENCODE (LANE, inst);
15559 do_neon_ld_st_lane ();
15562 /* L bit comes from bit mask. */
15563 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15564 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15565 inst.instruction |= inst.operands[1].reg << 16;
15567 if (inst.operands[1].postind)
15569 int postreg = inst.operands[1].imm & 0xf;
15570 constraint (!inst.operands[1].immisreg,
15571 _("post-index must be a register"));
15572 constraint (postreg == 0xd || postreg == 0xf,
15573 _("bad register for post-index"));
15574 inst.instruction |= postreg;
15576 else if (inst.operands[1].writeback)
15578 inst.instruction |= 0xd;
15581 inst.instruction |= 0xf;
15584 inst.instruction |= 0xf9000000;
15586 inst.instruction |= 0xf4000000;
15589 /* Overall per-instruction processing. */
15591 /* We need to be able to fix up arbitrary expressions in some statements.
15592 This is so that we can handle symbols that are an arbitrary distance from
15593 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15594 which returns part of an address in a form which will be valid for
15595 a data instruction. We do this by pushing the expression into a symbol
15596 in the expr_section, and creating a fix for that. */
15599 fix_new_arm (fragS * frag,
15613 /* Create an absolute valued symbol, so we have something to
15614 refer to in the object file. Unfortunately for us, gas's
15615 generic expression parsing will already have folded out
15616 any use of .set foo/.type foo %function that may have
15617 been used to set type information of the target location,
15618 that's being specified symbolically. We have to presume
15619 the user knows what they are doing. */
15623 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15625 symbol = symbol_find_or_make (name);
15626 S_SET_SEGMENT (symbol, absolute_section);
15627 symbol_set_frag (symbol, &zero_address_frag);
15628 S_SET_VALUE (symbol, exp->X_add_number);
15629 exp->X_op = O_symbol;
15630 exp->X_add_symbol = symbol;
15631 exp->X_add_number = 0;
15637 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15638 (enum bfd_reloc_code_real) reloc);
15642 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15643 pc_rel, (enum bfd_reloc_code_real) reloc);
15647 /* Mark whether the fix is to a THUMB instruction, or an ARM
15649 new_fix->tc_fix_data = thumb_mode;
15652 /* Create a frg for an instruction requiring relaxation. */
15654 output_relax_insn (void)
15660 /* The size of the instruction is unknown, so tie the debug info to the
15661 start of the instruction. */
15662 dwarf2_emit_insn (0);
15664 switch (inst.reloc.exp.X_op)
15667 sym = inst.reloc.exp.X_add_symbol;
15668 offset = inst.reloc.exp.X_add_number;
15672 offset = inst.reloc.exp.X_add_number;
15675 sym = make_expr_symbol (&inst.reloc.exp);
15679 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15680 inst.relax, sym, offset, NULL/*offset, opcode*/);
15681 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15684 /* Write a 32-bit thumb instruction to buf. */
15686 put_thumb32_insn (char * buf, unsigned long insn)
15688 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15689 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15693 output_inst (const char * str)
15699 as_bad ("%s -- `%s'", inst.error, str);
15704 output_relax_insn ();
15707 if (inst.size == 0)
15710 to = frag_more (inst.size);
15711 /* PR 9814: Record the thumb mode into the current frag so that we know
15712 what type of NOP padding to use, if necessary. We override any previous
15713 setting so that if the mode has changed then the NOPS that we use will
15714 match the encoding of the last instruction in the frag. */
15715 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15717 if (thumb_mode && (inst.size > THUMB_SIZE))
15719 gas_assert (inst.size == (2 * THUMB_SIZE));
15720 put_thumb32_insn (to, inst.instruction);
15722 else if (inst.size > INSN_SIZE)
15724 gas_assert (inst.size == (2 * INSN_SIZE));
15725 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15726 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15729 md_number_to_chars (to, inst.instruction, inst.size);
15731 if (inst.reloc.type != BFD_RELOC_UNUSED)
15732 fix_new_arm (frag_now, to - frag_now->fr_literal,
15733 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15736 dwarf2_emit_insn (inst.size);
15740 output_it_inst (int cond, int mask, char * to)
15742 unsigned long instruction = 0xbf00;
15745 instruction |= mask;
15746 instruction |= cond << 4;
15750 to = frag_more (2);
15752 dwarf2_emit_insn (2);
15756 md_number_to_chars (to, instruction, 2);
15761 /* Tag values used in struct asm_opcode's tag field. */
15764 OT_unconditional, /* Instruction cannot be conditionalized.
15765 The ARM condition field is still 0xE. */
15766 OT_unconditionalF, /* Instruction cannot be conditionalized
15767 and carries 0xF in its ARM condition field. */
15768 OT_csuffix, /* Instruction takes a conditional suffix. */
15769 OT_csuffixF, /* Some forms of the instruction take a conditional
15770 suffix, others place 0xF where the condition field
15772 OT_cinfix3, /* Instruction takes a conditional infix,
15773 beginning at character index 3. (In
15774 unified mode, it becomes a suffix.) */
15775 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15776 tsts, cmps, cmns, and teqs. */
15777 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15778 character index 3, even in unified mode. Used for
15779 legacy instructions where suffix and infix forms
15780 may be ambiguous. */
15781 OT_csuf_or_in3, /* Instruction takes either a conditional
15782 suffix or an infix at character index 3. */
15783 OT_odd_infix_unc, /* This is the unconditional variant of an
15784 instruction that takes a conditional infix
15785 at an unusual position. In unified mode,
15786 this variant will accept a suffix. */
15787 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15788 are the conditional variants of instructions that
15789 take conditional infixes in unusual positions.
15790 The infix appears at character index
15791 (tag - OT_odd_infix_0). These are not accepted
15792 in unified mode. */
15795 /* Subroutine of md_assemble, responsible for looking up the primary
15796 opcode from the mnemonic the user wrote. STR points to the
15797 beginning of the mnemonic.
15799 This is not simply a hash table lookup, because of conditional
15800 variants. Most instructions have conditional variants, which are
15801 expressed with a _conditional affix_ to the mnemonic. If we were
15802 to encode each conditional variant as a literal string in the opcode
15803 table, it would have approximately 20,000 entries.
15805 Most mnemonics take this affix as a suffix, and in unified syntax,
15806 'most' is upgraded to 'all'. However, in the divided syntax, some
15807 instructions take the affix as an infix, notably the s-variants of
15808 the arithmetic instructions. Of those instructions, all but six
15809 have the infix appear after the third character of the mnemonic.
15811 Accordingly, the algorithm for looking up primary opcodes given
15814 1. Look up the identifier in the opcode table.
15815 If we find a match, go to step U.
15817 2. Look up the last two characters of the identifier in the
15818 conditions table. If we find a match, look up the first N-2
15819 characters of the identifier in the opcode table. If we
15820 find a match, go to step CE.
15822 3. Look up the fourth and fifth characters of the identifier in
15823 the conditions table. If we find a match, extract those
15824 characters from the identifier, and look up the remaining
15825 characters in the opcode table. If we find a match, go
15830 U. Examine the tag field of the opcode structure, in case this is
15831 one of the six instructions with its conditional infix in an
15832 unusual place. If it is, the tag tells us where to find the
15833 infix; look it up in the conditions table and set inst.cond
15834 accordingly. Otherwise, this is an unconditional instruction.
15835 Again set inst.cond accordingly. Return the opcode structure.
15837 CE. Examine the tag field to make sure this is an instruction that
15838 should receive a conditional suffix. If it is not, fail.
15839 Otherwise, set inst.cond from the suffix we already looked up,
15840 and return the opcode structure.
15842 CM. Examine the tag field to make sure this is an instruction that
15843 should receive a conditional infix after the third character.
15844 If it is not, fail. Otherwise, undo the edits to the current
15845 line of input and proceed as for case CE. */
15847 static const struct asm_opcode *
15848 opcode_lookup (char **str)
15852 const struct asm_opcode *opcode;
15853 const struct asm_cond *cond;
15856 /* Scan up to the end of the mnemonic, which must end in white space,
15857 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15858 for (base = end = *str; *end != '\0'; end++)
15859 if (*end == ' ' || *end == '.')
15865 /* Handle a possible width suffix and/or Neon type suffix. */
15870 /* The .w and .n suffixes are only valid if the unified syntax is in
15872 if (unified_syntax && end[1] == 'w')
15874 else if (unified_syntax && end[1] == 'n')
15879 inst.vectype.elems = 0;
15881 *str = end + offset;
15883 if (end[offset] == '.')
15885 /* See if we have a Neon type suffix (possible in either unified or
15886 non-unified ARM syntax mode). */
15887 if (parse_neon_type (&inst.vectype, str) == FAIL)
15890 else if (end[offset] != '\0' && end[offset] != ' ')
15896 /* Look for unaffixed or special-case affixed mnemonic. */
15897 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15902 if (opcode->tag < OT_odd_infix_0)
15904 inst.cond = COND_ALWAYS;
15908 if (warn_on_deprecated && unified_syntax)
15909 as_warn (_("conditional infixes are deprecated in unified syntax"));
15910 affix = base + (opcode->tag - OT_odd_infix_0);
15911 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15914 inst.cond = cond->value;
15918 /* Cannot have a conditional suffix on a mnemonic of less than two
15920 if (end - base < 3)
15923 /* Look for suffixed mnemonic. */
15925 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15926 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15928 if (opcode && cond)
15931 switch (opcode->tag)
15933 case OT_cinfix3_legacy:
15934 /* Ignore conditional suffixes matched on infix only mnemonics. */
15938 case OT_cinfix3_deprecated:
15939 case OT_odd_infix_unc:
15940 if (!unified_syntax)
15942 /* else fall through */
15946 case OT_csuf_or_in3:
15947 inst.cond = cond->value;
15950 case OT_unconditional:
15951 case OT_unconditionalF:
15953 inst.cond = cond->value;
15956 /* Delayed diagnostic. */
15957 inst.error = BAD_COND;
15958 inst.cond = COND_ALWAYS;
15967 /* Cannot have a usual-position infix on a mnemonic of less than
15968 six characters (five would be a suffix). */
15969 if (end - base < 6)
15972 /* Look for infixed mnemonic in the usual position. */
15974 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15978 memcpy (save, affix, 2);
15979 memmove (affix, affix + 2, (end - affix) - 2);
15980 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15982 memmove (affix + 2, affix, (end - affix) - 2);
15983 memcpy (affix, save, 2);
15986 && (opcode->tag == OT_cinfix3
15987 || opcode->tag == OT_cinfix3_deprecated
15988 || opcode->tag == OT_csuf_or_in3
15989 || opcode->tag == OT_cinfix3_legacy))
15992 if (warn_on_deprecated && unified_syntax
15993 && (opcode->tag == OT_cinfix3
15994 || opcode->tag == OT_cinfix3_deprecated))
15995 as_warn (_("conditional infixes are deprecated in unified syntax"));
15997 inst.cond = cond->value;
16004 /* This function generates an initial IT instruction, leaving its block
16005 virtually open for the new instructions. Eventually,
16006 the mask will be updated by now_it_add_mask () each time
16007 a new instruction needs to be included in the IT block.
16008 Finally, the block is closed with close_automatic_it_block ().
16009 The block closure can be requested either from md_assemble (),
16010 a tencode (), or due to a label hook. */
16013 new_automatic_it_block (int cond)
16015 now_it.state = AUTOMATIC_IT_BLOCK;
16016 now_it.mask = 0x18;
16018 now_it.block_length = 1;
16019 mapping_state (MAP_THUMB);
16020 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16023 /* Close an automatic IT block.
16024 See comments in new_automatic_it_block (). */
16027 close_automatic_it_block (void)
16029 now_it.mask = 0x10;
16030 now_it.block_length = 0;
16033 /* Update the mask of the current automatically-generated IT
16034 instruction. See comments in new_automatic_it_block (). */
16037 now_it_add_mask (int cond)
16039 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16040 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16041 | ((bitvalue) << (nbit)))
16042 const int resulting_bit = (cond & 1);
16044 now_it.mask &= 0xf;
16045 now_it.mask = SET_BIT_VALUE (now_it.mask,
16047 (5 - now_it.block_length));
16048 now_it.mask = SET_BIT_VALUE (now_it.mask,
16050 ((5 - now_it.block_length) - 1) );
16051 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16054 #undef SET_BIT_VALUE
16057 /* The IT blocks handling machinery is accessed through the these functions:
16058 it_fsm_pre_encode () from md_assemble ()
16059 set_it_insn_type () optional, from the tencode functions
16060 set_it_insn_type_last () ditto
16061 in_it_block () ditto
16062 it_fsm_post_encode () from md_assemble ()
16063 force_automatic_it_block_close () from label habdling functions
16066 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16067 initializing the IT insn type with a generic initial value depending
16068 on the inst.condition.
16069 2) During the tencode function, two things may happen:
16070 a) The tencode function overrides the IT insn type by
16071 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16072 b) The tencode function queries the IT block state by
16073 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16075 Both set_it_insn_type and in_it_block run the internal FSM state
16076 handling function (handle_it_state), because: a) setting the IT insn
16077 type may incur in an invalid state (exiting the function),
16078 and b) querying the state requires the FSM to be updated.
16079 Specifically we want to avoid creating an IT block for conditional
16080 branches, so it_fsm_pre_encode is actually a guess and we can't
16081 determine whether an IT block is required until the tencode () routine
16082 has decided what type of instruction this actually it.
16083 Because of this, if set_it_insn_type and in_it_block have to be used,
16084 set_it_insn_type has to be called first.
16086 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16087 determines the insn IT type depending on the inst.cond code.
16088 When a tencode () routine encodes an instruction that can be
16089 either outside an IT block, or, in the case of being inside, has to be
16090 the last one, set_it_insn_type_last () will determine the proper
16091 IT instruction type based on the inst.cond code. Otherwise,
16092 set_it_insn_type can be called for overriding that logic or
16093 for covering other cases.
16095 Calling handle_it_state () may not transition the IT block state to
16096 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16097 still queried. Instead, if the FSM determines that the state should
16098 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16099 after the tencode () function: that's what it_fsm_post_encode () does.
16101 Since in_it_block () calls the state handling function to get an
16102 updated state, an error may occur (due to invalid insns combination).
16103 In that case, inst.error is set.
16104 Therefore, inst.error has to be checked after the execution of
16105 the tencode () routine.
16107 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16108 any pending state change (if any) that didn't take place in
16109 handle_it_state () as explained above. */
16112 it_fsm_pre_encode (void)
16114 if (inst.cond != COND_ALWAYS)
16115 inst.it_insn_type = INSIDE_IT_INSN;
16117 inst.it_insn_type = OUTSIDE_IT_INSN;
16119 now_it.state_handled = 0;
16122 /* IT state FSM handling function. */
16125 handle_it_state (void)
16127 now_it.state_handled = 1;
16129 switch (now_it.state)
16131 case OUTSIDE_IT_BLOCK:
16132 switch (inst.it_insn_type)
16134 case OUTSIDE_IT_INSN:
16137 case INSIDE_IT_INSN:
16138 case INSIDE_IT_LAST_INSN:
16139 if (thumb_mode == 0)
16142 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16143 as_tsktsk (_("Warning: conditional outside an IT block"\
16148 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16149 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16151 /* Automatically generate the IT instruction. */
16152 new_automatic_it_block (inst.cond);
16153 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16154 close_automatic_it_block ();
16158 inst.error = BAD_OUT_IT;
16164 case IF_INSIDE_IT_LAST_INSN:
16165 case NEUTRAL_IT_INSN:
16169 now_it.state = MANUAL_IT_BLOCK;
16170 now_it.block_length = 0;
16175 case AUTOMATIC_IT_BLOCK:
16176 /* Three things may happen now:
16177 a) We should increment current it block size;
16178 b) We should close current it block (closing insn or 4 insns);
16179 c) We should close current it block and start a new one (due
16180 to incompatible conditions or
16181 4 insns-length block reached). */
16183 switch (inst.it_insn_type)
16185 case OUTSIDE_IT_INSN:
16186 /* The closure of the block shall happen immediatelly,
16187 so any in_it_block () call reports the block as closed. */
16188 force_automatic_it_block_close ();
16191 case INSIDE_IT_INSN:
16192 case INSIDE_IT_LAST_INSN:
16193 case IF_INSIDE_IT_LAST_INSN:
16194 now_it.block_length++;
16196 if (now_it.block_length > 4
16197 || !now_it_compatible (inst.cond))
16199 force_automatic_it_block_close ();
16200 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16201 new_automatic_it_block (inst.cond);
16205 now_it_add_mask (inst.cond);
16208 if (now_it.state == AUTOMATIC_IT_BLOCK
16209 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16210 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16211 close_automatic_it_block ();
16214 case NEUTRAL_IT_INSN:
16215 now_it.block_length++;
16217 if (now_it.block_length > 4)
16218 force_automatic_it_block_close ();
16220 now_it_add_mask (now_it.cc & 1);
16224 close_automatic_it_block ();
16225 now_it.state = MANUAL_IT_BLOCK;
16230 case MANUAL_IT_BLOCK:
16232 /* Check conditional suffixes. */
16233 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16236 now_it.mask &= 0x1f;
16237 is_last = (now_it.mask == 0x10);
16239 switch (inst.it_insn_type)
16241 case OUTSIDE_IT_INSN:
16242 inst.error = BAD_NOT_IT;
16245 case INSIDE_IT_INSN:
16246 if (cond != inst.cond)
16248 inst.error = BAD_IT_COND;
16253 case INSIDE_IT_LAST_INSN:
16254 case IF_INSIDE_IT_LAST_INSN:
16255 if (cond != inst.cond)
16257 inst.error = BAD_IT_COND;
16262 inst.error = BAD_BRANCH;
16267 case NEUTRAL_IT_INSN:
16268 /* The BKPT instruction is unconditional even in an IT block. */
16272 inst.error = BAD_IT_IT;
16283 it_fsm_post_encode (void)
16287 if (!now_it.state_handled)
16288 handle_it_state ();
16290 is_last = (now_it.mask == 0x10);
16293 now_it.state = OUTSIDE_IT_BLOCK;
16299 force_automatic_it_block_close (void)
16301 if (now_it.state == AUTOMATIC_IT_BLOCK)
16303 close_automatic_it_block ();
16304 now_it.state = OUTSIDE_IT_BLOCK;
16312 if (!now_it.state_handled)
16313 handle_it_state ();
16315 return now_it.state != OUTSIDE_IT_BLOCK;
16319 md_assemble (char *str)
16322 const struct asm_opcode * opcode;
16324 /* Align the previous label if needed. */
16325 if (last_label_seen != NULL)
16327 symbol_set_frag (last_label_seen, frag_now);
16328 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16329 S_SET_SEGMENT (last_label_seen, now_seg);
16332 memset (&inst, '\0', sizeof (inst));
16333 inst.reloc.type = BFD_RELOC_UNUSED;
16335 opcode = opcode_lookup (&p);
16338 /* It wasn't an instruction, but it might be a register alias of
16339 the form alias .req reg, or a Neon .dn/.qn directive. */
16340 if (! create_register_alias (str, p)
16341 && ! create_neon_reg_alias (str, p))
16342 as_bad (_("bad instruction `%s'"), str);
16347 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16348 as_warn (_("s suffix on comparison instruction is deprecated"));
16350 /* The value which unconditional instructions should have in place of the
16351 condition field. */
16352 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16356 arm_feature_set variant;
16358 variant = cpu_variant;
16359 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16360 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16361 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16362 /* Check that this instruction is supported for this CPU. */
16363 if (!opcode->tvariant
16364 || (thumb_mode == 1
16365 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16367 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16370 if (inst.cond != COND_ALWAYS && !unified_syntax
16371 && opcode->tencode != do_t_branch)
16373 as_bad (_("Thumb does not support conditional execution"));
16377 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16379 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16380 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16381 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16383 /* Two things are addressed here.
16384 1) Implicit require narrow instructions on Thumb-1.
16385 This avoids relaxation accidentally introducing Thumb-2
16387 2) Reject wide instructions in non Thumb-2 cores. */
16388 if (inst.size_req == 0)
16390 else if (inst.size_req == 4)
16392 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16398 inst.instruction = opcode->tvalue;
16400 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16402 /* Prepare the it_insn_type for those encodings that don't set
16404 it_fsm_pre_encode ();
16406 opcode->tencode ();
16408 it_fsm_post_encode ();
16411 if (!(inst.error || inst.relax))
16413 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16414 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16415 if (inst.size_req && inst.size_req != inst.size)
16417 as_bad (_("cannot honor width suffix -- `%s'"), str);
16422 /* Something has gone badly wrong if we try to relax a fixed size
16424 gas_assert (inst.size_req == 0 || !inst.relax);
16426 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16427 *opcode->tvariant);
16428 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16429 set those bits when Thumb-2 32-bit instructions are seen. ie.
16430 anything other than bl/blx and v6-M instructions.
16431 This is overly pessimistic for relaxable instructions. */
16432 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16434 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16435 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16436 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16439 check_neon_suffixes;
16443 mapping_state (MAP_THUMB);
16446 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16450 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16451 is_bx = (opcode->aencode == do_bx);
16453 /* Check that this instruction is supported for this CPU. */
16454 if (!(is_bx && fix_v4bx)
16455 && !(opcode->avariant &&
16456 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16458 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16463 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16467 inst.instruction = opcode->avalue;
16468 if (opcode->tag == OT_unconditionalF)
16469 inst.instruction |= 0xF << 28;
16471 inst.instruction |= inst.cond << 28;
16472 inst.size = INSN_SIZE;
16473 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16475 it_fsm_pre_encode ();
16476 opcode->aencode ();
16477 it_fsm_post_encode ();
16479 /* Arm mode bx is marked as both v4T and v5 because it's still required
16480 on a hypothetical non-thumb v5 core. */
16482 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16484 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16485 *opcode->avariant);
16487 check_neon_suffixes;
16491 mapping_state (MAP_ARM);
16496 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16504 check_it_blocks_finished (void)
16509 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16510 if (seg_info (sect)->tc_segment_info_data.current_it.state
16511 == MANUAL_IT_BLOCK)
16513 as_warn (_("section '%s' finished with an open IT block."),
16517 if (now_it.state == MANUAL_IT_BLOCK)
16518 as_warn (_("file finished with an open IT block."));
16522 /* Various frobbings of labels and their addresses. */
16525 arm_start_line_hook (void)
16527 last_label_seen = NULL;
16531 arm_frob_label (symbolS * sym)
16533 last_label_seen = sym;
16535 ARM_SET_THUMB (sym, thumb_mode);
16537 #if defined OBJ_COFF || defined OBJ_ELF
16538 ARM_SET_INTERWORK (sym, support_interwork);
16541 force_automatic_it_block_close ();
16543 /* Note - do not allow local symbols (.Lxxx) to be labelled
16544 as Thumb functions. This is because these labels, whilst
16545 they exist inside Thumb code, are not the entry points for
16546 possible ARM->Thumb calls. Also, these labels can be used
16547 as part of a computed goto or switch statement. eg gcc
16548 can generate code that looks like this:
16550 ldr r2, [pc, .Laaa]
16560 The first instruction loads the address of the jump table.
16561 The second instruction converts a table index into a byte offset.
16562 The third instruction gets the jump address out of the table.
16563 The fourth instruction performs the jump.
16565 If the address stored at .Laaa is that of a symbol which has the
16566 Thumb_Func bit set, then the linker will arrange for this address
16567 to have the bottom bit set, which in turn would mean that the
16568 address computation performed by the third instruction would end
16569 up with the bottom bit set. Since the ARM is capable of unaligned
16570 word loads, the instruction would then load the incorrect address
16571 out of the jump table, and chaos would ensue. */
16572 if (label_is_thumb_function_name
16573 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16574 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16576 /* When the address of a Thumb function is taken the bottom
16577 bit of that address should be set. This will allow
16578 interworking between Arm and Thumb functions to work
16581 THUMB_SET_FUNC (sym, 1);
16583 label_is_thumb_function_name = FALSE;
16586 dwarf2_emit_label (sym);
16590 arm_data_in_code (void)
16592 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16594 *input_line_pointer = '/';
16595 input_line_pointer += 5;
16596 *input_line_pointer = 0;
16604 arm_canonicalize_symbol_name (char * name)
16608 if (thumb_mode && (len = strlen (name)) > 5
16609 && streq (name + len - 5, "/data"))
16610 *(name + len - 5) = 0;
16615 /* Table of all register names defined by default. The user can
16616 define additional names with .req. Note that all register names
16617 should appear in both upper and lowercase variants. Some registers
16618 also have mixed-case names. */
16620 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16621 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16622 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16623 #define REGSET(p,t) \
16624 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16625 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16626 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16627 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16628 #define REGSETH(p,t) \
16629 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16630 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16631 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16632 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16633 #define REGSET2(p,t) \
16634 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16635 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16636 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16637 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16638 #define SPLRBANK(base,bank,t) \
16639 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16640 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16641 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16642 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16643 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16644 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16646 static const struct reg_entry reg_names[] =
16648 /* ARM integer registers. */
16649 REGSET(r, RN), REGSET(R, RN),
16651 /* ATPCS synonyms. */
16652 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16653 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16654 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16656 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16657 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16658 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16660 /* Well-known aliases. */
16661 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16662 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16664 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16665 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16667 /* Coprocessor numbers. */
16668 REGSET(p, CP), REGSET(P, CP),
16670 /* Coprocessor register numbers. The "cr" variants are for backward
16672 REGSET(c, CN), REGSET(C, CN),
16673 REGSET(cr, CN), REGSET(CR, CN),
16675 /* ARM banked registers. */
16676 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16677 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16678 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16679 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16680 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16681 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16682 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16684 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16685 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16686 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16687 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16688 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16689 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16690 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16691 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16693 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16694 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16695 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16696 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16697 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16698 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16699 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16700 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16701 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16703 /* FPA registers. */
16704 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16705 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16707 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16708 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16710 /* VFP SP registers. */
16711 REGSET(s,VFS), REGSET(S,VFS),
16712 REGSETH(s,VFS), REGSETH(S,VFS),
16714 /* VFP DP Registers. */
16715 REGSET(d,VFD), REGSET(D,VFD),
16716 /* Extra Neon DP registers. */
16717 REGSETH(d,VFD), REGSETH(D,VFD),
16719 /* Neon QP registers. */
16720 REGSET2(q,NQ), REGSET2(Q,NQ),
16722 /* VFP control registers. */
16723 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16724 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16725 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16726 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16727 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16728 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16730 /* Maverick DSP coprocessor registers. */
16731 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16732 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16734 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16735 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16736 REGDEF(dspsc,0,DSPSC),
16738 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16739 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16740 REGDEF(DSPSC,0,DSPSC),
16742 /* iWMMXt data registers - p0, c0-15. */
16743 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16745 /* iWMMXt control registers - p1, c0-3. */
16746 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16747 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16748 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16749 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16751 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16752 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16753 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16754 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16755 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16757 /* XScale accumulator registers. */
16758 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16764 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16765 within psr_required_here. */
16766 static const struct asm_psr psrs[] =
16768 /* Backward compatibility notation. Note that "all" is no longer
16769 truly all possible PSR bits. */
16770 {"all", PSR_c | PSR_f},
16774 /* Individual flags. */
16780 /* Combinations of flags. */
16781 {"fs", PSR_f | PSR_s},
16782 {"fx", PSR_f | PSR_x},
16783 {"fc", PSR_f | PSR_c},
16784 {"sf", PSR_s | PSR_f},
16785 {"sx", PSR_s | PSR_x},
16786 {"sc", PSR_s | PSR_c},
16787 {"xf", PSR_x | PSR_f},
16788 {"xs", PSR_x | PSR_s},
16789 {"xc", PSR_x | PSR_c},
16790 {"cf", PSR_c | PSR_f},
16791 {"cs", PSR_c | PSR_s},
16792 {"cx", PSR_c | PSR_x},
16793 {"fsx", PSR_f | PSR_s | PSR_x},
16794 {"fsc", PSR_f | PSR_s | PSR_c},
16795 {"fxs", PSR_f | PSR_x | PSR_s},
16796 {"fxc", PSR_f | PSR_x | PSR_c},
16797 {"fcs", PSR_f | PSR_c | PSR_s},
16798 {"fcx", PSR_f | PSR_c | PSR_x},
16799 {"sfx", PSR_s | PSR_f | PSR_x},
16800 {"sfc", PSR_s | PSR_f | PSR_c},
16801 {"sxf", PSR_s | PSR_x | PSR_f},
16802 {"sxc", PSR_s | PSR_x | PSR_c},
16803 {"scf", PSR_s | PSR_c | PSR_f},
16804 {"scx", PSR_s | PSR_c | PSR_x},
16805 {"xfs", PSR_x | PSR_f | PSR_s},
16806 {"xfc", PSR_x | PSR_f | PSR_c},
16807 {"xsf", PSR_x | PSR_s | PSR_f},
16808 {"xsc", PSR_x | PSR_s | PSR_c},
16809 {"xcf", PSR_x | PSR_c | PSR_f},
16810 {"xcs", PSR_x | PSR_c | PSR_s},
16811 {"cfs", PSR_c | PSR_f | PSR_s},
16812 {"cfx", PSR_c | PSR_f | PSR_x},
16813 {"csf", PSR_c | PSR_s | PSR_f},
16814 {"csx", PSR_c | PSR_s | PSR_x},
16815 {"cxf", PSR_c | PSR_x | PSR_f},
16816 {"cxs", PSR_c | PSR_x | PSR_s},
16817 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16818 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16819 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16820 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16821 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16822 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16823 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16824 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16825 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16826 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16827 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16828 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16829 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16830 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16831 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16832 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16833 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16834 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16835 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16836 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16837 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16838 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16839 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16840 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16843 /* Table of V7M psr names. */
16844 static const struct asm_psr v7m_psrs[] =
16846 {"apsr", 0 }, {"APSR", 0 },
16847 {"iapsr", 1 }, {"IAPSR", 1 },
16848 {"eapsr", 2 }, {"EAPSR", 2 },
16849 {"psr", 3 }, {"PSR", 3 },
16850 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16851 {"ipsr", 5 }, {"IPSR", 5 },
16852 {"epsr", 6 }, {"EPSR", 6 },
16853 {"iepsr", 7 }, {"IEPSR", 7 },
16854 {"msp", 8 }, {"MSP", 8 },
16855 {"psp", 9 }, {"PSP", 9 },
16856 {"primask", 16}, {"PRIMASK", 16},
16857 {"basepri", 17}, {"BASEPRI", 17},
16858 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16859 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16860 {"faultmask", 19}, {"FAULTMASK", 19},
16861 {"control", 20}, {"CONTROL", 20}
16864 /* Table of all shift-in-operand names. */
16865 static const struct asm_shift_name shift_names [] =
16867 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16868 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16869 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16870 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16871 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16872 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16875 /* Table of all explicit relocation names. */
16877 static struct reloc_entry reloc_names[] =
16879 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16880 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16881 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16882 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16883 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16884 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16885 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16886 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16887 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16888 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16889 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16890 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16891 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16892 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16893 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16894 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16895 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16896 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16900 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16901 static const struct asm_cond conds[] =
16905 {"cs", 0x2}, {"hs", 0x2},
16906 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16920 static struct asm_barrier_opt barrier_opt_names[] =
16922 { "sy", 0xf }, { "SY", 0xf },
16923 { "un", 0x7 }, { "UN", 0x7 },
16924 { "st", 0xe }, { "ST", 0xe },
16925 { "unst", 0x6 }, { "UNST", 0x6 },
16926 { "ish", 0xb }, { "ISH", 0xb },
16927 { "sh", 0xb }, { "SH", 0xb },
16928 { "ishst", 0xa }, { "ISHST", 0xa },
16929 { "shst", 0xa }, { "SHST", 0xa },
16930 { "nsh", 0x7 }, { "NSH", 0x7 },
16931 { "nshst", 0x6 }, { "NSHST", 0x6 },
16932 { "osh", 0x3 }, { "OSH", 0x3 },
16933 { "oshst", 0x2 }, { "OSHST", 0x2 }
16936 /* Table of ARM-format instructions. */
16938 /* Macros for gluing together operand strings. N.B. In all cases
16939 other than OPS0, the trailing OP_stop comes from default
16940 zero-initialization of the unspecified elements of the array. */
16941 #define OPS0() { OP_stop, }
16942 #define OPS1(a) { OP_##a, }
16943 #define OPS2(a,b) { OP_##a,OP_##b, }
16944 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16945 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16946 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16947 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16949 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16950 This is useful when mixing operands for ARM and THUMB, i.e. using the
16951 MIX_ARM_THUMB_OPERANDS macro.
16952 In order to use these macros, prefix the number of operands with _
16954 #define OPS_1(a) { a, }
16955 #define OPS_2(a,b) { a,b, }
16956 #define OPS_3(a,b,c) { a,b,c, }
16957 #define OPS_4(a,b,c,d) { a,b,c,d, }
16958 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16959 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16961 /* These macros abstract out the exact format of the mnemonic table and
16962 save some repeated characters. */
16964 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16965 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16966 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16967 THUMB_VARIANT, do_##ae, do_##te }
16969 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16970 a T_MNEM_xyz enumerator. */
16971 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16972 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16973 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16974 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16976 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16977 infix after the third character. */
16978 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16979 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16980 THUMB_VARIANT, do_##ae, do_##te }
16981 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16982 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16983 THUMB_VARIANT, do_##ae, do_##te }
16984 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16985 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16986 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16987 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16988 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16989 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16990 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16991 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16993 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16994 appear in the condition table. */
16995 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16996 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16997 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16999 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17000 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17001 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17002 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17003 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17004 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17005 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17006 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17007 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17008 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17009 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17010 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17011 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17012 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17013 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17014 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17015 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17016 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17017 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17018 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17020 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17021 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17022 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17023 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17025 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17026 field is still 0xE. Many of the Thumb variants can be executed
17027 conditionally, so this is checked separately. */
17028 #define TUE(mnem, op, top, nops, ops, ae, te) \
17029 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17030 THUMB_VARIANT, do_##ae, do_##te }
17032 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17033 condition code field. */
17034 #define TUF(mnem, op, top, nops, ops, ae, te) \
17035 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17036 THUMB_VARIANT, do_##ae, do_##te }
17038 /* ARM-only variants of all the above. */
17039 #define CE(mnem, op, nops, ops, ae) \
17040 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17042 #define C3(mnem, op, nops, ops, ae) \
17043 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17045 /* Legacy mnemonics that always have conditional infix after the third
17047 #define CL(mnem, op, nops, ops, ae) \
17048 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17049 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17051 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17052 #define cCE(mnem, op, nops, ops, ae) \
17053 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17055 /* Legacy coprocessor instructions where conditional infix and conditional
17056 suffix are ambiguous. For consistency this includes all FPA instructions,
17057 not just the potentially ambiguous ones. */
17058 #define cCL(mnem, op, nops, ops, ae) \
17059 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17060 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17062 /* Coprocessor, takes either a suffix or a position-3 infix
17063 (for an FPA corner case). */
17064 #define C3E(mnem, op, nops, ops, ae) \
17065 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17066 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17068 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17069 { m1 #m2 m3, OPS##nops ops, \
17070 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17071 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17073 #define CM(m1, m2, op, nops, ops, ae) \
17074 xCM_ (m1, , m2, op, nops, ops, ae), \
17075 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17076 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17077 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17078 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17079 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17080 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17081 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17082 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17083 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17084 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17085 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17086 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17087 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17088 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17089 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17090 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17091 xCM_ (m1, le, m2, op, nops, ops, ae), \
17092 xCM_ (m1, al, m2, op, nops, ops, ae)
17094 #define UE(mnem, op, nops, ops, ae) \
17095 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17097 #define UF(mnem, op, nops, ops, ae) \
17098 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17100 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17101 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17102 use the same encoding function for each. */
17103 #define NUF(mnem, op, nops, ops, enc) \
17104 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17105 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17107 /* Neon data processing, version which indirects through neon_enc_tab for
17108 the various overloaded versions of opcodes. */
17109 #define nUF(mnem, op, nops, ops, enc) \
17110 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17111 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17113 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17115 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17116 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17117 THUMB_VARIANT, do_##enc, do_##enc }
17119 #define NCE(mnem, op, nops, ops, enc) \
17120 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17122 #define NCEF(mnem, op, nops, ops, enc) \
17123 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17125 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17126 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17127 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17128 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17130 #define nCE(mnem, op, nops, ops, enc) \
17131 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17133 #define nCEF(mnem, op, nops, ops, enc) \
17134 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17138 static const struct asm_opcode insns[] =
17140 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17141 #define THUMB_VARIANT &arm_ext_v4t
17142 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17143 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17144 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17145 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17146 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17147 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17148 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17149 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17150 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17151 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17152 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17153 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17154 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17155 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17156 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17157 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17159 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17160 for setting PSR flag bits. They are obsolete in V6 and do not
17161 have Thumb equivalents. */
17162 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17163 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17164 CL("tstp", 110f000, 2, (RR, SH), cmp),
17165 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17166 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17167 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17168 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17169 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17170 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17172 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17173 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17174 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17175 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17177 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17178 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17179 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17181 OP_ADDRGLDR),ldst, t_ldst),
17182 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17184 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17185 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17186 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17187 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17188 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17189 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17191 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17192 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17193 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17194 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17197 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17198 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17199 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17201 /* Thumb-compatibility pseudo ops. */
17202 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17203 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17204 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17205 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17206 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17207 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17208 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17209 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17210 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17211 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17212 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17213 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17215 /* These may simplify to neg. */
17216 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17217 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17219 #undef THUMB_VARIANT
17220 #define THUMB_VARIANT & arm_ext_v6
17222 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17224 /* V1 instructions with no Thumb analogue prior to V6T2. */
17225 #undef THUMB_VARIANT
17226 #define THUMB_VARIANT & arm_ext_v6t2
17228 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17229 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17230 CL("teqp", 130f000, 2, (RR, SH), cmp),
17232 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17233 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17234 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17235 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17237 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17238 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17240 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17241 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17243 /* V1 instructions with no Thumb analogue at all. */
17244 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17245 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17247 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17248 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17249 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17250 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17251 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17252 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17253 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17254 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17257 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17258 #undef THUMB_VARIANT
17259 #define THUMB_VARIANT & arm_ext_v4t
17261 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17262 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17264 #undef THUMB_VARIANT
17265 #define THUMB_VARIANT & arm_ext_v6t2
17267 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17268 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17270 /* Generic coprocessor instructions. */
17271 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17272 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17273 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17274 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17275 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17276 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17277 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17280 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17282 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17283 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17286 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17287 #undef THUMB_VARIANT
17288 #define THUMB_VARIANT & arm_ext_msr
17290 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17291 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17294 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17295 #undef THUMB_VARIANT
17296 #define THUMB_VARIANT & arm_ext_v6t2
17298 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17299 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17300 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17301 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17302 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17303 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17304 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17305 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17308 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17309 #undef THUMB_VARIANT
17310 #define THUMB_VARIANT & arm_ext_v4t
17312 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17313 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17314 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17315 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17316 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17317 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17320 #define ARM_VARIANT & arm_ext_v4t_5
17322 /* ARM Architecture 4T. */
17323 /* Note: bx (and blx) are required on V5, even if the processor does
17324 not support Thumb. */
17325 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17328 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17329 #undef THUMB_VARIANT
17330 #define THUMB_VARIANT & arm_ext_v5t
17332 /* Note: blx has 2 variants; the .value coded here is for
17333 BLX(2). Only this variant has conditional execution. */
17334 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17335 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17337 #undef THUMB_VARIANT
17338 #define THUMB_VARIANT & arm_ext_v6t2
17340 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17341 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17342 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17343 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17344 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17345 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17346 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17347 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17350 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17351 #undef THUMB_VARIANT
17352 #define THUMB_VARIANT &arm_ext_v5exp
17354 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17355 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17356 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17357 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17359 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17360 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17362 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17363 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17364 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17365 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17367 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17368 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17369 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17370 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17372 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17373 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17375 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17376 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17377 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17378 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17381 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17382 #undef THUMB_VARIANT
17383 #define THUMB_VARIANT &arm_ext_v6t2
17385 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17386 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17388 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17389 ADDRGLDRS), ldrd, t_ldstd),
17391 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17392 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17395 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17397 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17400 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17401 #undef THUMB_VARIANT
17402 #define THUMB_VARIANT & arm_ext_v6
17404 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17405 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17406 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17407 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17408 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17409 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17410 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17411 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17412 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17413 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17415 #undef THUMB_VARIANT
17416 #define THUMB_VARIANT & arm_ext_v6t2
17418 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17419 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17421 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17422 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17424 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17425 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17427 /* ARM V6 not included in V7M. */
17428 #undef THUMB_VARIANT
17429 #define THUMB_VARIANT & arm_ext_v6_notm
17430 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17431 UF(rfeib, 9900a00, 1, (RRw), rfe),
17432 UF(rfeda, 8100a00, 1, (RRw), rfe),
17433 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17434 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17435 UF(rfefa, 9900a00, 1, (RRw), rfe),
17436 UF(rfeea, 8100a00, 1, (RRw), rfe),
17437 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17438 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17439 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17440 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17441 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17443 /* ARM V6 not included in V7M (eg. integer SIMD). */
17444 #undef THUMB_VARIANT
17445 #define THUMB_VARIANT & arm_ext_v6_dsp
17446 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17447 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17448 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17449 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17450 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17451 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17452 /* Old name for QASX. */
17453 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17454 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17455 /* Old name for QSAX. */
17456 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17457 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17458 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17459 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17460 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17461 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17462 /* Old name for SASX. */
17463 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17464 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17465 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17466 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17467 /* Old name for SHASX. */
17468 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17469 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17470 /* Old name for SHSAX. */
17471 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17472 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17473 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17474 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17475 /* Old name for SSAX. */
17476 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17477 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17478 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17479 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17480 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17481 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17482 /* Old name for UASX. */
17483 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17484 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17485 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17486 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17487 /* Old name for UHASX. */
17488 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17489 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17490 /* Old name for UHSAX. */
17491 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17492 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17493 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17494 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17495 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17496 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17497 /* Old name for UQASX. */
17498 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17499 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17500 /* Old name for UQSAX. */
17501 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17502 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17503 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17504 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17505 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17506 /* Old name for USAX. */
17507 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17508 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17509 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17510 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17511 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17512 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17513 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17514 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17515 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17516 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17517 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17518 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17519 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17520 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17521 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17522 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17523 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17524 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17525 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17526 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17527 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17528 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17529 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17530 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17531 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17532 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17533 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17534 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17535 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17536 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17537 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17538 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17539 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17540 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17543 #define ARM_VARIANT & arm_ext_v6k
17544 #undef THUMB_VARIANT
17545 #define THUMB_VARIANT & arm_ext_v6k
17547 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17548 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17549 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17550 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17552 #undef THUMB_VARIANT
17553 #define THUMB_VARIANT & arm_ext_v6_notm
17554 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17556 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17557 RRnpcb), strexd, t_strexd),
17559 #undef THUMB_VARIANT
17560 #define THUMB_VARIANT & arm_ext_v6t2
17561 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17563 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17565 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17567 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17569 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17572 #define ARM_VARIANT & arm_ext_sec
17573 #undef THUMB_VARIANT
17574 #define THUMB_VARIANT & arm_ext_sec
17576 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17579 #define ARM_VARIANT & arm_ext_virt
17580 #undef THUMB_VARIANT
17581 #define THUMB_VARIANT & arm_ext_virt
17583 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17584 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17587 #define ARM_VARIANT & arm_ext_v6t2
17588 #undef THUMB_VARIANT
17589 #define THUMB_VARIANT & arm_ext_v6t2
17591 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17592 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17593 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17594 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17596 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17597 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17598 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17599 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17601 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17602 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17603 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17604 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17606 /* Thumb-only instructions. */
17608 #define ARM_VARIANT NULL
17609 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17610 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17612 /* ARM does not really have an IT instruction, so always allow it.
17613 The opcode is copied from Thumb in order to allow warnings in
17614 -mimplicit-it=[never | arm] modes. */
17616 #define ARM_VARIANT & arm_ext_v1
17618 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17619 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17620 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17621 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17622 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17623 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17624 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17625 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17626 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17627 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17628 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17629 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17630 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17631 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17632 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17633 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17634 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17635 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17637 /* Thumb2 only instructions. */
17639 #define ARM_VARIANT NULL
17641 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17642 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17643 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17644 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17645 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17646 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17648 /* Hardware division instructions. */
17650 #define ARM_VARIANT & arm_ext_adiv
17651 #undef THUMB_VARIANT
17652 #define THUMB_VARIANT & arm_ext_div
17654 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17655 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17657 /* ARM V6M/V7 instructions. */
17659 #define ARM_VARIANT & arm_ext_barrier
17660 #undef THUMB_VARIANT
17661 #define THUMB_VARIANT & arm_ext_barrier
17663 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17664 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17665 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17667 /* ARM V7 instructions. */
17669 #define ARM_VARIANT & arm_ext_v7
17670 #undef THUMB_VARIANT
17671 #define THUMB_VARIANT & arm_ext_v7
17673 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17674 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17677 #define ARM_VARIANT & arm_ext_mp
17678 #undef THUMB_VARIANT
17679 #define THUMB_VARIANT & arm_ext_mp
17681 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17684 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17686 cCE("wfs", e200110, 1, (RR), rd),
17687 cCE("rfs", e300110, 1, (RR), rd),
17688 cCE("wfc", e400110, 1, (RR), rd),
17689 cCE("rfc", e500110, 1, (RR), rd),
17691 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17692 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17693 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17694 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17696 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17697 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17698 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17699 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17701 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17702 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17703 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17704 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17705 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17706 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17707 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17708 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17709 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17710 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17711 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17712 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17714 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17715 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17716 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17717 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17718 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17719 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17720 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17721 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17722 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17723 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17724 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17725 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17727 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17728 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17729 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17730 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17731 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17732 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17733 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17734 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17735 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17736 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17737 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17738 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17740 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17741 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17742 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17743 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17744 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17745 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17746 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17747 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17748 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17749 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17750 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17751 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17753 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17754 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17755 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17756 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17757 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17758 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17759 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17760 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17761 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17762 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17763 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17764 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17766 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17767 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17768 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17769 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17770 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17771 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17772 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17773 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17774 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17775 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17776 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17777 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17779 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17780 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17781 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17782 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17783 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17784 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17785 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17786 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17787 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17788 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17789 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17790 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17792 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17793 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17794 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17795 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17796 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17797 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17798 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17799 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17800 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17801 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17802 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17803 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17805 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17806 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17807 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17808 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17809 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17810 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17811 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17812 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17813 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17814 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17815 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17816 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17818 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17819 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17820 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17821 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17822 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17823 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17824 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17825 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17826 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17827 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17828 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17829 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17831 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17832 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17833 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17834 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17835 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17836 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17837 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17838 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17839 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17840 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17841 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17842 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17844 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17845 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17846 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17847 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17848 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17849 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17850 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17851 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17852 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17853 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17854 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17855 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17857 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17858 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17859 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17860 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17861 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17862 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17863 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17864 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17865 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17866 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17867 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17868 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17870 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17871 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17872 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17873 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17874 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17875 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17876 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17877 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17878 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17879 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17880 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17881 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17883 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17884 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17885 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17886 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17887 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17888 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17889 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17890 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17891 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17892 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17893 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17894 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17896 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17897 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17898 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17899 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17900 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17901 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17902 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17903 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17904 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17905 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17906 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17907 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17909 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17910 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17911 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17912 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17913 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17914 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17915 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17916 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17917 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17918 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17919 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17920 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17922 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17923 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17924 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17936 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17949 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17958 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17961 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17962 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17963 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17965 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17971 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17974 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17975 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17976 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17978 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17984 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
17987 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
17988 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18001 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18014 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18027 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18040 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18053 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18065 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18066 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18067 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18069 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18070 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18078 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18079 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18080 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18081 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18083 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18084 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18085 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18086 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18087 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18088 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18089 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18090 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18091 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18092 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18093 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18094 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18096 /* The implementation of the FIX instruction is broken on some
18097 assemblers, in that it accepts a precision specifier as well as a
18098 rounding specifier, despite the fact that this is meaningless.
18099 To be more compatible, we accept it as well, though of course it
18100 does not set any bits. */
18101 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18102 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18103 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18104 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18105 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18106 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18107 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18108 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18109 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18110 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18111 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18112 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18113 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18115 /* Instructions that were new with the real FPA, call them V2. */
18117 #define ARM_VARIANT & fpu_fpa_ext_v2
18119 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18120 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18121 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18122 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18123 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18124 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18127 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18129 /* Moves and type conversions. */
18130 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18131 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18132 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18133 cCE("fmstat", ef1fa10, 0, (), noargs),
18134 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18135 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18136 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18137 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18138 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18139 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18140 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18141 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18142 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18143 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18145 /* Memory operations. */
18146 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18147 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18148 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18149 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18150 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18151 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18152 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18153 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18154 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18155 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18156 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18157 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18158 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18159 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18160 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18161 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18162 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18163 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18165 /* Monadic operations. */
18166 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18167 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18168 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18170 /* Dyadic operations. */
18171 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18172 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18173 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18174 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18175 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18176 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18177 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18178 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18179 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18182 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18183 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18184 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18185 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18187 /* Double precision load/store are still present on single precision
18188 implementations. */
18189 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18190 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18191 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18192 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18193 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18194 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18195 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18196 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18197 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18198 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18201 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18203 /* Moves and type conversions. */
18204 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18205 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18206 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18207 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18208 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18209 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18210 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18211 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18212 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18213 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18214 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18215 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18216 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18218 /* Monadic operations. */
18219 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18220 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18221 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18223 /* Dyadic operations. */
18224 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18225 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18226 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18227 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18228 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18229 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18230 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18231 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18232 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18235 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18236 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18237 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18238 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18241 #define ARM_VARIANT & fpu_vfp_ext_v2
18243 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18244 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18245 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18246 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18248 /* Instructions which may belong to either the Neon or VFP instruction sets.
18249 Individual encoder functions perform additional architecture checks. */
18251 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18252 #undef THUMB_VARIANT
18253 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18255 /* These mnemonics are unique to VFP. */
18256 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18257 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18258 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18259 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18260 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18261 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18262 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18263 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18264 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18265 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18267 /* Mnemonics shared by Neon and VFP. */
18268 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18269 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18270 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18272 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18273 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18275 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18276 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18278 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18279 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18280 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18281 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18282 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18283 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18284 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18285 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18287 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18288 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18289 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18290 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18293 /* NOTE: All VMOV encoding is special-cased! */
18294 NCE(vmov, 0, 1, (VMOV), neon_mov),
18295 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18297 #undef THUMB_VARIANT
18298 #define THUMB_VARIANT & fpu_neon_ext_v1
18300 #define ARM_VARIANT & fpu_neon_ext_v1
18302 /* Data processing with three registers of the same length. */
18303 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18304 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18305 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18306 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18307 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18308 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18309 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18310 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18311 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18312 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18313 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18314 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18315 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18316 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18317 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18318 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18319 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18320 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18321 /* If not immediate, fall back to neon_dyadic_i64_su.
18322 shl_imm should accept I8 I16 I32 I64,
18323 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18324 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18325 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18326 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18327 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18328 /* Logic ops, types optional & ignored. */
18329 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18330 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18331 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18332 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18333 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18334 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18335 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18336 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18337 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18338 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18339 /* Bitfield ops, untyped. */
18340 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18341 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18342 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18343 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18344 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18345 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18346 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18347 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18348 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18349 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18350 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18351 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18352 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18353 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18354 back to neon_dyadic_if_su. */
18355 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18356 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18357 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18358 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18359 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18360 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18361 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18362 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18363 /* Comparison. Type I8 I16 I32 F32. */
18364 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18365 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18366 /* As above, D registers only. */
18367 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18368 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18369 /* Int and float variants, signedness unimportant. */
18370 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18371 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18372 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18373 /* Add/sub take types I8 I16 I32 I64 F32. */
18374 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18375 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18376 /* vtst takes sizes 8, 16, 32. */
18377 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18378 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18379 /* VMUL takes I8 I16 I32 F32 P8. */
18380 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18381 /* VQD{R}MULH takes S16 S32. */
18382 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18383 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18384 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18385 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18386 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18387 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18388 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18389 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18390 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18391 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18392 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18393 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18394 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18395 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18396 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18397 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18399 /* Two address, int/float. Types S8 S16 S32 F32. */
18400 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18401 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18403 /* Data processing with two registers and a shift amount. */
18404 /* Right shifts, and variants with rounding.
18405 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18406 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18407 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18408 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18409 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18410 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18411 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18412 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18413 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18414 /* Shift and insert. Sizes accepted 8 16 32 64. */
18415 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18416 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18417 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18418 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18419 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18420 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18421 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18422 /* Right shift immediate, saturating & narrowing, with rounding variants.
18423 Types accepted S16 S32 S64 U16 U32 U64. */
18424 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18425 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18426 /* As above, unsigned. Types accepted S16 S32 S64. */
18427 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18428 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18429 /* Right shift narrowing. Types accepted I16 I32 I64. */
18430 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18431 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18432 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18433 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18434 /* CVT with optional immediate for fixed-point variant. */
18435 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18437 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18438 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18440 /* Data processing, three registers of different lengths. */
18441 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18442 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18443 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18444 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18445 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18446 /* If not scalar, fall back to neon_dyadic_long.
18447 Vector types as above, scalar types S16 S32 U16 U32. */
18448 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18449 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18450 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18451 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18452 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18453 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18454 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18455 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18456 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18457 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18458 /* Saturating doubling multiplies. Types S16 S32. */
18459 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18460 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18461 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18462 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18463 S16 S32 U16 U32. */
18464 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18466 /* Extract. Size 8. */
18467 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18468 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18470 /* Two registers, miscellaneous. */
18471 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18472 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18473 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18474 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18475 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18476 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18477 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18478 /* Vector replicate. Sizes 8 16 32. */
18479 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18480 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18481 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18482 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18483 /* VMOVN. Types I16 I32 I64. */
18484 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18485 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18486 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18487 /* VQMOVUN. Types S16 S32 S64. */
18488 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18489 /* VZIP / VUZP. Sizes 8 16 32. */
18490 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18491 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18492 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18493 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18494 /* VQABS / VQNEG. Types S8 S16 S32. */
18495 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18496 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18497 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18498 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18499 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18500 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18501 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18502 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18503 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18504 /* Reciprocal estimates. Types U32 F32. */
18505 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18506 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18507 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18508 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18509 /* VCLS. Types S8 S16 S32. */
18510 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18511 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18512 /* VCLZ. Types I8 I16 I32. */
18513 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18514 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18515 /* VCNT. Size 8. */
18516 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18517 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18518 /* Two address, untyped. */
18519 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18520 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18521 /* VTRN. Sizes 8 16 32. */
18522 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18523 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18525 /* Table lookup. Size 8. */
18526 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18527 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18529 #undef THUMB_VARIANT
18530 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18532 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18534 /* Neon element/structure load/store. */
18535 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18536 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18537 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18538 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18539 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18540 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18541 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18542 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18544 #undef THUMB_VARIANT
18545 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18547 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18548 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18549 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18550 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18551 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18552 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18553 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18554 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18555 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18556 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18558 #undef THUMB_VARIANT
18559 #define THUMB_VARIANT & fpu_vfp_ext_v3
18561 #define ARM_VARIANT & fpu_vfp_ext_v3
18563 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18564 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18565 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18566 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18567 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18568 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18569 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18570 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18571 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18574 #define ARM_VARIANT &fpu_vfp_ext_fma
18575 #undef THUMB_VARIANT
18576 #define THUMB_VARIANT &fpu_vfp_ext_fma
18577 /* Mnemonics shared by Neon and VFP. These are included in the
18578 VFP FMA variant; NEON and VFP FMA always includes the NEON
18579 FMA instructions. */
18580 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18581 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18582 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18583 the v form should always be used. */
18584 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18585 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18586 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18587 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18588 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18589 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18591 #undef THUMB_VARIANT
18593 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18595 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18596 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18597 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18598 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18599 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18600 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18601 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18602 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18605 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18607 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18608 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18609 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18610 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18611 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18612 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18613 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18614 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18615 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18616 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18617 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18618 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18619 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18620 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18621 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18622 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18623 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18624 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18625 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18626 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18627 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18628 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18629 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18630 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18631 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18632 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18633 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18634 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18635 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18636 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18637 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18638 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18639 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18640 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18641 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18642 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18643 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18644 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18645 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18646 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18647 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18648 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18649 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18650 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18651 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18652 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18653 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18654 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18655 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18656 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18657 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18658 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18659 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18662 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18669 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18674 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18675 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18676 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18677 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18689 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18690 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18691 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18692 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18693 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18696 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18703 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18704 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18706 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18707 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18708 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18709 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18710 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18711 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18712 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18713 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18714 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18715 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18716 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18717 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18718 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18719 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18720 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18721 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18722 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18723 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18724 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18725 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18726 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18727 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18728 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18729 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18730 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18731 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18732 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18733 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18734 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18735 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18736 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18737 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18738 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18739 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18740 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18741 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18742 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18743 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18744 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18745 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18746 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18747 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18748 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18749 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18750 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18751 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18752 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18753 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18754 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18755 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18759 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18760 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18761 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18762 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18763 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18764 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18765 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18766 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18767 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18768 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18771 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18773 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18774 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18775 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18776 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18777 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18778 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18779 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18784 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18785 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18786 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18787 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18788 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18789 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18790 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18791 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18792 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18793 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18794 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18806 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18809 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18810 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18818 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18819 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18821 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18822 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18823 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18829 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18832 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18834 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18835 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18836 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18837 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18838 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18839 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18840 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18841 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18842 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18843 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18844 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18845 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18846 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18847 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18848 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18849 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18850 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18851 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18852 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18853 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18854 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18855 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18856 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18857 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18858 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18859 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18860 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18861 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18862 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18863 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18864 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18865 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18866 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18867 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18868 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18869 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18870 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18871 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18872 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18873 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18874 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18875 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18876 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18877 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18878 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18879 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18880 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18881 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18882 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18883 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18884 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18885 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18886 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18887 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18888 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18889 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18890 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18891 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18892 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18893 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18894 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18895 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18896 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18897 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18898 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18899 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18900 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18901 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18902 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18903 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18904 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18905 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18906 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18907 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18908 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18909 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18912 #undef THUMB_VARIANT
18939 /* MD interface: bits in the object file. */
18941 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18942 for use in the a.out file, and stores them in the array pointed to by buf.
18943 This knows about the endian-ness of the target machine and does
18944 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18945 2 (short) and 4 (long) Floating numbers are put out as a series of
18946 LITTLENUMS (shorts, here at least). */
18949 md_number_to_chars (char * buf, valueT val, int n)
18951 if (target_big_endian)
18952 number_to_chars_bigendian (buf, val, n);
18954 number_to_chars_littleendian (buf, val, n);
18958 md_chars_to_number (char * buf, int n)
18961 unsigned char * where = (unsigned char *) buf;
18963 if (target_big_endian)
18968 result |= (*where++ & 255);
18976 result |= (where[n] & 255);
18983 /* MD interface: Sections. */
18985 /* Estimate the size of a frag before relaxing. Assume everything fits in
18989 md_estimate_size_before_relax (fragS * fragp,
18990 segT segtype ATTRIBUTE_UNUSED)
18996 /* Convert a machine dependent frag. */
18999 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19001 unsigned long insn;
19002 unsigned long old_op;
19010 buf = fragp->fr_literal + fragp->fr_fix;
19012 old_op = bfd_get_16(abfd, buf);
19013 if (fragp->fr_symbol)
19015 exp.X_op = O_symbol;
19016 exp.X_add_symbol = fragp->fr_symbol;
19020 exp.X_op = O_constant;
19022 exp.X_add_number = fragp->fr_offset;
19023 opcode = fragp->fr_subtype;
19026 case T_MNEM_ldr_pc:
19027 case T_MNEM_ldr_pc2:
19028 case T_MNEM_ldr_sp:
19029 case T_MNEM_str_sp:
19036 if (fragp->fr_var == 4)
19038 insn = THUMB_OP32 (opcode);
19039 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19041 insn |= (old_op & 0x700) << 4;
19045 insn |= (old_op & 7) << 12;
19046 insn |= (old_op & 0x38) << 13;
19048 insn |= 0x00000c00;
19049 put_thumb32_insn (buf, insn);
19050 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19054 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19056 pc_rel = (opcode == T_MNEM_ldr_pc2);
19059 if (fragp->fr_var == 4)
19061 insn = THUMB_OP32 (opcode);
19062 insn |= (old_op & 0xf0) << 4;
19063 put_thumb32_insn (buf, insn);
19064 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19068 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19069 exp.X_add_number -= 4;
19077 if (fragp->fr_var == 4)
19079 int r0off = (opcode == T_MNEM_mov
19080 || opcode == T_MNEM_movs) ? 0 : 8;
19081 insn = THUMB_OP32 (opcode);
19082 insn = (insn & 0xe1ffffff) | 0x10000000;
19083 insn |= (old_op & 0x700) << r0off;
19084 put_thumb32_insn (buf, insn);
19085 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19089 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19094 if (fragp->fr_var == 4)
19096 insn = THUMB_OP32(opcode);
19097 put_thumb32_insn (buf, insn);
19098 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19101 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19105 if (fragp->fr_var == 4)
19107 insn = THUMB_OP32(opcode);
19108 insn |= (old_op & 0xf00) << 14;
19109 put_thumb32_insn (buf, insn);
19110 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19113 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19116 case T_MNEM_add_sp:
19117 case T_MNEM_add_pc:
19118 case T_MNEM_inc_sp:
19119 case T_MNEM_dec_sp:
19120 if (fragp->fr_var == 4)
19122 /* ??? Choose between add and addw. */
19123 insn = THUMB_OP32 (opcode);
19124 insn |= (old_op & 0xf0) << 4;
19125 put_thumb32_insn (buf, insn);
19126 if (opcode == T_MNEM_add_pc)
19127 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19129 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19132 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19140 if (fragp->fr_var == 4)
19142 insn = THUMB_OP32 (opcode);
19143 insn |= (old_op & 0xf0) << 4;
19144 insn |= (old_op & 0xf) << 16;
19145 put_thumb32_insn (buf, insn);
19146 if (insn & (1 << 20))
19147 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19149 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19152 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19158 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19159 (enum bfd_reloc_code_real) reloc_type);
19160 fixp->fx_file = fragp->fr_file;
19161 fixp->fx_line = fragp->fr_line;
19162 fragp->fr_fix += fragp->fr_var;
19165 /* Return the size of a relaxable immediate operand instruction.
19166 SHIFT and SIZE specify the form of the allowable immediate. */
19168 relax_immediate (fragS *fragp, int size, int shift)
19174 /* ??? Should be able to do better than this. */
19175 if (fragp->fr_symbol)
19178 low = (1 << shift) - 1;
19179 mask = (1 << (shift + size)) - (1 << shift);
19180 offset = fragp->fr_offset;
19181 /* Force misaligned offsets to 32-bit variant. */
19184 if (offset & ~mask)
19189 /* Get the address of a symbol during relaxation. */
19191 relaxed_symbol_addr (fragS *fragp, long stretch)
19197 sym = fragp->fr_symbol;
19198 sym_frag = symbol_get_frag (sym);
19199 know (S_GET_SEGMENT (sym) != absolute_section
19200 || sym_frag == &zero_address_frag);
19201 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19203 /* If frag has yet to be reached on this pass, assume it will
19204 move by STRETCH just as we did. If this is not so, it will
19205 be because some frag between grows, and that will force
19209 && sym_frag->relax_marker != fragp->relax_marker)
19213 /* Adjust stretch for any alignment frag. Note that if have
19214 been expanding the earlier code, the symbol may be
19215 defined in what appears to be an earlier frag. FIXME:
19216 This doesn't handle the fr_subtype field, which specifies
19217 a maximum number of bytes to skip when doing an
19219 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19221 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19224 stretch = - ((- stretch)
19225 & ~ ((1 << (int) f->fr_offset) - 1));
19227 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19239 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19242 relax_adr (fragS *fragp, asection *sec, long stretch)
19247 /* Assume worst case for symbols not known to be in the same section. */
19248 if (fragp->fr_symbol == NULL
19249 || !S_IS_DEFINED (fragp->fr_symbol)
19250 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19251 || S_IS_WEAK (fragp->fr_symbol))
19254 val = relaxed_symbol_addr (fragp, stretch);
19255 addr = fragp->fr_address + fragp->fr_fix;
19256 addr = (addr + 4) & ~3;
19257 /* Force misaligned targets to 32-bit variant. */
19261 if (val < 0 || val > 1020)
19266 /* Return the size of a relaxable add/sub immediate instruction. */
19268 relax_addsub (fragS *fragp, asection *sec)
19273 buf = fragp->fr_literal + fragp->fr_fix;
19274 op = bfd_get_16(sec->owner, buf);
19275 if ((op & 0xf) == ((op >> 4) & 0xf))
19276 return relax_immediate (fragp, 8, 0);
19278 return relax_immediate (fragp, 3, 0);
19282 /* Return the size of a relaxable branch instruction. BITS is the
19283 size of the offset field in the narrow instruction. */
19286 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19292 /* Assume worst case for symbols not known to be in the same section. */
19293 if (!S_IS_DEFINED (fragp->fr_symbol)
19294 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19295 || S_IS_WEAK (fragp->fr_symbol))
19299 if (S_IS_DEFINED (fragp->fr_symbol)
19300 && ARM_IS_FUNC (fragp->fr_symbol))
19303 /* PR 12532. Global symbols with default visibility might
19304 be preempted, so do not relax relocations to them. */
19305 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19306 && (! S_IS_LOCAL (fragp->fr_symbol)))
19310 val = relaxed_symbol_addr (fragp, stretch);
19311 addr = fragp->fr_address + fragp->fr_fix + 4;
19314 /* Offset is a signed value *2 */
19316 if (val >= limit || val < -limit)
19322 /* Relax a machine dependent frag. This returns the amount by which
19323 the current size of the frag should change. */
19326 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19331 oldsize = fragp->fr_var;
19332 switch (fragp->fr_subtype)
19334 case T_MNEM_ldr_pc2:
19335 newsize = relax_adr (fragp, sec, stretch);
19337 case T_MNEM_ldr_pc:
19338 case T_MNEM_ldr_sp:
19339 case T_MNEM_str_sp:
19340 newsize = relax_immediate (fragp, 8, 2);
19344 newsize = relax_immediate (fragp, 5, 2);
19348 newsize = relax_immediate (fragp, 5, 1);
19352 newsize = relax_immediate (fragp, 5, 0);
19355 newsize = relax_adr (fragp, sec, stretch);
19361 newsize = relax_immediate (fragp, 8, 0);
19364 newsize = relax_branch (fragp, sec, 11, stretch);
19367 newsize = relax_branch (fragp, sec, 8, stretch);
19369 case T_MNEM_add_sp:
19370 case T_MNEM_add_pc:
19371 newsize = relax_immediate (fragp, 8, 2);
19373 case T_MNEM_inc_sp:
19374 case T_MNEM_dec_sp:
19375 newsize = relax_immediate (fragp, 7, 2);
19381 newsize = relax_addsub (fragp, sec);
19387 fragp->fr_var = newsize;
19388 /* Freeze wide instructions that are at or before the same location as
19389 in the previous pass. This avoids infinite loops.
19390 Don't freeze them unconditionally because targets may be artificially
19391 misaligned by the expansion of preceding frags. */
19392 if (stretch <= 0 && newsize > 2)
19394 md_convert_frag (sec->owner, sec, fragp);
19398 return newsize - oldsize;
19401 /* Round up a section size to the appropriate boundary. */
19404 md_section_align (segT segment ATTRIBUTE_UNUSED,
19407 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19408 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19410 /* For a.out, force the section size to be aligned. If we don't do
19411 this, BFD will align it for us, but it will not write out the
19412 final bytes of the section. This may be a bug in BFD, but it is
19413 easier to fix it here since that is how the other a.out targets
19417 align = bfd_get_section_alignment (stdoutput, segment);
19418 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19425 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19426 of an rs_align_code fragment. */
19429 arm_handle_align (fragS * fragP)
19431 static char const arm_noop[2][2][4] =
19434 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19435 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19438 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19439 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19442 static char const thumb_noop[2][2][2] =
19445 {0xc0, 0x46}, /* LE */
19446 {0x46, 0xc0}, /* BE */
19449 {0x00, 0xbf}, /* LE */
19450 {0xbf, 0x00} /* BE */
19453 static char const wide_thumb_noop[2][4] =
19454 { /* Wide Thumb-2 */
19455 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19456 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19459 unsigned bytes, fix, noop_size;
19462 const char *narrow_noop = NULL;
19467 if (fragP->fr_type != rs_align_code)
19470 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19471 p = fragP->fr_literal + fragP->fr_fix;
19474 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19475 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19477 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19479 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19481 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19483 narrow_noop = thumb_noop[1][target_big_endian];
19484 noop = wide_thumb_noop[target_big_endian];
19487 noop = thumb_noop[0][target_big_endian];
19495 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19496 [target_big_endian];
19503 fragP->fr_var = noop_size;
19505 if (bytes & (noop_size - 1))
19507 fix = bytes & (noop_size - 1);
19509 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19511 memset (p, 0, fix);
19518 if (bytes & noop_size)
19520 /* Insert a narrow noop. */
19521 memcpy (p, narrow_noop, noop_size);
19523 bytes -= noop_size;
19527 /* Use wide noops for the remainder */
19531 while (bytes >= noop_size)
19533 memcpy (p, noop, noop_size);
19535 bytes -= noop_size;
19539 fragP->fr_fix += fix;
19542 /* Called from md_do_align. Used to create an alignment
19543 frag in a code section. */
19546 arm_frag_align_code (int n, int max)
19550 /* We assume that there will never be a requirement
19551 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19552 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19557 _("alignments greater than %d bytes not supported in .text sections."),
19558 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19559 as_fatal ("%s", err_msg);
19562 p = frag_var (rs_align_code,
19563 MAX_MEM_FOR_RS_ALIGN_CODE,
19565 (relax_substateT) max,
19572 /* Perform target specific initialisation of a frag.
19573 Note - despite the name this initialisation is not done when the frag
19574 is created, but only when its type is assigned. A frag can be created
19575 and used a long time before its type is set, so beware of assuming that
19576 this initialisationis performed first. */
19580 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19582 /* Record whether this frag is in an ARM or a THUMB area. */
19583 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19586 #else /* OBJ_ELF is defined. */
19588 arm_init_frag (fragS * fragP, int max_chars)
19590 /* If the current ARM vs THUMB mode has not already
19591 been recorded into this frag then do so now. */
19592 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19594 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19596 /* Record a mapping symbol for alignment frags. We will delete this
19597 later if the alignment ends up empty. */
19598 switch (fragP->fr_type)
19601 case rs_align_test:
19603 mapping_state_2 (MAP_DATA, max_chars);
19605 case rs_align_code:
19606 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19614 /* When we change sections we need to issue a new mapping symbol. */
19617 arm_elf_change_section (void)
19619 /* Link an unlinked unwind index table section to the .text section. */
19620 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19621 && elf_linked_to_section (now_seg) == NULL)
19622 elf_linked_to_section (now_seg) = text_section;
19626 arm_elf_section_type (const char * str, size_t len)
19628 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19629 return SHT_ARM_EXIDX;
19634 /* Code to deal with unwinding tables. */
19636 static void add_unwind_adjustsp (offsetT);
19638 /* Generate any deferred unwind frame offset. */
19641 flush_pending_unwind (void)
19645 offset = unwind.pending_offset;
19646 unwind.pending_offset = 0;
19648 add_unwind_adjustsp (offset);
19651 /* Add an opcode to this list for this function. Two-byte opcodes should
19652 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19656 add_unwind_opcode (valueT op, int length)
19658 /* Add any deferred stack adjustment. */
19659 if (unwind.pending_offset)
19660 flush_pending_unwind ();
19662 unwind.sp_restored = 0;
19664 if (unwind.opcode_count + length > unwind.opcode_alloc)
19666 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19667 if (unwind.opcodes)
19668 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19669 unwind.opcode_alloc);
19671 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19676 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19678 unwind.opcode_count++;
19682 /* Add unwind opcodes to adjust the stack pointer. */
19685 add_unwind_adjustsp (offsetT offset)
19689 if (offset > 0x200)
19691 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19696 /* Long form: 0xb2, uleb128. */
19697 /* This might not fit in a word so add the individual bytes,
19698 remembering the list is built in reverse order. */
19699 o = (valueT) ((offset - 0x204) >> 2);
19701 add_unwind_opcode (0, 1);
19703 /* Calculate the uleb128 encoding of the offset. */
19707 bytes[n] = o & 0x7f;
19713 /* Add the insn. */
19715 add_unwind_opcode (bytes[n - 1], 1);
19716 add_unwind_opcode (0xb2, 1);
19718 else if (offset > 0x100)
19720 /* Two short opcodes. */
19721 add_unwind_opcode (0x3f, 1);
19722 op = (offset - 0x104) >> 2;
19723 add_unwind_opcode (op, 1);
19725 else if (offset > 0)
19727 /* Short opcode. */
19728 op = (offset - 4) >> 2;
19729 add_unwind_opcode (op, 1);
19731 else if (offset < 0)
19734 while (offset > 0x100)
19736 add_unwind_opcode (0x7f, 1);
19739 op = ((offset - 4) >> 2) | 0x40;
19740 add_unwind_opcode (op, 1);
19744 /* Finish the list of unwind opcodes for this function. */
19746 finish_unwind_opcodes (void)
19750 if (unwind.fp_used)
19752 /* Adjust sp as necessary. */
19753 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19754 flush_pending_unwind ();
19756 /* After restoring sp from the frame pointer. */
19757 op = 0x90 | unwind.fp_reg;
19758 add_unwind_opcode (op, 1);
19761 flush_pending_unwind ();
19765 /* Start an exception table entry. If idx is nonzero this is an index table
19769 start_unwind_section (const segT text_seg, int idx)
19771 const char * text_name;
19772 const char * prefix;
19773 const char * prefix_once;
19774 const char * group_name;
19778 size_t sec_name_len;
19785 prefix = ELF_STRING_ARM_unwind;
19786 prefix_once = ELF_STRING_ARM_unwind_once;
19787 type = SHT_ARM_EXIDX;
19791 prefix = ELF_STRING_ARM_unwind_info;
19792 prefix_once = ELF_STRING_ARM_unwind_info_once;
19793 type = SHT_PROGBITS;
19796 text_name = segment_name (text_seg);
19797 if (streq (text_name, ".text"))
19800 if (strncmp (text_name, ".gnu.linkonce.t.",
19801 strlen (".gnu.linkonce.t.")) == 0)
19803 prefix = prefix_once;
19804 text_name += strlen (".gnu.linkonce.t.");
19807 prefix_len = strlen (prefix);
19808 text_len = strlen (text_name);
19809 sec_name_len = prefix_len + text_len;
19810 sec_name = (char *) xmalloc (sec_name_len + 1);
19811 memcpy (sec_name, prefix, prefix_len);
19812 memcpy (sec_name + prefix_len, text_name, text_len);
19813 sec_name[prefix_len + text_len] = '\0';
19819 /* Handle COMDAT group. */
19820 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19822 group_name = elf_group_name (text_seg);
19823 if (group_name == NULL)
19825 as_bad (_("Group section `%s' has no group signature"),
19826 segment_name (text_seg));
19827 ignore_rest_of_line ();
19830 flags |= SHF_GROUP;
19834 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19836 /* Set the section link for index tables. */
19838 elf_linked_to_section (now_seg) = text_seg;
19842 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19843 personality routine data. Returns zero, or the index table value for
19844 and inline entry. */
19847 create_unwind_entry (int have_data)
19852 /* The current word of data. */
19854 /* The number of bytes left in this word. */
19857 finish_unwind_opcodes ();
19859 /* Remember the current text section. */
19860 unwind.saved_seg = now_seg;
19861 unwind.saved_subseg = now_subseg;
19863 start_unwind_section (now_seg, 0);
19865 if (unwind.personality_routine == NULL)
19867 if (unwind.personality_index == -2)
19870 as_bad (_("handlerdata in cantunwind frame"));
19871 return 1; /* EXIDX_CANTUNWIND. */
19874 /* Use a default personality routine if none is specified. */
19875 if (unwind.personality_index == -1)
19877 if (unwind.opcode_count > 3)
19878 unwind.personality_index = 1;
19880 unwind.personality_index = 0;
19883 /* Space for the personality routine entry. */
19884 if (unwind.personality_index == 0)
19886 if (unwind.opcode_count > 3)
19887 as_bad (_("too many unwind opcodes for personality routine 0"));
19891 /* All the data is inline in the index table. */
19894 while (unwind.opcode_count > 0)
19896 unwind.opcode_count--;
19897 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19901 /* Pad with "finish" opcodes. */
19903 data = (data << 8) | 0xb0;
19910 /* We get two opcodes "free" in the first word. */
19911 size = unwind.opcode_count - 2;
19914 /* An extra byte is required for the opcode count. */
19915 size = unwind.opcode_count + 1;
19917 size = (size + 3) >> 2;
19919 as_bad (_("too many unwind opcodes"));
19921 frag_align (2, 0, 0);
19922 record_alignment (now_seg, 2);
19923 unwind.table_entry = expr_build_dot ();
19925 /* Allocate the table entry. */
19926 ptr = frag_more ((size << 2) + 4);
19927 where = frag_now_fix () - ((size << 2) + 4);
19929 switch (unwind.personality_index)
19932 /* ??? Should this be a PLT generating relocation? */
19933 /* Custom personality routine. */
19934 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19935 BFD_RELOC_ARM_PREL31);
19940 /* Set the first byte to the number of additional words. */
19945 /* ABI defined personality routines. */
19947 /* Three opcodes bytes are packed into the first word. */
19954 /* The size and first two opcode bytes go in the first word. */
19955 data = ((0x80 + unwind.personality_index) << 8) | size;
19960 /* Should never happen. */
19964 /* Pack the opcodes into words (MSB first), reversing the list at the same
19966 while (unwind.opcode_count > 0)
19970 md_number_to_chars (ptr, data, 4);
19975 unwind.opcode_count--;
19977 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19980 /* Finish off the last word. */
19983 /* Pad with "finish" opcodes. */
19985 data = (data << 8) | 0xb0;
19987 md_number_to_chars (ptr, data, 4);
19992 /* Add an empty descriptor if there is no user-specified data. */
19993 ptr = frag_more (4);
19994 md_number_to_chars (ptr, 0, 4);
20001 /* Initialize the DWARF-2 unwind information for this procedure. */
20004 tc_arm_frame_initial_instructions (void)
20006 cfi_add_CFA_def_cfa (REG_SP, 0);
20008 #endif /* OBJ_ELF */
20010 /* Convert REGNAME to a DWARF-2 register number. */
20013 tc_arm_regname_to_dw2regnum (char *regname)
20015 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20025 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20029 exp.X_op = O_secrel;
20030 exp.X_add_symbol = symbol;
20031 exp.X_add_number = 0;
20032 emit_expr (&exp, size);
20036 /* MD interface: Symbol and relocation handling. */
20038 /* Return the address within the segment that a PC-relative fixup is
20039 relative to. For ARM, PC-relative fixups applied to instructions
20040 are generally relative to the location of the fixup plus 8 bytes.
20041 Thumb branches are offset by 4, and Thumb loads relative to PC
20042 require special handling. */
20045 md_pcrel_from_section (fixS * fixP, segT seg)
20047 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20049 /* If this is pc-relative and we are going to emit a relocation
20050 then we just want to put out any pipeline compensation that the linker
20051 will need. Otherwise we want to use the calculated base.
20052 For WinCE we skip the bias for externals as well, since this
20053 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20055 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20056 || (arm_force_relocation (fixP)
20058 && !S_IS_EXTERNAL (fixP->fx_addsy)
20064 switch (fixP->fx_r_type)
20066 /* PC relative addressing on the Thumb is slightly odd as the
20067 bottom two bits of the PC are forced to zero for the
20068 calculation. This happens *after* application of the
20069 pipeline offset. However, Thumb adrl already adjusts for
20070 this, so we need not do it again. */
20071 case BFD_RELOC_ARM_THUMB_ADD:
20074 case BFD_RELOC_ARM_THUMB_OFFSET:
20075 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20076 case BFD_RELOC_ARM_T32_ADD_PC12:
20077 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20078 return (base + 4) & ~3;
20080 /* Thumb branches are simply offset by +4. */
20081 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20082 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20083 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20084 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20085 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20088 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20090 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20091 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20092 && ARM_IS_FUNC (fixP->fx_addsy)
20093 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20094 base = fixP->fx_where + fixP->fx_frag->fr_address;
20097 /* BLX is like branches above, but forces the low two bits of PC to
20099 case BFD_RELOC_THUMB_PCREL_BLX:
20101 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20102 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20103 && THUMB_IS_FUNC (fixP->fx_addsy)
20104 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20105 base = fixP->fx_where + fixP->fx_frag->fr_address;
20106 return (base + 4) & ~3;
20108 /* ARM mode branches are offset by +8. However, the Windows CE
20109 loader expects the relocation not to take this into account. */
20110 case BFD_RELOC_ARM_PCREL_BLX:
20112 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20113 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20114 && ARM_IS_FUNC (fixP->fx_addsy)
20115 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20116 base = fixP->fx_where + fixP->fx_frag->fr_address;
20119 case BFD_RELOC_ARM_PCREL_CALL:
20121 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20122 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20123 && THUMB_IS_FUNC (fixP->fx_addsy)
20124 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20125 base = fixP->fx_where + fixP->fx_frag->fr_address;
20128 case BFD_RELOC_ARM_PCREL_BRANCH:
20129 case BFD_RELOC_ARM_PCREL_JUMP:
20130 case BFD_RELOC_ARM_PLT32:
20132 /* When handling fixups immediately, because we have already
20133 discovered the value of a symbol, or the address of the frag involved
20134 we must account for the offset by +8, as the OS loader will never see the reloc.
20135 see fixup_segment() in write.c
20136 The S_IS_EXTERNAL test handles the case of global symbols.
20137 Those need the calculated base, not just the pipe compensation the linker will need. */
20139 && fixP->fx_addsy != NULL
20140 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20141 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20149 /* ARM mode loads relative to PC are also offset by +8. Unlike
20150 branches, the Windows CE loader *does* expect the relocation
20151 to take this into account. */
20152 case BFD_RELOC_ARM_OFFSET_IMM:
20153 case BFD_RELOC_ARM_OFFSET_IMM8:
20154 case BFD_RELOC_ARM_HWLITERAL:
20155 case BFD_RELOC_ARM_LITERAL:
20156 case BFD_RELOC_ARM_CP_OFF_IMM:
20160 /* Other PC-relative relocations are un-offset. */
20166 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20167 Otherwise we have no need to default values of symbols. */
20170 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20173 if (name[0] == '_' && name[1] == 'G'
20174 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20178 if (symbol_find (name))
20179 as_bad (_("GOT already in the symbol table"));
20181 GOT_symbol = symbol_new (name, undefined_section,
20182 (valueT) 0, & zero_address_frag);
20192 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20193 computed as two separate immediate values, added together. We
20194 already know that this value cannot be computed by just one ARM
20197 static unsigned int
20198 validate_immediate_twopart (unsigned int val,
20199 unsigned int * highpart)
20204 for (i = 0; i < 32; i += 2)
20205 if (((a = rotate_left (val, i)) & 0xff) != 0)
20211 * highpart = (a >> 8) | ((i + 24) << 7);
20213 else if (a & 0xff0000)
20215 if (a & 0xff000000)
20217 * highpart = (a >> 16) | ((i + 16) << 7);
20221 gas_assert (a & 0xff000000);
20222 * highpart = (a >> 24) | ((i + 8) << 7);
20225 return (a & 0xff) | (i << 7);
20232 validate_offset_imm (unsigned int val, int hwse)
20234 if ((hwse && val > 255) || val > 4095)
20239 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20240 negative immediate constant by altering the instruction. A bit of
20245 by inverting the second operand, and
20248 by negating the second operand. */
20251 negate_data_op (unsigned long * instruction,
20252 unsigned long value)
20255 unsigned long negated, inverted;
20257 negated = encode_arm_immediate (-value);
20258 inverted = encode_arm_immediate (~value);
20260 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20263 /* First negates. */
20264 case OPCODE_SUB: /* ADD <-> SUB */
20265 new_inst = OPCODE_ADD;
20270 new_inst = OPCODE_SUB;
20274 case OPCODE_CMP: /* CMP <-> CMN */
20275 new_inst = OPCODE_CMN;
20280 new_inst = OPCODE_CMP;
20284 /* Now Inverted ops. */
20285 case OPCODE_MOV: /* MOV <-> MVN */
20286 new_inst = OPCODE_MVN;
20291 new_inst = OPCODE_MOV;
20295 case OPCODE_AND: /* AND <-> BIC */
20296 new_inst = OPCODE_BIC;
20301 new_inst = OPCODE_AND;
20305 case OPCODE_ADC: /* ADC <-> SBC */
20306 new_inst = OPCODE_SBC;
20311 new_inst = OPCODE_ADC;
20315 /* We cannot do anything. */
20320 if (value == (unsigned) FAIL)
20323 *instruction &= OPCODE_MASK;
20324 *instruction |= new_inst << DATA_OP_SHIFT;
20328 /* Like negate_data_op, but for Thumb-2. */
20330 static unsigned int
20331 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20335 unsigned int negated, inverted;
20337 negated = encode_thumb32_immediate (-value);
20338 inverted = encode_thumb32_immediate (~value);
20340 rd = (*instruction >> 8) & 0xf;
20341 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20344 /* ADD <-> SUB. Includes CMP <-> CMN. */
20345 case T2_OPCODE_SUB:
20346 new_inst = T2_OPCODE_ADD;
20350 case T2_OPCODE_ADD:
20351 new_inst = T2_OPCODE_SUB;
20355 /* ORR <-> ORN. Includes MOV <-> MVN. */
20356 case T2_OPCODE_ORR:
20357 new_inst = T2_OPCODE_ORN;
20361 case T2_OPCODE_ORN:
20362 new_inst = T2_OPCODE_ORR;
20366 /* AND <-> BIC. TST has no inverted equivalent. */
20367 case T2_OPCODE_AND:
20368 new_inst = T2_OPCODE_BIC;
20375 case T2_OPCODE_BIC:
20376 new_inst = T2_OPCODE_AND;
20381 case T2_OPCODE_ADC:
20382 new_inst = T2_OPCODE_SBC;
20386 case T2_OPCODE_SBC:
20387 new_inst = T2_OPCODE_ADC;
20391 /* We cannot do anything. */
20396 if (value == (unsigned int)FAIL)
20399 *instruction &= T2_OPCODE_MASK;
20400 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20404 /* Read a 32-bit thumb instruction from buf. */
20405 static unsigned long
20406 get_thumb32_insn (char * buf)
20408 unsigned long insn;
20409 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20410 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20416 /* We usually want to set the low bit on the address of thumb function
20417 symbols. In particular .word foo - . should have the low bit set.
20418 Generic code tries to fold the difference of two symbols to
20419 a constant. Prevent this and force a relocation when the first symbols
20420 is a thumb function. */
20423 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20425 if (op == O_subtract
20426 && l->X_op == O_symbol
20427 && r->X_op == O_symbol
20428 && THUMB_IS_FUNC (l->X_add_symbol))
20430 l->X_op = O_subtract;
20431 l->X_op_symbol = r->X_add_symbol;
20432 l->X_add_number -= r->X_add_number;
20436 /* Process as normal. */
20440 /* Encode Thumb2 unconditional branches and calls. The encoding
20441 for the 2 are identical for the immediate values. */
20444 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20446 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20449 addressT S, I1, I2, lo, hi;
20451 S = (value >> 24) & 0x01;
20452 I1 = (value >> 23) & 0x01;
20453 I2 = (value >> 22) & 0x01;
20454 hi = (value >> 12) & 0x3ff;
20455 lo = (value >> 1) & 0x7ff;
20456 newval = md_chars_to_number (buf, THUMB_SIZE);
20457 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20458 newval |= (S << 10) | hi;
20459 newval2 &= ~T2I1I2MASK;
20460 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20461 md_number_to_chars (buf, newval, THUMB_SIZE);
20462 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20466 md_apply_fix (fixS * fixP,
20470 offsetT value = * valP;
20472 unsigned int newimm;
20473 unsigned long temp;
20475 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20477 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20479 /* Note whether this will delete the relocation. */
20481 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20484 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20485 consistency with the behaviour on 32-bit hosts. Remember value
20487 value &= 0xffffffff;
20488 value ^= 0x80000000;
20489 value -= 0x80000000;
20492 fixP->fx_addnumber = value;
20494 /* Same treatment for fixP->fx_offset. */
20495 fixP->fx_offset &= 0xffffffff;
20496 fixP->fx_offset ^= 0x80000000;
20497 fixP->fx_offset -= 0x80000000;
20499 switch (fixP->fx_r_type)
20501 case BFD_RELOC_NONE:
20502 /* This will need to go in the object file. */
20506 case BFD_RELOC_ARM_IMMEDIATE:
20507 /* We claim that this fixup has been processed here,
20508 even if in fact we generate an error because we do
20509 not have a reloc for it, so tc_gen_reloc will reject it. */
20512 if (fixP->fx_addsy)
20514 const char *msg = 0;
20516 if (! S_IS_DEFINED (fixP->fx_addsy))
20517 msg = _("undefined symbol %s used as an immediate value");
20518 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20519 msg = _("symbol %s is in a different section");
20520 else if (S_IS_WEAK (fixP->fx_addsy))
20521 msg = _("symbol %s is weak and may be overridden later");
20525 as_bad_where (fixP->fx_file, fixP->fx_line,
20526 msg, S_GET_NAME (fixP->fx_addsy));
20531 newimm = encode_arm_immediate (value);
20532 temp = md_chars_to_number (buf, INSN_SIZE);
20534 /* If the instruction will fail, see if we can fix things up by
20535 changing the opcode. */
20536 if (newimm == (unsigned int) FAIL
20537 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20539 as_bad_where (fixP->fx_file, fixP->fx_line,
20540 _("invalid constant (%lx) after fixup"),
20541 (unsigned long) value);
20545 newimm |= (temp & 0xfffff000);
20546 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20549 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20551 unsigned int highpart = 0;
20552 unsigned int newinsn = 0xe1a00000; /* nop. */
20554 if (fixP->fx_addsy)
20556 const char *msg = 0;
20558 if (! S_IS_DEFINED (fixP->fx_addsy))
20559 msg = _("undefined symbol %s used as an immediate value");
20560 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20561 msg = _("symbol %s is in a different section");
20562 else if (S_IS_WEAK (fixP->fx_addsy))
20563 msg = _("symbol %s is weak and may be overridden later");
20567 as_bad_where (fixP->fx_file, fixP->fx_line,
20568 msg, S_GET_NAME (fixP->fx_addsy));
20573 newimm = encode_arm_immediate (value);
20574 temp = md_chars_to_number (buf, INSN_SIZE);
20576 /* If the instruction will fail, see if we can fix things up by
20577 changing the opcode. */
20578 if (newimm == (unsigned int) FAIL
20579 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20581 /* No ? OK - try using two ADD instructions to generate
20583 newimm = validate_immediate_twopart (value, & highpart);
20585 /* Yes - then make sure that the second instruction is
20587 if (newimm != (unsigned int) FAIL)
20589 /* Still No ? Try using a negated value. */
20590 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20591 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20592 /* Otherwise - give up. */
20595 as_bad_where (fixP->fx_file, fixP->fx_line,
20596 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20601 /* Replace the first operand in the 2nd instruction (which
20602 is the PC) with the destination register. We have
20603 already added in the PC in the first instruction and we
20604 do not want to do it again. */
20605 newinsn &= ~ 0xf0000;
20606 newinsn |= ((newinsn & 0x0f000) << 4);
20609 newimm |= (temp & 0xfffff000);
20610 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20612 highpart |= (newinsn & 0xfffff000);
20613 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20617 case BFD_RELOC_ARM_OFFSET_IMM:
20618 if (!fixP->fx_done && seg->use_rela_p)
20621 case BFD_RELOC_ARM_LITERAL:
20627 if (validate_offset_imm (value, 0) == FAIL)
20629 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20630 as_bad_where (fixP->fx_file, fixP->fx_line,
20631 _("invalid literal constant: pool needs to be closer"));
20633 as_bad_where (fixP->fx_file, fixP->fx_line,
20634 _("bad immediate value for offset (%ld)"),
20639 newval = md_chars_to_number (buf, INSN_SIZE);
20641 newval &= 0xfffff000;
20644 newval &= 0xff7ff000;
20645 newval |= value | (sign ? INDEX_UP : 0);
20647 md_number_to_chars (buf, newval, INSN_SIZE);
20650 case BFD_RELOC_ARM_OFFSET_IMM8:
20651 case BFD_RELOC_ARM_HWLITERAL:
20657 if (validate_offset_imm (value, 1) == FAIL)
20659 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20660 as_bad_where (fixP->fx_file, fixP->fx_line,
20661 _("invalid literal constant: pool needs to be closer"));
20663 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20668 newval = md_chars_to_number (buf, INSN_SIZE);
20670 newval &= 0xfffff0f0;
20673 newval &= 0xff7ff0f0;
20674 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20676 md_number_to_chars (buf, newval, INSN_SIZE);
20679 case BFD_RELOC_ARM_T32_OFFSET_U8:
20680 if (value < 0 || value > 1020 || value % 4 != 0)
20681 as_bad_where (fixP->fx_file, fixP->fx_line,
20682 _("bad immediate value for offset (%ld)"), (long) value);
20685 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20687 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20690 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20691 /* This is a complicated relocation used for all varieties of Thumb32
20692 load/store instruction with immediate offset:
20694 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20695 *4, optional writeback(W)
20696 (doubleword load/store)
20698 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20699 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20700 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20701 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20702 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20704 Uppercase letters indicate bits that are already encoded at
20705 this point. Lowercase letters are our problem. For the
20706 second block of instructions, the secondary opcode nybble
20707 (bits 8..11) is present, and bit 23 is zero, even if this is
20708 a PC-relative operation. */
20709 newval = md_chars_to_number (buf, THUMB_SIZE);
20711 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20713 if ((newval & 0xf0000000) == 0xe0000000)
20715 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20717 newval |= (1 << 23);
20720 if (value % 4 != 0)
20722 as_bad_where (fixP->fx_file, fixP->fx_line,
20723 _("offset not a multiple of 4"));
20729 as_bad_where (fixP->fx_file, fixP->fx_line,
20730 _("offset out of range"));
20735 else if ((newval & 0x000f0000) == 0x000f0000)
20737 /* PC-relative, 12-bit offset. */
20739 newval |= (1 << 23);
20744 as_bad_where (fixP->fx_file, fixP->fx_line,
20745 _("offset out of range"));
20750 else if ((newval & 0x00000100) == 0x00000100)
20752 /* Writeback: 8-bit, +/- offset. */
20754 newval |= (1 << 9);
20759 as_bad_where (fixP->fx_file, fixP->fx_line,
20760 _("offset out of range"));
20765 else if ((newval & 0x00000f00) == 0x00000e00)
20767 /* T-instruction: positive 8-bit offset. */
20768 if (value < 0 || value > 0xff)
20770 as_bad_where (fixP->fx_file, fixP->fx_line,
20771 _("offset out of range"));
20779 /* Positive 12-bit or negative 8-bit offset. */
20783 newval |= (1 << 23);
20793 as_bad_where (fixP->fx_file, fixP->fx_line,
20794 _("offset out of range"));
20801 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20802 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20805 case BFD_RELOC_ARM_SHIFT_IMM:
20806 newval = md_chars_to_number (buf, INSN_SIZE);
20807 if (((unsigned long) value) > 32
20809 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20811 as_bad_where (fixP->fx_file, fixP->fx_line,
20812 _("shift expression is too large"));
20817 /* Shifts of zero must be done as lsl. */
20819 else if (value == 32)
20821 newval &= 0xfffff07f;
20822 newval |= (value & 0x1f) << 7;
20823 md_number_to_chars (buf, newval, INSN_SIZE);
20826 case BFD_RELOC_ARM_T32_IMMEDIATE:
20827 case BFD_RELOC_ARM_T32_ADD_IMM:
20828 case BFD_RELOC_ARM_T32_IMM12:
20829 case BFD_RELOC_ARM_T32_ADD_PC12:
20830 /* We claim that this fixup has been processed here,
20831 even if in fact we generate an error because we do
20832 not have a reloc for it, so tc_gen_reloc will reject it. */
20836 && ! S_IS_DEFINED (fixP->fx_addsy))
20838 as_bad_where (fixP->fx_file, fixP->fx_line,
20839 _("undefined symbol %s used as an immediate value"),
20840 S_GET_NAME (fixP->fx_addsy));
20844 newval = md_chars_to_number (buf, THUMB_SIZE);
20846 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20849 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20850 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20852 newimm = encode_thumb32_immediate (value);
20853 if (newimm == (unsigned int) FAIL)
20854 newimm = thumb32_negate_data_op (&newval, value);
20856 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20857 && newimm == (unsigned int) FAIL)
20859 /* Turn add/sum into addw/subw. */
20860 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20861 newval = (newval & 0xfeffffff) | 0x02000000;
20862 /* No flat 12-bit imm encoding for addsw/subsw. */
20863 if ((newval & 0x00100000) == 0)
20865 /* 12 bit immediate for addw/subw. */
20869 newval ^= 0x00a00000;
20872 newimm = (unsigned int) FAIL;
20878 if (newimm == (unsigned int)FAIL)
20880 as_bad_where (fixP->fx_file, fixP->fx_line,
20881 _("invalid constant (%lx) after fixup"),
20882 (unsigned long) value);
20886 newval |= (newimm & 0x800) << 15;
20887 newval |= (newimm & 0x700) << 4;
20888 newval |= (newimm & 0x0ff);
20890 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20891 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20894 case BFD_RELOC_ARM_SMC:
20895 if (((unsigned long) value) > 0xffff)
20896 as_bad_where (fixP->fx_file, fixP->fx_line,
20897 _("invalid smc expression"));
20898 newval = md_chars_to_number (buf, INSN_SIZE);
20899 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20900 md_number_to_chars (buf, newval, INSN_SIZE);
20903 case BFD_RELOC_ARM_HVC:
20904 if (((unsigned long) value) > 0xffff)
20905 as_bad_where (fixP->fx_file, fixP->fx_line,
20906 _("invalid hvc expression"));
20907 newval = md_chars_to_number (buf, INSN_SIZE);
20908 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20909 md_number_to_chars (buf, newval, INSN_SIZE);
20912 case BFD_RELOC_ARM_SWI:
20913 if (fixP->tc_fix_data != 0)
20915 if (((unsigned long) value) > 0xff)
20916 as_bad_where (fixP->fx_file, fixP->fx_line,
20917 _("invalid swi expression"));
20918 newval = md_chars_to_number (buf, THUMB_SIZE);
20920 md_number_to_chars (buf, newval, THUMB_SIZE);
20924 if (((unsigned long) value) > 0x00ffffff)
20925 as_bad_where (fixP->fx_file, fixP->fx_line,
20926 _("invalid swi expression"));
20927 newval = md_chars_to_number (buf, INSN_SIZE);
20929 md_number_to_chars (buf, newval, INSN_SIZE);
20933 case BFD_RELOC_ARM_MULTI:
20934 if (((unsigned long) value) > 0xffff)
20935 as_bad_where (fixP->fx_file, fixP->fx_line,
20936 _("invalid expression in load/store multiple"));
20937 newval = value | md_chars_to_number (buf, INSN_SIZE);
20938 md_number_to_chars (buf, newval, INSN_SIZE);
20942 case BFD_RELOC_ARM_PCREL_CALL:
20944 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20946 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20947 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20948 && THUMB_IS_FUNC (fixP->fx_addsy))
20949 /* Flip the bl to blx. This is a simple flip
20950 bit here because we generate PCREL_CALL for
20951 unconditional bls. */
20953 newval = md_chars_to_number (buf, INSN_SIZE);
20954 newval = newval | 0x10000000;
20955 md_number_to_chars (buf, newval, INSN_SIZE);
20961 goto arm_branch_common;
20963 case BFD_RELOC_ARM_PCREL_JUMP:
20964 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20966 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20967 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20968 && THUMB_IS_FUNC (fixP->fx_addsy))
20970 /* This would map to a bl<cond>, b<cond>,
20971 b<always> to a Thumb function. We
20972 need to force a relocation for this particular
20974 newval = md_chars_to_number (buf, INSN_SIZE);
20978 case BFD_RELOC_ARM_PLT32:
20980 case BFD_RELOC_ARM_PCREL_BRANCH:
20982 goto arm_branch_common;
20984 case BFD_RELOC_ARM_PCREL_BLX:
20987 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20989 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20990 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20991 && ARM_IS_FUNC (fixP->fx_addsy))
20993 /* Flip the blx to a bl and warn. */
20994 const char *name = S_GET_NAME (fixP->fx_addsy);
20995 newval = 0xeb000000;
20996 as_warn_where (fixP->fx_file, fixP->fx_line,
20997 _("blx to '%s' an ARM ISA state function changed to bl"),
20999 md_number_to_chars (buf, newval, INSN_SIZE);
21005 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21006 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21010 /* We are going to store value (shifted right by two) in the
21011 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21012 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21013 also be be clear. */
21015 as_bad_where (fixP->fx_file, fixP->fx_line,
21016 _("misaligned branch destination"));
21017 if ((value & (offsetT)0xfe000000) != (offsetT)0
21018 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21019 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21021 if (fixP->fx_done || !seg->use_rela_p)
21023 newval = md_chars_to_number (buf, INSN_SIZE);
21024 newval |= (value >> 2) & 0x00ffffff;
21025 /* Set the H bit on BLX instructions. */
21029 newval |= 0x01000000;
21031 newval &= ~0x01000000;
21033 md_number_to_chars (buf, newval, INSN_SIZE);
21037 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21038 /* CBZ can only branch forward. */
21040 /* Attempts to use CBZ to branch to the next instruction
21041 (which, strictly speaking, are prohibited) will be turned into
21044 FIXME: It may be better to remove the instruction completely and
21045 perform relaxation. */
21048 newval = md_chars_to_number (buf, THUMB_SIZE);
21049 newval = 0xbf00; /* NOP encoding T1 */
21050 md_number_to_chars (buf, newval, THUMB_SIZE);
21055 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21057 if (fixP->fx_done || !seg->use_rela_p)
21059 newval = md_chars_to_number (buf, THUMB_SIZE);
21060 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21061 md_number_to_chars (buf, newval, THUMB_SIZE);
21066 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21067 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21068 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21070 if (fixP->fx_done || !seg->use_rela_p)
21072 newval = md_chars_to_number (buf, THUMB_SIZE);
21073 newval |= (value & 0x1ff) >> 1;
21074 md_number_to_chars (buf, newval, THUMB_SIZE);
21078 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21079 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21080 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21082 if (fixP->fx_done || !seg->use_rela_p)
21084 newval = md_chars_to_number (buf, THUMB_SIZE);
21085 newval |= (value & 0xfff) >> 1;
21086 md_number_to_chars (buf, newval, THUMB_SIZE);
21090 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21092 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21093 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21094 && ARM_IS_FUNC (fixP->fx_addsy)
21095 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21097 /* Force a relocation for a branch 20 bits wide. */
21100 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21101 as_bad_where (fixP->fx_file, fixP->fx_line,
21102 _("conditional branch out of range"));
21104 if (fixP->fx_done || !seg->use_rela_p)
21107 addressT S, J1, J2, lo, hi;
21109 S = (value & 0x00100000) >> 20;
21110 J2 = (value & 0x00080000) >> 19;
21111 J1 = (value & 0x00040000) >> 18;
21112 hi = (value & 0x0003f000) >> 12;
21113 lo = (value & 0x00000ffe) >> 1;
21115 newval = md_chars_to_number (buf, THUMB_SIZE);
21116 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21117 newval |= (S << 10) | hi;
21118 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21119 md_number_to_chars (buf, newval, THUMB_SIZE);
21120 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21124 case BFD_RELOC_THUMB_PCREL_BLX:
21125 /* If there is a blx from a thumb state function to
21126 another thumb function flip this to a bl and warn
21130 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21131 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21132 && THUMB_IS_FUNC (fixP->fx_addsy))
21134 const char *name = S_GET_NAME (fixP->fx_addsy);
21135 as_warn_where (fixP->fx_file, fixP->fx_line,
21136 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21138 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21139 newval = newval | 0x1000;
21140 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21141 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21146 goto thumb_bl_common;
21148 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21149 /* A bl from Thumb state ISA to an internal ARM state function
21150 is converted to a blx. */
21152 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21153 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21154 && ARM_IS_FUNC (fixP->fx_addsy)
21155 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21157 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21158 newval = newval & ~0x1000;
21159 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21160 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21167 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21168 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21169 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21172 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21173 /* For a BLX instruction, make sure that the relocation is rounded up
21174 to a word boundary. This follows the semantics of the instruction
21175 which specifies that bit 1 of the target address will come from bit
21176 1 of the base address. */
21177 value = (value + 1) & ~ 1;
21179 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21181 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21182 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21183 else if ((value & ~0x1ffffff)
21184 && ((value & ~0x1ffffff) != ~0x1ffffff))
21185 as_bad_where (fixP->fx_file, fixP->fx_line,
21186 _("Thumb2 branch out of range"));
21189 if (fixP->fx_done || !seg->use_rela_p)
21190 encode_thumb2_b_bl_offset (buf, value);
21194 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21195 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21196 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21198 if (fixP->fx_done || !seg->use_rela_p)
21199 encode_thumb2_b_bl_offset (buf, value);
21204 if (fixP->fx_done || !seg->use_rela_p)
21205 md_number_to_chars (buf, value, 1);
21209 if (fixP->fx_done || !seg->use_rela_p)
21210 md_number_to_chars (buf, value, 2);
21214 case BFD_RELOC_ARM_TLS_CALL:
21215 case BFD_RELOC_ARM_THM_TLS_CALL:
21216 case BFD_RELOC_ARM_TLS_DESCSEQ:
21217 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21218 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21221 case BFD_RELOC_ARM_TLS_GOTDESC:
21222 case BFD_RELOC_ARM_TLS_GD32:
21223 case BFD_RELOC_ARM_TLS_LE32:
21224 case BFD_RELOC_ARM_TLS_IE32:
21225 case BFD_RELOC_ARM_TLS_LDM32:
21226 case BFD_RELOC_ARM_TLS_LDO32:
21227 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21230 case BFD_RELOC_ARM_GOT32:
21231 case BFD_RELOC_ARM_GOTOFF:
21232 if (fixP->fx_done || !seg->use_rela_p)
21233 md_number_to_chars (buf, 0, 4);
21236 case BFD_RELOC_ARM_GOT_PREL:
21237 if (fixP->fx_done || !seg->use_rela_p)
21238 md_number_to_chars (buf, value, 4);
21241 case BFD_RELOC_ARM_TARGET2:
21242 /* TARGET2 is not partial-inplace, so we need to write the
21243 addend here for REL targets, because it won't be written out
21244 during reloc processing later. */
21245 if (fixP->fx_done || !seg->use_rela_p)
21246 md_number_to_chars (buf, fixP->fx_offset, 4);
21250 case BFD_RELOC_RVA:
21252 case BFD_RELOC_ARM_TARGET1:
21253 case BFD_RELOC_ARM_ROSEGREL32:
21254 case BFD_RELOC_ARM_SBREL32:
21255 case BFD_RELOC_32_PCREL:
21257 case BFD_RELOC_32_SECREL:
21259 if (fixP->fx_done || !seg->use_rela_p)
21261 /* For WinCE we only do this for pcrel fixups. */
21262 if (fixP->fx_done || fixP->fx_pcrel)
21264 md_number_to_chars (buf, value, 4);
21268 case BFD_RELOC_ARM_PREL31:
21269 if (fixP->fx_done || !seg->use_rela_p)
21271 newval = md_chars_to_number (buf, 4) & 0x80000000;
21272 if ((value ^ (value >> 1)) & 0x40000000)
21274 as_bad_where (fixP->fx_file, fixP->fx_line,
21275 _("rel31 relocation overflow"));
21277 newval |= value & 0x7fffffff;
21278 md_number_to_chars (buf, newval, 4);
21283 case BFD_RELOC_ARM_CP_OFF_IMM:
21284 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21285 if (value < -1023 || value > 1023 || (value & 3))
21286 as_bad_where (fixP->fx_file, fixP->fx_line,
21287 _("co-processor offset out of range"));
21292 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21293 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21294 newval = md_chars_to_number (buf, INSN_SIZE);
21296 newval = get_thumb32_insn (buf);
21298 newval &= 0xffffff00;
21301 newval &= 0xff7fff00;
21302 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21304 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21305 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21306 md_number_to_chars (buf, newval, INSN_SIZE);
21308 put_thumb32_insn (buf, newval);
21311 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21312 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21313 if (value < -255 || value > 255)
21314 as_bad_where (fixP->fx_file, fixP->fx_line,
21315 _("co-processor offset out of range"));
21317 goto cp_off_common;
21319 case BFD_RELOC_ARM_THUMB_OFFSET:
21320 newval = md_chars_to_number (buf, THUMB_SIZE);
21321 /* Exactly what ranges, and where the offset is inserted depends
21322 on the type of instruction, we can establish this from the
21324 switch (newval >> 12)
21326 case 4: /* PC load. */
21327 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21328 forced to zero for these loads; md_pcrel_from has already
21329 compensated for this. */
21331 as_bad_where (fixP->fx_file, fixP->fx_line,
21332 _("invalid offset, target not word aligned (0x%08lX)"),
21333 (((unsigned long) fixP->fx_frag->fr_address
21334 + (unsigned long) fixP->fx_where) & ~3)
21335 + (unsigned long) value);
21337 if (value & ~0x3fc)
21338 as_bad_where (fixP->fx_file, fixP->fx_line,
21339 _("invalid offset, value too big (0x%08lX)"),
21342 newval |= value >> 2;
21345 case 9: /* SP load/store. */
21346 if (value & ~0x3fc)
21347 as_bad_where (fixP->fx_file, fixP->fx_line,
21348 _("invalid offset, value too big (0x%08lX)"),
21350 newval |= value >> 2;
21353 case 6: /* Word load/store. */
21355 as_bad_where (fixP->fx_file, fixP->fx_line,
21356 _("invalid offset, value too big (0x%08lX)"),
21358 newval |= value << 4; /* 6 - 2. */
21361 case 7: /* Byte load/store. */
21363 as_bad_where (fixP->fx_file, fixP->fx_line,
21364 _("invalid offset, value too big (0x%08lX)"),
21366 newval |= value << 6;
21369 case 8: /* Halfword load/store. */
21371 as_bad_where (fixP->fx_file, fixP->fx_line,
21372 _("invalid offset, value too big (0x%08lX)"),
21374 newval |= value << 5; /* 6 - 1. */
21378 as_bad_where (fixP->fx_file, fixP->fx_line,
21379 "Unable to process relocation for thumb opcode: %lx",
21380 (unsigned long) newval);
21383 md_number_to_chars (buf, newval, THUMB_SIZE);
21386 case BFD_RELOC_ARM_THUMB_ADD:
21387 /* This is a complicated relocation, since we use it for all of
21388 the following immediate relocations:
21392 9bit ADD/SUB SP word-aligned
21393 10bit ADD PC/SP word-aligned
21395 The type of instruction being processed is encoded in the
21402 newval = md_chars_to_number (buf, THUMB_SIZE);
21404 int rd = (newval >> 4) & 0xf;
21405 int rs = newval & 0xf;
21406 int subtract = !!(newval & 0x8000);
21408 /* Check for HI regs, only very restricted cases allowed:
21409 Adjusting SP, and using PC or SP to get an address. */
21410 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21411 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21412 as_bad_where (fixP->fx_file, fixP->fx_line,
21413 _("invalid Hi register with immediate"));
21415 /* If value is negative, choose the opposite instruction. */
21419 subtract = !subtract;
21421 as_bad_where (fixP->fx_file, fixP->fx_line,
21422 _("immediate value out of range"));
21427 if (value & ~0x1fc)
21428 as_bad_where (fixP->fx_file, fixP->fx_line,
21429 _("invalid immediate for stack address calculation"));
21430 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21431 newval |= value >> 2;
21433 else if (rs == REG_PC || rs == REG_SP)
21435 if (subtract || value & ~0x3fc)
21436 as_bad_where (fixP->fx_file, fixP->fx_line,
21437 _("invalid immediate for address calculation (value = 0x%08lX)"),
21438 (unsigned long) value);
21439 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21441 newval |= value >> 2;
21446 as_bad_where (fixP->fx_file, fixP->fx_line,
21447 _("immediate value out of range"));
21448 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21449 newval |= (rd << 8) | value;
21454 as_bad_where (fixP->fx_file, fixP->fx_line,
21455 _("immediate value out of range"));
21456 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21457 newval |= rd | (rs << 3) | (value << 6);
21460 md_number_to_chars (buf, newval, THUMB_SIZE);
21463 case BFD_RELOC_ARM_THUMB_IMM:
21464 newval = md_chars_to_number (buf, THUMB_SIZE);
21465 if (value < 0 || value > 255)
21466 as_bad_where (fixP->fx_file, fixP->fx_line,
21467 _("invalid immediate: %ld is out of range"),
21470 md_number_to_chars (buf, newval, THUMB_SIZE);
21473 case BFD_RELOC_ARM_THUMB_SHIFT:
21474 /* 5bit shift value (0..32). LSL cannot take 32. */
21475 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21476 temp = newval & 0xf800;
21477 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21478 as_bad_where (fixP->fx_file, fixP->fx_line,
21479 _("invalid shift value: %ld"), (long) value);
21480 /* Shifts of zero must be encoded as LSL. */
21482 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21483 /* Shifts of 32 are encoded as zero. */
21484 else if (value == 32)
21486 newval |= value << 6;
21487 md_number_to_chars (buf, newval, THUMB_SIZE);
21490 case BFD_RELOC_VTABLE_INHERIT:
21491 case BFD_RELOC_VTABLE_ENTRY:
21495 case BFD_RELOC_ARM_MOVW:
21496 case BFD_RELOC_ARM_MOVT:
21497 case BFD_RELOC_ARM_THUMB_MOVW:
21498 case BFD_RELOC_ARM_THUMB_MOVT:
21499 if (fixP->fx_done || !seg->use_rela_p)
21501 /* REL format relocations are limited to a 16-bit addend. */
21502 if (!fixP->fx_done)
21504 if (value < -0x8000 || value > 0x7fff)
21505 as_bad_where (fixP->fx_file, fixP->fx_line,
21506 _("offset out of range"));
21508 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21509 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21514 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21515 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21517 newval = get_thumb32_insn (buf);
21518 newval &= 0xfbf08f00;
21519 newval |= (value & 0xf000) << 4;
21520 newval |= (value & 0x0800) << 15;
21521 newval |= (value & 0x0700) << 4;
21522 newval |= (value & 0x00ff);
21523 put_thumb32_insn (buf, newval);
21527 newval = md_chars_to_number (buf, 4);
21528 newval &= 0xfff0f000;
21529 newval |= value & 0x0fff;
21530 newval |= (value & 0xf000) << 4;
21531 md_number_to_chars (buf, newval, 4);
21536 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21537 case BFD_RELOC_ARM_ALU_PC_G0:
21538 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21539 case BFD_RELOC_ARM_ALU_PC_G1:
21540 case BFD_RELOC_ARM_ALU_PC_G2:
21541 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21542 case BFD_RELOC_ARM_ALU_SB_G0:
21543 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21544 case BFD_RELOC_ARM_ALU_SB_G1:
21545 case BFD_RELOC_ARM_ALU_SB_G2:
21546 gas_assert (!fixP->fx_done);
21547 if (!seg->use_rela_p)
21550 bfd_vma encoded_addend;
21551 bfd_vma addend_abs = abs (value);
21553 /* Check that the absolute value of the addend can be
21554 expressed as an 8-bit constant plus a rotation. */
21555 encoded_addend = encode_arm_immediate (addend_abs);
21556 if (encoded_addend == (unsigned int) FAIL)
21557 as_bad_where (fixP->fx_file, fixP->fx_line,
21558 _("the offset 0x%08lX is not representable"),
21559 (unsigned long) addend_abs);
21561 /* Extract the instruction. */
21562 insn = md_chars_to_number (buf, INSN_SIZE);
21564 /* If the addend is positive, use an ADD instruction.
21565 Otherwise use a SUB. Take care not to destroy the S bit. */
21566 insn &= 0xff1fffff;
21572 /* Place the encoded addend into the first 12 bits of the
21574 insn &= 0xfffff000;
21575 insn |= encoded_addend;
21577 /* Update the instruction. */
21578 md_number_to_chars (buf, insn, INSN_SIZE);
21582 case BFD_RELOC_ARM_LDR_PC_G0:
21583 case BFD_RELOC_ARM_LDR_PC_G1:
21584 case BFD_RELOC_ARM_LDR_PC_G2:
21585 case BFD_RELOC_ARM_LDR_SB_G0:
21586 case BFD_RELOC_ARM_LDR_SB_G1:
21587 case BFD_RELOC_ARM_LDR_SB_G2:
21588 gas_assert (!fixP->fx_done);
21589 if (!seg->use_rela_p)
21592 bfd_vma addend_abs = abs (value);
21594 /* Check that the absolute value of the addend can be
21595 encoded in 12 bits. */
21596 if (addend_abs >= 0x1000)
21597 as_bad_where (fixP->fx_file, fixP->fx_line,
21598 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21599 (unsigned long) addend_abs);
21601 /* Extract the instruction. */
21602 insn = md_chars_to_number (buf, INSN_SIZE);
21604 /* If the addend is negative, clear bit 23 of the instruction.
21605 Otherwise set it. */
21607 insn &= ~(1 << 23);
21611 /* Place the absolute value of the addend into the first 12 bits
21612 of the instruction. */
21613 insn &= 0xfffff000;
21614 insn |= addend_abs;
21616 /* Update the instruction. */
21617 md_number_to_chars (buf, insn, INSN_SIZE);
21621 case BFD_RELOC_ARM_LDRS_PC_G0:
21622 case BFD_RELOC_ARM_LDRS_PC_G1:
21623 case BFD_RELOC_ARM_LDRS_PC_G2:
21624 case BFD_RELOC_ARM_LDRS_SB_G0:
21625 case BFD_RELOC_ARM_LDRS_SB_G1:
21626 case BFD_RELOC_ARM_LDRS_SB_G2:
21627 gas_assert (!fixP->fx_done);
21628 if (!seg->use_rela_p)
21631 bfd_vma addend_abs = abs (value);
21633 /* Check that the absolute value of the addend can be
21634 encoded in 8 bits. */
21635 if (addend_abs >= 0x100)
21636 as_bad_where (fixP->fx_file, fixP->fx_line,
21637 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21638 (unsigned long) addend_abs);
21640 /* Extract the instruction. */
21641 insn = md_chars_to_number (buf, INSN_SIZE);
21643 /* If the addend is negative, clear bit 23 of the instruction.
21644 Otherwise set it. */
21646 insn &= ~(1 << 23);
21650 /* Place the first four bits of the absolute value of the addend
21651 into the first 4 bits of the instruction, and the remaining
21652 four into bits 8 .. 11. */
21653 insn &= 0xfffff0f0;
21654 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21656 /* Update the instruction. */
21657 md_number_to_chars (buf, insn, INSN_SIZE);
21661 case BFD_RELOC_ARM_LDC_PC_G0:
21662 case BFD_RELOC_ARM_LDC_PC_G1:
21663 case BFD_RELOC_ARM_LDC_PC_G2:
21664 case BFD_RELOC_ARM_LDC_SB_G0:
21665 case BFD_RELOC_ARM_LDC_SB_G1:
21666 case BFD_RELOC_ARM_LDC_SB_G2:
21667 gas_assert (!fixP->fx_done);
21668 if (!seg->use_rela_p)
21671 bfd_vma addend_abs = abs (value);
21673 /* Check that the absolute value of the addend is a multiple of
21674 four and, when divided by four, fits in 8 bits. */
21675 if (addend_abs & 0x3)
21676 as_bad_where (fixP->fx_file, fixP->fx_line,
21677 _("bad offset 0x%08lX (must be word-aligned)"),
21678 (unsigned long) addend_abs);
21680 if ((addend_abs >> 2) > 0xff)
21681 as_bad_where (fixP->fx_file, fixP->fx_line,
21682 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21683 (unsigned long) addend_abs);
21685 /* Extract the instruction. */
21686 insn = md_chars_to_number (buf, INSN_SIZE);
21688 /* If the addend is negative, clear bit 23 of the instruction.
21689 Otherwise set it. */
21691 insn &= ~(1 << 23);
21695 /* Place the addend (divided by four) into the first eight
21696 bits of the instruction. */
21697 insn &= 0xfffffff0;
21698 insn |= addend_abs >> 2;
21700 /* Update the instruction. */
21701 md_number_to_chars (buf, insn, INSN_SIZE);
21705 case BFD_RELOC_ARM_V4BX:
21706 /* This will need to go in the object file. */
21710 case BFD_RELOC_UNUSED:
21712 as_bad_where (fixP->fx_file, fixP->fx_line,
21713 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21717 /* Translate internal representation of relocation info to BFD target
21721 tc_gen_reloc (asection *section, fixS *fixp)
21724 bfd_reloc_code_real_type code;
21726 reloc = (arelent *) xmalloc (sizeof (arelent));
21728 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21729 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21730 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21732 if (fixp->fx_pcrel)
21734 if (section->use_rela_p)
21735 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21737 fixp->fx_offset = reloc->address;
21739 reloc->addend = fixp->fx_offset;
21741 switch (fixp->fx_r_type)
21744 if (fixp->fx_pcrel)
21746 code = BFD_RELOC_8_PCREL;
21751 if (fixp->fx_pcrel)
21753 code = BFD_RELOC_16_PCREL;
21758 if (fixp->fx_pcrel)
21760 code = BFD_RELOC_32_PCREL;
21764 case BFD_RELOC_ARM_MOVW:
21765 if (fixp->fx_pcrel)
21767 code = BFD_RELOC_ARM_MOVW_PCREL;
21771 case BFD_RELOC_ARM_MOVT:
21772 if (fixp->fx_pcrel)
21774 code = BFD_RELOC_ARM_MOVT_PCREL;
21778 case BFD_RELOC_ARM_THUMB_MOVW:
21779 if (fixp->fx_pcrel)
21781 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21785 case BFD_RELOC_ARM_THUMB_MOVT:
21786 if (fixp->fx_pcrel)
21788 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21792 case BFD_RELOC_NONE:
21793 case BFD_RELOC_ARM_PCREL_BRANCH:
21794 case BFD_RELOC_ARM_PCREL_BLX:
21795 case BFD_RELOC_RVA:
21796 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21797 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21798 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21799 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21800 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21801 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21802 case BFD_RELOC_VTABLE_ENTRY:
21803 case BFD_RELOC_VTABLE_INHERIT:
21805 case BFD_RELOC_32_SECREL:
21807 code = fixp->fx_r_type;
21810 case BFD_RELOC_THUMB_PCREL_BLX:
21812 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21813 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21816 code = BFD_RELOC_THUMB_PCREL_BLX;
21819 case BFD_RELOC_ARM_LITERAL:
21820 case BFD_RELOC_ARM_HWLITERAL:
21821 /* If this is called then the a literal has
21822 been referenced across a section boundary. */
21823 as_bad_where (fixp->fx_file, fixp->fx_line,
21824 _("literal referenced across section boundary"));
21828 case BFD_RELOC_ARM_TLS_CALL:
21829 case BFD_RELOC_ARM_THM_TLS_CALL:
21830 case BFD_RELOC_ARM_TLS_DESCSEQ:
21831 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21832 case BFD_RELOC_ARM_GOT32:
21833 case BFD_RELOC_ARM_GOTOFF:
21834 case BFD_RELOC_ARM_GOT_PREL:
21835 case BFD_RELOC_ARM_PLT32:
21836 case BFD_RELOC_ARM_TARGET1:
21837 case BFD_RELOC_ARM_ROSEGREL32:
21838 case BFD_RELOC_ARM_SBREL32:
21839 case BFD_RELOC_ARM_PREL31:
21840 case BFD_RELOC_ARM_TARGET2:
21841 case BFD_RELOC_ARM_TLS_LE32:
21842 case BFD_RELOC_ARM_TLS_LDO32:
21843 case BFD_RELOC_ARM_PCREL_CALL:
21844 case BFD_RELOC_ARM_PCREL_JUMP:
21845 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21846 case BFD_RELOC_ARM_ALU_PC_G0:
21847 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21848 case BFD_RELOC_ARM_ALU_PC_G1:
21849 case BFD_RELOC_ARM_ALU_PC_G2:
21850 case BFD_RELOC_ARM_LDR_PC_G0:
21851 case BFD_RELOC_ARM_LDR_PC_G1:
21852 case BFD_RELOC_ARM_LDR_PC_G2:
21853 case BFD_RELOC_ARM_LDRS_PC_G0:
21854 case BFD_RELOC_ARM_LDRS_PC_G1:
21855 case BFD_RELOC_ARM_LDRS_PC_G2:
21856 case BFD_RELOC_ARM_LDC_PC_G0:
21857 case BFD_RELOC_ARM_LDC_PC_G1:
21858 case BFD_RELOC_ARM_LDC_PC_G2:
21859 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21860 case BFD_RELOC_ARM_ALU_SB_G0:
21861 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21862 case BFD_RELOC_ARM_ALU_SB_G1:
21863 case BFD_RELOC_ARM_ALU_SB_G2:
21864 case BFD_RELOC_ARM_LDR_SB_G0:
21865 case BFD_RELOC_ARM_LDR_SB_G1:
21866 case BFD_RELOC_ARM_LDR_SB_G2:
21867 case BFD_RELOC_ARM_LDRS_SB_G0:
21868 case BFD_RELOC_ARM_LDRS_SB_G1:
21869 case BFD_RELOC_ARM_LDRS_SB_G2:
21870 case BFD_RELOC_ARM_LDC_SB_G0:
21871 case BFD_RELOC_ARM_LDC_SB_G1:
21872 case BFD_RELOC_ARM_LDC_SB_G2:
21873 case BFD_RELOC_ARM_V4BX:
21874 code = fixp->fx_r_type;
21877 case BFD_RELOC_ARM_TLS_GOTDESC:
21878 case BFD_RELOC_ARM_TLS_GD32:
21879 case BFD_RELOC_ARM_TLS_IE32:
21880 case BFD_RELOC_ARM_TLS_LDM32:
21881 /* BFD will include the symbol's address in the addend.
21882 But we don't want that, so subtract it out again here. */
21883 if (!S_IS_COMMON (fixp->fx_addsy))
21884 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21885 code = fixp->fx_r_type;
21889 case BFD_RELOC_ARM_IMMEDIATE:
21890 as_bad_where (fixp->fx_file, fixp->fx_line,
21891 _("internal relocation (type: IMMEDIATE) not fixed up"));
21894 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21895 as_bad_where (fixp->fx_file, fixp->fx_line,
21896 _("ADRL used for a symbol not defined in the same file"));
21899 case BFD_RELOC_ARM_OFFSET_IMM:
21900 if (section->use_rela_p)
21902 code = fixp->fx_r_type;
21906 if (fixp->fx_addsy != NULL
21907 && !S_IS_DEFINED (fixp->fx_addsy)
21908 && S_IS_LOCAL (fixp->fx_addsy))
21910 as_bad_where (fixp->fx_file, fixp->fx_line,
21911 _("undefined local label `%s'"),
21912 S_GET_NAME (fixp->fx_addsy));
21916 as_bad_where (fixp->fx_file, fixp->fx_line,
21917 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21924 switch (fixp->fx_r_type)
21926 case BFD_RELOC_NONE: type = "NONE"; break;
21927 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21928 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21929 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21930 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21931 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21932 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21933 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21934 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21935 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21936 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21937 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21938 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21939 default: type = _("<unknown>"); break;
21941 as_bad_where (fixp->fx_file, fixp->fx_line,
21942 _("cannot represent %s relocation in this object file format"),
21949 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21951 && fixp->fx_addsy == GOT_symbol)
21953 code = BFD_RELOC_ARM_GOTPC;
21954 reloc->addend = fixp->fx_offset = reloc->address;
21958 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21960 if (reloc->howto == NULL)
21962 as_bad_where (fixp->fx_file, fixp->fx_line,
21963 _("cannot represent %s relocation in this object file format"),
21964 bfd_get_reloc_code_name (code));
21968 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21969 vtable entry to be used in the relocation's section offset. */
21970 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21971 reloc->address = fixp->fx_offset;
21976 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21979 cons_fix_new_arm (fragS * frag,
21984 bfd_reloc_code_real_type type;
21988 FIXME: @@ Should look at CPU word size. */
21992 type = BFD_RELOC_8;
21995 type = BFD_RELOC_16;
21999 type = BFD_RELOC_32;
22002 type = BFD_RELOC_64;
22007 if (exp->X_op == O_secrel)
22009 exp->X_op = O_symbol;
22010 type = BFD_RELOC_32_SECREL;
22014 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22017 #if defined (OBJ_COFF)
22019 arm_validate_fix (fixS * fixP)
22021 /* If the destination of the branch is a defined symbol which does not have
22022 the THUMB_FUNC attribute, then we must be calling a function which has
22023 the (interfacearm) attribute. We look for the Thumb entry point to that
22024 function and change the branch to refer to that function instead. */
22025 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22026 && fixP->fx_addsy != NULL
22027 && S_IS_DEFINED (fixP->fx_addsy)
22028 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22030 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22037 arm_force_relocation (struct fix * fixp)
22039 #if defined (OBJ_COFF) && defined (TE_PE)
22040 if (fixp->fx_r_type == BFD_RELOC_RVA)
22044 /* In case we have a call or a branch to a function in ARM ISA mode from
22045 a thumb function or vice-versa force the relocation. These relocations
22046 are cleared off for some cores that might have blx and simple transformations
22050 switch (fixp->fx_r_type)
22052 case BFD_RELOC_ARM_PCREL_JUMP:
22053 case BFD_RELOC_ARM_PCREL_CALL:
22054 case BFD_RELOC_THUMB_PCREL_BLX:
22055 if (THUMB_IS_FUNC (fixp->fx_addsy))
22059 case BFD_RELOC_ARM_PCREL_BLX:
22060 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22061 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22062 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22063 if (ARM_IS_FUNC (fixp->fx_addsy))
22072 /* Resolve these relocations even if the symbol is extern or weak.
22073 Technically this is probably wrong due to symbol preemption.
22074 In practice these relocations do not have enough range to be useful
22075 at dynamic link time, and some code (e.g. in the Linux kernel)
22076 expects these references to be resolved. */
22077 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22078 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22079 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22080 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22081 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22082 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22083 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22084 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22085 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22086 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22087 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22088 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22089 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22090 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22093 /* Always leave these relocations for the linker. */
22094 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22095 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22096 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22099 /* Always generate relocations against function symbols. */
22100 if (fixp->fx_r_type == BFD_RELOC_32
22102 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22105 return generic_force_reloc (fixp);
22108 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22109 /* Relocations against function names must be left unadjusted,
22110 so that the linker can use this information to generate interworking
22111 stubs. The MIPS version of this function
22112 also prevents relocations that are mips-16 specific, but I do not
22113 know why it does this.
22116 There is one other problem that ought to be addressed here, but
22117 which currently is not: Taking the address of a label (rather
22118 than a function) and then later jumping to that address. Such
22119 addresses also ought to have their bottom bit set (assuming that
22120 they reside in Thumb code), but at the moment they will not. */
22123 arm_fix_adjustable (fixS * fixP)
22125 if (fixP->fx_addsy == NULL)
22128 /* Preserve relocations against symbols with function type. */
22129 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22132 if (THUMB_IS_FUNC (fixP->fx_addsy)
22133 && fixP->fx_subsy == NULL)
22136 /* We need the symbol name for the VTABLE entries. */
22137 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22138 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22141 /* Don't allow symbols to be discarded on GOT related relocs. */
22142 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22143 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22144 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22145 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22146 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22147 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22148 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22149 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22150 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22151 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22152 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22153 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22154 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22155 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22158 /* Similarly for group relocations. */
22159 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22160 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22161 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22164 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22165 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22166 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22167 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22168 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22169 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22170 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22171 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22172 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22177 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22182 elf32_arm_target_format (void)
22185 return (target_big_endian
22186 ? "elf32-bigarm-symbian"
22187 : "elf32-littlearm-symbian");
22188 #elif defined (TE_VXWORKS)
22189 return (target_big_endian
22190 ? "elf32-bigarm-vxworks"
22191 : "elf32-littlearm-vxworks");
22193 if (target_big_endian)
22194 return "elf32-bigarm";
22196 return "elf32-littlearm";
22201 armelf_frob_symbol (symbolS * symp,
22204 elf_frob_symbol (symp, puntp);
22208 /* MD interface: Finalization. */
22213 literal_pool * pool;
22215 /* Ensure that all the IT blocks are properly closed. */
22216 check_it_blocks_finished ();
22218 for (pool = list_of_pools; pool; pool = pool->next)
22220 /* Put it at the end of the relevant section. */
22221 subseg_set (pool->section, pool->sub_section);
22223 arm_elf_change_section ();
22230 /* Remove any excess mapping symbols generated for alignment frags in
22231 SEC. We may have created a mapping symbol before a zero byte
22232 alignment; remove it if there's a mapping symbol after the
22235 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22236 void *dummy ATTRIBUTE_UNUSED)
22238 segment_info_type *seginfo = seg_info (sec);
22241 if (seginfo == NULL || seginfo->frchainP == NULL)
22244 for (fragp = seginfo->frchainP->frch_root;
22246 fragp = fragp->fr_next)
22248 symbolS *sym = fragp->tc_frag_data.last_map;
22249 fragS *next = fragp->fr_next;
22251 /* Variable-sized frags have been converted to fixed size by
22252 this point. But if this was variable-sized to start with,
22253 there will be a fixed-size frag after it. So don't handle
22255 if (sym == NULL || next == NULL)
22258 if (S_GET_VALUE (sym) < next->fr_address)
22259 /* Not at the end of this frag. */
22261 know (S_GET_VALUE (sym) == next->fr_address);
22265 if (next->tc_frag_data.first_map != NULL)
22267 /* Next frag starts with a mapping symbol. Discard this
22269 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22273 if (next->fr_next == NULL)
22275 /* This mapping symbol is at the end of the section. Discard
22277 know (next->fr_fix == 0 && next->fr_var == 0);
22278 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22282 /* As long as we have empty frags without any mapping symbols,
22284 /* If the next frag is non-empty and does not start with a
22285 mapping symbol, then this mapping symbol is required. */
22286 if (next->fr_address != next->fr_next->fr_address)
22289 next = next->fr_next;
22291 while (next != NULL);
22296 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22300 arm_adjust_symtab (void)
22305 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22307 if (ARM_IS_THUMB (sym))
22309 if (THUMB_IS_FUNC (sym))
22311 /* Mark the symbol as a Thumb function. */
22312 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22313 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22314 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22316 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22317 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22319 as_bad (_("%s: unexpected function type: %d"),
22320 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22322 else switch (S_GET_STORAGE_CLASS (sym))
22325 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22328 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22331 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22339 if (ARM_IS_INTERWORK (sym))
22340 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22347 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22349 if (ARM_IS_THUMB (sym))
22351 elf_symbol_type * elf_sym;
22353 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22354 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22356 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22357 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22359 /* If it's a .thumb_func, declare it as so,
22360 otherwise tag label as .code 16. */
22361 if (THUMB_IS_FUNC (sym))
22362 elf_sym->internal_elf_sym.st_target_internal
22363 = ST_BRANCH_TO_THUMB;
22364 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22365 elf_sym->internal_elf_sym.st_info =
22366 ELF_ST_INFO (bind, STT_ARM_16BIT);
22371 /* Remove any overlapping mapping symbols generated by alignment frags. */
22372 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22373 /* Now do generic ELF adjustments. */
22374 elf_adjust_symtab ();
22378 /* MD interface: Initialization. */
22381 set_constant_flonums (void)
22385 for (i = 0; i < NUM_FLOAT_VALS; i++)
22386 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22390 /* Auto-select Thumb mode if it's the only available instruction set for the
22391 given architecture. */
22394 autoselect_thumb_from_cpu_variant (void)
22396 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22397 opcode_select (16);
22406 if ( (arm_ops_hsh = hash_new ()) == NULL
22407 || (arm_cond_hsh = hash_new ()) == NULL
22408 || (arm_shift_hsh = hash_new ()) == NULL
22409 || (arm_psr_hsh = hash_new ()) == NULL
22410 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22411 || (arm_reg_hsh = hash_new ()) == NULL
22412 || (arm_reloc_hsh = hash_new ()) == NULL
22413 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22414 as_fatal (_("virtual memory exhausted"));
22416 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22417 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22418 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22419 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22420 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22421 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22422 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22423 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22424 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22425 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22426 (void *) (v7m_psrs + i));
22427 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22428 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22430 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22432 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22433 (void *) (barrier_opt_names + i));
22435 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22437 struct reloc_entry * entry = reloc_names + i;
22439 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22440 /* This makes encode_branch() use the EABI versions of this relocation. */
22441 entry->reloc = BFD_RELOC_UNUSED;
22443 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22447 set_constant_flonums ();
22449 /* Set the cpu variant based on the command-line options. We prefer
22450 -mcpu= over -march= if both are set (as for GCC); and we prefer
22451 -mfpu= over any other way of setting the floating point unit.
22452 Use of legacy options with new options are faulted. */
22455 if (mcpu_cpu_opt || march_cpu_opt)
22456 as_bad (_("use of old and new-style options to set CPU type"));
22458 mcpu_cpu_opt = legacy_cpu;
22460 else if (!mcpu_cpu_opt)
22461 mcpu_cpu_opt = march_cpu_opt;
22466 as_bad (_("use of old and new-style options to set FPU type"));
22468 mfpu_opt = legacy_fpu;
22470 else if (!mfpu_opt)
22472 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22473 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22474 /* Some environments specify a default FPU. If they don't, infer it
22475 from the processor. */
22477 mfpu_opt = mcpu_fpu_opt;
22479 mfpu_opt = march_fpu_opt;
22481 mfpu_opt = &fpu_default;
22487 if (mcpu_cpu_opt != NULL)
22488 mfpu_opt = &fpu_default;
22489 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22490 mfpu_opt = &fpu_arch_vfp_v2;
22492 mfpu_opt = &fpu_arch_fpa;
22498 mcpu_cpu_opt = &cpu_default;
22499 selected_cpu = cpu_default;
22503 selected_cpu = *mcpu_cpu_opt;
22505 mcpu_cpu_opt = &arm_arch_any;
22508 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22510 autoselect_thumb_from_cpu_variant ();
22512 arm_arch_used = thumb_arch_used = arm_arch_none;
22514 #if defined OBJ_COFF || defined OBJ_ELF
22516 unsigned int flags = 0;
22518 #if defined OBJ_ELF
22519 flags = meabi_flags;
22521 switch (meabi_flags)
22523 case EF_ARM_EABI_UNKNOWN:
22525 /* Set the flags in the private structure. */
22526 if (uses_apcs_26) flags |= F_APCS26;
22527 if (support_interwork) flags |= F_INTERWORK;
22528 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22529 if (pic_code) flags |= F_PIC;
22530 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22531 flags |= F_SOFT_FLOAT;
22533 switch (mfloat_abi_opt)
22535 case ARM_FLOAT_ABI_SOFT:
22536 case ARM_FLOAT_ABI_SOFTFP:
22537 flags |= F_SOFT_FLOAT;
22540 case ARM_FLOAT_ABI_HARD:
22541 if (flags & F_SOFT_FLOAT)
22542 as_bad (_("hard-float conflicts with specified fpu"));
22546 /* Using pure-endian doubles (even if soft-float). */
22547 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22548 flags |= F_VFP_FLOAT;
22550 #if defined OBJ_ELF
22551 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22552 flags |= EF_ARM_MAVERICK_FLOAT;
22555 case EF_ARM_EABI_VER4:
22556 case EF_ARM_EABI_VER5:
22557 /* No additional flags to set. */
22564 bfd_set_private_flags (stdoutput, flags);
22566 /* We have run out flags in the COFF header to encode the
22567 status of ATPCS support, so instead we create a dummy,
22568 empty, debug section called .arm.atpcs. */
22573 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22577 bfd_set_section_flags
22578 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22579 bfd_set_section_size (stdoutput, sec, 0);
22580 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22586 /* Record the CPU type as well. */
22587 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22588 mach = bfd_mach_arm_iWMMXt2;
22589 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22590 mach = bfd_mach_arm_iWMMXt;
22591 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22592 mach = bfd_mach_arm_XScale;
22593 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22594 mach = bfd_mach_arm_ep9312;
22595 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22596 mach = bfd_mach_arm_5TE;
22597 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22599 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22600 mach = bfd_mach_arm_5T;
22602 mach = bfd_mach_arm_5;
22604 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22606 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22607 mach = bfd_mach_arm_4T;
22609 mach = bfd_mach_arm_4;
22611 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22612 mach = bfd_mach_arm_3M;
22613 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22614 mach = bfd_mach_arm_3;
22615 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22616 mach = bfd_mach_arm_2a;
22617 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22618 mach = bfd_mach_arm_2;
22620 mach = bfd_mach_arm_unknown;
22622 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22625 /* Command line processing. */
22628 Invocation line includes a switch not recognized by the base assembler.
22629 See if it's a processor-specific option.
22631 This routine is somewhat complicated by the need for backwards
22632 compatibility (since older releases of gcc can't be changed).
22633 The new options try to make the interface as compatible as
22636 New options (supported) are:
22638 -mcpu=<cpu name> Assemble for selected processor
22639 -march=<architecture name> Assemble for selected architecture
22640 -mfpu=<fpu architecture> Assemble for selected FPU.
22641 -EB/-mbig-endian Big-endian
22642 -EL/-mlittle-endian Little-endian
22643 -k Generate PIC code
22644 -mthumb Start in Thumb mode
22645 -mthumb-interwork Code supports ARM/Thumb interworking
22647 -m[no-]warn-deprecated Warn about deprecated features
22649 For now we will also provide support for:
22651 -mapcs-32 32-bit Program counter
22652 -mapcs-26 26-bit Program counter
22653 -macps-float Floats passed in FP registers
22654 -mapcs-reentrant Reentrant code
22656 (sometime these will probably be replaced with -mapcs=<list of options>
22657 and -matpcs=<list of options>)
22659 The remaining options are only supported for back-wards compatibility.
22660 Cpu variants, the arm part is optional:
22661 -m[arm]1 Currently not supported.
22662 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22663 -m[arm]3 Arm 3 processor
22664 -m[arm]6[xx], Arm 6 processors
22665 -m[arm]7[xx][t][[d]m] Arm 7 processors
22666 -m[arm]8[10] Arm 8 processors
22667 -m[arm]9[20][tdmi] Arm 9 processors
22668 -mstrongarm[110[0]] StrongARM processors
22669 -mxscale XScale processors
22670 -m[arm]v[2345[t[e]]] Arm architectures
22671 -mall All (except the ARM1)
22673 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22674 -mfpe-old (No float load/store multiples)
22675 -mvfpxd VFP Single precision
22677 -mno-fpu Disable all floating point instructions
22679 The following CPU names are recognized:
22680 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22681 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22682 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22683 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22684 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22685 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22686 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22690 const char * md_shortopts = "m:k";
22692 #ifdef ARM_BI_ENDIAN
22693 #define OPTION_EB (OPTION_MD_BASE + 0)
22694 #define OPTION_EL (OPTION_MD_BASE + 1)
22696 #if TARGET_BYTES_BIG_ENDIAN
22697 #define OPTION_EB (OPTION_MD_BASE + 0)
22699 #define OPTION_EL (OPTION_MD_BASE + 1)
22702 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22704 struct option md_longopts[] =
22707 {"EB", no_argument, NULL, OPTION_EB},
22710 {"EL", no_argument, NULL, OPTION_EL},
22712 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22713 {NULL, no_argument, NULL, 0}
22716 size_t md_longopts_size = sizeof (md_longopts);
22718 struct arm_option_table
22720 char *option; /* Option name to match. */
22721 char *help; /* Help information. */
22722 int *var; /* Variable to change. */
22723 int value; /* What to change it to. */
22724 char *deprecated; /* If non-null, print this message. */
22727 struct arm_option_table arm_opts[] =
22729 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22730 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22731 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22732 &support_interwork, 1, NULL},
22733 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22734 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22735 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22737 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22738 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22739 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22740 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22743 /* These are recognized by the assembler, but have no affect on code. */
22744 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22745 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22747 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22748 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22749 &warn_on_deprecated, 0, NULL},
22750 {NULL, NULL, NULL, 0, NULL}
22753 struct arm_legacy_option_table
22755 char *option; /* Option name to match. */
22756 const arm_feature_set **var; /* Variable to change. */
22757 const arm_feature_set value; /* What to change it to. */
22758 char *deprecated; /* If non-null, print this message. */
22761 const struct arm_legacy_option_table arm_legacy_opts[] =
22763 /* DON'T add any new processors to this list -- we want the whole list
22764 to go away... Add them to the processors table instead. */
22765 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22766 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22767 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22768 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22769 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22770 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22771 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22772 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22773 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22774 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22775 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22776 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22777 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22778 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22779 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22780 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22781 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22782 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22783 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22784 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22785 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22786 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22787 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22788 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22789 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22790 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22791 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22792 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22793 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22794 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22795 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22796 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22797 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22798 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22799 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22800 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22801 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22802 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22803 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22804 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22805 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22806 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22807 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22808 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22809 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22810 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22811 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22812 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22813 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22814 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22815 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22816 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22817 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22818 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22819 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22820 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22821 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22822 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22823 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22824 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22825 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22826 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22827 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22828 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22829 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22830 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22831 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22832 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22833 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22834 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22835 N_("use -mcpu=strongarm110")},
22836 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22837 N_("use -mcpu=strongarm1100")},
22838 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22839 N_("use -mcpu=strongarm1110")},
22840 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22841 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22842 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22844 /* Architecture variants -- don't add any more to this list either. */
22845 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22846 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22847 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22848 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22849 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22850 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22851 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22852 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22853 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22854 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22855 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22856 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22857 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22858 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22859 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22860 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22861 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22862 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22864 /* Floating point variants -- don't add any more to this list either. */
22865 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22866 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22867 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22868 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22869 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22871 {NULL, NULL, ARM_ARCH_NONE, NULL}
22874 struct arm_cpu_option_table
22877 const arm_feature_set value;
22878 /* For some CPUs we assume an FPU unless the user explicitly sets
22880 const arm_feature_set default_fpu;
22881 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22883 const char *canonical_name;
22886 /* This list should, at a minimum, contain all the cpu names
22887 recognized by GCC. */
22888 static const struct arm_cpu_option_table arm_cpus[] =
22890 {"all", ARM_ANY, FPU_ARCH_FPA, NULL},
22891 {"arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL},
22892 {"arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL},
22893 {"arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22894 {"arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL},
22895 {"arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22896 {"arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22897 {"arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22898 {"arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22899 {"arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22900 {"arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22901 {"arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22902 {"arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22903 {"arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22904 {"arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22905 {"arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL},
22906 {"arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22907 {"arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22908 {"arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22909 {"arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22910 {"arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22911 {"arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22912 {"arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22913 {"arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22914 {"arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22915 {"arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22916 {"arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22917 {"arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL},
22918 {"arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22919 {"arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22920 {"arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22921 {"arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22922 {"arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22923 {"strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22924 {"strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22925 {"strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22926 {"strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22927 {"strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22928 {"arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22929 {"arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"},
22930 {"arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22931 {"arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22932 {"arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22933 {"arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL},
22934 {"fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22935 {"fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL},
22936 /* For V5 or later processors we default to using VFP; but the user
22937 should really set the FPU type explicitly. */
22938 {"arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22939 {"arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22940 {"arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22941 {"arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"},
22942 {"arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22943 {"arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22944 {"arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"},
22945 {"arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22946 {"arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL},
22947 {"arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"},
22948 {"arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22949 {"arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22950 {"arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22951 {"arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22952 {"arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22953 {"arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"},
22954 {"arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL},
22955 {"arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22956 {"arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22957 {"arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM1026EJ-S"},
22958 {"arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL},
22959 {"fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22960 {"fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22961 {"fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22962 {"fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22963 {"fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL},
22964 {"arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"},
22965 {"arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL},
22966 {"arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2, "ARM1136JF-S"},
22967 {"arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL},
22968 {"mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"},
22969 {"mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"},
22970 {"arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL},
22971 {"arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL},
22972 {"arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL},
22973 {"arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL},
22974 {"cortex-a5", ARM_ARCH_V7A_MP_SEC,
22975 FPU_NONE, "Cortex-A5"},
22976 {"cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22977 FPU_ARCH_NEON_VFP_V4,
22979 {"cortex-a8", ARM_ARCH_V7A_SEC,
22980 ARM_FEATURE (0, FPU_VFP_V3
22981 | FPU_NEON_EXT_V1),
22983 {"cortex-a9", ARM_ARCH_V7A_MP_SEC,
22984 ARM_FEATURE (0, FPU_VFP_V3
22985 | FPU_NEON_EXT_V1),
22987 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22988 FPU_ARCH_NEON_VFP_V4,
22990 {"cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"},
22991 {"cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
22993 {"cortex-r5", ARM_ARCH_V7R_IDIV,
22994 FPU_NONE, "Cortex-R5"},
22995 {"cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"},
22996 {"cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"},
22997 {"cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"},
22998 {"cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"},
22999 /* ??? XSCALE is really an architecture. */
23000 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
23001 /* ??? iwmmxt is not a processor. */
23002 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL},
23003 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL},
23004 {"i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
23006 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"},
23007 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL}
23010 struct arm_arch_option_table
23013 const arm_feature_set value;
23014 const arm_feature_set default_fpu;
23017 /* This list should, at a minimum, contain all the architecture names
23018 recognized by GCC. */
23019 static const struct arm_arch_option_table arm_archs[] =
23021 {"all", ARM_ANY, FPU_ARCH_FPA},
23022 {"armv1", ARM_ARCH_V1, FPU_ARCH_FPA},
23023 {"armv2", ARM_ARCH_V2, FPU_ARCH_FPA},
23024 {"armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA},
23025 {"armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA},
23026 {"armv3", ARM_ARCH_V3, FPU_ARCH_FPA},
23027 {"armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA},
23028 {"armv4", ARM_ARCH_V4, FPU_ARCH_FPA},
23029 {"armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA},
23030 {"armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA},
23031 {"armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA},
23032 {"armv5", ARM_ARCH_V5, FPU_ARCH_VFP},
23033 {"armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP},
23034 {"armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP},
23035 {"armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP},
23036 {"armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP},
23037 {"armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP},
23038 {"armv6", ARM_ARCH_V6, FPU_ARCH_VFP},
23039 {"armv6j", ARM_ARCH_V6, FPU_ARCH_VFP},
23040 {"armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP},
23041 {"armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP},
23042 {"armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP},
23043 {"armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP},
23044 {"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
23045 {"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
23046 {"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
23047 {"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
23048 {"armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP},
23049 {"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
23050 /* The official spelling of the ARMv7 profile variants is the dashed form.
23051 Accept the non-dashed form for compatibility with old toolchains. */
23052 {"armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23053 {"armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23054 {"armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23055 {"armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP},
23056 {"armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP},
23057 {"armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP},
23058 {"armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP},
23059 {"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP},
23060 {"iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP},
23061 {"iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP},
23062 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23065 /* ISA extensions in the co-processor and main instruction set space. */
23066 struct arm_option_extension_value_table
23069 const arm_feature_set value;
23070 const arm_feature_set allowed_archs;
23073 /* The following table must be in alphabetical order with a NULL last entry.
23075 static const struct arm_option_extension_value_table arm_extensions[] =
23077 {"idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23078 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23079 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY},
23080 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY},
23081 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY},
23082 {"mp", ARM_FEATURE (ARM_EXT_MP, 0),
23083 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)},
23084 {"os", ARM_FEATURE (ARM_EXT_OS, 0),
23085 ARM_FEATURE (ARM_EXT_V6M, 0)},
23086 {"sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23087 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)},
23088 {"virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23089 ARM_FEATURE (ARM_EXT_V7A, 0)},
23090 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY},
23091 {NULL, ARM_ARCH_NONE, ARM_ARCH_NONE}
23094 /* ISA floating-point and Advanced SIMD extensions. */
23095 struct arm_option_fpu_value_table
23098 const arm_feature_set value;
23101 /* This list should, at a minimum, contain all the fpu names
23102 recognized by GCC. */
23103 static const struct arm_option_fpu_value_table arm_fpus[] =
23105 {"softfpa", FPU_NONE},
23106 {"fpe", FPU_ARCH_FPE},
23107 {"fpe2", FPU_ARCH_FPE},
23108 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23109 {"fpa", FPU_ARCH_FPA},
23110 {"fpa10", FPU_ARCH_FPA},
23111 {"fpa11", FPU_ARCH_FPA},
23112 {"arm7500fe", FPU_ARCH_FPA},
23113 {"softvfp", FPU_ARCH_VFP},
23114 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23115 {"vfp", FPU_ARCH_VFP_V2},
23116 {"vfp9", FPU_ARCH_VFP_V2},
23117 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23118 {"vfp10", FPU_ARCH_VFP_V2},
23119 {"vfp10-r0", FPU_ARCH_VFP_V1},
23120 {"vfpxd", FPU_ARCH_VFP_V1xD},
23121 {"vfpv2", FPU_ARCH_VFP_V2},
23122 {"vfpv3", FPU_ARCH_VFP_V3},
23123 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23124 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23125 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23126 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23127 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23128 {"arm1020t", FPU_ARCH_VFP_V1},
23129 {"arm1020e", FPU_ARCH_VFP_V2},
23130 {"arm1136jfs", FPU_ARCH_VFP_V2},
23131 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23132 {"maverick", FPU_ARCH_MAVERICK},
23133 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23134 {"neon-fp16", FPU_ARCH_NEON_FP16},
23135 {"vfpv4", FPU_ARCH_VFP_V4},
23136 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23137 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23138 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23139 {NULL, ARM_ARCH_NONE}
23142 struct arm_option_value_table
23148 static const struct arm_option_value_table arm_float_abis[] =
23150 {"hard", ARM_FLOAT_ABI_HARD},
23151 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23152 {"soft", ARM_FLOAT_ABI_SOFT},
23157 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23158 static const struct arm_option_value_table arm_eabis[] =
23160 {"gnu", EF_ARM_EABI_UNKNOWN},
23161 {"4", EF_ARM_EABI_VER4},
23162 {"5", EF_ARM_EABI_VER5},
23167 struct arm_long_option_table
23169 char * option; /* Substring to match. */
23170 char * help; /* Help information. */
23171 int (* func) (char * subopt); /* Function to decode sub-option. */
23172 char * deprecated; /* If non-null, print this message. */
23176 arm_parse_extension (char * str, const arm_feature_set **opt_p)
23178 arm_feature_set *ext_set = (arm_feature_set *)
23179 xmalloc (sizeof (arm_feature_set));
23181 /* We insist on extensions being specified in alphabetical order, and with
23182 extensions being added before being removed. We achieve this by having
23183 the global ARM_EXTENSIONS table in alphabetical order, and using the
23184 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23185 or removing it (0) and only allowing it to change in the order
23187 const struct arm_option_extension_value_table * opt = NULL;
23188 int adding_value = -1;
23190 /* Copy the feature set, so that we can modify it. */
23191 *ext_set = **opt_p;
23194 while (str != NULL && *str != 0)
23201 as_bad (_("invalid architectural extension"));
23206 ext = strchr (str, '+');
23209 optlen = ext - str;
23211 optlen = strlen (str);
23214 && strncmp (str, "no", 2) == 0)
23216 if (adding_value != 0)
23219 opt = arm_extensions;
23225 else if (optlen > 0)
23227 if (adding_value == -1)
23230 opt = arm_extensions;
23232 else if (adding_value != 1)
23234 as_bad (_("must specify extensions to add before specifying "
23235 "those to remove"));
23242 as_bad (_("missing architectural extension"));
23246 gas_assert (adding_value != -1);
23247 gas_assert (opt != NULL);
23249 /* Scan over the options table trying to find an exact match. */
23250 for (; opt->name != NULL; opt++)
23251 if (strncmp (opt->name, str, optlen) == 0
23252 && strlen (opt->name) == optlen)
23254 /* Check we can apply the extension to this architecture. */
23255 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23257 as_bad (_("extension does not apply to the base architecture"));
23261 /* Add or remove the extension. */
23263 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23265 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23270 if (opt->name == NULL)
23272 /* Did we fail to find an extension because it wasn't specified in
23273 alphabetical order, or because it does not exist? */
23275 for (opt = arm_extensions; opt->name != NULL; opt++)
23276 if (strncmp (opt->name, str, optlen) == 0)
23279 if (opt->name == NULL)
23280 as_bad (_("unknown architectural extension `%s'"), str);
23282 as_bad (_("architectural extensions must be specified in "
23283 "alphabetical order"));
23289 /* We should skip the extension we've just matched the next time
23301 arm_parse_cpu (char * str)
23303 const struct arm_cpu_option_table * opt;
23304 char * ext = strchr (str, '+');
23308 optlen = ext - str;
23310 optlen = strlen (str);
23314 as_bad (_("missing cpu name `%s'"), str);
23318 for (opt = arm_cpus; opt->name != NULL; opt++)
23319 if (strncmp (opt->name, str, optlen) == 0)
23321 mcpu_cpu_opt = &opt->value;
23322 mcpu_fpu_opt = &opt->default_fpu;
23323 if (opt->canonical_name)
23324 strcpy (selected_cpu_name, opt->canonical_name);
23329 for (i = 0; i < optlen; i++)
23330 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23331 selected_cpu_name[i] = 0;
23335 return arm_parse_extension (ext, &mcpu_cpu_opt);
23340 as_bad (_("unknown cpu `%s'"), str);
23345 arm_parse_arch (char * str)
23347 const struct arm_arch_option_table *opt;
23348 char *ext = strchr (str, '+');
23352 optlen = ext - str;
23354 optlen = strlen (str);
23358 as_bad (_("missing architecture name `%s'"), str);
23362 for (opt = arm_archs; opt->name != NULL; opt++)
23363 if (strncmp (opt->name, str, optlen) == 0)
23365 march_cpu_opt = &opt->value;
23366 march_fpu_opt = &opt->default_fpu;
23367 strcpy (selected_cpu_name, opt->name);
23370 return arm_parse_extension (ext, &march_cpu_opt);
23375 as_bad (_("unknown architecture `%s'\n"), str);
23380 arm_parse_fpu (char * str)
23382 const struct arm_option_fpu_value_table * opt;
23384 for (opt = arm_fpus; opt->name != NULL; opt++)
23385 if (streq (opt->name, str))
23387 mfpu_opt = &opt->value;
23391 as_bad (_("unknown floating point format `%s'\n"), str);
23396 arm_parse_float_abi (char * str)
23398 const struct arm_option_value_table * opt;
23400 for (opt = arm_float_abis; opt->name != NULL; opt++)
23401 if (streq (opt->name, str))
23403 mfloat_abi_opt = opt->value;
23407 as_bad (_("unknown floating point abi `%s'\n"), str);
23413 arm_parse_eabi (char * str)
23415 const struct arm_option_value_table *opt;
23417 for (opt = arm_eabis; opt->name != NULL; opt++)
23418 if (streq (opt->name, str))
23420 meabi_flags = opt->value;
23423 as_bad (_("unknown EABI `%s'\n"), str);
23429 arm_parse_it_mode (char * str)
23431 bfd_boolean ret = TRUE;
23433 if (streq ("arm", str))
23434 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23435 else if (streq ("thumb", str))
23436 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23437 else if (streq ("always", str))
23438 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23439 else if (streq ("never", str))
23440 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23443 as_bad (_("unknown implicit IT mode `%s', should be "\
23444 "arm, thumb, always, or never."), str);
23451 struct arm_long_option_table arm_long_opts[] =
23453 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23454 arm_parse_cpu, NULL},
23455 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23456 arm_parse_arch, NULL},
23457 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23458 arm_parse_fpu, NULL},
23459 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23460 arm_parse_float_abi, NULL},
23462 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23463 arm_parse_eabi, NULL},
23465 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23466 arm_parse_it_mode, NULL},
23467 {NULL, NULL, 0, NULL}
23471 md_parse_option (int c, char * arg)
23473 struct arm_option_table *opt;
23474 const struct arm_legacy_option_table *fopt;
23475 struct arm_long_option_table *lopt;
23481 target_big_endian = 1;
23487 target_big_endian = 0;
23491 case OPTION_FIX_V4BX:
23496 /* Listing option. Just ignore these, we don't support additional
23501 for (opt = arm_opts; opt->option != NULL; opt++)
23503 if (c == opt->option[0]
23504 && ((arg == NULL && opt->option[1] == 0)
23505 || streq (arg, opt->option + 1)))
23507 /* If the option is deprecated, tell the user. */
23508 if (warn_on_deprecated && opt->deprecated != NULL)
23509 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23510 arg ? arg : "", _(opt->deprecated));
23512 if (opt->var != NULL)
23513 *opt->var = opt->value;
23519 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23521 if (c == fopt->option[0]
23522 && ((arg == NULL && fopt->option[1] == 0)
23523 || streq (arg, fopt->option + 1)))
23525 /* If the option is deprecated, tell the user. */
23526 if (warn_on_deprecated && fopt->deprecated != NULL)
23527 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23528 arg ? arg : "", _(fopt->deprecated));
23530 if (fopt->var != NULL)
23531 *fopt->var = &fopt->value;
23537 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23539 /* These options are expected to have an argument. */
23540 if (c == lopt->option[0]
23542 && strncmp (arg, lopt->option + 1,
23543 strlen (lopt->option + 1)) == 0)
23545 /* If the option is deprecated, tell the user. */
23546 if (warn_on_deprecated && lopt->deprecated != NULL)
23547 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23548 _(lopt->deprecated));
23550 /* Call the sup-option parser. */
23551 return lopt->func (arg + strlen (lopt->option) - 1);
23562 md_show_usage (FILE * fp)
23564 struct arm_option_table *opt;
23565 struct arm_long_option_table *lopt;
23567 fprintf (fp, _(" ARM-specific assembler options:\n"));
23569 for (opt = arm_opts; opt->option != NULL; opt++)
23570 if (opt->help != NULL)
23571 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23573 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23574 if (lopt->help != NULL)
23575 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23579 -EB assemble code for a big-endian cpu\n"));
23584 -EL assemble code for a little-endian cpu\n"));
23588 --fix-v4bx Allow BX in ARMv4 code\n"));
23596 arm_feature_set flags;
23597 } cpu_arch_ver_table;
23599 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23600 least features first. */
23601 static const cpu_arch_ver_table cpu_arch_ver[] =
23607 {4, ARM_ARCH_V5TE},
23608 {5, ARM_ARCH_V5TEJ},
23612 {11, ARM_ARCH_V6M},
23613 {12, ARM_ARCH_V6SM},
23614 {8, ARM_ARCH_V6T2},
23615 {10, ARM_ARCH_V7A},
23616 {10, ARM_ARCH_V7R},
23617 {10, ARM_ARCH_V7M},
23621 /* Set an attribute if it has not already been set by the user. */
23623 aeabi_set_attribute_int (int tag, int value)
23626 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23627 || !attributes_set_explicitly[tag])
23628 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23632 aeabi_set_attribute_string (int tag, const char *value)
23635 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23636 || !attributes_set_explicitly[tag])
23637 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23640 /* Set the public EABI object attributes. */
23642 aeabi_set_public_attributes (void)
23646 arm_feature_set flags;
23647 arm_feature_set tmp;
23648 const cpu_arch_ver_table *p;
23650 /* Choose the architecture based on the capabilities of the requested cpu
23651 (if any) and/or the instructions actually used. */
23652 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23653 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23654 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23655 /*Allow the user to override the reported architecture. */
23658 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23659 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23662 /* We need to make sure that the attributes do not identify us as v6S-M
23663 when the only v6S-M feature in use is the Operating System Extensions. */
23664 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23665 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23666 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23670 for (p = cpu_arch_ver; p->val; p++)
23672 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23675 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23679 /* The table lookup above finds the last architecture to contribute
23680 a new feature. Unfortunately, Tag13 is a subset of the union of
23681 v6T2 and v7-M, so it is never seen as contributing a new feature.
23682 We can not search for the last entry which is entirely used,
23683 because if no CPU is specified we build up only those flags
23684 actually used. Perhaps we should separate out the specified
23685 and implicit cases. Avoid taking this path for -march=all by
23686 checking for contradictory v7-A / v7-M features. */
23688 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23689 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23690 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23693 /* Tag_CPU_name. */
23694 if (selected_cpu_name[0])
23698 q = selected_cpu_name;
23699 if (strncmp (q, "armv", 4) == 0)
23704 for (i = 0; q[i]; i++)
23705 q[i] = TOUPPER (q[i]);
23707 aeabi_set_attribute_string (Tag_CPU_name, q);
23710 /* Tag_CPU_arch. */
23711 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23713 /* Tag_CPU_arch_profile. */
23714 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23715 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23716 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23717 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23718 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23719 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23721 /* Tag_ARM_ISA_use. */
23722 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23724 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23726 /* Tag_THUMB_ISA_use. */
23727 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23729 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23730 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23732 /* Tag_VFP_arch. */
23733 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23734 aeabi_set_attribute_int (Tag_VFP_arch,
23735 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23737 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23738 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23739 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23740 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23741 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23742 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23743 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23744 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23745 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23747 /* Tag_ABI_HardFP_use. */
23748 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23749 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23750 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23752 /* Tag_WMMX_arch. */
23753 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23754 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23755 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23756 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23758 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23759 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23760 aeabi_set_attribute_int
23761 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23764 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23765 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23766 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23769 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23770 aeabi_set_attribute_int (Tag_DIV_use, 2);
23771 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23772 aeabi_set_attribute_int (Tag_DIV_use, 0);
23774 aeabi_set_attribute_int (Tag_DIV_use, 1);
23776 /* Tag_MP_extension_use. */
23777 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23778 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23780 /* Tag Virtualization_use. */
23781 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23783 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23786 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23789 /* Add the default contents for the .ARM.attributes section. */
23793 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23796 aeabi_set_public_attributes ();
23798 #endif /* OBJ_ELF */
23801 /* Parse a .cpu directive. */
23804 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23806 const struct arm_cpu_option_table *opt;
23810 name = input_line_pointer;
23811 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23812 input_line_pointer++;
23813 saved_char = *input_line_pointer;
23814 *input_line_pointer = 0;
23816 /* Skip the first "all" entry. */
23817 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23818 if (streq (opt->name, name))
23820 mcpu_cpu_opt = &opt->value;
23821 selected_cpu = opt->value;
23822 if (opt->canonical_name)
23823 strcpy (selected_cpu_name, opt->canonical_name);
23827 for (i = 0; opt->name[i]; i++)
23828 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23829 selected_cpu_name[i] = 0;
23831 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23832 *input_line_pointer = saved_char;
23833 demand_empty_rest_of_line ();
23836 as_bad (_("unknown cpu `%s'"), name);
23837 *input_line_pointer = saved_char;
23838 ignore_rest_of_line ();
23842 /* Parse a .arch directive. */
23845 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23847 const struct arm_arch_option_table *opt;
23851 name = input_line_pointer;
23852 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23853 input_line_pointer++;
23854 saved_char = *input_line_pointer;
23855 *input_line_pointer = 0;
23857 /* Skip the first "all" entry. */
23858 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23859 if (streq (opt->name, name))
23861 mcpu_cpu_opt = &opt->value;
23862 selected_cpu = opt->value;
23863 strcpy (selected_cpu_name, opt->name);
23864 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23865 *input_line_pointer = saved_char;
23866 demand_empty_rest_of_line ();
23870 as_bad (_("unknown architecture `%s'\n"), name);
23871 *input_line_pointer = saved_char;
23872 ignore_rest_of_line ();
23876 /* Parse a .object_arch directive. */
23879 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23881 const struct arm_arch_option_table *opt;
23885 name = input_line_pointer;
23886 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23887 input_line_pointer++;
23888 saved_char = *input_line_pointer;
23889 *input_line_pointer = 0;
23891 /* Skip the first "all" entry. */
23892 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23893 if (streq (opt->name, name))
23895 object_arch = &opt->value;
23896 *input_line_pointer = saved_char;
23897 demand_empty_rest_of_line ();
23901 as_bad (_("unknown architecture `%s'\n"), name);
23902 *input_line_pointer = saved_char;
23903 ignore_rest_of_line ();
23906 /* Parse a .arch_extension directive. */
23909 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23911 const struct arm_option_extension_value_table *opt;
23914 int adding_value = 1;
23916 name = input_line_pointer;
23917 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23918 input_line_pointer++;
23919 saved_char = *input_line_pointer;
23920 *input_line_pointer = 0;
23922 if (strlen (name) >= 2
23923 && strncmp (name, "no", 2) == 0)
23929 for (opt = arm_extensions; opt->name != NULL; opt++)
23930 if (streq (opt->name, name))
23932 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23934 as_bad (_("architectural extension `%s' is not allowed for the "
23935 "current base architecture"), name);
23940 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23942 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23944 mcpu_cpu_opt = &selected_cpu;
23945 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23946 *input_line_pointer = saved_char;
23947 demand_empty_rest_of_line ();
23951 if (opt->name == NULL)
23952 as_bad (_("unknown architecture `%s'\n"), name);
23954 *input_line_pointer = saved_char;
23955 ignore_rest_of_line ();
23958 /* Parse a .fpu directive. */
23961 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
23963 const struct arm_option_fpu_value_table *opt;
23967 name = input_line_pointer;
23968 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23969 input_line_pointer++;
23970 saved_char = *input_line_pointer;
23971 *input_line_pointer = 0;
23973 for (opt = arm_fpus; opt->name != NULL; opt++)
23974 if (streq (opt->name, name))
23976 mfpu_opt = &opt->value;
23977 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23978 *input_line_pointer = saved_char;
23979 demand_empty_rest_of_line ();
23983 as_bad (_("unknown floating point format `%s'\n"), name);
23984 *input_line_pointer = saved_char;
23985 ignore_rest_of_line ();
23988 /* Copy symbol information. */
23991 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
23993 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
23997 /* Given a symbolic attribute NAME, return the proper integer value.
23998 Returns -1 if the attribute is not known. */
24001 arm_convert_symbolic_attribute (const char *name)
24003 static const struct
24008 attribute_table[] =
24010 /* When you modify this table you should
24011 also modify the list in doc/c-arm.texi. */
24012 #define T(tag) {#tag, tag}
24013 T (Tag_CPU_raw_name),
24016 T (Tag_CPU_arch_profile),
24017 T (Tag_ARM_ISA_use),
24018 T (Tag_THUMB_ISA_use),
24022 T (Tag_Advanced_SIMD_arch),
24023 T (Tag_PCS_config),
24024 T (Tag_ABI_PCS_R9_use),
24025 T (Tag_ABI_PCS_RW_data),
24026 T (Tag_ABI_PCS_RO_data),
24027 T (Tag_ABI_PCS_GOT_use),
24028 T (Tag_ABI_PCS_wchar_t),
24029 T (Tag_ABI_FP_rounding),
24030 T (Tag_ABI_FP_denormal),
24031 T (Tag_ABI_FP_exceptions),
24032 T (Tag_ABI_FP_user_exceptions),
24033 T (Tag_ABI_FP_number_model),
24034 T (Tag_ABI_align_needed),
24035 T (Tag_ABI_align8_needed),
24036 T (Tag_ABI_align_preserved),
24037 T (Tag_ABI_align8_preserved),
24038 T (Tag_ABI_enum_size),
24039 T (Tag_ABI_HardFP_use),
24040 T (Tag_ABI_VFP_args),
24041 T (Tag_ABI_WMMX_args),
24042 T (Tag_ABI_optimization_goals),
24043 T (Tag_ABI_FP_optimization_goals),
24044 T (Tag_compatibility),
24045 T (Tag_CPU_unaligned_access),
24046 T (Tag_FP_HP_extension),
24047 T (Tag_VFP_HP_extension),
24048 T (Tag_ABI_FP_16bit_format),
24049 T (Tag_MPextension_use),
24051 T (Tag_nodefaults),
24052 T (Tag_also_compatible_with),
24053 T (Tag_conformance),
24055 T (Tag_Virtualization_use),
24056 /* We deliberately do not include Tag_MPextension_use_legacy. */
24064 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24065 if (streq (name, attribute_table[i].name))
24066 return attribute_table[i].tag;
24072 /* Apply sym value for relocations only in the case that
24073 they are for local symbols and you have the respective
24074 architectural feature for blx and simple switches. */
24076 arm_apply_sym_value (struct fix * fixP)
24079 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24080 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24082 switch (fixP->fx_r_type)
24084 case BFD_RELOC_ARM_PCREL_BLX:
24085 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24086 if (ARM_IS_FUNC (fixP->fx_addsy))
24090 case BFD_RELOC_ARM_PCREL_CALL:
24091 case BFD_RELOC_THUMB_PCREL_BLX:
24092 if (THUMB_IS_FUNC (fixP->fx_addsy))
24103 #endif /* OBJ_ELF */