1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
35 #include "libiberty.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS * table_entry;
55 symbolS * personality_routine;
56 int personality_index;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant;
129 static arm_feature_set arm_arch_used;
130 static arm_feature_set thumb_arch_used;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26 = FALSE;
134 static int atpcs = FALSE;
135 static int support_interwork = FALSE;
136 static int uses_apcs_float = FALSE;
137 static int pic_code = FALSE;
138 static int fix_v4bx = FALSE;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated = TRUE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
189 static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
190 static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
191 static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192 static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
193 static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194 static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195 static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196 static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
197 static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
198 static const arm_feature_set arm_ext_m =
199 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
200 static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
201 static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
202 static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
203 static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
204 static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
206 static const arm_feature_set arm_arch_any = ARM_ANY;
207 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
209 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
210 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
212 static const arm_feature_set arm_cext_iwmmxt2 =
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
214 static const arm_feature_set arm_cext_iwmmxt =
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
216 static const arm_feature_set arm_cext_xscale =
217 ARM_FEATURE (0, ARM_CEXT_XSCALE);
218 static const arm_feature_set arm_cext_maverick =
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
220 static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
221 static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
222 static const arm_feature_set fpu_vfp_ext_v1xd =
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
224 static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
225 static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
226 static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
227 static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
228 static const arm_feature_set fpu_vfp_ext_d32 =
229 ARM_FEATURE (0, FPU_VFP_EXT_D32);
230 static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
232 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
233 static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
234 static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
235 static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
237 static int mfloat_abi_opt = -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu.core == arm_arch_none.core
248 && selected_cpu.coproc == arm_arch_none.coproc;
253 static int meabi_flags = EABI_DEFAULT;
255 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
258 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
263 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS * GOT_symbol;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode = 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER = 0x00,
286 IMPLICIT_IT_MODE_ARM = 0x01,
287 IMPLICIT_IT_MODE_THUMB = 0x02,
288 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
290 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax = FALSE;
330 enum neon_el_type type;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el[NEON_MAX_TYPE_ELS];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN /* The IT insn has been parsed. */
354 /* The maximum number of operands we need. */
355 #define ARM_IT_MAX_OPERANDS 6
360 unsigned long instruction;
364 /* "uncond_value" is set to the value in place of the conditional field in
365 unconditional versions of the instruction, or -1 if nothing is
368 struct neon_type vectype;
369 /* This does not indicate an actual NEON instruction, only that
370 the mnemonic accepts neon-style type suffixes. */
372 /* Set to the opcode if the instruction needs relaxation.
373 Zero if the instruction is not relaxed. */
377 bfd_reloc_code_real_type type;
382 enum it_instruction_type it_insn_type;
388 struct neon_type_el vectype;
389 unsigned present : 1; /* Operand present. */
390 unsigned isreg : 1; /* Operand was a register. */
391 unsigned immisreg : 1; /* .imm field is a second register. */
392 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
393 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
394 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
395 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
396 instructions. This allows us to disambiguate ARM <-> vector insns. */
397 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
398 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
399 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
400 unsigned issingle : 1; /* Operand is VFP single-precision register. */
401 unsigned hasreloc : 1; /* Operand has relocation suffix. */
402 unsigned writeback : 1; /* Operand has trailing ! */
403 unsigned preind : 1; /* Preindexed address. */
404 unsigned postind : 1; /* Postindexed address. */
405 unsigned negative : 1; /* Index register was negated. */
406 unsigned shifted : 1; /* Shift applied to operation. */
407 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
408 } operands[ARM_IT_MAX_OPERANDS];
411 static struct arm_it inst;
413 #define NUM_FLOAT_VALS 8
415 const char * fp_const[] =
417 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
420 /* Number of littlenums required to hold an extended precision number. */
421 #define MAX_LITTLENUMS 6
423 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
433 #define CP_T_X 0x00008000
434 #define CP_T_Y 0x00400000
436 #define CONDS_BIT 0x00100000
437 #define LOAD_BIT 0x00100000
439 #define DOUBLE_LOAD_FLAG 0x00000001
443 const char * template_name;
447 #define COND_ALWAYS 0xE
451 const char * template_name;
455 struct asm_barrier_opt
457 const char * template_name;
461 /* The bit that distinguishes CPSR and SPSR. */
462 #define SPSR_BIT (1 << 22)
464 /* The individual PSR flag bits. */
465 #define PSR_c (1 << 16)
466 #define PSR_x (1 << 17)
467 #define PSR_s (1 << 18)
468 #define PSR_f (1 << 19)
473 bfd_reloc_code_real_type reloc;
478 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
479 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
484 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
487 /* Bits for DEFINED field in neon_typed_alias. */
488 #define NTA_HASTYPE 1
489 #define NTA_HASINDEX 2
491 struct neon_typed_alias
493 unsigned char defined;
495 struct neon_type_el eltype;
498 /* ARM register categories. This includes coprocessor numbers and various
499 architecture extensions' registers. */
526 /* Structure for a hash table entry for a register.
527 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
528 information which states whether a vector type or index is specified (for a
529 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
535 unsigned char builtin;
536 struct neon_typed_alias * neon;
539 /* Diagnostics used when we don't get a register of the expected type. */
540 const char * const reg_expected_msgs[] =
542 N_("ARM register expected"),
543 N_("bad or missing co-processor number"),
544 N_("co-processor register expected"),
545 N_("FPA register expected"),
546 N_("VFP single precision register expected"),
547 N_("VFP/Neon double precision register expected"),
548 N_("Neon quad precision register expected"),
549 N_("VFP single or double precision register expected"),
550 N_("Neon double or quad precision register expected"),
551 N_("VFP single, double or Neon quad precision register expected"),
552 N_("VFP system register expected"),
553 N_("Maverick MVF register expected"),
554 N_("Maverick MVD register expected"),
555 N_("Maverick MVFX register expected"),
556 N_("Maverick MVDX register expected"),
557 N_("Maverick MVAX register expected"),
558 N_("Maverick DSPSC register expected"),
559 N_("iWMMXt data register expected"),
560 N_("iWMMXt control register expected"),
561 N_("iWMMXt scalar register expected"),
562 N_("XScale accumulator register expected"),
565 /* Some well known registers that we refer to directly elsewhere. */
571 /* ARM instructions take 4bytes in the object file, Thumb instructions
577 /* Basic string to match. */
578 const char * template_name;
580 /* Parameters to instruction. */
581 unsigned int operands[8];
583 /* Conditional tag - see opcode_lookup. */
584 unsigned int tag : 4;
586 /* Basic instruction code. */
587 unsigned int avalue : 28;
589 /* Thumb-format instruction code. */
592 /* Which architecture variant provides this instruction. */
593 const arm_feature_set * avariant;
594 const arm_feature_set * tvariant;
596 /* Function to call to encode instruction in ARM format. */
597 void (* aencode) (void);
599 /* Function to call to encode instruction in Thumb format. */
600 void (* tencode) (void);
603 /* Defines for various bits that we will want to toggle. */
604 #define INST_IMMEDIATE 0x02000000
605 #define OFFSET_REG 0x02000000
606 #define HWOFFSET_IMM 0x00400000
607 #define SHIFT_BY_REG 0x00000010
608 #define PRE_INDEX 0x01000000
609 #define INDEX_UP 0x00800000
610 #define WRITE_BACK 0x00200000
611 #define LDM_TYPE_2_OR_3 0x00400000
612 #define CPSI_MMOD 0x00020000
614 #define LITERAL_MASK 0xf000f000
615 #define OPCODE_MASK 0xfe1fffff
616 #define V4_STR_BIT 0x00000020
618 #define T2_SUBS_PC_LR 0xf3de8f00
620 #define DATA_OP_SHIFT 21
622 #define T2_OPCODE_MASK 0xfe1fffff
623 #define T2_DATA_OP_SHIFT 21
625 /* Codes to distinguish the arithmetic instructions. */
636 #define OPCODE_CMP 10
637 #define OPCODE_CMN 11
638 #define OPCODE_ORR 12
639 #define OPCODE_MOV 13
640 #define OPCODE_BIC 14
641 #define OPCODE_MVN 15
643 #define T2_OPCODE_AND 0
644 #define T2_OPCODE_BIC 1
645 #define T2_OPCODE_ORR 2
646 #define T2_OPCODE_ORN 3
647 #define T2_OPCODE_EOR 4
648 #define T2_OPCODE_ADD 8
649 #define T2_OPCODE_ADC 10
650 #define T2_OPCODE_SBC 11
651 #define T2_OPCODE_SUB 13
652 #define T2_OPCODE_RSB 14
654 #define T_OPCODE_MUL 0x4340
655 #define T_OPCODE_TST 0x4200
656 #define T_OPCODE_CMN 0x42c0
657 #define T_OPCODE_NEG 0x4240
658 #define T_OPCODE_MVN 0x43c0
660 #define T_OPCODE_ADD_R3 0x1800
661 #define T_OPCODE_SUB_R3 0x1a00
662 #define T_OPCODE_ADD_HI 0x4400
663 #define T_OPCODE_ADD_ST 0xb000
664 #define T_OPCODE_SUB_ST 0xb080
665 #define T_OPCODE_ADD_SP 0xa800
666 #define T_OPCODE_ADD_PC 0xa000
667 #define T_OPCODE_ADD_I8 0x3000
668 #define T_OPCODE_SUB_I8 0x3800
669 #define T_OPCODE_ADD_I3 0x1c00
670 #define T_OPCODE_SUB_I3 0x1e00
672 #define T_OPCODE_ASR_R 0x4100
673 #define T_OPCODE_LSL_R 0x4080
674 #define T_OPCODE_LSR_R 0x40c0
675 #define T_OPCODE_ROR_R 0x41c0
676 #define T_OPCODE_ASR_I 0x1000
677 #define T_OPCODE_LSL_I 0x0000
678 #define T_OPCODE_LSR_I 0x0800
680 #define T_OPCODE_MOV_I8 0x2000
681 #define T_OPCODE_CMP_I8 0x2800
682 #define T_OPCODE_CMP_LR 0x4280
683 #define T_OPCODE_MOV_HR 0x4600
684 #define T_OPCODE_CMP_HR 0x4500
686 #define T_OPCODE_LDR_PC 0x4800
687 #define T_OPCODE_LDR_SP 0x9800
688 #define T_OPCODE_STR_SP 0x9000
689 #define T_OPCODE_LDR_IW 0x6800
690 #define T_OPCODE_STR_IW 0x6000
691 #define T_OPCODE_LDR_IH 0x8800
692 #define T_OPCODE_STR_IH 0x8000
693 #define T_OPCODE_LDR_IB 0x7800
694 #define T_OPCODE_STR_IB 0x7000
695 #define T_OPCODE_LDR_RW 0x5800
696 #define T_OPCODE_STR_RW 0x5000
697 #define T_OPCODE_LDR_RH 0x5a00
698 #define T_OPCODE_STR_RH 0x5200
699 #define T_OPCODE_LDR_RB 0x5c00
700 #define T_OPCODE_STR_RB 0x5400
702 #define T_OPCODE_PUSH 0xb400
703 #define T_OPCODE_POP 0xbc00
705 #define T_OPCODE_BRANCH 0xe000
707 #define THUMB_SIZE 2 /* Size of thumb instruction. */
708 #define THUMB_PP_PC_LR 0x0100
709 #define THUMB_LOAD_BIT 0x0800
710 #define THUMB2_LOAD_BIT 0x00100000
712 #define BAD_ARGS _("bad arguments to instruction")
713 #define BAD_SP _("r13 not allowed here")
714 #define BAD_PC _("r15 not allowed here")
715 #define BAD_COND _("instruction cannot be conditional")
716 #define BAD_OVERLAP _("registers may not be the same")
717 #define BAD_HIREG _("lo register required")
718 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
719 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
720 #define BAD_BRANCH _("branch must be last instruction in IT block")
721 #define BAD_NOT_IT _("instruction not allowed in IT block")
722 #define BAD_FPU _("selected FPU does not support instruction")
723 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
724 #define BAD_IT_COND _("incorrect condition in IT block")
725 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
726 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
727 #define BAD_PC_ADDRESSING \
728 _("cannot use register index with PC-relative addressing")
729 #define BAD_PC_WRITEBACK \
730 _("cannot use writeback with PC-relative addressing")
731 #define BAD_RANGE _("branch out of range")
733 static struct hash_control * arm_ops_hsh;
734 static struct hash_control * arm_cond_hsh;
735 static struct hash_control * arm_shift_hsh;
736 static struct hash_control * arm_psr_hsh;
737 static struct hash_control * arm_v7m_psr_hsh;
738 static struct hash_control * arm_reg_hsh;
739 static struct hash_control * arm_reloc_hsh;
740 static struct hash_control * arm_barrier_opt_hsh;
742 /* Stuff needed to resolve the label ambiguity
751 symbolS * last_label_seen;
752 static int label_is_thumb_function_name = FALSE;
754 /* Literal pool structure. Held on a per-section
755 and per-sub-section basis. */
757 #define MAX_LITERAL_POOL_SIZE 1024
758 typedef struct literal_pool
760 expressionS literals [MAX_LITERAL_POOL_SIZE];
761 unsigned int next_free_entry;
767 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
769 struct literal_pool * next;
772 /* Pointer to a linked list of literal pools. */
773 literal_pool * list_of_pools = NULL;
776 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
778 static struct current_it now_it;
782 now_it_compatible (int cond)
784 return (cond & ~1) == (now_it.cc & ~1);
788 conditional_insn (void)
790 return inst.cond != COND_ALWAYS;
793 static int in_it_block (void);
795 static int handle_it_state (void);
797 static void force_automatic_it_block_close (void);
799 static void it_fsm_post_encode (void);
801 #define set_it_insn_type(type) \
804 inst.it_insn_type = type; \
805 if (handle_it_state () == FAIL) \
810 #define set_it_insn_type_nonvoid(type, failret) \
813 inst.it_insn_type = type; \
814 if (handle_it_state () == FAIL) \
819 #define set_it_insn_type_last() \
822 if (inst.cond == COND_ALWAYS) \
823 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
825 set_it_insn_type (INSIDE_IT_LAST_INSN); \
831 /* This array holds the chars that always start a comment. If the
832 pre-processor is disabled, these aren't very useful. */
833 const char comment_chars[] = "@";
835 /* This array holds the chars that only start a comment at the beginning of
836 a line. If the line seems to have the form '# 123 filename'
837 .line and .file directives will appear in the pre-processed output. */
838 /* Note that input_file.c hand checks for '#' at the beginning of the
839 first line of the input file. This is because the compiler outputs
840 #NO_APP at the beginning of its output. */
841 /* Also note that comments like this one will always work. */
842 const char line_comment_chars[] = "#";
844 const char line_separator_chars[] = ";";
846 /* Chars that can be used to separate mant
847 from exp in floating point numbers. */
848 const char EXP_CHARS[] = "eE";
850 /* Chars that mean this number is a floating point constant. */
854 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
856 /* Prefix characters that indicate the start of an immediate
858 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
860 /* Separator character handling. */
862 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
865 skip_past_char (char ** str, char c)
876 #define skip_past_comma(str) skip_past_char (str, ',')
878 /* Arithmetic expressions (possibly involving symbols). */
880 /* Return TRUE if anything in the expression is a bignum. */
883 walk_no_bignums (symbolS * sp)
885 if (symbol_get_value_expression (sp)->X_op == O_big)
888 if (symbol_get_value_expression (sp)->X_add_symbol)
890 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
891 || (symbol_get_value_expression (sp)->X_op_symbol
892 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
898 static int in_my_get_expression = 0;
900 /* Third argument to my_get_expression. */
901 #define GE_NO_PREFIX 0
902 #define GE_IMM_PREFIX 1
903 #define GE_OPT_PREFIX 2
904 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
905 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
906 #define GE_OPT_PREFIX_BIG 3
909 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
914 /* In unified syntax, all prefixes are optional. */
916 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
921 case GE_NO_PREFIX: break;
923 if (!is_immediate_prefix (**str))
925 inst.error = _("immediate expression requires a # prefix");
931 case GE_OPT_PREFIX_BIG:
932 if (is_immediate_prefix (**str))
938 memset (ep, 0, sizeof (expressionS));
940 save_in = input_line_pointer;
941 input_line_pointer = *str;
942 in_my_get_expression = 1;
943 seg = expression (ep);
944 in_my_get_expression = 0;
946 if (ep->X_op == O_illegal || ep->X_op == O_absent)
948 /* We found a bad or missing expression in md_operand(). */
949 *str = input_line_pointer;
950 input_line_pointer = save_in;
951 if (inst.error == NULL)
952 inst.error = (ep->X_op == O_absent
953 ? _("missing expression") :_("bad expression"));
958 if (seg != absolute_section
959 && seg != text_section
960 && seg != data_section
961 && seg != bss_section
962 && seg != undefined_section)
964 inst.error = _("bad segment");
965 *str = input_line_pointer;
966 input_line_pointer = save_in;
973 /* Get rid of any bignums now, so that we don't generate an error for which
974 we can't establish a line number later on. Big numbers are never valid
975 in instructions, which is where this routine is always called. */
976 if (prefix_mode != GE_OPT_PREFIX_BIG
977 && (ep->X_op == O_big
979 && (walk_no_bignums (ep->X_add_symbol)
981 && walk_no_bignums (ep->X_op_symbol))))))
983 inst.error = _("invalid constant");
984 *str = input_line_pointer;
985 input_line_pointer = save_in;
989 *str = input_line_pointer;
990 input_line_pointer = save_in;
994 /* Turn a string in input_line_pointer into a floating point constant
995 of type TYPE, and store the appropriate bytes in *LITP. The number
996 of LITTLENUMS emitted is stored in *SIZEP. An error message is
997 returned, or NULL on OK.
999 Note that fp constants aren't represent in the normal way on the ARM.
1000 In big endian mode, things are as expected. However, in little endian
1001 mode fp constants are big-endian word-wise, and little-endian byte-wise
1002 within the words. For example, (double) 1.1 in big endian mode is
1003 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1004 the byte sequence 99 99 f1 3f 9a 99 99 99.
1006 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1009 md_atof (int type, char * litP, int * sizeP)
1012 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1044 return _("Unrecognized or unsupported floating point constant");
1047 t = atof_ieee (input_line_pointer, type, words);
1049 input_line_pointer = t;
1050 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1052 if (target_big_endian)
1054 for (i = 0; i < prec; i++)
1056 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1057 litP += sizeof (LITTLENUM_TYPE);
1062 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1063 for (i = prec - 1; i >= 0; i--)
1065 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1066 litP += sizeof (LITTLENUM_TYPE);
1069 /* For a 4 byte float the order of elements in `words' is 1 0.
1070 For an 8 byte float the order is 1 0 3 2. */
1071 for (i = 0; i < prec; i += 2)
1073 md_number_to_chars (litP, (valueT) words[i + 1],
1074 sizeof (LITTLENUM_TYPE));
1075 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1076 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1077 litP += 2 * sizeof (LITTLENUM_TYPE);
1084 /* We handle all bad expressions here, so that we can report the faulty
1085 instruction in the error message. */
1087 md_operand (expressionS * exp)
1089 if (in_my_get_expression)
1090 exp->X_op = O_illegal;
1093 /* Immediate values. */
1095 /* Generic immediate-value read function for use in directives.
1096 Accepts anything that 'expression' can fold to a constant.
1097 *val receives the number. */
1100 immediate_for_directive (int *val)
1103 exp.X_op = O_illegal;
1105 if (is_immediate_prefix (*input_line_pointer))
1107 input_line_pointer++;
1111 if (exp.X_op != O_constant)
1113 as_bad (_("expected #constant"));
1114 ignore_rest_of_line ();
1117 *val = exp.X_add_number;
1122 /* Register parsing. */
1124 /* Generic register parser. CCP points to what should be the
1125 beginning of a register name. If it is indeed a valid register
1126 name, advance CCP over it and return the reg_entry structure;
1127 otherwise return NULL. Does not issue diagnostics. */
1129 static struct reg_entry *
1130 arm_reg_parse_multi (char **ccp)
1134 struct reg_entry *reg;
1136 #ifdef REGISTER_PREFIX
1137 if (*start != REGISTER_PREFIX)
1141 #ifdef OPTIONAL_REGISTER_PREFIX
1142 if (*start == OPTIONAL_REGISTER_PREFIX)
1147 if (!ISALPHA (*p) || !is_name_beginner (*p))
1152 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1154 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1164 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1165 enum arm_reg_type type)
1167 /* Alternative syntaxes are accepted for a few register classes. */
1174 /* Generic coprocessor register names are allowed for these. */
1175 if (reg && reg->type == REG_TYPE_CN)
1180 /* For backward compatibility, a bare number is valid here. */
1182 unsigned long processor = strtoul (start, ccp, 10);
1183 if (*ccp != start && processor <= 15)
1187 case REG_TYPE_MMXWC:
1188 /* WC includes WCG. ??? I'm not sure this is true for all
1189 instructions that take WC registers. */
1190 if (reg && reg->type == REG_TYPE_MMXWCG)
1201 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1202 return value is the register number or FAIL. */
1205 arm_reg_parse (char **ccp, enum arm_reg_type type)
1208 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1211 /* Do not allow a scalar (reg+index) to parse as a register. */
1212 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1215 if (reg && reg->type == type)
1218 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1225 /* Parse a Neon type specifier. *STR should point at the leading '.'
1226 character. Does no verification at this stage that the type fits the opcode
1233 Can all be legally parsed by this function.
1235 Fills in neon_type struct pointer with parsed information, and updates STR
1236 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1237 type, FAIL if not. */
1240 parse_neon_type (struct neon_type *type, char **str)
1247 while (type->elems < NEON_MAX_TYPE_ELS)
1249 enum neon_el_type thistype = NT_untyped;
1250 unsigned thissize = -1u;
1257 /* Just a size without an explicit type. */
1261 switch (TOLOWER (*ptr))
1263 case 'i': thistype = NT_integer; break;
1264 case 'f': thistype = NT_float; break;
1265 case 'p': thistype = NT_poly; break;
1266 case 's': thistype = NT_signed; break;
1267 case 'u': thistype = NT_unsigned; break;
1269 thistype = NT_float;
1274 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1280 /* .f is an abbreviation for .f32. */
1281 if (thistype == NT_float && !ISDIGIT (*ptr))
1286 thissize = strtoul (ptr, &ptr, 10);
1288 if (thissize != 8 && thissize != 16 && thissize != 32
1291 as_bad (_("bad size %d in type specifier"), thissize);
1299 type->el[type->elems].type = thistype;
1300 type->el[type->elems].size = thissize;
1305 /* Empty/missing type is not a successful parse. */
1306 if (type->elems == 0)
1314 /* Errors may be set multiple times during parsing or bit encoding
1315 (particularly in the Neon bits), but usually the earliest error which is set
1316 will be the most meaningful. Avoid overwriting it with later (cascading)
1317 errors by calling this function. */
1320 first_error (const char *err)
1326 /* Parse a single type, e.g. ".s32", leading period included. */
1328 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1331 struct neon_type optype;
1335 if (parse_neon_type (&optype, &str) == SUCCESS)
1337 if (optype.elems == 1)
1338 *vectype = optype.el[0];
1341 first_error (_("only one type should be specified for operand"));
1347 first_error (_("vector type expected"));
1359 /* Special meanings for indices (which have a range of 0-7), which will fit into
1362 #define NEON_ALL_LANES 15
1363 #define NEON_INTERLEAVE_LANES 14
1365 /* Parse either a register or a scalar, with an optional type. Return the
1366 register number, and optionally fill in the actual type of the register
1367 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1368 type/index information in *TYPEINFO. */
1371 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1372 enum arm_reg_type *rtype,
1373 struct neon_typed_alias *typeinfo)
1376 struct reg_entry *reg = arm_reg_parse_multi (&str);
1377 struct neon_typed_alias atype;
1378 struct neon_type_el parsetype;
1382 atype.eltype.type = NT_invtype;
1383 atype.eltype.size = -1;
1385 /* Try alternate syntax for some types of register. Note these are mutually
1386 exclusive with the Neon syntax extensions. */
1389 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1397 /* Undo polymorphism when a set of register types may be accepted. */
1398 if ((type == REG_TYPE_NDQ
1399 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1400 || (type == REG_TYPE_VFSD
1401 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1402 || (type == REG_TYPE_NSDQ
1403 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1404 || reg->type == REG_TYPE_NQ))
1405 || (type == REG_TYPE_MMXWC
1406 && (reg->type == REG_TYPE_MMXWCG)))
1407 type = (enum arm_reg_type) reg->type;
1409 if (type != reg->type)
1415 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1417 if ((atype.defined & NTA_HASTYPE) != 0)
1419 first_error (_("can't redefine type for operand"));
1422 atype.defined |= NTA_HASTYPE;
1423 atype.eltype = parsetype;
1426 if (skip_past_char (&str, '[') == SUCCESS)
1428 if (type != REG_TYPE_VFD)
1430 first_error (_("only D registers may be indexed"));
1434 if ((atype.defined & NTA_HASINDEX) != 0)
1436 first_error (_("can't change index for operand"));
1440 atype.defined |= NTA_HASINDEX;
1442 if (skip_past_char (&str, ']') == SUCCESS)
1443 atype.index = NEON_ALL_LANES;
1448 my_get_expression (&exp, &str, GE_NO_PREFIX);
1450 if (exp.X_op != O_constant)
1452 first_error (_("constant expression required"));
1456 if (skip_past_char (&str, ']') == FAIL)
1459 atype.index = exp.X_add_number;
1474 /* Like arm_reg_parse, but allow allow the following extra features:
1475 - If RTYPE is non-zero, return the (possibly restricted) type of the
1476 register (e.g. Neon double or quad reg when either has been requested).
1477 - If this is a Neon vector type with additional type information, fill
1478 in the struct pointed to by VECTYPE (if non-NULL).
1479 This function will fault on encountering a scalar. */
1482 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1483 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1485 struct neon_typed_alias atype;
1487 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1492 /* Do not allow regname(... to parse as a register. */
1496 /* Do not allow a scalar (reg+index) to parse as a register. */
1497 if ((atype.defined & NTA_HASINDEX) != 0)
1499 first_error (_("register operand expected, but got scalar"));
1504 *vectype = atype.eltype;
1511 #define NEON_SCALAR_REG(X) ((X) >> 4)
1512 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1514 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1515 have enough information to be able to do a good job bounds-checking. So, we
1516 just do easy checks here, and do further checks later. */
1519 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1523 struct neon_typed_alias atype;
1525 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1527 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1530 if (atype.index == NEON_ALL_LANES)
1532 first_error (_("scalar must have an index"));
1535 else if (atype.index >= 64 / elsize)
1537 first_error (_("scalar index out of range"));
1542 *type = atype.eltype;
1546 return reg * 16 + atype.index;
1549 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1552 parse_reg_list (char ** strp)
1554 char * str = * strp;
1558 /* We come back here if we get ranges concatenated by '+' or '|'. */
1573 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1575 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1585 first_error (_("bad range in register list"));
1589 for (i = cur_reg + 1; i < reg; i++)
1591 if (range & (1 << i))
1593 (_("Warning: duplicated register (r%d) in register list"),
1601 if (range & (1 << reg))
1602 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1604 else if (reg <= cur_reg)
1605 as_tsktsk (_("Warning: register range not in ascending order"));
1610 while (skip_past_comma (&str) != FAIL
1611 || (in_range = 1, *str++ == '-'));
1616 first_error (_("missing `}'"));
1624 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1627 if (exp.X_op == O_constant)
1629 if (exp.X_add_number
1630 != (exp.X_add_number & 0x0000ffff))
1632 inst.error = _("invalid register mask");
1636 if ((range & exp.X_add_number) != 0)
1638 int regno = range & exp.X_add_number;
1641 regno = (1 << regno) - 1;
1643 (_("Warning: duplicated register (r%d) in register list"),
1647 range |= exp.X_add_number;
1651 if (inst.reloc.type != 0)
1653 inst.error = _("expression too complex");
1657 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1658 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1659 inst.reloc.pc_rel = 0;
1663 if (*str == '|' || *str == '+')
1669 while (another_range);
1675 /* Types of registers in a list. */
1684 /* Parse a VFP register list. If the string is invalid return FAIL.
1685 Otherwise return the number of registers, and set PBASE to the first
1686 register. Parses registers of type ETYPE.
1687 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1688 - Q registers can be used to specify pairs of D registers
1689 - { } can be omitted from around a singleton register list
1690 FIXME: This is not implemented, as it would require backtracking in
1693 This could be done (the meaning isn't really ambiguous), but doesn't
1694 fit in well with the current parsing framework.
1695 - 32 D registers may be used (also true for VFPv3).
1696 FIXME: Types are ignored in these register lists, which is probably a
1700 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1705 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1709 unsigned long mask = 0;
1714 inst.error = _("expecting {");
1723 regtype = REG_TYPE_VFS;
1728 regtype = REG_TYPE_VFD;
1731 case REGLIST_NEON_D:
1732 regtype = REG_TYPE_NDQ;
1736 if (etype != REGLIST_VFP_S)
1738 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1739 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1743 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1746 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1753 base_reg = max_regs;
1757 int setmask = 1, addregs = 1;
1759 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1761 if (new_base == FAIL)
1763 first_error (_(reg_expected_msgs[regtype]));
1767 if (new_base >= max_regs)
1769 first_error (_("register out of range in list"));
1773 /* Note: a value of 2 * n is returned for the register Q<n>. */
1774 if (regtype == REG_TYPE_NQ)
1780 if (new_base < base_reg)
1781 base_reg = new_base;
1783 if (mask & (setmask << new_base))
1785 first_error (_("invalid register list"));
1789 if ((mask >> new_base) != 0 && ! warned)
1791 as_tsktsk (_("register list not in ascending order"));
1795 mask |= setmask << new_base;
1798 if (*str == '-') /* We have the start of a range expression */
1804 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1807 inst.error = gettext (reg_expected_msgs[regtype]);
1811 if (high_range >= max_regs)
1813 first_error (_("register out of range in list"));
1817 if (regtype == REG_TYPE_NQ)
1818 high_range = high_range + 1;
1820 if (high_range <= new_base)
1822 inst.error = _("register range not in ascending order");
1826 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1828 if (mask & (setmask << new_base))
1830 inst.error = _("invalid register list");
1834 mask |= setmask << new_base;
1839 while (skip_past_comma (&str) != FAIL);
1843 /* Sanity check -- should have raised a parse error above. */
1844 if (count == 0 || count > max_regs)
1849 /* Final test -- the registers must be consecutive. */
1851 for (i = 0; i < count; i++)
1853 if ((mask & (1u << i)) == 0)
1855 inst.error = _("non-contiguous register range");
1865 /* True if two alias types are the same. */
1868 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1876 if (a->defined != b->defined)
1879 if ((a->defined & NTA_HASTYPE) != 0
1880 && (a->eltype.type != b->eltype.type
1881 || a->eltype.size != b->eltype.size))
1884 if ((a->defined & NTA_HASINDEX) != 0
1885 && (a->index != b->index))
1891 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1892 The base register is put in *PBASE.
1893 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1895 The register stride (minus one) is put in bit 4 of the return value.
1896 Bits [6:5] encode the list length (minus one).
1897 The type of the list elements is put in *ELTYPE, if non-NULL. */
1899 #define NEON_LANE(X) ((X) & 0xf)
1900 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1901 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1904 parse_neon_el_struct_list (char **str, unsigned *pbase,
1905 struct neon_type_el *eltype)
1912 int leading_brace = 0;
1913 enum arm_reg_type rtype = REG_TYPE_NDQ;
1914 const char *const incr_error = _("register stride must be 1 or 2");
1915 const char *const type_error = _("mismatched element/structure types in list");
1916 struct neon_typed_alias firsttype;
1918 if (skip_past_char (&ptr, '{') == SUCCESS)
1923 struct neon_typed_alias atype;
1924 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1928 first_error (_(reg_expected_msgs[rtype]));
1935 if (rtype == REG_TYPE_NQ)
1941 else if (reg_incr == -1)
1943 reg_incr = getreg - base_reg;
1944 if (reg_incr < 1 || reg_incr > 2)
1946 first_error (_(incr_error));
1950 else if (getreg != base_reg + reg_incr * count)
1952 first_error (_(incr_error));
1956 if (! neon_alias_types_same (&atype, &firsttype))
1958 first_error (_(type_error));
1962 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1966 struct neon_typed_alias htype;
1967 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1969 lane = NEON_INTERLEAVE_LANES;
1970 else if (lane != NEON_INTERLEAVE_LANES)
1972 first_error (_(type_error));
1977 else if (reg_incr != 1)
1979 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1983 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
1986 first_error (_(reg_expected_msgs[rtype]));
1989 if (! neon_alias_types_same (&htype, &firsttype))
1991 first_error (_(type_error));
1994 count += hireg + dregs - getreg;
1998 /* If we're using Q registers, we can't use [] or [n] syntax. */
1999 if (rtype == REG_TYPE_NQ)
2005 if ((atype.defined & NTA_HASINDEX) != 0)
2009 else if (lane != atype.index)
2011 first_error (_(type_error));
2015 else if (lane == -1)
2016 lane = NEON_INTERLEAVE_LANES;
2017 else if (lane != NEON_INTERLEAVE_LANES)
2019 first_error (_(type_error));
2024 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2026 /* No lane set by [x]. We must be interleaving structures. */
2028 lane = NEON_INTERLEAVE_LANES;
2031 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2032 || (count > 1 && reg_incr == -1))
2034 first_error (_("error parsing element/structure list"));
2038 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2040 first_error (_("expected }"));
2048 *eltype = firsttype.eltype;
2053 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2056 /* Parse an explicit relocation suffix on an expression. This is
2057 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2058 arm_reloc_hsh contains no entries, so this function can only
2059 succeed if there is no () after the word. Returns -1 on error,
2060 BFD_RELOC_UNUSED if there wasn't any suffix. */
2063 parse_reloc (char **str)
2065 struct reloc_entry *r;
2069 return BFD_RELOC_UNUSED;
2074 while (*q && *q != ')' && *q != ',')
2079 if ((r = (struct reloc_entry *)
2080 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2087 /* Directives: register aliases. */
2089 static struct reg_entry *
2090 insert_reg_alias (char *str, unsigned number, int type)
2092 struct reg_entry *new_reg;
2095 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2097 if (new_reg->builtin)
2098 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2100 /* Only warn about a redefinition if it's not defined as the
2102 else if (new_reg->number != number || new_reg->type != type)
2103 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2108 name = xstrdup (str);
2109 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2111 new_reg->name = name;
2112 new_reg->number = number;
2113 new_reg->type = type;
2114 new_reg->builtin = FALSE;
2115 new_reg->neon = NULL;
2117 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2124 insert_neon_reg_alias (char *str, int number, int type,
2125 struct neon_typed_alias *atype)
2127 struct reg_entry *reg = insert_reg_alias (str, number, type);
2131 first_error (_("attempt to redefine typed alias"));
2137 reg->neon = (struct neon_typed_alias *)
2138 xmalloc (sizeof (struct neon_typed_alias));
2139 *reg->neon = *atype;
2143 /* Look for the .req directive. This is of the form:
2145 new_register_name .req existing_register_name
2147 If we find one, or if it looks sufficiently like one that we want to
2148 handle any error here, return TRUE. Otherwise return FALSE. */
2151 create_register_alias (char * newname, char *p)
2153 struct reg_entry *old;
2154 char *oldname, *nbuf;
2157 /* The input scrubber ensures that whitespace after the mnemonic is
2158 collapsed to single spaces. */
2160 if (strncmp (oldname, " .req ", 6) != 0)
2164 if (*oldname == '\0')
2167 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2170 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2174 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2175 the desired alias name, and p points to its end. If not, then
2176 the desired alias name is in the global original_case_string. */
2177 #ifdef TC_CASE_SENSITIVE
2180 newname = original_case_string;
2181 nlen = strlen (newname);
2184 nbuf = (char *) alloca (nlen + 1);
2185 memcpy (nbuf, newname, nlen);
2188 /* Create aliases under the new name as stated; an all-lowercase
2189 version of the new name; and an all-uppercase version of the new
2191 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2193 for (p = nbuf; *p; p++)
2196 if (strncmp (nbuf, newname, nlen))
2198 /* If this attempt to create an additional alias fails, do not bother
2199 trying to create the all-lower case alias. We will fail and issue
2200 a second, duplicate error message. This situation arises when the
2201 programmer does something like:
2204 The second .req creates the "Foo" alias but then fails to create
2205 the artificial FOO alias because it has already been created by the
2207 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2211 for (p = nbuf; *p; p++)
2214 if (strncmp (nbuf, newname, nlen))
2215 insert_reg_alias (nbuf, old->number, old->type);
2221 /* Create a Neon typed/indexed register alias using directives, e.g.:
2226 These typed registers can be used instead of the types specified after the
2227 Neon mnemonic, so long as all operands given have types. Types can also be
2228 specified directly, e.g.:
2229 vadd d0.s32, d1.s32, d2.s32 */
2232 create_neon_reg_alias (char *newname, char *p)
2234 enum arm_reg_type basetype;
2235 struct reg_entry *basereg;
2236 struct reg_entry mybasereg;
2237 struct neon_type ntype;
2238 struct neon_typed_alias typeinfo;
2239 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2242 typeinfo.defined = 0;
2243 typeinfo.eltype.type = NT_invtype;
2244 typeinfo.eltype.size = -1;
2245 typeinfo.index = -1;
2249 if (strncmp (p, " .dn ", 5) == 0)
2250 basetype = REG_TYPE_VFD;
2251 else if (strncmp (p, " .qn ", 5) == 0)
2252 basetype = REG_TYPE_NQ;
2261 basereg = arm_reg_parse_multi (&p);
2263 if (basereg && basereg->type != basetype)
2265 as_bad (_("bad type for register"));
2269 if (basereg == NULL)
2272 /* Try parsing as an integer. */
2273 my_get_expression (&exp, &p, GE_NO_PREFIX);
2274 if (exp.X_op != O_constant)
2276 as_bad (_("expression must be constant"));
2279 basereg = &mybasereg;
2280 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2286 typeinfo = *basereg->neon;
2288 if (parse_neon_type (&ntype, &p) == SUCCESS)
2290 /* We got a type. */
2291 if (typeinfo.defined & NTA_HASTYPE)
2293 as_bad (_("can't redefine the type of a register alias"));
2297 typeinfo.defined |= NTA_HASTYPE;
2298 if (ntype.elems != 1)
2300 as_bad (_("you must specify a single type only"));
2303 typeinfo.eltype = ntype.el[0];
2306 if (skip_past_char (&p, '[') == SUCCESS)
2309 /* We got a scalar index. */
2311 if (typeinfo.defined & NTA_HASINDEX)
2313 as_bad (_("can't redefine the index of a scalar alias"));
2317 my_get_expression (&exp, &p, GE_NO_PREFIX);
2319 if (exp.X_op != O_constant)
2321 as_bad (_("scalar index must be constant"));
2325 typeinfo.defined |= NTA_HASINDEX;
2326 typeinfo.index = exp.X_add_number;
2328 if (skip_past_char (&p, ']') == FAIL)
2330 as_bad (_("expecting ]"));
2335 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2336 the desired alias name, and p points to its end. If not, then
2337 the desired alias name is in the global original_case_string. */
2338 #ifdef TC_CASE_SENSITIVE
2339 namelen = nameend - newname;
2341 newname = original_case_string;
2342 namelen = strlen (newname);
2345 namebuf = (char *) alloca (namelen + 1);
2346 strncpy (namebuf, newname, namelen);
2347 namebuf[namelen] = '\0';
2349 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2350 typeinfo.defined != 0 ? &typeinfo : NULL);
2352 /* Insert name in all uppercase. */
2353 for (p = namebuf; *p; p++)
2356 if (strncmp (namebuf, newname, namelen))
2357 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2358 typeinfo.defined != 0 ? &typeinfo : NULL);
2360 /* Insert name in all lowercase. */
2361 for (p = namebuf; *p; p++)
2364 if (strncmp (namebuf, newname, namelen))
2365 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2366 typeinfo.defined != 0 ? &typeinfo : NULL);
2371 /* Should never be called, as .req goes between the alias and the
2372 register name, not at the beginning of the line. */
2375 s_req (int a ATTRIBUTE_UNUSED)
2377 as_bad (_("invalid syntax for .req directive"));
2381 s_dn (int a ATTRIBUTE_UNUSED)
2383 as_bad (_("invalid syntax for .dn directive"));
2387 s_qn (int a ATTRIBUTE_UNUSED)
2389 as_bad (_("invalid syntax for .qn directive"));
2392 /* The .unreq directive deletes an alias which was previously defined
2393 by .req. For example:
2399 s_unreq (int a ATTRIBUTE_UNUSED)
2404 name = input_line_pointer;
2406 while (*input_line_pointer != 0
2407 && *input_line_pointer != ' '
2408 && *input_line_pointer != '\n')
2409 ++input_line_pointer;
2411 saved_char = *input_line_pointer;
2412 *input_line_pointer = 0;
2415 as_bad (_("invalid syntax for .unreq directive"));
2418 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2422 as_bad (_("unknown register alias '%s'"), name);
2423 else if (reg->builtin)
2424 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2431 hash_delete (arm_reg_hsh, name, FALSE);
2432 free ((char *) reg->name);
2437 /* Also locate the all upper case and all lower case versions.
2438 Do not complain if we cannot find one or the other as it
2439 was probably deleted above. */
2441 nbuf = strdup (name);
2442 for (p = nbuf; *p; p++)
2444 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2447 hash_delete (arm_reg_hsh, nbuf, FALSE);
2448 free ((char *) reg->name);
2454 for (p = nbuf; *p; p++)
2456 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2459 hash_delete (arm_reg_hsh, nbuf, FALSE);
2460 free ((char *) reg->name);
2470 *input_line_pointer = saved_char;
2471 demand_empty_rest_of_line ();
2474 /* Directives: Instruction set selection. */
2477 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2478 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2479 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2480 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2482 /* Create a new mapping symbol for the transition to STATE. */
2485 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2488 const char * symname;
2495 type = BSF_NO_FLAGS;
2499 type = BSF_NO_FLAGS;
2503 type = BSF_NO_FLAGS;
2509 symbolP = symbol_new (symname, now_seg, value, frag);
2510 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2515 THUMB_SET_FUNC (symbolP, 0);
2516 ARM_SET_THUMB (symbolP, 0);
2517 ARM_SET_INTERWORK (symbolP, support_interwork);
2521 THUMB_SET_FUNC (symbolP, 1);
2522 ARM_SET_THUMB (symbolP, 1);
2523 ARM_SET_INTERWORK (symbolP, support_interwork);
2531 /* Save the mapping symbols for future reference. Also check that
2532 we do not place two mapping symbols at the same offset within a
2533 frag. We'll handle overlap between frags in
2534 check_mapping_symbols.
2536 If .fill or other data filling directive generates zero sized data,
2537 the mapping symbol for the following code will have the same value
2538 as the one generated for the data filling directive. In this case,
2539 we replace the old symbol with the new one at the same address. */
2542 if (frag->tc_frag_data.first_map != NULL)
2544 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2545 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2547 frag->tc_frag_data.first_map = symbolP;
2549 if (frag->tc_frag_data.last_map != NULL)
2551 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2552 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2553 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2555 frag->tc_frag_data.last_map = symbolP;
2558 /* We must sometimes convert a region marked as code to data during
2559 code alignment, if an odd number of bytes have to be padded. The
2560 code mapping symbol is pushed to an aligned address. */
2563 insert_data_mapping_symbol (enum mstate state,
2564 valueT value, fragS *frag, offsetT bytes)
2566 /* If there was already a mapping symbol, remove it. */
2567 if (frag->tc_frag_data.last_map != NULL
2568 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2570 symbolS *symp = frag->tc_frag_data.last_map;
2574 know (frag->tc_frag_data.first_map == symp);
2575 frag->tc_frag_data.first_map = NULL;
2577 frag->tc_frag_data.last_map = NULL;
2578 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2581 make_mapping_symbol (MAP_DATA, value, frag);
2582 make_mapping_symbol (state, value + bytes, frag);
2585 static void mapping_state_2 (enum mstate state, int max_chars);
2587 /* Set the mapping state to STATE. Only call this when about to
2588 emit some STATE bytes to the file. */
2591 mapping_state (enum mstate state)
2593 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2595 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2597 if (mapstate == state)
2598 /* The mapping symbol has already been emitted.
2599 There is nothing else to do. */
2602 if (state == MAP_ARM || state == MAP_THUMB)
2604 All ARM instructions require 4-byte alignment.
2605 (Almost) all Thumb instructions require 2-byte alignment.
2607 When emitting instructions into any section, mark the section
2610 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2611 but themselves require 2-byte alignment; this applies to some
2612 PC- relative forms. However, these cases will invovle implicit
2613 literal pool generation or an explicit .align >=2, both of
2614 which will cause the section to me marked with sufficient
2615 alignment. Thus, we don't handle those cases here. */
2616 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2618 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2619 /* This case will be evaluated later in the next else. */
2621 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2622 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2624 /* Only add the symbol if the offset is > 0:
2625 if we're at the first frag, check it's size > 0;
2626 if we're not at the first frag, then for sure
2627 the offset is > 0. */
2628 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2629 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2632 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2635 mapping_state_2 (state, 0);
2639 /* Same as mapping_state, but MAX_CHARS bytes have already been
2640 allocated. Put the mapping symbol that far back. */
2643 mapping_state_2 (enum mstate state, int max_chars)
2645 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2647 if (!SEG_NORMAL (now_seg))
2650 if (mapstate == state)
2651 /* The mapping symbol has already been emitted.
2652 There is nothing else to do. */
2655 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2656 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2659 #define mapping_state(x) ((void)0)
2660 #define mapping_state_2(x, y) ((void)0)
2663 /* Find the real, Thumb encoded start of a Thumb function. */
2667 find_real_start (symbolS * symbolP)
2670 const char * name = S_GET_NAME (symbolP);
2671 symbolS * new_target;
2673 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2674 #define STUB_NAME ".real_start_of"
2679 /* The compiler may generate BL instructions to local labels because
2680 it needs to perform a branch to a far away location. These labels
2681 do not have a corresponding ".real_start_of" label. We check
2682 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2683 the ".real_start_of" convention for nonlocal branches. */
2684 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2687 real_start = ACONCAT ((STUB_NAME, name, NULL));
2688 new_target = symbol_find (real_start);
2690 if (new_target == NULL)
2692 as_warn (_("Failed to find real start of function: %s\n"), name);
2693 new_target = symbolP;
2701 opcode_select (int width)
2708 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2709 as_bad (_("selected processor does not support THUMB opcodes"));
2712 /* No need to force the alignment, since we will have been
2713 coming from ARM mode, which is word-aligned. */
2714 record_alignment (now_seg, 1);
2721 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2722 as_bad (_("selected processor does not support ARM opcodes"));
2727 frag_align (2, 0, 0);
2729 record_alignment (now_seg, 1);
2734 as_bad (_("invalid instruction size selected (%d)"), width);
2739 s_arm (int ignore ATTRIBUTE_UNUSED)
2742 demand_empty_rest_of_line ();
2746 s_thumb (int ignore ATTRIBUTE_UNUSED)
2749 demand_empty_rest_of_line ();
2753 s_code (int unused ATTRIBUTE_UNUSED)
2757 temp = get_absolute_expression ();
2762 opcode_select (temp);
2766 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2771 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2773 /* If we are not already in thumb mode go into it, EVEN if
2774 the target processor does not support thumb instructions.
2775 This is used by gcc/config/arm/lib1funcs.asm for example
2776 to compile interworking support functions even if the
2777 target processor should not support interworking. */
2781 record_alignment (now_seg, 1);
2784 demand_empty_rest_of_line ();
2788 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2792 /* The following label is the name/address of the start of a Thumb function.
2793 We need to know this for the interworking support. */
2794 label_is_thumb_function_name = TRUE;
2797 /* Perform a .set directive, but also mark the alias as
2798 being a thumb function. */
2801 s_thumb_set (int equiv)
2803 /* XXX the following is a duplicate of the code for s_set() in read.c
2804 We cannot just call that code as we need to get at the symbol that
2811 /* Especial apologies for the random logic:
2812 This just grew, and could be parsed much more simply!
2814 name = input_line_pointer;
2815 delim = get_symbol_end ();
2816 end_name = input_line_pointer;
2819 if (*input_line_pointer != ',')
2822 as_bad (_("expected comma after name \"%s\""), name);
2824 ignore_rest_of_line ();
2828 input_line_pointer++;
2831 if (name[0] == '.' && name[1] == '\0')
2833 /* XXX - this should not happen to .thumb_set. */
2837 if ((symbolP = symbol_find (name)) == NULL
2838 && (symbolP = md_undefined_symbol (name)) == NULL)
2841 /* When doing symbol listings, play games with dummy fragments living
2842 outside the normal fragment chain to record the file and line info
2844 if (listing & LISTING_SYMBOLS)
2846 extern struct list_info_struct * listing_tail;
2847 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2849 memset (dummy_frag, 0, sizeof (fragS));
2850 dummy_frag->fr_type = rs_fill;
2851 dummy_frag->line = listing_tail;
2852 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2853 dummy_frag->fr_symbol = symbolP;
2857 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2860 /* "set" symbols are local unless otherwise specified. */
2861 SF_SET_LOCAL (symbolP);
2862 #endif /* OBJ_COFF */
2863 } /* Make a new symbol. */
2865 symbol_table_insert (symbolP);
2870 && S_IS_DEFINED (symbolP)
2871 && S_GET_SEGMENT (symbolP) != reg_section)
2872 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2874 pseudo_set (symbolP);
2876 demand_empty_rest_of_line ();
2878 /* XXX Now we come to the Thumb specific bit of code. */
2880 THUMB_SET_FUNC (symbolP, 1);
2881 ARM_SET_THUMB (symbolP, 1);
2882 #if defined OBJ_ELF || defined OBJ_COFF
2883 ARM_SET_INTERWORK (symbolP, support_interwork);
2887 /* Directives: Mode selection. */
2889 /* .syntax [unified|divided] - choose the new unified syntax
2890 (same for Arm and Thumb encoding, modulo slight differences in what
2891 can be represented) or the old divergent syntax for each mode. */
2893 s_syntax (int unused ATTRIBUTE_UNUSED)
2897 name = input_line_pointer;
2898 delim = get_symbol_end ();
2900 if (!strcasecmp (name, "unified"))
2901 unified_syntax = TRUE;
2902 else if (!strcasecmp (name, "divided"))
2903 unified_syntax = FALSE;
2906 as_bad (_("unrecognized syntax mode \"%s\""), name);
2909 *input_line_pointer = delim;
2910 demand_empty_rest_of_line ();
2913 /* Directives: sectioning and alignment. */
2915 /* Same as s_align_ptwo but align 0 => align 2. */
2918 s_align (int unused ATTRIBUTE_UNUSED)
2923 long max_alignment = 15;
2925 temp = get_absolute_expression ();
2926 if (temp > max_alignment)
2927 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2930 as_bad (_("alignment negative. 0 assumed."));
2934 if (*input_line_pointer == ',')
2936 input_line_pointer++;
2937 temp_fill = get_absolute_expression ();
2949 /* Only make a frag if we HAVE to. */
2950 if (temp && !need_pass_2)
2952 if (!fill_p && subseg_text_p (now_seg))
2953 frag_align_code (temp, 0);
2955 frag_align (temp, (int) temp_fill, 0);
2957 demand_empty_rest_of_line ();
2959 record_alignment (now_seg, temp);
2963 s_bss (int ignore ATTRIBUTE_UNUSED)
2965 /* We don't support putting frags in the BSS segment, we fake it by
2966 marking in_bss, then looking at s_skip for clues. */
2967 subseg_set (bss_section, 0);
2968 demand_empty_rest_of_line ();
2970 #ifdef md_elf_section_change_hook
2971 md_elf_section_change_hook ();
2976 s_even (int ignore ATTRIBUTE_UNUSED)
2978 /* Never make frag if expect extra pass. */
2980 frag_align (1, 0, 0);
2982 record_alignment (now_seg, 1);
2984 demand_empty_rest_of_line ();
2987 /* Directives: Literal pools. */
2989 static literal_pool *
2990 find_literal_pool (void)
2992 literal_pool * pool;
2994 for (pool = list_of_pools; pool != NULL; pool = pool->next)
2996 if (pool->section == now_seg
2997 && pool->sub_section == now_subseg)
3004 static literal_pool *
3005 find_or_make_literal_pool (void)
3007 /* Next literal pool ID number. */
3008 static unsigned int latest_pool_num = 1;
3009 literal_pool * pool;
3011 pool = find_literal_pool ();
3015 /* Create a new pool. */
3016 pool = (literal_pool *) xmalloc (sizeof (* pool));
3020 pool->next_free_entry = 0;
3021 pool->section = now_seg;
3022 pool->sub_section = now_subseg;
3023 pool->next = list_of_pools;
3024 pool->symbol = NULL;
3026 /* Add it to the list. */
3027 list_of_pools = pool;
3030 /* New pools, and emptied pools, will have a NULL symbol. */
3031 if (pool->symbol == NULL)
3033 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3034 (valueT) 0, &zero_address_frag);
3035 pool->id = latest_pool_num ++;
3042 /* Add the literal in the global 'inst'
3043 structure to the relevant literal pool. */
3046 add_to_lit_pool (void)
3048 literal_pool * pool;
3051 pool = find_or_make_literal_pool ();
3053 /* Check if this literal value is already in the pool. */
3054 for (entry = 0; entry < pool->next_free_entry; entry ++)
3056 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3057 && (inst.reloc.exp.X_op == O_constant)
3058 && (pool->literals[entry].X_add_number
3059 == inst.reloc.exp.X_add_number)
3060 && (pool->literals[entry].X_unsigned
3061 == inst.reloc.exp.X_unsigned))
3064 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3065 && (inst.reloc.exp.X_op == O_symbol)
3066 && (pool->literals[entry].X_add_number
3067 == inst.reloc.exp.X_add_number)
3068 && (pool->literals[entry].X_add_symbol
3069 == inst.reloc.exp.X_add_symbol)
3070 && (pool->literals[entry].X_op_symbol
3071 == inst.reloc.exp.X_op_symbol))
3075 /* Do we need to create a new entry? */
3076 if (entry == pool->next_free_entry)
3078 if (entry >= MAX_LITERAL_POOL_SIZE)
3080 inst.error = _("literal pool overflow");
3084 pool->literals[entry] = inst.reloc.exp;
3086 /* PR ld/12974: Record the location of the first source line to reference
3087 this entry in the literal pool. If it turns out during linking that the
3088 symbol does not exist we will be able to give an accurate line number for
3089 the (first use of the) missing reference. */
3090 if (debug_type == DEBUG_DWARF2)
3091 dwarf2_where (pool->locs + entry);
3093 pool->next_free_entry += 1;
3096 inst.reloc.exp.X_op = O_symbol;
3097 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3098 inst.reloc.exp.X_add_symbol = pool->symbol;
3103 /* Can't use symbol_new here, so have to create a symbol and then at
3104 a later date assign it a value. Thats what these functions do. */
3107 symbol_locate (symbolS * symbolP,
3108 const char * name, /* It is copied, the caller can modify. */
3109 segT segment, /* Segment identifier (SEG_<something>). */
3110 valueT valu, /* Symbol value. */
3111 fragS * frag) /* Associated fragment. */
3113 unsigned int name_length;
3114 char * preserved_copy_of_name;
3116 name_length = strlen (name) + 1; /* +1 for \0. */
3117 obstack_grow (¬es, name, name_length);
3118 preserved_copy_of_name = (char *) obstack_finish (¬es);
3120 #ifdef tc_canonicalize_symbol_name
3121 preserved_copy_of_name =
3122 tc_canonicalize_symbol_name (preserved_copy_of_name);
3125 S_SET_NAME (symbolP, preserved_copy_of_name);
3127 S_SET_SEGMENT (symbolP, segment);
3128 S_SET_VALUE (symbolP, valu);
3129 symbol_clear_list_pointers (symbolP);
3131 symbol_set_frag (symbolP, frag);
3133 /* Link to end of symbol chain. */
3135 extern int symbol_table_frozen;
3137 if (symbol_table_frozen)
3141 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3143 obj_symbol_new_hook (symbolP);
3145 #ifdef tc_symbol_new_hook
3146 tc_symbol_new_hook (symbolP);
3150 verify_symbol_chain (symbol_rootP, symbol_lastP);
3151 #endif /* DEBUG_SYMS */
3156 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3159 literal_pool * pool;
3162 pool = find_literal_pool ();
3164 || pool->symbol == NULL
3165 || pool->next_free_entry == 0)
3168 mapping_state (MAP_DATA);
3170 /* Align pool as you have word accesses.
3171 Only make a frag if we have to. */
3173 frag_align (2, 0, 0);
3175 record_alignment (now_seg, 2);
3177 sprintf (sym_name, "$$lit_\002%x", pool->id);
3179 symbol_locate (pool->symbol, sym_name, now_seg,
3180 (valueT) frag_now_fix (), frag_now);
3181 symbol_table_insert (pool->symbol);
3183 ARM_SET_THUMB (pool->symbol, thumb_mode);
3185 #if defined OBJ_COFF || defined OBJ_ELF
3186 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3189 for (entry = 0; entry < pool->next_free_entry; entry ++)
3192 if (debug_type == DEBUG_DWARF2)
3193 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3195 /* First output the expression in the instruction to the pool. */
3196 emit_expr (&(pool->literals[entry]), 4); /* .word */
3199 /* Mark the pool as empty. */
3200 pool->next_free_entry = 0;
3201 pool->symbol = NULL;
3205 /* Forward declarations for functions below, in the MD interface
3207 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3208 static valueT create_unwind_entry (int);
3209 static void start_unwind_section (const segT, int);
3210 static void add_unwind_opcode (valueT, int);
3211 static void flush_pending_unwind (void);
3213 /* Directives: Data. */
3216 s_arm_elf_cons (int nbytes)
3220 #ifdef md_flush_pending_output
3221 md_flush_pending_output ();
3224 if (is_it_end_of_statement ())
3226 demand_empty_rest_of_line ();
3230 #ifdef md_cons_align
3231 md_cons_align (nbytes);
3234 mapping_state (MAP_DATA);
3238 char *base = input_line_pointer;
3242 if (exp.X_op != O_symbol)
3243 emit_expr (&exp, (unsigned int) nbytes);
3246 char *before_reloc = input_line_pointer;
3247 reloc = parse_reloc (&input_line_pointer);
3250 as_bad (_("unrecognized relocation suffix"));
3251 ignore_rest_of_line ();
3254 else if (reloc == BFD_RELOC_UNUSED)
3255 emit_expr (&exp, (unsigned int) nbytes);
3258 reloc_howto_type *howto = (reloc_howto_type *)
3259 bfd_reloc_type_lookup (stdoutput,
3260 (bfd_reloc_code_real_type) reloc);
3261 int size = bfd_get_reloc_size (howto);
3263 if (reloc == BFD_RELOC_ARM_PLT32)
3265 as_bad (_("(plt) is only valid on branch targets"));
3266 reloc = BFD_RELOC_UNUSED;
3271 as_bad (_("%s relocations do not fit in %d bytes"),
3272 howto->name, nbytes);
3275 /* We've parsed an expression stopping at O_symbol.
3276 But there may be more expression left now that we
3277 have parsed the relocation marker. Parse it again.
3278 XXX Surely there is a cleaner way to do this. */
3279 char *p = input_line_pointer;
3281 char *save_buf = (char *) alloca (input_line_pointer - base);
3282 memcpy (save_buf, base, input_line_pointer - base);
3283 memmove (base + (input_line_pointer - before_reloc),
3284 base, before_reloc - base);
3286 input_line_pointer = base + (input_line_pointer-before_reloc);
3288 memcpy (base, save_buf, p - base);
3290 offset = nbytes - size;
3291 p = frag_more ((int) nbytes);
3292 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3293 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3298 while (*input_line_pointer++ == ',');
3300 /* Put terminator back into stream. */
3301 input_line_pointer --;
3302 demand_empty_rest_of_line ();
3305 /* Emit an expression containing a 32-bit thumb instruction.
3306 Implementation based on put_thumb32_insn. */
3309 emit_thumb32_expr (expressionS * exp)
3311 expressionS exp_high = *exp;
3313 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3314 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3315 exp->X_add_number &= 0xffff;
3316 emit_expr (exp, (unsigned int) THUMB_SIZE);
3319 /* Guess the instruction size based on the opcode. */
3322 thumb_insn_size (int opcode)
3324 if ((unsigned int) opcode < 0xe800u)
3326 else if ((unsigned int) opcode >= 0xe8000000u)
3333 emit_insn (expressionS *exp, int nbytes)
3337 if (exp->X_op == O_constant)
3342 size = thumb_insn_size (exp->X_add_number);
3346 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3348 as_bad (_(".inst.n operand too big. "\
3349 "Use .inst.w instead"));
3354 if (now_it.state == AUTOMATIC_IT_BLOCK)
3355 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3357 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3359 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3360 emit_thumb32_expr (exp);
3362 emit_expr (exp, (unsigned int) size);
3364 it_fsm_post_encode ();
3368 as_bad (_("cannot determine Thumb instruction size. " \
3369 "Use .inst.n/.inst.w instead"));
3372 as_bad (_("constant expression required"));
3377 /* Like s_arm_elf_cons but do not use md_cons_align and
3378 set the mapping state to MAP_ARM/MAP_THUMB. */
3381 s_arm_elf_inst (int nbytes)
3383 if (is_it_end_of_statement ())
3385 demand_empty_rest_of_line ();
3389 /* Calling mapping_state () here will not change ARM/THUMB,
3390 but will ensure not to be in DATA state. */
3393 mapping_state (MAP_THUMB);
3398 as_bad (_("width suffixes are invalid in ARM mode"));
3399 ignore_rest_of_line ();
3405 mapping_state (MAP_ARM);
3414 if (! emit_insn (& exp, nbytes))
3416 ignore_rest_of_line ();
3420 while (*input_line_pointer++ == ',');
3422 /* Put terminator back into stream. */
3423 input_line_pointer --;
3424 demand_empty_rest_of_line ();
3427 /* Parse a .rel31 directive. */
3430 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3437 if (*input_line_pointer == '1')
3438 highbit = 0x80000000;
3439 else if (*input_line_pointer != '0')
3440 as_bad (_("expected 0 or 1"));
3442 input_line_pointer++;
3443 if (*input_line_pointer != ',')
3444 as_bad (_("missing comma"));
3445 input_line_pointer++;
3447 #ifdef md_flush_pending_output
3448 md_flush_pending_output ();
3451 #ifdef md_cons_align
3455 mapping_state (MAP_DATA);
3460 md_number_to_chars (p, highbit, 4);
3461 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3462 BFD_RELOC_ARM_PREL31);
3464 demand_empty_rest_of_line ();
3467 /* Directives: AEABI stack-unwind tables. */
3469 /* Parse an unwind_fnstart directive. Simply records the current location. */
3472 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3474 demand_empty_rest_of_line ();
3475 if (unwind.proc_start)
3477 as_bad (_("duplicate .fnstart directive"));
3481 /* Mark the start of the function. */
3482 unwind.proc_start = expr_build_dot ();
3484 /* Reset the rest of the unwind info. */
3485 unwind.opcode_count = 0;
3486 unwind.table_entry = NULL;
3487 unwind.personality_routine = NULL;
3488 unwind.personality_index = -1;
3489 unwind.frame_size = 0;
3490 unwind.fp_offset = 0;
3491 unwind.fp_reg = REG_SP;
3493 unwind.sp_restored = 0;
3497 /* Parse a handlerdata directive. Creates the exception handling table entry
3498 for the function. */
3501 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3503 demand_empty_rest_of_line ();
3504 if (!unwind.proc_start)
3505 as_bad (MISSING_FNSTART);
3507 if (unwind.table_entry)
3508 as_bad (_("duplicate .handlerdata directive"));
3510 create_unwind_entry (1);
3513 /* Parse an unwind_fnend directive. Generates the index table entry. */
3516 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3521 unsigned int marked_pr_dependency;
3523 demand_empty_rest_of_line ();
3525 if (!unwind.proc_start)
3527 as_bad (_(".fnend directive without .fnstart"));
3531 /* Add eh table entry. */
3532 if (unwind.table_entry == NULL)
3533 val = create_unwind_entry (0);
3537 /* Add index table entry. This is two words. */
3538 start_unwind_section (unwind.saved_seg, 1);
3539 frag_align (2, 0, 0);
3540 record_alignment (now_seg, 2);
3542 ptr = frag_more (8);
3543 where = frag_now_fix () - 8;
3545 /* Self relative offset of the function start. */
3546 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3547 BFD_RELOC_ARM_PREL31);
3549 /* Indicate dependency on EHABI-defined personality routines to the
3550 linker, if it hasn't been done already. */
3551 marked_pr_dependency
3552 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3553 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3554 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3556 static const char *const name[] =
3558 "__aeabi_unwind_cpp_pr0",
3559 "__aeabi_unwind_cpp_pr1",
3560 "__aeabi_unwind_cpp_pr2"
3562 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3563 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3564 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3565 |= 1 << unwind.personality_index;
3569 /* Inline exception table entry. */
3570 md_number_to_chars (ptr + 4, val, 4);
3572 /* Self relative offset of the table entry. */
3573 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3574 BFD_RELOC_ARM_PREL31);
3576 /* Restore the original section. */
3577 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3579 unwind.proc_start = NULL;
3583 /* Parse an unwind_cantunwind directive. */
3586 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3588 demand_empty_rest_of_line ();
3589 if (!unwind.proc_start)
3590 as_bad (MISSING_FNSTART);
3592 if (unwind.personality_routine || unwind.personality_index != -1)
3593 as_bad (_("personality routine specified for cantunwind frame"));
3595 unwind.personality_index = -2;
3599 /* Parse a personalityindex directive. */
3602 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3606 if (!unwind.proc_start)
3607 as_bad (MISSING_FNSTART);
3609 if (unwind.personality_routine || unwind.personality_index != -1)
3610 as_bad (_("duplicate .personalityindex directive"));
3614 if (exp.X_op != O_constant
3615 || exp.X_add_number < 0 || exp.X_add_number > 15)
3617 as_bad (_("bad personality routine number"));
3618 ignore_rest_of_line ();
3622 unwind.personality_index = exp.X_add_number;
3624 demand_empty_rest_of_line ();
3628 /* Parse a personality directive. */
3631 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3635 if (!unwind.proc_start)
3636 as_bad (MISSING_FNSTART);
3638 if (unwind.personality_routine || unwind.personality_index != -1)
3639 as_bad (_("duplicate .personality directive"));
3641 name = input_line_pointer;
3642 c = get_symbol_end ();
3643 p = input_line_pointer;
3644 unwind.personality_routine = symbol_find_or_make (name);
3646 demand_empty_rest_of_line ();
3650 /* Parse a directive saving core registers. */
3653 s_arm_unwind_save_core (void)
3659 range = parse_reg_list (&input_line_pointer);
3662 as_bad (_("expected register list"));
3663 ignore_rest_of_line ();
3667 demand_empty_rest_of_line ();
3669 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3670 into .unwind_save {..., sp...}. We aren't bothered about the value of
3671 ip because it is clobbered by calls. */
3672 if (unwind.sp_restored && unwind.fp_reg == 12
3673 && (range & 0x3000) == 0x1000)
3675 unwind.opcode_count--;
3676 unwind.sp_restored = 0;
3677 range = (range | 0x2000) & ~0x1000;
3678 unwind.pending_offset = 0;
3684 /* See if we can use the short opcodes. These pop a block of up to 8
3685 registers starting with r4, plus maybe r14. */
3686 for (n = 0; n < 8; n++)
3688 /* Break at the first non-saved register. */
3689 if ((range & (1 << (n + 4))) == 0)
3692 /* See if there are any other bits set. */
3693 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3695 /* Use the long form. */
3696 op = 0x8000 | ((range >> 4) & 0xfff);
3697 add_unwind_opcode (op, 2);
3701 /* Use the short form. */
3703 op = 0xa8; /* Pop r14. */
3705 op = 0xa0; /* Do not pop r14. */
3707 add_unwind_opcode (op, 1);
3714 op = 0xb100 | (range & 0xf);
3715 add_unwind_opcode (op, 2);
3718 /* Record the number of bytes pushed. */
3719 for (n = 0; n < 16; n++)
3721 if (range & (1 << n))
3722 unwind.frame_size += 4;
3727 /* Parse a directive saving FPA registers. */
3730 s_arm_unwind_save_fpa (int reg)
3736 /* Get Number of registers to transfer. */
3737 if (skip_past_comma (&input_line_pointer) != FAIL)
3740 exp.X_op = O_illegal;
3742 if (exp.X_op != O_constant)
3744 as_bad (_("expected , <constant>"));
3745 ignore_rest_of_line ();
3749 num_regs = exp.X_add_number;
3751 if (num_regs < 1 || num_regs > 4)
3753 as_bad (_("number of registers must be in the range [1:4]"));
3754 ignore_rest_of_line ();
3758 demand_empty_rest_of_line ();
3763 op = 0xb4 | (num_regs - 1);
3764 add_unwind_opcode (op, 1);
3769 op = 0xc800 | (reg << 4) | (num_regs - 1);
3770 add_unwind_opcode (op, 2);
3772 unwind.frame_size += num_regs * 12;
3776 /* Parse a directive saving VFP registers for ARMv6 and above. */
3779 s_arm_unwind_save_vfp_armv6 (void)
3784 int num_vfpv3_regs = 0;
3785 int num_regs_below_16;
3787 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3790 as_bad (_("expected register list"));
3791 ignore_rest_of_line ();
3795 demand_empty_rest_of_line ();
3797 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3798 than FSTMX/FLDMX-style ones). */
3800 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3802 num_vfpv3_regs = count;
3803 else if (start + count > 16)
3804 num_vfpv3_regs = start + count - 16;
3806 if (num_vfpv3_regs > 0)
3808 int start_offset = start > 16 ? start - 16 : 0;
3809 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3810 add_unwind_opcode (op, 2);
3813 /* Generate opcode for registers numbered in the range 0 .. 15. */
3814 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
3815 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
3816 if (num_regs_below_16 > 0)
3818 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3819 add_unwind_opcode (op, 2);
3822 unwind.frame_size += count * 8;
3826 /* Parse a directive saving VFP registers for pre-ARMv6. */
3829 s_arm_unwind_save_vfp (void)
3835 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
3838 as_bad (_("expected register list"));
3839 ignore_rest_of_line ();
3843 demand_empty_rest_of_line ();
3848 op = 0xb8 | (count - 1);
3849 add_unwind_opcode (op, 1);
3854 op = 0xb300 | (reg << 4) | (count - 1);
3855 add_unwind_opcode (op, 2);
3857 unwind.frame_size += count * 8 + 4;
3861 /* Parse a directive saving iWMMXt data registers. */
3864 s_arm_unwind_save_mmxwr (void)
3872 if (*input_line_pointer == '{')
3873 input_line_pointer++;
3877 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3881 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3886 as_tsktsk (_("register list not in ascending order"));
3889 if (*input_line_pointer == '-')
3891 input_line_pointer++;
3892 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
3895 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
3898 else if (reg >= hi_reg)
3900 as_bad (_("bad register range"));
3903 for (; reg < hi_reg; reg++)
3907 while (skip_past_comma (&input_line_pointer) != FAIL);
3909 if (*input_line_pointer == '}')
3910 input_line_pointer++;
3912 demand_empty_rest_of_line ();
3914 /* Generate any deferred opcodes because we're going to be looking at
3916 flush_pending_unwind ();
3918 for (i = 0; i < 16; i++)
3920 if (mask & (1 << i))
3921 unwind.frame_size += 8;
3924 /* Attempt to combine with a previous opcode. We do this because gcc
3925 likes to output separate unwind directives for a single block of
3927 if (unwind.opcode_count > 0)
3929 i = unwind.opcodes[unwind.opcode_count - 1];
3930 if ((i & 0xf8) == 0xc0)
3933 /* Only merge if the blocks are contiguous. */
3936 if ((mask & 0xfe00) == (1 << 9))
3938 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3939 unwind.opcode_count--;
3942 else if (i == 6 && unwind.opcode_count >= 2)
3944 i = unwind.opcodes[unwind.opcode_count - 2];
3948 op = 0xffff << (reg - 1);
3950 && ((mask & op) == (1u << (reg - 1))))
3952 op = (1 << (reg + i + 1)) - 1;
3953 op &= ~((1 << reg) - 1);
3955 unwind.opcode_count -= 2;
3962 /* We want to generate opcodes in the order the registers have been
3963 saved, ie. descending order. */
3964 for (reg = 15; reg >= -1; reg--)
3966 /* Save registers in blocks. */
3968 || !(mask & (1 << reg)))
3970 /* We found an unsaved reg. Generate opcodes to save the
3977 op = 0xc0 | (hi_reg - 10);
3978 add_unwind_opcode (op, 1);
3983 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
3984 add_unwind_opcode (op, 2);
3993 ignore_rest_of_line ();
3997 s_arm_unwind_save_mmxwcg (void)
4004 if (*input_line_pointer == '{')
4005 input_line_pointer++;
4009 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4013 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4019 as_tsktsk (_("register list not in ascending order"));
4022 if (*input_line_pointer == '-')
4024 input_line_pointer++;
4025 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4028 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4031 else if (reg >= hi_reg)
4033 as_bad (_("bad register range"));
4036 for (; reg < hi_reg; reg++)
4040 while (skip_past_comma (&input_line_pointer) != FAIL);
4042 if (*input_line_pointer == '}')
4043 input_line_pointer++;
4045 demand_empty_rest_of_line ();
4047 /* Generate any deferred opcodes because we're going to be looking at
4049 flush_pending_unwind ();
4051 for (reg = 0; reg < 16; reg++)
4053 if (mask & (1 << reg))
4054 unwind.frame_size += 4;
4057 add_unwind_opcode (op, 2);
4060 ignore_rest_of_line ();
4064 /* Parse an unwind_save directive.
4065 If the argument is non-zero, this is a .vsave directive. */
4068 s_arm_unwind_save (int arch_v6)
4071 struct reg_entry *reg;
4072 bfd_boolean had_brace = FALSE;
4074 if (!unwind.proc_start)
4075 as_bad (MISSING_FNSTART);
4077 /* Figure out what sort of save we have. */
4078 peek = input_line_pointer;
4086 reg = arm_reg_parse_multi (&peek);
4090 as_bad (_("register expected"));
4091 ignore_rest_of_line ();
4100 as_bad (_("FPA .unwind_save does not take a register list"));
4101 ignore_rest_of_line ();
4104 input_line_pointer = peek;
4105 s_arm_unwind_save_fpa (reg->number);
4108 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
4111 s_arm_unwind_save_vfp_armv6 ();
4113 s_arm_unwind_save_vfp ();
4115 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4116 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4119 as_bad (_(".unwind_save does not support this kind of register"));
4120 ignore_rest_of_line ();
4125 /* Parse an unwind_movsp directive. */
4128 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4134 if (!unwind.proc_start)
4135 as_bad (MISSING_FNSTART);
4137 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4140 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4141 ignore_rest_of_line ();
4145 /* Optional constant. */
4146 if (skip_past_comma (&input_line_pointer) != FAIL)
4148 if (immediate_for_directive (&offset) == FAIL)
4154 demand_empty_rest_of_line ();
4156 if (reg == REG_SP || reg == REG_PC)
4158 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4162 if (unwind.fp_reg != REG_SP)
4163 as_bad (_("unexpected .unwind_movsp directive"));
4165 /* Generate opcode to restore the value. */
4167 add_unwind_opcode (op, 1);
4169 /* Record the information for later. */
4170 unwind.fp_reg = reg;
4171 unwind.fp_offset = unwind.frame_size - offset;
4172 unwind.sp_restored = 1;
4175 /* Parse an unwind_pad directive. */
4178 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4182 if (!unwind.proc_start)
4183 as_bad (MISSING_FNSTART);
4185 if (immediate_for_directive (&offset) == FAIL)
4190 as_bad (_("stack increment must be multiple of 4"));
4191 ignore_rest_of_line ();
4195 /* Don't generate any opcodes, just record the details for later. */
4196 unwind.frame_size += offset;
4197 unwind.pending_offset += offset;
4199 demand_empty_rest_of_line ();
4202 /* Parse an unwind_setfp directive. */
4205 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4211 if (!unwind.proc_start)
4212 as_bad (MISSING_FNSTART);
4214 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4215 if (skip_past_comma (&input_line_pointer) == FAIL)
4218 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4220 if (fp_reg == FAIL || sp_reg == FAIL)
4222 as_bad (_("expected <reg>, <reg>"));
4223 ignore_rest_of_line ();
4227 /* Optional constant. */
4228 if (skip_past_comma (&input_line_pointer) != FAIL)
4230 if (immediate_for_directive (&offset) == FAIL)
4236 demand_empty_rest_of_line ();
4238 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4240 as_bad (_("register must be either sp or set by a previous"
4241 "unwind_movsp directive"));
4245 /* Don't generate any opcodes, just record the information for later. */
4246 unwind.fp_reg = fp_reg;
4248 if (sp_reg == REG_SP)
4249 unwind.fp_offset = unwind.frame_size - offset;
4251 unwind.fp_offset -= offset;
4254 /* Parse an unwind_raw directive. */
4257 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4260 /* This is an arbitrary limit. */
4261 unsigned char op[16];
4264 if (!unwind.proc_start)
4265 as_bad (MISSING_FNSTART);
4268 if (exp.X_op == O_constant
4269 && skip_past_comma (&input_line_pointer) != FAIL)
4271 unwind.frame_size += exp.X_add_number;
4275 exp.X_op = O_illegal;
4277 if (exp.X_op != O_constant)
4279 as_bad (_("expected <offset>, <opcode>"));
4280 ignore_rest_of_line ();
4286 /* Parse the opcode. */
4291 as_bad (_("unwind opcode too long"));
4292 ignore_rest_of_line ();
4294 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4296 as_bad (_("invalid unwind opcode"));
4297 ignore_rest_of_line ();
4300 op[count++] = exp.X_add_number;
4302 /* Parse the next byte. */
4303 if (skip_past_comma (&input_line_pointer) == FAIL)
4309 /* Add the opcode bytes in reverse order. */
4311 add_unwind_opcode (op[count], 1);
4313 demand_empty_rest_of_line ();
4317 /* Parse a .eabi_attribute directive. */
4320 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4322 int tag = s_vendor_attribute (OBJ_ATTR_PROC);
4324 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4325 attributes_set_explicitly[tag] = 1;
4328 /* Emit a tls fix for the symbol. */
4331 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4335 #ifdef md_flush_pending_output
4336 md_flush_pending_output ();
4339 #ifdef md_cons_align
4343 /* Since we're just labelling the code, there's no need to define a
4346 p = obstack_next_free (&frchain_now->frch_obstack);
4347 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4348 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4349 : BFD_RELOC_ARM_TLS_DESCSEQ);
4351 #endif /* OBJ_ELF */
4353 static void s_arm_arch (int);
4354 static void s_arm_object_arch (int);
4355 static void s_arm_cpu (int);
4356 static void s_arm_fpu (int);
4357 static void s_arm_arch_extension (int);
4362 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4369 if (exp.X_op == O_symbol)
4370 exp.X_op = O_secrel;
4372 emit_expr (&exp, 4);
4374 while (*input_line_pointer++ == ',');
4376 input_line_pointer--;
4377 demand_empty_rest_of_line ();
4381 /* This table describes all the machine specific pseudo-ops the assembler
4382 has to support. The fields are:
4383 pseudo-op name without dot
4384 function to call to execute this pseudo-op
4385 Integer arg to pass to the function. */
4387 const pseudo_typeS md_pseudo_table[] =
4389 /* Never called because '.req' does not start a line. */
4390 { "req", s_req, 0 },
4391 /* Following two are likewise never called. */
4394 { "unreq", s_unreq, 0 },
4395 { "bss", s_bss, 0 },
4396 { "align", s_align, 0 },
4397 { "arm", s_arm, 0 },
4398 { "thumb", s_thumb, 0 },
4399 { "code", s_code, 0 },
4400 { "force_thumb", s_force_thumb, 0 },
4401 { "thumb_func", s_thumb_func, 0 },
4402 { "thumb_set", s_thumb_set, 0 },
4403 { "even", s_even, 0 },
4404 { "ltorg", s_ltorg, 0 },
4405 { "pool", s_ltorg, 0 },
4406 { "syntax", s_syntax, 0 },
4407 { "cpu", s_arm_cpu, 0 },
4408 { "arch", s_arm_arch, 0 },
4409 { "object_arch", s_arm_object_arch, 0 },
4410 { "fpu", s_arm_fpu, 0 },
4411 { "arch_extension", s_arm_arch_extension, 0 },
4413 { "word", s_arm_elf_cons, 4 },
4414 { "long", s_arm_elf_cons, 4 },
4415 { "inst.n", s_arm_elf_inst, 2 },
4416 { "inst.w", s_arm_elf_inst, 4 },
4417 { "inst", s_arm_elf_inst, 0 },
4418 { "rel31", s_arm_rel31, 0 },
4419 { "fnstart", s_arm_unwind_fnstart, 0 },
4420 { "fnend", s_arm_unwind_fnend, 0 },
4421 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4422 { "personality", s_arm_unwind_personality, 0 },
4423 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4424 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4425 { "save", s_arm_unwind_save, 0 },
4426 { "vsave", s_arm_unwind_save, 1 },
4427 { "movsp", s_arm_unwind_movsp, 0 },
4428 { "pad", s_arm_unwind_pad, 0 },
4429 { "setfp", s_arm_unwind_setfp, 0 },
4430 { "unwind_raw", s_arm_unwind_raw, 0 },
4431 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4432 { "tlsdescseq", s_arm_tls_descseq, 0 },
4436 /* These are used for dwarf. */
4440 /* These are used for dwarf2. */
4441 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4442 { "loc", dwarf2_directive_loc, 0 },
4443 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4445 { "extend", float_cons, 'x' },
4446 { "ldouble", float_cons, 'x' },
4447 { "packed", float_cons, 'p' },
4449 {"secrel32", pe_directive_secrel, 0},
4454 /* Parser functions used exclusively in instruction operands. */
4456 /* Generic immediate-value read function for use in insn parsing.
4457 STR points to the beginning of the immediate (the leading #);
4458 VAL receives the value; if the value is outside [MIN, MAX]
4459 issue an error. PREFIX_OPT is true if the immediate prefix is
4463 parse_immediate (char **str, int *val, int min, int max,
4464 bfd_boolean prefix_opt)
4467 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4468 if (exp.X_op != O_constant)
4470 inst.error = _("constant expression required");
4474 if (exp.X_add_number < min || exp.X_add_number > max)
4476 inst.error = _("immediate value out of range");
4480 *val = exp.X_add_number;
4484 /* Less-generic immediate-value read function with the possibility of loading a
4485 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4486 instructions. Puts the result directly in inst.operands[i]. */
4489 parse_big_immediate (char **str, int i)
4494 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4496 if (exp.X_op == O_constant)
4498 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4499 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4500 O_constant. We have to be careful not to break compilation for
4501 32-bit X_add_number, though. */
4502 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4504 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4505 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4506 inst.operands[i].regisimm = 1;
4509 else if (exp.X_op == O_big
4510 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
4512 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4514 /* Bignums have their least significant bits in
4515 generic_bignum[0]. Make sure we put 32 bits in imm and
4516 32 bits in reg, in a (hopefully) portable way. */
4517 gas_assert (parts != 0);
4519 /* Make sure that the number is not too big.
4520 PR 11972: Bignums can now be sign-extended to the
4521 size of a .octa so check that the out of range bits
4522 are all zero or all one. */
4523 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4525 LITTLENUM_TYPE m = -1;
4527 if (generic_bignum[parts * 2] != 0
4528 && generic_bignum[parts * 2] != m)
4531 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4532 if (generic_bignum[j] != generic_bignum[j-1])
4536 inst.operands[i].imm = 0;
4537 for (j = 0; j < parts; j++, idx++)
4538 inst.operands[i].imm |= generic_bignum[idx]
4539 << (LITTLENUM_NUMBER_OF_BITS * j);
4540 inst.operands[i].reg = 0;
4541 for (j = 0; j < parts; j++, idx++)
4542 inst.operands[i].reg |= generic_bignum[idx]
4543 << (LITTLENUM_NUMBER_OF_BITS * j);
4544 inst.operands[i].regisimm = 1;
4554 /* Returns the pseudo-register number of an FPA immediate constant,
4555 or FAIL if there isn't a valid constant here. */
4558 parse_fpa_immediate (char ** str)
4560 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4566 /* First try and match exact strings, this is to guarantee
4567 that some formats will work even for cross assembly. */
4569 for (i = 0; fp_const[i]; i++)
4571 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4575 *str += strlen (fp_const[i]);
4576 if (is_end_of_line[(unsigned char) **str])
4582 /* Just because we didn't get a match doesn't mean that the constant
4583 isn't valid, just that it is in a format that we don't
4584 automatically recognize. Try parsing it with the standard
4585 expression routines. */
4587 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4589 /* Look for a raw floating point number. */
4590 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4591 && is_end_of_line[(unsigned char) *save_in])
4593 for (i = 0; i < NUM_FLOAT_VALS; i++)
4595 for (j = 0; j < MAX_LITTLENUMS; j++)
4597 if (words[j] != fp_values[i][j])
4601 if (j == MAX_LITTLENUMS)
4609 /* Try and parse a more complex expression, this will probably fail
4610 unless the code uses a floating point prefix (eg "0f"). */
4611 save_in = input_line_pointer;
4612 input_line_pointer = *str;
4613 if (expression (&exp) == absolute_section
4614 && exp.X_op == O_big
4615 && exp.X_add_number < 0)
4617 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4619 if (gen_to_words (words, 5, (long) 15) == 0)
4621 for (i = 0; i < NUM_FLOAT_VALS; i++)
4623 for (j = 0; j < MAX_LITTLENUMS; j++)
4625 if (words[j] != fp_values[i][j])
4629 if (j == MAX_LITTLENUMS)
4631 *str = input_line_pointer;
4632 input_line_pointer = save_in;
4639 *str = input_line_pointer;
4640 input_line_pointer = save_in;
4641 inst.error = _("invalid FPA immediate expression");
4645 /* Returns 1 if a number has "quarter-precision" float format
4646 0baBbbbbbc defgh000 00000000 00000000. */
4649 is_quarter_float (unsigned imm)
4651 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4652 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4655 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4656 0baBbbbbbc defgh000 00000000 00000000.
4657 The zero and minus-zero cases need special handling, since they can't be
4658 encoded in the "quarter-precision" float format, but can nonetheless be
4659 loaded as integer constants. */
4662 parse_qfloat_immediate (char **ccp, int *immed)
4666 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4667 int found_fpchar = 0;
4669 skip_past_char (&str, '#');
4671 /* We must not accidentally parse an integer as a floating-point number. Make
4672 sure that the value we parse is not an integer by checking for special
4673 characters '.' or 'e'.
4674 FIXME: This is a horrible hack, but doing better is tricky because type
4675 information isn't in a very usable state at parse time. */
4677 skip_whitespace (fpnum);
4679 if (strncmp (fpnum, "0x", 2) == 0)
4683 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
4684 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4694 if ((str = atof_ieee (str, 's', words)) != NULL)
4696 unsigned fpword = 0;
4699 /* Our FP word must be 32 bits (single-precision FP). */
4700 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
4702 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4706 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
4719 /* Shift operands. */
4722 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4725 struct asm_shift_name
4728 enum shift_kind kind;
4731 /* Third argument to parse_shift. */
4732 enum parse_shift_mode
4734 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4735 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4736 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4737 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4738 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4741 /* Parse a <shift> specifier on an ARM data processing instruction.
4742 This has three forms:
4744 (LSL|LSR|ASL|ASR|ROR) Rs
4745 (LSL|LSR|ASL|ASR|ROR) #imm
4748 Note that ASL is assimilated to LSL in the instruction encoding, and
4749 RRX to ROR #0 (which cannot be written as such). */
4752 parse_shift (char **str, int i, enum parse_shift_mode mode)
4754 const struct asm_shift_name *shift_name;
4755 enum shift_kind shift;
4760 for (p = *str; ISALPHA (*p); p++)
4765 inst.error = _("shift expression expected");
4769 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
4772 if (shift_name == NULL)
4774 inst.error = _("shift expression expected");
4778 shift = shift_name->kind;
4782 case NO_SHIFT_RESTRICT:
4783 case SHIFT_IMMEDIATE: break;
4785 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4786 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4788 inst.error = _("'LSL' or 'ASR' required");
4793 case SHIFT_LSL_IMMEDIATE:
4794 if (shift != SHIFT_LSL)
4796 inst.error = _("'LSL' required");
4801 case SHIFT_ASR_IMMEDIATE:
4802 if (shift != SHIFT_ASR)
4804 inst.error = _("'ASR' required");
4812 if (shift != SHIFT_RRX)
4814 /* Whitespace can appear here if the next thing is a bare digit. */
4815 skip_whitespace (p);
4817 if (mode == NO_SHIFT_RESTRICT
4818 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
4820 inst.operands[i].imm = reg;
4821 inst.operands[i].immisreg = 1;
4823 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4826 inst.operands[i].shift_kind = shift;
4827 inst.operands[i].shifted = 1;
4832 /* Parse a <shifter_operand> for an ARM data processing instruction:
4835 #<immediate>, <rotate>
4839 where <shift> is defined by parse_shift above, and <rotate> is a
4840 multiple of 2 between 0 and 30. Validation of immediate operands
4841 is deferred to md_apply_fix. */
4844 parse_shifter_operand (char **str, int i)
4849 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
4851 inst.operands[i].reg = value;
4852 inst.operands[i].isreg = 1;
4854 /* parse_shift will override this if appropriate */
4855 inst.reloc.exp.X_op = O_constant;
4856 inst.reloc.exp.X_add_number = 0;
4858 if (skip_past_comma (str) == FAIL)
4861 /* Shift operation on register. */
4862 return parse_shift (str, i, NO_SHIFT_RESTRICT);
4865 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4868 if (skip_past_comma (str) == SUCCESS)
4870 /* #x, y -- ie explicit rotation by Y. */
4871 if (my_get_expression (&exp, str, GE_NO_PREFIX))
4874 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
4876 inst.error = _("constant expression expected");
4880 value = exp.X_add_number;
4881 if (value < 0 || value > 30 || value % 2 != 0)
4883 inst.error = _("invalid rotation");
4886 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4888 inst.error = _("invalid constant");
4892 /* Encode as specified. */
4893 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4897 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4898 inst.reloc.pc_rel = 0;
4902 /* Group relocation information. Each entry in the table contains the
4903 textual name of the relocation as may appear in assembler source
4904 and must end with a colon.
4905 Along with this textual name are the relocation codes to be used if
4906 the corresponding instruction is an ALU instruction (ADD or SUB only),
4907 an LDR, an LDRS, or an LDC. */
4909 struct group_reloc_table_entry
4920 /* Varieties of non-ALU group relocation. */
4927 static struct group_reloc_table_entry group_reloc_table[] =
4928 { /* Program counter relative: */
4930 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4935 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4936 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4937 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4938 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4940 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4945 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4946 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4947 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4948 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4950 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4951 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4952 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4953 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4954 /* Section base relative */
4956 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4961 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4962 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4963 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4964 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4966 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4971 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
4972 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
4973 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
4974 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
4976 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
4977 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
4978 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
4979 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
4981 /* Given the address of a pointer pointing to the textual name of a group
4982 relocation as may appear in assembler source, attempt to find its details
4983 in group_reloc_table. The pointer will be updated to the character after
4984 the trailing colon. On failure, FAIL will be returned; SUCCESS
4985 otherwise. On success, *entry will be updated to point at the relevant
4986 group_reloc_table entry. */
4989 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
4992 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
4994 int length = strlen (group_reloc_table[i].name);
4996 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
4997 && (*str)[length] == ':')
4999 *out = &group_reloc_table[i];
5000 *str += (length + 1);
5008 /* Parse a <shifter_operand> for an ARM data processing instruction
5009 (as for parse_shifter_operand) where group relocations are allowed:
5012 #<immediate>, <rotate>
5013 #:<group_reloc>:<expression>
5017 where <group_reloc> is one of the strings defined in group_reloc_table.
5018 The hashes are optional.
5020 Everything else is as for parse_shifter_operand. */
5022 static parse_operand_result
5023 parse_shifter_operand_group_reloc (char **str, int i)
5025 /* Determine if we have the sequence of characters #: or just :
5026 coming next. If we do, then we check for a group relocation.
5027 If we don't, punt the whole lot to parse_shifter_operand. */
5029 if (((*str)[0] == '#' && (*str)[1] == ':')
5030 || (*str)[0] == ':')
5032 struct group_reloc_table_entry *entry;
5034 if ((*str)[0] == '#')
5039 /* Try to parse a group relocation. Anything else is an error. */
5040 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5042 inst.error = _("unknown group relocation");
5043 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5046 /* We now have the group relocation table entry corresponding to
5047 the name in the assembler source. Next, we parse the expression. */
5048 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5049 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5051 /* Record the relocation type (always the ALU variant here). */
5052 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5053 gas_assert (inst.reloc.type != 0);
5055 return PARSE_OPERAND_SUCCESS;
5058 return parse_shifter_operand (str, i) == SUCCESS
5059 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5061 /* Never reached. */
5064 /* Parse a Neon alignment expression. Information is written to
5065 inst.operands[i]. We assume the initial ':' has been skipped.
5067 align .imm = align << 8, .immisalign=1, .preind=0 */
5068 static parse_operand_result
5069 parse_neon_alignment (char **str, int i)
5074 my_get_expression (&exp, &p, GE_NO_PREFIX);
5076 if (exp.X_op != O_constant)
5078 inst.error = _("alignment must be constant");
5079 return PARSE_OPERAND_FAIL;
5082 inst.operands[i].imm = exp.X_add_number << 8;
5083 inst.operands[i].immisalign = 1;
5084 /* Alignments are not pre-indexes. */
5085 inst.operands[i].preind = 0;
5088 return PARSE_OPERAND_SUCCESS;
5091 /* Parse all forms of an ARM address expression. Information is written
5092 to inst.operands[i] and/or inst.reloc.
5094 Preindexed addressing (.preind=1):
5096 [Rn, #offset] .reg=Rn .reloc.exp=offset
5097 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5098 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5099 .shift_kind=shift .reloc.exp=shift_imm
5101 These three may have a trailing ! which causes .writeback to be set also.
5103 Postindexed addressing (.postind=1, .writeback=1):
5105 [Rn], #offset .reg=Rn .reloc.exp=offset
5106 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5107 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5108 .shift_kind=shift .reloc.exp=shift_imm
5110 Unindexed addressing (.preind=0, .postind=0):
5112 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5116 [Rn]{!} shorthand for [Rn,#0]{!}
5117 =immediate .isreg=0 .reloc.exp=immediate
5118 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5120 It is the caller's responsibility to check for addressing modes not
5121 supported by the instruction, and to set inst.reloc.type. */
5123 static parse_operand_result
5124 parse_address_main (char **str, int i, int group_relocations,
5125 group_reloc_type group_type)
5130 if (skip_past_char (&p, '[') == FAIL)
5132 if (skip_past_char (&p, '=') == FAIL)
5134 /* Bare address - translate to PC-relative offset. */
5135 inst.reloc.pc_rel = 1;
5136 inst.operands[i].reg = REG_PC;
5137 inst.operands[i].isreg = 1;
5138 inst.operands[i].preind = 1;
5140 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5142 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5143 return PARSE_OPERAND_FAIL;
5146 return PARSE_OPERAND_SUCCESS;
5149 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5151 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5152 return PARSE_OPERAND_FAIL;
5154 inst.operands[i].reg = reg;
5155 inst.operands[i].isreg = 1;
5157 if (skip_past_comma (&p) == SUCCESS)
5159 inst.operands[i].preind = 1;
5162 else if (*p == '-') p++, inst.operands[i].negative = 1;
5164 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5166 inst.operands[i].imm = reg;
5167 inst.operands[i].immisreg = 1;
5169 if (skip_past_comma (&p) == SUCCESS)
5170 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5171 return PARSE_OPERAND_FAIL;
5173 else if (skip_past_char (&p, ':') == SUCCESS)
5175 /* FIXME: '@' should be used here, but it's filtered out by generic
5176 code before we get to see it here. This may be subject to
5178 parse_operand_result result = parse_neon_alignment (&p, i);
5180 if (result != PARSE_OPERAND_SUCCESS)
5185 if (inst.operands[i].negative)
5187 inst.operands[i].negative = 0;
5191 if (group_relocations
5192 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5194 struct group_reloc_table_entry *entry;
5196 /* Skip over the #: or : sequence. */
5202 /* Try to parse a group relocation. Anything else is an
5204 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5206 inst.error = _("unknown group relocation");
5207 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5210 /* We now have the group relocation table entry corresponding to
5211 the name in the assembler source. Next, we parse the
5213 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5214 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5216 /* Record the relocation type. */
5220 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5224 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5228 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5235 if (inst.reloc.type == 0)
5237 inst.error = _("this group relocation is not allowed on this instruction");
5238 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5244 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5245 return PARSE_OPERAND_FAIL;
5246 /* If the offset is 0, find out if it's a +0 or -0. */
5247 if (inst.reloc.exp.X_op == O_constant
5248 && inst.reloc.exp.X_add_number == 0)
5250 skip_whitespace (q);
5254 skip_whitespace (q);
5257 inst.operands[i].negative = 1;
5262 else if (skip_past_char (&p, ':') == SUCCESS)
5264 /* FIXME: '@' should be used here, but it's filtered out by generic code
5265 before we get to see it here. This may be subject to change. */
5266 parse_operand_result result = parse_neon_alignment (&p, i);
5268 if (result != PARSE_OPERAND_SUCCESS)
5272 if (skip_past_char (&p, ']') == FAIL)
5274 inst.error = _("']' expected");
5275 return PARSE_OPERAND_FAIL;
5278 if (skip_past_char (&p, '!') == SUCCESS)
5279 inst.operands[i].writeback = 1;
5281 else if (skip_past_comma (&p) == SUCCESS)
5283 if (skip_past_char (&p, '{') == SUCCESS)
5285 /* [Rn], {expr} - unindexed, with option */
5286 if (parse_immediate (&p, &inst.operands[i].imm,
5287 0, 255, TRUE) == FAIL)
5288 return PARSE_OPERAND_FAIL;
5290 if (skip_past_char (&p, '}') == FAIL)
5292 inst.error = _("'}' expected at end of 'option' field");
5293 return PARSE_OPERAND_FAIL;
5295 if (inst.operands[i].preind)
5297 inst.error = _("cannot combine index with option");
5298 return PARSE_OPERAND_FAIL;
5301 return PARSE_OPERAND_SUCCESS;
5305 inst.operands[i].postind = 1;
5306 inst.operands[i].writeback = 1;
5308 if (inst.operands[i].preind)
5310 inst.error = _("cannot combine pre- and post-indexing");
5311 return PARSE_OPERAND_FAIL;
5315 else if (*p == '-') p++, inst.operands[i].negative = 1;
5317 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5319 /* We might be using the immediate for alignment already. If we
5320 are, OR the register number into the low-order bits. */
5321 if (inst.operands[i].immisalign)
5322 inst.operands[i].imm |= reg;
5324 inst.operands[i].imm = reg;
5325 inst.operands[i].immisreg = 1;
5327 if (skip_past_comma (&p) == SUCCESS)
5328 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5329 return PARSE_OPERAND_FAIL;
5334 if (inst.operands[i].negative)
5336 inst.operands[i].negative = 0;
5339 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5340 return PARSE_OPERAND_FAIL;
5341 /* If the offset is 0, find out if it's a +0 or -0. */
5342 if (inst.reloc.exp.X_op == O_constant
5343 && inst.reloc.exp.X_add_number == 0)
5345 skip_whitespace (q);
5349 skip_whitespace (q);
5352 inst.operands[i].negative = 1;
5358 /* If at this point neither .preind nor .postind is set, we have a
5359 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5360 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5362 inst.operands[i].preind = 1;
5363 inst.reloc.exp.X_op = O_constant;
5364 inst.reloc.exp.X_add_number = 0;
5367 return PARSE_OPERAND_SUCCESS;
5371 parse_address (char **str, int i)
5373 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5377 static parse_operand_result
5378 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5380 return parse_address_main (str, i, 1, type);
5383 /* Parse an operand for a MOVW or MOVT instruction. */
5385 parse_half (char **str)
5390 skip_past_char (&p, '#');
5391 if (strncasecmp (p, ":lower16:", 9) == 0)
5392 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5393 else if (strncasecmp (p, ":upper16:", 9) == 0)
5394 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5396 if (inst.reloc.type != BFD_RELOC_UNUSED)
5399 skip_whitespace (p);
5402 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5405 if (inst.reloc.type == BFD_RELOC_UNUSED)
5407 if (inst.reloc.exp.X_op != O_constant)
5409 inst.error = _("constant expression expected");
5412 if (inst.reloc.exp.X_add_number < 0
5413 || inst.reloc.exp.X_add_number > 0xffff)
5415 inst.error = _("immediate value out of range");
5423 /* Miscellaneous. */
5425 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5426 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5428 parse_psr (char **str, bfd_boolean lhs)
5431 unsigned long psr_field;
5432 const struct asm_psr *psr;
5434 bfd_boolean is_apsr = FALSE;
5435 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5437 /* PR gas/12698: If the user has specified -march=all then m_profile will
5438 be TRUE, but we want to ignore it in this case as we are building for any
5439 CPU type, including non-m variants. */
5440 if (selected_cpu.core == arm_arch_any.core)
5443 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5444 feature for ease of use and backwards compatibility. */
5446 if (strncasecmp (p, "SPSR", 4) == 0)
5449 goto unsupported_psr;
5451 psr_field = SPSR_BIT;
5453 else if (strncasecmp (p, "CPSR", 4) == 0)
5456 goto unsupported_psr;
5460 else if (strncasecmp (p, "APSR", 4) == 0)
5462 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5463 and ARMv7-R architecture CPUs. */
5472 while (ISALNUM (*p) || *p == '_');
5474 if (strncasecmp (start, "iapsr", 5) == 0
5475 || strncasecmp (start, "eapsr", 5) == 0
5476 || strncasecmp (start, "xpsr", 4) == 0
5477 || strncasecmp (start, "psr", 3) == 0)
5478 p = start + strcspn (start, "rR") + 1;
5480 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5486 /* If APSR is being written, a bitfield may be specified. Note that
5487 APSR itself is handled above. */
5488 if (psr->field <= 3)
5490 psr_field = psr->field;
5496 /* M-profile MSR instructions have the mask field set to "10", except
5497 *PSR variants which modify APSR, which may use a different mask (and
5498 have been handled already). Do that by setting the PSR_f field
5500 return psr->field | (lhs ? PSR_f : 0);
5503 goto unsupported_psr;
5509 /* A suffix follows. */
5515 while (ISALNUM (*p) || *p == '_');
5519 /* APSR uses a notation for bits, rather than fields. */
5520 unsigned int nzcvq_bits = 0;
5521 unsigned int g_bit = 0;
5524 for (bit = start; bit != p; bit++)
5526 switch (TOLOWER (*bit))
5529 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5533 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5537 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5541 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5545 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5549 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5553 inst.error = _("unexpected bit specified after APSR");
5558 if (nzcvq_bits == 0x1f)
5563 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5565 inst.error = _("selected processor does not "
5566 "support DSP extension");
5573 if ((nzcvq_bits & 0x20) != 0
5574 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5575 || (g_bit & 0x2) != 0)
5577 inst.error = _("bad bitmask specified after APSR");
5583 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5588 psr_field |= psr->field;
5594 goto error; /* Garbage after "[CS]PSR". */
5596 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5597 is deprecated, but allow it anyway. */
5601 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5604 else if (!m_profile)
5605 /* These bits are never right for M-profile devices: don't set them
5606 (only code paths which read/write APSR reach here). */
5607 psr_field |= (PSR_c | PSR_f);
5613 inst.error = _("selected processor does not support requested special "
5614 "purpose register");
5618 inst.error = _("flag for {c}psr instruction expected");
5622 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5623 value suitable for splatting into the AIF field of the instruction. */
5626 parse_cps_flags (char **str)
5635 case '\0': case ',':
5638 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5639 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5640 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5643 inst.error = _("unrecognized CPS flag");
5648 if (saw_a_flag == 0)
5650 inst.error = _("missing CPS flags");
5658 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5659 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5662 parse_endian_specifier (char **str)
5667 if (strncasecmp (s, "BE", 2))
5669 else if (strncasecmp (s, "LE", 2))
5673 inst.error = _("valid endian specifiers are be or le");
5677 if (ISALNUM (s[2]) || s[2] == '_')
5679 inst.error = _("valid endian specifiers are be or le");
5684 return little_endian;
5687 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5688 value suitable for poking into the rotate field of an sxt or sxta
5689 instruction, or FAIL on error. */
5692 parse_ror (char **str)
5697 if (strncasecmp (s, "ROR", 3) == 0)
5701 inst.error = _("missing rotation field after comma");
5705 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5710 case 0: *str = s; return 0x0;
5711 case 8: *str = s; return 0x1;
5712 case 16: *str = s; return 0x2;
5713 case 24: *str = s; return 0x3;
5716 inst.error = _("rotation can only be 0, 8, 16, or 24");
5721 /* Parse a conditional code (from conds[] below). The value returned is in the
5722 range 0 .. 14, or FAIL. */
5724 parse_cond (char **str)
5727 const struct asm_cond *c;
5729 /* Condition codes are always 2 characters, so matching up to
5730 3 characters is sufficient. */
5735 while (ISALPHA (*q) && n < 3)
5737 cond[n] = TOLOWER (*q);
5742 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
5745 inst.error = _("condition required");
5753 /* Parse an option for a barrier instruction. Returns the encoding for the
5756 parse_barrier (char **str)
5759 const struct asm_barrier_opt *o;
5762 while (ISALPHA (*q))
5765 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
5774 /* Parse the operands of a table branch instruction. Similar to a memory
5777 parse_tb (char **str)
5782 if (skip_past_char (&p, '[') == FAIL)
5784 inst.error = _("'[' expected");
5788 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5790 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5793 inst.operands[0].reg = reg;
5795 if (skip_past_comma (&p) == FAIL)
5797 inst.error = _("',' expected");
5801 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5803 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5806 inst.operands[0].imm = reg;
5808 if (skip_past_comma (&p) == SUCCESS)
5810 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5812 if (inst.reloc.exp.X_add_number != 1)
5814 inst.error = _("invalid shift");
5817 inst.operands[0].shifted = 1;
5820 if (skip_past_char (&p, ']') == FAIL)
5822 inst.error = _("']' expected");
5829 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5830 information on the types the operands can take and how they are encoded.
5831 Up to four operands may be read; this function handles setting the
5832 ".present" field for each read operand itself.
5833 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5834 else returns FAIL. */
5837 parse_neon_mov (char **str, int *which_operand)
5839 int i = *which_operand, val;
5840 enum arm_reg_type rtype;
5842 struct neon_type_el optype;
5844 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5846 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5847 inst.operands[i].reg = val;
5848 inst.operands[i].isscalar = 1;
5849 inst.operands[i].vectype = optype;
5850 inst.operands[i++].present = 1;
5852 if (skip_past_comma (&ptr) == FAIL)
5855 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5858 inst.operands[i].reg = val;
5859 inst.operands[i].isreg = 1;
5860 inst.operands[i].present = 1;
5862 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
5865 /* Cases 0, 1, 2, 3, 5 (D only). */
5866 if (skip_past_comma (&ptr) == FAIL)
5869 inst.operands[i].reg = val;
5870 inst.operands[i].isreg = 1;
5871 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5872 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5873 inst.operands[i].isvec = 1;
5874 inst.operands[i].vectype = optype;
5875 inst.operands[i++].present = 1;
5877 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5879 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5880 Case 13: VMOV <Sd>, <Rm> */
5881 inst.operands[i].reg = val;
5882 inst.operands[i].isreg = 1;
5883 inst.operands[i].present = 1;
5885 if (rtype == REG_TYPE_NQ)
5887 first_error (_("can't use Neon quad register here"));
5890 else if (rtype != REG_TYPE_VFS)
5893 if (skip_past_comma (&ptr) == FAIL)
5895 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5897 inst.operands[i].reg = val;
5898 inst.operands[i].isreg = 1;
5899 inst.operands[i].present = 1;
5902 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
5905 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5906 Case 1: VMOV<c><q> <Dd>, <Dm>
5907 Case 8: VMOV.F32 <Sd>, <Sm>
5908 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5910 inst.operands[i].reg = val;
5911 inst.operands[i].isreg = 1;
5912 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5913 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5914 inst.operands[i].isvec = 1;
5915 inst.operands[i].vectype = optype;
5916 inst.operands[i].present = 1;
5918 if (skip_past_comma (&ptr) == SUCCESS)
5923 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5926 inst.operands[i].reg = val;
5927 inst.operands[i].isreg = 1;
5928 inst.operands[i++].present = 1;
5930 if (skip_past_comma (&ptr) == FAIL)
5933 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5936 inst.operands[i].reg = val;
5937 inst.operands[i].isreg = 1;
5938 inst.operands[i].present = 1;
5941 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
5942 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5943 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5944 Case 10: VMOV.F32 <Sd>, #<imm>
5945 Case 11: VMOV.F64 <Dd>, #<imm> */
5946 inst.operands[i].immisfloat = 1;
5947 else if (parse_big_immediate (&ptr, i) == SUCCESS)
5948 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5949 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5953 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5957 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5960 inst.operands[i].reg = val;
5961 inst.operands[i].isreg = 1;
5962 inst.operands[i++].present = 1;
5964 if (skip_past_comma (&ptr) == FAIL)
5967 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5969 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5970 inst.operands[i].reg = val;
5971 inst.operands[i].isscalar = 1;
5972 inst.operands[i].present = 1;
5973 inst.operands[i].vectype = optype;
5975 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5977 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5978 inst.operands[i].reg = val;
5979 inst.operands[i].isreg = 1;
5980 inst.operands[i++].present = 1;
5982 if (skip_past_comma (&ptr) == FAIL)
5985 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
5988 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
5992 inst.operands[i].reg = val;
5993 inst.operands[i].isreg = 1;
5994 inst.operands[i].isvec = 1;
5995 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5996 inst.operands[i].vectype = optype;
5997 inst.operands[i].present = 1;
5999 if (rtype == REG_TYPE_VFS)
6003 if (skip_past_comma (&ptr) == FAIL)
6005 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6008 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6011 inst.operands[i].reg = val;
6012 inst.operands[i].isreg = 1;
6013 inst.operands[i].isvec = 1;
6014 inst.operands[i].issingle = 1;
6015 inst.operands[i].vectype = optype;
6016 inst.operands[i].present = 1;
6019 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6023 inst.operands[i].reg = val;
6024 inst.operands[i].isreg = 1;
6025 inst.operands[i].isvec = 1;
6026 inst.operands[i].issingle = 1;
6027 inst.operands[i].vectype = optype;
6028 inst.operands[i].present = 1;
6033 first_error (_("parse error"));
6037 /* Successfully parsed the operands. Update args. */
6043 first_error (_("expected comma"));
6047 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6051 /* Use this macro when the operand constraints are different
6052 for ARM and THUMB (e.g. ldrd). */
6053 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6054 ((arm_operand) | ((thumb_operand) << 16))
6056 /* Matcher codes for parse_operands. */
6057 enum operand_parse_code
6059 OP_stop, /* end of line */
6061 OP_RR, /* ARM register */
6062 OP_RRnpc, /* ARM register, not r15 */
6063 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6064 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6065 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6066 optional trailing ! */
6067 OP_RRw, /* ARM register, not r15, optional trailing ! */
6068 OP_RCP, /* Coprocessor number */
6069 OP_RCN, /* Coprocessor register */
6070 OP_RF, /* FPA register */
6071 OP_RVS, /* VFP single precision register */
6072 OP_RVD, /* VFP double precision register (0..15) */
6073 OP_RND, /* Neon double precision register (0..31) */
6074 OP_RNQ, /* Neon quad precision register */
6075 OP_RVSD, /* VFP single or double precision register */
6076 OP_RNDQ, /* Neon double or quad precision register */
6077 OP_RNSDQ, /* Neon single, double or quad precision register */
6078 OP_RNSC, /* Neon scalar D[X] */
6079 OP_RVC, /* VFP control register */
6080 OP_RMF, /* Maverick F register */
6081 OP_RMD, /* Maverick D register */
6082 OP_RMFX, /* Maverick FX register */
6083 OP_RMDX, /* Maverick DX register */
6084 OP_RMAX, /* Maverick AX register */
6085 OP_RMDS, /* Maverick DSPSC register */
6086 OP_RIWR, /* iWMMXt wR register */
6087 OP_RIWC, /* iWMMXt wC register */
6088 OP_RIWG, /* iWMMXt wCG register */
6089 OP_RXA, /* XScale accumulator register */
6091 OP_REGLST, /* ARM register list */
6092 OP_VRSLST, /* VFP single-precision register list */
6093 OP_VRDLST, /* VFP double-precision register list */
6094 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6095 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6096 OP_NSTRLST, /* Neon element/structure list */
6098 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6099 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6100 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6101 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6102 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6103 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6104 OP_VMOV, /* Neon VMOV operands. */
6105 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6106 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6107 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6109 OP_I0, /* immediate zero */
6110 OP_I7, /* immediate value 0 .. 7 */
6111 OP_I15, /* 0 .. 15 */
6112 OP_I16, /* 1 .. 16 */
6113 OP_I16z, /* 0 .. 16 */
6114 OP_I31, /* 0 .. 31 */
6115 OP_I31w, /* 0 .. 31, optional trailing ! */
6116 OP_I32, /* 1 .. 32 */
6117 OP_I32z, /* 0 .. 32 */
6118 OP_I63, /* 0 .. 63 */
6119 OP_I63s, /* -64 .. 63 */
6120 OP_I64, /* 1 .. 64 */
6121 OP_I64z, /* 0 .. 64 */
6122 OP_I255, /* 0 .. 255 */
6124 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6125 OP_I7b, /* 0 .. 7 */
6126 OP_I15b, /* 0 .. 15 */
6127 OP_I31b, /* 0 .. 31 */
6129 OP_SH, /* shifter operand */
6130 OP_SHG, /* shifter operand with possible group relocation */
6131 OP_ADDR, /* Memory address expression (any mode) */
6132 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6133 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6134 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6135 OP_EXP, /* arbitrary expression */
6136 OP_EXPi, /* same, with optional immediate prefix */
6137 OP_EXPr, /* same, with optional relocation suffix */
6138 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6140 OP_CPSF, /* CPS flags */
6141 OP_ENDI, /* Endianness specifier */
6142 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6143 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6144 OP_COND, /* conditional code */
6145 OP_TB, /* Table branch. */
6147 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6149 OP_RRnpc_I0, /* ARM register or literal 0 */
6150 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6151 OP_RR_EXi, /* ARM register or expression with imm prefix */
6152 OP_RF_IF, /* FPA register or immediate */
6153 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6154 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6156 /* Optional operands. */
6157 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6158 OP_oI31b, /* 0 .. 31 */
6159 OP_oI32b, /* 1 .. 32 */
6160 OP_oI32z, /* 0 .. 32 */
6161 OP_oIffffb, /* 0 .. 65535 */
6162 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6164 OP_oRR, /* ARM register */
6165 OP_oRRnpc, /* ARM register, not the PC */
6166 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6167 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6168 OP_oRND, /* Optional Neon double precision register */
6169 OP_oRNQ, /* Optional Neon quad precision register */
6170 OP_oRNDQ, /* Optional Neon double or quad precision register */
6171 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6172 OP_oSHll, /* LSL immediate */
6173 OP_oSHar, /* ASR immediate */
6174 OP_oSHllar, /* LSL or ASR immediate */
6175 OP_oROR, /* ROR 0/8/16/24 */
6176 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6178 /* Some pre-defined mixed (ARM/THUMB) operands. */
6179 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6180 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6181 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6183 OP_FIRST_OPTIONAL = OP_oI7b
6186 /* Generic instruction operand parser. This does no encoding and no
6187 semantic validation; it merely squirrels values away in the inst
6188 structure. Returns SUCCESS or FAIL depending on whether the
6189 specified grammar matched. */
6191 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6193 unsigned const int *upat = pattern;
6194 char *backtrack_pos = 0;
6195 const char *backtrack_error = 0;
6196 int i, val, backtrack_index = 0;
6197 enum arm_reg_type rtype;
6198 parse_operand_result result;
6199 unsigned int op_parse_code;
6201 #define po_char_or_fail(chr) \
6204 if (skip_past_char (&str, chr) == FAIL) \
6209 #define po_reg_or_fail(regtype) \
6212 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6213 & inst.operands[i].vectype); \
6216 first_error (_(reg_expected_msgs[regtype])); \
6219 inst.operands[i].reg = val; \
6220 inst.operands[i].isreg = 1; \
6221 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6222 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6223 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6224 || rtype == REG_TYPE_VFD \
6225 || rtype == REG_TYPE_NQ); \
6229 #define po_reg_or_goto(regtype, label) \
6232 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6233 & inst.operands[i].vectype); \
6237 inst.operands[i].reg = val; \
6238 inst.operands[i].isreg = 1; \
6239 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6240 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6241 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6242 || rtype == REG_TYPE_VFD \
6243 || rtype == REG_TYPE_NQ); \
6247 #define po_imm_or_fail(min, max, popt) \
6250 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6252 inst.operands[i].imm = val; \
6256 #define po_scalar_or_goto(elsz, label) \
6259 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6262 inst.operands[i].reg = val; \
6263 inst.operands[i].isscalar = 1; \
6267 #define po_misc_or_fail(expr) \
6275 #define po_misc_or_fail_no_backtrack(expr) \
6279 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6280 backtrack_pos = 0; \
6281 if (result != PARSE_OPERAND_SUCCESS) \
6286 #define po_barrier_or_imm(str) \
6289 val = parse_barrier (&str); \
6292 if (ISALPHA (*str)) \
6299 if ((inst.instruction & 0xf0) == 0x60 \
6302 /* ISB can only take SY as an option. */ \
6303 inst.error = _("invalid barrier type"); \
6310 skip_whitespace (str);
6312 for (i = 0; upat[i] != OP_stop; i++)
6314 op_parse_code = upat[i];
6315 if (op_parse_code >= 1<<16)
6316 op_parse_code = thumb ? (op_parse_code >> 16)
6317 : (op_parse_code & ((1<<16)-1));
6319 if (op_parse_code >= OP_FIRST_OPTIONAL)
6321 /* Remember where we are in case we need to backtrack. */
6322 gas_assert (!backtrack_pos);
6323 backtrack_pos = str;
6324 backtrack_error = inst.error;
6325 backtrack_index = i;
6328 if (i > 0 && (i > 1 || inst.operands[0].present))
6329 po_char_or_fail (',');
6331 switch (op_parse_code)
6339 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6340 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6341 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6342 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6343 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6344 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6346 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6348 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6350 /* Also accept generic coprocessor regs for unknown registers. */
6352 po_reg_or_fail (REG_TYPE_CN);
6354 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6355 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6356 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6357 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6358 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6359 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6360 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6361 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6362 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6363 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6365 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6367 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6368 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6370 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6372 /* Neon scalar. Using an element size of 8 means that some invalid
6373 scalars are accepted here, so deal with those in later code. */
6374 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6378 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6381 po_imm_or_fail (0, 0, TRUE);
6386 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6391 po_scalar_or_goto (8, try_rr);
6394 po_reg_or_fail (REG_TYPE_RN);
6400 po_scalar_or_goto (8, try_nsdq);
6403 po_reg_or_fail (REG_TYPE_NSDQ);
6409 po_scalar_or_goto (8, try_ndq);
6412 po_reg_or_fail (REG_TYPE_NDQ);
6418 po_scalar_or_goto (8, try_vfd);
6421 po_reg_or_fail (REG_TYPE_VFD);
6426 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6427 not careful then bad things might happen. */
6428 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6433 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6436 /* There's a possibility of getting a 64-bit immediate here, so
6437 we need special handling. */
6438 if (parse_big_immediate (&str, i) == FAIL)
6440 inst.error = _("immediate value is out of range");
6448 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6451 po_imm_or_fail (0, 63, TRUE);
6456 po_char_or_fail ('[');
6457 po_reg_or_fail (REG_TYPE_RN);
6458 po_char_or_fail (']');
6464 po_reg_or_fail (REG_TYPE_RN);
6465 if (skip_past_char (&str, '!') == SUCCESS)
6466 inst.operands[i].writeback = 1;
6470 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6471 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6472 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6473 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6474 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6475 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6476 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6477 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6478 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6479 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6480 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6481 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6483 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6485 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6486 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6488 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6489 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6490 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6491 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6493 /* Immediate variants */
6495 po_char_or_fail ('{');
6496 po_imm_or_fail (0, 255, TRUE);
6497 po_char_or_fail ('}');
6501 /* The expression parser chokes on a trailing !, so we have
6502 to find it first and zap it. */
6505 while (*s && *s != ',')
6510 inst.operands[i].writeback = 1;
6512 po_imm_or_fail (0, 31, TRUE);
6520 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6525 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6530 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6532 if (inst.reloc.exp.X_op == O_symbol)
6534 val = parse_reloc (&str);
6537 inst.error = _("unrecognized relocation suffix");
6540 else if (val != BFD_RELOC_UNUSED)
6542 inst.operands[i].imm = val;
6543 inst.operands[i].hasreloc = 1;
6548 /* Operand for MOVW or MOVT. */
6550 po_misc_or_fail (parse_half (&str));
6553 /* Register or expression. */
6554 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6555 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6557 /* Register or immediate. */
6558 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6559 I0: po_imm_or_fail (0, 0, FALSE); break;
6561 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6563 if (!is_immediate_prefix (*str))
6566 val = parse_fpa_immediate (&str);
6569 /* FPA immediates are encoded as registers 8-15.
6570 parse_fpa_immediate has already applied the offset. */
6571 inst.operands[i].reg = val;
6572 inst.operands[i].isreg = 1;
6575 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6576 I32z: po_imm_or_fail (0, 32, FALSE); break;
6578 /* Two kinds of register. */
6581 struct reg_entry *rege = arm_reg_parse_multi (&str);
6583 || (rege->type != REG_TYPE_MMXWR
6584 && rege->type != REG_TYPE_MMXWC
6585 && rege->type != REG_TYPE_MMXWCG))
6587 inst.error = _("iWMMXt data or control register expected");
6590 inst.operands[i].reg = rege->number;
6591 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6597 struct reg_entry *rege = arm_reg_parse_multi (&str);
6599 || (rege->type != REG_TYPE_MMXWC
6600 && rege->type != REG_TYPE_MMXWCG))
6602 inst.error = _("iWMMXt control register expected");
6605 inst.operands[i].reg = rege->number;
6606 inst.operands[i].isreg = 1;
6611 case OP_CPSF: val = parse_cps_flags (&str); break;
6612 case OP_ENDI: val = parse_endian_specifier (&str); break;
6613 case OP_oROR: val = parse_ror (&str); break;
6614 case OP_COND: val = parse_cond (&str); break;
6615 case OP_oBARRIER_I15:
6616 po_barrier_or_imm (str); break;
6618 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
6624 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6625 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6627 inst.error = _("Banked registers are not available with this "
6633 val = parse_psr (&str, op_parse_code == OP_wPSR);
6637 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6640 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6642 if (strncasecmp (str, "APSR_", 5) == 0)
6649 case 'c': found = (found & 1) ? 16 : found | 1; break;
6650 case 'n': found = (found & 2) ? 16 : found | 2; break;
6651 case 'z': found = (found & 4) ? 16 : found | 4; break;
6652 case 'v': found = (found & 8) ? 16 : found | 8; break;
6653 default: found = 16;
6657 inst.operands[i].isvec = 1;
6658 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6659 inst.operands[i].reg = REG_PC;
6666 po_misc_or_fail (parse_tb (&str));
6669 /* Register lists. */
6671 val = parse_reg_list (&str);
6674 inst.operands[1].writeback = 1;
6680 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
6684 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
6688 /* Allow Q registers too. */
6689 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6694 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6696 inst.operands[i].issingle = 1;
6701 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6706 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6707 &inst.operands[i].vectype);
6710 /* Addressing modes */
6712 po_misc_or_fail (parse_address (&str, i));
6716 po_misc_or_fail_no_backtrack (
6717 parse_address_group_reloc (&str, i, GROUP_LDR));
6721 po_misc_or_fail_no_backtrack (
6722 parse_address_group_reloc (&str, i, GROUP_LDRS));
6726 po_misc_or_fail_no_backtrack (
6727 parse_address_group_reloc (&str, i, GROUP_LDC));
6731 po_misc_or_fail (parse_shifter_operand (&str, i));
6735 po_misc_or_fail_no_backtrack (
6736 parse_shifter_operand_group_reloc (&str, i));
6740 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6744 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6748 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6752 as_fatal (_("unhandled operand code %d"), op_parse_code);
6755 /* Various value-based sanity checks and shared operations. We
6756 do not signal immediate failures for the register constraints;
6757 this allows a syntax error to take precedence. */
6758 switch (op_parse_code)
6766 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6767 inst.error = BAD_PC;
6772 if (inst.operands[i].isreg)
6774 if (inst.operands[i].reg == REG_PC)
6775 inst.error = BAD_PC;
6776 else if (inst.operands[i].reg == REG_SP)
6777 inst.error = BAD_SP;
6782 if (inst.operands[i].isreg
6783 && inst.operands[i].reg == REG_PC
6784 && (inst.operands[i].writeback || thumb))
6785 inst.error = BAD_PC;
6794 case OP_oBARRIER_I15:
6803 inst.operands[i].imm = val;
6810 /* If we get here, this operand was successfully parsed. */
6811 inst.operands[i].present = 1;
6815 inst.error = BAD_ARGS;
6820 /* The parse routine should already have set inst.error, but set a
6821 default here just in case. */
6823 inst.error = _("syntax error");
6827 /* Do not backtrack over a trailing optional argument that
6828 absorbed some text. We will only fail again, with the
6829 'garbage following instruction' error message, which is
6830 probably less helpful than the current one. */
6831 if (backtrack_index == i && backtrack_pos != str
6832 && upat[i+1] == OP_stop)
6835 inst.error = _("syntax error");
6839 /* Try again, skipping the optional argument at backtrack_pos. */
6840 str = backtrack_pos;
6841 inst.error = backtrack_error;
6842 inst.operands[backtrack_index].present = 0;
6843 i = backtrack_index;
6847 /* Check that we have parsed all the arguments. */
6848 if (*str != '\0' && !inst.error)
6849 inst.error = _("garbage following instruction");
6851 return inst.error ? FAIL : SUCCESS;
6854 #undef po_char_or_fail
6855 #undef po_reg_or_fail
6856 #undef po_reg_or_goto
6857 #undef po_imm_or_fail
6858 #undef po_scalar_or_fail
6859 #undef po_barrier_or_imm
6861 /* Shorthand macro for instruction encoding functions issuing errors. */
6862 #define constraint(expr, err) \
6873 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6874 instructions are unpredictable if these registers are used. This
6875 is the BadReg predicate in ARM's Thumb-2 documentation. */
6876 #define reject_bad_reg(reg) \
6878 if (reg == REG_SP || reg == REG_PC) \
6880 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6885 /* If REG is R13 (the stack pointer), warn that its use is
6887 #define warn_deprecated_sp(reg) \
6889 if (warn_on_deprecated && reg == REG_SP) \
6890 as_warn (_("use of r13 is deprecated")); \
6893 /* Functions for operand encoding. ARM, then Thumb. */
6895 #define rotate_left(v, n) (v << n | v >> (32 - n))
6897 /* If VAL can be encoded in the immediate field of an ARM instruction,
6898 return the encoded form. Otherwise, return FAIL. */
6901 encode_arm_immediate (unsigned int val)
6905 for (i = 0; i < 32; i += 2)
6906 if ((a = rotate_left (val, i)) <= 0xff)
6907 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6912 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6913 return the encoded form. Otherwise, return FAIL. */
6915 encode_thumb32_immediate (unsigned int val)
6922 for (i = 1; i <= 24; i++)
6925 if ((val & ~(0xff << i)) == 0)
6926 return ((val >> i) & 0x7f) | ((32 - i) << 7);
6930 if (val == ((a << 16) | a))
6932 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6936 if (val == ((a << 16) | a))
6937 return 0x200 | (a >> 8);
6941 /* Encode a VFP SP or DP register number into inst.instruction. */
6944 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6946 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6949 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
6952 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
6955 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
6960 first_error (_("D register out of range for selected VFP version"));
6968 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
6972 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
6976 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
6980 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
6984 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
6988 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
6996 /* Encode a <shift> in an ARM-format instruction. The immediate,
6997 if any, is handled by md_apply_fix. */
6999 encode_arm_shift (int i)
7001 if (inst.operands[i].shift_kind == SHIFT_RRX)
7002 inst.instruction |= SHIFT_ROR << 5;
7005 inst.instruction |= inst.operands[i].shift_kind << 5;
7006 if (inst.operands[i].immisreg)
7008 inst.instruction |= SHIFT_BY_REG;
7009 inst.instruction |= inst.operands[i].imm << 8;
7012 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7017 encode_arm_shifter_operand (int i)
7019 if (inst.operands[i].isreg)
7021 inst.instruction |= inst.operands[i].reg;
7022 encode_arm_shift (i);
7026 inst.instruction |= INST_IMMEDIATE;
7027 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7028 inst.instruction |= inst.operands[i].imm;
7032 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7034 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7036 gas_assert (inst.operands[i].isreg);
7037 inst.instruction |= inst.operands[i].reg << 16;
7039 if (inst.operands[i].preind)
7043 inst.error = _("instruction does not accept preindexed addressing");
7046 inst.instruction |= PRE_INDEX;
7047 if (inst.operands[i].writeback)
7048 inst.instruction |= WRITE_BACK;
7051 else if (inst.operands[i].postind)
7053 gas_assert (inst.operands[i].writeback);
7055 inst.instruction |= WRITE_BACK;
7057 else /* unindexed - only for coprocessor */
7059 inst.error = _("instruction does not accept unindexed addressing");
7063 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7064 && (((inst.instruction & 0x000f0000) >> 16)
7065 == ((inst.instruction & 0x0000f000) >> 12)))
7066 as_warn ((inst.instruction & LOAD_BIT)
7067 ? _("destination register same as write-back base")
7068 : _("source register same as write-back base"));
7071 /* inst.operands[i] was set up by parse_address. Encode it into an
7072 ARM-format mode 2 load or store instruction. If is_t is true,
7073 reject forms that cannot be used with a T instruction (i.e. not
7076 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7078 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7080 encode_arm_addr_mode_common (i, is_t);
7082 if (inst.operands[i].immisreg)
7084 constraint ((inst.operands[i].imm == REG_PC
7085 || (is_pc && inst.operands[i].writeback)),
7087 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7088 inst.instruction |= inst.operands[i].imm;
7089 if (!inst.operands[i].negative)
7090 inst.instruction |= INDEX_UP;
7091 if (inst.operands[i].shifted)
7093 if (inst.operands[i].shift_kind == SHIFT_RRX)
7094 inst.instruction |= SHIFT_ROR << 5;
7097 inst.instruction |= inst.operands[i].shift_kind << 5;
7098 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7102 else /* immediate offset in inst.reloc */
7104 if (is_pc && !inst.reloc.pc_rel)
7106 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7108 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7109 cannot use PC in addressing.
7110 PC cannot be used in writeback addressing, either. */
7111 constraint ((is_t || inst.operands[i].writeback),
7114 /* Use of PC in str is deprecated for ARMv7. */
7115 if (warn_on_deprecated
7117 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7118 as_warn (_("use of PC in this instruction is deprecated"));
7121 if (inst.reloc.type == BFD_RELOC_UNUSED)
7123 /* Prefer + for zero encoded value. */
7124 if (!inst.operands[i].negative)
7125 inst.instruction |= INDEX_UP;
7126 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7131 /* inst.operands[i] was set up by parse_address. Encode it into an
7132 ARM-format mode 3 load or store instruction. Reject forms that
7133 cannot be used with such instructions. If is_t is true, reject
7134 forms that cannot be used with a T instruction (i.e. not
7137 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7139 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7141 inst.error = _("instruction does not accept scaled register index");
7145 encode_arm_addr_mode_common (i, is_t);
7147 if (inst.operands[i].immisreg)
7149 constraint ((inst.operands[i].imm == REG_PC
7150 || inst.operands[i].reg == REG_PC),
7152 inst.instruction |= inst.operands[i].imm;
7153 if (!inst.operands[i].negative)
7154 inst.instruction |= INDEX_UP;
7156 else /* immediate offset in inst.reloc */
7158 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7159 && inst.operands[i].writeback),
7161 inst.instruction |= HWOFFSET_IMM;
7162 if (inst.reloc.type == BFD_RELOC_UNUSED)
7164 /* Prefer + for zero encoded value. */
7165 if (!inst.operands[i].negative)
7166 inst.instruction |= INDEX_UP;
7168 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7173 /* inst.operands[i] was set up by parse_address. Encode it into an
7174 ARM-format instruction. Reject all forms which cannot be encoded
7175 into a coprocessor load/store instruction. If wb_ok is false,
7176 reject use of writeback; if unind_ok is false, reject use of
7177 unindexed addressing. If reloc_override is not 0, use it instead
7178 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7179 (in which case it is preserved). */
7182 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7184 inst.instruction |= inst.operands[i].reg << 16;
7186 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7188 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7190 gas_assert (!inst.operands[i].writeback);
7193 inst.error = _("instruction does not support unindexed addressing");
7196 inst.instruction |= inst.operands[i].imm;
7197 inst.instruction |= INDEX_UP;
7201 if (inst.operands[i].preind)
7202 inst.instruction |= PRE_INDEX;
7204 if (inst.operands[i].writeback)
7206 if (inst.operands[i].reg == REG_PC)
7208 inst.error = _("pc may not be used with write-back");
7213 inst.error = _("instruction does not support writeback");
7216 inst.instruction |= WRITE_BACK;
7220 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7221 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7222 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7223 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
7226 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7228 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
7231 /* Prefer + for zero encoded value. */
7232 if (!inst.operands[i].negative)
7233 inst.instruction |= INDEX_UP;
7238 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7239 Determine whether it can be performed with a move instruction; if
7240 it can, convert inst.instruction to that move instruction and
7241 return TRUE; if it can't, convert inst.instruction to a literal-pool
7242 load and return FALSE. If this is not a valid thing to do in the
7243 current context, set inst.error and return TRUE.
7245 inst.operands[i] describes the destination register. */
7248 move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7253 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7257 if ((inst.instruction & tbit) == 0)
7259 inst.error = _("invalid pseudo operation");
7262 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
7264 inst.error = _("constant expression expected");
7267 if (inst.reloc.exp.X_op == O_constant)
7271 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7273 /* This can be done with a mov(1) instruction. */
7274 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7275 inst.instruction |= inst.reloc.exp.X_add_number;
7281 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7284 /* This can be done with a mov instruction. */
7285 inst.instruction &= LITERAL_MASK;
7286 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7287 inst.instruction |= value & 0xfff;
7291 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7294 /* This can be done with a mvn instruction. */
7295 inst.instruction &= LITERAL_MASK;
7296 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7297 inst.instruction |= value & 0xfff;
7303 if (add_to_lit_pool () == FAIL)
7305 inst.error = _("literal pool insertion failed");
7308 inst.operands[1].reg = REG_PC;
7309 inst.operands[1].isreg = 1;
7310 inst.operands[1].preind = 1;
7311 inst.reloc.pc_rel = 1;
7312 inst.reloc.type = (thumb_p
7313 ? BFD_RELOC_ARM_THUMB_OFFSET
7315 ? BFD_RELOC_ARM_HWLITERAL
7316 : BFD_RELOC_ARM_LITERAL));
7320 /* Functions for instruction encoding, sorted by sub-architecture.
7321 First some generics; their names are taken from the conventional
7322 bit positions for register arguments in ARM format instructions. */
7332 inst.instruction |= inst.operands[0].reg << 12;
7338 inst.instruction |= inst.operands[0].reg << 12;
7339 inst.instruction |= inst.operands[1].reg;
7345 inst.instruction |= inst.operands[0].reg << 12;
7346 inst.instruction |= inst.operands[1].reg << 16;
7352 inst.instruction |= inst.operands[0].reg << 16;
7353 inst.instruction |= inst.operands[1].reg << 12;
7359 unsigned Rn = inst.operands[2].reg;
7360 /* Enforce restrictions on SWP instruction. */
7361 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
7363 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7364 _("Rn must not overlap other operands"));
7366 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7367 if (warn_on_deprecated
7368 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
7369 as_warn (_("swp{b} use is deprecated for this architecture"));
7372 inst.instruction |= inst.operands[0].reg << 12;
7373 inst.instruction |= inst.operands[1].reg;
7374 inst.instruction |= Rn << 16;
7380 inst.instruction |= inst.operands[0].reg << 12;
7381 inst.instruction |= inst.operands[1].reg << 16;
7382 inst.instruction |= inst.operands[2].reg;
7388 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7389 constraint (((inst.reloc.exp.X_op != O_constant
7390 && inst.reloc.exp.X_op != O_illegal)
7391 || inst.reloc.exp.X_add_number != 0),
7393 inst.instruction |= inst.operands[0].reg;
7394 inst.instruction |= inst.operands[1].reg << 12;
7395 inst.instruction |= inst.operands[2].reg << 16;
7401 inst.instruction |= inst.operands[0].imm;
7407 inst.instruction |= inst.operands[0].reg << 12;
7408 encode_arm_cp_address (1, TRUE, TRUE, 0);
7411 /* ARM instructions, in alphabetical order by function name (except
7412 that wrapper functions appear immediately after the function they
7415 /* This is a pseudo-op of the form "adr rd, label" to be converted
7416 into a relative address of the form "add rd, pc, #label-.-8". */
7421 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7423 /* Frag hacking will turn this into a sub instruction if the offset turns
7424 out to be negative. */
7425 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
7426 inst.reloc.pc_rel = 1;
7427 inst.reloc.exp.X_add_number -= 8;
7430 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7431 into a relative address of the form:
7432 add rd, pc, #low(label-.-8)"
7433 add rd, rd, #high(label-.-8)" */
7438 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
7440 /* Frag hacking will turn this into a sub instruction if the offset turns
7441 out to be negative. */
7442 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
7443 inst.reloc.pc_rel = 1;
7444 inst.size = INSN_SIZE * 2;
7445 inst.reloc.exp.X_add_number -= 8;
7451 if (!inst.operands[1].present)
7452 inst.operands[1].reg = inst.operands[0].reg;
7453 inst.instruction |= inst.operands[0].reg << 12;
7454 inst.instruction |= inst.operands[1].reg << 16;
7455 encode_arm_shifter_operand (2);
7461 if (inst.operands[0].present)
7463 constraint ((inst.instruction & 0xf0) != 0x40
7464 && inst.operands[0].imm > 0xf
7465 && inst.operands[0].imm < 0x0,
7466 _("bad barrier type"));
7467 inst.instruction |= inst.operands[0].imm;
7470 inst.instruction |= 0xf;
7476 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7477 constraint (msb > 32, _("bit-field extends past end of register"));
7478 /* The instruction encoding stores the LSB and MSB,
7479 not the LSB and width. */
7480 inst.instruction |= inst.operands[0].reg << 12;
7481 inst.instruction |= inst.operands[1].imm << 7;
7482 inst.instruction |= (msb - 1) << 16;
7490 /* #0 in second position is alternative syntax for bfc, which is
7491 the same instruction but with REG_PC in the Rm field. */
7492 if (!inst.operands[1].isreg)
7493 inst.operands[1].reg = REG_PC;
7495 msb = inst.operands[2].imm + inst.operands[3].imm;
7496 constraint (msb > 32, _("bit-field extends past end of register"));
7497 /* The instruction encoding stores the LSB and MSB,
7498 not the LSB and width. */
7499 inst.instruction |= inst.operands[0].reg << 12;
7500 inst.instruction |= inst.operands[1].reg;
7501 inst.instruction |= inst.operands[2].imm << 7;
7502 inst.instruction |= (msb - 1) << 16;
7508 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7509 _("bit-field extends past end of register"));
7510 inst.instruction |= inst.operands[0].reg << 12;
7511 inst.instruction |= inst.operands[1].reg;
7512 inst.instruction |= inst.operands[2].imm << 7;
7513 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7516 /* ARM V5 breakpoint instruction (argument parse)
7517 BKPT <16 bit unsigned immediate>
7518 Instruction is not conditional.
7519 The bit pattern given in insns[] has the COND_ALWAYS condition,
7520 and it is an error if the caller tried to override that. */
7525 /* Top 12 of 16 bits to bits 19:8. */
7526 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
7528 /* Bottom 4 of 16 bits to bits 3:0. */
7529 inst.instruction |= inst.operands[0].imm & 0xf;
7533 encode_branch (int default_reloc)
7535 if (inst.operands[0].hasreloc)
7537 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7538 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7539 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7540 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7541 ? BFD_RELOC_ARM_PLT32
7542 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
7545 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
7546 inst.reloc.pc_rel = 1;
7553 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7554 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7557 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7564 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7566 if (inst.cond == COND_ALWAYS)
7567 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7569 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7573 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7576 /* ARM V5 branch-link-exchange instruction (argument parse)
7577 BLX <target_addr> ie BLX(1)
7578 BLX{<condition>} <Rm> ie BLX(2)
7579 Unfortunately, there are two different opcodes for this mnemonic.
7580 So, the insns[].value is not used, and the code here zaps values
7581 into inst.instruction.
7582 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7587 if (inst.operands[0].isreg)
7589 /* Arg is a register; the opcode provided by insns[] is correct.
7590 It is not illegal to do "blx pc", just useless. */
7591 if (inst.operands[0].reg == REG_PC)
7592 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7594 inst.instruction |= inst.operands[0].reg;
7598 /* Arg is an address; this instruction cannot be executed
7599 conditionally, and the opcode must be adjusted.
7600 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7601 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7602 constraint (inst.cond != COND_ALWAYS, BAD_COND);
7603 inst.instruction = 0xfa000000;
7604 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
7611 bfd_boolean want_reloc;
7613 if (inst.operands[0].reg == REG_PC)
7614 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7616 inst.instruction |= inst.operands[0].reg;
7617 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7618 it is for ARMv4t or earlier. */
7619 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7620 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7624 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
7629 inst.reloc.type = BFD_RELOC_ARM_V4BX;
7633 /* ARM v5TEJ. Jump to Jazelle code. */
7638 if (inst.operands[0].reg == REG_PC)
7639 as_tsktsk (_("use of r15 in bxj is not really useful"));
7641 inst.instruction |= inst.operands[0].reg;
7644 /* Co-processor data operation:
7645 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7646 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7650 inst.instruction |= inst.operands[0].reg << 8;
7651 inst.instruction |= inst.operands[1].imm << 20;
7652 inst.instruction |= inst.operands[2].reg << 12;
7653 inst.instruction |= inst.operands[3].reg << 16;
7654 inst.instruction |= inst.operands[4].reg;
7655 inst.instruction |= inst.operands[5].imm << 5;
7661 inst.instruction |= inst.operands[0].reg << 16;
7662 encode_arm_shifter_operand (1);
7665 /* Transfer between coprocessor and ARM registers.
7666 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7671 No special properties. */
7678 Rd = inst.operands[2].reg;
7681 if (inst.instruction == 0xee000010
7682 || inst.instruction == 0xfe000010)
7684 reject_bad_reg (Rd);
7687 constraint (Rd == REG_SP, BAD_SP);
7692 if (inst.instruction == 0xe000010)
7693 constraint (Rd == REG_PC, BAD_PC);
7697 inst.instruction |= inst.operands[0].reg << 8;
7698 inst.instruction |= inst.operands[1].imm << 21;
7699 inst.instruction |= Rd << 12;
7700 inst.instruction |= inst.operands[3].reg << 16;
7701 inst.instruction |= inst.operands[4].reg;
7702 inst.instruction |= inst.operands[5].imm << 5;
7705 /* Transfer between coprocessor register and pair of ARM registers.
7706 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7711 Two XScale instructions are special cases of these:
7713 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7714 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7716 Result unpredictable if Rd or Rn is R15. */
7723 Rd = inst.operands[2].reg;
7724 Rn = inst.operands[3].reg;
7728 reject_bad_reg (Rd);
7729 reject_bad_reg (Rn);
7733 constraint (Rd == REG_PC, BAD_PC);
7734 constraint (Rn == REG_PC, BAD_PC);
7737 inst.instruction |= inst.operands[0].reg << 8;
7738 inst.instruction |= inst.operands[1].imm << 4;
7739 inst.instruction |= Rd << 12;
7740 inst.instruction |= Rn << 16;
7741 inst.instruction |= inst.operands[4].reg;
7747 inst.instruction |= inst.operands[0].imm << 6;
7748 if (inst.operands[1].present)
7750 inst.instruction |= CPSI_MMOD;
7751 inst.instruction |= inst.operands[1].imm;
7758 inst.instruction |= inst.operands[0].imm;
7764 unsigned Rd, Rn, Rm;
7766 Rd = inst.operands[0].reg;
7767 Rn = (inst.operands[1].present
7768 ? inst.operands[1].reg : Rd);
7769 Rm = inst.operands[2].reg;
7771 constraint ((Rd == REG_PC), BAD_PC);
7772 constraint ((Rn == REG_PC), BAD_PC);
7773 constraint ((Rm == REG_PC), BAD_PC);
7775 inst.instruction |= Rd << 16;
7776 inst.instruction |= Rn << 0;
7777 inst.instruction |= Rm << 8;
7783 /* There is no IT instruction in ARM mode. We
7784 process it to do the validation as if in
7785 thumb mode, just in case the code gets
7786 assembled for thumb using the unified syntax. */
7791 set_it_insn_type (IT_INSN);
7792 now_it.mask = (inst.instruction & 0xf) | 0x10;
7793 now_it.cc = inst.operands[0].imm;
7800 int base_reg = inst.operands[0].reg;
7801 int range = inst.operands[1].imm;
7803 inst.instruction |= base_reg << 16;
7804 inst.instruction |= range;
7806 if (inst.operands[1].writeback)
7807 inst.instruction |= LDM_TYPE_2_OR_3;
7809 if (inst.operands[0].writeback)
7811 inst.instruction |= WRITE_BACK;
7812 /* Check for unpredictable uses of writeback. */
7813 if (inst.instruction & LOAD_BIT)
7815 /* Not allowed in LDM type 2. */
7816 if ((inst.instruction & LDM_TYPE_2_OR_3)
7817 && ((range & (1 << REG_PC)) == 0))
7818 as_warn (_("writeback of base register is UNPREDICTABLE"));
7819 /* Only allowed if base reg not in list for other types. */
7820 else if (range & (1 << base_reg))
7821 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7825 /* Not allowed for type 2. */
7826 if (inst.instruction & LDM_TYPE_2_OR_3)
7827 as_warn (_("writeback of base register is UNPREDICTABLE"));
7828 /* Only allowed if base reg not in list, or first in list. */
7829 else if ((range & (1 << base_reg))
7830 && (range & ((1 << base_reg) - 1)))
7831 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7836 /* ARMv5TE load-consecutive (argument parse)
7845 constraint (inst.operands[0].reg % 2 != 0,
7846 _("first transfer register must be even"));
7847 constraint (inst.operands[1].present
7848 && inst.operands[1].reg != inst.operands[0].reg + 1,
7849 _("can only transfer two consecutive registers"));
7850 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7851 constraint (!inst.operands[2].isreg, _("'[' expected"));
7853 if (!inst.operands[1].present)
7854 inst.operands[1].reg = inst.operands[0].reg + 1;
7856 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7857 register and the first register written; we have to diagnose
7858 overlap between the base and the second register written here. */
7860 if (inst.operands[2].reg == inst.operands[1].reg
7861 && (inst.operands[2].writeback || inst.operands[2].postind))
7862 as_warn (_("base register written back, and overlaps "
7863 "second transfer register"));
7865 if (!(inst.instruction & V4_STR_BIT))
7867 /* For an index-register load, the index register must not overlap the
7868 destination (even if not write-back). */
7869 if (inst.operands[2].immisreg
7870 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
7871 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
7872 as_warn (_("index register overlaps transfer register"));
7874 inst.instruction |= inst.operands[0].reg << 12;
7875 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
7881 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
7882 || inst.operands[1].postind || inst.operands[1].writeback
7883 || inst.operands[1].immisreg || inst.operands[1].shifted
7884 || inst.operands[1].negative
7885 /* This can arise if the programmer has written
7887 or if they have mistakenly used a register name as the last
7890 It is very difficult to distinguish between these two cases
7891 because "rX" might actually be a label. ie the register
7892 name has been occluded by a symbol of the same name. So we
7893 just generate a general 'bad addressing mode' type error
7894 message and leave it up to the programmer to discover the
7895 true cause and fix their mistake. */
7896 || (inst.operands[1].reg == REG_PC),
7899 constraint (inst.reloc.exp.X_op != O_constant
7900 || inst.reloc.exp.X_add_number != 0,
7901 _("offset must be zero in ARM encoding"));
7903 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
7905 inst.instruction |= inst.operands[0].reg << 12;
7906 inst.instruction |= inst.operands[1].reg << 16;
7907 inst.reloc.type = BFD_RELOC_UNUSED;
7913 constraint (inst.operands[0].reg % 2 != 0,
7914 _("even register required"));
7915 constraint (inst.operands[1].present
7916 && inst.operands[1].reg != inst.operands[0].reg + 1,
7917 _("can only load two consecutive registers"));
7918 /* If op 1 were present and equal to PC, this function wouldn't
7919 have been called in the first place. */
7920 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
7922 inst.instruction |= inst.operands[0].reg << 12;
7923 inst.instruction |= inst.operands[2].reg << 16;
7926 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
7927 which is not a multiple of four is UNPREDICTABLE. */
7929 check_ldr_r15_aligned (void)
7931 constraint (!(inst.operands[1].immisreg)
7932 && (inst.operands[0].reg == REG_PC
7933 && inst.operands[1].reg == REG_PC
7934 && (inst.reloc.exp.X_add_number & 0x3)),
7935 _("ldr to register 15 must be 4-byte alligned"));
7941 inst.instruction |= inst.operands[0].reg << 12;
7942 if (!inst.operands[1].isreg)
7943 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
7945 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
7946 check_ldr_r15_aligned ();
7952 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7954 if (inst.operands[1].preind)
7956 constraint (inst.reloc.exp.X_op != O_constant
7957 || inst.reloc.exp.X_add_number != 0,
7958 _("this instruction requires a post-indexed address"));
7960 inst.operands[1].preind = 0;
7961 inst.operands[1].postind = 1;
7962 inst.operands[1].writeback = 1;
7964 inst.instruction |= inst.operands[0].reg << 12;
7965 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
7968 /* Halfword and signed-byte load/store operations. */
7973 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
7974 inst.instruction |= inst.operands[0].reg << 12;
7975 if (!inst.operands[1].isreg)
7976 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
7978 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
7984 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7986 if (inst.operands[1].preind)
7988 constraint (inst.reloc.exp.X_op != O_constant
7989 || inst.reloc.exp.X_add_number != 0,
7990 _("this instruction requires a post-indexed address"));
7992 inst.operands[1].preind = 0;
7993 inst.operands[1].postind = 1;
7994 inst.operands[1].writeback = 1;
7996 inst.instruction |= inst.operands[0].reg << 12;
7997 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8000 /* Co-processor register load/store.
8001 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8005 inst.instruction |= inst.operands[0].reg << 8;
8006 inst.instruction |= inst.operands[1].reg << 12;
8007 encode_arm_cp_address (2, TRUE, TRUE, 0);
8013 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8014 if (inst.operands[0].reg == inst.operands[1].reg
8015 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8016 && !(inst.instruction & 0x00400000))
8017 as_tsktsk (_("Rd and Rm should be different in mla"));
8019 inst.instruction |= inst.operands[0].reg << 16;
8020 inst.instruction |= inst.operands[1].reg;
8021 inst.instruction |= inst.operands[2].reg << 8;
8022 inst.instruction |= inst.operands[3].reg << 12;
8028 inst.instruction |= inst.operands[0].reg << 12;
8029 encode_arm_shifter_operand (1);
8032 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8039 top = (inst.instruction & 0x00400000) != 0;
8040 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8041 _(":lower16: not allowed this instruction"));
8042 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8043 _(":upper16: not allowed instruction"));
8044 inst.instruction |= inst.operands[0].reg << 12;
8045 if (inst.reloc.type == BFD_RELOC_UNUSED)
8047 imm = inst.reloc.exp.X_add_number;
8048 /* The value is in two pieces: 0:11, 16:19. */
8049 inst.instruction |= (imm & 0x00000fff);
8050 inst.instruction |= (imm & 0x0000f000) << 4;
8054 static void do_vfp_nsyn_opcode (const char *);
8057 do_vfp_nsyn_mrs (void)
8059 if (inst.operands[0].isvec)
8061 if (inst.operands[1].reg != 1)
8062 first_error (_("operand 1 must be FPSCR"));
8063 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8064 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8065 do_vfp_nsyn_opcode ("fmstat");
8067 else if (inst.operands[1].isvec)
8068 do_vfp_nsyn_opcode ("fmrx");
8076 do_vfp_nsyn_msr (void)
8078 if (inst.operands[0].isvec)
8079 do_vfp_nsyn_opcode ("fmxr");
8089 unsigned Rt = inst.operands[0].reg;
8091 if (thumb_mode && inst.operands[0].reg == REG_SP)
8093 inst.error = BAD_SP;
8097 /* APSR_ sets isvec. All other refs to PC are illegal. */
8098 if (!inst.operands[0].isvec && inst.operands[0].reg == REG_PC)
8100 inst.error = BAD_PC;
8104 if (inst.operands[1].reg != 1)
8105 first_error (_("operand 1 must be FPSCR"));
8107 inst.instruction |= (Rt << 12);
8113 unsigned Rt = inst.operands[1].reg;
8116 reject_bad_reg (Rt);
8117 else if (Rt == REG_PC)
8119 inst.error = BAD_PC;
8123 if (inst.operands[0].reg != 1)
8124 first_error (_("operand 0 must be FPSCR"));
8126 inst.instruction |= (Rt << 12);
8134 if (do_vfp_nsyn_mrs () == SUCCESS)
8137 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8138 inst.instruction |= inst.operands[0].reg << 12;
8140 if (inst.operands[1].isreg)
8142 br = inst.operands[1].reg;
8143 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8144 as_bad (_("bad register for mrs"));
8148 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8149 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8151 _("'APSR', 'CPSR' or 'SPSR' expected"));
8152 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8155 inst.instruction |= br;
8158 /* Two possible forms:
8159 "{C|S}PSR_<field>, Rm",
8160 "{C|S}PSR_f, #expression". */
8165 if (do_vfp_nsyn_msr () == SUCCESS)
8168 inst.instruction |= inst.operands[0].imm;
8169 if (inst.operands[1].isreg)
8170 inst.instruction |= inst.operands[1].reg;
8173 inst.instruction |= INST_IMMEDIATE;
8174 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8175 inst.reloc.pc_rel = 0;
8182 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8184 if (!inst.operands[2].present)
8185 inst.operands[2].reg = inst.operands[0].reg;
8186 inst.instruction |= inst.operands[0].reg << 16;
8187 inst.instruction |= inst.operands[1].reg;
8188 inst.instruction |= inst.operands[2].reg << 8;
8190 if (inst.operands[0].reg == inst.operands[1].reg
8191 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8192 as_tsktsk (_("Rd and Rm should be different in mul"));
8195 /* Long Multiply Parser
8196 UMULL RdLo, RdHi, Rm, Rs
8197 SMULL RdLo, RdHi, Rm, Rs
8198 UMLAL RdLo, RdHi, Rm, Rs
8199 SMLAL RdLo, RdHi, Rm, Rs. */
8204 inst.instruction |= inst.operands[0].reg << 12;
8205 inst.instruction |= inst.operands[1].reg << 16;
8206 inst.instruction |= inst.operands[2].reg;
8207 inst.instruction |= inst.operands[3].reg << 8;
8209 /* rdhi and rdlo must be different. */
8210 if (inst.operands[0].reg == inst.operands[1].reg)
8211 as_tsktsk (_("rdhi and rdlo must be different"));
8213 /* rdhi, rdlo and rm must all be different before armv6. */
8214 if ((inst.operands[0].reg == inst.operands[2].reg
8215 || inst.operands[1].reg == inst.operands[2].reg)
8216 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8217 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8223 if (inst.operands[0].present
8224 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
8226 /* Architectural NOP hints are CPSR sets with no bits selected. */
8227 inst.instruction &= 0xf0000000;
8228 inst.instruction |= 0x0320f000;
8229 if (inst.operands[0].present)
8230 inst.instruction |= inst.operands[0].imm;
8234 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8235 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8236 Condition defaults to COND_ALWAYS.
8237 Error if Rd, Rn or Rm are R15. */
8242 inst.instruction |= inst.operands[0].reg << 12;
8243 inst.instruction |= inst.operands[1].reg << 16;
8244 inst.instruction |= inst.operands[2].reg;
8245 if (inst.operands[3].present)
8246 encode_arm_shift (3);
8249 /* ARM V6 PKHTB (Argument Parse). */
8254 if (!inst.operands[3].present)
8256 /* If the shift specifier is omitted, turn the instruction
8257 into pkhbt rd, rm, rn. */
8258 inst.instruction &= 0xfff00010;
8259 inst.instruction |= inst.operands[0].reg << 12;
8260 inst.instruction |= inst.operands[1].reg;
8261 inst.instruction |= inst.operands[2].reg << 16;
8265 inst.instruction |= inst.operands[0].reg << 12;
8266 inst.instruction |= inst.operands[1].reg << 16;
8267 inst.instruction |= inst.operands[2].reg;
8268 encode_arm_shift (3);
8272 /* ARMv5TE: Preload-Cache
8273 MP Extensions: Preload for write
8277 Syntactically, like LDR with B=1, W=0, L=1. */
8282 constraint (!inst.operands[0].isreg,
8283 _("'[' expected after PLD mnemonic"));
8284 constraint (inst.operands[0].postind,
8285 _("post-indexed expression used in preload instruction"));
8286 constraint (inst.operands[0].writeback,
8287 _("writeback used in preload instruction"));
8288 constraint (!inst.operands[0].preind,
8289 _("unindexed addressing used in preload instruction"));
8290 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8293 /* ARMv7: PLI <addr_mode> */
8297 constraint (!inst.operands[0].isreg,
8298 _("'[' expected after PLI mnemonic"));
8299 constraint (inst.operands[0].postind,
8300 _("post-indexed expression used in preload instruction"));
8301 constraint (inst.operands[0].writeback,
8302 _("writeback used in preload instruction"));
8303 constraint (!inst.operands[0].preind,
8304 _("unindexed addressing used in preload instruction"));
8305 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8306 inst.instruction &= ~PRE_INDEX;
8312 inst.operands[1] = inst.operands[0];
8313 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8314 inst.operands[0].isreg = 1;
8315 inst.operands[0].writeback = 1;
8316 inst.operands[0].reg = REG_SP;
8320 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8321 word at the specified address and the following word
8323 Unconditionally executed.
8324 Error if Rn is R15. */
8329 inst.instruction |= inst.operands[0].reg << 16;
8330 if (inst.operands[0].writeback)
8331 inst.instruction |= WRITE_BACK;
8334 /* ARM V6 ssat (argument parse). */
8339 inst.instruction |= inst.operands[0].reg << 12;
8340 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8341 inst.instruction |= inst.operands[2].reg;
8343 if (inst.operands[3].present)
8344 encode_arm_shift (3);
8347 /* ARM V6 usat (argument parse). */
8352 inst.instruction |= inst.operands[0].reg << 12;
8353 inst.instruction |= inst.operands[1].imm << 16;
8354 inst.instruction |= inst.operands[2].reg;
8356 if (inst.operands[3].present)
8357 encode_arm_shift (3);
8360 /* ARM V6 ssat16 (argument parse). */
8365 inst.instruction |= inst.operands[0].reg << 12;
8366 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8367 inst.instruction |= inst.operands[2].reg;
8373 inst.instruction |= inst.operands[0].reg << 12;
8374 inst.instruction |= inst.operands[1].imm << 16;
8375 inst.instruction |= inst.operands[2].reg;
8378 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8379 preserving the other bits.
8381 setend <endian_specifier>, where <endian_specifier> is either
8387 if (inst.operands[0].imm)
8388 inst.instruction |= 0x200;
8394 unsigned int Rm = (inst.operands[1].present
8395 ? inst.operands[1].reg
8396 : inst.operands[0].reg);
8398 inst.instruction |= inst.operands[0].reg << 12;
8399 inst.instruction |= Rm;
8400 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
8402 inst.instruction |= inst.operands[2].reg << 8;
8403 inst.instruction |= SHIFT_BY_REG;
8404 /* PR 12854: Error on extraneous shifts. */
8405 constraint (inst.operands[2].shifted,
8406 _("extraneous shift as part of operand to shift insn"));
8409 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
8415 inst.reloc.type = BFD_RELOC_ARM_SMC;
8416 inst.reloc.pc_rel = 0;
8422 inst.reloc.type = BFD_RELOC_ARM_HVC;
8423 inst.reloc.pc_rel = 0;
8429 inst.reloc.type = BFD_RELOC_ARM_SWI;
8430 inst.reloc.pc_rel = 0;
8433 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8434 SMLAxy{cond} Rd,Rm,Rs,Rn
8435 SMLAWy{cond} Rd,Rm,Rs,Rn
8436 Error if any register is R15. */
8441 inst.instruction |= inst.operands[0].reg << 16;
8442 inst.instruction |= inst.operands[1].reg;
8443 inst.instruction |= inst.operands[2].reg << 8;
8444 inst.instruction |= inst.operands[3].reg << 12;
8447 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8448 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8449 Error if any register is R15.
8450 Warning if Rdlo == Rdhi. */
8455 inst.instruction |= inst.operands[0].reg << 12;
8456 inst.instruction |= inst.operands[1].reg << 16;
8457 inst.instruction |= inst.operands[2].reg;
8458 inst.instruction |= inst.operands[3].reg << 8;
8460 if (inst.operands[0].reg == inst.operands[1].reg)
8461 as_tsktsk (_("rdhi and rdlo must be different"));
8464 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8465 SMULxy{cond} Rd,Rm,Rs
8466 Error if any register is R15. */
8471 inst.instruction |= inst.operands[0].reg << 16;
8472 inst.instruction |= inst.operands[1].reg;
8473 inst.instruction |= inst.operands[2].reg << 8;
8476 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8477 the same for both ARM and Thumb-2. */
8484 if (inst.operands[0].present)
8486 reg = inst.operands[0].reg;
8487 constraint (reg != REG_SP, _("SRS base register must be r13"));
8492 inst.instruction |= reg << 16;
8493 inst.instruction |= inst.operands[1].imm;
8494 if (inst.operands[0].writeback || inst.operands[1].writeback)
8495 inst.instruction |= WRITE_BACK;
8498 /* ARM V6 strex (argument parse). */
8503 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8504 || inst.operands[2].postind || inst.operands[2].writeback
8505 || inst.operands[2].immisreg || inst.operands[2].shifted
8506 || inst.operands[2].negative
8507 /* See comment in do_ldrex(). */
8508 || (inst.operands[2].reg == REG_PC),
8511 constraint (inst.operands[0].reg == inst.operands[1].reg
8512 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8514 constraint (inst.reloc.exp.X_op != O_constant
8515 || inst.reloc.exp.X_add_number != 0,
8516 _("offset must be zero in ARM encoding"));
8518 inst.instruction |= inst.operands[0].reg << 12;
8519 inst.instruction |= inst.operands[1].reg;
8520 inst.instruction |= inst.operands[2].reg << 16;
8521 inst.reloc.type = BFD_RELOC_UNUSED;
8527 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8528 || inst.operands[2].postind || inst.operands[2].writeback
8529 || inst.operands[2].immisreg || inst.operands[2].shifted
8530 || inst.operands[2].negative,
8533 constraint (inst.operands[0].reg == inst.operands[1].reg
8534 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8542 constraint (inst.operands[1].reg % 2 != 0,
8543 _("even register required"));
8544 constraint (inst.operands[2].present
8545 && inst.operands[2].reg != inst.operands[1].reg + 1,
8546 _("can only store two consecutive registers"));
8547 /* If op 2 were present and equal to PC, this function wouldn't
8548 have been called in the first place. */
8549 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
8551 constraint (inst.operands[0].reg == inst.operands[1].reg
8552 || inst.operands[0].reg == inst.operands[1].reg + 1
8553 || inst.operands[0].reg == inst.operands[3].reg,
8556 inst.instruction |= inst.operands[0].reg << 12;
8557 inst.instruction |= inst.operands[1].reg;
8558 inst.instruction |= inst.operands[3].reg << 16;
8561 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8562 extends it to 32-bits, and adds the result to a value in another
8563 register. You can specify a rotation by 0, 8, 16, or 24 bits
8564 before extracting the 16-bit value.
8565 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8566 Condition defaults to COND_ALWAYS.
8567 Error if any register uses R15. */
8572 inst.instruction |= inst.operands[0].reg << 12;
8573 inst.instruction |= inst.operands[1].reg << 16;
8574 inst.instruction |= inst.operands[2].reg;
8575 inst.instruction |= inst.operands[3].imm << 10;
8580 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8581 Condition defaults to COND_ALWAYS.
8582 Error if any register uses R15. */
8587 inst.instruction |= inst.operands[0].reg << 12;
8588 inst.instruction |= inst.operands[1].reg;
8589 inst.instruction |= inst.operands[2].imm << 10;
8592 /* VFP instructions. In a logical order: SP variant first, monad
8593 before dyad, arithmetic then move then load/store. */
8596 do_vfp_sp_monadic (void)
8598 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8599 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8603 do_vfp_sp_dyadic (void)
8605 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8606 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8607 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8611 do_vfp_sp_compare_z (void)
8613 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8617 do_vfp_dp_sp_cvt (void)
8619 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8620 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
8624 do_vfp_sp_dp_cvt (void)
8626 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8627 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8631 do_vfp_reg_from_sp (void)
8633 inst.instruction |= inst.operands[0].reg << 12;
8634 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8638 do_vfp_reg2_from_sp2 (void)
8640 constraint (inst.operands[2].imm != 2,
8641 _("only two consecutive VFP SP registers allowed here"));
8642 inst.instruction |= inst.operands[0].reg << 12;
8643 inst.instruction |= inst.operands[1].reg << 16;
8644 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
8648 do_vfp_sp_from_reg (void)
8650 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
8651 inst.instruction |= inst.operands[1].reg << 12;
8655 do_vfp_sp2_from_reg2 (void)
8657 constraint (inst.operands[0].imm != 2,
8658 _("only two consecutive VFP SP registers allowed here"));
8659 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
8660 inst.instruction |= inst.operands[1].reg << 12;
8661 inst.instruction |= inst.operands[2].reg << 16;
8665 do_vfp_sp_ldst (void)
8667 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8668 encode_arm_cp_address (1, FALSE, TRUE, 0);
8672 do_vfp_dp_ldst (void)
8674 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8675 encode_arm_cp_address (1, FALSE, TRUE, 0);
8680 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
8682 if (inst.operands[0].writeback)
8683 inst.instruction |= WRITE_BACK;
8685 constraint (ldstm_type != VFP_LDSTMIA,
8686 _("this addressing mode requires base-register writeback"));
8687 inst.instruction |= inst.operands[0].reg << 16;
8688 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
8689 inst.instruction |= inst.operands[1].imm;
8693 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
8697 if (inst.operands[0].writeback)
8698 inst.instruction |= WRITE_BACK;
8700 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8701 _("this addressing mode requires base-register writeback"));
8703 inst.instruction |= inst.operands[0].reg << 16;
8704 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8706 count = inst.operands[1].imm << 1;
8707 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8710 inst.instruction |= count;
8714 do_vfp_sp_ldstmia (void)
8716 vfp_sp_ldstm (VFP_LDSTMIA);
8720 do_vfp_sp_ldstmdb (void)
8722 vfp_sp_ldstm (VFP_LDSTMDB);
8726 do_vfp_dp_ldstmia (void)
8728 vfp_dp_ldstm (VFP_LDSTMIA);
8732 do_vfp_dp_ldstmdb (void)
8734 vfp_dp_ldstm (VFP_LDSTMDB);
8738 do_vfp_xp_ldstmia (void)
8740 vfp_dp_ldstm (VFP_LDSTMIAX);
8744 do_vfp_xp_ldstmdb (void)
8746 vfp_dp_ldstm (VFP_LDSTMDBX);
8750 do_vfp_dp_rd_rm (void)
8752 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8753 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8757 do_vfp_dp_rn_rd (void)
8759 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8760 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8764 do_vfp_dp_rd_rn (void)
8766 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8767 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8771 do_vfp_dp_rd_rn_rm (void)
8773 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8774 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8775 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8781 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8785 do_vfp_dp_rm_rd_rn (void)
8787 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8788 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8789 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8792 /* VFPv3 instructions. */
8794 do_vfp_sp_const (void)
8796 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8797 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8798 inst.instruction |= (inst.operands[1].imm & 0x0f);
8802 do_vfp_dp_const (void)
8804 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8805 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8806 inst.instruction |= (inst.operands[1].imm & 0x0f);
8810 vfp_conv (int srcsize)
8812 int immbits = srcsize - inst.operands[1].imm;
8814 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8816 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8817 i.e. immbits must be in range 0 - 16. */
8818 inst.error = _("immediate value out of range, expected range [0, 16]");
8821 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
8823 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8824 i.e. immbits must be in range 0 - 31. */
8825 inst.error = _("immediate value out of range, expected range [1, 32]");
8829 inst.instruction |= (immbits & 1) << 5;
8830 inst.instruction |= (immbits >> 1);
8834 do_vfp_sp_conv_16 (void)
8836 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8841 do_vfp_dp_conv_16 (void)
8843 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8848 do_vfp_sp_conv_32 (void)
8850 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8855 do_vfp_dp_conv_32 (void)
8857 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8861 /* FPA instructions. Also in a logical order. */
8866 inst.instruction |= inst.operands[0].reg << 16;
8867 inst.instruction |= inst.operands[1].reg;
8871 do_fpa_ldmstm (void)
8873 inst.instruction |= inst.operands[0].reg << 12;
8874 switch (inst.operands[1].imm)
8876 case 1: inst.instruction |= CP_T_X; break;
8877 case 2: inst.instruction |= CP_T_Y; break;
8878 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
8883 if (inst.instruction & (PRE_INDEX | INDEX_UP))
8885 /* The instruction specified "ea" or "fd", so we can only accept
8886 [Rn]{!}. The instruction does not really support stacking or
8887 unstacking, so we have to emulate these by setting appropriate
8888 bits and offsets. */
8889 constraint (inst.reloc.exp.X_op != O_constant
8890 || inst.reloc.exp.X_add_number != 0,
8891 _("this instruction does not support indexing"));
8893 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
8894 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
8896 if (!(inst.instruction & INDEX_UP))
8897 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
8899 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
8901 inst.operands[2].preind = 0;
8902 inst.operands[2].postind = 1;
8906 encode_arm_cp_address (2, TRUE, TRUE, 0);
8909 /* iWMMXt instructions: strictly in alphabetical order. */
8912 do_iwmmxt_tandorc (void)
8914 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
8918 do_iwmmxt_textrc (void)
8920 inst.instruction |= inst.operands[0].reg << 12;
8921 inst.instruction |= inst.operands[1].imm;
8925 do_iwmmxt_textrm (void)
8927 inst.instruction |= inst.operands[0].reg << 12;
8928 inst.instruction |= inst.operands[1].reg << 16;
8929 inst.instruction |= inst.operands[2].imm;
8933 do_iwmmxt_tinsr (void)
8935 inst.instruction |= inst.operands[0].reg << 16;
8936 inst.instruction |= inst.operands[1].reg << 12;
8937 inst.instruction |= inst.operands[2].imm;
8941 do_iwmmxt_tmia (void)
8943 inst.instruction |= inst.operands[0].reg << 5;
8944 inst.instruction |= inst.operands[1].reg;
8945 inst.instruction |= inst.operands[2].reg << 12;
8949 do_iwmmxt_waligni (void)
8951 inst.instruction |= inst.operands[0].reg << 12;
8952 inst.instruction |= inst.operands[1].reg << 16;
8953 inst.instruction |= inst.operands[2].reg;
8954 inst.instruction |= inst.operands[3].imm << 20;
8958 do_iwmmxt_wmerge (void)
8960 inst.instruction |= inst.operands[0].reg << 12;
8961 inst.instruction |= inst.operands[1].reg << 16;
8962 inst.instruction |= inst.operands[2].reg;
8963 inst.instruction |= inst.operands[3].imm << 21;
8967 do_iwmmxt_wmov (void)
8969 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8970 inst.instruction |= inst.operands[0].reg << 12;
8971 inst.instruction |= inst.operands[1].reg << 16;
8972 inst.instruction |= inst.operands[1].reg;
8976 do_iwmmxt_wldstbh (void)
8979 inst.instruction |= inst.operands[0].reg << 12;
8981 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
8983 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
8984 encode_arm_cp_address (1, TRUE, FALSE, reloc);
8988 do_iwmmxt_wldstw (void)
8990 /* RIWR_RIWC clears .isreg for a control register. */
8991 if (!inst.operands[0].isreg)
8993 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8994 inst.instruction |= 0xf0000000;
8997 inst.instruction |= inst.operands[0].reg << 12;
8998 encode_arm_cp_address (1, TRUE, TRUE, 0);
9002 do_iwmmxt_wldstd (void)
9004 inst.instruction |= inst.operands[0].reg << 12;
9005 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9006 && inst.operands[1].immisreg)
9008 inst.instruction &= ~0x1a000ff;
9009 inst.instruction |= (0xf << 28);
9010 if (inst.operands[1].preind)
9011 inst.instruction |= PRE_INDEX;
9012 if (!inst.operands[1].negative)
9013 inst.instruction |= INDEX_UP;
9014 if (inst.operands[1].writeback)
9015 inst.instruction |= WRITE_BACK;
9016 inst.instruction |= inst.operands[1].reg << 16;
9017 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9018 inst.instruction |= inst.operands[1].imm;
9021 encode_arm_cp_address (1, TRUE, FALSE, 0);
9025 do_iwmmxt_wshufh (void)
9027 inst.instruction |= inst.operands[0].reg << 12;
9028 inst.instruction |= inst.operands[1].reg << 16;
9029 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9030 inst.instruction |= (inst.operands[2].imm & 0x0f);
9034 do_iwmmxt_wzero (void)
9036 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9037 inst.instruction |= inst.operands[0].reg;
9038 inst.instruction |= inst.operands[0].reg << 12;
9039 inst.instruction |= inst.operands[0].reg << 16;
9043 do_iwmmxt_wrwrwr_or_imm5 (void)
9045 if (inst.operands[2].isreg)
9048 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9049 _("immediate operand requires iWMMXt2"));
9051 if (inst.operands[2].imm == 0)
9053 switch ((inst.instruction >> 20) & 0xf)
9059 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9060 inst.operands[2].imm = 16;
9061 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9067 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9068 inst.operands[2].imm = 32;
9069 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9076 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9078 wrn = (inst.instruction >> 16) & 0xf;
9079 inst.instruction &= 0xff0fff0f;
9080 inst.instruction |= wrn;
9081 /* Bail out here; the instruction is now assembled. */
9086 /* Map 32 -> 0, etc. */
9087 inst.operands[2].imm &= 0x1f;
9088 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9092 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9093 operations first, then control, shift, and load/store. */
9095 /* Insns like "foo X,Y,Z". */
9098 do_mav_triple (void)
9100 inst.instruction |= inst.operands[0].reg << 16;
9101 inst.instruction |= inst.operands[1].reg;
9102 inst.instruction |= inst.operands[2].reg << 12;
9105 /* Insns like "foo W,X,Y,Z".
9106 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9111 inst.instruction |= inst.operands[0].reg << 5;
9112 inst.instruction |= inst.operands[1].reg << 12;
9113 inst.instruction |= inst.operands[2].reg << 16;
9114 inst.instruction |= inst.operands[3].reg;
9117 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9121 inst.instruction |= inst.operands[1].reg << 12;
9124 /* Maverick shift immediate instructions.
9125 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9126 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9131 int imm = inst.operands[2].imm;
9133 inst.instruction |= inst.operands[0].reg << 12;
9134 inst.instruction |= inst.operands[1].reg << 16;
9136 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9137 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9138 Bit 4 should be 0. */
9139 imm = (imm & 0xf) | ((imm & 0x70) << 1);
9141 inst.instruction |= imm;
9144 /* XScale instructions. Also sorted arithmetic before move. */
9146 /* Xscale multiply-accumulate (argument parse)
9149 MIAxycc acc0,Rm,Rs. */
9154 inst.instruction |= inst.operands[1].reg;
9155 inst.instruction |= inst.operands[2].reg << 12;
9158 /* Xscale move-accumulator-register (argument parse)
9160 MARcc acc0,RdLo,RdHi. */
9165 inst.instruction |= inst.operands[1].reg << 12;
9166 inst.instruction |= inst.operands[2].reg << 16;
9169 /* Xscale move-register-accumulator (argument parse)
9171 MRAcc RdLo,RdHi,acc0. */
9176 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9177 inst.instruction |= inst.operands[0].reg << 12;
9178 inst.instruction |= inst.operands[1].reg << 16;
9181 /* Encoding functions relevant only to Thumb. */
9183 /* inst.operands[i] is a shifted-register operand; encode
9184 it into inst.instruction in the format used by Thumb32. */
9187 encode_thumb32_shifted_operand (int i)
9189 unsigned int value = inst.reloc.exp.X_add_number;
9190 unsigned int shift = inst.operands[i].shift_kind;
9192 constraint (inst.operands[i].immisreg,
9193 _("shift by register not allowed in thumb mode"));
9194 inst.instruction |= inst.operands[i].reg;
9195 if (shift == SHIFT_RRX)
9196 inst.instruction |= SHIFT_ROR << 4;
9199 constraint (inst.reloc.exp.X_op != O_constant,
9200 _("expression too complex"));
9202 constraint (value > 32
9203 || (value == 32 && (shift == SHIFT_LSL
9204 || shift == SHIFT_ROR)),
9205 _("shift expression is too large"));
9209 else if (value == 32)
9212 inst.instruction |= shift << 4;
9213 inst.instruction |= (value & 0x1c) << 10;
9214 inst.instruction |= (value & 0x03) << 6;
9219 /* inst.operands[i] was set up by parse_address. Encode it into a
9220 Thumb32 format load or store instruction. Reject forms that cannot
9221 be used with such instructions. If is_t is true, reject forms that
9222 cannot be used with a T instruction; if is_d is true, reject forms
9223 that cannot be used with a D instruction. If it is a store insn,
9227 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9229 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
9231 constraint (!inst.operands[i].isreg,
9232 _("Instruction does not support =N addresses"));
9234 inst.instruction |= inst.operands[i].reg << 16;
9235 if (inst.operands[i].immisreg)
9237 constraint (is_pc, BAD_PC_ADDRESSING);
9238 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9239 constraint (inst.operands[i].negative,
9240 _("Thumb does not support negative register indexing"));
9241 constraint (inst.operands[i].postind,
9242 _("Thumb does not support register post-indexing"));
9243 constraint (inst.operands[i].writeback,
9244 _("Thumb does not support register indexing with writeback"));
9245 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9246 _("Thumb supports only LSL in shifted register indexing"));
9248 inst.instruction |= inst.operands[i].imm;
9249 if (inst.operands[i].shifted)
9251 constraint (inst.reloc.exp.X_op != O_constant,
9252 _("expression too complex"));
9253 constraint (inst.reloc.exp.X_add_number < 0
9254 || inst.reloc.exp.X_add_number > 3,
9255 _("shift out of range"));
9256 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9258 inst.reloc.type = BFD_RELOC_UNUSED;
9260 else if (inst.operands[i].preind)
9262 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
9263 constraint (is_t && inst.operands[i].writeback,
9264 _("cannot use writeback with this instruction"));
9265 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0)
9266 && !inst.reloc.pc_rel, BAD_PC_ADDRESSING);
9270 inst.instruction |= 0x01000000;
9271 if (inst.operands[i].writeback)
9272 inst.instruction |= 0x00200000;
9276 inst.instruction |= 0x00000c00;
9277 if (inst.operands[i].writeback)
9278 inst.instruction |= 0x00000100;
9280 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9282 else if (inst.operands[i].postind)
9284 gas_assert (inst.operands[i].writeback);
9285 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9286 constraint (is_t, _("cannot use post-indexing with this instruction"));
9289 inst.instruction |= 0x00200000;
9291 inst.instruction |= 0x00000900;
9292 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9294 else /* unindexed - only for coprocessor */
9295 inst.error = _("instruction does not accept unindexed addressing");
9298 /* Table of Thumb instructions which exist in both 16- and 32-bit
9299 encodings (the latter only in post-V6T2 cores). The index is the
9300 value used in the insns table below. When there is more than one
9301 possible 16-bit encoding for the instruction, this table always
9303 Also contains several pseudo-instructions used during relaxation. */
9304 #define T16_32_TAB \
9305 X(_adc, 4140, eb400000), \
9306 X(_adcs, 4140, eb500000), \
9307 X(_add, 1c00, eb000000), \
9308 X(_adds, 1c00, eb100000), \
9309 X(_addi, 0000, f1000000), \
9310 X(_addis, 0000, f1100000), \
9311 X(_add_pc,000f, f20f0000), \
9312 X(_add_sp,000d, f10d0000), \
9313 X(_adr, 000f, f20f0000), \
9314 X(_and, 4000, ea000000), \
9315 X(_ands, 4000, ea100000), \
9316 X(_asr, 1000, fa40f000), \
9317 X(_asrs, 1000, fa50f000), \
9318 X(_b, e000, f000b000), \
9319 X(_bcond, d000, f0008000), \
9320 X(_bic, 4380, ea200000), \
9321 X(_bics, 4380, ea300000), \
9322 X(_cmn, 42c0, eb100f00), \
9323 X(_cmp, 2800, ebb00f00), \
9324 X(_cpsie, b660, f3af8400), \
9325 X(_cpsid, b670, f3af8600), \
9326 X(_cpy, 4600, ea4f0000), \
9327 X(_dec_sp,80dd, f1ad0d00), \
9328 X(_eor, 4040, ea800000), \
9329 X(_eors, 4040, ea900000), \
9330 X(_inc_sp,00dd, f10d0d00), \
9331 X(_ldmia, c800, e8900000), \
9332 X(_ldr, 6800, f8500000), \
9333 X(_ldrb, 7800, f8100000), \
9334 X(_ldrh, 8800, f8300000), \
9335 X(_ldrsb, 5600, f9100000), \
9336 X(_ldrsh, 5e00, f9300000), \
9337 X(_ldr_pc,4800, f85f0000), \
9338 X(_ldr_pc2,4800, f85f0000), \
9339 X(_ldr_sp,9800, f85d0000), \
9340 X(_lsl, 0000, fa00f000), \
9341 X(_lsls, 0000, fa10f000), \
9342 X(_lsr, 0800, fa20f000), \
9343 X(_lsrs, 0800, fa30f000), \
9344 X(_mov, 2000, ea4f0000), \
9345 X(_movs, 2000, ea5f0000), \
9346 X(_mul, 4340, fb00f000), \
9347 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9348 X(_mvn, 43c0, ea6f0000), \
9349 X(_mvns, 43c0, ea7f0000), \
9350 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9351 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9352 X(_orr, 4300, ea400000), \
9353 X(_orrs, 4300, ea500000), \
9354 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9355 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9356 X(_rev, ba00, fa90f080), \
9357 X(_rev16, ba40, fa90f090), \
9358 X(_revsh, bac0, fa90f0b0), \
9359 X(_ror, 41c0, fa60f000), \
9360 X(_rors, 41c0, fa70f000), \
9361 X(_sbc, 4180, eb600000), \
9362 X(_sbcs, 4180, eb700000), \
9363 X(_stmia, c000, e8800000), \
9364 X(_str, 6000, f8400000), \
9365 X(_strb, 7000, f8000000), \
9366 X(_strh, 8000, f8200000), \
9367 X(_str_sp,9000, f84d0000), \
9368 X(_sub, 1e00, eba00000), \
9369 X(_subs, 1e00, ebb00000), \
9370 X(_subi, 8000, f1a00000), \
9371 X(_subis, 8000, f1b00000), \
9372 X(_sxtb, b240, fa4ff080), \
9373 X(_sxth, b200, fa0ff080), \
9374 X(_tst, 4200, ea100f00), \
9375 X(_uxtb, b2c0, fa5ff080), \
9376 X(_uxth, b280, fa1ff080), \
9377 X(_nop, bf00, f3af8000), \
9378 X(_yield, bf10, f3af8001), \
9379 X(_wfe, bf20, f3af8002), \
9380 X(_wfi, bf30, f3af8003), \
9381 X(_sev, bf40, f3af8004),
9383 /* To catch errors in encoding functions, the codes are all offset by
9384 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9385 as 16-bit instructions. */
9386 #define X(a,b,c) T_MNEM##a
9387 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9390 #define X(a,b,c) 0x##b
9391 static const unsigned short thumb_op16[] = { T16_32_TAB };
9392 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9395 #define X(a,b,c) 0x##c
9396 static const unsigned int thumb_op32[] = { T16_32_TAB };
9397 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9398 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9402 /* Thumb instruction encoders, in alphabetical order. */
9407 do_t_add_sub_w (void)
9411 Rd = inst.operands[0].reg;
9412 Rn = inst.operands[1].reg;
9414 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9415 is the SP-{plus,minus}-immediate form of the instruction. */
9417 constraint (Rd == REG_PC, BAD_PC);
9419 reject_bad_reg (Rd);
9421 inst.instruction |= (Rn << 16) | (Rd << 8);
9422 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9425 /* Parse an add or subtract instruction. We get here with inst.instruction
9426 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9433 Rd = inst.operands[0].reg;
9434 Rs = (inst.operands[1].present
9435 ? inst.operands[1].reg /* Rd, Rs, foo */
9436 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9439 set_it_insn_type_last ();
9447 flags = (inst.instruction == T_MNEM_adds
9448 || inst.instruction == T_MNEM_subs);
9450 narrow = !in_it_block ();
9452 narrow = in_it_block ();
9453 if (!inst.operands[2].isreg)
9457 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9459 add = (inst.instruction == T_MNEM_add
9460 || inst.instruction == T_MNEM_adds);
9462 if (inst.size_req != 4)
9464 /* Attempt to use a narrow opcode, with relaxation if
9466 if (Rd == REG_SP && Rs == REG_SP && !flags)
9467 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9468 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9469 opcode = T_MNEM_add_sp;
9470 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9471 opcode = T_MNEM_add_pc;
9472 else if (Rd <= 7 && Rs <= 7 && narrow)
9475 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9477 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9481 inst.instruction = THUMB_OP16(opcode);
9482 inst.instruction |= (Rd << 4) | Rs;
9483 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9484 if (inst.size_req != 2)
9485 inst.relax = opcode;
9488 constraint (inst.size_req == 2, BAD_HIREG);
9490 if (inst.size_req == 4
9491 || (inst.size_req != 2 && !opcode))
9495 constraint (add, BAD_PC);
9496 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9497 _("only SUBS PC, LR, #const allowed"));
9498 constraint (inst.reloc.exp.X_op != O_constant,
9499 _("expression too complex"));
9500 constraint (inst.reloc.exp.X_add_number < 0
9501 || inst.reloc.exp.X_add_number > 0xff,
9502 _("immediate value out of range"));
9503 inst.instruction = T2_SUBS_PC_LR
9504 | inst.reloc.exp.X_add_number;
9505 inst.reloc.type = BFD_RELOC_UNUSED;
9508 else if (Rs == REG_PC)
9510 /* Always use addw/subw. */
9511 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9512 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9516 inst.instruction = THUMB_OP32 (inst.instruction);
9517 inst.instruction = (inst.instruction & 0xe1ffffff)
9520 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9522 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9524 inst.instruction |= Rd << 8;
9525 inst.instruction |= Rs << 16;
9530 unsigned int value = inst.reloc.exp.X_add_number;
9531 unsigned int shift = inst.operands[2].shift_kind;
9533 Rn = inst.operands[2].reg;
9534 /* See if we can do this with a 16-bit instruction. */
9535 if (!inst.operands[2].shifted && inst.size_req != 4)
9537 if (Rd > 7 || Rs > 7 || Rn > 7)
9542 inst.instruction = ((inst.instruction == T_MNEM_adds
9543 || inst.instruction == T_MNEM_add)
9546 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9550 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
9552 /* Thumb-1 cores (except v6-M) require at least one high
9553 register in a narrow non flag setting add. */
9554 if (Rd > 7 || Rn > 7
9555 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9556 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
9563 inst.instruction = T_OPCODE_ADD_HI;
9564 inst.instruction |= (Rd & 8) << 4;
9565 inst.instruction |= (Rd & 7);
9566 inst.instruction |= Rn << 3;
9572 constraint (Rd == REG_PC, BAD_PC);
9573 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9574 constraint (Rs == REG_PC, BAD_PC);
9575 reject_bad_reg (Rn);
9577 /* If we get here, it can't be done in 16 bits. */
9578 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9579 _("shift must be constant"));
9580 inst.instruction = THUMB_OP32 (inst.instruction);
9581 inst.instruction |= Rd << 8;
9582 inst.instruction |= Rs << 16;
9583 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9584 _("shift value over 3 not allowed in thumb mode"));
9585 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9586 _("only LSL shift allowed in thumb mode"));
9587 encode_thumb32_shifted_operand (2);
9592 constraint (inst.instruction == T_MNEM_adds
9593 || inst.instruction == T_MNEM_subs,
9596 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
9598 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9599 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9602 inst.instruction = (inst.instruction == T_MNEM_add
9604 inst.instruction |= (Rd << 4) | Rs;
9605 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9609 Rn = inst.operands[2].reg;
9610 constraint (inst.operands[2].shifted, _("unshifted register required"));
9612 /* We now have Rd, Rs, and Rn set to registers. */
9613 if (Rd > 7 || Rs > 7 || Rn > 7)
9615 /* Can't do this for SUB. */
9616 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9617 inst.instruction = T_OPCODE_ADD_HI;
9618 inst.instruction |= (Rd & 8) << 4;
9619 inst.instruction |= (Rd & 7);
9621 inst.instruction |= Rn << 3;
9623 inst.instruction |= Rs << 3;
9625 constraint (1, _("dest must overlap one source register"));
9629 inst.instruction = (inst.instruction == T_MNEM_add
9630 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9631 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9641 Rd = inst.operands[0].reg;
9642 reject_bad_reg (Rd);
9644 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
9646 /* Defer to section relaxation. */
9647 inst.relax = inst.instruction;
9648 inst.instruction = THUMB_OP16 (inst.instruction);
9649 inst.instruction |= Rd << 4;
9651 else if (unified_syntax && inst.size_req != 2)
9653 /* Generate a 32-bit opcode. */
9654 inst.instruction = THUMB_OP32 (inst.instruction);
9655 inst.instruction |= Rd << 8;
9656 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9657 inst.reloc.pc_rel = 1;
9661 /* Generate a 16-bit opcode. */
9662 inst.instruction = THUMB_OP16 (inst.instruction);
9663 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9664 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9665 inst.reloc.pc_rel = 1;
9667 inst.instruction |= Rd << 4;
9671 /* Arithmetic instructions for which there is just one 16-bit
9672 instruction encoding, and it allows only two low registers.
9673 For maximal compatibility with ARM syntax, we allow three register
9674 operands even when Thumb-32 instructions are not available, as long
9675 as the first two are identical. For instance, both "sbc r0,r1" and
9676 "sbc r0,r0,r1" are allowed. */
9682 Rd = inst.operands[0].reg;
9683 Rs = (inst.operands[1].present
9684 ? inst.operands[1].reg /* Rd, Rs, foo */
9685 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9686 Rn = inst.operands[2].reg;
9688 reject_bad_reg (Rd);
9689 reject_bad_reg (Rs);
9690 if (inst.operands[2].isreg)
9691 reject_bad_reg (Rn);
9695 if (!inst.operands[2].isreg)
9697 /* For an immediate, we always generate a 32-bit opcode;
9698 section relaxation will shrink it later if possible. */
9699 inst.instruction = THUMB_OP32 (inst.instruction);
9700 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9701 inst.instruction |= Rd << 8;
9702 inst.instruction |= Rs << 16;
9703 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9709 /* See if we can do this with a 16-bit instruction. */
9710 if (THUMB_SETS_FLAGS (inst.instruction))
9711 narrow = !in_it_block ();
9713 narrow = in_it_block ();
9715 if (Rd > 7 || Rn > 7 || Rs > 7)
9717 if (inst.operands[2].shifted)
9719 if (inst.size_req == 4)
9725 inst.instruction = THUMB_OP16 (inst.instruction);
9726 inst.instruction |= Rd;
9727 inst.instruction |= Rn << 3;
9731 /* If we get here, it can't be done in 16 bits. */
9732 constraint (inst.operands[2].shifted
9733 && inst.operands[2].immisreg,
9734 _("shift must be constant"));
9735 inst.instruction = THUMB_OP32 (inst.instruction);
9736 inst.instruction |= Rd << 8;
9737 inst.instruction |= Rs << 16;
9738 encode_thumb32_shifted_operand (2);
9743 /* On its face this is a lie - the instruction does set the
9744 flags. However, the only supported mnemonic in this mode
9746 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9748 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9749 _("unshifted register required"));
9750 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9751 constraint (Rd != Rs,
9752 _("dest and source1 must be the same register"));
9754 inst.instruction = THUMB_OP16 (inst.instruction);
9755 inst.instruction |= Rd;
9756 inst.instruction |= Rn << 3;
9760 /* Similarly, but for instructions where the arithmetic operation is
9761 commutative, so we can allow either of them to be different from
9762 the destination operand in a 16-bit instruction. For instance, all
9763 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9770 Rd = inst.operands[0].reg;
9771 Rs = (inst.operands[1].present
9772 ? inst.operands[1].reg /* Rd, Rs, foo */
9773 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9774 Rn = inst.operands[2].reg;
9776 reject_bad_reg (Rd);
9777 reject_bad_reg (Rs);
9778 if (inst.operands[2].isreg)
9779 reject_bad_reg (Rn);
9783 if (!inst.operands[2].isreg)
9785 /* For an immediate, we always generate a 32-bit opcode;
9786 section relaxation will shrink it later if possible. */
9787 inst.instruction = THUMB_OP32 (inst.instruction);
9788 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9789 inst.instruction |= Rd << 8;
9790 inst.instruction |= Rs << 16;
9791 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9797 /* See if we can do this with a 16-bit instruction. */
9798 if (THUMB_SETS_FLAGS (inst.instruction))
9799 narrow = !in_it_block ();
9801 narrow = in_it_block ();
9803 if (Rd > 7 || Rn > 7 || Rs > 7)
9805 if (inst.operands[2].shifted)
9807 if (inst.size_req == 4)
9814 inst.instruction = THUMB_OP16 (inst.instruction);
9815 inst.instruction |= Rd;
9816 inst.instruction |= Rn << 3;
9821 inst.instruction = THUMB_OP16 (inst.instruction);
9822 inst.instruction |= Rd;
9823 inst.instruction |= Rs << 3;
9828 /* If we get here, it can't be done in 16 bits. */
9829 constraint (inst.operands[2].shifted
9830 && inst.operands[2].immisreg,
9831 _("shift must be constant"));
9832 inst.instruction = THUMB_OP32 (inst.instruction);
9833 inst.instruction |= Rd << 8;
9834 inst.instruction |= Rs << 16;
9835 encode_thumb32_shifted_operand (2);
9840 /* On its face this is a lie - the instruction does set the
9841 flags. However, the only supported mnemonic in this mode
9843 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
9845 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9846 _("unshifted register required"));
9847 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9849 inst.instruction = THUMB_OP16 (inst.instruction);
9850 inst.instruction |= Rd;
9853 inst.instruction |= Rn << 3;
9855 inst.instruction |= Rs << 3;
9857 constraint (1, _("dest must overlap one source register"));
9864 if (inst.operands[0].present)
9866 constraint ((inst.instruction & 0xf0) != 0x40
9867 && inst.operands[0].imm > 0xf
9868 && inst.operands[0].imm < 0x0,
9869 _("bad barrier type"));
9870 inst.instruction |= inst.operands[0].imm;
9873 inst.instruction |= 0xf;
9880 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9881 constraint (msb > 32, _("bit-field extends past end of register"));
9882 /* The instruction encoding stores the LSB and MSB,
9883 not the LSB and width. */
9884 Rd = inst.operands[0].reg;
9885 reject_bad_reg (Rd);
9886 inst.instruction |= Rd << 8;
9887 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
9888 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
9889 inst.instruction |= msb - 1;
9898 Rd = inst.operands[0].reg;
9899 reject_bad_reg (Rd);
9901 /* #0 in second position is alternative syntax for bfc, which is
9902 the same instruction but with REG_PC in the Rm field. */
9903 if (!inst.operands[1].isreg)
9907 Rn = inst.operands[1].reg;
9908 reject_bad_reg (Rn);
9911 msb = inst.operands[2].imm + inst.operands[3].imm;
9912 constraint (msb > 32, _("bit-field extends past end of register"));
9913 /* The instruction encoding stores the LSB and MSB,
9914 not the LSB and width. */
9915 inst.instruction |= Rd << 8;
9916 inst.instruction |= Rn << 16;
9917 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9918 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9919 inst.instruction |= msb - 1;
9927 Rd = inst.operands[0].reg;
9928 Rn = inst.operands[1].reg;
9930 reject_bad_reg (Rd);
9931 reject_bad_reg (Rn);
9933 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9934 _("bit-field extends past end of register"));
9935 inst.instruction |= Rd << 8;
9936 inst.instruction |= Rn << 16;
9937 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
9938 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
9939 inst.instruction |= inst.operands[3].imm - 1;
9942 /* ARM V5 Thumb BLX (argument parse)
9943 BLX <target_addr> which is BLX(1)
9944 BLX <Rm> which is BLX(2)
9945 Unfortunately, there are two different opcodes for this mnemonic.
9946 So, the insns[].value is not used, and the code here zaps values
9947 into inst.instruction.
9949 ??? How to take advantage of the additional two bits of displacement
9950 available in Thumb32 mode? Need new relocation? */
9955 set_it_insn_type_last ();
9957 if (inst.operands[0].isreg)
9959 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9960 /* We have a register, so this is BLX(2). */
9961 inst.instruction |= inst.operands[0].reg << 3;
9965 /* No register. This must be BLX(1). */
9966 inst.instruction = 0xf000e800;
9967 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
9979 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
9983 /* Conditional branches inside IT blocks are encoded as unconditional
9990 if (cond != COND_ALWAYS)
9991 opcode = T_MNEM_bcond;
9993 opcode = inst.instruction;
9996 && (inst.size_req == 4
9997 || (inst.size_req != 2
9998 && (inst.operands[0].hasreloc
9999 || inst.reloc.exp.X_op == O_constant))))
10001 inst.instruction = THUMB_OP32(opcode);
10002 if (cond == COND_ALWAYS)
10003 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10006 gas_assert (cond != 0xF);
10007 inst.instruction |= cond << 22;
10008 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10013 inst.instruction = THUMB_OP16(opcode);
10014 if (cond == COND_ALWAYS)
10015 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10018 inst.instruction |= cond << 8;
10019 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10021 /* Allow section relaxation. */
10022 if (unified_syntax && inst.size_req != 2)
10023 inst.relax = opcode;
10025 inst.reloc.type = reloc;
10026 inst.reloc.pc_rel = 1;
10032 constraint (inst.cond != COND_ALWAYS,
10033 _("instruction is always unconditional"));
10034 if (inst.operands[0].present)
10036 constraint (inst.operands[0].imm > 255,
10037 _("immediate value out of range"));
10038 inst.instruction |= inst.operands[0].imm;
10039 set_it_insn_type (NEUTRAL_IT_INSN);
10044 do_t_branch23 (void)
10046 set_it_insn_type_last ();
10047 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10049 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10050 this file. We used to simply ignore the PLT reloc type here --
10051 the branch encoding is now needed to deal with TLSCALL relocs.
10052 So if we see a PLT reloc now, put it back to how it used to be to
10053 keep the preexisting behaviour. */
10054 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10055 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10057 #if defined(OBJ_COFF)
10058 /* If the destination of the branch is a defined symbol which does not have
10059 the THUMB_FUNC attribute, then we must be calling a function which has
10060 the (interfacearm) attribute. We look for the Thumb entry point to that
10061 function and change the branch to refer to that function instead. */
10062 if ( inst.reloc.exp.X_op == O_symbol
10063 && inst.reloc.exp.X_add_symbol != NULL
10064 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10065 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10066 inst.reloc.exp.X_add_symbol =
10067 find_real_start (inst.reloc.exp.X_add_symbol);
10074 set_it_insn_type_last ();
10075 inst.instruction |= inst.operands[0].reg << 3;
10076 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10077 should cause the alignment to be checked once it is known. This is
10078 because BX PC only works if the instruction is word aligned. */
10086 set_it_insn_type_last ();
10087 Rm = inst.operands[0].reg;
10088 reject_bad_reg (Rm);
10089 inst.instruction |= Rm << 16;
10098 Rd = inst.operands[0].reg;
10099 Rm = inst.operands[1].reg;
10101 reject_bad_reg (Rd);
10102 reject_bad_reg (Rm);
10104 inst.instruction |= Rd << 8;
10105 inst.instruction |= Rm << 16;
10106 inst.instruction |= Rm;
10112 set_it_insn_type (OUTSIDE_IT_INSN);
10113 inst.instruction |= inst.operands[0].imm;
10119 set_it_insn_type (OUTSIDE_IT_INSN);
10121 && (inst.operands[1].present || inst.size_req == 4)
10122 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
10124 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10125 inst.instruction = 0xf3af8000;
10126 inst.instruction |= imod << 9;
10127 inst.instruction |= inst.operands[0].imm << 5;
10128 if (inst.operands[1].present)
10129 inst.instruction |= 0x100 | inst.operands[1].imm;
10133 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10134 && (inst.operands[0].imm & 4),
10135 _("selected processor does not support 'A' form "
10136 "of this instruction"));
10137 constraint (inst.operands[1].present || inst.size_req == 4,
10138 _("Thumb does not support the 2-argument "
10139 "form of this instruction"));
10140 inst.instruction |= inst.operands[0].imm;
10144 /* THUMB CPY instruction (argument parse). */
10149 if (inst.size_req == 4)
10151 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10152 inst.instruction |= inst.operands[0].reg << 8;
10153 inst.instruction |= inst.operands[1].reg;
10157 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10158 inst.instruction |= (inst.operands[0].reg & 0x7);
10159 inst.instruction |= inst.operands[1].reg << 3;
10166 set_it_insn_type (OUTSIDE_IT_INSN);
10167 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10168 inst.instruction |= inst.operands[0].reg;
10169 inst.reloc.pc_rel = 1;
10170 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10176 inst.instruction |= inst.operands[0].imm;
10182 unsigned Rd, Rn, Rm;
10184 Rd = inst.operands[0].reg;
10185 Rn = (inst.operands[1].present
10186 ? inst.operands[1].reg : Rd);
10187 Rm = inst.operands[2].reg;
10189 reject_bad_reg (Rd);
10190 reject_bad_reg (Rn);
10191 reject_bad_reg (Rm);
10193 inst.instruction |= Rd << 8;
10194 inst.instruction |= Rn << 16;
10195 inst.instruction |= Rm;
10201 if (unified_syntax && inst.size_req == 4)
10202 inst.instruction = THUMB_OP32 (inst.instruction);
10204 inst.instruction = THUMB_OP16 (inst.instruction);
10210 unsigned int cond = inst.operands[0].imm;
10212 set_it_insn_type (IT_INSN);
10213 now_it.mask = (inst.instruction & 0xf) | 0x10;
10216 /* If the condition is a negative condition, invert the mask. */
10217 if ((cond & 0x1) == 0x0)
10219 unsigned int mask = inst.instruction & 0x000f;
10221 if ((mask & 0x7) == 0)
10222 /* no conversion needed */;
10223 else if ((mask & 0x3) == 0)
10225 else if ((mask & 0x1) == 0)
10230 inst.instruction &= 0xfff0;
10231 inst.instruction |= mask;
10234 inst.instruction |= cond << 4;
10237 /* Helper function used for both push/pop and ldm/stm. */
10239 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10243 load = (inst.instruction & (1 << 20)) != 0;
10245 if (mask & (1 << 13))
10246 inst.error = _("SP not allowed in register list");
10248 if ((mask & (1 << base)) != 0
10250 inst.error = _("having the base register in the register list when "
10251 "using write back is UNPREDICTABLE");
10255 if (mask & (1 << 15))
10257 if (mask & (1 << 14))
10258 inst.error = _("LR and PC should not both be in register list");
10260 set_it_insn_type_last ();
10265 if (mask & (1 << 15))
10266 inst.error = _("PC not allowed in register list");
10269 if ((mask & (mask - 1)) == 0)
10271 /* Single register transfers implemented as str/ldr. */
10274 if (inst.instruction & (1 << 23))
10275 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10277 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10281 if (inst.instruction & (1 << 23))
10282 inst.instruction = 0x00800000; /* ia -> [base] */
10284 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10287 inst.instruction |= 0xf8400000;
10289 inst.instruction |= 0x00100000;
10291 mask = ffs (mask) - 1;
10294 else if (writeback)
10295 inst.instruction |= WRITE_BACK;
10297 inst.instruction |= mask;
10298 inst.instruction |= base << 16;
10304 /* This really doesn't seem worth it. */
10305 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10306 _("expression too complex"));
10307 constraint (inst.operands[1].writeback,
10308 _("Thumb load/store multiple does not support {reglist}^"));
10310 if (unified_syntax)
10312 bfd_boolean narrow;
10316 /* See if we can use a 16-bit instruction. */
10317 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10318 && inst.size_req != 4
10319 && !(inst.operands[1].imm & ~0xff))
10321 mask = 1 << inst.operands[0].reg;
10323 if (inst.operands[0].reg <= 7)
10325 if (inst.instruction == T_MNEM_stmia
10326 ? inst.operands[0].writeback
10327 : (inst.operands[0].writeback
10328 == !(inst.operands[1].imm & mask)))
10330 if (inst.instruction == T_MNEM_stmia
10331 && (inst.operands[1].imm & mask)
10332 && (inst.operands[1].imm & (mask - 1)))
10333 as_warn (_("value stored for r%d is UNKNOWN"),
10334 inst.operands[0].reg);
10336 inst.instruction = THUMB_OP16 (inst.instruction);
10337 inst.instruction |= inst.operands[0].reg << 8;
10338 inst.instruction |= inst.operands[1].imm;
10341 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10343 /* This means 1 register in reg list one of 3 situations:
10344 1. Instruction is stmia, but without writeback.
10345 2. lmdia without writeback, but with Rn not in
10347 3. ldmia with writeback, but with Rn in reglist.
10348 Case 3 is UNPREDICTABLE behaviour, so we handle
10349 case 1 and 2 which can be converted into a 16-bit
10350 str or ldr. The SP cases are handled below. */
10351 unsigned long opcode;
10352 /* First, record an error for Case 3. */
10353 if (inst.operands[1].imm & mask
10354 && inst.operands[0].writeback)
10356 _("having the base register in the register list when "
10357 "using write back is UNPREDICTABLE");
10359 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
10361 inst.instruction = THUMB_OP16 (opcode);
10362 inst.instruction |= inst.operands[0].reg << 3;
10363 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10367 else if (inst.operands[0] .reg == REG_SP)
10369 if (inst.operands[0].writeback)
10372 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10373 ? T_MNEM_push : T_MNEM_pop);
10374 inst.instruction |= inst.operands[1].imm;
10377 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10380 THUMB_OP16 (inst.instruction == T_MNEM_stmia
10381 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
10382 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
10390 if (inst.instruction < 0xffff)
10391 inst.instruction = THUMB_OP32 (inst.instruction);
10393 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10394 inst.operands[0].writeback);
10399 constraint (inst.operands[0].reg > 7
10400 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
10401 constraint (inst.instruction != T_MNEM_ldmia
10402 && inst.instruction != T_MNEM_stmia,
10403 _("Thumb-2 instruction only valid in unified syntax"));
10404 if (inst.instruction == T_MNEM_stmia)
10406 if (!inst.operands[0].writeback)
10407 as_warn (_("this instruction will write back the base register"));
10408 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10409 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
10410 as_warn (_("value stored for r%d is UNKNOWN"),
10411 inst.operands[0].reg);
10415 if (!inst.operands[0].writeback
10416 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10417 as_warn (_("this instruction will write back the base register"));
10418 else if (inst.operands[0].writeback
10419 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10420 as_warn (_("this instruction will not write back the base register"));
10423 inst.instruction = THUMB_OP16 (inst.instruction);
10424 inst.instruction |= inst.operands[0].reg << 8;
10425 inst.instruction |= inst.operands[1].imm;
10432 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10433 || inst.operands[1].postind || inst.operands[1].writeback
10434 || inst.operands[1].immisreg || inst.operands[1].shifted
10435 || inst.operands[1].negative,
10438 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10440 inst.instruction |= inst.operands[0].reg << 12;
10441 inst.instruction |= inst.operands[1].reg << 16;
10442 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10448 if (!inst.operands[1].present)
10450 constraint (inst.operands[0].reg == REG_LR,
10451 _("r14 not allowed as first register "
10452 "when second register is omitted"));
10453 inst.operands[1].reg = inst.operands[0].reg + 1;
10455 constraint (inst.operands[0].reg == inst.operands[1].reg,
10458 inst.instruction |= inst.operands[0].reg << 12;
10459 inst.instruction |= inst.operands[1].reg << 8;
10460 inst.instruction |= inst.operands[2].reg << 16;
10466 unsigned long opcode;
10469 if (inst.operands[0].isreg
10470 && !inst.operands[0].preind
10471 && inst.operands[0].reg == REG_PC)
10472 set_it_insn_type_last ();
10474 opcode = inst.instruction;
10475 if (unified_syntax)
10477 if (!inst.operands[1].isreg)
10479 if (opcode <= 0xffff)
10480 inst.instruction = THUMB_OP32 (opcode);
10481 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10484 if (inst.operands[1].isreg
10485 && !inst.operands[1].writeback
10486 && !inst.operands[1].shifted && !inst.operands[1].postind
10487 && !inst.operands[1].negative && inst.operands[0].reg <= 7
10488 && opcode <= 0xffff
10489 && inst.size_req != 4)
10491 /* Insn may have a 16-bit form. */
10492 Rn = inst.operands[1].reg;
10493 if (inst.operands[1].immisreg)
10495 inst.instruction = THUMB_OP16 (opcode);
10497 if (Rn <= 7 && inst.operands[1].imm <= 7)
10499 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10500 reject_bad_reg (inst.operands[1].imm);
10502 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10503 && opcode != T_MNEM_ldrsb)
10504 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10505 || (Rn == REG_SP && opcode == T_MNEM_str))
10512 if (inst.reloc.pc_rel)
10513 opcode = T_MNEM_ldr_pc2;
10515 opcode = T_MNEM_ldr_pc;
10519 if (opcode == T_MNEM_ldr)
10520 opcode = T_MNEM_ldr_sp;
10522 opcode = T_MNEM_str_sp;
10524 inst.instruction = inst.operands[0].reg << 8;
10528 inst.instruction = inst.operands[0].reg;
10529 inst.instruction |= inst.operands[1].reg << 3;
10531 inst.instruction |= THUMB_OP16 (opcode);
10532 if (inst.size_req == 2)
10533 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10535 inst.relax = opcode;
10539 /* Definitely a 32-bit variant. */
10541 /* Warning for Erratum 752419. */
10542 if (opcode == T_MNEM_ldr
10543 && inst.operands[0].reg == REG_SP
10544 && inst.operands[1].writeback == 1
10545 && !inst.operands[1].immisreg)
10547 if (no_cpu_selected ()
10548 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
10549 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10550 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
10551 as_warn (_("This instruction may be unpredictable "
10552 "if executed on M-profile cores "
10553 "with interrupts enabled."));
10556 /* Do some validations regarding addressing modes. */
10557 if (inst.operands[1].immisreg)
10558 reject_bad_reg (inst.operands[1].imm);
10560 constraint (inst.operands[1].writeback == 1
10561 && inst.operands[0].reg == inst.operands[1].reg,
10564 inst.instruction = THUMB_OP32 (opcode);
10565 inst.instruction |= inst.operands[0].reg << 12;
10566 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
10567 check_ldr_r15_aligned ();
10571 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10573 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
10575 /* Only [Rn,Rm] is acceptable. */
10576 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10577 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10578 || inst.operands[1].postind || inst.operands[1].shifted
10579 || inst.operands[1].negative,
10580 _("Thumb does not support this addressing mode"));
10581 inst.instruction = THUMB_OP16 (inst.instruction);
10585 inst.instruction = THUMB_OP16 (inst.instruction);
10586 if (!inst.operands[1].isreg)
10587 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10590 constraint (!inst.operands[1].preind
10591 || inst.operands[1].shifted
10592 || inst.operands[1].writeback,
10593 _("Thumb does not support this addressing mode"));
10594 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
10596 constraint (inst.instruction & 0x0600,
10597 _("byte or halfword not valid for base register"));
10598 constraint (inst.operands[1].reg == REG_PC
10599 && !(inst.instruction & THUMB_LOAD_BIT),
10600 _("r15 based store not allowed"));
10601 constraint (inst.operands[1].immisreg,
10602 _("invalid base register for register offset"));
10604 if (inst.operands[1].reg == REG_PC)
10605 inst.instruction = T_OPCODE_LDR_PC;
10606 else if (inst.instruction & THUMB_LOAD_BIT)
10607 inst.instruction = T_OPCODE_LDR_SP;
10609 inst.instruction = T_OPCODE_STR_SP;
10611 inst.instruction |= inst.operands[0].reg << 8;
10612 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10616 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10617 if (!inst.operands[1].immisreg)
10619 /* Immediate offset. */
10620 inst.instruction |= inst.operands[0].reg;
10621 inst.instruction |= inst.operands[1].reg << 3;
10622 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10626 /* Register offset. */
10627 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10628 constraint (inst.operands[1].negative,
10629 _("Thumb does not support this addressing mode"));
10632 switch (inst.instruction)
10634 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10635 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10636 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10637 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10638 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10639 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10640 case 0x5600 /* ldrsb */:
10641 case 0x5e00 /* ldrsh */: break;
10645 inst.instruction |= inst.operands[0].reg;
10646 inst.instruction |= inst.operands[1].reg << 3;
10647 inst.instruction |= inst.operands[1].imm << 6;
10653 if (!inst.operands[1].present)
10655 inst.operands[1].reg = inst.operands[0].reg + 1;
10656 constraint (inst.operands[0].reg == REG_LR,
10657 _("r14 not allowed here"));
10658 constraint (inst.operands[0].reg == REG_R12,
10659 _("r12 not allowed here"));
10662 if (inst.operands[2].writeback
10663 && (inst.operands[0].reg == inst.operands[2].reg
10664 || inst.operands[1].reg == inst.operands[2].reg))
10665 as_warn (_("base register written back, and overlaps "
10666 "one of transfer registers"));
10668 inst.instruction |= inst.operands[0].reg << 12;
10669 inst.instruction |= inst.operands[1].reg << 8;
10670 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
10676 inst.instruction |= inst.operands[0].reg << 12;
10677 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10683 unsigned Rd, Rn, Rm, Ra;
10685 Rd = inst.operands[0].reg;
10686 Rn = inst.operands[1].reg;
10687 Rm = inst.operands[2].reg;
10688 Ra = inst.operands[3].reg;
10690 reject_bad_reg (Rd);
10691 reject_bad_reg (Rn);
10692 reject_bad_reg (Rm);
10693 reject_bad_reg (Ra);
10695 inst.instruction |= Rd << 8;
10696 inst.instruction |= Rn << 16;
10697 inst.instruction |= Rm;
10698 inst.instruction |= Ra << 12;
10704 unsigned RdLo, RdHi, Rn, Rm;
10706 RdLo = inst.operands[0].reg;
10707 RdHi = inst.operands[1].reg;
10708 Rn = inst.operands[2].reg;
10709 Rm = inst.operands[3].reg;
10711 reject_bad_reg (RdLo);
10712 reject_bad_reg (RdHi);
10713 reject_bad_reg (Rn);
10714 reject_bad_reg (Rm);
10716 inst.instruction |= RdLo << 12;
10717 inst.instruction |= RdHi << 8;
10718 inst.instruction |= Rn << 16;
10719 inst.instruction |= Rm;
10723 do_t_mov_cmp (void)
10727 Rn = inst.operands[0].reg;
10728 Rm = inst.operands[1].reg;
10731 set_it_insn_type_last ();
10733 if (unified_syntax)
10735 int r0off = (inst.instruction == T_MNEM_mov
10736 || inst.instruction == T_MNEM_movs) ? 8 : 16;
10737 unsigned long opcode;
10738 bfd_boolean narrow;
10739 bfd_boolean low_regs;
10741 low_regs = (Rn <= 7 && Rm <= 7);
10742 opcode = inst.instruction;
10743 if (in_it_block ())
10744 narrow = opcode != T_MNEM_movs;
10746 narrow = opcode != T_MNEM_movs || low_regs;
10747 if (inst.size_req == 4
10748 || inst.operands[1].shifted)
10751 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10752 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10753 && !inst.operands[1].shifted
10757 inst.instruction = T2_SUBS_PC_LR;
10761 if (opcode == T_MNEM_cmp)
10763 constraint (Rn == REG_PC, BAD_PC);
10766 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10768 warn_deprecated_sp (Rm);
10769 /* R15 was documented as a valid choice for Rm in ARMv6,
10770 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10771 tools reject R15, so we do too. */
10772 constraint (Rm == REG_PC, BAD_PC);
10775 reject_bad_reg (Rm);
10777 else if (opcode == T_MNEM_mov
10778 || opcode == T_MNEM_movs)
10780 if (inst.operands[1].isreg)
10782 if (opcode == T_MNEM_movs)
10784 reject_bad_reg (Rn);
10785 reject_bad_reg (Rm);
10789 /* This is mov.n. */
10790 if ((Rn == REG_SP || Rn == REG_PC)
10791 && (Rm == REG_SP || Rm == REG_PC))
10793 as_warn (_("Use of r%u as a source register is "
10794 "deprecated when r%u is the destination "
10795 "register."), Rm, Rn);
10800 /* This is mov.w. */
10801 constraint (Rn == REG_PC, BAD_PC);
10802 constraint (Rm == REG_PC, BAD_PC);
10803 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
10807 reject_bad_reg (Rn);
10810 if (!inst.operands[1].isreg)
10812 /* Immediate operand. */
10813 if (!in_it_block () && opcode == T_MNEM_mov)
10815 if (low_regs && narrow)
10817 inst.instruction = THUMB_OP16 (opcode);
10818 inst.instruction |= Rn << 8;
10819 if (inst.size_req == 2)
10820 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
10822 inst.relax = opcode;
10826 inst.instruction = THUMB_OP32 (inst.instruction);
10827 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10828 inst.instruction |= Rn << r0off;
10829 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10832 else if (inst.operands[1].shifted && inst.operands[1].immisreg
10833 && (inst.instruction == T_MNEM_mov
10834 || inst.instruction == T_MNEM_movs))
10836 /* Register shifts are encoded as separate shift instructions. */
10837 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
10839 if (in_it_block ())
10844 if (inst.size_req == 4)
10847 if (!low_regs || inst.operands[1].imm > 7)
10853 switch (inst.operands[1].shift_kind)
10856 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
10859 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
10862 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
10865 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
10871 inst.instruction = opcode;
10874 inst.instruction |= Rn;
10875 inst.instruction |= inst.operands[1].imm << 3;
10880 inst.instruction |= CONDS_BIT;
10882 inst.instruction |= Rn << 8;
10883 inst.instruction |= Rm << 16;
10884 inst.instruction |= inst.operands[1].imm;
10889 /* Some mov with immediate shift have narrow variants.
10890 Register shifts are handled above. */
10891 if (low_regs && inst.operands[1].shifted
10892 && (inst.instruction == T_MNEM_mov
10893 || inst.instruction == T_MNEM_movs))
10895 if (in_it_block ())
10896 narrow = (inst.instruction == T_MNEM_mov);
10898 narrow = (inst.instruction == T_MNEM_movs);
10903 switch (inst.operands[1].shift_kind)
10905 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
10906 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
10907 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
10908 default: narrow = FALSE; break;
10914 inst.instruction |= Rn;
10915 inst.instruction |= Rm << 3;
10916 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
10920 inst.instruction = THUMB_OP32 (inst.instruction);
10921 inst.instruction |= Rn << r0off;
10922 encode_thumb32_shifted_operand (1);
10926 switch (inst.instruction)
10929 /* In v4t or v5t a move of two lowregs produces unpredictable
10930 results. Don't allow this. */
10933 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
10934 "MOV Rd, Rs with two low registers is not "
10935 "permitted on this architecture");
10936 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
10940 inst.instruction = T_OPCODE_MOV_HR;
10941 inst.instruction |= (Rn & 0x8) << 4;
10942 inst.instruction |= (Rn & 0x7);
10943 inst.instruction |= Rm << 3;
10947 /* We know we have low registers at this point.
10948 Generate LSLS Rd, Rs, #0. */
10949 inst.instruction = T_OPCODE_LSL_I;
10950 inst.instruction |= Rn;
10951 inst.instruction |= Rm << 3;
10957 inst.instruction = T_OPCODE_CMP_LR;
10958 inst.instruction |= Rn;
10959 inst.instruction |= Rm << 3;
10963 inst.instruction = T_OPCODE_CMP_HR;
10964 inst.instruction |= (Rn & 0x8) << 4;
10965 inst.instruction |= (Rn & 0x7);
10966 inst.instruction |= Rm << 3;
10973 inst.instruction = THUMB_OP16 (inst.instruction);
10975 /* PR 10443: Do not silently ignore shifted operands. */
10976 constraint (inst.operands[1].shifted,
10977 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10979 if (inst.operands[1].isreg)
10981 if (Rn < 8 && Rm < 8)
10983 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10984 since a MOV instruction produces unpredictable results. */
10985 if (inst.instruction == T_OPCODE_MOV_I8)
10986 inst.instruction = T_OPCODE_ADD_I3;
10988 inst.instruction = T_OPCODE_CMP_LR;
10990 inst.instruction |= Rn;
10991 inst.instruction |= Rm << 3;
10995 if (inst.instruction == T_OPCODE_MOV_I8)
10996 inst.instruction = T_OPCODE_MOV_HR;
10998 inst.instruction = T_OPCODE_CMP_HR;
11004 constraint (Rn > 7,
11005 _("only lo regs allowed with immediate"));
11006 inst.instruction |= Rn << 8;
11007 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11018 top = (inst.instruction & 0x00800000) != 0;
11019 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11021 constraint (top, _(":lower16: not allowed this instruction"));
11022 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11024 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11026 constraint (!top, _(":upper16: not allowed this instruction"));
11027 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11030 Rd = inst.operands[0].reg;
11031 reject_bad_reg (Rd);
11033 inst.instruction |= Rd << 8;
11034 if (inst.reloc.type == BFD_RELOC_UNUSED)
11036 imm = inst.reloc.exp.X_add_number;
11037 inst.instruction |= (imm & 0xf000) << 4;
11038 inst.instruction |= (imm & 0x0800) << 15;
11039 inst.instruction |= (imm & 0x0700) << 4;
11040 inst.instruction |= (imm & 0x00ff);
11045 do_t_mvn_tst (void)
11049 Rn = inst.operands[0].reg;
11050 Rm = inst.operands[1].reg;
11052 if (inst.instruction == T_MNEM_cmp
11053 || inst.instruction == T_MNEM_cmn)
11054 constraint (Rn == REG_PC, BAD_PC);
11056 reject_bad_reg (Rn);
11057 reject_bad_reg (Rm);
11059 if (unified_syntax)
11061 int r0off = (inst.instruction == T_MNEM_mvn
11062 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11063 bfd_boolean narrow;
11065 if (inst.size_req == 4
11066 || inst.instruction > 0xffff
11067 || inst.operands[1].shifted
11068 || Rn > 7 || Rm > 7)
11070 else if (inst.instruction == T_MNEM_cmn)
11072 else if (THUMB_SETS_FLAGS (inst.instruction))
11073 narrow = !in_it_block ();
11075 narrow = in_it_block ();
11077 if (!inst.operands[1].isreg)
11079 /* For an immediate, we always generate a 32-bit opcode;
11080 section relaxation will shrink it later if possible. */
11081 if (inst.instruction < 0xffff)
11082 inst.instruction = THUMB_OP32 (inst.instruction);
11083 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11084 inst.instruction |= Rn << r0off;
11085 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11089 /* See if we can do this with a 16-bit instruction. */
11092 inst.instruction = THUMB_OP16 (inst.instruction);
11093 inst.instruction |= Rn;
11094 inst.instruction |= Rm << 3;
11098 constraint (inst.operands[1].shifted
11099 && inst.operands[1].immisreg,
11100 _("shift must be constant"));
11101 if (inst.instruction < 0xffff)
11102 inst.instruction = THUMB_OP32 (inst.instruction);
11103 inst.instruction |= Rn << r0off;
11104 encode_thumb32_shifted_operand (1);
11110 constraint (inst.instruction > 0xffff
11111 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11112 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11113 _("unshifted register required"));
11114 constraint (Rn > 7 || Rm > 7,
11117 inst.instruction = THUMB_OP16 (inst.instruction);
11118 inst.instruction |= Rn;
11119 inst.instruction |= Rm << 3;
11128 if (do_vfp_nsyn_mrs () == SUCCESS)
11131 Rd = inst.operands[0].reg;
11132 reject_bad_reg (Rd);
11133 inst.instruction |= Rd << 8;
11135 if (inst.operands[1].isreg)
11137 unsigned br = inst.operands[1].reg;
11138 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11139 as_bad (_("bad register for mrs"));
11141 inst.instruction |= br & (0xf << 16);
11142 inst.instruction |= (br & 0x300) >> 4;
11143 inst.instruction |= (br & SPSR_BIT) >> 2;
11147 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11149 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11150 constraint (flags != 0, _("selected processor does not support "
11151 "requested special purpose register"));
11153 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11155 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11156 _("'APSR', 'CPSR' or 'SPSR' expected"));
11158 inst.instruction |= (flags & SPSR_BIT) >> 2;
11159 inst.instruction |= inst.operands[1].imm & 0xff;
11160 inst.instruction |= 0xf0000;
11170 if (do_vfp_nsyn_msr () == SUCCESS)
11173 constraint (!inst.operands[1].isreg,
11174 _("Thumb encoding does not support an immediate here"));
11176 if (inst.operands[0].isreg)
11177 flags = (int)(inst.operands[0].reg);
11179 flags = inst.operands[0].imm;
11181 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
11183 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11185 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11186 && (bits & ~(PSR_s | PSR_f)) != 0)
11187 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11189 _("selected processor does not support requested special "
11190 "purpose register"));
11193 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11194 "requested special purpose register"));
11196 Rn = inst.operands[1].reg;
11197 reject_bad_reg (Rn);
11199 inst.instruction |= (flags & SPSR_BIT) >> 2;
11200 inst.instruction |= (flags & 0xf0000) >> 8;
11201 inst.instruction |= (flags & 0x300) >> 4;
11202 inst.instruction |= (flags & 0xff);
11203 inst.instruction |= Rn << 16;
11209 bfd_boolean narrow;
11210 unsigned Rd, Rn, Rm;
11212 if (!inst.operands[2].present)
11213 inst.operands[2].reg = inst.operands[0].reg;
11215 Rd = inst.operands[0].reg;
11216 Rn = inst.operands[1].reg;
11217 Rm = inst.operands[2].reg;
11219 if (unified_syntax)
11221 if (inst.size_req == 4
11227 else if (inst.instruction == T_MNEM_muls)
11228 narrow = !in_it_block ();
11230 narrow = in_it_block ();
11234 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
11235 constraint (Rn > 7 || Rm > 7,
11242 /* 16-bit MULS/Conditional MUL. */
11243 inst.instruction = THUMB_OP16 (inst.instruction);
11244 inst.instruction |= Rd;
11247 inst.instruction |= Rm << 3;
11249 inst.instruction |= Rn << 3;
11251 constraint (1, _("dest must overlap one source register"));
11255 constraint (inst.instruction != T_MNEM_mul,
11256 _("Thumb-2 MUL must not set flags"));
11258 inst.instruction = THUMB_OP32 (inst.instruction);
11259 inst.instruction |= Rd << 8;
11260 inst.instruction |= Rn << 16;
11261 inst.instruction |= Rm << 0;
11263 reject_bad_reg (Rd);
11264 reject_bad_reg (Rn);
11265 reject_bad_reg (Rm);
11272 unsigned RdLo, RdHi, Rn, Rm;
11274 RdLo = inst.operands[0].reg;
11275 RdHi = inst.operands[1].reg;
11276 Rn = inst.operands[2].reg;
11277 Rm = inst.operands[3].reg;
11279 reject_bad_reg (RdLo);
11280 reject_bad_reg (RdHi);
11281 reject_bad_reg (Rn);
11282 reject_bad_reg (Rm);
11284 inst.instruction |= RdLo << 12;
11285 inst.instruction |= RdHi << 8;
11286 inst.instruction |= Rn << 16;
11287 inst.instruction |= Rm;
11290 as_tsktsk (_("rdhi and rdlo must be different"));
11296 set_it_insn_type (NEUTRAL_IT_INSN);
11298 if (unified_syntax)
11300 if (inst.size_req == 4 || inst.operands[0].imm > 15)
11302 inst.instruction = THUMB_OP32 (inst.instruction);
11303 inst.instruction |= inst.operands[0].imm;
11307 /* PR9722: Check for Thumb2 availability before
11308 generating a thumb2 nop instruction. */
11309 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
11311 inst.instruction = THUMB_OP16 (inst.instruction);
11312 inst.instruction |= inst.operands[0].imm << 4;
11315 inst.instruction = 0x46c0;
11320 constraint (inst.operands[0].present,
11321 _("Thumb does not support NOP with hints"));
11322 inst.instruction = 0x46c0;
11329 if (unified_syntax)
11331 bfd_boolean narrow;
11333 if (THUMB_SETS_FLAGS (inst.instruction))
11334 narrow = !in_it_block ();
11336 narrow = in_it_block ();
11337 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11339 if (inst.size_req == 4)
11344 inst.instruction = THUMB_OP32 (inst.instruction);
11345 inst.instruction |= inst.operands[0].reg << 8;
11346 inst.instruction |= inst.operands[1].reg << 16;
11350 inst.instruction = THUMB_OP16 (inst.instruction);
11351 inst.instruction |= inst.operands[0].reg;
11352 inst.instruction |= inst.operands[1].reg << 3;
11357 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11359 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11361 inst.instruction = THUMB_OP16 (inst.instruction);
11362 inst.instruction |= inst.operands[0].reg;
11363 inst.instruction |= inst.operands[1].reg << 3;
11372 Rd = inst.operands[0].reg;
11373 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11375 reject_bad_reg (Rd);
11376 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11377 reject_bad_reg (Rn);
11379 inst.instruction |= Rd << 8;
11380 inst.instruction |= Rn << 16;
11382 if (!inst.operands[2].isreg)
11384 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11385 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11391 Rm = inst.operands[2].reg;
11392 reject_bad_reg (Rm);
11394 constraint (inst.operands[2].shifted
11395 && inst.operands[2].immisreg,
11396 _("shift must be constant"));
11397 encode_thumb32_shifted_operand (2);
11404 unsigned Rd, Rn, Rm;
11406 Rd = inst.operands[0].reg;
11407 Rn = inst.operands[1].reg;
11408 Rm = inst.operands[2].reg;
11410 reject_bad_reg (Rd);
11411 reject_bad_reg (Rn);
11412 reject_bad_reg (Rm);
11414 inst.instruction |= Rd << 8;
11415 inst.instruction |= Rn << 16;
11416 inst.instruction |= Rm;
11417 if (inst.operands[3].present)
11419 unsigned int val = inst.reloc.exp.X_add_number;
11420 constraint (inst.reloc.exp.X_op != O_constant,
11421 _("expression too complex"));
11422 inst.instruction |= (val & 0x1c) << 10;
11423 inst.instruction |= (val & 0x03) << 6;
11430 if (!inst.operands[3].present)
11434 inst.instruction &= ~0x00000020;
11436 /* PR 10168. Swap the Rm and Rn registers. */
11437 Rtmp = inst.operands[1].reg;
11438 inst.operands[1].reg = inst.operands[2].reg;
11439 inst.operands[2].reg = Rtmp;
11447 if (inst.operands[0].immisreg)
11448 reject_bad_reg (inst.operands[0].imm);
11450 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11454 do_t_push_pop (void)
11458 constraint (inst.operands[0].writeback,
11459 _("push/pop do not support {reglist}^"));
11460 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11461 _("expression too complex"));
11463 mask = inst.operands[0].imm;
11464 if ((mask & ~0xff) == 0)
11465 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
11466 else if ((inst.instruction == T_MNEM_push
11467 && (mask & ~0xff) == 1 << REG_LR)
11468 || (inst.instruction == T_MNEM_pop
11469 && (mask & ~0xff) == 1 << REG_PC))
11471 inst.instruction = THUMB_OP16 (inst.instruction);
11472 inst.instruction |= THUMB_PP_PC_LR;
11473 inst.instruction |= mask & 0xff;
11475 else if (unified_syntax)
11477 inst.instruction = THUMB_OP32 (inst.instruction);
11478 encode_thumb2_ldmstm (13, mask, TRUE);
11482 inst.error = _("invalid register list to push/pop instruction");
11492 Rd = inst.operands[0].reg;
11493 Rm = inst.operands[1].reg;
11495 reject_bad_reg (Rd);
11496 reject_bad_reg (Rm);
11498 inst.instruction |= Rd << 8;
11499 inst.instruction |= Rm << 16;
11500 inst.instruction |= Rm;
11508 Rd = inst.operands[0].reg;
11509 Rm = inst.operands[1].reg;
11511 reject_bad_reg (Rd);
11512 reject_bad_reg (Rm);
11514 if (Rd <= 7 && Rm <= 7
11515 && inst.size_req != 4)
11517 inst.instruction = THUMB_OP16 (inst.instruction);
11518 inst.instruction |= Rd;
11519 inst.instruction |= Rm << 3;
11521 else if (unified_syntax)
11523 inst.instruction = THUMB_OP32 (inst.instruction);
11524 inst.instruction |= Rd << 8;
11525 inst.instruction |= Rm << 16;
11526 inst.instruction |= Rm;
11529 inst.error = BAD_HIREG;
11537 Rd = inst.operands[0].reg;
11538 Rm = inst.operands[1].reg;
11540 reject_bad_reg (Rd);
11541 reject_bad_reg (Rm);
11543 inst.instruction |= Rd << 8;
11544 inst.instruction |= Rm;
11552 Rd = inst.operands[0].reg;
11553 Rs = (inst.operands[1].present
11554 ? inst.operands[1].reg /* Rd, Rs, foo */
11555 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11557 reject_bad_reg (Rd);
11558 reject_bad_reg (Rs);
11559 if (inst.operands[2].isreg)
11560 reject_bad_reg (inst.operands[2].reg);
11562 inst.instruction |= Rd << 8;
11563 inst.instruction |= Rs << 16;
11564 if (!inst.operands[2].isreg)
11566 bfd_boolean narrow;
11568 if ((inst.instruction & 0x00100000) != 0)
11569 narrow = !in_it_block ();
11571 narrow = in_it_block ();
11573 if (Rd > 7 || Rs > 7)
11576 if (inst.size_req == 4 || !unified_syntax)
11579 if (inst.reloc.exp.X_op != O_constant
11580 || inst.reloc.exp.X_add_number != 0)
11583 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11584 relaxation, but it doesn't seem worth the hassle. */
11587 inst.reloc.type = BFD_RELOC_UNUSED;
11588 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11589 inst.instruction |= Rs << 3;
11590 inst.instruction |= Rd;
11594 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11595 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11599 encode_thumb32_shifted_operand (2);
11605 set_it_insn_type (OUTSIDE_IT_INSN);
11606 if (inst.operands[0].imm)
11607 inst.instruction |= 0x8;
11613 if (!inst.operands[1].present)
11614 inst.operands[1].reg = inst.operands[0].reg;
11616 if (unified_syntax)
11618 bfd_boolean narrow;
11621 switch (inst.instruction)
11624 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11626 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11628 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11630 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11634 if (THUMB_SETS_FLAGS (inst.instruction))
11635 narrow = !in_it_block ();
11637 narrow = in_it_block ();
11638 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11640 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11642 if (inst.operands[2].isreg
11643 && (inst.operands[1].reg != inst.operands[0].reg
11644 || inst.operands[2].reg > 7))
11646 if (inst.size_req == 4)
11649 reject_bad_reg (inst.operands[0].reg);
11650 reject_bad_reg (inst.operands[1].reg);
11654 if (inst.operands[2].isreg)
11656 reject_bad_reg (inst.operands[2].reg);
11657 inst.instruction = THUMB_OP32 (inst.instruction);
11658 inst.instruction |= inst.operands[0].reg << 8;
11659 inst.instruction |= inst.operands[1].reg << 16;
11660 inst.instruction |= inst.operands[2].reg;
11662 /* PR 12854: Error on extraneous shifts. */
11663 constraint (inst.operands[2].shifted,
11664 _("extraneous shift as part of operand to shift insn"));
11668 inst.operands[1].shifted = 1;
11669 inst.operands[1].shift_kind = shift_kind;
11670 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11671 ? T_MNEM_movs : T_MNEM_mov);
11672 inst.instruction |= inst.operands[0].reg << 8;
11673 encode_thumb32_shifted_operand (1);
11674 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11675 inst.reloc.type = BFD_RELOC_UNUSED;
11680 if (inst.operands[2].isreg)
11682 switch (shift_kind)
11684 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11685 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11686 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11687 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
11691 inst.instruction |= inst.operands[0].reg;
11692 inst.instruction |= inst.operands[2].reg << 3;
11694 /* PR 12854: Error on extraneous shifts. */
11695 constraint (inst.operands[2].shifted,
11696 _("extraneous shift as part of operand to shift insn"));
11700 switch (shift_kind)
11702 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11703 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11704 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11707 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11708 inst.instruction |= inst.operands[0].reg;
11709 inst.instruction |= inst.operands[1].reg << 3;
11715 constraint (inst.operands[0].reg > 7
11716 || inst.operands[1].reg > 7, BAD_HIREG);
11717 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11719 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11721 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11722 constraint (inst.operands[0].reg != inst.operands[1].reg,
11723 _("source1 and dest must be same register"));
11725 switch (inst.instruction)
11727 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11728 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11729 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11730 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11734 inst.instruction |= inst.operands[0].reg;
11735 inst.instruction |= inst.operands[2].reg << 3;
11737 /* PR 12854: Error on extraneous shifts. */
11738 constraint (inst.operands[2].shifted,
11739 _("extraneous shift as part of operand to shift insn"));
11743 switch (inst.instruction)
11745 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11746 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11747 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11748 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11751 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11752 inst.instruction |= inst.operands[0].reg;
11753 inst.instruction |= inst.operands[1].reg << 3;
11761 unsigned Rd, Rn, Rm;
11763 Rd = inst.operands[0].reg;
11764 Rn = inst.operands[1].reg;
11765 Rm = inst.operands[2].reg;
11767 reject_bad_reg (Rd);
11768 reject_bad_reg (Rn);
11769 reject_bad_reg (Rm);
11771 inst.instruction |= Rd << 8;
11772 inst.instruction |= Rn << 16;
11773 inst.instruction |= Rm;
11779 unsigned Rd, Rn, Rm;
11781 Rd = inst.operands[0].reg;
11782 Rm = inst.operands[1].reg;
11783 Rn = inst.operands[2].reg;
11785 reject_bad_reg (Rd);
11786 reject_bad_reg (Rn);
11787 reject_bad_reg (Rm);
11789 inst.instruction |= Rd << 8;
11790 inst.instruction |= Rn << 16;
11791 inst.instruction |= Rm;
11797 unsigned int value = inst.reloc.exp.X_add_number;
11798 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
11799 _("SMC is not permitted on this architecture"));
11800 constraint (inst.reloc.exp.X_op != O_constant,
11801 _("expression too complex"));
11802 inst.reloc.type = BFD_RELOC_UNUSED;
11803 inst.instruction |= (value & 0xf000) >> 12;
11804 inst.instruction |= (value & 0x0ff0);
11805 inst.instruction |= (value & 0x000f) << 16;
11811 unsigned int value = inst.reloc.exp.X_add_number;
11813 inst.reloc.type = BFD_RELOC_UNUSED;
11814 inst.instruction |= (value & 0x0fff);
11815 inst.instruction |= (value & 0xf000) << 4;
11819 do_t_ssat_usat (int bias)
11823 Rd = inst.operands[0].reg;
11824 Rn = inst.operands[2].reg;
11826 reject_bad_reg (Rd);
11827 reject_bad_reg (Rn);
11829 inst.instruction |= Rd << 8;
11830 inst.instruction |= inst.operands[1].imm - bias;
11831 inst.instruction |= Rn << 16;
11833 if (inst.operands[3].present)
11835 offsetT shift_amount = inst.reloc.exp.X_add_number;
11837 inst.reloc.type = BFD_RELOC_UNUSED;
11839 constraint (inst.reloc.exp.X_op != O_constant,
11840 _("expression too complex"));
11842 if (shift_amount != 0)
11844 constraint (shift_amount > 31,
11845 _("shift expression is too large"));
11847 if (inst.operands[3].shift_kind == SHIFT_ASR)
11848 inst.instruction |= 0x00200000; /* sh bit. */
11850 inst.instruction |= (shift_amount & 0x1c) << 10;
11851 inst.instruction |= (shift_amount & 0x03) << 6;
11859 do_t_ssat_usat (1);
11867 Rd = inst.operands[0].reg;
11868 Rn = inst.operands[2].reg;
11870 reject_bad_reg (Rd);
11871 reject_bad_reg (Rn);
11873 inst.instruction |= Rd << 8;
11874 inst.instruction |= inst.operands[1].imm - 1;
11875 inst.instruction |= Rn << 16;
11881 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
11882 || inst.operands[2].postind || inst.operands[2].writeback
11883 || inst.operands[2].immisreg || inst.operands[2].shifted
11884 || inst.operands[2].negative,
11887 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
11889 inst.instruction |= inst.operands[0].reg << 8;
11890 inst.instruction |= inst.operands[1].reg << 12;
11891 inst.instruction |= inst.operands[2].reg << 16;
11892 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11898 if (!inst.operands[2].present)
11899 inst.operands[2].reg = inst.operands[1].reg + 1;
11901 constraint (inst.operands[0].reg == inst.operands[1].reg
11902 || inst.operands[0].reg == inst.operands[2].reg
11903 || inst.operands[0].reg == inst.operands[3].reg,
11906 inst.instruction |= inst.operands[0].reg;
11907 inst.instruction |= inst.operands[1].reg << 12;
11908 inst.instruction |= inst.operands[2].reg << 8;
11909 inst.instruction |= inst.operands[3].reg << 16;
11915 unsigned Rd, Rn, Rm;
11917 Rd = inst.operands[0].reg;
11918 Rn = inst.operands[1].reg;
11919 Rm = inst.operands[2].reg;
11921 reject_bad_reg (Rd);
11922 reject_bad_reg (Rn);
11923 reject_bad_reg (Rm);
11925 inst.instruction |= Rd << 8;
11926 inst.instruction |= Rn << 16;
11927 inst.instruction |= Rm;
11928 inst.instruction |= inst.operands[3].imm << 4;
11936 Rd = inst.operands[0].reg;
11937 Rm = inst.operands[1].reg;
11939 reject_bad_reg (Rd);
11940 reject_bad_reg (Rm);
11942 if (inst.instruction <= 0xffff
11943 && inst.size_req != 4
11944 && Rd <= 7 && Rm <= 7
11945 && (!inst.operands[2].present || inst.operands[2].imm == 0))
11947 inst.instruction = THUMB_OP16 (inst.instruction);
11948 inst.instruction |= Rd;
11949 inst.instruction |= Rm << 3;
11951 else if (unified_syntax)
11953 if (inst.instruction <= 0xffff)
11954 inst.instruction = THUMB_OP32 (inst.instruction);
11955 inst.instruction |= Rd << 8;
11956 inst.instruction |= Rm;
11957 inst.instruction |= inst.operands[2].imm << 4;
11961 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
11962 _("Thumb encoding does not support rotation"));
11963 constraint (1, BAD_HIREG);
11970 /* We have to do the following check manually as ARM_EXT_OS only applies
11972 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
11974 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
11975 /* This only applies to the v6m howver, not later architectures. */
11976 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
11977 as_bad (_("SVC is not permitted on this architecture"));
11978 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
11981 inst.reloc.type = BFD_RELOC_ARM_SWI;
11990 half = (inst.instruction & 0x10) != 0;
11991 set_it_insn_type_last ();
11992 constraint (inst.operands[0].immisreg,
11993 _("instruction requires register index"));
11995 Rn = inst.operands[0].reg;
11996 Rm = inst.operands[0].imm;
11998 constraint (Rn == REG_SP, BAD_SP);
11999 reject_bad_reg (Rm);
12001 constraint (!half && inst.operands[0].shifted,
12002 _("instruction does not allow shifted index"));
12003 inst.instruction |= (Rn << 16) | Rm;
12009 do_t_ssat_usat (0);
12017 Rd = inst.operands[0].reg;
12018 Rn = inst.operands[2].reg;
12020 reject_bad_reg (Rd);
12021 reject_bad_reg (Rn);
12023 inst.instruction |= Rd << 8;
12024 inst.instruction |= inst.operands[1].imm;
12025 inst.instruction |= Rn << 16;
12028 /* Neon instruction encoder helpers. */
12030 /* Encodings for the different types for various Neon opcodes. */
12032 /* An "invalid" code for the following tables. */
12035 struct neon_tab_entry
12038 unsigned float_or_poly;
12039 unsigned scalar_or_imm;
12042 /* Map overloaded Neon opcodes to their respective encodings. */
12043 #define NEON_ENC_TAB \
12044 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12045 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12046 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12047 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12048 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12049 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12050 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12051 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12052 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12053 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12054 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12055 /* Register variants of the following two instructions are encoded as
12056 vcge / vcgt with the operands reversed. */ \
12057 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12058 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12059 X(vfma, N_INV, 0x0000c10, N_INV), \
12060 X(vfms, N_INV, 0x0200c10, N_INV), \
12061 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12062 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12063 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12064 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12065 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12066 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12067 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12068 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12069 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12070 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12071 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12072 X(vshl, 0x0000400, N_INV, 0x0800510), \
12073 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12074 X(vand, 0x0000110, N_INV, 0x0800030), \
12075 X(vbic, 0x0100110, N_INV, 0x0800030), \
12076 X(veor, 0x1000110, N_INV, N_INV), \
12077 X(vorn, 0x0300110, N_INV, 0x0800010), \
12078 X(vorr, 0x0200110, N_INV, 0x0800010), \
12079 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12080 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12081 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12082 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12083 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12084 X(vst1, 0x0000000, 0x0800000, N_INV), \
12085 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12086 X(vst2, 0x0000100, 0x0800100, N_INV), \
12087 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12088 X(vst3, 0x0000200, 0x0800200, N_INV), \
12089 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12090 X(vst4, 0x0000300, 0x0800300, N_INV), \
12091 X(vmovn, 0x1b20200, N_INV, N_INV), \
12092 X(vtrn, 0x1b20080, N_INV, N_INV), \
12093 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12094 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12095 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12096 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12097 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12098 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12099 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12100 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12101 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12102 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12103 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12107 #define X(OPC,I,F,S) N_MNEM_##OPC
12112 static const struct neon_tab_entry neon_enc_tab[] =
12114 #define X(OPC,I,F,S) { (I), (F), (S) }
12119 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12120 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12121 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12122 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12123 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12124 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12125 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12126 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12127 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12128 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12129 #define NEON_ENC_SINGLE_(X) \
12130 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12131 #define NEON_ENC_DOUBLE_(X) \
12132 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12134 #define NEON_ENCODE(type, inst) \
12137 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12138 inst.is_neon = 1; \
12142 #define check_neon_suffixes \
12145 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12147 as_bad (_("invalid neon suffix for non neon instruction")); \
12153 /* Define shapes for instruction operands. The following mnemonic characters
12154 are used in this table:
12156 F - VFP S<n> register
12157 D - Neon D<n> register
12158 Q - Neon Q<n> register
12162 L - D<n> register list
12164 This table is used to generate various data:
12165 - enumerations of the form NS_DDR to be used as arguments to
12167 - a table classifying shapes into single, double, quad, mixed.
12168 - a table used to drive neon_select_shape. */
12170 #define NEON_SHAPE_DEF \
12171 X(3, (D, D, D), DOUBLE), \
12172 X(3, (Q, Q, Q), QUAD), \
12173 X(3, (D, D, I), DOUBLE), \
12174 X(3, (Q, Q, I), QUAD), \
12175 X(3, (D, D, S), DOUBLE), \
12176 X(3, (Q, Q, S), QUAD), \
12177 X(2, (D, D), DOUBLE), \
12178 X(2, (Q, Q), QUAD), \
12179 X(2, (D, S), DOUBLE), \
12180 X(2, (Q, S), QUAD), \
12181 X(2, (D, R), DOUBLE), \
12182 X(2, (Q, R), QUAD), \
12183 X(2, (D, I), DOUBLE), \
12184 X(2, (Q, I), QUAD), \
12185 X(3, (D, L, D), DOUBLE), \
12186 X(2, (D, Q), MIXED), \
12187 X(2, (Q, D), MIXED), \
12188 X(3, (D, Q, I), MIXED), \
12189 X(3, (Q, D, I), MIXED), \
12190 X(3, (Q, D, D), MIXED), \
12191 X(3, (D, Q, Q), MIXED), \
12192 X(3, (Q, Q, D), MIXED), \
12193 X(3, (Q, D, S), MIXED), \
12194 X(3, (D, Q, S), MIXED), \
12195 X(4, (D, D, D, I), DOUBLE), \
12196 X(4, (Q, Q, Q, I), QUAD), \
12197 X(2, (F, F), SINGLE), \
12198 X(3, (F, F, F), SINGLE), \
12199 X(2, (F, I), SINGLE), \
12200 X(2, (F, D), MIXED), \
12201 X(2, (D, F), MIXED), \
12202 X(3, (F, F, I), MIXED), \
12203 X(4, (R, R, F, F), SINGLE), \
12204 X(4, (F, F, R, R), SINGLE), \
12205 X(3, (D, R, R), DOUBLE), \
12206 X(3, (R, R, D), DOUBLE), \
12207 X(2, (S, R), SINGLE), \
12208 X(2, (R, S), SINGLE), \
12209 X(2, (F, R), SINGLE), \
12210 X(2, (R, F), SINGLE)
12212 #define S2(A,B) NS_##A##B
12213 #define S3(A,B,C) NS_##A##B##C
12214 #define S4(A,B,C,D) NS_##A##B##C##D
12216 #define X(N, L, C) S##N L
12229 enum neon_shape_class
12237 #define X(N, L, C) SC_##C
12239 static enum neon_shape_class neon_shape_class[] =
12257 /* Register widths of above. */
12258 static unsigned neon_shape_el_size[] =
12269 struct neon_shape_info
12272 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12275 #define S2(A,B) { SE_##A, SE_##B }
12276 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12277 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12279 #define X(N, L, C) { N, S##N L }
12281 static struct neon_shape_info neon_shape_tab[] =
12291 /* Bit masks used in type checking given instructions.
12292 'N_EQK' means the type must be the same as (or based on in some way) the key
12293 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12294 set, various other bits can be set as well in order to modify the meaning of
12295 the type constraint. */
12297 enum neon_type_mask
12320 N_KEY = 0x1000000, /* Key element (main type specifier). */
12321 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
12322 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
12323 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12324 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12325 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12326 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12327 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12328 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12329 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12331 N_MAX_NONSPECIAL = N_F64
12334 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12336 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12337 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12338 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12339 #define N_SUF_32 (N_SU_32 | N_F32)
12340 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12341 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12343 /* Pass this as the first type argument to neon_check_type to ignore types
12345 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12347 /* Select a "shape" for the current instruction (describing register types or
12348 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12349 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12350 function of operand parsing, so this function doesn't need to be called.
12351 Shapes should be listed in order of decreasing length. */
12353 static enum neon_shape
12354 neon_select_shape (enum neon_shape shape, ...)
12357 enum neon_shape first_shape = shape;
12359 /* Fix missing optional operands. FIXME: we don't know at this point how
12360 many arguments we should have, so this makes the assumption that we have
12361 > 1. This is true of all current Neon opcodes, I think, but may not be
12362 true in the future. */
12363 if (!inst.operands[1].present)
12364 inst.operands[1] = inst.operands[0];
12366 va_start (ap, shape);
12368 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
12373 for (j = 0; j < neon_shape_tab[shape].els; j++)
12375 if (!inst.operands[j].present)
12381 switch (neon_shape_tab[shape].el[j])
12384 if (!(inst.operands[j].isreg
12385 && inst.operands[j].isvec
12386 && inst.operands[j].issingle
12387 && !inst.operands[j].isquad))
12392 if (!(inst.operands[j].isreg
12393 && inst.operands[j].isvec
12394 && !inst.operands[j].isquad
12395 && !inst.operands[j].issingle))
12400 if (!(inst.operands[j].isreg
12401 && !inst.operands[j].isvec))
12406 if (!(inst.operands[j].isreg
12407 && inst.operands[j].isvec
12408 && inst.operands[j].isquad
12409 && !inst.operands[j].issingle))
12414 if (!(!inst.operands[j].isreg
12415 && !inst.operands[j].isscalar))
12420 if (!(!inst.operands[j].isreg
12421 && inst.operands[j].isscalar))
12431 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12432 /* We've matched all the entries in the shape table, and we don't
12433 have any left over operands which have not been matched. */
12439 if (shape == NS_NULL && first_shape != NS_NULL)
12440 first_error (_("invalid instruction shape"));
12445 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12446 means the Q bit should be set). */
12449 neon_quad (enum neon_shape shape)
12451 return neon_shape_class[shape] == SC_QUAD;
12455 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
12458 /* Allow modification to be made to types which are constrained to be
12459 based on the key element, based on bits set alongside N_EQK. */
12460 if ((typebits & N_EQK) != 0)
12462 if ((typebits & N_HLF) != 0)
12464 else if ((typebits & N_DBL) != 0)
12466 if ((typebits & N_SGN) != 0)
12467 *g_type = NT_signed;
12468 else if ((typebits & N_UNS) != 0)
12469 *g_type = NT_unsigned;
12470 else if ((typebits & N_INT) != 0)
12471 *g_type = NT_integer;
12472 else if ((typebits & N_FLT) != 0)
12473 *g_type = NT_float;
12474 else if ((typebits & N_SIZ) != 0)
12475 *g_type = NT_untyped;
12479 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12480 operand type, i.e. the single type specified in a Neon instruction when it
12481 is the only one given. */
12483 static struct neon_type_el
12484 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12486 struct neon_type_el dest = *key;
12488 gas_assert ((thisarg & N_EQK) != 0);
12490 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12495 /* Convert Neon type and size into compact bitmask representation. */
12497 static enum neon_type_mask
12498 type_chk_of_el_type (enum neon_el_type type, unsigned size)
12505 case 8: return N_8;
12506 case 16: return N_16;
12507 case 32: return N_32;
12508 case 64: return N_64;
12516 case 8: return N_I8;
12517 case 16: return N_I16;
12518 case 32: return N_I32;
12519 case 64: return N_I64;
12527 case 16: return N_F16;
12528 case 32: return N_F32;
12529 case 64: return N_F64;
12537 case 8: return N_P8;
12538 case 16: return N_P16;
12546 case 8: return N_S8;
12547 case 16: return N_S16;
12548 case 32: return N_S32;
12549 case 64: return N_S64;
12557 case 8: return N_U8;
12558 case 16: return N_U16;
12559 case 32: return N_U32;
12560 case 64: return N_U64;
12571 /* Convert compact Neon bitmask type representation to a type and size. Only
12572 handles the case where a single bit is set in the mask. */
12575 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
12576 enum neon_type_mask mask)
12578 if ((mask & N_EQK) != 0)
12581 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12583 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_P16)) != 0)
12585 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
12587 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64)) != 0)
12592 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12594 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
12595 *type = NT_unsigned;
12596 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
12597 *type = NT_integer;
12598 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
12599 *type = NT_untyped;
12600 else if ((mask & (N_P8 | N_P16)) != 0)
12602 else if ((mask & (N_F32 | N_F64)) != 0)
12610 /* Modify a bitmask of allowed types. This is only needed for type
12614 modify_types_allowed (unsigned allowed, unsigned mods)
12617 enum neon_el_type type;
12623 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12625 if (el_type_of_type_chk (&type, &size,
12626 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12628 neon_modify_type_size (mods, &type, &size);
12629 destmask |= type_chk_of_el_type (type, size);
12636 /* Check type and return type classification.
12637 The manual states (paraphrase): If one datatype is given, it indicates the
12639 - the second operand, if there is one
12640 - the operand, if there is no second operand
12641 - the result, if there are no operands.
12642 This isn't quite good enough though, so we use a concept of a "key" datatype
12643 which is set on a per-instruction basis, which is the one which matters when
12644 only one data type is written.
12645 Note: this function has side-effects (e.g. filling in missing operands). All
12646 Neon instructions should call it before performing bit encoding. */
12648 static struct neon_type_el
12649 neon_check_type (unsigned els, enum neon_shape ns, ...)
12652 unsigned i, pass, key_el = 0;
12653 unsigned types[NEON_MAX_TYPE_ELS];
12654 enum neon_el_type k_type = NT_invtype;
12655 unsigned k_size = -1u;
12656 struct neon_type_el badtype = {NT_invtype, -1};
12657 unsigned key_allowed = 0;
12659 /* Optional registers in Neon instructions are always (not) in operand 1.
12660 Fill in the missing operand here, if it was omitted. */
12661 if (els > 1 && !inst.operands[1].present)
12662 inst.operands[1] = inst.operands[0];
12664 /* Suck up all the varargs. */
12666 for (i = 0; i < els; i++)
12668 unsigned thisarg = va_arg (ap, unsigned);
12669 if (thisarg == N_IGNORE_TYPE)
12674 types[i] = thisarg;
12675 if ((thisarg & N_KEY) != 0)
12680 if (inst.vectype.elems > 0)
12681 for (i = 0; i < els; i++)
12682 if (inst.operands[i].vectype.type != NT_invtype)
12684 first_error (_("types specified in both the mnemonic and operands"));
12688 /* Duplicate inst.vectype elements here as necessary.
12689 FIXME: No idea if this is exactly the same as the ARM assembler,
12690 particularly when an insn takes one register and one non-register
12692 if (inst.vectype.elems == 1 && els > 1)
12695 inst.vectype.elems = els;
12696 inst.vectype.el[key_el] = inst.vectype.el[0];
12697 for (j = 0; j < els; j++)
12699 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12702 else if (inst.vectype.elems == 0 && els > 0)
12705 /* No types were given after the mnemonic, so look for types specified
12706 after each operand. We allow some flexibility here; as long as the
12707 "key" operand has a type, we can infer the others. */
12708 for (j = 0; j < els; j++)
12709 if (inst.operands[j].vectype.type != NT_invtype)
12710 inst.vectype.el[j] = inst.operands[j].vectype;
12712 if (inst.operands[key_el].vectype.type != NT_invtype)
12714 for (j = 0; j < els; j++)
12715 if (inst.operands[j].vectype.type == NT_invtype)
12716 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12721 first_error (_("operand types can't be inferred"));
12725 else if (inst.vectype.elems != els)
12727 first_error (_("type specifier has the wrong number of parts"));
12731 for (pass = 0; pass < 2; pass++)
12733 for (i = 0; i < els; i++)
12735 unsigned thisarg = types[i];
12736 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12737 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12738 enum neon_el_type g_type = inst.vectype.el[i].type;
12739 unsigned g_size = inst.vectype.el[i].size;
12741 /* Decay more-specific signed & unsigned types to sign-insensitive
12742 integer types if sign-specific variants are unavailable. */
12743 if ((g_type == NT_signed || g_type == NT_unsigned)
12744 && (types_allowed & N_SU_ALL) == 0)
12745 g_type = NT_integer;
12747 /* If only untyped args are allowed, decay any more specific types to
12748 them. Some instructions only care about signs for some element
12749 sizes, so handle that properly. */
12750 if ((g_size == 8 && (types_allowed & N_8) != 0)
12751 || (g_size == 16 && (types_allowed & N_16) != 0)
12752 || (g_size == 32 && (types_allowed & N_32) != 0)
12753 || (g_size == 64 && (types_allowed & N_64) != 0))
12754 g_type = NT_untyped;
12758 if ((thisarg & N_KEY) != 0)
12762 key_allowed = thisarg & ~N_KEY;
12767 if ((thisarg & N_VFP) != 0)
12769 enum neon_shape_el regshape;
12770 unsigned regwidth, match;
12772 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12775 first_error (_("invalid instruction shape"));
12778 regshape = neon_shape_tab[ns].el[i];
12779 regwidth = neon_shape_el_size[regshape];
12781 /* In VFP mode, operands must match register widths. If we
12782 have a key operand, use its width, else use the width of
12783 the current operand. */
12789 if (regwidth != match)
12791 first_error (_("operand size must match register width"));
12796 if ((thisarg & N_EQK) == 0)
12798 unsigned given_type = type_chk_of_el_type (g_type, g_size);
12800 if ((given_type & types_allowed) == 0)
12802 first_error (_("bad type in Neon instruction"));
12808 enum neon_el_type mod_k_type = k_type;
12809 unsigned mod_k_size = k_size;
12810 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
12811 if (g_type != mod_k_type || g_size != mod_k_size)
12813 first_error (_("inconsistent types in Neon instruction"));
12821 return inst.vectype.el[key_el];
12824 /* Neon-style VFP instruction forwarding. */
12826 /* Thumb VFP instructions have 0xE in the condition field. */
12829 do_vfp_cond_or_thumb (void)
12834 inst.instruction |= 0xe0000000;
12836 inst.instruction |= inst.cond << 28;
12839 /* Look up and encode a simple mnemonic, for use as a helper function for the
12840 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12841 etc. It is assumed that operand parsing has already been done, and that the
12842 operands are in the form expected by the given opcode (this isn't necessarily
12843 the same as the form in which they were parsed, hence some massaging must
12844 take place before this function is called).
12845 Checks current arch version against that in the looked-up opcode. */
12848 do_vfp_nsyn_opcode (const char *opname)
12850 const struct asm_opcode *opcode;
12852 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
12857 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
12858 thumb_mode ? *opcode->tvariant : *opcode->avariant),
12865 inst.instruction = opcode->tvalue;
12866 opcode->tencode ();
12870 inst.instruction = (inst.cond << 28) | opcode->avalue;
12871 opcode->aencode ();
12876 do_vfp_nsyn_add_sub (enum neon_shape rs)
12878 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
12883 do_vfp_nsyn_opcode ("fadds");
12885 do_vfp_nsyn_opcode ("fsubs");
12890 do_vfp_nsyn_opcode ("faddd");
12892 do_vfp_nsyn_opcode ("fsubd");
12896 /* Check operand types to see if this is a VFP instruction, and if so call
12900 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
12902 enum neon_shape rs;
12903 struct neon_type_el et;
12908 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
12909 et = neon_check_type (2, rs,
12910 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12914 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
12915 et = neon_check_type (3, rs,
12916 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
12923 if (et.type != NT_invtype)
12934 do_vfp_nsyn_mla_mls (enum neon_shape rs)
12936 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
12941 do_vfp_nsyn_opcode ("fmacs");
12943 do_vfp_nsyn_opcode ("fnmacs");
12948 do_vfp_nsyn_opcode ("fmacd");
12950 do_vfp_nsyn_opcode ("fnmacd");
12955 do_vfp_nsyn_fma_fms (enum neon_shape rs)
12957 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
12962 do_vfp_nsyn_opcode ("ffmas");
12964 do_vfp_nsyn_opcode ("ffnmas");
12969 do_vfp_nsyn_opcode ("ffmad");
12971 do_vfp_nsyn_opcode ("ffnmad");
12976 do_vfp_nsyn_mul (enum neon_shape rs)
12979 do_vfp_nsyn_opcode ("fmuls");
12981 do_vfp_nsyn_opcode ("fmuld");
12985 do_vfp_nsyn_abs_neg (enum neon_shape rs)
12987 int is_neg = (inst.instruction & 0x80) != 0;
12988 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
12993 do_vfp_nsyn_opcode ("fnegs");
12995 do_vfp_nsyn_opcode ("fabss");
13000 do_vfp_nsyn_opcode ("fnegd");
13002 do_vfp_nsyn_opcode ("fabsd");
13006 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13007 insns belong to Neon, and are handled elsewhere. */
13010 do_vfp_nsyn_ldm_stm (int is_dbmode)
13012 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13016 do_vfp_nsyn_opcode ("fldmdbs");
13018 do_vfp_nsyn_opcode ("fldmias");
13023 do_vfp_nsyn_opcode ("fstmdbs");
13025 do_vfp_nsyn_opcode ("fstmias");
13030 do_vfp_nsyn_sqrt (void)
13032 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13033 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13036 do_vfp_nsyn_opcode ("fsqrts");
13038 do_vfp_nsyn_opcode ("fsqrtd");
13042 do_vfp_nsyn_div (void)
13044 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13045 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13046 N_F32 | N_F64 | N_KEY | N_VFP);
13049 do_vfp_nsyn_opcode ("fdivs");
13051 do_vfp_nsyn_opcode ("fdivd");
13055 do_vfp_nsyn_nmul (void)
13057 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13058 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13059 N_F32 | N_F64 | N_KEY | N_VFP);
13063 NEON_ENCODE (SINGLE, inst);
13064 do_vfp_sp_dyadic ();
13068 NEON_ENCODE (DOUBLE, inst);
13069 do_vfp_dp_rd_rn_rm ();
13071 do_vfp_cond_or_thumb ();
13075 do_vfp_nsyn_cmp (void)
13077 if (inst.operands[1].isreg)
13079 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13080 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13084 NEON_ENCODE (SINGLE, inst);
13085 do_vfp_sp_monadic ();
13089 NEON_ENCODE (DOUBLE, inst);
13090 do_vfp_dp_rd_rm ();
13095 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13096 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13098 switch (inst.instruction & 0x0fffffff)
13101 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13104 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13112 NEON_ENCODE (SINGLE, inst);
13113 do_vfp_sp_compare_z ();
13117 NEON_ENCODE (DOUBLE, inst);
13121 do_vfp_cond_or_thumb ();
13125 nsyn_insert_sp (void)
13127 inst.operands[1] = inst.operands[0];
13128 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
13129 inst.operands[0].reg = REG_SP;
13130 inst.operands[0].isreg = 1;
13131 inst.operands[0].writeback = 1;
13132 inst.operands[0].present = 1;
13136 do_vfp_nsyn_push (void)
13139 if (inst.operands[1].issingle)
13140 do_vfp_nsyn_opcode ("fstmdbs");
13142 do_vfp_nsyn_opcode ("fstmdbd");
13146 do_vfp_nsyn_pop (void)
13149 if (inst.operands[1].issingle)
13150 do_vfp_nsyn_opcode ("fldmias");
13152 do_vfp_nsyn_opcode ("fldmiad");
13155 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13156 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13159 neon_dp_fixup (struct arm_it* insn)
13161 unsigned int i = insn->instruction;
13166 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13177 insn->instruction = i;
13180 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13184 neon_logbits (unsigned x)
13186 return ffs (x) - 4;
13189 #define LOW4(R) ((R) & 0xf)
13190 #define HI1(R) (((R) >> 4) & 1)
13192 /* Encode insns with bit pattern:
13194 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13195 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13197 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13198 different meaning for some instruction. */
13201 neon_three_same (int isquad, int ubit, int size)
13203 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13204 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13205 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13206 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13207 inst.instruction |= LOW4 (inst.operands[2].reg);
13208 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13209 inst.instruction |= (isquad != 0) << 6;
13210 inst.instruction |= (ubit != 0) << 24;
13212 inst.instruction |= neon_logbits (size) << 20;
13214 neon_dp_fixup (&inst);
13217 /* Encode instructions of the form:
13219 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13220 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13222 Don't write size if SIZE == -1. */
13225 neon_two_same (int qbit, int ubit, int size)
13227 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13228 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13229 inst.instruction |= LOW4 (inst.operands[1].reg);
13230 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13231 inst.instruction |= (qbit != 0) << 6;
13232 inst.instruction |= (ubit != 0) << 24;
13235 inst.instruction |= neon_logbits (size) << 18;
13237 neon_dp_fixup (&inst);
13240 /* Neon instruction encoders, in approximate order of appearance. */
13243 do_neon_dyadic_i_su (void)
13245 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13246 struct neon_type_el et = neon_check_type (3, rs,
13247 N_EQK, N_EQK, N_SU_32 | N_KEY);
13248 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13252 do_neon_dyadic_i64_su (void)
13254 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13255 struct neon_type_el et = neon_check_type (3, rs,
13256 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13257 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13261 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
13264 unsigned size = et.size >> 3;
13265 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13266 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13267 inst.instruction |= LOW4 (inst.operands[1].reg);
13268 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13269 inst.instruction |= (isquad != 0) << 6;
13270 inst.instruction |= immbits << 16;
13271 inst.instruction |= (size >> 3) << 7;
13272 inst.instruction |= (size & 0x7) << 19;
13274 inst.instruction |= (uval != 0) << 24;
13276 neon_dp_fixup (&inst);
13280 do_neon_shl_imm (void)
13282 if (!inst.operands[2].isreg)
13284 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13285 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
13286 NEON_ENCODE (IMMED, inst);
13287 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
13291 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13292 struct neon_type_el et = neon_check_type (3, rs,
13293 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13296 /* VSHL/VQSHL 3-register variants have syntax such as:
13298 whereas other 3-register operations encoded by neon_three_same have
13301 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13303 tmp = inst.operands[2].reg;
13304 inst.operands[2].reg = inst.operands[1].reg;
13305 inst.operands[1].reg = tmp;
13306 NEON_ENCODE (INTEGER, inst);
13307 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13312 do_neon_qshl_imm (void)
13314 if (!inst.operands[2].isreg)
13316 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13317 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
13319 NEON_ENCODE (IMMED, inst);
13320 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
13321 inst.operands[2].imm);
13325 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13326 struct neon_type_el et = neon_check_type (3, rs,
13327 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
13330 /* See note in do_neon_shl_imm. */
13331 tmp = inst.operands[2].reg;
13332 inst.operands[2].reg = inst.operands[1].reg;
13333 inst.operands[1].reg = tmp;
13334 NEON_ENCODE (INTEGER, inst);
13335 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13340 do_neon_rshl (void)
13342 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13343 struct neon_type_el et = neon_check_type (3, rs,
13344 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13347 tmp = inst.operands[2].reg;
13348 inst.operands[2].reg = inst.operands[1].reg;
13349 inst.operands[1].reg = tmp;
13350 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13354 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13356 /* Handle .I8 pseudo-instructions. */
13359 /* Unfortunately, this will make everything apart from zero out-of-range.
13360 FIXME is this the intended semantics? There doesn't seem much point in
13361 accepting .I8 if so. */
13362 immediate |= immediate << 8;
13368 if (immediate == (immediate & 0x000000ff))
13370 *immbits = immediate;
13373 else if (immediate == (immediate & 0x0000ff00))
13375 *immbits = immediate >> 8;
13378 else if (immediate == (immediate & 0x00ff0000))
13380 *immbits = immediate >> 16;
13383 else if (immediate == (immediate & 0xff000000))
13385 *immbits = immediate >> 24;
13388 if ((immediate & 0xffff) != (immediate >> 16))
13389 goto bad_immediate;
13390 immediate &= 0xffff;
13393 if (immediate == (immediate & 0x000000ff))
13395 *immbits = immediate;
13398 else if (immediate == (immediate & 0x0000ff00))
13400 *immbits = immediate >> 8;
13405 first_error (_("immediate value out of range"));
13409 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13413 neon_bits_same_in_bytes (unsigned imm)
13415 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
13416 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13417 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13418 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
13421 /* For immediate of above form, return 0bABCD. */
13424 neon_squash_bits (unsigned imm)
13426 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
13427 | ((imm & 0x01000000) >> 21);
13430 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13433 neon_qfloat_bits (unsigned imm)
13435 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
13438 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13439 the instruction. *OP is passed as the initial value of the op field, and
13440 may be set to a different value depending on the constant (i.e.
13441 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13442 MVN). If the immediate looks like a repeated pattern then also
13443 try smaller element sizes. */
13446 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13447 unsigned *immbits, int *op, int size,
13448 enum neon_el_type type)
13450 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13452 if (type == NT_float && !float_p)
13455 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13457 if (size != 32 || *op == 1)
13459 *immbits = neon_qfloat_bits (immlo);
13465 if (neon_bits_same_in_bytes (immhi)
13466 && neon_bits_same_in_bytes (immlo))
13470 *immbits = (neon_squash_bits (immhi) << 4)
13471 | neon_squash_bits (immlo);
13476 if (immhi != immlo)
13482 if (immlo == (immlo & 0x000000ff))
13487 else if (immlo == (immlo & 0x0000ff00))
13489 *immbits = immlo >> 8;
13492 else if (immlo == (immlo & 0x00ff0000))
13494 *immbits = immlo >> 16;
13497 else if (immlo == (immlo & 0xff000000))
13499 *immbits = immlo >> 24;
13502 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13504 *immbits = (immlo >> 8) & 0xff;
13507 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13509 *immbits = (immlo >> 16) & 0xff;
13513 if ((immlo & 0xffff) != (immlo >> 16))
13520 if (immlo == (immlo & 0x000000ff))
13525 else if (immlo == (immlo & 0x0000ff00))
13527 *immbits = immlo >> 8;
13531 if ((immlo & 0xff) != (immlo >> 8))
13536 if (immlo == (immlo & 0x000000ff))
13538 /* Don't allow MVN with 8-bit immediate. */
13548 /* Write immediate bits [7:0] to the following locations:
13550 |28/24|23 19|18 16|15 4|3 0|
13551 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13553 This function is used by VMOV/VMVN/VORR/VBIC. */
13556 neon_write_immbits (unsigned immbits)
13558 inst.instruction |= immbits & 0xf;
13559 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13560 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13563 /* Invert low-order SIZE bits of XHI:XLO. */
13566 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13568 unsigned immlo = xlo ? *xlo : 0;
13569 unsigned immhi = xhi ? *xhi : 0;
13574 immlo = (~immlo) & 0xff;
13578 immlo = (~immlo) & 0xffff;
13582 immhi = (~immhi) & 0xffffffff;
13583 /* fall through. */
13586 immlo = (~immlo) & 0xffffffff;
13601 do_neon_logic (void)
13603 if (inst.operands[2].present && inst.operands[2].isreg)
13605 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13606 neon_check_type (3, rs, N_IGNORE_TYPE);
13607 /* U bit and size field were set as part of the bitmask. */
13608 NEON_ENCODE (INTEGER, inst);
13609 neon_three_same (neon_quad (rs), 0, -1);
13613 const int three_ops_form = (inst.operands[2].present
13614 && !inst.operands[2].isreg);
13615 const int immoperand = (three_ops_form ? 2 : 1);
13616 enum neon_shape rs = (three_ops_form
13617 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13618 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
13619 struct neon_type_el et = neon_check_type (2, rs,
13620 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
13621 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
13625 if (et.type == NT_invtype)
13628 if (three_ops_form)
13629 constraint (inst.operands[0].reg != inst.operands[1].reg,
13630 _("first and second operands shall be the same register"));
13632 NEON_ENCODE (IMMED, inst);
13634 immbits = inst.operands[immoperand].imm;
13637 /* .i64 is a pseudo-op, so the immediate must be a repeating
13639 if (immbits != (inst.operands[immoperand].regisimm ?
13640 inst.operands[immoperand].reg : 0))
13642 /* Set immbits to an invalid constant. */
13643 immbits = 0xdeadbeef;
13650 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13654 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13658 /* Pseudo-instruction for VBIC. */
13659 neon_invert_size (&immbits, 0, et.size);
13660 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13664 /* Pseudo-instruction for VORR. */
13665 neon_invert_size (&immbits, 0, et.size);
13666 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13676 inst.instruction |= neon_quad (rs) << 6;
13677 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13678 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13679 inst.instruction |= cmode << 8;
13680 neon_write_immbits (immbits);
13682 neon_dp_fixup (&inst);
13687 do_neon_bitfield (void)
13689 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13690 neon_check_type (3, rs, N_IGNORE_TYPE);
13691 neon_three_same (neon_quad (rs), 0, -1);
13695 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
13698 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13699 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
13701 if (et.type == NT_float)
13703 NEON_ENCODE (FLOAT, inst);
13704 neon_three_same (neon_quad (rs), 0, -1);
13708 NEON_ENCODE (INTEGER, inst);
13709 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
13714 do_neon_dyadic_if_su (void)
13716 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13720 do_neon_dyadic_if_su_d (void)
13722 /* This version only allow D registers, but that constraint is enforced during
13723 operand parsing so we don't need to do anything extra here. */
13724 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
13728 do_neon_dyadic_if_i_d (void)
13730 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13731 affected if we specify unsigned args. */
13732 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13735 enum vfp_or_neon_is_neon_bits
13738 NEON_CHECK_ARCH = 2
13741 /* Call this function if an instruction which may have belonged to the VFP or
13742 Neon instruction sets, but turned out to be a Neon instruction (due to the
13743 operand types involved, etc.). We have to check and/or fix-up a couple of
13746 - Make sure the user hasn't attempted to make a Neon instruction
13748 - Alter the value in the condition code field if necessary.
13749 - Make sure that the arch supports Neon instructions.
13751 Which of these operations take place depends on bits from enum
13752 vfp_or_neon_is_neon_bits.
13754 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13755 current instruction's condition is COND_ALWAYS, the condition field is
13756 changed to inst.uncond_value. This is necessary because instructions shared
13757 between VFP and Neon may be conditional for the VFP variants only, and the
13758 unconditional Neon version must have, e.g., 0xF in the condition field. */
13761 vfp_or_neon_is_neon (unsigned check)
13763 /* Conditions are always legal in Thumb mode (IT blocks). */
13764 if (!thumb_mode && (check & NEON_CHECK_CC))
13766 if (inst.cond != COND_ALWAYS)
13768 first_error (_(BAD_COND));
13771 if (inst.uncond_value != -1)
13772 inst.instruction |= inst.uncond_value << 28;
13775 if ((check & NEON_CHECK_ARCH)
13776 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
13778 first_error (_(BAD_FPU));
13786 do_neon_addsub_if_i (void)
13788 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
13791 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13794 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13795 affected if we specify unsigned args. */
13796 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
13799 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13801 V<op> A,B (A is operand 0, B is operand 2)
13806 so handle that case specially. */
13809 neon_exchange_operands (void)
13811 void *scratch = alloca (sizeof (inst.operands[0]));
13812 if (inst.operands[1].present)
13814 /* Swap operands[1] and operands[2]. */
13815 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
13816 inst.operands[1] = inst.operands[2];
13817 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
13821 inst.operands[1] = inst.operands[2];
13822 inst.operands[2] = inst.operands[0];
13827 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
13829 if (inst.operands[2].isreg)
13832 neon_exchange_operands ();
13833 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
13837 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
13838 struct neon_type_el et = neon_check_type (2, rs,
13839 N_EQK | N_SIZ, immtypes | N_KEY);
13841 NEON_ENCODE (IMMED, inst);
13842 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13843 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13844 inst.instruction |= LOW4 (inst.operands[1].reg);
13845 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13846 inst.instruction |= neon_quad (rs) << 6;
13847 inst.instruction |= (et.type == NT_float) << 10;
13848 inst.instruction |= neon_logbits (et.size) << 18;
13850 neon_dp_fixup (&inst);
13857 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
13861 do_neon_cmp_inv (void)
13863 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
13869 neon_compare (N_IF_32, N_IF_32, FALSE);
13872 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13873 scalars, which are encoded in 5 bits, M : Rm.
13874 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13875 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13879 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
13881 unsigned regno = NEON_SCALAR_REG (scalar);
13882 unsigned elno = NEON_SCALAR_INDEX (scalar);
13887 if (regno > 7 || elno > 3)
13889 return regno | (elno << 3);
13892 if (regno > 15 || elno > 1)
13894 return regno | (elno << 4);
13898 first_error (_("scalar out of range for multiply instruction"));
13904 /* Encode multiply / multiply-accumulate scalar instructions. */
13907 neon_mul_mac (struct neon_type_el et, int ubit)
13911 /* Give a more helpful error message if we have an invalid type. */
13912 if (et.type == NT_invtype)
13915 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
13916 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13917 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13918 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13919 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13920 inst.instruction |= LOW4 (scalar);
13921 inst.instruction |= HI1 (scalar) << 5;
13922 inst.instruction |= (et.type == NT_float) << 8;
13923 inst.instruction |= neon_logbits (et.size) << 20;
13924 inst.instruction |= (ubit != 0) << 24;
13926 neon_dp_fixup (&inst);
13930 do_neon_mac_maybe_scalar (void)
13932 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
13935 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13938 if (inst.operands[2].isscalar)
13940 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
13941 struct neon_type_el et = neon_check_type (3, rs,
13942 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
13943 NEON_ENCODE (SCALAR, inst);
13944 neon_mul_mac (et, neon_quad (rs));
13948 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13949 affected if we specify unsigned args. */
13950 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13955 do_neon_fmac (void)
13957 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
13960 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13963 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
13969 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13970 struct neon_type_el et = neon_check_type (3, rs,
13971 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
13972 neon_three_same (neon_quad (rs), 0, et.size);
13975 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13976 same types as the MAC equivalents. The polynomial type for this instruction
13977 is encoded the same as the integer type. */
13982 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
13985 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
13988 if (inst.operands[2].isscalar)
13989 do_neon_mac_maybe_scalar ();
13991 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
13995 do_neon_qdmulh (void)
13997 if (inst.operands[2].isscalar)
13999 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14000 struct neon_type_el et = neon_check_type (3, rs,
14001 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14002 NEON_ENCODE (SCALAR, inst);
14003 neon_mul_mac (et, neon_quad (rs));
14007 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14008 struct neon_type_el et = neon_check_type (3, rs,
14009 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14010 NEON_ENCODE (INTEGER, inst);
14011 /* The U bit (rounding) comes from bit mask. */
14012 neon_three_same (neon_quad (rs), 0, et.size);
14017 do_neon_fcmp_absolute (void)
14019 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14020 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14021 /* Size field comes from bit mask. */
14022 neon_three_same (neon_quad (rs), 1, -1);
14026 do_neon_fcmp_absolute_inv (void)
14028 neon_exchange_operands ();
14029 do_neon_fcmp_absolute ();
14033 do_neon_step (void)
14035 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14036 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14037 neon_three_same (neon_quad (rs), 0, -1);
14041 do_neon_abs_neg (void)
14043 enum neon_shape rs;
14044 struct neon_type_el et;
14046 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14049 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14052 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14053 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14055 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14056 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14057 inst.instruction |= LOW4 (inst.operands[1].reg);
14058 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14059 inst.instruction |= neon_quad (rs) << 6;
14060 inst.instruction |= (et.type == NT_float) << 10;
14061 inst.instruction |= neon_logbits (et.size) << 18;
14063 neon_dp_fixup (&inst);
14069 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14070 struct neon_type_el et = neon_check_type (2, rs,
14071 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14072 int imm = inst.operands[2].imm;
14073 constraint (imm < 0 || (unsigned)imm >= et.size,
14074 _("immediate out of range for insert"));
14075 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14081 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14082 struct neon_type_el et = neon_check_type (2, rs,
14083 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14084 int imm = inst.operands[2].imm;
14085 constraint (imm < 1 || (unsigned)imm > et.size,
14086 _("immediate out of range for insert"));
14087 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14091 do_neon_qshlu_imm (void)
14093 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14094 struct neon_type_el et = neon_check_type (2, rs,
14095 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14096 int imm = inst.operands[2].imm;
14097 constraint (imm < 0 || (unsigned)imm >= et.size,
14098 _("immediate out of range for shift"));
14099 /* Only encodes the 'U present' variant of the instruction.
14100 In this case, signed types have OP (bit 8) set to 0.
14101 Unsigned types have OP set to 1. */
14102 inst.instruction |= (et.type == NT_unsigned) << 8;
14103 /* The rest of the bits are the same as other immediate shifts. */
14104 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14108 do_neon_qmovn (void)
14110 struct neon_type_el et = neon_check_type (2, NS_DQ,
14111 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14112 /* Saturating move where operands can be signed or unsigned, and the
14113 destination has the same signedness. */
14114 NEON_ENCODE (INTEGER, inst);
14115 if (et.type == NT_unsigned)
14116 inst.instruction |= 0xc0;
14118 inst.instruction |= 0x80;
14119 neon_two_same (0, 1, et.size / 2);
14123 do_neon_qmovun (void)
14125 struct neon_type_el et = neon_check_type (2, NS_DQ,
14126 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14127 /* Saturating move with unsigned results. Operands must be signed. */
14128 NEON_ENCODE (INTEGER, inst);
14129 neon_two_same (0, 1, et.size / 2);
14133 do_neon_rshift_sat_narrow (void)
14135 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14136 or unsigned. If operands are unsigned, results must also be unsigned. */
14137 struct neon_type_el et = neon_check_type (2, NS_DQI,
14138 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14139 int imm = inst.operands[2].imm;
14140 /* This gets the bounds check, size encoding and immediate bits calculation
14144 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14145 VQMOVN.I<size> <Dd>, <Qm>. */
14148 inst.operands[2].present = 0;
14149 inst.instruction = N_MNEM_vqmovn;
14154 constraint (imm < 1 || (unsigned)imm > et.size,
14155 _("immediate out of range"));
14156 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14160 do_neon_rshift_sat_narrow_u (void)
14162 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14163 or unsigned. If operands are unsigned, results must also be unsigned. */
14164 struct neon_type_el et = neon_check_type (2, NS_DQI,
14165 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14166 int imm = inst.operands[2].imm;
14167 /* This gets the bounds check, size encoding and immediate bits calculation
14171 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14172 VQMOVUN.I<size> <Dd>, <Qm>. */
14175 inst.operands[2].present = 0;
14176 inst.instruction = N_MNEM_vqmovun;
14181 constraint (imm < 1 || (unsigned)imm > et.size,
14182 _("immediate out of range"));
14183 /* FIXME: The manual is kind of unclear about what value U should have in
14184 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14186 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14190 do_neon_movn (void)
14192 struct neon_type_el et = neon_check_type (2, NS_DQ,
14193 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14194 NEON_ENCODE (INTEGER, inst);
14195 neon_two_same (0, 1, et.size / 2);
14199 do_neon_rshift_narrow (void)
14201 struct neon_type_el et = neon_check_type (2, NS_DQI,
14202 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14203 int imm = inst.operands[2].imm;
14204 /* This gets the bounds check, size encoding and immediate bits calculation
14208 /* If immediate is zero then we are a pseudo-instruction for
14209 VMOVN.I<size> <Dd>, <Qm> */
14212 inst.operands[2].present = 0;
14213 inst.instruction = N_MNEM_vmovn;
14218 constraint (imm < 1 || (unsigned)imm > et.size,
14219 _("immediate out of range for narrowing operation"));
14220 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14224 do_neon_shll (void)
14226 /* FIXME: Type checking when lengthening. */
14227 struct neon_type_el et = neon_check_type (2, NS_QDI,
14228 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14229 unsigned imm = inst.operands[2].imm;
14231 if (imm == et.size)
14233 /* Maximum shift variant. */
14234 NEON_ENCODE (INTEGER, inst);
14235 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14236 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14237 inst.instruction |= LOW4 (inst.operands[1].reg);
14238 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14239 inst.instruction |= neon_logbits (et.size) << 18;
14241 neon_dp_fixup (&inst);
14245 /* A more-specific type check for non-max versions. */
14246 et = neon_check_type (2, NS_QDI,
14247 N_EQK | N_DBL, N_SU_32 | N_KEY);
14248 NEON_ENCODE (IMMED, inst);
14249 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14253 /* Check the various types for the VCVT instruction, and return which version
14254 the current instruction is. */
14257 neon_cvt_flavour (enum neon_shape rs)
14259 #define CVT_VAR(C,X,Y) \
14260 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14261 if (et.type != NT_invtype) \
14263 inst.error = NULL; \
14266 struct neon_type_el et;
14267 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
14268 || rs == NS_FF) ? N_VFP : 0;
14269 /* The instruction versions which take an immediate take one register
14270 argument, which is extended to the width of the full register. Thus the
14271 "source" and "destination" registers must have the same width. Hack that
14272 here by making the size equal to the key (wider, in this case) operand. */
14273 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
14275 CVT_VAR (0, N_S32, N_F32);
14276 CVT_VAR (1, N_U32, N_F32);
14277 CVT_VAR (2, N_F32, N_S32);
14278 CVT_VAR (3, N_F32, N_U32);
14279 /* Half-precision conversions. */
14280 CVT_VAR (4, N_F32, N_F16);
14281 CVT_VAR (5, N_F16, N_F32);
14285 /* VFP instructions. */
14286 CVT_VAR (6, N_F32, N_F64);
14287 CVT_VAR (7, N_F64, N_F32);
14288 CVT_VAR (8, N_S32, N_F64 | key);
14289 CVT_VAR (9, N_U32, N_F64 | key);
14290 CVT_VAR (10, N_F64 | key, N_S32);
14291 CVT_VAR (11, N_F64 | key, N_U32);
14292 /* VFP instructions with bitshift. */
14293 CVT_VAR (12, N_F32 | key, N_S16);
14294 CVT_VAR (13, N_F32 | key, N_U16);
14295 CVT_VAR (14, N_F64 | key, N_S16);
14296 CVT_VAR (15, N_F64 | key, N_U16);
14297 CVT_VAR (16, N_S16, N_F32 | key);
14298 CVT_VAR (17, N_U16, N_F32 | key);
14299 CVT_VAR (18, N_S16, N_F64 | key);
14300 CVT_VAR (19, N_U16, N_F64 | key);
14306 /* Neon-syntax VFP conversions. */
14309 do_vfp_nsyn_cvt (enum neon_shape rs, int flavour)
14311 const char *opname = 0;
14313 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
14315 /* Conversions with immediate bitshift. */
14316 const char *enc[] =
14340 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14342 opname = enc[flavour];
14343 constraint (inst.operands[0].reg != inst.operands[1].reg,
14344 _("operands 0 and 1 must be the same register"));
14345 inst.operands[1] = inst.operands[2];
14346 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14351 /* Conversions without bitshift. */
14352 const char *enc[] =
14368 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc))
14369 opname = enc[flavour];
14373 do_vfp_nsyn_opcode (opname);
14377 do_vfp_nsyn_cvtz (void)
14379 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
14380 int flavour = neon_cvt_flavour (rs);
14381 const char *enc[] =
14395 if (flavour >= 0 && flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
14396 do_vfp_nsyn_opcode (enc[flavour]);
14400 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED)
14402 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
14403 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
14404 int flavour = neon_cvt_flavour (rs);
14406 /* PR11109: Handle round-to-zero for VCVT conversions. */
14408 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
14409 && (flavour == 0 || flavour == 1 || flavour == 8 || flavour == 9)
14410 && (rs == NS_FD || rs == NS_FF))
14412 do_vfp_nsyn_cvtz ();
14416 /* VFP rather than Neon conversions. */
14419 do_vfp_nsyn_cvt (rs, flavour);
14429 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14431 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14434 /* Fixed-point conversion with #0 immediate is encoded as an
14435 integer conversion. */
14436 if (inst.operands[2].present && inst.operands[2].imm == 0)
14438 immbits = 32 - inst.operands[2].imm;
14439 NEON_ENCODE (IMMED, inst);
14441 inst.instruction |= enctab[flavour];
14442 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14443 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14444 inst.instruction |= LOW4 (inst.operands[1].reg);
14445 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14446 inst.instruction |= neon_quad (rs) << 6;
14447 inst.instruction |= 1 << 21;
14448 inst.instruction |= immbits << 16;
14450 neon_dp_fixup (&inst);
14458 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
14460 NEON_ENCODE (INTEGER, inst);
14462 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14466 inst.instruction |= enctab[flavour];
14468 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14469 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14470 inst.instruction |= LOW4 (inst.operands[1].reg);
14471 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14472 inst.instruction |= neon_quad (rs) << 6;
14473 inst.instruction |= 2 << 18;
14475 neon_dp_fixup (&inst);
14479 /* Half-precision conversions for Advanced SIMD -- neon. */
14484 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14486 as_bad (_("operand size must match register width"));
14491 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14493 as_bad (_("operand size must match register width"));
14498 inst.instruction = 0x3b60600;
14500 inst.instruction = 0x3b60700;
14502 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14503 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14504 inst.instruction |= LOW4 (inst.operands[1].reg);
14505 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14506 neon_dp_fixup (&inst);
14510 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14511 do_vfp_nsyn_cvt (rs, flavour);
14516 do_neon_cvtr (void)
14518 do_neon_cvt_1 (FALSE);
14524 do_neon_cvt_1 (TRUE);
14528 do_neon_cvtb (void)
14530 inst.instruction = 0xeb20a40;
14532 /* The sizes are attached to the mnemonic. */
14533 if (inst.vectype.el[0].type != NT_invtype
14534 && inst.vectype.el[0].size == 16)
14535 inst.instruction |= 0x00010000;
14537 /* Programmer's syntax: the sizes are attached to the operands. */
14538 else if (inst.operands[0].vectype.type != NT_invtype
14539 && inst.operands[0].vectype.size == 16)
14540 inst.instruction |= 0x00010000;
14542 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14543 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
14544 do_vfp_cond_or_thumb ();
14549 do_neon_cvtt (void)
14552 inst.instruction |= 0x80;
14556 neon_move_immediate (void)
14558 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14559 struct neon_type_el et = neon_check_type (2, rs,
14560 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14561 unsigned immlo, immhi = 0, immbits;
14562 int op, cmode, float_p;
14564 constraint (et.type == NT_invtype,
14565 _("operand size must be specified for immediate VMOV"));
14567 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14568 op = (inst.instruction & (1 << 5)) != 0;
14570 immlo = inst.operands[1].imm;
14571 if (inst.operands[1].regisimm)
14572 immhi = inst.operands[1].reg;
14574 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
14575 _("immediate has bits set outside the operand size"));
14577 float_p = inst.operands[1].immisfloat;
14579 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
14580 et.size, et.type)) == FAIL)
14582 /* Invert relevant bits only. */
14583 neon_invert_size (&immlo, &immhi, et.size);
14584 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14585 with one or the other; those cases are caught by
14586 neon_cmode_for_move_imm. */
14588 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14589 &op, et.size, et.type)) == FAIL)
14591 first_error (_("immediate out of range"));
14596 inst.instruction &= ~(1 << 5);
14597 inst.instruction |= op << 5;
14599 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14600 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14601 inst.instruction |= neon_quad (rs) << 6;
14602 inst.instruction |= cmode << 8;
14604 neon_write_immbits (immbits);
14610 if (inst.operands[1].isreg)
14612 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14614 NEON_ENCODE (INTEGER, inst);
14615 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14616 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14617 inst.instruction |= LOW4 (inst.operands[1].reg);
14618 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14619 inst.instruction |= neon_quad (rs) << 6;
14623 NEON_ENCODE (IMMED, inst);
14624 neon_move_immediate ();
14627 neon_dp_fixup (&inst);
14630 /* Encode instructions of form:
14632 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14633 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14636 neon_mixed_length (struct neon_type_el et, unsigned size)
14638 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14639 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14640 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14641 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14642 inst.instruction |= LOW4 (inst.operands[2].reg);
14643 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14644 inst.instruction |= (et.type == NT_unsigned) << 24;
14645 inst.instruction |= neon_logbits (size) << 20;
14647 neon_dp_fixup (&inst);
14651 do_neon_dyadic_long (void)
14653 /* FIXME: Type checking for lengthening op. */
14654 struct neon_type_el et = neon_check_type (3, NS_QDD,
14655 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
14656 neon_mixed_length (et, et.size);
14660 do_neon_abal (void)
14662 struct neon_type_el et = neon_check_type (3, NS_QDD,
14663 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
14664 neon_mixed_length (et, et.size);
14668 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
14670 if (inst.operands[2].isscalar)
14672 struct neon_type_el et = neon_check_type (3, NS_QDS,
14673 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
14674 NEON_ENCODE (SCALAR, inst);
14675 neon_mul_mac (et, et.type == NT_unsigned);
14679 struct neon_type_el et = neon_check_type (3, NS_QDD,
14680 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
14681 NEON_ENCODE (INTEGER, inst);
14682 neon_mixed_length (et, et.size);
14687 do_neon_mac_maybe_scalar_long (void)
14689 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
14693 do_neon_dyadic_wide (void)
14695 struct neon_type_el et = neon_check_type (3, NS_QQD,
14696 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
14697 neon_mixed_length (et, et.size);
14701 do_neon_dyadic_narrow (void)
14703 struct neon_type_el et = neon_check_type (3, NS_QDD,
14704 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
14705 /* Operand sign is unimportant, and the U bit is part of the opcode,
14706 so force the operand type to integer. */
14707 et.type = NT_integer;
14708 neon_mixed_length (et, et.size / 2);
14712 do_neon_mul_sat_scalar_long (void)
14714 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
14718 do_neon_vmull (void)
14720 if (inst.operands[2].isscalar)
14721 do_neon_mac_maybe_scalar_long ();
14724 struct neon_type_el et = neon_check_type (3, NS_QDD,
14725 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_KEY);
14726 if (et.type == NT_poly)
14727 NEON_ENCODE (POLY, inst);
14729 NEON_ENCODE (INTEGER, inst);
14730 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14731 zero. Should be OK as-is. */
14732 neon_mixed_length (et, et.size);
14739 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
14740 struct neon_type_el et = neon_check_type (3, rs,
14741 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14742 unsigned imm = (inst.operands[3].imm * et.size) / 8;
14744 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
14745 _("shift out of range"));
14746 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14747 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14748 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14749 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14750 inst.instruction |= LOW4 (inst.operands[2].reg);
14751 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14752 inst.instruction |= neon_quad (rs) << 6;
14753 inst.instruction |= imm << 8;
14755 neon_dp_fixup (&inst);
14761 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14762 struct neon_type_el et = neon_check_type (2, rs,
14763 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14764 unsigned op = (inst.instruction >> 7) & 3;
14765 /* N (width of reversed regions) is encoded as part of the bitmask. We
14766 extract it here to check the elements to be reversed are smaller.
14767 Otherwise we'd get a reserved instruction. */
14768 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
14769 gas_assert (elsize != 0);
14770 constraint (et.size >= elsize,
14771 _("elements must be smaller than reversal region"));
14772 neon_two_same (neon_quad (rs), 1, et.size);
14778 if (inst.operands[1].isscalar)
14780 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
14781 struct neon_type_el et = neon_check_type (2, rs,
14782 N_EQK, N_8 | N_16 | N_32 | N_KEY);
14783 unsigned sizebits = et.size >> 3;
14784 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
14785 int logsize = neon_logbits (et.size);
14786 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
14788 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
14791 NEON_ENCODE (SCALAR, inst);
14792 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14793 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14794 inst.instruction |= LOW4 (dm);
14795 inst.instruction |= HI1 (dm) << 5;
14796 inst.instruction |= neon_quad (rs) << 6;
14797 inst.instruction |= x << 17;
14798 inst.instruction |= sizebits << 16;
14800 neon_dp_fixup (&inst);
14804 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
14805 struct neon_type_el et = neon_check_type (2, rs,
14806 N_8 | N_16 | N_32 | N_KEY, N_EQK);
14807 /* Duplicate ARM register to lanes of vector. */
14808 NEON_ENCODE (ARMREG, inst);
14811 case 8: inst.instruction |= 0x400000; break;
14812 case 16: inst.instruction |= 0x000020; break;
14813 case 32: inst.instruction |= 0x000000; break;
14816 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
14817 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
14818 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
14819 inst.instruction |= neon_quad (rs) << 21;
14820 /* The encoding for this instruction is identical for the ARM and Thumb
14821 variants, except for the condition field. */
14822 do_vfp_cond_or_thumb ();
14826 /* VMOV has particularly many variations. It can be one of:
14827 0. VMOV<c><q> <Qd>, <Qm>
14828 1. VMOV<c><q> <Dd>, <Dm>
14829 (Register operations, which are VORR with Rm = Rn.)
14830 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14831 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14833 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14834 (ARM register to scalar.)
14835 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14836 (Two ARM registers to vector.)
14837 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14838 (Scalar to ARM register.)
14839 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14840 (Vector to two ARM registers.)
14841 8. VMOV.F32 <Sd>, <Sm>
14842 9. VMOV.F64 <Dd>, <Dm>
14843 (VFP register moves.)
14844 10. VMOV.F32 <Sd>, #imm
14845 11. VMOV.F64 <Dd>, #imm
14846 (VFP float immediate load.)
14847 12. VMOV <Rd>, <Sm>
14848 (VFP single to ARM reg.)
14849 13. VMOV <Sd>, <Rm>
14850 (ARM reg to VFP single.)
14851 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14852 (Two ARM regs to two VFP singles.)
14853 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14854 (Two VFP singles to two ARM regs.)
14856 These cases can be disambiguated using neon_select_shape, except cases 1/9
14857 and 3/11 which depend on the operand type too.
14859 All the encoded bits are hardcoded by this function.
14861 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14862 Cases 5, 7 may be used with VFPv2 and above.
14864 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14865 can specify a type where it doesn't make sense to, and is ignored). */
14870 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
14871 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
14873 struct neon_type_el et;
14874 const char *ldconst = 0;
14878 case NS_DD: /* case 1/9. */
14879 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14880 /* It is not an error here if no type is given. */
14882 if (et.type == NT_float && et.size == 64)
14884 do_vfp_nsyn_opcode ("fcpyd");
14887 /* fall through. */
14889 case NS_QQ: /* case 0/1. */
14891 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14893 /* The architecture manual I have doesn't explicitly state which
14894 value the U bit should have for register->register moves, but
14895 the equivalent VORR instruction has U = 0, so do that. */
14896 inst.instruction = 0x0200110;
14897 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14898 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14899 inst.instruction |= LOW4 (inst.operands[1].reg);
14900 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14901 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14902 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14903 inst.instruction |= neon_quad (rs) << 6;
14905 neon_dp_fixup (&inst);
14909 case NS_DI: /* case 3/11. */
14910 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
14912 if (et.type == NT_float && et.size == 64)
14914 /* case 11 (fconstd). */
14915 ldconst = "fconstd";
14916 goto encode_fconstd;
14918 /* fall through. */
14920 case NS_QI: /* case 2/3. */
14921 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14923 inst.instruction = 0x0800010;
14924 neon_move_immediate ();
14925 neon_dp_fixup (&inst);
14928 case NS_SR: /* case 4. */
14930 unsigned bcdebits = 0;
14932 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
14933 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
14935 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
14936 logsize = neon_logbits (et.size);
14938 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14941 && et.size != 32, _(BAD_FPU));
14942 constraint (et.type == NT_invtype, _("bad type for scalar"));
14943 constraint (x >= 64 / et.size, _("scalar index out of range"));
14947 case 8: bcdebits = 0x8; break;
14948 case 16: bcdebits = 0x1; break;
14949 case 32: bcdebits = 0x0; break;
14953 bcdebits |= x << logsize;
14955 inst.instruction = 0xe000b10;
14956 do_vfp_cond_or_thumb ();
14957 inst.instruction |= LOW4 (dn) << 16;
14958 inst.instruction |= HI1 (dn) << 7;
14959 inst.instruction |= inst.operands[1].reg << 12;
14960 inst.instruction |= (bcdebits & 3) << 5;
14961 inst.instruction |= (bcdebits >> 2) << 21;
14965 case NS_DRR: /* case 5 (fmdrr). */
14966 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
14969 inst.instruction = 0xc400b10;
14970 do_vfp_cond_or_thumb ();
14971 inst.instruction |= LOW4 (inst.operands[0].reg);
14972 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
14973 inst.instruction |= inst.operands[1].reg << 12;
14974 inst.instruction |= inst.operands[2].reg << 16;
14977 case NS_RS: /* case 6. */
14980 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
14981 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
14982 unsigned abcdebits = 0;
14984 et = neon_check_type (2, NS_NULL,
14985 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
14986 logsize = neon_logbits (et.size);
14988 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
14990 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
14991 && et.size != 32, _(BAD_FPU));
14992 constraint (et.type == NT_invtype, _("bad type for scalar"));
14993 constraint (x >= 64 / et.size, _("scalar index out of range"));
14997 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
14998 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
14999 case 32: abcdebits = 0x00; break;
15003 abcdebits |= x << logsize;
15004 inst.instruction = 0xe100b10;
15005 do_vfp_cond_or_thumb ();
15006 inst.instruction |= LOW4 (dn) << 16;
15007 inst.instruction |= HI1 (dn) << 7;
15008 inst.instruction |= inst.operands[0].reg << 12;
15009 inst.instruction |= (abcdebits & 3) << 5;
15010 inst.instruction |= (abcdebits >> 2) << 21;
15014 case NS_RRD: /* case 7 (fmrrd). */
15015 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15018 inst.instruction = 0xc500b10;
15019 do_vfp_cond_or_thumb ();
15020 inst.instruction |= inst.operands[0].reg << 12;
15021 inst.instruction |= inst.operands[1].reg << 16;
15022 inst.instruction |= LOW4 (inst.operands[2].reg);
15023 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15026 case NS_FF: /* case 8 (fcpys). */
15027 do_vfp_nsyn_opcode ("fcpys");
15030 case NS_FI: /* case 10 (fconsts). */
15031 ldconst = "fconsts";
15033 if (is_quarter_float (inst.operands[1].imm))
15035 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15036 do_vfp_nsyn_opcode (ldconst);
15039 first_error (_("immediate out of range"));
15042 case NS_RF: /* case 12 (fmrs). */
15043 do_vfp_nsyn_opcode ("fmrs");
15046 case NS_FR: /* case 13 (fmsr). */
15047 do_vfp_nsyn_opcode ("fmsr");
15050 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15051 (one of which is a list), but we have parsed four. Do some fiddling to
15052 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15054 case NS_RRFF: /* case 14 (fmrrs). */
15055 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
15056 _("VFP registers must be adjacent"));
15057 inst.operands[2].imm = 2;
15058 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15059 do_vfp_nsyn_opcode ("fmrrs");
15062 case NS_FFRR: /* case 15 (fmsrr). */
15063 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
15064 _("VFP registers must be adjacent"));
15065 inst.operands[1] = inst.operands[2];
15066 inst.operands[2] = inst.operands[3];
15067 inst.operands[0].imm = 2;
15068 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15069 do_vfp_nsyn_opcode ("fmsrr");
15078 do_neon_rshift_round_imm (void)
15080 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
15081 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15082 int imm = inst.operands[2].imm;
15084 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15087 inst.operands[2].present = 0;
15092 constraint (imm < 1 || (unsigned)imm > et.size,
15093 _("immediate out of range for shift"));
15094 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
15099 do_neon_movl (void)
15101 struct neon_type_el et = neon_check_type (2, NS_QD,
15102 N_EQK | N_DBL, N_SU_32 | N_KEY);
15103 unsigned sizebits = et.size >> 3;
15104 inst.instruction |= sizebits << 19;
15105 neon_two_same (0, et.type == NT_unsigned, -1);
15111 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15112 struct neon_type_el et = neon_check_type (2, rs,
15113 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15114 NEON_ENCODE (INTEGER, inst);
15115 neon_two_same (neon_quad (rs), 1, et.size);
15119 do_neon_zip_uzp (void)
15121 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15122 struct neon_type_el et = neon_check_type (2, rs,
15123 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15124 if (rs == NS_DD && et.size == 32)
15126 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15127 inst.instruction = N_MNEM_vtrn;
15131 neon_two_same (neon_quad (rs), 1, et.size);
15135 do_neon_sat_abs_neg (void)
15137 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15138 struct neon_type_el et = neon_check_type (2, rs,
15139 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15140 neon_two_same (neon_quad (rs), 1, et.size);
15144 do_neon_pair_long (void)
15146 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15147 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15148 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15149 inst.instruction |= (et.type == NT_unsigned) << 7;
15150 neon_two_same (neon_quad (rs), 1, et.size);
15154 do_neon_recip_est (void)
15156 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15157 struct neon_type_el et = neon_check_type (2, rs,
15158 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15159 inst.instruction |= (et.type == NT_float) << 8;
15160 neon_two_same (neon_quad (rs), 1, et.size);
15166 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15167 struct neon_type_el et = neon_check_type (2, rs,
15168 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
15169 neon_two_same (neon_quad (rs), 1, et.size);
15175 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15176 struct neon_type_el et = neon_check_type (2, rs,
15177 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
15178 neon_two_same (neon_quad (rs), 1, et.size);
15184 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15185 struct neon_type_el et = neon_check_type (2, rs,
15186 N_EQK | N_INT, N_8 | N_KEY);
15187 neon_two_same (neon_quad (rs), 1, et.size);
15193 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15194 neon_two_same (neon_quad (rs), 1, -1);
15198 do_neon_tbl_tbx (void)
15200 unsigned listlenbits;
15201 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
15203 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15205 first_error (_("bad list length for table lookup"));
15209 listlenbits = inst.operands[1].imm - 1;
15210 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15211 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15212 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15213 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15214 inst.instruction |= LOW4 (inst.operands[2].reg);
15215 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15216 inst.instruction |= listlenbits << 8;
15218 neon_dp_fixup (&inst);
15222 do_neon_ldm_stm (void)
15224 /* P, U and L bits are part of bitmask. */
15225 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15226 unsigned offsetbits = inst.operands[1].imm * 2;
15228 if (inst.operands[1].issingle)
15230 do_vfp_nsyn_ldm_stm (is_dbmode);
15234 constraint (is_dbmode && !inst.operands[0].writeback,
15235 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15237 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
15238 _("register list must contain at least 1 and at most 16 "
15241 inst.instruction |= inst.operands[0].reg << 16;
15242 inst.instruction |= inst.operands[0].writeback << 21;
15243 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15244 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15246 inst.instruction |= offsetbits;
15248 do_vfp_cond_or_thumb ();
15252 do_neon_ldr_str (void)
15254 int is_ldr = (inst.instruction & (1 << 20)) != 0;
15256 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15257 And is UNPREDICTABLE in thumb mode. */
15259 && inst.operands[1].reg == REG_PC
15260 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
15262 if (!thumb_mode && warn_on_deprecated)
15263 as_warn (_("Use of PC here is deprecated"));
15265 inst.error = _("Use of PC here is UNPREDICTABLE");
15268 if (inst.operands[0].issingle)
15271 do_vfp_nsyn_opcode ("flds");
15273 do_vfp_nsyn_opcode ("fsts");
15278 do_vfp_nsyn_opcode ("fldd");
15280 do_vfp_nsyn_opcode ("fstd");
15284 /* "interleave" version also handles non-interleaving register VLD1/VST1
15288 do_neon_ld_st_interleave (void)
15290 struct neon_type_el et = neon_check_type (1, NS_NULL,
15291 N_8 | N_16 | N_32 | N_64);
15292 unsigned alignbits = 0;
15294 /* The bits in this table go:
15295 0: register stride of one (0) or two (1)
15296 1,2: register list length, minus one (1, 2, 3, 4).
15297 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15298 We use -1 for invalid entries. */
15299 const int typetable[] =
15301 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15302 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15303 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15304 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15308 if (et.type == NT_invtype)
15311 if (inst.operands[1].immisalign)
15312 switch (inst.operands[1].imm >> 8)
15314 case 64: alignbits = 1; break;
15316 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
15317 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15318 goto bad_alignment;
15322 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15323 goto bad_alignment;
15328 first_error (_("bad alignment"));
15332 inst.instruction |= alignbits << 4;
15333 inst.instruction |= neon_logbits (et.size) << 6;
15335 /* Bits [4:6] of the immediate in a list specifier encode register stride
15336 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15337 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15338 up the right value for "type" in a table based on this value and the given
15339 list style, then stick it back. */
15340 idx = ((inst.operands[0].imm >> 4) & 7)
15341 | (((inst.instruction >> 8) & 3) << 3);
15343 typebits = typetable[idx];
15345 constraint (typebits == -1, _("bad list type for instruction"));
15347 inst.instruction &= ~0xf00;
15348 inst.instruction |= typebits << 8;
15351 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15352 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15353 otherwise. The variable arguments are a list of pairs of legal (size, align)
15354 values, terminated with -1. */
15357 neon_alignment_bit (int size, int align, int *do_align, ...)
15360 int result = FAIL, thissize, thisalign;
15362 if (!inst.operands[1].immisalign)
15368 va_start (ap, do_align);
15372 thissize = va_arg (ap, int);
15373 if (thissize == -1)
15375 thisalign = va_arg (ap, int);
15377 if (size == thissize && align == thisalign)
15380 while (result != SUCCESS);
15384 if (result == SUCCESS)
15387 first_error (_("unsupported alignment for instruction"));
15393 do_neon_ld_st_lane (void)
15395 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15396 int align_good, do_align = 0;
15397 int logsize = neon_logbits (et.size);
15398 int align = inst.operands[1].imm >> 8;
15399 int n = (inst.instruction >> 8) & 3;
15400 int max_el = 64 / et.size;
15402 if (et.type == NT_invtype)
15405 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
15406 _("bad list length"));
15407 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
15408 _("scalar index out of range"));
15409 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
15411 _("stride of 2 unavailable when element size is 8"));
15415 case 0: /* VLD1 / VST1. */
15416 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
15418 if (align_good == FAIL)
15422 unsigned alignbits = 0;
15425 case 16: alignbits = 0x1; break;
15426 case 32: alignbits = 0x3; break;
15429 inst.instruction |= alignbits << 4;
15433 case 1: /* VLD2 / VST2. */
15434 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
15436 if (align_good == FAIL)
15439 inst.instruction |= 1 << 4;
15442 case 2: /* VLD3 / VST3. */
15443 constraint (inst.operands[1].immisalign,
15444 _("can't use alignment with this instruction"));
15447 case 3: /* VLD4 / VST4. */
15448 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15449 16, 64, 32, 64, 32, 128, -1);
15450 if (align_good == FAIL)
15454 unsigned alignbits = 0;
15457 case 8: alignbits = 0x1; break;
15458 case 16: alignbits = 0x1; break;
15459 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15462 inst.instruction |= alignbits << 4;
15469 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15470 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15471 inst.instruction |= 1 << (4 + logsize);
15473 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15474 inst.instruction |= logsize << 10;
15477 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15480 do_neon_ld_dup (void)
15482 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
15483 int align_good, do_align = 0;
15485 if (et.type == NT_invtype)
15488 switch ((inst.instruction >> 8) & 3)
15490 case 0: /* VLD1. */
15491 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
15492 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15493 &do_align, 16, 16, 32, 32, -1);
15494 if (align_good == FAIL)
15496 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
15499 case 2: inst.instruction |= 1 << 5; break;
15500 default: first_error (_("bad list length")); return;
15502 inst.instruction |= neon_logbits (et.size) << 6;
15505 case 1: /* VLD2. */
15506 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
15507 &do_align, 8, 16, 16, 32, 32, 64, -1);
15508 if (align_good == FAIL)
15510 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
15511 _("bad list length"));
15512 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15513 inst.instruction |= 1 << 5;
15514 inst.instruction |= neon_logbits (et.size) << 6;
15517 case 2: /* VLD3. */
15518 constraint (inst.operands[1].immisalign,
15519 _("can't use alignment with this instruction"));
15520 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
15521 _("bad list length"));
15522 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15523 inst.instruction |= 1 << 5;
15524 inst.instruction |= neon_logbits (et.size) << 6;
15527 case 3: /* VLD4. */
15529 int align = inst.operands[1].imm >> 8;
15530 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15531 16, 64, 32, 64, 32, 128, -1);
15532 if (align_good == FAIL)
15534 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15535 _("bad list length"));
15536 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15537 inst.instruction |= 1 << 5;
15538 if (et.size == 32 && align == 128)
15539 inst.instruction |= 0x3 << 6;
15541 inst.instruction |= neon_logbits (et.size) << 6;
15548 inst.instruction |= do_align << 4;
15551 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15552 apart from bits [11:4]. */
15555 do_neon_ldx_stx (void)
15557 if (inst.operands[1].isreg)
15558 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15560 switch (NEON_LANE (inst.operands[0].imm))
15562 case NEON_INTERLEAVE_LANES:
15563 NEON_ENCODE (INTERLV, inst);
15564 do_neon_ld_st_interleave ();
15567 case NEON_ALL_LANES:
15568 NEON_ENCODE (DUP, inst);
15573 NEON_ENCODE (LANE, inst);
15574 do_neon_ld_st_lane ();
15577 /* L bit comes from bit mask. */
15578 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15579 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15580 inst.instruction |= inst.operands[1].reg << 16;
15582 if (inst.operands[1].postind)
15584 int postreg = inst.operands[1].imm & 0xf;
15585 constraint (!inst.operands[1].immisreg,
15586 _("post-index must be a register"));
15587 constraint (postreg == 0xd || postreg == 0xf,
15588 _("bad register for post-index"));
15589 inst.instruction |= postreg;
15591 else if (inst.operands[1].writeback)
15593 inst.instruction |= 0xd;
15596 inst.instruction |= 0xf;
15599 inst.instruction |= 0xf9000000;
15601 inst.instruction |= 0xf4000000;
15604 /* Overall per-instruction processing. */
15606 /* We need to be able to fix up arbitrary expressions in some statements.
15607 This is so that we can handle symbols that are an arbitrary distance from
15608 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15609 which returns part of an address in a form which will be valid for
15610 a data instruction. We do this by pushing the expression into a symbol
15611 in the expr_section, and creating a fix for that. */
15614 fix_new_arm (fragS * frag,
15628 /* Create an absolute valued symbol, so we have something to
15629 refer to in the object file. Unfortunately for us, gas's
15630 generic expression parsing will already have folded out
15631 any use of .set foo/.type foo %function that may have
15632 been used to set type information of the target location,
15633 that's being specified symbolically. We have to presume
15634 the user knows what they are doing. */
15638 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
15640 symbol = symbol_find_or_make (name);
15641 S_SET_SEGMENT (symbol, absolute_section);
15642 symbol_set_frag (symbol, &zero_address_frag);
15643 S_SET_VALUE (symbol, exp->X_add_number);
15644 exp->X_op = O_symbol;
15645 exp->X_add_symbol = symbol;
15646 exp->X_add_number = 0;
15652 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
15653 (enum bfd_reloc_code_real) reloc);
15657 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
15658 pc_rel, (enum bfd_reloc_code_real) reloc);
15662 /* Mark whether the fix is to a THUMB instruction, or an ARM
15664 new_fix->tc_fix_data = thumb_mode;
15667 /* Create a frg for an instruction requiring relaxation. */
15669 output_relax_insn (void)
15675 /* The size of the instruction is unknown, so tie the debug info to the
15676 start of the instruction. */
15677 dwarf2_emit_insn (0);
15679 switch (inst.reloc.exp.X_op)
15682 sym = inst.reloc.exp.X_add_symbol;
15683 offset = inst.reloc.exp.X_add_number;
15687 offset = inst.reloc.exp.X_add_number;
15690 sym = make_expr_symbol (&inst.reloc.exp);
15694 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
15695 inst.relax, sym, offset, NULL/*offset, opcode*/);
15696 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
15699 /* Write a 32-bit thumb instruction to buf. */
15701 put_thumb32_insn (char * buf, unsigned long insn)
15703 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
15704 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
15708 output_inst (const char * str)
15714 as_bad ("%s -- `%s'", inst.error, str);
15719 output_relax_insn ();
15722 if (inst.size == 0)
15725 to = frag_more (inst.size);
15726 /* PR 9814: Record the thumb mode into the current frag so that we know
15727 what type of NOP padding to use, if necessary. We override any previous
15728 setting so that if the mode has changed then the NOPS that we use will
15729 match the encoding of the last instruction in the frag. */
15730 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
15732 if (thumb_mode && (inst.size > THUMB_SIZE))
15734 gas_assert (inst.size == (2 * THUMB_SIZE));
15735 put_thumb32_insn (to, inst.instruction);
15737 else if (inst.size > INSN_SIZE)
15739 gas_assert (inst.size == (2 * INSN_SIZE));
15740 md_number_to_chars (to, inst.instruction, INSN_SIZE);
15741 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
15744 md_number_to_chars (to, inst.instruction, inst.size);
15746 if (inst.reloc.type != BFD_RELOC_UNUSED)
15747 fix_new_arm (frag_now, to - frag_now->fr_literal,
15748 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
15751 dwarf2_emit_insn (inst.size);
15755 output_it_inst (int cond, int mask, char * to)
15757 unsigned long instruction = 0xbf00;
15760 instruction |= mask;
15761 instruction |= cond << 4;
15765 to = frag_more (2);
15767 dwarf2_emit_insn (2);
15771 md_number_to_chars (to, instruction, 2);
15776 /* Tag values used in struct asm_opcode's tag field. */
15779 OT_unconditional, /* Instruction cannot be conditionalized.
15780 The ARM condition field is still 0xE. */
15781 OT_unconditionalF, /* Instruction cannot be conditionalized
15782 and carries 0xF in its ARM condition field. */
15783 OT_csuffix, /* Instruction takes a conditional suffix. */
15784 OT_csuffixF, /* Some forms of the instruction take a conditional
15785 suffix, others place 0xF where the condition field
15787 OT_cinfix3, /* Instruction takes a conditional infix,
15788 beginning at character index 3. (In
15789 unified mode, it becomes a suffix.) */
15790 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
15791 tsts, cmps, cmns, and teqs. */
15792 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
15793 character index 3, even in unified mode. Used for
15794 legacy instructions where suffix and infix forms
15795 may be ambiguous. */
15796 OT_csuf_or_in3, /* Instruction takes either a conditional
15797 suffix or an infix at character index 3. */
15798 OT_odd_infix_unc, /* This is the unconditional variant of an
15799 instruction that takes a conditional infix
15800 at an unusual position. In unified mode,
15801 this variant will accept a suffix. */
15802 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
15803 are the conditional variants of instructions that
15804 take conditional infixes in unusual positions.
15805 The infix appears at character index
15806 (tag - OT_odd_infix_0). These are not accepted
15807 in unified mode. */
15810 /* Subroutine of md_assemble, responsible for looking up the primary
15811 opcode from the mnemonic the user wrote. STR points to the
15812 beginning of the mnemonic.
15814 This is not simply a hash table lookup, because of conditional
15815 variants. Most instructions have conditional variants, which are
15816 expressed with a _conditional affix_ to the mnemonic. If we were
15817 to encode each conditional variant as a literal string in the opcode
15818 table, it would have approximately 20,000 entries.
15820 Most mnemonics take this affix as a suffix, and in unified syntax,
15821 'most' is upgraded to 'all'. However, in the divided syntax, some
15822 instructions take the affix as an infix, notably the s-variants of
15823 the arithmetic instructions. Of those instructions, all but six
15824 have the infix appear after the third character of the mnemonic.
15826 Accordingly, the algorithm for looking up primary opcodes given
15829 1. Look up the identifier in the opcode table.
15830 If we find a match, go to step U.
15832 2. Look up the last two characters of the identifier in the
15833 conditions table. If we find a match, look up the first N-2
15834 characters of the identifier in the opcode table. If we
15835 find a match, go to step CE.
15837 3. Look up the fourth and fifth characters of the identifier in
15838 the conditions table. If we find a match, extract those
15839 characters from the identifier, and look up the remaining
15840 characters in the opcode table. If we find a match, go
15845 U. Examine the tag field of the opcode structure, in case this is
15846 one of the six instructions with its conditional infix in an
15847 unusual place. If it is, the tag tells us where to find the
15848 infix; look it up in the conditions table and set inst.cond
15849 accordingly. Otherwise, this is an unconditional instruction.
15850 Again set inst.cond accordingly. Return the opcode structure.
15852 CE. Examine the tag field to make sure this is an instruction that
15853 should receive a conditional suffix. If it is not, fail.
15854 Otherwise, set inst.cond from the suffix we already looked up,
15855 and return the opcode structure.
15857 CM. Examine the tag field to make sure this is an instruction that
15858 should receive a conditional infix after the third character.
15859 If it is not, fail. Otherwise, undo the edits to the current
15860 line of input and proceed as for case CE. */
15862 static const struct asm_opcode *
15863 opcode_lookup (char **str)
15867 const struct asm_opcode *opcode;
15868 const struct asm_cond *cond;
15871 /* Scan up to the end of the mnemonic, which must end in white space,
15872 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15873 for (base = end = *str; *end != '\0'; end++)
15874 if (*end == ' ' || *end == '.')
15880 /* Handle a possible width suffix and/or Neon type suffix. */
15885 /* The .w and .n suffixes are only valid if the unified syntax is in
15887 if (unified_syntax && end[1] == 'w')
15889 else if (unified_syntax && end[1] == 'n')
15894 inst.vectype.elems = 0;
15896 *str = end + offset;
15898 if (end[offset] == '.')
15900 /* See if we have a Neon type suffix (possible in either unified or
15901 non-unified ARM syntax mode). */
15902 if (parse_neon_type (&inst.vectype, str) == FAIL)
15905 else if (end[offset] != '\0' && end[offset] != ' ')
15911 /* Look for unaffixed or special-case affixed mnemonic. */
15912 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15917 if (opcode->tag < OT_odd_infix_0)
15919 inst.cond = COND_ALWAYS;
15923 if (warn_on_deprecated && unified_syntax)
15924 as_warn (_("conditional infixes are deprecated in unified syntax"));
15925 affix = base + (opcode->tag - OT_odd_infix_0);
15926 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15929 inst.cond = cond->value;
15933 /* Cannot have a conditional suffix on a mnemonic of less than two
15935 if (end - base < 3)
15938 /* Look for suffixed mnemonic. */
15940 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15941 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15943 if (opcode && cond)
15946 switch (opcode->tag)
15948 case OT_cinfix3_legacy:
15949 /* Ignore conditional suffixes matched on infix only mnemonics. */
15953 case OT_cinfix3_deprecated:
15954 case OT_odd_infix_unc:
15955 if (!unified_syntax)
15957 /* else fall through */
15961 case OT_csuf_or_in3:
15962 inst.cond = cond->value;
15965 case OT_unconditional:
15966 case OT_unconditionalF:
15968 inst.cond = cond->value;
15971 /* Delayed diagnostic. */
15972 inst.error = BAD_COND;
15973 inst.cond = COND_ALWAYS;
15982 /* Cannot have a usual-position infix on a mnemonic of less than
15983 six characters (five would be a suffix). */
15984 if (end - base < 6)
15987 /* Look for infixed mnemonic in the usual position. */
15989 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
15993 memcpy (save, affix, 2);
15994 memmove (affix, affix + 2, (end - affix) - 2);
15995 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
15997 memmove (affix + 2, affix, (end - affix) - 2);
15998 memcpy (affix, save, 2);
16001 && (opcode->tag == OT_cinfix3
16002 || opcode->tag == OT_cinfix3_deprecated
16003 || opcode->tag == OT_csuf_or_in3
16004 || opcode->tag == OT_cinfix3_legacy))
16007 if (warn_on_deprecated && unified_syntax
16008 && (opcode->tag == OT_cinfix3
16009 || opcode->tag == OT_cinfix3_deprecated))
16010 as_warn (_("conditional infixes are deprecated in unified syntax"));
16012 inst.cond = cond->value;
16019 /* This function generates an initial IT instruction, leaving its block
16020 virtually open for the new instructions. Eventually,
16021 the mask will be updated by now_it_add_mask () each time
16022 a new instruction needs to be included in the IT block.
16023 Finally, the block is closed with close_automatic_it_block ().
16024 The block closure can be requested either from md_assemble (),
16025 a tencode (), or due to a label hook. */
16028 new_automatic_it_block (int cond)
16030 now_it.state = AUTOMATIC_IT_BLOCK;
16031 now_it.mask = 0x18;
16033 now_it.block_length = 1;
16034 mapping_state (MAP_THUMB);
16035 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
16038 /* Close an automatic IT block.
16039 See comments in new_automatic_it_block (). */
16042 close_automatic_it_block (void)
16044 now_it.mask = 0x10;
16045 now_it.block_length = 0;
16048 /* Update the mask of the current automatically-generated IT
16049 instruction. See comments in new_automatic_it_block (). */
16052 now_it_add_mask (int cond)
16054 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16055 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
16056 | ((bitvalue) << (nbit)))
16057 const int resulting_bit = (cond & 1);
16059 now_it.mask &= 0xf;
16060 now_it.mask = SET_BIT_VALUE (now_it.mask,
16062 (5 - now_it.block_length));
16063 now_it.mask = SET_BIT_VALUE (now_it.mask,
16065 ((5 - now_it.block_length) - 1) );
16066 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16069 #undef SET_BIT_VALUE
16072 /* The IT blocks handling machinery is accessed through the these functions:
16073 it_fsm_pre_encode () from md_assemble ()
16074 set_it_insn_type () optional, from the tencode functions
16075 set_it_insn_type_last () ditto
16076 in_it_block () ditto
16077 it_fsm_post_encode () from md_assemble ()
16078 force_automatic_it_block_close () from label habdling functions
16081 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
16082 initializing the IT insn type with a generic initial value depending
16083 on the inst.condition.
16084 2) During the tencode function, two things may happen:
16085 a) The tencode function overrides the IT insn type by
16086 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16087 b) The tencode function queries the IT block state by
16088 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16090 Both set_it_insn_type and in_it_block run the internal FSM state
16091 handling function (handle_it_state), because: a) setting the IT insn
16092 type may incur in an invalid state (exiting the function),
16093 and b) querying the state requires the FSM to be updated.
16094 Specifically we want to avoid creating an IT block for conditional
16095 branches, so it_fsm_pre_encode is actually a guess and we can't
16096 determine whether an IT block is required until the tencode () routine
16097 has decided what type of instruction this actually it.
16098 Because of this, if set_it_insn_type and in_it_block have to be used,
16099 set_it_insn_type has to be called first.
16101 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16102 determines the insn IT type depending on the inst.cond code.
16103 When a tencode () routine encodes an instruction that can be
16104 either outside an IT block, or, in the case of being inside, has to be
16105 the last one, set_it_insn_type_last () will determine the proper
16106 IT instruction type based on the inst.cond code. Otherwise,
16107 set_it_insn_type can be called for overriding that logic or
16108 for covering other cases.
16110 Calling handle_it_state () may not transition the IT block state to
16111 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16112 still queried. Instead, if the FSM determines that the state should
16113 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16114 after the tencode () function: that's what it_fsm_post_encode () does.
16116 Since in_it_block () calls the state handling function to get an
16117 updated state, an error may occur (due to invalid insns combination).
16118 In that case, inst.error is set.
16119 Therefore, inst.error has to be checked after the execution of
16120 the tencode () routine.
16122 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16123 any pending state change (if any) that didn't take place in
16124 handle_it_state () as explained above. */
16127 it_fsm_pre_encode (void)
16129 if (inst.cond != COND_ALWAYS)
16130 inst.it_insn_type = INSIDE_IT_INSN;
16132 inst.it_insn_type = OUTSIDE_IT_INSN;
16134 now_it.state_handled = 0;
16137 /* IT state FSM handling function. */
16140 handle_it_state (void)
16142 now_it.state_handled = 1;
16144 switch (now_it.state)
16146 case OUTSIDE_IT_BLOCK:
16147 switch (inst.it_insn_type)
16149 case OUTSIDE_IT_INSN:
16152 case INSIDE_IT_INSN:
16153 case INSIDE_IT_LAST_INSN:
16154 if (thumb_mode == 0)
16157 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16158 as_tsktsk (_("Warning: conditional outside an IT block"\
16163 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16164 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16166 /* Automatically generate the IT instruction. */
16167 new_automatic_it_block (inst.cond);
16168 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16169 close_automatic_it_block ();
16173 inst.error = BAD_OUT_IT;
16179 case IF_INSIDE_IT_LAST_INSN:
16180 case NEUTRAL_IT_INSN:
16184 now_it.state = MANUAL_IT_BLOCK;
16185 now_it.block_length = 0;
16190 case AUTOMATIC_IT_BLOCK:
16191 /* Three things may happen now:
16192 a) We should increment current it block size;
16193 b) We should close current it block (closing insn or 4 insns);
16194 c) We should close current it block and start a new one (due
16195 to incompatible conditions or
16196 4 insns-length block reached). */
16198 switch (inst.it_insn_type)
16200 case OUTSIDE_IT_INSN:
16201 /* The closure of the block shall happen immediatelly,
16202 so any in_it_block () call reports the block as closed. */
16203 force_automatic_it_block_close ();
16206 case INSIDE_IT_INSN:
16207 case INSIDE_IT_LAST_INSN:
16208 case IF_INSIDE_IT_LAST_INSN:
16209 now_it.block_length++;
16211 if (now_it.block_length > 4
16212 || !now_it_compatible (inst.cond))
16214 force_automatic_it_block_close ();
16215 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16216 new_automatic_it_block (inst.cond);
16220 now_it_add_mask (inst.cond);
16223 if (now_it.state == AUTOMATIC_IT_BLOCK
16224 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16225 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16226 close_automatic_it_block ();
16229 case NEUTRAL_IT_INSN:
16230 now_it.block_length++;
16232 if (now_it.block_length > 4)
16233 force_automatic_it_block_close ();
16235 now_it_add_mask (now_it.cc & 1);
16239 close_automatic_it_block ();
16240 now_it.state = MANUAL_IT_BLOCK;
16245 case MANUAL_IT_BLOCK:
16247 /* Check conditional suffixes. */
16248 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
16251 now_it.mask &= 0x1f;
16252 is_last = (now_it.mask == 0x10);
16254 switch (inst.it_insn_type)
16256 case OUTSIDE_IT_INSN:
16257 inst.error = BAD_NOT_IT;
16260 case INSIDE_IT_INSN:
16261 if (cond != inst.cond)
16263 inst.error = BAD_IT_COND;
16268 case INSIDE_IT_LAST_INSN:
16269 case IF_INSIDE_IT_LAST_INSN:
16270 if (cond != inst.cond)
16272 inst.error = BAD_IT_COND;
16277 inst.error = BAD_BRANCH;
16282 case NEUTRAL_IT_INSN:
16283 /* The BKPT instruction is unconditional even in an IT block. */
16287 inst.error = BAD_IT_IT;
16298 it_fsm_post_encode (void)
16302 if (!now_it.state_handled)
16303 handle_it_state ();
16305 is_last = (now_it.mask == 0x10);
16308 now_it.state = OUTSIDE_IT_BLOCK;
16314 force_automatic_it_block_close (void)
16316 if (now_it.state == AUTOMATIC_IT_BLOCK)
16318 close_automatic_it_block ();
16319 now_it.state = OUTSIDE_IT_BLOCK;
16327 if (!now_it.state_handled)
16328 handle_it_state ();
16330 return now_it.state != OUTSIDE_IT_BLOCK;
16334 md_assemble (char *str)
16337 const struct asm_opcode * opcode;
16339 /* Align the previous label if needed. */
16340 if (last_label_seen != NULL)
16342 symbol_set_frag (last_label_seen, frag_now);
16343 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
16344 S_SET_SEGMENT (last_label_seen, now_seg);
16347 memset (&inst, '\0', sizeof (inst));
16348 inst.reloc.type = BFD_RELOC_UNUSED;
16350 opcode = opcode_lookup (&p);
16353 /* It wasn't an instruction, but it might be a register alias of
16354 the form alias .req reg, or a Neon .dn/.qn directive. */
16355 if (! create_register_alias (str, p)
16356 && ! create_neon_reg_alias (str, p))
16357 as_bad (_("bad instruction `%s'"), str);
16362 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
16363 as_warn (_("s suffix on comparison instruction is deprecated"));
16365 /* The value which unconditional instructions should have in place of the
16366 condition field. */
16367 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
16371 arm_feature_set variant;
16373 variant = cpu_variant;
16374 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16375 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
16376 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
16377 /* Check that this instruction is supported for this CPU. */
16378 if (!opcode->tvariant
16379 || (thumb_mode == 1
16380 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
16382 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
16385 if (inst.cond != COND_ALWAYS && !unified_syntax
16386 && opcode->tencode != do_t_branch)
16388 as_bad (_("Thumb does not support conditional execution"));
16392 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
16394 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
16395 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
16396 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
16398 /* Two things are addressed here.
16399 1) Implicit require narrow instructions on Thumb-1.
16400 This avoids relaxation accidentally introducing Thumb-2
16402 2) Reject wide instructions in non Thumb-2 cores. */
16403 if (inst.size_req == 0)
16405 else if (inst.size_req == 4)
16407 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
16413 inst.instruction = opcode->tvalue;
16415 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
16417 /* Prepare the it_insn_type for those encodings that don't set
16419 it_fsm_pre_encode ();
16421 opcode->tencode ();
16423 it_fsm_post_encode ();
16426 if (!(inst.error || inst.relax))
16428 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
16429 inst.size = (inst.instruction > 0xffff ? 4 : 2);
16430 if (inst.size_req && inst.size_req != inst.size)
16432 as_bad (_("cannot honor width suffix -- `%s'"), str);
16437 /* Something has gone badly wrong if we try to relax a fixed size
16439 gas_assert (inst.size_req == 0 || !inst.relax);
16441 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16442 *opcode->tvariant);
16443 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16444 set those bits when Thumb-2 32-bit instructions are seen. ie.
16445 anything other than bl/blx and v6-M instructions.
16446 This is overly pessimistic for relaxable instructions. */
16447 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
16449 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
16450 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
16451 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
16454 check_neon_suffixes;
16458 mapping_state (MAP_THUMB);
16461 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
16465 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16466 is_bx = (opcode->aencode == do_bx);
16468 /* Check that this instruction is supported for this CPU. */
16469 if (!(is_bx && fix_v4bx)
16470 && !(opcode->avariant &&
16471 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
16473 as_bad (_("selected processor does not support ARM mode `%s'"), str);
16478 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
16482 inst.instruction = opcode->avalue;
16483 if (opcode->tag == OT_unconditionalF)
16484 inst.instruction |= 0xF << 28;
16486 inst.instruction |= inst.cond << 28;
16487 inst.size = INSN_SIZE;
16488 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
16490 it_fsm_pre_encode ();
16491 opcode->aencode ();
16492 it_fsm_post_encode ();
16494 /* Arm mode bx is marked as both v4T and v5 because it's still required
16495 on a hypothetical non-thumb v5 core. */
16497 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
16499 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
16500 *opcode->avariant);
16502 check_neon_suffixes;
16506 mapping_state (MAP_ARM);
16511 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16519 check_it_blocks_finished (void)
16524 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
16525 if (seg_info (sect)->tc_segment_info_data.current_it.state
16526 == MANUAL_IT_BLOCK)
16528 as_warn (_("section '%s' finished with an open IT block."),
16532 if (now_it.state == MANUAL_IT_BLOCK)
16533 as_warn (_("file finished with an open IT block."));
16537 /* Various frobbings of labels and their addresses. */
16540 arm_start_line_hook (void)
16542 last_label_seen = NULL;
16546 arm_frob_label (symbolS * sym)
16548 last_label_seen = sym;
16550 ARM_SET_THUMB (sym, thumb_mode);
16552 #if defined OBJ_COFF || defined OBJ_ELF
16553 ARM_SET_INTERWORK (sym, support_interwork);
16556 force_automatic_it_block_close ();
16558 /* Note - do not allow local symbols (.Lxxx) to be labelled
16559 as Thumb functions. This is because these labels, whilst
16560 they exist inside Thumb code, are not the entry points for
16561 possible ARM->Thumb calls. Also, these labels can be used
16562 as part of a computed goto or switch statement. eg gcc
16563 can generate code that looks like this:
16565 ldr r2, [pc, .Laaa]
16575 The first instruction loads the address of the jump table.
16576 The second instruction converts a table index into a byte offset.
16577 The third instruction gets the jump address out of the table.
16578 The fourth instruction performs the jump.
16580 If the address stored at .Laaa is that of a symbol which has the
16581 Thumb_Func bit set, then the linker will arrange for this address
16582 to have the bottom bit set, which in turn would mean that the
16583 address computation performed by the third instruction would end
16584 up with the bottom bit set. Since the ARM is capable of unaligned
16585 word loads, the instruction would then load the incorrect address
16586 out of the jump table, and chaos would ensue. */
16587 if (label_is_thumb_function_name
16588 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
16589 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
16591 /* When the address of a Thumb function is taken the bottom
16592 bit of that address should be set. This will allow
16593 interworking between Arm and Thumb functions to work
16596 THUMB_SET_FUNC (sym, 1);
16598 label_is_thumb_function_name = FALSE;
16601 dwarf2_emit_label (sym);
16605 arm_data_in_code (void)
16607 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
16609 *input_line_pointer = '/';
16610 input_line_pointer += 5;
16611 *input_line_pointer = 0;
16619 arm_canonicalize_symbol_name (char * name)
16623 if (thumb_mode && (len = strlen (name)) > 5
16624 && streq (name + len - 5, "/data"))
16625 *(name + len - 5) = 0;
16630 /* Table of all register names defined by default. The user can
16631 define additional names with .req. Note that all register names
16632 should appear in both upper and lowercase variants. Some registers
16633 also have mixed-case names. */
16635 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16636 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16637 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16638 #define REGSET(p,t) \
16639 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16640 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16641 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16642 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16643 #define REGSETH(p,t) \
16644 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16645 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16646 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16647 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16648 #define REGSET2(p,t) \
16649 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16650 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16651 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16652 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16653 #define SPLRBANK(base,bank,t) \
16654 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16655 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16656 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16657 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16658 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16659 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16661 static const struct reg_entry reg_names[] =
16663 /* ARM integer registers. */
16664 REGSET(r, RN), REGSET(R, RN),
16666 /* ATPCS synonyms. */
16667 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
16668 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
16669 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
16671 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
16672 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
16673 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
16675 /* Well-known aliases. */
16676 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
16677 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
16679 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
16680 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
16682 /* Coprocessor numbers. */
16683 REGSET(p, CP), REGSET(P, CP),
16685 /* Coprocessor register numbers. The "cr" variants are for backward
16687 REGSET(c, CN), REGSET(C, CN),
16688 REGSET(cr, CN), REGSET(CR, CN),
16690 /* ARM banked registers. */
16691 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
16692 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
16693 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
16694 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
16695 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
16696 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
16697 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
16699 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
16700 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
16701 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
16702 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
16703 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
16704 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(SP_fiq,512|(13<<16),RNB),
16705 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
16706 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
16708 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
16709 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
16710 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
16711 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
16712 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
16713 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
16714 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
16715 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
16716 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
16718 /* FPA registers. */
16719 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
16720 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
16722 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
16723 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
16725 /* VFP SP registers. */
16726 REGSET(s,VFS), REGSET(S,VFS),
16727 REGSETH(s,VFS), REGSETH(S,VFS),
16729 /* VFP DP Registers. */
16730 REGSET(d,VFD), REGSET(D,VFD),
16731 /* Extra Neon DP registers. */
16732 REGSETH(d,VFD), REGSETH(D,VFD),
16734 /* Neon QP registers. */
16735 REGSET2(q,NQ), REGSET2(Q,NQ),
16737 /* VFP control registers. */
16738 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
16739 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
16740 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
16741 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
16742 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
16743 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
16745 /* Maverick DSP coprocessor registers. */
16746 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
16747 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
16749 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
16750 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
16751 REGDEF(dspsc,0,DSPSC),
16753 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
16754 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
16755 REGDEF(DSPSC,0,DSPSC),
16757 /* iWMMXt data registers - p0, c0-15. */
16758 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
16760 /* iWMMXt control registers - p1, c0-3. */
16761 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
16762 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
16763 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
16764 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
16766 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16767 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
16768 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
16769 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
16770 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
16772 /* XScale accumulator registers. */
16773 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
16779 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16780 within psr_required_here. */
16781 static const struct asm_psr psrs[] =
16783 /* Backward compatibility notation. Note that "all" is no longer
16784 truly all possible PSR bits. */
16785 {"all", PSR_c | PSR_f},
16789 /* Individual flags. */
16795 /* Combinations of flags. */
16796 {"fs", PSR_f | PSR_s},
16797 {"fx", PSR_f | PSR_x},
16798 {"fc", PSR_f | PSR_c},
16799 {"sf", PSR_s | PSR_f},
16800 {"sx", PSR_s | PSR_x},
16801 {"sc", PSR_s | PSR_c},
16802 {"xf", PSR_x | PSR_f},
16803 {"xs", PSR_x | PSR_s},
16804 {"xc", PSR_x | PSR_c},
16805 {"cf", PSR_c | PSR_f},
16806 {"cs", PSR_c | PSR_s},
16807 {"cx", PSR_c | PSR_x},
16808 {"fsx", PSR_f | PSR_s | PSR_x},
16809 {"fsc", PSR_f | PSR_s | PSR_c},
16810 {"fxs", PSR_f | PSR_x | PSR_s},
16811 {"fxc", PSR_f | PSR_x | PSR_c},
16812 {"fcs", PSR_f | PSR_c | PSR_s},
16813 {"fcx", PSR_f | PSR_c | PSR_x},
16814 {"sfx", PSR_s | PSR_f | PSR_x},
16815 {"sfc", PSR_s | PSR_f | PSR_c},
16816 {"sxf", PSR_s | PSR_x | PSR_f},
16817 {"sxc", PSR_s | PSR_x | PSR_c},
16818 {"scf", PSR_s | PSR_c | PSR_f},
16819 {"scx", PSR_s | PSR_c | PSR_x},
16820 {"xfs", PSR_x | PSR_f | PSR_s},
16821 {"xfc", PSR_x | PSR_f | PSR_c},
16822 {"xsf", PSR_x | PSR_s | PSR_f},
16823 {"xsc", PSR_x | PSR_s | PSR_c},
16824 {"xcf", PSR_x | PSR_c | PSR_f},
16825 {"xcs", PSR_x | PSR_c | PSR_s},
16826 {"cfs", PSR_c | PSR_f | PSR_s},
16827 {"cfx", PSR_c | PSR_f | PSR_x},
16828 {"csf", PSR_c | PSR_s | PSR_f},
16829 {"csx", PSR_c | PSR_s | PSR_x},
16830 {"cxf", PSR_c | PSR_x | PSR_f},
16831 {"cxs", PSR_c | PSR_x | PSR_s},
16832 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
16833 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
16834 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
16835 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
16836 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
16837 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
16838 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
16839 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
16840 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
16841 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
16842 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
16843 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
16844 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
16845 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
16846 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
16847 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
16848 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
16849 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
16850 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
16851 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
16852 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
16853 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
16854 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
16855 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
16858 /* Table of V7M psr names. */
16859 static const struct asm_psr v7m_psrs[] =
16861 {"apsr", 0 }, {"APSR", 0 },
16862 {"iapsr", 1 }, {"IAPSR", 1 },
16863 {"eapsr", 2 }, {"EAPSR", 2 },
16864 {"psr", 3 }, {"PSR", 3 },
16865 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16866 {"ipsr", 5 }, {"IPSR", 5 },
16867 {"epsr", 6 }, {"EPSR", 6 },
16868 {"iepsr", 7 }, {"IEPSR", 7 },
16869 {"msp", 8 }, {"MSP", 8 },
16870 {"psp", 9 }, {"PSP", 9 },
16871 {"primask", 16}, {"PRIMASK", 16},
16872 {"basepri", 17}, {"BASEPRI", 17},
16873 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16874 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16875 {"faultmask", 19}, {"FAULTMASK", 19},
16876 {"control", 20}, {"CONTROL", 20}
16879 /* Table of all shift-in-operand names. */
16880 static const struct asm_shift_name shift_names [] =
16882 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
16883 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
16884 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
16885 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
16886 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
16887 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
16890 /* Table of all explicit relocation names. */
16892 static struct reloc_entry reloc_names[] =
16894 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
16895 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
16896 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
16897 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
16898 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
16899 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
16900 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
16901 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
16902 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
16903 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
16904 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
16905 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
16906 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
16907 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
16908 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
16909 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
16910 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
16911 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
16915 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16916 static const struct asm_cond conds[] =
16920 {"cs", 0x2}, {"hs", 0x2},
16921 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16935 static struct asm_barrier_opt barrier_opt_names[] =
16937 { "sy", 0xf }, { "SY", 0xf },
16938 { "un", 0x7 }, { "UN", 0x7 },
16939 { "st", 0xe }, { "ST", 0xe },
16940 { "unst", 0x6 }, { "UNST", 0x6 },
16941 { "ish", 0xb }, { "ISH", 0xb },
16942 { "sh", 0xb }, { "SH", 0xb },
16943 { "ishst", 0xa }, { "ISHST", 0xa },
16944 { "shst", 0xa }, { "SHST", 0xa },
16945 { "nsh", 0x7 }, { "NSH", 0x7 },
16946 { "nshst", 0x6 }, { "NSHST", 0x6 },
16947 { "osh", 0x3 }, { "OSH", 0x3 },
16948 { "oshst", 0x2 }, { "OSHST", 0x2 }
16951 /* Table of ARM-format instructions. */
16953 /* Macros for gluing together operand strings. N.B. In all cases
16954 other than OPS0, the trailing OP_stop comes from default
16955 zero-initialization of the unspecified elements of the array. */
16956 #define OPS0() { OP_stop, }
16957 #define OPS1(a) { OP_##a, }
16958 #define OPS2(a,b) { OP_##a,OP_##b, }
16959 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16960 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16961 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16962 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16964 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16965 This is useful when mixing operands for ARM and THUMB, i.e. using the
16966 MIX_ARM_THUMB_OPERANDS macro.
16967 In order to use these macros, prefix the number of operands with _
16969 #define OPS_1(a) { a, }
16970 #define OPS_2(a,b) { a,b, }
16971 #define OPS_3(a,b,c) { a,b,c, }
16972 #define OPS_4(a,b,c,d) { a,b,c,d, }
16973 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16974 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16976 /* These macros abstract out the exact format of the mnemonic table and
16977 save some repeated characters. */
16979 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16980 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16981 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16982 THUMB_VARIANT, do_##ae, do_##te }
16984 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16985 a T_MNEM_xyz enumerator. */
16986 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16987 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16988 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16989 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16991 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16992 infix after the third character. */
16993 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16994 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16995 THUMB_VARIANT, do_##ae, do_##te }
16996 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16997 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16998 THUMB_VARIANT, do_##ae, do_##te }
16999 #define TC3(mnem, aop, top, nops, ops, ae, te) \
17000 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
17001 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
17002 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
17003 #define tC3(mnem, aop, top, nops, ops, ae, te) \
17004 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17005 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
17006 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
17008 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
17009 appear in the condition table. */
17010 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
17011 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17012 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
17014 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
17015 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
17016 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
17017 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
17018 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
17019 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
17020 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
17021 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
17022 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
17023 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
17024 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
17025 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
17026 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
17027 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
17028 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
17029 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
17030 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
17031 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
17032 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
17033 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
17035 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
17036 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
17037 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
17038 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
17040 /* Mnemonic that cannot be conditionalized. The ARM condition-code
17041 field is still 0xE. Many of the Thumb variants can be executed
17042 conditionally, so this is checked separately. */
17043 #define TUE(mnem, op, top, nops, ops, ae, te) \
17044 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17045 THUMB_VARIANT, do_##ae, do_##te }
17047 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17048 condition code field. */
17049 #define TUF(mnem, op, top, nops, ops, ae, te) \
17050 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
17051 THUMB_VARIANT, do_##ae, do_##te }
17053 /* ARM-only variants of all the above. */
17054 #define CE(mnem, op, nops, ops, ae) \
17055 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17057 #define C3(mnem, op, nops, ops, ae) \
17058 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17060 /* Legacy mnemonics that always have conditional infix after the third
17062 #define CL(mnem, op, nops, ops, ae) \
17063 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17064 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17066 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17067 #define cCE(mnem, op, nops, ops, ae) \
17068 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17070 /* Legacy coprocessor instructions where conditional infix and conditional
17071 suffix are ambiguous. For consistency this includes all FPA instructions,
17072 not just the potentially ambiguous ones. */
17073 #define cCL(mnem, op, nops, ops, ae) \
17074 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
17075 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17077 /* Coprocessor, takes either a suffix or a position-3 infix
17078 (for an FPA corner case). */
17079 #define C3E(mnem, op, nops, ops, ae) \
17080 { mnem, OPS##nops ops, OT_csuf_or_in3, \
17081 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17083 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
17084 { m1 #m2 m3, OPS##nops ops, \
17085 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
17086 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17088 #define CM(m1, m2, op, nops, ops, ae) \
17089 xCM_ (m1, , m2, op, nops, ops, ae), \
17090 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17091 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17092 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17093 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17094 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17095 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17096 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17097 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17098 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17099 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17100 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17101 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17102 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17103 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17104 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17105 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17106 xCM_ (m1, le, m2, op, nops, ops, ae), \
17107 xCM_ (m1, al, m2, op, nops, ops, ae)
17109 #define UE(mnem, op, nops, ops, ae) \
17110 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17112 #define UF(mnem, op, nops, ops, ae) \
17113 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17115 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17116 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17117 use the same encoding function for each. */
17118 #define NUF(mnem, op, nops, ops, enc) \
17119 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17120 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17122 /* Neon data processing, version which indirects through neon_enc_tab for
17123 the various overloaded versions of opcodes. */
17124 #define nUF(mnem, op, nops, ops, enc) \
17125 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17126 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17128 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17130 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17131 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17132 THUMB_VARIANT, do_##enc, do_##enc }
17134 #define NCE(mnem, op, nops, ops, enc) \
17135 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17137 #define NCEF(mnem, op, nops, ops, enc) \
17138 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17140 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17141 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17142 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17143 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17145 #define nCE(mnem, op, nops, ops, enc) \
17146 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17148 #define nCEF(mnem, op, nops, ops, enc) \
17149 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17153 static const struct asm_opcode insns[] =
17155 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17156 #define THUMB_VARIANT &arm_ext_v4t
17157 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17158 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17159 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17160 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17161 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17162 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17163 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17164 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17165 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17166 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17167 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17168 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17169 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17170 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17171 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17172 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
17174 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17175 for setting PSR flag bits. They are obsolete in V6 and do not
17176 have Thumb equivalents. */
17177 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17178 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17179 CL("tstp", 110f000, 2, (RR, SH), cmp),
17180 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17181 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17182 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17183 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17184 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17185 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17187 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17188 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17189 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17190 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
17192 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
17193 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17194 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
17196 OP_ADDRGLDR),ldst, t_ldst),
17197 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
17199 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17200 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17201 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17202 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17203 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17204 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17206 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
17207 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
17208 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
17209 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
17212 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
17213 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
17214 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
17216 /* Thumb-compatibility pseudo ops. */
17217 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
17218 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
17219 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
17220 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
17221 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
17222 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
17223 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
17224 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
17225 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
17226 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
17227 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
17228 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
17230 /* These may simplify to neg. */
17231 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
17232 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
17234 #undef THUMB_VARIANT
17235 #define THUMB_VARIANT & arm_ext_v6
17237 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
17239 /* V1 instructions with no Thumb analogue prior to V6T2. */
17240 #undef THUMB_VARIANT
17241 #define THUMB_VARIANT & arm_ext_v6t2
17243 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17244 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
17245 CL("teqp", 130f000, 2, (RR, SH), cmp),
17247 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17248 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17249 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
17250 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
17252 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17253 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17255 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17256 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
17258 /* V1 instructions with no Thumb analogue at all. */
17259 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
17260 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
17262 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
17263 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
17264 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
17265 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
17266 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
17267 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
17268 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
17269 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
17272 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17273 #undef THUMB_VARIANT
17274 #define THUMB_VARIANT & arm_ext_v4t
17276 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17277 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
17279 #undef THUMB_VARIANT
17280 #define THUMB_VARIANT & arm_ext_v6t2
17282 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17283 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
17285 /* Generic coprocessor instructions. */
17286 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17287 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17288 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17289 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17290 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17291 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17292 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
17295 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17297 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17298 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
17301 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17302 #undef THUMB_VARIANT
17303 #define THUMB_VARIANT & arm_ext_msr
17305 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
17306 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
17309 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17310 #undef THUMB_VARIANT
17311 #define THUMB_VARIANT & arm_ext_v6t2
17313 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17314 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17315 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17316 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17317 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17318 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17319 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
17320 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
17323 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17324 #undef THUMB_VARIANT
17325 #define THUMB_VARIANT & arm_ext_v4t
17327 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17328 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17329 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17330 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17331 tCM("ld","sh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17332 tCM("ld","sb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
17335 #define ARM_VARIANT & arm_ext_v4t_5
17337 /* ARM Architecture 4T. */
17338 /* Note: bx (and blx) are required on V5, even if the processor does
17339 not support Thumb. */
17340 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
17343 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17344 #undef THUMB_VARIANT
17345 #define THUMB_VARIANT & arm_ext_v5t
17347 /* Note: blx has 2 variants; the .value coded here is for
17348 BLX(2). Only this variant has conditional execution. */
17349 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
17350 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
17352 #undef THUMB_VARIANT
17353 #define THUMB_VARIANT & arm_ext_v6t2
17355 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
17356 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17357 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17358 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17359 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
17360 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
17361 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17362 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
17365 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17366 #undef THUMB_VARIANT
17367 #define THUMB_VARIANT &arm_ext_v5exp
17369 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17370 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17371 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17372 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17374 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17375 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
17377 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17378 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17379 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17380 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
17382 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17383 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17384 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17385 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17387 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17388 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17390 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17391 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17392 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17393 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
17396 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17397 #undef THUMB_VARIANT
17398 #define THUMB_VARIANT &arm_ext_v6t2
17400 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
17401 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
17403 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
17404 ADDRGLDRS), ldrd, t_ldstd),
17406 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17407 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17410 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17412 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
17415 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17416 #undef THUMB_VARIANT
17417 #define THUMB_VARIANT & arm_ext_v6
17419 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
17420 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
17421 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17422 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17423 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
17424 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17425 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17426 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17427 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17428 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
17430 #undef THUMB_VARIANT
17431 #define THUMB_VARIANT & arm_ext_v6t2
17433 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
17434 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17436 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17437 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
17439 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
17440 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
17442 /* ARM V6 not included in V7M. */
17443 #undef THUMB_VARIANT
17444 #define THUMB_VARIANT & arm_ext_v6_notm
17445 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17446 UF(rfeib, 9900a00, 1, (RRw), rfe),
17447 UF(rfeda, 8100a00, 1, (RRw), rfe),
17448 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17449 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
17450 UF(rfefa, 9900a00, 1, (RRw), rfe),
17451 UF(rfeea, 8100a00, 1, (RRw), rfe),
17452 TUF("rfeed", 9100a00, e810c000, 1, (RRw), rfe, rfe),
17453 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
17454 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
17455 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
17456 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
17458 /* ARM V6 not included in V7M (eg. integer SIMD). */
17459 #undef THUMB_VARIANT
17460 #define THUMB_VARIANT & arm_ext_v6_dsp
17461 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
17462 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
17463 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
17464 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17465 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17466 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17467 /* Old name for QASX. */
17468 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17469 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17470 /* Old name for QSAX. */
17471 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17472 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17473 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17474 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17475 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17476 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17477 /* Old name for SASX. */
17478 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17479 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17480 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17481 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17482 /* Old name for SHASX. */
17483 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17484 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17485 /* Old name for SHSAX. */
17486 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17487 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17488 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17489 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17490 /* Old name for SSAX. */
17491 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17492 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17493 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17494 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17495 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17496 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17497 /* Old name for UASX. */
17498 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17499 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17500 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17501 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17502 /* Old name for UHASX. */
17503 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17504 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17505 /* Old name for UHSAX. */
17506 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17507 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17508 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17509 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17510 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17511 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17512 /* Old name for UQASX. */
17513 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17514 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17515 /* Old name for UQSAX. */
17516 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17517 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17518 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17519 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17520 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17521 /* Old name for USAX. */
17522 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17523 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17524 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17525 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17526 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17527 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17528 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17529 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17530 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
17531 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
17532 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
17533 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17534 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17535 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17536 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17537 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17538 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17539 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17540 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
17541 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17542 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17543 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17544 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17545 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17546 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17547 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17548 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17549 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17550 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17551 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
17552 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
17553 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
17554 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
17555 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
17558 #define ARM_VARIANT & arm_ext_v6k
17559 #undef THUMB_VARIANT
17560 #define THUMB_VARIANT & arm_ext_v6k
17562 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
17563 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
17564 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
17565 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
17567 #undef THUMB_VARIANT
17568 #define THUMB_VARIANT & arm_ext_v6_notm
17569 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
17571 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
17572 RRnpcb), strexd, t_strexd),
17574 #undef THUMB_VARIANT
17575 #define THUMB_VARIANT & arm_ext_v6t2
17576 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
17578 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
17580 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17582 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
17584 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
17587 #define ARM_VARIANT & arm_ext_sec
17588 #undef THUMB_VARIANT
17589 #define THUMB_VARIANT & arm_ext_sec
17591 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
17594 #define ARM_VARIANT & arm_ext_virt
17595 #undef THUMB_VARIANT
17596 #define THUMB_VARIANT & arm_ext_virt
17598 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
17599 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
17602 #define ARM_VARIANT & arm_ext_v6t2
17603 #undef THUMB_VARIANT
17604 #define THUMB_VARIANT & arm_ext_v6t2
17606 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
17607 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
17608 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17609 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
17611 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
17612 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
17613 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
17614 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
17616 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17617 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17618 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17619 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
17621 /* Thumb-only instructions. */
17623 #define ARM_VARIANT NULL
17624 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
17625 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
17627 /* ARM does not really have an IT instruction, so always allow it.
17628 The opcode is copied from Thumb in order to allow warnings in
17629 -mimplicit-it=[never | arm] modes. */
17631 #define ARM_VARIANT & arm_ext_v1
17633 TUE("it", bf08, bf08, 1, (COND), it, t_it),
17634 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
17635 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
17636 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
17637 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
17638 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
17639 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
17640 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
17641 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
17642 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
17643 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
17644 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
17645 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
17646 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
17647 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
17648 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17649 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
17650 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
17652 /* Thumb2 only instructions. */
17654 #define ARM_VARIANT NULL
17656 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17657 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
17658 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
17659 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
17660 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
17661 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
17663 /* Hardware division instructions. */
17665 #define ARM_VARIANT & arm_ext_adiv
17666 #undef THUMB_VARIANT
17667 #define THUMB_VARIANT & arm_ext_div
17669 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
17670 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
17672 /* ARM V6M/V7 instructions. */
17674 #define ARM_VARIANT & arm_ext_barrier
17675 #undef THUMB_VARIANT
17676 #define THUMB_VARIANT & arm_ext_barrier
17678 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, t_barrier),
17679 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, t_barrier),
17680 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, t_barrier),
17682 /* ARM V7 instructions. */
17684 #define ARM_VARIANT & arm_ext_v7
17685 #undef THUMB_VARIANT
17686 #define THUMB_VARIANT & arm_ext_v7
17688 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
17689 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
17692 #define ARM_VARIANT & arm_ext_mp
17693 #undef THUMB_VARIANT
17694 #define THUMB_VARIANT & arm_ext_mp
17696 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
17699 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17701 cCE("wfs", e200110, 1, (RR), rd),
17702 cCE("rfs", e300110, 1, (RR), rd),
17703 cCE("wfc", e400110, 1, (RR), rd),
17704 cCE("rfc", e500110, 1, (RR), rd),
17706 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
17707 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
17708 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
17709 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
17711 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
17712 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
17713 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
17714 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
17716 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
17717 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
17718 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
17719 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
17720 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
17721 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
17722 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
17723 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
17724 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
17725 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
17726 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
17727 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
17729 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
17730 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
17731 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
17732 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
17733 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
17734 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
17735 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
17736 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
17737 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
17738 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
17739 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
17740 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
17742 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
17743 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
17744 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
17745 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
17746 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
17747 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
17748 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
17749 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
17750 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
17751 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
17752 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
17753 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
17755 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
17756 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
17757 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
17758 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
17759 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
17760 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
17761 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
17762 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
17763 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
17764 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
17765 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
17766 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
17768 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
17769 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
17770 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
17771 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
17772 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
17773 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
17774 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
17775 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
17776 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
17777 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
17778 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
17779 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
17781 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
17782 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
17783 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
17784 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
17785 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
17786 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
17787 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
17788 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
17789 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
17790 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
17791 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
17792 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
17794 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
17795 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
17796 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
17797 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
17798 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
17799 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
17800 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
17801 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
17802 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
17803 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
17804 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
17805 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
17807 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
17808 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
17809 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
17810 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
17811 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
17812 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
17813 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
17814 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
17815 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
17816 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
17817 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
17818 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
17820 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
17821 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
17822 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
17823 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
17824 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
17825 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
17826 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
17827 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
17828 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
17829 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
17830 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
17831 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
17833 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
17834 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
17835 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
17836 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
17837 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
17838 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
17839 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
17840 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
17841 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
17842 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
17843 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
17844 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
17846 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
17847 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
17848 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
17849 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
17850 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
17851 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
17852 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
17853 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
17854 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
17855 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
17856 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
17857 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
17859 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
17860 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
17861 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
17862 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
17863 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
17864 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
17865 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
17866 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
17867 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
17868 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
17869 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
17870 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
17872 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
17873 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
17874 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
17875 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
17876 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
17877 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
17878 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
17879 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
17880 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
17881 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
17882 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
17883 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
17885 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
17886 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
17887 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
17888 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
17889 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
17890 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
17891 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
17892 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
17893 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
17894 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
17895 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
17896 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
17898 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
17899 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
17900 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
17901 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
17902 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
17903 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
17904 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
17905 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
17906 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
17907 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
17908 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
17909 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
17911 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
17912 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
17913 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
17914 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
17915 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
17916 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
17917 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
17918 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
17919 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
17920 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
17921 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
17922 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
17924 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
17925 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
17926 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
17927 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
17928 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
17929 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17930 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17931 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17932 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
17933 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
17934 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
17935 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
17937 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
17938 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
17939 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
17940 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
17941 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
17942 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17943 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17944 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17945 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
17946 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
17947 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
17948 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
17950 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
17951 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
17952 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
17953 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
17954 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
17955 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17956 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17957 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17958 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
17959 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
17960 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
17961 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
17963 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
17964 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
17965 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
17966 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
17967 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
17968 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17969 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17970 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17971 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
17972 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
17973 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
17974 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
17976 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
17977 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
17978 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
17979 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
17980 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
17981 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17982 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17983 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17984 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
17985 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
17986 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
17987 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
17989 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
17990 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
17991 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
17992 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
17993 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
17994 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
17995 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
17996 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
17997 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
17998 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
17999 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18000 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18002 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18003 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18004 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18005 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18006 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18007 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18008 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18009 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18010 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18011 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18012 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18013 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18015 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18016 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18017 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18018 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18019 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18020 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18021 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18022 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18023 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18024 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18025 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18026 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18028 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18029 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18030 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18031 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18032 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18033 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18034 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18035 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18036 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18037 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18038 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18039 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18041 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18042 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18043 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18044 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18045 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18046 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18047 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18048 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18049 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18050 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18051 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18052 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18054 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18055 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18056 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18057 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18058 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18059 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18060 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18061 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18062 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18063 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18064 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18065 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18067 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18068 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18069 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18070 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18071 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18072 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18073 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18074 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18075 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18076 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18077 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18078 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18080 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18081 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18082 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18083 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18084 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18085 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18086 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18087 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18088 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18089 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18090 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18091 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18093 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
18094 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
18095 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
18096 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
18098 cCL("flts", e000110, 2, (RF, RR), rn_rd),
18099 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
18100 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
18101 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
18102 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
18103 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
18104 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
18105 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
18106 cCL("flte", e080110, 2, (RF, RR), rn_rd),
18107 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
18108 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
18109 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
18111 /* The implementation of the FIX instruction is broken on some
18112 assemblers, in that it accepts a precision specifier as well as a
18113 rounding specifier, despite the fact that this is meaningless.
18114 To be more compatible, we accept it as well, though of course it
18115 does not set any bits. */
18116 cCE("fix", e100110, 2, (RR, RF), rd_rm),
18117 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
18118 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
18119 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
18120 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
18121 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
18122 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
18123 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
18124 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
18125 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
18126 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
18127 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
18128 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
18130 /* Instructions that were new with the real FPA, call them V2. */
18132 #define ARM_VARIANT & fpu_fpa_ext_v2
18134 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18135 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18136 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18137 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18138 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18139 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
18142 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18144 /* Moves and type conversions. */
18145 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
18146 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
18147 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
18148 cCE("fmstat", ef1fa10, 0, (), noargs),
18149 cCE("vmrs", ef10a10, 2, (APSR_RR, RVC), vmrs),
18150 cCE("vmsr", ee10a10, 2, (RVC, RR), vmsr),
18151 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
18152 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
18153 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
18154 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18155 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
18156 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
18157 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
18158 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
18160 /* Memory operations. */
18161 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18162 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
18163 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18164 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18165 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18166 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18167 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18168 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18169 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18170 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18171 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18172 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
18173 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18174 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
18175 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18176 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
18177 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18178 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
18180 /* Monadic operations. */
18181 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
18182 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
18183 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
18185 /* Dyadic operations. */
18186 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18187 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18188 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18189 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18190 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18191 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18192 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18193 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18194 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18197 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
18198 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
18199 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
18200 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
18202 /* Double precision load/store are still present on single precision
18203 implementations. */
18204 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18205 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
18206 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18207 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18208 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18209 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18210 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18211 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
18212 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18213 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
18216 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18218 /* Moves and type conversions. */
18219 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18220 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18221 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18222 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
18223 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
18224 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
18225 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
18226 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
18227 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
18228 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18229 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18230 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
18231 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
18233 /* Monadic operations. */
18234 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18235 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18236 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18238 /* Dyadic operations. */
18239 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18240 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18241 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18242 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18243 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18244 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18245 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18246 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18247 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18250 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
18251 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
18252 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
18253 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
18256 #define ARM_VARIANT & fpu_vfp_ext_v2
18258 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
18259 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
18260 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
18261 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
18263 /* Instructions which may belong to either the Neon or VFP instruction sets.
18264 Individual encoder functions perform additional architecture checks. */
18266 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18267 #undef THUMB_VARIANT
18268 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18270 /* These mnemonics are unique to VFP. */
18271 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
18272 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
18273 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18274 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18275 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18276 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18277 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
18278 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
18279 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
18280 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
18282 /* Mnemonics shared by Neon and VFP. */
18283 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
18284 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18285 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
18287 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18288 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
18290 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18291 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
18293 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18294 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18295 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18296 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18297 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18298 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
18299 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18300 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
18302 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
18303 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
18304 nCEF(vcvtb, _vcvt, 2, (RVS, RVS), neon_cvtb),
18305 nCEF(vcvtt, _vcvt, 2, (RVS, RVS), neon_cvtt),
18308 /* NOTE: All VMOV encoding is special-cased! */
18309 NCE(vmov, 0, 1, (VMOV), neon_mov),
18310 NCE(vmovq, 0, 1, (VMOV), neon_mov),
18312 #undef THUMB_VARIANT
18313 #define THUMB_VARIANT & fpu_neon_ext_v1
18315 #define ARM_VARIANT & fpu_neon_ext_v1
18317 /* Data processing with three registers of the same length. */
18318 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18319 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
18320 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
18321 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18322 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18323 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18324 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18325 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
18326 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
18327 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18328 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18329 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18330 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
18331 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
18332 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18333 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18334 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
18335 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
18336 /* If not immediate, fall back to neon_dyadic_i64_su.
18337 shl_imm should accept I8 I16 I32 I64,
18338 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18339 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
18340 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
18341 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
18342 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
18343 /* Logic ops, types optional & ignored. */
18344 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18345 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18346 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18347 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18348 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18349 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18350 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
18351 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
18352 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
18353 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
18354 /* Bitfield ops, untyped. */
18355 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18356 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18357 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18358 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18359 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
18360 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
18361 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18362 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18363 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18364 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18365 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18366 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
18367 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
18368 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18369 back to neon_dyadic_if_su. */
18370 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18371 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18372 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
18373 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
18374 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18375 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18376 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
18377 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
18378 /* Comparison. Type I8 I16 I32 F32. */
18379 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
18380 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
18381 /* As above, D registers only. */
18382 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18383 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
18384 /* Int and float variants, signedness unimportant. */
18385 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18386 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
18387 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
18388 /* Add/sub take types I8 I16 I32 I64 F32. */
18389 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18390 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
18391 /* vtst takes sizes 8, 16, 32. */
18392 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
18393 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
18394 /* VMUL takes I8 I16 I32 F32 P8. */
18395 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
18396 /* VQD{R}MULH takes S16 S32. */
18397 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18398 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18399 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
18400 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
18401 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18402 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18403 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
18404 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
18405 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18406 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18407 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
18408 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
18409 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18410 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18411 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
18412 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
18414 /* Two address, int/float. Types S8 S16 S32 F32. */
18415 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
18416 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
18418 /* Data processing with two registers and a shift amount. */
18419 /* Right shifts, and variants with rounding.
18420 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18421 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18422 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18423 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
18424 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
18425 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18426 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18427 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
18428 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
18429 /* Shift and insert. Sizes accepted 8 16 32 64. */
18430 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
18431 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
18432 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
18433 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
18434 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18435 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
18436 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
18437 /* Right shift immediate, saturating & narrowing, with rounding variants.
18438 Types accepted S16 S32 S64 U16 U32 U64. */
18439 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18440 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
18441 /* As above, unsigned. Types accepted S16 S32 S64. */
18442 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18443 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
18444 /* Right shift narrowing. Types accepted I16 I32 I64. */
18445 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18446 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
18447 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18448 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
18449 /* CVT with optional immediate for fixed-point variant. */
18450 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
18452 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
18453 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
18455 /* Data processing, three registers of different lengths. */
18456 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18457 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
18458 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
18459 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
18460 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
18461 /* If not scalar, fall back to neon_dyadic_long.
18462 Vector types as above, scalar types S16 S32 U16 U32. */
18463 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18464 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
18465 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18466 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18467 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
18468 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18469 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18470 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18471 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18472 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
18473 /* Saturating doubling multiplies. Types S16 S32. */
18474 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18475 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18476 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
18477 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18478 S16 S32 U16 U32. */
18479 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
18481 /* Extract. Size 8. */
18482 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
18483 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
18485 /* Two registers, miscellaneous. */
18486 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18487 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
18488 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
18489 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
18490 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
18491 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
18492 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
18493 /* Vector replicate. Sizes 8 16 32. */
18494 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
18495 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
18496 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18497 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
18498 /* VMOVN. Types I16 I32 I64. */
18499 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
18500 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18501 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
18502 /* VQMOVUN. Types S16 S32 S64. */
18503 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
18504 /* VZIP / VUZP. Sizes 8 16 32. */
18505 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
18506 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
18507 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
18508 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
18509 /* VQABS / VQNEG. Types S8 S16 S32. */
18510 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18511 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
18512 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
18513 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
18514 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18515 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
18516 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
18517 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
18518 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
18519 /* Reciprocal estimates. Types U32 F32. */
18520 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
18521 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
18522 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
18523 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
18524 /* VCLS. Types S8 S16 S32. */
18525 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
18526 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
18527 /* VCLZ. Types I8 I16 I32. */
18528 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
18529 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
18530 /* VCNT. Size 8. */
18531 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
18532 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
18533 /* Two address, untyped. */
18534 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
18535 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
18536 /* VTRN. Sizes 8 16 32. */
18537 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
18538 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
18540 /* Table lookup. Size 8. */
18541 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18542 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
18544 #undef THUMB_VARIANT
18545 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18547 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18549 /* Neon element/structure load/store. */
18550 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18551 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
18552 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18553 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
18554 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18555 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
18556 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18557 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
18559 #undef THUMB_VARIANT
18560 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18562 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18563 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
18564 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18565 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18566 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18567 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18568 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18569 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18570 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
18571 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
18573 #undef THUMB_VARIANT
18574 #define THUMB_VARIANT & fpu_vfp_ext_v3
18576 #define ARM_VARIANT & fpu_vfp_ext_v3
18578 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
18579 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18580 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18581 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18582 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18583 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18584 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18585 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
18586 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
18589 #define ARM_VARIANT &fpu_vfp_ext_fma
18590 #undef THUMB_VARIANT
18591 #define THUMB_VARIANT &fpu_vfp_ext_fma
18592 /* Mnemonics shared by Neon and VFP. These are included in the
18593 VFP FMA variant; NEON and VFP FMA always includes the NEON
18594 FMA instructions. */
18595 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18596 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
18597 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18598 the v form should always be used. */
18599 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18600 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
18601 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18602 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
18603 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18604 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
18606 #undef THUMB_VARIANT
18608 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18610 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18611 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18612 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18613 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18614 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18615 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
18616 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
18617 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
18620 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18622 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
18623 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
18624 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
18625 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
18626 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
18627 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
18628 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
18629 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
18630 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
18631 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18632 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18633 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
18634 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18635 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18636 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
18637 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18638 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18639 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
18640 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
18641 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
18642 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18643 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18644 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18645 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18646 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18647 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
18648 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
18649 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
18650 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
18651 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
18652 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
18653 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
18654 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
18655 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
18656 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
18657 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
18658 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
18659 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18660 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18661 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18662 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18663 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18664 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18665 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18666 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18667 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18668 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
18669 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18670 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18671 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18672 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18673 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18674 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18675 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18676 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18677 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18678 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18679 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18680 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18681 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18682 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18683 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18684 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18685 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18686 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18687 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18688 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18689 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18690 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18691 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18692 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18693 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18694 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18695 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18696 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18697 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18698 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18699 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18700 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18701 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18702 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18703 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18704 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18705 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18706 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18707 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18708 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18709 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18710 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
18711 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18712 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18713 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18714 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18715 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18716 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18717 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18718 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18719 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18720 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18721 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18722 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18723 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18724 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18725 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18726 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18727 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18728 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18729 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18730 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18731 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18732 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
18733 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18734 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18735 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18736 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18737 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18738 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18739 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18740 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18741 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18742 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18743 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18744 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18745 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18746 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18747 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18748 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18749 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
18750 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
18751 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18752 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
18753 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
18754 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
18755 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18756 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18757 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18758 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18759 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18760 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18761 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18762 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18763 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18764 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
18765 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
18766 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
18767 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
18768 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
18769 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
18770 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18771 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18772 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18773 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
18774 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
18775 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
18776 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
18777 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
18778 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
18779 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18780 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18781 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18782 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18783 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
18786 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18788 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
18789 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
18790 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
18791 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
18792 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
18793 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
18794 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18795 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18796 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18797 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18798 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18799 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18800 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18801 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18802 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18803 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18804 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18805 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18806 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18807 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18808 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
18809 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18810 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18811 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18812 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18813 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18814 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18815 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18816 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18817 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18818 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18819 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18820 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18821 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18822 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18823 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18824 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18825 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18826 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18827 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18828 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18829 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18830 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18831 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18832 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18833 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18834 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18835 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18836 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18837 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18838 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18839 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18840 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18841 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18842 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18843 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18844 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
18847 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18849 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18850 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18851 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18852 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18853 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
18854 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
18855 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
18856 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
18857 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
18858 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
18859 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
18860 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
18861 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
18862 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
18863 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
18864 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
18865 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
18866 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
18867 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
18868 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
18869 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
18870 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
18871 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
18872 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
18873 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
18874 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
18875 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
18876 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
18877 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
18878 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
18879 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
18880 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
18881 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
18882 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
18883 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
18884 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
18885 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
18886 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
18887 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
18888 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
18889 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
18890 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
18891 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
18892 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
18893 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
18894 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
18895 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
18896 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
18897 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
18898 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
18899 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
18900 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
18901 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
18902 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
18903 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
18904 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
18905 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
18906 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
18907 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
18908 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
18909 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
18910 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
18911 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
18912 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
18913 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18914 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18915 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18916 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18917 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18918 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
18919 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18920 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
18921 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18922 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
18923 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18924 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
18927 #undef THUMB_VARIANT
18954 /* MD interface: bits in the object file. */
18956 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18957 for use in the a.out file, and stores them in the array pointed to by buf.
18958 This knows about the endian-ness of the target machine and does
18959 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18960 2 (short) and 4 (long) Floating numbers are put out as a series of
18961 LITTLENUMS (shorts, here at least). */
18964 md_number_to_chars (char * buf, valueT val, int n)
18966 if (target_big_endian)
18967 number_to_chars_bigendian (buf, val, n);
18969 number_to_chars_littleendian (buf, val, n);
18973 md_chars_to_number (char * buf, int n)
18976 unsigned char * where = (unsigned char *) buf;
18978 if (target_big_endian)
18983 result |= (*where++ & 255);
18991 result |= (where[n] & 255);
18998 /* MD interface: Sections. */
19000 /* Estimate the size of a frag before relaxing. Assume everything fits in
19004 md_estimate_size_before_relax (fragS * fragp,
19005 segT segtype ATTRIBUTE_UNUSED)
19011 /* Convert a machine dependent frag. */
19014 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19016 unsigned long insn;
19017 unsigned long old_op;
19025 buf = fragp->fr_literal + fragp->fr_fix;
19027 old_op = bfd_get_16(abfd, buf);
19028 if (fragp->fr_symbol)
19030 exp.X_op = O_symbol;
19031 exp.X_add_symbol = fragp->fr_symbol;
19035 exp.X_op = O_constant;
19037 exp.X_add_number = fragp->fr_offset;
19038 opcode = fragp->fr_subtype;
19041 case T_MNEM_ldr_pc:
19042 case T_MNEM_ldr_pc2:
19043 case T_MNEM_ldr_sp:
19044 case T_MNEM_str_sp:
19051 if (fragp->fr_var == 4)
19053 insn = THUMB_OP32 (opcode);
19054 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19056 insn |= (old_op & 0x700) << 4;
19060 insn |= (old_op & 7) << 12;
19061 insn |= (old_op & 0x38) << 13;
19063 insn |= 0x00000c00;
19064 put_thumb32_insn (buf, insn);
19065 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19069 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19071 pc_rel = (opcode == T_MNEM_ldr_pc2);
19074 if (fragp->fr_var == 4)
19076 insn = THUMB_OP32 (opcode);
19077 insn |= (old_op & 0xf0) << 4;
19078 put_thumb32_insn (buf, insn);
19079 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
19083 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19084 exp.X_add_number -= 4;
19092 if (fragp->fr_var == 4)
19094 int r0off = (opcode == T_MNEM_mov
19095 || opcode == T_MNEM_movs) ? 0 : 8;
19096 insn = THUMB_OP32 (opcode);
19097 insn = (insn & 0xe1ffffff) | 0x10000000;
19098 insn |= (old_op & 0x700) << r0off;
19099 put_thumb32_insn (buf, insn);
19100 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19104 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
19109 if (fragp->fr_var == 4)
19111 insn = THUMB_OP32(opcode);
19112 put_thumb32_insn (buf, insn);
19113 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
19116 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
19120 if (fragp->fr_var == 4)
19122 insn = THUMB_OP32(opcode);
19123 insn |= (old_op & 0xf00) << 14;
19124 put_thumb32_insn (buf, insn);
19125 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
19128 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
19131 case T_MNEM_add_sp:
19132 case T_MNEM_add_pc:
19133 case T_MNEM_inc_sp:
19134 case T_MNEM_dec_sp:
19135 if (fragp->fr_var == 4)
19137 /* ??? Choose between add and addw. */
19138 insn = THUMB_OP32 (opcode);
19139 insn |= (old_op & 0xf0) << 4;
19140 put_thumb32_insn (buf, insn);
19141 if (opcode == T_MNEM_add_pc)
19142 reloc_type = BFD_RELOC_ARM_T32_IMM12;
19144 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19147 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19155 if (fragp->fr_var == 4)
19157 insn = THUMB_OP32 (opcode);
19158 insn |= (old_op & 0xf0) << 4;
19159 insn |= (old_op & 0xf) << 16;
19160 put_thumb32_insn (buf, insn);
19161 if (insn & (1 << 20))
19162 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
19164 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
19167 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
19173 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
19174 (enum bfd_reloc_code_real) reloc_type);
19175 fixp->fx_file = fragp->fr_file;
19176 fixp->fx_line = fragp->fr_line;
19177 fragp->fr_fix += fragp->fr_var;
19180 /* Return the size of a relaxable immediate operand instruction.
19181 SHIFT and SIZE specify the form of the allowable immediate. */
19183 relax_immediate (fragS *fragp, int size, int shift)
19189 /* ??? Should be able to do better than this. */
19190 if (fragp->fr_symbol)
19193 low = (1 << shift) - 1;
19194 mask = (1 << (shift + size)) - (1 << shift);
19195 offset = fragp->fr_offset;
19196 /* Force misaligned offsets to 32-bit variant. */
19199 if (offset & ~mask)
19204 /* Get the address of a symbol during relaxation. */
19206 relaxed_symbol_addr (fragS *fragp, long stretch)
19212 sym = fragp->fr_symbol;
19213 sym_frag = symbol_get_frag (sym);
19214 know (S_GET_SEGMENT (sym) != absolute_section
19215 || sym_frag == &zero_address_frag);
19216 addr = S_GET_VALUE (sym) + fragp->fr_offset;
19218 /* If frag has yet to be reached on this pass, assume it will
19219 move by STRETCH just as we did. If this is not so, it will
19220 be because some frag between grows, and that will force
19224 && sym_frag->relax_marker != fragp->relax_marker)
19228 /* Adjust stretch for any alignment frag. Note that if have
19229 been expanding the earlier code, the symbol may be
19230 defined in what appears to be an earlier frag. FIXME:
19231 This doesn't handle the fr_subtype field, which specifies
19232 a maximum number of bytes to skip when doing an
19234 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
19236 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
19239 stretch = - ((- stretch)
19240 & ~ ((1 << (int) f->fr_offset) - 1));
19242 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
19254 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19257 relax_adr (fragS *fragp, asection *sec, long stretch)
19262 /* Assume worst case for symbols not known to be in the same section. */
19263 if (fragp->fr_symbol == NULL
19264 || !S_IS_DEFINED (fragp->fr_symbol)
19265 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19266 || S_IS_WEAK (fragp->fr_symbol))
19269 val = relaxed_symbol_addr (fragp, stretch);
19270 addr = fragp->fr_address + fragp->fr_fix;
19271 addr = (addr + 4) & ~3;
19272 /* Force misaligned targets to 32-bit variant. */
19276 if (val < 0 || val > 1020)
19281 /* Return the size of a relaxable add/sub immediate instruction. */
19283 relax_addsub (fragS *fragp, asection *sec)
19288 buf = fragp->fr_literal + fragp->fr_fix;
19289 op = bfd_get_16(sec->owner, buf);
19290 if ((op & 0xf) == ((op >> 4) & 0xf))
19291 return relax_immediate (fragp, 8, 0);
19293 return relax_immediate (fragp, 3, 0);
19297 /* Return the size of a relaxable branch instruction. BITS is the
19298 size of the offset field in the narrow instruction. */
19301 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
19307 /* Assume worst case for symbols not known to be in the same section. */
19308 if (!S_IS_DEFINED (fragp->fr_symbol)
19309 || sec != S_GET_SEGMENT (fragp->fr_symbol)
19310 || S_IS_WEAK (fragp->fr_symbol))
19314 if (S_IS_DEFINED (fragp->fr_symbol)
19315 && ARM_IS_FUNC (fragp->fr_symbol))
19318 /* PR 12532. Global symbols with default visibility might
19319 be preempted, so do not relax relocations to them. */
19320 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp->fr_symbol)) == STV_DEFAULT)
19321 && (! S_IS_LOCAL (fragp->fr_symbol)))
19325 val = relaxed_symbol_addr (fragp, stretch);
19326 addr = fragp->fr_address + fragp->fr_fix + 4;
19329 /* Offset is a signed value *2 */
19331 if (val >= limit || val < -limit)
19337 /* Relax a machine dependent frag. This returns the amount by which
19338 the current size of the frag should change. */
19341 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
19346 oldsize = fragp->fr_var;
19347 switch (fragp->fr_subtype)
19349 case T_MNEM_ldr_pc2:
19350 newsize = relax_adr (fragp, sec, stretch);
19352 case T_MNEM_ldr_pc:
19353 case T_MNEM_ldr_sp:
19354 case T_MNEM_str_sp:
19355 newsize = relax_immediate (fragp, 8, 2);
19359 newsize = relax_immediate (fragp, 5, 2);
19363 newsize = relax_immediate (fragp, 5, 1);
19367 newsize = relax_immediate (fragp, 5, 0);
19370 newsize = relax_adr (fragp, sec, stretch);
19376 newsize = relax_immediate (fragp, 8, 0);
19379 newsize = relax_branch (fragp, sec, 11, stretch);
19382 newsize = relax_branch (fragp, sec, 8, stretch);
19384 case T_MNEM_add_sp:
19385 case T_MNEM_add_pc:
19386 newsize = relax_immediate (fragp, 8, 2);
19388 case T_MNEM_inc_sp:
19389 case T_MNEM_dec_sp:
19390 newsize = relax_immediate (fragp, 7, 2);
19396 newsize = relax_addsub (fragp, sec);
19402 fragp->fr_var = newsize;
19403 /* Freeze wide instructions that are at or before the same location as
19404 in the previous pass. This avoids infinite loops.
19405 Don't freeze them unconditionally because targets may be artificially
19406 misaligned by the expansion of preceding frags. */
19407 if (stretch <= 0 && newsize > 2)
19409 md_convert_frag (sec->owner, sec, fragp);
19413 return newsize - oldsize;
19416 /* Round up a section size to the appropriate boundary. */
19419 md_section_align (segT segment ATTRIBUTE_UNUSED,
19422 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19423 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
19425 /* For a.out, force the section size to be aligned. If we don't do
19426 this, BFD will align it for us, but it will not write out the
19427 final bytes of the section. This may be a bug in BFD, but it is
19428 easier to fix it here since that is how the other a.out targets
19432 align = bfd_get_section_alignment (stdoutput, segment);
19433 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
19440 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19441 of an rs_align_code fragment. */
19444 arm_handle_align (fragS * fragP)
19446 static char const arm_noop[2][2][4] =
19449 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19450 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19453 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19454 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19457 static char const thumb_noop[2][2][2] =
19460 {0xc0, 0x46}, /* LE */
19461 {0x46, 0xc0}, /* BE */
19464 {0x00, 0xbf}, /* LE */
19465 {0xbf, 0x00} /* BE */
19468 static char const wide_thumb_noop[2][4] =
19469 { /* Wide Thumb-2 */
19470 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19471 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19474 unsigned bytes, fix, noop_size;
19477 const char *narrow_noop = NULL;
19482 if (fragP->fr_type != rs_align_code)
19485 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
19486 p = fragP->fr_literal + fragP->fr_fix;
19489 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
19490 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
19492 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
19494 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
19496 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
19498 narrow_noop = thumb_noop[1][target_big_endian];
19499 noop = wide_thumb_noop[target_big_endian];
19502 noop = thumb_noop[0][target_big_endian];
19510 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
19511 [target_big_endian];
19518 fragP->fr_var = noop_size;
19520 if (bytes & (noop_size - 1))
19522 fix = bytes & (noop_size - 1);
19524 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
19526 memset (p, 0, fix);
19533 if (bytes & noop_size)
19535 /* Insert a narrow noop. */
19536 memcpy (p, narrow_noop, noop_size);
19538 bytes -= noop_size;
19542 /* Use wide noops for the remainder */
19546 while (bytes >= noop_size)
19548 memcpy (p, noop, noop_size);
19550 bytes -= noop_size;
19554 fragP->fr_fix += fix;
19557 /* Called from md_do_align. Used to create an alignment
19558 frag in a code section. */
19561 arm_frag_align_code (int n, int max)
19565 /* We assume that there will never be a requirement
19566 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19567 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
19572 _("alignments greater than %d bytes not supported in .text sections."),
19573 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
19574 as_fatal ("%s", err_msg);
19577 p = frag_var (rs_align_code,
19578 MAX_MEM_FOR_RS_ALIGN_CODE,
19580 (relax_substateT) max,
19587 /* Perform target specific initialisation of a frag.
19588 Note - despite the name this initialisation is not done when the frag
19589 is created, but only when its type is assigned. A frag can be created
19590 and used a long time before its type is set, so beware of assuming that
19591 this initialisationis performed first. */
19595 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
19597 /* Record whether this frag is in an ARM or a THUMB area. */
19598 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19601 #else /* OBJ_ELF is defined. */
19603 arm_init_frag (fragS * fragP, int max_chars)
19605 /* If the current ARM vs THUMB mode has not already
19606 been recorded into this frag then do so now. */
19607 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
19609 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
19611 /* Record a mapping symbol for alignment frags. We will delete this
19612 later if the alignment ends up empty. */
19613 switch (fragP->fr_type)
19616 case rs_align_test:
19618 mapping_state_2 (MAP_DATA, max_chars);
19620 case rs_align_code:
19621 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
19629 /* When we change sections we need to issue a new mapping symbol. */
19632 arm_elf_change_section (void)
19634 /* Link an unlinked unwind index table section to the .text section. */
19635 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
19636 && elf_linked_to_section (now_seg) == NULL)
19637 elf_linked_to_section (now_seg) = text_section;
19641 arm_elf_section_type (const char * str, size_t len)
19643 if (len == 5 && strncmp (str, "exidx", 5) == 0)
19644 return SHT_ARM_EXIDX;
19649 /* Code to deal with unwinding tables. */
19651 static void add_unwind_adjustsp (offsetT);
19653 /* Generate any deferred unwind frame offset. */
19656 flush_pending_unwind (void)
19660 offset = unwind.pending_offset;
19661 unwind.pending_offset = 0;
19663 add_unwind_adjustsp (offset);
19666 /* Add an opcode to this list for this function. Two-byte opcodes should
19667 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19671 add_unwind_opcode (valueT op, int length)
19673 /* Add any deferred stack adjustment. */
19674 if (unwind.pending_offset)
19675 flush_pending_unwind ();
19677 unwind.sp_restored = 0;
19679 if (unwind.opcode_count + length > unwind.opcode_alloc)
19681 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
19682 if (unwind.opcodes)
19683 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
19684 unwind.opcode_alloc);
19686 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
19691 unwind.opcodes[unwind.opcode_count] = op & 0xff;
19693 unwind.opcode_count++;
19697 /* Add unwind opcodes to adjust the stack pointer. */
19700 add_unwind_adjustsp (offsetT offset)
19704 if (offset > 0x200)
19706 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19711 /* Long form: 0xb2, uleb128. */
19712 /* This might not fit in a word so add the individual bytes,
19713 remembering the list is built in reverse order. */
19714 o = (valueT) ((offset - 0x204) >> 2);
19716 add_unwind_opcode (0, 1);
19718 /* Calculate the uleb128 encoding of the offset. */
19722 bytes[n] = o & 0x7f;
19728 /* Add the insn. */
19730 add_unwind_opcode (bytes[n - 1], 1);
19731 add_unwind_opcode (0xb2, 1);
19733 else if (offset > 0x100)
19735 /* Two short opcodes. */
19736 add_unwind_opcode (0x3f, 1);
19737 op = (offset - 0x104) >> 2;
19738 add_unwind_opcode (op, 1);
19740 else if (offset > 0)
19742 /* Short opcode. */
19743 op = (offset - 4) >> 2;
19744 add_unwind_opcode (op, 1);
19746 else if (offset < 0)
19749 while (offset > 0x100)
19751 add_unwind_opcode (0x7f, 1);
19754 op = ((offset - 4) >> 2) | 0x40;
19755 add_unwind_opcode (op, 1);
19759 /* Finish the list of unwind opcodes for this function. */
19761 finish_unwind_opcodes (void)
19765 if (unwind.fp_used)
19767 /* Adjust sp as necessary. */
19768 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
19769 flush_pending_unwind ();
19771 /* After restoring sp from the frame pointer. */
19772 op = 0x90 | unwind.fp_reg;
19773 add_unwind_opcode (op, 1);
19776 flush_pending_unwind ();
19780 /* Start an exception table entry. If idx is nonzero this is an index table
19784 start_unwind_section (const segT text_seg, int idx)
19786 const char * text_name;
19787 const char * prefix;
19788 const char * prefix_once;
19789 const char * group_name;
19793 size_t sec_name_len;
19800 prefix = ELF_STRING_ARM_unwind;
19801 prefix_once = ELF_STRING_ARM_unwind_once;
19802 type = SHT_ARM_EXIDX;
19806 prefix = ELF_STRING_ARM_unwind_info;
19807 prefix_once = ELF_STRING_ARM_unwind_info_once;
19808 type = SHT_PROGBITS;
19811 text_name = segment_name (text_seg);
19812 if (streq (text_name, ".text"))
19815 if (strncmp (text_name, ".gnu.linkonce.t.",
19816 strlen (".gnu.linkonce.t.")) == 0)
19818 prefix = prefix_once;
19819 text_name += strlen (".gnu.linkonce.t.");
19822 prefix_len = strlen (prefix);
19823 text_len = strlen (text_name);
19824 sec_name_len = prefix_len + text_len;
19825 sec_name = (char *) xmalloc (sec_name_len + 1);
19826 memcpy (sec_name, prefix, prefix_len);
19827 memcpy (sec_name + prefix_len, text_name, text_len);
19828 sec_name[prefix_len + text_len] = '\0';
19834 /* Handle COMDAT group. */
19835 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
19837 group_name = elf_group_name (text_seg);
19838 if (group_name == NULL)
19840 as_bad (_("Group section `%s' has no group signature"),
19841 segment_name (text_seg));
19842 ignore_rest_of_line ();
19845 flags |= SHF_GROUP;
19849 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
19851 /* Set the section link for index tables. */
19853 elf_linked_to_section (now_seg) = text_seg;
19857 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19858 personality routine data. Returns zero, or the index table value for
19859 and inline entry. */
19862 create_unwind_entry (int have_data)
19867 /* The current word of data. */
19869 /* The number of bytes left in this word. */
19872 finish_unwind_opcodes ();
19874 /* Remember the current text section. */
19875 unwind.saved_seg = now_seg;
19876 unwind.saved_subseg = now_subseg;
19878 start_unwind_section (now_seg, 0);
19880 if (unwind.personality_routine == NULL)
19882 if (unwind.personality_index == -2)
19885 as_bad (_("handlerdata in cantunwind frame"));
19886 return 1; /* EXIDX_CANTUNWIND. */
19889 /* Use a default personality routine if none is specified. */
19890 if (unwind.personality_index == -1)
19892 if (unwind.opcode_count > 3)
19893 unwind.personality_index = 1;
19895 unwind.personality_index = 0;
19898 /* Space for the personality routine entry. */
19899 if (unwind.personality_index == 0)
19901 if (unwind.opcode_count > 3)
19902 as_bad (_("too many unwind opcodes for personality routine 0"));
19906 /* All the data is inline in the index table. */
19909 while (unwind.opcode_count > 0)
19911 unwind.opcode_count--;
19912 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19916 /* Pad with "finish" opcodes. */
19918 data = (data << 8) | 0xb0;
19925 /* We get two opcodes "free" in the first word. */
19926 size = unwind.opcode_count - 2;
19929 /* An extra byte is required for the opcode count. */
19930 size = unwind.opcode_count + 1;
19932 size = (size + 3) >> 2;
19934 as_bad (_("too many unwind opcodes"));
19936 frag_align (2, 0, 0);
19937 record_alignment (now_seg, 2);
19938 unwind.table_entry = expr_build_dot ();
19940 /* Allocate the table entry. */
19941 ptr = frag_more ((size << 2) + 4);
19942 where = frag_now_fix () - ((size << 2) + 4);
19944 switch (unwind.personality_index)
19947 /* ??? Should this be a PLT generating relocation? */
19948 /* Custom personality routine. */
19949 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
19950 BFD_RELOC_ARM_PREL31);
19955 /* Set the first byte to the number of additional words. */
19960 /* ABI defined personality routines. */
19962 /* Three opcodes bytes are packed into the first word. */
19969 /* The size and first two opcode bytes go in the first word. */
19970 data = ((0x80 + unwind.personality_index) << 8) | size;
19975 /* Should never happen. */
19979 /* Pack the opcodes into words (MSB first), reversing the list at the same
19981 while (unwind.opcode_count > 0)
19985 md_number_to_chars (ptr, data, 4);
19990 unwind.opcode_count--;
19992 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
19995 /* Finish off the last word. */
19998 /* Pad with "finish" opcodes. */
20000 data = (data << 8) | 0xb0;
20002 md_number_to_chars (ptr, data, 4);
20007 /* Add an empty descriptor if there is no user-specified data. */
20008 ptr = frag_more (4);
20009 md_number_to_chars (ptr, 0, 4);
20016 /* Initialize the DWARF-2 unwind information for this procedure. */
20019 tc_arm_frame_initial_instructions (void)
20021 cfi_add_CFA_def_cfa (REG_SP, 0);
20023 #endif /* OBJ_ELF */
20025 /* Convert REGNAME to a DWARF-2 register number. */
20028 tc_arm_regname_to_dw2regnum (char *regname)
20030 int reg = arm_reg_parse (®name, REG_TYPE_RN);
20040 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
20044 exp.X_op = O_secrel;
20045 exp.X_add_symbol = symbol;
20046 exp.X_add_number = 0;
20047 emit_expr (&exp, size);
20051 /* MD interface: Symbol and relocation handling. */
20053 /* Return the address within the segment that a PC-relative fixup is
20054 relative to. For ARM, PC-relative fixups applied to instructions
20055 are generally relative to the location of the fixup plus 8 bytes.
20056 Thumb branches are offset by 4, and Thumb loads relative to PC
20057 require special handling. */
20060 md_pcrel_from_section (fixS * fixP, segT seg)
20062 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
20064 /* If this is pc-relative and we are going to emit a relocation
20065 then we just want to put out any pipeline compensation that the linker
20066 will need. Otherwise we want to use the calculated base.
20067 For WinCE we skip the bias for externals as well, since this
20068 is how the MS ARM-CE assembler behaves and we want to be compatible. */
20070 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
20071 || (arm_force_relocation (fixP)
20073 && !S_IS_EXTERNAL (fixP->fx_addsy)
20079 switch (fixP->fx_r_type)
20081 /* PC relative addressing on the Thumb is slightly odd as the
20082 bottom two bits of the PC are forced to zero for the
20083 calculation. This happens *after* application of the
20084 pipeline offset. However, Thumb adrl already adjusts for
20085 this, so we need not do it again. */
20086 case BFD_RELOC_ARM_THUMB_ADD:
20089 case BFD_RELOC_ARM_THUMB_OFFSET:
20090 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20091 case BFD_RELOC_ARM_T32_ADD_PC12:
20092 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
20093 return (base + 4) & ~3;
20095 /* Thumb branches are simply offset by +4. */
20096 case BFD_RELOC_THUMB_PCREL_BRANCH7:
20097 case BFD_RELOC_THUMB_PCREL_BRANCH9:
20098 case BFD_RELOC_THUMB_PCREL_BRANCH12:
20099 case BFD_RELOC_THUMB_PCREL_BRANCH20:
20100 case BFD_RELOC_THUMB_PCREL_BRANCH25:
20103 case BFD_RELOC_THUMB_PCREL_BRANCH23:
20105 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20106 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20107 && ARM_IS_FUNC (fixP->fx_addsy)
20108 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20109 base = fixP->fx_where + fixP->fx_frag->fr_address;
20112 /* BLX is like branches above, but forces the low two bits of PC to
20114 case BFD_RELOC_THUMB_PCREL_BLX:
20116 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20117 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20118 && THUMB_IS_FUNC (fixP->fx_addsy)
20119 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20120 base = fixP->fx_where + fixP->fx_frag->fr_address;
20121 return (base + 4) & ~3;
20123 /* ARM mode branches are offset by +8. However, the Windows CE
20124 loader expects the relocation not to take this into account. */
20125 case BFD_RELOC_ARM_PCREL_BLX:
20127 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20128 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20129 && ARM_IS_FUNC (fixP->fx_addsy)
20130 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20131 base = fixP->fx_where + fixP->fx_frag->fr_address;
20134 case BFD_RELOC_ARM_PCREL_CALL:
20136 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20137 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20138 && THUMB_IS_FUNC (fixP->fx_addsy)
20139 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
20140 base = fixP->fx_where + fixP->fx_frag->fr_address;
20143 case BFD_RELOC_ARM_PCREL_BRANCH:
20144 case BFD_RELOC_ARM_PCREL_JUMP:
20145 case BFD_RELOC_ARM_PLT32:
20147 /* When handling fixups immediately, because we have already
20148 discovered the value of a symbol, or the address of the frag involved
20149 we must account for the offset by +8, as the OS loader will never see the reloc.
20150 see fixup_segment() in write.c
20151 The S_IS_EXTERNAL test handles the case of global symbols.
20152 Those need the calculated base, not just the pipe compensation the linker will need. */
20154 && fixP->fx_addsy != NULL
20155 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20156 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
20164 /* ARM mode loads relative to PC are also offset by +8. Unlike
20165 branches, the Windows CE loader *does* expect the relocation
20166 to take this into account. */
20167 case BFD_RELOC_ARM_OFFSET_IMM:
20168 case BFD_RELOC_ARM_OFFSET_IMM8:
20169 case BFD_RELOC_ARM_HWLITERAL:
20170 case BFD_RELOC_ARM_LITERAL:
20171 case BFD_RELOC_ARM_CP_OFF_IMM:
20175 /* Other PC-relative relocations are un-offset. */
20181 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20182 Otherwise we have no need to default values of symbols. */
20185 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
20188 if (name[0] == '_' && name[1] == 'G'
20189 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
20193 if (symbol_find (name))
20194 as_bad (_("GOT already in the symbol table"));
20196 GOT_symbol = symbol_new (name, undefined_section,
20197 (valueT) 0, & zero_address_frag);
20207 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20208 computed as two separate immediate values, added together. We
20209 already know that this value cannot be computed by just one ARM
20212 static unsigned int
20213 validate_immediate_twopart (unsigned int val,
20214 unsigned int * highpart)
20219 for (i = 0; i < 32; i += 2)
20220 if (((a = rotate_left (val, i)) & 0xff) != 0)
20226 * highpart = (a >> 8) | ((i + 24) << 7);
20228 else if (a & 0xff0000)
20230 if (a & 0xff000000)
20232 * highpart = (a >> 16) | ((i + 16) << 7);
20236 gas_assert (a & 0xff000000);
20237 * highpart = (a >> 24) | ((i + 8) << 7);
20240 return (a & 0xff) | (i << 7);
20247 validate_offset_imm (unsigned int val, int hwse)
20249 if ((hwse && val > 255) || val > 4095)
20254 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20255 negative immediate constant by altering the instruction. A bit of
20260 by inverting the second operand, and
20263 by negating the second operand. */
20266 negate_data_op (unsigned long * instruction,
20267 unsigned long value)
20270 unsigned long negated, inverted;
20272 negated = encode_arm_immediate (-value);
20273 inverted = encode_arm_immediate (~value);
20275 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
20278 /* First negates. */
20279 case OPCODE_SUB: /* ADD <-> SUB */
20280 new_inst = OPCODE_ADD;
20285 new_inst = OPCODE_SUB;
20289 case OPCODE_CMP: /* CMP <-> CMN */
20290 new_inst = OPCODE_CMN;
20295 new_inst = OPCODE_CMP;
20299 /* Now Inverted ops. */
20300 case OPCODE_MOV: /* MOV <-> MVN */
20301 new_inst = OPCODE_MVN;
20306 new_inst = OPCODE_MOV;
20310 case OPCODE_AND: /* AND <-> BIC */
20311 new_inst = OPCODE_BIC;
20316 new_inst = OPCODE_AND;
20320 case OPCODE_ADC: /* ADC <-> SBC */
20321 new_inst = OPCODE_SBC;
20326 new_inst = OPCODE_ADC;
20330 /* We cannot do anything. */
20335 if (value == (unsigned) FAIL)
20338 *instruction &= OPCODE_MASK;
20339 *instruction |= new_inst << DATA_OP_SHIFT;
20343 /* Like negate_data_op, but for Thumb-2. */
20345 static unsigned int
20346 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
20350 unsigned int negated, inverted;
20352 negated = encode_thumb32_immediate (-value);
20353 inverted = encode_thumb32_immediate (~value);
20355 rd = (*instruction >> 8) & 0xf;
20356 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
20359 /* ADD <-> SUB. Includes CMP <-> CMN. */
20360 case T2_OPCODE_SUB:
20361 new_inst = T2_OPCODE_ADD;
20365 case T2_OPCODE_ADD:
20366 new_inst = T2_OPCODE_SUB;
20370 /* ORR <-> ORN. Includes MOV <-> MVN. */
20371 case T2_OPCODE_ORR:
20372 new_inst = T2_OPCODE_ORN;
20376 case T2_OPCODE_ORN:
20377 new_inst = T2_OPCODE_ORR;
20381 /* AND <-> BIC. TST has no inverted equivalent. */
20382 case T2_OPCODE_AND:
20383 new_inst = T2_OPCODE_BIC;
20390 case T2_OPCODE_BIC:
20391 new_inst = T2_OPCODE_AND;
20396 case T2_OPCODE_ADC:
20397 new_inst = T2_OPCODE_SBC;
20401 case T2_OPCODE_SBC:
20402 new_inst = T2_OPCODE_ADC;
20406 /* We cannot do anything. */
20411 if (value == (unsigned int)FAIL)
20414 *instruction &= T2_OPCODE_MASK;
20415 *instruction |= new_inst << T2_DATA_OP_SHIFT;
20419 /* Read a 32-bit thumb instruction from buf. */
20420 static unsigned long
20421 get_thumb32_insn (char * buf)
20423 unsigned long insn;
20424 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
20425 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20431 /* We usually want to set the low bit on the address of thumb function
20432 symbols. In particular .word foo - . should have the low bit set.
20433 Generic code tries to fold the difference of two symbols to
20434 a constant. Prevent this and force a relocation when the first symbols
20435 is a thumb function. */
20438 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
20440 if (op == O_subtract
20441 && l->X_op == O_symbol
20442 && r->X_op == O_symbol
20443 && THUMB_IS_FUNC (l->X_add_symbol))
20445 l->X_op = O_subtract;
20446 l->X_op_symbol = r->X_add_symbol;
20447 l->X_add_number -= r->X_add_number;
20451 /* Process as normal. */
20455 /* Encode Thumb2 unconditional branches and calls. The encoding
20456 for the 2 are identical for the immediate values. */
20459 encode_thumb2_b_bl_offset (char * buf, offsetT value)
20461 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20464 addressT S, I1, I2, lo, hi;
20466 S = (value >> 24) & 0x01;
20467 I1 = (value >> 23) & 0x01;
20468 I2 = (value >> 22) & 0x01;
20469 hi = (value >> 12) & 0x3ff;
20470 lo = (value >> 1) & 0x7ff;
20471 newval = md_chars_to_number (buf, THUMB_SIZE);
20472 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
20473 newval |= (S << 10) | hi;
20474 newval2 &= ~T2I1I2MASK;
20475 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
20476 md_number_to_chars (buf, newval, THUMB_SIZE);
20477 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
20481 md_apply_fix (fixS * fixP,
20485 offsetT value = * valP;
20487 unsigned int newimm;
20488 unsigned long temp;
20490 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
20492 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
20494 /* Note whether this will delete the relocation. */
20496 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
20499 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20500 consistency with the behaviour on 32-bit hosts. Remember value
20502 value &= 0xffffffff;
20503 value ^= 0x80000000;
20504 value -= 0x80000000;
20507 fixP->fx_addnumber = value;
20509 /* Same treatment for fixP->fx_offset. */
20510 fixP->fx_offset &= 0xffffffff;
20511 fixP->fx_offset ^= 0x80000000;
20512 fixP->fx_offset -= 0x80000000;
20514 switch (fixP->fx_r_type)
20516 case BFD_RELOC_NONE:
20517 /* This will need to go in the object file. */
20521 case BFD_RELOC_ARM_IMMEDIATE:
20522 /* We claim that this fixup has been processed here,
20523 even if in fact we generate an error because we do
20524 not have a reloc for it, so tc_gen_reloc will reject it. */
20527 if (fixP->fx_addsy)
20529 const char *msg = 0;
20531 if (! S_IS_DEFINED (fixP->fx_addsy))
20532 msg = _("undefined symbol %s used as an immediate value");
20533 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20534 msg = _("symbol %s is in a different section");
20535 else if (S_IS_WEAK (fixP->fx_addsy))
20536 msg = _("symbol %s is weak and may be overridden later");
20540 as_bad_where (fixP->fx_file, fixP->fx_line,
20541 msg, S_GET_NAME (fixP->fx_addsy));
20546 newimm = encode_arm_immediate (value);
20547 temp = md_chars_to_number (buf, INSN_SIZE);
20549 /* If the instruction will fail, see if we can fix things up by
20550 changing the opcode. */
20551 if (newimm == (unsigned int) FAIL
20552 && (newimm = negate_data_op (&temp, value)) == (unsigned int) FAIL)
20554 as_bad_where (fixP->fx_file, fixP->fx_line,
20555 _("invalid constant (%lx) after fixup"),
20556 (unsigned long) value);
20560 newimm |= (temp & 0xfffff000);
20561 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20564 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
20566 unsigned int highpart = 0;
20567 unsigned int newinsn = 0xe1a00000; /* nop. */
20569 if (fixP->fx_addsy)
20571 const char *msg = 0;
20573 if (! S_IS_DEFINED (fixP->fx_addsy))
20574 msg = _("undefined symbol %s used as an immediate value");
20575 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
20576 msg = _("symbol %s is in a different section");
20577 else if (S_IS_WEAK (fixP->fx_addsy))
20578 msg = _("symbol %s is weak and may be overridden later");
20582 as_bad_where (fixP->fx_file, fixP->fx_line,
20583 msg, S_GET_NAME (fixP->fx_addsy));
20588 newimm = encode_arm_immediate (value);
20589 temp = md_chars_to_number (buf, INSN_SIZE);
20591 /* If the instruction will fail, see if we can fix things up by
20592 changing the opcode. */
20593 if (newimm == (unsigned int) FAIL
20594 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
20596 /* No ? OK - try using two ADD instructions to generate
20598 newimm = validate_immediate_twopart (value, & highpart);
20600 /* Yes - then make sure that the second instruction is
20602 if (newimm != (unsigned int) FAIL)
20604 /* Still No ? Try using a negated value. */
20605 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
20606 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
20607 /* Otherwise - give up. */
20610 as_bad_where (fixP->fx_file, fixP->fx_line,
20611 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20616 /* Replace the first operand in the 2nd instruction (which
20617 is the PC) with the destination register. We have
20618 already added in the PC in the first instruction and we
20619 do not want to do it again. */
20620 newinsn &= ~ 0xf0000;
20621 newinsn |= ((newinsn & 0x0f000) << 4);
20624 newimm |= (temp & 0xfffff000);
20625 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
20627 highpart |= (newinsn & 0xfffff000);
20628 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
20632 case BFD_RELOC_ARM_OFFSET_IMM:
20633 if (!fixP->fx_done && seg->use_rela_p)
20636 case BFD_RELOC_ARM_LITERAL:
20642 if (validate_offset_imm (value, 0) == FAIL)
20644 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
20645 as_bad_where (fixP->fx_file, fixP->fx_line,
20646 _("invalid literal constant: pool needs to be closer"));
20648 as_bad_where (fixP->fx_file, fixP->fx_line,
20649 _("bad immediate value for offset (%ld)"),
20654 newval = md_chars_to_number (buf, INSN_SIZE);
20656 newval &= 0xfffff000;
20659 newval &= 0xff7ff000;
20660 newval |= value | (sign ? INDEX_UP : 0);
20662 md_number_to_chars (buf, newval, INSN_SIZE);
20665 case BFD_RELOC_ARM_OFFSET_IMM8:
20666 case BFD_RELOC_ARM_HWLITERAL:
20672 if (validate_offset_imm (value, 1) == FAIL)
20674 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
20675 as_bad_where (fixP->fx_file, fixP->fx_line,
20676 _("invalid literal constant: pool needs to be closer"));
20678 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20683 newval = md_chars_to_number (buf, INSN_SIZE);
20685 newval &= 0xfffff0f0;
20688 newval &= 0xff7ff0f0;
20689 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
20691 md_number_to_chars (buf, newval, INSN_SIZE);
20694 case BFD_RELOC_ARM_T32_OFFSET_U8:
20695 if (value < 0 || value > 1020 || value % 4 != 0)
20696 as_bad_where (fixP->fx_file, fixP->fx_line,
20697 _("bad immediate value for offset (%ld)"), (long) value);
20700 newval = md_chars_to_number (buf+2, THUMB_SIZE);
20702 md_number_to_chars (buf+2, newval, THUMB_SIZE);
20705 case BFD_RELOC_ARM_T32_OFFSET_IMM:
20706 /* This is a complicated relocation used for all varieties of Thumb32
20707 load/store instruction with immediate offset:
20709 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20710 *4, optional writeback(W)
20711 (doubleword load/store)
20713 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20714 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20715 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20716 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20717 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20719 Uppercase letters indicate bits that are already encoded at
20720 this point. Lowercase letters are our problem. For the
20721 second block of instructions, the secondary opcode nybble
20722 (bits 8..11) is present, and bit 23 is zero, even if this is
20723 a PC-relative operation. */
20724 newval = md_chars_to_number (buf, THUMB_SIZE);
20726 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
20728 if ((newval & 0xf0000000) == 0xe0000000)
20730 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20732 newval |= (1 << 23);
20735 if (value % 4 != 0)
20737 as_bad_where (fixP->fx_file, fixP->fx_line,
20738 _("offset not a multiple of 4"));
20744 as_bad_where (fixP->fx_file, fixP->fx_line,
20745 _("offset out of range"));
20750 else if ((newval & 0x000f0000) == 0x000f0000)
20752 /* PC-relative, 12-bit offset. */
20754 newval |= (1 << 23);
20759 as_bad_where (fixP->fx_file, fixP->fx_line,
20760 _("offset out of range"));
20765 else if ((newval & 0x00000100) == 0x00000100)
20767 /* Writeback: 8-bit, +/- offset. */
20769 newval |= (1 << 9);
20774 as_bad_where (fixP->fx_file, fixP->fx_line,
20775 _("offset out of range"));
20780 else if ((newval & 0x00000f00) == 0x00000e00)
20782 /* T-instruction: positive 8-bit offset. */
20783 if (value < 0 || value > 0xff)
20785 as_bad_where (fixP->fx_file, fixP->fx_line,
20786 _("offset out of range"));
20794 /* Positive 12-bit or negative 8-bit offset. */
20798 newval |= (1 << 23);
20808 as_bad_where (fixP->fx_file, fixP->fx_line,
20809 _("offset out of range"));
20816 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
20817 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
20820 case BFD_RELOC_ARM_SHIFT_IMM:
20821 newval = md_chars_to_number (buf, INSN_SIZE);
20822 if (((unsigned long) value) > 32
20824 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
20826 as_bad_where (fixP->fx_file, fixP->fx_line,
20827 _("shift expression is too large"));
20832 /* Shifts of zero must be done as lsl. */
20834 else if (value == 32)
20836 newval &= 0xfffff07f;
20837 newval |= (value & 0x1f) << 7;
20838 md_number_to_chars (buf, newval, INSN_SIZE);
20841 case BFD_RELOC_ARM_T32_IMMEDIATE:
20842 case BFD_RELOC_ARM_T32_ADD_IMM:
20843 case BFD_RELOC_ARM_T32_IMM12:
20844 case BFD_RELOC_ARM_T32_ADD_PC12:
20845 /* We claim that this fixup has been processed here,
20846 even if in fact we generate an error because we do
20847 not have a reloc for it, so tc_gen_reloc will reject it. */
20851 && ! S_IS_DEFINED (fixP->fx_addsy))
20853 as_bad_where (fixP->fx_file, fixP->fx_line,
20854 _("undefined symbol %s used as an immediate value"),
20855 S_GET_NAME (fixP->fx_addsy));
20859 newval = md_chars_to_number (buf, THUMB_SIZE);
20861 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
20864 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
20865 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20867 newimm = encode_thumb32_immediate (value);
20868 if (newimm == (unsigned int) FAIL)
20869 newimm = thumb32_negate_data_op (&newval, value);
20871 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
20872 && newimm == (unsigned int) FAIL)
20874 /* Turn add/sum into addw/subw. */
20875 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
20876 newval = (newval & 0xfeffffff) | 0x02000000;
20877 /* No flat 12-bit imm encoding for addsw/subsw. */
20878 if ((newval & 0x00100000) == 0)
20880 /* 12 bit immediate for addw/subw. */
20884 newval ^= 0x00a00000;
20887 newimm = (unsigned int) FAIL;
20893 if (newimm == (unsigned int)FAIL)
20895 as_bad_where (fixP->fx_file, fixP->fx_line,
20896 _("invalid constant (%lx) after fixup"),
20897 (unsigned long) value);
20901 newval |= (newimm & 0x800) << 15;
20902 newval |= (newimm & 0x700) << 4;
20903 newval |= (newimm & 0x0ff);
20905 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
20906 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
20909 case BFD_RELOC_ARM_SMC:
20910 if (((unsigned long) value) > 0xffff)
20911 as_bad_where (fixP->fx_file, fixP->fx_line,
20912 _("invalid smc expression"));
20913 newval = md_chars_to_number (buf, INSN_SIZE);
20914 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20915 md_number_to_chars (buf, newval, INSN_SIZE);
20918 case BFD_RELOC_ARM_HVC:
20919 if (((unsigned long) value) > 0xffff)
20920 as_bad_where (fixP->fx_file, fixP->fx_line,
20921 _("invalid hvc expression"));
20922 newval = md_chars_to_number (buf, INSN_SIZE);
20923 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
20924 md_number_to_chars (buf, newval, INSN_SIZE);
20927 case BFD_RELOC_ARM_SWI:
20928 if (fixP->tc_fix_data != 0)
20930 if (((unsigned long) value) > 0xff)
20931 as_bad_where (fixP->fx_file, fixP->fx_line,
20932 _("invalid swi expression"));
20933 newval = md_chars_to_number (buf, THUMB_SIZE);
20935 md_number_to_chars (buf, newval, THUMB_SIZE);
20939 if (((unsigned long) value) > 0x00ffffff)
20940 as_bad_where (fixP->fx_file, fixP->fx_line,
20941 _("invalid swi expression"));
20942 newval = md_chars_to_number (buf, INSN_SIZE);
20944 md_number_to_chars (buf, newval, INSN_SIZE);
20948 case BFD_RELOC_ARM_MULTI:
20949 if (((unsigned long) value) > 0xffff)
20950 as_bad_where (fixP->fx_file, fixP->fx_line,
20951 _("invalid expression in load/store multiple"));
20952 newval = value | md_chars_to_number (buf, INSN_SIZE);
20953 md_number_to_chars (buf, newval, INSN_SIZE);
20957 case BFD_RELOC_ARM_PCREL_CALL:
20959 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20961 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20962 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20963 && THUMB_IS_FUNC (fixP->fx_addsy))
20964 /* Flip the bl to blx. This is a simple flip
20965 bit here because we generate PCREL_CALL for
20966 unconditional bls. */
20968 newval = md_chars_to_number (buf, INSN_SIZE);
20969 newval = newval | 0x10000000;
20970 md_number_to_chars (buf, newval, INSN_SIZE);
20976 goto arm_branch_common;
20978 case BFD_RELOC_ARM_PCREL_JUMP:
20979 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
20981 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
20982 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
20983 && THUMB_IS_FUNC (fixP->fx_addsy))
20985 /* This would map to a bl<cond>, b<cond>,
20986 b<always> to a Thumb function. We
20987 need to force a relocation for this particular
20989 newval = md_chars_to_number (buf, INSN_SIZE);
20993 case BFD_RELOC_ARM_PLT32:
20995 case BFD_RELOC_ARM_PCREL_BRANCH:
20997 goto arm_branch_common;
20999 case BFD_RELOC_ARM_PCREL_BLX:
21002 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21004 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21005 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21006 && ARM_IS_FUNC (fixP->fx_addsy))
21008 /* Flip the blx to a bl and warn. */
21009 const char *name = S_GET_NAME (fixP->fx_addsy);
21010 newval = 0xeb000000;
21011 as_warn_where (fixP->fx_file, fixP->fx_line,
21012 _("blx to '%s' an ARM ISA state function changed to bl"),
21014 md_number_to_chars (buf, newval, INSN_SIZE);
21020 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21021 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
21025 /* We are going to store value (shifted right by two) in the
21026 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21027 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21028 also be be clear. */
21030 as_bad_where (fixP->fx_file, fixP->fx_line,
21031 _("misaligned branch destination"));
21032 if ((value & (offsetT)0xfe000000) != (offsetT)0
21033 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
21034 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21036 if (fixP->fx_done || !seg->use_rela_p)
21038 newval = md_chars_to_number (buf, INSN_SIZE);
21039 newval |= (value >> 2) & 0x00ffffff;
21040 /* Set the H bit on BLX instructions. */
21044 newval |= 0x01000000;
21046 newval &= ~0x01000000;
21048 md_number_to_chars (buf, newval, INSN_SIZE);
21052 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
21053 /* CBZ can only branch forward. */
21055 /* Attempts to use CBZ to branch to the next instruction
21056 (which, strictly speaking, are prohibited) will be turned into
21059 FIXME: It may be better to remove the instruction completely and
21060 perform relaxation. */
21063 newval = md_chars_to_number (buf, THUMB_SIZE);
21064 newval = 0xbf00; /* NOP encoding T1 */
21065 md_number_to_chars (buf, newval, THUMB_SIZE);
21070 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21072 if (fixP->fx_done || !seg->use_rela_p)
21074 newval = md_chars_to_number (buf, THUMB_SIZE);
21075 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
21076 md_number_to_chars (buf, newval, THUMB_SIZE);
21081 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
21082 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
21083 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21085 if (fixP->fx_done || !seg->use_rela_p)
21087 newval = md_chars_to_number (buf, THUMB_SIZE);
21088 newval |= (value & 0x1ff) >> 1;
21089 md_number_to_chars (buf, newval, THUMB_SIZE);
21093 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
21094 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
21095 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21097 if (fixP->fx_done || !seg->use_rela_p)
21099 newval = md_chars_to_number (buf, THUMB_SIZE);
21100 newval |= (value & 0xfff) >> 1;
21101 md_number_to_chars (buf, newval, THUMB_SIZE);
21105 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21107 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21108 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21109 && ARM_IS_FUNC (fixP->fx_addsy)
21110 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21112 /* Force a relocation for a branch 20 bits wide. */
21115 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
21116 as_bad_where (fixP->fx_file, fixP->fx_line,
21117 _("conditional branch out of range"));
21119 if (fixP->fx_done || !seg->use_rela_p)
21122 addressT S, J1, J2, lo, hi;
21124 S = (value & 0x00100000) >> 20;
21125 J2 = (value & 0x00080000) >> 19;
21126 J1 = (value & 0x00040000) >> 18;
21127 hi = (value & 0x0003f000) >> 12;
21128 lo = (value & 0x00000ffe) >> 1;
21130 newval = md_chars_to_number (buf, THUMB_SIZE);
21131 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21132 newval |= (S << 10) | hi;
21133 newval2 |= (J1 << 13) | (J2 << 11) | lo;
21134 md_number_to_chars (buf, newval, THUMB_SIZE);
21135 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21139 case BFD_RELOC_THUMB_PCREL_BLX:
21140 /* If there is a blx from a thumb state function to
21141 another thumb function flip this to a bl and warn
21145 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21146 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21147 && THUMB_IS_FUNC (fixP->fx_addsy))
21149 const char *name = S_GET_NAME (fixP->fx_addsy);
21150 as_warn_where (fixP->fx_file, fixP->fx_line,
21151 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21153 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21154 newval = newval | 0x1000;
21155 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21156 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21161 goto thumb_bl_common;
21163 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21164 /* A bl from Thumb state ISA to an internal ARM state function
21165 is converted to a blx. */
21167 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21168 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21169 && ARM_IS_FUNC (fixP->fx_addsy)
21170 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21172 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21173 newval = newval & ~0x1000;
21174 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
21175 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
21182 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4 &&
21183 fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21184 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
21187 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
21188 /* For a BLX instruction, make sure that the relocation is rounded up
21189 to a word boundary. This follows the semantics of the instruction
21190 which specifies that bit 1 of the target address will come from bit
21191 1 of the base address. */
21192 value = (value + 1) & ~ 1;
21194 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
21196 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
21197 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21198 else if ((value & ~0x1ffffff)
21199 && ((value & ~0x1ffffff) != ~0x1ffffff))
21200 as_bad_where (fixP->fx_file, fixP->fx_line,
21201 _("Thumb2 branch out of range"));
21204 if (fixP->fx_done || !seg->use_rela_p)
21205 encode_thumb2_b_bl_offset (buf, value);
21209 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21210 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
21211 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
21213 if (fixP->fx_done || !seg->use_rela_p)
21214 encode_thumb2_b_bl_offset (buf, value);
21219 if (fixP->fx_done || !seg->use_rela_p)
21220 md_number_to_chars (buf, value, 1);
21224 if (fixP->fx_done || !seg->use_rela_p)
21225 md_number_to_chars (buf, value, 2);
21229 case BFD_RELOC_ARM_TLS_CALL:
21230 case BFD_RELOC_ARM_THM_TLS_CALL:
21231 case BFD_RELOC_ARM_TLS_DESCSEQ:
21232 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21233 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21236 case BFD_RELOC_ARM_TLS_GOTDESC:
21237 case BFD_RELOC_ARM_TLS_GD32:
21238 case BFD_RELOC_ARM_TLS_LE32:
21239 case BFD_RELOC_ARM_TLS_IE32:
21240 case BFD_RELOC_ARM_TLS_LDM32:
21241 case BFD_RELOC_ARM_TLS_LDO32:
21242 S_SET_THREAD_LOCAL (fixP->fx_addsy);
21245 case BFD_RELOC_ARM_GOT32:
21246 case BFD_RELOC_ARM_GOTOFF:
21247 if (fixP->fx_done || !seg->use_rela_p)
21248 md_number_to_chars (buf, 0, 4);
21251 case BFD_RELOC_ARM_GOT_PREL:
21252 if (fixP->fx_done || !seg->use_rela_p)
21253 md_number_to_chars (buf, value, 4);
21256 case BFD_RELOC_ARM_TARGET2:
21257 /* TARGET2 is not partial-inplace, so we need to write the
21258 addend here for REL targets, because it won't be written out
21259 during reloc processing later. */
21260 if (fixP->fx_done || !seg->use_rela_p)
21261 md_number_to_chars (buf, fixP->fx_offset, 4);
21265 case BFD_RELOC_RVA:
21267 case BFD_RELOC_ARM_TARGET1:
21268 case BFD_RELOC_ARM_ROSEGREL32:
21269 case BFD_RELOC_ARM_SBREL32:
21270 case BFD_RELOC_32_PCREL:
21272 case BFD_RELOC_32_SECREL:
21274 if (fixP->fx_done || !seg->use_rela_p)
21276 /* For WinCE we only do this for pcrel fixups. */
21277 if (fixP->fx_done || fixP->fx_pcrel)
21279 md_number_to_chars (buf, value, 4);
21283 case BFD_RELOC_ARM_PREL31:
21284 if (fixP->fx_done || !seg->use_rela_p)
21286 newval = md_chars_to_number (buf, 4) & 0x80000000;
21287 if ((value ^ (value >> 1)) & 0x40000000)
21289 as_bad_where (fixP->fx_file, fixP->fx_line,
21290 _("rel31 relocation overflow"));
21292 newval |= value & 0x7fffffff;
21293 md_number_to_chars (buf, newval, 4);
21298 case BFD_RELOC_ARM_CP_OFF_IMM:
21299 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21300 if (value < -1023 || value > 1023 || (value & 3))
21301 as_bad_where (fixP->fx_file, fixP->fx_line,
21302 _("co-processor offset out of range"));
21307 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21308 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21309 newval = md_chars_to_number (buf, INSN_SIZE);
21311 newval = get_thumb32_insn (buf);
21313 newval &= 0xffffff00;
21316 newval &= 0xff7fff00;
21317 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
21319 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
21320 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
21321 md_number_to_chars (buf, newval, INSN_SIZE);
21323 put_thumb32_insn (buf, newval);
21326 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
21327 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
21328 if (value < -255 || value > 255)
21329 as_bad_where (fixP->fx_file, fixP->fx_line,
21330 _("co-processor offset out of range"));
21332 goto cp_off_common;
21334 case BFD_RELOC_ARM_THUMB_OFFSET:
21335 newval = md_chars_to_number (buf, THUMB_SIZE);
21336 /* Exactly what ranges, and where the offset is inserted depends
21337 on the type of instruction, we can establish this from the
21339 switch (newval >> 12)
21341 case 4: /* PC load. */
21342 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21343 forced to zero for these loads; md_pcrel_from has already
21344 compensated for this. */
21346 as_bad_where (fixP->fx_file, fixP->fx_line,
21347 _("invalid offset, target not word aligned (0x%08lX)"),
21348 (((unsigned long) fixP->fx_frag->fr_address
21349 + (unsigned long) fixP->fx_where) & ~3)
21350 + (unsigned long) value);
21352 if (value & ~0x3fc)
21353 as_bad_where (fixP->fx_file, fixP->fx_line,
21354 _("invalid offset, value too big (0x%08lX)"),
21357 newval |= value >> 2;
21360 case 9: /* SP load/store. */
21361 if (value & ~0x3fc)
21362 as_bad_where (fixP->fx_file, fixP->fx_line,
21363 _("invalid offset, value too big (0x%08lX)"),
21365 newval |= value >> 2;
21368 case 6: /* Word load/store. */
21370 as_bad_where (fixP->fx_file, fixP->fx_line,
21371 _("invalid offset, value too big (0x%08lX)"),
21373 newval |= value << 4; /* 6 - 2. */
21376 case 7: /* Byte load/store. */
21378 as_bad_where (fixP->fx_file, fixP->fx_line,
21379 _("invalid offset, value too big (0x%08lX)"),
21381 newval |= value << 6;
21384 case 8: /* Halfword load/store. */
21386 as_bad_where (fixP->fx_file, fixP->fx_line,
21387 _("invalid offset, value too big (0x%08lX)"),
21389 newval |= value << 5; /* 6 - 1. */
21393 as_bad_where (fixP->fx_file, fixP->fx_line,
21394 "Unable to process relocation for thumb opcode: %lx",
21395 (unsigned long) newval);
21398 md_number_to_chars (buf, newval, THUMB_SIZE);
21401 case BFD_RELOC_ARM_THUMB_ADD:
21402 /* This is a complicated relocation, since we use it for all of
21403 the following immediate relocations:
21407 9bit ADD/SUB SP word-aligned
21408 10bit ADD PC/SP word-aligned
21410 The type of instruction being processed is encoded in the
21417 newval = md_chars_to_number (buf, THUMB_SIZE);
21419 int rd = (newval >> 4) & 0xf;
21420 int rs = newval & 0xf;
21421 int subtract = !!(newval & 0x8000);
21423 /* Check for HI regs, only very restricted cases allowed:
21424 Adjusting SP, and using PC or SP to get an address. */
21425 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
21426 || (rs > 7 && rs != REG_SP && rs != REG_PC))
21427 as_bad_where (fixP->fx_file, fixP->fx_line,
21428 _("invalid Hi register with immediate"));
21430 /* If value is negative, choose the opposite instruction. */
21434 subtract = !subtract;
21436 as_bad_where (fixP->fx_file, fixP->fx_line,
21437 _("immediate value out of range"));
21442 if (value & ~0x1fc)
21443 as_bad_where (fixP->fx_file, fixP->fx_line,
21444 _("invalid immediate for stack address calculation"));
21445 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
21446 newval |= value >> 2;
21448 else if (rs == REG_PC || rs == REG_SP)
21450 if (subtract || value & ~0x3fc)
21451 as_bad_where (fixP->fx_file, fixP->fx_line,
21452 _("invalid immediate for address calculation (value = 0x%08lX)"),
21453 (unsigned long) value);
21454 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
21456 newval |= value >> 2;
21461 as_bad_where (fixP->fx_file, fixP->fx_line,
21462 _("immediate value out of range"));
21463 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
21464 newval |= (rd << 8) | value;
21469 as_bad_where (fixP->fx_file, fixP->fx_line,
21470 _("immediate value out of range"));
21471 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
21472 newval |= rd | (rs << 3) | (value << 6);
21475 md_number_to_chars (buf, newval, THUMB_SIZE);
21478 case BFD_RELOC_ARM_THUMB_IMM:
21479 newval = md_chars_to_number (buf, THUMB_SIZE);
21480 if (value < 0 || value > 255)
21481 as_bad_where (fixP->fx_file, fixP->fx_line,
21482 _("invalid immediate: %ld is out of range"),
21485 md_number_to_chars (buf, newval, THUMB_SIZE);
21488 case BFD_RELOC_ARM_THUMB_SHIFT:
21489 /* 5bit shift value (0..32). LSL cannot take 32. */
21490 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
21491 temp = newval & 0xf800;
21492 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
21493 as_bad_where (fixP->fx_file, fixP->fx_line,
21494 _("invalid shift value: %ld"), (long) value);
21495 /* Shifts of zero must be encoded as LSL. */
21497 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
21498 /* Shifts of 32 are encoded as zero. */
21499 else if (value == 32)
21501 newval |= value << 6;
21502 md_number_to_chars (buf, newval, THUMB_SIZE);
21505 case BFD_RELOC_VTABLE_INHERIT:
21506 case BFD_RELOC_VTABLE_ENTRY:
21510 case BFD_RELOC_ARM_MOVW:
21511 case BFD_RELOC_ARM_MOVT:
21512 case BFD_RELOC_ARM_THUMB_MOVW:
21513 case BFD_RELOC_ARM_THUMB_MOVT:
21514 if (fixP->fx_done || !seg->use_rela_p)
21516 /* REL format relocations are limited to a 16-bit addend. */
21517 if (!fixP->fx_done)
21519 if (value < -0x8000 || value > 0x7fff)
21520 as_bad_where (fixP->fx_file, fixP->fx_line,
21521 _("offset out of range"));
21523 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
21524 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21529 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
21530 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
21532 newval = get_thumb32_insn (buf);
21533 newval &= 0xfbf08f00;
21534 newval |= (value & 0xf000) << 4;
21535 newval |= (value & 0x0800) << 15;
21536 newval |= (value & 0x0700) << 4;
21537 newval |= (value & 0x00ff);
21538 put_thumb32_insn (buf, newval);
21542 newval = md_chars_to_number (buf, 4);
21543 newval &= 0xfff0f000;
21544 newval |= value & 0x0fff;
21545 newval |= (value & 0xf000) << 4;
21546 md_number_to_chars (buf, newval, 4);
21551 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21552 case BFD_RELOC_ARM_ALU_PC_G0:
21553 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21554 case BFD_RELOC_ARM_ALU_PC_G1:
21555 case BFD_RELOC_ARM_ALU_PC_G2:
21556 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21557 case BFD_RELOC_ARM_ALU_SB_G0:
21558 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21559 case BFD_RELOC_ARM_ALU_SB_G1:
21560 case BFD_RELOC_ARM_ALU_SB_G2:
21561 gas_assert (!fixP->fx_done);
21562 if (!seg->use_rela_p)
21565 bfd_vma encoded_addend;
21566 bfd_vma addend_abs = abs (value);
21568 /* Check that the absolute value of the addend can be
21569 expressed as an 8-bit constant plus a rotation. */
21570 encoded_addend = encode_arm_immediate (addend_abs);
21571 if (encoded_addend == (unsigned int) FAIL)
21572 as_bad_where (fixP->fx_file, fixP->fx_line,
21573 _("the offset 0x%08lX is not representable"),
21574 (unsigned long) addend_abs);
21576 /* Extract the instruction. */
21577 insn = md_chars_to_number (buf, INSN_SIZE);
21579 /* If the addend is positive, use an ADD instruction.
21580 Otherwise use a SUB. Take care not to destroy the S bit. */
21581 insn &= 0xff1fffff;
21587 /* Place the encoded addend into the first 12 bits of the
21589 insn &= 0xfffff000;
21590 insn |= encoded_addend;
21592 /* Update the instruction. */
21593 md_number_to_chars (buf, insn, INSN_SIZE);
21597 case BFD_RELOC_ARM_LDR_PC_G0:
21598 case BFD_RELOC_ARM_LDR_PC_G1:
21599 case BFD_RELOC_ARM_LDR_PC_G2:
21600 case BFD_RELOC_ARM_LDR_SB_G0:
21601 case BFD_RELOC_ARM_LDR_SB_G1:
21602 case BFD_RELOC_ARM_LDR_SB_G2:
21603 gas_assert (!fixP->fx_done);
21604 if (!seg->use_rela_p)
21607 bfd_vma addend_abs = abs (value);
21609 /* Check that the absolute value of the addend can be
21610 encoded in 12 bits. */
21611 if (addend_abs >= 0x1000)
21612 as_bad_where (fixP->fx_file, fixP->fx_line,
21613 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21614 (unsigned long) addend_abs);
21616 /* Extract the instruction. */
21617 insn = md_chars_to_number (buf, INSN_SIZE);
21619 /* If the addend is negative, clear bit 23 of the instruction.
21620 Otherwise set it. */
21622 insn &= ~(1 << 23);
21626 /* Place the absolute value of the addend into the first 12 bits
21627 of the instruction. */
21628 insn &= 0xfffff000;
21629 insn |= addend_abs;
21631 /* Update the instruction. */
21632 md_number_to_chars (buf, insn, INSN_SIZE);
21636 case BFD_RELOC_ARM_LDRS_PC_G0:
21637 case BFD_RELOC_ARM_LDRS_PC_G1:
21638 case BFD_RELOC_ARM_LDRS_PC_G2:
21639 case BFD_RELOC_ARM_LDRS_SB_G0:
21640 case BFD_RELOC_ARM_LDRS_SB_G1:
21641 case BFD_RELOC_ARM_LDRS_SB_G2:
21642 gas_assert (!fixP->fx_done);
21643 if (!seg->use_rela_p)
21646 bfd_vma addend_abs = abs (value);
21648 /* Check that the absolute value of the addend can be
21649 encoded in 8 bits. */
21650 if (addend_abs >= 0x100)
21651 as_bad_where (fixP->fx_file, fixP->fx_line,
21652 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21653 (unsigned long) addend_abs);
21655 /* Extract the instruction. */
21656 insn = md_chars_to_number (buf, INSN_SIZE);
21658 /* If the addend is negative, clear bit 23 of the instruction.
21659 Otherwise set it. */
21661 insn &= ~(1 << 23);
21665 /* Place the first four bits of the absolute value of the addend
21666 into the first 4 bits of the instruction, and the remaining
21667 four into bits 8 .. 11. */
21668 insn &= 0xfffff0f0;
21669 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
21671 /* Update the instruction. */
21672 md_number_to_chars (buf, insn, INSN_SIZE);
21676 case BFD_RELOC_ARM_LDC_PC_G0:
21677 case BFD_RELOC_ARM_LDC_PC_G1:
21678 case BFD_RELOC_ARM_LDC_PC_G2:
21679 case BFD_RELOC_ARM_LDC_SB_G0:
21680 case BFD_RELOC_ARM_LDC_SB_G1:
21681 case BFD_RELOC_ARM_LDC_SB_G2:
21682 gas_assert (!fixP->fx_done);
21683 if (!seg->use_rela_p)
21686 bfd_vma addend_abs = abs (value);
21688 /* Check that the absolute value of the addend is a multiple of
21689 four and, when divided by four, fits in 8 bits. */
21690 if (addend_abs & 0x3)
21691 as_bad_where (fixP->fx_file, fixP->fx_line,
21692 _("bad offset 0x%08lX (must be word-aligned)"),
21693 (unsigned long) addend_abs);
21695 if ((addend_abs >> 2) > 0xff)
21696 as_bad_where (fixP->fx_file, fixP->fx_line,
21697 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21698 (unsigned long) addend_abs);
21700 /* Extract the instruction. */
21701 insn = md_chars_to_number (buf, INSN_SIZE);
21703 /* If the addend is negative, clear bit 23 of the instruction.
21704 Otherwise set it. */
21706 insn &= ~(1 << 23);
21710 /* Place the addend (divided by four) into the first eight
21711 bits of the instruction. */
21712 insn &= 0xfffffff0;
21713 insn |= addend_abs >> 2;
21715 /* Update the instruction. */
21716 md_number_to_chars (buf, insn, INSN_SIZE);
21720 case BFD_RELOC_ARM_V4BX:
21721 /* This will need to go in the object file. */
21725 case BFD_RELOC_UNUSED:
21727 as_bad_where (fixP->fx_file, fixP->fx_line,
21728 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
21732 /* Translate internal representation of relocation info to BFD target
21736 tc_gen_reloc (asection *section, fixS *fixp)
21739 bfd_reloc_code_real_type code;
21741 reloc = (arelent *) xmalloc (sizeof (arelent));
21743 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
21744 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
21745 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
21747 if (fixp->fx_pcrel)
21749 if (section->use_rela_p)
21750 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
21752 fixp->fx_offset = reloc->address;
21754 reloc->addend = fixp->fx_offset;
21756 switch (fixp->fx_r_type)
21759 if (fixp->fx_pcrel)
21761 code = BFD_RELOC_8_PCREL;
21766 if (fixp->fx_pcrel)
21768 code = BFD_RELOC_16_PCREL;
21773 if (fixp->fx_pcrel)
21775 code = BFD_RELOC_32_PCREL;
21779 case BFD_RELOC_ARM_MOVW:
21780 if (fixp->fx_pcrel)
21782 code = BFD_RELOC_ARM_MOVW_PCREL;
21786 case BFD_RELOC_ARM_MOVT:
21787 if (fixp->fx_pcrel)
21789 code = BFD_RELOC_ARM_MOVT_PCREL;
21793 case BFD_RELOC_ARM_THUMB_MOVW:
21794 if (fixp->fx_pcrel)
21796 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
21800 case BFD_RELOC_ARM_THUMB_MOVT:
21801 if (fixp->fx_pcrel)
21803 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
21807 case BFD_RELOC_NONE:
21808 case BFD_RELOC_ARM_PCREL_BRANCH:
21809 case BFD_RELOC_ARM_PCREL_BLX:
21810 case BFD_RELOC_RVA:
21811 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21812 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21813 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21814 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21815 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21816 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21817 case BFD_RELOC_VTABLE_ENTRY:
21818 case BFD_RELOC_VTABLE_INHERIT:
21820 case BFD_RELOC_32_SECREL:
21822 code = fixp->fx_r_type;
21825 case BFD_RELOC_THUMB_PCREL_BLX:
21827 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
21828 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
21831 code = BFD_RELOC_THUMB_PCREL_BLX;
21834 case BFD_RELOC_ARM_LITERAL:
21835 case BFD_RELOC_ARM_HWLITERAL:
21836 /* If this is called then the a literal has
21837 been referenced across a section boundary. */
21838 as_bad_where (fixp->fx_file, fixp->fx_line,
21839 _("literal referenced across section boundary"));
21843 case BFD_RELOC_ARM_TLS_CALL:
21844 case BFD_RELOC_ARM_THM_TLS_CALL:
21845 case BFD_RELOC_ARM_TLS_DESCSEQ:
21846 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
21847 case BFD_RELOC_ARM_GOT32:
21848 case BFD_RELOC_ARM_GOTOFF:
21849 case BFD_RELOC_ARM_GOT_PREL:
21850 case BFD_RELOC_ARM_PLT32:
21851 case BFD_RELOC_ARM_TARGET1:
21852 case BFD_RELOC_ARM_ROSEGREL32:
21853 case BFD_RELOC_ARM_SBREL32:
21854 case BFD_RELOC_ARM_PREL31:
21855 case BFD_RELOC_ARM_TARGET2:
21856 case BFD_RELOC_ARM_TLS_LE32:
21857 case BFD_RELOC_ARM_TLS_LDO32:
21858 case BFD_RELOC_ARM_PCREL_CALL:
21859 case BFD_RELOC_ARM_PCREL_JUMP:
21860 case BFD_RELOC_ARM_ALU_PC_G0_NC:
21861 case BFD_RELOC_ARM_ALU_PC_G0:
21862 case BFD_RELOC_ARM_ALU_PC_G1_NC:
21863 case BFD_RELOC_ARM_ALU_PC_G1:
21864 case BFD_RELOC_ARM_ALU_PC_G2:
21865 case BFD_RELOC_ARM_LDR_PC_G0:
21866 case BFD_RELOC_ARM_LDR_PC_G1:
21867 case BFD_RELOC_ARM_LDR_PC_G2:
21868 case BFD_RELOC_ARM_LDRS_PC_G0:
21869 case BFD_RELOC_ARM_LDRS_PC_G1:
21870 case BFD_RELOC_ARM_LDRS_PC_G2:
21871 case BFD_RELOC_ARM_LDC_PC_G0:
21872 case BFD_RELOC_ARM_LDC_PC_G1:
21873 case BFD_RELOC_ARM_LDC_PC_G2:
21874 case BFD_RELOC_ARM_ALU_SB_G0_NC:
21875 case BFD_RELOC_ARM_ALU_SB_G0:
21876 case BFD_RELOC_ARM_ALU_SB_G1_NC:
21877 case BFD_RELOC_ARM_ALU_SB_G1:
21878 case BFD_RELOC_ARM_ALU_SB_G2:
21879 case BFD_RELOC_ARM_LDR_SB_G0:
21880 case BFD_RELOC_ARM_LDR_SB_G1:
21881 case BFD_RELOC_ARM_LDR_SB_G2:
21882 case BFD_RELOC_ARM_LDRS_SB_G0:
21883 case BFD_RELOC_ARM_LDRS_SB_G1:
21884 case BFD_RELOC_ARM_LDRS_SB_G2:
21885 case BFD_RELOC_ARM_LDC_SB_G0:
21886 case BFD_RELOC_ARM_LDC_SB_G1:
21887 case BFD_RELOC_ARM_LDC_SB_G2:
21888 case BFD_RELOC_ARM_V4BX:
21889 code = fixp->fx_r_type;
21892 case BFD_RELOC_ARM_TLS_GOTDESC:
21893 case BFD_RELOC_ARM_TLS_GD32:
21894 case BFD_RELOC_ARM_TLS_IE32:
21895 case BFD_RELOC_ARM_TLS_LDM32:
21896 /* BFD will include the symbol's address in the addend.
21897 But we don't want that, so subtract it out again here. */
21898 if (!S_IS_COMMON (fixp->fx_addsy))
21899 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
21900 code = fixp->fx_r_type;
21904 case BFD_RELOC_ARM_IMMEDIATE:
21905 as_bad_where (fixp->fx_file, fixp->fx_line,
21906 _("internal relocation (type: IMMEDIATE) not fixed up"));
21909 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21910 as_bad_where (fixp->fx_file, fixp->fx_line,
21911 _("ADRL used for a symbol not defined in the same file"));
21914 case BFD_RELOC_ARM_OFFSET_IMM:
21915 if (section->use_rela_p)
21917 code = fixp->fx_r_type;
21921 if (fixp->fx_addsy != NULL
21922 && !S_IS_DEFINED (fixp->fx_addsy)
21923 && S_IS_LOCAL (fixp->fx_addsy))
21925 as_bad_where (fixp->fx_file, fixp->fx_line,
21926 _("undefined local label `%s'"),
21927 S_GET_NAME (fixp->fx_addsy));
21931 as_bad_where (fixp->fx_file, fixp->fx_line,
21932 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21939 switch (fixp->fx_r_type)
21941 case BFD_RELOC_NONE: type = "NONE"; break;
21942 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
21943 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
21944 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
21945 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
21946 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
21947 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
21948 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
21949 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
21950 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
21951 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
21952 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
21953 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
21954 default: type = _("<unknown>"); break;
21956 as_bad_where (fixp->fx_file, fixp->fx_line,
21957 _("cannot represent %s relocation in this object file format"),
21964 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
21966 && fixp->fx_addsy == GOT_symbol)
21968 code = BFD_RELOC_ARM_GOTPC;
21969 reloc->addend = fixp->fx_offset = reloc->address;
21973 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
21975 if (reloc->howto == NULL)
21977 as_bad_where (fixp->fx_file, fixp->fx_line,
21978 _("cannot represent %s relocation in this object file format"),
21979 bfd_get_reloc_code_name (code));
21983 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21984 vtable entry to be used in the relocation's section offset. */
21985 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
21986 reloc->address = fixp->fx_offset;
21991 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21994 cons_fix_new_arm (fragS * frag,
21999 bfd_reloc_code_real_type type;
22003 FIXME: @@ Should look at CPU word size. */
22007 type = BFD_RELOC_8;
22010 type = BFD_RELOC_16;
22014 type = BFD_RELOC_32;
22017 type = BFD_RELOC_64;
22022 if (exp->X_op == O_secrel)
22024 exp->X_op = O_symbol;
22025 type = BFD_RELOC_32_SECREL;
22029 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22032 #if defined (OBJ_COFF)
22034 arm_validate_fix (fixS * fixP)
22036 /* If the destination of the branch is a defined symbol which does not have
22037 the THUMB_FUNC attribute, then we must be calling a function which has
22038 the (interfacearm) attribute. We look for the Thumb entry point to that
22039 function and change the branch to refer to that function instead. */
22040 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
22041 && fixP->fx_addsy != NULL
22042 && S_IS_DEFINED (fixP->fx_addsy)
22043 && ! THUMB_IS_FUNC (fixP->fx_addsy))
22045 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
22052 arm_force_relocation (struct fix * fixp)
22054 #if defined (OBJ_COFF) && defined (TE_PE)
22055 if (fixp->fx_r_type == BFD_RELOC_RVA)
22059 /* In case we have a call or a branch to a function in ARM ISA mode from
22060 a thumb function or vice-versa force the relocation. These relocations
22061 are cleared off for some cores that might have blx and simple transformations
22065 switch (fixp->fx_r_type)
22067 case BFD_RELOC_ARM_PCREL_JUMP:
22068 case BFD_RELOC_ARM_PCREL_CALL:
22069 case BFD_RELOC_THUMB_PCREL_BLX:
22070 if (THUMB_IS_FUNC (fixp->fx_addsy))
22074 case BFD_RELOC_ARM_PCREL_BLX:
22075 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22076 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22077 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22078 if (ARM_IS_FUNC (fixp->fx_addsy))
22087 /* Resolve these relocations even if the symbol is extern or weak.
22088 Technically this is probably wrong due to symbol preemption.
22089 In practice these relocations do not have enough range to be useful
22090 at dynamic link time, and some code (e.g. in the Linux kernel)
22091 expects these references to be resolved. */
22092 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
22093 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
22094 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
22095 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
22096 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22097 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
22098 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
22099 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
22100 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22101 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
22102 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
22103 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
22104 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
22105 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
22108 /* Always leave these relocations for the linker. */
22109 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22110 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22111 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22114 /* Always generate relocations against function symbols. */
22115 if (fixp->fx_r_type == BFD_RELOC_32
22117 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
22120 return generic_force_reloc (fixp);
22123 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22124 /* Relocations against function names must be left unadjusted,
22125 so that the linker can use this information to generate interworking
22126 stubs. The MIPS version of this function
22127 also prevents relocations that are mips-16 specific, but I do not
22128 know why it does this.
22131 There is one other problem that ought to be addressed here, but
22132 which currently is not: Taking the address of a label (rather
22133 than a function) and then later jumping to that address. Such
22134 addresses also ought to have their bottom bit set (assuming that
22135 they reside in Thumb code), but at the moment they will not. */
22138 arm_fix_adjustable (fixS * fixP)
22140 if (fixP->fx_addsy == NULL)
22143 /* Preserve relocations against symbols with function type. */
22144 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
22147 if (THUMB_IS_FUNC (fixP->fx_addsy)
22148 && fixP->fx_subsy == NULL)
22151 /* We need the symbol name for the VTABLE entries. */
22152 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
22153 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22156 /* Don't allow symbols to be discarded on GOT related relocs. */
22157 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
22158 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
22159 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
22160 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
22161 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
22162 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
22163 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
22164 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
22165 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
22166 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
22167 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
22168 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
22169 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
22170 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
22173 /* Similarly for group relocations. */
22174 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
22175 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
22176 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
22179 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22180 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
22181 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22182 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
22183 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
22184 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22185 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
22186 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
22187 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
22192 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22197 elf32_arm_target_format (void)
22200 return (target_big_endian
22201 ? "elf32-bigarm-symbian"
22202 : "elf32-littlearm-symbian");
22203 #elif defined (TE_VXWORKS)
22204 return (target_big_endian
22205 ? "elf32-bigarm-vxworks"
22206 : "elf32-littlearm-vxworks");
22208 if (target_big_endian)
22209 return "elf32-bigarm";
22211 return "elf32-littlearm";
22216 armelf_frob_symbol (symbolS * symp,
22219 elf_frob_symbol (symp, puntp);
22223 /* MD interface: Finalization. */
22228 literal_pool * pool;
22230 /* Ensure that all the IT blocks are properly closed. */
22231 check_it_blocks_finished ();
22233 for (pool = list_of_pools; pool; pool = pool->next)
22235 /* Put it at the end of the relevant section. */
22236 subseg_set (pool->section, pool->sub_section);
22238 arm_elf_change_section ();
22245 /* Remove any excess mapping symbols generated for alignment frags in
22246 SEC. We may have created a mapping symbol before a zero byte
22247 alignment; remove it if there's a mapping symbol after the
22250 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
22251 void *dummy ATTRIBUTE_UNUSED)
22253 segment_info_type *seginfo = seg_info (sec);
22256 if (seginfo == NULL || seginfo->frchainP == NULL)
22259 for (fragp = seginfo->frchainP->frch_root;
22261 fragp = fragp->fr_next)
22263 symbolS *sym = fragp->tc_frag_data.last_map;
22264 fragS *next = fragp->fr_next;
22266 /* Variable-sized frags have been converted to fixed size by
22267 this point. But if this was variable-sized to start with,
22268 there will be a fixed-size frag after it. So don't handle
22270 if (sym == NULL || next == NULL)
22273 if (S_GET_VALUE (sym) < next->fr_address)
22274 /* Not at the end of this frag. */
22276 know (S_GET_VALUE (sym) == next->fr_address);
22280 if (next->tc_frag_data.first_map != NULL)
22282 /* Next frag starts with a mapping symbol. Discard this
22284 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22288 if (next->fr_next == NULL)
22290 /* This mapping symbol is at the end of the section. Discard
22292 know (next->fr_fix == 0 && next->fr_var == 0);
22293 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
22297 /* As long as we have empty frags without any mapping symbols,
22299 /* If the next frag is non-empty and does not start with a
22300 mapping symbol, then this mapping symbol is required. */
22301 if (next->fr_address != next->fr_next->fr_address)
22304 next = next->fr_next;
22306 while (next != NULL);
22311 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22315 arm_adjust_symtab (void)
22320 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22322 if (ARM_IS_THUMB (sym))
22324 if (THUMB_IS_FUNC (sym))
22326 /* Mark the symbol as a Thumb function. */
22327 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
22328 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
22329 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
22331 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
22332 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
22334 as_bad (_("%s: unexpected function type: %d"),
22335 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
22337 else switch (S_GET_STORAGE_CLASS (sym))
22340 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
22343 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
22346 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
22354 if (ARM_IS_INTERWORK (sym))
22355 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
22362 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
22364 if (ARM_IS_THUMB (sym))
22366 elf_symbol_type * elf_sym;
22368 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
22369 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
22371 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
22372 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
22374 /* If it's a .thumb_func, declare it as so,
22375 otherwise tag label as .code 16. */
22376 if (THUMB_IS_FUNC (sym))
22377 elf_sym->internal_elf_sym.st_target_internal
22378 = ST_BRANCH_TO_THUMB;
22379 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
22380 elf_sym->internal_elf_sym.st_info =
22381 ELF_ST_INFO (bind, STT_ARM_16BIT);
22386 /* Remove any overlapping mapping symbols generated by alignment frags. */
22387 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
22388 /* Now do generic ELF adjustments. */
22389 elf_adjust_symtab ();
22393 /* MD interface: Initialization. */
22396 set_constant_flonums (void)
22400 for (i = 0; i < NUM_FLOAT_VALS; i++)
22401 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
22405 /* Auto-select Thumb mode if it's the only available instruction set for the
22406 given architecture. */
22409 autoselect_thumb_from_cpu_variant (void)
22411 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
22412 opcode_select (16);
22421 if ( (arm_ops_hsh = hash_new ()) == NULL
22422 || (arm_cond_hsh = hash_new ()) == NULL
22423 || (arm_shift_hsh = hash_new ()) == NULL
22424 || (arm_psr_hsh = hash_new ()) == NULL
22425 || (arm_v7m_psr_hsh = hash_new ()) == NULL
22426 || (arm_reg_hsh = hash_new ()) == NULL
22427 || (arm_reloc_hsh = hash_new ()) == NULL
22428 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
22429 as_fatal (_("virtual memory exhausted"));
22431 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
22432 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
22433 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
22434 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
22435 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
22436 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
22437 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
22438 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
22439 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
22440 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
22441 (void *) (v7m_psrs + i));
22442 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
22443 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
22445 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
22447 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
22448 (void *) (barrier_opt_names + i));
22450 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
22452 struct reloc_entry * entry = reloc_names + i;
22454 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
22455 /* This makes encode_branch() use the EABI versions of this relocation. */
22456 entry->reloc = BFD_RELOC_UNUSED;
22458 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
22462 set_constant_flonums ();
22464 /* Set the cpu variant based on the command-line options. We prefer
22465 -mcpu= over -march= if both are set (as for GCC); and we prefer
22466 -mfpu= over any other way of setting the floating point unit.
22467 Use of legacy options with new options are faulted. */
22470 if (mcpu_cpu_opt || march_cpu_opt)
22471 as_bad (_("use of old and new-style options to set CPU type"));
22473 mcpu_cpu_opt = legacy_cpu;
22475 else if (!mcpu_cpu_opt)
22476 mcpu_cpu_opt = march_cpu_opt;
22481 as_bad (_("use of old and new-style options to set FPU type"));
22483 mfpu_opt = legacy_fpu;
22485 else if (!mfpu_opt)
22487 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22488 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22489 /* Some environments specify a default FPU. If they don't, infer it
22490 from the processor. */
22492 mfpu_opt = mcpu_fpu_opt;
22494 mfpu_opt = march_fpu_opt;
22496 mfpu_opt = &fpu_default;
22502 if (mcpu_cpu_opt != NULL)
22503 mfpu_opt = &fpu_default;
22504 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
22505 mfpu_opt = &fpu_arch_vfp_v2;
22507 mfpu_opt = &fpu_arch_fpa;
22513 mcpu_cpu_opt = &cpu_default;
22514 selected_cpu = cpu_default;
22518 selected_cpu = *mcpu_cpu_opt;
22520 mcpu_cpu_opt = &arm_arch_any;
22523 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
22525 autoselect_thumb_from_cpu_variant ();
22527 arm_arch_used = thumb_arch_used = arm_arch_none;
22529 #if defined OBJ_COFF || defined OBJ_ELF
22531 unsigned int flags = 0;
22533 #if defined OBJ_ELF
22534 flags = meabi_flags;
22536 switch (meabi_flags)
22538 case EF_ARM_EABI_UNKNOWN:
22540 /* Set the flags in the private structure. */
22541 if (uses_apcs_26) flags |= F_APCS26;
22542 if (support_interwork) flags |= F_INTERWORK;
22543 if (uses_apcs_float) flags |= F_APCS_FLOAT;
22544 if (pic_code) flags |= F_PIC;
22545 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
22546 flags |= F_SOFT_FLOAT;
22548 switch (mfloat_abi_opt)
22550 case ARM_FLOAT_ABI_SOFT:
22551 case ARM_FLOAT_ABI_SOFTFP:
22552 flags |= F_SOFT_FLOAT;
22555 case ARM_FLOAT_ABI_HARD:
22556 if (flags & F_SOFT_FLOAT)
22557 as_bad (_("hard-float conflicts with specified fpu"));
22561 /* Using pure-endian doubles (even if soft-float). */
22562 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
22563 flags |= F_VFP_FLOAT;
22565 #if defined OBJ_ELF
22566 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
22567 flags |= EF_ARM_MAVERICK_FLOAT;
22570 case EF_ARM_EABI_VER4:
22571 case EF_ARM_EABI_VER5:
22572 /* No additional flags to set. */
22579 bfd_set_private_flags (stdoutput, flags);
22581 /* We have run out flags in the COFF header to encode the
22582 status of ATPCS support, so instead we create a dummy,
22583 empty, debug section called .arm.atpcs. */
22588 sec = bfd_make_section (stdoutput, ".arm.atpcs");
22592 bfd_set_section_flags
22593 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
22594 bfd_set_section_size (stdoutput, sec, 0);
22595 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
22601 /* Record the CPU type as well. */
22602 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
22603 mach = bfd_mach_arm_iWMMXt2;
22604 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
22605 mach = bfd_mach_arm_iWMMXt;
22606 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
22607 mach = bfd_mach_arm_XScale;
22608 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
22609 mach = bfd_mach_arm_ep9312;
22610 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
22611 mach = bfd_mach_arm_5TE;
22612 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
22614 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22615 mach = bfd_mach_arm_5T;
22617 mach = bfd_mach_arm_5;
22619 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
22621 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
22622 mach = bfd_mach_arm_4T;
22624 mach = bfd_mach_arm_4;
22626 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
22627 mach = bfd_mach_arm_3M;
22628 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
22629 mach = bfd_mach_arm_3;
22630 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
22631 mach = bfd_mach_arm_2a;
22632 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
22633 mach = bfd_mach_arm_2;
22635 mach = bfd_mach_arm_unknown;
22637 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
22640 /* Command line processing. */
22643 Invocation line includes a switch not recognized by the base assembler.
22644 See if it's a processor-specific option.
22646 This routine is somewhat complicated by the need for backwards
22647 compatibility (since older releases of gcc can't be changed).
22648 The new options try to make the interface as compatible as
22651 New options (supported) are:
22653 -mcpu=<cpu name> Assemble for selected processor
22654 -march=<architecture name> Assemble for selected architecture
22655 -mfpu=<fpu architecture> Assemble for selected FPU.
22656 -EB/-mbig-endian Big-endian
22657 -EL/-mlittle-endian Little-endian
22658 -k Generate PIC code
22659 -mthumb Start in Thumb mode
22660 -mthumb-interwork Code supports ARM/Thumb interworking
22662 -m[no-]warn-deprecated Warn about deprecated features
22664 For now we will also provide support for:
22666 -mapcs-32 32-bit Program counter
22667 -mapcs-26 26-bit Program counter
22668 -macps-float Floats passed in FP registers
22669 -mapcs-reentrant Reentrant code
22671 (sometime these will probably be replaced with -mapcs=<list of options>
22672 and -matpcs=<list of options>)
22674 The remaining options are only supported for back-wards compatibility.
22675 Cpu variants, the arm part is optional:
22676 -m[arm]1 Currently not supported.
22677 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22678 -m[arm]3 Arm 3 processor
22679 -m[arm]6[xx], Arm 6 processors
22680 -m[arm]7[xx][t][[d]m] Arm 7 processors
22681 -m[arm]8[10] Arm 8 processors
22682 -m[arm]9[20][tdmi] Arm 9 processors
22683 -mstrongarm[110[0]] StrongARM processors
22684 -mxscale XScale processors
22685 -m[arm]v[2345[t[e]]] Arm architectures
22686 -mall All (except the ARM1)
22688 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22689 -mfpe-old (No float load/store multiples)
22690 -mvfpxd VFP Single precision
22692 -mno-fpu Disable all floating point instructions
22694 The following CPU names are recognized:
22695 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22696 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22697 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22698 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22699 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22700 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22701 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22705 const char * md_shortopts = "m:k";
22707 #ifdef ARM_BI_ENDIAN
22708 #define OPTION_EB (OPTION_MD_BASE + 0)
22709 #define OPTION_EL (OPTION_MD_BASE + 1)
22711 #if TARGET_BYTES_BIG_ENDIAN
22712 #define OPTION_EB (OPTION_MD_BASE + 0)
22714 #define OPTION_EL (OPTION_MD_BASE + 1)
22717 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22719 struct option md_longopts[] =
22722 {"EB", no_argument, NULL, OPTION_EB},
22725 {"EL", no_argument, NULL, OPTION_EL},
22727 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
22728 {NULL, no_argument, NULL, 0}
22731 size_t md_longopts_size = sizeof (md_longopts);
22733 struct arm_option_table
22735 char *option; /* Option name to match. */
22736 char *help; /* Help information. */
22737 int *var; /* Variable to change. */
22738 int value; /* What to change it to. */
22739 char *deprecated; /* If non-null, print this message. */
22742 struct arm_option_table arm_opts[] =
22744 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
22745 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
22746 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22747 &support_interwork, 1, NULL},
22748 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
22749 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
22750 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
22752 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
22753 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
22754 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
22755 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
22758 /* These are recognized by the assembler, but have no affect on code. */
22759 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
22760 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
22762 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
22763 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22764 &warn_on_deprecated, 0, NULL},
22765 {NULL, NULL, NULL, 0, NULL}
22768 struct arm_legacy_option_table
22770 char *option; /* Option name to match. */
22771 const arm_feature_set **var; /* Variable to change. */
22772 const arm_feature_set value; /* What to change it to. */
22773 char *deprecated; /* If non-null, print this message. */
22776 const struct arm_legacy_option_table arm_legacy_opts[] =
22778 /* DON'T add any new processors to this list -- we want the whole list
22779 to go away... Add them to the processors table instead. */
22780 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22781 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
22782 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22783 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
22784 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22785 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
22786 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22787 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
22788 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22789 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
22790 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22791 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
22792 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22793 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
22794 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22795 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
22796 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22797 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
22798 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22799 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
22800 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22801 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
22802 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22803 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
22804 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22805 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
22806 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22807 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
22808 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22809 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
22810 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22811 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
22812 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22813 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
22814 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22815 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
22816 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22817 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
22818 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22819 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
22820 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22821 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
22822 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22823 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
22824 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22825 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
22826 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22827 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22828 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22829 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
22830 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22831 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
22832 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22833 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
22834 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22835 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
22836 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22837 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
22838 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22839 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
22840 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22841 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
22842 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22843 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
22844 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22845 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
22846 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22847 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
22848 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
22849 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
22850 N_("use -mcpu=strongarm110")},
22851 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
22852 N_("use -mcpu=strongarm1100")},
22853 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
22854 N_("use -mcpu=strongarm1110")},
22855 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
22856 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
22857 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
22859 /* Architecture variants -- don't add any more to this list either. */
22860 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22861 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
22862 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22863 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
22864 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22865 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
22866 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22867 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
22868 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22869 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
22870 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22871 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
22872 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22873 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
22874 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22875 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
22876 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22877 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
22879 /* Floating point variants -- don't add any more to this list either. */
22880 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
22881 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
22882 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
22883 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
22884 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22886 {NULL, NULL, ARM_ARCH_NONE, NULL}
22889 struct arm_cpu_option_table
22893 const arm_feature_set value;
22894 /* For some CPUs we assume an FPU unless the user explicitly sets
22896 const arm_feature_set default_fpu;
22897 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22899 const char *canonical_name;
22902 /* This list should, at a minimum, contain all the cpu names
22903 recognized by GCC. */
22904 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
22905 static const struct arm_cpu_option_table arm_cpus[] =
22907 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
22908 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
22909 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
22910 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
22911 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
22912 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22913 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22914 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22915 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22916 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22917 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22918 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22919 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22920 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22921 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22922 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
22923 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22924 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22925 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22926 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22927 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22928 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22929 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22930 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22931 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22932 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22933 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22934 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
22935 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22936 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22937 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22938 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22939 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22940 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22941 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22942 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22943 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22944 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22945 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22946 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
22947 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22948 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22949 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22950 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
22951 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22952 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
22953 /* For V5 or later processors we default to using VFP; but the user
22954 should really set the FPU type explicitly. */
22955 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22956 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22957 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
22958 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
22959 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
22960 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22961 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
22962 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22963 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
22964 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
22965 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22966 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22967 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22968 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22969 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22970 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
22971 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
22972 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22973 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22974 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
22976 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
22977 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22978 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22979 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22980 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22981 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
22982 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
22983 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
22984 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
22986 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
22987 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
22988 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
22989 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
22990 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
22991 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
22992 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
22993 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
22994 FPU_NONE, "Cortex-A5"),
22995 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
22996 FPU_ARCH_NEON_VFP_V4,
22998 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
22999 ARM_FEATURE (0, FPU_VFP_V3
23000 | FPU_NEON_EXT_V1),
23002 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23003 ARM_FEATURE (0, FPU_VFP_V3
23004 | FPU_NEON_EXT_V1),
23006 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23007 FPU_ARCH_NEON_VFP_V4,
23009 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23010 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23012 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23013 FPU_NONE, "Cortex-R5"),
23014 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23015 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23016 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23017 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
23018 /* ??? XSCALE is really an architecture. */
23019 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23020 /* ??? iwmmxt is not a processor. */
23021 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
23022 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
23023 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
23025 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
23028 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
23032 struct arm_arch_option_table
23036 const arm_feature_set value;
23037 const arm_feature_set default_fpu;
23040 /* This list should, at a minimum, contain all the architecture names
23041 recognized by GCC. */
23042 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
23043 static const struct arm_arch_option_table arm_archs[] =
23045 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
23046 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
23047 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
23048 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
23049 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
23050 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
23051 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
23052 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
23053 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
23054 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
23055 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
23056 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
23057 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
23058 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
23059 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
23060 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
23061 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
23062 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
23063 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
23064 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
23065 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
23066 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
23067 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
23068 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
23069 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
23070 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
23071 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
23072 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
23073 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
23074 /* The official spelling of the ARMv7 profile variants is the dashed form.
23075 Accept the non-dashed form for compatibility with old toolchains. */
23076 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23077 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23078 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23079 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
23080 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
23081 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
23082 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
23083 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
23084 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
23085 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
23086 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23088 #undef ARM_ARCH_OPT
23090 /* ISA extensions in the co-processor and main instruction set space. */
23091 struct arm_option_extension_value_table
23095 const arm_feature_set value;
23096 const arm_feature_set allowed_archs;
23099 /* The following table must be in alphabetical order with a NULL last entry.
23101 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
23102 static const struct arm_option_extension_value_table arm_extensions[] =
23104 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
23105 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23106 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
23107 ARM_EXT_OPT ("iwmmxt2",
23108 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
23109 ARM_EXT_OPT ("maverick",
23110 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
23111 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
23112 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
23113 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
23114 ARM_FEATURE (ARM_EXT_V6M, 0)),
23115 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
23116 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
23117 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
23119 ARM_FEATURE (ARM_EXT_V7A, 0)),
23120 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
23121 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
23125 /* ISA floating-point and Advanced SIMD extensions. */
23126 struct arm_option_fpu_value_table
23129 const arm_feature_set value;
23132 /* This list should, at a minimum, contain all the fpu names
23133 recognized by GCC. */
23134 static const struct arm_option_fpu_value_table arm_fpus[] =
23136 {"softfpa", FPU_NONE},
23137 {"fpe", FPU_ARCH_FPE},
23138 {"fpe2", FPU_ARCH_FPE},
23139 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
23140 {"fpa", FPU_ARCH_FPA},
23141 {"fpa10", FPU_ARCH_FPA},
23142 {"fpa11", FPU_ARCH_FPA},
23143 {"arm7500fe", FPU_ARCH_FPA},
23144 {"softvfp", FPU_ARCH_VFP},
23145 {"softvfp+vfp", FPU_ARCH_VFP_V2},
23146 {"vfp", FPU_ARCH_VFP_V2},
23147 {"vfp9", FPU_ARCH_VFP_V2},
23148 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
23149 {"vfp10", FPU_ARCH_VFP_V2},
23150 {"vfp10-r0", FPU_ARCH_VFP_V1},
23151 {"vfpxd", FPU_ARCH_VFP_V1xD},
23152 {"vfpv2", FPU_ARCH_VFP_V2},
23153 {"vfpv3", FPU_ARCH_VFP_V3},
23154 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
23155 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
23156 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
23157 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
23158 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
23159 {"arm1020t", FPU_ARCH_VFP_V1},
23160 {"arm1020e", FPU_ARCH_VFP_V2},
23161 {"arm1136jfs", FPU_ARCH_VFP_V2},
23162 {"arm1136jf-s", FPU_ARCH_VFP_V2},
23163 {"maverick", FPU_ARCH_MAVERICK},
23164 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
23165 {"neon-fp16", FPU_ARCH_NEON_FP16},
23166 {"vfpv4", FPU_ARCH_VFP_V4},
23167 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
23168 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
23169 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
23170 {NULL, ARM_ARCH_NONE}
23173 struct arm_option_value_table
23179 static const struct arm_option_value_table arm_float_abis[] =
23181 {"hard", ARM_FLOAT_ABI_HARD},
23182 {"softfp", ARM_FLOAT_ABI_SOFTFP},
23183 {"soft", ARM_FLOAT_ABI_SOFT},
23188 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23189 static const struct arm_option_value_table arm_eabis[] =
23191 {"gnu", EF_ARM_EABI_UNKNOWN},
23192 {"4", EF_ARM_EABI_VER4},
23193 {"5", EF_ARM_EABI_VER5},
23198 struct arm_long_option_table
23200 char * option; /* Substring to match. */
23201 char * help; /* Help information. */
23202 int (* func) (char * subopt); /* Function to decode sub-option. */
23203 char * deprecated; /* If non-null, print this message. */
23207 arm_parse_extension (char *str, const arm_feature_set **opt_p)
23209 arm_feature_set *ext_set = (arm_feature_set *)
23210 xmalloc (sizeof (arm_feature_set));
23212 /* We insist on extensions being specified in alphabetical order, and with
23213 extensions being added before being removed. We achieve this by having
23214 the global ARM_EXTENSIONS table in alphabetical order, and using the
23215 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23216 or removing it (0) and only allowing it to change in the order
23218 const struct arm_option_extension_value_table * opt = NULL;
23219 int adding_value = -1;
23221 /* Copy the feature set, so that we can modify it. */
23222 *ext_set = **opt_p;
23225 while (str != NULL && *str != 0)
23232 as_bad (_("invalid architectural extension"));
23237 ext = strchr (str, '+');
23242 len = strlen (str);
23244 if (len >= 2 && strncmp (str, "no", 2) == 0)
23246 if (adding_value != 0)
23249 opt = arm_extensions;
23257 if (adding_value == -1)
23260 opt = arm_extensions;
23262 else if (adding_value != 1)
23264 as_bad (_("must specify extensions to add before specifying "
23265 "those to remove"));
23272 as_bad (_("missing architectural extension"));
23276 gas_assert (adding_value != -1);
23277 gas_assert (opt != NULL);
23279 /* Scan over the options table trying to find an exact match. */
23280 for (; opt->name != NULL; opt++)
23281 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23283 /* Check we can apply the extension to this architecture. */
23284 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
23286 as_bad (_("extension does not apply to the base architecture"));
23290 /* Add or remove the extension. */
23292 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
23294 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
23299 if (opt->name == NULL)
23301 /* Did we fail to find an extension because it wasn't specified in
23302 alphabetical order, or because it does not exist? */
23304 for (opt = arm_extensions; opt->name != NULL; opt++)
23305 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23308 if (opt->name == NULL)
23309 as_bad (_("unknown architectural extension `%s'"), str);
23311 as_bad (_("architectural extensions must be specified in "
23312 "alphabetical order"));
23318 /* We should skip the extension we've just matched the next time
23330 arm_parse_cpu (char *str)
23332 const struct arm_cpu_option_table *opt;
23333 char *ext = strchr (str, '+');
23339 len = strlen (str);
23343 as_bad (_("missing cpu name `%s'"), str);
23347 for (opt = arm_cpus; opt->name != NULL; opt++)
23348 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23350 mcpu_cpu_opt = &opt->value;
23351 mcpu_fpu_opt = &opt->default_fpu;
23352 if (opt->canonical_name)
23353 strcpy (selected_cpu_name, opt->canonical_name);
23358 for (i = 0; i < len; i++)
23359 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23360 selected_cpu_name[i] = 0;
23364 return arm_parse_extension (ext, &mcpu_cpu_opt);
23369 as_bad (_("unknown cpu `%s'"), str);
23374 arm_parse_arch (char *str)
23376 const struct arm_arch_option_table *opt;
23377 char *ext = strchr (str, '+');
23383 len = strlen (str);
23387 as_bad (_("missing architecture name `%s'"), str);
23391 for (opt = arm_archs; opt->name != NULL; opt++)
23392 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
23394 march_cpu_opt = &opt->value;
23395 march_fpu_opt = &opt->default_fpu;
23396 strcpy (selected_cpu_name, opt->name);
23399 return arm_parse_extension (ext, &march_cpu_opt);
23404 as_bad (_("unknown architecture `%s'\n"), str);
23409 arm_parse_fpu (char * str)
23411 const struct arm_option_fpu_value_table * opt;
23413 for (opt = arm_fpus; opt->name != NULL; opt++)
23414 if (streq (opt->name, str))
23416 mfpu_opt = &opt->value;
23420 as_bad (_("unknown floating point format `%s'\n"), str);
23425 arm_parse_float_abi (char * str)
23427 const struct arm_option_value_table * opt;
23429 for (opt = arm_float_abis; opt->name != NULL; opt++)
23430 if (streq (opt->name, str))
23432 mfloat_abi_opt = opt->value;
23436 as_bad (_("unknown floating point abi `%s'\n"), str);
23442 arm_parse_eabi (char * str)
23444 const struct arm_option_value_table *opt;
23446 for (opt = arm_eabis; opt->name != NULL; opt++)
23447 if (streq (opt->name, str))
23449 meabi_flags = opt->value;
23452 as_bad (_("unknown EABI `%s'\n"), str);
23458 arm_parse_it_mode (char * str)
23460 bfd_boolean ret = TRUE;
23462 if (streq ("arm", str))
23463 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
23464 else if (streq ("thumb", str))
23465 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
23466 else if (streq ("always", str))
23467 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
23468 else if (streq ("never", str))
23469 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
23472 as_bad (_("unknown implicit IT mode `%s', should be "\
23473 "arm, thumb, always, or never."), str);
23480 struct arm_long_option_table arm_long_opts[] =
23482 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23483 arm_parse_cpu, NULL},
23484 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23485 arm_parse_arch, NULL},
23486 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23487 arm_parse_fpu, NULL},
23488 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23489 arm_parse_float_abi, NULL},
23491 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23492 arm_parse_eabi, NULL},
23494 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23495 arm_parse_it_mode, NULL},
23496 {NULL, NULL, 0, NULL}
23500 md_parse_option (int c, char * arg)
23502 struct arm_option_table *opt;
23503 const struct arm_legacy_option_table *fopt;
23504 struct arm_long_option_table *lopt;
23510 target_big_endian = 1;
23516 target_big_endian = 0;
23520 case OPTION_FIX_V4BX:
23525 /* Listing option. Just ignore these, we don't support additional
23530 for (opt = arm_opts; opt->option != NULL; opt++)
23532 if (c == opt->option[0]
23533 && ((arg == NULL && opt->option[1] == 0)
23534 || streq (arg, opt->option + 1)))
23536 /* If the option is deprecated, tell the user. */
23537 if (warn_on_deprecated && opt->deprecated != NULL)
23538 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23539 arg ? arg : "", _(opt->deprecated));
23541 if (opt->var != NULL)
23542 *opt->var = opt->value;
23548 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
23550 if (c == fopt->option[0]
23551 && ((arg == NULL && fopt->option[1] == 0)
23552 || streq (arg, fopt->option + 1)))
23554 /* If the option is deprecated, tell the user. */
23555 if (warn_on_deprecated && fopt->deprecated != NULL)
23556 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
23557 arg ? arg : "", _(fopt->deprecated));
23559 if (fopt->var != NULL)
23560 *fopt->var = &fopt->value;
23566 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23568 /* These options are expected to have an argument. */
23569 if (c == lopt->option[0]
23571 && strncmp (arg, lopt->option + 1,
23572 strlen (lopt->option + 1)) == 0)
23574 /* If the option is deprecated, tell the user. */
23575 if (warn_on_deprecated && lopt->deprecated != NULL)
23576 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
23577 _(lopt->deprecated));
23579 /* Call the sup-option parser. */
23580 return lopt->func (arg + strlen (lopt->option) - 1);
23591 md_show_usage (FILE * fp)
23593 struct arm_option_table *opt;
23594 struct arm_long_option_table *lopt;
23596 fprintf (fp, _(" ARM-specific assembler options:\n"));
23598 for (opt = arm_opts; opt->option != NULL; opt++)
23599 if (opt->help != NULL)
23600 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
23602 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
23603 if (lopt->help != NULL)
23604 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
23608 -EB assemble code for a big-endian cpu\n"));
23613 -EL assemble code for a little-endian cpu\n"));
23617 --fix-v4bx Allow BX in ARMv4 code\n"));
23625 arm_feature_set flags;
23626 } cpu_arch_ver_table;
23628 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23629 least features first. */
23630 static const cpu_arch_ver_table cpu_arch_ver[] =
23636 {4, ARM_ARCH_V5TE},
23637 {5, ARM_ARCH_V5TEJ},
23641 {11, ARM_ARCH_V6M},
23642 {12, ARM_ARCH_V6SM},
23643 {8, ARM_ARCH_V6T2},
23644 {10, ARM_ARCH_V7A},
23645 {10, ARM_ARCH_V7R},
23646 {10, ARM_ARCH_V7M},
23650 /* Set an attribute if it has not already been set by the user. */
23652 aeabi_set_attribute_int (int tag, int value)
23655 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23656 || !attributes_set_explicitly[tag])
23657 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
23661 aeabi_set_attribute_string (int tag, const char *value)
23664 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
23665 || !attributes_set_explicitly[tag])
23666 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
23669 /* Set the public EABI object attributes. */
23671 aeabi_set_public_attributes (void)
23675 arm_feature_set flags;
23676 arm_feature_set tmp;
23677 const cpu_arch_ver_table *p;
23679 /* Choose the architecture based on the capabilities of the requested cpu
23680 (if any) and/or the instructions actually used. */
23681 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
23682 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
23683 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
23685 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
23686 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
23688 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
23689 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
23691 /* Allow the user to override the reported architecture. */
23694 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
23695 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
23698 /* We need to make sure that the attributes do not identify us as v6S-M
23699 when the only v6S-M feature in use is the Operating System Extensions. */
23700 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
23701 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
23702 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
23706 for (p = cpu_arch_ver; p->val; p++)
23708 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
23711 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
23715 /* The table lookup above finds the last architecture to contribute
23716 a new feature. Unfortunately, Tag13 is a subset of the union of
23717 v6T2 and v7-M, so it is never seen as contributing a new feature.
23718 We can not search for the last entry which is entirely used,
23719 because if no CPU is specified we build up only those flags
23720 actually used. Perhaps we should separate out the specified
23721 and implicit cases. Avoid taking this path for -march=all by
23722 checking for contradictory v7-A / v7-M features. */
23724 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
23725 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
23726 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
23729 /* Tag_CPU_name. */
23730 if (selected_cpu_name[0])
23734 q = selected_cpu_name;
23735 if (strncmp (q, "armv", 4) == 0)
23740 for (i = 0; q[i]; i++)
23741 q[i] = TOUPPER (q[i]);
23743 aeabi_set_attribute_string (Tag_CPU_name, q);
23746 /* Tag_CPU_arch. */
23747 aeabi_set_attribute_int (Tag_CPU_arch, arch);
23749 /* Tag_CPU_arch_profile. */
23750 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
23751 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'A');
23752 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
23753 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'R');
23754 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
23755 aeabi_set_attribute_int (Tag_CPU_arch_profile, 'M');
23757 /* Tag_ARM_ISA_use. */
23758 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
23760 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
23762 /* Tag_THUMB_ISA_use. */
23763 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
23765 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
23766 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
23768 /* Tag_VFP_arch. */
23769 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
23770 aeabi_set_attribute_int (Tag_VFP_arch,
23771 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
23773 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
23774 aeabi_set_attribute_int (Tag_VFP_arch, 3);
23775 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
23776 aeabi_set_attribute_int (Tag_VFP_arch, 4);
23777 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
23778 aeabi_set_attribute_int (Tag_VFP_arch, 2);
23779 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
23780 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
23781 aeabi_set_attribute_int (Tag_VFP_arch, 1);
23783 /* Tag_ABI_HardFP_use. */
23784 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
23785 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
23786 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
23788 /* Tag_WMMX_arch. */
23789 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
23790 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
23791 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
23792 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
23794 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23795 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
23796 aeabi_set_attribute_int
23797 (Tag_Advanced_SIMD_arch, (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma)
23800 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23801 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16))
23802 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
23805 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv))
23806 aeabi_set_attribute_int (Tag_DIV_use, 2);
23807 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_div))
23808 aeabi_set_attribute_int (Tag_DIV_use, 0);
23810 aeabi_set_attribute_int (Tag_DIV_use, 1);
23812 /* Tag_MP_extension_use. */
23813 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
23814 aeabi_set_attribute_int (Tag_MPextension_use, 1);
23816 /* Tag Virtualization_use. */
23817 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
23819 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
23822 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
23825 /* Add the default contents for the .ARM.attributes section. */
23829 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
23832 aeabi_set_public_attributes ();
23834 #endif /* OBJ_ELF */
23837 /* Parse a .cpu directive. */
23840 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
23842 const struct arm_cpu_option_table *opt;
23846 name = input_line_pointer;
23847 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23848 input_line_pointer++;
23849 saved_char = *input_line_pointer;
23850 *input_line_pointer = 0;
23852 /* Skip the first "all" entry. */
23853 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
23854 if (streq (opt->name, name))
23856 mcpu_cpu_opt = &opt->value;
23857 selected_cpu = opt->value;
23858 if (opt->canonical_name)
23859 strcpy (selected_cpu_name, opt->canonical_name);
23863 for (i = 0; opt->name[i]; i++)
23864 selected_cpu_name[i] = TOUPPER (opt->name[i]);
23866 selected_cpu_name[i] = 0;
23868 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23869 *input_line_pointer = saved_char;
23870 demand_empty_rest_of_line ();
23873 as_bad (_("unknown cpu `%s'"), name);
23874 *input_line_pointer = saved_char;
23875 ignore_rest_of_line ();
23879 /* Parse a .arch directive. */
23882 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
23884 const struct arm_arch_option_table *opt;
23888 name = input_line_pointer;
23889 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23890 input_line_pointer++;
23891 saved_char = *input_line_pointer;
23892 *input_line_pointer = 0;
23894 /* Skip the first "all" entry. */
23895 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23896 if (streq (opt->name, name))
23898 mcpu_cpu_opt = &opt->value;
23899 selected_cpu = opt->value;
23900 strcpy (selected_cpu_name, opt->name);
23901 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23902 *input_line_pointer = saved_char;
23903 demand_empty_rest_of_line ();
23907 as_bad (_("unknown architecture `%s'\n"), name);
23908 *input_line_pointer = saved_char;
23909 ignore_rest_of_line ();
23913 /* Parse a .object_arch directive. */
23916 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
23918 const struct arm_arch_option_table *opt;
23922 name = input_line_pointer;
23923 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23924 input_line_pointer++;
23925 saved_char = *input_line_pointer;
23926 *input_line_pointer = 0;
23928 /* Skip the first "all" entry. */
23929 for (opt = arm_archs + 1; opt->name != NULL; opt++)
23930 if (streq (opt->name, name))
23932 object_arch = &opt->value;
23933 *input_line_pointer = saved_char;
23934 demand_empty_rest_of_line ();
23938 as_bad (_("unknown architecture `%s'\n"), name);
23939 *input_line_pointer = saved_char;
23940 ignore_rest_of_line ();
23943 /* Parse a .arch_extension directive. */
23946 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
23948 const struct arm_option_extension_value_table *opt;
23951 int adding_value = 1;
23953 name = input_line_pointer;
23954 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
23955 input_line_pointer++;
23956 saved_char = *input_line_pointer;
23957 *input_line_pointer = 0;
23959 if (strlen (name) >= 2
23960 && strncmp (name, "no", 2) == 0)
23966 for (opt = arm_extensions; opt->name != NULL; opt++)
23967 if (streq (opt->name, name))
23969 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
23971 as_bad (_("architectural extension `%s' is not allowed for the "
23972 "current base architecture"), name);
23977 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
23979 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
23981 mcpu_cpu_opt = &selected_cpu;
23982 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
23983 *input_line_pointer = saved_char;
23984 demand_empty_rest_of_line ();
23988 if (opt->name == NULL)
23989 as_bad (_("unknown architecture `%s'\n"), name);
23991 *input_line_pointer = saved_char;
23992 ignore_rest_of_line ();
23995 /* Parse a .fpu directive. */
23998 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
24000 const struct arm_option_fpu_value_table *opt;
24004 name = input_line_pointer;
24005 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24006 input_line_pointer++;
24007 saved_char = *input_line_pointer;
24008 *input_line_pointer = 0;
24010 for (opt = arm_fpus; opt->name != NULL; opt++)
24011 if (streq (opt->name, name))
24013 mfpu_opt = &opt->value;
24014 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24015 *input_line_pointer = saved_char;
24016 demand_empty_rest_of_line ();
24020 as_bad (_("unknown floating point format `%s'\n"), name);
24021 *input_line_pointer = saved_char;
24022 ignore_rest_of_line ();
24025 /* Copy symbol information. */
24028 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
24030 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
24034 /* Given a symbolic attribute NAME, return the proper integer value.
24035 Returns -1 if the attribute is not known. */
24038 arm_convert_symbolic_attribute (const char *name)
24040 static const struct
24045 attribute_table[] =
24047 /* When you modify this table you should
24048 also modify the list in doc/c-arm.texi. */
24049 #define T(tag) {#tag, tag}
24050 T (Tag_CPU_raw_name),
24053 T (Tag_CPU_arch_profile),
24054 T (Tag_ARM_ISA_use),
24055 T (Tag_THUMB_ISA_use),
24059 T (Tag_Advanced_SIMD_arch),
24060 T (Tag_PCS_config),
24061 T (Tag_ABI_PCS_R9_use),
24062 T (Tag_ABI_PCS_RW_data),
24063 T (Tag_ABI_PCS_RO_data),
24064 T (Tag_ABI_PCS_GOT_use),
24065 T (Tag_ABI_PCS_wchar_t),
24066 T (Tag_ABI_FP_rounding),
24067 T (Tag_ABI_FP_denormal),
24068 T (Tag_ABI_FP_exceptions),
24069 T (Tag_ABI_FP_user_exceptions),
24070 T (Tag_ABI_FP_number_model),
24071 T (Tag_ABI_align_needed),
24072 T (Tag_ABI_align8_needed),
24073 T (Tag_ABI_align_preserved),
24074 T (Tag_ABI_align8_preserved),
24075 T (Tag_ABI_enum_size),
24076 T (Tag_ABI_HardFP_use),
24077 T (Tag_ABI_VFP_args),
24078 T (Tag_ABI_WMMX_args),
24079 T (Tag_ABI_optimization_goals),
24080 T (Tag_ABI_FP_optimization_goals),
24081 T (Tag_compatibility),
24082 T (Tag_CPU_unaligned_access),
24083 T (Tag_FP_HP_extension),
24084 T (Tag_VFP_HP_extension),
24085 T (Tag_ABI_FP_16bit_format),
24086 T (Tag_MPextension_use),
24088 T (Tag_nodefaults),
24089 T (Tag_also_compatible_with),
24090 T (Tag_conformance),
24092 T (Tag_Virtualization_use),
24093 /* We deliberately do not include Tag_MPextension_use_legacy. */
24101 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
24102 if (streq (name, attribute_table[i].name))
24103 return attribute_table[i].tag;
24109 /* Apply sym value for relocations only in the case that
24110 they are for local symbols and you have the respective
24111 architectural feature for blx and simple switches. */
24113 arm_apply_sym_value (struct fix * fixP)
24116 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
24117 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
24119 switch (fixP->fx_r_type)
24121 case BFD_RELOC_ARM_PCREL_BLX:
24122 case BFD_RELOC_THUMB_PCREL_BRANCH23:
24123 if (ARM_IS_FUNC (fixP->fx_addsy))
24127 case BFD_RELOC_ARM_PCREL_CALL:
24128 case BFD_RELOC_THUMB_PCREL_BLX:
24129 if (THUMB_IS_FUNC (fixP->fx_addsy))
24140 #endif /* OBJ_ELF */