1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant;
127 static arm_feature_set arm_arch_used;
128 static arm_feature_set thumb_arch_used;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26 = FALSE;
132 static int atpcs = FALSE;
133 static int support_interwork = FALSE;
134 static int uses_apcs_float = FALSE;
135 static int pic_code = FALSE;
136 static int fix_v4bx = FALSE;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated = TRUE;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax = FALSE;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set *legacy_cpu = NULL;
147 static const arm_feature_set *legacy_fpu = NULL;
149 static const arm_feature_set *mcpu_cpu_opt = NULL;
150 static const arm_feature_set *mcpu_fpu_opt = NULL;
151 static const arm_feature_set *march_cpu_opt = NULL;
152 static const arm_feature_set *march_fpu_opt = NULL;
153 static const arm_feature_set *mfpu_opt = NULL;
154 static const arm_feature_set *object_arch = NULL;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default = FPU_DEFAULT;
158 static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159 static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
160 static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161 static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
162 static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163 static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164 static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165 static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
168 static const arm_feature_set cpu_default = CPU_DEFAULT;
171 static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
172 static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
173 static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
174 static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
175 static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
176 static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
177 static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
178 static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
179 static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
181 static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
182 static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
183 static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
184 static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
185 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
186 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
187 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
188 static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);
189 static const arm_feature_set arm_ext_v6_notm =
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
191 static const arm_feature_set arm_ext_v6_dsp =
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
193 static const arm_feature_set arm_ext_barrier =
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
195 static const arm_feature_set arm_ext_msr =
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
197 static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
198 static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
199 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
200 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
201 static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
202 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
203 static const arm_feature_set arm_ext_m =
204 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M);
205 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
206 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
207 static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
208 static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
209 static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
210 static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
212 static const arm_feature_set arm_arch_any = ARM_ANY;
213 static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1, -1);
214 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
215 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
216 static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
218 static const arm_feature_set arm_cext_iwmmxt2 =
219 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
220 static const arm_feature_set arm_cext_iwmmxt =
221 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
222 static const arm_feature_set arm_cext_xscale =
223 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
224 static const arm_feature_set arm_cext_maverick =
225 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
226 static const arm_feature_set fpu_fpa_ext_v1 =
227 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
228 static const arm_feature_set fpu_fpa_ext_v2 =
229 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
230 static const arm_feature_set fpu_vfp_ext_v1xd =
231 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
232 static const arm_feature_set fpu_vfp_ext_v1 =
233 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
234 static const arm_feature_set fpu_vfp_ext_v2 =
235 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
236 static const arm_feature_set fpu_vfp_ext_v3xd =
237 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
238 static const arm_feature_set fpu_vfp_ext_v3 =
239 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
240 static const arm_feature_set fpu_vfp_ext_d32 =
241 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
242 static const arm_feature_set fpu_neon_ext_v1 =
243 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
244 static const arm_feature_set fpu_vfp_v3_or_neon_ext =
245 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
246 static const arm_feature_set fpu_vfp_fp16 =
247 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
248 static const arm_feature_set fpu_neon_ext_fma =
249 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
250 static const arm_feature_set fpu_vfp_ext_fma =
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
252 static const arm_feature_set fpu_vfp_ext_armv8 =
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
254 static const arm_feature_set fpu_vfp_ext_armv8xd =
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
256 static const arm_feature_set fpu_neon_ext_armv8 =
257 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
258 static const arm_feature_set fpu_crypto_ext_armv8 =
259 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
260 static const arm_feature_set crc_ext_armv8 =
261 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
262 static const arm_feature_set fpu_neon_ext_v8_1 =
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA);
265 static int mfloat_abi_opt = -1;
266 /* Record user cpu selection for object attributes. */
267 static arm_feature_set selected_cpu = ARM_ARCH_NONE;
268 /* Must be long enough to hold any of the names in arm_cpus. */
269 static char selected_cpu_name[16];
271 extern FLONUM_TYPE generic_floating_point_number;
273 /* Return if no cpu was selected on command-line. */
275 no_cpu_selected (void)
277 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
282 static int meabi_flags = EABI_DEFAULT;
284 static int meabi_flags = EF_ARM_EABI_UNKNOWN;
287 static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
292 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
297 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
298 symbolS * GOT_symbol;
301 /* 0: assemble for ARM,
302 1: assemble for Thumb,
303 2: assemble for Thumb even though target CPU does not support thumb
305 static int thumb_mode = 0;
306 /* A value distinct from the possible values for thumb_mode that we
307 can use to record whether thumb_mode has been copied into the
308 tc_frag_data field of a frag. */
309 #define MODE_RECORDED (1 << 4)
311 /* Specifies the intrinsic IT insn behavior mode. */
312 enum implicit_it_mode
314 IMPLICIT_IT_MODE_NEVER = 0x00,
315 IMPLICIT_IT_MODE_ARM = 0x01,
316 IMPLICIT_IT_MODE_THUMB = 0x02,
317 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
319 static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
321 /* If unified_syntax is true, we are processing the new unified
322 ARM/Thumb syntax. Important differences from the old ARM mode:
324 - Immediate operands do not require a # prefix.
325 - Conditional affixes always appear at the end of the
326 instruction. (For backward compatibility, those instructions
327 that formerly had them in the middle, continue to accept them
329 - The IT instruction may appear, and if it does is validated
330 against subsequent conditional affixes. It does not generate
333 Important differences from the old Thumb mode:
335 - Immediate operands do not require a # prefix.
336 - Most of the V6T2 instructions are only available in unified mode.
337 - The .N and .W suffixes are recognized and honored (it is an error
338 if they cannot be honored).
339 - All instructions set the flags if and only if they have an 's' affix.
340 - Conditional affixes may be used. They are validated against
341 preceding IT instructions. Unlike ARM mode, you cannot use a
342 conditional affix except in the scope of an IT instruction. */
344 static bfd_boolean unified_syntax = FALSE;
346 /* An immediate operand can start with #, and ld*, st*, pld operands
347 can contain [ and ]. We need to tell APP not to elide whitespace
348 before a [, which can appear as the first operand for pld.
349 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
350 const char arm_symbol_chars[] = "#[]{}";
365 enum neon_el_type type;
369 #define NEON_MAX_TYPE_ELS 4
373 struct neon_type_el el[NEON_MAX_TYPE_ELS];
377 enum it_instruction_type
382 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
383 if inside, should be the last one. */
384 NEUTRAL_IT_INSN, /* This could be either inside or outside,
385 i.e. BKPT and NOP. */
386 IT_INSN /* The IT insn has been parsed. */
389 /* The maximum number of operands we need. */
390 #define ARM_IT_MAX_OPERANDS 6
395 unsigned long instruction;
399 /* "uncond_value" is set to the value in place of the conditional field in
400 unconditional versions of the instruction, or -1 if nothing is
403 struct neon_type vectype;
404 /* This does not indicate an actual NEON instruction, only that
405 the mnemonic accepts neon-style type suffixes. */
407 /* Set to the opcode if the instruction needs relaxation.
408 Zero if the instruction is not relaxed. */
412 bfd_reloc_code_real_type type;
417 enum it_instruction_type it_insn_type;
423 struct neon_type_el vectype;
424 unsigned present : 1; /* Operand present. */
425 unsigned isreg : 1; /* Operand was a register. */
426 unsigned immisreg : 1; /* .imm field is a second register. */
427 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
428 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
429 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
430 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
431 instructions. This allows us to disambiguate ARM <-> vector insns. */
432 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
433 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
434 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
435 unsigned issingle : 1; /* Operand is VFP single-precision register. */
436 unsigned hasreloc : 1; /* Operand has relocation suffix. */
437 unsigned writeback : 1; /* Operand has trailing ! */
438 unsigned preind : 1; /* Preindexed address. */
439 unsigned postind : 1; /* Postindexed address. */
440 unsigned negative : 1; /* Index register was negated. */
441 unsigned shifted : 1; /* Shift applied to operation. */
442 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
443 } operands[ARM_IT_MAX_OPERANDS];
446 static struct arm_it inst;
448 #define NUM_FLOAT_VALS 8
450 const char * fp_const[] =
452 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
455 /* Number of littlenums required to hold an extended precision number. */
456 #define MAX_LITTLENUMS 6
458 LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
468 #define CP_T_X 0x00008000
469 #define CP_T_Y 0x00400000
471 #define CONDS_BIT 0x00100000
472 #define LOAD_BIT 0x00100000
474 #define DOUBLE_LOAD_FLAG 0x00000001
478 const char * template_name;
482 #define COND_ALWAYS 0xE
486 const char * template_name;
490 struct asm_barrier_opt
492 const char * template_name;
494 const arm_feature_set arch;
497 /* The bit that distinguishes CPSR and SPSR. */
498 #define SPSR_BIT (1 << 22)
500 /* The individual PSR flag bits. */
501 #define PSR_c (1 << 16)
502 #define PSR_x (1 << 17)
503 #define PSR_s (1 << 18)
504 #define PSR_f (1 << 19)
509 bfd_reloc_code_real_type reloc;
514 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
515 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
520 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
523 /* Bits for DEFINED field in neon_typed_alias. */
524 #define NTA_HASTYPE 1
525 #define NTA_HASINDEX 2
527 struct neon_typed_alias
529 unsigned char defined;
531 struct neon_type_el eltype;
534 /* ARM register categories. This includes coprocessor numbers and various
535 architecture extensions' registers. */
562 /* Structure for a hash table entry for a register.
563 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
564 information which states whether a vector type or index is specified (for a
565 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
571 unsigned char builtin;
572 struct neon_typed_alias * neon;
575 /* Diagnostics used when we don't get a register of the expected type. */
576 const char * const reg_expected_msgs[] =
578 N_("ARM register expected"),
579 N_("bad or missing co-processor number"),
580 N_("co-processor register expected"),
581 N_("FPA register expected"),
582 N_("VFP single precision register expected"),
583 N_("VFP/Neon double precision register expected"),
584 N_("Neon quad precision register expected"),
585 N_("VFP single or double precision register expected"),
586 N_("Neon double or quad precision register expected"),
587 N_("VFP single, double or Neon quad precision register expected"),
588 N_("VFP system register expected"),
589 N_("Maverick MVF register expected"),
590 N_("Maverick MVD register expected"),
591 N_("Maverick MVFX register expected"),
592 N_("Maverick MVDX register expected"),
593 N_("Maverick MVAX register expected"),
594 N_("Maverick DSPSC register expected"),
595 N_("iWMMXt data register expected"),
596 N_("iWMMXt control register expected"),
597 N_("iWMMXt scalar register expected"),
598 N_("XScale accumulator register expected"),
601 /* Some well known registers that we refer to directly elsewhere. */
607 /* ARM instructions take 4bytes in the object file, Thumb instructions
613 /* Basic string to match. */
614 const char * template_name;
616 /* Parameters to instruction. */
617 unsigned int operands[8];
619 /* Conditional tag - see opcode_lookup. */
620 unsigned int tag : 4;
622 /* Basic instruction code. */
623 unsigned int avalue : 28;
625 /* Thumb-format instruction code. */
628 /* Which architecture variant provides this instruction. */
629 const arm_feature_set * avariant;
630 const arm_feature_set * tvariant;
632 /* Function to call to encode instruction in ARM format. */
633 void (* aencode) (void);
635 /* Function to call to encode instruction in Thumb format. */
636 void (* tencode) (void);
639 /* Defines for various bits that we will want to toggle. */
640 #define INST_IMMEDIATE 0x02000000
641 #define OFFSET_REG 0x02000000
642 #define HWOFFSET_IMM 0x00400000
643 #define SHIFT_BY_REG 0x00000010
644 #define PRE_INDEX 0x01000000
645 #define INDEX_UP 0x00800000
646 #define WRITE_BACK 0x00200000
647 #define LDM_TYPE_2_OR_3 0x00400000
648 #define CPSI_MMOD 0x00020000
650 #define LITERAL_MASK 0xf000f000
651 #define OPCODE_MASK 0xfe1fffff
652 #define V4_STR_BIT 0x00000020
653 #define VLDR_VMOV_SAME 0x0040f000
655 #define T2_SUBS_PC_LR 0xf3de8f00
657 #define DATA_OP_SHIFT 21
659 #define T2_OPCODE_MASK 0xfe1fffff
660 #define T2_DATA_OP_SHIFT 21
662 #define A_COND_MASK 0xf0000000
663 #define A_PUSH_POP_OP_MASK 0x0fff0000
665 /* Opcodes for pushing/poping registers to/from the stack. */
666 #define A1_OPCODE_PUSH 0x092d0000
667 #define A2_OPCODE_PUSH 0x052d0004
668 #define A2_OPCODE_POP 0x049d0004
670 /* Codes to distinguish the arithmetic instructions. */
681 #define OPCODE_CMP 10
682 #define OPCODE_CMN 11
683 #define OPCODE_ORR 12
684 #define OPCODE_MOV 13
685 #define OPCODE_BIC 14
686 #define OPCODE_MVN 15
688 #define T2_OPCODE_AND 0
689 #define T2_OPCODE_BIC 1
690 #define T2_OPCODE_ORR 2
691 #define T2_OPCODE_ORN 3
692 #define T2_OPCODE_EOR 4
693 #define T2_OPCODE_ADD 8
694 #define T2_OPCODE_ADC 10
695 #define T2_OPCODE_SBC 11
696 #define T2_OPCODE_SUB 13
697 #define T2_OPCODE_RSB 14
699 #define T_OPCODE_MUL 0x4340
700 #define T_OPCODE_TST 0x4200
701 #define T_OPCODE_CMN 0x42c0
702 #define T_OPCODE_NEG 0x4240
703 #define T_OPCODE_MVN 0x43c0
705 #define T_OPCODE_ADD_R3 0x1800
706 #define T_OPCODE_SUB_R3 0x1a00
707 #define T_OPCODE_ADD_HI 0x4400
708 #define T_OPCODE_ADD_ST 0xb000
709 #define T_OPCODE_SUB_ST 0xb080
710 #define T_OPCODE_ADD_SP 0xa800
711 #define T_OPCODE_ADD_PC 0xa000
712 #define T_OPCODE_ADD_I8 0x3000
713 #define T_OPCODE_SUB_I8 0x3800
714 #define T_OPCODE_ADD_I3 0x1c00
715 #define T_OPCODE_SUB_I3 0x1e00
717 #define T_OPCODE_ASR_R 0x4100
718 #define T_OPCODE_LSL_R 0x4080
719 #define T_OPCODE_LSR_R 0x40c0
720 #define T_OPCODE_ROR_R 0x41c0
721 #define T_OPCODE_ASR_I 0x1000
722 #define T_OPCODE_LSL_I 0x0000
723 #define T_OPCODE_LSR_I 0x0800
725 #define T_OPCODE_MOV_I8 0x2000
726 #define T_OPCODE_CMP_I8 0x2800
727 #define T_OPCODE_CMP_LR 0x4280
728 #define T_OPCODE_MOV_HR 0x4600
729 #define T_OPCODE_CMP_HR 0x4500
731 #define T_OPCODE_LDR_PC 0x4800
732 #define T_OPCODE_LDR_SP 0x9800
733 #define T_OPCODE_STR_SP 0x9000
734 #define T_OPCODE_LDR_IW 0x6800
735 #define T_OPCODE_STR_IW 0x6000
736 #define T_OPCODE_LDR_IH 0x8800
737 #define T_OPCODE_STR_IH 0x8000
738 #define T_OPCODE_LDR_IB 0x7800
739 #define T_OPCODE_STR_IB 0x7000
740 #define T_OPCODE_LDR_RW 0x5800
741 #define T_OPCODE_STR_RW 0x5000
742 #define T_OPCODE_LDR_RH 0x5a00
743 #define T_OPCODE_STR_RH 0x5200
744 #define T_OPCODE_LDR_RB 0x5c00
745 #define T_OPCODE_STR_RB 0x5400
747 #define T_OPCODE_PUSH 0xb400
748 #define T_OPCODE_POP 0xbc00
750 #define T_OPCODE_BRANCH 0xe000
752 #define THUMB_SIZE 2 /* Size of thumb instruction. */
753 #define THUMB_PP_PC_LR 0x0100
754 #define THUMB_LOAD_BIT 0x0800
755 #define THUMB2_LOAD_BIT 0x00100000
757 #define BAD_ARGS _("bad arguments to instruction")
758 #define BAD_SP _("r13 not allowed here")
759 #define BAD_PC _("r15 not allowed here")
760 #define BAD_COND _("instruction cannot be conditional")
761 #define BAD_OVERLAP _("registers may not be the same")
762 #define BAD_HIREG _("lo register required")
763 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
764 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
765 #define BAD_BRANCH _("branch must be last instruction in IT block")
766 #define BAD_NOT_IT _("instruction not allowed in IT block")
767 #define BAD_FPU _("selected FPU does not support instruction")
768 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
769 #define BAD_IT_COND _("incorrect condition in IT block")
770 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
771 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
772 #define BAD_PC_ADDRESSING \
773 _("cannot use register index with PC-relative addressing")
774 #define BAD_PC_WRITEBACK \
775 _("cannot use writeback with PC-relative addressing")
776 #define BAD_RANGE _("branch out of range")
777 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
779 static struct hash_control * arm_ops_hsh;
780 static struct hash_control * arm_cond_hsh;
781 static struct hash_control * arm_shift_hsh;
782 static struct hash_control * arm_psr_hsh;
783 static struct hash_control * arm_v7m_psr_hsh;
784 static struct hash_control * arm_reg_hsh;
785 static struct hash_control * arm_reloc_hsh;
786 static struct hash_control * arm_barrier_opt_hsh;
788 /* Stuff needed to resolve the label ambiguity
797 symbolS * last_label_seen;
798 static int label_is_thumb_function_name = FALSE;
800 /* Literal pool structure. Held on a per-section
801 and per-sub-section basis. */
803 #define MAX_LITERAL_POOL_SIZE 1024
804 typedef struct literal_pool
806 expressionS literals [MAX_LITERAL_POOL_SIZE];
807 unsigned int next_free_entry;
813 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
815 struct literal_pool * next;
816 unsigned int alignment;
819 /* Pointer to a linked list of literal pools. */
820 literal_pool * list_of_pools = NULL;
822 typedef enum asmfunc_states
825 WAITING_ASMFUNC_NAME,
829 static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
832 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
834 static struct current_it now_it;
838 now_it_compatible (int cond)
840 return (cond & ~1) == (now_it.cc & ~1);
844 conditional_insn (void)
846 return inst.cond != COND_ALWAYS;
849 static int in_it_block (void);
851 static int handle_it_state (void);
853 static void force_automatic_it_block_close (void);
855 static void it_fsm_post_encode (void);
857 #define set_it_insn_type(type) \
860 inst.it_insn_type = type; \
861 if (handle_it_state () == FAIL) \
866 #define set_it_insn_type_nonvoid(type, failret) \
869 inst.it_insn_type = type; \
870 if (handle_it_state () == FAIL) \
875 #define set_it_insn_type_last() \
878 if (inst.cond == COND_ALWAYS) \
879 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
881 set_it_insn_type (INSIDE_IT_LAST_INSN); \
887 /* This array holds the chars that always start a comment. If the
888 pre-processor is disabled, these aren't very useful. */
889 char arm_comment_chars[] = "@";
891 /* This array holds the chars that only start a comment at the beginning of
892 a line. If the line seems to have the form '# 123 filename'
893 .line and .file directives will appear in the pre-processed output. */
894 /* Note that input_file.c hand checks for '#' at the beginning of the
895 first line of the input file. This is because the compiler outputs
896 #NO_APP at the beginning of its output. */
897 /* Also note that comments like this one will always work. */
898 const char line_comment_chars[] = "#";
900 char arm_line_separator_chars[] = ";";
902 /* Chars that can be used to separate mant
903 from exp in floating point numbers. */
904 const char EXP_CHARS[] = "eE";
906 /* Chars that mean this number is a floating point constant. */
910 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
912 /* Prefix characters that indicate the start of an immediate
914 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
916 /* Separator character handling. */
918 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
921 skip_past_char (char ** str, char c)
923 /* PR gas/14987: Allow for whitespace before the expected character. */
924 skip_whitespace (*str);
935 #define skip_past_comma(str) skip_past_char (str, ',')
937 /* Arithmetic expressions (possibly involving symbols). */
939 /* Return TRUE if anything in the expression is a bignum. */
942 walk_no_bignums (symbolS * sp)
944 if (symbol_get_value_expression (sp)->X_op == O_big)
947 if (symbol_get_value_expression (sp)->X_add_symbol)
949 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
950 || (symbol_get_value_expression (sp)->X_op_symbol
951 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
957 static int in_my_get_expression = 0;
959 /* Third argument to my_get_expression. */
960 #define GE_NO_PREFIX 0
961 #define GE_IMM_PREFIX 1
962 #define GE_OPT_PREFIX 2
963 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
964 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
965 #define GE_OPT_PREFIX_BIG 3
968 my_get_expression (expressionS * ep, char ** str, int prefix_mode)
973 /* In unified syntax, all prefixes are optional. */
975 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
980 case GE_NO_PREFIX: break;
982 if (!is_immediate_prefix (**str))
984 inst.error = _("immediate expression requires a # prefix");
990 case GE_OPT_PREFIX_BIG:
991 if (is_immediate_prefix (**str))
997 memset (ep, 0, sizeof (expressionS));
999 save_in = input_line_pointer;
1000 input_line_pointer = *str;
1001 in_my_get_expression = 1;
1002 seg = expression (ep);
1003 in_my_get_expression = 0;
1005 if (ep->X_op == O_illegal || ep->X_op == O_absent)
1007 /* We found a bad or missing expression in md_operand(). */
1008 *str = input_line_pointer;
1009 input_line_pointer = save_in;
1010 if (inst.error == NULL)
1011 inst.error = (ep->X_op == O_absent
1012 ? _("missing expression") :_("bad expression"));
1017 if (seg != absolute_section
1018 && seg != text_section
1019 && seg != data_section
1020 && seg != bss_section
1021 && seg != undefined_section)
1023 inst.error = _("bad segment");
1024 *str = input_line_pointer;
1025 input_line_pointer = save_in;
1032 /* Get rid of any bignums now, so that we don't generate an error for which
1033 we can't establish a line number later on. Big numbers are never valid
1034 in instructions, which is where this routine is always called. */
1035 if (prefix_mode != GE_OPT_PREFIX_BIG
1036 && (ep->X_op == O_big
1037 || (ep->X_add_symbol
1038 && (walk_no_bignums (ep->X_add_symbol)
1040 && walk_no_bignums (ep->X_op_symbol))))))
1042 inst.error = _("invalid constant");
1043 *str = input_line_pointer;
1044 input_line_pointer = save_in;
1048 *str = input_line_pointer;
1049 input_line_pointer = save_in;
1053 /* Turn a string in input_line_pointer into a floating point constant
1054 of type TYPE, and store the appropriate bytes in *LITP. The number
1055 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1056 returned, or NULL on OK.
1058 Note that fp constants aren't represent in the normal way on the ARM.
1059 In big endian mode, things are as expected. However, in little endian
1060 mode fp constants are big-endian word-wise, and little-endian byte-wise
1061 within the words. For example, (double) 1.1 in big endian mode is
1062 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1063 the byte sequence 99 99 f1 3f 9a 99 99 99.
1065 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1068 md_atof (int type, char * litP, int * sizeP)
1071 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1103 return _("Unrecognized or unsupported floating point constant");
1106 t = atof_ieee (input_line_pointer, type, words);
1108 input_line_pointer = t;
1109 *sizeP = prec * sizeof (LITTLENUM_TYPE);
1111 if (target_big_endian)
1113 for (i = 0; i < prec; i++)
1115 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1116 litP += sizeof (LITTLENUM_TYPE);
1121 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1122 for (i = prec - 1; i >= 0; i--)
1124 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1125 litP += sizeof (LITTLENUM_TYPE);
1128 /* For a 4 byte float the order of elements in `words' is 1 0.
1129 For an 8 byte float the order is 1 0 3 2. */
1130 for (i = 0; i < prec; i += 2)
1132 md_number_to_chars (litP, (valueT) words[i + 1],
1133 sizeof (LITTLENUM_TYPE));
1134 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1135 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1136 litP += 2 * sizeof (LITTLENUM_TYPE);
1143 /* We handle all bad expressions here, so that we can report the faulty
1144 instruction in the error message. */
1146 md_operand (expressionS * exp)
1148 if (in_my_get_expression)
1149 exp->X_op = O_illegal;
1152 /* Immediate values. */
1154 /* Generic immediate-value read function for use in directives.
1155 Accepts anything that 'expression' can fold to a constant.
1156 *val receives the number. */
1159 immediate_for_directive (int *val)
1162 exp.X_op = O_illegal;
1164 if (is_immediate_prefix (*input_line_pointer))
1166 input_line_pointer++;
1170 if (exp.X_op != O_constant)
1172 as_bad (_("expected #constant"));
1173 ignore_rest_of_line ();
1176 *val = exp.X_add_number;
1181 /* Register parsing. */
1183 /* Generic register parser. CCP points to what should be the
1184 beginning of a register name. If it is indeed a valid register
1185 name, advance CCP over it and return the reg_entry structure;
1186 otherwise return NULL. Does not issue diagnostics. */
1188 static struct reg_entry *
1189 arm_reg_parse_multi (char **ccp)
1193 struct reg_entry *reg;
1195 skip_whitespace (start);
1197 #ifdef REGISTER_PREFIX
1198 if (*start != REGISTER_PREFIX)
1202 #ifdef OPTIONAL_REGISTER_PREFIX
1203 if (*start == OPTIONAL_REGISTER_PREFIX)
1208 if (!ISALPHA (*p) || !is_name_beginner (*p))
1213 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1215 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1225 arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1226 enum arm_reg_type type)
1228 /* Alternative syntaxes are accepted for a few register classes. */
1235 /* Generic coprocessor register names are allowed for these. */
1236 if (reg && reg->type == REG_TYPE_CN)
1241 /* For backward compatibility, a bare number is valid here. */
1243 unsigned long processor = strtoul (start, ccp, 10);
1244 if (*ccp != start && processor <= 15)
1248 case REG_TYPE_MMXWC:
1249 /* WC includes WCG. ??? I'm not sure this is true for all
1250 instructions that take WC registers. */
1251 if (reg && reg->type == REG_TYPE_MMXWCG)
1262 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1263 return value is the register number or FAIL. */
1266 arm_reg_parse (char **ccp, enum arm_reg_type type)
1269 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1272 /* Do not allow a scalar (reg+index) to parse as a register. */
1273 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1276 if (reg && reg->type == type)
1279 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1286 /* Parse a Neon type specifier. *STR should point at the leading '.'
1287 character. Does no verification at this stage that the type fits the opcode
1294 Can all be legally parsed by this function.
1296 Fills in neon_type struct pointer with parsed information, and updates STR
1297 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1298 type, FAIL if not. */
1301 parse_neon_type (struct neon_type *type, char **str)
1308 while (type->elems < NEON_MAX_TYPE_ELS)
1310 enum neon_el_type thistype = NT_untyped;
1311 unsigned thissize = -1u;
1318 /* Just a size without an explicit type. */
1322 switch (TOLOWER (*ptr))
1324 case 'i': thistype = NT_integer; break;
1325 case 'f': thistype = NT_float; break;
1326 case 'p': thistype = NT_poly; break;
1327 case 's': thistype = NT_signed; break;
1328 case 'u': thistype = NT_unsigned; break;
1330 thistype = NT_float;
1335 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1341 /* .f is an abbreviation for .f32. */
1342 if (thistype == NT_float && !ISDIGIT (*ptr))
1347 thissize = strtoul (ptr, &ptr, 10);
1349 if (thissize != 8 && thissize != 16 && thissize != 32
1352 as_bad (_("bad size %d in type specifier"), thissize);
1360 type->el[type->elems].type = thistype;
1361 type->el[type->elems].size = thissize;
1366 /* Empty/missing type is not a successful parse. */
1367 if (type->elems == 0)
1375 /* Errors may be set multiple times during parsing or bit encoding
1376 (particularly in the Neon bits), but usually the earliest error which is set
1377 will be the most meaningful. Avoid overwriting it with later (cascading)
1378 errors by calling this function. */
1381 first_error (const char *err)
1387 /* Parse a single type, e.g. ".s32", leading period included. */
1389 parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1392 struct neon_type optype;
1396 if (parse_neon_type (&optype, &str) == SUCCESS)
1398 if (optype.elems == 1)
1399 *vectype = optype.el[0];
1402 first_error (_("only one type should be specified for operand"));
1408 first_error (_("vector type expected"));
1420 /* Special meanings for indices (which have a range of 0-7), which will fit into
1423 #define NEON_ALL_LANES 15
1424 #define NEON_INTERLEAVE_LANES 14
1426 /* Parse either a register or a scalar, with an optional type. Return the
1427 register number, and optionally fill in the actual type of the register
1428 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1429 type/index information in *TYPEINFO. */
1432 parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1433 enum arm_reg_type *rtype,
1434 struct neon_typed_alias *typeinfo)
1437 struct reg_entry *reg = arm_reg_parse_multi (&str);
1438 struct neon_typed_alias atype;
1439 struct neon_type_el parsetype;
1443 atype.eltype.type = NT_invtype;
1444 atype.eltype.size = -1;
1446 /* Try alternate syntax for some types of register. Note these are mutually
1447 exclusive with the Neon syntax extensions. */
1450 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1458 /* Undo polymorphism when a set of register types may be accepted. */
1459 if ((type == REG_TYPE_NDQ
1460 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1461 || (type == REG_TYPE_VFSD
1462 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1463 || (type == REG_TYPE_NSDQ
1464 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1465 || reg->type == REG_TYPE_NQ))
1466 || (type == REG_TYPE_MMXWC
1467 && (reg->type == REG_TYPE_MMXWCG)))
1468 type = (enum arm_reg_type) reg->type;
1470 if (type != reg->type)
1476 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1478 if ((atype.defined & NTA_HASTYPE) != 0)
1480 first_error (_("can't redefine type for operand"));
1483 atype.defined |= NTA_HASTYPE;
1484 atype.eltype = parsetype;
1487 if (skip_past_char (&str, '[') == SUCCESS)
1489 if (type != REG_TYPE_VFD)
1491 first_error (_("only D registers may be indexed"));
1495 if ((atype.defined & NTA_HASINDEX) != 0)
1497 first_error (_("can't change index for operand"));
1501 atype.defined |= NTA_HASINDEX;
1503 if (skip_past_char (&str, ']') == SUCCESS)
1504 atype.index = NEON_ALL_LANES;
1509 my_get_expression (&exp, &str, GE_NO_PREFIX);
1511 if (exp.X_op != O_constant)
1513 first_error (_("constant expression required"));
1517 if (skip_past_char (&str, ']') == FAIL)
1520 atype.index = exp.X_add_number;
1535 /* Like arm_reg_parse, but allow allow the following extra features:
1536 - If RTYPE is non-zero, return the (possibly restricted) type of the
1537 register (e.g. Neon double or quad reg when either has been requested).
1538 - If this is a Neon vector type with additional type information, fill
1539 in the struct pointed to by VECTYPE (if non-NULL).
1540 This function will fault on encountering a scalar. */
1543 arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1544 enum arm_reg_type *rtype, struct neon_type_el *vectype)
1546 struct neon_typed_alias atype;
1548 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1553 /* Do not allow regname(... to parse as a register. */
1557 /* Do not allow a scalar (reg+index) to parse as a register. */
1558 if ((atype.defined & NTA_HASINDEX) != 0)
1560 first_error (_("register operand expected, but got scalar"));
1565 *vectype = atype.eltype;
1572 #define NEON_SCALAR_REG(X) ((X) >> 4)
1573 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1575 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1576 have enough information to be able to do a good job bounds-checking. So, we
1577 just do easy checks here, and do further checks later. */
1580 parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
1584 struct neon_typed_alias atype;
1586 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
1588 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1591 if (atype.index == NEON_ALL_LANES)
1593 first_error (_("scalar must have an index"));
1596 else if (atype.index >= 64 / elsize)
1598 first_error (_("scalar index out of range"));
1603 *type = atype.eltype;
1607 return reg * 16 + atype.index;
1610 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1613 parse_reg_list (char ** strp)
1615 char * str = * strp;
1619 /* We come back here if we get ranges concatenated by '+' or '|'. */
1622 skip_whitespace (str);
1636 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
1638 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
1648 first_error (_("bad range in register list"));
1652 for (i = cur_reg + 1; i < reg; i++)
1654 if (range & (1 << i))
1656 (_("Warning: duplicated register (r%d) in register list"),
1664 if (range & (1 << reg))
1665 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1667 else if (reg <= cur_reg)
1668 as_tsktsk (_("Warning: register range not in ascending order"));
1673 while (skip_past_comma (&str) != FAIL
1674 || (in_range = 1, *str++ == '-'));
1677 if (skip_past_char (&str, '}') == FAIL)
1679 first_error (_("missing `}'"));
1687 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
1690 if (exp.X_op == O_constant)
1692 if (exp.X_add_number
1693 != (exp.X_add_number & 0x0000ffff))
1695 inst.error = _("invalid register mask");
1699 if ((range & exp.X_add_number) != 0)
1701 int regno = range & exp.X_add_number;
1704 regno = (1 << regno) - 1;
1706 (_("Warning: duplicated register (r%d) in register list"),
1710 range |= exp.X_add_number;
1714 if (inst.reloc.type != 0)
1716 inst.error = _("expression too complex");
1720 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
1721 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1722 inst.reloc.pc_rel = 0;
1726 if (*str == '|' || *str == '+')
1732 while (another_range);
1738 /* Types of registers in a list. */
1747 /* Parse a VFP register list. If the string is invalid return FAIL.
1748 Otherwise return the number of registers, and set PBASE to the first
1749 register. Parses registers of type ETYPE.
1750 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1751 - Q registers can be used to specify pairs of D registers
1752 - { } can be omitted from around a singleton register list
1753 FIXME: This is not implemented, as it would require backtracking in
1756 This could be done (the meaning isn't really ambiguous), but doesn't
1757 fit in well with the current parsing framework.
1758 - 32 D registers may be used (also true for VFPv3).
1759 FIXME: Types are ignored in these register lists, which is probably a
1763 parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
1768 enum arm_reg_type regtype = (enum arm_reg_type) 0;
1772 unsigned long mask = 0;
1775 if (skip_past_char (&str, '{') == FAIL)
1777 inst.error = _("expecting {");
1784 regtype = REG_TYPE_VFS;
1789 regtype = REG_TYPE_VFD;
1792 case REGLIST_NEON_D:
1793 regtype = REG_TYPE_NDQ;
1797 if (etype != REGLIST_VFP_S)
1799 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1800 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
1804 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1807 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1814 base_reg = max_regs;
1818 int setmask = 1, addregs = 1;
1820 new_base = arm_typed_reg_parse (&str, regtype, ®type, NULL);
1822 if (new_base == FAIL)
1824 first_error (_(reg_expected_msgs[regtype]));
1828 if (new_base >= max_regs)
1830 first_error (_("register out of range in list"));
1834 /* Note: a value of 2 * n is returned for the register Q<n>. */
1835 if (regtype == REG_TYPE_NQ)
1841 if (new_base < base_reg)
1842 base_reg = new_base;
1844 if (mask & (setmask << new_base))
1846 first_error (_("invalid register list"));
1850 if ((mask >> new_base) != 0 && ! warned)
1852 as_tsktsk (_("register list not in ascending order"));
1856 mask |= setmask << new_base;
1859 if (*str == '-') /* We have the start of a range expression */
1865 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
1868 inst.error = gettext (reg_expected_msgs[regtype]);
1872 if (high_range >= max_regs)
1874 first_error (_("register out of range in list"));
1878 if (regtype == REG_TYPE_NQ)
1879 high_range = high_range + 1;
1881 if (high_range <= new_base)
1883 inst.error = _("register range not in ascending order");
1887 for (new_base += addregs; new_base <= high_range; new_base += addregs)
1889 if (mask & (setmask << new_base))
1891 inst.error = _("invalid register list");
1895 mask |= setmask << new_base;
1900 while (skip_past_comma (&str) != FAIL);
1904 /* Sanity check -- should have raised a parse error above. */
1905 if (count == 0 || count > max_regs)
1910 /* Final test -- the registers must be consecutive. */
1912 for (i = 0; i < count; i++)
1914 if ((mask & (1u << i)) == 0)
1916 inst.error = _("non-contiguous register range");
1926 /* True if two alias types are the same. */
1929 neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1937 if (a->defined != b->defined)
1940 if ((a->defined & NTA_HASTYPE) != 0
1941 && (a->eltype.type != b->eltype.type
1942 || a->eltype.size != b->eltype.size))
1945 if ((a->defined & NTA_HASINDEX) != 0
1946 && (a->index != b->index))
1952 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1953 The base register is put in *PBASE.
1954 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1956 The register stride (minus one) is put in bit 4 of the return value.
1957 Bits [6:5] encode the list length (minus one).
1958 The type of the list elements is put in *ELTYPE, if non-NULL. */
1960 #define NEON_LANE(X) ((X) & 0xf)
1961 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1962 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1965 parse_neon_el_struct_list (char **str, unsigned *pbase,
1966 struct neon_type_el *eltype)
1973 int leading_brace = 0;
1974 enum arm_reg_type rtype = REG_TYPE_NDQ;
1975 const char *const incr_error = _("register stride must be 1 or 2");
1976 const char *const type_error = _("mismatched element/structure types in list");
1977 struct neon_typed_alias firsttype;
1979 if (skip_past_char (&ptr, '{') == SUCCESS)
1984 struct neon_typed_alias atype;
1985 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1989 first_error (_(reg_expected_msgs[rtype]));
1996 if (rtype == REG_TYPE_NQ)
2002 else if (reg_incr == -1)
2004 reg_incr = getreg - base_reg;
2005 if (reg_incr < 1 || reg_incr > 2)
2007 first_error (_(incr_error));
2011 else if (getreg != base_reg + reg_incr * count)
2013 first_error (_(incr_error));
2017 if (! neon_alias_types_same (&atype, &firsttype))
2019 first_error (_(type_error));
2023 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2027 struct neon_typed_alias htype;
2028 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2030 lane = NEON_INTERLEAVE_LANES;
2031 else if (lane != NEON_INTERLEAVE_LANES)
2033 first_error (_(type_error));
2038 else if (reg_incr != 1)
2040 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2044 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2047 first_error (_(reg_expected_msgs[rtype]));
2050 if (! neon_alias_types_same (&htype, &firsttype))
2052 first_error (_(type_error));
2055 count += hireg + dregs - getreg;
2059 /* If we're using Q registers, we can't use [] or [n] syntax. */
2060 if (rtype == REG_TYPE_NQ)
2066 if ((atype.defined & NTA_HASINDEX) != 0)
2070 else if (lane != atype.index)
2072 first_error (_(type_error));
2076 else if (lane == -1)
2077 lane = NEON_INTERLEAVE_LANES;
2078 else if (lane != NEON_INTERLEAVE_LANES)
2080 first_error (_(type_error));
2085 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2087 /* No lane set by [x]. We must be interleaving structures. */
2089 lane = NEON_INTERLEAVE_LANES;
2092 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2093 || (count > 1 && reg_incr == -1))
2095 first_error (_("error parsing element/structure list"));
2099 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2101 first_error (_("expected }"));
2109 *eltype = firsttype.eltype;
2114 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2117 /* Parse an explicit relocation suffix on an expression. This is
2118 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2119 arm_reloc_hsh contains no entries, so this function can only
2120 succeed if there is no () after the word. Returns -1 on error,
2121 BFD_RELOC_UNUSED if there wasn't any suffix. */
2124 parse_reloc (char **str)
2126 struct reloc_entry *r;
2130 return BFD_RELOC_UNUSED;
2135 while (*q && *q != ')' && *q != ',')
2140 if ((r = (struct reloc_entry *)
2141 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2148 /* Directives: register aliases. */
2150 static struct reg_entry *
2151 insert_reg_alias (char *str, unsigned number, int type)
2153 struct reg_entry *new_reg;
2156 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
2158 if (new_reg->builtin)
2159 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2161 /* Only warn about a redefinition if it's not defined as the
2163 else if (new_reg->number != number || new_reg->type != type)
2164 as_warn (_("ignoring redefinition of register alias '%s'"), str);
2169 name = xstrdup (str);
2170 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
2172 new_reg->name = name;
2173 new_reg->number = number;
2174 new_reg->type = type;
2175 new_reg->builtin = FALSE;
2176 new_reg->neon = NULL;
2178 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
2185 insert_neon_reg_alias (char *str, int number, int type,
2186 struct neon_typed_alias *atype)
2188 struct reg_entry *reg = insert_reg_alias (str, number, type);
2192 first_error (_("attempt to redefine typed alias"));
2198 reg->neon = (struct neon_typed_alias *)
2199 xmalloc (sizeof (struct neon_typed_alias));
2200 *reg->neon = *atype;
2204 /* Look for the .req directive. This is of the form:
2206 new_register_name .req existing_register_name
2208 If we find one, or if it looks sufficiently like one that we want to
2209 handle any error here, return TRUE. Otherwise return FALSE. */
2212 create_register_alias (char * newname, char *p)
2214 struct reg_entry *old;
2215 char *oldname, *nbuf;
2218 /* The input scrubber ensures that whitespace after the mnemonic is
2219 collapsed to single spaces. */
2221 if (strncmp (oldname, " .req ", 6) != 0)
2225 if (*oldname == '\0')
2228 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
2231 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2235 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2236 the desired alias name, and p points to its end. If not, then
2237 the desired alias name is in the global original_case_string. */
2238 #ifdef TC_CASE_SENSITIVE
2241 newname = original_case_string;
2242 nlen = strlen (newname);
2245 nbuf = (char *) alloca (nlen + 1);
2246 memcpy (nbuf, newname, nlen);
2249 /* Create aliases under the new name as stated; an all-lowercase
2250 version of the new name; and an all-uppercase version of the new
2252 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2254 for (p = nbuf; *p; p++)
2257 if (strncmp (nbuf, newname, nlen))
2259 /* If this attempt to create an additional alias fails, do not bother
2260 trying to create the all-lower case alias. We will fail and issue
2261 a second, duplicate error message. This situation arises when the
2262 programmer does something like:
2265 The second .req creates the "Foo" alias but then fails to create
2266 the artificial FOO alias because it has already been created by the
2268 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2272 for (p = nbuf; *p; p++)
2275 if (strncmp (nbuf, newname, nlen))
2276 insert_reg_alias (nbuf, old->number, old->type);
2282 /* Create a Neon typed/indexed register alias using directives, e.g.:
2287 These typed registers can be used instead of the types specified after the
2288 Neon mnemonic, so long as all operands given have types. Types can also be
2289 specified directly, e.g.:
2290 vadd d0.s32, d1.s32, d2.s32 */
2293 create_neon_reg_alias (char *newname, char *p)
2295 enum arm_reg_type basetype;
2296 struct reg_entry *basereg;
2297 struct reg_entry mybasereg;
2298 struct neon_type ntype;
2299 struct neon_typed_alias typeinfo;
2300 char *namebuf, *nameend ATTRIBUTE_UNUSED;
2303 typeinfo.defined = 0;
2304 typeinfo.eltype.type = NT_invtype;
2305 typeinfo.eltype.size = -1;
2306 typeinfo.index = -1;
2310 if (strncmp (p, " .dn ", 5) == 0)
2311 basetype = REG_TYPE_VFD;
2312 else if (strncmp (p, " .qn ", 5) == 0)
2313 basetype = REG_TYPE_NQ;
2322 basereg = arm_reg_parse_multi (&p);
2324 if (basereg && basereg->type != basetype)
2326 as_bad (_("bad type for register"));
2330 if (basereg == NULL)
2333 /* Try parsing as an integer. */
2334 my_get_expression (&exp, &p, GE_NO_PREFIX);
2335 if (exp.X_op != O_constant)
2337 as_bad (_("expression must be constant"));
2340 basereg = &mybasereg;
2341 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2347 typeinfo = *basereg->neon;
2349 if (parse_neon_type (&ntype, &p) == SUCCESS)
2351 /* We got a type. */
2352 if (typeinfo.defined & NTA_HASTYPE)
2354 as_bad (_("can't redefine the type of a register alias"));
2358 typeinfo.defined |= NTA_HASTYPE;
2359 if (ntype.elems != 1)
2361 as_bad (_("you must specify a single type only"));
2364 typeinfo.eltype = ntype.el[0];
2367 if (skip_past_char (&p, '[') == SUCCESS)
2370 /* We got a scalar index. */
2372 if (typeinfo.defined & NTA_HASINDEX)
2374 as_bad (_("can't redefine the index of a scalar alias"));
2378 my_get_expression (&exp, &p, GE_NO_PREFIX);
2380 if (exp.X_op != O_constant)
2382 as_bad (_("scalar index must be constant"));
2386 typeinfo.defined |= NTA_HASINDEX;
2387 typeinfo.index = exp.X_add_number;
2389 if (skip_past_char (&p, ']') == FAIL)
2391 as_bad (_("expecting ]"));
2396 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2397 the desired alias name, and p points to its end. If not, then
2398 the desired alias name is in the global original_case_string. */
2399 #ifdef TC_CASE_SENSITIVE
2400 namelen = nameend - newname;
2402 newname = original_case_string;
2403 namelen = strlen (newname);
2406 namebuf = (char *) alloca (namelen + 1);
2407 strncpy (namebuf, newname, namelen);
2408 namebuf[namelen] = '\0';
2410 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2411 typeinfo.defined != 0 ? &typeinfo : NULL);
2413 /* Insert name in all uppercase. */
2414 for (p = namebuf; *p; p++)
2417 if (strncmp (namebuf, newname, namelen))
2418 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2419 typeinfo.defined != 0 ? &typeinfo : NULL);
2421 /* Insert name in all lowercase. */
2422 for (p = namebuf; *p; p++)
2425 if (strncmp (namebuf, newname, namelen))
2426 insert_neon_reg_alias (namebuf, basereg->number, basetype,
2427 typeinfo.defined != 0 ? &typeinfo : NULL);
2432 /* Should never be called, as .req goes between the alias and the
2433 register name, not at the beginning of the line. */
2436 s_req (int a ATTRIBUTE_UNUSED)
2438 as_bad (_("invalid syntax for .req directive"));
2442 s_dn (int a ATTRIBUTE_UNUSED)
2444 as_bad (_("invalid syntax for .dn directive"));
2448 s_qn (int a ATTRIBUTE_UNUSED)
2450 as_bad (_("invalid syntax for .qn directive"));
2453 /* The .unreq directive deletes an alias which was previously defined
2454 by .req. For example:
2460 s_unreq (int a ATTRIBUTE_UNUSED)
2465 name = input_line_pointer;
2467 while (*input_line_pointer != 0
2468 && *input_line_pointer != ' '
2469 && *input_line_pointer != '\n')
2470 ++input_line_pointer;
2472 saved_char = *input_line_pointer;
2473 *input_line_pointer = 0;
2476 as_bad (_("invalid syntax for .unreq directive"));
2479 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
2483 as_bad (_("unknown register alias '%s'"), name);
2484 else if (reg->builtin)
2485 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2492 hash_delete (arm_reg_hsh, name, FALSE);
2493 free ((char *) reg->name);
2498 /* Also locate the all upper case and all lower case versions.
2499 Do not complain if we cannot find one or the other as it
2500 was probably deleted above. */
2502 nbuf = strdup (name);
2503 for (p = nbuf; *p; p++)
2505 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2508 hash_delete (arm_reg_hsh, nbuf, FALSE);
2509 free ((char *) reg->name);
2515 for (p = nbuf; *p; p++)
2517 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
2520 hash_delete (arm_reg_hsh, nbuf, FALSE);
2521 free ((char *) reg->name);
2531 *input_line_pointer = saved_char;
2532 demand_empty_rest_of_line ();
2535 /* Directives: Instruction set selection. */
2538 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2539 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2540 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2541 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2543 /* Create a new mapping symbol for the transition to STATE. */
2546 make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2549 const char * symname;
2556 type = BSF_NO_FLAGS;
2560 type = BSF_NO_FLAGS;
2564 type = BSF_NO_FLAGS;
2570 symbolP = symbol_new (symname, now_seg, value, frag);
2571 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2576 THUMB_SET_FUNC (symbolP, 0);
2577 ARM_SET_THUMB (symbolP, 0);
2578 ARM_SET_INTERWORK (symbolP, support_interwork);
2582 THUMB_SET_FUNC (symbolP, 1);
2583 ARM_SET_THUMB (symbolP, 1);
2584 ARM_SET_INTERWORK (symbolP, support_interwork);
2592 /* Save the mapping symbols for future reference. Also check that
2593 we do not place two mapping symbols at the same offset within a
2594 frag. We'll handle overlap between frags in
2595 check_mapping_symbols.
2597 If .fill or other data filling directive generates zero sized data,
2598 the mapping symbol for the following code will have the same value
2599 as the one generated for the data filling directive. In this case,
2600 we replace the old symbol with the new one at the same address. */
2603 if (frag->tc_frag_data.first_map != NULL)
2605 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2606 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2608 frag->tc_frag_data.first_map = symbolP;
2610 if (frag->tc_frag_data.last_map != NULL)
2612 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
2613 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2614 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2616 frag->tc_frag_data.last_map = symbolP;
2619 /* We must sometimes convert a region marked as code to data during
2620 code alignment, if an odd number of bytes have to be padded. The
2621 code mapping symbol is pushed to an aligned address. */
2624 insert_data_mapping_symbol (enum mstate state,
2625 valueT value, fragS *frag, offsetT bytes)
2627 /* If there was already a mapping symbol, remove it. */
2628 if (frag->tc_frag_data.last_map != NULL
2629 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2631 symbolS *symp = frag->tc_frag_data.last_map;
2635 know (frag->tc_frag_data.first_map == symp);
2636 frag->tc_frag_data.first_map = NULL;
2638 frag->tc_frag_data.last_map = NULL;
2639 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
2642 make_mapping_symbol (MAP_DATA, value, frag);
2643 make_mapping_symbol (state, value + bytes, frag);
2646 static void mapping_state_2 (enum mstate state, int max_chars);
2648 /* Set the mapping state to STATE. Only call this when about to
2649 emit some STATE bytes to the file. */
2651 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2653 mapping_state (enum mstate state)
2655 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2657 if (mapstate == state)
2658 /* The mapping symbol has already been emitted.
2659 There is nothing else to do. */
2662 if (state == MAP_ARM || state == MAP_THUMB)
2664 All ARM instructions require 4-byte alignment.
2665 (Almost) all Thumb instructions require 2-byte alignment.
2667 When emitting instructions into any section, mark the section
2670 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2671 but themselves require 2-byte alignment; this applies to some
2672 PC- relative forms. However, these cases will invovle implicit
2673 literal pool generation or an explicit .align >=2, both of
2674 which will cause the section to me marked with sufficient
2675 alignment. Thus, we don't handle those cases here. */
2676 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2678 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
2679 /* This case will be evaluated later. */
2682 mapping_state_2 (state, 0);
2685 /* Same as mapping_state, but MAX_CHARS bytes have already been
2686 allocated. Put the mapping symbol that far back. */
2689 mapping_state_2 (enum mstate state, int max_chars)
2691 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2693 if (!SEG_NORMAL (now_seg))
2696 if (mapstate == state)
2697 /* The mapping symbol has already been emitted.
2698 There is nothing else to do. */
2701 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2702 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2704 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2705 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2708 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2711 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2712 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
2716 #define mapping_state(x) ((void)0)
2717 #define mapping_state_2(x, y) ((void)0)
2720 /* Find the real, Thumb encoded start of a Thumb function. */
2724 find_real_start (symbolS * symbolP)
2727 const char * name = S_GET_NAME (symbolP);
2728 symbolS * new_target;
2730 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2731 #define STUB_NAME ".real_start_of"
2736 /* The compiler may generate BL instructions to local labels because
2737 it needs to perform a branch to a far away location. These labels
2738 do not have a corresponding ".real_start_of" label. We check
2739 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2740 the ".real_start_of" convention for nonlocal branches. */
2741 if (S_IS_LOCAL (symbolP) || name[0] == '.')
2744 real_start = ACONCAT ((STUB_NAME, name, NULL));
2745 new_target = symbol_find (real_start);
2747 if (new_target == NULL)
2749 as_warn (_("Failed to find real start of function: %s\n"), name);
2750 new_target = symbolP;
2758 opcode_select (int width)
2765 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
2766 as_bad (_("selected processor does not support THUMB opcodes"));
2769 /* No need to force the alignment, since we will have been
2770 coming from ARM mode, which is word-aligned. */
2771 record_alignment (now_seg, 1);
2778 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
2779 as_bad (_("selected processor does not support ARM opcodes"));
2784 frag_align (2, 0, 0);
2786 record_alignment (now_seg, 1);
2791 as_bad (_("invalid instruction size selected (%d)"), width);
2796 s_arm (int ignore ATTRIBUTE_UNUSED)
2799 demand_empty_rest_of_line ();
2803 s_thumb (int ignore ATTRIBUTE_UNUSED)
2806 demand_empty_rest_of_line ();
2810 s_code (int unused ATTRIBUTE_UNUSED)
2814 temp = get_absolute_expression ();
2819 opcode_select (temp);
2823 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2828 s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2830 /* If we are not already in thumb mode go into it, EVEN if
2831 the target processor does not support thumb instructions.
2832 This is used by gcc/config/arm/lib1funcs.asm for example
2833 to compile interworking support functions even if the
2834 target processor should not support interworking. */
2838 record_alignment (now_seg, 1);
2841 demand_empty_rest_of_line ();
2845 s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2849 /* The following label is the name/address of the start of a Thumb function.
2850 We need to know this for the interworking support. */
2851 label_is_thumb_function_name = TRUE;
2854 /* Perform a .set directive, but also mark the alias as
2855 being a thumb function. */
2858 s_thumb_set (int equiv)
2860 /* XXX the following is a duplicate of the code for s_set() in read.c
2861 We cannot just call that code as we need to get at the symbol that
2868 /* Especial apologies for the random logic:
2869 This just grew, and could be parsed much more simply!
2871 name = input_line_pointer;
2872 delim = get_symbol_end ();
2873 end_name = input_line_pointer;
2876 if (*input_line_pointer != ',')
2879 as_bad (_("expected comma after name \"%s\""), name);
2881 ignore_rest_of_line ();
2885 input_line_pointer++;
2888 if (name[0] == '.' && name[1] == '\0')
2890 /* XXX - this should not happen to .thumb_set. */
2894 if ((symbolP = symbol_find (name)) == NULL
2895 && (symbolP = md_undefined_symbol (name)) == NULL)
2898 /* When doing symbol listings, play games with dummy fragments living
2899 outside the normal fragment chain to record the file and line info
2901 if (listing & LISTING_SYMBOLS)
2903 extern struct list_info_struct * listing_tail;
2904 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
2906 memset (dummy_frag, 0, sizeof (fragS));
2907 dummy_frag->fr_type = rs_fill;
2908 dummy_frag->line = listing_tail;
2909 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2910 dummy_frag->fr_symbol = symbolP;
2914 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2917 /* "set" symbols are local unless otherwise specified. */
2918 SF_SET_LOCAL (symbolP);
2919 #endif /* OBJ_COFF */
2920 } /* Make a new symbol. */
2922 symbol_table_insert (symbolP);
2927 && S_IS_DEFINED (symbolP)
2928 && S_GET_SEGMENT (symbolP) != reg_section)
2929 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2931 pseudo_set (symbolP);
2933 demand_empty_rest_of_line ();
2935 /* XXX Now we come to the Thumb specific bit of code. */
2937 THUMB_SET_FUNC (symbolP, 1);
2938 ARM_SET_THUMB (symbolP, 1);
2939 #if defined OBJ_ELF || defined OBJ_COFF
2940 ARM_SET_INTERWORK (symbolP, support_interwork);
2944 /* Directives: Mode selection. */
2946 /* .syntax [unified|divided] - choose the new unified syntax
2947 (same for Arm and Thumb encoding, modulo slight differences in what
2948 can be represented) or the old divergent syntax for each mode. */
2950 s_syntax (int unused ATTRIBUTE_UNUSED)
2954 name = input_line_pointer;
2955 delim = get_symbol_end ();
2957 if (!strcasecmp (name, "unified"))
2958 unified_syntax = TRUE;
2959 else if (!strcasecmp (name, "divided"))
2960 unified_syntax = FALSE;
2963 as_bad (_("unrecognized syntax mode \"%s\""), name);
2966 *input_line_pointer = delim;
2967 demand_empty_rest_of_line ();
2970 /* Directives: sectioning and alignment. */
2972 /* Same as s_align_ptwo but align 0 => align 2. */
2975 s_align (int unused ATTRIBUTE_UNUSED)
2980 long max_alignment = 15;
2982 temp = get_absolute_expression ();
2983 if (temp > max_alignment)
2984 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2987 as_bad (_("alignment negative. 0 assumed."));
2991 if (*input_line_pointer == ',')
2993 input_line_pointer++;
2994 temp_fill = get_absolute_expression ();
3006 /* Only make a frag if we HAVE to. */
3007 if (temp && !need_pass_2)
3009 if (!fill_p && subseg_text_p (now_seg))
3010 frag_align_code (temp, 0);
3012 frag_align (temp, (int) temp_fill, 0);
3014 demand_empty_rest_of_line ();
3016 record_alignment (now_seg, temp);
3020 s_bss (int ignore ATTRIBUTE_UNUSED)
3022 /* We don't support putting frags in the BSS segment, we fake it by
3023 marking in_bss, then looking at s_skip for clues. */
3024 subseg_set (bss_section, 0);
3025 demand_empty_rest_of_line ();
3027 #ifdef md_elf_section_change_hook
3028 md_elf_section_change_hook ();
3033 s_even (int ignore ATTRIBUTE_UNUSED)
3035 /* Never make frag if expect extra pass. */
3037 frag_align (1, 0, 0);
3039 record_alignment (now_seg, 1);
3041 demand_empty_rest_of_line ();
3044 /* Directives: CodeComposer Studio. */
3046 /* .ref (for CodeComposer Studio syntax only). */
3048 s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3050 if (codecomposer_syntax)
3051 ignore_rest_of_line ();
3053 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3056 /* If name is not NULL, then it is used for marking the beginning of a
3057 function, wherease if it is NULL then it means the function end. */
3059 asmfunc_debug (const char * name)
3061 static const char * last_name = NULL;
3065 gas_assert (last_name == NULL);
3068 if (debug_type == DEBUG_STABS)
3069 stabs_generate_asm_func (name, name);
3073 gas_assert (last_name != NULL);
3075 if (debug_type == DEBUG_STABS)
3076 stabs_generate_asm_endfunc (last_name, last_name);
3083 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3085 if (codecomposer_syntax)
3087 switch (asmfunc_state)
3089 case OUTSIDE_ASMFUNC:
3090 asmfunc_state = WAITING_ASMFUNC_NAME;
3093 case WAITING_ASMFUNC_NAME:
3094 as_bad (_(".asmfunc repeated."));
3097 case WAITING_ENDASMFUNC:
3098 as_bad (_(".asmfunc without function."));
3101 demand_empty_rest_of_line ();
3104 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3108 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3110 if (codecomposer_syntax)
3112 switch (asmfunc_state)
3114 case OUTSIDE_ASMFUNC:
3115 as_bad (_(".endasmfunc without a .asmfunc."));
3118 case WAITING_ASMFUNC_NAME:
3119 as_bad (_(".endasmfunc without function."));
3122 case WAITING_ENDASMFUNC:
3123 asmfunc_state = OUTSIDE_ASMFUNC;
3124 asmfunc_debug (NULL);
3127 demand_empty_rest_of_line ();
3130 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3134 s_ccs_def (int name)
3136 if (codecomposer_syntax)
3139 as_bad (_(".def pseudo-op only available with -mccs flag."));
3142 /* Directives: Literal pools. */
3144 static literal_pool *
3145 find_literal_pool (void)
3147 literal_pool * pool;
3149 for (pool = list_of_pools; pool != NULL; pool = pool->next)
3151 if (pool->section == now_seg
3152 && pool->sub_section == now_subseg)
3159 static literal_pool *
3160 find_or_make_literal_pool (void)
3162 /* Next literal pool ID number. */
3163 static unsigned int latest_pool_num = 1;
3164 literal_pool * pool;
3166 pool = find_literal_pool ();
3170 /* Create a new pool. */
3171 pool = (literal_pool *) xmalloc (sizeof (* pool));
3175 pool->next_free_entry = 0;
3176 pool->section = now_seg;
3177 pool->sub_section = now_subseg;
3178 pool->next = list_of_pools;
3179 pool->symbol = NULL;
3180 pool->alignment = 2;
3182 /* Add it to the list. */
3183 list_of_pools = pool;
3186 /* New pools, and emptied pools, will have a NULL symbol. */
3187 if (pool->symbol == NULL)
3189 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3190 (valueT) 0, &zero_address_frag);
3191 pool->id = latest_pool_num ++;
3198 /* Add the literal in the global 'inst'
3199 structure to the relevant literal pool. */
3202 add_to_lit_pool (unsigned int nbytes)
3204 #define PADDING_SLOT 0x1
3205 #define LIT_ENTRY_SIZE_MASK 0xFF
3206 literal_pool * pool;
3207 unsigned int entry, pool_size = 0;
3208 bfd_boolean padding_slot_p = FALSE;
3214 imm1 = inst.operands[1].imm;
3215 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3216 : inst.reloc.exp.X_unsigned ? 0
3217 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
3218 if (target_big_endian)
3221 imm2 = inst.operands[1].imm;
3225 pool = find_or_make_literal_pool ();
3227 /* Check if this literal value is already in the pool. */
3228 for (entry = 0; entry < pool->next_free_entry; entry ++)
3232 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3233 && (inst.reloc.exp.X_op == O_constant)
3234 && (pool->literals[entry].X_add_number
3235 == inst.reloc.exp.X_add_number)
3236 && (pool->literals[entry].X_md == nbytes)
3237 && (pool->literals[entry].X_unsigned
3238 == inst.reloc.exp.X_unsigned))
3241 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3242 && (inst.reloc.exp.X_op == O_symbol)
3243 && (pool->literals[entry].X_add_number
3244 == inst.reloc.exp.X_add_number)
3245 && (pool->literals[entry].X_add_symbol
3246 == inst.reloc.exp.X_add_symbol)
3247 && (pool->literals[entry].X_op_symbol
3248 == inst.reloc.exp.X_op_symbol)
3249 && (pool->literals[entry].X_md == nbytes))
3252 else if ((nbytes == 8)
3253 && !(pool_size & 0x7)
3254 && ((entry + 1) != pool->next_free_entry)
3255 && (pool->literals[entry].X_op == O_constant)
3256 && (pool->literals[entry].X_add_number == (offsetT) imm1)
3257 && (pool->literals[entry].X_unsigned
3258 == inst.reloc.exp.X_unsigned)
3259 && (pool->literals[entry + 1].X_op == O_constant)
3260 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3261 && (pool->literals[entry + 1].X_unsigned
3262 == inst.reloc.exp.X_unsigned))
3265 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3266 if (padding_slot_p && (nbytes == 4))
3272 /* Do we need to create a new entry? */
3273 if (entry == pool->next_free_entry)
3275 if (entry >= MAX_LITERAL_POOL_SIZE)
3277 inst.error = _("literal pool overflow");
3283 /* For 8-byte entries, we align to an 8-byte boundary,
3284 and split it into two 4-byte entries, because on 32-bit
3285 host, 8-byte constants are treated as big num, thus
3286 saved in "generic_bignum" which will be overwritten
3287 by later assignments.
3289 We also need to make sure there is enough space for
3292 We also check to make sure the literal operand is a
3294 if (!(inst.reloc.exp.X_op == O_constant
3295 || inst.reloc.exp.X_op == O_big))
3297 inst.error = _("invalid type for literal pool");
3300 else if (pool_size & 0x7)
3302 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3304 inst.error = _("literal pool overflow");
3308 pool->literals[entry] = inst.reloc.exp;
3309 pool->literals[entry].X_add_number = 0;
3310 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3311 pool->next_free_entry += 1;
3314 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3316 inst.error = _("literal pool overflow");
3320 pool->literals[entry] = inst.reloc.exp;
3321 pool->literals[entry].X_op = O_constant;
3322 pool->literals[entry].X_add_number = imm1;
3323 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3324 pool->literals[entry++].X_md = 4;
3325 pool->literals[entry] = inst.reloc.exp;
3326 pool->literals[entry].X_op = O_constant;
3327 pool->literals[entry].X_add_number = imm2;
3328 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3329 pool->literals[entry].X_md = 4;
3330 pool->alignment = 3;
3331 pool->next_free_entry += 1;
3335 pool->literals[entry] = inst.reloc.exp;
3336 pool->literals[entry].X_md = 4;
3340 /* PR ld/12974: Record the location of the first source line to reference
3341 this entry in the literal pool. If it turns out during linking that the
3342 symbol does not exist we will be able to give an accurate line number for
3343 the (first use of the) missing reference. */
3344 if (debug_type == DEBUG_DWARF2)
3345 dwarf2_where (pool->locs + entry);
3347 pool->next_free_entry += 1;
3349 else if (padding_slot_p)
3351 pool->literals[entry] = inst.reloc.exp;
3352 pool->literals[entry].X_md = nbytes;
3355 inst.reloc.exp.X_op = O_symbol;
3356 inst.reloc.exp.X_add_number = pool_size;
3357 inst.reloc.exp.X_add_symbol = pool->symbol;
3363 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest)
3365 bfd_boolean ret = TRUE;
3367 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3369 const char *label = rest;
3371 while (!is_end_of_line[(int) label[-1]])
3376 as_bad (_("Invalid label '%s'"), label);
3380 asmfunc_debug (label);
3382 asmfunc_state = WAITING_ENDASMFUNC;
3388 /* Can't use symbol_new here, so have to create a symbol and then at
3389 a later date assign it a value. Thats what these functions do. */
3392 symbol_locate (symbolS * symbolP,
3393 const char * name, /* It is copied, the caller can modify. */
3394 segT segment, /* Segment identifier (SEG_<something>). */
3395 valueT valu, /* Symbol value. */
3396 fragS * frag) /* Associated fragment. */
3399 char * preserved_copy_of_name;
3401 name_length = strlen (name) + 1; /* +1 for \0. */
3402 obstack_grow (¬es, name, name_length);
3403 preserved_copy_of_name = (char *) obstack_finish (¬es);
3405 #ifdef tc_canonicalize_symbol_name
3406 preserved_copy_of_name =
3407 tc_canonicalize_symbol_name (preserved_copy_of_name);
3410 S_SET_NAME (symbolP, preserved_copy_of_name);
3412 S_SET_SEGMENT (symbolP, segment);
3413 S_SET_VALUE (symbolP, valu);
3414 symbol_clear_list_pointers (symbolP);
3416 symbol_set_frag (symbolP, frag);
3418 /* Link to end of symbol chain. */
3420 extern int symbol_table_frozen;
3422 if (symbol_table_frozen)
3426 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3428 obj_symbol_new_hook (symbolP);
3430 #ifdef tc_symbol_new_hook
3431 tc_symbol_new_hook (symbolP);
3435 verify_symbol_chain (symbol_rootP, symbol_lastP);
3436 #endif /* DEBUG_SYMS */
3440 s_ltorg (int ignored ATTRIBUTE_UNUSED)
3443 literal_pool * pool;
3446 pool = find_literal_pool ();
3448 || pool->symbol == NULL
3449 || pool->next_free_entry == 0)
3452 /* Align pool as you have word accesses.
3453 Only make a frag if we have to. */
3455 frag_align (pool->alignment, 0, 0);
3457 record_alignment (now_seg, 2);
3460 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3461 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3463 sprintf (sym_name, "$$lit_\002%x", pool->id);
3465 symbol_locate (pool->symbol, sym_name, now_seg,
3466 (valueT) frag_now_fix (), frag_now);
3467 symbol_table_insert (pool->symbol);
3469 ARM_SET_THUMB (pool->symbol, thumb_mode);
3471 #if defined OBJ_COFF || defined OBJ_ELF
3472 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3475 for (entry = 0; entry < pool->next_free_entry; entry ++)
3478 if (debug_type == DEBUG_DWARF2)
3479 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3481 /* First output the expression in the instruction to the pool. */
3482 emit_expr (&(pool->literals[entry]),
3483 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3486 /* Mark the pool as empty. */
3487 pool->next_free_entry = 0;
3488 pool->symbol = NULL;
3492 /* Forward declarations for functions below, in the MD interface
3494 static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3495 static valueT create_unwind_entry (int);
3496 static void start_unwind_section (const segT, int);
3497 static void add_unwind_opcode (valueT, int);
3498 static void flush_pending_unwind (void);
3500 /* Directives: Data. */
3503 s_arm_elf_cons (int nbytes)
3507 #ifdef md_flush_pending_output
3508 md_flush_pending_output ();
3511 if (is_it_end_of_statement ())
3513 demand_empty_rest_of_line ();
3517 #ifdef md_cons_align
3518 md_cons_align (nbytes);
3521 mapping_state (MAP_DATA);
3525 char *base = input_line_pointer;
3529 if (exp.X_op != O_symbol)
3530 emit_expr (&exp, (unsigned int) nbytes);
3533 char *before_reloc = input_line_pointer;
3534 reloc = parse_reloc (&input_line_pointer);
3537 as_bad (_("unrecognized relocation suffix"));
3538 ignore_rest_of_line ();
3541 else if (reloc == BFD_RELOC_UNUSED)
3542 emit_expr (&exp, (unsigned int) nbytes);
3545 reloc_howto_type *howto = (reloc_howto_type *)
3546 bfd_reloc_type_lookup (stdoutput,
3547 (bfd_reloc_code_real_type) reloc);
3548 int size = bfd_get_reloc_size (howto);
3550 if (reloc == BFD_RELOC_ARM_PLT32)
3552 as_bad (_("(plt) is only valid on branch targets"));
3553 reloc = BFD_RELOC_UNUSED;
3558 as_bad (_("%s relocations do not fit in %d bytes"),
3559 howto->name, nbytes);
3562 /* We've parsed an expression stopping at O_symbol.
3563 But there may be more expression left now that we
3564 have parsed the relocation marker. Parse it again.
3565 XXX Surely there is a cleaner way to do this. */
3566 char *p = input_line_pointer;
3568 char *save_buf = (char *) alloca (input_line_pointer - base);
3569 memcpy (save_buf, base, input_line_pointer - base);
3570 memmove (base + (input_line_pointer - before_reloc),
3571 base, before_reloc - base);
3573 input_line_pointer = base + (input_line_pointer-before_reloc);
3575 memcpy (base, save_buf, p - base);
3577 offset = nbytes - size;
3578 p = frag_more (nbytes);
3579 memset (p, 0, nbytes);
3580 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3581 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3586 while (*input_line_pointer++ == ',');
3588 /* Put terminator back into stream. */
3589 input_line_pointer --;
3590 demand_empty_rest_of_line ();
3593 /* Emit an expression containing a 32-bit thumb instruction.
3594 Implementation based on put_thumb32_insn. */
3597 emit_thumb32_expr (expressionS * exp)
3599 expressionS exp_high = *exp;
3601 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3602 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3603 exp->X_add_number &= 0xffff;
3604 emit_expr (exp, (unsigned int) THUMB_SIZE);
3607 /* Guess the instruction size based on the opcode. */
3610 thumb_insn_size (int opcode)
3612 if ((unsigned int) opcode < 0xe800u)
3614 else if ((unsigned int) opcode >= 0xe8000000u)
3621 emit_insn (expressionS *exp, int nbytes)
3625 if (exp->X_op == O_constant)
3630 size = thumb_insn_size (exp->X_add_number);
3634 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3636 as_bad (_(".inst.n operand too big. "\
3637 "Use .inst.w instead"));
3642 if (now_it.state == AUTOMATIC_IT_BLOCK)
3643 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3645 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3647 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3648 emit_thumb32_expr (exp);
3650 emit_expr (exp, (unsigned int) size);
3652 it_fsm_post_encode ();
3656 as_bad (_("cannot determine Thumb instruction size. " \
3657 "Use .inst.n/.inst.w instead"));
3660 as_bad (_("constant expression required"));
3665 /* Like s_arm_elf_cons but do not use md_cons_align and
3666 set the mapping state to MAP_ARM/MAP_THUMB. */
3669 s_arm_elf_inst (int nbytes)
3671 if (is_it_end_of_statement ())
3673 demand_empty_rest_of_line ();
3677 /* Calling mapping_state () here will not change ARM/THUMB,
3678 but will ensure not to be in DATA state. */
3681 mapping_state (MAP_THUMB);
3686 as_bad (_("width suffixes are invalid in ARM mode"));
3687 ignore_rest_of_line ();
3693 mapping_state (MAP_ARM);
3702 if (! emit_insn (& exp, nbytes))
3704 ignore_rest_of_line ();
3708 while (*input_line_pointer++ == ',');
3710 /* Put terminator back into stream. */
3711 input_line_pointer --;
3712 demand_empty_rest_of_line ();
3715 /* Parse a .rel31 directive. */
3718 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3725 if (*input_line_pointer == '1')
3726 highbit = 0x80000000;
3727 else if (*input_line_pointer != '0')
3728 as_bad (_("expected 0 or 1"));
3730 input_line_pointer++;
3731 if (*input_line_pointer != ',')
3732 as_bad (_("missing comma"));
3733 input_line_pointer++;
3735 #ifdef md_flush_pending_output
3736 md_flush_pending_output ();
3739 #ifdef md_cons_align
3743 mapping_state (MAP_DATA);
3748 md_number_to_chars (p, highbit, 4);
3749 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3750 BFD_RELOC_ARM_PREL31);
3752 demand_empty_rest_of_line ();
3755 /* Directives: AEABI stack-unwind tables. */
3757 /* Parse an unwind_fnstart directive. Simply records the current location. */
3760 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3762 demand_empty_rest_of_line ();
3763 if (unwind.proc_start)
3765 as_bad (_("duplicate .fnstart directive"));
3769 /* Mark the start of the function. */
3770 unwind.proc_start = expr_build_dot ();
3772 /* Reset the rest of the unwind info. */
3773 unwind.opcode_count = 0;
3774 unwind.table_entry = NULL;
3775 unwind.personality_routine = NULL;
3776 unwind.personality_index = -1;
3777 unwind.frame_size = 0;
3778 unwind.fp_offset = 0;
3779 unwind.fp_reg = REG_SP;
3781 unwind.sp_restored = 0;
3785 /* Parse a handlerdata directive. Creates the exception handling table entry
3786 for the function. */
3789 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3791 demand_empty_rest_of_line ();
3792 if (!unwind.proc_start)
3793 as_bad (MISSING_FNSTART);
3795 if (unwind.table_entry)
3796 as_bad (_("duplicate .handlerdata directive"));
3798 create_unwind_entry (1);
3801 /* Parse an unwind_fnend directive. Generates the index table entry. */
3804 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3809 unsigned int marked_pr_dependency;
3811 demand_empty_rest_of_line ();
3813 if (!unwind.proc_start)
3815 as_bad (_(".fnend directive without .fnstart"));
3819 /* Add eh table entry. */
3820 if (unwind.table_entry == NULL)
3821 val = create_unwind_entry (0);
3825 /* Add index table entry. This is two words. */
3826 start_unwind_section (unwind.saved_seg, 1);
3827 frag_align (2, 0, 0);
3828 record_alignment (now_seg, 2);
3830 ptr = frag_more (8);
3832 where = frag_now_fix () - 8;
3834 /* Self relative offset of the function start. */
3835 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3836 BFD_RELOC_ARM_PREL31);
3838 /* Indicate dependency on EHABI-defined personality routines to the
3839 linker, if it hasn't been done already. */
3840 marked_pr_dependency
3841 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
3842 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3843 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3845 static const char *const name[] =
3847 "__aeabi_unwind_cpp_pr0",
3848 "__aeabi_unwind_cpp_pr1",
3849 "__aeabi_unwind_cpp_pr2"
3851 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3852 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
3853 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
3854 |= 1 << unwind.personality_index;
3858 /* Inline exception table entry. */
3859 md_number_to_chars (ptr + 4, val, 4);
3861 /* Self relative offset of the table entry. */
3862 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3863 BFD_RELOC_ARM_PREL31);
3865 /* Restore the original section. */
3866 subseg_set (unwind.saved_seg, unwind.saved_subseg);
3868 unwind.proc_start = NULL;
3872 /* Parse an unwind_cantunwind directive. */
3875 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3877 demand_empty_rest_of_line ();
3878 if (!unwind.proc_start)
3879 as_bad (MISSING_FNSTART);
3881 if (unwind.personality_routine || unwind.personality_index != -1)
3882 as_bad (_("personality routine specified for cantunwind frame"));
3884 unwind.personality_index = -2;
3888 /* Parse a personalityindex directive. */
3891 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3895 if (!unwind.proc_start)
3896 as_bad (MISSING_FNSTART);
3898 if (unwind.personality_routine || unwind.personality_index != -1)
3899 as_bad (_("duplicate .personalityindex directive"));
3903 if (exp.X_op != O_constant
3904 || exp.X_add_number < 0 || exp.X_add_number > 15)
3906 as_bad (_("bad personality routine number"));
3907 ignore_rest_of_line ();
3911 unwind.personality_index = exp.X_add_number;
3913 demand_empty_rest_of_line ();
3917 /* Parse a personality directive. */
3920 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3924 if (!unwind.proc_start)
3925 as_bad (MISSING_FNSTART);
3927 if (unwind.personality_routine || unwind.personality_index != -1)
3928 as_bad (_("duplicate .personality directive"));
3930 name = input_line_pointer;
3931 c = get_symbol_end ();
3932 p = input_line_pointer;
3933 unwind.personality_routine = symbol_find_or_make (name);
3935 demand_empty_rest_of_line ();
3939 /* Parse a directive saving core registers. */
3942 s_arm_unwind_save_core (void)
3948 range = parse_reg_list (&input_line_pointer);
3951 as_bad (_("expected register list"));
3952 ignore_rest_of_line ();
3956 demand_empty_rest_of_line ();
3958 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3959 into .unwind_save {..., sp...}. We aren't bothered about the value of
3960 ip because it is clobbered by calls. */
3961 if (unwind.sp_restored && unwind.fp_reg == 12
3962 && (range & 0x3000) == 0x1000)
3964 unwind.opcode_count--;
3965 unwind.sp_restored = 0;
3966 range = (range | 0x2000) & ~0x1000;
3967 unwind.pending_offset = 0;
3973 /* See if we can use the short opcodes. These pop a block of up to 8
3974 registers starting with r4, plus maybe r14. */
3975 for (n = 0; n < 8; n++)
3977 /* Break at the first non-saved register. */
3978 if ((range & (1 << (n + 4))) == 0)
3981 /* See if there are any other bits set. */
3982 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3984 /* Use the long form. */
3985 op = 0x8000 | ((range >> 4) & 0xfff);
3986 add_unwind_opcode (op, 2);
3990 /* Use the short form. */
3992 op = 0xa8; /* Pop r14. */
3994 op = 0xa0; /* Do not pop r14. */
3996 add_unwind_opcode (op, 1);
4003 op = 0xb100 | (range & 0xf);
4004 add_unwind_opcode (op, 2);
4007 /* Record the number of bytes pushed. */
4008 for (n = 0; n < 16; n++)
4010 if (range & (1 << n))
4011 unwind.frame_size += 4;
4016 /* Parse a directive saving FPA registers. */
4019 s_arm_unwind_save_fpa (int reg)
4025 /* Get Number of registers to transfer. */
4026 if (skip_past_comma (&input_line_pointer) != FAIL)
4029 exp.X_op = O_illegal;
4031 if (exp.X_op != O_constant)
4033 as_bad (_("expected , <constant>"));
4034 ignore_rest_of_line ();
4038 num_regs = exp.X_add_number;
4040 if (num_regs < 1 || num_regs > 4)
4042 as_bad (_("number of registers must be in the range [1:4]"));
4043 ignore_rest_of_line ();
4047 demand_empty_rest_of_line ();
4052 op = 0xb4 | (num_regs - 1);
4053 add_unwind_opcode (op, 1);
4058 op = 0xc800 | (reg << 4) | (num_regs - 1);
4059 add_unwind_opcode (op, 2);
4061 unwind.frame_size += num_regs * 12;
4065 /* Parse a directive saving VFP registers for ARMv6 and above. */
4068 s_arm_unwind_save_vfp_armv6 (void)
4073 int num_vfpv3_regs = 0;
4074 int num_regs_below_16;
4076 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4079 as_bad (_("expected register list"));
4080 ignore_rest_of_line ();
4084 demand_empty_rest_of_line ();
4086 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4087 than FSTMX/FLDMX-style ones). */
4089 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4091 num_vfpv3_regs = count;
4092 else if (start + count > 16)
4093 num_vfpv3_regs = start + count - 16;
4095 if (num_vfpv3_regs > 0)
4097 int start_offset = start > 16 ? start - 16 : 0;
4098 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4099 add_unwind_opcode (op, 2);
4102 /* Generate opcode for registers numbered in the range 0 .. 15. */
4103 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4104 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4105 if (num_regs_below_16 > 0)
4107 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4108 add_unwind_opcode (op, 2);
4111 unwind.frame_size += count * 8;
4115 /* Parse a directive saving VFP registers for pre-ARMv6. */
4118 s_arm_unwind_save_vfp (void)
4124 count = parse_vfp_reg_list (&input_line_pointer, ®, REGLIST_VFP_D);
4127 as_bad (_("expected register list"));
4128 ignore_rest_of_line ();
4132 demand_empty_rest_of_line ();
4137 op = 0xb8 | (count - 1);
4138 add_unwind_opcode (op, 1);
4143 op = 0xb300 | (reg << 4) | (count - 1);
4144 add_unwind_opcode (op, 2);
4146 unwind.frame_size += count * 8 + 4;
4150 /* Parse a directive saving iWMMXt data registers. */
4153 s_arm_unwind_save_mmxwr (void)
4161 if (*input_line_pointer == '{')
4162 input_line_pointer++;
4166 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4170 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4175 as_tsktsk (_("register list not in ascending order"));
4178 if (*input_line_pointer == '-')
4180 input_line_pointer++;
4181 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4184 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4187 else if (reg >= hi_reg)
4189 as_bad (_("bad register range"));
4192 for (; reg < hi_reg; reg++)
4196 while (skip_past_comma (&input_line_pointer) != FAIL);
4198 skip_past_char (&input_line_pointer, '}');
4200 demand_empty_rest_of_line ();
4202 /* Generate any deferred opcodes because we're going to be looking at
4204 flush_pending_unwind ();
4206 for (i = 0; i < 16; i++)
4208 if (mask & (1 << i))
4209 unwind.frame_size += 8;
4212 /* Attempt to combine with a previous opcode. We do this because gcc
4213 likes to output separate unwind directives for a single block of
4215 if (unwind.opcode_count > 0)
4217 i = unwind.opcodes[unwind.opcode_count - 1];
4218 if ((i & 0xf8) == 0xc0)
4221 /* Only merge if the blocks are contiguous. */
4224 if ((mask & 0xfe00) == (1 << 9))
4226 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4227 unwind.opcode_count--;
4230 else if (i == 6 && unwind.opcode_count >= 2)
4232 i = unwind.opcodes[unwind.opcode_count - 2];
4236 op = 0xffff << (reg - 1);
4238 && ((mask & op) == (1u << (reg - 1))))
4240 op = (1 << (reg + i + 1)) - 1;
4241 op &= ~((1 << reg) - 1);
4243 unwind.opcode_count -= 2;
4250 /* We want to generate opcodes in the order the registers have been
4251 saved, ie. descending order. */
4252 for (reg = 15; reg >= -1; reg--)
4254 /* Save registers in blocks. */
4256 || !(mask & (1 << reg)))
4258 /* We found an unsaved reg. Generate opcodes to save the
4265 op = 0xc0 | (hi_reg - 10);
4266 add_unwind_opcode (op, 1);
4271 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4272 add_unwind_opcode (op, 2);
4281 ignore_rest_of_line ();
4285 s_arm_unwind_save_mmxwcg (void)
4292 if (*input_line_pointer == '{')
4293 input_line_pointer++;
4295 skip_whitespace (input_line_pointer);
4299 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4303 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4309 as_tsktsk (_("register list not in ascending order"));
4312 if (*input_line_pointer == '-')
4314 input_line_pointer++;
4315 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4318 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4321 else if (reg >= hi_reg)
4323 as_bad (_("bad register range"));
4326 for (; reg < hi_reg; reg++)
4330 while (skip_past_comma (&input_line_pointer) != FAIL);
4332 skip_past_char (&input_line_pointer, '}');
4334 demand_empty_rest_of_line ();
4336 /* Generate any deferred opcodes because we're going to be looking at
4338 flush_pending_unwind ();
4340 for (reg = 0; reg < 16; reg++)
4342 if (mask & (1 << reg))
4343 unwind.frame_size += 4;
4346 add_unwind_opcode (op, 2);
4349 ignore_rest_of_line ();
4353 /* Parse an unwind_save directive.
4354 If the argument is non-zero, this is a .vsave directive. */
4357 s_arm_unwind_save (int arch_v6)
4360 struct reg_entry *reg;
4361 bfd_boolean had_brace = FALSE;
4363 if (!unwind.proc_start)
4364 as_bad (MISSING_FNSTART);
4366 /* Figure out what sort of save we have. */
4367 peek = input_line_pointer;
4375 reg = arm_reg_parse_multi (&peek);
4379 as_bad (_("register expected"));
4380 ignore_rest_of_line ();
4389 as_bad (_("FPA .unwind_save does not take a register list"));
4390 ignore_rest_of_line ();
4393 input_line_pointer = peek;
4394 s_arm_unwind_save_fpa (reg->number);
4398 s_arm_unwind_save_core ();
4403 s_arm_unwind_save_vfp_armv6 ();
4405 s_arm_unwind_save_vfp ();
4408 case REG_TYPE_MMXWR:
4409 s_arm_unwind_save_mmxwr ();
4412 case REG_TYPE_MMXWCG:
4413 s_arm_unwind_save_mmxwcg ();
4417 as_bad (_(".unwind_save does not support this kind of register"));
4418 ignore_rest_of_line ();
4423 /* Parse an unwind_movsp directive. */
4426 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4432 if (!unwind.proc_start)
4433 as_bad (MISSING_FNSTART);
4435 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4438 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4439 ignore_rest_of_line ();
4443 /* Optional constant. */
4444 if (skip_past_comma (&input_line_pointer) != FAIL)
4446 if (immediate_for_directive (&offset) == FAIL)
4452 demand_empty_rest_of_line ();
4454 if (reg == REG_SP || reg == REG_PC)
4456 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4460 if (unwind.fp_reg != REG_SP)
4461 as_bad (_("unexpected .unwind_movsp directive"));
4463 /* Generate opcode to restore the value. */
4465 add_unwind_opcode (op, 1);
4467 /* Record the information for later. */
4468 unwind.fp_reg = reg;
4469 unwind.fp_offset = unwind.frame_size - offset;
4470 unwind.sp_restored = 1;
4473 /* Parse an unwind_pad directive. */
4476 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4480 if (!unwind.proc_start)
4481 as_bad (MISSING_FNSTART);
4483 if (immediate_for_directive (&offset) == FAIL)
4488 as_bad (_("stack increment must be multiple of 4"));
4489 ignore_rest_of_line ();
4493 /* Don't generate any opcodes, just record the details for later. */
4494 unwind.frame_size += offset;
4495 unwind.pending_offset += offset;
4497 demand_empty_rest_of_line ();
4500 /* Parse an unwind_setfp directive. */
4503 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4509 if (!unwind.proc_start)
4510 as_bad (MISSING_FNSTART);
4512 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4513 if (skip_past_comma (&input_line_pointer) == FAIL)
4516 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4518 if (fp_reg == FAIL || sp_reg == FAIL)
4520 as_bad (_("expected <reg>, <reg>"));
4521 ignore_rest_of_line ();
4525 /* Optional constant. */
4526 if (skip_past_comma (&input_line_pointer) != FAIL)
4528 if (immediate_for_directive (&offset) == FAIL)
4534 demand_empty_rest_of_line ();
4536 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4538 as_bad (_("register must be either sp or set by a previous"
4539 "unwind_movsp directive"));
4543 /* Don't generate any opcodes, just record the information for later. */
4544 unwind.fp_reg = fp_reg;
4546 if (sp_reg == REG_SP)
4547 unwind.fp_offset = unwind.frame_size - offset;
4549 unwind.fp_offset -= offset;
4552 /* Parse an unwind_raw directive. */
4555 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4558 /* This is an arbitrary limit. */
4559 unsigned char op[16];
4562 if (!unwind.proc_start)
4563 as_bad (MISSING_FNSTART);
4566 if (exp.X_op == O_constant
4567 && skip_past_comma (&input_line_pointer) != FAIL)
4569 unwind.frame_size += exp.X_add_number;
4573 exp.X_op = O_illegal;
4575 if (exp.X_op != O_constant)
4577 as_bad (_("expected <offset>, <opcode>"));
4578 ignore_rest_of_line ();
4584 /* Parse the opcode. */
4589 as_bad (_("unwind opcode too long"));
4590 ignore_rest_of_line ();
4592 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4594 as_bad (_("invalid unwind opcode"));
4595 ignore_rest_of_line ();
4598 op[count++] = exp.X_add_number;
4600 /* Parse the next byte. */
4601 if (skip_past_comma (&input_line_pointer) == FAIL)
4607 /* Add the opcode bytes in reverse order. */
4609 add_unwind_opcode (op[count], 1);
4611 demand_empty_rest_of_line ();
4615 /* Parse a .eabi_attribute directive. */
4618 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4620 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
4622 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4623 attributes_set_explicitly[tag] = 1;
4626 /* Emit a tls fix for the symbol. */
4629 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4633 #ifdef md_flush_pending_output
4634 md_flush_pending_output ();
4637 #ifdef md_cons_align
4641 /* Since we're just labelling the code, there's no need to define a
4644 p = obstack_next_free (&frchain_now->frch_obstack);
4645 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4646 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4647 : BFD_RELOC_ARM_TLS_DESCSEQ);
4649 #endif /* OBJ_ELF */
4651 static void s_arm_arch (int);
4652 static void s_arm_object_arch (int);
4653 static void s_arm_cpu (int);
4654 static void s_arm_fpu (int);
4655 static void s_arm_arch_extension (int);
4660 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
4667 if (exp.X_op == O_symbol)
4668 exp.X_op = O_secrel;
4670 emit_expr (&exp, 4);
4672 while (*input_line_pointer++ == ',');
4674 input_line_pointer--;
4675 demand_empty_rest_of_line ();
4679 /* This table describes all the machine specific pseudo-ops the assembler
4680 has to support. The fields are:
4681 pseudo-op name without dot
4682 function to call to execute this pseudo-op
4683 Integer arg to pass to the function. */
4685 const pseudo_typeS md_pseudo_table[] =
4687 /* Never called because '.req' does not start a line. */
4688 { "req", s_req, 0 },
4689 /* Following two are likewise never called. */
4692 { "unreq", s_unreq, 0 },
4693 { "bss", s_bss, 0 },
4694 { "align", s_align, 0 },
4695 { "arm", s_arm, 0 },
4696 { "thumb", s_thumb, 0 },
4697 { "code", s_code, 0 },
4698 { "force_thumb", s_force_thumb, 0 },
4699 { "thumb_func", s_thumb_func, 0 },
4700 { "thumb_set", s_thumb_set, 0 },
4701 { "even", s_even, 0 },
4702 { "ltorg", s_ltorg, 0 },
4703 { "pool", s_ltorg, 0 },
4704 { "syntax", s_syntax, 0 },
4705 { "cpu", s_arm_cpu, 0 },
4706 { "arch", s_arm_arch, 0 },
4707 { "object_arch", s_arm_object_arch, 0 },
4708 { "fpu", s_arm_fpu, 0 },
4709 { "arch_extension", s_arm_arch_extension, 0 },
4711 { "word", s_arm_elf_cons, 4 },
4712 { "long", s_arm_elf_cons, 4 },
4713 { "inst.n", s_arm_elf_inst, 2 },
4714 { "inst.w", s_arm_elf_inst, 4 },
4715 { "inst", s_arm_elf_inst, 0 },
4716 { "rel31", s_arm_rel31, 0 },
4717 { "fnstart", s_arm_unwind_fnstart, 0 },
4718 { "fnend", s_arm_unwind_fnend, 0 },
4719 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4720 { "personality", s_arm_unwind_personality, 0 },
4721 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4722 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4723 { "save", s_arm_unwind_save, 0 },
4724 { "vsave", s_arm_unwind_save, 1 },
4725 { "movsp", s_arm_unwind_movsp, 0 },
4726 { "pad", s_arm_unwind_pad, 0 },
4727 { "setfp", s_arm_unwind_setfp, 0 },
4728 { "unwind_raw", s_arm_unwind_raw, 0 },
4729 { "eabi_attribute", s_arm_eabi_attribute, 0 },
4730 { "tlsdescseq", s_arm_tls_descseq, 0 },
4734 /* These are used for dwarf. */
4738 /* These are used for dwarf2. */
4739 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4740 { "loc", dwarf2_directive_loc, 0 },
4741 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
4743 { "extend", float_cons, 'x' },
4744 { "ldouble", float_cons, 'x' },
4745 { "packed", float_cons, 'p' },
4747 {"secrel32", pe_directive_secrel, 0},
4750 /* These are for compatibility with CodeComposer Studio. */
4751 {"ref", s_ccs_ref, 0},
4752 {"def", s_ccs_def, 0},
4753 {"asmfunc", s_ccs_asmfunc, 0},
4754 {"endasmfunc", s_ccs_endasmfunc, 0},
4759 /* Parser functions used exclusively in instruction operands. */
4761 /* Generic immediate-value read function for use in insn parsing.
4762 STR points to the beginning of the immediate (the leading #);
4763 VAL receives the value; if the value is outside [MIN, MAX]
4764 issue an error. PREFIX_OPT is true if the immediate prefix is
4768 parse_immediate (char **str, int *val, int min, int max,
4769 bfd_boolean prefix_opt)
4772 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4773 if (exp.X_op != O_constant)
4775 inst.error = _("constant expression required");
4779 if (exp.X_add_number < min || exp.X_add_number > max)
4781 inst.error = _("immediate value out of range");
4785 *val = exp.X_add_number;
4789 /* Less-generic immediate-value read function with the possibility of loading a
4790 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4791 instructions. Puts the result directly in inst.operands[i]. */
4794 parse_big_immediate (char **str, int i, expressionS *in_exp,
4795 bfd_boolean allow_symbol_p)
4798 expressionS *exp_p = in_exp ? in_exp : &exp;
4801 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
4803 if (exp_p->X_op == O_constant)
4805 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
4806 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4807 O_constant. We have to be careful not to break compilation for
4808 32-bit X_add_number, though. */
4809 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
4811 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4812 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4814 inst.operands[i].regisimm = 1;
4817 else if (exp_p->X_op == O_big
4818 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
4820 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
4822 /* Bignums have their least significant bits in
4823 generic_bignum[0]. Make sure we put 32 bits in imm and
4824 32 bits in reg, in a (hopefully) portable way. */
4825 gas_assert (parts != 0);
4827 /* Make sure that the number is not too big.
4828 PR 11972: Bignums can now be sign-extended to the
4829 size of a .octa so check that the out of range bits
4830 are all zero or all one. */
4831 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
4833 LITTLENUM_TYPE m = -1;
4835 if (generic_bignum[parts * 2] != 0
4836 && generic_bignum[parts * 2] != m)
4839 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
4840 if (generic_bignum[j] != generic_bignum[j-1])
4844 inst.operands[i].imm = 0;
4845 for (j = 0; j < parts; j++, idx++)
4846 inst.operands[i].imm |= generic_bignum[idx]
4847 << (LITTLENUM_NUMBER_OF_BITS * j);
4848 inst.operands[i].reg = 0;
4849 for (j = 0; j < parts; j++, idx++)
4850 inst.operands[i].reg |= generic_bignum[idx]
4851 << (LITTLENUM_NUMBER_OF_BITS * j);
4852 inst.operands[i].regisimm = 1;
4854 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
4862 /* Returns the pseudo-register number of an FPA immediate constant,
4863 or FAIL if there isn't a valid constant here. */
4866 parse_fpa_immediate (char ** str)
4868 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4874 /* First try and match exact strings, this is to guarantee
4875 that some formats will work even for cross assembly. */
4877 for (i = 0; fp_const[i]; i++)
4879 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
4883 *str += strlen (fp_const[i]);
4884 if (is_end_of_line[(unsigned char) **str])
4890 /* Just because we didn't get a match doesn't mean that the constant
4891 isn't valid, just that it is in a format that we don't
4892 automatically recognize. Try parsing it with the standard
4893 expression routines. */
4895 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
4897 /* Look for a raw floating point number. */
4898 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4899 && is_end_of_line[(unsigned char) *save_in])
4901 for (i = 0; i < NUM_FLOAT_VALS; i++)
4903 for (j = 0; j < MAX_LITTLENUMS; j++)
4905 if (words[j] != fp_values[i][j])
4909 if (j == MAX_LITTLENUMS)
4917 /* Try and parse a more complex expression, this will probably fail
4918 unless the code uses a floating point prefix (eg "0f"). */
4919 save_in = input_line_pointer;
4920 input_line_pointer = *str;
4921 if (expression (&exp) == absolute_section
4922 && exp.X_op == O_big
4923 && exp.X_add_number < 0)
4925 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4927 #define X_PRECISION 5
4928 #define E_PRECISION 15L
4929 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
4931 for (i = 0; i < NUM_FLOAT_VALS; i++)
4933 for (j = 0; j < MAX_LITTLENUMS; j++)
4935 if (words[j] != fp_values[i][j])
4939 if (j == MAX_LITTLENUMS)
4941 *str = input_line_pointer;
4942 input_line_pointer = save_in;
4949 *str = input_line_pointer;
4950 input_line_pointer = save_in;
4951 inst.error = _("invalid FPA immediate expression");
4955 /* Returns 1 if a number has "quarter-precision" float format
4956 0baBbbbbbc defgh000 00000000 00000000. */
4959 is_quarter_float (unsigned imm)
4961 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4962 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4966 /* Detect the presence of a floating point or integer zero constant,
4970 parse_ifimm_zero (char **in)
4974 if (!is_immediate_prefix (**in))
4979 /* Accept #0x0 as a synonym for #0. */
4980 if (strncmp (*in, "0x", 2) == 0)
4983 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
4988 error_code = atof_generic (in, ".", EXP_CHARS,
4989 &generic_floating_point_number);
4992 && generic_floating_point_number.sign == '+'
4993 && (generic_floating_point_number.low
4994 > generic_floating_point_number.leader))
5000 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5001 0baBbbbbbc defgh000 00000000 00000000.
5002 The zero and minus-zero cases need special handling, since they can't be
5003 encoded in the "quarter-precision" float format, but can nonetheless be
5004 loaded as integer constants. */
5007 parse_qfloat_immediate (char **ccp, int *immed)
5011 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5012 int found_fpchar = 0;
5014 skip_past_char (&str, '#');
5016 /* We must not accidentally parse an integer as a floating-point number. Make
5017 sure that the value we parse is not an integer by checking for special
5018 characters '.' or 'e'.
5019 FIXME: This is a horrible hack, but doing better is tricky because type
5020 information isn't in a very usable state at parse time. */
5022 skip_whitespace (fpnum);
5024 if (strncmp (fpnum, "0x", 2) == 0)
5028 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5029 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5039 if ((str = atof_ieee (str, 's', words)) != NULL)
5041 unsigned fpword = 0;
5044 /* Our FP word must be 32 bits (single-precision FP). */
5045 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5047 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5051 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5064 /* Shift operands. */
5067 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5070 struct asm_shift_name
5073 enum shift_kind kind;
5076 /* Third argument to parse_shift. */
5077 enum parse_shift_mode
5079 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5080 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5081 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5082 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5083 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5086 /* Parse a <shift> specifier on an ARM data processing instruction.
5087 This has three forms:
5089 (LSL|LSR|ASL|ASR|ROR) Rs
5090 (LSL|LSR|ASL|ASR|ROR) #imm
5093 Note that ASL is assimilated to LSL in the instruction encoding, and
5094 RRX to ROR #0 (which cannot be written as such). */
5097 parse_shift (char **str, int i, enum parse_shift_mode mode)
5099 const struct asm_shift_name *shift_name;
5100 enum shift_kind shift;
5105 for (p = *str; ISALPHA (*p); p++)
5110 inst.error = _("shift expression expected");
5114 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
5117 if (shift_name == NULL)
5119 inst.error = _("shift expression expected");
5123 shift = shift_name->kind;
5127 case NO_SHIFT_RESTRICT:
5128 case SHIFT_IMMEDIATE: break;
5130 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5131 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5133 inst.error = _("'LSL' or 'ASR' required");
5138 case SHIFT_LSL_IMMEDIATE:
5139 if (shift != SHIFT_LSL)
5141 inst.error = _("'LSL' required");
5146 case SHIFT_ASR_IMMEDIATE:
5147 if (shift != SHIFT_ASR)
5149 inst.error = _("'ASR' required");
5157 if (shift != SHIFT_RRX)
5159 /* Whitespace can appear here if the next thing is a bare digit. */
5160 skip_whitespace (p);
5162 if (mode == NO_SHIFT_RESTRICT
5163 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5165 inst.operands[i].imm = reg;
5166 inst.operands[i].immisreg = 1;
5168 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5171 inst.operands[i].shift_kind = shift;
5172 inst.operands[i].shifted = 1;
5177 /* Parse a <shifter_operand> for an ARM data processing instruction:
5180 #<immediate>, <rotate>
5184 where <shift> is defined by parse_shift above, and <rotate> is a
5185 multiple of 2 between 0 and 30. Validation of immediate operands
5186 is deferred to md_apply_fix. */
5189 parse_shifter_operand (char **str, int i)
5194 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5196 inst.operands[i].reg = value;
5197 inst.operands[i].isreg = 1;
5199 /* parse_shift will override this if appropriate */
5200 inst.reloc.exp.X_op = O_constant;
5201 inst.reloc.exp.X_add_number = 0;
5203 if (skip_past_comma (str) == FAIL)
5206 /* Shift operation on register. */
5207 return parse_shift (str, i, NO_SHIFT_RESTRICT);
5210 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5213 if (skip_past_comma (str) == SUCCESS)
5215 /* #x, y -- ie explicit rotation by Y. */
5216 if (my_get_expression (&exp, str, GE_NO_PREFIX))
5219 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
5221 inst.error = _("constant expression expected");
5225 value = exp.X_add_number;
5226 if (value < 0 || value > 30 || value % 2 != 0)
5228 inst.error = _("invalid rotation");
5231 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5233 inst.error = _("invalid constant");
5237 /* Encode as specified. */
5238 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5242 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5243 inst.reloc.pc_rel = 0;
5247 /* Group relocation information. Each entry in the table contains the
5248 textual name of the relocation as may appear in assembler source
5249 and must end with a colon.
5250 Along with this textual name are the relocation codes to be used if
5251 the corresponding instruction is an ALU instruction (ADD or SUB only),
5252 an LDR, an LDRS, or an LDC. */
5254 struct group_reloc_table_entry
5265 /* Varieties of non-ALU group relocation. */
5272 static struct group_reloc_table_entry group_reloc_table[] =
5273 { /* Program counter relative: */
5275 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5280 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5281 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5282 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5283 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5285 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5290 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5291 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5292 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5293 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5295 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5296 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5297 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5298 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5299 /* Section base relative */
5301 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5306 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5307 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5308 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5309 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5311 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5316 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5317 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5318 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5319 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5321 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5322 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5323 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5324 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5326 /* Given the address of a pointer pointing to the textual name of a group
5327 relocation as may appear in assembler source, attempt to find its details
5328 in group_reloc_table. The pointer will be updated to the character after
5329 the trailing colon. On failure, FAIL will be returned; SUCCESS
5330 otherwise. On success, *entry will be updated to point at the relevant
5331 group_reloc_table entry. */
5334 find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5337 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5339 int length = strlen (group_reloc_table[i].name);
5341 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5342 && (*str)[length] == ':')
5344 *out = &group_reloc_table[i];
5345 *str += (length + 1);
5353 /* Parse a <shifter_operand> for an ARM data processing instruction
5354 (as for parse_shifter_operand) where group relocations are allowed:
5357 #<immediate>, <rotate>
5358 #:<group_reloc>:<expression>
5362 where <group_reloc> is one of the strings defined in group_reloc_table.
5363 The hashes are optional.
5365 Everything else is as for parse_shifter_operand. */
5367 static parse_operand_result
5368 parse_shifter_operand_group_reloc (char **str, int i)
5370 /* Determine if we have the sequence of characters #: or just :
5371 coming next. If we do, then we check for a group relocation.
5372 If we don't, punt the whole lot to parse_shifter_operand. */
5374 if (((*str)[0] == '#' && (*str)[1] == ':')
5375 || (*str)[0] == ':')
5377 struct group_reloc_table_entry *entry;
5379 if ((*str)[0] == '#')
5384 /* Try to parse a group relocation. Anything else is an error. */
5385 if (find_group_reloc_table_entry (str, &entry) == FAIL)
5387 inst.error = _("unknown group relocation");
5388 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5391 /* We now have the group relocation table entry corresponding to
5392 the name in the assembler source. Next, we parse the expression. */
5393 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
5394 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5396 /* Record the relocation type (always the ALU variant here). */
5397 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
5398 gas_assert (inst.reloc.type != 0);
5400 return PARSE_OPERAND_SUCCESS;
5403 return parse_shifter_operand (str, i) == SUCCESS
5404 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5406 /* Never reached. */
5409 /* Parse a Neon alignment expression. Information is written to
5410 inst.operands[i]. We assume the initial ':' has been skipped.
5412 align .imm = align << 8, .immisalign=1, .preind=0 */
5413 static parse_operand_result
5414 parse_neon_alignment (char **str, int i)
5419 my_get_expression (&exp, &p, GE_NO_PREFIX);
5421 if (exp.X_op != O_constant)
5423 inst.error = _("alignment must be constant");
5424 return PARSE_OPERAND_FAIL;
5427 inst.operands[i].imm = exp.X_add_number << 8;
5428 inst.operands[i].immisalign = 1;
5429 /* Alignments are not pre-indexes. */
5430 inst.operands[i].preind = 0;
5433 return PARSE_OPERAND_SUCCESS;
5436 /* Parse all forms of an ARM address expression. Information is written
5437 to inst.operands[i] and/or inst.reloc.
5439 Preindexed addressing (.preind=1):
5441 [Rn, #offset] .reg=Rn .reloc.exp=offset
5442 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5443 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5444 .shift_kind=shift .reloc.exp=shift_imm
5446 These three may have a trailing ! which causes .writeback to be set also.
5448 Postindexed addressing (.postind=1, .writeback=1):
5450 [Rn], #offset .reg=Rn .reloc.exp=offset
5451 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5452 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5453 .shift_kind=shift .reloc.exp=shift_imm
5455 Unindexed addressing (.preind=0, .postind=0):
5457 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5461 [Rn]{!} shorthand for [Rn,#0]{!}
5462 =immediate .isreg=0 .reloc.exp=immediate
5463 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5465 It is the caller's responsibility to check for addressing modes not
5466 supported by the instruction, and to set inst.reloc.type. */
5468 static parse_operand_result
5469 parse_address_main (char **str, int i, int group_relocations,
5470 group_reloc_type group_type)
5475 if (skip_past_char (&p, '[') == FAIL)
5477 if (skip_past_char (&p, '=') == FAIL)
5479 /* Bare address - translate to PC-relative offset. */
5480 inst.reloc.pc_rel = 1;
5481 inst.operands[i].reg = REG_PC;
5482 inst.operands[i].isreg = 1;
5483 inst.operands[i].preind = 1;
5485 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5486 return PARSE_OPERAND_FAIL;
5488 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5489 /*allow_symbol_p=*/TRUE))
5490 return PARSE_OPERAND_FAIL;
5493 return PARSE_OPERAND_SUCCESS;
5496 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5497 skip_whitespace (p);
5499 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5501 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5502 return PARSE_OPERAND_FAIL;
5504 inst.operands[i].reg = reg;
5505 inst.operands[i].isreg = 1;
5507 if (skip_past_comma (&p) == SUCCESS)
5509 inst.operands[i].preind = 1;
5512 else if (*p == '-') p++, inst.operands[i].negative = 1;
5514 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5516 inst.operands[i].imm = reg;
5517 inst.operands[i].immisreg = 1;
5519 if (skip_past_comma (&p) == SUCCESS)
5520 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5521 return PARSE_OPERAND_FAIL;
5523 else if (skip_past_char (&p, ':') == SUCCESS)
5525 /* FIXME: '@' should be used here, but it's filtered out by generic
5526 code before we get to see it here. This may be subject to
5528 parse_operand_result result = parse_neon_alignment (&p, i);
5530 if (result != PARSE_OPERAND_SUCCESS)
5535 if (inst.operands[i].negative)
5537 inst.operands[i].negative = 0;
5541 if (group_relocations
5542 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
5544 struct group_reloc_table_entry *entry;
5546 /* Skip over the #: or : sequence. */
5552 /* Try to parse a group relocation. Anything else is an
5554 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5556 inst.error = _("unknown group relocation");
5557 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5560 /* We now have the group relocation table entry corresponding to
5561 the name in the assembler source. Next, we parse the
5563 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5566 /* Record the relocation type. */
5570 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5574 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5578 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5585 if (inst.reloc.type == 0)
5587 inst.error = _("this group relocation is not allowed on this instruction");
5588 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5594 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5595 return PARSE_OPERAND_FAIL;
5596 /* If the offset is 0, find out if it's a +0 or -0. */
5597 if (inst.reloc.exp.X_op == O_constant
5598 && inst.reloc.exp.X_add_number == 0)
5600 skip_whitespace (q);
5604 skip_whitespace (q);
5607 inst.operands[i].negative = 1;
5612 else if (skip_past_char (&p, ':') == SUCCESS)
5614 /* FIXME: '@' should be used here, but it's filtered out by generic code
5615 before we get to see it here. This may be subject to change. */
5616 parse_operand_result result = parse_neon_alignment (&p, i);
5618 if (result != PARSE_OPERAND_SUCCESS)
5622 if (skip_past_char (&p, ']') == FAIL)
5624 inst.error = _("']' expected");
5625 return PARSE_OPERAND_FAIL;
5628 if (skip_past_char (&p, '!') == SUCCESS)
5629 inst.operands[i].writeback = 1;
5631 else if (skip_past_comma (&p) == SUCCESS)
5633 if (skip_past_char (&p, '{') == SUCCESS)
5635 /* [Rn], {expr} - unindexed, with option */
5636 if (parse_immediate (&p, &inst.operands[i].imm,
5637 0, 255, TRUE) == FAIL)
5638 return PARSE_OPERAND_FAIL;
5640 if (skip_past_char (&p, '}') == FAIL)
5642 inst.error = _("'}' expected at end of 'option' field");
5643 return PARSE_OPERAND_FAIL;
5645 if (inst.operands[i].preind)
5647 inst.error = _("cannot combine index with option");
5648 return PARSE_OPERAND_FAIL;
5651 return PARSE_OPERAND_SUCCESS;
5655 inst.operands[i].postind = 1;
5656 inst.operands[i].writeback = 1;
5658 if (inst.operands[i].preind)
5660 inst.error = _("cannot combine pre- and post-indexing");
5661 return PARSE_OPERAND_FAIL;
5665 else if (*p == '-') p++, inst.operands[i].negative = 1;
5667 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5669 /* We might be using the immediate for alignment already. If we
5670 are, OR the register number into the low-order bits. */
5671 if (inst.operands[i].immisalign)
5672 inst.operands[i].imm |= reg;
5674 inst.operands[i].imm = reg;
5675 inst.operands[i].immisreg = 1;
5677 if (skip_past_comma (&p) == SUCCESS)
5678 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
5679 return PARSE_OPERAND_FAIL;
5684 if (inst.operands[i].negative)
5686 inst.operands[i].negative = 0;
5689 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5690 return PARSE_OPERAND_FAIL;
5691 /* If the offset is 0, find out if it's a +0 or -0. */
5692 if (inst.reloc.exp.X_op == O_constant
5693 && inst.reloc.exp.X_add_number == 0)
5695 skip_whitespace (q);
5699 skip_whitespace (q);
5702 inst.operands[i].negative = 1;
5708 /* If at this point neither .preind nor .postind is set, we have a
5709 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5710 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5712 inst.operands[i].preind = 1;
5713 inst.reloc.exp.X_op = O_constant;
5714 inst.reloc.exp.X_add_number = 0;
5717 return PARSE_OPERAND_SUCCESS;
5721 parse_address (char **str, int i)
5723 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
5727 static parse_operand_result
5728 parse_address_group_reloc (char **str, int i, group_reloc_type type)
5730 return parse_address_main (str, i, 1, type);
5733 /* Parse an operand for a MOVW or MOVT instruction. */
5735 parse_half (char **str)
5740 skip_past_char (&p, '#');
5741 if (strncasecmp (p, ":lower16:", 9) == 0)
5742 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5743 else if (strncasecmp (p, ":upper16:", 9) == 0)
5744 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5746 if (inst.reloc.type != BFD_RELOC_UNUSED)
5749 skip_whitespace (p);
5752 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5755 if (inst.reloc.type == BFD_RELOC_UNUSED)
5757 if (inst.reloc.exp.X_op != O_constant)
5759 inst.error = _("constant expression expected");
5762 if (inst.reloc.exp.X_add_number < 0
5763 || inst.reloc.exp.X_add_number > 0xffff)
5765 inst.error = _("immediate value out of range");
5773 /* Miscellaneous. */
5775 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5776 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5778 parse_psr (char **str, bfd_boolean lhs)
5781 unsigned long psr_field;
5782 const struct asm_psr *psr;
5784 bfd_boolean is_apsr = FALSE;
5785 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
5787 /* PR gas/12698: If the user has specified -march=all then m_profile will
5788 be TRUE, but we want to ignore it in this case as we are building for any
5789 CPU type, including non-m variants. */
5790 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
5793 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5794 feature for ease of use and backwards compatibility. */
5796 if (strncasecmp (p, "SPSR", 4) == 0)
5799 goto unsupported_psr;
5801 psr_field = SPSR_BIT;
5803 else if (strncasecmp (p, "CPSR", 4) == 0)
5806 goto unsupported_psr;
5810 else if (strncasecmp (p, "APSR", 4) == 0)
5812 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5813 and ARMv7-R architecture CPUs. */
5822 while (ISALNUM (*p) || *p == '_');
5824 if (strncasecmp (start, "iapsr", 5) == 0
5825 || strncasecmp (start, "eapsr", 5) == 0
5826 || strncasecmp (start, "xpsr", 4) == 0
5827 || strncasecmp (start, "psr", 3) == 0)
5828 p = start + strcspn (start, "rR") + 1;
5830 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
5836 /* If APSR is being written, a bitfield may be specified. Note that
5837 APSR itself is handled above. */
5838 if (psr->field <= 3)
5840 psr_field = psr->field;
5846 /* M-profile MSR instructions have the mask field set to "10", except
5847 *PSR variants which modify APSR, which may use a different mask (and
5848 have been handled already). Do that by setting the PSR_f field
5850 return psr->field | (lhs ? PSR_f : 0);
5853 goto unsupported_psr;
5859 /* A suffix follows. */
5865 while (ISALNUM (*p) || *p == '_');
5869 /* APSR uses a notation for bits, rather than fields. */
5870 unsigned int nzcvq_bits = 0;
5871 unsigned int g_bit = 0;
5874 for (bit = start; bit != p; bit++)
5876 switch (TOLOWER (*bit))
5879 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5883 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5887 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5891 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5895 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5899 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5903 inst.error = _("unexpected bit specified after APSR");
5908 if (nzcvq_bits == 0x1f)
5913 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
5915 inst.error = _("selected processor does not "
5916 "support DSP extension");
5923 if ((nzcvq_bits & 0x20) != 0
5924 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5925 || (g_bit & 0x2) != 0)
5927 inst.error = _("bad bitmask specified after APSR");
5933 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
5938 psr_field |= psr->field;
5944 goto error; /* Garbage after "[CS]PSR". */
5946 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5947 is deprecated, but allow it anyway. */
5951 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5954 else if (!m_profile)
5955 /* These bits are never right for M-profile devices: don't set them
5956 (only code paths which read/write APSR reach here). */
5957 psr_field |= (PSR_c | PSR_f);
5963 inst.error = _("selected processor does not support requested special "
5964 "purpose register");
5968 inst.error = _("flag for {c}psr instruction expected");
5972 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5973 value suitable for splatting into the AIF field of the instruction. */
5976 parse_cps_flags (char **str)
5985 case '\0': case ',':
5988 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5989 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5990 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
5993 inst.error = _("unrecognized CPS flag");
5998 if (saw_a_flag == 0)
6000 inst.error = _("missing CPS flags");
6008 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6009 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6012 parse_endian_specifier (char **str)
6017 if (strncasecmp (s, "BE", 2))
6019 else if (strncasecmp (s, "LE", 2))
6023 inst.error = _("valid endian specifiers are be or le");
6027 if (ISALNUM (s[2]) || s[2] == '_')
6029 inst.error = _("valid endian specifiers are be or le");
6034 return little_endian;
6037 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6038 value suitable for poking into the rotate field of an sxt or sxta
6039 instruction, or FAIL on error. */
6042 parse_ror (char **str)
6047 if (strncasecmp (s, "ROR", 3) == 0)
6051 inst.error = _("missing rotation field after comma");
6055 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6060 case 0: *str = s; return 0x0;
6061 case 8: *str = s; return 0x1;
6062 case 16: *str = s; return 0x2;
6063 case 24: *str = s; return 0x3;
6066 inst.error = _("rotation can only be 0, 8, 16, or 24");
6071 /* Parse a conditional code (from conds[] below). The value returned is in the
6072 range 0 .. 14, or FAIL. */
6074 parse_cond (char **str)
6077 const struct asm_cond *c;
6079 /* Condition codes are always 2 characters, so matching up to
6080 3 characters is sufficient. */
6085 while (ISALPHA (*q) && n < 3)
6087 cond[n] = TOLOWER (*q);
6092 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
6095 inst.error = _("condition required");
6103 /* If the given feature available in the selected CPU, mark it as used.
6104 Returns TRUE iff feature is available. */
6106 mark_feature_used (const arm_feature_set *feature)
6108 /* Ensure the option is valid on the current architecture. */
6109 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6112 /* Add the appropriate architecture feature for the barrier option used.
6115 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6117 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6122 /* Parse an option for a barrier instruction. Returns the encoding for the
6125 parse_barrier (char **str)
6128 const struct asm_barrier_opt *o;
6131 while (ISALPHA (*q))
6134 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
6139 if (!mark_feature_used (&o->arch))
6146 /* Parse the operands of a table branch instruction. Similar to a memory
6149 parse_tb (char **str)
6154 if (skip_past_char (&p, '[') == FAIL)
6156 inst.error = _("'[' expected");
6160 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6162 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6165 inst.operands[0].reg = reg;
6167 if (skip_past_comma (&p) == FAIL)
6169 inst.error = _("',' expected");
6173 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6175 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6178 inst.operands[0].imm = reg;
6180 if (skip_past_comma (&p) == SUCCESS)
6182 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6184 if (inst.reloc.exp.X_add_number != 1)
6186 inst.error = _("invalid shift");
6189 inst.operands[0].shifted = 1;
6192 if (skip_past_char (&p, ']') == FAIL)
6194 inst.error = _("']' expected");
6201 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6202 information on the types the operands can take and how they are encoded.
6203 Up to four operands may be read; this function handles setting the
6204 ".present" field for each read operand itself.
6205 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6206 else returns FAIL. */
6209 parse_neon_mov (char **str, int *which_operand)
6211 int i = *which_operand, val;
6212 enum arm_reg_type rtype;
6214 struct neon_type_el optype;
6216 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6218 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6219 inst.operands[i].reg = val;
6220 inst.operands[i].isscalar = 1;
6221 inst.operands[i].vectype = optype;
6222 inst.operands[i++].present = 1;
6224 if (skip_past_comma (&ptr) == FAIL)
6227 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6230 inst.operands[i].reg = val;
6231 inst.operands[i].isreg = 1;
6232 inst.operands[i].present = 1;
6234 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6237 /* Cases 0, 1, 2, 3, 5 (D only). */
6238 if (skip_past_comma (&ptr) == FAIL)
6241 inst.operands[i].reg = val;
6242 inst.operands[i].isreg = 1;
6243 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6244 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6245 inst.operands[i].isvec = 1;
6246 inst.operands[i].vectype = optype;
6247 inst.operands[i++].present = 1;
6249 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6251 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6252 Case 13: VMOV <Sd>, <Rm> */
6253 inst.operands[i].reg = val;
6254 inst.operands[i].isreg = 1;
6255 inst.operands[i].present = 1;
6257 if (rtype == REG_TYPE_NQ)
6259 first_error (_("can't use Neon quad register here"));
6262 else if (rtype != REG_TYPE_VFS)
6265 if (skip_past_comma (&ptr) == FAIL)
6267 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6269 inst.operands[i].reg = val;
6270 inst.operands[i].isreg = 1;
6271 inst.operands[i].present = 1;
6274 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6277 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6278 Case 1: VMOV<c><q> <Dd>, <Dm>
6279 Case 8: VMOV.F32 <Sd>, <Sm>
6280 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6282 inst.operands[i].reg = val;
6283 inst.operands[i].isreg = 1;
6284 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6285 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6286 inst.operands[i].isvec = 1;
6287 inst.operands[i].vectype = optype;
6288 inst.operands[i].present = 1;
6290 if (skip_past_comma (&ptr) == SUCCESS)
6295 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6298 inst.operands[i].reg = val;
6299 inst.operands[i].isreg = 1;
6300 inst.operands[i++].present = 1;
6302 if (skip_past_comma (&ptr) == FAIL)
6305 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6308 inst.operands[i].reg = val;
6309 inst.operands[i].isreg = 1;
6310 inst.operands[i].present = 1;
6313 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6316 Case 10: VMOV.F32 <Sd>, #<imm>
6317 Case 11: VMOV.F64 <Dd>, #<imm> */
6318 inst.operands[i].immisfloat = 1;
6319 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6321 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6322 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6326 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6330 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6333 inst.operands[i].reg = val;
6334 inst.operands[i].isreg = 1;
6335 inst.operands[i++].present = 1;
6337 if (skip_past_comma (&ptr) == FAIL)
6340 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
6342 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6343 inst.operands[i].reg = val;
6344 inst.operands[i].isscalar = 1;
6345 inst.operands[i].present = 1;
6346 inst.operands[i].vectype = optype;
6348 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6350 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6351 inst.operands[i].reg = val;
6352 inst.operands[i].isreg = 1;
6353 inst.operands[i++].present = 1;
6355 if (skip_past_comma (&ptr) == FAIL)
6358 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6361 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6365 inst.operands[i].reg = val;
6366 inst.operands[i].isreg = 1;
6367 inst.operands[i].isvec = 1;
6368 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6369 inst.operands[i].vectype = optype;
6370 inst.operands[i].present = 1;
6372 if (rtype == REG_TYPE_VFS)
6376 if (skip_past_comma (&ptr) == FAIL)
6378 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6381 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6384 inst.operands[i].reg = val;
6385 inst.operands[i].isreg = 1;
6386 inst.operands[i].isvec = 1;
6387 inst.operands[i].issingle = 1;
6388 inst.operands[i].vectype = optype;
6389 inst.operands[i].present = 1;
6392 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
6396 inst.operands[i].reg = val;
6397 inst.operands[i].isreg = 1;
6398 inst.operands[i].isvec = 1;
6399 inst.operands[i].issingle = 1;
6400 inst.operands[i].vectype = optype;
6401 inst.operands[i].present = 1;
6406 first_error (_("parse error"));
6410 /* Successfully parsed the operands. Update args. */
6416 first_error (_("expected comma"));
6420 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
6424 /* Use this macro when the operand constraints are different
6425 for ARM and THUMB (e.g. ldrd). */
6426 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6427 ((arm_operand) | ((thumb_operand) << 16))
6429 /* Matcher codes for parse_operands. */
6430 enum operand_parse_code
6432 OP_stop, /* end of line */
6434 OP_RR, /* ARM register */
6435 OP_RRnpc, /* ARM register, not r15 */
6436 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6437 OP_RRnpcb, /* ARM register, not r15, in square brackets */
6438 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
6439 optional trailing ! */
6440 OP_RRw, /* ARM register, not r15, optional trailing ! */
6441 OP_RCP, /* Coprocessor number */
6442 OP_RCN, /* Coprocessor register */
6443 OP_RF, /* FPA register */
6444 OP_RVS, /* VFP single precision register */
6445 OP_RVD, /* VFP double precision register (0..15) */
6446 OP_RND, /* Neon double precision register (0..31) */
6447 OP_RNQ, /* Neon quad precision register */
6448 OP_RVSD, /* VFP single or double precision register */
6449 OP_RNDQ, /* Neon double or quad precision register */
6450 OP_RNSDQ, /* Neon single, double or quad precision register */
6451 OP_RNSC, /* Neon scalar D[X] */
6452 OP_RVC, /* VFP control register */
6453 OP_RMF, /* Maverick F register */
6454 OP_RMD, /* Maverick D register */
6455 OP_RMFX, /* Maverick FX register */
6456 OP_RMDX, /* Maverick DX register */
6457 OP_RMAX, /* Maverick AX register */
6458 OP_RMDS, /* Maverick DSPSC register */
6459 OP_RIWR, /* iWMMXt wR register */
6460 OP_RIWC, /* iWMMXt wC register */
6461 OP_RIWG, /* iWMMXt wCG register */
6462 OP_RXA, /* XScale accumulator register */
6464 OP_REGLST, /* ARM register list */
6465 OP_VRSLST, /* VFP single-precision register list */
6466 OP_VRDLST, /* VFP double-precision register list */
6467 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
6468 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6469 OP_NSTRLST, /* Neon element/structure list */
6471 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
6472 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
6473 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
6474 OP_RR_RNSC, /* ARM reg or Neon scalar. */
6475 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
6476 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6477 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6478 OP_VMOV, /* Neon VMOV operands. */
6479 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6480 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
6481 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6483 OP_I0, /* immediate zero */
6484 OP_I7, /* immediate value 0 .. 7 */
6485 OP_I15, /* 0 .. 15 */
6486 OP_I16, /* 1 .. 16 */
6487 OP_I16z, /* 0 .. 16 */
6488 OP_I31, /* 0 .. 31 */
6489 OP_I31w, /* 0 .. 31, optional trailing ! */
6490 OP_I32, /* 1 .. 32 */
6491 OP_I32z, /* 0 .. 32 */
6492 OP_I63, /* 0 .. 63 */
6493 OP_I63s, /* -64 .. 63 */
6494 OP_I64, /* 1 .. 64 */
6495 OP_I64z, /* 0 .. 64 */
6496 OP_I255, /* 0 .. 255 */
6498 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6499 OP_I7b, /* 0 .. 7 */
6500 OP_I15b, /* 0 .. 15 */
6501 OP_I31b, /* 0 .. 31 */
6503 OP_SH, /* shifter operand */
6504 OP_SHG, /* shifter operand with possible group relocation */
6505 OP_ADDR, /* Memory address expression (any mode) */
6506 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6507 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6508 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
6509 OP_EXP, /* arbitrary expression */
6510 OP_EXPi, /* same, with optional immediate prefix */
6511 OP_EXPr, /* same, with optional relocation suffix */
6512 OP_HALF, /* 0 .. 65535 or low/high reloc. */
6514 OP_CPSF, /* CPS flags */
6515 OP_ENDI, /* Endianness specifier */
6516 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6517 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
6518 OP_COND, /* conditional code */
6519 OP_TB, /* Table branch. */
6521 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6523 OP_RRnpc_I0, /* ARM register or literal 0 */
6524 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6525 OP_RR_EXi, /* ARM register or expression with imm prefix */
6526 OP_RF_IF, /* FPA register or immediate */
6527 OP_RIWR_RIWC, /* iWMMXt R or C reg */
6528 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
6530 /* Optional operands. */
6531 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6532 OP_oI31b, /* 0 .. 31 */
6533 OP_oI32b, /* 1 .. 32 */
6534 OP_oI32z, /* 0 .. 32 */
6535 OP_oIffffb, /* 0 .. 65535 */
6536 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6538 OP_oRR, /* ARM register */
6539 OP_oRRnpc, /* ARM register, not the PC */
6540 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6541 OP_oRRw, /* ARM register, not r15, optional trailing ! */
6542 OP_oRND, /* Optional Neon double precision register */
6543 OP_oRNQ, /* Optional Neon quad precision register */
6544 OP_oRNDQ, /* Optional Neon double or quad precision register */
6545 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
6546 OP_oSHll, /* LSL immediate */
6547 OP_oSHar, /* ASR immediate */
6548 OP_oSHllar, /* LSL or ASR immediate */
6549 OP_oROR, /* ROR 0/8/16/24 */
6550 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
6552 /* Some pre-defined mixed (ARM/THUMB) operands. */
6553 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6554 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6555 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6557 OP_FIRST_OPTIONAL = OP_oI7b
6560 /* Generic instruction operand parser. This does no encoding and no
6561 semantic validation; it merely squirrels values away in the inst
6562 structure. Returns SUCCESS or FAIL depending on whether the
6563 specified grammar matched. */
6565 parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
6567 unsigned const int *upat = pattern;
6568 char *backtrack_pos = 0;
6569 const char *backtrack_error = 0;
6570 int i, val = 0, backtrack_index = 0;
6571 enum arm_reg_type rtype;
6572 parse_operand_result result;
6573 unsigned int op_parse_code;
6575 #define po_char_or_fail(chr) \
6578 if (skip_past_char (&str, chr) == FAIL) \
6583 #define po_reg_or_fail(regtype) \
6586 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6587 & inst.operands[i].vectype); \
6590 first_error (_(reg_expected_msgs[regtype])); \
6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6598 || rtype == REG_TYPE_VFD \
6599 || rtype == REG_TYPE_NQ); \
6603 #define po_reg_or_goto(regtype, label) \
6606 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6607 & inst.operands[i].vectype); \
6611 inst.operands[i].reg = val; \
6612 inst.operands[i].isreg = 1; \
6613 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6614 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6615 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6616 || rtype == REG_TYPE_VFD \
6617 || rtype == REG_TYPE_NQ); \
6621 #define po_imm_or_fail(min, max, popt) \
6624 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6626 inst.operands[i].imm = val; \
6630 #define po_scalar_or_goto(elsz, label) \
6633 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6636 inst.operands[i].reg = val; \
6637 inst.operands[i].isscalar = 1; \
6641 #define po_misc_or_fail(expr) \
6649 #define po_misc_or_fail_no_backtrack(expr) \
6653 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6654 backtrack_pos = 0; \
6655 if (result != PARSE_OPERAND_SUCCESS) \
6660 #define po_barrier_or_imm(str) \
6663 val = parse_barrier (&str); \
6664 if (val == FAIL && ! ISALPHA (*str)) \
6667 /* ISB can only take SY as an option. */ \
6668 || ((inst.instruction & 0xf0) == 0x60 \
6671 inst.error = _("invalid barrier type"); \
6672 backtrack_pos = 0; \
6678 skip_whitespace (str);
6680 for (i = 0; upat[i] != OP_stop; i++)
6682 op_parse_code = upat[i];
6683 if (op_parse_code >= 1<<16)
6684 op_parse_code = thumb ? (op_parse_code >> 16)
6685 : (op_parse_code & ((1<<16)-1));
6687 if (op_parse_code >= OP_FIRST_OPTIONAL)
6689 /* Remember where we are in case we need to backtrack. */
6690 gas_assert (!backtrack_pos);
6691 backtrack_pos = str;
6692 backtrack_error = inst.error;
6693 backtrack_index = i;
6696 if (i > 0 && (i > 1 || inst.operands[0].present))
6697 po_char_or_fail (',');
6699 switch (op_parse_code)
6707 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6708 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6709 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6710 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6711 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6712 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
6714 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
6716 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6718 /* Also accept generic coprocessor regs for unknown registers. */
6720 po_reg_or_fail (REG_TYPE_CN);
6722 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6723 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6724 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6725 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6726 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6727 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6728 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6729 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6730 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6731 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
6733 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
6735 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
6736 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6738 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6740 /* Neon scalar. Using an element size of 8 means that some invalid
6741 scalars are accepted here, so deal with those in later code. */
6742 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6746 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6749 po_imm_or_fail (0, 0, TRUE);
6754 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6759 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6762 if (parse_ifimm_zero (&str))
6763 inst.operands[i].imm = 0;
6767 = _("only floating point zero is allowed as immediate value");
6775 po_scalar_or_goto (8, try_rr);
6778 po_reg_or_fail (REG_TYPE_RN);
6784 po_scalar_or_goto (8, try_nsdq);
6787 po_reg_or_fail (REG_TYPE_NSDQ);
6793 po_scalar_or_goto (8, try_ndq);
6796 po_reg_or_fail (REG_TYPE_NDQ);
6802 po_scalar_or_goto (8, try_vfd);
6805 po_reg_or_fail (REG_TYPE_VFD);
6810 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6811 not careful then bad things might happen. */
6812 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6817 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6820 /* There's a possibility of getting a 64-bit immediate here, so
6821 we need special handling. */
6822 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6825 inst.error = _("immediate value is out of range");
6833 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6836 po_imm_or_fail (0, 63, TRUE);
6841 po_char_or_fail ('[');
6842 po_reg_or_fail (REG_TYPE_RN);
6843 po_char_or_fail (']');
6849 po_reg_or_fail (REG_TYPE_RN);
6850 if (skip_past_char (&str, '!') == SUCCESS)
6851 inst.operands[i].writeback = 1;
6855 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6856 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6857 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
6858 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
6859 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6860 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
6861 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
6862 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
6863 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6864 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6865 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
6866 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
6868 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6870 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6871 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6873 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
6874 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6875 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
6876 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6878 /* Immediate variants */
6880 po_char_or_fail ('{');
6881 po_imm_or_fail (0, 255, TRUE);
6882 po_char_or_fail ('}');
6886 /* The expression parser chokes on a trailing !, so we have
6887 to find it first and zap it. */
6890 while (*s && *s != ',')
6895 inst.operands[i].writeback = 1;
6897 po_imm_or_fail (0, 31, TRUE);
6905 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6910 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6915 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6917 if (inst.reloc.exp.X_op == O_symbol)
6919 val = parse_reloc (&str);
6922 inst.error = _("unrecognized relocation suffix");
6925 else if (val != BFD_RELOC_UNUSED)
6927 inst.operands[i].imm = val;
6928 inst.operands[i].hasreloc = 1;
6933 /* Operand for MOVW or MOVT. */
6935 po_misc_or_fail (parse_half (&str));
6938 /* Register or expression. */
6939 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6940 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
6942 /* Register or immediate. */
6943 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6944 I0: po_imm_or_fail (0, 0, FALSE); break;
6946 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6948 if (!is_immediate_prefix (*str))
6951 val = parse_fpa_immediate (&str);
6954 /* FPA immediates are encoded as registers 8-15.
6955 parse_fpa_immediate has already applied the offset. */
6956 inst.operands[i].reg = val;
6957 inst.operands[i].isreg = 1;
6960 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6961 I32z: po_imm_or_fail (0, 32, FALSE); break;
6963 /* Two kinds of register. */
6966 struct reg_entry *rege = arm_reg_parse_multi (&str);
6968 || (rege->type != REG_TYPE_MMXWR
6969 && rege->type != REG_TYPE_MMXWC
6970 && rege->type != REG_TYPE_MMXWCG))
6972 inst.error = _("iWMMXt data or control register expected");
6975 inst.operands[i].reg = rege->number;
6976 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6982 struct reg_entry *rege = arm_reg_parse_multi (&str);
6984 || (rege->type != REG_TYPE_MMXWC
6985 && rege->type != REG_TYPE_MMXWCG))
6987 inst.error = _("iWMMXt control register expected");
6990 inst.operands[i].reg = rege->number;
6991 inst.operands[i].isreg = 1;
6996 case OP_CPSF: val = parse_cps_flags (&str); break;
6997 case OP_ENDI: val = parse_endian_specifier (&str); break;
6998 case OP_oROR: val = parse_ror (&str); break;
6999 case OP_COND: val = parse_cond (&str); break;
7000 case OP_oBARRIER_I15:
7001 po_barrier_or_imm (str); break;
7003 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
7009 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7010 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7012 inst.error = _("Banked registers are not available with this "
7018 val = parse_psr (&str, op_parse_code == OP_wPSR);
7022 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7025 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7027 if (strncasecmp (str, "APSR_", 5) == 0)
7034 case 'c': found = (found & 1) ? 16 : found | 1; break;
7035 case 'n': found = (found & 2) ? 16 : found | 2; break;
7036 case 'z': found = (found & 4) ? 16 : found | 4; break;
7037 case 'v': found = (found & 8) ? 16 : found | 8; break;
7038 default: found = 16;
7042 inst.operands[i].isvec = 1;
7043 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7044 inst.operands[i].reg = REG_PC;
7051 po_misc_or_fail (parse_tb (&str));
7054 /* Register lists. */
7056 val = parse_reg_list (&str);
7059 inst.operands[i].writeback = 1;
7065 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
7069 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
7073 /* Allow Q registers too. */
7074 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7079 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7081 inst.operands[i].issingle = 1;
7086 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7091 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7092 &inst.operands[i].vectype);
7095 /* Addressing modes */
7097 po_misc_or_fail (parse_address (&str, i));
7101 po_misc_or_fail_no_backtrack (
7102 parse_address_group_reloc (&str, i, GROUP_LDR));
7106 po_misc_or_fail_no_backtrack (
7107 parse_address_group_reloc (&str, i, GROUP_LDRS));
7111 po_misc_or_fail_no_backtrack (
7112 parse_address_group_reloc (&str, i, GROUP_LDC));
7116 po_misc_or_fail (parse_shifter_operand (&str, i));
7120 po_misc_or_fail_no_backtrack (
7121 parse_shifter_operand_group_reloc (&str, i));
7125 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7129 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7133 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7137 as_fatal (_("unhandled operand code %d"), op_parse_code);
7140 /* Various value-based sanity checks and shared operations. We
7141 do not signal immediate failures for the register constraints;
7142 this allows a syntax error to take precedence. */
7143 switch (op_parse_code)
7151 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7152 inst.error = BAD_PC;
7157 if (inst.operands[i].isreg)
7159 if (inst.operands[i].reg == REG_PC)
7160 inst.error = BAD_PC;
7161 else if (inst.operands[i].reg == REG_SP)
7162 inst.error = BAD_SP;
7167 if (inst.operands[i].isreg
7168 && inst.operands[i].reg == REG_PC
7169 && (inst.operands[i].writeback || thumb))
7170 inst.error = BAD_PC;
7179 case OP_oBARRIER_I15:
7188 inst.operands[i].imm = val;
7195 /* If we get here, this operand was successfully parsed. */
7196 inst.operands[i].present = 1;
7200 inst.error = BAD_ARGS;
7205 /* The parse routine should already have set inst.error, but set a
7206 default here just in case. */
7208 inst.error = _("syntax error");
7212 /* Do not backtrack over a trailing optional argument that
7213 absorbed some text. We will only fail again, with the
7214 'garbage following instruction' error message, which is
7215 probably less helpful than the current one. */
7216 if (backtrack_index == i && backtrack_pos != str
7217 && upat[i+1] == OP_stop)
7220 inst.error = _("syntax error");
7224 /* Try again, skipping the optional argument at backtrack_pos. */
7225 str = backtrack_pos;
7226 inst.error = backtrack_error;
7227 inst.operands[backtrack_index].present = 0;
7228 i = backtrack_index;
7232 /* Check that we have parsed all the arguments. */
7233 if (*str != '\0' && !inst.error)
7234 inst.error = _("garbage following instruction");
7236 return inst.error ? FAIL : SUCCESS;
7239 #undef po_char_or_fail
7240 #undef po_reg_or_fail
7241 #undef po_reg_or_goto
7242 #undef po_imm_or_fail
7243 #undef po_scalar_or_fail
7244 #undef po_barrier_or_imm
7246 /* Shorthand macro for instruction encoding functions issuing errors. */
7247 #define constraint(expr, err) \
7258 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7259 instructions are unpredictable if these registers are used. This
7260 is the BadReg predicate in ARM's Thumb-2 documentation. */
7261 #define reject_bad_reg(reg) \
7263 if (reg == REG_SP || reg == REG_PC) \
7265 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7270 /* If REG is R13 (the stack pointer), warn that its use is
7272 #define warn_deprecated_sp(reg) \
7274 if (warn_on_deprecated && reg == REG_SP) \
7275 as_tsktsk (_("use of r13 is deprecated")); \
7278 /* Functions for operand encoding. ARM, then Thumb. */
7280 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7282 /* If VAL can be encoded in the immediate field of an ARM instruction,
7283 return the encoded form. Otherwise, return FAIL. */
7286 encode_arm_immediate (unsigned int val)
7290 for (i = 0; i < 32; i += 2)
7291 if ((a = rotate_left (val, i)) <= 0xff)
7292 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7297 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7298 return the encoded form. Otherwise, return FAIL. */
7300 encode_thumb32_immediate (unsigned int val)
7307 for (i = 1; i <= 24; i++)
7310 if ((val & ~(0xff << i)) == 0)
7311 return ((val >> i) & 0x7f) | ((32 - i) << 7);
7315 if (val == ((a << 16) | a))
7317 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7321 if (val == ((a << 16) | a))
7322 return 0x200 | (a >> 8);
7326 /* Encode a VFP SP or DP register number into inst.instruction. */
7329 encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7331 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7334 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
7337 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7340 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7345 first_error (_("D register out of range for selected VFP version"));
7353 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7357 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7361 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7365 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7369 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7373 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7381 /* Encode a <shift> in an ARM-format instruction. The immediate,
7382 if any, is handled by md_apply_fix. */
7384 encode_arm_shift (int i)
7386 if (inst.operands[i].shift_kind == SHIFT_RRX)
7387 inst.instruction |= SHIFT_ROR << 5;
7390 inst.instruction |= inst.operands[i].shift_kind << 5;
7391 if (inst.operands[i].immisreg)
7393 inst.instruction |= SHIFT_BY_REG;
7394 inst.instruction |= inst.operands[i].imm << 8;
7397 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7402 encode_arm_shifter_operand (int i)
7404 if (inst.operands[i].isreg)
7406 inst.instruction |= inst.operands[i].reg;
7407 encode_arm_shift (i);
7411 inst.instruction |= INST_IMMEDIATE;
7412 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7413 inst.instruction |= inst.operands[i].imm;
7417 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7419 encode_arm_addr_mode_common (int i, bfd_boolean is_t)
7422 Generate an error if the operand is not a register. */
7423 constraint (!inst.operands[i].isreg,
7424 _("Instruction does not support =N addresses"));
7426 inst.instruction |= inst.operands[i].reg << 16;
7428 if (inst.operands[i].preind)
7432 inst.error = _("instruction does not accept preindexed addressing");
7435 inst.instruction |= PRE_INDEX;
7436 if (inst.operands[i].writeback)
7437 inst.instruction |= WRITE_BACK;
7440 else if (inst.operands[i].postind)
7442 gas_assert (inst.operands[i].writeback);
7444 inst.instruction |= WRITE_BACK;
7446 else /* unindexed - only for coprocessor */
7448 inst.error = _("instruction does not accept unindexed addressing");
7452 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7453 && (((inst.instruction & 0x000f0000) >> 16)
7454 == ((inst.instruction & 0x0000f000) >> 12)))
7455 as_warn ((inst.instruction & LOAD_BIT)
7456 ? _("destination register same as write-back base")
7457 : _("source register same as write-back base"));
7460 /* inst.operands[i] was set up by parse_address. Encode it into an
7461 ARM-format mode 2 load or store instruction. If is_t is true,
7462 reject forms that cannot be used with a T instruction (i.e. not
7465 encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
7467 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7469 encode_arm_addr_mode_common (i, is_t);
7471 if (inst.operands[i].immisreg)
7473 constraint ((inst.operands[i].imm == REG_PC
7474 || (is_pc && inst.operands[i].writeback)),
7476 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7477 inst.instruction |= inst.operands[i].imm;
7478 if (!inst.operands[i].negative)
7479 inst.instruction |= INDEX_UP;
7480 if (inst.operands[i].shifted)
7482 if (inst.operands[i].shift_kind == SHIFT_RRX)
7483 inst.instruction |= SHIFT_ROR << 5;
7486 inst.instruction |= inst.operands[i].shift_kind << 5;
7487 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7491 else /* immediate offset in inst.reloc */
7493 if (is_pc && !inst.reloc.pc_rel)
7495 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
7497 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7498 cannot use PC in addressing.
7499 PC cannot be used in writeback addressing, either. */
7500 constraint ((is_t || inst.operands[i].writeback),
7503 /* Use of PC in str is deprecated for ARMv7. */
7504 if (warn_on_deprecated
7506 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7507 as_tsktsk (_("use of PC in this instruction is deprecated"));
7510 if (inst.reloc.type == BFD_RELOC_UNUSED)
7512 /* Prefer + for zero encoded value. */
7513 if (!inst.operands[i].negative)
7514 inst.instruction |= INDEX_UP;
7515 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7520 /* inst.operands[i] was set up by parse_address. Encode it into an
7521 ARM-format mode 3 load or store instruction. Reject forms that
7522 cannot be used with such instructions. If is_t is true, reject
7523 forms that cannot be used with a T instruction (i.e. not
7526 encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
7528 if (inst.operands[i].immisreg && inst.operands[i].shifted)
7530 inst.error = _("instruction does not accept scaled register index");
7534 encode_arm_addr_mode_common (i, is_t);
7536 if (inst.operands[i].immisreg)
7538 constraint ((inst.operands[i].imm == REG_PC
7539 || (is_t && inst.operands[i].reg == REG_PC)),
7541 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7543 inst.instruction |= inst.operands[i].imm;
7544 if (!inst.operands[i].negative)
7545 inst.instruction |= INDEX_UP;
7547 else /* immediate offset in inst.reloc */
7549 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7550 && inst.operands[i].writeback),
7552 inst.instruction |= HWOFFSET_IMM;
7553 if (inst.reloc.type == BFD_RELOC_UNUSED)
7555 /* Prefer + for zero encoded value. */
7556 if (!inst.operands[i].negative)
7557 inst.instruction |= INDEX_UP;
7559 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7564 /* Write immediate bits [7:0] to the following locations:
7566 |28/24|23 19|18 16|15 4|3 0|
7567 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7569 This function is used by VMOV/VMVN/VORR/VBIC. */
7572 neon_write_immbits (unsigned immbits)
7574 inst.instruction |= immbits & 0xf;
7575 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7576 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7579 /* Invert low-order SIZE bits of XHI:XLO. */
7582 neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7584 unsigned immlo = xlo ? *xlo : 0;
7585 unsigned immhi = xhi ? *xhi : 0;
7590 immlo = (~immlo) & 0xff;
7594 immlo = (~immlo) & 0xffff;
7598 immhi = (~immhi) & 0xffffffff;
7602 immlo = (~immlo) & 0xffffffff;
7616 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7620 neon_bits_same_in_bytes (unsigned imm)
7622 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7623 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7624 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7625 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7628 /* For immediate of above form, return 0bABCD. */
7631 neon_squash_bits (unsigned imm)
7633 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7634 | ((imm & 0x01000000) >> 21);
7637 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7640 neon_qfloat_bits (unsigned imm)
7642 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7645 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7646 the instruction. *OP is passed as the initial value of the op field, and
7647 may be set to a different value depending on the constant (i.e.
7648 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7649 MVN). If the immediate looks like a repeated pattern then also
7650 try smaller element sizes. */
7653 neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7654 unsigned *immbits, int *op, int size,
7655 enum neon_el_type type)
7657 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7659 if (type == NT_float && !float_p)
7662 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
7664 if (size != 32 || *op == 1)
7666 *immbits = neon_qfloat_bits (immlo);
7672 if (neon_bits_same_in_bytes (immhi)
7673 && neon_bits_same_in_bytes (immlo))
7677 *immbits = (neon_squash_bits (immhi) << 4)
7678 | neon_squash_bits (immlo);
7689 if (immlo == (immlo & 0x000000ff))
7694 else if (immlo == (immlo & 0x0000ff00))
7696 *immbits = immlo >> 8;
7699 else if (immlo == (immlo & 0x00ff0000))
7701 *immbits = immlo >> 16;
7704 else if (immlo == (immlo & 0xff000000))
7706 *immbits = immlo >> 24;
7709 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7711 *immbits = (immlo >> 8) & 0xff;
7714 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7716 *immbits = (immlo >> 16) & 0xff;
7720 if ((immlo & 0xffff) != (immlo >> 16))
7727 if (immlo == (immlo & 0x000000ff))
7732 else if (immlo == (immlo & 0x0000ff00))
7734 *immbits = immlo >> 8;
7738 if ((immlo & 0xff) != (immlo >> 8))
7743 if (immlo == (immlo & 0x000000ff))
7745 /* Don't allow MVN with 8-bit immediate. */
7755 /* Returns TRUE if double precision value V may be cast
7756 to single precision without loss of accuracy. */
7759 is_double_a_single (long int v)
7761 int exp = (int) (v >> 52) & 0x7FF;
7762 long int mantissa = (v & 0xFFFFFFFFFFFFFl);
7764 return (exp == 0 || exp == 0x7FF
7765 || (exp >= 1023 - 126 && exp <= 1023 + 127))
7766 && (mantissa & 0x1FFFFFFFl) == 0;
7769 /* Returns a double precision value casted to single precision
7770 (ignoring the least significant bits in exponent and mantissa). */
7773 double_to_single (long int v)
7775 int sign = (int) ((v >> 63) & 1l);
7776 int exp = (int) (v >> 52) & 0x7FF;
7777 long int mantissa = (v & 0xFFFFFFFFFFFFFl);
7783 exp = exp - 1023 + 127;
7792 /* No denormalized numbers. */
7798 return (sign << 31) | (exp << 23) | mantissa;
7808 static void do_vfp_nsyn_opcode (const char *);
7810 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7811 Determine whether it can be performed with a move instruction; if
7812 it can, convert inst.instruction to that move instruction and
7813 return TRUE; if it can't, convert inst.instruction to a literal-pool
7814 load and return FALSE. If this is not a valid thing to do in the
7815 current context, set inst.error and return TRUE.
7817 inst.operands[i] describes the destination register. */
7820 move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
7823 bfd_boolean thumb_p = (t == CONST_THUMB);
7824 bfd_boolean arm_p = (t == CONST_ARM);
7827 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7831 if ((inst.instruction & tbit) == 0)
7833 inst.error = _("invalid pseudo operation");
7837 if (inst.reloc.exp.X_op != O_constant
7838 && inst.reloc.exp.X_op != O_symbol
7839 && inst.reloc.exp.X_op != O_big)
7841 inst.error = _("constant expression expected");
7845 if (inst.reloc.exp.X_op == O_constant
7846 || inst.reloc.exp.X_op == O_big)
7850 if (inst.reloc.exp.X_op == O_big)
7852 LITTLENUM_TYPE w[X_PRECISION];
7855 if (inst.reloc.exp.X_add_number == -1)
7857 gen_to_words (w, X_PRECISION, E_PRECISION);
7859 /* FIXME: Should we check words w[2..5] ? */
7864 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
7865 | (l[0] & LITTLENUM_MASK);
7868 v = inst.reloc.exp.X_add_number;
7870 if (!inst.operands[i].issingle)
7872 if (thumb_p && inst.reloc.exp.X_op == O_constant)
7874 if (!unified_syntax && (v & ~0xFF) == 0)
7876 /* This can be done with a mov(1) instruction. */
7877 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7878 inst.instruction |= v;
7882 else if (arm_p && inst.reloc.exp.X_op == O_constant)
7884 int value = encode_arm_immediate (v);
7887 /* This can be done with a mov instruction. */
7888 inst.instruction &= LITERAL_MASK;
7889 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7890 inst.instruction |= value & 0xfff;
7894 value = encode_arm_immediate (~ v);
7897 /* This can be done with a mvn instruction. */
7898 inst.instruction &= LITERAL_MASK;
7899 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7900 inst.instruction |= value & 0xfff;
7904 else if (t == CONST_VEC)
7907 unsigned immbits = 0;
7908 unsigned immlo = inst.operands[1].imm;
7909 unsigned immhi = inst.operands[1].regisimm
7910 ? inst.operands[1].reg
7911 : inst.reloc.exp.X_unsigned
7913 : ((bfd_int64_t)((int) immlo)) >> 32;
7914 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7915 &op, 64, NT_invtype);
7919 neon_invert_size (&immlo, &immhi, 64);
7921 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7922 &op, 64, NT_invtype);
7927 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
7933 /* Fill other bits in vmov encoding for both thumb and arm. */
7935 inst.instruction |= (0x7 << 29) | (0xF << 24);
7937 inst.instruction |= (0xF << 28) | (0x1 << 25);
7938 neon_write_immbits (immbits);
7946 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
7947 if (inst.operands[i].issingle
7948 && is_quarter_float (inst.operands[1].imm)
7949 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
7951 inst.operands[1].imm =
7952 neon_qfloat_bits (v);
7953 do_vfp_nsyn_opcode ("fconsts");
7956 else if (!inst.operands[1].issingle
7957 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
7959 if (is_double_a_single (v)
7960 && is_quarter_float (double_to_single (v)))
7962 inst.operands[1].imm =
7963 neon_qfloat_bits (double_to_single (v));
7964 do_vfp_nsyn_opcode ("fconstd");
7971 if (add_to_lit_pool ((!inst.operands[i].isvec
7972 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
7975 inst.operands[1].reg = REG_PC;
7976 inst.operands[1].isreg = 1;
7977 inst.operands[1].preind = 1;
7978 inst.reloc.pc_rel = 1;
7979 inst.reloc.type = (thumb_p
7980 ? BFD_RELOC_ARM_THUMB_OFFSET
7982 ? BFD_RELOC_ARM_HWLITERAL
7983 : BFD_RELOC_ARM_LITERAL));
7987 /* inst.operands[i] was set up by parse_address. Encode it into an
7988 ARM-format instruction. Reject all forms which cannot be encoded
7989 into a coprocessor load/store instruction. If wb_ok is false,
7990 reject use of writeback; if unind_ok is false, reject use of
7991 unindexed addressing. If reloc_override is not 0, use it instead
7992 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7993 (in which case it is preserved). */
7996 encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7998 if (!inst.operands[i].isreg)
8001 if (! inst.operands[0].isvec)
8003 inst.error = _("invalid co-processor operand");
8006 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8010 inst.instruction |= inst.operands[i].reg << 16;
8012 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8014 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8016 gas_assert (!inst.operands[i].writeback);
8019 inst.error = _("instruction does not support unindexed addressing");
8022 inst.instruction |= inst.operands[i].imm;
8023 inst.instruction |= INDEX_UP;
8027 if (inst.operands[i].preind)
8028 inst.instruction |= PRE_INDEX;
8030 if (inst.operands[i].writeback)
8032 if (inst.operands[i].reg == REG_PC)
8034 inst.error = _("pc may not be used with write-back");
8039 inst.error = _("instruction does not support writeback");
8042 inst.instruction |= WRITE_BACK;
8046 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
8047 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
8048 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
8049 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
8052 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8054 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
8057 /* Prefer + for zero encoded value. */
8058 if (!inst.operands[i].negative)
8059 inst.instruction |= INDEX_UP;
8064 /* Functions for instruction encoding, sorted by sub-architecture.
8065 First some generics; their names are taken from the conventional
8066 bit positions for register arguments in ARM format instructions. */
8076 inst.instruction |= inst.operands[0].reg << 12;
8082 inst.instruction |= inst.operands[0].reg << 12;
8083 inst.instruction |= inst.operands[1].reg;
8089 inst.instruction |= inst.operands[0].reg;
8090 inst.instruction |= inst.operands[1].reg << 16;
8096 inst.instruction |= inst.operands[0].reg << 12;
8097 inst.instruction |= inst.operands[1].reg << 16;
8103 inst.instruction |= inst.operands[0].reg << 16;
8104 inst.instruction |= inst.operands[1].reg << 12;
8108 check_obsolete (const arm_feature_set *feature, const char *msg)
8110 if (ARM_CPU_IS_ANY (cpu_variant))
8112 as_tsktsk ("%s", msg);
8115 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
8127 unsigned Rn = inst.operands[2].reg;
8128 /* Enforce restrictions on SWP instruction. */
8129 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
8131 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8132 _("Rn must not overlap other operands"));
8134 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8136 if (!check_obsolete (&arm_ext_v8,
8137 _("swp{b} use is obsoleted for ARMv8 and later"))
8138 && warn_on_deprecated
8139 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8140 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8143 inst.instruction |= inst.operands[0].reg << 12;
8144 inst.instruction |= inst.operands[1].reg;
8145 inst.instruction |= Rn << 16;
8151 inst.instruction |= inst.operands[0].reg << 12;
8152 inst.instruction |= inst.operands[1].reg << 16;
8153 inst.instruction |= inst.operands[2].reg;
8159 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8160 constraint (((inst.reloc.exp.X_op != O_constant
8161 && inst.reloc.exp.X_op != O_illegal)
8162 || inst.reloc.exp.X_add_number != 0),
8164 inst.instruction |= inst.operands[0].reg;
8165 inst.instruction |= inst.operands[1].reg << 12;
8166 inst.instruction |= inst.operands[2].reg << 16;
8172 inst.instruction |= inst.operands[0].imm;
8178 inst.instruction |= inst.operands[0].reg << 12;
8179 encode_arm_cp_address (1, TRUE, TRUE, 0);
8182 /* ARM instructions, in alphabetical order by function name (except
8183 that wrapper functions appear immediately after the function they
8186 /* This is a pseudo-op of the form "adr rd, label" to be converted
8187 into a relative address of the form "add rd, pc, #label-.-8". */
8192 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8194 /* Frag hacking will turn this into a sub instruction if the offset turns
8195 out to be negative. */
8196 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8197 inst.reloc.pc_rel = 1;
8198 inst.reloc.exp.X_add_number -= 8;
8201 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8202 into a relative address of the form:
8203 add rd, pc, #low(label-.-8)"
8204 add rd, rd, #high(label-.-8)" */
8209 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
8211 /* Frag hacking will turn this into a sub instruction if the offset turns
8212 out to be negative. */
8213 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
8214 inst.reloc.pc_rel = 1;
8215 inst.size = INSN_SIZE * 2;
8216 inst.reloc.exp.X_add_number -= 8;
8222 if (!inst.operands[1].present)
8223 inst.operands[1].reg = inst.operands[0].reg;
8224 inst.instruction |= inst.operands[0].reg << 12;
8225 inst.instruction |= inst.operands[1].reg << 16;
8226 encode_arm_shifter_operand (2);
8232 if (inst.operands[0].present)
8233 inst.instruction |= inst.operands[0].imm;
8235 inst.instruction |= 0xf;
8241 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8242 constraint (msb > 32, _("bit-field extends past end of register"));
8243 /* The instruction encoding stores the LSB and MSB,
8244 not the LSB and width. */
8245 inst.instruction |= inst.operands[0].reg << 12;
8246 inst.instruction |= inst.operands[1].imm << 7;
8247 inst.instruction |= (msb - 1) << 16;
8255 /* #0 in second position is alternative syntax for bfc, which is
8256 the same instruction but with REG_PC in the Rm field. */
8257 if (!inst.operands[1].isreg)
8258 inst.operands[1].reg = REG_PC;
8260 msb = inst.operands[2].imm + inst.operands[3].imm;
8261 constraint (msb > 32, _("bit-field extends past end of register"));
8262 /* The instruction encoding stores the LSB and MSB,
8263 not the LSB and width. */
8264 inst.instruction |= inst.operands[0].reg << 12;
8265 inst.instruction |= inst.operands[1].reg;
8266 inst.instruction |= inst.operands[2].imm << 7;
8267 inst.instruction |= (msb - 1) << 16;
8273 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8274 _("bit-field extends past end of register"));
8275 inst.instruction |= inst.operands[0].reg << 12;
8276 inst.instruction |= inst.operands[1].reg;
8277 inst.instruction |= inst.operands[2].imm << 7;
8278 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8281 /* ARM V5 breakpoint instruction (argument parse)
8282 BKPT <16 bit unsigned immediate>
8283 Instruction is not conditional.
8284 The bit pattern given in insns[] has the COND_ALWAYS condition,
8285 and it is an error if the caller tried to override that. */
8290 /* Top 12 of 16 bits to bits 19:8. */
8291 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
8293 /* Bottom 4 of 16 bits to bits 3:0. */
8294 inst.instruction |= inst.operands[0].imm & 0xf;
8298 encode_branch (int default_reloc)
8300 if (inst.operands[0].hasreloc)
8302 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8303 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8304 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8305 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8306 ? BFD_RELOC_ARM_PLT32
8307 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
8310 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
8311 inst.reloc.pc_rel = 1;
8318 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8319 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8322 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8329 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8331 if (inst.cond == COND_ALWAYS)
8332 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8334 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8338 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8341 /* ARM V5 branch-link-exchange instruction (argument parse)
8342 BLX <target_addr> ie BLX(1)
8343 BLX{<condition>} <Rm> ie BLX(2)
8344 Unfortunately, there are two different opcodes for this mnemonic.
8345 So, the insns[].value is not used, and the code here zaps values
8346 into inst.instruction.
8347 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8352 if (inst.operands[0].isreg)
8354 /* Arg is a register; the opcode provided by insns[] is correct.
8355 It is not illegal to do "blx pc", just useless. */
8356 if (inst.operands[0].reg == REG_PC)
8357 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8359 inst.instruction |= inst.operands[0].reg;
8363 /* Arg is an address; this instruction cannot be executed
8364 conditionally, and the opcode must be adjusted.
8365 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8366 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8367 constraint (inst.cond != COND_ALWAYS, BAD_COND);
8368 inst.instruction = 0xfa000000;
8369 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
8376 bfd_boolean want_reloc;
8378 if (inst.operands[0].reg == REG_PC)
8379 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8381 inst.instruction |= inst.operands[0].reg;
8382 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8383 it is for ARMv4t or earlier. */
8384 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8385 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
8389 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
8394 inst.reloc.type = BFD_RELOC_ARM_V4BX;
8398 /* ARM v5TEJ. Jump to Jazelle code. */
8403 if (inst.operands[0].reg == REG_PC)
8404 as_tsktsk (_("use of r15 in bxj is not really useful"));
8406 inst.instruction |= inst.operands[0].reg;
8409 /* Co-processor data operation:
8410 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8411 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8415 inst.instruction |= inst.operands[0].reg << 8;
8416 inst.instruction |= inst.operands[1].imm << 20;
8417 inst.instruction |= inst.operands[2].reg << 12;
8418 inst.instruction |= inst.operands[3].reg << 16;
8419 inst.instruction |= inst.operands[4].reg;
8420 inst.instruction |= inst.operands[5].imm << 5;
8426 inst.instruction |= inst.operands[0].reg << 16;
8427 encode_arm_shifter_operand (1);
8430 /* Transfer between coprocessor and ARM registers.
8431 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8436 No special properties. */
8438 struct deprecated_coproc_regs_s
8445 arm_feature_set deprecated;
8446 arm_feature_set obsoleted;
8447 const char *dep_msg;
8448 const char *obs_msg;
8451 #define DEPR_ACCESS_V8 \
8452 N_("This coprocessor register access is deprecated in ARMv8")
8454 /* Table of all deprecated coprocessor registers. */
8455 static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8457 {15, 0, 7, 10, 5, /* CP15DMB. */
8458 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8459 DEPR_ACCESS_V8, NULL},
8460 {15, 0, 7, 10, 4, /* CP15DSB. */
8461 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8462 DEPR_ACCESS_V8, NULL},
8463 {15, 0, 7, 5, 4, /* CP15ISB. */
8464 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8465 DEPR_ACCESS_V8, NULL},
8466 {14, 6, 1, 0, 0, /* TEEHBR. */
8467 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8468 DEPR_ACCESS_V8, NULL},
8469 {14, 6, 0, 0, 0, /* TEECR. */
8470 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
8471 DEPR_ACCESS_V8, NULL},
8474 #undef DEPR_ACCESS_V8
8476 static const size_t deprecated_coproc_reg_count =
8477 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8485 Rd = inst.operands[2].reg;
8488 if (inst.instruction == 0xee000010
8489 || inst.instruction == 0xfe000010)
8491 reject_bad_reg (Rd);
8494 constraint (Rd == REG_SP, BAD_SP);
8499 if (inst.instruction == 0xe000010)
8500 constraint (Rd == REG_PC, BAD_PC);
8503 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8505 const struct deprecated_coproc_regs_s *r =
8506 deprecated_coproc_regs + i;
8508 if (inst.operands[0].reg == r->cp
8509 && inst.operands[1].imm == r->opc1
8510 && inst.operands[3].reg == r->crn
8511 && inst.operands[4].reg == r->crm
8512 && inst.operands[5].imm == r->opc2)
8514 if (! ARM_CPU_IS_ANY (cpu_variant)
8515 && warn_on_deprecated
8516 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
8517 as_tsktsk ("%s", r->dep_msg);
8521 inst.instruction |= inst.operands[0].reg << 8;
8522 inst.instruction |= inst.operands[1].imm << 21;
8523 inst.instruction |= Rd << 12;
8524 inst.instruction |= inst.operands[3].reg << 16;
8525 inst.instruction |= inst.operands[4].reg;
8526 inst.instruction |= inst.operands[5].imm << 5;
8529 /* Transfer between coprocessor register and pair of ARM registers.
8530 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8535 Two XScale instructions are special cases of these:
8537 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8538 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8540 Result unpredictable if Rd or Rn is R15. */
8547 Rd = inst.operands[2].reg;
8548 Rn = inst.operands[3].reg;
8552 reject_bad_reg (Rd);
8553 reject_bad_reg (Rn);
8557 constraint (Rd == REG_PC, BAD_PC);
8558 constraint (Rn == REG_PC, BAD_PC);
8561 inst.instruction |= inst.operands[0].reg << 8;
8562 inst.instruction |= inst.operands[1].imm << 4;
8563 inst.instruction |= Rd << 12;
8564 inst.instruction |= Rn << 16;
8565 inst.instruction |= inst.operands[4].reg;
8571 inst.instruction |= inst.operands[0].imm << 6;
8572 if (inst.operands[1].present)
8574 inst.instruction |= CPSI_MMOD;
8575 inst.instruction |= inst.operands[1].imm;
8582 inst.instruction |= inst.operands[0].imm;
8588 unsigned Rd, Rn, Rm;
8590 Rd = inst.operands[0].reg;
8591 Rn = (inst.operands[1].present
8592 ? inst.operands[1].reg : Rd);
8593 Rm = inst.operands[2].reg;
8595 constraint ((Rd == REG_PC), BAD_PC);
8596 constraint ((Rn == REG_PC), BAD_PC);
8597 constraint ((Rm == REG_PC), BAD_PC);
8599 inst.instruction |= Rd << 16;
8600 inst.instruction |= Rn << 0;
8601 inst.instruction |= Rm << 8;
8607 /* There is no IT instruction in ARM mode. We
8608 process it to do the validation as if in
8609 thumb mode, just in case the code gets
8610 assembled for thumb using the unified syntax. */
8615 set_it_insn_type (IT_INSN);
8616 now_it.mask = (inst.instruction & 0xf) | 0x10;
8617 now_it.cc = inst.operands[0].imm;
8621 /* If there is only one register in the register list,
8622 then return its register number. Otherwise return -1. */
8624 only_one_reg_in_list (int range)
8626 int i = ffs (range) - 1;
8627 return (i > 15 || range != (1 << i)) ? -1 : i;
8631 encode_ldmstm(int from_push_pop_mnem)
8633 int base_reg = inst.operands[0].reg;
8634 int range = inst.operands[1].imm;
8637 inst.instruction |= base_reg << 16;
8638 inst.instruction |= range;
8640 if (inst.operands[1].writeback)
8641 inst.instruction |= LDM_TYPE_2_OR_3;
8643 if (inst.operands[0].writeback)
8645 inst.instruction |= WRITE_BACK;
8646 /* Check for unpredictable uses of writeback. */
8647 if (inst.instruction & LOAD_BIT)
8649 /* Not allowed in LDM type 2. */
8650 if ((inst.instruction & LDM_TYPE_2_OR_3)
8651 && ((range & (1 << REG_PC)) == 0))
8652 as_warn (_("writeback of base register is UNPREDICTABLE"));
8653 /* Only allowed if base reg not in list for other types. */
8654 else if (range & (1 << base_reg))
8655 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8659 /* Not allowed for type 2. */
8660 if (inst.instruction & LDM_TYPE_2_OR_3)
8661 as_warn (_("writeback of base register is UNPREDICTABLE"));
8662 /* Only allowed if base reg not in list, or first in list. */
8663 else if ((range & (1 << base_reg))
8664 && (range & ((1 << base_reg) - 1)))
8665 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8669 /* If PUSH/POP has only one register, then use the A2 encoding. */
8670 one_reg = only_one_reg_in_list (range);
8671 if (from_push_pop_mnem && one_reg >= 0)
8673 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8675 inst.instruction &= A_COND_MASK;
8676 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8677 inst.instruction |= one_reg << 12;
8684 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
8687 /* ARMv5TE load-consecutive (argument parse)
8696 constraint (inst.operands[0].reg % 2 != 0,
8697 _("first transfer register must be even"));
8698 constraint (inst.operands[1].present
8699 && inst.operands[1].reg != inst.operands[0].reg + 1,
8700 _("can only transfer two consecutive registers"));
8701 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8702 constraint (!inst.operands[2].isreg, _("'[' expected"));
8704 if (!inst.operands[1].present)
8705 inst.operands[1].reg = inst.operands[0].reg + 1;
8707 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8708 register and the first register written; we have to diagnose
8709 overlap between the base and the second register written here. */
8711 if (inst.operands[2].reg == inst.operands[1].reg
8712 && (inst.operands[2].writeback || inst.operands[2].postind))
8713 as_warn (_("base register written back, and overlaps "
8714 "second transfer register"));
8716 if (!(inst.instruction & V4_STR_BIT))
8718 /* For an index-register load, the index register must not overlap the
8719 destination (even if not write-back). */
8720 if (inst.operands[2].immisreg
8721 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8722 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8723 as_warn (_("index register overlaps transfer register"));
8725 inst.instruction |= inst.operands[0].reg << 12;
8726 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
8732 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8733 || inst.operands[1].postind || inst.operands[1].writeback
8734 || inst.operands[1].immisreg || inst.operands[1].shifted
8735 || inst.operands[1].negative
8736 /* This can arise if the programmer has written
8738 or if they have mistakenly used a register name as the last
8741 It is very difficult to distinguish between these two cases
8742 because "rX" might actually be a label. ie the register
8743 name has been occluded by a symbol of the same name. So we
8744 just generate a general 'bad addressing mode' type error
8745 message and leave it up to the programmer to discover the
8746 true cause and fix their mistake. */
8747 || (inst.operands[1].reg == REG_PC),
8750 constraint (inst.reloc.exp.X_op != O_constant
8751 || inst.reloc.exp.X_add_number != 0,
8752 _("offset must be zero in ARM encoding"));
8754 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8756 inst.instruction |= inst.operands[0].reg << 12;
8757 inst.instruction |= inst.operands[1].reg << 16;
8758 inst.reloc.type = BFD_RELOC_UNUSED;
8764 constraint (inst.operands[0].reg % 2 != 0,
8765 _("even register required"));
8766 constraint (inst.operands[1].present
8767 && inst.operands[1].reg != inst.operands[0].reg + 1,
8768 _("can only load two consecutive registers"));
8769 /* If op 1 were present and equal to PC, this function wouldn't
8770 have been called in the first place. */
8771 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8773 inst.instruction |= inst.operands[0].reg << 12;
8774 inst.instruction |= inst.operands[2].reg << 16;
8777 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8778 which is not a multiple of four is UNPREDICTABLE. */
8780 check_ldr_r15_aligned (void)
8782 constraint (!(inst.operands[1].immisreg)
8783 && (inst.operands[0].reg == REG_PC
8784 && inst.operands[1].reg == REG_PC
8785 && (inst.reloc.exp.X_add_number & 0x3)),
8786 _("ldr to register 15 must be 4-byte alligned"));
8792 inst.instruction |= inst.operands[0].reg << 12;
8793 if (!inst.operands[1].isreg)
8794 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
8796 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
8797 check_ldr_r15_aligned ();
8803 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8805 if (inst.operands[1].preind)
8807 constraint (inst.reloc.exp.X_op != O_constant
8808 || inst.reloc.exp.X_add_number != 0,
8809 _("this instruction requires a post-indexed address"));
8811 inst.operands[1].preind = 0;
8812 inst.operands[1].postind = 1;
8813 inst.operands[1].writeback = 1;
8815 inst.instruction |= inst.operands[0].reg << 12;
8816 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8819 /* Halfword and signed-byte load/store operations. */
8824 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8825 inst.instruction |= inst.operands[0].reg << 12;
8826 if (!inst.operands[1].isreg)
8827 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
8829 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
8835 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8837 if (inst.operands[1].preind)
8839 constraint (inst.reloc.exp.X_op != O_constant
8840 || inst.reloc.exp.X_add_number != 0,
8841 _("this instruction requires a post-indexed address"));
8843 inst.operands[1].preind = 0;
8844 inst.operands[1].postind = 1;
8845 inst.operands[1].writeback = 1;
8847 inst.instruction |= inst.operands[0].reg << 12;
8848 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8851 /* Co-processor register load/store.
8852 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8856 inst.instruction |= inst.operands[0].reg << 8;
8857 inst.instruction |= inst.operands[1].reg << 12;
8858 encode_arm_cp_address (2, TRUE, TRUE, 0);
8864 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8865 if (inst.operands[0].reg == inst.operands[1].reg
8866 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
8867 && !(inst.instruction & 0x00400000))
8868 as_tsktsk (_("Rd and Rm should be different in mla"));
8870 inst.instruction |= inst.operands[0].reg << 16;
8871 inst.instruction |= inst.operands[1].reg;
8872 inst.instruction |= inst.operands[2].reg << 8;
8873 inst.instruction |= inst.operands[3].reg << 12;
8879 inst.instruction |= inst.operands[0].reg << 12;
8880 encode_arm_shifter_operand (1);
8883 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8890 top = (inst.instruction & 0x00400000) != 0;
8891 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8892 _(":lower16: not allowed this instruction"));
8893 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8894 _(":upper16: not allowed instruction"));
8895 inst.instruction |= inst.operands[0].reg << 12;
8896 if (inst.reloc.type == BFD_RELOC_UNUSED)
8898 imm = inst.reloc.exp.X_add_number;
8899 /* The value is in two pieces: 0:11, 16:19. */
8900 inst.instruction |= (imm & 0x00000fff);
8901 inst.instruction |= (imm & 0x0000f000) << 4;
8906 do_vfp_nsyn_mrs (void)
8908 if (inst.operands[0].isvec)
8910 if (inst.operands[1].reg != 1)
8911 first_error (_("operand 1 must be FPSCR"));
8912 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8913 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8914 do_vfp_nsyn_opcode ("fmstat");
8916 else if (inst.operands[1].isvec)
8917 do_vfp_nsyn_opcode ("fmrx");
8925 do_vfp_nsyn_msr (void)
8927 if (inst.operands[0].isvec)
8928 do_vfp_nsyn_opcode ("fmxr");
8938 unsigned Rt = inst.operands[0].reg;
8940 if (thumb_mode && Rt == REG_SP)
8942 inst.error = BAD_SP;
8946 /* APSR_ sets isvec. All other refs to PC are illegal. */
8947 if (!inst.operands[0].isvec && Rt == REG_PC)
8949 inst.error = BAD_PC;
8953 /* If we get through parsing the register name, we just insert the number
8954 generated into the instruction without further validation. */
8955 inst.instruction |= (inst.operands[1].reg << 16);
8956 inst.instruction |= (Rt << 12);
8962 unsigned Rt = inst.operands[1].reg;
8965 reject_bad_reg (Rt);
8966 else if (Rt == REG_PC)
8968 inst.error = BAD_PC;
8972 /* If we get through parsing the register name, we just insert the number
8973 generated into the instruction without further validation. */
8974 inst.instruction |= (inst.operands[0].reg << 16);
8975 inst.instruction |= (Rt << 12);
8983 if (do_vfp_nsyn_mrs () == SUCCESS)
8986 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
8987 inst.instruction |= inst.operands[0].reg << 12;
8989 if (inst.operands[1].isreg)
8991 br = inst.operands[1].reg;
8992 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8993 as_bad (_("bad register for mrs"));
8997 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8998 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
9000 _("'APSR', 'CPSR' or 'SPSR' expected"));
9001 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
9004 inst.instruction |= br;
9007 /* Two possible forms:
9008 "{C|S}PSR_<field>, Rm",
9009 "{C|S}PSR_f, #expression". */
9014 if (do_vfp_nsyn_msr () == SUCCESS)
9017 inst.instruction |= inst.operands[0].imm;
9018 if (inst.operands[1].isreg)
9019 inst.instruction |= inst.operands[1].reg;
9022 inst.instruction |= INST_IMMEDIATE;
9023 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
9024 inst.reloc.pc_rel = 0;
9031 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
9033 if (!inst.operands[2].present)
9034 inst.operands[2].reg = inst.operands[0].reg;
9035 inst.instruction |= inst.operands[0].reg << 16;
9036 inst.instruction |= inst.operands[1].reg;
9037 inst.instruction |= inst.operands[2].reg << 8;
9039 if (inst.operands[0].reg == inst.operands[1].reg
9040 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9041 as_tsktsk (_("Rd and Rm should be different in mul"));
9044 /* Long Multiply Parser
9045 UMULL RdLo, RdHi, Rm, Rs
9046 SMULL RdLo, RdHi, Rm, Rs
9047 UMLAL RdLo, RdHi, Rm, Rs
9048 SMLAL RdLo, RdHi, Rm, Rs. */
9053 inst.instruction |= inst.operands[0].reg << 12;
9054 inst.instruction |= inst.operands[1].reg << 16;
9055 inst.instruction |= inst.operands[2].reg;
9056 inst.instruction |= inst.operands[3].reg << 8;
9058 /* rdhi and rdlo must be different. */
9059 if (inst.operands[0].reg == inst.operands[1].reg)
9060 as_tsktsk (_("rdhi and rdlo must be different"));
9062 /* rdhi, rdlo and rm must all be different before armv6. */
9063 if ((inst.operands[0].reg == inst.operands[2].reg
9064 || inst.operands[1].reg == inst.operands[2].reg)
9065 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
9066 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9072 if (inst.operands[0].present
9073 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
9075 /* Architectural NOP hints are CPSR sets with no bits selected. */
9076 inst.instruction &= 0xf0000000;
9077 inst.instruction |= 0x0320f000;
9078 if (inst.operands[0].present)
9079 inst.instruction |= inst.operands[0].imm;
9083 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9084 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9085 Condition defaults to COND_ALWAYS.
9086 Error if Rd, Rn or Rm are R15. */
9091 inst.instruction |= inst.operands[0].reg << 12;
9092 inst.instruction |= inst.operands[1].reg << 16;
9093 inst.instruction |= inst.operands[2].reg;
9094 if (inst.operands[3].present)
9095 encode_arm_shift (3);
9098 /* ARM V6 PKHTB (Argument Parse). */
9103 if (!inst.operands[3].present)
9105 /* If the shift specifier is omitted, turn the instruction
9106 into pkhbt rd, rm, rn. */
9107 inst.instruction &= 0xfff00010;
9108 inst.instruction |= inst.operands[0].reg << 12;
9109 inst.instruction |= inst.operands[1].reg;
9110 inst.instruction |= inst.operands[2].reg << 16;
9114 inst.instruction |= inst.operands[0].reg << 12;
9115 inst.instruction |= inst.operands[1].reg << 16;
9116 inst.instruction |= inst.operands[2].reg;
9117 encode_arm_shift (3);
9121 /* ARMv5TE: Preload-Cache
9122 MP Extensions: Preload for write
9126 Syntactically, like LDR with B=1, W=0, L=1. */
9131 constraint (!inst.operands[0].isreg,
9132 _("'[' expected after PLD mnemonic"));
9133 constraint (inst.operands[0].postind,
9134 _("post-indexed expression used in preload instruction"));
9135 constraint (inst.operands[0].writeback,
9136 _("writeback used in preload instruction"));
9137 constraint (!inst.operands[0].preind,
9138 _("unindexed addressing used in preload instruction"));
9139 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9142 /* ARMv7: PLI <addr_mode> */
9146 constraint (!inst.operands[0].isreg,
9147 _("'[' expected after PLI mnemonic"));
9148 constraint (inst.operands[0].postind,
9149 _("post-indexed expression used in preload instruction"));
9150 constraint (inst.operands[0].writeback,
9151 _("writeback used in preload instruction"));
9152 constraint (!inst.operands[0].preind,
9153 _("unindexed addressing used in preload instruction"));
9154 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9155 inst.instruction &= ~PRE_INDEX;
9161 constraint (inst.operands[0].writeback,
9162 _("push/pop do not support {reglist}^"));
9163 inst.operands[1] = inst.operands[0];
9164 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9165 inst.operands[0].isreg = 1;
9166 inst.operands[0].writeback = 1;
9167 inst.operands[0].reg = REG_SP;
9168 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
9171 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9172 word at the specified address and the following word
9174 Unconditionally executed.
9175 Error if Rn is R15. */
9180 inst.instruction |= inst.operands[0].reg << 16;
9181 if (inst.operands[0].writeback)
9182 inst.instruction |= WRITE_BACK;
9185 /* ARM V6 ssat (argument parse). */
9190 inst.instruction |= inst.operands[0].reg << 12;
9191 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9192 inst.instruction |= inst.operands[2].reg;
9194 if (inst.operands[3].present)
9195 encode_arm_shift (3);
9198 /* ARM V6 usat (argument parse). */
9203 inst.instruction |= inst.operands[0].reg << 12;
9204 inst.instruction |= inst.operands[1].imm << 16;
9205 inst.instruction |= inst.operands[2].reg;
9207 if (inst.operands[3].present)
9208 encode_arm_shift (3);
9211 /* ARM V6 ssat16 (argument parse). */
9216 inst.instruction |= inst.operands[0].reg << 12;
9217 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9218 inst.instruction |= inst.operands[2].reg;
9224 inst.instruction |= inst.operands[0].reg << 12;
9225 inst.instruction |= inst.operands[1].imm << 16;
9226 inst.instruction |= inst.operands[2].reg;
9229 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9230 preserving the other bits.
9232 setend <endian_specifier>, where <endian_specifier> is either
9238 if (warn_on_deprecated
9239 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9240 as_tsktsk (_("setend use is deprecated for ARMv8"));
9242 if (inst.operands[0].imm)
9243 inst.instruction |= 0x200;
9249 unsigned int Rm = (inst.operands[1].present
9250 ? inst.operands[1].reg
9251 : inst.operands[0].reg);
9253 inst.instruction |= inst.operands[0].reg << 12;
9254 inst.instruction |= Rm;
9255 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
9257 inst.instruction |= inst.operands[2].reg << 8;
9258 inst.instruction |= SHIFT_BY_REG;
9259 /* PR 12854: Error on extraneous shifts. */
9260 constraint (inst.operands[2].shifted,
9261 _("extraneous shift as part of operand to shift insn"));
9264 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
9270 inst.reloc.type = BFD_RELOC_ARM_SMC;
9271 inst.reloc.pc_rel = 0;
9277 inst.reloc.type = BFD_RELOC_ARM_HVC;
9278 inst.reloc.pc_rel = 0;
9284 inst.reloc.type = BFD_RELOC_ARM_SWI;
9285 inst.reloc.pc_rel = 0;
9291 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9292 _("selected processor does not support SETPAN instruction"));
9294 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
9300 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
9301 _("selected processor does not support SETPAN instruction"));
9303 inst.instruction |= (inst.operands[0].imm << 3);
9306 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9307 SMLAxy{cond} Rd,Rm,Rs,Rn
9308 SMLAWy{cond} Rd,Rm,Rs,Rn
9309 Error if any register is R15. */
9314 inst.instruction |= inst.operands[0].reg << 16;
9315 inst.instruction |= inst.operands[1].reg;
9316 inst.instruction |= inst.operands[2].reg << 8;
9317 inst.instruction |= inst.operands[3].reg << 12;
9320 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9321 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9322 Error if any register is R15.
9323 Warning if Rdlo == Rdhi. */
9328 inst.instruction |= inst.operands[0].reg << 12;
9329 inst.instruction |= inst.operands[1].reg << 16;
9330 inst.instruction |= inst.operands[2].reg;
9331 inst.instruction |= inst.operands[3].reg << 8;
9333 if (inst.operands[0].reg == inst.operands[1].reg)
9334 as_tsktsk (_("rdhi and rdlo must be different"));
9337 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9338 SMULxy{cond} Rd,Rm,Rs
9339 Error if any register is R15. */
9344 inst.instruction |= inst.operands[0].reg << 16;
9345 inst.instruction |= inst.operands[1].reg;
9346 inst.instruction |= inst.operands[2].reg << 8;
9349 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9350 the same for both ARM and Thumb-2. */
9357 if (inst.operands[0].present)
9359 reg = inst.operands[0].reg;
9360 constraint (reg != REG_SP, _("SRS base register must be r13"));
9365 inst.instruction |= reg << 16;
9366 inst.instruction |= inst.operands[1].imm;
9367 if (inst.operands[0].writeback || inst.operands[1].writeback)
9368 inst.instruction |= WRITE_BACK;
9371 /* ARM V6 strex (argument parse). */
9376 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9377 || inst.operands[2].postind || inst.operands[2].writeback
9378 || inst.operands[2].immisreg || inst.operands[2].shifted
9379 || inst.operands[2].negative
9380 /* See comment in do_ldrex(). */
9381 || (inst.operands[2].reg == REG_PC),
9384 constraint (inst.operands[0].reg == inst.operands[1].reg
9385 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9387 constraint (inst.reloc.exp.X_op != O_constant
9388 || inst.reloc.exp.X_add_number != 0,
9389 _("offset must be zero in ARM encoding"));
9391 inst.instruction |= inst.operands[0].reg << 12;
9392 inst.instruction |= inst.operands[1].reg;
9393 inst.instruction |= inst.operands[2].reg << 16;
9394 inst.reloc.type = BFD_RELOC_UNUSED;
9400 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9401 || inst.operands[2].postind || inst.operands[2].writeback
9402 || inst.operands[2].immisreg || inst.operands[2].shifted
9403 || inst.operands[2].negative,
9406 constraint (inst.operands[0].reg == inst.operands[1].reg
9407 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9415 constraint (inst.operands[1].reg % 2 != 0,
9416 _("even register required"));
9417 constraint (inst.operands[2].present
9418 && inst.operands[2].reg != inst.operands[1].reg + 1,
9419 _("can only store two consecutive registers"));
9420 /* If op 2 were present and equal to PC, this function wouldn't
9421 have been called in the first place. */
9422 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
9424 constraint (inst.operands[0].reg == inst.operands[1].reg
9425 || inst.operands[0].reg == inst.operands[1].reg + 1
9426 || inst.operands[0].reg == inst.operands[3].reg,
9429 inst.instruction |= inst.operands[0].reg << 12;
9430 inst.instruction |= inst.operands[1].reg;
9431 inst.instruction |= inst.operands[3].reg << 16;
9438 constraint (inst.operands[0].reg == inst.operands[1].reg
9439 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9447 constraint (inst.operands[0].reg == inst.operands[1].reg
9448 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9453 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9454 extends it to 32-bits, and adds the result to a value in another
9455 register. You can specify a rotation by 0, 8, 16, or 24 bits
9456 before extracting the 16-bit value.
9457 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9458 Condition defaults to COND_ALWAYS.
9459 Error if any register uses R15. */
9464 inst.instruction |= inst.operands[0].reg << 12;
9465 inst.instruction |= inst.operands[1].reg << 16;
9466 inst.instruction |= inst.operands[2].reg;
9467 inst.instruction |= inst.operands[3].imm << 10;
9472 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9473 Condition defaults to COND_ALWAYS.
9474 Error if any register uses R15. */
9479 inst.instruction |= inst.operands[0].reg << 12;
9480 inst.instruction |= inst.operands[1].reg;
9481 inst.instruction |= inst.operands[2].imm << 10;
9484 /* VFP instructions. In a logical order: SP variant first, monad
9485 before dyad, arithmetic then move then load/store. */
9488 do_vfp_sp_monadic (void)
9490 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9491 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9495 do_vfp_sp_dyadic (void)
9497 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9498 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9499 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9503 do_vfp_sp_compare_z (void)
9505 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9509 do_vfp_dp_sp_cvt (void)
9511 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9512 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
9516 do_vfp_sp_dp_cvt (void)
9518 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9519 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9523 do_vfp_reg_from_sp (void)
9525 inst.instruction |= inst.operands[0].reg << 12;
9526 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9530 do_vfp_reg2_from_sp2 (void)
9532 constraint (inst.operands[2].imm != 2,
9533 _("only two consecutive VFP SP registers allowed here"));
9534 inst.instruction |= inst.operands[0].reg << 12;
9535 inst.instruction |= inst.operands[1].reg << 16;
9536 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
9540 do_vfp_sp_from_reg (void)
9542 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
9543 inst.instruction |= inst.operands[1].reg << 12;
9547 do_vfp_sp2_from_reg2 (void)
9549 constraint (inst.operands[0].imm != 2,
9550 _("only two consecutive VFP SP registers allowed here"));
9551 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
9552 inst.instruction |= inst.operands[1].reg << 12;
9553 inst.instruction |= inst.operands[2].reg << 16;
9557 do_vfp_sp_ldst (void)
9559 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9560 encode_arm_cp_address (1, FALSE, TRUE, 0);
9564 do_vfp_dp_ldst (void)
9566 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9567 encode_arm_cp_address (1, FALSE, TRUE, 0);
9572 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
9574 if (inst.operands[0].writeback)
9575 inst.instruction |= WRITE_BACK;
9577 constraint (ldstm_type != VFP_LDSTMIA,
9578 _("this addressing mode requires base-register writeback"));
9579 inst.instruction |= inst.operands[0].reg << 16;
9580 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
9581 inst.instruction |= inst.operands[1].imm;
9585 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
9589 if (inst.operands[0].writeback)
9590 inst.instruction |= WRITE_BACK;
9592 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9593 _("this addressing mode requires base-register writeback"));
9595 inst.instruction |= inst.operands[0].reg << 16;
9596 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9598 count = inst.operands[1].imm << 1;
9599 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9602 inst.instruction |= count;
9606 do_vfp_sp_ldstmia (void)
9608 vfp_sp_ldstm (VFP_LDSTMIA);
9612 do_vfp_sp_ldstmdb (void)
9614 vfp_sp_ldstm (VFP_LDSTMDB);
9618 do_vfp_dp_ldstmia (void)
9620 vfp_dp_ldstm (VFP_LDSTMIA);
9624 do_vfp_dp_ldstmdb (void)
9626 vfp_dp_ldstm (VFP_LDSTMDB);
9630 do_vfp_xp_ldstmia (void)
9632 vfp_dp_ldstm (VFP_LDSTMIAX);
9636 do_vfp_xp_ldstmdb (void)
9638 vfp_dp_ldstm (VFP_LDSTMDBX);
9642 do_vfp_dp_rd_rm (void)
9644 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9645 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9649 do_vfp_dp_rn_rd (void)
9651 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9652 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9656 do_vfp_dp_rd_rn (void)
9658 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9659 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9663 do_vfp_dp_rd_rn_rm (void)
9665 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9666 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9667 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9673 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9677 do_vfp_dp_rm_rd_rn (void)
9679 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9680 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9681 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9684 /* VFPv3 instructions. */
9686 do_vfp_sp_const (void)
9688 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9689 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9690 inst.instruction |= (inst.operands[1].imm & 0x0f);
9694 do_vfp_dp_const (void)
9696 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9697 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9698 inst.instruction |= (inst.operands[1].imm & 0x0f);
9702 vfp_conv (int srcsize)
9704 int immbits = srcsize - inst.operands[1].imm;
9706 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9708 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9709 i.e. immbits must be in range 0 - 16. */
9710 inst.error = _("immediate value out of range, expected range [0, 16]");
9713 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
9715 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9716 i.e. immbits must be in range 0 - 31. */
9717 inst.error = _("immediate value out of range, expected range [1, 32]");
9721 inst.instruction |= (immbits & 1) << 5;
9722 inst.instruction |= (immbits >> 1);
9726 do_vfp_sp_conv_16 (void)
9728 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9733 do_vfp_dp_conv_16 (void)
9735 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9740 do_vfp_sp_conv_32 (void)
9742 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9747 do_vfp_dp_conv_32 (void)
9749 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9753 /* FPA instructions. Also in a logical order. */
9758 inst.instruction |= inst.operands[0].reg << 16;
9759 inst.instruction |= inst.operands[1].reg;
9763 do_fpa_ldmstm (void)
9765 inst.instruction |= inst.operands[0].reg << 12;
9766 switch (inst.operands[1].imm)
9768 case 1: inst.instruction |= CP_T_X; break;
9769 case 2: inst.instruction |= CP_T_Y; break;
9770 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9775 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9777 /* The instruction specified "ea" or "fd", so we can only accept
9778 [Rn]{!}. The instruction does not really support stacking or
9779 unstacking, so we have to emulate these by setting appropriate
9780 bits and offsets. */
9781 constraint (inst.reloc.exp.X_op != O_constant
9782 || inst.reloc.exp.X_add_number != 0,
9783 _("this instruction does not support indexing"));
9785 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9786 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
9788 if (!(inst.instruction & INDEX_UP))
9789 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
9791 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9793 inst.operands[2].preind = 0;
9794 inst.operands[2].postind = 1;
9798 encode_arm_cp_address (2, TRUE, TRUE, 0);
9801 /* iWMMXt instructions: strictly in alphabetical order. */
9804 do_iwmmxt_tandorc (void)
9806 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9810 do_iwmmxt_textrc (void)
9812 inst.instruction |= inst.operands[0].reg << 12;
9813 inst.instruction |= inst.operands[1].imm;
9817 do_iwmmxt_textrm (void)
9819 inst.instruction |= inst.operands[0].reg << 12;
9820 inst.instruction |= inst.operands[1].reg << 16;
9821 inst.instruction |= inst.operands[2].imm;
9825 do_iwmmxt_tinsr (void)
9827 inst.instruction |= inst.operands[0].reg << 16;
9828 inst.instruction |= inst.operands[1].reg << 12;
9829 inst.instruction |= inst.operands[2].imm;
9833 do_iwmmxt_tmia (void)
9835 inst.instruction |= inst.operands[0].reg << 5;
9836 inst.instruction |= inst.operands[1].reg;
9837 inst.instruction |= inst.operands[2].reg << 12;
9841 do_iwmmxt_waligni (void)
9843 inst.instruction |= inst.operands[0].reg << 12;
9844 inst.instruction |= inst.operands[1].reg << 16;
9845 inst.instruction |= inst.operands[2].reg;
9846 inst.instruction |= inst.operands[3].imm << 20;
9850 do_iwmmxt_wmerge (void)
9852 inst.instruction |= inst.operands[0].reg << 12;
9853 inst.instruction |= inst.operands[1].reg << 16;
9854 inst.instruction |= inst.operands[2].reg;
9855 inst.instruction |= inst.operands[3].imm << 21;
9859 do_iwmmxt_wmov (void)
9861 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9862 inst.instruction |= inst.operands[0].reg << 12;
9863 inst.instruction |= inst.operands[1].reg << 16;
9864 inst.instruction |= inst.operands[1].reg;
9868 do_iwmmxt_wldstbh (void)
9871 inst.instruction |= inst.operands[0].reg << 12;
9873 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9875 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9876 encode_arm_cp_address (1, TRUE, FALSE, reloc);
9880 do_iwmmxt_wldstw (void)
9882 /* RIWR_RIWC clears .isreg for a control register. */
9883 if (!inst.operands[0].isreg)
9885 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9886 inst.instruction |= 0xf0000000;
9889 inst.instruction |= inst.operands[0].reg << 12;
9890 encode_arm_cp_address (1, TRUE, TRUE, 0);
9894 do_iwmmxt_wldstd (void)
9896 inst.instruction |= inst.operands[0].reg << 12;
9897 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9898 && inst.operands[1].immisreg)
9900 inst.instruction &= ~0x1a000ff;
9901 inst.instruction |= (0xf << 28);
9902 if (inst.operands[1].preind)
9903 inst.instruction |= PRE_INDEX;
9904 if (!inst.operands[1].negative)
9905 inst.instruction |= INDEX_UP;
9906 if (inst.operands[1].writeback)
9907 inst.instruction |= WRITE_BACK;
9908 inst.instruction |= inst.operands[1].reg << 16;
9909 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9910 inst.instruction |= inst.operands[1].imm;
9913 encode_arm_cp_address (1, TRUE, FALSE, 0);
9917 do_iwmmxt_wshufh (void)
9919 inst.instruction |= inst.operands[0].reg << 12;
9920 inst.instruction |= inst.operands[1].reg << 16;
9921 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9922 inst.instruction |= (inst.operands[2].imm & 0x0f);
9926 do_iwmmxt_wzero (void)
9928 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9929 inst.instruction |= inst.operands[0].reg;
9930 inst.instruction |= inst.operands[0].reg << 12;
9931 inst.instruction |= inst.operands[0].reg << 16;
9935 do_iwmmxt_wrwrwr_or_imm5 (void)
9937 if (inst.operands[2].isreg)
9940 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9941 _("immediate operand requires iWMMXt2"));
9943 if (inst.operands[2].imm == 0)
9945 switch ((inst.instruction >> 20) & 0xf)
9951 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9952 inst.operands[2].imm = 16;
9953 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9959 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9960 inst.operands[2].imm = 32;
9961 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9968 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9970 wrn = (inst.instruction >> 16) & 0xf;
9971 inst.instruction &= 0xff0fff0f;
9972 inst.instruction |= wrn;
9973 /* Bail out here; the instruction is now assembled. */
9978 /* Map 32 -> 0, etc. */
9979 inst.operands[2].imm &= 0x1f;
9980 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9984 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9985 operations first, then control, shift, and load/store. */
9987 /* Insns like "foo X,Y,Z". */
9990 do_mav_triple (void)
9992 inst.instruction |= inst.operands[0].reg << 16;
9993 inst.instruction |= inst.operands[1].reg;
9994 inst.instruction |= inst.operands[2].reg << 12;
9997 /* Insns like "foo W,X,Y,Z".
9998 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10003 inst.instruction |= inst.operands[0].reg << 5;
10004 inst.instruction |= inst.operands[1].reg << 12;
10005 inst.instruction |= inst.operands[2].reg << 16;
10006 inst.instruction |= inst.operands[3].reg;
10009 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10011 do_mav_dspsc (void)
10013 inst.instruction |= inst.operands[1].reg << 12;
10016 /* Maverick shift immediate instructions.
10017 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10018 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10021 do_mav_shift (void)
10023 int imm = inst.operands[2].imm;
10025 inst.instruction |= inst.operands[0].reg << 12;
10026 inst.instruction |= inst.operands[1].reg << 16;
10028 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10029 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10030 Bit 4 should be 0. */
10031 imm = (imm & 0xf) | ((imm & 0x70) << 1);
10033 inst.instruction |= imm;
10036 /* XScale instructions. Also sorted arithmetic before move. */
10038 /* Xscale multiply-accumulate (argument parse)
10041 MIAxycc acc0,Rm,Rs. */
10046 inst.instruction |= inst.operands[1].reg;
10047 inst.instruction |= inst.operands[2].reg << 12;
10050 /* Xscale move-accumulator-register (argument parse)
10052 MARcc acc0,RdLo,RdHi. */
10057 inst.instruction |= inst.operands[1].reg << 12;
10058 inst.instruction |= inst.operands[2].reg << 16;
10061 /* Xscale move-register-accumulator (argument parse)
10063 MRAcc RdLo,RdHi,acc0. */
10068 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
10069 inst.instruction |= inst.operands[0].reg << 12;
10070 inst.instruction |= inst.operands[1].reg << 16;
10073 /* Encoding functions relevant only to Thumb. */
10075 /* inst.operands[i] is a shifted-register operand; encode
10076 it into inst.instruction in the format used by Thumb32. */
10079 encode_thumb32_shifted_operand (int i)
10081 unsigned int value = inst.reloc.exp.X_add_number;
10082 unsigned int shift = inst.operands[i].shift_kind;
10084 constraint (inst.operands[i].immisreg,
10085 _("shift by register not allowed in thumb mode"));
10086 inst.instruction |= inst.operands[i].reg;
10087 if (shift == SHIFT_RRX)
10088 inst.instruction |= SHIFT_ROR << 4;
10091 constraint (inst.reloc.exp.X_op != O_constant,
10092 _("expression too complex"));
10094 constraint (value > 32
10095 || (value == 32 && (shift == SHIFT_LSL
10096 || shift == SHIFT_ROR)),
10097 _("shift expression is too large"));
10101 else if (value == 32)
10104 inst.instruction |= shift << 4;
10105 inst.instruction |= (value & 0x1c) << 10;
10106 inst.instruction |= (value & 0x03) << 6;
10111 /* inst.operands[i] was set up by parse_address. Encode it into a
10112 Thumb32 format load or store instruction. Reject forms that cannot
10113 be used with such instructions. If is_t is true, reject forms that
10114 cannot be used with a T instruction; if is_d is true, reject forms
10115 that cannot be used with a D instruction. If it is a store insn,
10116 reject PC in Rn. */
10119 encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
10121 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
10123 constraint (!inst.operands[i].isreg,
10124 _("Instruction does not support =N addresses"));
10126 inst.instruction |= inst.operands[i].reg << 16;
10127 if (inst.operands[i].immisreg)
10129 constraint (is_pc, BAD_PC_ADDRESSING);
10130 constraint (is_t || is_d, _("cannot use register index with this instruction"));
10131 constraint (inst.operands[i].negative,
10132 _("Thumb does not support negative register indexing"));
10133 constraint (inst.operands[i].postind,
10134 _("Thumb does not support register post-indexing"));
10135 constraint (inst.operands[i].writeback,
10136 _("Thumb does not support register indexing with writeback"));
10137 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
10138 _("Thumb supports only LSL in shifted register indexing"));
10140 inst.instruction |= inst.operands[i].imm;
10141 if (inst.operands[i].shifted)
10143 constraint (inst.reloc.exp.X_op != O_constant,
10144 _("expression too complex"));
10145 constraint (inst.reloc.exp.X_add_number < 0
10146 || inst.reloc.exp.X_add_number > 3,
10147 _("shift out of range"));
10148 inst.instruction |= inst.reloc.exp.X_add_number << 4;
10150 inst.reloc.type = BFD_RELOC_UNUSED;
10152 else if (inst.operands[i].preind)
10154 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
10155 constraint (is_t && inst.operands[i].writeback,
10156 _("cannot use writeback with this instruction"));
10157 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10158 BAD_PC_ADDRESSING);
10162 inst.instruction |= 0x01000000;
10163 if (inst.operands[i].writeback)
10164 inst.instruction |= 0x00200000;
10168 inst.instruction |= 0x00000c00;
10169 if (inst.operands[i].writeback)
10170 inst.instruction |= 0x00000100;
10172 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10174 else if (inst.operands[i].postind)
10176 gas_assert (inst.operands[i].writeback);
10177 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10178 constraint (is_t, _("cannot use post-indexing with this instruction"));
10181 inst.instruction |= 0x00200000;
10183 inst.instruction |= 0x00000900;
10184 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10186 else /* unindexed - only for coprocessor */
10187 inst.error = _("instruction does not accept unindexed addressing");
10190 /* Table of Thumb instructions which exist in both 16- and 32-bit
10191 encodings (the latter only in post-V6T2 cores). The index is the
10192 value used in the insns table below. When there is more than one
10193 possible 16-bit encoding for the instruction, this table always
10195 Also contains several pseudo-instructions used during relaxation. */
10196 #define T16_32_TAB \
10197 X(_adc, 4140, eb400000), \
10198 X(_adcs, 4140, eb500000), \
10199 X(_add, 1c00, eb000000), \
10200 X(_adds, 1c00, eb100000), \
10201 X(_addi, 0000, f1000000), \
10202 X(_addis, 0000, f1100000), \
10203 X(_add_pc,000f, f20f0000), \
10204 X(_add_sp,000d, f10d0000), \
10205 X(_adr, 000f, f20f0000), \
10206 X(_and, 4000, ea000000), \
10207 X(_ands, 4000, ea100000), \
10208 X(_asr, 1000, fa40f000), \
10209 X(_asrs, 1000, fa50f000), \
10210 X(_b, e000, f000b000), \
10211 X(_bcond, d000, f0008000), \
10212 X(_bic, 4380, ea200000), \
10213 X(_bics, 4380, ea300000), \
10214 X(_cmn, 42c0, eb100f00), \
10215 X(_cmp, 2800, ebb00f00), \
10216 X(_cpsie, b660, f3af8400), \
10217 X(_cpsid, b670, f3af8600), \
10218 X(_cpy, 4600, ea4f0000), \
10219 X(_dec_sp,80dd, f1ad0d00), \
10220 X(_eor, 4040, ea800000), \
10221 X(_eors, 4040, ea900000), \
10222 X(_inc_sp,00dd, f10d0d00), \
10223 X(_ldmia, c800, e8900000), \
10224 X(_ldr, 6800, f8500000), \
10225 X(_ldrb, 7800, f8100000), \
10226 X(_ldrh, 8800, f8300000), \
10227 X(_ldrsb, 5600, f9100000), \
10228 X(_ldrsh, 5e00, f9300000), \
10229 X(_ldr_pc,4800, f85f0000), \
10230 X(_ldr_pc2,4800, f85f0000), \
10231 X(_ldr_sp,9800, f85d0000), \
10232 X(_lsl, 0000, fa00f000), \
10233 X(_lsls, 0000, fa10f000), \
10234 X(_lsr, 0800, fa20f000), \
10235 X(_lsrs, 0800, fa30f000), \
10236 X(_mov, 2000, ea4f0000), \
10237 X(_movs, 2000, ea5f0000), \
10238 X(_mul, 4340, fb00f000), \
10239 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10240 X(_mvn, 43c0, ea6f0000), \
10241 X(_mvns, 43c0, ea7f0000), \
10242 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10243 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10244 X(_orr, 4300, ea400000), \
10245 X(_orrs, 4300, ea500000), \
10246 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10247 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10248 X(_rev, ba00, fa90f080), \
10249 X(_rev16, ba40, fa90f090), \
10250 X(_revsh, bac0, fa90f0b0), \
10251 X(_ror, 41c0, fa60f000), \
10252 X(_rors, 41c0, fa70f000), \
10253 X(_sbc, 4180, eb600000), \
10254 X(_sbcs, 4180, eb700000), \
10255 X(_stmia, c000, e8800000), \
10256 X(_str, 6000, f8400000), \
10257 X(_strb, 7000, f8000000), \
10258 X(_strh, 8000, f8200000), \
10259 X(_str_sp,9000, f84d0000), \
10260 X(_sub, 1e00, eba00000), \
10261 X(_subs, 1e00, ebb00000), \
10262 X(_subi, 8000, f1a00000), \
10263 X(_subis, 8000, f1b00000), \
10264 X(_sxtb, b240, fa4ff080), \
10265 X(_sxth, b200, fa0ff080), \
10266 X(_tst, 4200, ea100f00), \
10267 X(_uxtb, b2c0, fa5ff080), \
10268 X(_uxth, b280, fa1ff080), \
10269 X(_nop, bf00, f3af8000), \
10270 X(_yield, bf10, f3af8001), \
10271 X(_wfe, bf20, f3af8002), \
10272 X(_wfi, bf30, f3af8003), \
10273 X(_sev, bf40, f3af8004), \
10274 X(_sevl, bf50, f3af8005), \
10275 X(_udf, de00, f7f0a000)
10277 /* To catch errors in encoding functions, the codes are all offset by
10278 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10279 as 16-bit instructions. */
10280 #define X(a,b,c) T_MNEM##a
10281 enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10284 #define X(a,b,c) 0x##b
10285 static const unsigned short thumb_op16[] = { T16_32_TAB };
10286 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10289 #define X(a,b,c) 0x##c
10290 static const unsigned int thumb_op32[] = { T16_32_TAB };
10291 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10292 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10296 /* Thumb instruction encoders, in alphabetical order. */
10298 /* ADDW or SUBW. */
10301 do_t_add_sub_w (void)
10305 Rd = inst.operands[0].reg;
10306 Rn = inst.operands[1].reg;
10308 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10309 is the SP-{plus,minus}-immediate form of the instruction. */
10311 constraint (Rd == REG_PC, BAD_PC);
10313 reject_bad_reg (Rd);
10315 inst.instruction |= (Rn << 16) | (Rd << 8);
10316 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10319 /* Parse an add or subtract instruction. We get here with inst.instruction
10320 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10323 do_t_add_sub (void)
10327 Rd = inst.operands[0].reg;
10328 Rs = (inst.operands[1].present
10329 ? inst.operands[1].reg /* Rd, Rs, foo */
10330 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10333 set_it_insn_type_last ();
10335 if (unified_syntax)
10338 bfd_boolean narrow;
10341 flags = (inst.instruction == T_MNEM_adds
10342 || inst.instruction == T_MNEM_subs);
10344 narrow = !in_it_block ();
10346 narrow = in_it_block ();
10347 if (!inst.operands[2].isreg)
10351 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10353 add = (inst.instruction == T_MNEM_add
10354 || inst.instruction == T_MNEM_adds);
10356 if (inst.size_req != 4)
10358 /* Attempt to use a narrow opcode, with relaxation if
10360 if (Rd == REG_SP && Rs == REG_SP && !flags)
10361 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10362 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10363 opcode = T_MNEM_add_sp;
10364 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10365 opcode = T_MNEM_add_pc;
10366 else if (Rd <= 7 && Rs <= 7 && narrow)
10369 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10371 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10375 inst.instruction = THUMB_OP16(opcode);
10376 inst.instruction |= (Rd << 4) | Rs;
10377 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10378 if (inst.size_req != 2)
10379 inst.relax = opcode;
10382 constraint (inst.size_req == 2, BAD_HIREG);
10384 if (inst.size_req == 4
10385 || (inst.size_req != 2 && !opcode))
10389 constraint (add, BAD_PC);
10390 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10391 _("only SUBS PC, LR, #const allowed"));
10392 constraint (inst.reloc.exp.X_op != O_constant,
10393 _("expression too complex"));
10394 constraint (inst.reloc.exp.X_add_number < 0
10395 || inst.reloc.exp.X_add_number > 0xff,
10396 _("immediate value out of range"));
10397 inst.instruction = T2_SUBS_PC_LR
10398 | inst.reloc.exp.X_add_number;
10399 inst.reloc.type = BFD_RELOC_UNUSED;
10402 else if (Rs == REG_PC)
10404 /* Always use addw/subw. */
10405 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10406 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10410 inst.instruction = THUMB_OP32 (inst.instruction);
10411 inst.instruction = (inst.instruction & 0xe1ffffff)
10414 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10416 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10418 inst.instruction |= Rd << 8;
10419 inst.instruction |= Rs << 16;
10424 unsigned int value = inst.reloc.exp.X_add_number;
10425 unsigned int shift = inst.operands[2].shift_kind;
10427 Rn = inst.operands[2].reg;
10428 /* See if we can do this with a 16-bit instruction. */
10429 if (!inst.operands[2].shifted && inst.size_req != 4)
10431 if (Rd > 7 || Rs > 7 || Rn > 7)
10436 inst.instruction = ((inst.instruction == T_MNEM_adds
10437 || inst.instruction == T_MNEM_add)
10439 : T_OPCODE_SUB_R3);
10440 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10444 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
10446 /* Thumb-1 cores (except v6-M) require at least one high
10447 register in a narrow non flag setting add. */
10448 if (Rd > 7 || Rn > 7
10449 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10450 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
10457 inst.instruction = T_OPCODE_ADD_HI;
10458 inst.instruction |= (Rd & 8) << 4;
10459 inst.instruction |= (Rd & 7);
10460 inst.instruction |= Rn << 3;
10466 constraint (Rd == REG_PC, BAD_PC);
10467 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10468 constraint (Rs == REG_PC, BAD_PC);
10469 reject_bad_reg (Rn);
10471 /* If we get here, it can't be done in 16 bits. */
10472 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10473 _("shift must be constant"));
10474 inst.instruction = THUMB_OP32 (inst.instruction);
10475 inst.instruction |= Rd << 8;
10476 inst.instruction |= Rs << 16;
10477 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10478 _("shift value over 3 not allowed in thumb mode"));
10479 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10480 _("only LSL shift allowed in thumb mode"));
10481 encode_thumb32_shifted_operand (2);
10486 constraint (inst.instruction == T_MNEM_adds
10487 || inst.instruction == T_MNEM_subs,
10490 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
10492 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10493 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10496 inst.instruction = (inst.instruction == T_MNEM_add
10497 ? 0x0000 : 0x8000);
10498 inst.instruction |= (Rd << 4) | Rs;
10499 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10503 Rn = inst.operands[2].reg;
10504 constraint (inst.operands[2].shifted, _("unshifted register required"));
10506 /* We now have Rd, Rs, and Rn set to registers. */
10507 if (Rd > 7 || Rs > 7 || Rn > 7)
10509 /* Can't do this for SUB. */
10510 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10511 inst.instruction = T_OPCODE_ADD_HI;
10512 inst.instruction |= (Rd & 8) << 4;
10513 inst.instruction |= (Rd & 7);
10515 inst.instruction |= Rn << 3;
10517 inst.instruction |= Rs << 3;
10519 constraint (1, _("dest must overlap one source register"));
10523 inst.instruction = (inst.instruction == T_MNEM_add
10524 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10525 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10535 Rd = inst.operands[0].reg;
10536 reject_bad_reg (Rd);
10538 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
10540 /* Defer to section relaxation. */
10541 inst.relax = inst.instruction;
10542 inst.instruction = THUMB_OP16 (inst.instruction);
10543 inst.instruction |= Rd << 4;
10545 else if (unified_syntax && inst.size_req != 2)
10547 /* Generate a 32-bit opcode. */
10548 inst.instruction = THUMB_OP32 (inst.instruction);
10549 inst.instruction |= Rd << 8;
10550 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10551 inst.reloc.pc_rel = 1;
10555 /* Generate a 16-bit opcode. */
10556 inst.instruction = THUMB_OP16 (inst.instruction);
10557 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10558 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10559 inst.reloc.pc_rel = 1;
10561 inst.instruction |= Rd << 4;
10565 /* Arithmetic instructions for which there is just one 16-bit
10566 instruction encoding, and it allows only two low registers.
10567 For maximal compatibility with ARM syntax, we allow three register
10568 operands even when Thumb-32 instructions are not available, as long
10569 as the first two are identical. For instance, both "sbc r0,r1" and
10570 "sbc r0,r0,r1" are allowed. */
10576 Rd = inst.operands[0].reg;
10577 Rs = (inst.operands[1].present
10578 ? inst.operands[1].reg /* Rd, Rs, foo */
10579 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10580 Rn = inst.operands[2].reg;
10582 reject_bad_reg (Rd);
10583 reject_bad_reg (Rs);
10584 if (inst.operands[2].isreg)
10585 reject_bad_reg (Rn);
10587 if (unified_syntax)
10589 if (!inst.operands[2].isreg)
10591 /* For an immediate, we always generate a 32-bit opcode;
10592 section relaxation will shrink it later if possible. */
10593 inst.instruction = THUMB_OP32 (inst.instruction);
10594 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10595 inst.instruction |= Rd << 8;
10596 inst.instruction |= Rs << 16;
10597 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10601 bfd_boolean narrow;
10603 /* See if we can do this with a 16-bit instruction. */
10604 if (THUMB_SETS_FLAGS (inst.instruction))
10605 narrow = !in_it_block ();
10607 narrow = in_it_block ();
10609 if (Rd > 7 || Rn > 7 || Rs > 7)
10611 if (inst.operands[2].shifted)
10613 if (inst.size_req == 4)
10619 inst.instruction = THUMB_OP16 (inst.instruction);
10620 inst.instruction |= Rd;
10621 inst.instruction |= Rn << 3;
10625 /* If we get here, it can't be done in 16 bits. */
10626 constraint (inst.operands[2].shifted
10627 && inst.operands[2].immisreg,
10628 _("shift must be constant"));
10629 inst.instruction = THUMB_OP32 (inst.instruction);
10630 inst.instruction |= Rd << 8;
10631 inst.instruction |= Rs << 16;
10632 encode_thumb32_shifted_operand (2);
10637 /* On its face this is a lie - the instruction does set the
10638 flags. However, the only supported mnemonic in this mode
10639 says it doesn't. */
10640 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10642 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10643 _("unshifted register required"));
10644 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10645 constraint (Rd != Rs,
10646 _("dest and source1 must be the same register"));
10648 inst.instruction = THUMB_OP16 (inst.instruction);
10649 inst.instruction |= Rd;
10650 inst.instruction |= Rn << 3;
10654 /* Similarly, but for instructions where the arithmetic operation is
10655 commutative, so we can allow either of them to be different from
10656 the destination operand in a 16-bit instruction. For instance, all
10657 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10664 Rd = inst.operands[0].reg;
10665 Rs = (inst.operands[1].present
10666 ? inst.operands[1].reg /* Rd, Rs, foo */
10667 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10668 Rn = inst.operands[2].reg;
10670 reject_bad_reg (Rd);
10671 reject_bad_reg (Rs);
10672 if (inst.operands[2].isreg)
10673 reject_bad_reg (Rn);
10675 if (unified_syntax)
10677 if (!inst.operands[2].isreg)
10679 /* For an immediate, we always generate a 32-bit opcode;
10680 section relaxation will shrink it later if possible. */
10681 inst.instruction = THUMB_OP32 (inst.instruction);
10682 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10683 inst.instruction |= Rd << 8;
10684 inst.instruction |= Rs << 16;
10685 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10689 bfd_boolean narrow;
10691 /* See if we can do this with a 16-bit instruction. */
10692 if (THUMB_SETS_FLAGS (inst.instruction))
10693 narrow = !in_it_block ();
10695 narrow = in_it_block ();
10697 if (Rd > 7 || Rn > 7 || Rs > 7)
10699 if (inst.operands[2].shifted)
10701 if (inst.size_req == 4)
10708 inst.instruction = THUMB_OP16 (inst.instruction);
10709 inst.instruction |= Rd;
10710 inst.instruction |= Rn << 3;
10715 inst.instruction = THUMB_OP16 (inst.instruction);
10716 inst.instruction |= Rd;
10717 inst.instruction |= Rs << 3;
10722 /* If we get here, it can't be done in 16 bits. */
10723 constraint (inst.operands[2].shifted
10724 && inst.operands[2].immisreg,
10725 _("shift must be constant"));
10726 inst.instruction = THUMB_OP32 (inst.instruction);
10727 inst.instruction |= Rd << 8;
10728 inst.instruction |= Rs << 16;
10729 encode_thumb32_shifted_operand (2);
10734 /* On its face this is a lie - the instruction does set the
10735 flags. However, the only supported mnemonic in this mode
10736 says it doesn't. */
10737 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
10739 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10740 _("unshifted register required"));
10741 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10743 inst.instruction = THUMB_OP16 (inst.instruction);
10744 inst.instruction |= Rd;
10747 inst.instruction |= Rn << 3;
10749 inst.instruction |= Rs << 3;
10751 constraint (1, _("dest must overlap one source register"));
10759 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10760 constraint (msb > 32, _("bit-field extends past end of register"));
10761 /* The instruction encoding stores the LSB and MSB,
10762 not the LSB and width. */
10763 Rd = inst.operands[0].reg;
10764 reject_bad_reg (Rd);
10765 inst.instruction |= Rd << 8;
10766 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10767 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10768 inst.instruction |= msb - 1;
10777 Rd = inst.operands[0].reg;
10778 reject_bad_reg (Rd);
10780 /* #0 in second position is alternative syntax for bfc, which is
10781 the same instruction but with REG_PC in the Rm field. */
10782 if (!inst.operands[1].isreg)
10786 Rn = inst.operands[1].reg;
10787 reject_bad_reg (Rn);
10790 msb = inst.operands[2].imm + inst.operands[3].imm;
10791 constraint (msb > 32, _("bit-field extends past end of register"));
10792 /* The instruction encoding stores the LSB and MSB,
10793 not the LSB and width. */
10794 inst.instruction |= Rd << 8;
10795 inst.instruction |= Rn << 16;
10796 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10797 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10798 inst.instruction |= msb - 1;
10806 Rd = inst.operands[0].reg;
10807 Rn = inst.operands[1].reg;
10809 reject_bad_reg (Rd);
10810 reject_bad_reg (Rn);
10812 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10813 _("bit-field extends past end of register"));
10814 inst.instruction |= Rd << 8;
10815 inst.instruction |= Rn << 16;
10816 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10817 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10818 inst.instruction |= inst.operands[3].imm - 1;
10821 /* ARM V5 Thumb BLX (argument parse)
10822 BLX <target_addr> which is BLX(1)
10823 BLX <Rm> which is BLX(2)
10824 Unfortunately, there are two different opcodes for this mnemonic.
10825 So, the insns[].value is not used, and the code here zaps values
10826 into inst.instruction.
10828 ??? How to take advantage of the additional two bits of displacement
10829 available in Thumb32 mode? Need new relocation? */
10834 set_it_insn_type_last ();
10836 if (inst.operands[0].isreg)
10838 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10839 /* We have a register, so this is BLX(2). */
10840 inst.instruction |= inst.operands[0].reg << 3;
10844 /* No register. This must be BLX(1). */
10845 inst.instruction = 0xf000e800;
10846 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
10858 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10860 if (in_it_block ())
10862 /* Conditional branches inside IT blocks are encoded as unconditional
10864 cond = COND_ALWAYS;
10869 if (cond != COND_ALWAYS)
10870 opcode = T_MNEM_bcond;
10872 opcode = inst.instruction;
10875 && (inst.size_req == 4
10876 || (inst.size_req != 2
10877 && (inst.operands[0].hasreloc
10878 || inst.reloc.exp.X_op == O_constant))))
10880 inst.instruction = THUMB_OP32(opcode);
10881 if (cond == COND_ALWAYS)
10882 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
10885 gas_assert (cond != 0xF);
10886 inst.instruction |= cond << 22;
10887 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
10892 inst.instruction = THUMB_OP16(opcode);
10893 if (cond == COND_ALWAYS)
10894 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
10897 inst.instruction |= cond << 8;
10898 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
10900 /* Allow section relaxation. */
10901 if (unified_syntax && inst.size_req != 2)
10902 inst.relax = opcode;
10904 inst.reloc.type = reloc;
10905 inst.reloc.pc_rel = 1;
10908 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10909 between the two is the maximum immediate allowed - which is passed in
10912 do_t_bkpt_hlt1 (int range)
10914 constraint (inst.cond != COND_ALWAYS,
10915 _("instruction is always unconditional"));
10916 if (inst.operands[0].present)
10918 constraint (inst.operands[0].imm > range,
10919 _("immediate value out of range"));
10920 inst.instruction |= inst.operands[0].imm;
10923 set_it_insn_type (NEUTRAL_IT_INSN);
10929 do_t_bkpt_hlt1 (63);
10935 do_t_bkpt_hlt1 (255);
10939 do_t_branch23 (void)
10941 set_it_insn_type_last ();
10942 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
10944 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10945 this file. We used to simply ignore the PLT reloc type here --
10946 the branch encoding is now needed to deal with TLSCALL relocs.
10947 So if we see a PLT reloc now, put it back to how it used to be to
10948 keep the preexisting behaviour. */
10949 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10950 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
10952 #if defined(OBJ_COFF)
10953 /* If the destination of the branch is a defined symbol which does not have
10954 the THUMB_FUNC attribute, then we must be calling a function which has
10955 the (interfacearm) attribute. We look for the Thumb entry point to that
10956 function and change the branch to refer to that function instead. */
10957 if ( inst.reloc.exp.X_op == O_symbol
10958 && inst.reloc.exp.X_add_symbol != NULL
10959 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10960 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10961 inst.reloc.exp.X_add_symbol =
10962 find_real_start (inst.reloc.exp.X_add_symbol);
10969 set_it_insn_type_last ();
10970 inst.instruction |= inst.operands[0].reg << 3;
10971 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10972 should cause the alignment to be checked once it is known. This is
10973 because BX PC only works if the instruction is word aligned. */
10981 set_it_insn_type_last ();
10982 Rm = inst.operands[0].reg;
10983 reject_bad_reg (Rm);
10984 inst.instruction |= Rm << 16;
10993 Rd = inst.operands[0].reg;
10994 Rm = inst.operands[1].reg;
10996 reject_bad_reg (Rd);
10997 reject_bad_reg (Rm);
10999 inst.instruction |= Rd << 8;
11000 inst.instruction |= Rm << 16;
11001 inst.instruction |= Rm;
11007 set_it_insn_type (OUTSIDE_IT_INSN);
11008 inst.instruction |= inst.operands[0].imm;
11014 set_it_insn_type (OUTSIDE_IT_INSN);
11016 && (inst.operands[1].present || inst.size_req == 4)
11017 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
11019 unsigned int imod = (inst.instruction & 0x0030) >> 4;
11020 inst.instruction = 0xf3af8000;
11021 inst.instruction |= imod << 9;
11022 inst.instruction |= inst.operands[0].imm << 5;
11023 if (inst.operands[1].present)
11024 inst.instruction |= 0x100 | inst.operands[1].imm;
11028 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
11029 && (inst.operands[0].imm & 4),
11030 _("selected processor does not support 'A' form "
11031 "of this instruction"));
11032 constraint (inst.operands[1].present || inst.size_req == 4,
11033 _("Thumb does not support the 2-argument "
11034 "form of this instruction"));
11035 inst.instruction |= inst.operands[0].imm;
11039 /* THUMB CPY instruction (argument parse). */
11044 if (inst.size_req == 4)
11046 inst.instruction = THUMB_OP32 (T_MNEM_mov);
11047 inst.instruction |= inst.operands[0].reg << 8;
11048 inst.instruction |= inst.operands[1].reg;
11052 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
11053 inst.instruction |= (inst.operands[0].reg & 0x7);
11054 inst.instruction |= inst.operands[1].reg << 3;
11061 set_it_insn_type (OUTSIDE_IT_INSN);
11062 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11063 inst.instruction |= inst.operands[0].reg;
11064 inst.reloc.pc_rel = 1;
11065 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
11071 inst.instruction |= inst.operands[0].imm;
11077 unsigned Rd, Rn, Rm;
11079 Rd = inst.operands[0].reg;
11080 Rn = (inst.operands[1].present
11081 ? inst.operands[1].reg : Rd);
11082 Rm = inst.operands[2].reg;
11084 reject_bad_reg (Rd);
11085 reject_bad_reg (Rn);
11086 reject_bad_reg (Rm);
11088 inst.instruction |= Rd << 8;
11089 inst.instruction |= Rn << 16;
11090 inst.instruction |= Rm;
11096 if (unified_syntax && inst.size_req == 4)
11097 inst.instruction = THUMB_OP32 (inst.instruction);
11099 inst.instruction = THUMB_OP16 (inst.instruction);
11105 unsigned int cond = inst.operands[0].imm;
11107 set_it_insn_type (IT_INSN);
11108 now_it.mask = (inst.instruction & 0xf) | 0x10;
11110 now_it.warn_deprecated = FALSE;
11112 /* If the condition is a negative condition, invert the mask. */
11113 if ((cond & 0x1) == 0x0)
11115 unsigned int mask = inst.instruction & 0x000f;
11117 if ((mask & 0x7) == 0)
11119 /* No conversion needed. */
11120 now_it.block_length = 1;
11122 else if ((mask & 0x3) == 0)
11125 now_it.block_length = 2;
11127 else if ((mask & 0x1) == 0)
11130 now_it.block_length = 3;
11135 now_it.block_length = 4;
11138 inst.instruction &= 0xfff0;
11139 inst.instruction |= mask;
11142 inst.instruction |= cond << 4;
11145 /* Helper function used for both push/pop and ldm/stm. */
11147 encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11151 load = (inst.instruction & (1 << 20)) != 0;
11153 if (mask & (1 << 13))
11154 inst.error = _("SP not allowed in register list");
11156 if ((mask & (1 << base)) != 0
11158 inst.error = _("having the base register in the register list when "
11159 "using write back is UNPREDICTABLE");
11163 if (mask & (1 << 15))
11165 if (mask & (1 << 14))
11166 inst.error = _("LR and PC should not both be in register list");
11168 set_it_insn_type_last ();
11173 if (mask & (1 << 15))
11174 inst.error = _("PC not allowed in register list");
11177 if ((mask & (mask - 1)) == 0)
11179 /* Single register transfers implemented as str/ldr. */
11182 if (inst.instruction & (1 << 23))
11183 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11185 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11189 if (inst.instruction & (1 << 23))
11190 inst.instruction = 0x00800000; /* ia -> [base] */
11192 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11195 inst.instruction |= 0xf8400000;
11197 inst.instruction |= 0x00100000;
11199 mask = ffs (mask) - 1;
11202 else if (writeback)
11203 inst.instruction |= WRITE_BACK;
11205 inst.instruction |= mask;
11206 inst.instruction |= base << 16;
11212 /* This really doesn't seem worth it. */
11213 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11214 _("expression too complex"));
11215 constraint (inst.operands[1].writeback,
11216 _("Thumb load/store multiple does not support {reglist}^"));
11218 if (unified_syntax)
11220 bfd_boolean narrow;
11224 /* See if we can use a 16-bit instruction. */
11225 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11226 && inst.size_req != 4
11227 && !(inst.operands[1].imm & ~0xff))
11229 mask = 1 << inst.operands[0].reg;
11231 if (inst.operands[0].reg <= 7)
11233 if (inst.instruction == T_MNEM_stmia
11234 ? inst.operands[0].writeback
11235 : (inst.operands[0].writeback
11236 == !(inst.operands[1].imm & mask)))
11238 if (inst.instruction == T_MNEM_stmia
11239 && (inst.operands[1].imm & mask)
11240 && (inst.operands[1].imm & (mask - 1)))
11241 as_warn (_("value stored for r%d is UNKNOWN"),
11242 inst.operands[0].reg);
11244 inst.instruction = THUMB_OP16 (inst.instruction);
11245 inst.instruction |= inst.operands[0].reg << 8;
11246 inst.instruction |= inst.operands[1].imm;
11249 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11251 /* This means 1 register in reg list one of 3 situations:
11252 1. Instruction is stmia, but without writeback.
11253 2. lmdia without writeback, but with Rn not in
11255 3. ldmia with writeback, but with Rn in reglist.
11256 Case 3 is UNPREDICTABLE behaviour, so we handle
11257 case 1 and 2 which can be converted into a 16-bit
11258 str or ldr. The SP cases are handled below. */
11259 unsigned long opcode;
11260 /* First, record an error for Case 3. */
11261 if (inst.operands[1].imm & mask
11262 && inst.operands[0].writeback)
11264 _("having the base register in the register list when "
11265 "using write back is UNPREDICTABLE");
11267 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
11269 inst.instruction = THUMB_OP16 (opcode);
11270 inst.instruction |= inst.operands[0].reg << 3;
11271 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11275 else if (inst.operands[0] .reg == REG_SP)
11277 if (inst.operands[0].writeback)
11280 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11281 ? T_MNEM_push : T_MNEM_pop);
11282 inst.instruction |= inst.operands[1].imm;
11285 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11288 THUMB_OP16 (inst.instruction == T_MNEM_stmia
11289 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
11290 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
11298 if (inst.instruction < 0xffff)
11299 inst.instruction = THUMB_OP32 (inst.instruction);
11301 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11302 inst.operands[0].writeback);
11307 constraint (inst.operands[0].reg > 7
11308 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
11309 constraint (inst.instruction != T_MNEM_ldmia
11310 && inst.instruction != T_MNEM_stmia,
11311 _("Thumb-2 instruction only valid in unified syntax"));
11312 if (inst.instruction == T_MNEM_stmia)
11314 if (!inst.operands[0].writeback)
11315 as_warn (_("this instruction will write back the base register"));
11316 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11317 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
11318 as_warn (_("value stored for r%d is UNKNOWN"),
11319 inst.operands[0].reg);
11323 if (!inst.operands[0].writeback
11324 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11325 as_warn (_("this instruction will write back the base register"));
11326 else if (inst.operands[0].writeback
11327 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11328 as_warn (_("this instruction will not write back the base register"));
11331 inst.instruction = THUMB_OP16 (inst.instruction);
11332 inst.instruction |= inst.operands[0].reg << 8;
11333 inst.instruction |= inst.operands[1].imm;
11340 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11341 || inst.operands[1].postind || inst.operands[1].writeback
11342 || inst.operands[1].immisreg || inst.operands[1].shifted
11343 || inst.operands[1].negative,
11346 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11348 inst.instruction |= inst.operands[0].reg << 12;
11349 inst.instruction |= inst.operands[1].reg << 16;
11350 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11356 if (!inst.operands[1].present)
11358 constraint (inst.operands[0].reg == REG_LR,
11359 _("r14 not allowed as first register "
11360 "when second register is omitted"));
11361 inst.operands[1].reg = inst.operands[0].reg + 1;
11363 constraint (inst.operands[0].reg == inst.operands[1].reg,
11366 inst.instruction |= inst.operands[0].reg << 12;
11367 inst.instruction |= inst.operands[1].reg << 8;
11368 inst.instruction |= inst.operands[2].reg << 16;
11374 unsigned long opcode;
11377 if (inst.operands[0].isreg
11378 && !inst.operands[0].preind
11379 && inst.operands[0].reg == REG_PC)
11380 set_it_insn_type_last ();
11382 opcode = inst.instruction;
11383 if (unified_syntax)
11385 if (!inst.operands[1].isreg)
11387 if (opcode <= 0xffff)
11388 inst.instruction = THUMB_OP32 (opcode);
11389 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11392 if (inst.operands[1].isreg
11393 && !inst.operands[1].writeback
11394 && !inst.operands[1].shifted && !inst.operands[1].postind
11395 && !inst.operands[1].negative && inst.operands[0].reg <= 7
11396 && opcode <= 0xffff
11397 && inst.size_req != 4)
11399 /* Insn may have a 16-bit form. */
11400 Rn = inst.operands[1].reg;
11401 if (inst.operands[1].immisreg)
11403 inst.instruction = THUMB_OP16 (opcode);
11405 if (Rn <= 7 && inst.operands[1].imm <= 7)
11407 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11408 reject_bad_reg (inst.operands[1].imm);
11410 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11411 && opcode != T_MNEM_ldrsb)
11412 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11413 || (Rn == REG_SP && opcode == T_MNEM_str))
11420 if (inst.reloc.pc_rel)
11421 opcode = T_MNEM_ldr_pc2;
11423 opcode = T_MNEM_ldr_pc;
11427 if (opcode == T_MNEM_ldr)
11428 opcode = T_MNEM_ldr_sp;
11430 opcode = T_MNEM_str_sp;
11432 inst.instruction = inst.operands[0].reg << 8;
11436 inst.instruction = inst.operands[0].reg;
11437 inst.instruction |= inst.operands[1].reg << 3;
11439 inst.instruction |= THUMB_OP16 (opcode);
11440 if (inst.size_req == 2)
11441 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11443 inst.relax = opcode;
11447 /* Definitely a 32-bit variant. */
11449 /* Warning for Erratum 752419. */
11450 if (opcode == T_MNEM_ldr
11451 && inst.operands[0].reg == REG_SP
11452 && inst.operands[1].writeback == 1
11453 && !inst.operands[1].immisreg)
11455 if (no_cpu_selected ()
11456 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
11457 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11458 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
11459 as_warn (_("This instruction may be unpredictable "
11460 "if executed on M-profile cores "
11461 "with interrupts enabled."));
11464 /* Do some validations regarding addressing modes. */
11465 if (inst.operands[1].immisreg)
11466 reject_bad_reg (inst.operands[1].imm);
11468 constraint (inst.operands[1].writeback == 1
11469 && inst.operands[0].reg == inst.operands[1].reg,
11472 inst.instruction = THUMB_OP32 (opcode);
11473 inst.instruction |= inst.operands[0].reg << 12;
11474 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
11475 check_ldr_r15_aligned ();
11479 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11481 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
11483 /* Only [Rn,Rm] is acceptable. */
11484 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11485 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11486 || inst.operands[1].postind || inst.operands[1].shifted
11487 || inst.operands[1].negative,
11488 _("Thumb does not support this addressing mode"));
11489 inst.instruction = THUMB_OP16 (inst.instruction);
11493 inst.instruction = THUMB_OP16 (inst.instruction);
11494 if (!inst.operands[1].isreg)
11495 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
11498 constraint (!inst.operands[1].preind
11499 || inst.operands[1].shifted
11500 || inst.operands[1].writeback,
11501 _("Thumb does not support this addressing mode"));
11502 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
11504 constraint (inst.instruction & 0x0600,
11505 _("byte or halfword not valid for base register"));
11506 constraint (inst.operands[1].reg == REG_PC
11507 && !(inst.instruction & THUMB_LOAD_BIT),
11508 _("r15 based store not allowed"));
11509 constraint (inst.operands[1].immisreg,
11510 _("invalid base register for register offset"));
11512 if (inst.operands[1].reg == REG_PC)
11513 inst.instruction = T_OPCODE_LDR_PC;
11514 else if (inst.instruction & THUMB_LOAD_BIT)
11515 inst.instruction = T_OPCODE_LDR_SP;
11517 inst.instruction = T_OPCODE_STR_SP;
11519 inst.instruction |= inst.operands[0].reg << 8;
11520 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11524 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11525 if (!inst.operands[1].immisreg)
11527 /* Immediate offset. */
11528 inst.instruction |= inst.operands[0].reg;
11529 inst.instruction |= inst.operands[1].reg << 3;
11530 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11534 /* Register offset. */
11535 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11536 constraint (inst.operands[1].negative,
11537 _("Thumb does not support this addressing mode"));
11540 switch (inst.instruction)
11542 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11543 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11544 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11545 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11546 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11547 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11548 case 0x5600 /* ldrsb */:
11549 case 0x5e00 /* ldrsh */: break;
11553 inst.instruction |= inst.operands[0].reg;
11554 inst.instruction |= inst.operands[1].reg << 3;
11555 inst.instruction |= inst.operands[1].imm << 6;
11561 if (!inst.operands[1].present)
11563 inst.operands[1].reg = inst.operands[0].reg + 1;
11564 constraint (inst.operands[0].reg == REG_LR,
11565 _("r14 not allowed here"));
11566 constraint (inst.operands[0].reg == REG_R12,
11567 _("r12 not allowed here"));
11570 if (inst.operands[2].writeback
11571 && (inst.operands[0].reg == inst.operands[2].reg
11572 || inst.operands[1].reg == inst.operands[2].reg))
11573 as_warn (_("base register written back, and overlaps "
11574 "one of transfer registers"));
11576 inst.instruction |= inst.operands[0].reg << 12;
11577 inst.instruction |= inst.operands[1].reg << 8;
11578 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
11584 inst.instruction |= inst.operands[0].reg << 12;
11585 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11591 unsigned Rd, Rn, Rm, Ra;
11593 Rd = inst.operands[0].reg;
11594 Rn = inst.operands[1].reg;
11595 Rm = inst.operands[2].reg;
11596 Ra = inst.operands[3].reg;
11598 reject_bad_reg (Rd);
11599 reject_bad_reg (Rn);
11600 reject_bad_reg (Rm);
11601 reject_bad_reg (Ra);
11603 inst.instruction |= Rd << 8;
11604 inst.instruction |= Rn << 16;
11605 inst.instruction |= Rm;
11606 inst.instruction |= Ra << 12;
11612 unsigned RdLo, RdHi, Rn, Rm;
11614 RdLo = inst.operands[0].reg;
11615 RdHi = inst.operands[1].reg;
11616 Rn = inst.operands[2].reg;
11617 Rm = inst.operands[3].reg;
11619 reject_bad_reg (RdLo);
11620 reject_bad_reg (RdHi);
11621 reject_bad_reg (Rn);
11622 reject_bad_reg (Rm);
11624 inst.instruction |= RdLo << 12;
11625 inst.instruction |= RdHi << 8;
11626 inst.instruction |= Rn << 16;
11627 inst.instruction |= Rm;
11631 do_t_mov_cmp (void)
11635 Rn = inst.operands[0].reg;
11636 Rm = inst.operands[1].reg;
11639 set_it_insn_type_last ();
11641 if (unified_syntax)
11643 int r0off = (inst.instruction == T_MNEM_mov
11644 || inst.instruction == T_MNEM_movs) ? 8 : 16;
11645 unsigned long opcode;
11646 bfd_boolean narrow;
11647 bfd_boolean low_regs;
11649 low_regs = (Rn <= 7 && Rm <= 7);
11650 opcode = inst.instruction;
11651 if (in_it_block ())
11652 narrow = opcode != T_MNEM_movs;
11654 narrow = opcode != T_MNEM_movs || low_regs;
11655 if (inst.size_req == 4
11656 || inst.operands[1].shifted)
11659 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11660 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11661 && !inst.operands[1].shifted
11665 inst.instruction = T2_SUBS_PC_LR;
11669 if (opcode == T_MNEM_cmp)
11671 constraint (Rn == REG_PC, BAD_PC);
11674 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11676 warn_deprecated_sp (Rm);
11677 /* R15 was documented as a valid choice for Rm in ARMv6,
11678 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11679 tools reject R15, so we do too. */
11680 constraint (Rm == REG_PC, BAD_PC);
11683 reject_bad_reg (Rm);
11685 else if (opcode == T_MNEM_mov
11686 || opcode == T_MNEM_movs)
11688 if (inst.operands[1].isreg)
11690 if (opcode == T_MNEM_movs)
11692 reject_bad_reg (Rn);
11693 reject_bad_reg (Rm);
11697 /* This is mov.n. */
11698 if ((Rn == REG_SP || Rn == REG_PC)
11699 && (Rm == REG_SP || Rm == REG_PC))
11701 as_tsktsk (_("Use of r%u as a source register is "
11702 "deprecated when r%u is the destination "
11703 "register."), Rm, Rn);
11708 /* This is mov.w. */
11709 constraint (Rn == REG_PC, BAD_PC);
11710 constraint (Rm == REG_PC, BAD_PC);
11711 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11715 reject_bad_reg (Rn);
11718 if (!inst.operands[1].isreg)
11720 /* Immediate operand. */
11721 if (!in_it_block () && opcode == T_MNEM_mov)
11723 if (low_regs && narrow)
11725 inst.instruction = THUMB_OP16 (opcode);
11726 inst.instruction |= Rn << 8;
11727 if (inst.size_req == 2)
11728 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11730 inst.relax = opcode;
11734 inst.instruction = THUMB_OP32 (inst.instruction);
11735 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11736 inst.instruction |= Rn << r0off;
11737 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11740 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11741 && (inst.instruction == T_MNEM_mov
11742 || inst.instruction == T_MNEM_movs))
11744 /* Register shifts are encoded as separate shift instructions. */
11745 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11747 if (in_it_block ())
11752 if (inst.size_req == 4)
11755 if (!low_regs || inst.operands[1].imm > 7)
11761 switch (inst.operands[1].shift_kind)
11764 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11767 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11770 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11773 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11779 inst.instruction = opcode;
11782 inst.instruction |= Rn;
11783 inst.instruction |= inst.operands[1].imm << 3;
11788 inst.instruction |= CONDS_BIT;
11790 inst.instruction |= Rn << 8;
11791 inst.instruction |= Rm << 16;
11792 inst.instruction |= inst.operands[1].imm;
11797 /* Some mov with immediate shift have narrow variants.
11798 Register shifts are handled above. */
11799 if (low_regs && inst.operands[1].shifted
11800 && (inst.instruction == T_MNEM_mov
11801 || inst.instruction == T_MNEM_movs))
11803 if (in_it_block ())
11804 narrow = (inst.instruction == T_MNEM_mov);
11806 narrow = (inst.instruction == T_MNEM_movs);
11811 switch (inst.operands[1].shift_kind)
11813 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11814 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11815 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11816 default: narrow = FALSE; break;
11822 inst.instruction |= Rn;
11823 inst.instruction |= Rm << 3;
11824 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11828 inst.instruction = THUMB_OP32 (inst.instruction);
11829 inst.instruction |= Rn << r0off;
11830 encode_thumb32_shifted_operand (1);
11834 switch (inst.instruction)
11837 /* In v4t or v5t a move of two lowregs produces unpredictable
11838 results. Don't allow this. */
11841 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11842 "MOV Rd, Rs with two low registers is not "
11843 "permitted on this architecture");
11844 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
11848 inst.instruction = T_OPCODE_MOV_HR;
11849 inst.instruction |= (Rn & 0x8) << 4;
11850 inst.instruction |= (Rn & 0x7);
11851 inst.instruction |= Rm << 3;
11855 /* We know we have low registers at this point.
11856 Generate LSLS Rd, Rs, #0. */
11857 inst.instruction = T_OPCODE_LSL_I;
11858 inst.instruction |= Rn;
11859 inst.instruction |= Rm << 3;
11865 inst.instruction = T_OPCODE_CMP_LR;
11866 inst.instruction |= Rn;
11867 inst.instruction |= Rm << 3;
11871 inst.instruction = T_OPCODE_CMP_HR;
11872 inst.instruction |= (Rn & 0x8) << 4;
11873 inst.instruction |= (Rn & 0x7);
11874 inst.instruction |= Rm << 3;
11881 inst.instruction = THUMB_OP16 (inst.instruction);
11883 /* PR 10443: Do not silently ignore shifted operands. */
11884 constraint (inst.operands[1].shifted,
11885 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11887 if (inst.operands[1].isreg)
11889 if (Rn < 8 && Rm < 8)
11891 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11892 since a MOV instruction produces unpredictable results. */
11893 if (inst.instruction == T_OPCODE_MOV_I8)
11894 inst.instruction = T_OPCODE_ADD_I3;
11896 inst.instruction = T_OPCODE_CMP_LR;
11898 inst.instruction |= Rn;
11899 inst.instruction |= Rm << 3;
11903 if (inst.instruction == T_OPCODE_MOV_I8)
11904 inst.instruction = T_OPCODE_MOV_HR;
11906 inst.instruction = T_OPCODE_CMP_HR;
11912 constraint (Rn > 7,
11913 _("only lo regs allowed with immediate"));
11914 inst.instruction |= Rn << 8;
11915 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11926 top = (inst.instruction & 0x00800000) != 0;
11927 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11929 constraint (top, _(":lower16: not allowed this instruction"));
11930 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11932 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11934 constraint (!top, _(":upper16: not allowed this instruction"));
11935 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11938 Rd = inst.operands[0].reg;
11939 reject_bad_reg (Rd);
11941 inst.instruction |= Rd << 8;
11942 if (inst.reloc.type == BFD_RELOC_UNUSED)
11944 imm = inst.reloc.exp.X_add_number;
11945 inst.instruction |= (imm & 0xf000) << 4;
11946 inst.instruction |= (imm & 0x0800) << 15;
11947 inst.instruction |= (imm & 0x0700) << 4;
11948 inst.instruction |= (imm & 0x00ff);
11953 do_t_mvn_tst (void)
11957 Rn = inst.operands[0].reg;
11958 Rm = inst.operands[1].reg;
11960 if (inst.instruction == T_MNEM_cmp
11961 || inst.instruction == T_MNEM_cmn)
11962 constraint (Rn == REG_PC, BAD_PC);
11964 reject_bad_reg (Rn);
11965 reject_bad_reg (Rm);
11967 if (unified_syntax)
11969 int r0off = (inst.instruction == T_MNEM_mvn
11970 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
11971 bfd_boolean narrow;
11973 if (inst.size_req == 4
11974 || inst.instruction > 0xffff
11975 || inst.operands[1].shifted
11976 || Rn > 7 || Rm > 7)
11978 else if (inst.instruction == T_MNEM_cmn
11979 || inst.instruction == T_MNEM_tst)
11981 else if (THUMB_SETS_FLAGS (inst.instruction))
11982 narrow = !in_it_block ();
11984 narrow = in_it_block ();
11986 if (!inst.operands[1].isreg)
11988 /* For an immediate, we always generate a 32-bit opcode;
11989 section relaxation will shrink it later if possible. */
11990 if (inst.instruction < 0xffff)
11991 inst.instruction = THUMB_OP32 (inst.instruction);
11992 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11993 inst.instruction |= Rn << r0off;
11994 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11998 /* See if we can do this with a 16-bit instruction. */
12001 inst.instruction = THUMB_OP16 (inst.instruction);
12002 inst.instruction |= Rn;
12003 inst.instruction |= Rm << 3;
12007 constraint (inst.operands[1].shifted
12008 && inst.operands[1].immisreg,
12009 _("shift must be constant"));
12010 if (inst.instruction < 0xffff)
12011 inst.instruction = THUMB_OP32 (inst.instruction);
12012 inst.instruction |= Rn << r0off;
12013 encode_thumb32_shifted_operand (1);
12019 constraint (inst.instruction > 0xffff
12020 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
12021 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
12022 _("unshifted register required"));
12023 constraint (Rn > 7 || Rm > 7,
12026 inst.instruction = THUMB_OP16 (inst.instruction);
12027 inst.instruction |= Rn;
12028 inst.instruction |= Rm << 3;
12037 if (do_vfp_nsyn_mrs () == SUCCESS)
12040 Rd = inst.operands[0].reg;
12041 reject_bad_reg (Rd);
12042 inst.instruction |= Rd << 8;
12044 if (inst.operands[1].isreg)
12046 unsigned br = inst.operands[1].reg;
12047 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
12048 as_bad (_("bad register for mrs"));
12050 inst.instruction |= br & (0xf << 16);
12051 inst.instruction |= (br & 0x300) >> 4;
12052 inst.instruction |= (br & SPSR_BIT) >> 2;
12056 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12058 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12060 /* PR gas/12698: The constraint is only applied for m_profile.
12061 If the user has specified -march=all, we want to ignore it as
12062 we are building for any CPU type, including non-m variants. */
12063 bfd_boolean m_profile =
12064 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12065 constraint ((flags != 0) && m_profile, _("selected processor does "
12066 "not support requested special purpose register"));
12069 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12071 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
12072 _("'APSR', 'CPSR' or 'SPSR' expected"));
12074 inst.instruction |= (flags & SPSR_BIT) >> 2;
12075 inst.instruction |= inst.operands[1].imm & 0xff;
12076 inst.instruction |= 0xf0000;
12086 if (do_vfp_nsyn_msr () == SUCCESS)
12089 constraint (!inst.operands[1].isreg,
12090 _("Thumb encoding does not support an immediate here"));
12092 if (inst.operands[0].isreg)
12093 flags = (int)(inst.operands[0].reg);
12095 flags = inst.operands[0].imm;
12097 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
12099 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
12101 /* PR gas/12698: The constraint is only applied for m_profile.
12102 If the user has specified -march=all, we want to ignore it as
12103 we are building for any CPU type, including non-m variants. */
12104 bfd_boolean m_profile =
12105 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
12106 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12107 && (bits & ~(PSR_s | PSR_f)) != 0)
12108 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
12109 && bits != PSR_f)) && m_profile,
12110 _("selected processor does not support requested special "
12111 "purpose register"));
12114 constraint ((flags & 0xff) != 0, _("selected processor does not support "
12115 "requested special purpose register"));
12117 Rn = inst.operands[1].reg;
12118 reject_bad_reg (Rn);
12120 inst.instruction |= (flags & SPSR_BIT) >> 2;
12121 inst.instruction |= (flags & 0xf0000) >> 8;
12122 inst.instruction |= (flags & 0x300) >> 4;
12123 inst.instruction |= (flags & 0xff);
12124 inst.instruction |= Rn << 16;
12130 bfd_boolean narrow;
12131 unsigned Rd, Rn, Rm;
12133 if (!inst.operands[2].present)
12134 inst.operands[2].reg = inst.operands[0].reg;
12136 Rd = inst.operands[0].reg;
12137 Rn = inst.operands[1].reg;
12138 Rm = inst.operands[2].reg;
12140 if (unified_syntax)
12142 if (inst.size_req == 4
12148 else if (inst.instruction == T_MNEM_muls)
12149 narrow = !in_it_block ();
12151 narrow = in_it_block ();
12155 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
12156 constraint (Rn > 7 || Rm > 7,
12163 /* 16-bit MULS/Conditional MUL. */
12164 inst.instruction = THUMB_OP16 (inst.instruction);
12165 inst.instruction |= Rd;
12168 inst.instruction |= Rm << 3;
12170 inst.instruction |= Rn << 3;
12172 constraint (1, _("dest must overlap one source register"));
12176 constraint (inst.instruction != T_MNEM_mul,
12177 _("Thumb-2 MUL must not set flags"));
12179 inst.instruction = THUMB_OP32 (inst.instruction);
12180 inst.instruction |= Rd << 8;
12181 inst.instruction |= Rn << 16;
12182 inst.instruction |= Rm << 0;
12184 reject_bad_reg (Rd);
12185 reject_bad_reg (Rn);
12186 reject_bad_reg (Rm);
12193 unsigned RdLo, RdHi, Rn, Rm;
12195 RdLo = inst.operands[0].reg;
12196 RdHi = inst.operands[1].reg;
12197 Rn = inst.operands[2].reg;
12198 Rm = inst.operands[3].reg;
12200 reject_bad_reg (RdLo);
12201 reject_bad_reg (RdHi);
12202 reject_bad_reg (Rn);
12203 reject_bad_reg (Rm);
12205 inst.instruction |= RdLo << 12;
12206 inst.instruction |= RdHi << 8;
12207 inst.instruction |= Rn << 16;
12208 inst.instruction |= Rm;
12211 as_tsktsk (_("rdhi and rdlo must be different"));
12217 set_it_insn_type (NEUTRAL_IT_INSN);
12219 if (unified_syntax)
12221 if (inst.size_req == 4 || inst.operands[0].imm > 15)
12223 inst.instruction = THUMB_OP32 (inst.instruction);
12224 inst.instruction |= inst.operands[0].imm;
12228 /* PR9722: Check for Thumb2 availability before
12229 generating a thumb2 nop instruction. */
12230 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
12232 inst.instruction = THUMB_OP16 (inst.instruction);
12233 inst.instruction |= inst.operands[0].imm << 4;
12236 inst.instruction = 0x46c0;
12241 constraint (inst.operands[0].present,
12242 _("Thumb does not support NOP with hints"));
12243 inst.instruction = 0x46c0;
12250 if (unified_syntax)
12252 bfd_boolean narrow;
12254 if (THUMB_SETS_FLAGS (inst.instruction))
12255 narrow = !in_it_block ();
12257 narrow = in_it_block ();
12258 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12260 if (inst.size_req == 4)
12265 inst.instruction = THUMB_OP32 (inst.instruction);
12266 inst.instruction |= inst.operands[0].reg << 8;
12267 inst.instruction |= inst.operands[1].reg << 16;
12271 inst.instruction = THUMB_OP16 (inst.instruction);
12272 inst.instruction |= inst.operands[0].reg;
12273 inst.instruction |= inst.operands[1].reg << 3;
12278 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12280 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12282 inst.instruction = THUMB_OP16 (inst.instruction);
12283 inst.instruction |= inst.operands[0].reg;
12284 inst.instruction |= inst.operands[1].reg << 3;
12293 Rd = inst.operands[0].reg;
12294 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12296 reject_bad_reg (Rd);
12297 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12298 reject_bad_reg (Rn);
12300 inst.instruction |= Rd << 8;
12301 inst.instruction |= Rn << 16;
12303 if (!inst.operands[2].isreg)
12305 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12306 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12312 Rm = inst.operands[2].reg;
12313 reject_bad_reg (Rm);
12315 constraint (inst.operands[2].shifted
12316 && inst.operands[2].immisreg,
12317 _("shift must be constant"));
12318 encode_thumb32_shifted_operand (2);
12325 unsigned Rd, Rn, Rm;
12327 Rd = inst.operands[0].reg;
12328 Rn = inst.operands[1].reg;
12329 Rm = inst.operands[2].reg;
12331 reject_bad_reg (Rd);
12332 reject_bad_reg (Rn);
12333 reject_bad_reg (Rm);
12335 inst.instruction |= Rd << 8;
12336 inst.instruction |= Rn << 16;
12337 inst.instruction |= Rm;
12338 if (inst.operands[3].present)
12340 unsigned int val = inst.reloc.exp.X_add_number;
12341 constraint (inst.reloc.exp.X_op != O_constant,
12342 _("expression too complex"));
12343 inst.instruction |= (val & 0x1c) << 10;
12344 inst.instruction |= (val & 0x03) << 6;
12351 if (!inst.operands[3].present)
12355 inst.instruction &= ~0x00000020;
12357 /* PR 10168. Swap the Rm and Rn registers. */
12358 Rtmp = inst.operands[1].reg;
12359 inst.operands[1].reg = inst.operands[2].reg;
12360 inst.operands[2].reg = Rtmp;
12368 if (inst.operands[0].immisreg)
12369 reject_bad_reg (inst.operands[0].imm);
12371 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12375 do_t_push_pop (void)
12379 constraint (inst.operands[0].writeback,
12380 _("push/pop do not support {reglist}^"));
12381 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12382 _("expression too complex"));
12384 mask = inst.operands[0].imm;
12385 if (inst.size_req != 4 && (mask & ~0xff) == 0)
12386 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
12387 else if (inst.size_req != 4
12388 && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push
12389 ? REG_LR : REG_PC)))
12391 inst.instruction = THUMB_OP16 (inst.instruction);
12392 inst.instruction |= THUMB_PP_PC_LR;
12393 inst.instruction |= mask & 0xff;
12395 else if (unified_syntax)
12397 inst.instruction = THUMB_OP32 (inst.instruction);
12398 encode_thumb2_ldmstm (13, mask, TRUE);
12402 inst.error = _("invalid register list to push/pop instruction");
12412 Rd = inst.operands[0].reg;
12413 Rm = inst.operands[1].reg;
12415 reject_bad_reg (Rd);
12416 reject_bad_reg (Rm);
12418 inst.instruction |= Rd << 8;
12419 inst.instruction |= Rm << 16;
12420 inst.instruction |= Rm;
12428 Rd = inst.operands[0].reg;
12429 Rm = inst.operands[1].reg;
12431 reject_bad_reg (Rd);
12432 reject_bad_reg (Rm);
12434 if (Rd <= 7 && Rm <= 7
12435 && inst.size_req != 4)
12437 inst.instruction = THUMB_OP16 (inst.instruction);
12438 inst.instruction |= Rd;
12439 inst.instruction |= Rm << 3;
12441 else if (unified_syntax)
12443 inst.instruction = THUMB_OP32 (inst.instruction);
12444 inst.instruction |= Rd << 8;
12445 inst.instruction |= Rm << 16;
12446 inst.instruction |= Rm;
12449 inst.error = BAD_HIREG;
12457 Rd = inst.operands[0].reg;
12458 Rm = inst.operands[1].reg;
12460 reject_bad_reg (Rd);
12461 reject_bad_reg (Rm);
12463 inst.instruction |= Rd << 8;
12464 inst.instruction |= Rm;
12472 Rd = inst.operands[0].reg;
12473 Rs = (inst.operands[1].present
12474 ? inst.operands[1].reg /* Rd, Rs, foo */
12475 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
12477 reject_bad_reg (Rd);
12478 reject_bad_reg (Rs);
12479 if (inst.operands[2].isreg)
12480 reject_bad_reg (inst.operands[2].reg);
12482 inst.instruction |= Rd << 8;
12483 inst.instruction |= Rs << 16;
12484 if (!inst.operands[2].isreg)
12486 bfd_boolean narrow;
12488 if ((inst.instruction & 0x00100000) != 0)
12489 narrow = !in_it_block ();
12491 narrow = in_it_block ();
12493 if (Rd > 7 || Rs > 7)
12496 if (inst.size_req == 4 || !unified_syntax)
12499 if (inst.reloc.exp.X_op != O_constant
12500 || inst.reloc.exp.X_add_number != 0)
12503 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12504 relaxation, but it doesn't seem worth the hassle. */
12507 inst.reloc.type = BFD_RELOC_UNUSED;
12508 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12509 inst.instruction |= Rs << 3;
12510 inst.instruction |= Rd;
12514 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12515 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12519 encode_thumb32_shifted_operand (2);
12525 if (warn_on_deprecated
12526 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12527 as_tsktsk (_("setend use is deprecated for ARMv8"));
12529 set_it_insn_type (OUTSIDE_IT_INSN);
12530 if (inst.operands[0].imm)
12531 inst.instruction |= 0x8;
12537 if (!inst.operands[1].present)
12538 inst.operands[1].reg = inst.operands[0].reg;
12540 if (unified_syntax)
12542 bfd_boolean narrow;
12545 switch (inst.instruction)
12548 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12550 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12552 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12554 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12558 if (THUMB_SETS_FLAGS (inst.instruction))
12559 narrow = !in_it_block ();
12561 narrow = in_it_block ();
12562 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12564 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12566 if (inst.operands[2].isreg
12567 && (inst.operands[1].reg != inst.operands[0].reg
12568 || inst.operands[2].reg > 7))
12570 if (inst.size_req == 4)
12573 reject_bad_reg (inst.operands[0].reg);
12574 reject_bad_reg (inst.operands[1].reg);
12578 if (inst.operands[2].isreg)
12580 reject_bad_reg (inst.operands[2].reg);
12581 inst.instruction = THUMB_OP32 (inst.instruction);
12582 inst.instruction |= inst.operands[0].reg << 8;
12583 inst.instruction |= inst.operands[1].reg << 16;
12584 inst.instruction |= inst.operands[2].reg;
12586 /* PR 12854: Error on extraneous shifts. */
12587 constraint (inst.operands[2].shifted,
12588 _("extraneous shift as part of operand to shift insn"));
12592 inst.operands[1].shifted = 1;
12593 inst.operands[1].shift_kind = shift_kind;
12594 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12595 ? T_MNEM_movs : T_MNEM_mov);
12596 inst.instruction |= inst.operands[0].reg << 8;
12597 encode_thumb32_shifted_operand (1);
12598 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12599 inst.reloc.type = BFD_RELOC_UNUSED;
12604 if (inst.operands[2].isreg)
12606 switch (shift_kind)
12608 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12609 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12610 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12611 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
12615 inst.instruction |= inst.operands[0].reg;
12616 inst.instruction |= inst.operands[2].reg << 3;
12618 /* PR 12854: Error on extraneous shifts. */
12619 constraint (inst.operands[2].shifted,
12620 _("extraneous shift as part of operand to shift insn"));
12624 switch (shift_kind)
12626 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12627 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12628 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
12631 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12632 inst.instruction |= inst.operands[0].reg;
12633 inst.instruction |= inst.operands[1].reg << 3;
12639 constraint (inst.operands[0].reg > 7
12640 || inst.operands[1].reg > 7, BAD_HIREG);
12641 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12643 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12645 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12646 constraint (inst.operands[0].reg != inst.operands[1].reg,
12647 _("source1 and dest must be same register"));
12649 switch (inst.instruction)
12651 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12652 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12653 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12654 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12658 inst.instruction |= inst.operands[0].reg;
12659 inst.instruction |= inst.operands[2].reg << 3;
12661 /* PR 12854: Error on extraneous shifts. */
12662 constraint (inst.operands[2].shifted,
12663 _("extraneous shift as part of operand to shift insn"));
12667 switch (inst.instruction)
12669 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12670 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12671 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12672 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12675 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12676 inst.instruction |= inst.operands[0].reg;
12677 inst.instruction |= inst.operands[1].reg << 3;
12685 unsigned Rd, Rn, Rm;
12687 Rd = inst.operands[0].reg;
12688 Rn = inst.operands[1].reg;
12689 Rm = inst.operands[2].reg;
12691 reject_bad_reg (Rd);
12692 reject_bad_reg (Rn);
12693 reject_bad_reg (Rm);
12695 inst.instruction |= Rd << 8;
12696 inst.instruction |= Rn << 16;
12697 inst.instruction |= Rm;
12703 unsigned Rd, Rn, Rm;
12705 Rd = inst.operands[0].reg;
12706 Rm = inst.operands[1].reg;
12707 Rn = inst.operands[2].reg;
12709 reject_bad_reg (Rd);
12710 reject_bad_reg (Rn);
12711 reject_bad_reg (Rm);
12713 inst.instruction |= Rd << 8;
12714 inst.instruction |= Rn << 16;
12715 inst.instruction |= Rm;
12721 unsigned int value = inst.reloc.exp.X_add_number;
12722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12723 _("SMC is not permitted on this architecture"));
12724 constraint (inst.reloc.exp.X_op != O_constant,
12725 _("expression too complex"));
12726 inst.reloc.type = BFD_RELOC_UNUSED;
12727 inst.instruction |= (value & 0xf000) >> 12;
12728 inst.instruction |= (value & 0x0ff0);
12729 inst.instruction |= (value & 0x000f) << 16;
12730 /* PR gas/15623: SMC instructions must be last in an IT block. */
12731 set_it_insn_type_last ();
12737 unsigned int value = inst.reloc.exp.X_add_number;
12739 inst.reloc.type = BFD_RELOC_UNUSED;
12740 inst.instruction |= (value & 0x0fff);
12741 inst.instruction |= (value & 0xf000) << 4;
12745 do_t_ssat_usat (int bias)
12749 Rd = inst.operands[0].reg;
12750 Rn = inst.operands[2].reg;
12752 reject_bad_reg (Rd);
12753 reject_bad_reg (Rn);
12755 inst.instruction |= Rd << 8;
12756 inst.instruction |= inst.operands[1].imm - bias;
12757 inst.instruction |= Rn << 16;
12759 if (inst.operands[3].present)
12761 offsetT shift_amount = inst.reloc.exp.X_add_number;
12763 inst.reloc.type = BFD_RELOC_UNUSED;
12765 constraint (inst.reloc.exp.X_op != O_constant,
12766 _("expression too complex"));
12768 if (shift_amount != 0)
12770 constraint (shift_amount > 31,
12771 _("shift expression is too large"));
12773 if (inst.operands[3].shift_kind == SHIFT_ASR)
12774 inst.instruction |= 0x00200000; /* sh bit. */
12776 inst.instruction |= (shift_amount & 0x1c) << 10;
12777 inst.instruction |= (shift_amount & 0x03) << 6;
12785 do_t_ssat_usat (1);
12793 Rd = inst.operands[0].reg;
12794 Rn = inst.operands[2].reg;
12796 reject_bad_reg (Rd);
12797 reject_bad_reg (Rn);
12799 inst.instruction |= Rd << 8;
12800 inst.instruction |= inst.operands[1].imm - 1;
12801 inst.instruction |= Rn << 16;
12807 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12808 || inst.operands[2].postind || inst.operands[2].writeback
12809 || inst.operands[2].immisreg || inst.operands[2].shifted
12810 || inst.operands[2].negative,
12813 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12815 inst.instruction |= inst.operands[0].reg << 8;
12816 inst.instruction |= inst.operands[1].reg << 12;
12817 inst.instruction |= inst.operands[2].reg << 16;
12818 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
12824 if (!inst.operands[2].present)
12825 inst.operands[2].reg = inst.operands[1].reg + 1;
12827 constraint (inst.operands[0].reg == inst.operands[1].reg
12828 || inst.operands[0].reg == inst.operands[2].reg
12829 || inst.operands[0].reg == inst.operands[3].reg,
12832 inst.instruction |= inst.operands[0].reg;
12833 inst.instruction |= inst.operands[1].reg << 12;
12834 inst.instruction |= inst.operands[2].reg << 8;
12835 inst.instruction |= inst.operands[3].reg << 16;
12841 unsigned Rd, Rn, Rm;
12843 Rd = inst.operands[0].reg;
12844 Rn = inst.operands[1].reg;
12845 Rm = inst.operands[2].reg;
12847 reject_bad_reg (Rd);
12848 reject_bad_reg (Rn);
12849 reject_bad_reg (Rm);
12851 inst.instruction |= Rd << 8;
12852 inst.instruction |= Rn << 16;
12853 inst.instruction |= Rm;
12854 inst.instruction |= inst.operands[3].imm << 4;
12862 Rd = inst.operands[0].reg;
12863 Rm = inst.operands[1].reg;
12865 reject_bad_reg (Rd);
12866 reject_bad_reg (Rm);
12868 if (inst.instruction <= 0xffff
12869 && inst.size_req != 4
12870 && Rd <= 7 && Rm <= 7
12871 && (!inst.operands[2].present || inst.operands[2].imm == 0))
12873 inst.instruction = THUMB_OP16 (inst.instruction);
12874 inst.instruction |= Rd;
12875 inst.instruction |= Rm << 3;
12877 else if (unified_syntax)
12879 if (inst.instruction <= 0xffff)
12880 inst.instruction = THUMB_OP32 (inst.instruction);
12881 inst.instruction |= Rd << 8;
12882 inst.instruction |= Rm;
12883 inst.instruction |= inst.operands[2].imm << 4;
12887 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12888 _("Thumb encoding does not support rotation"));
12889 constraint (1, BAD_HIREG);
12896 /* We have to do the following check manually as ARM_EXT_OS only applies
12898 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12900 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12901 /* This only applies to the v6m howver, not later architectures. */
12902 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
12903 as_bad (_("SVC is not permitted on this architecture"));
12904 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12907 inst.reloc.type = BFD_RELOC_ARM_SWI;
12916 half = (inst.instruction & 0x10) != 0;
12917 set_it_insn_type_last ();
12918 constraint (inst.operands[0].immisreg,
12919 _("instruction requires register index"));
12921 Rn = inst.operands[0].reg;
12922 Rm = inst.operands[0].imm;
12924 constraint (Rn == REG_SP, BAD_SP);
12925 reject_bad_reg (Rm);
12927 constraint (!half && inst.operands[0].shifted,
12928 _("instruction does not allow shifted index"));
12929 inst.instruction |= (Rn << 16) | Rm;
12935 if (!inst.operands[0].present)
12936 inst.operands[0].imm = 0;
12938 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
12940 constraint (inst.size_req == 2,
12941 _("immediate value out of range"));
12942 inst.instruction = THUMB_OP32 (inst.instruction);
12943 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
12944 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
12948 inst.instruction = THUMB_OP16 (inst.instruction);
12949 inst.instruction |= inst.operands[0].imm;
12952 set_it_insn_type (NEUTRAL_IT_INSN);
12959 do_t_ssat_usat (0);
12967 Rd = inst.operands[0].reg;
12968 Rn = inst.operands[2].reg;
12970 reject_bad_reg (Rd);
12971 reject_bad_reg (Rn);
12973 inst.instruction |= Rd << 8;
12974 inst.instruction |= inst.operands[1].imm;
12975 inst.instruction |= Rn << 16;
12978 /* Neon instruction encoder helpers. */
12980 /* Encodings for the different types for various Neon opcodes. */
12982 /* An "invalid" code for the following tables. */
12985 struct neon_tab_entry
12988 unsigned float_or_poly;
12989 unsigned scalar_or_imm;
12992 /* Map overloaded Neon opcodes to their respective encodings. */
12993 #define NEON_ENC_TAB \
12994 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12995 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12996 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12997 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12998 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12999 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13000 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13001 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13002 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13003 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13004 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13005 /* Register variants of the following two instructions are encoded as
13006 vcge / vcgt with the operands reversed. */ \
13007 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13008 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13009 X(vfma, N_INV, 0x0000c10, N_INV), \
13010 X(vfms, N_INV, 0x0200c10, N_INV), \
13011 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13012 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13013 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13014 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13015 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13016 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13017 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13018 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13019 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13020 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13021 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13022 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13023 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13024 X(vshl, 0x0000400, N_INV, 0x0800510), \
13025 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13026 X(vand, 0x0000110, N_INV, 0x0800030), \
13027 X(vbic, 0x0100110, N_INV, 0x0800030), \
13028 X(veor, 0x1000110, N_INV, N_INV), \
13029 X(vorn, 0x0300110, N_INV, 0x0800010), \
13030 X(vorr, 0x0200110, N_INV, 0x0800010), \
13031 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13032 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13033 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13034 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13035 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13036 X(vst1, 0x0000000, 0x0800000, N_INV), \
13037 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13038 X(vst2, 0x0000100, 0x0800100, N_INV), \
13039 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13040 X(vst3, 0x0000200, 0x0800200, N_INV), \
13041 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13042 X(vst4, 0x0000300, 0x0800300, N_INV), \
13043 X(vmovn, 0x1b20200, N_INV, N_INV), \
13044 X(vtrn, 0x1b20080, N_INV, N_INV), \
13045 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13046 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13047 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13048 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13049 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13050 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13051 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13052 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13053 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13054 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13055 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13056 X(vseleq, 0xe000a00, N_INV, N_INV), \
13057 X(vselvs, 0xe100a00, N_INV, N_INV), \
13058 X(vselge, 0xe200a00, N_INV, N_INV), \
13059 X(vselgt, 0xe300a00, N_INV, N_INV), \
13060 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13061 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13062 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13063 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13064 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13065 X(aes, 0x3b00300, N_INV, N_INV), \
13066 X(sha3op, 0x2000c00, N_INV, N_INV), \
13067 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13068 X(sha2op, 0x3ba0380, N_INV, N_INV)
13072 #define X(OPC,I,F,S) N_MNEM_##OPC
13077 static const struct neon_tab_entry neon_enc_tab[] =
13079 #define X(OPC,I,F,S) { (I), (F), (S) }
13084 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13085 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13086 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13087 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13088 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13089 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13090 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13091 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13092 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13093 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13094 #define NEON_ENC_SINGLE_(X) \
13095 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13096 #define NEON_ENC_DOUBLE_(X) \
13097 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13098 #define NEON_ENC_FPV8_(X) \
13099 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13101 #define NEON_ENCODE(type, inst) \
13104 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13105 inst.is_neon = 1; \
13109 #define check_neon_suffixes \
13112 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13114 as_bad (_("invalid neon suffix for non neon instruction")); \
13120 /* Define shapes for instruction operands. The following mnemonic characters
13121 are used in this table:
13123 F - VFP S<n> register
13124 D - Neon D<n> register
13125 Q - Neon Q<n> register
13129 L - D<n> register list
13131 This table is used to generate various data:
13132 - enumerations of the form NS_DDR to be used as arguments to
13134 - a table classifying shapes into single, double, quad, mixed.
13135 - a table used to drive neon_select_shape. */
13137 #define NEON_SHAPE_DEF \
13138 X(3, (D, D, D), DOUBLE), \
13139 X(3, (Q, Q, Q), QUAD), \
13140 X(3, (D, D, I), DOUBLE), \
13141 X(3, (Q, Q, I), QUAD), \
13142 X(3, (D, D, S), DOUBLE), \
13143 X(3, (Q, Q, S), QUAD), \
13144 X(2, (D, D), DOUBLE), \
13145 X(2, (Q, Q), QUAD), \
13146 X(2, (D, S), DOUBLE), \
13147 X(2, (Q, S), QUAD), \
13148 X(2, (D, R), DOUBLE), \
13149 X(2, (Q, R), QUAD), \
13150 X(2, (D, I), DOUBLE), \
13151 X(2, (Q, I), QUAD), \
13152 X(3, (D, L, D), DOUBLE), \
13153 X(2, (D, Q), MIXED), \
13154 X(2, (Q, D), MIXED), \
13155 X(3, (D, Q, I), MIXED), \
13156 X(3, (Q, D, I), MIXED), \
13157 X(3, (Q, D, D), MIXED), \
13158 X(3, (D, Q, Q), MIXED), \
13159 X(3, (Q, Q, D), MIXED), \
13160 X(3, (Q, D, S), MIXED), \
13161 X(3, (D, Q, S), MIXED), \
13162 X(4, (D, D, D, I), DOUBLE), \
13163 X(4, (Q, Q, Q, I), QUAD), \
13164 X(2, (F, F), SINGLE), \
13165 X(3, (F, F, F), SINGLE), \
13166 X(2, (F, I), SINGLE), \
13167 X(2, (F, D), MIXED), \
13168 X(2, (D, F), MIXED), \
13169 X(3, (F, F, I), MIXED), \
13170 X(4, (R, R, F, F), SINGLE), \
13171 X(4, (F, F, R, R), SINGLE), \
13172 X(3, (D, R, R), DOUBLE), \
13173 X(3, (R, R, D), DOUBLE), \
13174 X(2, (S, R), SINGLE), \
13175 X(2, (R, S), SINGLE), \
13176 X(2, (F, R), SINGLE), \
13177 X(2, (R, F), SINGLE)
13179 #define S2(A,B) NS_##A##B
13180 #define S3(A,B,C) NS_##A##B##C
13181 #define S4(A,B,C,D) NS_##A##B##C##D
13183 #define X(N, L, C) S##N L
13196 enum neon_shape_class
13204 #define X(N, L, C) SC_##C
13206 static enum neon_shape_class neon_shape_class[] =
13224 /* Register widths of above. */
13225 static unsigned neon_shape_el_size[] =
13236 struct neon_shape_info
13239 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13242 #define S2(A,B) { SE_##A, SE_##B }
13243 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13244 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13246 #define X(N, L, C) { N, S##N L }
13248 static struct neon_shape_info neon_shape_tab[] =
13258 /* Bit masks used in type checking given instructions.
13259 'N_EQK' means the type must be the same as (or based on in some way) the key
13260 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13261 set, various other bits can be set as well in order to modify the meaning of
13262 the type constraint. */
13264 enum neon_type_mask
13288 N_KEY = 0x1000000, /* Key element (main type specifier). */
13289 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
13290 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
13291 N_UNT = 0x8000000, /* Must be explicitly untyped. */
13292 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13293 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13294 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13295 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13296 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13297 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13298 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13300 N_MAX_NONSPECIAL = N_P64
13303 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13305 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13306 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13307 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13308 #define N_SUF_32 (N_SU_32 | N_F32)
13309 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13310 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13312 /* Pass this as the first type argument to neon_check_type to ignore types
13314 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13316 /* Select a "shape" for the current instruction (describing register types or
13317 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13318 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13319 function of operand parsing, so this function doesn't need to be called.
13320 Shapes should be listed in order of decreasing length. */
13322 static enum neon_shape
13323 neon_select_shape (enum neon_shape shape, ...)
13326 enum neon_shape first_shape = shape;
13328 /* Fix missing optional operands. FIXME: we don't know at this point how
13329 many arguments we should have, so this makes the assumption that we have
13330 > 1. This is true of all current Neon opcodes, I think, but may not be
13331 true in the future. */
13332 if (!inst.operands[1].present)
13333 inst.operands[1] = inst.operands[0];
13335 va_start (ap, shape);
13337 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
13342 for (j = 0; j < neon_shape_tab[shape].els; j++)
13344 if (!inst.operands[j].present)
13350 switch (neon_shape_tab[shape].el[j])
13353 if (!(inst.operands[j].isreg
13354 && inst.operands[j].isvec
13355 && inst.operands[j].issingle
13356 && !inst.operands[j].isquad))
13361 if (!(inst.operands[j].isreg
13362 && inst.operands[j].isvec
13363 && !inst.operands[j].isquad
13364 && !inst.operands[j].issingle))
13369 if (!(inst.operands[j].isreg
13370 && !inst.operands[j].isvec))
13375 if (!(inst.operands[j].isreg
13376 && inst.operands[j].isvec
13377 && inst.operands[j].isquad
13378 && !inst.operands[j].issingle))
13383 if (!(!inst.operands[j].isreg
13384 && !inst.operands[j].isscalar))
13389 if (!(!inst.operands[j].isreg
13390 && inst.operands[j].isscalar))
13400 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13401 /* We've matched all the entries in the shape table, and we don't
13402 have any left over operands which have not been matched. */
13408 if (shape == NS_NULL && first_shape != NS_NULL)
13409 first_error (_("invalid instruction shape"));
13414 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13415 means the Q bit should be set). */
13418 neon_quad (enum neon_shape shape)
13420 return neon_shape_class[shape] == SC_QUAD;
13424 neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
13427 /* Allow modification to be made to types which are constrained to be
13428 based on the key element, based on bits set alongside N_EQK. */
13429 if ((typebits & N_EQK) != 0)
13431 if ((typebits & N_HLF) != 0)
13433 else if ((typebits & N_DBL) != 0)
13435 if ((typebits & N_SGN) != 0)
13436 *g_type = NT_signed;
13437 else if ((typebits & N_UNS) != 0)
13438 *g_type = NT_unsigned;
13439 else if ((typebits & N_INT) != 0)
13440 *g_type = NT_integer;
13441 else if ((typebits & N_FLT) != 0)
13442 *g_type = NT_float;
13443 else if ((typebits & N_SIZ) != 0)
13444 *g_type = NT_untyped;
13448 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13449 operand type, i.e. the single type specified in a Neon instruction when it
13450 is the only one given. */
13452 static struct neon_type_el
13453 neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13455 struct neon_type_el dest = *key;
13457 gas_assert ((thisarg & N_EQK) != 0);
13459 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13464 /* Convert Neon type and size into compact bitmask representation. */
13466 static enum neon_type_mask
13467 type_chk_of_el_type (enum neon_el_type type, unsigned size)
13474 case 8: return N_8;
13475 case 16: return N_16;
13476 case 32: return N_32;
13477 case 64: return N_64;
13485 case 8: return N_I8;
13486 case 16: return N_I16;
13487 case 32: return N_I32;
13488 case 64: return N_I64;
13496 case 16: return N_F16;
13497 case 32: return N_F32;
13498 case 64: return N_F64;
13506 case 8: return N_P8;
13507 case 16: return N_P16;
13508 case 64: return N_P64;
13516 case 8: return N_S8;
13517 case 16: return N_S16;
13518 case 32: return N_S32;
13519 case 64: return N_S64;
13527 case 8: return N_U8;
13528 case 16: return N_U16;
13529 case 32: return N_U32;
13530 case 64: return N_U64;
13541 /* Convert compact Neon bitmask type representation to a type and size. Only
13542 handles the case where a single bit is set in the mask. */
13545 el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
13546 enum neon_type_mask mask)
13548 if ((mask & N_EQK) != 0)
13551 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13553 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
13555 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
13557 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
13562 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13564 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
13565 *type = NT_unsigned;
13566 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
13567 *type = NT_integer;
13568 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
13569 *type = NT_untyped;
13570 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
13572 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
13580 /* Modify a bitmask of allowed types. This is only needed for type
13584 modify_types_allowed (unsigned allowed, unsigned mods)
13587 enum neon_el_type type;
13593 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13595 if (el_type_of_type_chk (&type, &size,
13596 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13598 neon_modify_type_size (mods, &type, &size);
13599 destmask |= type_chk_of_el_type (type, size);
13606 /* Check type and return type classification.
13607 The manual states (paraphrase): If one datatype is given, it indicates the
13609 - the second operand, if there is one
13610 - the operand, if there is no second operand
13611 - the result, if there are no operands.
13612 This isn't quite good enough though, so we use a concept of a "key" datatype
13613 which is set on a per-instruction basis, which is the one which matters when
13614 only one data type is written.
13615 Note: this function has side-effects (e.g. filling in missing operands). All
13616 Neon instructions should call it before performing bit encoding. */
13618 static struct neon_type_el
13619 neon_check_type (unsigned els, enum neon_shape ns, ...)
13622 unsigned i, pass, key_el = 0;
13623 unsigned types[NEON_MAX_TYPE_ELS];
13624 enum neon_el_type k_type = NT_invtype;
13625 unsigned k_size = -1u;
13626 struct neon_type_el badtype = {NT_invtype, -1};
13627 unsigned key_allowed = 0;
13629 /* Optional registers in Neon instructions are always (not) in operand 1.
13630 Fill in the missing operand here, if it was omitted. */
13631 if (els > 1 && !inst.operands[1].present)
13632 inst.operands[1] = inst.operands[0];
13634 /* Suck up all the varargs. */
13636 for (i = 0; i < els; i++)
13638 unsigned thisarg = va_arg (ap, unsigned);
13639 if (thisarg == N_IGNORE_TYPE)
13644 types[i] = thisarg;
13645 if ((thisarg & N_KEY) != 0)
13650 if (inst.vectype.elems > 0)
13651 for (i = 0; i < els; i++)
13652 if (inst.operands[i].vectype.type != NT_invtype)
13654 first_error (_("types specified in both the mnemonic and operands"));
13658 /* Duplicate inst.vectype elements here as necessary.
13659 FIXME: No idea if this is exactly the same as the ARM assembler,
13660 particularly when an insn takes one register and one non-register
13662 if (inst.vectype.elems == 1 && els > 1)
13665 inst.vectype.elems = els;
13666 inst.vectype.el[key_el] = inst.vectype.el[0];
13667 for (j = 0; j < els; j++)
13669 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13672 else if (inst.vectype.elems == 0 && els > 0)
13675 /* No types were given after the mnemonic, so look for types specified
13676 after each operand. We allow some flexibility here; as long as the
13677 "key" operand has a type, we can infer the others. */
13678 for (j = 0; j < els; j++)
13679 if (inst.operands[j].vectype.type != NT_invtype)
13680 inst.vectype.el[j] = inst.operands[j].vectype;
13682 if (inst.operands[key_el].vectype.type != NT_invtype)
13684 for (j = 0; j < els; j++)
13685 if (inst.operands[j].vectype.type == NT_invtype)
13686 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13691 first_error (_("operand types can't be inferred"));
13695 else if (inst.vectype.elems != els)
13697 first_error (_("type specifier has the wrong number of parts"));
13701 for (pass = 0; pass < 2; pass++)
13703 for (i = 0; i < els; i++)
13705 unsigned thisarg = types[i];
13706 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13707 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13708 enum neon_el_type g_type = inst.vectype.el[i].type;
13709 unsigned g_size = inst.vectype.el[i].size;
13711 /* Decay more-specific signed & unsigned types to sign-insensitive
13712 integer types if sign-specific variants are unavailable. */
13713 if ((g_type == NT_signed || g_type == NT_unsigned)
13714 && (types_allowed & N_SU_ALL) == 0)
13715 g_type = NT_integer;
13717 /* If only untyped args are allowed, decay any more specific types to
13718 them. Some instructions only care about signs for some element
13719 sizes, so handle that properly. */
13720 if (((types_allowed & N_UNT) == 0)
13721 && ((g_size == 8 && (types_allowed & N_8) != 0)
13722 || (g_size == 16 && (types_allowed & N_16) != 0)
13723 || (g_size == 32 && (types_allowed & N_32) != 0)
13724 || (g_size == 64 && (types_allowed & N_64) != 0)))
13725 g_type = NT_untyped;
13729 if ((thisarg & N_KEY) != 0)
13733 key_allowed = thisarg & ~N_KEY;
13738 if ((thisarg & N_VFP) != 0)
13740 enum neon_shape_el regshape;
13741 unsigned regwidth, match;
13743 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13746 first_error (_("invalid instruction shape"));
13749 regshape = neon_shape_tab[ns].el[i];
13750 regwidth = neon_shape_el_size[regshape];
13752 /* In VFP mode, operands must match register widths. If we
13753 have a key operand, use its width, else use the width of
13754 the current operand. */
13760 if (regwidth != match)
13762 first_error (_("operand size must match register width"));
13767 if ((thisarg & N_EQK) == 0)
13769 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13771 if ((given_type & types_allowed) == 0)
13773 first_error (_("bad type in Neon instruction"));
13779 enum neon_el_type mod_k_type = k_type;
13780 unsigned mod_k_size = k_size;
13781 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13782 if (g_type != mod_k_type || g_size != mod_k_size)
13784 first_error (_("inconsistent types in Neon instruction"));
13792 return inst.vectype.el[key_el];
13795 /* Neon-style VFP instruction forwarding. */
13797 /* Thumb VFP instructions have 0xE in the condition field. */
13800 do_vfp_cond_or_thumb (void)
13805 inst.instruction |= 0xe0000000;
13807 inst.instruction |= inst.cond << 28;
13810 /* Look up and encode a simple mnemonic, for use as a helper function for the
13811 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13812 etc. It is assumed that operand parsing has already been done, and that the
13813 operands are in the form expected by the given opcode (this isn't necessarily
13814 the same as the form in which they were parsed, hence some massaging must
13815 take place before this function is called).
13816 Checks current arch version against that in the looked-up opcode. */
13819 do_vfp_nsyn_opcode (const char *opname)
13821 const struct asm_opcode *opcode;
13823 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
13828 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
13829 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13836 inst.instruction = opcode->tvalue;
13837 opcode->tencode ();
13841 inst.instruction = (inst.cond << 28) | opcode->avalue;
13842 opcode->aencode ();
13847 do_vfp_nsyn_add_sub (enum neon_shape rs)
13849 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13854 do_vfp_nsyn_opcode ("fadds");
13856 do_vfp_nsyn_opcode ("fsubs");
13861 do_vfp_nsyn_opcode ("faddd");
13863 do_vfp_nsyn_opcode ("fsubd");
13867 /* Check operand types to see if this is a VFP instruction, and if so call
13871 try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13873 enum neon_shape rs;
13874 struct neon_type_el et;
13879 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13880 et = neon_check_type (2, rs,
13881 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13885 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13886 et = neon_check_type (3, rs,
13887 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
13894 if (et.type != NT_invtype)
13905 do_vfp_nsyn_mla_mls (enum neon_shape rs)
13907 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
13912 do_vfp_nsyn_opcode ("fmacs");
13914 do_vfp_nsyn_opcode ("fnmacs");
13919 do_vfp_nsyn_opcode ("fmacd");
13921 do_vfp_nsyn_opcode ("fnmacd");
13926 do_vfp_nsyn_fma_fms (enum neon_shape rs)
13928 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13933 do_vfp_nsyn_opcode ("ffmas");
13935 do_vfp_nsyn_opcode ("ffnmas");
13940 do_vfp_nsyn_opcode ("ffmad");
13942 do_vfp_nsyn_opcode ("ffnmad");
13947 do_vfp_nsyn_mul (enum neon_shape rs)
13950 do_vfp_nsyn_opcode ("fmuls");
13952 do_vfp_nsyn_opcode ("fmuld");
13956 do_vfp_nsyn_abs_neg (enum neon_shape rs)
13958 int is_neg = (inst.instruction & 0x80) != 0;
13959 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13964 do_vfp_nsyn_opcode ("fnegs");
13966 do_vfp_nsyn_opcode ("fabss");
13971 do_vfp_nsyn_opcode ("fnegd");
13973 do_vfp_nsyn_opcode ("fabsd");
13977 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13978 insns belong to Neon, and are handled elsewhere. */
13981 do_vfp_nsyn_ldm_stm (int is_dbmode)
13983 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13987 do_vfp_nsyn_opcode ("fldmdbs");
13989 do_vfp_nsyn_opcode ("fldmias");
13994 do_vfp_nsyn_opcode ("fstmdbs");
13996 do_vfp_nsyn_opcode ("fstmias");
14001 do_vfp_nsyn_sqrt (void)
14003 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
14004 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
14007 do_vfp_nsyn_opcode ("fsqrts");
14009 do_vfp_nsyn_opcode ("fsqrtd");
14013 do_vfp_nsyn_div (void)
14015 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
14016 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14017 N_F32 | N_F64 | N_KEY | N_VFP);
14020 do_vfp_nsyn_opcode ("fdivs");
14022 do_vfp_nsyn_opcode ("fdivd");
14026 do_vfp_nsyn_nmul (void)
14028 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
14029 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
14030 N_F32 | N_F64 | N_KEY | N_VFP);
14034 NEON_ENCODE (SINGLE, inst);
14035 do_vfp_sp_dyadic ();
14039 NEON_ENCODE (DOUBLE, inst);
14040 do_vfp_dp_rd_rn_rm ();
14042 do_vfp_cond_or_thumb ();
14046 do_vfp_nsyn_cmp (void)
14048 if (inst.operands[1].isreg)
14050 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
14051 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
14055 NEON_ENCODE (SINGLE, inst);
14056 do_vfp_sp_monadic ();
14060 NEON_ENCODE (DOUBLE, inst);
14061 do_vfp_dp_rd_rm ();
14066 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
14067 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
14069 switch (inst.instruction & 0x0fffffff)
14072 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
14075 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
14083 NEON_ENCODE (SINGLE, inst);
14084 do_vfp_sp_compare_z ();
14088 NEON_ENCODE (DOUBLE, inst);
14092 do_vfp_cond_or_thumb ();
14096 nsyn_insert_sp (void)
14098 inst.operands[1] = inst.operands[0];
14099 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
14100 inst.operands[0].reg = REG_SP;
14101 inst.operands[0].isreg = 1;
14102 inst.operands[0].writeback = 1;
14103 inst.operands[0].present = 1;
14107 do_vfp_nsyn_push (void)
14110 if (inst.operands[1].issingle)
14111 do_vfp_nsyn_opcode ("fstmdbs");
14113 do_vfp_nsyn_opcode ("fstmdbd");
14117 do_vfp_nsyn_pop (void)
14120 if (inst.operands[1].issingle)
14121 do_vfp_nsyn_opcode ("fldmias");
14123 do_vfp_nsyn_opcode ("fldmiad");
14126 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14127 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14130 neon_dp_fixup (struct arm_it* insn)
14132 unsigned int i = insn->instruction;
14137 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14148 insn->instruction = i;
14151 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14155 neon_logbits (unsigned x)
14157 return ffs (x) - 4;
14160 #define LOW4(R) ((R) & 0xf)
14161 #define HI1(R) (((R) >> 4) & 1)
14163 /* Encode insns with bit pattern:
14165 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14166 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14168 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14169 different meaning for some instruction. */
14172 neon_three_same (int isquad, int ubit, int size)
14174 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14175 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14176 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14177 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14178 inst.instruction |= LOW4 (inst.operands[2].reg);
14179 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14180 inst.instruction |= (isquad != 0) << 6;
14181 inst.instruction |= (ubit != 0) << 24;
14183 inst.instruction |= neon_logbits (size) << 20;
14185 neon_dp_fixup (&inst);
14188 /* Encode instructions of the form:
14190 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14191 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14193 Don't write size if SIZE == -1. */
14196 neon_two_same (int qbit, int ubit, int size)
14198 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14199 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14200 inst.instruction |= LOW4 (inst.operands[1].reg);
14201 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14202 inst.instruction |= (qbit != 0) << 6;
14203 inst.instruction |= (ubit != 0) << 24;
14206 inst.instruction |= neon_logbits (size) << 18;
14208 neon_dp_fixup (&inst);
14211 /* Neon instruction encoders, in approximate order of appearance. */
14214 do_neon_dyadic_i_su (void)
14216 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14217 struct neon_type_el et = neon_check_type (3, rs,
14218 N_EQK, N_EQK, N_SU_32 | N_KEY);
14219 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14223 do_neon_dyadic_i64_su (void)
14225 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14226 struct neon_type_el et = neon_check_type (3, rs,
14227 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14228 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14232 neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
14235 unsigned size = et.size >> 3;
14236 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14237 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14238 inst.instruction |= LOW4 (inst.operands[1].reg);
14239 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14240 inst.instruction |= (isquad != 0) << 6;
14241 inst.instruction |= immbits << 16;
14242 inst.instruction |= (size >> 3) << 7;
14243 inst.instruction |= (size & 0x7) << 19;
14245 inst.instruction |= (uval != 0) << 24;
14247 neon_dp_fixup (&inst);
14251 do_neon_shl_imm (void)
14253 if (!inst.operands[2].isreg)
14255 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14256 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
14257 int imm = inst.operands[2].imm;
14259 constraint (imm < 0 || (unsigned)imm >= et.size,
14260 _("immediate out of range for shift"));
14261 NEON_ENCODE (IMMED, inst);
14262 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14266 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14267 struct neon_type_el et = neon_check_type (3, rs,
14268 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14271 /* VSHL/VQSHL 3-register variants have syntax such as:
14273 whereas other 3-register operations encoded by neon_three_same have
14276 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14278 tmp = inst.operands[2].reg;
14279 inst.operands[2].reg = inst.operands[1].reg;
14280 inst.operands[1].reg = tmp;
14281 NEON_ENCODE (INTEGER, inst);
14282 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14287 do_neon_qshl_imm (void)
14289 if (!inst.operands[2].isreg)
14291 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14292 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
14293 int imm = inst.operands[2].imm;
14295 constraint (imm < 0 || (unsigned)imm >= et.size,
14296 _("immediate out of range for shift"));
14297 NEON_ENCODE (IMMED, inst);
14298 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
14302 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14303 struct neon_type_el et = neon_check_type (3, rs,
14304 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
14307 /* See note in do_neon_shl_imm. */
14308 tmp = inst.operands[2].reg;
14309 inst.operands[2].reg = inst.operands[1].reg;
14310 inst.operands[1].reg = tmp;
14311 NEON_ENCODE (INTEGER, inst);
14312 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14317 do_neon_rshl (void)
14319 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14320 struct neon_type_el et = neon_check_type (3, rs,
14321 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14324 tmp = inst.operands[2].reg;
14325 inst.operands[2].reg = inst.operands[1].reg;
14326 inst.operands[1].reg = tmp;
14327 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14331 neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14333 /* Handle .I8 pseudo-instructions. */
14336 /* Unfortunately, this will make everything apart from zero out-of-range.
14337 FIXME is this the intended semantics? There doesn't seem much point in
14338 accepting .I8 if so. */
14339 immediate |= immediate << 8;
14345 if (immediate == (immediate & 0x000000ff))
14347 *immbits = immediate;
14350 else if (immediate == (immediate & 0x0000ff00))
14352 *immbits = immediate >> 8;
14355 else if (immediate == (immediate & 0x00ff0000))
14357 *immbits = immediate >> 16;
14360 else if (immediate == (immediate & 0xff000000))
14362 *immbits = immediate >> 24;
14365 if ((immediate & 0xffff) != (immediate >> 16))
14366 goto bad_immediate;
14367 immediate &= 0xffff;
14370 if (immediate == (immediate & 0x000000ff))
14372 *immbits = immediate;
14375 else if (immediate == (immediate & 0x0000ff00))
14377 *immbits = immediate >> 8;
14382 first_error (_("immediate value out of range"));
14387 do_neon_logic (void)
14389 if (inst.operands[2].present && inst.operands[2].isreg)
14391 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14392 neon_check_type (3, rs, N_IGNORE_TYPE);
14393 /* U bit and size field were set as part of the bitmask. */
14394 NEON_ENCODE (INTEGER, inst);
14395 neon_three_same (neon_quad (rs), 0, -1);
14399 const int three_ops_form = (inst.operands[2].present
14400 && !inst.operands[2].isreg);
14401 const int immoperand = (three_ops_form ? 2 : 1);
14402 enum neon_shape rs = (three_ops_form
14403 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14404 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
14405 struct neon_type_el et = neon_check_type (2, rs,
14406 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
14407 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
14411 if (et.type == NT_invtype)
14414 if (three_ops_form)
14415 constraint (inst.operands[0].reg != inst.operands[1].reg,
14416 _("first and second operands shall be the same register"));
14418 NEON_ENCODE (IMMED, inst);
14420 immbits = inst.operands[immoperand].imm;
14423 /* .i64 is a pseudo-op, so the immediate must be a repeating
14425 if (immbits != (inst.operands[immoperand].regisimm ?
14426 inst.operands[immoperand].reg : 0))
14428 /* Set immbits to an invalid constant. */
14429 immbits = 0xdeadbeef;
14436 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14440 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14444 /* Pseudo-instruction for VBIC. */
14445 neon_invert_size (&immbits, 0, et.size);
14446 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14450 /* Pseudo-instruction for VORR. */
14451 neon_invert_size (&immbits, 0, et.size);
14452 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14462 inst.instruction |= neon_quad (rs) << 6;
14463 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14464 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14465 inst.instruction |= cmode << 8;
14466 neon_write_immbits (immbits);
14468 neon_dp_fixup (&inst);
14473 do_neon_bitfield (void)
14475 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14476 neon_check_type (3, rs, N_IGNORE_TYPE);
14477 neon_three_same (neon_quad (rs), 0, -1);
14481 neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
14484 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14485 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
14487 if (et.type == NT_float)
14489 NEON_ENCODE (FLOAT, inst);
14490 neon_three_same (neon_quad (rs), 0, -1);
14494 NEON_ENCODE (INTEGER, inst);
14495 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
14500 do_neon_dyadic_if_su (void)
14502 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14506 do_neon_dyadic_if_su_d (void)
14508 /* This version only allow D registers, but that constraint is enforced during
14509 operand parsing so we don't need to do anything extra here. */
14510 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
14514 do_neon_dyadic_if_i_d (void)
14516 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14517 affected if we specify unsigned args. */
14518 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14521 enum vfp_or_neon_is_neon_bits
14524 NEON_CHECK_ARCH = 2,
14525 NEON_CHECK_ARCH8 = 4
14528 /* Call this function if an instruction which may have belonged to the VFP or
14529 Neon instruction sets, but turned out to be a Neon instruction (due to the
14530 operand types involved, etc.). We have to check and/or fix-up a couple of
14533 - Make sure the user hasn't attempted to make a Neon instruction
14535 - Alter the value in the condition code field if necessary.
14536 - Make sure that the arch supports Neon instructions.
14538 Which of these operations take place depends on bits from enum
14539 vfp_or_neon_is_neon_bits.
14541 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14542 current instruction's condition is COND_ALWAYS, the condition field is
14543 changed to inst.uncond_value. This is necessary because instructions shared
14544 between VFP and Neon may be conditional for the VFP variants only, and the
14545 unconditional Neon version must have, e.g., 0xF in the condition field. */
14548 vfp_or_neon_is_neon (unsigned check)
14550 /* Conditions are always legal in Thumb mode (IT blocks). */
14551 if (!thumb_mode && (check & NEON_CHECK_CC))
14553 if (inst.cond != COND_ALWAYS)
14555 first_error (_(BAD_COND));
14558 if (inst.uncond_value != -1)
14559 inst.instruction |= inst.uncond_value << 28;
14562 if ((check & NEON_CHECK_ARCH)
14563 && !mark_feature_used (&fpu_neon_ext_v1))
14565 first_error (_(BAD_FPU));
14569 if ((check & NEON_CHECK_ARCH8)
14570 && !mark_feature_used (&fpu_neon_ext_armv8))
14572 first_error (_(BAD_FPU));
14580 do_neon_addsub_if_i (void)
14582 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14585 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14588 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14589 affected if we specify unsigned args. */
14590 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
14593 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14595 V<op> A,B (A is operand 0, B is operand 2)
14600 so handle that case specially. */
14603 neon_exchange_operands (void)
14605 void *scratch = alloca (sizeof (inst.operands[0]));
14606 if (inst.operands[1].present)
14608 /* Swap operands[1] and operands[2]. */
14609 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14610 inst.operands[1] = inst.operands[2];
14611 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14615 inst.operands[1] = inst.operands[2];
14616 inst.operands[2] = inst.operands[0];
14621 neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14623 if (inst.operands[2].isreg)
14626 neon_exchange_operands ();
14627 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
14631 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14632 struct neon_type_el et = neon_check_type (2, rs,
14633 N_EQK | N_SIZ, immtypes | N_KEY);
14635 NEON_ENCODE (IMMED, inst);
14636 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14637 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14638 inst.instruction |= LOW4 (inst.operands[1].reg);
14639 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14640 inst.instruction |= neon_quad (rs) << 6;
14641 inst.instruction |= (et.type == NT_float) << 10;
14642 inst.instruction |= neon_logbits (et.size) << 18;
14644 neon_dp_fixup (&inst);
14651 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14655 do_neon_cmp_inv (void)
14657 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14663 neon_compare (N_IF_32, N_IF_32, FALSE);
14666 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14667 scalars, which are encoded in 5 bits, M : Rm.
14668 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14669 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14673 neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14675 unsigned regno = NEON_SCALAR_REG (scalar);
14676 unsigned elno = NEON_SCALAR_INDEX (scalar);
14681 if (regno > 7 || elno > 3)
14683 return regno | (elno << 3);
14686 if (regno > 15 || elno > 1)
14688 return regno | (elno << 4);
14692 first_error (_("scalar out of range for multiply instruction"));
14698 /* Encode multiply / multiply-accumulate scalar instructions. */
14701 neon_mul_mac (struct neon_type_el et, int ubit)
14705 /* Give a more helpful error message if we have an invalid type. */
14706 if (et.type == NT_invtype)
14709 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
14710 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14711 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14712 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14713 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14714 inst.instruction |= LOW4 (scalar);
14715 inst.instruction |= HI1 (scalar) << 5;
14716 inst.instruction |= (et.type == NT_float) << 8;
14717 inst.instruction |= neon_logbits (et.size) << 20;
14718 inst.instruction |= (ubit != 0) << 24;
14720 neon_dp_fixup (&inst);
14724 do_neon_mac_maybe_scalar (void)
14726 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14729 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14732 if (inst.operands[2].isscalar)
14734 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14735 struct neon_type_el et = neon_check_type (3, rs,
14736 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
14737 NEON_ENCODE (SCALAR, inst);
14738 neon_mul_mac (et, neon_quad (rs));
14742 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14743 affected if we specify unsigned args. */
14744 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14749 do_neon_fmac (void)
14751 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14754 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14757 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14763 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14764 struct neon_type_el et = neon_check_type (3, rs,
14765 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
14766 neon_three_same (neon_quad (rs), 0, et.size);
14769 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14770 same types as the MAC equivalents. The polynomial type for this instruction
14771 is encoded the same as the integer type. */
14776 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14779 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14782 if (inst.operands[2].isscalar)
14783 do_neon_mac_maybe_scalar ();
14785 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
14789 do_neon_qdmulh (void)
14791 if (inst.operands[2].isscalar)
14793 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
14794 struct neon_type_el et = neon_check_type (3, rs,
14795 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14796 NEON_ENCODE (SCALAR, inst);
14797 neon_mul_mac (et, neon_quad (rs));
14801 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14802 struct neon_type_el et = neon_check_type (3, rs,
14803 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
14804 NEON_ENCODE (INTEGER, inst);
14805 /* The U bit (rounding) comes from bit mask. */
14806 neon_three_same (neon_quad (rs), 0, et.size);
14811 do_neon_fcmp_absolute (void)
14813 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14814 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14815 /* Size field comes from bit mask. */
14816 neon_three_same (neon_quad (rs), 1, -1);
14820 do_neon_fcmp_absolute_inv (void)
14822 neon_exchange_operands ();
14823 do_neon_fcmp_absolute ();
14827 do_neon_step (void)
14829 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14830 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14831 neon_three_same (neon_quad (rs), 0, -1);
14835 do_neon_abs_neg (void)
14837 enum neon_shape rs;
14838 struct neon_type_el et;
14840 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14843 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14846 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14847 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
14849 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14850 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14851 inst.instruction |= LOW4 (inst.operands[1].reg);
14852 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14853 inst.instruction |= neon_quad (rs) << 6;
14854 inst.instruction |= (et.type == NT_float) << 10;
14855 inst.instruction |= neon_logbits (et.size) << 18;
14857 neon_dp_fixup (&inst);
14863 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14864 struct neon_type_el et = neon_check_type (2, rs,
14865 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14866 int imm = inst.operands[2].imm;
14867 constraint (imm < 0 || (unsigned)imm >= et.size,
14868 _("immediate out of range for insert"));
14869 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14875 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14876 struct neon_type_el et = neon_check_type (2, rs,
14877 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14878 int imm = inst.operands[2].imm;
14879 constraint (imm < 1 || (unsigned)imm > et.size,
14880 _("immediate out of range for insert"));
14881 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
14885 do_neon_qshlu_imm (void)
14887 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
14888 struct neon_type_el et = neon_check_type (2, rs,
14889 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14890 int imm = inst.operands[2].imm;
14891 constraint (imm < 0 || (unsigned)imm >= et.size,
14892 _("immediate out of range for shift"));
14893 /* Only encodes the 'U present' variant of the instruction.
14894 In this case, signed types have OP (bit 8) set to 0.
14895 Unsigned types have OP set to 1. */
14896 inst.instruction |= (et.type == NT_unsigned) << 8;
14897 /* The rest of the bits are the same as other immediate shifts. */
14898 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
14902 do_neon_qmovn (void)
14904 struct neon_type_el et = neon_check_type (2, NS_DQ,
14905 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14906 /* Saturating move where operands can be signed or unsigned, and the
14907 destination has the same signedness. */
14908 NEON_ENCODE (INTEGER, inst);
14909 if (et.type == NT_unsigned)
14910 inst.instruction |= 0xc0;
14912 inst.instruction |= 0x80;
14913 neon_two_same (0, 1, et.size / 2);
14917 do_neon_qmovun (void)
14919 struct neon_type_el et = neon_check_type (2, NS_DQ,
14920 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14921 /* Saturating move with unsigned results. Operands must be signed. */
14922 NEON_ENCODE (INTEGER, inst);
14923 neon_two_same (0, 1, et.size / 2);
14927 do_neon_rshift_sat_narrow (void)
14929 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14930 or unsigned. If operands are unsigned, results must also be unsigned. */
14931 struct neon_type_el et = neon_check_type (2, NS_DQI,
14932 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14933 int imm = inst.operands[2].imm;
14934 /* This gets the bounds check, size encoding and immediate bits calculation
14938 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14939 VQMOVN.I<size> <Dd>, <Qm>. */
14942 inst.operands[2].present = 0;
14943 inst.instruction = N_MNEM_vqmovn;
14948 constraint (imm < 1 || (unsigned)imm > et.size,
14949 _("immediate out of range"));
14950 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14954 do_neon_rshift_sat_narrow_u (void)
14956 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14957 or unsigned. If operands are unsigned, results must also be unsigned. */
14958 struct neon_type_el et = neon_check_type (2, NS_DQI,
14959 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14960 int imm = inst.operands[2].imm;
14961 /* This gets the bounds check, size encoding and immediate bits calculation
14965 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14966 VQMOVUN.I<size> <Dd>, <Qm>. */
14969 inst.operands[2].present = 0;
14970 inst.instruction = N_MNEM_vqmovun;
14975 constraint (imm < 1 || (unsigned)imm > et.size,
14976 _("immediate out of range"));
14977 /* FIXME: The manual is kind of unclear about what value U should have in
14978 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14980 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14984 do_neon_movn (void)
14986 struct neon_type_el et = neon_check_type (2, NS_DQ,
14987 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14988 NEON_ENCODE (INTEGER, inst);
14989 neon_two_same (0, 1, et.size / 2);
14993 do_neon_rshift_narrow (void)
14995 struct neon_type_el et = neon_check_type (2, NS_DQI,
14996 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14997 int imm = inst.operands[2].imm;
14998 /* This gets the bounds check, size encoding and immediate bits calculation
15002 /* If immediate is zero then we are a pseudo-instruction for
15003 VMOVN.I<size> <Dd>, <Qm> */
15006 inst.operands[2].present = 0;
15007 inst.instruction = N_MNEM_vmovn;
15012 constraint (imm < 1 || (unsigned)imm > et.size,
15013 _("immediate out of range for narrowing operation"));
15014 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
15018 do_neon_shll (void)
15020 /* FIXME: Type checking when lengthening. */
15021 struct neon_type_el et = neon_check_type (2, NS_QDI,
15022 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
15023 unsigned imm = inst.operands[2].imm;
15025 if (imm == et.size)
15027 /* Maximum shift variant. */
15028 NEON_ENCODE (INTEGER, inst);
15029 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15030 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15031 inst.instruction |= LOW4 (inst.operands[1].reg);
15032 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15033 inst.instruction |= neon_logbits (et.size) << 18;
15035 neon_dp_fixup (&inst);
15039 /* A more-specific type check for non-max versions. */
15040 et = neon_check_type (2, NS_QDI,
15041 N_EQK | N_DBL, N_SU_32 | N_KEY);
15042 NEON_ENCODE (IMMED, inst);
15043 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
15047 /* Check the various types for the VCVT instruction, and return which version
15048 the current instruction is. */
15050 #define CVT_FLAVOUR_VAR \
15051 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15052 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15053 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15054 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15055 /* Half-precision conversions. */ \
15056 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15057 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15058 /* VFP instructions. */ \
15059 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15060 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15061 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15062 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15063 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15064 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15065 /* VFP instructions with bitshift. */ \
15066 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15067 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15068 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15069 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15070 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15071 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15072 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15073 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15075 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15076 neon_cvt_flavour_##C,
15078 /* The different types of conversions we can do. */
15079 enum neon_cvt_flavour
15082 neon_cvt_flavour_invalid,
15083 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
15088 static enum neon_cvt_flavour
15089 get_neon_cvt_flavour (enum neon_shape rs)
15091 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15092 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15093 if (et.type != NT_invtype) \
15095 inst.error = NULL; \
15096 return (neon_cvt_flavour_##C); \
15099 struct neon_type_el et;
15100 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
15101 || rs == NS_FF) ? N_VFP : 0;
15102 /* The instruction versions which take an immediate take one register
15103 argument, which is extended to the width of the full register. Thus the
15104 "source" and "destination" registers must have the same width. Hack that
15105 here by making the size equal to the key (wider, in this case) operand. */
15106 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
15110 return neon_cvt_flavour_invalid;
15125 /* Neon-syntax VFP conversions. */
15128 do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
15130 const char *opname = 0;
15132 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
15134 /* Conversions with immediate bitshift. */
15135 const char *enc[] =
15137 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15143 if (flavour < (int) ARRAY_SIZE (enc))
15145 opname = enc[flavour];
15146 constraint (inst.operands[0].reg != inst.operands[1].reg,
15147 _("operands 0 and 1 must be the same register"));
15148 inst.operands[1] = inst.operands[2];
15149 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
15154 /* Conversions without bitshift. */
15155 const char *enc[] =
15157 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15163 if (flavour < (int) ARRAY_SIZE (enc))
15164 opname = enc[flavour];
15168 do_vfp_nsyn_opcode (opname);
15172 do_vfp_nsyn_cvtz (void)
15174 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
15175 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15176 const char *enc[] =
15178 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15184 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
15185 do_vfp_nsyn_opcode (enc[flavour]);
15189 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
15190 enum neon_cvt_mode mode)
15195 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15196 D register operands. */
15197 if (flavour == neon_cvt_flavour_s32_f64
15198 || flavour == neon_cvt_flavour_u32_f64)
15199 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15202 set_it_insn_type (OUTSIDE_IT_INSN);
15206 case neon_cvt_flavour_s32_f64:
15210 case neon_cvt_flavour_s32_f32:
15214 case neon_cvt_flavour_u32_f64:
15218 case neon_cvt_flavour_u32_f32:
15223 first_error (_("invalid instruction shape"));
15229 case neon_cvt_mode_a: rm = 0; break;
15230 case neon_cvt_mode_n: rm = 1; break;
15231 case neon_cvt_mode_p: rm = 2; break;
15232 case neon_cvt_mode_m: rm = 3; break;
15233 default: first_error (_("invalid rounding mode")); return;
15236 NEON_ENCODE (FPV8, inst);
15237 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15238 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15239 inst.instruction |= sz << 8;
15240 inst.instruction |= op << 7;
15241 inst.instruction |= rm << 16;
15242 inst.instruction |= 0xf0000000;
15243 inst.is_neon = TRUE;
15247 do_neon_cvt_1 (enum neon_cvt_mode mode)
15249 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
15250 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
15251 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
15253 /* PR11109: Handle round-to-zero for VCVT conversions. */
15254 if (mode == neon_cvt_mode_z
15255 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
15256 && (flavour == neon_cvt_flavour_s32_f32
15257 || flavour == neon_cvt_flavour_u32_f32
15258 || flavour == neon_cvt_flavour_s32_f64
15259 || flavour == neon_cvt_flavour_u32_f64)
15260 && (rs == NS_FD || rs == NS_FF))
15262 do_vfp_nsyn_cvtz ();
15266 /* VFP rather than Neon conversions. */
15267 if (flavour >= neon_cvt_flavour_first_fp)
15269 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15270 do_vfp_nsyn_cvt (rs, flavour);
15272 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15283 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
15285 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15288 /* Fixed-point conversion with #0 immediate is encoded as an
15289 integer conversion. */
15290 if (inst.operands[2].present && inst.operands[2].imm == 0)
15292 immbits = 32 - inst.operands[2].imm;
15293 NEON_ENCODE (IMMED, inst);
15294 if (flavour != neon_cvt_flavour_invalid)
15295 inst.instruction |= enctab[flavour];
15296 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15297 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15298 inst.instruction |= LOW4 (inst.operands[1].reg);
15299 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15300 inst.instruction |= neon_quad (rs) << 6;
15301 inst.instruction |= 1 << 21;
15302 inst.instruction |= immbits << 16;
15304 neon_dp_fixup (&inst);
15310 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15312 NEON_ENCODE (FLOAT, inst);
15313 set_it_insn_type (OUTSIDE_IT_INSN);
15315 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15318 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15319 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15320 inst.instruction |= LOW4 (inst.operands[1].reg);
15321 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15322 inst.instruction |= neon_quad (rs) << 6;
15323 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
15324 inst.instruction |= mode << 8;
15326 inst.instruction |= 0xfc000000;
15328 inst.instruction |= 0xf0000000;
15334 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
15336 NEON_ENCODE (INTEGER, inst);
15338 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15341 if (flavour != neon_cvt_flavour_invalid)
15342 inst.instruction |= enctab[flavour];
15344 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15345 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15346 inst.instruction |= LOW4 (inst.operands[1].reg);
15347 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15348 inst.instruction |= neon_quad (rs) << 6;
15349 inst.instruction |= 2 << 18;
15351 neon_dp_fixup (&inst);
15356 /* Half-precision conversions for Advanced SIMD -- neon. */
15361 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15363 as_bad (_("operand size must match register width"));
15368 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15370 as_bad (_("operand size must match register width"));
15375 inst.instruction = 0x3b60600;
15377 inst.instruction = 0x3b60700;
15379 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15380 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15381 inst.instruction |= LOW4 (inst.operands[1].reg);
15382 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15383 neon_dp_fixup (&inst);
15387 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15388 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15389 do_vfp_nsyn_cvt (rs, flavour);
15391 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15396 do_neon_cvtr (void)
15398 do_neon_cvt_1 (neon_cvt_mode_x);
15404 do_neon_cvt_1 (neon_cvt_mode_z);
15408 do_neon_cvta (void)
15410 do_neon_cvt_1 (neon_cvt_mode_a);
15414 do_neon_cvtn (void)
15416 do_neon_cvt_1 (neon_cvt_mode_n);
15420 do_neon_cvtp (void)
15422 do_neon_cvt_1 (neon_cvt_mode_p);
15426 do_neon_cvtm (void)
15428 do_neon_cvt_1 (neon_cvt_mode_m);
15432 do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
15435 mark_feature_used (&fpu_vfp_ext_armv8);
15437 encode_arm_vfp_reg (inst.operands[0].reg,
15438 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15439 encode_arm_vfp_reg (inst.operands[1].reg,
15440 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
15441 inst.instruction |= to ? 0x10000 : 0;
15442 inst.instruction |= t ? 0x80 : 0;
15443 inst.instruction |= is_double ? 0x100 : 0;
15444 do_vfp_cond_or_thumb ();
15448 do_neon_cvttb_1 (bfd_boolean t)
15450 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
15454 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
15457 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
15459 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
15462 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
15464 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
15466 /* The VCVTB and VCVTT instructions with D-register operands
15467 don't work for SP only targets. */
15468 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15472 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
15474 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
15476 /* The VCVTB and VCVTT instructions with D-register operands
15477 don't work for SP only targets. */
15478 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15482 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
15489 do_neon_cvtb (void)
15491 do_neon_cvttb_1 (FALSE);
15496 do_neon_cvtt (void)
15498 do_neon_cvttb_1 (TRUE);
15502 neon_move_immediate (void)
15504 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
15505 struct neon_type_el et = neon_check_type (2, rs,
15506 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
15507 unsigned immlo, immhi = 0, immbits;
15508 int op, cmode, float_p;
15510 constraint (et.type == NT_invtype,
15511 _("operand size must be specified for immediate VMOV"));
15513 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15514 op = (inst.instruction & (1 << 5)) != 0;
15516 immlo = inst.operands[1].imm;
15517 if (inst.operands[1].regisimm)
15518 immhi = inst.operands[1].reg;
15520 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
15521 _("immediate has bits set outside the operand size"));
15523 float_p = inst.operands[1].immisfloat;
15525 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
15526 et.size, et.type)) == FAIL)
15528 /* Invert relevant bits only. */
15529 neon_invert_size (&immlo, &immhi, et.size);
15530 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15531 with one or the other; those cases are caught by
15532 neon_cmode_for_move_imm. */
15534 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15535 &op, et.size, et.type)) == FAIL)
15537 first_error (_("immediate out of range"));
15542 inst.instruction &= ~(1 << 5);
15543 inst.instruction |= op << 5;
15545 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15546 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15547 inst.instruction |= neon_quad (rs) << 6;
15548 inst.instruction |= cmode << 8;
15550 neon_write_immbits (immbits);
15556 if (inst.operands[1].isreg)
15558 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15560 NEON_ENCODE (INTEGER, inst);
15561 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15562 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15563 inst.instruction |= LOW4 (inst.operands[1].reg);
15564 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15565 inst.instruction |= neon_quad (rs) << 6;
15569 NEON_ENCODE (IMMED, inst);
15570 neon_move_immediate ();
15573 neon_dp_fixup (&inst);
15576 /* Encode instructions of form:
15578 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15579 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15582 neon_mixed_length (struct neon_type_el et, unsigned size)
15584 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15585 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15586 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15587 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15588 inst.instruction |= LOW4 (inst.operands[2].reg);
15589 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15590 inst.instruction |= (et.type == NT_unsigned) << 24;
15591 inst.instruction |= neon_logbits (size) << 20;
15593 neon_dp_fixup (&inst);
15597 do_neon_dyadic_long (void)
15599 /* FIXME: Type checking for lengthening op. */
15600 struct neon_type_el et = neon_check_type (3, NS_QDD,
15601 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15602 neon_mixed_length (et, et.size);
15606 do_neon_abal (void)
15608 struct neon_type_el et = neon_check_type (3, NS_QDD,
15609 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15610 neon_mixed_length (et, et.size);
15614 neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15616 if (inst.operands[2].isscalar)
15618 struct neon_type_el et = neon_check_type (3, NS_QDS,
15619 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
15620 NEON_ENCODE (SCALAR, inst);
15621 neon_mul_mac (et, et.type == NT_unsigned);
15625 struct neon_type_el et = neon_check_type (3, NS_QDD,
15626 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
15627 NEON_ENCODE (INTEGER, inst);
15628 neon_mixed_length (et, et.size);
15633 do_neon_mac_maybe_scalar_long (void)
15635 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15639 do_neon_dyadic_wide (void)
15641 struct neon_type_el et = neon_check_type (3, NS_QQD,
15642 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15643 neon_mixed_length (et, et.size);
15647 do_neon_dyadic_narrow (void)
15649 struct neon_type_el et = neon_check_type (3, NS_QDD,
15650 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
15651 /* Operand sign is unimportant, and the U bit is part of the opcode,
15652 so force the operand type to integer. */
15653 et.type = NT_integer;
15654 neon_mixed_length (et, et.size / 2);
15658 do_neon_mul_sat_scalar_long (void)
15660 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15664 do_neon_vmull (void)
15666 if (inst.operands[2].isscalar)
15667 do_neon_mac_maybe_scalar_long ();
15670 struct neon_type_el et = neon_check_type (3, NS_QDD,
15671 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
15673 if (et.type == NT_poly)
15674 NEON_ENCODE (POLY, inst);
15676 NEON_ENCODE (INTEGER, inst);
15678 /* For polynomial encoding the U bit must be zero, and the size must
15679 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15680 obviously, as 0b10). */
15683 /* Check we're on the correct architecture. */
15684 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15686 _("Instruction form not available on this architecture.");
15691 neon_mixed_length (et, et.size);
15698 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
15699 struct neon_type_el et = neon_check_type (3, rs,
15700 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15701 unsigned imm = (inst.operands[3].imm * et.size) / 8;
15703 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15704 _("shift out of range"));
15705 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15706 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15707 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15708 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15709 inst.instruction |= LOW4 (inst.operands[2].reg);
15710 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15711 inst.instruction |= neon_quad (rs) << 6;
15712 inst.instruction |= imm << 8;
15714 neon_dp_fixup (&inst);
15720 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15721 struct neon_type_el et = neon_check_type (2, rs,
15722 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15723 unsigned op = (inst.instruction >> 7) & 3;
15724 /* N (width of reversed regions) is encoded as part of the bitmask. We
15725 extract it here to check the elements to be reversed are smaller.
15726 Otherwise we'd get a reserved instruction. */
15727 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
15728 gas_assert (elsize != 0);
15729 constraint (et.size >= elsize,
15730 _("elements must be smaller than reversal region"));
15731 neon_two_same (neon_quad (rs), 1, et.size);
15737 if (inst.operands[1].isscalar)
15739 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
15740 struct neon_type_el et = neon_check_type (2, rs,
15741 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15742 unsigned sizebits = et.size >> 3;
15743 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
15744 int logsize = neon_logbits (et.size);
15745 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
15747 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
15750 NEON_ENCODE (SCALAR, inst);
15751 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15752 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15753 inst.instruction |= LOW4 (dm);
15754 inst.instruction |= HI1 (dm) << 5;
15755 inst.instruction |= neon_quad (rs) << 6;
15756 inst.instruction |= x << 17;
15757 inst.instruction |= sizebits << 16;
15759 neon_dp_fixup (&inst);
15763 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15764 struct neon_type_el et = neon_check_type (2, rs,
15765 N_8 | N_16 | N_32 | N_KEY, N_EQK);
15766 /* Duplicate ARM register to lanes of vector. */
15767 NEON_ENCODE (ARMREG, inst);
15770 case 8: inst.instruction |= 0x400000; break;
15771 case 16: inst.instruction |= 0x000020; break;
15772 case 32: inst.instruction |= 0x000000; break;
15775 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15776 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15777 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
15778 inst.instruction |= neon_quad (rs) << 21;
15779 /* The encoding for this instruction is identical for the ARM and Thumb
15780 variants, except for the condition field. */
15781 do_vfp_cond_or_thumb ();
15785 /* VMOV has particularly many variations. It can be one of:
15786 0. VMOV<c><q> <Qd>, <Qm>
15787 1. VMOV<c><q> <Dd>, <Dm>
15788 (Register operations, which are VORR with Rm = Rn.)
15789 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15790 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15792 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15793 (ARM register to scalar.)
15794 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15795 (Two ARM registers to vector.)
15796 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15797 (Scalar to ARM register.)
15798 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15799 (Vector to two ARM registers.)
15800 8. VMOV.F32 <Sd>, <Sm>
15801 9. VMOV.F64 <Dd>, <Dm>
15802 (VFP register moves.)
15803 10. VMOV.F32 <Sd>, #imm
15804 11. VMOV.F64 <Dd>, #imm
15805 (VFP float immediate load.)
15806 12. VMOV <Rd>, <Sm>
15807 (VFP single to ARM reg.)
15808 13. VMOV <Sd>, <Rm>
15809 (ARM reg to VFP single.)
15810 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15811 (Two ARM regs to two VFP singles.)
15812 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15813 (Two VFP singles to two ARM regs.)
15815 These cases can be disambiguated using neon_select_shape, except cases 1/9
15816 and 3/11 which depend on the operand type too.
15818 All the encoded bits are hardcoded by this function.
15820 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15821 Cases 5, 7 may be used with VFPv2 and above.
15823 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15824 can specify a type where it doesn't make sense to, and is ignored). */
15829 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15830 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15832 struct neon_type_el et;
15833 const char *ldconst = 0;
15837 case NS_DD: /* case 1/9. */
15838 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15839 /* It is not an error here if no type is given. */
15841 if (et.type == NT_float && et.size == 64)
15843 do_vfp_nsyn_opcode ("fcpyd");
15846 /* fall through. */
15848 case NS_QQ: /* case 0/1. */
15850 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15852 /* The architecture manual I have doesn't explicitly state which
15853 value the U bit should have for register->register moves, but
15854 the equivalent VORR instruction has U = 0, so do that. */
15855 inst.instruction = 0x0200110;
15856 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15857 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15858 inst.instruction |= LOW4 (inst.operands[1].reg);
15859 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15860 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15861 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15862 inst.instruction |= neon_quad (rs) << 6;
15864 neon_dp_fixup (&inst);
15868 case NS_DI: /* case 3/11. */
15869 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15871 if (et.type == NT_float && et.size == 64)
15873 /* case 11 (fconstd). */
15874 ldconst = "fconstd";
15875 goto encode_fconstd;
15877 /* fall through. */
15879 case NS_QI: /* case 2/3. */
15880 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15882 inst.instruction = 0x0800010;
15883 neon_move_immediate ();
15884 neon_dp_fixup (&inst);
15887 case NS_SR: /* case 4. */
15889 unsigned bcdebits = 0;
15891 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15892 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
15894 /* .<size> is optional here, defaulting to .32. */
15895 if (inst.vectype.elems == 0
15896 && inst.operands[0].vectype.type == NT_invtype
15897 && inst.operands[1].vectype.type == NT_invtype)
15899 inst.vectype.el[0].type = NT_untyped;
15900 inst.vectype.el[0].size = 32;
15901 inst.vectype.elems = 1;
15904 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15905 logsize = neon_logbits (et.size);
15907 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15909 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15910 && et.size != 32, _(BAD_FPU));
15911 constraint (et.type == NT_invtype, _("bad type for scalar"));
15912 constraint (x >= 64 / et.size, _("scalar index out of range"));
15916 case 8: bcdebits = 0x8; break;
15917 case 16: bcdebits = 0x1; break;
15918 case 32: bcdebits = 0x0; break;
15922 bcdebits |= x << logsize;
15924 inst.instruction = 0xe000b10;
15925 do_vfp_cond_or_thumb ();
15926 inst.instruction |= LOW4 (dn) << 16;
15927 inst.instruction |= HI1 (dn) << 7;
15928 inst.instruction |= inst.operands[1].reg << 12;
15929 inst.instruction |= (bcdebits & 3) << 5;
15930 inst.instruction |= (bcdebits >> 2) << 21;
15934 case NS_DRR: /* case 5 (fmdrr). */
15935 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15938 inst.instruction = 0xc400b10;
15939 do_vfp_cond_or_thumb ();
15940 inst.instruction |= LOW4 (inst.operands[0].reg);
15941 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15942 inst.instruction |= inst.operands[1].reg << 12;
15943 inst.instruction |= inst.operands[2].reg << 16;
15946 case NS_RS: /* case 6. */
15949 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15950 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15951 unsigned abcdebits = 0;
15953 /* .<dt> is optional here, defaulting to .32. */
15954 if (inst.vectype.elems == 0
15955 && inst.operands[0].vectype.type == NT_invtype
15956 && inst.operands[1].vectype.type == NT_invtype)
15958 inst.vectype.el[0].type = NT_untyped;
15959 inst.vectype.el[0].size = 32;
15960 inst.vectype.elems = 1;
15963 et = neon_check_type (2, NS_NULL,
15964 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
15965 logsize = neon_logbits (et.size);
15967 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15969 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15970 && et.size != 32, _(BAD_FPU));
15971 constraint (et.type == NT_invtype, _("bad type for scalar"));
15972 constraint (x >= 64 / et.size, _("scalar index out of range"));
15976 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15977 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15978 case 32: abcdebits = 0x00; break;
15982 abcdebits |= x << logsize;
15983 inst.instruction = 0xe100b10;
15984 do_vfp_cond_or_thumb ();
15985 inst.instruction |= LOW4 (dn) << 16;
15986 inst.instruction |= HI1 (dn) << 7;
15987 inst.instruction |= inst.operands[0].reg << 12;
15988 inst.instruction |= (abcdebits & 3) << 5;
15989 inst.instruction |= (abcdebits >> 2) << 21;
15993 case NS_RRD: /* case 7 (fmrrd). */
15994 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
15997 inst.instruction = 0xc500b10;
15998 do_vfp_cond_or_thumb ();
15999 inst.instruction |= inst.operands[0].reg << 12;
16000 inst.instruction |= inst.operands[1].reg << 16;
16001 inst.instruction |= LOW4 (inst.operands[2].reg);
16002 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16005 case NS_FF: /* case 8 (fcpys). */
16006 do_vfp_nsyn_opcode ("fcpys");
16009 case NS_FI: /* case 10 (fconsts). */
16010 ldconst = "fconsts";
16012 if (is_quarter_float (inst.operands[1].imm))
16014 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
16015 do_vfp_nsyn_opcode (ldconst);
16018 first_error (_("immediate out of range"));
16021 case NS_RF: /* case 12 (fmrs). */
16022 do_vfp_nsyn_opcode ("fmrs");
16025 case NS_FR: /* case 13 (fmsr). */
16026 do_vfp_nsyn_opcode ("fmsr");
16029 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16030 (one of which is a list), but we have parsed four. Do some fiddling to
16031 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16033 case NS_RRFF: /* case 14 (fmrrs). */
16034 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
16035 _("VFP registers must be adjacent"));
16036 inst.operands[2].imm = 2;
16037 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16038 do_vfp_nsyn_opcode ("fmrrs");
16041 case NS_FFRR: /* case 15 (fmsrr). */
16042 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
16043 _("VFP registers must be adjacent"));
16044 inst.operands[1] = inst.operands[2];
16045 inst.operands[2] = inst.operands[3];
16046 inst.operands[0].imm = 2;
16047 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
16048 do_vfp_nsyn_opcode ("fmsrr");
16052 /* neon_select_shape has determined that the instruction
16053 shape is wrong and has already set the error message. */
16062 do_neon_rshift_round_imm (void)
16064 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16065 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16066 int imm = inst.operands[2].imm;
16068 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16071 inst.operands[2].present = 0;
16076 constraint (imm < 1 || (unsigned)imm > et.size,
16077 _("immediate out of range for shift"));
16078 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
16083 do_neon_movl (void)
16085 struct neon_type_el et = neon_check_type (2, NS_QD,
16086 N_EQK | N_DBL, N_SU_32 | N_KEY);
16087 unsigned sizebits = et.size >> 3;
16088 inst.instruction |= sizebits << 19;
16089 neon_two_same (0, et.type == NT_unsigned, -1);
16095 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16096 struct neon_type_el et = neon_check_type (2, rs,
16097 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16098 NEON_ENCODE (INTEGER, inst);
16099 neon_two_same (neon_quad (rs), 1, et.size);
16103 do_neon_zip_uzp (void)
16105 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16106 struct neon_type_el et = neon_check_type (2, rs,
16107 N_EQK, N_8 | N_16 | N_32 | N_KEY);
16108 if (rs == NS_DD && et.size == 32)
16110 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16111 inst.instruction = N_MNEM_vtrn;
16115 neon_two_same (neon_quad (rs), 1, et.size);
16119 do_neon_sat_abs_neg (void)
16121 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16122 struct neon_type_el et = neon_check_type (2, rs,
16123 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16124 neon_two_same (neon_quad (rs), 1, et.size);
16128 do_neon_pair_long (void)
16130 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16131 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
16132 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16133 inst.instruction |= (et.type == NT_unsigned) << 7;
16134 neon_two_same (neon_quad (rs), 1, et.size);
16138 do_neon_recip_est (void)
16140 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16141 struct neon_type_el et = neon_check_type (2, rs,
16142 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
16143 inst.instruction |= (et.type == NT_float) << 8;
16144 neon_two_same (neon_quad (rs), 1, et.size);
16150 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16151 struct neon_type_el et = neon_check_type (2, rs,
16152 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
16153 neon_two_same (neon_quad (rs), 1, et.size);
16159 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16160 struct neon_type_el et = neon_check_type (2, rs,
16161 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
16162 neon_two_same (neon_quad (rs), 1, et.size);
16168 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16169 struct neon_type_el et = neon_check_type (2, rs,
16170 N_EQK | N_INT, N_8 | N_KEY);
16171 neon_two_same (neon_quad (rs), 1, et.size);
16177 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16178 neon_two_same (neon_quad (rs), 1, -1);
16182 do_neon_tbl_tbx (void)
16184 unsigned listlenbits;
16185 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
16187 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16189 first_error (_("bad list length for table lookup"));
16193 listlenbits = inst.operands[1].imm - 1;
16194 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16195 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16196 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16197 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16198 inst.instruction |= LOW4 (inst.operands[2].reg);
16199 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16200 inst.instruction |= listlenbits << 8;
16202 neon_dp_fixup (&inst);
16206 do_neon_ldm_stm (void)
16208 /* P, U and L bits are part of bitmask. */
16209 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16210 unsigned offsetbits = inst.operands[1].imm * 2;
16212 if (inst.operands[1].issingle)
16214 do_vfp_nsyn_ldm_stm (is_dbmode);
16218 constraint (is_dbmode && !inst.operands[0].writeback,
16219 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16221 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16222 _("register list must contain at least 1 and at most 16 "
16225 inst.instruction |= inst.operands[0].reg << 16;
16226 inst.instruction |= inst.operands[0].writeback << 21;
16227 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16228 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16230 inst.instruction |= offsetbits;
16232 do_vfp_cond_or_thumb ();
16236 do_neon_ldr_str (void)
16238 int is_ldr = (inst.instruction & (1 << 20)) != 0;
16240 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16241 And is UNPREDICTABLE in thumb mode. */
16243 && inst.operands[1].reg == REG_PC
16244 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
16247 inst.error = _("Use of PC here is UNPREDICTABLE");
16248 else if (warn_on_deprecated)
16249 as_tsktsk (_("Use of PC here is deprecated"));
16252 if (inst.operands[0].issingle)
16255 do_vfp_nsyn_opcode ("flds");
16257 do_vfp_nsyn_opcode ("fsts");
16262 do_vfp_nsyn_opcode ("fldd");
16264 do_vfp_nsyn_opcode ("fstd");
16268 /* "interleave" version also handles non-interleaving register VLD1/VST1
16272 do_neon_ld_st_interleave (void)
16274 struct neon_type_el et = neon_check_type (1, NS_NULL,
16275 N_8 | N_16 | N_32 | N_64);
16276 unsigned alignbits = 0;
16278 /* The bits in this table go:
16279 0: register stride of one (0) or two (1)
16280 1,2: register list length, minus one (1, 2, 3, 4).
16281 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16282 We use -1 for invalid entries. */
16283 const int typetable[] =
16285 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16286 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16287 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16288 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16292 if (et.type == NT_invtype)
16295 if (inst.operands[1].immisalign)
16296 switch (inst.operands[1].imm >> 8)
16298 case 64: alignbits = 1; break;
16300 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
16301 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16302 goto bad_alignment;
16306 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16307 goto bad_alignment;
16312 first_error (_("bad alignment"));
16316 inst.instruction |= alignbits << 4;
16317 inst.instruction |= neon_logbits (et.size) << 6;
16319 /* Bits [4:6] of the immediate in a list specifier encode register stride
16320 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16321 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16322 up the right value for "type" in a table based on this value and the given
16323 list style, then stick it back. */
16324 idx = ((inst.operands[0].imm >> 4) & 7)
16325 | (((inst.instruction >> 8) & 3) << 3);
16327 typebits = typetable[idx];
16329 constraint (typebits == -1, _("bad list type for instruction"));
16330 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16331 _("bad element type for instruction"));
16333 inst.instruction &= ~0xf00;
16334 inst.instruction |= typebits << 8;
16337 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16338 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16339 otherwise. The variable arguments are a list of pairs of legal (size, align)
16340 values, terminated with -1. */
16343 neon_alignment_bit (int size, int align, int *do_align, ...)
16346 int result = FAIL, thissize, thisalign;
16348 if (!inst.operands[1].immisalign)
16354 va_start (ap, do_align);
16358 thissize = va_arg (ap, int);
16359 if (thissize == -1)
16361 thisalign = va_arg (ap, int);
16363 if (size == thissize && align == thisalign)
16366 while (result != SUCCESS);
16370 if (result == SUCCESS)
16373 first_error (_("unsupported alignment for instruction"));
16379 do_neon_ld_st_lane (void)
16381 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16382 int align_good, do_align = 0;
16383 int logsize = neon_logbits (et.size);
16384 int align = inst.operands[1].imm >> 8;
16385 int n = (inst.instruction >> 8) & 3;
16386 int max_el = 64 / et.size;
16388 if (et.type == NT_invtype)
16391 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
16392 _("bad list length"));
16393 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
16394 _("scalar index out of range"));
16395 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
16397 _("stride of 2 unavailable when element size is 8"));
16401 case 0: /* VLD1 / VST1. */
16402 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
16404 if (align_good == FAIL)
16408 unsigned alignbits = 0;
16411 case 16: alignbits = 0x1; break;
16412 case 32: alignbits = 0x3; break;
16415 inst.instruction |= alignbits << 4;
16419 case 1: /* VLD2 / VST2. */
16420 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
16422 if (align_good == FAIL)
16425 inst.instruction |= 1 << 4;
16428 case 2: /* VLD3 / VST3. */
16429 constraint (inst.operands[1].immisalign,
16430 _("can't use alignment with this instruction"));
16433 case 3: /* VLD4 / VST4. */
16434 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
16435 16, 64, 32, 64, 32, 128, -1);
16436 if (align_good == FAIL)
16440 unsigned alignbits = 0;
16443 case 8: alignbits = 0x1; break;
16444 case 16: alignbits = 0x1; break;
16445 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
16448 inst.instruction |= alignbits << 4;
16455 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16456 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16457 inst.instruction |= 1 << (4 + logsize);
16459 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
16460 inst.instruction |= logsize << 10;
16463 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16466 do_neon_ld_dup (void)
16468 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
16469 int align_good, do_align = 0;
16471 if (et.type == NT_invtype)
16474 switch ((inst.instruction >> 8) & 3)
16476 case 0: /* VLD1. */
16477 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
16478 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16479 &do_align, 16, 16, 32, 32, -1);
16480 if (align_good == FAIL)
16482 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
16485 case 2: inst.instruction |= 1 << 5; break;
16486 default: first_error (_("bad list length")); return;
16488 inst.instruction |= neon_logbits (et.size) << 6;
16491 case 1: /* VLD2. */
16492 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
16493 &do_align, 8, 16, 16, 32, 32, 64, -1);
16494 if (align_good == FAIL)
16496 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
16497 _("bad list length"));
16498 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16499 inst.instruction |= 1 << 5;
16500 inst.instruction |= neon_logbits (et.size) << 6;
16503 case 2: /* VLD3. */
16504 constraint (inst.operands[1].immisalign,
16505 _("can't use alignment with this instruction"));
16506 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
16507 _("bad list length"));
16508 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16509 inst.instruction |= 1 << 5;
16510 inst.instruction |= neon_logbits (et.size) << 6;
16513 case 3: /* VLD4. */
16515 int align = inst.operands[1].imm >> 8;
16516 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
16517 16, 64, 32, 64, 32, 128, -1);
16518 if (align_good == FAIL)
16520 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16521 _("bad list length"));
16522 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16523 inst.instruction |= 1 << 5;
16524 if (et.size == 32 && align == 128)
16525 inst.instruction |= 0x3 << 6;
16527 inst.instruction |= neon_logbits (et.size) << 6;
16534 inst.instruction |= do_align << 4;
16537 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16538 apart from bits [11:4]. */
16541 do_neon_ldx_stx (void)
16543 if (inst.operands[1].isreg)
16544 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16546 switch (NEON_LANE (inst.operands[0].imm))
16548 case NEON_INTERLEAVE_LANES:
16549 NEON_ENCODE (INTERLV, inst);
16550 do_neon_ld_st_interleave ();
16553 case NEON_ALL_LANES:
16554 NEON_ENCODE (DUP, inst);
16555 if (inst.instruction == N_INV)
16557 first_error ("only loads support such operands");
16564 NEON_ENCODE (LANE, inst);
16565 do_neon_ld_st_lane ();
16568 /* L bit comes from bit mask. */
16569 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16570 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16571 inst.instruction |= inst.operands[1].reg << 16;
16573 if (inst.operands[1].postind)
16575 int postreg = inst.operands[1].imm & 0xf;
16576 constraint (!inst.operands[1].immisreg,
16577 _("post-index must be a register"));
16578 constraint (postreg == 0xd || postreg == 0xf,
16579 _("bad register for post-index"));
16580 inst.instruction |= postreg;
16584 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16585 constraint (inst.reloc.exp.X_op != O_constant
16586 || inst.reloc.exp.X_add_number != 0,
16589 if (inst.operands[1].writeback)
16591 inst.instruction |= 0xd;
16594 inst.instruction |= 0xf;
16598 inst.instruction |= 0xf9000000;
16600 inst.instruction |= 0xf4000000;
16605 do_vfp_nsyn_fpv8 (enum neon_shape rs)
16607 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16608 D register operands. */
16609 if (neon_shape_class[rs] == SC_DOUBLE)
16610 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16613 NEON_ENCODE (FPV8, inst);
16616 do_vfp_sp_dyadic ();
16618 do_vfp_dp_rd_rn_rm ();
16621 inst.instruction |= 0x100;
16623 inst.instruction |= 0xf0000000;
16629 set_it_insn_type (OUTSIDE_IT_INSN);
16631 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16632 first_error (_("invalid instruction shape"));
16638 set_it_insn_type (OUTSIDE_IT_INSN);
16640 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16643 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16646 neon_dyadic_misc (NT_untyped, N_F32, 0);
16650 do_vrint_1 (enum neon_cvt_mode mode)
16652 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16653 struct neon_type_el et;
16658 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16659 D register operands. */
16660 if (neon_shape_class[rs] == SC_DOUBLE)
16661 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16664 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16665 if (et.type != NT_invtype)
16667 /* VFP encodings. */
16668 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16669 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16670 set_it_insn_type (OUTSIDE_IT_INSN);
16672 NEON_ENCODE (FPV8, inst);
16674 do_vfp_sp_monadic ();
16676 do_vfp_dp_rd_rm ();
16680 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16681 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16682 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16683 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16684 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16685 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16686 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16690 inst.instruction |= (rs == NS_DD) << 8;
16691 do_vfp_cond_or_thumb ();
16695 /* Neon encodings (or something broken...). */
16697 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16699 if (et.type == NT_invtype)
16702 set_it_insn_type (OUTSIDE_IT_INSN);
16703 NEON_ENCODE (FLOAT, inst);
16705 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16708 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16709 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16710 inst.instruction |= LOW4 (inst.operands[1].reg);
16711 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16712 inst.instruction |= neon_quad (rs) << 6;
16715 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16716 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16717 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16718 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16719 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16720 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16721 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16726 inst.instruction |= 0xfc000000;
16728 inst.instruction |= 0xf0000000;
16735 do_vrint_1 (neon_cvt_mode_x);
16741 do_vrint_1 (neon_cvt_mode_z);
16747 do_vrint_1 (neon_cvt_mode_r);
16753 do_vrint_1 (neon_cvt_mode_a);
16759 do_vrint_1 (neon_cvt_mode_n);
16765 do_vrint_1 (neon_cvt_mode_p);
16771 do_vrint_1 (neon_cvt_mode_m);
16774 /* Crypto v1 instructions. */
16776 do_crypto_2op_1 (unsigned elttype, int op)
16778 set_it_insn_type (OUTSIDE_IT_INSN);
16780 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16786 NEON_ENCODE (INTEGER, inst);
16787 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16788 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16789 inst.instruction |= LOW4 (inst.operands[1].reg);
16790 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16792 inst.instruction |= op << 6;
16795 inst.instruction |= 0xfc000000;
16797 inst.instruction |= 0xf0000000;
16801 do_crypto_3op_1 (int u, int op)
16803 set_it_insn_type (OUTSIDE_IT_INSN);
16805 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16806 N_32 | N_UNT | N_KEY).type == NT_invtype)
16811 NEON_ENCODE (INTEGER, inst);
16812 neon_three_same (1, u, 8 << op);
16818 do_crypto_2op_1 (N_8, 0);
16824 do_crypto_2op_1 (N_8, 1);
16830 do_crypto_2op_1 (N_8, 2);
16836 do_crypto_2op_1 (N_8, 3);
16842 do_crypto_3op_1 (0, 0);
16848 do_crypto_3op_1 (0, 1);
16854 do_crypto_3op_1 (0, 2);
16860 do_crypto_3op_1 (0, 3);
16866 do_crypto_3op_1 (1, 0);
16872 do_crypto_3op_1 (1, 1);
16876 do_sha256su1 (void)
16878 do_crypto_3op_1 (1, 2);
16884 do_crypto_2op_1 (N_32, -1);
16890 do_crypto_2op_1 (N_32, 0);
16894 do_sha256su0 (void)
16896 do_crypto_2op_1 (N_32, 1);
16900 do_crc32_1 (unsigned int poly, unsigned int sz)
16902 unsigned int Rd = inst.operands[0].reg;
16903 unsigned int Rn = inst.operands[1].reg;
16904 unsigned int Rm = inst.operands[2].reg;
16906 set_it_insn_type (OUTSIDE_IT_INSN);
16907 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16908 inst.instruction |= LOW4 (Rn) << 16;
16909 inst.instruction |= LOW4 (Rm);
16910 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16911 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16913 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16914 as_warn (UNPRED_REG ("r15"));
16915 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16916 as_warn (UNPRED_REG ("r13"));
16956 /* Overall per-instruction processing. */
16958 /* We need to be able to fix up arbitrary expressions in some statements.
16959 This is so that we can handle symbols that are an arbitrary distance from
16960 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16961 which returns part of an address in a form which will be valid for
16962 a data instruction. We do this by pushing the expression into a symbol
16963 in the expr_section, and creating a fix for that. */
16966 fix_new_arm (fragS * frag,
16980 /* Create an absolute valued symbol, so we have something to
16981 refer to in the object file. Unfortunately for us, gas's
16982 generic expression parsing will already have folded out
16983 any use of .set foo/.type foo %function that may have
16984 been used to set type information of the target location,
16985 that's being specified symbolically. We have to presume
16986 the user knows what they are doing. */
16990 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16992 symbol = symbol_find_or_make (name);
16993 S_SET_SEGMENT (symbol, absolute_section);
16994 symbol_set_frag (symbol, &zero_address_frag);
16995 S_SET_VALUE (symbol, exp->X_add_number);
16996 exp->X_op = O_symbol;
16997 exp->X_add_symbol = symbol;
16998 exp->X_add_number = 0;
17004 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
17005 (enum bfd_reloc_code_real) reloc);
17009 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
17010 pc_rel, (enum bfd_reloc_code_real) reloc);
17014 /* Mark whether the fix is to a THUMB instruction, or an ARM
17016 new_fix->tc_fix_data = thumb_mode;
17019 /* Create a frg for an instruction requiring relaxation. */
17021 output_relax_insn (void)
17027 /* The size of the instruction is unknown, so tie the debug info to the
17028 start of the instruction. */
17029 dwarf2_emit_insn (0);
17031 switch (inst.reloc.exp.X_op)
17034 sym = inst.reloc.exp.X_add_symbol;
17035 offset = inst.reloc.exp.X_add_number;
17039 offset = inst.reloc.exp.X_add_number;
17042 sym = make_expr_symbol (&inst.reloc.exp);
17046 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
17047 inst.relax, sym, offset, NULL/*offset, opcode*/);
17048 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
17051 /* Write a 32-bit thumb instruction to buf. */
17053 put_thumb32_insn (char * buf, unsigned long insn)
17055 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
17056 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
17060 output_inst (const char * str)
17066 as_bad ("%s -- `%s'", inst.error, str);
17071 output_relax_insn ();
17074 if (inst.size == 0)
17077 to = frag_more (inst.size);
17078 /* PR 9814: Record the thumb mode into the current frag so that we know
17079 what type of NOP padding to use, if necessary. We override any previous
17080 setting so that if the mode has changed then the NOPS that we use will
17081 match the encoding of the last instruction in the frag. */
17082 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
17084 if (thumb_mode && (inst.size > THUMB_SIZE))
17086 gas_assert (inst.size == (2 * THUMB_SIZE));
17087 put_thumb32_insn (to, inst.instruction);
17089 else if (inst.size > INSN_SIZE)
17091 gas_assert (inst.size == (2 * INSN_SIZE));
17092 md_number_to_chars (to, inst.instruction, INSN_SIZE);
17093 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
17096 md_number_to_chars (to, inst.instruction, inst.size);
17098 if (inst.reloc.type != BFD_RELOC_UNUSED)
17099 fix_new_arm (frag_now, to - frag_now->fr_literal,
17100 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
17103 dwarf2_emit_insn (inst.size);
17107 output_it_inst (int cond, int mask, char * to)
17109 unsigned long instruction = 0xbf00;
17112 instruction |= mask;
17113 instruction |= cond << 4;
17117 to = frag_more (2);
17119 dwarf2_emit_insn (2);
17123 md_number_to_chars (to, instruction, 2);
17128 /* Tag values used in struct asm_opcode's tag field. */
17131 OT_unconditional, /* Instruction cannot be conditionalized.
17132 The ARM condition field is still 0xE. */
17133 OT_unconditionalF, /* Instruction cannot be conditionalized
17134 and carries 0xF in its ARM condition field. */
17135 OT_csuffix, /* Instruction takes a conditional suffix. */
17136 OT_csuffixF, /* Some forms of the instruction take a conditional
17137 suffix, others place 0xF where the condition field
17139 OT_cinfix3, /* Instruction takes a conditional infix,
17140 beginning at character index 3. (In
17141 unified mode, it becomes a suffix.) */
17142 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
17143 tsts, cmps, cmns, and teqs. */
17144 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
17145 character index 3, even in unified mode. Used for
17146 legacy instructions where suffix and infix forms
17147 may be ambiguous. */
17148 OT_csuf_or_in3, /* Instruction takes either a conditional
17149 suffix or an infix at character index 3. */
17150 OT_odd_infix_unc, /* This is the unconditional variant of an
17151 instruction that takes a conditional infix
17152 at an unusual position. In unified mode,
17153 this variant will accept a suffix. */
17154 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
17155 are the conditional variants of instructions that
17156 take conditional infixes in unusual positions.
17157 The infix appears at character index
17158 (tag - OT_odd_infix_0). These are not accepted
17159 in unified mode. */
17162 /* Subroutine of md_assemble, responsible for looking up the primary
17163 opcode from the mnemonic the user wrote. STR points to the
17164 beginning of the mnemonic.
17166 This is not simply a hash table lookup, because of conditional
17167 variants. Most instructions have conditional variants, which are
17168 expressed with a _conditional affix_ to the mnemonic. If we were
17169 to encode each conditional variant as a literal string in the opcode
17170 table, it would have approximately 20,000 entries.
17172 Most mnemonics take this affix as a suffix, and in unified syntax,
17173 'most' is upgraded to 'all'. However, in the divided syntax, some
17174 instructions take the affix as an infix, notably the s-variants of
17175 the arithmetic instructions. Of those instructions, all but six
17176 have the infix appear after the third character of the mnemonic.
17178 Accordingly, the algorithm for looking up primary opcodes given
17181 1. Look up the identifier in the opcode table.
17182 If we find a match, go to step U.
17184 2. Look up the last two characters of the identifier in the
17185 conditions table. If we find a match, look up the first N-2
17186 characters of the identifier in the opcode table. If we
17187 find a match, go to step CE.
17189 3. Look up the fourth and fifth characters of the identifier in
17190 the conditions table. If we find a match, extract those
17191 characters from the identifier, and look up the remaining
17192 characters in the opcode table. If we find a match, go
17197 U. Examine the tag field of the opcode structure, in case this is
17198 one of the six instructions with its conditional infix in an
17199 unusual place. If it is, the tag tells us where to find the
17200 infix; look it up in the conditions table and set inst.cond
17201 accordingly. Otherwise, this is an unconditional instruction.
17202 Again set inst.cond accordingly. Return the opcode structure.
17204 CE. Examine the tag field to make sure this is an instruction that
17205 should receive a conditional suffix. If it is not, fail.
17206 Otherwise, set inst.cond from the suffix we already looked up,
17207 and return the opcode structure.
17209 CM. Examine the tag field to make sure this is an instruction that
17210 should receive a conditional infix after the third character.
17211 If it is not, fail. Otherwise, undo the edits to the current
17212 line of input and proceed as for case CE. */
17214 static const struct asm_opcode *
17215 opcode_lookup (char **str)
17219 const struct asm_opcode *opcode;
17220 const struct asm_cond *cond;
17223 /* Scan up to the end of the mnemonic, which must end in white space,
17224 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17225 for (base = end = *str; *end != '\0'; end++)
17226 if (*end == ' ' || *end == '.')
17232 /* Handle a possible width suffix and/or Neon type suffix. */
17237 /* The .w and .n suffixes are only valid if the unified syntax is in
17239 if (unified_syntax && end[1] == 'w')
17241 else if (unified_syntax && end[1] == 'n')
17246 inst.vectype.elems = 0;
17248 *str = end + offset;
17250 if (end[offset] == '.')
17252 /* See if we have a Neon type suffix (possible in either unified or
17253 non-unified ARM syntax mode). */
17254 if (parse_neon_type (&inst.vectype, str) == FAIL)
17257 else if (end[offset] != '\0' && end[offset] != ' ')
17263 /* Look for unaffixed or special-case affixed mnemonic. */
17264 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17269 if (opcode->tag < OT_odd_infix_0)
17271 inst.cond = COND_ALWAYS;
17275 if (warn_on_deprecated && unified_syntax)
17276 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17277 affix = base + (opcode->tag - OT_odd_infix_0);
17278 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17281 inst.cond = cond->value;
17285 /* Cannot have a conditional suffix on a mnemonic of less than two
17287 if (end - base < 3)
17290 /* Look for suffixed mnemonic. */
17292 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17293 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17295 if (opcode && cond)
17298 switch (opcode->tag)
17300 case OT_cinfix3_legacy:
17301 /* Ignore conditional suffixes matched on infix only mnemonics. */
17305 case OT_cinfix3_deprecated:
17306 case OT_odd_infix_unc:
17307 if (!unified_syntax)
17309 /* else fall through */
17313 case OT_csuf_or_in3:
17314 inst.cond = cond->value;
17317 case OT_unconditional:
17318 case OT_unconditionalF:
17320 inst.cond = cond->value;
17323 /* Delayed diagnostic. */
17324 inst.error = BAD_COND;
17325 inst.cond = COND_ALWAYS;
17334 /* Cannot have a usual-position infix on a mnemonic of less than
17335 six characters (five would be a suffix). */
17336 if (end - base < 6)
17339 /* Look for infixed mnemonic in the usual position. */
17341 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17345 memcpy (save, affix, 2);
17346 memmove (affix, affix + 2, (end - affix) - 2);
17347 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
17349 memmove (affix + 2, affix, (end - affix) - 2);
17350 memcpy (affix, save, 2);
17353 && (opcode->tag == OT_cinfix3
17354 || opcode->tag == OT_cinfix3_deprecated
17355 || opcode->tag == OT_csuf_or_in3
17356 || opcode->tag == OT_cinfix3_legacy))
17359 if (warn_on_deprecated && unified_syntax
17360 && (opcode->tag == OT_cinfix3
17361 || opcode->tag == OT_cinfix3_deprecated))
17362 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17364 inst.cond = cond->value;
17371 /* This function generates an initial IT instruction, leaving its block
17372 virtually open for the new instructions. Eventually,
17373 the mask will be updated by now_it_add_mask () each time
17374 a new instruction needs to be included in the IT block.
17375 Finally, the block is closed with close_automatic_it_block ().
17376 The block closure can be requested either from md_assemble (),
17377 a tencode (), or due to a label hook. */
17380 new_automatic_it_block (int cond)
17382 now_it.state = AUTOMATIC_IT_BLOCK;
17383 now_it.mask = 0x18;
17385 now_it.block_length = 1;
17386 mapping_state (MAP_THUMB);
17387 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
17388 now_it.warn_deprecated = FALSE;
17389 now_it.insn_cond = TRUE;
17392 /* Close an automatic IT block.
17393 See comments in new_automatic_it_block (). */
17396 close_automatic_it_block (void)
17398 now_it.mask = 0x10;
17399 now_it.block_length = 0;
17402 /* Update the mask of the current automatically-generated IT
17403 instruction. See comments in new_automatic_it_block (). */
17406 now_it_add_mask (int cond)
17408 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17409 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17410 | ((bitvalue) << (nbit)))
17411 const int resulting_bit = (cond & 1);
17413 now_it.mask &= 0xf;
17414 now_it.mask = SET_BIT_VALUE (now_it.mask,
17416 (5 - now_it.block_length));
17417 now_it.mask = SET_BIT_VALUE (now_it.mask,
17419 ((5 - now_it.block_length) - 1) );
17420 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
17423 #undef SET_BIT_VALUE
17426 /* The IT blocks handling machinery is accessed through the these functions:
17427 it_fsm_pre_encode () from md_assemble ()
17428 set_it_insn_type () optional, from the tencode functions
17429 set_it_insn_type_last () ditto
17430 in_it_block () ditto
17431 it_fsm_post_encode () from md_assemble ()
17432 force_automatic_it_block_close () from label habdling functions
17435 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17436 initializing the IT insn type with a generic initial value depending
17437 on the inst.condition.
17438 2) During the tencode function, two things may happen:
17439 a) The tencode function overrides the IT insn type by
17440 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17441 b) The tencode function queries the IT block state by
17442 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17444 Both set_it_insn_type and in_it_block run the internal FSM state
17445 handling function (handle_it_state), because: a) setting the IT insn
17446 type may incur in an invalid state (exiting the function),
17447 and b) querying the state requires the FSM to be updated.
17448 Specifically we want to avoid creating an IT block for conditional
17449 branches, so it_fsm_pre_encode is actually a guess and we can't
17450 determine whether an IT block is required until the tencode () routine
17451 has decided what type of instruction this actually it.
17452 Because of this, if set_it_insn_type and in_it_block have to be used,
17453 set_it_insn_type has to be called first.
17455 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17456 determines the insn IT type depending on the inst.cond code.
17457 When a tencode () routine encodes an instruction that can be
17458 either outside an IT block, or, in the case of being inside, has to be
17459 the last one, set_it_insn_type_last () will determine the proper
17460 IT instruction type based on the inst.cond code. Otherwise,
17461 set_it_insn_type can be called for overriding that logic or
17462 for covering other cases.
17464 Calling handle_it_state () may not transition the IT block state to
17465 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17466 still queried. Instead, if the FSM determines that the state should
17467 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17468 after the tencode () function: that's what it_fsm_post_encode () does.
17470 Since in_it_block () calls the state handling function to get an
17471 updated state, an error may occur (due to invalid insns combination).
17472 In that case, inst.error is set.
17473 Therefore, inst.error has to be checked after the execution of
17474 the tencode () routine.
17476 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17477 any pending state change (if any) that didn't take place in
17478 handle_it_state () as explained above. */
17481 it_fsm_pre_encode (void)
17483 if (inst.cond != COND_ALWAYS)
17484 inst.it_insn_type = INSIDE_IT_INSN;
17486 inst.it_insn_type = OUTSIDE_IT_INSN;
17488 now_it.state_handled = 0;
17491 /* IT state FSM handling function. */
17494 handle_it_state (void)
17496 now_it.state_handled = 1;
17497 now_it.insn_cond = FALSE;
17499 switch (now_it.state)
17501 case OUTSIDE_IT_BLOCK:
17502 switch (inst.it_insn_type)
17504 case OUTSIDE_IT_INSN:
17507 case INSIDE_IT_INSN:
17508 case INSIDE_IT_LAST_INSN:
17509 if (thumb_mode == 0)
17512 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
17513 as_tsktsk (_("Warning: conditional outside an IT block"\
17518 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
17519 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
17521 /* Automatically generate the IT instruction. */
17522 new_automatic_it_block (inst.cond);
17523 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
17524 close_automatic_it_block ();
17528 inst.error = BAD_OUT_IT;
17534 case IF_INSIDE_IT_LAST_INSN:
17535 case NEUTRAL_IT_INSN:
17539 now_it.state = MANUAL_IT_BLOCK;
17540 now_it.block_length = 0;
17545 case AUTOMATIC_IT_BLOCK:
17546 /* Three things may happen now:
17547 a) We should increment current it block size;
17548 b) We should close current it block (closing insn or 4 insns);
17549 c) We should close current it block and start a new one (due
17550 to incompatible conditions or
17551 4 insns-length block reached). */
17553 switch (inst.it_insn_type)
17555 case OUTSIDE_IT_INSN:
17556 /* The closure of the block shall happen immediatelly,
17557 so any in_it_block () call reports the block as closed. */
17558 force_automatic_it_block_close ();
17561 case INSIDE_IT_INSN:
17562 case INSIDE_IT_LAST_INSN:
17563 case IF_INSIDE_IT_LAST_INSN:
17564 now_it.block_length++;
17566 if (now_it.block_length > 4
17567 || !now_it_compatible (inst.cond))
17569 force_automatic_it_block_close ();
17570 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17571 new_automatic_it_block (inst.cond);
17575 now_it.insn_cond = TRUE;
17576 now_it_add_mask (inst.cond);
17579 if (now_it.state == AUTOMATIC_IT_BLOCK
17580 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17581 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17582 close_automatic_it_block ();
17585 case NEUTRAL_IT_INSN:
17586 now_it.block_length++;
17587 now_it.insn_cond = TRUE;
17589 if (now_it.block_length > 4)
17590 force_automatic_it_block_close ();
17592 now_it_add_mask (now_it.cc & 1);
17596 close_automatic_it_block ();
17597 now_it.state = MANUAL_IT_BLOCK;
17602 case MANUAL_IT_BLOCK:
17604 /* Check conditional suffixes. */
17605 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17608 now_it.mask &= 0x1f;
17609 is_last = (now_it.mask == 0x10);
17610 now_it.insn_cond = TRUE;
17612 switch (inst.it_insn_type)
17614 case OUTSIDE_IT_INSN:
17615 inst.error = BAD_NOT_IT;
17618 case INSIDE_IT_INSN:
17619 if (cond != inst.cond)
17621 inst.error = BAD_IT_COND;
17626 case INSIDE_IT_LAST_INSN:
17627 case IF_INSIDE_IT_LAST_INSN:
17628 if (cond != inst.cond)
17630 inst.error = BAD_IT_COND;
17635 inst.error = BAD_BRANCH;
17640 case NEUTRAL_IT_INSN:
17641 /* The BKPT instruction is unconditional even in an IT block. */
17645 inst.error = BAD_IT_IT;
17655 struct depr_insn_mask
17657 unsigned long pattern;
17658 unsigned long mask;
17659 const char* description;
17662 /* List of 16-bit instruction patterns deprecated in an IT block in
17664 static const struct depr_insn_mask depr_it_insns[] = {
17665 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17666 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17667 { 0xa000, 0xb800, N_("ADR") },
17668 { 0x4800, 0xf800, N_("Literal loads") },
17669 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17670 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17671 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17672 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17673 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
17678 it_fsm_post_encode (void)
17682 if (!now_it.state_handled)
17683 handle_it_state ();
17685 if (now_it.insn_cond
17686 && !now_it.warn_deprecated
17687 && warn_on_deprecated
17688 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17690 if (inst.instruction >= 0x10000)
17692 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
17693 "deprecated in ARMv8"));
17694 now_it.warn_deprecated = TRUE;
17698 const struct depr_insn_mask *p = depr_it_insns;
17700 while (p->mask != 0)
17702 if ((inst.instruction & p->mask) == p->pattern)
17704 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
17705 "of the following class are deprecated in ARMv8: "
17706 "%s"), p->description);
17707 now_it.warn_deprecated = TRUE;
17715 if (now_it.block_length > 1)
17717 as_tsktsk (_("IT blocks containing more than one conditional "
17718 "instruction are deprecated in ARMv8"));
17719 now_it.warn_deprecated = TRUE;
17723 is_last = (now_it.mask == 0x10);
17726 now_it.state = OUTSIDE_IT_BLOCK;
17732 force_automatic_it_block_close (void)
17734 if (now_it.state == AUTOMATIC_IT_BLOCK)
17736 close_automatic_it_block ();
17737 now_it.state = OUTSIDE_IT_BLOCK;
17745 if (!now_it.state_handled)
17746 handle_it_state ();
17748 return now_it.state != OUTSIDE_IT_BLOCK;
17752 md_assemble (char *str)
17755 const struct asm_opcode * opcode;
17757 /* Align the previous label if needed. */
17758 if (last_label_seen != NULL)
17760 symbol_set_frag (last_label_seen, frag_now);
17761 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17762 S_SET_SEGMENT (last_label_seen, now_seg);
17765 memset (&inst, '\0', sizeof (inst));
17766 inst.reloc.type = BFD_RELOC_UNUSED;
17768 opcode = opcode_lookup (&p);
17771 /* It wasn't an instruction, but it might be a register alias of
17772 the form alias .req reg, or a Neon .dn/.qn directive. */
17773 if (! create_register_alias (str, p)
17774 && ! create_neon_reg_alias (str, p))
17775 as_bad (_("bad instruction `%s'"), str);
17780 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
17781 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
17783 /* The value which unconditional instructions should have in place of the
17784 condition field. */
17785 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17789 arm_feature_set variant;
17791 variant = cpu_variant;
17792 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17793 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17794 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
17795 /* Check that this instruction is supported for this CPU. */
17796 if (!opcode->tvariant
17797 || (thumb_mode == 1
17798 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
17800 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
17803 if (inst.cond != COND_ALWAYS && !unified_syntax
17804 && opcode->tencode != do_t_branch)
17806 as_bad (_("Thumb does not support conditional execution"));
17810 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
17812 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
17813 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17814 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17816 /* Two things are addressed here.
17817 1) Implicit require narrow instructions on Thumb-1.
17818 This avoids relaxation accidentally introducing Thumb-2
17820 2) Reject wide instructions in non Thumb-2 cores. */
17821 if (inst.size_req == 0)
17823 else if (inst.size_req == 4)
17825 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
17831 inst.instruction = opcode->tvalue;
17833 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
17835 /* Prepare the it_insn_type for those encodings that don't set
17837 it_fsm_pre_encode ();
17839 opcode->tencode ();
17841 it_fsm_post_encode ();
17844 if (!(inst.error || inst.relax))
17846 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
17847 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17848 if (inst.size_req && inst.size_req != inst.size)
17850 as_bad (_("cannot honor width suffix -- `%s'"), str);
17855 /* Something has gone badly wrong if we try to relax a fixed size
17857 gas_assert (inst.size_req == 0 || !inst.relax);
17859 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17860 *opcode->tvariant);
17861 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17862 set those bits when Thumb-2 32-bit instructions are seen. ie.
17863 anything other than bl/blx and v6-M instructions.
17864 The impact of relaxable instructions will be considered later after we
17865 finish all relaxation. */
17866 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17867 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17868 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
17869 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17872 check_neon_suffixes;
17876 mapping_state (MAP_THUMB);
17879 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
17883 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17884 is_bx = (opcode->aencode == do_bx);
17886 /* Check that this instruction is supported for this CPU. */
17887 if (!(is_bx && fix_v4bx)
17888 && !(opcode->avariant &&
17889 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
17891 as_bad (_("selected processor does not support ARM mode `%s'"), str);
17896 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17900 inst.instruction = opcode->avalue;
17901 if (opcode->tag == OT_unconditionalF)
17902 inst.instruction |= 0xF << 28;
17904 inst.instruction |= inst.cond << 28;
17905 inst.size = INSN_SIZE;
17906 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
17908 it_fsm_pre_encode ();
17909 opcode->aencode ();
17910 it_fsm_post_encode ();
17912 /* Arm mode bx is marked as both v4T and v5 because it's still required
17913 on a hypothetical non-thumb v5 core. */
17915 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
17917 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17918 *opcode->avariant);
17920 check_neon_suffixes;
17924 mapping_state (MAP_ARM);
17929 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17937 check_it_blocks_finished (void)
17942 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17943 if (seg_info (sect)->tc_segment_info_data.current_it.state
17944 == MANUAL_IT_BLOCK)
17946 as_warn (_("section '%s' finished with an open IT block."),
17950 if (now_it.state == MANUAL_IT_BLOCK)
17951 as_warn (_("file finished with an open IT block."));
17955 /* Various frobbings of labels and their addresses. */
17958 arm_start_line_hook (void)
17960 last_label_seen = NULL;
17964 arm_frob_label (symbolS * sym)
17966 last_label_seen = sym;
17968 ARM_SET_THUMB (sym, thumb_mode);
17970 #if defined OBJ_COFF || defined OBJ_ELF
17971 ARM_SET_INTERWORK (sym, support_interwork);
17974 force_automatic_it_block_close ();
17976 /* Note - do not allow local symbols (.Lxxx) to be labelled
17977 as Thumb functions. This is because these labels, whilst
17978 they exist inside Thumb code, are not the entry points for
17979 possible ARM->Thumb calls. Also, these labels can be used
17980 as part of a computed goto or switch statement. eg gcc
17981 can generate code that looks like this:
17983 ldr r2, [pc, .Laaa]
17993 The first instruction loads the address of the jump table.
17994 The second instruction converts a table index into a byte offset.
17995 The third instruction gets the jump address out of the table.
17996 The fourth instruction performs the jump.
17998 If the address stored at .Laaa is that of a symbol which has the
17999 Thumb_Func bit set, then the linker will arrange for this address
18000 to have the bottom bit set, which in turn would mean that the
18001 address computation performed by the third instruction would end
18002 up with the bottom bit set. Since the ARM is capable of unaligned
18003 word loads, the instruction would then load the incorrect address
18004 out of the jump table, and chaos would ensue. */
18005 if (label_is_thumb_function_name
18006 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
18007 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
18009 /* When the address of a Thumb function is taken the bottom
18010 bit of that address should be set. This will allow
18011 interworking between Arm and Thumb functions to work
18014 THUMB_SET_FUNC (sym, 1);
18016 label_is_thumb_function_name = FALSE;
18019 dwarf2_emit_label (sym);
18023 arm_data_in_code (void)
18025 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
18027 *input_line_pointer = '/';
18028 input_line_pointer += 5;
18029 *input_line_pointer = 0;
18037 arm_canonicalize_symbol_name (char * name)
18041 if (thumb_mode && (len = strlen (name)) > 5
18042 && streq (name + len - 5, "/data"))
18043 *(name + len - 5) = 0;
18048 /* Table of all register names defined by default. The user can
18049 define additional names with .req. Note that all register names
18050 should appear in both upper and lowercase variants. Some registers
18051 also have mixed-case names. */
18053 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18054 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18055 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18056 #define REGSET(p,t) \
18057 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18058 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18059 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18060 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18061 #define REGSETH(p,t) \
18062 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18063 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18064 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18065 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18066 #define REGSET2(p,t) \
18067 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18068 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18069 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18070 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18071 #define SPLRBANK(base,bank,t) \
18072 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18073 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18074 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18075 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18076 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18077 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18079 static const struct reg_entry reg_names[] =
18081 /* ARM integer registers. */
18082 REGSET(r, RN), REGSET(R, RN),
18084 /* ATPCS synonyms. */
18085 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
18086 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
18087 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
18089 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
18090 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
18091 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
18093 /* Well-known aliases. */
18094 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
18095 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
18097 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
18098 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
18100 /* Coprocessor numbers. */
18101 REGSET(p, CP), REGSET(P, CP),
18103 /* Coprocessor register numbers. The "cr" variants are for backward
18105 REGSET(c, CN), REGSET(C, CN),
18106 REGSET(cr, CN), REGSET(CR, CN),
18108 /* ARM banked registers. */
18109 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
18110 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
18111 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
18112 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
18113 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
18114 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
18115 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
18117 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
18118 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
18119 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
18120 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
18121 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
18122 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
18123 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
18124 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
18126 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
18127 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
18128 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
18129 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
18130 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
18131 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
18132 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
18133 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
18134 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
18136 /* FPA registers. */
18137 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
18138 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
18140 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
18141 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
18143 /* VFP SP registers. */
18144 REGSET(s,VFS), REGSET(S,VFS),
18145 REGSETH(s,VFS), REGSETH(S,VFS),
18147 /* VFP DP Registers. */
18148 REGSET(d,VFD), REGSET(D,VFD),
18149 /* Extra Neon DP registers. */
18150 REGSETH(d,VFD), REGSETH(D,VFD),
18152 /* Neon QP registers. */
18153 REGSET2(q,NQ), REGSET2(Q,NQ),
18155 /* VFP control registers. */
18156 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
18157 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
18158 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
18159 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
18160 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
18161 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
18163 /* Maverick DSP coprocessor registers. */
18164 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
18165 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
18167 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
18168 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
18169 REGDEF(dspsc,0,DSPSC),
18171 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
18172 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
18173 REGDEF(DSPSC,0,DSPSC),
18175 /* iWMMXt data registers - p0, c0-15. */
18176 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
18178 /* iWMMXt control registers - p1, c0-3. */
18179 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
18180 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
18181 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
18182 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
18184 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18185 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
18186 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
18187 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
18188 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
18190 /* XScale accumulator registers. */
18191 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
18197 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18198 within psr_required_here. */
18199 static const struct asm_psr psrs[] =
18201 /* Backward compatibility notation. Note that "all" is no longer
18202 truly all possible PSR bits. */
18203 {"all", PSR_c | PSR_f},
18207 /* Individual flags. */
18213 /* Combinations of flags. */
18214 {"fs", PSR_f | PSR_s},
18215 {"fx", PSR_f | PSR_x},
18216 {"fc", PSR_f | PSR_c},
18217 {"sf", PSR_s | PSR_f},
18218 {"sx", PSR_s | PSR_x},
18219 {"sc", PSR_s | PSR_c},
18220 {"xf", PSR_x | PSR_f},
18221 {"xs", PSR_x | PSR_s},
18222 {"xc", PSR_x | PSR_c},
18223 {"cf", PSR_c | PSR_f},
18224 {"cs", PSR_c | PSR_s},
18225 {"cx", PSR_c | PSR_x},
18226 {"fsx", PSR_f | PSR_s | PSR_x},
18227 {"fsc", PSR_f | PSR_s | PSR_c},
18228 {"fxs", PSR_f | PSR_x | PSR_s},
18229 {"fxc", PSR_f | PSR_x | PSR_c},
18230 {"fcs", PSR_f | PSR_c | PSR_s},
18231 {"fcx", PSR_f | PSR_c | PSR_x},
18232 {"sfx", PSR_s | PSR_f | PSR_x},
18233 {"sfc", PSR_s | PSR_f | PSR_c},
18234 {"sxf", PSR_s | PSR_x | PSR_f},
18235 {"sxc", PSR_s | PSR_x | PSR_c},
18236 {"scf", PSR_s | PSR_c | PSR_f},
18237 {"scx", PSR_s | PSR_c | PSR_x},
18238 {"xfs", PSR_x | PSR_f | PSR_s},
18239 {"xfc", PSR_x | PSR_f | PSR_c},
18240 {"xsf", PSR_x | PSR_s | PSR_f},
18241 {"xsc", PSR_x | PSR_s | PSR_c},
18242 {"xcf", PSR_x | PSR_c | PSR_f},
18243 {"xcs", PSR_x | PSR_c | PSR_s},
18244 {"cfs", PSR_c | PSR_f | PSR_s},
18245 {"cfx", PSR_c | PSR_f | PSR_x},
18246 {"csf", PSR_c | PSR_s | PSR_f},
18247 {"csx", PSR_c | PSR_s | PSR_x},
18248 {"cxf", PSR_c | PSR_x | PSR_f},
18249 {"cxs", PSR_c | PSR_x | PSR_s},
18250 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
18251 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
18252 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
18253 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
18254 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
18255 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
18256 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
18257 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
18258 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
18259 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
18260 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
18261 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
18262 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
18263 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
18264 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
18265 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
18266 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
18267 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
18268 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
18269 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
18270 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
18271 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
18272 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
18273 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
18276 /* Table of V7M psr names. */
18277 static const struct asm_psr v7m_psrs[] =
18279 {"apsr", 0 }, {"APSR", 0 },
18280 {"iapsr", 1 }, {"IAPSR", 1 },
18281 {"eapsr", 2 }, {"EAPSR", 2 },
18282 {"psr", 3 }, {"PSR", 3 },
18283 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18284 {"ipsr", 5 }, {"IPSR", 5 },
18285 {"epsr", 6 }, {"EPSR", 6 },
18286 {"iepsr", 7 }, {"IEPSR", 7 },
18287 {"msp", 8 }, {"MSP", 8 },
18288 {"psp", 9 }, {"PSP", 9 },
18289 {"primask", 16}, {"PRIMASK", 16},
18290 {"basepri", 17}, {"BASEPRI", 17},
18291 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18292 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18293 {"faultmask", 19}, {"FAULTMASK", 19},
18294 {"control", 20}, {"CONTROL", 20}
18297 /* Table of all shift-in-operand names. */
18298 static const struct asm_shift_name shift_names [] =
18300 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
18301 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
18302 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
18303 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
18304 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
18305 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
18308 /* Table of all explicit relocation names. */
18310 static struct reloc_entry reloc_names[] =
18312 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
18313 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
18314 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
18315 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
18316 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
18317 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
18318 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
18319 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
18320 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
18321 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
18322 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
18323 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
18324 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
18325 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
18326 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
18327 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
18328 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
18329 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
18333 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18334 static const struct asm_cond conds[] =
18338 {"cs", 0x2}, {"hs", 0x2},
18339 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18353 #define UL_BARRIER(L,U,CODE,FEAT) \
18354 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18355 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18357 static struct asm_barrier_opt barrier_opt_names[] =
18359 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
18360 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
18361 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
18362 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
18363 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
18364 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
18365 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
18366 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
18367 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
18368 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
18369 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
18370 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
18371 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
18372 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
18373 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
18374 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
18379 /* Table of ARM-format instructions. */
18381 /* Macros for gluing together operand strings. N.B. In all cases
18382 other than OPS0, the trailing OP_stop comes from default
18383 zero-initialization of the unspecified elements of the array. */
18384 #define OPS0() { OP_stop, }
18385 #define OPS1(a) { OP_##a, }
18386 #define OPS2(a,b) { OP_##a,OP_##b, }
18387 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18388 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18389 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18390 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18392 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18393 This is useful when mixing operands for ARM and THUMB, i.e. using the
18394 MIX_ARM_THUMB_OPERANDS macro.
18395 In order to use these macros, prefix the number of operands with _
18397 #define OPS_1(a) { a, }
18398 #define OPS_2(a,b) { a,b, }
18399 #define OPS_3(a,b,c) { a,b,c, }
18400 #define OPS_4(a,b,c,d) { a,b,c,d, }
18401 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18402 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18404 /* These macros abstract out the exact format of the mnemonic table and
18405 save some repeated characters. */
18407 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18408 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18409 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18410 THUMB_VARIANT, do_##ae, do_##te }
18412 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18413 a T_MNEM_xyz enumerator. */
18414 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18415 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18416 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18417 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18419 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18420 infix after the third character. */
18421 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18422 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18423 THUMB_VARIANT, do_##ae, do_##te }
18424 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18425 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18426 THUMB_VARIANT, do_##ae, do_##te }
18427 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18428 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18429 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18430 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18431 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18432 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18433 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18434 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18436 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18437 field is still 0xE. Many of the Thumb variants can be executed
18438 conditionally, so this is checked separately. */
18439 #define TUE(mnem, op, top, nops, ops, ae, te) \
18440 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18441 THUMB_VARIANT, do_##ae, do_##te }
18443 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18444 Used by mnemonics that have very minimal differences in the encoding for
18445 ARM and Thumb variants and can be handled in a common function. */
18446 #define TUEc(mnem, op, top, nops, ops, en) \
18447 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18448 THUMB_VARIANT, do_##en, do_##en }
18450 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18451 condition code field. */
18452 #define TUF(mnem, op, top, nops, ops, ae, te) \
18453 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18454 THUMB_VARIANT, do_##ae, do_##te }
18456 /* ARM-only variants of all the above. */
18457 #define CE(mnem, op, nops, ops, ae) \
18458 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18460 #define C3(mnem, op, nops, ops, ae) \
18461 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18463 /* Legacy mnemonics that always have conditional infix after the third
18465 #define CL(mnem, op, nops, ops, ae) \
18466 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18467 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18469 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18470 #define cCE(mnem, op, nops, ops, ae) \
18471 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18473 /* Legacy coprocessor instructions where conditional infix and conditional
18474 suffix are ambiguous. For consistency this includes all FPA instructions,
18475 not just the potentially ambiguous ones. */
18476 #define cCL(mnem, op, nops, ops, ae) \
18477 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18478 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18480 /* Coprocessor, takes either a suffix or a position-3 infix
18481 (for an FPA corner case). */
18482 #define C3E(mnem, op, nops, ops, ae) \
18483 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18484 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18486 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18487 { m1 #m2 m3, OPS##nops ops, \
18488 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18489 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18491 #define CM(m1, m2, op, nops, ops, ae) \
18492 xCM_ (m1, , m2, op, nops, ops, ae), \
18493 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18494 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18495 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18496 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18497 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18498 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18499 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18500 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18501 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18502 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18503 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18504 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18505 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18506 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18507 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18508 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18509 xCM_ (m1, le, m2, op, nops, ops, ae), \
18510 xCM_ (m1, al, m2, op, nops, ops, ae)
18512 #define UE(mnem, op, nops, ops, ae) \
18513 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18515 #define UF(mnem, op, nops, ops, ae) \
18516 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18518 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18519 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18520 use the same encoding function for each. */
18521 #define NUF(mnem, op, nops, ops, enc) \
18522 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18523 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18525 /* Neon data processing, version which indirects through neon_enc_tab for
18526 the various overloaded versions of opcodes. */
18527 #define nUF(mnem, op, nops, ops, enc) \
18528 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18529 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18531 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18533 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18534 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18535 THUMB_VARIANT, do_##enc, do_##enc }
18537 #define NCE(mnem, op, nops, ops, enc) \
18538 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18540 #define NCEF(mnem, op, nops, ops, enc) \
18541 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18543 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18544 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18545 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18546 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18548 #define nCE(mnem, op, nops, ops, enc) \
18549 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18551 #define nCEF(mnem, op, nops, ops, enc) \
18552 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18556 static const struct asm_opcode insns[] =
18558 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18559 #define THUMB_VARIANT & arm_ext_v4t
18560 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18561 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18562 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18563 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18564 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18565 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18566 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18567 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18568 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18569 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18570 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18571 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18572 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18573 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18574 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18575 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
18577 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18578 for setting PSR flag bits. They are obsolete in V6 and do not
18579 have Thumb equivalents. */
18580 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18581 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18582 CL("tstp", 110f000, 2, (RR, SH), cmp),
18583 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18584 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18585 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18586 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18587 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18588 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18590 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18591 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18592 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18593 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18595 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
18596 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18597 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18599 OP_ADDRGLDR),ldst, t_ldst),
18600 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18602 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18603 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18604 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18605 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18606 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18607 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18609 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18610 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18611 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18612 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
18615 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
18616 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
18617 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
18618 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
18620 /* Thumb-compatibility pseudo ops. */
18621 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18622 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18623 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18624 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18625 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18626 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18627 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18628 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18629 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18630 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18631 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18632 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
18634 /* These may simplify to neg. */
18635 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18636 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
18638 #undef THUMB_VARIANT
18639 #define THUMB_VARIANT & arm_ext_v6
18641 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
18643 /* V1 instructions with no Thumb analogue prior to V6T2. */
18644 #undef THUMB_VARIANT
18645 #define THUMB_VARIANT & arm_ext_v6t2
18647 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18648 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18649 CL("teqp", 130f000, 2, (RR, SH), cmp),
18651 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18652 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18653 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18654 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18656 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18657 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18659 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18660 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18662 /* V1 instructions with no Thumb analogue at all. */
18663 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
18664 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18666 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18667 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18668 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18669 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18670 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18671 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18672 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18673 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18676 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18677 #undef THUMB_VARIANT
18678 #define THUMB_VARIANT & arm_ext_v4t
18680 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18681 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18683 #undef THUMB_VARIANT
18684 #define THUMB_VARIANT & arm_ext_v6t2
18686 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18687 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18689 /* Generic coprocessor instructions. */
18690 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18691 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18692 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18693 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18694 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18695 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18696 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
18699 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18701 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18702 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18705 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18706 #undef THUMB_VARIANT
18707 #define THUMB_VARIANT & arm_ext_msr
18709 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18710 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
18713 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18714 #undef THUMB_VARIANT
18715 #define THUMB_VARIANT & arm_ext_v6t2
18717 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18718 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18719 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18720 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18721 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18722 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18723 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18724 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18727 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18728 #undef THUMB_VARIANT
18729 #define THUMB_VARIANT & arm_ext_v4t
18731 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18732 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18733 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18734 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18735 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18736 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18739 #define ARM_VARIANT & arm_ext_v4t_5
18741 /* ARM Architecture 4T. */
18742 /* Note: bx (and blx) are required on V5, even if the processor does
18743 not support Thumb. */
18744 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
18747 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18748 #undef THUMB_VARIANT
18749 #define THUMB_VARIANT & arm_ext_v5t
18751 /* Note: blx has 2 variants; the .value coded here is for
18752 BLX(2). Only this variant has conditional execution. */
18753 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18754 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
18756 #undef THUMB_VARIANT
18757 #define THUMB_VARIANT & arm_ext_v6t2
18759 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18760 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18761 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18762 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18763 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18764 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18765 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18766 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18769 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18770 #undef THUMB_VARIANT
18771 #define THUMB_VARIANT & arm_ext_v5exp
18773 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18774 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18775 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18776 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18778 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18779 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18781 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18782 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18783 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18784 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18786 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18787 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18788 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18789 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18791 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18792 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18794 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18795 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18796 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18797 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18800 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18801 #undef THUMB_VARIANT
18802 #define THUMB_VARIANT & arm_ext_v6t2
18804 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
18805 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18807 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18808 ADDRGLDRS), ldrd, t_ldstd),
18810 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18811 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18814 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18816 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
18819 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18820 #undef THUMB_VARIANT
18821 #define THUMB_VARIANT & arm_ext_v6
18823 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18824 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18825 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18826 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18827 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18828 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18829 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18830 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18831 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18832 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
18834 #undef THUMB_VARIANT
18835 #define THUMB_VARIANT & arm_ext_v6t2
18837 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18838 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18840 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18841 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18843 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18844 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
18846 /* ARM V6 not included in V7M. */
18847 #undef THUMB_VARIANT
18848 #define THUMB_VARIANT & arm_ext_v6_notm
18849 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18850 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18851 UF(rfeib, 9900a00, 1, (RRw), rfe),
18852 UF(rfeda, 8100a00, 1, (RRw), rfe),
18853 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18854 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
18855 UF(rfefa, 8100a00, 1, (RRw), rfe),
18856 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18857 UF(rfeed, 9900a00, 1, (RRw), rfe),
18858 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18859 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18860 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18861 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
18862 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
18863 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
18864 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
18865 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18866 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
18868 /* ARM V6 not included in V7M (eg. integer SIMD). */
18869 #undef THUMB_VARIANT
18870 #define THUMB_VARIANT & arm_ext_v6_dsp
18871 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18872 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18873 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18874 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18875 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18876 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18877 /* Old name for QASX. */
18878 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18879 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18880 /* Old name for QSAX. */
18881 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18882 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18883 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18884 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18885 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18886 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18887 /* Old name for SASX. */
18888 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18889 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18890 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18891 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18892 /* Old name for SHASX. */
18893 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18894 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18895 /* Old name for SHSAX. */
18896 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18897 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18898 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18899 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18900 /* Old name for SSAX. */
18901 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18902 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18903 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18904 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18905 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18906 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18907 /* Old name for UASX. */
18908 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18909 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18910 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18911 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18912 /* Old name for UHASX. */
18913 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18914 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18915 /* Old name for UHSAX. */
18916 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18917 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18918 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18919 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18920 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18921 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18922 /* Old name for UQASX. */
18923 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18924 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18925 /* Old name for UQSAX. */
18926 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18927 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18928 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18929 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18930 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18931 /* Old name for USAX. */
18932 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18933 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18934 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18935 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18936 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18937 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18938 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18939 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18940 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18941 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18942 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18943 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18944 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18945 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18946 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18947 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18948 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18949 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18950 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18951 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18952 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18953 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18954 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18955 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18956 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18957 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18958 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18959 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18960 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18961 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18962 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18963 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18964 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18965 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
18968 #define ARM_VARIANT & arm_ext_v6k
18969 #undef THUMB_VARIANT
18970 #define THUMB_VARIANT & arm_ext_v6k
18972 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18973 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18974 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18975 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
18977 #undef THUMB_VARIANT
18978 #define THUMB_VARIANT & arm_ext_v6_notm
18979 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18981 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18982 RRnpcb), strexd, t_strexd),
18984 #undef THUMB_VARIANT
18985 #define THUMB_VARIANT & arm_ext_v6t2
18986 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18988 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18990 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18992 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18994 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
18997 #define ARM_VARIANT & arm_ext_sec
18998 #undef THUMB_VARIANT
18999 #define THUMB_VARIANT & arm_ext_sec
19001 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
19004 #define ARM_VARIANT & arm_ext_virt
19005 #undef THUMB_VARIANT
19006 #define THUMB_VARIANT & arm_ext_virt
19008 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
19009 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
19012 #define ARM_VARIANT & arm_ext_pan
19013 #undef THUMB_VARIANT
19014 #define THUMB_VARIANT & arm_ext_pan
19016 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
19019 #define ARM_VARIANT & arm_ext_v6t2
19020 #undef THUMB_VARIANT
19021 #define THUMB_VARIANT & arm_ext_v6t2
19023 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
19024 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
19025 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19026 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
19028 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
19029 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
19030 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
19031 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
19033 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19034 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19035 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19036 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
19038 /* Thumb-only instructions. */
19040 #define ARM_VARIANT NULL
19041 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
19042 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
19044 /* ARM does not really have an IT instruction, so always allow it.
19045 The opcode is copied from Thumb in order to allow warnings in
19046 -mimplicit-it=[never | arm] modes. */
19048 #define ARM_VARIANT & arm_ext_v1
19050 TUE("it", bf08, bf08, 1, (COND), it, t_it),
19051 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
19052 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
19053 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
19054 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
19055 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
19056 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
19057 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
19058 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
19059 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
19060 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
19061 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
19062 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
19063 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
19064 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
19065 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19066 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
19067 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
19069 /* Thumb2 only instructions. */
19071 #define ARM_VARIANT NULL
19073 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19074 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
19075 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
19076 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
19077 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
19078 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
19080 /* Hardware division instructions. */
19082 #define ARM_VARIANT & arm_ext_adiv
19083 #undef THUMB_VARIANT
19084 #define THUMB_VARIANT & arm_ext_div
19086 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
19087 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
19089 /* ARM V6M/V7 instructions. */
19091 #define ARM_VARIANT & arm_ext_barrier
19092 #undef THUMB_VARIANT
19093 #define THUMB_VARIANT & arm_ext_barrier
19095 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
19096 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
19097 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
19099 /* ARM V7 instructions. */
19101 #define ARM_VARIANT & arm_ext_v7
19102 #undef THUMB_VARIANT
19103 #define THUMB_VARIANT & arm_ext_v7
19105 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
19106 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
19109 #define ARM_VARIANT & arm_ext_mp
19110 #undef THUMB_VARIANT
19111 #define THUMB_VARIANT & arm_ext_mp
19113 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
19115 /* AArchv8 instructions. */
19117 #define ARM_VARIANT & arm_ext_v8
19118 #undef THUMB_VARIANT
19119 #define THUMB_VARIANT & arm_ext_v8
19121 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
19122 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
19123 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19124 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
19126 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
19127 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19128 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
19130 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
19132 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
19134 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
19136 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19137 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19138 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
19139 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19140 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19141 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
19143 /* ARMv8 T32 only. */
19145 #define ARM_VARIANT NULL
19146 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
19147 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
19148 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
19150 /* FP for ARMv8. */
19152 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19153 #undef THUMB_VARIANT
19154 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19156 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
19157 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
19158 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
19159 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
19160 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19161 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19162 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
19163 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
19164 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
19165 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
19166 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
19167 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
19168 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
19169 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
19170 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
19171 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
19172 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
19174 /* Crypto v1 extensions. */
19176 #define ARM_VARIANT & fpu_crypto_ext_armv8
19177 #undef THUMB_VARIANT
19178 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19180 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
19181 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
19182 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
19183 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
19184 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
19185 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
19186 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
19187 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
19188 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
19189 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
19190 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
19191 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
19192 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
19193 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
19196 #define ARM_VARIANT & crc_ext_armv8
19197 #undef THUMB_VARIANT
19198 #define THUMB_VARIANT & crc_ext_armv8
19199 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
19200 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
19201 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
19202 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
19203 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
19204 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
19207 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19208 #undef THUMB_VARIANT
19209 #define THUMB_VARIANT NULL
19211 cCE("wfs", e200110, 1, (RR), rd),
19212 cCE("rfs", e300110, 1, (RR), rd),
19213 cCE("wfc", e400110, 1, (RR), rd),
19214 cCE("rfc", e500110, 1, (RR), rd),
19216 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
19217 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
19218 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
19219 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
19221 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
19222 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
19223 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
19224 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
19226 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
19227 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
19228 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
19229 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
19230 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
19231 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
19232 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
19233 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
19234 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
19235 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
19236 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
19237 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
19239 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
19240 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
19241 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
19242 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
19243 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
19244 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
19245 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
19246 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
19247 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
19248 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
19249 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
19250 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
19252 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
19253 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
19254 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
19255 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
19256 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
19257 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
19258 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
19259 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
19260 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
19261 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
19262 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
19263 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
19265 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
19266 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
19267 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
19268 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
19269 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
19270 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
19271 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
19272 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
19273 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
19274 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
19275 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
19276 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
19278 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
19279 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
19280 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
19281 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
19282 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
19283 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
19284 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
19285 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
19286 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
19287 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
19288 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
19289 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
19291 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
19292 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
19293 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
19294 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
19295 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
19296 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
19297 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
19298 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
19299 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
19300 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
19301 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
19302 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
19304 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
19305 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
19306 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
19307 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
19308 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
19309 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
19310 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
19311 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
19312 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
19313 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
19314 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
19315 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
19317 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
19318 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
19319 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
19320 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
19321 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
19322 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
19323 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
19324 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
19325 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
19326 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
19327 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
19328 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
19330 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
19331 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
19332 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
19333 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
19334 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
19335 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
19336 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
19337 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
19338 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
19339 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
19340 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
19341 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
19343 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
19344 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
19345 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
19346 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
19347 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
19348 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
19349 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
19350 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
19351 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
19352 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
19353 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
19354 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
19356 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
19357 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
19358 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
19359 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
19360 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
19361 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
19362 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
19363 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
19364 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
19365 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
19366 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
19367 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
19369 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
19370 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
19371 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
19372 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
19373 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
19374 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
19375 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
19376 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
19377 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
19378 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
19379 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
19380 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
19382 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
19383 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
19384 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
19385 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
19386 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
19387 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
19388 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
19389 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
19390 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
19391 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
19392 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
19393 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
19395 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
19396 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
19397 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
19398 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
19399 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
19400 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
19401 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
19402 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
19403 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
19404 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
19405 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
19406 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
19408 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
19409 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
19410 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
19411 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
19412 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
19413 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
19414 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
19415 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
19416 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
19417 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
19418 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
19419 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
19421 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
19422 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
19423 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
19424 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
19425 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
19426 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
19427 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
19428 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
19429 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
19430 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
19431 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
19432 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
19434 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
19435 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
19436 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
19437 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
19438 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
19439 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19440 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19441 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19442 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
19443 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
19444 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
19445 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
19447 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
19448 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
19449 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
19450 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
19451 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
19452 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19453 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19454 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19455 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
19456 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
19457 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
19458 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
19460 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
19461 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
19462 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
19463 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
19464 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
19465 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19466 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19467 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19468 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
19469 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
19470 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
19471 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
19473 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
19474 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
19475 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
19476 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
19477 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
19478 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19479 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19480 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19481 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
19482 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
19483 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
19484 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
19486 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
19487 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
19488 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
19489 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
19490 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
19491 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19492 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19493 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19494 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
19495 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
19496 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
19497 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
19499 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
19500 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
19501 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
19502 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
19503 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
19504 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19505 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19506 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19507 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
19508 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
19509 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
19510 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
19512 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
19513 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
19514 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
19515 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
19516 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
19517 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19518 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19519 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19520 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
19521 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
19522 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
19523 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
19525 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
19526 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
19527 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
19528 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
19529 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
19530 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19531 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19532 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19533 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
19534 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
19535 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
19536 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
19538 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
19539 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
19540 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
19541 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
19542 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
19543 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19544 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19545 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19546 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
19547 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
19548 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
19549 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
19551 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
19552 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
19553 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
19554 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
19555 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
19556 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19557 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19558 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19559 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
19560 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
19561 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
19562 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
19564 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19565 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19566 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19567 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19568 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19569 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19570 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19571 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19572 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19573 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19574 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19575 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19577 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19578 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19579 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19580 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19581 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19582 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19583 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19584 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19585 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19586 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19587 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19588 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19590 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19591 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19592 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19593 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19594 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19595 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19596 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19597 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19598 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19599 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19600 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19601 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19603 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19604 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19605 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19606 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19608 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19609 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19610 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19611 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19612 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19613 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19614 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19615 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19616 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19617 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19618 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19619 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
19621 /* The implementation of the FIX instruction is broken on some
19622 assemblers, in that it accepts a precision specifier as well as a
19623 rounding specifier, despite the fact that this is meaningless.
19624 To be more compatible, we accept it as well, though of course it
19625 does not set any bits. */
19626 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19627 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19628 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19629 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19630 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19631 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19632 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19633 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19634 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19635 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19636 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19637 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19638 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
19640 /* Instructions that were new with the real FPA, call them V2. */
19642 #define ARM_VARIANT & fpu_fpa_ext_v2
19644 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19645 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19646 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19647 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19648 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19649 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19652 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19654 /* Moves and type conversions. */
19655 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19656 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19657 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19658 cCE("fmstat", ef1fa10, 0, (), noargs),
19659 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19660 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
19661 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19662 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19663 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19664 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19665 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19666 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19667 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19668 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
19670 /* Memory operations. */
19671 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19672 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19673 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19674 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19675 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19676 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19677 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19678 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19679 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19680 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19681 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19682 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19683 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19684 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19685 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19686 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19687 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19688 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19690 /* Monadic operations. */
19691 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19692 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19693 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
19695 /* Dyadic operations. */
19696 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19697 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19698 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19699 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19700 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19701 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19702 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19703 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19704 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19707 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19708 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19709 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19710 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
19712 /* Double precision load/store are still present on single precision
19713 implementations. */
19714 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19715 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19716 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19717 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19718 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19719 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19720 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19721 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19722 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19723 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19726 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19728 /* Moves and type conversions. */
19729 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19730 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19731 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19732 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19733 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19734 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19735 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19736 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19737 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19738 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19739 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19740 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19741 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19743 /* Monadic operations. */
19744 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19745 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19746 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19748 /* Dyadic operations. */
19749 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19750 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19751 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19752 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19753 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19754 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19755 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19756 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19757 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19760 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19761 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19762 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19763 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
19766 #define ARM_VARIANT & fpu_vfp_ext_v2
19768 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19769 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19770 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19771 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
19773 /* Instructions which may belong to either the Neon or VFP instruction sets.
19774 Individual encoder functions perform additional architecture checks. */
19776 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19777 #undef THUMB_VARIANT
19778 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19780 /* These mnemonics are unique to VFP. */
19781 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19782 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
19783 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19784 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19785 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19786 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
19787 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
19788 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19789 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19790 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19792 /* Mnemonics shared by Neon and VFP. */
19793 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19794 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19795 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19797 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19798 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19800 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19801 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19803 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19804 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19805 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19806 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19807 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19808 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19809 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19810 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19812 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
19813 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
19814 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19815 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
19818 /* NOTE: All VMOV encoding is special-cased! */
19819 NCE(vmov, 0, 1, (VMOV), neon_mov),
19820 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19822 #undef THUMB_VARIANT
19823 #define THUMB_VARIANT & fpu_neon_ext_v1
19825 #define ARM_VARIANT & fpu_neon_ext_v1
19827 /* Data processing with three registers of the same length. */
19828 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19829 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19830 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19831 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19832 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19833 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19834 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19835 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19836 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19837 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19838 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19839 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19840 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19841 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19842 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19843 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19844 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19845 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19846 /* If not immediate, fall back to neon_dyadic_i64_su.
19847 shl_imm should accept I8 I16 I32 I64,
19848 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19849 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19850 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19851 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19852 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
19853 /* Logic ops, types optional & ignored. */
19854 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19855 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19856 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19857 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19858 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19859 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19860 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19861 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19862 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19863 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
19864 /* Bitfield ops, untyped. */
19865 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19866 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19867 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19868 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19869 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19870 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19871 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19872 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19873 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19874 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19875 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19876 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19877 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19878 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19879 back to neon_dyadic_if_su. */
19880 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19881 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19882 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19883 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19884 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19885 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19886 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19887 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19888 /* Comparison. Type I8 I16 I32 F32. */
19889 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19890 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
19891 /* As above, D registers only. */
19892 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19893 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19894 /* Int and float variants, signedness unimportant. */
19895 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19896 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19897 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
19898 /* Add/sub take types I8 I16 I32 I64 F32. */
19899 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19900 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19901 /* vtst takes sizes 8, 16, 32. */
19902 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19903 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19904 /* VMUL takes I8 I16 I32 F32 P8. */
19905 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
19906 /* VQD{R}MULH takes S16 S32. */
19907 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19908 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19909 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19910 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19911 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19912 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19913 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19914 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19915 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19916 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19917 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19918 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19919 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19920 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19921 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19922 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19923 /* ARM v8.1 extension. */
19924 nUF(vqrdmlah, _vqrdmlah, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19925 nUF(vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19926 nUF(vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19927 nUF(vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19929 /* Two address, int/float. Types S8 S16 S32 F32. */
19930 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
19931 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19933 /* Data processing with two registers and a shift amount. */
19934 /* Right shifts, and variants with rounding.
19935 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19936 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19937 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19938 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19939 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19940 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19941 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19942 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19943 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19944 /* Shift and insert. Sizes accepted 8 16 32 64. */
19945 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19946 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19947 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19948 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19949 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19950 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19951 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19952 /* Right shift immediate, saturating & narrowing, with rounding variants.
19953 Types accepted S16 S32 S64 U16 U32 U64. */
19954 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19955 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19956 /* As above, unsigned. Types accepted S16 S32 S64. */
19957 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19958 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19959 /* Right shift narrowing. Types accepted I16 I32 I64. */
19960 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19961 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19962 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19963 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
19964 /* CVT with optional immediate for fixed-point variant. */
19965 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
19967 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19968 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
19970 /* Data processing, three registers of different lengths. */
19971 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19972 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19973 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19974 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19975 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19976 /* If not scalar, fall back to neon_dyadic_long.
19977 Vector types as above, scalar types S16 S32 U16 U32. */
19978 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19979 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19980 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19981 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19982 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19983 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19984 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19985 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19986 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19987 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19988 /* Saturating doubling multiplies. Types S16 S32. */
19989 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19990 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19991 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19992 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19993 S16 S32 U16 U32. */
19994 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
19996 /* Extract. Size 8. */
19997 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19998 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
20000 /* Two registers, miscellaneous. */
20001 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20002 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
20003 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
20004 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
20005 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
20006 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
20007 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
20008 /* Vector replicate. Sizes 8 16 32. */
20009 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
20010 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
20011 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20012 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
20013 /* VMOVN. Types I16 I32 I64. */
20014 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
20015 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20016 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
20017 /* VQMOVUN. Types S16 S32 S64. */
20018 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
20019 /* VZIP / VUZP. Sizes 8 16 32. */
20020 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
20021 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
20022 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
20023 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
20024 /* VQABS / VQNEG. Types S8 S16 S32. */
20025 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20026 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
20027 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
20028 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
20029 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20030 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
20031 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
20032 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
20033 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
20034 /* Reciprocal estimates. Types U32 F32. */
20035 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
20036 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
20037 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
20038 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
20039 /* VCLS. Types S8 S16 S32. */
20040 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
20041 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
20042 /* VCLZ. Types I8 I16 I32. */
20043 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
20044 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
20045 /* VCNT. Size 8. */
20046 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
20047 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
20048 /* Two address, untyped. */
20049 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
20050 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
20051 /* VTRN. Sizes 8 16 32. */
20052 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
20053 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
20055 /* Table lookup. Size 8. */
20056 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20057 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
20059 #undef THUMB_VARIANT
20060 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20062 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20064 /* Neon element/structure load/store. */
20065 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20066 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
20067 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20068 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
20069 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20070 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
20071 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20072 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
20074 #undef THUMB_VARIANT
20075 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20077 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20078 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
20079 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20080 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20081 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20082 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20083 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20084 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20085 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
20086 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
20088 #undef THUMB_VARIANT
20089 #define THUMB_VARIANT & fpu_vfp_ext_v3
20091 #define ARM_VARIANT & fpu_vfp_ext_v3
20093 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
20094 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20095 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20096 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20097 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20098 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20099 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20100 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
20101 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
20104 #define ARM_VARIANT & fpu_vfp_ext_fma
20105 #undef THUMB_VARIANT
20106 #define THUMB_VARIANT & fpu_vfp_ext_fma
20107 /* Mnemonics shared by Neon and VFP. These are included in the
20108 VFP FMA variant; NEON and VFP FMA always includes the NEON
20109 FMA instructions. */
20110 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20111 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
20112 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20113 the v form should always be used. */
20114 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20115 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
20116 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20117 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
20118 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20119 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
20121 #undef THUMB_VARIANT
20123 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20125 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20126 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20127 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20128 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20129 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20130 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
20131 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
20132 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
20135 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20137 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
20138 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
20139 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
20140 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
20141 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
20142 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
20143 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
20144 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
20145 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
20146 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20147 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20148 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
20149 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20150 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20151 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
20152 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20153 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20154 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
20155 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
20156 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
20157 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20158 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20159 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20160 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20161 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20162 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20163 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
20164 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
20165 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
20166 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
20167 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
20168 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
20169 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
20170 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
20171 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
20172 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
20173 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
20174 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20175 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20176 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20177 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20178 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20179 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20180 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20181 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20182 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20183 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
20184 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20185 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20186 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20187 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20188 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20189 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20190 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20191 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20192 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20193 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20194 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20195 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20196 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20197 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20198 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20199 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20200 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20201 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20202 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20203 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20204 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20205 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20206 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20207 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20208 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20209 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20210 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20211 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20212 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20213 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20214 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20215 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20216 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20217 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20218 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20219 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20220 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20221 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20222 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20223 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20224 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20225 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
20226 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20227 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20228 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20229 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20230 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20231 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20232 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20233 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20234 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20235 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20236 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20237 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20238 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20239 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20240 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20241 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20242 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20243 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20244 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20245 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20246 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20247 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
20248 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20249 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20250 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20251 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20252 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20253 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20254 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20255 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20256 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20257 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20258 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20259 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20260 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20261 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20262 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20263 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20264 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20265 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20266 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20267 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20268 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20269 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20270 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20271 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20272 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20273 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20274 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20275 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20276 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20277 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20278 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20279 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
20280 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
20281 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
20282 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
20283 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
20284 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
20285 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20286 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20287 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20288 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
20289 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
20290 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
20291 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
20292 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
20293 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
20294 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20295 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20296 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20297 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20298 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
20301 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20303 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
20304 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
20305 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
20306 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
20307 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
20308 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
20309 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20310 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20311 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20312 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20313 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20314 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20315 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20316 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20317 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20318 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20319 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20320 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20321 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20322 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20323 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
20324 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20325 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20326 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20327 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20328 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20329 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20330 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20331 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20332 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20333 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20334 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20335 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20336 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20337 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20338 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20339 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20340 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20341 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20342 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20343 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20344 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20345 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20346 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20347 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20348 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20349 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20350 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20351 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20352 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20353 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20354 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20355 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20356 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20357 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20358 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20359 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20362 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20364 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20365 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20366 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20367 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20368 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20369 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20370 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20371 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20372 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
20373 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
20374 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
20375 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
20376 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
20377 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
20378 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
20379 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
20380 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
20381 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
20382 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
20383 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
20384 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
20385 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
20386 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
20387 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
20388 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
20389 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
20390 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
20391 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
20392 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
20393 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
20394 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
20395 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
20396 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
20397 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
20398 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
20399 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
20400 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
20401 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
20402 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
20403 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
20404 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
20405 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
20406 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
20407 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
20408 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
20409 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
20410 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
20411 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
20412 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
20413 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
20414 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
20415 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
20416 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
20417 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
20418 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
20419 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
20420 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
20421 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
20422 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
20423 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
20424 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
20425 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
20426 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
20427 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
20428 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20429 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20430 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20431 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20432 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20433 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20434 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20435 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20436 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20437 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20438 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20439 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20442 #undef THUMB_VARIANT
20468 /* MD interface: bits in the object file. */
20470 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20471 for use in the a.out file, and stores them in the array pointed to by buf.
20472 This knows about the endian-ness of the target machine and does
20473 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20474 2 (short) and 4 (long) Floating numbers are put out as a series of
20475 LITTLENUMS (shorts, here at least). */
20478 md_number_to_chars (char * buf, valueT val, int n)
20480 if (target_big_endian)
20481 number_to_chars_bigendian (buf, val, n);
20483 number_to_chars_littleendian (buf, val, n);
20487 md_chars_to_number (char * buf, int n)
20490 unsigned char * where = (unsigned char *) buf;
20492 if (target_big_endian)
20497 result |= (*where++ & 255);
20505 result |= (where[n] & 255);
20512 /* MD interface: Sections. */
20514 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20515 that an rs_machine_dependent frag may reach. */
20518 arm_frag_max_var (fragS *fragp)
20520 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20521 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20523 Note that we generate relaxable instructions even for cases that don't
20524 really need it, like an immediate that's a trivial constant. So we're
20525 overestimating the instruction size for some of those cases. Rather
20526 than putting more intelligence here, it would probably be better to
20527 avoid generating a relaxation frag in the first place when it can be
20528 determined up front that a short instruction will suffice. */
20530 gas_assert (fragp->fr_type == rs_machine_dependent);
20534 /* Estimate the size of a frag before relaxing. Assume everything fits in
20538 md_estimate_size_before_relax (fragS * fragp,
20539 segT segtype ATTRIBUTE_UNUSED)
20545 /* Convert a machine dependent frag. */
20548 md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
20550 unsigned long insn;
20551 unsigned long old_op;
20559 buf = fragp->fr_literal + fragp->fr_fix;
20561 old_op = bfd_get_16(abfd, buf);
20562 if (fragp->fr_symbol)
20564 exp.X_op = O_symbol;
20565 exp.X_add_symbol = fragp->fr_symbol;
20569 exp.X_op = O_constant;
20571 exp.X_add_number = fragp->fr_offset;
20572 opcode = fragp->fr_subtype;
20575 case T_MNEM_ldr_pc:
20576 case T_MNEM_ldr_pc2:
20577 case T_MNEM_ldr_sp:
20578 case T_MNEM_str_sp:
20585 if (fragp->fr_var == 4)
20587 insn = THUMB_OP32 (opcode);
20588 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20590 insn |= (old_op & 0x700) << 4;
20594 insn |= (old_op & 7) << 12;
20595 insn |= (old_op & 0x38) << 13;
20597 insn |= 0x00000c00;
20598 put_thumb32_insn (buf, insn);
20599 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20603 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20605 pc_rel = (opcode == T_MNEM_ldr_pc2);
20608 if (fragp->fr_var == 4)
20610 insn = THUMB_OP32 (opcode);
20611 insn |= (old_op & 0xf0) << 4;
20612 put_thumb32_insn (buf, insn);
20613 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20617 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20618 exp.X_add_number -= 4;
20626 if (fragp->fr_var == 4)
20628 int r0off = (opcode == T_MNEM_mov
20629 || opcode == T_MNEM_movs) ? 0 : 8;
20630 insn = THUMB_OP32 (opcode);
20631 insn = (insn & 0xe1ffffff) | 0x10000000;
20632 insn |= (old_op & 0x700) << r0off;
20633 put_thumb32_insn (buf, insn);
20634 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20638 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20643 if (fragp->fr_var == 4)
20645 insn = THUMB_OP32(opcode);
20646 put_thumb32_insn (buf, insn);
20647 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20650 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20654 if (fragp->fr_var == 4)
20656 insn = THUMB_OP32(opcode);
20657 insn |= (old_op & 0xf00) << 14;
20658 put_thumb32_insn (buf, insn);
20659 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20662 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20665 case T_MNEM_add_sp:
20666 case T_MNEM_add_pc:
20667 case T_MNEM_inc_sp:
20668 case T_MNEM_dec_sp:
20669 if (fragp->fr_var == 4)
20671 /* ??? Choose between add and addw. */
20672 insn = THUMB_OP32 (opcode);
20673 insn |= (old_op & 0xf0) << 4;
20674 put_thumb32_insn (buf, insn);
20675 if (opcode == T_MNEM_add_pc)
20676 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20678 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20681 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20689 if (fragp->fr_var == 4)
20691 insn = THUMB_OP32 (opcode);
20692 insn |= (old_op & 0xf0) << 4;
20693 insn |= (old_op & 0xf) << 16;
20694 put_thumb32_insn (buf, insn);
20695 if (insn & (1 << 20))
20696 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20698 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20701 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20707 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
20708 (enum bfd_reloc_code_real) reloc_type);
20709 fixp->fx_file = fragp->fr_file;
20710 fixp->fx_line = fragp->fr_line;
20711 fragp->fr_fix += fragp->fr_var;
20713 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20714 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
20715 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
20716 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
20719 /* Return the size of a relaxable immediate operand instruction.
20720 SHIFT and SIZE specify the form of the allowable immediate. */
20722 relax_immediate (fragS *fragp, int size, int shift)
20728 /* ??? Should be able to do better than this. */
20729 if (fragp->fr_symbol)
20732 low = (1 << shift) - 1;
20733 mask = (1 << (shift + size)) - (1 << shift);
20734 offset = fragp->fr_offset;
20735 /* Force misaligned offsets to 32-bit variant. */
20738 if (offset & ~mask)
20743 /* Get the address of a symbol during relaxation. */
20745 relaxed_symbol_addr (fragS *fragp, long stretch)
20751 sym = fragp->fr_symbol;
20752 sym_frag = symbol_get_frag (sym);
20753 know (S_GET_SEGMENT (sym) != absolute_section
20754 || sym_frag == &zero_address_frag);
20755 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20757 /* If frag has yet to be reached on this pass, assume it will
20758 move by STRETCH just as we did. If this is not so, it will
20759 be because some frag between grows, and that will force
20763 && sym_frag->relax_marker != fragp->relax_marker)
20767 /* Adjust stretch for any alignment frag. Note that if have
20768 been expanding the earlier code, the symbol may be
20769 defined in what appears to be an earlier frag. FIXME:
20770 This doesn't handle the fr_subtype field, which specifies
20771 a maximum number of bytes to skip when doing an
20773 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20775 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20778 stretch = - ((- stretch)
20779 & ~ ((1 << (int) f->fr_offset) - 1));
20781 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20793 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20796 relax_adr (fragS *fragp, asection *sec, long stretch)
20801 /* Assume worst case for symbols not known to be in the same section. */
20802 if (fragp->fr_symbol == NULL
20803 || !S_IS_DEFINED (fragp->fr_symbol)
20804 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20805 || S_IS_WEAK (fragp->fr_symbol))
20808 val = relaxed_symbol_addr (fragp, stretch);
20809 addr = fragp->fr_address + fragp->fr_fix;
20810 addr = (addr + 4) & ~3;
20811 /* Force misaligned targets to 32-bit variant. */
20815 if (val < 0 || val > 1020)
20820 /* Return the size of a relaxable add/sub immediate instruction. */
20822 relax_addsub (fragS *fragp, asection *sec)
20827 buf = fragp->fr_literal + fragp->fr_fix;
20828 op = bfd_get_16(sec->owner, buf);
20829 if ((op & 0xf) == ((op >> 4) & 0xf))
20830 return relax_immediate (fragp, 8, 0);
20832 return relax_immediate (fragp, 3, 0);
20835 /* Return TRUE iff the definition of symbol S could be pre-empted
20836 (overridden) at link or load time. */
20838 symbol_preemptible (symbolS *s)
20840 /* Weak symbols can always be pre-empted. */
20844 /* Non-global symbols cannot be pre-empted. */
20845 if (! S_IS_EXTERNAL (s))
20849 /* In ELF, a global symbol can be marked protected, or private. In that
20850 case it can't be pre-empted (other definitions in the same link unit
20851 would violate the ODR). */
20852 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20856 /* Other global symbols might be pre-empted. */
20860 /* Return the size of a relaxable branch instruction. BITS is the
20861 size of the offset field in the narrow instruction. */
20864 relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
20870 /* Assume worst case for symbols not known to be in the same section. */
20871 if (!S_IS_DEFINED (fragp->fr_symbol)
20872 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20873 || S_IS_WEAK (fragp->fr_symbol))
20877 /* A branch to a function in ARM state will require interworking. */
20878 if (S_IS_DEFINED (fragp->fr_symbol)
20879 && ARM_IS_FUNC (fragp->fr_symbol))
20883 if (symbol_preemptible (fragp->fr_symbol))
20886 val = relaxed_symbol_addr (fragp, stretch);
20887 addr = fragp->fr_address + fragp->fr_fix + 4;
20890 /* Offset is a signed value *2 */
20892 if (val >= limit || val < -limit)
20898 /* Relax a machine dependent frag. This returns the amount by which
20899 the current size of the frag should change. */
20902 arm_relax_frag (asection *sec, fragS *fragp, long stretch)
20907 oldsize = fragp->fr_var;
20908 switch (fragp->fr_subtype)
20910 case T_MNEM_ldr_pc2:
20911 newsize = relax_adr (fragp, sec, stretch);
20913 case T_MNEM_ldr_pc:
20914 case T_MNEM_ldr_sp:
20915 case T_MNEM_str_sp:
20916 newsize = relax_immediate (fragp, 8, 2);
20920 newsize = relax_immediate (fragp, 5, 2);
20924 newsize = relax_immediate (fragp, 5, 1);
20928 newsize = relax_immediate (fragp, 5, 0);
20931 newsize = relax_adr (fragp, sec, stretch);
20937 newsize = relax_immediate (fragp, 8, 0);
20940 newsize = relax_branch (fragp, sec, 11, stretch);
20943 newsize = relax_branch (fragp, sec, 8, stretch);
20945 case T_MNEM_add_sp:
20946 case T_MNEM_add_pc:
20947 newsize = relax_immediate (fragp, 8, 2);
20949 case T_MNEM_inc_sp:
20950 case T_MNEM_dec_sp:
20951 newsize = relax_immediate (fragp, 7, 2);
20957 newsize = relax_addsub (fragp, sec);
20963 fragp->fr_var = newsize;
20964 /* Freeze wide instructions that are at or before the same location as
20965 in the previous pass. This avoids infinite loops.
20966 Don't freeze them unconditionally because targets may be artificially
20967 misaligned by the expansion of preceding frags. */
20968 if (stretch <= 0 && newsize > 2)
20970 md_convert_frag (sec->owner, sec, fragp);
20974 return newsize - oldsize;
20977 /* Round up a section size to the appropriate boundary. */
20980 md_section_align (segT segment ATTRIBUTE_UNUSED,
20983 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20984 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20986 /* For a.out, force the section size to be aligned. If we don't do
20987 this, BFD will align it for us, but it will not write out the
20988 final bytes of the section. This may be a bug in BFD, but it is
20989 easier to fix it here since that is how the other a.out targets
20993 align = bfd_get_section_alignment (stdoutput, segment);
20994 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
21001 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21002 of an rs_align_code fragment. */
21005 arm_handle_align (fragS * fragP)
21007 static char const arm_noop[2][2][4] =
21010 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21011 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21014 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21015 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21018 static char const thumb_noop[2][2][2] =
21021 {0xc0, 0x46}, /* LE */
21022 {0x46, 0xc0}, /* BE */
21025 {0x00, 0xbf}, /* LE */
21026 {0xbf, 0x00} /* BE */
21029 static char const wide_thumb_noop[2][4] =
21030 { /* Wide Thumb-2 */
21031 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21032 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21035 unsigned bytes, fix, noop_size;
21038 const char *narrow_noop = NULL;
21043 if (fragP->fr_type != rs_align_code)
21046 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
21047 p = fragP->fr_literal + fragP->fr_fix;
21050 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
21051 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
21053 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
21055 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
21057 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21058 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
21060 narrow_noop = thumb_noop[1][target_big_endian];
21061 noop = wide_thumb_noop[target_big_endian];
21064 noop = thumb_noop[0][target_big_endian];
21072 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
21073 ? selected_cpu : arm_arch_none,
21075 [target_big_endian];
21082 fragP->fr_var = noop_size;
21084 if (bytes & (noop_size - 1))
21086 fix = bytes & (noop_size - 1);
21088 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
21090 memset (p, 0, fix);
21097 if (bytes & noop_size)
21099 /* Insert a narrow noop. */
21100 memcpy (p, narrow_noop, noop_size);
21102 bytes -= noop_size;
21106 /* Use wide noops for the remainder */
21110 while (bytes >= noop_size)
21112 memcpy (p, noop, noop_size);
21114 bytes -= noop_size;
21118 fragP->fr_fix += fix;
21121 /* Called from md_do_align. Used to create an alignment
21122 frag in a code section. */
21125 arm_frag_align_code (int n, int max)
21129 /* We assume that there will never be a requirement
21130 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21131 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
21136 _("alignments greater than %d bytes not supported in .text sections."),
21137 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
21138 as_fatal ("%s", err_msg);
21141 p = frag_var (rs_align_code,
21142 MAX_MEM_FOR_RS_ALIGN_CODE,
21144 (relax_substateT) max,
21151 /* Perform target specific initialisation of a frag.
21152 Note - despite the name this initialisation is not done when the frag
21153 is created, but only when its type is assigned. A frag can be created
21154 and used a long time before its type is set, so beware of assuming that
21155 this initialisationis performed first. */
21159 arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
21161 /* Record whether this frag is in an ARM or a THUMB area. */
21162 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21165 #else /* OBJ_ELF is defined. */
21167 arm_init_frag (fragS * fragP, int max_chars)
21169 int frag_thumb_mode;
21171 /* If the current ARM vs THUMB mode has not already
21172 been recorded into this frag then do so now. */
21173 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
21174 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21176 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
21178 /* Record a mapping symbol for alignment frags. We will delete this
21179 later if the alignment ends up empty. */
21180 switch (fragP->fr_type)
21183 case rs_align_test:
21185 mapping_state_2 (MAP_DATA, max_chars);
21187 case rs_align_code:
21188 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
21195 /* When we change sections we need to issue a new mapping symbol. */
21198 arm_elf_change_section (void)
21200 /* Link an unlinked unwind index table section to the .text section. */
21201 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
21202 && elf_linked_to_section (now_seg) == NULL)
21203 elf_linked_to_section (now_seg) = text_section;
21207 arm_elf_section_type (const char * str, size_t len)
21209 if (len == 5 && strncmp (str, "exidx", 5) == 0)
21210 return SHT_ARM_EXIDX;
21215 /* Code to deal with unwinding tables. */
21217 static void add_unwind_adjustsp (offsetT);
21219 /* Generate any deferred unwind frame offset. */
21222 flush_pending_unwind (void)
21226 offset = unwind.pending_offset;
21227 unwind.pending_offset = 0;
21229 add_unwind_adjustsp (offset);
21232 /* Add an opcode to this list for this function. Two-byte opcodes should
21233 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21237 add_unwind_opcode (valueT op, int length)
21239 /* Add any deferred stack adjustment. */
21240 if (unwind.pending_offset)
21241 flush_pending_unwind ();
21243 unwind.sp_restored = 0;
21245 if (unwind.opcode_count + length > unwind.opcode_alloc)
21247 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
21248 if (unwind.opcodes)
21249 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
21250 unwind.opcode_alloc);
21252 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
21257 unwind.opcodes[unwind.opcode_count] = op & 0xff;
21259 unwind.opcode_count++;
21263 /* Add unwind opcodes to adjust the stack pointer. */
21266 add_unwind_adjustsp (offsetT offset)
21270 if (offset > 0x200)
21272 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21277 /* Long form: 0xb2, uleb128. */
21278 /* This might not fit in a word so add the individual bytes,
21279 remembering the list is built in reverse order. */
21280 o = (valueT) ((offset - 0x204) >> 2);
21282 add_unwind_opcode (0, 1);
21284 /* Calculate the uleb128 encoding of the offset. */
21288 bytes[n] = o & 0x7f;
21294 /* Add the insn. */
21296 add_unwind_opcode (bytes[n - 1], 1);
21297 add_unwind_opcode (0xb2, 1);
21299 else if (offset > 0x100)
21301 /* Two short opcodes. */
21302 add_unwind_opcode (0x3f, 1);
21303 op = (offset - 0x104) >> 2;
21304 add_unwind_opcode (op, 1);
21306 else if (offset > 0)
21308 /* Short opcode. */
21309 op = (offset - 4) >> 2;
21310 add_unwind_opcode (op, 1);
21312 else if (offset < 0)
21315 while (offset > 0x100)
21317 add_unwind_opcode (0x7f, 1);
21320 op = ((offset - 4) >> 2) | 0x40;
21321 add_unwind_opcode (op, 1);
21325 /* Finish the list of unwind opcodes for this function. */
21327 finish_unwind_opcodes (void)
21331 if (unwind.fp_used)
21333 /* Adjust sp as necessary. */
21334 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
21335 flush_pending_unwind ();
21337 /* After restoring sp from the frame pointer. */
21338 op = 0x90 | unwind.fp_reg;
21339 add_unwind_opcode (op, 1);
21342 flush_pending_unwind ();
21346 /* Start an exception table entry. If idx is nonzero this is an index table
21350 start_unwind_section (const segT text_seg, int idx)
21352 const char * text_name;
21353 const char * prefix;
21354 const char * prefix_once;
21355 const char * group_name;
21359 size_t sec_name_len;
21366 prefix = ELF_STRING_ARM_unwind;
21367 prefix_once = ELF_STRING_ARM_unwind_once;
21368 type = SHT_ARM_EXIDX;
21372 prefix = ELF_STRING_ARM_unwind_info;
21373 prefix_once = ELF_STRING_ARM_unwind_info_once;
21374 type = SHT_PROGBITS;
21377 text_name = segment_name (text_seg);
21378 if (streq (text_name, ".text"))
21381 if (strncmp (text_name, ".gnu.linkonce.t.",
21382 strlen (".gnu.linkonce.t.")) == 0)
21384 prefix = prefix_once;
21385 text_name += strlen (".gnu.linkonce.t.");
21388 prefix_len = strlen (prefix);
21389 text_len = strlen (text_name);
21390 sec_name_len = prefix_len + text_len;
21391 sec_name = (char *) xmalloc (sec_name_len + 1);
21392 memcpy (sec_name, prefix, prefix_len);
21393 memcpy (sec_name + prefix_len, text_name, text_len);
21394 sec_name[prefix_len + text_len] = '\0';
21400 /* Handle COMDAT group. */
21401 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
21403 group_name = elf_group_name (text_seg);
21404 if (group_name == NULL)
21406 as_bad (_("Group section `%s' has no group signature"),
21407 segment_name (text_seg));
21408 ignore_rest_of_line ();
21411 flags |= SHF_GROUP;
21415 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
21417 /* Set the section link for index tables. */
21419 elf_linked_to_section (now_seg) = text_seg;
21423 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21424 personality routine data. Returns zero, or the index table value for
21425 an inline entry. */
21428 create_unwind_entry (int have_data)
21433 /* The current word of data. */
21435 /* The number of bytes left in this word. */
21438 finish_unwind_opcodes ();
21440 /* Remember the current text section. */
21441 unwind.saved_seg = now_seg;
21442 unwind.saved_subseg = now_subseg;
21444 start_unwind_section (now_seg, 0);
21446 if (unwind.personality_routine == NULL)
21448 if (unwind.personality_index == -2)
21451 as_bad (_("handlerdata in cantunwind frame"));
21452 return 1; /* EXIDX_CANTUNWIND. */
21455 /* Use a default personality routine if none is specified. */
21456 if (unwind.personality_index == -1)
21458 if (unwind.opcode_count > 3)
21459 unwind.personality_index = 1;
21461 unwind.personality_index = 0;
21464 /* Space for the personality routine entry. */
21465 if (unwind.personality_index == 0)
21467 if (unwind.opcode_count > 3)
21468 as_bad (_("too many unwind opcodes for personality routine 0"));
21472 /* All the data is inline in the index table. */
21475 while (unwind.opcode_count > 0)
21477 unwind.opcode_count--;
21478 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21482 /* Pad with "finish" opcodes. */
21484 data = (data << 8) | 0xb0;
21491 /* We get two opcodes "free" in the first word. */
21492 size = unwind.opcode_count - 2;
21496 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21497 if (unwind.personality_index != -1)
21499 as_bad (_("attempt to recreate an unwind entry"));
21503 /* An extra byte is required for the opcode count. */
21504 size = unwind.opcode_count + 1;
21507 size = (size + 3) >> 2;
21509 as_bad (_("too many unwind opcodes"));
21511 frag_align (2, 0, 0);
21512 record_alignment (now_seg, 2);
21513 unwind.table_entry = expr_build_dot ();
21515 /* Allocate the table entry. */
21516 ptr = frag_more ((size << 2) + 4);
21517 /* PR 13449: Zero the table entries in case some of them are not used. */
21518 memset (ptr, 0, (size << 2) + 4);
21519 where = frag_now_fix () - ((size << 2) + 4);
21521 switch (unwind.personality_index)
21524 /* ??? Should this be a PLT generating relocation? */
21525 /* Custom personality routine. */
21526 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
21527 BFD_RELOC_ARM_PREL31);
21532 /* Set the first byte to the number of additional words. */
21533 data = size > 0 ? size - 1 : 0;
21537 /* ABI defined personality routines. */
21539 /* Three opcodes bytes are packed into the first word. */
21546 /* The size and first two opcode bytes go in the first word. */
21547 data = ((0x80 + unwind.personality_index) << 8) | size;
21552 /* Should never happen. */
21556 /* Pack the opcodes into words (MSB first), reversing the list at the same
21558 while (unwind.opcode_count > 0)
21562 md_number_to_chars (ptr, data, 4);
21567 unwind.opcode_count--;
21569 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21572 /* Finish off the last word. */
21575 /* Pad with "finish" opcodes. */
21577 data = (data << 8) | 0xb0;
21579 md_number_to_chars (ptr, data, 4);
21584 /* Add an empty descriptor if there is no user-specified data. */
21585 ptr = frag_more (4);
21586 md_number_to_chars (ptr, 0, 4);
21593 /* Initialize the DWARF-2 unwind information for this procedure. */
21596 tc_arm_frame_initial_instructions (void)
21598 cfi_add_CFA_def_cfa (REG_SP, 0);
21600 #endif /* OBJ_ELF */
21602 /* Convert REGNAME to a DWARF-2 register number. */
21605 tc_arm_regname_to_dw2regnum (char *regname)
21607 int reg = arm_reg_parse (®name, REG_TYPE_RN);
21611 /* PR 16694: Allow VFP registers as well. */
21612 reg = arm_reg_parse (®name, REG_TYPE_VFS);
21616 reg = arm_reg_parse (®name, REG_TYPE_VFD);
21625 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
21629 exp.X_op = O_secrel;
21630 exp.X_add_symbol = symbol;
21631 exp.X_add_number = 0;
21632 emit_expr (&exp, size);
21636 /* MD interface: Symbol and relocation handling. */
21638 /* Return the address within the segment that a PC-relative fixup is
21639 relative to. For ARM, PC-relative fixups applied to instructions
21640 are generally relative to the location of the fixup plus 8 bytes.
21641 Thumb branches are offset by 4, and Thumb loads relative to PC
21642 require special handling. */
21645 md_pcrel_from_section (fixS * fixP, segT seg)
21647 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21649 /* If this is pc-relative and we are going to emit a relocation
21650 then we just want to put out any pipeline compensation that the linker
21651 will need. Otherwise we want to use the calculated base.
21652 For WinCE we skip the bias for externals as well, since this
21653 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21655 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
21656 || (arm_force_relocation (fixP)
21658 && !S_IS_EXTERNAL (fixP->fx_addsy)
21664 switch (fixP->fx_r_type)
21666 /* PC relative addressing on the Thumb is slightly odd as the
21667 bottom two bits of the PC are forced to zero for the
21668 calculation. This happens *after* application of the
21669 pipeline offset. However, Thumb adrl already adjusts for
21670 this, so we need not do it again. */
21671 case BFD_RELOC_ARM_THUMB_ADD:
21674 case BFD_RELOC_ARM_THUMB_OFFSET:
21675 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21676 case BFD_RELOC_ARM_T32_ADD_PC12:
21677 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
21678 return (base + 4) & ~3;
21680 /* Thumb branches are simply offset by +4. */
21681 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21682 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21683 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21684 case BFD_RELOC_THUMB_PCREL_BRANCH20:
21685 case BFD_RELOC_THUMB_PCREL_BRANCH25:
21688 case BFD_RELOC_THUMB_PCREL_BRANCH23:
21690 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21691 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21692 && ARM_IS_FUNC (fixP->fx_addsy)
21693 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21694 base = fixP->fx_where + fixP->fx_frag->fr_address;
21697 /* BLX is like branches above, but forces the low two bits of PC to
21699 case BFD_RELOC_THUMB_PCREL_BLX:
21701 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21702 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21703 && THUMB_IS_FUNC (fixP->fx_addsy)
21704 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21705 base = fixP->fx_where + fixP->fx_frag->fr_address;
21706 return (base + 4) & ~3;
21708 /* ARM mode branches are offset by +8. However, the Windows CE
21709 loader expects the relocation not to take this into account. */
21710 case BFD_RELOC_ARM_PCREL_BLX:
21712 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21713 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21714 && ARM_IS_FUNC (fixP->fx_addsy)
21715 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21716 base = fixP->fx_where + fixP->fx_frag->fr_address;
21719 case BFD_RELOC_ARM_PCREL_CALL:
21721 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21722 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
21723 && THUMB_IS_FUNC (fixP->fx_addsy)
21724 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21725 base = fixP->fx_where + fixP->fx_frag->fr_address;
21728 case BFD_RELOC_ARM_PCREL_BRANCH:
21729 case BFD_RELOC_ARM_PCREL_JUMP:
21730 case BFD_RELOC_ARM_PLT32:
21732 /* When handling fixups immediately, because we have already
21733 discovered the value of a symbol, or the address of the frag involved
21734 we must account for the offset by +8, as the OS loader will never see the reloc.
21735 see fixup_segment() in write.c
21736 The S_IS_EXTERNAL test handles the case of global symbols.
21737 Those need the calculated base, not just the pipe compensation the linker will need. */
21739 && fixP->fx_addsy != NULL
21740 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21741 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21749 /* ARM mode loads relative to PC are also offset by +8. Unlike
21750 branches, the Windows CE loader *does* expect the relocation
21751 to take this into account. */
21752 case BFD_RELOC_ARM_OFFSET_IMM:
21753 case BFD_RELOC_ARM_OFFSET_IMM8:
21754 case BFD_RELOC_ARM_HWLITERAL:
21755 case BFD_RELOC_ARM_LITERAL:
21756 case BFD_RELOC_ARM_CP_OFF_IMM:
21760 /* Other PC-relative relocations are un-offset. */
21766 static bfd_boolean flag_warn_syms = TRUE;
21769 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
21771 /* PR 18347 - Warn if the user attempts to create a symbol with the same
21772 name as an ARM instruction. Whilst strictly speaking it is allowed, it
21773 does mean that the resulting code might be very confusing to the reader.
21774 Also this warning can be triggered if the user omits an operand before
21775 an immediate address, eg:
21779 GAS treats this as an assignment of the value of the symbol foo to a
21780 symbol LDR, and so (without this code) it will not issue any kind of
21781 warning or error message.
21783 Note - ARM instructions are case-insensitive but the strings in the hash
21784 table are all stored in lower case, so we must first ensure that name is
21786 if (flag_warn_syms && arm_ops_hsh)
21788 char * nbuf = strdup (name);
21791 for (p = nbuf; *p; p++)
21793 if (hash_find (arm_ops_hsh, nbuf) != NULL)
21795 static struct hash_control * already_warned = NULL;
21797 if (already_warned == NULL)
21798 already_warned = hash_new ();
21799 /* Only warn about the symbol once. To keep the code
21800 simple we let hash_insert do the lookup for us. */
21801 if (hash_insert (already_warned, name, NULL) == NULL)
21802 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
21811 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21812 Otherwise we have no need to default values of symbols. */
21815 md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
21818 if (name[0] == '_' && name[1] == 'G'
21819 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21823 if (symbol_find (name))
21824 as_bad (_("GOT already in the symbol table"));
21826 GOT_symbol = symbol_new (name, undefined_section,
21827 (valueT) 0, & zero_address_frag);
21837 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21838 computed as two separate immediate values, added together. We
21839 already know that this value cannot be computed by just one ARM
21842 static unsigned int
21843 validate_immediate_twopart (unsigned int val,
21844 unsigned int * highpart)
21849 for (i = 0; i < 32; i += 2)
21850 if (((a = rotate_left (val, i)) & 0xff) != 0)
21856 * highpart = (a >> 8) | ((i + 24) << 7);
21858 else if (a & 0xff0000)
21860 if (a & 0xff000000)
21862 * highpart = (a >> 16) | ((i + 16) << 7);
21866 gas_assert (a & 0xff000000);
21867 * highpart = (a >> 24) | ((i + 8) << 7);
21870 return (a & 0xff) | (i << 7);
21877 validate_offset_imm (unsigned int val, int hwse)
21879 if ((hwse && val > 255) || val > 4095)
21884 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21885 negative immediate constant by altering the instruction. A bit of
21890 by inverting the second operand, and
21893 by negating the second operand. */
21896 negate_data_op (unsigned long * instruction,
21897 unsigned long value)
21900 unsigned long negated, inverted;
21902 negated = encode_arm_immediate (-value);
21903 inverted = encode_arm_immediate (~value);
21905 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21908 /* First negates. */
21909 case OPCODE_SUB: /* ADD <-> SUB */
21910 new_inst = OPCODE_ADD;
21915 new_inst = OPCODE_SUB;
21919 case OPCODE_CMP: /* CMP <-> CMN */
21920 new_inst = OPCODE_CMN;
21925 new_inst = OPCODE_CMP;
21929 /* Now Inverted ops. */
21930 case OPCODE_MOV: /* MOV <-> MVN */
21931 new_inst = OPCODE_MVN;
21936 new_inst = OPCODE_MOV;
21940 case OPCODE_AND: /* AND <-> BIC */
21941 new_inst = OPCODE_BIC;
21946 new_inst = OPCODE_AND;
21950 case OPCODE_ADC: /* ADC <-> SBC */
21951 new_inst = OPCODE_SBC;
21956 new_inst = OPCODE_ADC;
21960 /* We cannot do anything. */
21965 if (value == (unsigned) FAIL)
21968 *instruction &= OPCODE_MASK;
21969 *instruction |= new_inst << DATA_OP_SHIFT;
21973 /* Like negate_data_op, but for Thumb-2. */
21975 static unsigned int
21976 thumb32_negate_data_op (offsetT *instruction, unsigned int value)
21980 unsigned int negated, inverted;
21982 negated = encode_thumb32_immediate (-value);
21983 inverted = encode_thumb32_immediate (~value);
21985 rd = (*instruction >> 8) & 0xf;
21986 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21989 /* ADD <-> SUB. Includes CMP <-> CMN. */
21990 case T2_OPCODE_SUB:
21991 new_inst = T2_OPCODE_ADD;
21995 case T2_OPCODE_ADD:
21996 new_inst = T2_OPCODE_SUB;
22000 /* ORR <-> ORN. Includes MOV <-> MVN. */
22001 case T2_OPCODE_ORR:
22002 new_inst = T2_OPCODE_ORN;
22006 case T2_OPCODE_ORN:
22007 new_inst = T2_OPCODE_ORR;
22011 /* AND <-> BIC. TST has no inverted equivalent. */
22012 case T2_OPCODE_AND:
22013 new_inst = T2_OPCODE_BIC;
22020 case T2_OPCODE_BIC:
22021 new_inst = T2_OPCODE_AND;
22026 case T2_OPCODE_ADC:
22027 new_inst = T2_OPCODE_SBC;
22031 case T2_OPCODE_SBC:
22032 new_inst = T2_OPCODE_ADC;
22036 /* We cannot do anything. */
22041 if (value == (unsigned int)FAIL)
22044 *instruction &= T2_OPCODE_MASK;
22045 *instruction |= new_inst << T2_DATA_OP_SHIFT;
22049 /* Read a 32-bit thumb instruction from buf. */
22050 static unsigned long
22051 get_thumb32_insn (char * buf)
22053 unsigned long insn;
22054 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
22055 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22061 /* We usually want to set the low bit on the address of thumb function
22062 symbols. In particular .word foo - . should have the low bit set.
22063 Generic code tries to fold the difference of two symbols to
22064 a constant. Prevent this and force a relocation when the first symbols
22065 is a thumb function. */
22068 arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
22070 if (op == O_subtract
22071 && l->X_op == O_symbol
22072 && r->X_op == O_symbol
22073 && THUMB_IS_FUNC (l->X_add_symbol))
22075 l->X_op = O_subtract;
22076 l->X_op_symbol = r->X_add_symbol;
22077 l->X_add_number -= r->X_add_number;
22081 /* Process as normal. */
22085 /* Encode Thumb2 unconditional branches and calls. The encoding
22086 for the 2 are identical for the immediate values. */
22089 encode_thumb2_b_bl_offset (char * buf, offsetT value)
22091 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22094 addressT S, I1, I2, lo, hi;
22096 S = (value >> 24) & 0x01;
22097 I1 = (value >> 23) & 0x01;
22098 I2 = (value >> 22) & 0x01;
22099 hi = (value >> 12) & 0x3ff;
22100 lo = (value >> 1) & 0x7ff;
22101 newval = md_chars_to_number (buf, THUMB_SIZE);
22102 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22103 newval |= (S << 10) | hi;
22104 newval2 &= ~T2I1I2MASK;
22105 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
22106 md_number_to_chars (buf, newval, THUMB_SIZE);
22107 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22111 md_apply_fix (fixS * fixP,
22115 offsetT value = * valP;
22117 unsigned int newimm;
22118 unsigned long temp;
22120 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
22122 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
22124 /* Note whether this will delete the relocation. */
22126 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
22129 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22130 consistency with the behaviour on 32-bit hosts. Remember value
22132 value &= 0xffffffff;
22133 value ^= 0x80000000;
22134 value -= 0x80000000;
22137 fixP->fx_addnumber = value;
22139 /* Same treatment for fixP->fx_offset. */
22140 fixP->fx_offset &= 0xffffffff;
22141 fixP->fx_offset ^= 0x80000000;
22142 fixP->fx_offset -= 0x80000000;
22144 switch (fixP->fx_r_type)
22146 case BFD_RELOC_NONE:
22147 /* This will need to go in the object file. */
22151 case BFD_RELOC_ARM_IMMEDIATE:
22152 /* We claim that this fixup has been processed here,
22153 even if in fact we generate an error because we do
22154 not have a reloc for it, so tc_gen_reloc will reject it. */
22157 if (fixP->fx_addsy)
22159 const char *msg = 0;
22161 if (! S_IS_DEFINED (fixP->fx_addsy))
22162 msg = _("undefined symbol %s used as an immediate value");
22163 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22164 msg = _("symbol %s is in a different section");
22165 else if (S_IS_WEAK (fixP->fx_addsy))
22166 msg = _("symbol %s is weak and may be overridden later");
22170 as_bad_where (fixP->fx_file, fixP->fx_line,
22171 msg, S_GET_NAME (fixP->fx_addsy));
22176 temp = md_chars_to_number (buf, INSN_SIZE);
22178 /* If the offset is negative, we should use encoding A2 for ADR. */
22179 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
22180 newimm = negate_data_op (&temp, value);
22183 newimm = encode_arm_immediate (value);
22185 /* If the instruction will fail, see if we can fix things up by
22186 changing the opcode. */
22187 if (newimm == (unsigned int) FAIL)
22188 newimm = negate_data_op (&temp, value);
22191 if (newimm == (unsigned int) FAIL)
22193 as_bad_where (fixP->fx_file, fixP->fx_line,
22194 _("invalid constant (%lx) after fixup"),
22195 (unsigned long) value);
22199 newimm |= (temp & 0xfffff000);
22200 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22203 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22205 unsigned int highpart = 0;
22206 unsigned int newinsn = 0xe1a00000; /* nop. */
22208 if (fixP->fx_addsy)
22210 const char *msg = 0;
22212 if (! S_IS_DEFINED (fixP->fx_addsy))
22213 msg = _("undefined symbol %s used as an immediate value");
22214 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22215 msg = _("symbol %s is in a different section");
22216 else if (S_IS_WEAK (fixP->fx_addsy))
22217 msg = _("symbol %s is weak and may be overridden later");
22221 as_bad_where (fixP->fx_file, fixP->fx_line,
22222 msg, S_GET_NAME (fixP->fx_addsy));
22227 newimm = encode_arm_immediate (value);
22228 temp = md_chars_to_number (buf, INSN_SIZE);
22230 /* If the instruction will fail, see if we can fix things up by
22231 changing the opcode. */
22232 if (newimm == (unsigned int) FAIL
22233 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
22235 /* No ? OK - try using two ADD instructions to generate
22237 newimm = validate_immediate_twopart (value, & highpart);
22239 /* Yes - then make sure that the second instruction is
22241 if (newimm != (unsigned int) FAIL)
22243 /* Still No ? Try using a negated value. */
22244 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
22245 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
22246 /* Otherwise - give up. */
22249 as_bad_where (fixP->fx_file, fixP->fx_line,
22250 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22255 /* Replace the first operand in the 2nd instruction (which
22256 is the PC) with the destination register. We have
22257 already added in the PC in the first instruction and we
22258 do not want to do it again. */
22259 newinsn &= ~ 0xf0000;
22260 newinsn |= ((newinsn & 0x0f000) << 4);
22263 newimm |= (temp & 0xfffff000);
22264 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
22266 highpart |= (newinsn & 0xfffff000);
22267 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
22271 case BFD_RELOC_ARM_OFFSET_IMM:
22272 if (!fixP->fx_done && seg->use_rela_p)
22275 case BFD_RELOC_ARM_LITERAL:
22281 if (validate_offset_imm (value, 0) == FAIL)
22283 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
22284 as_bad_where (fixP->fx_file, fixP->fx_line,
22285 _("invalid literal constant: pool needs to be closer"));
22287 as_bad_where (fixP->fx_file, fixP->fx_line,
22288 _("bad immediate value for offset (%ld)"),
22293 newval = md_chars_to_number (buf, INSN_SIZE);
22295 newval &= 0xfffff000;
22298 newval &= 0xff7ff000;
22299 newval |= value | (sign ? INDEX_UP : 0);
22301 md_number_to_chars (buf, newval, INSN_SIZE);
22304 case BFD_RELOC_ARM_OFFSET_IMM8:
22305 case BFD_RELOC_ARM_HWLITERAL:
22311 if (validate_offset_imm (value, 1) == FAIL)
22313 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
22314 as_bad_where (fixP->fx_file, fixP->fx_line,
22315 _("invalid literal constant: pool needs to be closer"));
22317 as_bad_where (fixP->fx_file, fixP->fx_line,
22318 _("bad immediate value for 8-bit offset (%ld)"),
22323 newval = md_chars_to_number (buf, INSN_SIZE);
22325 newval &= 0xfffff0f0;
22328 newval &= 0xff7ff0f0;
22329 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
22331 md_number_to_chars (buf, newval, INSN_SIZE);
22334 case BFD_RELOC_ARM_T32_OFFSET_U8:
22335 if (value < 0 || value > 1020 || value % 4 != 0)
22336 as_bad_where (fixP->fx_file, fixP->fx_line,
22337 _("bad immediate value for offset (%ld)"), (long) value);
22340 newval = md_chars_to_number (buf+2, THUMB_SIZE);
22342 md_number_to_chars (buf+2, newval, THUMB_SIZE);
22345 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22346 /* This is a complicated relocation used for all varieties of Thumb32
22347 load/store instruction with immediate offset:
22349 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22350 *4, optional writeback(W)
22351 (doubleword load/store)
22353 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22354 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22355 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22356 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22357 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22359 Uppercase letters indicate bits that are already encoded at
22360 this point. Lowercase letters are our problem. For the
22361 second block of instructions, the secondary opcode nybble
22362 (bits 8..11) is present, and bit 23 is zero, even if this is
22363 a PC-relative operation. */
22364 newval = md_chars_to_number (buf, THUMB_SIZE);
22366 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
22368 if ((newval & 0xf0000000) == 0xe0000000)
22370 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22372 newval |= (1 << 23);
22375 if (value % 4 != 0)
22377 as_bad_where (fixP->fx_file, fixP->fx_line,
22378 _("offset not a multiple of 4"));
22384 as_bad_where (fixP->fx_file, fixP->fx_line,
22385 _("offset out of range"));
22390 else if ((newval & 0x000f0000) == 0x000f0000)
22392 /* PC-relative, 12-bit offset. */
22394 newval |= (1 << 23);
22399 as_bad_where (fixP->fx_file, fixP->fx_line,
22400 _("offset out of range"));
22405 else if ((newval & 0x00000100) == 0x00000100)
22407 /* Writeback: 8-bit, +/- offset. */
22409 newval |= (1 << 9);
22414 as_bad_where (fixP->fx_file, fixP->fx_line,
22415 _("offset out of range"));
22420 else if ((newval & 0x00000f00) == 0x00000e00)
22422 /* T-instruction: positive 8-bit offset. */
22423 if (value < 0 || value > 0xff)
22425 as_bad_where (fixP->fx_file, fixP->fx_line,
22426 _("offset out of range"));
22434 /* Positive 12-bit or negative 8-bit offset. */
22438 newval |= (1 << 23);
22448 as_bad_where (fixP->fx_file, fixP->fx_line,
22449 _("offset out of range"));
22456 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
22457 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
22460 case BFD_RELOC_ARM_SHIFT_IMM:
22461 newval = md_chars_to_number (buf, INSN_SIZE);
22462 if (((unsigned long) value) > 32
22464 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
22466 as_bad_where (fixP->fx_file, fixP->fx_line,
22467 _("shift expression is too large"));
22472 /* Shifts of zero must be done as lsl. */
22474 else if (value == 32)
22476 newval &= 0xfffff07f;
22477 newval |= (value & 0x1f) << 7;
22478 md_number_to_chars (buf, newval, INSN_SIZE);
22481 case BFD_RELOC_ARM_T32_IMMEDIATE:
22482 case BFD_RELOC_ARM_T32_ADD_IMM:
22483 case BFD_RELOC_ARM_T32_IMM12:
22484 case BFD_RELOC_ARM_T32_ADD_PC12:
22485 /* We claim that this fixup has been processed here,
22486 even if in fact we generate an error because we do
22487 not have a reloc for it, so tc_gen_reloc will reject it. */
22491 && ! S_IS_DEFINED (fixP->fx_addsy))
22493 as_bad_where (fixP->fx_file, fixP->fx_line,
22494 _("undefined symbol %s used as an immediate value"),
22495 S_GET_NAME (fixP->fx_addsy));
22499 newval = md_chars_to_number (buf, THUMB_SIZE);
22501 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
22504 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22505 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
22507 newimm = encode_thumb32_immediate (value);
22508 if (newimm == (unsigned int) FAIL)
22509 newimm = thumb32_negate_data_op (&newval, value);
22511 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
22512 && newimm == (unsigned int) FAIL)
22514 /* Turn add/sum into addw/subw. */
22515 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
22516 newval = (newval & 0xfeffffff) | 0x02000000;
22517 /* No flat 12-bit imm encoding for addsw/subsw. */
22518 if ((newval & 0x00100000) == 0)
22520 /* 12 bit immediate for addw/subw. */
22524 newval ^= 0x00a00000;
22527 newimm = (unsigned int) FAIL;
22533 if (newimm == (unsigned int)FAIL)
22535 as_bad_where (fixP->fx_file, fixP->fx_line,
22536 _("invalid constant (%lx) after fixup"),
22537 (unsigned long) value);
22541 newval |= (newimm & 0x800) << 15;
22542 newval |= (newimm & 0x700) << 4;
22543 newval |= (newimm & 0x0ff);
22545 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
22546 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
22549 case BFD_RELOC_ARM_SMC:
22550 if (((unsigned long) value) > 0xffff)
22551 as_bad_where (fixP->fx_file, fixP->fx_line,
22552 _("invalid smc expression"));
22553 newval = md_chars_to_number (buf, INSN_SIZE);
22554 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22555 md_number_to_chars (buf, newval, INSN_SIZE);
22558 case BFD_RELOC_ARM_HVC:
22559 if (((unsigned long) value) > 0xffff)
22560 as_bad_where (fixP->fx_file, fixP->fx_line,
22561 _("invalid hvc expression"));
22562 newval = md_chars_to_number (buf, INSN_SIZE);
22563 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22564 md_number_to_chars (buf, newval, INSN_SIZE);
22567 case BFD_RELOC_ARM_SWI:
22568 if (fixP->tc_fix_data != 0)
22570 if (((unsigned long) value) > 0xff)
22571 as_bad_where (fixP->fx_file, fixP->fx_line,
22572 _("invalid swi expression"));
22573 newval = md_chars_to_number (buf, THUMB_SIZE);
22575 md_number_to_chars (buf, newval, THUMB_SIZE);
22579 if (((unsigned long) value) > 0x00ffffff)
22580 as_bad_where (fixP->fx_file, fixP->fx_line,
22581 _("invalid swi expression"));
22582 newval = md_chars_to_number (buf, INSN_SIZE);
22584 md_number_to_chars (buf, newval, INSN_SIZE);
22588 case BFD_RELOC_ARM_MULTI:
22589 if (((unsigned long) value) > 0xffff)
22590 as_bad_where (fixP->fx_file, fixP->fx_line,
22591 _("invalid expression in load/store multiple"));
22592 newval = value | md_chars_to_number (buf, INSN_SIZE);
22593 md_number_to_chars (buf, newval, INSN_SIZE);
22597 case BFD_RELOC_ARM_PCREL_CALL:
22599 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22601 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22602 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22603 && THUMB_IS_FUNC (fixP->fx_addsy))
22604 /* Flip the bl to blx. This is a simple flip
22605 bit here because we generate PCREL_CALL for
22606 unconditional bls. */
22608 newval = md_chars_to_number (buf, INSN_SIZE);
22609 newval = newval | 0x10000000;
22610 md_number_to_chars (buf, newval, INSN_SIZE);
22616 goto arm_branch_common;
22618 case BFD_RELOC_ARM_PCREL_JUMP:
22619 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22621 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22622 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22623 && THUMB_IS_FUNC (fixP->fx_addsy))
22625 /* This would map to a bl<cond>, b<cond>,
22626 b<always> to a Thumb function. We
22627 need to force a relocation for this particular
22629 newval = md_chars_to_number (buf, INSN_SIZE);
22633 case BFD_RELOC_ARM_PLT32:
22635 case BFD_RELOC_ARM_PCREL_BRANCH:
22637 goto arm_branch_common;
22639 case BFD_RELOC_ARM_PCREL_BLX:
22642 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22644 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22645 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22646 && ARM_IS_FUNC (fixP->fx_addsy))
22648 /* Flip the blx to a bl and warn. */
22649 const char *name = S_GET_NAME (fixP->fx_addsy);
22650 newval = 0xeb000000;
22651 as_warn_where (fixP->fx_file, fixP->fx_line,
22652 _("blx to '%s' an ARM ISA state function changed to bl"),
22654 md_number_to_chars (buf, newval, INSN_SIZE);
22660 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22661 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
22665 /* We are going to store value (shifted right by two) in the
22666 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22667 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22668 also be be clear. */
22670 as_bad_where (fixP->fx_file, fixP->fx_line,
22671 _("misaligned branch destination"));
22672 if ((value & (offsetT)0xfe000000) != (offsetT)0
22673 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
22674 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22676 if (fixP->fx_done || !seg->use_rela_p)
22678 newval = md_chars_to_number (buf, INSN_SIZE);
22679 newval |= (value >> 2) & 0x00ffffff;
22680 /* Set the H bit on BLX instructions. */
22684 newval |= 0x01000000;
22686 newval &= ~0x01000000;
22688 md_number_to_chars (buf, newval, INSN_SIZE);
22692 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22693 /* CBZ can only branch forward. */
22695 /* Attempts to use CBZ to branch to the next instruction
22696 (which, strictly speaking, are prohibited) will be turned into
22699 FIXME: It may be better to remove the instruction completely and
22700 perform relaxation. */
22703 newval = md_chars_to_number (buf, THUMB_SIZE);
22704 newval = 0xbf00; /* NOP encoding T1 */
22705 md_number_to_chars (buf, newval, THUMB_SIZE);
22710 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22712 if (fixP->fx_done || !seg->use_rela_p)
22714 newval = md_chars_to_number (buf, THUMB_SIZE);
22715 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22716 md_number_to_chars (buf, newval, THUMB_SIZE);
22721 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
22722 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
22723 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22725 if (fixP->fx_done || !seg->use_rela_p)
22727 newval = md_chars_to_number (buf, THUMB_SIZE);
22728 newval |= (value & 0x1ff) >> 1;
22729 md_number_to_chars (buf, newval, THUMB_SIZE);
22733 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
22734 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
22735 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22737 if (fixP->fx_done || !seg->use_rela_p)
22739 newval = md_chars_to_number (buf, THUMB_SIZE);
22740 newval |= (value & 0xfff) >> 1;
22741 md_number_to_chars (buf, newval, THUMB_SIZE);
22745 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22747 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22748 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22749 && ARM_IS_FUNC (fixP->fx_addsy)
22750 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22752 /* Force a relocation for a branch 20 bits wide. */
22755 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
22756 as_bad_where (fixP->fx_file, fixP->fx_line,
22757 _("conditional branch out of range"));
22759 if (fixP->fx_done || !seg->use_rela_p)
22762 addressT S, J1, J2, lo, hi;
22764 S = (value & 0x00100000) >> 20;
22765 J2 = (value & 0x00080000) >> 19;
22766 J1 = (value & 0x00040000) >> 18;
22767 hi = (value & 0x0003f000) >> 12;
22768 lo = (value & 0x00000ffe) >> 1;
22770 newval = md_chars_to_number (buf, THUMB_SIZE);
22771 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22772 newval |= (S << 10) | hi;
22773 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22774 md_number_to_chars (buf, newval, THUMB_SIZE);
22775 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22779 case BFD_RELOC_THUMB_PCREL_BLX:
22780 /* If there is a blx from a thumb state function to
22781 another thumb function flip this to a bl and warn
22785 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22786 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22787 && THUMB_IS_FUNC (fixP->fx_addsy))
22789 const char *name = S_GET_NAME (fixP->fx_addsy);
22790 as_warn_where (fixP->fx_file, fixP->fx_line,
22791 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22793 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22794 newval = newval | 0x1000;
22795 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22796 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22801 goto thumb_bl_common;
22803 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22804 /* A bl from Thumb state ISA to an internal ARM state function
22805 is converted to a blx. */
22807 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22808 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
22809 && ARM_IS_FUNC (fixP->fx_addsy)
22810 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22812 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22813 newval = newval & ~0x1000;
22814 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22815 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22821 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22822 /* For a BLX instruction, make sure that the relocation is rounded up
22823 to a word boundary. This follows the semantics of the instruction
22824 which specifies that bit 1 of the target address will come from bit
22825 1 of the base address. */
22826 value = (value + 3) & ~ 3;
22829 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22830 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22831 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22834 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22836 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22837 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22838 else if ((value & ~0x1ffffff)
22839 && ((value & ~0x1ffffff) != ~0x1ffffff))
22840 as_bad_where (fixP->fx_file, fixP->fx_line,
22841 _("Thumb2 branch out of range"));
22844 if (fixP->fx_done || !seg->use_rela_p)
22845 encode_thumb2_b_bl_offset (buf, value);
22849 case BFD_RELOC_THUMB_PCREL_BRANCH25:
22850 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22851 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22853 if (fixP->fx_done || !seg->use_rela_p)
22854 encode_thumb2_b_bl_offset (buf, value);
22859 if (fixP->fx_done || !seg->use_rela_p)
22864 if (fixP->fx_done || !seg->use_rela_p)
22865 md_number_to_chars (buf, value, 2);
22869 case BFD_RELOC_ARM_TLS_CALL:
22870 case BFD_RELOC_ARM_THM_TLS_CALL:
22871 case BFD_RELOC_ARM_TLS_DESCSEQ:
22872 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22873 case BFD_RELOC_ARM_TLS_GOTDESC:
22874 case BFD_RELOC_ARM_TLS_GD32:
22875 case BFD_RELOC_ARM_TLS_LE32:
22876 case BFD_RELOC_ARM_TLS_IE32:
22877 case BFD_RELOC_ARM_TLS_LDM32:
22878 case BFD_RELOC_ARM_TLS_LDO32:
22879 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22882 case BFD_RELOC_ARM_GOT32:
22883 case BFD_RELOC_ARM_GOTOFF:
22886 case BFD_RELOC_ARM_GOT_PREL:
22887 if (fixP->fx_done || !seg->use_rela_p)
22888 md_number_to_chars (buf, value, 4);
22891 case BFD_RELOC_ARM_TARGET2:
22892 /* TARGET2 is not partial-inplace, so we need to write the
22893 addend here for REL targets, because it won't be written out
22894 during reloc processing later. */
22895 if (fixP->fx_done || !seg->use_rela_p)
22896 md_number_to_chars (buf, fixP->fx_offset, 4);
22900 case BFD_RELOC_RVA:
22902 case BFD_RELOC_ARM_TARGET1:
22903 case BFD_RELOC_ARM_ROSEGREL32:
22904 case BFD_RELOC_ARM_SBREL32:
22905 case BFD_RELOC_32_PCREL:
22907 case BFD_RELOC_32_SECREL:
22909 if (fixP->fx_done || !seg->use_rela_p)
22911 /* For WinCE we only do this for pcrel fixups. */
22912 if (fixP->fx_done || fixP->fx_pcrel)
22914 md_number_to_chars (buf, value, 4);
22918 case BFD_RELOC_ARM_PREL31:
22919 if (fixP->fx_done || !seg->use_rela_p)
22921 newval = md_chars_to_number (buf, 4) & 0x80000000;
22922 if ((value ^ (value >> 1)) & 0x40000000)
22924 as_bad_where (fixP->fx_file, fixP->fx_line,
22925 _("rel31 relocation overflow"));
22927 newval |= value & 0x7fffffff;
22928 md_number_to_chars (buf, newval, 4);
22933 case BFD_RELOC_ARM_CP_OFF_IMM:
22934 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
22935 if (value < -1023 || value > 1023 || (value & 3))
22936 as_bad_where (fixP->fx_file, fixP->fx_line,
22937 _("co-processor offset out of range"));
22942 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22943 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22944 newval = md_chars_to_number (buf, INSN_SIZE);
22946 newval = get_thumb32_insn (buf);
22948 newval &= 0xffffff00;
22951 newval &= 0xff7fff00;
22952 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22954 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22955 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22956 md_number_to_chars (buf, newval, INSN_SIZE);
22958 put_thumb32_insn (buf, newval);
22961 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
22962 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
22963 if (value < -255 || value > 255)
22964 as_bad_where (fixP->fx_file, fixP->fx_line,
22965 _("co-processor offset out of range"));
22967 goto cp_off_common;
22969 case BFD_RELOC_ARM_THUMB_OFFSET:
22970 newval = md_chars_to_number (buf, THUMB_SIZE);
22971 /* Exactly what ranges, and where the offset is inserted depends
22972 on the type of instruction, we can establish this from the
22974 switch (newval >> 12)
22976 case 4: /* PC load. */
22977 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22978 forced to zero for these loads; md_pcrel_from has already
22979 compensated for this. */
22981 as_bad_where (fixP->fx_file, fixP->fx_line,
22982 _("invalid offset, target not word aligned (0x%08lX)"),
22983 (((unsigned long) fixP->fx_frag->fr_address
22984 + (unsigned long) fixP->fx_where) & ~3)
22985 + (unsigned long) value);
22987 if (value & ~0x3fc)
22988 as_bad_where (fixP->fx_file, fixP->fx_line,
22989 _("invalid offset, value too big (0x%08lX)"),
22992 newval |= value >> 2;
22995 case 9: /* SP load/store. */
22996 if (value & ~0x3fc)
22997 as_bad_where (fixP->fx_file, fixP->fx_line,
22998 _("invalid offset, value too big (0x%08lX)"),
23000 newval |= value >> 2;
23003 case 6: /* Word load/store. */
23005 as_bad_where (fixP->fx_file, fixP->fx_line,
23006 _("invalid offset, value too big (0x%08lX)"),
23008 newval |= value << 4; /* 6 - 2. */
23011 case 7: /* Byte load/store. */
23013 as_bad_where (fixP->fx_file, fixP->fx_line,
23014 _("invalid offset, value too big (0x%08lX)"),
23016 newval |= value << 6;
23019 case 8: /* Halfword load/store. */
23021 as_bad_where (fixP->fx_file, fixP->fx_line,
23022 _("invalid offset, value too big (0x%08lX)"),
23024 newval |= value << 5; /* 6 - 1. */
23028 as_bad_where (fixP->fx_file, fixP->fx_line,
23029 "Unable to process relocation for thumb opcode: %lx",
23030 (unsigned long) newval);
23033 md_number_to_chars (buf, newval, THUMB_SIZE);
23036 case BFD_RELOC_ARM_THUMB_ADD:
23037 /* This is a complicated relocation, since we use it for all of
23038 the following immediate relocations:
23042 9bit ADD/SUB SP word-aligned
23043 10bit ADD PC/SP word-aligned
23045 The type of instruction being processed is encoded in the
23052 newval = md_chars_to_number (buf, THUMB_SIZE);
23054 int rd = (newval >> 4) & 0xf;
23055 int rs = newval & 0xf;
23056 int subtract = !!(newval & 0x8000);
23058 /* Check for HI regs, only very restricted cases allowed:
23059 Adjusting SP, and using PC or SP to get an address. */
23060 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
23061 || (rs > 7 && rs != REG_SP && rs != REG_PC))
23062 as_bad_where (fixP->fx_file, fixP->fx_line,
23063 _("invalid Hi register with immediate"));
23065 /* If value is negative, choose the opposite instruction. */
23069 subtract = !subtract;
23071 as_bad_where (fixP->fx_file, fixP->fx_line,
23072 _("immediate value out of range"));
23077 if (value & ~0x1fc)
23078 as_bad_where (fixP->fx_file, fixP->fx_line,
23079 _("invalid immediate for stack address calculation"));
23080 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
23081 newval |= value >> 2;
23083 else if (rs == REG_PC || rs == REG_SP)
23085 if (subtract || value & ~0x3fc)
23086 as_bad_where (fixP->fx_file, fixP->fx_line,
23087 _("invalid immediate for address calculation (value = 0x%08lX)"),
23088 (unsigned long) value);
23089 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
23091 newval |= value >> 2;
23096 as_bad_where (fixP->fx_file, fixP->fx_line,
23097 _("immediate value out of range"));
23098 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
23099 newval |= (rd << 8) | value;
23104 as_bad_where (fixP->fx_file, fixP->fx_line,
23105 _("immediate value out of range"));
23106 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
23107 newval |= rd | (rs << 3) | (value << 6);
23110 md_number_to_chars (buf, newval, THUMB_SIZE);
23113 case BFD_RELOC_ARM_THUMB_IMM:
23114 newval = md_chars_to_number (buf, THUMB_SIZE);
23115 if (value < 0 || value > 255)
23116 as_bad_where (fixP->fx_file, fixP->fx_line,
23117 _("invalid immediate: %ld is out of range"),
23120 md_number_to_chars (buf, newval, THUMB_SIZE);
23123 case BFD_RELOC_ARM_THUMB_SHIFT:
23124 /* 5bit shift value (0..32). LSL cannot take 32. */
23125 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
23126 temp = newval & 0xf800;
23127 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
23128 as_bad_where (fixP->fx_file, fixP->fx_line,
23129 _("invalid shift value: %ld"), (long) value);
23130 /* Shifts of zero must be encoded as LSL. */
23132 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
23133 /* Shifts of 32 are encoded as zero. */
23134 else if (value == 32)
23136 newval |= value << 6;
23137 md_number_to_chars (buf, newval, THUMB_SIZE);
23140 case BFD_RELOC_VTABLE_INHERIT:
23141 case BFD_RELOC_VTABLE_ENTRY:
23145 case BFD_RELOC_ARM_MOVW:
23146 case BFD_RELOC_ARM_MOVT:
23147 case BFD_RELOC_ARM_THUMB_MOVW:
23148 case BFD_RELOC_ARM_THUMB_MOVT:
23149 if (fixP->fx_done || !seg->use_rela_p)
23151 /* REL format relocations are limited to a 16-bit addend. */
23152 if (!fixP->fx_done)
23154 if (value < -0x8000 || value > 0x7fff)
23155 as_bad_where (fixP->fx_file, fixP->fx_line,
23156 _("offset out of range"));
23158 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23159 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23164 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23165 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
23167 newval = get_thumb32_insn (buf);
23168 newval &= 0xfbf08f00;
23169 newval |= (value & 0xf000) << 4;
23170 newval |= (value & 0x0800) << 15;
23171 newval |= (value & 0x0700) << 4;
23172 newval |= (value & 0x00ff);
23173 put_thumb32_insn (buf, newval);
23177 newval = md_chars_to_number (buf, 4);
23178 newval &= 0xfff0f000;
23179 newval |= value & 0x0fff;
23180 newval |= (value & 0xf000) << 4;
23181 md_number_to_chars (buf, newval, 4);
23186 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23187 case BFD_RELOC_ARM_ALU_PC_G0:
23188 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23189 case BFD_RELOC_ARM_ALU_PC_G1:
23190 case BFD_RELOC_ARM_ALU_PC_G2:
23191 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23192 case BFD_RELOC_ARM_ALU_SB_G0:
23193 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23194 case BFD_RELOC_ARM_ALU_SB_G1:
23195 case BFD_RELOC_ARM_ALU_SB_G2:
23196 gas_assert (!fixP->fx_done);
23197 if (!seg->use_rela_p)
23200 bfd_vma encoded_addend;
23201 bfd_vma addend_abs = abs (value);
23203 /* Check that the absolute value of the addend can be
23204 expressed as an 8-bit constant plus a rotation. */
23205 encoded_addend = encode_arm_immediate (addend_abs);
23206 if (encoded_addend == (unsigned int) FAIL)
23207 as_bad_where (fixP->fx_file, fixP->fx_line,
23208 _("the offset 0x%08lX is not representable"),
23209 (unsigned long) addend_abs);
23211 /* Extract the instruction. */
23212 insn = md_chars_to_number (buf, INSN_SIZE);
23214 /* If the addend is positive, use an ADD instruction.
23215 Otherwise use a SUB. Take care not to destroy the S bit. */
23216 insn &= 0xff1fffff;
23222 /* Place the encoded addend into the first 12 bits of the
23224 insn &= 0xfffff000;
23225 insn |= encoded_addend;
23227 /* Update the instruction. */
23228 md_number_to_chars (buf, insn, INSN_SIZE);
23232 case BFD_RELOC_ARM_LDR_PC_G0:
23233 case BFD_RELOC_ARM_LDR_PC_G1:
23234 case BFD_RELOC_ARM_LDR_PC_G2:
23235 case BFD_RELOC_ARM_LDR_SB_G0:
23236 case BFD_RELOC_ARM_LDR_SB_G1:
23237 case BFD_RELOC_ARM_LDR_SB_G2:
23238 gas_assert (!fixP->fx_done);
23239 if (!seg->use_rela_p)
23242 bfd_vma addend_abs = abs (value);
23244 /* Check that the absolute value of the addend can be
23245 encoded in 12 bits. */
23246 if (addend_abs >= 0x1000)
23247 as_bad_where (fixP->fx_file, fixP->fx_line,
23248 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23249 (unsigned long) addend_abs);
23251 /* Extract the instruction. */
23252 insn = md_chars_to_number (buf, INSN_SIZE);
23254 /* If the addend is negative, clear bit 23 of the instruction.
23255 Otherwise set it. */
23257 insn &= ~(1 << 23);
23261 /* Place the absolute value of the addend into the first 12 bits
23262 of the instruction. */
23263 insn &= 0xfffff000;
23264 insn |= addend_abs;
23266 /* Update the instruction. */
23267 md_number_to_chars (buf, insn, INSN_SIZE);
23271 case BFD_RELOC_ARM_LDRS_PC_G0:
23272 case BFD_RELOC_ARM_LDRS_PC_G1:
23273 case BFD_RELOC_ARM_LDRS_PC_G2:
23274 case BFD_RELOC_ARM_LDRS_SB_G0:
23275 case BFD_RELOC_ARM_LDRS_SB_G1:
23276 case BFD_RELOC_ARM_LDRS_SB_G2:
23277 gas_assert (!fixP->fx_done);
23278 if (!seg->use_rela_p)
23281 bfd_vma addend_abs = abs (value);
23283 /* Check that the absolute value of the addend can be
23284 encoded in 8 bits. */
23285 if (addend_abs >= 0x100)
23286 as_bad_where (fixP->fx_file, fixP->fx_line,
23287 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23288 (unsigned long) addend_abs);
23290 /* Extract the instruction. */
23291 insn = md_chars_to_number (buf, INSN_SIZE);
23293 /* If the addend is negative, clear bit 23 of the instruction.
23294 Otherwise set it. */
23296 insn &= ~(1 << 23);
23300 /* Place the first four bits of the absolute value of the addend
23301 into the first 4 bits of the instruction, and the remaining
23302 four into bits 8 .. 11. */
23303 insn &= 0xfffff0f0;
23304 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
23306 /* Update the instruction. */
23307 md_number_to_chars (buf, insn, INSN_SIZE);
23311 case BFD_RELOC_ARM_LDC_PC_G0:
23312 case BFD_RELOC_ARM_LDC_PC_G1:
23313 case BFD_RELOC_ARM_LDC_PC_G2:
23314 case BFD_RELOC_ARM_LDC_SB_G0:
23315 case BFD_RELOC_ARM_LDC_SB_G1:
23316 case BFD_RELOC_ARM_LDC_SB_G2:
23317 gas_assert (!fixP->fx_done);
23318 if (!seg->use_rela_p)
23321 bfd_vma addend_abs = abs (value);
23323 /* Check that the absolute value of the addend is a multiple of
23324 four and, when divided by four, fits in 8 bits. */
23325 if (addend_abs & 0x3)
23326 as_bad_where (fixP->fx_file, fixP->fx_line,
23327 _("bad offset 0x%08lX (must be word-aligned)"),
23328 (unsigned long) addend_abs);
23330 if ((addend_abs >> 2) > 0xff)
23331 as_bad_where (fixP->fx_file, fixP->fx_line,
23332 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23333 (unsigned long) addend_abs);
23335 /* Extract the instruction. */
23336 insn = md_chars_to_number (buf, INSN_SIZE);
23338 /* If the addend is negative, clear bit 23 of the instruction.
23339 Otherwise set it. */
23341 insn &= ~(1 << 23);
23345 /* Place the addend (divided by four) into the first eight
23346 bits of the instruction. */
23347 insn &= 0xfffffff0;
23348 insn |= addend_abs >> 2;
23350 /* Update the instruction. */
23351 md_number_to_chars (buf, insn, INSN_SIZE);
23355 case BFD_RELOC_ARM_V4BX:
23356 /* This will need to go in the object file. */
23360 case BFD_RELOC_UNUSED:
23362 as_bad_where (fixP->fx_file, fixP->fx_line,
23363 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
23367 /* Translate internal representation of relocation info to BFD target
23371 tc_gen_reloc (asection *section, fixS *fixp)
23374 bfd_reloc_code_real_type code;
23376 reloc = (arelent *) xmalloc (sizeof (arelent));
23378 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
23379 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
23380 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
23382 if (fixp->fx_pcrel)
23384 if (section->use_rela_p)
23385 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
23387 fixp->fx_offset = reloc->address;
23389 reloc->addend = fixp->fx_offset;
23391 switch (fixp->fx_r_type)
23394 if (fixp->fx_pcrel)
23396 code = BFD_RELOC_8_PCREL;
23401 if (fixp->fx_pcrel)
23403 code = BFD_RELOC_16_PCREL;
23408 if (fixp->fx_pcrel)
23410 code = BFD_RELOC_32_PCREL;
23414 case BFD_RELOC_ARM_MOVW:
23415 if (fixp->fx_pcrel)
23417 code = BFD_RELOC_ARM_MOVW_PCREL;
23421 case BFD_RELOC_ARM_MOVT:
23422 if (fixp->fx_pcrel)
23424 code = BFD_RELOC_ARM_MOVT_PCREL;
23428 case BFD_RELOC_ARM_THUMB_MOVW:
23429 if (fixp->fx_pcrel)
23431 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
23435 case BFD_RELOC_ARM_THUMB_MOVT:
23436 if (fixp->fx_pcrel)
23438 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
23442 case BFD_RELOC_NONE:
23443 case BFD_RELOC_ARM_PCREL_BRANCH:
23444 case BFD_RELOC_ARM_PCREL_BLX:
23445 case BFD_RELOC_RVA:
23446 case BFD_RELOC_THUMB_PCREL_BRANCH7:
23447 case BFD_RELOC_THUMB_PCREL_BRANCH9:
23448 case BFD_RELOC_THUMB_PCREL_BRANCH12:
23449 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23450 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23451 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23452 case BFD_RELOC_VTABLE_ENTRY:
23453 case BFD_RELOC_VTABLE_INHERIT:
23455 case BFD_RELOC_32_SECREL:
23457 code = fixp->fx_r_type;
23460 case BFD_RELOC_THUMB_PCREL_BLX:
23462 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23463 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
23466 code = BFD_RELOC_THUMB_PCREL_BLX;
23469 case BFD_RELOC_ARM_LITERAL:
23470 case BFD_RELOC_ARM_HWLITERAL:
23471 /* If this is called then the a literal has
23472 been referenced across a section boundary. */
23473 as_bad_where (fixp->fx_file, fixp->fx_line,
23474 _("literal referenced across section boundary"));
23478 case BFD_RELOC_ARM_TLS_CALL:
23479 case BFD_RELOC_ARM_THM_TLS_CALL:
23480 case BFD_RELOC_ARM_TLS_DESCSEQ:
23481 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
23482 case BFD_RELOC_ARM_GOT32:
23483 case BFD_RELOC_ARM_GOTOFF:
23484 case BFD_RELOC_ARM_GOT_PREL:
23485 case BFD_RELOC_ARM_PLT32:
23486 case BFD_RELOC_ARM_TARGET1:
23487 case BFD_RELOC_ARM_ROSEGREL32:
23488 case BFD_RELOC_ARM_SBREL32:
23489 case BFD_RELOC_ARM_PREL31:
23490 case BFD_RELOC_ARM_TARGET2:
23491 case BFD_RELOC_ARM_TLS_LE32:
23492 case BFD_RELOC_ARM_TLS_LDO32:
23493 case BFD_RELOC_ARM_PCREL_CALL:
23494 case BFD_RELOC_ARM_PCREL_JUMP:
23495 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23496 case BFD_RELOC_ARM_ALU_PC_G0:
23497 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23498 case BFD_RELOC_ARM_ALU_PC_G1:
23499 case BFD_RELOC_ARM_ALU_PC_G2:
23500 case BFD_RELOC_ARM_LDR_PC_G0:
23501 case BFD_RELOC_ARM_LDR_PC_G1:
23502 case BFD_RELOC_ARM_LDR_PC_G2:
23503 case BFD_RELOC_ARM_LDRS_PC_G0:
23504 case BFD_RELOC_ARM_LDRS_PC_G1:
23505 case BFD_RELOC_ARM_LDRS_PC_G2:
23506 case BFD_RELOC_ARM_LDC_PC_G0:
23507 case BFD_RELOC_ARM_LDC_PC_G1:
23508 case BFD_RELOC_ARM_LDC_PC_G2:
23509 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23510 case BFD_RELOC_ARM_ALU_SB_G0:
23511 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23512 case BFD_RELOC_ARM_ALU_SB_G1:
23513 case BFD_RELOC_ARM_ALU_SB_G2:
23514 case BFD_RELOC_ARM_LDR_SB_G0:
23515 case BFD_RELOC_ARM_LDR_SB_G1:
23516 case BFD_RELOC_ARM_LDR_SB_G2:
23517 case BFD_RELOC_ARM_LDRS_SB_G0:
23518 case BFD_RELOC_ARM_LDRS_SB_G1:
23519 case BFD_RELOC_ARM_LDRS_SB_G2:
23520 case BFD_RELOC_ARM_LDC_SB_G0:
23521 case BFD_RELOC_ARM_LDC_SB_G1:
23522 case BFD_RELOC_ARM_LDC_SB_G2:
23523 case BFD_RELOC_ARM_V4BX:
23524 code = fixp->fx_r_type;
23527 case BFD_RELOC_ARM_TLS_GOTDESC:
23528 case BFD_RELOC_ARM_TLS_GD32:
23529 case BFD_RELOC_ARM_TLS_IE32:
23530 case BFD_RELOC_ARM_TLS_LDM32:
23531 /* BFD will include the symbol's address in the addend.
23532 But we don't want that, so subtract it out again here. */
23533 if (!S_IS_COMMON (fixp->fx_addsy))
23534 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
23535 code = fixp->fx_r_type;
23539 case BFD_RELOC_ARM_IMMEDIATE:
23540 as_bad_where (fixp->fx_file, fixp->fx_line,
23541 _("internal relocation (type: IMMEDIATE) not fixed up"));
23544 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
23545 as_bad_where (fixp->fx_file, fixp->fx_line,
23546 _("ADRL used for a symbol not defined in the same file"));
23549 case BFD_RELOC_ARM_OFFSET_IMM:
23550 if (section->use_rela_p)
23552 code = fixp->fx_r_type;
23556 if (fixp->fx_addsy != NULL
23557 && !S_IS_DEFINED (fixp->fx_addsy)
23558 && S_IS_LOCAL (fixp->fx_addsy))
23560 as_bad_where (fixp->fx_file, fixp->fx_line,
23561 _("undefined local label `%s'"),
23562 S_GET_NAME (fixp->fx_addsy));
23566 as_bad_where (fixp->fx_file, fixp->fx_line,
23567 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23574 switch (fixp->fx_r_type)
23576 case BFD_RELOC_NONE: type = "NONE"; break;
23577 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
23578 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
23579 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
23580 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
23581 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
23582 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
23583 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
23584 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
23585 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
23586 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
23587 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
23588 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
23589 default: type = _("<unknown>"); break;
23591 as_bad_where (fixp->fx_file, fixp->fx_line,
23592 _("cannot represent %s relocation in this object file format"),
23599 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
23601 && fixp->fx_addsy == GOT_symbol)
23603 code = BFD_RELOC_ARM_GOTPC;
23604 reloc->addend = fixp->fx_offset = reloc->address;
23608 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
23610 if (reloc->howto == NULL)
23612 as_bad_where (fixp->fx_file, fixp->fx_line,
23613 _("cannot represent %s relocation in this object file format"),
23614 bfd_get_reloc_code_name (code));
23618 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23619 vtable entry to be used in the relocation's section offset. */
23620 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23621 reloc->address = fixp->fx_offset;
23626 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23629 cons_fix_new_arm (fragS * frag,
23633 bfd_reloc_code_real_type reloc)
23638 FIXME: @@ Should look at CPU word size. */
23642 reloc = BFD_RELOC_8;
23645 reloc = BFD_RELOC_16;
23649 reloc = BFD_RELOC_32;
23652 reloc = BFD_RELOC_64;
23657 if (exp->X_op == O_secrel)
23659 exp->X_op = O_symbol;
23660 reloc = BFD_RELOC_32_SECREL;
23664 fix_new_exp (frag, where, size, exp, pcrel, reloc);
23667 #if defined (OBJ_COFF)
23669 arm_validate_fix (fixS * fixP)
23671 /* If the destination of the branch is a defined symbol which does not have
23672 the THUMB_FUNC attribute, then we must be calling a function which has
23673 the (interfacearm) attribute. We look for the Thumb entry point to that
23674 function and change the branch to refer to that function instead. */
23675 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23676 && fixP->fx_addsy != NULL
23677 && S_IS_DEFINED (fixP->fx_addsy)
23678 && ! THUMB_IS_FUNC (fixP->fx_addsy))
23680 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
23687 arm_force_relocation (struct fix * fixp)
23689 #if defined (OBJ_COFF) && defined (TE_PE)
23690 if (fixp->fx_r_type == BFD_RELOC_RVA)
23694 /* In case we have a call or a branch to a function in ARM ISA mode from
23695 a thumb function or vice-versa force the relocation. These relocations
23696 are cleared off for some cores that might have blx and simple transformations
23700 switch (fixp->fx_r_type)
23702 case BFD_RELOC_ARM_PCREL_JUMP:
23703 case BFD_RELOC_ARM_PCREL_CALL:
23704 case BFD_RELOC_THUMB_PCREL_BLX:
23705 if (THUMB_IS_FUNC (fixp->fx_addsy))
23709 case BFD_RELOC_ARM_PCREL_BLX:
23710 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23711 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23712 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23713 if (ARM_IS_FUNC (fixp->fx_addsy))
23722 /* Resolve these relocations even if the symbol is extern or weak.
23723 Technically this is probably wrong due to symbol preemption.
23724 In practice these relocations do not have enough range to be useful
23725 at dynamic link time, and some code (e.g. in the Linux kernel)
23726 expects these references to be resolved. */
23727 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23728 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
23729 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
23730 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
23731 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23732 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23733 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
23734 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
23735 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23736 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
23737 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23738 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23739 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23740 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
23743 /* Always leave these relocations for the linker. */
23744 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23745 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23746 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23749 /* Always generate relocations against function symbols. */
23750 if (fixp->fx_r_type == BFD_RELOC_32
23752 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23755 return generic_force_reloc (fixp);
23758 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23759 /* Relocations against function names must be left unadjusted,
23760 so that the linker can use this information to generate interworking
23761 stubs. The MIPS version of this function
23762 also prevents relocations that are mips-16 specific, but I do not
23763 know why it does this.
23766 There is one other problem that ought to be addressed here, but
23767 which currently is not: Taking the address of a label (rather
23768 than a function) and then later jumping to that address. Such
23769 addresses also ought to have their bottom bit set (assuming that
23770 they reside in Thumb code), but at the moment they will not. */
23773 arm_fix_adjustable (fixS * fixP)
23775 if (fixP->fx_addsy == NULL)
23778 /* Preserve relocations against symbols with function type. */
23779 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
23782 if (THUMB_IS_FUNC (fixP->fx_addsy)
23783 && fixP->fx_subsy == NULL)
23786 /* We need the symbol name for the VTABLE entries. */
23787 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23788 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23791 /* Don't allow symbols to be discarded on GOT related relocs. */
23792 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23793 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23794 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23795 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23796 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23797 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23798 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23799 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
23800 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23801 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23802 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23803 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23804 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
23805 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
23808 /* Similarly for group relocations. */
23809 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23810 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23811 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23814 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23815 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23816 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23817 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23818 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23819 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23820 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23821 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23822 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
23827 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23832 elf32_arm_target_format (void)
23835 return (target_big_endian
23836 ? "elf32-bigarm-symbian"
23837 : "elf32-littlearm-symbian");
23838 #elif defined (TE_VXWORKS)
23839 return (target_big_endian
23840 ? "elf32-bigarm-vxworks"
23841 : "elf32-littlearm-vxworks");
23842 #elif defined (TE_NACL)
23843 return (target_big_endian
23844 ? "elf32-bigarm-nacl"
23845 : "elf32-littlearm-nacl");
23847 if (target_big_endian)
23848 return "elf32-bigarm";
23850 return "elf32-littlearm";
23855 armelf_frob_symbol (symbolS * symp,
23858 elf_frob_symbol (symp, puntp);
23862 /* MD interface: Finalization. */
23867 literal_pool * pool;
23869 /* Ensure that all the IT blocks are properly closed. */
23870 check_it_blocks_finished ();
23872 for (pool = list_of_pools; pool; pool = pool->next)
23874 /* Put it at the end of the relevant section. */
23875 subseg_set (pool->section, pool->sub_section);
23877 arm_elf_change_section ();
23884 /* Remove any excess mapping symbols generated for alignment frags in
23885 SEC. We may have created a mapping symbol before a zero byte
23886 alignment; remove it if there's a mapping symbol after the
23889 check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23890 void *dummy ATTRIBUTE_UNUSED)
23892 segment_info_type *seginfo = seg_info (sec);
23895 if (seginfo == NULL || seginfo->frchainP == NULL)
23898 for (fragp = seginfo->frchainP->frch_root;
23900 fragp = fragp->fr_next)
23902 symbolS *sym = fragp->tc_frag_data.last_map;
23903 fragS *next = fragp->fr_next;
23905 /* Variable-sized frags have been converted to fixed size by
23906 this point. But if this was variable-sized to start with,
23907 there will be a fixed-size frag after it. So don't handle
23909 if (sym == NULL || next == NULL)
23912 if (S_GET_VALUE (sym) < next->fr_address)
23913 /* Not at the end of this frag. */
23915 know (S_GET_VALUE (sym) == next->fr_address);
23919 if (next->tc_frag_data.first_map != NULL)
23921 /* Next frag starts with a mapping symbol. Discard this
23923 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23927 if (next->fr_next == NULL)
23929 /* This mapping symbol is at the end of the section. Discard
23931 know (next->fr_fix == 0 && next->fr_var == 0);
23932 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23936 /* As long as we have empty frags without any mapping symbols,
23938 /* If the next frag is non-empty and does not start with a
23939 mapping symbol, then this mapping symbol is required. */
23940 if (next->fr_address != next->fr_next->fr_address)
23943 next = next->fr_next;
23945 while (next != NULL);
23950 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23954 arm_adjust_symtab (void)
23959 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23961 if (ARM_IS_THUMB (sym))
23963 if (THUMB_IS_FUNC (sym))
23965 /* Mark the symbol as a Thumb function. */
23966 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23967 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23968 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
23970 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23971 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23973 as_bad (_("%s: unexpected function type: %d"),
23974 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23976 else switch (S_GET_STORAGE_CLASS (sym))
23979 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23982 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23985 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23993 if (ARM_IS_INTERWORK (sym))
23994 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
24001 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
24003 if (ARM_IS_THUMB (sym))
24005 elf_symbol_type * elf_sym;
24007 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
24008 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
24010 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
24011 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
24013 /* If it's a .thumb_func, declare it as so,
24014 otherwise tag label as .code 16. */
24015 if (THUMB_IS_FUNC (sym))
24016 elf_sym->internal_elf_sym.st_target_internal
24017 = ST_BRANCH_TO_THUMB;
24018 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24019 elf_sym->internal_elf_sym.st_info =
24020 ELF_ST_INFO (bind, STT_ARM_16BIT);
24025 /* Remove any overlapping mapping symbols generated by alignment frags. */
24026 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
24027 /* Now do generic ELF adjustments. */
24028 elf_adjust_symtab ();
24032 /* MD interface: Initialization. */
24035 set_constant_flonums (void)
24039 for (i = 0; i < NUM_FLOAT_VALS; i++)
24040 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
24044 /* Auto-select Thumb mode if it's the only available instruction set for the
24045 given architecture. */
24048 autoselect_thumb_from_cpu_variant (void)
24050 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
24051 opcode_select (16);
24060 if ( (arm_ops_hsh = hash_new ()) == NULL
24061 || (arm_cond_hsh = hash_new ()) == NULL
24062 || (arm_shift_hsh = hash_new ()) == NULL
24063 || (arm_psr_hsh = hash_new ()) == NULL
24064 || (arm_v7m_psr_hsh = hash_new ()) == NULL
24065 || (arm_reg_hsh = hash_new ()) == NULL
24066 || (arm_reloc_hsh = hash_new ()) == NULL
24067 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
24068 as_fatal (_("virtual memory exhausted"));
24070 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
24071 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
24072 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
24073 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
24074 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
24075 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
24076 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
24077 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
24078 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
24079 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
24080 (void *) (v7m_psrs + i));
24081 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
24082 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
24084 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
24086 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
24087 (void *) (barrier_opt_names + i));
24089 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
24091 struct reloc_entry * entry = reloc_names + i;
24093 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
24094 /* This makes encode_branch() use the EABI versions of this relocation. */
24095 entry->reloc = BFD_RELOC_UNUSED;
24097 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
24101 set_constant_flonums ();
24103 /* Set the cpu variant based on the command-line options. We prefer
24104 -mcpu= over -march= if both are set (as for GCC); and we prefer
24105 -mfpu= over any other way of setting the floating point unit.
24106 Use of legacy options with new options are faulted. */
24109 if (mcpu_cpu_opt || march_cpu_opt)
24110 as_bad (_("use of old and new-style options to set CPU type"));
24112 mcpu_cpu_opt = legacy_cpu;
24114 else if (!mcpu_cpu_opt)
24115 mcpu_cpu_opt = march_cpu_opt;
24120 as_bad (_("use of old and new-style options to set FPU type"));
24122 mfpu_opt = legacy_fpu;
24124 else if (!mfpu_opt)
24126 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24127 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24128 /* Some environments specify a default FPU. If they don't, infer it
24129 from the processor. */
24131 mfpu_opt = mcpu_fpu_opt;
24133 mfpu_opt = march_fpu_opt;
24135 mfpu_opt = &fpu_default;
24141 if (mcpu_cpu_opt != NULL)
24142 mfpu_opt = &fpu_default;
24143 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
24144 mfpu_opt = &fpu_arch_vfp_v2;
24146 mfpu_opt = &fpu_arch_fpa;
24152 mcpu_cpu_opt = &cpu_default;
24153 selected_cpu = cpu_default;
24155 else if (no_cpu_selected ())
24156 selected_cpu = cpu_default;
24159 selected_cpu = *mcpu_cpu_opt;
24161 mcpu_cpu_opt = &arm_arch_any;
24164 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
24166 autoselect_thumb_from_cpu_variant ();
24168 arm_arch_used = thumb_arch_used = arm_arch_none;
24170 #if defined OBJ_COFF || defined OBJ_ELF
24172 unsigned int flags = 0;
24174 #if defined OBJ_ELF
24175 flags = meabi_flags;
24177 switch (meabi_flags)
24179 case EF_ARM_EABI_UNKNOWN:
24181 /* Set the flags in the private structure. */
24182 if (uses_apcs_26) flags |= F_APCS26;
24183 if (support_interwork) flags |= F_INTERWORK;
24184 if (uses_apcs_float) flags |= F_APCS_FLOAT;
24185 if (pic_code) flags |= F_PIC;
24186 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
24187 flags |= F_SOFT_FLOAT;
24189 switch (mfloat_abi_opt)
24191 case ARM_FLOAT_ABI_SOFT:
24192 case ARM_FLOAT_ABI_SOFTFP:
24193 flags |= F_SOFT_FLOAT;
24196 case ARM_FLOAT_ABI_HARD:
24197 if (flags & F_SOFT_FLOAT)
24198 as_bad (_("hard-float conflicts with specified fpu"));
24202 /* Using pure-endian doubles (even if soft-float). */
24203 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
24204 flags |= F_VFP_FLOAT;
24206 #if defined OBJ_ELF
24207 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
24208 flags |= EF_ARM_MAVERICK_FLOAT;
24211 case EF_ARM_EABI_VER4:
24212 case EF_ARM_EABI_VER5:
24213 /* No additional flags to set. */
24220 bfd_set_private_flags (stdoutput, flags);
24222 /* We have run out flags in the COFF header to encode the
24223 status of ATPCS support, so instead we create a dummy,
24224 empty, debug section called .arm.atpcs. */
24229 sec = bfd_make_section (stdoutput, ".arm.atpcs");
24233 bfd_set_section_flags
24234 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
24235 bfd_set_section_size (stdoutput, sec, 0);
24236 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
24242 /* Record the CPU type as well. */
24243 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
24244 mach = bfd_mach_arm_iWMMXt2;
24245 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
24246 mach = bfd_mach_arm_iWMMXt;
24247 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
24248 mach = bfd_mach_arm_XScale;
24249 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
24250 mach = bfd_mach_arm_ep9312;
24251 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
24252 mach = bfd_mach_arm_5TE;
24253 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
24255 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24256 mach = bfd_mach_arm_5T;
24258 mach = bfd_mach_arm_5;
24260 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
24262 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
24263 mach = bfd_mach_arm_4T;
24265 mach = bfd_mach_arm_4;
24267 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
24268 mach = bfd_mach_arm_3M;
24269 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
24270 mach = bfd_mach_arm_3;
24271 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
24272 mach = bfd_mach_arm_2a;
24273 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
24274 mach = bfd_mach_arm_2;
24276 mach = bfd_mach_arm_unknown;
24278 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
24281 /* Command line processing. */
24284 Invocation line includes a switch not recognized by the base assembler.
24285 See if it's a processor-specific option.
24287 This routine is somewhat complicated by the need for backwards
24288 compatibility (since older releases of gcc can't be changed).
24289 The new options try to make the interface as compatible as
24292 New options (supported) are:
24294 -mcpu=<cpu name> Assemble for selected processor
24295 -march=<architecture name> Assemble for selected architecture
24296 -mfpu=<fpu architecture> Assemble for selected FPU.
24297 -EB/-mbig-endian Big-endian
24298 -EL/-mlittle-endian Little-endian
24299 -k Generate PIC code
24300 -mthumb Start in Thumb mode
24301 -mthumb-interwork Code supports ARM/Thumb interworking
24303 -m[no-]warn-deprecated Warn about deprecated features
24304 -m[no-]warn-syms Warn when symbols match instructions
24306 For now we will also provide support for:
24308 -mapcs-32 32-bit Program counter
24309 -mapcs-26 26-bit Program counter
24310 -macps-float Floats passed in FP registers
24311 -mapcs-reentrant Reentrant code
24313 (sometime these will probably be replaced with -mapcs=<list of options>
24314 and -matpcs=<list of options>)
24316 The remaining options are only supported for back-wards compatibility.
24317 Cpu variants, the arm part is optional:
24318 -m[arm]1 Currently not supported.
24319 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24320 -m[arm]3 Arm 3 processor
24321 -m[arm]6[xx], Arm 6 processors
24322 -m[arm]7[xx][t][[d]m] Arm 7 processors
24323 -m[arm]8[10] Arm 8 processors
24324 -m[arm]9[20][tdmi] Arm 9 processors
24325 -mstrongarm[110[0]] StrongARM processors
24326 -mxscale XScale processors
24327 -m[arm]v[2345[t[e]]] Arm architectures
24328 -mall All (except the ARM1)
24330 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24331 -mfpe-old (No float load/store multiples)
24332 -mvfpxd VFP Single precision
24334 -mno-fpu Disable all floating point instructions
24336 The following CPU names are recognized:
24337 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24338 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24339 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24340 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24341 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24342 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24343 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24347 const char * md_shortopts = "m:k";
24349 #ifdef ARM_BI_ENDIAN
24350 #define OPTION_EB (OPTION_MD_BASE + 0)
24351 #define OPTION_EL (OPTION_MD_BASE + 1)
24353 #if TARGET_BYTES_BIG_ENDIAN
24354 #define OPTION_EB (OPTION_MD_BASE + 0)
24356 #define OPTION_EL (OPTION_MD_BASE + 1)
24359 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
24361 struct option md_longopts[] =
24364 {"EB", no_argument, NULL, OPTION_EB},
24367 {"EL", no_argument, NULL, OPTION_EL},
24369 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
24370 {NULL, no_argument, NULL, 0}
24374 size_t md_longopts_size = sizeof (md_longopts);
24376 struct arm_option_table
24378 char *option; /* Option name to match. */
24379 char *help; /* Help information. */
24380 int *var; /* Variable to change. */
24381 int value; /* What to change it to. */
24382 char *deprecated; /* If non-null, print this message. */
24385 struct arm_option_table arm_opts[] =
24387 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
24388 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
24389 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24390 &support_interwork, 1, NULL},
24391 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
24392 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
24393 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
24395 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
24396 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
24397 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
24398 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
24401 /* These are recognized by the assembler, but have no affect on code. */
24402 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
24403 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
24405 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
24406 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24407 &warn_on_deprecated, 0, NULL},
24408 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
24409 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
24410 {NULL, NULL, NULL, 0, NULL}
24413 struct arm_legacy_option_table
24415 char *option; /* Option name to match. */
24416 const arm_feature_set **var; /* Variable to change. */
24417 const arm_feature_set value; /* What to change it to. */
24418 char *deprecated; /* If non-null, print this message. */
24421 const struct arm_legacy_option_table arm_legacy_opts[] =
24423 /* DON'T add any new processors to this list -- we want the whole list
24424 to go away... Add them to the processors table instead. */
24425 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24426 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24427 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24428 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24429 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24430 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24431 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24432 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24433 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24434 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24435 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24436 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24437 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24438 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24439 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24440 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24441 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24442 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24443 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24444 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24445 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24446 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24447 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24448 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24449 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24450 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24451 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24452 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24453 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24454 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24455 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24456 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24457 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24458 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24459 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24460 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24461 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24462 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24463 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24464 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24465 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24466 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24467 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24468 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24469 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24470 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24471 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24472 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24473 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24474 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24475 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24476 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24477 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24478 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24479 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24480 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24481 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24482 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24483 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24484 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24485 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24486 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24487 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24488 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24489 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24490 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24491 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24492 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24493 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
24494 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
24495 N_("use -mcpu=strongarm110")},
24496 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
24497 N_("use -mcpu=strongarm1100")},
24498 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
24499 N_("use -mcpu=strongarm1110")},
24500 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
24501 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
24502 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
24504 /* Architecture variants -- don't add any more to this list either. */
24505 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24506 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24507 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24508 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24509 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24510 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24511 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24512 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24513 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24514 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24515 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24516 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24517 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24518 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24519 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24520 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24521 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
24522 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
24524 /* Floating point variants -- don't add any more to this list either. */
24525 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
24526 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
24527 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
24528 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
24529 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24531 {NULL, NULL, ARM_ARCH_NONE, NULL}
24534 struct arm_cpu_option_table
24538 const arm_feature_set value;
24539 /* For some CPUs we assume an FPU unless the user explicitly sets
24541 const arm_feature_set default_fpu;
24542 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24544 const char *canonical_name;
24547 /* This list should, at a minimum, contain all the cpu names
24548 recognized by GCC. */
24549 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24550 static const struct arm_cpu_option_table arm_cpus[] =
24552 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
24553 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
24554 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
24555 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24556 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24557 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24558 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24559 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24560 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24561 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24562 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24563 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24564 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24565 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24566 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24567 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24568 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24569 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24570 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24571 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24572 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24573 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24574 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24575 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24576 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24577 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24578 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24579 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24580 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24581 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24582 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24583 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24584 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24585 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24586 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24587 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24588 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24589 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24590 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24591 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
24592 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24593 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24594 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24595 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24596 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24597 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24598 /* For V5 or later processors we default to using VFP; but the user
24599 should really set the FPU type explicitly. */
24600 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24601 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24602 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24603 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24604 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24605 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24606 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
24607 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24608 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24609 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
24610 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24611 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24612 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24613 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24614 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24615 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
24616 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24617 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24618 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24619 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
24621 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24622 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24623 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24624 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24625 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24626 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24627 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
24628 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
24629 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
24631 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
24632 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
24633 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
24634 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
24635 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
24636 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
24637 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
24638 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
24639 FPU_NONE, "Cortex-A5"),
24640 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24642 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
24643 ARM_FEATURE_COPROC (FPU_VFP_V3
24644 | FPU_NEON_EXT_V1),
24646 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
24647 ARM_FEATURE_COPROC (FPU_VFP_V3
24648 | FPU_NEON_EXT_V1),
24650 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24652 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24654 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24656 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24658 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24660 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24662 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
24663 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24665 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24666 FPU_NONE, "Cortex-R5"),
24667 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24668 FPU_ARCH_VFP_V3D16,
24670 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
24671 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24672 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24673 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24674 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
24675 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
24676 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24679 /* ??? XSCALE is really an architecture. */
24680 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24681 /* ??? iwmmxt is not a processor. */
24682 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24683 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24684 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
24686 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
24687 FPU_ARCH_MAVERICK, "ARM920T"),
24688 /* Marvell processors. */
24689 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP
24691 FPU_ARCH_VFP_V3D16, NULL),
24692 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP
24694 FPU_ARCH_NEON_VFP_V4, NULL),
24695 /* APM X-Gene family. */
24696 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24698 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24701 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
24705 struct arm_arch_option_table
24709 const arm_feature_set value;
24710 const arm_feature_set default_fpu;
24713 /* This list should, at a minimum, contain all the architecture names
24714 recognized by GCC. */
24715 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24716 static const struct arm_arch_option_table arm_archs[] =
24718 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24719 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24720 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24721 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24722 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24723 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24724 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24725 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24726 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24727 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24728 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24729 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24730 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24731 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24732 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24733 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24734 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24735 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24736 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24737 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24738 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24739 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24740 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24741 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24742 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24743 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24744 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24745 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24746 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
24747 /* The official spelling of the ARMv7 profile variants is the dashed form.
24748 Accept the non-dashed form for compatibility with old toolchains. */
24749 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24750 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
24751 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24752 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24753 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24754 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24755 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24756 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
24757 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
24758 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP),
24759 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24760 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24761 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24762 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
24764 #undef ARM_ARCH_OPT
24766 /* ISA extensions in the co-processor and main instruction set space. */
24767 struct arm_option_extension_value_table
24771 const arm_feature_set merge_value;
24772 const arm_feature_set clear_value;
24773 const arm_feature_set allowed_archs;
24776 /* The following table must be in alphabetical order with a NULL last entry.
24778 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
24779 static const struct arm_option_extension_value_table arm_extensions[] =
24781 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
24782 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24783 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24784 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
24785 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24786 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
24787 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24788 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
24789 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
24790 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)),
24791 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
24792 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ANY),
24793 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
24794 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ANY),
24795 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
24796 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ANY),
24797 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
24798 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
24799 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A | ARM_EXT_V7R)),
24800 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24801 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
24802 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24803 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
24804 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
24805 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
24806 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
24807 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
24808 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24809 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
24810 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
24811 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V7A)),
24812 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
24814 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
24815 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
24816 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8,
24817 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
24818 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
24819 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
24820 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ANY),
24821 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
24825 /* ISA floating-point and Advanced SIMD extensions. */
24826 struct arm_option_fpu_value_table
24829 const arm_feature_set value;
24832 /* This list should, at a minimum, contain all the fpu names
24833 recognized by GCC. */
24834 static const struct arm_option_fpu_value_table arm_fpus[] =
24836 {"softfpa", FPU_NONE},
24837 {"fpe", FPU_ARCH_FPE},
24838 {"fpe2", FPU_ARCH_FPE},
24839 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24840 {"fpa", FPU_ARCH_FPA},
24841 {"fpa10", FPU_ARCH_FPA},
24842 {"fpa11", FPU_ARCH_FPA},
24843 {"arm7500fe", FPU_ARCH_FPA},
24844 {"softvfp", FPU_ARCH_VFP},
24845 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24846 {"vfp", FPU_ARCH_VFP_V2},
24847 {"vfp9", FPU_ARCH_VFP_V2},
24848 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
24849 {"vfp10", FPU_ARCH_VFP_V2},
24850 {"vfp10-r0", FPU_ARCH_VFP_V1},
24851 {"vfpxd", FPU_ARCH_VFP_V1xD},
24852 {"vfpv2", FPU_ARCH_VFP_V2},
24853 {"vfpv3", FPU_ARCH_VFP_V3},
24854 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
24855 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
24856 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24857 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24858 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
24859 {"arm1020t", FPU_ARCH_VFP_V1},
24860 {"arm1020e", FPU_ARCH_VFP_V2},
24861 {"arm1136jfs", FPU_ARCH_VFP_V2},
24862 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24863 {"maverick", FPU_ARCH_MAVERICK},
24864 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
24865 {"neon-fp16", FPU_ARCH_NEON_FP16},
24866 {"vfpv4", FPU_ARCH_VFP_V4},
24867 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
24868 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
24869 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
24870 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
24871 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
24872 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24873 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24874 {"crypto-neon-fp-armv8",
24875 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
24876 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
24877 {NULL, ARM_ARCH_NONE}
24880 struct arm_option_value_table
24886 static const struct arm_option_value_table arm_float_abis[] =
24888 {"hard", ARM_FLOAT_ABI_HARD},
24889 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24890 {"soft", ARM_FLOAT_ABI_SOFT},
24895 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24896 static const struct arm_option_value_table arm_eabis[] =
24898 {"gnu", EF_ARM_EABI_UNKNOWN},
24899 {"4", EF_ARM_EABI_VER4},
24900 {"5", EF_ARM_EABI_VER5},
24905 struct arm_long_option_table
24907 char * option; /* Substring to match. */
24908 char * help; /* Help information. */
24909 int (* func) (char * subopt); /* Function to decode sub-option. */
24910 char * deprecated; /* If non-null, print this message. */
24914 arm_parse_extension (char *str, const arm_feature_set **opt_p)
24916 arm_feature_set *ext_set = (arm_feature_set *)
24917 xmalloc (sizeof (arm_feature_set));
24919 /* We insist on extensions being specified in alphabetical order, and with
24920 extensions being added before being removed. We achieve this by having
24921 the global ARM_EXTENSIONS table in alphabetical order, and using the
24922 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24923 or removing it (0) and only allowing it to change in the order
24925 const struct arm_option_extension_value_table * opt = NULL;
24926 int adding_value = -1;
24928 /* Copy the feature set, so that we can modify it. */
24929 *ext_set = **opt_p;
24932 while (str != NULL && *str != 0)
24939 as_bad (_("invalid architectural extension"));
24944 ext = strchr (str, '+');
24949 len = strlen (str);
24951 if (len >= 2 && strncmp (str, "no", 2) == 0)
24953 if (adding_value != 0)
24956 opt = arm_extensions;
24964 if (adding_value == -1)
24967 opt = arm_extensions;
24969 else if (adding_value != 1)
24971 as_bad (_("must specify extensions to add before specifying "
24972 "those to remove"));
24979 as_bad (_("missing architectural extension"));
24983 gas_assert (adding_value != -1);
24984 gas_assert (opt != NULL);
24986 /* Scan over the options table trying to find an exact match. */
24987 for (; opt->name != NULL; opt++)
24988 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
24990 /* Check we can apply the extension to this architecture. */
24991 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24993 as_bad (_("extension does not apply to the base architecture"));
24997 /* Add or remove the extension. */
24999 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
25001 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
25006 if (opt->name == NULL)
25008 /* Did we fail to find an extension because it wasn't specified in
25009 alphabetical order, or because it does not exist? */
25011 for (opt = arm_extensions; opt->name != NULL; opt++)
25012 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25015 if (opt->name == NULL)
25016 as_bad (_("unknown architectural extension `%s'"), str);
25018 as_bad (_("architectural extensions must be specified in "
25019 "alphabetical order"));
25025 /* We should skip the extension we've just matched the next time
25037 arm_parse_cpu (char *str)
25039 const struct arm_cpu_option_table *opt;
25040 char *ext = strchr (str, '+');
25046 len = strlen (str);
25050 as_bad (_("missing cpu name `%s'"), str);
25054 for (opt = arm_cpus; opt->name != NULL; opt++)
25055 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25057 mcpu_cpu_opt = &opt->value;
25058 mcpu_fpu_opt = &opt->default_fpu;
25059 if (opt->canonical_name)
25060 strcpy (selected_cpu_name, opt->canonical_name);
25065 for (i = 0; i < len; i++)
25066 selected_cpu_name[i] = TOUPPER (opt->name[i]);
25067 selected_cpu_name[i] = 0;
25071 return arm_parse_extension (ext, &mcpu_cpu_opt);
25076 as_bad (_("unknown cpu `%s'"), str);
25081 arm_parse_arch (char *str)
25083 const struct arm_arch_option_table *opt;
25084 char *ext = strchr (str, '+');
25090 len = strlen (str);
25094 as_bad (_("missing architecture name `%s'"), str);
25098 for (opt = arm_archs; opt->name != NULL; opt++)
25099 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
25101 march_cpu_opt = &opt->value;
25102 march_fpu_opt = &opt->default_fpu;
25103 strcpy (selected_cpu_name, opt->name);
25106 return arm_parse_extension (ext, &march_cpu_opt);
25111 as_bad (_("unknown architecture `%s'\n"), str);
25116 arm_parse_fpu (char * str)
25118 const struct arm_option_fpu_value_table * opt;
25120 for (opt = arm_fpus; opt->name != NULL; opt++)
25121 if (streq (opt->name, str))
25123 mfpu_opt = &opt->value;
25127 as_bad (_("unknown floating point format `%s'\n"), str);
25132 arm_parse_float_abi (char * str)
25134 const struct arm_option_value_table * opt;
25136 for (opt = arm_float_abis; opt->name != NULL; opt++)
25137 if (streq (opt->name, str))
25139 mfloat_abi_opt = opt->value;
25143 as_bad (_("unknown floating point abi `%s'\n"), str);
25149 arm_parse_eabi (char * str)
25151 const struct arm_option_value_table *opt;
25153 for (opt = arm_eabis; opt->name != NULL; opt++)
25154 if (streq (opt->name, str))
25156 meabi_flags = opt->value;
25159 as_bad (_("unknown EABI `%s'\n"), str);
25165 arm_parse_it_mode (char * str)
25167 bfd_boolean ret = TRUE;
25169 if (streq ("arm", str))
25170 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
25171 else if (streq ("thumb", str))
25172 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
25173 else if (streq ("always", str))
25174 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
25175 else if (streq ("never", str))
25176 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
25179 as_bad (_("unknown implicit IT mode `%s', should be "\
25180 "arm, thumb, always, or never."), str);
25188 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED)
25190 codecomposer_syntax = TRUE;
25191 arm_comment_chars[0] = ';';
25192 arm_line_separator_chars[0] = 0;
25196 struct arm_long_option_table arm_long_opts[] =
25198 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25199 arm_parse_cpu, NULL},
25200 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25201 arm_parse_arch, NULL},
25202 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25203 arm_parse_fpu, NULL},
25204 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25205 arm_parse_float_abi, NULL},
25207 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25208 arm_parse_eabi, NULL},
25210 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25211 arm_parse_it_mode, NULL},
25212 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25213 arm_ccs_mode, NULL},
25214 {NULL, NULL, 0, NULL}
25218 md_parse_option (int c, char * arg)
25220 struct arm_option_table *opt;
25221 const struct arm_legacy_option_table *fopt;
25222 struct arm_long_option_table *lopt;
25228 target_big_endian = 1;
25234 target_big_endian = 0;
25238 case OPTION_FIX_V4BX:
25243 /* Listing option. Just ignore these, we don't support additional
25248 for (opt = arm_opts; opt->option != NULL; opt++)
25250 if (c == opt->option[0]
25251 && ((arg == NULL && opt->option[1] == 0)
25252 || streq (arg, opt->option + 1)))
25254 /* If the option is deprecated, tell the user. */
25255 if (warn_on_deprecated && opt->deprecated != NULL)
25256 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25257 arg ? arg : "", _(opt->deprecated));
25259 if (opt->var != NULL)
25260 *opt->var = opt->value;
25266 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
25268 if (c == fopt->option[0]
25269 && ((arg == NULL && fopt->option[1] == 0)
25270 || streq (arg, fopt->option + 1)))
25272 /* If the option is deprecated, tell the user. */
25273 if (warn_on_deprecated && fopt->deprecated != NULL)
25274 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25275 arg ? arg : "", _(fopt->deprecated));
25277 if (fopt->var != NULL)
25278 *fopt->var = &fopt->value;
25284 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25286 /* These options are expected to have an argument. */
25287 if (c == lopt->option[0]
25289 && strncmp (arg, lopt->option + 1,
25290 strlen (lopt->option + 1)) == 0)
25292 /* If the option is deprecated, tell the user. */
25293 if (warn_on_deprecated && lopt->deprecated != NULL)
25294 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
25295 _(lopt->deprecated));
25297 /* Call the sup-option parser. */
25298 return lopt->func (arg + strlen (lopt->option) - 1);
25309 md_show_usage (FILE * fp)
25311 struct arm_option_table *opt;
25312 struct arm_long_option_table *lopt;
25314 fprintf (fp, _(" ARM-specific assembler options:\n"));
25316 for (opt = arm_opts; opt->option != NULL; opt++)
25317 if (opt->help != NULL)
25318 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
25320 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25321 if (lopt->help != NULL)
25322 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
25326 -EB assemble code for a big-endian cpu\n"));
25331 -EL assemble code for a little-endian cpu\n"));
25335 --fix-v4bx Allow BX in ARMv4 code\n"));
25343 arm_feature_set flags;
25344 } cpu_arch_ver_table;
25346 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25347 least features first. */
25348 static const cpu_arch_ver_table cpu_arch_ver[] =
25354 {4, ARM_ARCH_V5TE},
25355 {5, ARM_ARCH_V5TEJ},
25359 {11, ARM_ARCH_V6M},
25360 {12, ARM_ARCH_V6SM},
25361 {8, ARM_ARCH_V6T2},
25362 {10, ARM_ARCH_V7VE},
25363 {10, ARM_ARCH_V7R},
25364 {10, ARM_ARCH_V7M},
25365 {14, ARM_ARCH_V8A},
25369 /* Set an attribute if it has not already been set by the user. */
25371 aeabi_set_attribute_int (int tag, int value)
25374 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25375 || !attributes_set_explicitly[tag])
25376 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
25380 aeabi_set_attribute_string (int tag, const char *value)
25383 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25384 || !attributes_set_explicitly[tag])
25385 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
25388 /* Set the public EABI object attributes. */
25390 aeabi_set_public_attributes (void)
25395 int fp16_optional = 0;
25396 arm_feature_set flags;
25397 arm_feature_set tmp;
25398 const cpu_arch_ver_table *p;
25400 /* Choose the architecture based on the capabilities of the requested cpu
25401 (if any) and/or the instructions actually used. */
25402 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
25403 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
25404 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
25406 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
25407 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
25409 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
25410 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
25412 selected_cpu = flags;
25414 /* Allow the user to override the reported architecture. */
25417 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
25418 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
25421 /* We need to make sure that the attributes do not identify us as v6S-M
25422 when the only v6S-M feature in use is the Operating System Extensions. */
25423 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
25424 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
25425 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
25429 for (p = cpu_arch_ver; p->val; p++)
25431 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
25434 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
25438 /* The table lookup above finds the last architecture to contribute
25439 a new feature. Unfortunately, Tag13 is a subset of the union of
25440 v6T2 and v7-M, so it is never seen as contributing a new feature.
25441 We can not search for the last entry which is entirely used,
25442 because if no CPU is specified we build up only those flags
25443 actually used. Perhaps we should separate out the specified
25444 and implicit cases. Avoid taking this path for -march=all by
25445 checking for contradictory v7-A / v7-M features. */
25447 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
25448 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
25449 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
25452 /* Tag_CPU_name. */
25453 if (selected_cpu_name[0])
25457 q = selected_cpu_name;
25458 if (strncmp (q, "armv", 4) == 0)
25463 for (i = 0; q[i]; i++)
25464 q[i] = TOUPPER (q[i]);
25466 aeabi_set_attribute_string (Tag_CPU_name, q);
25469 /* Tag_CPU_arch. */
25470 aeabi_set_attribute_int (Tag_CPU_arch, arch);
25472 /* Tag_CPU_arch_profile. */
25473 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
25475 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
25477 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
25482 if (profile != '\0')
25483 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
25485 /* Tag_ARM_ISA_use. */
25486 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
25488 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
25490 /* Tag_THUMB_ISA_use. */
25491 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
25493 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
25494 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
25496 /* Tag_VFP_arch. */
25497 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
25498 aeabi_set_attribute_int (Tag_VFP_arch,
25499 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25501 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
25502 aeabi_set_attribute_int (Tag_VFP_arch,
25503 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25505 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
25508 aeabi_set_attribute_int (Tag_VFP_arch, 3);
25510 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
25512 aeabi_set_attribute_int (Tag_VFP_arch, 4);
25515 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
25516 aeabi_set_attribute_int (Tag_VFP_arch, 2);
25517 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
25518 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
25519 aeabi_set_attribute_int (Tag_VFP_arch, 1);
25521 /* Tag_ABI_HardFP_use. */
25522 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
25523 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
25524 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
25526 /* Tag_WMMX_arch. */
25527 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
25528 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
25529 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
25530 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
25532 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25533 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
25534 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
25535 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
25537 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
25539 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
25543 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
25548 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25549 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
25550 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
25554 We set Tag_DIV_use to two when integer divide instructions have been used
25555 in ARM state, or when Thumb integer divide instructions have been used,
25556 but we have no architecture profile set, nor have we any ARM instructions.
25558 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25561 For new architectures we will have to check these tests. */
25562 gas_assert (arch <= TAG_CPU_ARCH_V8);
25563 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
25564 aeabi_set_attribute_int (Tag_DIV_use, 0);
25565 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
25566 || (profile == '\0'
25567 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
25568 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
25569 aeabi_set_attribute_int (Tag_DIV_use, 2);
25571 /* Tag_MP_extension_use. */
25572 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
25573 aeabi_set_attribute_int (Tag_MPextension_use, 1);
25575 /* Tag Virtualization_use. */
25576 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
25578 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
25581 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
25584 /* Add the default contents for the .ARM.attributes section. */
25588 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
25591 aeabi_set_public_attributes ();
25593 #endif /* OBJ_ELF */
25596 /* Parse a .cpu directive. */
25599 s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
25601 const struct arm_cpu_option_table *opt;
25605 name = input_line_pointer;
25606 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25607 input_line_pointer++;
25608 saved_char = *input_line_pointer;
25609 *input_line_pointer = 0;
25611 /* Skip the first "all" entry. */
25612 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
25613 if (streq (opt->name, name))
25615 mcpu_cpu_opt = &opt->value;
25616 selected_cpu = opt->value;
25617 if (opt->canonical_name)
25618 strcpy (selected_cpu_name, opt->canonical_name);
25622 for (i = 0; opt->name[i]; i++)
25623 selected_cpu_name[i] = TOUPPER (opt->name[i]);
25625 selected_cpu_name[i] = 0;
25627 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25628 *input_line_pointer = saved_char;
25629 demand_empty_rest_of_line ();
25632 as_bad (_("unknown cpu `%s'"), name);
25633 *input_line_pointer = saved_char;
25634 ignore_rest_of_line ();
25638 /* Parse a .arch directive. */
25641 s_arm_arch (int ignored ATTRIBUTE_UNUSED)
25643 const struct arm_arch_option_table *opt;
25647 name = input_line_pointer;
25648 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25649 input_line_pointer++;
25650 saved_char = *input_line_pointer;
25651 *input_line_pointer = 0;
25653 /* Skip the first "all" entry. */
25654 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25655 if (streq (opt->name, name))
25657 mcpu_cpu_opt = &opt->value;
25658 selected_cpu = opt->value;
25659 strcpy (selected_cpu_name, opt->name);
25660 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25661 *input_line_pointer = saved_char;
25662 demand_empty_rest_of_line ();
25666 as_bad (_("unknown architecture `%s'\n"), name);
25667 *input_line_pointer = saved_char;
25668 ignore_rest_of_line ();
25672 /* Parse a .object_arch directive. */
25675 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
25677 const struct arm_arch_option_table *opt;
25681 name = input_line_pointer;
25682 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25683 input_line_pointer++;
25684 saved_char = *input_line_pointer;
25685 *input_line_pointer = 0;
25687 /* Skip the first "all" entry. */
25688 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25689 if (streq (opt->name, name))
25691 object_arch = &opt->value;
25692 *input_line_pointer = saved_char;
25693 demand_empty_rest_of_line ();
25697 as_bad (_("unknown architecture `%s'\n"), name);
25698 *input_line_pointer = saved_char;
25699 ignore_rest_of_line ();
25702 /* Parse a .arch_extension directive. */
25705 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
25707 const struct arm_option_extension_value_table *opt;
25710 int adding_value = 1;
25712 name = input_line_pointer;
25713 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25714 input_line_pointer++;
25715 saved_char = *input_line_pointer;
25716 *input_line_pointer = 0;
25718 if (strlen (name) >= 2
25719 && strncmp (name, "no", 2) == 0)
25725 for (opt = arm_extensions; opt->name != NULL; opt++)
25726 if (streq (opt->name, name))
25728 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25730 as_bad (_("architectural extension `%s' is not allowed for the "
25731 "current base architecture"), name);
25736 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
25739 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
25741 mcpu_cpu_opt = &selected_cpu;
25742 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25743 *input_line_pointer = saved_char;
25744 demand_empty_rest_of_line ();
25748 if (opt->name == NULL)
25749 as_bad (_("unknown architecture extension `%s'\n"), name);
25751 *input_line_pointer = saved_char;
25752 ignore_rest_of_line ();
25755 /* Parse a .fpu directive. */
25758 s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25760 const struct arm_option_fpu_value_table *opt;
25764 name = input_line_pointer;
25765 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25766 input_line_pointer++;
25767 saved_char = *input_line_pointer;
25768 *input_line_pointer = 0;
25770 for (opt = arm_fpus; opt->name != NULL; opt++)
25771 if (streq (opt->name, name))
25773 mfpu_opt = &opt->value;
25774 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25775 *input_line_pointer = saved_char;
25776 demand_empty_rest_of_line ();
25780 as_bad (_("unknown floating point format `%s'\n"), name);
25781 *input_line_pointer = saved_char;
25782 ignore_rest_of_line ();
25785 /* Copy symbol information. */
25788 arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25790 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25794 /* Given a symbolic attribute NAME, return the proper integer value.
25795 Returns -1 if the attribute is not known. */
25798 arm_convert_symbolic_attribute (const char *name)
25800 static const struct
25805 attribute_table[] =
25807 /* When you modify this table you should
25808 also modify the list in doc/c-arm.texi. */
25809 #define T(tag) {#tag, tag}
25810 T (Tag_CPU_raw_name),
25813 T (Tag_CPU_arch_profile),
25814 T (Tag_ARM_ISA_use),
25815 T (Tag_THUMB_ISA_use),
25819 T (Tag_Advanced_SIMD_arch),
25820 T (Tag_PCS_config),
25821 T (Tag_ABI_PCS_R9_use),
25822 T (Tag_ABI_PCS_RW_data),
25823 T (Tag_ABI_PCS_RO_data),
25824 T (Tag_ABI_PCS_GOT_use),
25825 T (Tag_ABI_PCS_wchar_t),
25826 T (Tag_ABI_FP_rounding),
25827 T (Tag_ABI_FP_denormal),
25828 T (Tag_ABI_FP_exceptions),
25829 T (Tag_ABI_FP_user_exceptions),
25830 T (Tag_ABI_FP_number_model),
25831 T (Tag_ABI_align_needed),
25832 T (Tag_ABI_align8_needed),
25833 T (Tag_ABI_align_preserved),
25834 T (Tag_ABI_align8_preserved),
25835 T (Tag_ABI_enum_size),
25836 T (Tag_ABI_HardFP_use),
25837 T (Tag_ABI_VFP_args),
25838 T (Tag_ABI_WMMX_args),
25839 T (Tag_ABI_optimization_goals),
25840 T (Tag_ABI_FP_optimization_goals),
25841 T (Tag_compatibility),
25842 T (Tag_CPU_unaligned_access),
25843 T (Tag_FP_HP_extension),
25844 T (Tag_VFP_HP_extension),
25845 T (Tag_ABI_FP_16bit_format),
25846 T (Tag_MPextension_use),
25848 T (Tag_nodefaults),
25849 T (Tag_also_compatible_with),
25850 T (Tag_conformance),
25852 T (Tag_Virtualization_use),
25853 /* We deliberately do not include Tag_MPextension_use_legacy. */
25861 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
25862 if (streq (name, attribute_table[i].name))
25863 return attribute_table[i].tag;
25869 /* Apply sym value for relocations only in the case that they are for
25870 local symbols in the same segment as the fixup and you have the
25871 respective architectural feature for blx and simple switches. */
25873 arm_apply_sym_value (struct fix * fixP, segT this_seg)
25876 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
25877 /* PR 17444: If the local symbol is in a different section then a reloc
25878 will always be generated for it, so applying the symbol value now
25879 will result in a double offset being stored in the relocation. */
25880 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
25881 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
25883 switch (fixP->fx_r_type)
25885 case BFD_RELOC_ARM_PCREL_BLX:
25886 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25887 if (ARM_IS_FUNC (fixP->fx_addsy))
25891 case BFD_RELOC_ARM_PCREL_CALL:
25892 case BFD_RELOC_THUMB_PCREL_BLX:
25893 if (THUMB_IS_FUNC (fixP->fx_addsy))
25904 #endif /* OBJ_ELF */